From f6037c77e2308e8fd50824c1a1bfa914ecca5b89 Mon Sep 17 00:00:00 2001 From: Vesim Date: Thu, 18 Mar 2021 18:01:50 +0100 Subject: [PATCH 001/138] initial commit --- README.md | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 README.md diff --git a/README.md b/README.md new file mode 100644 index 0000000..e69de29 From e32d230c0747cccc156579a7f89d4cc84397c24c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Mon, 26 Apr 2021 22:37:30 +0200 Subject: [PATCH 002/138] Create thoughts.md --- thoughts.md | 262 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 262 insertions(+) create mode 100644 thoughts.md diff --git a/thoughts.md b/thoughts.md new file mode 100644 index 0000000..3df4111 --- /dev/null +++ b/thoughts.md @@ -0,0 +1,262 @@ +# microzig Design Meeting + +## Package structure + +`microzig` package exports all functions and types available in the HAL as well as `microzig.mcu` which will provide access to the MCU. All functions in `microzig` which are not generic will be inline-forwarded to the `board` or `mcu` package. + +``` +root + |- std + |- microzig + | |- mcu (should be specified if "board" does not exit) + | |- build_options (defines if "mcu" and/or "board" exists) + | \- board (must export ".mcu") + | \- mcu + \- mcu (user decision) +``` + +## Minimal Root file + +Declaring `panic` in the root file will cause `builtin` to reference the proper package which will then instantiate microzig which will reference `mcu` package which will instantiate `reset` (or similar) which will invoke `microzig.main()` which will invoke `root.main()`. Oh boy :laughing: + +```zig +const micro = @import("micro"); + +pub const panic = micro.panic; // this will instantiate microzig + +comptime { _ = micro }; // this should not be necessary + +pub fn main() void { + +} +``` + +## `microzig.mcu` + +`microzig` exports a symbol `mcu` which will provide access to the MCU, CPU and board features + +```zig +// mcu.zig in microzig.zig +const config = @import("build_options"); + +usingnamespace if(config.has_board) + @import("board").mcu +else + @import("mcu"); + +pub const has_board = config.has_board; +pub const board = @import("board"); +``` + +## Interrupt API + +All interrupt handlers are static and will be collected from `root.interrupt_handlers`. Each symbol will be verified if it's a valid interrupt vector. +A symbol can be a function `fn() void`, or a anonymous enum literal `.hang` or `.reset`. + +`microzig.interrupts.enable` and `microzig.interrupts.disable` will allow masking/unmasking those interrupts, `.cli()` and `.sei()` will globally disable/enable interrupts + +`microzig.interrupts` also provides some handling of critical sections + +```zig +pub fn main() void { + micro.interrupts.enable(.WDT); // enables the WDT interrupt + micro.interrupts.disable(.WDT); // enables the WDT interrupt + micro.interrupts.enable(.WTF); // yields compile error "WTF is not a valid interrupt" + micro.interrupts.enable(.PCINT0); // yields compile error "PCINT0 has no defined interrupt handler" + micro.interrupts.enable(.NMI); // yields compile error "NMI cannot be masked" + micro.interrupts.enableAll(); + micro.interrupts.batchEnable(.{ .NMI, .WDT }); + + micro.interrupts.cli(); // set interrupt enabled (global enable) + + { // critical section + var crit = micro.interrupts.enterCriticalSection(); + defer crit.leave(); + } +} + +var TIMER2_OVF_RUNTIME: fn()void = foo; + +pub const interrupt_handlers = struct { + + // AVR + pub fn TIMER2_OVF() void { TIMER2_OVF_RUNTIME(); } + pub fn WDT() void { } + + pub const PCINT1 = .reset; + pub const PCINT2 = .hang; + + // cortex-mX exceptions + pub fn NMI() void { } + pub fn HardFault() void {} + + // LPC 1768 interrupt/irq + pub fn SSP1() void { } +}; +``` + +## Timer API + +microzig should allow having a general purpose timer mechanism + +```zig +pub var cpu_frequency = 16.0 * micro.clock.mega_hertz; + +pub const sleep_mode = .timer; // timer, busyloop, whatever + +pub fn main() !void { + led.init(); + + while(true) { + led.toggle(); + micro.sleep(100_000); // sleep 100ms + } +} +``` + +## GPIO API + +`microzig.Pin` parses a pin definition and returns a type that encodes all relevant info and functions to route that pin. +`microzig.Gpio` is a GPIO port/pin configuration that allows modifying pin levels. + +```zig + +// micro.Pin returns a type containing all relevant pin information +const status_led_pin = micro.Pin("PA3"); + +// generate a runtime possible pin that cannot be used in all APIs +var generic_pic: micro.RuntimePin.init(status_led_pin); + +// 4 Bit IEEE-488 bit banging register +const serial_out = micro.GpioOutputRegister(.{ + micro.Pin("PA0"), + micro.Pin("PA1"), + micro.Pin("PA3"), // whoopsies, i miswired, let the software fix that + micro.Pin("PA2"), +}); + +pub fn bitBang(nibble: u4) void { + serial_out.write(nibble); +} + +pub fn main() !void { + + // Route all gpio pins from the bit bang register + inline for(serial_out.pins) |pin| { + pin.route(".gpio"); + } + serial_out.init(); + + // route that pin to UART.RXD + status_led_pin.route(.uart0_rxd); + + //var uart_read_dma_channel = micro.Dma.init(.{.channel = 1}); + + const status_led = micro.Gpio(status_led_pin, .{ + .mode = .output, // { input, output, input_output, open_drain, generic } + .initial_state = .unspecificed, // { unspecified, low, high, floating, driven } + }); + status_led.init(); + + switch(status_led.mode) { + // only reading API is available + .input => { + _ = status_led.read(); + }, + + // reading and writing is available + .output => { + _ = status_led.read(); + status_led.write(.high); + + // "subvariant" of the write + status_led.toggle(); + status_led.setToHigh(); + status_led.setToLow(); + }, + + // reading, writing and changing direction is available + .input_output => { + status_led.setDirection(.input, undefined); + _ = status_led.read(); + status_led.setDirection(.output, .high); // reqires a defined state after setting the direction + status_led.write(.high); + }, + + // reading and setDive is available + .open_drain => { + status_led.setDrive(.disabled); + _ = status_led.read(); + status_led.setDrive(.enabled); + }, + + // will have all available APIs enabled + .generic => {}, + } + + // AVR: PORTA[3] => "PA3" + // NXP: PORT[1][3] => "P1.3" + // PICO: PORT[1] => "P3" + // STM: PORT[A][3] => "A3" + // ESP32: PORT[1] => "P3" +``` + + +## UART example + +```zig +const std = @import("std"); +const micro = @import("µzig"); + +// if const it can be comptime-optimized +pub var cpu_frequency = 100.0 * micro.clock.mega_hertz; + +// if this is enabled, a event loop will run +// in microzig.main() that allows using `async`/`await` "just like that" *grin* +pub const io_mode = .evented; + +pub fn main() !void { + var debug_port = micro.Uart.init(0, .{ + .baud_rate = 9600, + .stop_bits = .@"2", + .parity = .none, // { none, even, odd, mark, space } + .data_bits = .@"8", // 5, 6, 7, 8, or 9 data bits + //.in_dma_channel = 0, + //.out_dma_channel = 0, + }); + + debug_port.configureDMA(???); + + try debug_port.writer().writeAll("Hello, World!"); + + var line_buffer: [64]u8 = undefined; + const len = try debug_port.reader().readUntilDelimiter(&line_buffer, '\n'); +} +``` + + + + +## Initialization + +somewhere inside micro.zig +```zig +extern fn reset() noreturn { + if(@hasDecl(mcu, "mcu_reset")) { + mcu.mcu_reset(); + @unreachable(); + } + // zeroing bss, copying .data, setting stack address + + if(@hasDecl(root, "early_main")) // idk about the name + root.early_main(); + else { + mcu.init(); + + if(@hasDecl(root, "main")) + root.main(); + else + @compileError("main or entry_main missing") + } +} +``` From bbfdb421d808f852630a97c9330477981af9c97d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Tue, 27 Apr 2021 21:32:09 +0200 Subject: [PATCH 003/138] File structure, draft 1 --- .gitattributes | 1 + .gitignore | 1 + build.zig | 178 ++++++++++++++++++ src/core/gpio.zig | 2 + src/core/interrupts.zig | 58 ++++++ src/core/microzig.zig | 19 ++ src/core/pin.zig | 2 + .../boards/arduino-nano/arduino-nano.zig | 0 .../boards/mbed-lpc1768/mbed-lpc1768.zig | 0 src/modules/chips/atmega328p/atmega328p.zig | 0 src/modules/chips/lpc1768/lpc1768.zig | 0 src/modules/cpus/avr/avr5.zig | 0 src/modules/cpus/avr/linker.ld | 31 +++ src/modules/cpus/cortex-m3/cortex-m3.zig | 0 src/modules/cpus/cortex-m3/linker.ld | 79 ++++++++ src/tools/linkerscript-gen.zig | 20 ++ tests/minimal.zig | 8 + 17 files changed, 399 insertions(+) create mode 100644 .gitattributes create mode 100644 .gitignore create mode 100644 build.zig create mode 100644 src/core/gpio.zig create mode 100644 src/core/interrupts.zig create mode 100644 src/core/microzig.zig create mode 100644 src/core/pin.zig create mode 100644 src/modules/boards/arduino-nano/arduino-nano.zig create mode 100644 src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig create mode 100644 src/modules/chips/atmega328p/atmega328p.zig create mode 100644 src/modules/chips/lpc1768/lpc1768.zig create mode 100644 src/modules/cpus/avr/avr5.zig create mode 100644 src/modules/cpus/avr/linker.ld create mode 100644 src/modules/cpus/cortex-m3/cortex-m3.zig create mode 100644 src/modules/cpus/cortex-m3/linker.ld create mode 100644 src/tools/linkerscript-gen.zig create mode 100644 tests/minimal.zig diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..0cb064a --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +*.zig text=auto eol=lf diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3cef7be --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +zig-cache/ diff --git a/build.zig b/build.zig new file mode 100644 index 0000000..2d315ba --- /dev/null +++ b/build.zig @@ -0,0 +1,178 @@ +//! Some words on the build script here: +//! We cannot use a test runner here as we're building for freestanding. +//! This means we need to use addExecutable() instead of using + +const std = @import("std"); + +const Board = struct { + name: []const u8, + path: []const u8, + chip: Chip, +}; + +const Chip = struct { + name: []const u8, + path: []const u8, + cpu: Cpu, +}; + +const Cpu = struct { + name: []const u8, + path: []const u8, + target: std.zig.CrossTarget, + linker_script: []const u8, +}; + +pub const Backing = union(enum) { + board: Board, + chip: Chip, +}; + +fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) *std.build.LibExeObjStep { + const Pkg = std.build.Pkg; + + const exe = builder.addExecutable(name, source); + + // TODO: + // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. + // - This requires building another tool that runs on the host that compiles those files and emits the linker script. + // - src/tools/linkerscript-gen.zig is the source file for this + + exe.bundle_compiler_rt = false; + + switch (backing) { + .chip => |chip| { + exe.addBuildOption(bool, "microzig_has_board", false); + exe.addBuildOption([]const u8, "microzig_chip_name", chip.name); + exe.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); + exe.setTarget(chip.cpu.target); + exe.setLinkerScriptPath(chip.cpu.linker_script); + exe.addPackage(Pkg{ + .name = "microzig", + .path = "src/core/microzig.zig", + .dependencies = &[_]Pkg{ + Pkg{ + .name = "chip", + .path = chip.path, + .dependencies = &[_]Pkg{ + Pkg{ + .name = "cpu", + .path = chip.cpu.path, + }, + }, + }, + }, + }); + }, + .board => |board| { + exe.addBuildOption(bool, "microzig_has_board", true); + exe.addBuildOption([]const u8, "microzig_board_name", board.name); + exe.addBuildOption([]const u8, "microzig_chip_name", board.chip.name); + exe.addBuildOption([]const u8, "microzig_cpu_name", board.chip.cpu.name); + exe.setTarget(board.chip.cpu.target); + exe.setLinkerScriptPath(board.chip.cpu.linker_script); + exe.addPackage(Pkg{ + .name = "microzig", + .path = "src/core/microzig.zig", + .dependencies = &[_]Pkg{ + Pkg{ + .name = "board", + .path = board.path, + .dependencies = &[_]Pkg{ + Pkg{ + .name = "chip", + .path = board.chip.path, + .dependencies = &[_]Pkg{ + Pkg{ + .name = "cpu", + .path = board.chip.cpu.path, + }, + }, + }, + }, + }, + }, + }); + }, + } + return exe; +} + +const pkgs = struct { + const cpus = struct { + const avr5 = Cpu{ + .name = "avr", + .path = "src/modules/cpus/avr/avr5.zig", + .linker_script = "src/modules/cpus/avr/linker.ld", + .target = std.zig.CrossTarget{ + .cpu_arch = .avr, + .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + }; + const cortex_m3 = Cpu{ + .name = "cortex-m3", + .path = "src/modules/cpus/cortex-m3/cortex-m3.zig", + .linker_script = "src/modules/cpus/cortex-m3/linker.ld", + .target = std.zig.CrossTarget{ + .cpu_arch = .arm, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .eabi, + }, + }; + }; + + const chips = struct { + const atmega328p = Chip{ + .name = "AtMega328p", + .path = "src/modules/chips/atmega328p/atmega328p.zig", + .cpu = cpus.avr5, + }; + const lpc1768 = Chip{ + .name = "mcu", + .path = "src/modules/chips/lpc1768/lpc1768.zig", + .cpu = cpus.cortex_m3, + }; + }; + + const boards = struct { + const arduino_nano = Board{ + .name = "board", + .path = "src/modules/boards/arduino-nano/arduino-nano.zig", + .chip = chips.atmega328p, + }; + const mbed_lpc1768 = Board{ + .name = "mbed LPC1768", + .path = "src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig", + .chip = chips.lpc1768, + }; + }; +}; + +pub fn build(b: *std.build.Builder) void { + const mode = b.standardReleaseOptions(); + + const test_step = b.step("test", "Builds and runs the library test suite"); + + const BuildConfig = struct { name: []const u8, backing: Backing }; + const all_backings = [_]BuildConfig{ + BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, + BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = pkgs.boards.mbed_lpc1768 } }, + BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, + BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, + }; + + inline for (all_backings) |cfg| { + const exe = addEmbeddedExecutable( + b, + "test-minimal-" ++ cfg.name, + "tests/minimal.zig", + cfg.backing, + ); + exe.setBuildMode(mode); + + test_step.dependOn(&exe.step); + } +} diff --git a/src/core/gpio.zig b/src/core/gpio.zig new file mode 100644 index 0000000..718e6fb --- /dev/null +++ b/src/core/gpio.zig @@ -0,0 +1,2 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); diff --git a/src/core/interrupts.zig b/src/core/interrupts.zig new file mode 100644 index 0000000..27d158a --- /dev/null +++ b/src/core/interrupts.zig @@ -0,0 +1,58 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); + +/// Unmasks the given interrupt and enables its execution. +/// Note that interrupts must be globally enabled with `sei()` as well. +pub fn enable(comptime interrupt: anytype) void { + @panic("not implemented yet!"); +} + +/// Masks the given interrupt and disables its execution. +pub fn disable(comptime interrupt: anytype) void { + @panic("not implemented yet!"); +} + +/// Returns true when the given interrupt is unmasked. +pub fn isEnabled(comptime interrupt: anytype) bool { + @panic("not implemented yet!"); +} + +/// *Set Enable Interrupt*, will enable IRQs globally, but keep the masking done via +/// `enable` and `disable` intact. +pub fn sei() void { + @panic("not implemented yet!"); +} + +/// *Clear Enable Interrupt*, will disable IRQs globally, but keep the masking done via +/// `enable` and `disable` intact. +pub fn cli() void { + @panic("not implemented yet!"); +} + +/// Returns true, when interrupts are globally enabled via `sei()`. +pub fn areGloballyEnabled() bool { + @panic("not implemented yet!"); +} + +/// Enters a critical section and disables interrupts globally. +/// Call `.leave()` on the return value to restore the previous state. +pub fn enterCriticalSection() CriticalSection { + var section = CriticalSection{ + .enable_on_leave = areGloballyEnabled(), + }; + cli(); + return section; +} + +/// A critical section structure that allows restoring the interrupt +/// status that was set before entering. +const CriticalSection = struct { + enable_on_leave: bool, + + /// Leaves the critical section and restores the interrupt state. + pub fn leave(self: @This()) void { + if (self.enable_on_leave) { + sei(); + } + } +}; diff --git a/src/core/microzig.zig b/src/core/microzig.zig new file mode 100644 index 0000000..463db09 --- /dev/null +++ b/src/core/microzig.zig @@ -0,0 +1,19 @@ +const std = @import("std"); + +/// Module that helps with interrupt handling. +pub const interrupts = @import("interrupts.zig"); + +/// The microzig panic handler. Will disable interrupts and loop endlessly. +/// Export this symbol from your main file to enable microzig: +/// ``` +/// const micro = @import("microzig"); +/// pub const panic = micro.panic; +/// ``` +pub fn panic(message: []const u8, stack_trace: ?*std.builtin.StackTrace) noreturn { + while (true) { + interrupts.cli(); + + // "this loop has side effects, don't optimize the endless loop away please. thanks!" + asm volatile ("" ::: "memory"); + } +} diff --git a/src/core/pin.zig b/src/core/pin.zig new file mode 100644 index 0000000..718e6fb --- /dev/null +++ b/src/core/pin.zig @@ -0,0 +1,2 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); diff --git a/src/modules/boards/arduino-nano/arduino-nano.zig b/src/modules/boards/arduino-nano/arduino-nano.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/cpus/avr/linker.ld b/src/modules/cpus/avr/linker.ld new file mode 100644 index 0000000..f17cabd --- /dev/null +++ b/src/modules/cpus/avr/linker.ld @@ -0,0 +1,31 @@ +MEMORY +{ + flash (rx) : ORIGIN = 0, LENGTH = 32K + ram (rw!x) : ORIGIN = 0x800100, LENGTH = 2K +} + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + } > flash + + .data : + { + __data_start = .; + *(.rodata*) + *(.data*) + __data_end = .; + } > ram AT> flash + + .bss (NOLOAD) : + { + __bss_start = .; + *(.bss*) + __bss_end = .; + } > ram + + __data_load_start = LOADADDR(.data); +} \ No newline at end of file diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/modules/cpus/cortex-m3/linker.ld b/src/modules/cpus/cortex-m3/linker.ld new file mode 100644 index 0000000..17b070a --- /dev/null +++ b/src/modules/cpus/cortex-m3/linker.ld @@ -0,0 +1,79 @@ +MEMORY +{ + flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k + ram0 (rw!x) : ORIGIN = 0x10000000, LENGTH = 32k + ram1 (rw!x) : ORIGIN = 0x2007C000, LENGTH = 32k +} +SECTIONS +{ + . = 0; + /* Code-Speicher im Flash ***********/ + .text : + { + __code_start__ = .; + + LONG( ORIGIN(ram1) + LENGTH(ram1) ) + KEEP(*( .isr_vector )); + + *(.text) + *(.text.*) + + . = ALIGN(4); + __code_end__ = .; + + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + + } >flash + + . = ALIGN(4); + + /* contains unwinding information */ + .ARM.exidx : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + . = ALIGN(4); + } >flash + + . = ALIGN(4); + + /* Konstanten im Flash ****************/ + .rodata . : + { + . = ALIGN(4); + *(.rodata) + . = ALIGN(4); + *(.rodata.*) + } >flash + + . = ALIGN(4); + + PROVIDE (__text__end = .); + + .data : AT (__text__end) + { + PROVIDE (__data__start = .); + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + PROVIDE (__data__end = .); + } >ram0 + + .bss : + { + PROVIDE (__bss__start = .); + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b*) + . = ALIGN(4); + PROVIDE (__bss__end = .); + } >ram0 + + _end = .; + PROVIDE (end = .); +} \ No newline at end of file diff --git a/src/tools/linkerscript-gen.zig b/src/tools/linkerscript-gen.zig new file mode 100644 index 0000000..c3266df --- /dev/null +++ b/src/tools/linkerscript-gen.zig @@ -0,0 +1,20 @@ +const std = @import("std"); + +const chip = @import("chip"); + +pub fn main() !u8 { + var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator); + + const allocator = &arena.deinit(); + + const args = try std.process.argsAlloc(allocator); + if (args.len < 2) { + std.log.err("Missing CLI argument. Give the output file name!"); + return 1; + } + + var dest_file = try std.fs.cwd().createFile(args[1], .{}); + defer dest_file.close(); + + try dest_file.writeAll("THIS FILE IS NOT USABLE YET!"); +} diff --git a/tests/minimal.zig b/tests/minimal.zig new file mode 100644 index 0000000..9ad7f13 --- /dev/null +++ b/tests/minimal.zig @@ -0,0 +1,8 @@ +const micro = @import("microzig"); + +// this will instantiate microzig and pull in all dependencies +pub const panic = micro.panic; + +pub fn main() void { + return; +} From e68a2829813f4ce6e2d86164423810c31f84f90c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Wed, 28 Apr 2021 01:22:08 +0200 Subject: [PATCH 004/138] Implements (untested) startup for AVR and LPC1768. --- build.zig | 208 +++++++++++------- src/core/interrupts.zig | 4 +- src/core/microzig.zig | 57 +++++ .../boards/arduino-nano/arduino-nano.zig | 29 +++ .../boards/mbed-lpc1768/mbed-lpc1768.zig | 6 + src/modules/chips/atmega328p/atmega328p.zig | 8 + src/modules/chips/lpc1768/lpc1768.zig | 9 + src/modules/cpus/avr/avr5.zig | 106 +++++++++ src/modules/cpus/avr/linker.ld | 31 --- src/modules/cpus/cortex-m3/cortex-m3.zig | 85 +++++++ src/modules/cpus/cortex-m3/linker.ld | 79 ------- src/modules/linker/linker.zig | 20 ++ src/tools/linkerscript-gen.zig | 126 ++++++++++- tests/minimal.zig | 2 +- 14 files changed, 571 insertions(+), 199 deletions(-) delete mode 100644 src/modules/cpus/avr/linker.ld delete mode 100644 src/modules/cpus/cortex-m3/linker.ld create mode 100644 src/modules/linker/linker.zig diff --git a/build.zig b/build.zig index 2d315ba..3f3dda7 100644 --- a/build.zig +++ b/build.zig @@ -4,35 +4,106 @@ const std = @import("std"); -const Board = struct { - name: []const u8, - path: []const u8, - chip: Chip, -}; +pub fn build(b: *std.build.Builder) void { + const mode = b.standardReleaseOptions(); -const Chip = struct { - name: []const u8, - path: []const u8, - cpu: Cpu, -}; + const test_step = b.step("test", "Builds and runs the library test suite"); -const Cpu = struct { - name: []const u8, - path: []const u8, - target: std.zig.CrossTarget, - linker_script: []const u8, -}; + const BuildConfig = struct { name: []const u8, backing: Backing }; + const all_backings = [_]BuildConfig{ + BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, + BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = pkgs.boards.mbed_lpc1768 } }, + BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, + BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, + }; -pub const Backing = union(enum) { - board: Board, - chip: Chip, -}; + inline for (all_backings) |cfg| { + const exe = addEmbeddedExecutable( + b, + "test-minimal-" ++ cfg.name, + "tests/minimal.zig", + cfg.backing, + ); + exe.setBuildMode(mode); + exe.install(); + + test_step.dependOn(&exe.step); + } +} fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) *std.build.LibExeObjStep { const Pkg = std.build.Pkg; + const chip = switch (backing) { + .chip => |c| c, + .board => |b| b.chip, + }; + + const chip_package = Pkg{ + .name = "chip", + .path = chip.path, + .dependencies = &[_]Pkg{ + Pkg{ + .name = "cpu", + .path = chip.cpu.path, + }, + Pkg{ + .name = "microzig-linker", + .path = "src/modules/linker/linker.zig", + }, + }, + }; + + const linker_script_name = blk: { + const hash = hash_blk: { + var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); + + hasher.update(chip.name); + hasher.update(chip.path); + hasher.update(chip.cpu.name); + hasher.update(chip.cpu.path); + + var mac: [16]u8 = undefined; + hasher.final(&mac); + break :hash_blk mac; + }; + + const file_prefix = "zig-cache/microzig/"; + const file_suffix = ".ld"; + + var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; + const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + file_prefix, + std.fmt.fmtSliceHexLower(&hash), + file_suffix, + }) catch unreachable; + + break :blk builder.dupe(filename); + }; + + const linkerscript_gen = builder.addExecutable("linkerscript-gen", "src/tools/linkerscript-gen.zig"); + linkerscript_gen.addPackage(chip_package); + linkerscript_gen.addPackage(Pkg{ + .name = "microzig-linker", + .path = "src/modules/linker/linker.zig", + }); + linkerscript_gen.addBuildOption([]const u8, "microzig_chip_name", chip.name); + linkerscript_gen.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); + linkerscript_gen.addBuildOption([]const u8, "microzig_target_triple", chip.cpu.target.zigTriple(builder.allocator) catch unreachable); + + const linkerscript_invocation = linkerscript_gen.run(); + linkerscript_invocation.addArg(linker_script_name); + const exe = builder.addExecutable(name, source); + // might not be true for all machines (Pi Pico), but + // for the HAL it's true (it doesn't know the concept of threading) + exe.single_threaded = true; + exe.setTarget(chip.cpu.target); + + exe.setLinkerScriptPath(linker_script_name); + exe.step.dependOn(&linkerscript_invocation.step); + // TODO: // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. @@ -41,55 +112,30 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: exe.bundle_compiler_rt = false; switch (backing) { - .chip => |chip| { + .chip => { exe.addBuildOption(bool, "microzig_has_board", false); exe.addBuildOption([]const u8, "microzig_chip_name", chip.name); exe.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); - exe.setTarget(chip.cpu.target); - exe.setLinkerScriptPath(chip.cpu.linker_script); exe.addPackage(Pkg{ .name = "microzig", .path = "src/core/microzig.zig", - .dependencies = &[_]Pkg{ - Pkg{ - .name = "chip", - .path = chip.path, - .dependencies = &[_]Pkg{ - Pkg{ - .name = "cpu", - .path = chip.cpu.path, - }, - }, - }, - }, + .dependencies = &[_]Pkg{chip_package}, }); }, .board => |board| { exe.addBuildOption(bool, "microzig_has_board", true); exe.addBuildOption([]const u8, "microzig_board_name", board.name); - exe.addBuildOption([]const u8, "microzig_chip_name", board.chip.name); - exe.addBuildOption([]const u8, "microzig_cpu_name", board.chip.cpu.name); - exe.setTarget(board.chip.cpu.target); - exe.setLinkerScriptPath(board.chip.cpu.linker_script); + exe.addBuildOption([]const u8, "microzig_chip_name", chip.name); + exe.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); exe.addPackage(Pkg{ .name = "microzig", .path = "src/core/microzig.zig", .dependencies = &[_]Pkg{ + chip_package, Pkg{ .name = "board", .path = board.path, - .dependencies = &[_]Pkg{ - Pkg{ - .name = "chip", - .path = board.chip.path, - .dependencies = &[_]Pkg{ - Pkg{ - .name = "cpu", - .path = board.chip.cpu.path, - }, - }, - }, - }, + .dependencies = &[_]Pkg{chip_package}, }, }, }); @@ -98,10 +144,34 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: return exe; } +const Board = struct { + name: []const u8, + path: []const u8, + chip: Chip, +}; + +const Chip = struct { + name: []const u8, + path: []const u8, + cpu: Cpu, +}; + +const Cpu = struct { + name: []const u8, + path: []const u8, + target: std.zig.CrossTarget, + linker_script: []const u8, +}; + +pub const Backing = union(enum) { + board: Board, + chip: Chip, +}; + const pkgs = struct { const cpus = struct { const avr5 = Cpu{ - .name = "avr", + .name = "AVR5", .path = "src/modules/cpus/avr/avr5.zig", .linker_script = "src/modules/cpus/avr/linker.ld", .target = std.zig.CrossTarget{ @@ -112,7 +182,7 @@ const pkgs = struct { }, }; const cortex_m3 = Cpu{ - .name = "cortex-m3", + .name = "ARM Cortex-M3", .path = "src/modules/cpus/cortex-m3/cortex-m3.zig", .linker_script = "src/modules/cpus/cortex-m3/linker.ld", .target = std.zig.CrossTarget{ @@ -126,12 +196,12 @@ const pkgs = struct { const chips = struct { const atmega328p = Chip{ - .name = "AtMega328p", + .name = "ATmega328p", .path = "src/modules/chips/atmega328p/atmega328p.zig", .cpu = cpus.avr5, }; const lpc1768 = Chip{ - .name = "mcu", + .name = "NXP LPC1768", .path = "src/modules/chips/lpc1768/lpc1768.zig", .cpu = cpus.cortex_m3, }; @@ -139,7 +209,7 @@ const pkgs = struct { const boards = struct { const arduino_nano = Board{ - .name = "board", + .name = "Arduino Nano", .path = "src/modules/boards/arduino-nano/arduino-nano.zig", .chip = chips.atmega328p, }; @@ -150,29 +220,3 @@ const pkgs = struct { }; }; }; - -pub fn build(b: *std.build.Builder) void { - const mode = b.standardReleaseOptions(); - - const test_step = b.step("test", "Builds and runs the library test suite"); - - const BuildConfig = struct { name: []const u8, backing: Backing }; - const all_backings = [_]BuildConfig{ - BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, - BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = pkgs.boards.mbed_lpc1768 } }, - BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, - BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, - }; - - inline for (all_backings) |cfg| { - const exe = addEmbeddedExecutable( - b, - "test-minimal-" ++ cfg.name, - "tests/minimal.zig", - cfg.backing, - ); - exe.setBuildMode(mode); - - test_step.dependOn(&exe.step); - } -} diff --git a/src/core/interrupts.zig b/src/core/interrupts.zig index 27d158a..8ca66bc 100644 --- a/src/core/interrupts.zig +++ b/src/core/interrupts.zig @@ -20,13 +20,13 @@ pub fn isEnabled(comptime interrupt: anytype) bool { /// *Set Enable Interrupt*, will enable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. pub fn sei() void { - @panic("not implemented yet!"); + micro.chip.cpu.sei(); } /// *Clear Enable Interrupt*, will disable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. pub fn cli() void { - @panic("not implemented yet!"); + micro.chip.cpu.cli(); } /// Returns true, when interrupts are globally enabled via `sei()`. diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 463db09..3c5ee8f 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -1,4 +1,11 @@ const std = @import("std"); +const root = @import("root"); + +/// Provides access to the low level features of the current microchip. +pub const chip = @import("chip"); + +/// Provides access to the low level features of the CPU. +pub const cpu = chip.cpu; /// Module that helps with interrupt handling. pub const interrupts = @import("interrupts.zig"); @@ -10,6 +17,11 @@ pub const interrupts = @import("interrupts.zig"); /// pub const panic = micro.panic; /// ``` pub fn panic(message: []const u8, stack_trace: ?*std.builtin.StackTrace) noreturn { + hang(); +} + +/// Hangs the processor and will stop doing anything useful. Use with caution! +pub fn hang() noreturn { while (true) { interrupts.cli(); @@ -17,3 +29,48 @@ pub fn panic(message: []const u8, stack_trace: ?*std.builtin.StackTrace) noretur asm volatile ("" ::: "memory"); } } + +/// This is the logical entry point for microzig. +/// It will invoke the main function from the root source file +/// and provides error return handling as well as a event loop if requested. +/// +/// Why is this function exported? +/// This is due to the modular design of microzig to allow the "chip" dependency of microzig +/// to call into our main function here. If we would use a normal function call, we'd have a +/// circular dependency between the `microzig` and `chip` package. This function is also likely +/// to be invoked from assembly, so it's also convenient in that regard. +export fn microzig_main() noreturn { + if (!@hasDecl(root, "main")) + @compileError("The root source file must provide a public function main!"); + + const main = @field(root, "main"); + const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); + + const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; + if (info != .Fn or info.Fn.args.len > 0) + @compileError(invalid_main_msg); + + const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); + + if (info.Fn.calling_convention == .Async) + @compileError("TODO: Embedded event loop not supported yet. Please try again later."); + + if (@typeInfo(return_type) == .ErrorUnion) { + main() catch |err| { + // TODO: + // - Compute maximum size on the type of "err" + // - Do not emit error names when std.builtin.strip is set. + var msg: [64]u8 = undefined; + @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@tagName(err)}) catch @panic("main() returned error.")); + }; + } else { + main(); + } + + // main returned, just hang around here a bit + hang(); +} + +comptime { + _ = cpu.startup_logic; +} diff --git a/src/modules/boards/arduino-nano/arduino-nano.zig b/src/modules/boards/arduino-nano/arduino-nano.zig index e69de29..c622669 100644 --- a/src/modules/boards/arduino-nano/arduino-nano.zig +++ b/src/modules/boards/arduino-nano/arduino-nano.zig @@ -0,0 +1,29 @@ +pub const chip = @import("chip"); + +pub const pin_map = .{ + // Port A + .D0 = "PD0", + .D1 = "PD1", + .D2 = "PD2", + .D3 = "PD3", + .D4 = "PD4", + .D5 = "PD5", + .D6 = "PD6", + .D7 = "PD7", + // Port B + .D8 = "PB0", + .D9 = "PB1", + .D10 = "PB2", + .D11 = "PB3", + .D12 = "PB4", + .D13 = "PB5", + // Port C (Analog) + .A0 = "PC0", + .A1 = "PC1", + .A2 = "PC2", + .A3 = "PC3", + .A4 = "PC4", + .A5 = "PC5", + .A6 = "ADC6", + .A7 = "ADC7", +}; diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig index e69de29..09e63c0 100644 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig @@ -0,0 +1,6 @@ +pub const chip = @import("chip"); +pub const chip = @import("chip"); + +pub const pin_map = .{ + // TODO: Fill this +}; diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index e69de29..3277db7 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -0,0 +1,8 @@ +const micro_linker = @import("microzig-linker"); + +pub const cpu = @import("cpu"); + +pub const memory_regions = [_]micro_linker.MemoryRegion{ + micro_linker.MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, + micro_linker.MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, +}; diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index e69de29..5fa7874 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -0,0 +1,9 @@ +const micro_linker = @import("microzig-linker"); + +pub const cpu = @import("cpu"); + +pub const memory_regions = [_]micro_linker.MemoryRegion{ + micro_linker.MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, + micro_linker.MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, + micro_linker.MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, +}; diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index e69de29..9994b74 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -0,0 +1,106 @@ +const std = @import("std"); + +pub fn sei() void { + asm volatile ("sei"); +} + +pub fn cli() void { + asm volatile ("cli"); +} + +pub const startup_logic = struct { + comptime { + asm ( + \\.section microzig_flash_start + \\ jmp _start + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + \\ jmp _unhandled_vector + ); + } + + export fn _unhandled_vector() callconv(.Naked) noreturn { + @panic("Unhandled interrupt"); + } + + extern fn microzig_main() noreturn; + + export fn _start() callconv(.Naked) noreturn { + // At startup the stack pointer is at the end of RAM + // so, no need to set it manually! + + copy_data_to_ram(); + clear_bss(); + + microzig_main(); + } + + fn copy_data_to_ram() void { + asm volatile ( + \\ ; load Z register with the address of the data in flash + \\ ldi r30, lo8(microzig_data_load_start) + \\ ldi r31, hi8(microzig_data_load_start) + \\ ; load X register with address of the data in ram + \\ ldi r26, lo8(microzig_data_start) + \\ ldi r27, hi8(microzig_data_start) + \\ ; load address of end of the data in ram + \\ ldi r24, lo8(microzig_data_end) + \\ ldi r25, hi8(microzig_data_end) + \\ rjmp .L2 + \\ + \\.L1: + \\ lpm r18, Z+ ; copy from Z into r18 and increment Z + \\ st X+, r18 ; store r18 at location X and increment X + \\ + \\.L2: + \\ cp r26, r24 + \\ cpc r27, r25 ; check and branch if we are at the end of data + \\ brne .L1 + ); + // Probably a good idea to add clobbers here, but compiler doesn't seem to care + } + + fn clear_bss() void { + asm volatile ( + \\ ; load X register with the beginning of bss section + \\ ldi r26, lo8(microzig_bss_start) + \\ ldi r27, hi8(microzig_bss_start) + \\ ; load end of the bss in registers + \\ ldi r24, lo8(microzig_bss_end) + \\ ldi r25, hi8(microzig_bss_end) + \\ ldi r18, 0x00 + \\ rjmp .L4 + \\ + \\.L3: + \\ st X+, r18 + \\ + \\.L4: + \\ cp r26, r24 + \\ cpc r27, r25 ; check and branch if we are at the end of bss + \\ brne .L3 + ); + // Probably a good idea to add clobbers here, but compiler doesn't seem to care + } +}; diff --git a/src/modules/cpus/avr/linker.ld b/src/modules/cpus/avr/linker.ld deleted file mode 100644 index f17cabd..0000000 --- a/src/modules/cpus/avr/linker.ld +++ /dev/null @@ -1,31 +0,0 @@ -MEMORY -{ - flash (rx) : ORIGIN = 0, LENGTH = 32K - ram (rw!x) : ORIGIN = 0x800100, LENGTH = 2K -} - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - } > flash - - .data : - { - __data_start = .; - *(.rodata*) - *(.data*) - __data_end = .; - } > ram AT> flash - - .bss (NOLOAD) : - { - __bss_start = .; - *(.bss*) - __bss_end = .; - } > ram - - __data_load_start = LOADADDR(.data); -} \ No newline at end of file diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig index e69de29..b1f6d7a 100644 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ b/src/modules/cpus/cortex-m3/cortex-m3.zig @@ -0,0 +1,85 @@ +const std = @import("std"); + +pub fn sei() void { + __enable_irq(); +} + +pub fn cli() void { + __disable_irq(); +} + +pub fn __enable_irq() void { + asm volatile ("cpsie i"); +} +pub fn __disable_irq() void { + asm volatile ("cpsid i"); +} + +pub fn __enable_fault_irq() void { + asm volatile ("cpsie f"); +} +pub fn __disable_fault_irq() void { + asm volatile ("cpsid f"); +} + +pub fn __NOP() void { + asm volatile ("nop"); +} +pub fn __WFI() void { + asm volatile ("wfi"); +} +pub fn __WFE() void { + asm volatile ("wfe"); +} +pub fn __SEV() void { + asm volatile ("sev"); +} +pub fn __ISB() void { + asm volatile ("isb"); +} +pub fn __DSB() void { + asm volatile ("dsb"); +} +pub fn __DMB() void { + asm volatile ("dmb"); +} +pub fn __CLREX() void { + asm volatile ("clrex"); +} + +pub const startup_logic = struct { + const InterruptVector = fn () callconv(.C) void; + + const VectorTable = extern struct { + initial_stack_pointer: u32, + reset: InterruptVector, + nmi: InterruptVector = unhandledInterrupt, + hard_fault: InterruptVector = unhandledInterrupt, + mpu_fault: InterruptVector = unhandledInterrupt, + bus_fault: InterruptVector = unhandledInterrupt, + usage_fault: InterruptVector = unhandledInterrupt, + + reserved: u32 = 0, + }; + + export const vectors linksection("microzig_flash_start") = VectorTable{ + // TODO: How to compute/get the initial stack pointer? + .initial_stack_pointer = 0x1000_7FFC, // HACK: hardcoded, do not keep! + .reset = _start, + }; + + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + + extern fn microzig_main() noreturn; + + fn _start() callconv(.C) noreturn { + + // TODO: + // - Load .data + // - Clear .bss + + microzig_main(); + } +}; diff --git a/src/modules/cpus/cortex-m3/linker.ld b/src/modules/cpus/cortex-m3/linker.ld deleted file mode 100644 index 17b070a..0000000 --- a/src/modules/cpus/cortex-m3/linker.ld +++ /dev/null @@ -1,79 +0,0 @@ -MEMORY -{ - flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k - ram0 (rw!x) : ORIGIN = 0x10000000, LENGTH = 32k - ram1 (rw!x) : ORIGIN = 0x2007C000, LENGTH = 32k -} -SECTIONS -{ - . = 0; - /* Code-Speicher im Flash ***********/ - .text : - { - __code_start__ = .; - - LONG( ORIGIN(ram1) + LENGTH(ram1) ) - KEEP(*( .isr_vector )); - - *(.text) - *(.text.*) - - . = ALIGN(4); - __code_end__ = .; - - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - - } >flash - - . = ALIGN(4); - - /* contains unwinding information */ - .ARM.exidx : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - . = ALIGN(4); - } >flash - - . = ALIGN(4); - - /* Konstanten im Flash ****************/ - .rodata . : - { - . = ALIGN(4); - *(.rodata) - . = ALIGN(4); - *(.rodata.*) - } >flash - - . = ALIGN(4); - - PROVIDE (__text__end = .); - - .data : AT (__text__end) - { - PROVIDE (__data__start = .); - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - PROVIDE (__data__end = .); - } >ram0 - - .bss : - { - PROVIDE (__bss__start = .); - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b*) - . = ALIGN(4); - PROVIDE (__bss__end = .); - } >ram0 - - _end = .; - PROVIDE (end = .); -} \ No newline at end of file diff --git a/src/modules/linker/linker.zig b/src/modules/linker/linker.zig new file mode 100644 index 0000000..f6508b2 --- /dev/null +++ b/src/modules/linker/linker.zig @@ -0,0 +1,20 @@ +//! This module is meant to be used to define linking apis + +pub const MemoryRegion = struct { + kind: Kind, + offset: u64, + length: u64, + + pub const Kind = union(enum) { + flash, + ram, + custom: RegionSpec, + }; + + pub const RegionSpec = struct { + name: []const u8, + executable: bool, + readable: bool, + writeable: bool, + }; +}; diff --git a/src/tools/linkerscript-gen.zig b/src/tools/linkerscript-gen.zig index c3266df..a23c272 100644 --- a/src/tools/linkerscript-gen.zig +++ b/src/tools/linkerscript-gen.zig @@ -1,20 +1,138 @@ const std = @import("std"); - +const build_options = @import("build_options"); const chip = @import("chip"); +const micro_linker = @import("microzig-linker"); + +const target = blk: { + @setEvalBranchQuota(20_000); + + const t = std.zig.CrossTarget.parse(std.zig.CrossTarget.ParseOptions{ + .arch_os_abi = build_options.microzig_target_triple, + }) catch unreachable; + std.debug.assert(t.cpu_arch != null); + break :blk t; +}; pub fn main() !u8 { var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator); + defer arena.deinit(); - const allocator = &arena.deinit(); + const allocator = &arena.allocator; const args = try std.process.argsAlloc(allocator); + if (args.len < 2) { - std.log.err("Missing CLI argument. Give the output file name!"); + std.log.err("Missing CLI argument. Give the output file name!", .{}); return 1; } + if (std.fs.path.dirname(args[1])) |dir| { + try std.fs.cwd().makePath(dir); + } + var dest_file = try std.fs.cwd().createFile(args[1], .{}); defer dest_file.close(); - try dest_file.writeAll("THIS FILE IS NOT USABLE YET!"); + var writer = dest_file.writer(); + + try writer.writeAll("/*\n * This file was auto-generated by microzig\n *\n"); + try writer.print(" * Target CPU: {s}\n", .{build_options.microzig_cpu_name}); + try writer.print(" * Target Chip: {s}\n", .{build_options.microzig_chip_name}); + try writer.writeAll(" */\n\n"); + + try writer.writeAll( + \\ + // This is not the "true" entry point, but there's no such thing on embedded platforms + // anyways. This is the logical entrypoint that should be invoked when + // stack, .data and .bss are set up and the CPU is ready to be used. + \\ENTRY(microzig_main); + \\ + \\ + ); + + try writer.writeAll("MEMORY\n{\n"); + { + var counters = [2]usize{ 0, 0 }; + for (chip.memory_regions) |region| { + // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k + + switch (region.kind) { + .flash => { + try writer.print(" flash{d} (rx!w)", .{counters[0]}); + counters[0] += 1; + }, + .ram => { + try writer.print(" ram{d} (rw!x)", .{counters[1]}); + counters[1] += 1; + }, + .custom => |custom| { + try writer.print(" {s} (", .{custom.name}); + if (custom.readable) try writer.writeAll("r"); + if (custom.writeable) try writer.writeAll("w"); + if (custom.executable) try writer.writeAll("x"); + + if (!custom.readable or !custom.writeable or !custom.executable) { + try writer.writeAll("!"); + if (!custom.readable) try writer.writeAll("r"); + if (!custom.writeable) try writer.writeAll("w"); + if (!custom.executable) try writer.writeAll("x"); + } + try writer.writeAll(")"); + }, + } + try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length }); + } + } + + try writer.writeAll("}\n\nSECTIONS\n{\n"); + { + try writer.writeAll( + \\ .text : + \\ { + \\ KEEP(*(microzig_flash_start)) + \\ *(.text*) + \\ } > flash0 + \\ + \\ + ); + + if (target.cpu_arch.? == .arm or target.cpu_arch.? == .thumb) { + try writer.writeAll( + \\ .ARM.exidx : { + \\ *(.ARM.exidx* .gnu.linkonce.armexidx.*) + \\ } >flash0 + \\ + \\ + ); + } + + try writer.writeAll( + \\ .data : + \\ { + \\ microzig_data_start = .; + \\ *(.rodata*) + \\ *(.data*) + \\ microzig_data_end = .; + \\ } > ram0 AT> flash0 + \\ + \\ .bss (NOLOAD) : + \\ { + \\ microzig_bss_start = .; + \\ *(.bss*) + \\ microzig_bss_end = .; + \\ } > ram0 + \\ + \\ microzig_data_load_start = LOADADDR(.data); + \\ + ); + } + try writer.writeAll("}\n"); + + // TODO: Assert that the flash can actually hold all data! + // try writer.writeAll( + // \\ + // \\ ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" ); + // \\ + // ); + return 0; } diff --git a/tests/minimal.zig b/tests/minimal.zig index 9ad7f13..17a2105 100644 --- a/tests/minimal.zig +++ b/tests/minimal.zig @@ -4,5 +4,5 @@ const micro = @import("microzig"); pub const panic = micro.panic; pub fn main() void { - return; + // This function will contain the application logic. } From 6cdf641f32de994b12f5e7507700726486147f35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Wed, 28 Apr 2021 22:36:29 +0200 Subject: [PATCH 005/138] Continues blinky setup. --- build.zig | 92 ++++++++++--- src/core/gpio.zig | 122 ++++++++++++++++++ src/core/microzig.zig | 11 ++ src/core/pin.zig | 32 +++++ .../boards/mbed-lpc1768/mbed-lpc1768.zig | 47 ++++++- src/modules/chips/atmega328p/atmega328p.zig | 46 +++++++ src/modules/chips/lpc1768/lpc1768.zig | 47 +++++++ tests/blinky.zig | 37 ++++++ 8 files changed, 414 insertions(+), 20 deletions(-) create mode 100644 tests/blinky.zig diff --git a/build.zig b/build.zig index 3f3dda7..02b841b 100644 --- a/build.zig +++ b/build.zig @@ -17,17 +17,25 @@ pub fn build(b: *std.build.Builder) void { BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, }; + const Test = struct { name: []const u8, source: []const u8 }; + const all_tests = [_]Test{ + Test{ .name = "minimal", .source = "tests/minimal.zig" }, + Test{ .name = "blinky", .source = "tests/blinky.zig" }, + }; + inline for (all_backings) |cfg| { - const exe = addEmbeddedExecutable( - b, - "test-minimal-" ++ cfg.name, - "tests/minimal.zig", - cfg.backing, - ); - exe.setBuildMode(mode); - exe.install(); - - test_step.dependOn(&exe.step); + inline for (all_tests) |tst| { + const exe = addEmbeddedExecutable( + b, + "test-" ++ tst.name ++ "-" ++ cfg.name, + tst.source, + cfg.backing, + ); + exe.setBuildMode(mode); + exe.install(); + + test_step.dependOn(&exe.step); + } } } @@ -39,6 +47,8 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: .board => |b| b.chip, }; + const has_board = (backing == .board); + const chip_package = Pkg{ .name = "chip", .path = chip.path, @@ -81,6 +91,58 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: break :blk builder.dupe(filename); }; + const config_file_name = blk: { + const hash = hash_blk: { + var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); + + hasher.update(chip.name); + hasher.update(chip.path); + hasher.update(chip.cpu.name); + hasher.update(chip.cpu.path); + + if (backing == .board) { + hasher.update(backing.board.name); + hasher.update(backing.board.path); + } + + var mac: [16]u8 = undefined; + hasher.final(&mac); + break :hash_blk mac; + }; + + const file_prefix = "zig-cache/microzig/config-"; + const file_suffix = ".zig"; + + var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; + const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + file_prefix, + std.fmt.fmtSliceHexLower(&hash), + file_suffix, + }) catch unreachable; + + break :blk builder.dupe(filename); + }; + + { + var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; + defer config_file.close(); + + var writer = config_file.writer(); + + writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; + if (has_board) { + writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; + } + + writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; + writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + } + + const config_pkg = Pkg{ + .name = "microzig-config", + .path = config_file_name, + }; + const linkerscript_gen = builder.addExecutable("linkerscript-gen", "src/tools/linkerscript-gen.zig"); linkerscript_gen.addPackage(chip_package); linkerscript_gen.addPackage(Pkg{ @@ -113,24 +175,18 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: switch (backing) { .chip => { - exe.addBuildOption(bool, "microzig_has_board", false); - exe.addBuildOption([]const u8, "microzig_chip_name", chip.name); - exe.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); exe.addPackage(Pkg{ .name = "microzig", .path = "src/core/microzig.zig", - .dependencies = &[_]Pkg{chip_package}, + .dependencies = &[_]Pkg{ config_pkg, chip_package }, }); }, .board => |board| { - exe.addBuildOption(bool, "microzig_has_board", true); - exe.addBuildOption([]const u8, "microzig_board_name", board.name); - exe.addBuildOption([]const u8, "microzig_chip_name", chip.name); - exe.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); exe.addPackage(Pkg{ .name = "microzig", .path = "src/core/microzig.zig", .dependencies = &[_]Pkg{ + config_pkg, chip_package, Pkg{ .name = "board", diff --git a/src/core/gpio.zig b/src/core/gpio.zig index 718e6fb..fc5665f 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -1,2 +1,124 @@ const std = @import("std"); const micro = @import("microzig.zig"); +const chip = @import("chip"); + +pub const Mode = enum { + input, + output, + input_output, + open_drain, + generic, +}; + +pub const State = enum(u1) { + low = 0, + high = 1, +}; + +pub const Drive = enum(u1) { + disabled = 0, + enabled = 1, +}; + +pub const Direction = enum(u1) { + input = 0, + output = 1, +}; + +pub fn Gpio(comptime pin: type, config: anytype) type { + const mode = @as(Mode, config.mode); + const Generic = struct { + // all pins: + fn init() void { + switch (mode) { + .input, .generic, .input_output => { + setDirection(.input, undefined); + }, + .output => { + if (comptime !@hasField(@TypeOf(config), "initial_state")) + @compileError("An output pin requires initial_state to be either .high or .low"); + setDirection(.output, switch (config.initial_state) { + .low => State.low, + .high => State.high, + else => @compileError("An output pin requires initial_state to be either .high or .low"), + }); + }, + .open_drain => { + if (comptime !@hasField(@TypeOf(config), "initial_state")) + @compileError("An open_drain pin requires initial_state to be either .floating or .driven"); + setDirection(.input, undefined); + setDrive(switch (config.initial_state) { + .floating => Drive.disabled, + .driven => Drive.enabled, + else => @compileError("An open_drain pin requires initial_state to be either .floating or .driven"), + }); + }, + } + } + + fn read() State { + return @intToEnum(State, chip.gpio.read(pin.source_pin)); + } + + // outputs: + fn write(state: State) void { + chip.gpio.write(pin.source_pin, @enumToInt(state)); + } + + fn setToHigh() void { + write(.high); + } + fn setToLow() void { + write(.low); + } + fn toggle() void { + if (comptime @hasDecl(chip.gpio, "toggle")) { + chip.gpio.toggle(pin.source_pin); + } else { + write(switch (read()) { + .low => State.high, + .high => State.low, + }); + } + } + + // bi-di: + fn setDirection(dir: Direction, output_state: State) void {} + fn getDirection() Direction {} + + // open drain + fn setDrive(drive: Drive) void {} + fn getDrive() Drive {} + }; + // return only a subset of Generic for the requested pin. + switch (mode) { + .input => return struct { + pub const init = Generic.init; + pub const read = Generic.read; + }, + .output => return struct { + pub const init = Generic.init; + pub const read = Generic.read; + pub const write = Generic.write; + pub const setToHigh = Generic.setToHigh; + pub const setToLow = Generic.setToLow; + pub const toggle = Generic.toggle; + }, + .input_output => return struct { + pub const init = Generic.init; + pub const read = Generic.read; + pub const write = Generic.write; + pub const setToHigh = Generic.setToHigh; + pub const setToLow = Generic.setToLow; + pub const setDirection = Generic.setDirection; + pub const getDirection = Generic.getDirection; + }, + .open_drain => return struct { + pub const init = Generic.init; + pub const read = Generic.read; + pub const setDrive = Generic.setDrive; + pub const getDrive = Generic.getDrive; + }, + .generic => Generic, + } +} diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 3c5ee8f..f3d23ad 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -1,6 +1,11 @@ const std = @import("std"); const root = @import("root"); +/// Contains build-time generated configuration options for microzig. +/// Contains a CPU target description, chip, board and cpu information +/// and so on. +pub const config = @import("microzig-config"); + /// Provides access to the low level features of the current microchip. pub const chip = @import("chip"); @@ -10,6 +15,12 @@ pub const cpu = chip.cpu; /// Module that helps with interrupt handling. pub const interrupts = @import("interrupts.zig"); +const gpio = @import("gpio.zig"); +pub const Gpio = gpio.Gpio; + +const pin = @import("pin.zig"); +pub const Pin = pin.Pin; + /// The microzig panic handler. Will disable interrupts and loop endlessly. /// Export this symbol from your main file to enable microzig: /// ``` diff --git a/src/core/pin.zig b/src/core/pin.zig index 718e6fb..c7c5db4 100644 --- a/src/core/pin.zig +++ b/src/core/pin.zig @@ -1,2 +1,34 @@ const std = @import("std"); const micro = @import("microzig.zig"); +const chip = @import("chip"); +const board = @import("board"); + +/// Returns a type that will manage the Pin defined by `spec`. +/// Spec is either the pin as named in the datasheet of the chip +/// or, if a board is present, as named on the board. +/// +/// When a name conflict happens, pin names can be prefixed with `board:` +/// to force-select a pin from the board and with `chip:` to force-select +/// the pin from the chip. +pub fn Pin(comptime spec: []const u8) type { + // TODO: Depened on board and chip here + + // Pins can be namespaced with "Board:" for board and "Chip:" for chip + const pin = if (std.mem.startsWith(u8, spec, "board:")) + chip.parsePin(@field(board.pin_map, spec)) + else if (std.mem.startsWith(u8, spec, "chip:")) + chip.parsePin(spec) + else if (micro.config.has_board and @hasField(@TypeOf(board.pin_map), spec)) + chip.parsePin(@field(board.pin_map, spec)) + else + chip.parsePin(spec); + + return struct { + pub const name = spec; + pub const source_pin = pin; + + pub fn route(target: pin.Targets) void { + unreachable; + } + }; +} diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig index 09e63c0..4994c7f 100644 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig @@ -1,6 +1,49 @@ pub const chip = @import("chip"); -pub const chip = @import("chip"); pub const pin_map = .{ - // TODO: Fill this + // Onboard-LEDs + .@"LED-1" = "P1.18", + .@"LED-2" = "P1.20", + .@"LED-3" = "P1.21", + .@"LED-4" = "P1.23", + .@"LED_LINK" = "P1.25", + .@"LED_SPEED" = "P1.26", + + // Ethernet + .@"TD+" = "P1.0", + .@"TD-" = "P1.1", + .@"RD+" = "P1.9", + .@"RD-" = "P1.10", + + // USB + .@"D+" = "P0.29", + .@"D-" = "P0.30", + + // GPIO pins + .@"DIP5" = "P0.9", + .@"DIP6" = "P0.8", + .@"DIP7" = "P0.7", + .@"DIP8" = "P0.6", + .@"DIP9" = "P0.0", + .@"DIP10" = "P0.1", + .@"DIP11" = "P0.18", + .@"DIP12" = "P0.17", + .@"DIP13" = "P0.15", + .@"DIP14" = "P0.16", + .@"DIP15" = "P0.23", + .@"DIP16" = "P0.24", + .@"DIP17" = "P0.25", + .@"DIP18" = "P0.26", + .@"DIP19" = "P1.30", + .@"DIP20" = "P1.31", + .@"DIP21" = "P2.5", + .@"DIP22" = "P2.4", + .@"DIP23" = "P2.3", + .@"DIP24" = "P2.2", + .@"DIP25" = "P2.1", + .@"DIP26" = "P2.0", + .@"DIP27" = "P0.11", + .@"DIP28" = "P0.10", + .@"DIP29" = "P0.5", + .@"DIP30" = "P0.4", }; diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 3277db7..876679d 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,3 +1,4 @@ +const std = @import("std"); const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); @@ -6,3 +7,48 @@ pub const memory_regions = [_]micro_linker.MemoryRegion{ micro_linker.MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, micro_linker.MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, }; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme."; + + if (spec.len != 3) + @compileError(invalid_format_msg); + if (spec[0] != 'P') + @compileError(invalid_format_msg); + + return struct { + pub const port: u8 = std.ascii.toUpper(spec[1]) - 'A'; + pub const pin: u3 = @intCast(u3, spec[2] - '0'); + }; +} + +pub const gpio = struct { + fn dirReg(comptime pin: type) *volatile u8 { + return @intToPtr(*volatile u8, 0x01); + } + fn portReg(comptime pin: type) *volatile u8 { + return @intToPtr(*volatile u8, 0x01); + } + fn pinReg(comptime pin: type) *volatile u8 { + return @intToPtr(*volatile u8, 0x01); + } + + pub fn read(comptime pin: type) u1 { + return if ((pinReg(pin).* & (1 << pin.pin)) != 0) + @as(u1, 1) + else + 0; + } + + pub fn write(comptime pin: type, state: u1) void { + if (state == 1) { + portReg(pin).* |= (1 << pin.pin); + } else { + portReg(pin).* &= ~@as(u8, 1 << pin.pin); + } + } + + pub fn toggle(comptime pin: type) void { + portReg(pin).* ^= (1 << pin.pin); + } +}; diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 5fa7874..7bde22e 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -1,3 +1,4 @@ +const std = @import("std"); const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); @@ -7,3 +8,49 @@ pub const memory_regions = [_]micro_linker.MemoryRegion{ micro_linker.MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, micro_linker.MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, }; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme."; + if (spec[0] != 'P') + @compileError(invalid_format_msg); + + const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg); + + return struct { + pub const port: u3 = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); + pub const pin: u5 = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); + + const gpio_register = @intToPtr(*volatile registers.GPIO, registers.gpio_base + 0x20 * @as(u32, port)); + const gpio_mask: u32 = (1 << pin); + }; +} + +pub const gpio = struct { + pub fn read(comptime pin: type) u1 { + return if ((pin.gpio_register.pin & pin.gpio_mask) != 0) + @as(u1, 1) + else + 0; + } + + pub fn write(comptime pin: type, state: u1) void { + if (state == 1) { + pin.gpio_register.set = pin.gpio_mask; + } else { + pin.gpio_register.clr = pin.gpio_mask; + } + } +}; + +pub const registers = struct { + pub const GPIO = extern struct { + dir: u32, // 0x00 + pad: [3]u32, + mask: u32, // 0x10 + pin: u32, // 0x14, + set: u32, // 0x18, + clr: u32, // 0x1C, + }; + + pub const gpio_base = 0x2009_C000; +}; diff --git a/tests/blinky.zig b/tests/blinky.zig new file mode 100644 index 0000000..7b30cee --- /dev/null +++ b/tests/blinky.zig @@ -0,0 +1,37 @@ +const micro = @import("microzig"); + +// this will instantiate microzig and pull in all dependencies +pub const panic = micro.panic; + +// Configures the led_pin to a hardware pin +const led_pin = switch (@import("builtin").cpu.arch) { + .avr => if (micro.config.has_board) + micro.Pin("D13") + else + micro.Pin("PB5"), + .arm => if (micro.config.has_board) + micro.Pin("LED-1") + else + micro.Pin("P1.18"), + else => @compileError("Unsupported platform!"), +}; + +pub fn main() void { + const led = micro.Gpio(led_pin, .{ + .mode = .output, + .initial_state = .low, + }); + led.init(); + + while (true) { + busyloop(); + led.toggle(); + } +} + +fn busyloop() void { + var i: u24 = 0; + while (i < 100_000) : (i += 1) { + @import("std").mem.doNotOptimizeAway(i); + } +} From 26681f7b3098802cb4c0cfc3e3a062a7202773dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Wed, 28 Apr 2021 23:57:39 +0200 Subject: [PATCH 006/138] blinky works for lpc1768 --- .gitignore | 1 + src/core/gpio.zig | 26 +++++++++++++++++--- src/core/interrupts.zig | 8 +++--- src/modules/chips/atmega328p/atmega328p.zig | 7 ++++++ src/modules/chips/lpc1768/lpc1768.zig | 7 ++++++ src/modules/cpus/cortex-m3/cortex-m3.zig | 27 ++++++++++++++++++--- 6 files changed, 65 insertions(+), 11 deletions(-) diff --git a/.gitignore b/.gitignore index 3cef7be..ac2eddc 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,2 @@ zig-cache/ +dev-scripts/ \ No newline at end of file diff --git a/src/core/gpio.zig b/src/core/gpio.zig index fc5665f..bbbe57d 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -83,12 +83,30 @@ pub fn Gpio(comptime pin: type, config: anytype) type { } // bi-di: - fn setDirection(dir: Direction, output_state: State) void {} - fn getDirection() Direction {} + fn setDirection(dir: Direction, output_state: State) void { + switch (dir) { + .output => { + chip.gpio.setOutput(pin.source_pin); + write(output_state); + }, + .input => chip.gpio.setInput(pin.source_pin), + } + } + fn getDirection() Direction { + if (chip.gpio.isOutput(pin.source_pin)) { + return .output; + } else { + return .input; + } + } // open drain - fn setDrive(drive: Drive) void {} - fn getDrive() Drive {} + fn setDrive(drive: Drive) void { + @compileError("open drain not implemented yet!"); + } + fn getDrive() Drive { + @compileError("open drain not implemented yet!"); + } }; // return only a subset of Generic for the requested pin. switch (mode) { diff --git a/src/core/interrupts.zig b/src/core/interrupts.zig index 8ca66bc..10013c4 100644 --- a/src/core/interrupts.zig +++ b/src/core/interrupts.zig @@ -4,17 +4,17 @@ const micro = @import("microzig.zig"); /// Unmasks the given interrupt and enables its execution. /// Note that interrupts must be globally enabled with `sei()` as well. pub fn enable(comptime interrupt: anytype) void { - @panic("not implemented yet!"); + @compileError("not implemented yet!"); } /// Masks the given interrupt and disables its execution. pub fn disable(comptime interrupt: anytype) void { - @panic("not implemented yet!"); + @compileError("not implemented yet!"); } /// Returns true when the given interrupt is unmasked. pub fn isEnabled(comptime interrupt: anytype) bool { - @panic("not implemented yet!"); + @compileError("not implemented yet!"); } /// *Set Enable Interrupt*, will enable IRQs globally, but keep the masking done via @@ -31,7 +31,7 @@ pub fn cli() void { /// Returns true, when interrupts are globally enabled via `sei()`. pub fn areGloballyEnabled() bool { - @panic("not implemented yet!"); + @compileError("not implemented yet!"); } /// Enters a critical section and disables interrupts globally. diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 876679d..3e6b978 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -33,6 +33,13 @@ pub const gpio = struct { return @intToPtr(*volatile u8, 0x01); } + pub fn setOutput(comptime pin: type) void { + dirReg(pin).* |= (1 << pin.pin); + } + pub fn setInput(comptime pin: type) void { + dirReg(pin).* &= ~(@as(u8, 1) << pin.pin); + } + pub fn read(comptime pin: type) u1 { return if ((pinReg(pin).* & (1 << pin.pin)) != 0) @as(u1, 1) diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 7bde22e..ec7e100 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -26,6 +26,13 @@ pub fn parsePin(comptime spec: []const u8) type { } pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + pin.gpio_register.dir |= pin.gpio_mask; + } + pub fn setInput(comptime pin: type) void { + pin.gpio_register.dir &= ~pin.gpio_mask; + } + pub fn read(comptime pin: type) u1 { return if ((pin.gpio_register.pin & pin.gpio_mask) != 0) @as(u1, 1) diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig index b1f6d7a..4c82311 100644 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ b/src/modules/cpus/cortex-m3/cortex-m3.zig @@ -74,11 +74,32 @@ pub const startup_logic = struct { extern fn microzig_main() noreturn; + extern var microzig_data_start: c_void; + extern var microzig_data_end: c_void; + extern var microzig_bss_start: c_void; + extern var microzig_bss_end: c_void; + extern const microzig_data_load_start: c_void; + fn _start() callconv(.C) noreturn { - // TODO: - // - Load .data - // - Clear .bss + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, µzig_bss_start); + const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, µzig_data_start); + const data_end = @ptrCast([*]u8, µzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, µzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } microzig_main(); } From 284d19814d453c942dd296c83dbfc06c1b9fadef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Thu, 29 Apr 2021 00:41:35 +0200 Subject: [PATCH 007/138] Implements blinky for AVR. --- src/modules/chips/atmega328p/atmega328p.zig | 62 +++++++++++++++------ tests/blinky.zig | 4 +- 2 files changed, 48 insertions(+), 18 deletions(-) diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 3e6b978..7192049 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -8,8 +8,14 @@ pub const memory_regions = [_]micro_linker.MemoryRegion{ micro_linker.MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, }; +const Port = enum(u8) { + B = 1, + C = 2, + D = 3, +}; + pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme."; + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; if (spec.len != 3) @compileError(invalid_format_msg); @@ -17,31 +23,41 @@ pub fn parsePin(comptime spec: []const u8) type { @compileError(invalid_format_msg); return struct { - pub const port: u8 = std.ascii.toUpper(spec[1]) - 'A'; - pub const pin: u3 = @intCast(u3, spec[2] - '0'); + pub const port: Port = std.meta.stringToEnum(Port, spec[1..2]) orelse @compileError(invalid_format_msg); + pub const pin: u3 = std.fmt.parseInt(u3, spec[2..3], 10) catch @compileError(invalid_format_msg); }; } pub const gpio = struct { - fn dirReg(comptime pin: type) *volatile u8 { - return @intToPtr(*volatile u8, 0x01); - } - fn portReg(comptime pin: type) *volatile u8 { - return @intToPtr(*volatile u8, 0x01); - } - fn pinReg(comptime pin: type) *volatile u8 { - return @intToPtr(*volatile u8, 0x01); + fn regs(comptime desc: type) type { + return struct { + const pin_addr = 3 * @enumToInt(desc.port) + 0x00; + const dir_addr = 3 * @enumToInt(desc.port) + 0x01; + const port_addr = 3 * @enumToInt(desc.port) + 0x02; + + const pin = @intToPtr(*volatile u8, pin_addr); + const dir = @intToPtr(*volatile u8, dir_addr); + const port = @intToPtr(*volatile u8, port_addr); + }; } pub fn setOutput(comptime pin: type) void { - dirReg(pin).* |= (1 << pin.pin); + asm volatile ("sbi %[port], %[pin]" + : + : [port] "I" (regs(pin).dir_addr), + [pin] "I" (pin.pin) + ); } pub fn setInput(comptime pin: type) void { - dirReg(pin).* &= ~(@as(u8, 1) << pin.pin); + asm volatile ("cbi %[port], %[pin]" + : + : [port] "I" (regs(pin).dir_addr), + [pin] "I" (pin.pin) + ); } pub fn read(comptime pin: type) u1 { - return if ((pinReg(pin).* & (1 << pin.pin)) != 0) + return if ((regs(pin).pin.* & (1 << pin.pin)) != 0) @as(u1, 1) else 0; @@ -49,13 +65,25 @@ pub const gpio = struct { pub fn write(comptime pin: type, state: u1) void { if (state == 1) { - portReg(pin).* |= (1 << pin.pin); + asm volatile ("sbi %[port], %[pin]" + : + : [port] "I" (regs(pin).port_addr), + [pin] "I" (pin.pin) + ); } else { - portReg(pin).* &= ~@as(u8, 1 << pin.pin); + asm volatile ("cbi %[port], %[pin]" + : + : [port] "I" (regs(pin).port_addr), + [pin] "I" (pin.pin) + ); } } pub fn toggle(comptime pin: type) void { - portReg(pin).* ^= (1 << pin.pin); + asm volatile ("sbi %[port], %[pin]" + : + : [port] "I" (regs(pin).pin_addr), + [pin] "I" (pin.pin) + ); } }; diff --git a/tests/blinky.zig b/tests/blinky.zig index 7b30cee..3dece30 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -30,8 +30,10 @@ pub fn main() void { } fn busyloop() void { + const limit = 100_000; + var i: u24 = 0; - while (i < 100_000) : (i += 1) { + while (i < limit) : (i += 1) { @import("std").mem.doNotOptimizeAway(i); } } From 1aad7b52f6381967caf1a3b92b50b4329114eb8b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Thu, 29 Apr 2021 00:45:23 +0200 Subject: [PATCH 008/138] Ports over sbi, cbi to avr5.zig. --- src/modules/chips/atmega328p/atmega328p.zig | 31 ++++----------------- src/modules/cpus/avr/avr5.zig | 20 +++++++++++-- 2 files changed, 24 insertions(+), 27 deletions(-) diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 7192049..da30901 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -42,18 +42,11 @@ pub const gpio = struct { } pub fn setOutput(comptime pin: type) void { - asm volatile ("sbi %[port], %[pin]" - : - : [port] "I" (regs(pin).dir_addr), - [pin] "I" (pin.pin) - ); + cpu.sbi(regs(pin).dir_addr, pin.pin); } + pub fn setInput(comptime pin: type) void { - asm volatile ("cbi %[port], %[pin]" - : - : [port] "I" (regs(pin).dir_addr), - [pin] "I" (pin.pin) - ); + cpu.cbi(regs(pin).dir_addr, pin.pin); } pub fn read(comptime pin: type) u1 { @@ -65,25 +58,13 @@ pub const gpio = struct { pub fn write(comptime pin: type, state: u1) void { if (state == 1) { - asm volatile ("sbi %[port], %[pin]" - : - : [port] "I" (regs(pin).port_addr), - [pin] "I" (pin.pin) - ); + cpu.sbi(regs(pin).port_addr, pin.pin); } else { - asm volatile ("cbi %[port], %[pin]" - : - : [port] "I" (regs(pin).port_addr), - [pin] "I" (pin.pin) - ); + cpu.cbi(regs(pin).port_addr, pin.pin); } } pub fn toggle(comptime pin: type) void { - asm volatile ("sbi %[port], %[pin]" - : - : [port] "I" (regs(pin).pin_addr), - [pin] "I" (pin.pin) - ); + cpu.sbi(regs(pin).pin_addr, pin.pin); } }; diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index 9994b74..baa0093 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -1,13 +1,29 @@ const std = @import("std"); -pub fn sei() void { +pub fn sei() callconv(.Inline) void { asm volatile ("sei"); } -pub fn cli() void { +pub fn cli() callconv(.Inline) void { asm volatile ("cli"); } +pub fn sbi(comptime reg: u5, comptime bit: u3) callconv(.Inline) void { + asm volatile ("sbi %[reg], %[bit]" + : + : [reg] "I" (reg), + [bit] "I" (bit) + ); +} + +pub fn cbi(comptime reg: u5, comptime bit: u3) callconv(.Inline) void { + asm volatile ("cbi %[reg], %[bit]" + : + : [reg] "I" (reg), + [bit] "I" (bit) + ); +} + pub const startup_logic = struct { comptime { asm ( From f5bc3be1aecb3ea26d801877e64ed9031fbd46e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Thu, 29 Apr 2021 22:40:33 +0200 Subject: [PATCH 009/138] Introduces the first SVD generated binding for LPC1768. svd2zig contains a hack for missing register sizes. --- build.zig | 20 +- src/core/mmio.zig | 50 + src/modules/chips/lpc1768/lpc1768.zig | 51 +- src/modules/chips/lpc1768/registers.zig | 17579 ++++++++++++++++++++++ src/tools/README.md | 10 + src/tools/svd2zig.py | 106 + 6 files changed, 17792 insertions(+), 24 deletions(-) create mode 100644 src/core/mmio.zig create mode 100644 src/modules/chips/lpc1768/registers.zig create mode 100644 src/tools/README.md create mode 100755 src/tools/svd2zig.py diff --git a/build.zig b/build.zig index 02b841b..1c34f1f 100644 --- a/build.zig +++ b/build.zig @@ -23,6 +23,8 @@ pub fn build(b: *std.build.Builder) void { Test{ .name = "blinky", .source = "tests/blinky.zig" }, }; + const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); + inline for (all_backings) |cfg| { inline for (all_tests) |tst| { const exe = addEmbeddedExecutable( @@ -31,10 +33,13 @@ pub fn build(b: *std.build.Builder) void { tst.source, cfg.backing, ); - exe.setBuildMode(mode); - exe.install(); - test_step.dependOn(&exe.step); + if (filter == null or exe.target.cpu_arch.? == filter.?) { + exe.setBuildMode(mode); + exe.install(); + + test_step.dependOn(&exe.step); + } } } } @@ -53,9 +58,11 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: .name = "chip", .path = chip.path, .dependencies = &[_]Pkg{ + pkgs.mmio, Pkg{ .name = "cpu", .path = chip.cpu.path, + .dependencies = &[_]Pkg{pkgs.mmio}, }, Pkg{ .name = "microzig-linker", @@ -191,7 +198,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: Pkg{ .name = "board", .path = board.path, - .dependencies = &[_]Pkg{chip_package}, + .dependencies = &[_]Pkg{ chip_package, pkgs.mmio }, }, }, }); @@ -225,6 +232,11 @@ pub const Backing = union(enum) { }; const pkgs = struct { + const mmio = std.build.Pkg{ + .name = "microzig-mmio", + .path = "src/core/mmio.zig", + }; + const cpus = struct { const avr5 = Cpu{ .name = "AVR5", diff --git a/src/core/mmio.zig b/src/core/mmio.zig new file mode 100644 index 0000000..d433007 --- /dev/null +++ b/src/core/mmio.zig @@ -0,0 +1,50 @@ +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile MMIO(size, PackedT) { + return @intToPtr(*volatile MMIO(size, PackedT), addr); +} + +pub fn MMIO(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError("IntT and PackedT must have the same size!"); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.*); + } + + pub fn write(addr: *volatile Self, val: PackedT) void { + addr.* = @bitCast(IntT, val); + } + + pub fn set(addr: *volatile Self, fields: anytype) void { + var val = read(); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(val); + } + + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(val); + } + }; +} diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index ec7e100..843979f 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -2,6 +2,7 @@ const std = @import("std"); const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); +pub const registers = @import("registers.zig"); pub const memory_regions = [_]micro_linker.MemoryRegion{ micro_linker.MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, @@ -16,25 +17,37 @@ pub fn parsePin(comptime spec: []const u8) type { const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg); - return struct { - pub const port: u3 = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); - pub const pin: u5 = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); + const _port: u3 = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); + const _pin: u5 = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); + + const _regs = struct { + const name_suffix = std.fmt.comptimePrint("{d}", .{_port}); + + const dir = @field(registers.GPIO, "DIR" ++ name_suffix); + const pin = @field(registers.GPIO, "PIN" ++ name_suffix); + const set = @field(registers.GPIO, "SET" ++ name_suffix); + const clr = @field(registers.GPIO, "CLR" ++ name_suffix); + const mask = @field(registers.GPIO, "MASK" ++ name_suffix); + }; - const gpio_register = @intToPtr(*volatile registers.GPIO, registers.gpio_base + 0x20 * @as(u32, port)); + return struct { + pub const port = _port; + pub const pin = _pin; + pub const regs = _regs; const gpio_mask: u32 = (1 << pin); }; } pub const gpio = struct { pub fn setOutput(comptime pin: type) void { - pin.gpio_register.dir |= pin.gpio_mask; + pin.regs.dir.raw |= pin.gpio_mask; } pub fn setInput(comptime pin: type) void { - pin.gpio_register.dir &= ~pin.gpio_mask; + pin.regs.dir.raw &= ~pin.gpio_mask; } pub fn read(comptime pin: type) u1 { - return if ((pin.gpio_register.pin & pin.gpio_mask) != 0) + return if ((pin.regs.pin.raw & pin.gpio_mask) != 0) @as(u1, 1) else 0; @@ -42,22 +55,20 @@ pub const gpio = struct { pub fn write(comptime pin: type, state: u1) void { if (state == 1) { - pin.gpio_register.set = pin.gpio_mask; + pin.regs.set.raw = pin.gpio_mask; } else { - pin.gpio_register.clr = pin.gpio_mask; + pin.regs.clr.raw = pin.gpio_mask; } } }; -pub const registers = struct { - pub const GPIO = extern struct { - dir: u32, // 0x00 - pad: [3]u32, - mask: u32, // 0x10 - pin: u32, // 0x14, - set: u32, // 0x18, - clr: u32, // 0x1C, - }; +// pub const GPIO = extern struct { +// dir: u32, // 0x00 +// pad: [3]u32, +// mask: u32, // 0x10 +// pin: u32, // 0x14, +// set: u32, // 0x18, +// clr: u32, // 0x1C, +// }; - pub const gpio_base = 0x2009_C000; -}; +// pub const gpio_base = 0x2009_C000; diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig new file mode 100644 index 0000000..b0a6b05 --- /dev/null +++ b/src/modules/chips/lpc1768/registers.zig @@ -0,0 +1,17579 @@ +// generated using svd2zig.py +// DO NOT EDIT +// based on LPC176x5x version 0.2 +const mmio = @import("microzig-mmio").mmio; +const Name = "LPC176x5x"; +pub const WDT = extern struct { + pub const Address: u32 = 0x40000000; + // byte offset: 0 Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer. + pub const MOD = mmio(Address + 0x00000000, 32, packed struct { + WDEN: bool, // bit offset: 0 desc: Watchdog enable bit. This bit is Set Only. + WDRESET: bool, // bit offset: 1 desc: Watchdog reset enable bit. This bit is Set Only. See Table 652. + WDTOF: bool, // bit offset: 2 desc: Watchdog time-out flag. Set when the watchdog timer times out, cleared by software. + WDINT: bool, // bit offset: 3 desc: Watchdog interrupt flag. Cleared by software. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Watchdog timer constant register. The value in this register determines the time-out value. + pub const TC = mmio(Address + 0x00000004, 32, packed struct { + Count: u32, // bit offset: 0 desc: Watchdog time-out interval. + }); + // byte offset: 8 Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. + pub const FEED = mmio(Address + 0x00000008, 32, packed struct { + Feed: u8, // bit offset: 0 desc: Feed value should be 0xAA followed by 0x55. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Watchdog timer value register. This register reads out the current value of the Watchdog timer. + pub const TV = mmio(Address + 0x0000000c, 32, packed struct { + Count: u32, // bit offset: 0 desc: Counter timer value. + }); + // byte offset: 16 Watchdog clock select register. + pub const CLKSEL = mmio(Address + 0x00000010, 32, packed struct { + CLKSEL: u2, // bit offset: 0 desc: Selects source of WDT clock + reserved29: u1 = 0, + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + LOCK: bool, // bit offset: 31 desc: If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. + }); +}; +pub const TIMER0 = extern struct { + pub const Address: u32 = 0x40004000; + // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + pub const IR = mmio(Address + 0x00000000, 32, packed struct { + MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + pub const TCR = mmio(Address + 0x00000004, 32, packed struct { + CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + pub const TC = mmio(Address + 0x00000008, 32, packed struct { + TC: u32, // bit offset: 0 desc: Timer counter value. + }); + // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. + pub const PR = mmio(Address + 0x0000000c, 32, packed struct { + PM: u32, // bit offset: 0 desc: Prescale counter maximum value. + }); + // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + pub const PC = mmio(Address + 0x00000010, 32, packed struct { + PC: u32, // bit offset: 0 desc: Prescale counter value. + }); + // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + pub const MCR = mmio(Address + 0x00000014, 32, packed struct { + MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 + MR0R: bool, // bit offset: 1 desc: Reset on MR0 + MR0S: bool, // bit offset: 2 desc: Stop on MR0 + MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 + MR1R: bool, // bit offset: 4 desc: Reset on MR1 + MR1S: bool, // bit offset: 5 desc: Stop on MR1 + MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 + MR2R: bool, // bit offset: 7 desc: Reset on MR2 + MR2S: bool, // bit offset: 8 desc: Stop on MR2. + MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 + MR3R: bool, // bit offset: 10 desc: Reset on MR3 + MR3S: bool, // bit offset: 11 desc: Stop on MR3 + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + pub const CCR = mmio(Address + 0x00000028, 32, packed struct { + CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge + CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge + CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event + CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge + CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge + CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 60 External Match Register. The EMR controls the external match pins. + pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { + EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { + CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIMER1 = extern struct { + pub const Address: u32 = 0x40008000; + // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + pub const IR = mmio(Address + 0x00000000, 32, packed struct { + MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + pub const TCR = mmio(Address + 0x00000004, 32, packed struct { + CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + pub const TC = mmio(Address + 0x00000008, 32, packed struct { + TC: u32, // bit offset: 0 desc: Timer counter value. + }); + // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. + pub const PR = mmio(Address + 0x0000000c, 32, packed struct { + PM: u32, // bit offset: 0 desc: Prescale counter maximum value. + }); + // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + pub const PC = mmio(Address + 0x00000010, 32, packed struct { + PC: u32, // bit offset: 0 desc: Prescale counter value. + }); + // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + pub const MCR = mmio(Address + 0x00000014, 32, packed struct { + MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 + MR0R: bool, // bit offset: 1 desc: Reset on MR0 + MR0S: bool, // bit offset: 2 desc: Stop on MR0 + MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 + MR1R: bool, // bit offset: 4 desc: Reset on MR1 + MR1S: bool, // bit offset: 5 desc: Stop on MR1 + MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 + MR2R: bool, // bit offset: 7 desc: Reset on MR2 + MR2S: bool, // bit offset: 8 desc: Stop on MR2. + MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 + MR3R: bool, // bit offset: 10 desc: Reset on MR3 + MR3S: bool, // bit offset: 11 desc: Stop on MR3 + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + pub const CCR = mmio(Address + 0x00000028, 32, packed struct { + CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge + CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge + CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event + CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge + CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge + CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 60 External Match Register. The EMR controls the external match pins. + pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { + EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { + CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART0 = extern struct { + pub const Address: u32 = 0x4000c000; + // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). + pub const RBR = mmio(Address + 0x00000000, 32, packed struct { + RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). + pub const THR = mmio(Address + 0x00000000, 32, packed struct { + THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLL = mmio(Address + 0x00000000, 32, packed struct { + DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLM = mmio(Address + 0x00000004, 32, packed struct { + DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. + ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = mmio(Address + 0x00000008, 32, packed struct { + INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + reserved2: u1 = 0, + reserved1: u1 = 0, + FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. + ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = mmio(Address + 0x00000008, 32, packed struct { + FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. + RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. + TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. + DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + reserved2: u1 = 0, + reserved1: u1 = 0, + RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. + pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { + WLS: u2, // bit offset: 0 desc: Word Length Select. + SBS: bool, // bit offset: 2 desc: Stop Bit Select + PE: bool, // bit offset: 3 desc: Parity Enable. + PS: u2, // bit offset: 4 desc: Parity Select + BC: bool, // bit offset: 6 desc: Break Control + DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. + pub const LSR = mmio(Address + 0x00000014, 32, packed struct { + RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { + PAD: u8, // bit offset: 0 desc: A readable, writable byte. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = mmio(Address + 0x00000020, 32, packed struct { + START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. + AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = mmio(Address + 0x00000028, 32, packed struct { + DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. + MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. + pub const TER = mmio(Address + 0x00000030, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. + pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { + NMMEN: bool, // bit offset: 0 desc: NMM enable. + RXDIS: bool, // bit offset: 1 desc: Receiver enable. + AADEN: bool, // bit offset: 2 desc: AAD enable. + reserved1: u1 = 0, + DCTRL: bool, // bit offset: 4 desc: Direction control enable. + OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. + pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { + ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 RS-485/EIA-485 direction control delay. + pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { + DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART1 = extern struct { + pub const Address: u32 = 0x40010000; + // byte offset: 0 DLAB =0 Receiver Buffer Register. Contains the next received character to be read. + pub const RBR = mmio(Address + 0x00000000, 32, packed struct { + RBR: u8, // bit offset: 0 desc: The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. + pub const THR = mmio(Address + 0x00000000, 32, packed struct { + THR: u8, // bit offset: 0 desc: Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. + pub const DLL = mmio(Address + 0x00000000, 32, packed struct { + DLLSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. + pub const DLM = mmio(Address + 0x00000004, 32, packed struct { + DLMSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. + THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. + RXIE: bool, // bit offset: 2 desc: RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. + MSIE: bool, // bit offset: 3 desc: Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CTSIE: bool, // bit offset: 7 desc: CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. + ABEOIE: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. + ABTOIE: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = mmio(Address + 0x00000008, 32, packed struct { + INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. + INTID: u3, // bit offset: 1 desc: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). + reserved2: u1 = 0, + reserved1: u1 = 0, + FIFOENABLE: u2, // bit offset: 6 desc: Copies of FCR[0]. + ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 FIFO Control Register. Controls UART1 FIFO usage and modes. + pub const FCR = mmio(Address + 0x00000008, 32, packed struct { + FIFOEN: bool, // bit offset: 0 desc: FIFO enable. + RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. + TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. + DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. + reserved2: u1 = 0, + reserved1: u1 = 0, + RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. + pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { + WLS: u2, // bit offset: 0 desc: Word Length Select. + SBS: bool, // bit offset: 2 desc: Stop Bit Select. + PE: bool, // bit offset: 3 desc: Parity Enable. + PS: u2, // bit offset: 4 desc: Parity Select. + BC: bool, // bit offset: 6 desc: Break Control. + DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit (DLAB) + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Modem Control Register. Contains controls for flow control handshaking and loopback mode. + pub const MCR = mmio(Address + 0x00000010, 32, packed struct { + DTRCTRL: bool, // bit offset: 0 desc: DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. + RTSCTRL: bool, // bit offset: 1 desc: RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. + reserved2: u1 = 0, + reserved1: u1 = 0, + LMS: bool, // bit offset: 4 desc: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. + reserved2: u1 = 0, + RTSEN: bool, // bit offset: 6 desc: RTS enable. + CTSEN: bool, // bit offset: 7 desc: CTS enable. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. + pub const LSR = mmio(Address + 0x00000014, 32, packed struct { + RDR: bool, // bit offset: 0 desc: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. + OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. + PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. + FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. + BI: bool, // bit offset: 4 desc: Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. + THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. + TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. + RXFE: bool, // bit offset: 7 desc: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Modem Status Register. Contains handshake signal status flags. + pub const MSR = mmio(Address + 0x00000018, 32, packed struct { + DCTS: bool, // bit offset: 0 desc: Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. + DDSR: bool, // bit offset: 1 desc: Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. + TERI: bool, // bit offset: 2 desc: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. + DDCD: bool, // bit offset: 3 desc: Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. + CTS: bool, // bit offset: 4 desc: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. + DSR: bool, // bit offset: 5 desc: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. + RI: bool, // bit offset: 6 desc: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. + DCD: bool, // bit offset: 7 desc: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { + Pad: u8, // bit offset: 0 desc: A readable, writable byte. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = mmio(Address + 0x00000020, 32, packed struct { + START: bool, // bit offset: 0 desc: Auto-baud start bit. This bit is automatically cleared after auto-baud completion. + MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. + AUTORESTART: bool, // bit offset: 2 desc: Auto-baud restart bit. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only). + ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only). + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = mmio(Address + 0x00000028, 32, packed struct { + DIVADDVAL: u4, // bit offset: 0 desc: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate. + MULVAL: u4, // bit offset: 4 desc: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. + pub const TER = mmio(Address + 0x00000030, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. + pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { + NMMEN: bool, // bit offset: 0 desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. + RXDIS: bool, // bit offset: 1 desc: Receive enable. + AADEN: bool, // bit offset: 2 desc: Auto Address Detect (AAD) enable. + SEL: bool, // bit offset: 3 desc: Direction control. + DCTRL: bool, // bit offset: 4 desc: Direction control enable. + OINV: bool, // bit offset: 5 desc: Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. + pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { + ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 RS-485/EIA-485 direction control delay. + pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { + DLY: u8, // bit offset: 0 desc: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const PWM1 = extern struct { + pub const Address: u32 = 0x40018000; + // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending. + pub const IR = mmio(Address + 0x00000000, 32, packed struct { + PWMMR0INT: bool, // bit offset: 0 desc: Interrupt flag for PWM match channel 0. + PWMMR1INT: bool, // bit offset: 1 desc: Interrupt flag for PWM match channel 1. + PWMMR2INT: bool, // bit offset: 2 desc: Interrupt flag for PWM match channel 2. + PWMMR3INT: bool, // bit offset: 3 desc: Interrupt flag for PWM match channel 3. + PWMCAP0INT: bool, // bit offset: 4 desc: Interrupt flag for capture input 0 + PWMCAP1INT: bool, // bit offset: 5 desc: Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). + reserved2: u1 = 0, + reserved1: u1 = 0, + PWMMR4INT: bool, // bit offset: 8 desc: Interrupt flag for PWM match channel 4. + PWMMR5INT: bool, // bit offset: 9 desc: Interrupt flag for PWM match channel 5. + PWMMR6INT: bool, // bit offset: 10 desc: Interrupt flag for PWM match channel 6. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. + pub const TCR = mmio(Address + 0x00000004, 32, packed struct { + CE: bool, // bit offset: 0 desc: Counter Enable + CR: bool, // bit offset: 1 desc: Counter Reset + reserved1: u1 = 0, + PWMEN: bool, // bit offset: 3 desc: PWM Enable + MDIS: bool, // bit offset: 4 desc: Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + pub const TC = mmio(Address + 0x00000008, 32, packed struct { + TC: u32, // bit offset: 0 desc: Timer counter value. + }); + // byte offset: 12 Prescale Register. Determines how often the PWM counter is incremented. + pub const PR = mmio(Address + 0x0000000c, 32, packed struct { + PM: u32, // bit offset: 0 desc: Prescale counter maximum value. + }); + // byte offset: 16 Prescale Counter. Prescaler for the main PWM counter. + pub const PC = mmio(Address + 0x00000010, 32, packed struct { + PC: u32, // bit offset: 0 desc: Prescale counter value. + }); + // byte offset: 20 Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs. + pub const MCR = mmio(Address + 0x00000014, 32, packed struct { + PWMMR0I: bool, // bit offset: 0 desc: Interrupt PWM0 + PWMMR0R: bool, // bit offset: 1 desc: Reset PWM0 + PWMMR0S: bool, // bit offset: 2 desc: Stop PWM0 + PWMMR1I: bool, // bit offset: 3 desc: Interrupt PWM1 + PWMMR1R: bool, // bit offset: 4 desc: Reset PWM1 + PWMMR1S: bool, // bit offset: 5 desc: Stop PWM1 + PWMMR2I: bool, // bit offset: 6 desc: Interrupt PWM0 + PWMMR2R: bool, // bit offset: 7 desc: Reset PWM0 + PWMMR2S: bool, // bit offset: 8 desc: Stop PWM0 + PWMMR3I: bool, // bit offset: 9 desc: Interrupt PWM3 + PWMMR3R: bool, // bit offset: 10 desc: Reset PWM3 + PWMMR3S: bool, // bit offset: 11 desc: Stop PWM0 + PWMMR4I: bool, // bit offset: 12 desc: Interrupt PWM4 + PWMMR4R: bool, // bit offset: 13 desc: Reset PWM4 + PWMMR4S: bool, // bit offset: 14 desc: Stop PWM4 + PWMMR5I: bool, // bit offset: 15 desc: Interrupt PWM5 + PWMMR5R: bool, // bit offset: 16 desc: Reset PWM5 + PWMMR5S: bool, // bit offset: 17 desc: Stop PWM5 + PWMMR6I: bool, // bit offset: 18 desc: Interrupt PWM6 + PWMMR6R: bool, // bit offset: 19 desc: Reset PWM6 + PWMMR6S: bool, // bit offset: 20 desc: Stop PWM6 + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event. + pub const CCR = mmio(Address + 0x00000028, 32, packed struct { + CAP0_R: bool, // bit offset: 0 desc: Capture on PWMn_CAP0 rising edge + CAP0_F: bool, // bit offset: 1 desc: Capture on PWMn_CAP0 falling edge + CAP0_I: bool, // bit offset: 2 desc: Interrupt on PWMn_CAP0 event + CAP1_R: bool, // bit offset: 3 desc: Capture on PWMn_CAP1 rising edge. Reserved for PWM0. + CAP1_F: bool, // bit offset: 4 desc: Capture on PWMn_CAP1 falling edge. Reserved for PWM0. + CAP1_I: bool, // bit offset: 5 desc: Interrupt on PWMn_CAP1 event. Reserved for PWM0. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. + PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. + PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. + PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. + PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + reserved3: u1 = 0, + reserved2: u1 = 0, + PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. + PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. + PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. + PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. + PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. + PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + }); + // byte offset: 48 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. + PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. + PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. + PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. + PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + reserved3: u1 = 0, + reserved2: u1 = 0, + PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. + PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. + PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. + PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. + PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. + PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + }); + // byte offset: 64 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR4 = mmio(Address + 0x00000040, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 68 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR5 = mmio(Address + 0x00000044, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 72 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. + pub const MR6 = mmio(Address + 0x00000048, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 76 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. + pub const PCR = mmio(Address + 0x0000004c, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. + PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. + PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. + PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. + PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + reserved3: u1 = 0, + reserved2: u1 = 0, + PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. + PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. + PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. + PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. + PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. + PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 Load Enable Register. Enables use of updated PWM match values. + pub const LER = mmio(Address + 0x00000050, 32, packed struct { + MAT0LATCHEN: bool, // bit offset: 0 desc: Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. + MAT1LATCHEN: bool, // bit offset: 1 desc: Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. + MAT2LATCHEN: bool, // bit offset: 2 desc: Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. + MAT3LATCHEN: bool, // bit offset: 3 desc: Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. + MAT4LATCHEN: bool, // bit offset: 4 desc: Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. + MAT5LATCHEN: bool, // bit offset: 5 desc: Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. + MAT6LATCHEN: bool, // bit offset: 6 desc: Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { + MOD: u2, // bit offset: 0 desc: Counter/ Timer Mode + CIS: u2, // bit offset: 2 desc: Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C0 = extern struct { + pub const Address: u32 = 0x4001c000; + // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AA: bool, // bit offset: 2 desc: Assert acknowledge flag. + SI: bool, // bit offset: 3 desc: I2C interrupt flag. + STO: bool, // bit offset: 4 desc: STOP flag. + STA: bool, // bit offset: 5 desc: START flag. + I2EN: bool, // bit offset: 6 desc: I2C interface enable. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. + pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. + pub const DAT = mmio(Address + 0x00000008, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. + pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { + SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. + pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { + SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. + reserved2: u1 = 0, + STAC: bool, // bit offset: 5 desc: START flag Clear bit. + I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Monitor mode control register. + pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { + MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. + ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. + MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); +}; +pub const SPI = extern struct { + pub const Address: u32 = 0x40020000; + // byte offset: 0 SPI Control Register. This register controls the operation of the SPI. + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + BITENABLE: bool, // bit offset: 2 desc: The SPI controller sends and receives 8 bits of data per transfer. + CPHA: bool, // bit offset: 3 desc: Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. + CPOL: bool, // bit offset: 4 desc: Clock polarity control. + MSTR: bool, // bit offset: 5 desc: Master mode select. + LSBF: bool, // bit offset: 6 desc: LSB First controls which direction each byte is shifted when transferred. + SPIE: bool, // bit offset: 7 desc: Serial peripheral interrupt enable. + BITS: u4, // bit offset: 8 desc: When bit 2 of this register is 1, this field controls the number of bits per transfer: + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 SPI Status Register. This register shows the status of the SPI. + pub const SR = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABRT: bool, // bit offset: 3 desc: Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. + MODF: bool, // bit offset: 4 desc: Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. + ROVR: bool, // bit offset: 5 desc: Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. + WCOL: bool, // bit offset: 6 desc: Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. + SPIF: bool, // bit offset: 7 desc: SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. + pub const DR = mmio(Address + 0x00000008, 32, packed struct { + DATALOW: u8, // bit offset: 0 desc: SPI Bi-directional data port. + DATAHIGH: u8, // bit offset: 8 desc: If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 SPI Clock Counter Register. This register controls the frequency of a master's SCK0. + pub const CCR = mmio(Address + 0x0000000c, 32, packed struct { + COUNTER: u8, // bit offset: 0 desc: SPI0 Clock counter setting. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. + pub const INT = mmio(Address + 0x0000001c, 32, packed struct { + SPIF: bool, // bit offset: 0 desc: SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const RTC = extern struct { + pub const Address: u32 = 0x40024000; + // byte offset: 0 Interrupt Location Register + pub const ILR = mmio(Address + 0x00000000, 32, packed struct { + RTCCIF: bool, // bit offset: 0 desc: When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. + RTCALF: bool, // bit offset: 1 desc: When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Clock Control Register + pub const CCR = mmio(Address + 0x00000008, 32, packed struct { + CLKEN: bool, // bit offset: 0 desc: Clock Enable. + CTCRST: bool, // bit offset: 1 desc: CTC Reset. + reserved2: u1 = 0, + reserved1: u1 = 0, + CCALEN: bool, // bit offset: 4 desc: Calibration counter enable. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Counter Increment Interrupt Register + pub const CIIR = mmio(Address + 0x0000000c, 32, packed struct { + IMSEC: bool, // bit offset: 0 desc: When 1, an increment of the Second value generates an interrupt. + IMMIN: bool, // bit offset: 1 desc: When 1, an increment of the Minute value generates an interrupt. + IMHOUR: bool, // bit offset: 2 desc: When 1, an increment of the Hour value generates an interrupt. + IMDOM: bool, // bit offset: 3 desc: When 1, an increment of the Day of Month value generates an interrupt. + IMDOW: bool, // bit offset: 4 desc: When 1, an increment of the Day of Week value generates an interrupt. + IMDOY: bool, // bit offset: 5 desc: When 1, an increment of the Day of Year value generates an interrupt. + IMMON: bool, // bit offset: 6 desc: When 1, an increment of the Month value generates an interrupt. + IMYEAR: bool, // bit offset: 7 desc: When 1, an increment of the Year value generates an interrupt. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Alarm Mask Register + pub const AMR = mmio(Address + 0x00000010, 32, packed struct { + AMRSEC: bool, // bit offset: 0 desc: When 1, the Second value is not compared for the alarm. + AMRMIN: bool, // bit offset: 1 desc: When 1, the Minutes value is not compared for the alarm. + AMRHOUR: bool, // bit offset: 2 desc: When 1, the Hour value is not compared for the alarm. + AMRDOM: bool, // bit offset: 3 desc: When 1, the Day of Month value is not compared for the alarm. + AMRDOW: bool, // bit offset: 4 desc: When 1, the Day of Week value is not compared for the alarm. + AMRDOY: bool, // bit offset: 5 desc: When 1, the Day of Year value is not compared for the alarm. + AMRMON: bool, // bit offset: 6 desc: When 1, the Month value is not compared for the alarm. + AMRYEAR: bool, // bit offset: 7 desc: When 1, the Year value is not compared for the alarm. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Consolidated Time Register 0 + pub const CTIME0 = mmio(Address + 0x00000014, 32, packed struct { + SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + reserved2: u1 = 0, + reserved1: u1 = 0, + MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59 + reserved3: u1 = 0, + reserved2: u1 = 0, + HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23 + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6 + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Consolidated Time Register 1 + pub const CTIME1 = mmio(Address + 0x00000018, 32, packed struct { + DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095. + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Consolidated Time Register 2 + pub const CTIME2 = mmio(Address + 0x0000001c, 32, packed struct { + DOY: u12, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Seconds Counter + pub const SEC = mmio(Address + 0x00000020, 32, packed struct { + SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Minutes Register + pub const MIN = mmio(Address + 0x00000024, 32, packed struct { + MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Hours Register + pub const HRS = mmio(Address + 0x00000028, 32, packed struct { + HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Day of Month Register + pub const DOM = mmio(Address + 0x0000002c, 32, packed struct { + DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Day of Week Register + pub const DOW = mmio(Address + 0x00000030, 32, packed struct { + DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 Day of Year Register + pub const DOY = mmio(Address + 0x00000034, 32, packed struct { + DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 Months Register + pub const MONTH = mmio(Address + 0x00000038, 32, packed struct { + MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 Years Register + pub const YEAR = mmio(Address + 0x0000003c, 32, packed struct { + YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 Calibration Value Register + pub const CALIBRATION = mmio(Address + 0x00000040, 32, packed struct { + CALVAL: u17, // bit offset: 0 desc: If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. + CALDIR: bool, // bit offset: 17 desc: Calibration direction + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 General Purpose Register 0 + pub const GPREG0 = mmio(Address + 0x00000044, 32, packed struct { + GP: u32, // bit offset: 0 desc: General purpose storage. + }); + // byte offset: 72 General Purpose Register 0 + pub const GPREG1 = mmio(Address + 0x00000048, 32, packed struct { + GP: u32, // bit offset: 0 desc: General purpose storage. + }); + // byte offset: 76 General Purpose Register 0 + pub const GPREG2 = mmio(Address + 0x0000004c, 32, packed struct { + GP: u32, // bit offset: 0 desc: General purpose storage. + }); + // byte offset: 80 General Purpose Register 0 + pub const GPREG3 = mmio(Address + 0x00000050, 32, packed struct { + GP: u32, // bit offset: 0 desc: General purpose storage. + }); + // byte offset: 84 General Purpose Register 0 + pub const GPREG4 = mmio(Address + 0x00000054, 32, packed struct { + GP: u32, // bit offset: 0 desc: General purpose storage. + }); + // byte offset: 88 RTC Auxiliary Enable register + pub const RTC_AUXEN = mmio(Address + 0x00000058, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RTC_OSCFEN: bool, // bit offset: 4 desc: Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 RTC Auxiliary control register + pub const RTC_AUX = mmio(Address + 0x0000005c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RTC_OSCF: bool, // bit offset: 4 desc: RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. + reserved2: u1 = 0, + RTC_PDOUT: bool, // bit offset: 6 desc: When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 Alarm value for Seconds + pub const ASEC = mmio(Address + 0x00000060, 32, packed struct { + SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 100 Alarm value for Minutes + pub const AMIN = mmio(Address + 0x00000064, 32, packed struct { + MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 104 Alarm value for Hours + pub const AHRS = mmio(Address + 0x00000068, 32, packed struct { + HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 108 Alarm value for Day of Month + pub const ADOM = mmio(Address + 0x0000006c, 32, packed struct { + DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Alarm value for Day of Week + pub const ADOW = mmio(Address + 0x00000070, 32, packed struct { + DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 Alarm value for Day of Year + pub const ADOY = mmio(Address + 0x00000074, 32, packed struct { + DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 120 Alarm value for Months + pub const AMON = mmio(Address + 0x00000078, 32, packed struct { + MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 124 Alarm value for Year + pub const AYRS = mmio(Address + 0x0000007c, 32, packed struct { + YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOINT = extern struct { + pub const Address: u32 = 0x40028080; + // byte offset: 0 GPIO overall Interrupt Status. + pub const STATUS = mmio(Address + 0x00000000, 32, packed struct { + P0INT: bool, // bit offset: 0 desc: Port 0 GPIO interrupt pending. + reserved1: u1 = 0, + P2INT: bool, // bit offset: 2 desc: Port 2 GPIO interrupt pending. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR0 = mmio(Address + 0x00000004, 32, packed struct { + P0_0REI: bool, // bit offset: 0 desc: Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_1REI: bool, // bit offset: 1 desc: Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_2REI: bool, // bit offset: 2 desc: Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_3REI: bool, // bit offset: 3 desc: Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_4REI: bool, // bit offset: 4 desc: Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_5REI: bool, // bit offset: 5 desc: Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_6REI: bool, // bit offset: 6 desc: Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_7REI: bool, // bit offset: 7 desc: Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_8REI: bool, // bit offset: 8 desc: Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_9REI: bool, // bit offset: 9 desc: Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_10REI: bool, // bit offset: 10 desc: Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_11REI: bool, // bit offset: 11 desc: Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_12REI: bool, // bit offset: 12 desc: Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_13REI: bool, // bit offset: 13 desc: Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_14REI: bool, // bit offset: 14 desc: Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_15REI: bool, // bit offset: 15 desc: Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_16REI: bool, // bit offset: 16 desc: Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_17REI: bool, // bit offset: 17 desc: Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_18REI: bool, // bit offset: 18 desc: Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_19REI: bool, // bit offset: 19 desc: Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_20REI: bool, // bit offset: 20 desc: Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_21REI: bool, // bit offset: 21 desc: Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_22REI: bool, // bit offset: 22 desc: Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_23REI: bool, // bit offset: 23 desc: Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_24REI: bool, // bit offset: 24 desc: Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_25REI: bool, // bit offset: 25 desc: Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_26REI: bool, // bit offset: 26 desc: Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_27REI: bool, // bit offset: 27 desc: Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_28REI: bool, // bit offset: 28 desc: Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_29REI: bool, // bit offset: 29 desc: Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_30REI: bool, // bit offset: 30 desc: Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + padding1: u1 = 0, + }); + // byte offset: 8 GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF0 = mmio(Address + 0x00000008, 32, packed struct { + P0_0FEI: bool, // bit offset: 0 desc: Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_1FEI: bool, // bit offset: 1 desc: Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_2FEI: bool, // bit offset: 2 desc: Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_3FEI: bool, // bit offset: 3 desc: Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_4FEI: bool, // bit offset: 4 desc: Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_5FEI: bool, // bit offset: 5 desc: Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_6FEI: bool, // bit offset: 6 desc: Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_7FEI: bool, // bit offset: 7 desc: Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_8FEI: bool, // bit offset: 8 desc: Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_9FEI: bool, // bit offset: 9 desc: Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_10FEI: bool, // bit offset: 10 desc: Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_11FEI: bool, // bit offset: 11 desc: Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_12FEI: bool, // bit offset: 12 desc: Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_13FEI: bool, // bit offset: 13 desc: Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_14FEI: bool, // bit offset: 14 desc: Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_15FEI: bool, // bit offset: 15 desc: Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_16FEI: bool, // bit offset: 16 desc: Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_17FEI: bool, // bit offset: 17 desc: Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_18FEI: bool, // bit offset: 18 desc: Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_19FEI: bool, // bit offset: 19 desc: Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_20FEI: bool, // bit offset: 20 desc: Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_21FEI: bool, // bit offset: 21 desc: Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_22FEI: bool, // bit offset: 22 desc: Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_23FEI: bool, // bit offset: 23 desc: Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_24FEI: bool, // bit offset: 24 desc: Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_25FEI: bool, // bit offset: 25 desc: Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_26FEI: bool, // bit offset: 26 desc: Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_27FEI: bool, // bit offset: 27 desc: Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_28FEI: bool, // bit offset: 28 desc: Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_29FEI: bool, // bit offset: 29 desc: Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_30FEI: bool, // bit offset: 30 desc: Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + padding1: u1 = 0, + }); + // byte offset: 12 GPIO Interrupt Clear. + pub const CLR0 = mmio(Address + 0x0000000c, 32, packed struct { + P0_0CI: bool, // bit offset: 0 desc: Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_1CI: bool, // bit offset: 1 desc: Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_2CI: bool, // bit offset: 2 desc: Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_3CI: bool, // bit offset: 3 desc: Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_4CI: bool, // bit offset: 4 desc: Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_5CI: bool, // bit offset: 5 desc: Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_6CI: bool, // bit offset: 6 desc: Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_7CI: bool, // bit offset: 7 desc: Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_8CI: bool, // bit offset: 8 desc: Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_9CI: bool, // bit offset: 9 desc: Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_10CI: bool, // bit offset: 10 desc: Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_11CI: bool, // bit offset: 11 desc: Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_12CI: bool, // bit offset: 12 desc: Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_13CI: bool, // bit offset: 13 desc: Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_14CI: bool, // bit offset: 14 desc: Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_15CI: bool, // bit offset: 15 desc: Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_16CI: bool, // bit offset: 16 desc: Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_17CI: bool, // bit offset: 17 desc: Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_18CI: bool, // bit offset: 18 desc: Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_19CI: bool, // bit offset: 19 desc: Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_20CI: bool, // bit offset: 20 desc: Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_21CI: bool, // bit offset: 21 desc: Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_22CI: bool, // bit offset: 22 desc: Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_23CI: bool, // bit offset: 23 desc: Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_24CI: bool, // bit offset: 24 desc: Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_25CI: bool, // bit offset: 25 desc: Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_26CI: bool, // bit offset: 26 desc: Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_27CI: bool, // bit offset: 27 desc: Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_28CI: bool, // bit offset: 28 desc: Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_29CI: bool, // bit offset: 29 desc: Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_30CI: bool, // bit offset: 30 desc: Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + padding1: u1 = 0, + }); + // byte offset: 16 GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR0 = mmio(Address + 0x00000010, 32, packed struct { + P0_0ER: bool, // bit offset: 0 desc: Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_1ER: bool, // bit offset: 1 desc: Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_2ER: bool, // bit offset: 2 desc: Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_3ER: bool, // bit offset: 3 desc: Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_4ER: bool, // bit offset: 4 desc: Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_5ER: bool, // bit offset: 5 desc: Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_6ER: bool, // bit offset: 6 desc: Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_7ER: bool, // bit offset: 7 desc: Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_8ER: bool, // bit offset: 8 desc: Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_9ER: bool, // bit offset: 9 desc: Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_10ER: bool, // bit offset: 10 desc: Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_11ER: bool, // bit offset: 11 desc: Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_12ER: bool, // bit offset: 12 desc: Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_13ER: bool, // bit offset: 13 desc: Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_14ER: bool, // bit offset: 14 desc: Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_15ER: bool, // bit offset: 15 desc: Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_16ER: bool, // bit offset: 16 desc: Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_17ER: bool, // bit offset: 17 desc: Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_18ER: bool, // bit offset: 18 desc: Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_19ER: bool, // bit offset: 19 desc: Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_20ER: bool, // bit offset: 20 desc: Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_21ER: bool, // bit offset: 21 desc: Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_22ER: bool, // bit offset: 22 desc: Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_23ER: bool, // bit offset: 23 desc: Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_24ER: bool, // bit offset: 24 desc: Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_25ER: bool, // bit offset: 25 desc: Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_26ER: bool, // bit offset: 26 desc: Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_27ER: bool, // bit offset: 27 desc: Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_28ER: bool, // bit offset: 28 desc: Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_29ER: bool, // bit offset: 29 desc: Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_30ER: bool, // bit offset: 30 desc: Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + padding1: u1 = 0, + }); + // byte offset: 20 GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF0 = mmio(Address + 0x00000014, 32, packed struct { + P0_0EF: bool, // bit offset: 0 desc: Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_1EF: bool, // bit offset: 1 desc: Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_2EF: bool, // bit offset: 2 desc: Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_3EF: bool, // bit offset: 3 desc: Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_4EF: bool, // bit offset: 4 desc: Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_5EF: bool, // bit offset: 5 desc: Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_6EF: bool, // bit offset: 6 desc: Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_7EF: bool, // bit offset: 7 desc: Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_8EF: bool, // bit offset: 8 desc: Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_9EF: bool, // bit offset: 9 desc: Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_10EF: bool, // bit offset: 10 desc: Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_11EF: bool, // bit offset: 11 desc: Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_12EF: bool, // bit offset: 12 desc: Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_13EF: bool, // bit offset: 13 desc: Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_14EF: bool, // bit offset: 14 desc: Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_15EF: bool, // bit offset: 15 desc: Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_16EF: bool, // bit offset: 16 desc: Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_17EF: bool, // bit offset: 17 desc: Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_18EF: bool, // bit offset: 18 desc: Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_19EF: bool, // bit offset: 19 desc: Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_20EF: bool, // bit offset: 20 desc: Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_21EF: bool, // bit offset: 21 desc: Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_22EF: bool, // bit offset: 22 desc: Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_23EF: bool, // bit offset: 23 desc: Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_24EF: bool, // bit offset: 24 desc: Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_25EF: bool, // bit offset: 25 desc: Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_26EF: bool, // bit offset: 26 desc: Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_27EF: bool, // bit offset: 27 desc: Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_28EF: bool, // bit offset: 28 desc: Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_29EF: bool, // bit offset: 29 desc: Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_30EF: bool, // bit offset: 30 desc: Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + padding1: u1 = 0, + }); + // byte offset: 36 GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR2 = mmio(Address + 0x00000024, 32, packed struct { + P2_0REI: bool, // bit offset: 0 desc: Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_1REI: bool, // bit offset: 1 desc: Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_2REI: bool, // bit offset: 2 desc: Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_3REI: bool, // bit offset: 3 desc: Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_4REI: bool, // bit offset: 4 desc: Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_5REI: bool, // bit offset: 5 desc: Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_6REI: bool, // bit offset: 6 desc: Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_7REI: bool, // bit offset: 7 desc: Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_8REI: bool, // bit offset: 8 desc: Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_9REI: bool, // bit offset: 9 desc: Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_10REI: bool, // bit offset: 10 desc: Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_11REI: bool, // bit offset: 11 desc: Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_12REI: bool, // bit offset: 12 desc: Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_13REI: bool, // bit offset: 13 desc: Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF2 = mmio(Address + 0x00000028, 32, packed struct { + P2_0FEI: bool, // bit offset: 0 desc: Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_1FEI: bool, // bit offset: 1 desc: Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_2FEI: bool, // bit offset: 2 desc: Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_3FEI: bool, // bit offset: 3 desc: Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_4FEI: bool, // bit offset: 4 desc: Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_5FEI: bool, // bit offset: 5 desc: Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_6FEI: bool, // bit offset: 6 desc: Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_7FEI: bool, // bit offset: 7 desc: Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_8FEI: bool, // bit offset: 8 desc: Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_9FEI: bool, // bit offset: 9 desc: Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_10FEI: bool, // bit offset: 10 desc: Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_11FEI: bool, // bit offset: 11 desc: Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_12FEI: bool, // bit offset: 12 desc: Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_13FEI: bool, // bit offset: 13 desc: Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 GPIO Interrupt Clear. + pub const CLR2 = mmio(Address + 0x0000002c, 32, packed struct { + P2_0CI: bool, // bit offset: 0 desc: Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_1CI: bool, // bit offset: 1 desc: Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_2CI: bool, // bit offset: 2 desc: Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_3CI: bool, // bit offset: 3 desc: Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_4CI: bool, // bit offset: 4 desc: Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_5CI: bool, // bit offset: 5 desc: Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_6CI: bool, // bit offset: 6 desc: Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_7CI: bool, // bit offset: 7 desc: Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_8CI: bool, // bit offset: 8 desc: Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_9CI: bool, // bit offset: 9 desc: Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_10CI: bool, // bit offset: 10 desc: Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_11CI: bool, // bit offset: 11 desc: Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_12CI: bool, // bit offset: 12 desc: Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_13CI: bool, // bit offset: 13 desc: Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR2 = mmio(Address + 0x00000030, 32, packed struct { + P2_0ER: bool, // bit offset: 0 desc: Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_1ER: bool, // bit offset: 1 desc: Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_2ER: bool, // bit offset: 2 desc: Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_3ER: bool, // bit offset: 3 desc: Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_4ER: bool, // bit offset: 4 desc: Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_5ER: bool, // bit offset: 5 desc: Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_6ER: bool, // bit offset: 6 desc: Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_7ER: bool, // bit offset: 7 desc: Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_8ER: bool, // bit offset: 8 desc: Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_9ER: bool, // bit offset: 9 desc: Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_10ER: bool, // bit offset: 10 desc: Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_11ER: bool, // bit offset: 11 desc: Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_12ER: bool, // bit offset: 12 desc: Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_13ER: bool, // bit offset: 13 desc: Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF2 = mmio(Address + 0x00000034, 32, packed struct { + P2_0EF: bool, // bit offset: 0 desc: Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_1EF: bool, // bit offset: 1 desc: Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_2EF: bool, // bit offset: 2 desc: Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_3EF: bool, // bit offset: 3 desc: Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_4EF: bool, // bit offset: 4 desc: Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_5EF: bool, // bit offset: 5 desc: Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_6EF: bool, // bit offset: 6 desc: Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_7EF: bool, // bit offset: 7 desc: Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_8EF: bool, // bit offset: 8 desc: Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_9EF: bool, // bit offset: 9 desc: Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_10EF: bool, // bit offset: 10 desc: Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_11EF: bool, // bit offset: 11 desc: Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_12EF: bool, // bit offset: 12 desc: Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_13EF: bool, // bit offset: 13 desc: Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const PINCONNECT = extern struct { + pub const Address: u32 = 0x4002c000; + // byte offset: 0 Pin function select register 0. + pub const PINSEL0 = mmio(Address + 0x00000000, 32, packed struct { + P0_0: u2, // bit offset: 0 desc: Pin function select P0.0. + P0_1: u2, // bit offset: 2 desc: Pin function select P0.1. + P0_2: u2, // bit offset: 4 desc: Pin function select P0.2. + P0_3: u2, // bit offset: 6 desc: Pin function select P0.3. + P0_4: u2, // bit offset: 8 desc: Pin function select P0.4. + P0_5: u2, // bit offset: 10 desc: Pin function select P0.5. + P0_6: u2, // bit offset: 12 desc: Pin function select P0.6. + P0_7: u2, // bit offset: 14 desc: Pin function select P0.7. + P0_8: u2, // bit offset: 16 desc: Pin function select P0.8. + P0_9: u2, // bit offset: 18 desc: Pin function select P0.9. + P0_10: u2, // bit offset: 20 desc: Pin function select P0.10. + P0_11: u2, // bit offset: 22 desc: Pin function select P0.11. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P0_15: u2, // bit offset: 30 desc: Pin function select P0.15. + }); + // byte offset: 4 Pin function select register 1. + pub const PINSEL1 = mmio(Address + 0x00000004, 32, packed struct { + P0_16: u2, // bit offset: 0 desc: Pin function select P0.16. + P0_17: u2, // bit offset: 2 desc: Pin function select P0.17. + P0_18: u2, // bit offset: 4 desc: Pin function select P0.18. + P0_19: u2, // bit offset: 6 desc: Pin function select P019. + P0_20: u2, // bit offset: 8 desc: Pin function select P0.20. + P0_21: u2, // bit offset: 10 desc: Pin function select P0.21. + P0_22: u2, // bit offset: 12 desc: Pin function select P022 + P0_23: u2, // bit offset: 14 desc: Pin function select P023. + P0_24: u2, // bit offset: 16 desc: Pin function select P0.24. + P0_25: u2, // bit offset: 18 desc: Pin function select P0.25. + P0_26: u2, // bit offset: 20 desc: Pin function select P0.26. + P0_27: u2, // bit offset: 22 desc: Pin function select P0.27. + P0_28: u2, // bit offset: 24 desc: Pin function select P0.28. + P0_29: u2, // bit offset: 26 desc: Pin function select P0.29 + P0_30: u2, // bit offset: 28 desc: Pin function select P0.30. + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Pin function select register 2. + pub const PINSEL2 = mmio(Address + 0x00000008, 32, packed struct { + P1_0: u2, // bit offset: 0 desc: Pin function select P1.0. + P1_1: u2, // bit offset: 2 desc: Pin function select P1.1. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P1_4: u2, // bit offset: 8 desc: Pin function select P1.4. + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + P1_8: u2, // bit offset: 16 desc: Pin function select P1.8. + P1_9: u2, // bit offset: 18 desc: Pin function select P1.9. + P1_10: u2, // bit offset: 20 desc: Pin function select P1.10. + P1_14: u2, // bit offset: 22 desc: Pin function select P1.14. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + P1_15: u2, // bit offset: 30 desc: Pin function select P1.15. + }); + // byte offset: 12 Pin function select register 3. + pub const PINSEL3 = mmio(Address + 0x0000000c, 32, packed struct { + P1_16: u2, // bit offset: 0 desc: Pin function select P1.16. + P1_17: u2, // bit offset: 2 desc: Pin function select P1.17. + P1_18: u2, // bit offset: 4 desc: Pin function select P1.18. + P1_19: u2, // bit offset: 6 desc: Pin function select P1.19. + P1_20: u2, // bit offset: 8 desc: Pin function select P1.20. + P1_21: u2, // bit offset: 10 desc: Pin function select P1.21. + P1_22: u2, // bit offset: 12 desc: Pin function select P1.22 + P1_23: u2, // bit offset: 14 desc: Pin function select P1.23. + P1_24: u2, // bit offset: 16 desc: Pin function select P1.24. + P1_25: u2, // bit offset: 18 desc: Pin function select P1.25. + P1_26: u2, // bit offset: 20 desc: Pin function select P1.26. + P1_27: u2, // bit offset: 22 desc: Pin function select P1.27. + P1_28: u2, // bit offset: 24 desc: Pin function select P1.28. + P1_29: u2, // bit offset: 26 desc: Pin function select P1.29 + P1_30: u2, // bit offset: 28 desc: Pin function select P1.30. + P1_31: u2, // bit offset: 30 desc: Pin function select P1.31. + }); + // byte offset: 16 Pin function select register 4 + pub const PINSEL4 = mmio(Address + 0x00000010, 32, packed struct { + P2_0: u2, // bit offset: 0 desc: Pin function select P2.0. + P2_1: u2, // bit offset: 2 desc: Pin function select P2.1. + P2_2: u2, // bit offset: 4 desc: Pin function select P2.2. + P2_3: u2, // bit offset: 6 desc: Pin function select P2.3. + P2_4: u2, // bit offset: 8 desc: Pin function select P2.4. + P2_5: u2, // bit offset: 10 desc: Pin function select P2.5. + P2_6: u2, // bit offset: 12 desc: Pin function select P2.6. + P2_7: u2, // bit offset: 14 desc: Pin function select P2.7. + P2_8: u2, // bit offset: 16 desc: Pin function select P2.8. + P2_9: u2, // bit offset: 18 desc: Pin function select P2.9. + P2_10: u2, // bit offset: 20 desc: Pin function select P2.10. + P2_11: u2, // bit offset: 22 desc: Pin function select P2.11. + P2_12: u2, // bit offset: 24 desc: Pin function select P2.12. + P2_13: u2, // bit offset: 26 desc: Pin function select P2.13. + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Pin function select register 7 + pub const PINSEL7 = mmio(Address + 0x0000001c, 32, packed struct { + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P3_25: u2, // bit offset: 18 desc: Pin function select P3.25. + P3_26: u2, // bit offset: 20 desc: Pin function select P3.26. + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Pin function select register 9 + pub const PINSEL9 = mmio(Address + 0x00000024, 32, packed struct { + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P4_28: u2, // bit offset: 24 desc: Pin function select P4.28. + P4_29: u2, // bit offset: 26 desc: Pin function select P4.29. + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Pin function select register 10 + pub const PINSEL10 = mmio(Address + 0x00000028, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TPIUCTRL: bool, // bit offset: 3 desc: TPIU interface pins control. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 Pin mode select register 0 + pub const PINMODE0 = mmio(Address + 0x00000040, 32, packed struct { + P0_00MODE: u2, // bit offset: 0 desc: Port 0 pin 0 on-chip pull-up/down resistor control. + P0_01MODE: u2, // bit offset: 2 desc: Port 0 pin 1 control. + P0_02MODE: u2, // bit offset: 4 desc: Port 0 pin 2 control. + P0_03MODE: u2, // bit offset: 6 desc: Port 0 pin 3 control. + P0_04MODE: u2, // bit offset: 8 desc: Port 0 pin 4 control. + P0_05MODE: u2, // bit offset: 10 desc: Port 0 pin 5 control. + P0_06MODE: u2, // bit offset: 12 desc: Port 0 pin 6 control. + P0_07MODE: u2, // bit offset: 14 desc: Port 0 pin 7 control. + P0_08MODE: u2, // bit offset: 16 desc: Port 0 pin 8 control. + P0_09MODE: u2, // bit offset: 18 desc: Port 0 pin 9 control. + P0_10MODE: u2, // bit offset: 20 desc: Port 0 pin 10 control. + P0_11MODE: u2, // bit offset: 22 desc: Port 0 pin 11 control. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P0_15MODE: u2, // bit offset: 30 desc: Port 0 pin 15 control. + }); + // byte offset: 68 Pin mode select register 1 + pub const PINMODE1 = mmio(Address + 0x00000044, 32, packed struct { + P0_16MODE: u2, // bit offset: 0 desc: Port 1 pin 16 control. + P0_17MODE: u2, // bit offset: 2 desc: Port 1 pin 17 control. + P0_18MODE: u2, // bit offset: 4 desc: Port 1 pin 18 control. + P0_19MODE: u2, // bit offset: 6 desc: Port 1 pin 19 control. + P0_20MODE: u2, // bit offset: 8 desc: Port 1 pin 20 control. + P0_21MODE: u2, // bit offset: 10 desc: Port 1 pin 21 control. + P0_22MODE: u2, // bit offset: 12 desc: Port 1 pin 22 control. + P0_23MODE: u2, // bit offset: 14 desc: Port 1 pin 23 control. + P0_24MODE: u2, // bit offset: 16 desc: Port 1 pin 24 control. + P0_25MODE: u2, // bit offset: 18 desc: Port 1 pin 25 control. + P0_26MODE: u2, // bit offset: 20 desc: Port 1 pin 26 control. + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 Pin mode select register 2 + pub const PINMODE2 = mmio(Address + 0x00000048, 32, packed struct { + P1_00MODE: u2, // bit offset: 0 desc: Port 1 pin 0 control. + P1_01MODE: u2, // bit offset: 2 desc: Port 1 pin 1 control. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P1_04MODE: u2, // bit offset: 8 desc: Port 1 pin 4 control. + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + P1_08MODE: u2, // bit offset: 16 desc: Port 1 pin 8 control. + P1_09MODE: u2, // bit offset: 18 desc: Port 1 pin 9 control. + P1_10MODE: u2, // bit offset: 20 desc: Port 1 pin 10 control. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + P1_14MODE: u2, // bit offset: 28 desc: Port 1 pin 14 control. + P1_15MODE: u2, // bit offset: 30 desc: Port 1 pin 15 control. + }); + // byte offset: 76 Pin mode select register 3. + pub const PINMODE3 = mmio(Address + 0x0000004c, 32, packed struct { + P1_16MODE: u2, // bit offset: 0 desc: Port 1 pin 16 control. + P1_17MODE: u2, // bit offset: 2 desc: Port 1 pin 17 control. + P1_18MODE: u2, // bit offset: 4 desc: Port 1 pin 18 control. + P1_19MODE: u2, // bit offset: 6 desc: Port 1 pin 19 control. + P1_20MODE: u2, // bit offset: 8 desc: Port 1 pin 20 control. + P1_21MODE: u2, // bit offset: 10 desc: Port 1 pin 21 control. + P1_22MODE: u2, // bit offset: 12 desc: Port 1 pin 22 control. + P1_23MODE: u2, // bit offset: 14 desc: Port 1 pin 23 control. + P1_24MODE: u2, // bit offset: 16 desc: Port 1 pin 24 control. + P1_25MODE: u2, // bit offset: 18 desc: Port 1 pin 25 control. + P1_26MODE: u2, // bit offset: 20 desc: Port 1 pin 26 control. + P1_27MODE: u2, // bit offset: 22 desc: Port 1 pin 27 control. + P1_28MODE: u2, // bit offset: 24 desc: Port 1 pin 28 control. + P1_29MODE: u2, // bit offset: 26 desc: Port 1 pin 29 control. + P1_30MODE: u2, // bit offset: 28 desc: Port 1 pin 30 control. + P1_31MODE: u2, // bit offset: 30 desc: Port 1 pin 31 control. + }); + // byte offset: 80 Pin mode select register 4 + pub const PINMODE4 = mmio(Address + 0x00000050, 32, packed struct { + P2_00MODE: u2, // bit offset: 0 desc: Port 2 pin 0 control. + P2_01MODE: u2, // bit offset: 2 desc: Port 2 pin 1 control. + P2_02MODE: u2, // bit offset: 4 desc: Port 2 pin 2 control. + P2_03MODE: u2, // bit offset: 6 desc: Port 2 pin 3 control. + P2_04MODE: u2, // bit offset: 8 desc: Port 2 pin 4 control. + P2_05MODE: u2, // bit offset: 10 desc: Port 2 pin 5 control. + P2_06MODE: u2, // bit offset: 12 desc: Port 2 pin 6 control. + P2_07MODE: u2, // bit offset: 14 desc: Port 2 pin 7 control. + P2_08MODE: u2, // bit offset: 16 desc: Port 2 pin 8 control. + P2_09MODE: u2, // bit offset: 18 desc: Port 2 pin 9 control. + P2_10MODE: u2, // bit offset: 20 desc: Port 2 pin 10 control. + P2_11MODE: u2, // bit offset: 22 desc: Port 2 pin 11 control. + P2_12MODE: u2, // bit offset: 24 desc: Port 2 pin 12 control. + P2_13MODE: u2, // bit offset: 26 desc: Port 2 pin 13 control. + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 Pin mode select register 7 + pub const PINMODE7 = mmio(Address + 0x0000005c, 32, packed struct { + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P3_25MODE: u2, // bit offset: 18 desc: Port 3 pin 25 control. + P3_26MODE: u2, // bit offset: 20 desc: Port 3 pin 26 control. + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 100 Pin mode select register 9 + pub const PINMODE9 = mmio(Address + 0x00000064, 32, packed struct { + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P4_28MODE: u2, // bit offset: 24 desc: Port 4 pin 28 control. + P4_29MODE: u2, // bit offset: 26 desc: Port 4 pin 29 control. + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 104 Open drain mode control register 0 + pub const PINMODE_OD0 = mmio(Address + 0x00000068, 32, packed struct { + P0_00OD: bool, // bit offset: 0 desc: Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_01OD: bool, // bit offset: 1 desc: Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_02OD: bool, // bit offset: 2 desc: Port 0 pin 2 open drain mode control + P0_03OD: bool, // bit offset: 3 desc: Port 0 pin 3 open drain mode control + P0_04OD: bool, // bit offset: 4 desc: Port 0 pin 4 open drain mode control + P0_05OD: bool, // bit offset: 5 desc: Port 0 pin 5 open drain mode control + P0_06OD: bool, // bit offset: 6 desc: Port 0 pin 6 open drain mode control + P0_07OD: bool, // bit offset: 7 desc: Port 0 pin 7 open drain mode control + P0_08OD: bool, // bit offset: 8 desc: Port 0 pin 8 open drain mode control + P0_09OD: bool, // bit offset: 9 desc: Port 0 pin 9 open drain mode control + P0_10OD: bool, // bit offset: 10 desc: Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_11OD: bool, // bit offset: 11 desc: Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P0_15OD: bool, // bit offset: 15 desc: Port 0 pin 15 open drain mode control + P0_16OD: bool, // bit offset: 16 desc: Port 0 pin 16 open drain mode control + P0_17OD: bool, // bit offset: 17 desc: Port 0 pin 17 open drain mode control + P0_18OD: bool, // bit offset: 18 desc: Port 0 pin 18 open drain mode control + P0_19OD: bool, // bit offset: 19 desc: Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_20OD: bool, // bit offset: 20 desc: Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_21OD: bool, // bit offset: 21 desc: Port 0 pin 21 open drain mode control + P0_22OD: bool, // bit offset: 22 desc: Port 0 pin 22 open drain mode control + P0_23OD: bool, // bit offset: 23 desc: Port 0 pin 23 open drain mode control + P0_24OD: bool, // bit offset: 24 desc: Port 0 pin 24open drain mode control + P0_25OD: bool, // bit offset: 25 desc: Port 0 pin 25 open drain mode control + P0_26OD: bool, // bit offset: 26 desc: Port 0 pin 26 open drain mode control + reserved3: u1 = 0, + reserved2: u1 = 0, + P0_29OD: bool, // bit offset: 29 desc: Port 0 pin 29 open drain mode control + P0_30OD: bool, // bit offset: 30 desc: Port 0 pin 30 open drain mode control + padding1: u1 = 0, + }); + // byte offset: 108 Open drain mode control register 1 + pub const PINMODE_OD1 = mmio(Address + 0x0000006c, 32, packed struct { + P1_00OD: bool, // bit offset: 0 desc: Port 1 pin 0 open drain mode control. + P1_01OD: bool, // bit offset: 1 desc: Port 1 pin 1 open drain mode control, see P1.00OD + reserved2: u1 = 0, + reserved1: u1 = 0, + P1_04OD: bool, // bit offset: 4 desc: Port 1 pin 4 open drain mode control, see P1.00OD + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + P1_08OD: bool, // bit offset: 8 desc: Port 1 pin 8 open drain mode control, see P1.00OD + P1_09OD: bool, // bit offset: 9 desc: Port 1 pin 9 open drain mode control, see P1.00OD + P1_10OD: bool, // bit offset: 10 desc: Port 1 pin 10 open drain mode control, see P1.00OD + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + P1_14OD: bool, // bit offset: 14 desc: Port 1 pin 14 open drain mode control, see P1.00OD + P1_15OD: bool, // bit offset: 15 desc: Port 1 pin 15 open drain mode control, see P1.00OD + P1_16OD: bool, // bit offset: 16 desc: Port 1 pin 16 open drain mode control, see P1.00OD + P1_17OD: bool, // bit offset: 17 desc: Port 1 pin 17 open drain mode control, see P1.00OD + P1_18OD: bool, // bit offset: 18 desc: Port 1 pin 18 open drain mode control, see P1.00OD + P1_19OD: bool, // bit offset: 19 desc: Port 1 pin 19 open drain mode control, see P1.00OD + P1_20OD: bool, // bit offset: 20 desc: Port 1 pin 20open drain mode control, see P1.00OD + P1_21OD: bool, // bit offset: 21 desc: Port 1 pin 21 open drain mode control, see P1.00OD + P1_22OD: bool, // bit offset: 22 desc: Port 1 pin 22 open drain mode control, see P1.00OD + P1_23OD: bool, // bit offset: 23 desc: Port 1 pin 23 open drain mode control, see P1.00OD + P1_24OD: bool, // bit offset: 24 desc: Port 1 pin 24open drain mode control, see P1.00OD + P1_25OD: bool, // bit offset: 25 desc: Port 1 pin 25 open drain mode control, see P1.00OD + P1_26OD: bool, // bit offset: 26 desc: Port 1 pin 26 open drain mode control, see P1.00OD + P1_27OD: bool, // bit offset: 27 desc: Port 1 pin 27 open drain mode control, see P1.00OD + P1_28OD: bool, // bit offset: 28 desc: Port 1 pin 28 open drain mode control, see P1.00OD + P1_29OD: bool, // bit offset: 29 desc: Port 1 pin 29 open drain mode control, see P1.00OD + P1_30OD: bool, // bit offset: 30 desc: Port 1 pin 30 open drain mode control, see P1.00OD + P1_31OD: bool, // bit offset: 31 desc: Port 1 pin 31 open drain mode control. + }); + // byte offset: 112 Open drain mode control register 2 + pub const PINMODE_OD2 = mmio(Address + 0x00000070, 32, packed struct { + P2_00OD: bool, // bit offset: 0 desc: Port 2 pin 0 open drain mode control. + P2_01OD: bool, // bit offset: 1 desc: Port 2 pin 1 open drain mode control, see P2.00OD + P2_02OD: bool, // bit offset: 2 desc: Port 2 pin 2 open drain mode control, see P2.00OD + P2_03OD: bool, // bit offset: 3 desc: Port 2 pin 3 open drain mode control, see P2.00OD + P2_04OD: bool, // bit offset: 4 desc: Port 2 pin 4 open drain mode control, see P2.00OD + P2_05OD: bool, // bit offset: 5 desc: Port 2 pin 5 open drain mode control, see P2.00OD + P2_06OD: bool, // bit offset: 6 desc: Port 2 pin 6 open drain mode control, see P2.00OD + P2_07OD: bool, // bit offset: 7 desc: Port 2 pin 7 open drain mode control, see P2.00OD + P2_08OD: bool, // bit offset: 8 desc: Port 2 pin 8 open drain mode control, see P2.00OD + P2_09OD: bool, // bit offset: 9 desc: Port 2 pin 9 open drain mode control, see P2.00OD + P2_10OD: bool, // bit offset: 10 desc: Port 2 pin 10 open drain mode control, see P2.00OD + P2_11OD: bool, // bit offset: 11 desc: Port 2 pin 11 open drain mode control, see P2.00OD + P2_12OD: bool, // bit offset: 12 desc: Port 2 pin 12 open drain mode control, see P2.00OD + P2_13OD: bool, // bit offset: 13 desc: Port 2 pin 13 open drain mode control, see P2.00OD + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 Open drain mode control register 3 + pub const PINMODE_OD3 = mmio(Address + 0x00000074, 32, packed struct { + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P3_25OD: bool, // bit offset: 25 desc: Port 3 pin 25 open drain mode control. + P3_26OD: bool, // bit offset: 26 desc: Port 3 pin 26 open drain mode control, see P3.25OD + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 120 Open drain mode control register 4 + pub const PINMODE_OD4 = mmio(Address + 0x00000078, 32, packed struct { + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + P4_28OD: bool, // bit offset: 28 desc: Port 4 pin 28 open drain mode control. + P4_29OD: bool, // bit offset: 29 desc: Port 4 pin 29 open drain mode control, see P4.28OD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 124 I2C Pin Configuration register + pub const I2CPADCFG = mmio(Address + 0x0000007c, 32, packed struct { + SDADRV0: bool, // bit offset: 0 desc: Drive mode control for the SDA0 pin, P0.27. + SDAI2C0: bool, // bit offset: 1 desc: I 2C filter mode control for the SDA0 pin, P0.27. + SCLDRV0: bool, // bit offset: 2 desc: Drive mode control for the SCL0 pin, P0.28. + SCLI2C0: bool, // bit offset: 3 desc: I 2C filter mode control for the SCL0 pin, P0.28. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SSP1 = extern struct { + pub const Address: u32 = 0x40030000; + // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { + DSS: u4, // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + FRF: u2, // bit offset: 4 desc: Frame Format. + CPOL: bool, // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. + CPHA: bool, // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control Register 1. Selects master/slave and other modes. + pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { + LBM: bool, // bit offset: 0 desc: Loop Back Mode. + SSE: bool, // bit offset: 1 desc: SSP Enable. + MS: bool, // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. + SOD: bool, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = mmio(Address + 0x00000008, 32, packed struct { + DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Status Register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + TFE: bool, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TNF: bool, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + RNE: bool, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RFF: bool, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + BSY: bool, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Clock Prescale Register + pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { + CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Interrupt Mask Set and Clear Register + pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { + RORIM: bool, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTIM: bool, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXIM: bool, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + TXIM: bool, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Raw Interrupt Status Register + pub const RIS = mmio(Address + 0x00000018, 32, packed struct { + RORRIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTRIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXRIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. + TXRIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Masked Interrupt Status Register + pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { + RORMIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + RTMIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXMIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + TXMIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 SSPICR Interrupt Clear Register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + RORIC: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + RTIC: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 SSP0 DMA control register + pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { + RXDMAE: bool, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. + TXDMAE: bool, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC = extern struct { + pub const Address: u32 = 0x40034000; + // byte offset: 0 A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + SEL: u8, // bit offset: 0 desc: Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. + CLKDIV: u8, // bit offset: 8 desc: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. + BURST: bool, // bit offset: 16 desc: Burst mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PDN: bool, // bit offset: 21 desc: Power down mode + reserved3: u1 = 0, + reserved2: u1 = 0, + START: u3, // bit offset: 24 desc: When the BURST bit is 0, these bits control whether and when an A/D conversion is started: + EDGE: bool, // bit offset: 27 desc: This bit is significant only when the START field contains 010-111. In these cases: + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion. + pub const GDR = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. + }); + // byte offset: 12 A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. + pub const INTEN = mmio(Address + 0x0000000c, 32, packed struct { + ADINTEN0: bool, // bit offset: 0 desc: Interrupt enable + ADINTEN1: bool, // bit offset: 1 desc: Interrupt enable + ADINTEN2: bool, // bit offset: 2 desc: Interrupt enable + ADINTEN3: bool, // bit offset: 3 desc: Interrupt enable + ADINTEN4: bool, // bit offset: 4 desc: Interrupt enable + ADINTEN5: bool, // bit offset: 5 desc: Interrupt enable + ADINTEN6: bool, // bit offset: 6 desc: Interrupt enable + ADINTEN7: bool, // bit offset: 7 desc: Interrupt enable + ADGINTEN: bool, // bit offset: 8 desc: Interrupt enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_0 = mmio(Address + 0x00000010, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 20 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_1 = mmio(Address + 0x00000014, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 24 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_2 = mmio(Address + 0x00000018, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 28 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_3 = mmio(Address + 0x0000001c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 32 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_4 = mmio(Address + 0x00000020, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 36 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_5 = mmio(Address + 0x00000024, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 40 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_6 = mmio(Address + 0x00000028, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 44 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. + pub const DR_7 = mmio(Address + 0x0000002c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }); + // byte offset: 48 A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. + pub const STAT = mmio(Address + 0x00000030, 32, packed struct { + DONE0: bool, // bit offset: 0 desc: This bit mirrors the DONE status flag from the result register for A/D channel 0. + DONE1: bool, // bit offset: 1 desc: This bit mirrors the DONE status flag from the result register for A/D channel 1. + DONE2: bool, // bit offset: 2 desc: This bit mirrors the DONE status flag from the result register for A/D channel 2. + DONE3: bool, // bit offset: 3 desc: This bit mirrors the DONE status flag from the result register for A/D channel 3. + DONE4: bool, // bit offset: 4 desc: This bit mirrors the DONE status flag from the result register for A/D channel 4. + DONE5: bool, // bit offset: 5 desc: This bit mirrors the DONE status flag from the result register for A/D channel 5. + DONE6: bool, // bit offset: 6 desc: This bit mirrors the DONE status flag from the result register for A/D channel 6. + DONE7: bool, // bit offset: 7 desc: This bit mirrors the DONE status flag from the result register for A/D channel 7. + OVERRUN0: bool, // bit offset: 8 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. + OVERRUN1: bool, // bit offset: 9 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. + OVERRUN2: bool, // bit offset: 10 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. + OVERRUN3: bool, // bit offset: 11 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. + OVERRUN4: bool, // bit offset: 12 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. + OVERRUN5: bool, // bit offset: 13 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. + OVERRUN6: bool, // bit offset: 14 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. + OVERRUN7: bool, // bit offset: 15 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. + ADINT: bool, // bit offset: 16 desc: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 ADC trim register. + pub const TRM = mmio(Address + 0x00000034, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADCOFFS: u4, // bit offset: 4 desc: Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. + TRIM: u4, // bit offset: 8 desc: written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CANAFRAM = extern struct { + pub const Address: u32 = 0x40038000; + // byte offset: 0 CAN AF ram access register + pub const MASK_0 = mmio(Address + 0x00000000, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 4 CAN AF ram access register + pub const MASK_1 = mmio(Address + 0x00000004, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 8 CAN AF ram access register + pub const MASK_2 = mmio(Address + 0x00000008, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 12 CAN AF ram access register + pub const MASK_3 = mmio(Address + 0x0000000c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 16 CAN AF ram access register + pub const MASK_4 = mmio(Address + 0x00000010, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 20 CAN AF ram access register + pub const MASK_5 = mmio(Address + 0x00000014, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 24 CAN AF ram access register + pub const MASK_6 = mmio(Address + 0x00000018, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 28 CAN AF ram access register + pub const MASK_7 = mmio(Address + 0x0000001c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 32 CAN AF ram access register + pub const MASK_8 = mmio(Address + 0x00000020, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 36 CAN AF ram access register + pub const MASK_9 = mmio(Address + 0x00000024, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 40 CAN AF ram access register + pub const MASK_10 = mmio(Address + 0x00000028, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 44 CAN AF ram access register + pub const MASK_11 = mmio(Address + 0x0000002c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 48 CAN AF ram access register + pub const MASK_12 = mmio(Address + 0x00000030, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 52 CAN AF ram access register + pub const MASK_13 = mmio(Address + 0x00000034, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 56 CAN AF ram access register + pub const MASK_14 = mmio(Address + 0x00000038, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 60 CAN AF ram access register + pub const MASK_15 = mmio(Address + 0x0000003c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 64 CAN AF ram access register + pub const MASK_16 = mmio(Address + 0x00000040, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 68 CAN AF ram access register + pub const MASK_17 = mmio(Address + 0x00000044, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 72 CAN AF ram access register + pub const MASK_18 = mmio(Address + 0x00000048, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 76 CAN AF ram access register + pub const MASK_19 = mmio(Address + 0x0000004c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 80 CAN AF ram access register + pub const MASK_20 = mmio(Address + 0x00000050, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 84 CAN AF ram access register + pub const MASK_21 = mmio(Address + 0x00000054, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 88 CAN AF ram access register + pub const MASK_22 = mmio(Address + 0x00000058, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 92 CAN AF ram access register + pub const MASK_23 = mmio(Address + 0x0000005c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 96 CAN AF ram access register + pub const MASK_24 = mmio(Address + 0x00000060, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 100 CAN AF ram access register + pub const MASK_25 = mmio(Address + 0x00000064, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 104 CAN AF ram access register + pub const MASK_26 = mmio(Address + 0x00000068, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 108 CAN AF ram access register + pub const MASK_27 = mmio(Address + 0x0000006c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 112 CAN AF ram access register + pub const MASK_28 = mmio(Address + 0x00000070, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 116 CAN AF ram access register + pub const MASK_29 = mmio(Address + 0x00000074, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 120 CAN AF ram access register + pub const MASK_30 = mmio(Address + 0x00000078, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 124 CAN AF ram access register + pub const MASK_31 = mmio(Address + 0x0000007c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 128 CAN AF ram access register + pub const MASK_32 = mmio(Address + 0x00000080, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 132 CAN AF ram access register + pub const MASK_33 = mmio(Address + 0x00000084, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 136 CAN AF ram access register + pub const MASK_34 = mmio(Address + 0x00000088, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 140 CAN AF ram access register + pub const MASK_35 = mmio(Address + 0x0000008c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 144 CAN AF ram access register + pub const MASK_36 = mmio(Address + 0x00000090, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 148 CAN AF ram access register + pub const MASK_37 = mmio(Address + 0x00000094, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 152 CAN AF ram access register + pub const MASK_38 = mmio(Address + 0x00000098, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 156 CAN AF ram access register + pub const MASK_39 = mmio(Address + 0x0000009c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 160 CAN AF ram access register + pub const MASK_40 = mmio(Address + 0x000000a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 164 CAN AF ram access register + pub const MASK_41 = mmio(Address + 0x000000a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 168 CAN AF ram access register + pub const MASK_42 = mmio(Address + 0x000000a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 172 CAN AF ram access register + pub const MASK_43 = mmio(Address + 0x000000ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 176 CAN AF ram access register + pub const MASK_44 = mmio(Address + 0x000000b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 180 CAN AF ram access register + pub const MASK_45 = mmio(Address + 0x000000b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 184 CAN AF ram access register + pub const MASK_46 = mmio(Address + 0x000000b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 188 CAN AF ram access register + pub const MASK_47 = mmio(Address + 0x000000bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 192 CAN AF ram access register + pub const MASK_48 = mmio(Address + 0x000000c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 196 CAN AF ram access register + pub const MASK_49 = mmio(Address + 0x000000c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 200 CAN AF ram access register + pub const MASK_50 = mmio(Address + 0x000000c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 204 CAN AF ram access register + pub const MASK_51 = mmio(Address + 0x000000cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 208 CAN AF ram access register + pub const MASK_52 = mmio(Address + 0x000000d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 212 CAN AF ram access register + pub const MASK_53 = mmio(Address + 0x000000d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 216 CAN AF ram access register + pub const MASK_54 = mmio(Address + 0x000000d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 220 CAN AF ram access register + pub const MASK_55 = mmio(Address + 0x000000dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 224 CAN AF ram access register + pub const MASK_56 = mmio(Address + 0x000000e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 228 CAN AF ram access register + pub const MASK_57 = mmio(Address + 0x000000e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 232 CAN AF ram access register + pub const MASK_58 = mmio(Address + 0x000000e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 236 CAN AF ram access register + pub const MASK_59 = mmio(Address + 0x000000ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 240 CAN AF ram access register + pub const MASK_60 = mmio(Address + 0x000000f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 244 CAN AF ram access register + pub const MASK_61 = mmio(Address + 0x000000f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 248 CAN AF ram access register + pub const MASK_62 = mmio(Address + 0x000000f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 252 CAN AF ram access register + pub const MASK_63 = mmio(Address + 0x000000fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 256 CAN AF ram access register + pub const MASK_64 = mmio(Address + 0x00000100, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 260 CAN AF ram access register + pub const MASK_65 = mmio(Address + 0x00000104, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 264 CAN AF ram access register + pub const MASK_66 = mmio(Address + 0x00000108, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 268 CAN AF ram access register + pub const MASK_67 = mmio(Address + 0x0000010c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 272 CAN AF ram access register + pub const MASK_68 = mmio(Address + 0x00000110, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 276 CAN AF ram access register + pub const MASK_69 = mmio(Address + 0x00000114, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 280 CAN AF ram access register + pub const MASK_70 = mmio(Address + 0x00000118, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 284 CAN AF ram access register + pub const MASK_71 = mmio(Address + 0x0000011c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 288 CAN AF ram access register + pub const MASK_72 = mmio(Address + 0x00000120, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 292 CAN AF ram access register + pub const MASK_73 = mmio(Address + 0x00000124, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 296 CAN AF ram access register + pub const MASK_74 = mmio(Address + 0x00000128, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 300 CAN AF ram access register + pub const MASK_75 = mmio(Address + 0x0000012c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 304 CAN AF ram access register + pub const MASK_76 = mmio(Address + 0x00000130, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 308 CAN AF ram access register + pub const MASK_77 = mmio(Address + 0x00000134, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 312 CAN AF ram access register + pub const MASK_78 = mmio(Address + 0x00000138, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 316 CAN AF ram access register + pub const MASK_79 = mmio(Address + 0x0000013c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 320 CAN AF ram access register + pub const MASK_80 = mmio(Address + 0x00000140, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 324 CAN AF ram access register + pub const MASK_81 = mmio(Address + 0x00000144, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 328 CAN AF ram access register + pub const MASK_82 = mmio(Address + 0x00000148, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 332 CAN AF ram access register + pub const MASK_83 = mmio(Address + 0x0000014c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 336 CAN AF ram access register + pub const MASK_84 = mmio(Address + 0x00000150, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 340 CAN AF ram access register + pub const MASK_85 = mmio(Address + 0x00000154, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 344 CAN AF ram access register + pub const MASK_86 = mmio(Address + 0x00000158, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 348 CAN AF ram access register + pub const MASK_87 = mmio(Address + 0x0000015c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 352 CAN AF ram access register + pub const MASK_88 = mmio(Address + 0x00000160, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 356 CAN AF ram access register + pub const MASK_89 = mmio(Address + 0x00000164, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 360 CAN AF ram access register + pub const MASK_90 = mmio(Address + 0x00000168, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 364 CAN AF ram access register + pub const MASK_91 = mmio(Address + 0x0000016c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 368 CAN AF ram access register + pub const MASK_92 = mmio(Address + 0x00000170, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 372 CAN AF ram access register + pub const MASK_93 = mmio(Address + 0x00000174, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 376 CAN AF ram access register + pub const MASK_94 = mmio(Address + 0x00000178, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 380 CAN AF ram access register + pub const MASK_95 = mmio(Address + 0x0000017c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 384 CAN AF ram access register + pub const MASK_96 = mmio(Address + 0x00000180, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 388 CAN AF ram access register + pub const MASK_97 = mmio(Address + 0x00000184, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 392 CAN AF ram access register + pub const MASK_98 = mmio(Address + 0x00000188, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 396 CAN AF ram access register + pub const MASK_99 = mmio(Address + 0x0000018c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 400 CAN AF ram access register + pub const MASK_100 = mmio(Address + 0x00000190, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 404 CAN AF ram access register + pub const MASK_101 = mmio(Address + 0x00000194, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 408 CAN AF ram access register + pub const MASK_102 = mmio(Address + 0x00000198, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 412 CAN AF ram access register + pub const MASK_103 = mmio(Address + 0x0000019c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 416 CAN AF ram access register + pub const MASK_104 = mmio(Address + 0x000001a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 420 CAN AF ram access register + pub const MASK_105 = mmio(Address + 0x000001a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 424 CAN AF ram access register + pub const MASK_106 = mmio(Address + 0x000001a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 428 CAN AF ram access register + pub const MASK_107 = mmio(Address + 0x000001ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 432 CAN AF ram access register + pub const MASK_108 = mmio(Address + 0x000001b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 436 CAN AF ram access register + pub const MASK_109 = mmio(Address + 0x000001b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 440 CAN AF ram access register + pub const MASK_110 = mmio(Address + 0x000001b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 444 CAN AF ram access register + pub const MASK_111 = mmio(Address + 0x000001bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 448 CAN AF ram access register + pub const MASK_112 = mmio(Address + 0x000001c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 452 CAN AF ram access register + pub const MASK_113 = mmio(Address + 0x000001c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 456 CAN AF ram access register + pub const MASK_114 = mmio(Address + 0x000001c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 460 CAN AF ram access register + pub const MASK_115 = mmio(Address + 0x000001cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 464 CAN AF ram access register + pub const MASK_116 = mmio(Address + 0x000001d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 468 CAN AF ram access register + pub const MASK_117 = mmio(Address + 0x000001d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 472 CAN AF ram access register + pub const MASK_118 = mmio(Address + 0x000001d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 476 CAN AF ram access register + pub const MASK_119 = mmio(Address + 0x000001dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 480 CAN AF ram access register + pub const MASK_120 = mmio(Address + 0x000001e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 484 CAN AF ram access register + pub const MASK_121 = mmio(Address + 0x000001e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 488 CAN AF ram access register + pub const MASK_122 = mmio(Address + 0x000001e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 492 CAN AF ram access register + pub const MASK_123 = mmio(Address + 0x000001ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 496 CAN AF ram access register + pub const MASK_124 = mmio(Address + 0x000001f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 500 CAN AF ram access register + pub const MASK_125 = mmio(Address + 0x000001f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 504 CAN AF ram access register + pub const MASK_126 = mmio(Address + 0x000001f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 508 CAN AF ram access register + pub const MASK_127 = mmio(Address + 0x000001fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 512 CAN AF ram access register + pub const MASK_128 = mmio(Address + 0x00000200, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 516 CAN AF ram access register + pub const MASK_129 = mmio(Address + 0x00000204, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 520 CAN AF ram access register + pub const MASK_130 = mmio(Address + 0x00000208, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 524 CAN AF ram access register + pub const MASK_131 = mmio(Address + 0x0000020c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 528 CAN AF ram access register + pub const MASK_132 = mmio(Address + 0x00000210, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 532 CAN AF ram access register + pub const MASK_133 = mmio(Address + 0x00000214, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 536 CAN AF ram access register + pub const MASK_134 = mmio(Address + 0x00000218, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 540 CAN AF ram access register + pub const MASK_135 = mmio(Address + 0x0000021c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 544 CAN AF ram access register + pub const MASK_136 = mmio(Address + 0x00000220, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 548 CAN AF ram access register + pub const MASK_137 = mmio(Address + 0x00000224, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 552 CAN AF ram access register + pub const MASK_138 = mmio(Address + 0x00000228, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 556 CAN AF ram access register + pub const MASK_139 = mmio(Address + 0x0000022c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 560 CAN AF ram access register + pub const MASK_140 = mmio(Address + 0x00000230, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 564 CAN AF ram access register + pub const MASK_141 = mmio(Address + 0x00000234, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 568 CAN AF ram access register + pub const MASK_142 = mmio(Address + 0x00000238, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 572 CAN AF ram access register + pub const MASK_143 = mmio(Address + 0x0000023c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 576 CAN AF ram access register + pub const MASK_144 = mmio(Address + 0x00000240, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 580 CAN AF ram access register + pub const MASK_145 = mmio(Address + 0x00000244, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 584 CAN AF ram access register + pub const MASK_146 = mmio(Address + 0x00000248, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 588 CAN AF ram access register + pub const MASK_147 = mmio(Address + 0x0000024c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 592 CAN AF ram access register + pub const MASK_148 = mmio(Address + 0x00000250, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 596 CAN AF ram access register + pub const MASK_149 = mmio(Address + 0x00000254, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 600 CAN AF ram access register + pub const MASK_150 = mmio(Address + 0x00000258, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 604 CAN AF ram access register + pub const MASK_151 = mmio(Address + 0x0000025c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 608 CAN AF ram access register + pub const MASK_152 = mmio(Address + 0x00000260, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 612 CAN AF ram access register + pub const MASK_153 = mmio(Address + 0x00000264, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 616 CAN AF ram access register + pub const MASK_154 = mmio(Address + 0x00000268, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 620 CAN AF ram access register + pub const MASK_155 = mmio(Address + 0x0000026c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 624 CAN AF ram access register + pub const MASK_156 = mmio(Address + 0x00000270, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 628 CAN AF ram access register + pub const MASK_157 = mmio(Address + 0x00000274, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 632 CAN AF ram access register + pub const MASK_158 = mmio(Address + 0x00000278, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 636 CAN AF ram access register + pub const MASK_159 = mmio(Address + 0x0000027c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 640 CAN AF ram access register + pub const MASK_160 = mmio(Address + 0x00000280, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 644 CAN AF ram access register + pub const MASK_161 = mmio(Address + 0x00000284, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 648 CAN AF ram access register + pub const MASK_162 = mmio(Address + 0x00000288, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 652 CAN AF ram access register + pub const MASK_163 = mmio(Address + 0x0000028c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 656 CAN AF ram access register + pub const MASK_164 = mmio(Address + 0x00000290, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 660 CAN AF ram access register + pub const MASK_165 = mmio(Address + 0x00000294, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 664 CAN AF ram access register + pub const MASK_166 = mmio(Address + 0x00000298, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 668 CAN AF ram access register + pub const MASK_167 = mmio(Address + 0x0000029c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 672 CAN AF ram access register + pub const MASK_168 = mmio(Address + 0x000002a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 676 CAN AF ram access register + pub const MASK_169 = mmio(Address + 0x000002a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 680 CAN AF ram access register + pub const MASK_170 = mmio(Address + 0x000002a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 684 CAN AF ram access register + pub const MASK_171 = mmio(Address + 0x000002ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 688 CAN AF ram access register + pub const MASK_172 = mmio(Address + 0x000002b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 692 CAN AF ram access register + pub const MASK_173 = mmio(Address + 0x000002b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 696 CAN AF ram access register + pub const MASK_174 = mmio(Address + 0x000002b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 700 CAN AF ram access register + pub const MASK_175 = mmio(Address + 0x000002bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 704 CAN AF ram access register + pub const MASK_176 = mmio(Address + 0x000002c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 708 CAN AF ram access register + pub const MASK_177 = mmio(Address + 0x000002c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 712 CAN AF ram access register + pub const MASK_178 = mmio(Address + 0x000002c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 716 CAN AF ram access register + pub const MASK_179 = mmio(Address + 0x000002cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 720 CAN AF ram access register + pub const MASK_180 = mmio(Address + 0x000002d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 724 CAN AF ram access register + pub const MASK_181 = mmio(Address + 0x000002d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 728 CAN AF ram access register + pub const MASK_182 = mmio(Address + 0x000002d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 732 CAN AF ram access register + pub const MASK_183 = mmio(Address + 0x000002dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 736 CAN AF ram access register + pub const MASK_184 = mmio(Address + 0x000002e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 740 CAN AF ram access register + pub const MASK_185 = mmio(Address + 0x000002e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 744 CAN AF ram access register + pub const MASK_186 = mmio(Address + 0x000002e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 748 CAN AF ram access register + pub const MASK_187 = mmio(Address + 0x000002ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 752 CAN AF ram access register + pub const MASK_188 = mmio(Address + 0x000002f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 756 CAN AF ram access register + pub const MASK_189 = mmio(Address + 0x000002f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 760 CAN AF ram access register + pub const MASK_190 = mmio(Address + 0x000002f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 764 CAN AF ram access register + pub const MASK_191 = mmio(Address + 0x000002fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 768 CAN AF ram access register + pub const MASK_192 = mmio(Address + 0x00000300, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 772 CAN AF ram access register + pub const MASK_193 = mmio(Address + 0x00000304, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 776 CAN AF ram access register + pub const MASK_194 = mmio(Address + 0x00000308, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 780 CAN AF ram access register + pub const MASK_195 = mmio(Address + 0x0000030c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 784 CAN AF ram access register + pub const MASK_196 = mmio(Address + 0x00000310, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 788 CAN AF ram access register + pub const MASK_197 = mmio(Address + 0x00000314, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 792 CAN AF ram access register + pub const MASK_198 = mmio(Address + 0x00000318, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 796 CAN AF ram access register + pub const MASK_199 = mmio(Address + 0x0000031c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 800 CAN AF ram access register + pub const MASK_200 = mmio(Address + 0x00000320, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 804 CAN AF ram access register + pub const MASK_201 = mmio(Address + 0x00000324, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 808 CAN AF ram access register + pub const MASK_202 = mmio(Address + 0x00000328, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 812 CAN AF ram access register + pub const MASK_203 = mmio(Address + 0x0000032c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 816 CAN AF ram access register + pub const MASK_204 = mmio(Address + 0x00000330, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 820 CAN AF ram access register + pub const MASK_205 = mmio(Address + 0x00000334, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 824 CAN AF ram access register + pub const MASK_206 = mmio(Address + 0x00000338, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 828 CAN AF ram access register + pub const MASK_207 = mmio(Address + 0x0000033c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 832 CAN AF ram access register + pub const MASK_208 = mmio(Address + 0x00000340, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 836 CAN AF ram access register + pub const MASK_209 = mmio(Address + 0x00000344, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 840 CAN AF ram access register + pub const MASK_210 = mmio(Address + 0x00000348, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 844 CAN AF ram access register + pub const MASK_211 = mmio(Address + 0x0000034c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 848 CAN AF ram access register + pub const MASK_212 = mmio(Address + 0x00000350, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 852 CAN AF ram access register + pub const MASK_213 = mmio(Address + 0x00000354, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 856 CAN AF ram access register + pub const MASK_214 = mmio(Address + 0x00000358, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 860 CAN AF ram access register + pub const MASK_215 = mmio(Address + 0x0000035c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 864 CAN AF ram access register + pub const MASK_216 = mmio(Address + 0x00000360, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 868 CAN AF ram access register + pub const MASK_217 = mmio(Address + 0x00000364, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 872 CAN AF ram access register + pub const MASK_218 = mmio(Address + 0x00000368, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 876 CAN AF ram access register + pub const MASK_219 = mmio(Address + 0x0000036c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 880 CAN AF ram access register + pub const MASK_220 = mmio(Address + 0x00000370, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 884 CAN AF ram access register + pub const MASK_221 = mmio(Address + 0x00000374, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 888 CAN AF ram access register + pub const MASK_222 = mmio(Address + 0x00000378, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 892 CAN AF ram access register + pub const MASK_223 = mmio(Address + 0x0000037c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 896 CAN AF ram access register + pub const MASK_224 = mmio(Address + 0x00000380, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 900 CAN AF ram access register + pub const MASK_225 = mmio(Address + 0x00000384, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 904 CAN AF ram access register + pub const MASK_226 = mmio(Address + 0x00000388, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 908 CAN AF ram access register + pub const MASK_227 = mmio(Address + 0x0000038c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 912 CAN AF ram access register + pub const MASK_228 = mmio(Address + 0x00000390, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 916 CAN AF ram access register + pub const MASK_229 = mmio(Address + 0x00000394, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 920 CAN AF ram access register + pub const MASK_230 = mmio(Address + 0x00000398, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 924 CAN AF ram access register + pub const MASK_231 = mmio(Address + 0x0000039c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 928 CAN AF ram access register + pub const MASK_232 = mmio(Address + 0x000003a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 932 CAN AF ram access register + pub const MASK_233 = mmio(Address + 0x000003a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 936 CAN AF ram access register + pub const MASK_234 = mmio(Address + 0x000003a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 940 CAN AF ram access register + pub const MASK_235 = mmio(Address + 0x000003ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 944 CAN AF ram access register + pub const MASK_236 = mmio(Address + 0x000003b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 948 CAN AF ram access register + pub const MASK_237 = mmio(Address + 0x000003b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 952 CAN AF ram access register + pub const MASK_238 = mmio(Address + 0x000003b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 956 CAN AF ram access register + pub const MASK_239 = mmio(Address + 0x000003bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 960 CAN AF ram access register + pub const MASK_240 = mmio(Address + 0x000003c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 964 CAN AF ram access register + pub const MASK_241 = mmio(Address + 0x000003c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 968 CAN AF ram access register + pub const MASK_242 = mmio(Address + 0x000003c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 972 CAN AF ram access register + pub const MASK_243 = mmio(Address + 0x000003cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 976 CAN AF ram access register + pub const MASK_244 = mmio(Address + 0x000003d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 980 CAN AF ram access register + pub const MASK_245 = mmio(Address + 0x000003d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 984 CAN AF ram access register + pub const MASK_246 = mmio(Address + 0x000003d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 988 CAN AF ram access register + pub const MASK_247 = mmio(Address + 0x000003dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 992 CAN AF ram access register + pub const MASK_248 = mmio(Address + 0x000003e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 996 CAN AF ram access register + pub const MASK_249 = mmio(Address + 0x000003e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1000 CAN AF ram access register + pub const MASK_250 = mmio(Address + 0x000003e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1004 CAN AF ram access register + pub const MASK_251 = mmio(Address + 0x000003ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1008 CAN AF ram access register + pub const MASK_252 = mmio(Address + 0x000003f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1012 CAN AF ram access register + pub const MASK_253 = mmio(Address + 0x000003f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1016 CAN AF ram access register + pub const MASK_254 = mmio(Address + 0x000003f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1020 CAN AF ram access register + pub const MASK_255 = mmio(Address + 0x000003fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1024 CAN AF ram access register + pub const MASK_256 = mmio(Address + 0x00000400, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1028 CAN AF ram access register + pub const MASK_257 = mmio(Address + 0x00000404, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1032 CAN AF ram access register + pub const MASK_258 = mmio(Address + 0x00000408, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1036 CAN AF ram access register + pub const MASK_259 = mmio(Address + 0x0000040c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1040 CAN AF ram access register + pub const MASK_260 = mmio(Address + 0x00000410, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1044 CAN AF ram access register + pub const MASK_261 = mmio(Address + 0x00000414, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1048 CAN AF ram access register + pub const MASK_262 = mmio(Address + 0x00000418, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1052 CAN AF ram access register + pub const MASK_263 = mmio(Address + 0x0000041c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1056 CAN AF ram access register + pub const MASK_264 = mmio(Address + 0x00000420, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1060 CAN AF ram access register + pub const MASK_265 = mmio(Address + 0x00000424, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1064 CAN AF ram access register + pub const MASK_266 = mmio(Address + 0x00000428, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1068 CAN AF ram access register + pub const MASK_267 = mmio(Address + 0x0000042c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1072 CAN AF ram access register + pub const MASK_268 = mmio(Address + 0x00000430, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1076 CAN AF ram access register + pub const MASK_269 = mmio(Address + 0x00000434, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1080 CAN AF ram access register + pub const MASK_270 = mmio(Address + 0x00000438, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1084 CAN AF ram access register + pub const MASK_271 = mmio(Address + 0x0000043c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1088 CAN AF ram access register + pub const MASK_272 = mmio(Address + 0x00000440, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1092 CAN AF ram access register + pub const MASK_273 = mmio(Address + 0x00000444, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1096 CAN AF ram access register + pub const MASK_274 = mmio(Address + 0x00000448, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1100 CAN AF ram access register + pub const MASK_275 = mmio(Address + 0x0000044c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1104 CAN AF ram access register + pub const MASK_276 = mmio(Address + 0x00000450, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1108 CAN AF ram access register + pub const MASK_277 = mmio(Address + 0x00000454, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1112 CAN AF ram access register + pub const MASK_278 = mmio(Address + 0x00000458, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1116 CAN AF ram access register + pub const MASK_279 = mmio(Address + 0x0000045c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1120 CAN AF ram access register + pub const MASK_280 = mmio(Address + 0x00000460, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1124 CAN AF ram access register + pub const MASK_281 = mmio(Address + 0x00000464, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1128 CAN AF ram access register + pub const MASK_282 = mmio(Address + 0x00000468, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1132 CAN AF ram access register + pub const MASK_283 = mmio(Address + 0x0000046c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1136 CAN AF ram access register + pub const MASK_284 = mmio(Address + 0x00000470, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1140 CAN AF ram access register + pub const MASK_285 = mmio(Address + 0x00000474, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1144 CAN AF ram access register + pub const MASK_286 = mmio(Address + 0x00000478, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1148 CAN AF ram access register + pub const MASK_287 = mmio(Address + 0x0000047c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1152 CAN AF ram access register + pub const MASK_288 = mmio(Address + 0x00000480, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1156 CAN AF ram access register + pub const MASK_289 = mmio(Address + 0x00000484, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1160 CAN AF ram access register + pub const MASK_290 = mmio(Address + 0x00000488, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1164 CAN AF ram access register + pub const MASK_291 = mmio(Address + 0x0000048c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1168 CAN AF ram access register + pub const MASK_292 = mmio(Address + 0x00000490, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1172 CAN AF ram access register + pub const MASK_293 = mmio(Address + 0x00000494, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1176 CAN AF ram access register + pub const MASK_294 = mmio(Address + 0x00000498, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1180 CAN AF ram access register + pub const MASK_295 = mmio(Address + 0x0000049c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1184 CAN AF ram access register + pub const MASK_296 = mmio(Address + 0x000004a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1188 CAN AF ram access register + pub const MASK_297 = mmio(Address + 0x000004a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1192 CAN AF ram access register + pub const MASK_298 = mmio(Address + 0x000004a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1196 CAN AF ram access register + pub const MASK_299 = mmio(Address + 0x000004ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1200 CAN AF ram access register + pub const MASK_300 = mmio(Address + 0x000004b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1204 CAN AF ram access register + pub const MASK_301 = mmio(Address + 0x000004b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1208 CAN AF ram access register + pub const MASK_302 = mmio(Address + 0x000004b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1212 CAN AF ram access register + pub const MASK_303 = mmio(Address + 0x000004bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1216 CAN AF ram access register + pub const MASK_304 = mmio(Address + 0x000004c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1220 CAN AF ram access register + pub const MASK_305 = mmio(Address + 0x000004c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1224 CAN AF ram access register + pub const MASK_306 = mmio(Address + 0x000004c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1228 CAN AF ram access register + pub const MASK_307 = mmio(Address + 0x000004cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1232 CAN AF ram access register + pub const MASK_308 = mmio(Address + 0x000004d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1236 CAN AF ram access register + pub const MASK_309 = mmio(Address + 0x000004d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1240 CAN AF ram access register + pub const MASK_310 = mmio(Address + 0x000004d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1244 CAN AF ram access register + pub const MASK_311 = mmio(Address + 0x000004dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1248 CAN AF ram access register + pub const MASK_312 = mmio(Address + 0x000004e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1252 CAN AF ram access register + pub const MASK_313 = mmio(Address + 0x000004e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1256 CAN AF ram access register + pub const MASK_314 = mmio(Address + 0x000004e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1260 CAN AF ram access register + pub const MASK_315 = mmio(Address + 0x000004ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1264 CAN AF ram access register + pub const MASK_316 = mmio(Address + 0x000004f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1268 CAN AF ram access register + pub const MASK_317 = mmio(Address + 0x000004f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1272 CAN AF ram access register + pub const MASK_318 = mmio(Address + 0x000004f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1276 CAN AF ram access register + pub const MASK_319 = mmio(Address + 0x000004fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1280 CAN AF ram access register + pub const MASK_320 = mmio(Address + 0x00000500, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1284 CAN AF ram access register + pub const MASK_321 = mmio(Address + 0x00000504, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1288 CAN AF ram access register + pub const MASK_322 = mmio(Address + 0x00000508, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1292 CAN AF ram access register + pub const MASK_323 = mmio(Address + 0x0000050c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1296 CAN AF ram access register + pub const MASK_324 = mmio(Address + 0x00000510, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1300 CAN AF ram access register + pub const MASK_325 = mmio(Address + 0x00000514, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1304 CAN AF ram access register + pub const MASK_326 = mmio(Address + 0x00000518, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1308 CAN AF ram access register + pub const MASK_327 = mmio(Address + 0x0000051c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1312 CAN AF ram access register + pub const MASK_328 = mmio(Address + 0x00000520, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1316 CAN AF ram access register + pub const MASK_329 = mmio(Address + 0x00000524, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1320 CAN AF ram access register + pub const MASK_330 = mmio(Address + 0x00000528, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1324 CAN AF ram access register + pub const MASK_331 = mmio(Address + 0x0000052c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1328 CAN AF ram access register + pub const MASK_332 = mmio(Address + 0x00000530, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1332 CAN AF ram access register + pub const MASK_333 = mmio(Address + 0x00000534, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1336 CAN AF ram access register + pub const MASK_334 = mmio(Address + 0x00000538, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1340 CAN AF ram access register + pub const MASK_335 = mmio(Address + 0x0000053c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1344 CAN AF ram access register + pub const MASK_336 = mmio(Address + 0x00000540, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1348 CAN AF ram access register + pub const MASK_337 = mmio(Address + 0x00000544, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1352 CAN AF ram access register + pub const MASK_338 = mmio(Address + 0x00000548, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1356 CAN AF ram access register + pub const MASK_339 = mmio(Address + 0x0000054c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1360 CAN AF ram access register + pub const MASK_340 = mmio(Address + 0x00000550, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1364 CAN AF ram access register + pub const MASK_341 = mmio(Address + 0x00000554, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1368 CAN AF ram access register + pub const MASK_342 = mmio(Address + 0x00000558, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1372 CAN AF ram access register + pub const MASK_343 = mmio(Address + 0x0000055c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1376 CAN AF ram access register + pub const MASK_344 = mmio(Address + 0x00000560, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1380 CAN AF ram access register + pub const MASK_345 = mmio(Address + 0x00000564, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1384 CAN AF ram access register + pub const MASK_346 = mmio(Address + 0x00000568, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1388 CAN AF ram access register + pub const MASK_347 = mmio(Address + 0x0000056c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1392 CAN AF ram access register + pub const MASK_348 = mmio(Address + 0x00000570, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1396 CAN AF ram access register + pub const MASK_349 = mmio(Address + 0x00000574, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1400 CAN AF ram access register + pub const MASK_350 = mmio(Address + 0x00000578, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1404 CAN AF ram access register + pub const MASK_351 = mmio(Address + 0x0000057c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1408 CAN AF ram access register + pub const MASK_352 = mmio(Address + 0x00000580, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1412 CAN AF ram access register + pub const MASK_353 = mmio(Address + 0x00000584, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1416 CAN AF ram access register + pub const MASK_354 = mmio(Address + 0x00000588, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1420 CAN AF ram access register + pub const MASK_355 = mmio(Address + 0x0000058c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1424 CAN AF ram access register + pub const MASK_356 = mmio(Address + 0x00000590, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1428 CAN AF ram access register + pub const MASK_357 = mmio(Address + 0x00000594, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1432 CAN AF ram access register + pub const MASK_358 = mmio(Address + 0x00000598, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1436 CAN AF ram access register + pub const MASK_359 = mmio(Address + 0x0000059c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1440 CAN AF ram access register + pub const MASK_360 = mmio(Address + 0x000005a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1444 CAN AF ram access register + pub const MASK_361 = mmio(Address + 0x000005a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1448 CAN AF ram access register + pub const MASK_362 = mmio(Address + 0x000005a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1452 CAN AF ram access register + pub const MASK_363 = mmio(Address + 0x000005ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1456 CAN AF ram access register + pub const MASK_364 = mmio(Address + 0x000005b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1460 CAN AF ram access register + pub const MASK_365 = mmio(Address + 0x000005b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1464 CAN AF ram access register + pub const MASK_366 = mmio(Address + 0x000005b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1468 CAN AF ram access register + pub const MASK_367 = mmio(Address + 0x000005bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1472 CAN AF ram access register + pub const MASK_368 = mmio(Address + 0x000005c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1476 CAN AF ram access register + pub const MASK_369 = mmio(Address + 0x000005c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1480 CAN AF ram access register + pub const MASK_370 = mmio(Address + 0x000005c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1484 CAN AF ram access register + pub const MASK_371 = mmio(Address + 0x000005cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1488 CAN AF ram access register + pub const MASK_372 = mmio(Address + 0x000005d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1492 CAN AF ram access register + pub const MASK_373 = mmio(Address + 0x000005d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1496 CAN AF ram access register + pub const MASK_374 = mmio(Address + 0x000005d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1500 CAN AF ram access register + pub const MASK_375 = mmio(Address + 0x000005dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1504 CAN AF ram access register + pub const MASK_376 = mmio(Address + 0x000005e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1508 CAN AF ram access register + pub const MASK_377 = mmio(Address + 0x000005e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1512 CAN AF ram access register + pub const MASK_378 = mmio(Address + 0x000005e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1516 CAN AF ram access register + pub const MASK_379 = mmio(Address + 0x000005ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1520 CAN AF ram access register + pub const MASK_380 = mmio(Address + 0x000005f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1524 CAN AF ram access register + pub const MASK_381 = mmio(Address + 0x000005f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1528 CAN AF ram access register + pub const MASK_382 = mmio(Address + 0x000005f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1532 CAN AF ram access register + pub const MASK_383 = mmio(Address + 0x000005fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1536 CAN AF ram access register + pub const MASK_384 = mmio(Address + 0x00000600, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1540 CAN AF ram access register + pub const MASK_385 = mmio(Address + 0x00000604, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1544 CAN AF ram access register + pub const MASK_386 = mmio(Address + 0x00000608, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1548 CAN AF ram access register + pub const MASK_387 = mmio(Address + 0x0000060c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1552 CAN AF ram access register + pub const MASK_388 = mmio(Address + 0x00000610, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1556 CAN AF ram access register + pub const MASK_389 = mmio(Address + 0x00000614, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1560 CAN AF ram access register + pub const MASK_390 = mmio(Address + 0x00000618, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1564 CAN AF ram access register + pub const MASK_391 = mmio(Address + 0x0000061c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1568 CAN AF ram access register + pub const MASK_392 = mmio(Address + 0x00000620, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1572 CAN AF ram access register + pub const MASK_393 = mmio(Address + 0x00000624, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1576 CAN AF ram access register + pub const MASK_394 = mmio(Address + 0x00000628, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1580 CAN AF ram access register + pub const MASK_395 = mmio(Address + 0x0000062c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1584 CAN AF ram access register + pub const MASK_396 = mmio(Address + 0x00000630, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1588 CAN AF ram access register + pub const MASK_397 = mmio(Address + 0x00000634, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1592 CAN AF ram access register + pub const MASK_398 = mmio(Address + 0x00000638, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1596 CAN AF ram access register + pub const MASK_399 = mmio(Address + 0x0000063c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1600 CAN AF ram access register + pub const MASK_400 = mmio(Address + 0x00000640, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1604 CAN AF ram access register + pub const MASK_401 = mmio(Address + 0x00000644, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1608 CAN AF ram access register + pub const MASK_402 = mmio(Address + 0x00000648, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1612 CAN AF ram access register + pub const MASK_403 = mmio(Address + 0x0000064c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1616 CAN AF ram access register + pub const MASK_404 = mmio(Address + 0x00000650, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1620 CAN AF ram access register + pub const MASK_405 = mmio(Address + 0x00000654, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1624 CAN AF ram access register + pub const MASK_406 = mmio(Address + 0x00000658, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1628 CAN AF ram access register + pub const MASK_407 = mmio(Address + 0x0000065c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1632 CAN AF ram access register + pub const MASK_408 = mmio(Address + 0x00000660, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1636 CAN AF ram access register + pub const MASK_409 = mmio(Address + 0x00000664, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1640 CAN AF ram access register + pub const MASK_410 = mmio(Address + 0x00000668, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1644 CAN AF ram access register + pub const MASK_411 = mmio(Address + 0x0000066c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1648 CAN AF ram access register + pub const MASK_412 = mmio(Address + 0x00000670, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1652 CAN AF ram access register + pub const MASK_413 = mmio(Address + 0x00000674, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1656 CAN AF ram access register + pub const MASK_414 = mmio(Address + 0x00000678, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1660 CAN AF ram access register + pub const MASK_415 = mmio(Address + 0x0000067c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1664 CAN AF ram access register + pub const MASK_416 = mmio(Address + 0x00000680, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1668 CAN AF ram access register + pub const MASK_417 = mmio(Address + 0x00000684, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1672 CAN AF ram access register + pub const MASK_418 = mmio(Address + 0x00000688, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1676 CAN AF ram access register + pub const MASK_419 = mmio(Address + 0x0000068c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1680 CAN AF ram access register + pub const MASK_420 = mmio(Address + 0x00000690, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1684 CAN AF ram access register + pub const MASK_421 = mmio(Address + 0x00000694, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1688 CAN AF ram access register + pub const MASK_422 = mmio(Address + 0x00000698, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1692 CAN AF ram access register + pub const MASK_423 = mmio(Address + 0x0000069c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1696 CAN AF ram access register + pub const MASK_424 = mmio(Address + 0x000006a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1700 CAN AF ram access register + pub const MASK_425 = mmio(Address + 0x000006a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1704 CAN AF ram access register + pub const MASK_426 = mmio(Address + 0x000006a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1708 CAN AF ram access register + pub const MASK_427 = mmio(Address + 0x000006ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1712 CAN AF ram access register + pub const MASK_428 = mmio(Address + 0x000006b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1716 CAN AF ram access register + pub const MASK_429 = mmio(Address + 0x000006b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1720 CAN AF ram access register + pub const MASK_430 = mmio(Address + 0x000006b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1724 CAN AF ram access register + pub const MASK_431 = mmio(Address + 0x000006bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1728 CAN AF ram access register + pub const MASK_432 = mmio(Address + 0x000006c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1732 CAN AF ram access register + pub const MASK_433 = mmio(Address + 0x000006c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1736 CAN AF ram access register + pub const MASK_434 = mmio(Address + 0x000006c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1740 CAN AF ram access register + pub const MASK_435 = mmio(Address + 0x000006cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1744 CAN AF ram access register + pub const MASK_436 = mmio(Address + 0x000006d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1748 CAN AF ram access register + pub const MASK_437 = mmio(Address + 0x000006d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1752 CAN AF ram access register + pub const MASK_438 = mmio(Address + 0x000006d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1756 CAN AF ram access register + pub const MASK_439 = mmio(Address + 0x000006dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1760 CAN AF ram access register + pub const MASK_440 = mmio(Address + 0x000006e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1764 CAN AF ram access register + pub const MASK_441 = mmio(Address + 0x000006e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1768 CAN AF ram access register + pub const MASK_442 = mmio(Address + 0x000006e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1772 CAN AF ram access register + pub const MASK_443 = mmio(Address + 0x000006ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1776 CAN AF ram access register + pub const MASK_444 = mmio(Address + 0x000006f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1780 CAN AF ram access register + pub const MASK_445 = mmio(Address + 0x000006f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1784 CAN AF ram access register + pub const MASK_446 = mmio(Address + 0x000006f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1788 CAN AF ram access register + pub const MASK_447 = mmio(Address + 0x000006fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1792 CAN AF ram access register + pub const MASK_448 = mmio(Address + 0x00000700, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1796 CAN AF ram access register + pub const MASK_449 = mmio(Address + 0x00000704, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1800 CAN AF ram access register + pub const MASK_450 = mmio(Address + 0x00000708, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1804 CAN AF ram access register + pub const MASK_451 = mmio(Address + 0x0000070c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1808 CAN AF ram access register + pub const MASK_452 = mmio(Address + 0x00000710, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1812 CAN AF ram access register + pub const MASK_453 = mmio(Address + 0x00000714, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1816 CAN AF ram access register + pub const MASK_454 = mmio(Address + 0x00000718, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1820 CAN AF ram access register + pub const MASK_455 = mmio(Address + 0x0000071c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1824 CAN AF ram access register + pub const MASK_456 = mmio(Address + 0x00000720, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1828 CAN AF ram access register + pub const MASK_457 = mmio(Address + 0x00000724, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1832 CAN AF ram access register + pub const MASK_458 = mmio(Address + 0x00000728, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1836 CAN AF ram access register + pub const MASK_459 = mmio(Address + 0x0000072c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1840 CAN AF ram access register + pub const MASK_460 = mmio(Address + 0x00000730, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1844 CAN AF ram access register + pub const MASK_461 = mmio(Address + 0x00000734, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1848 CAN AF ram access register + pub const MASK_462 = mmio(Address + 0x00000738, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1852 CAN AF ram access register + pub const MASK_463 = mmio(Address + 0x0000073c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1856 CAN AF ram access register + pub const MASK_464 = mmio(Address + 0x00000740, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1860 CAN AF ram access register + pub const MASK_465 = mmio(Address + 0x00000744, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1864 CAN AF ram access register + pub const MASK_466 = mmio(Address + 0x00000748, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1868 CAN AF ram access register + pub const MASK_467 = mmio(Address + 0x0000074c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1872 CAN AF ram access register + pub const MASK_468 = mmio(Address + 0x00000750, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1876 CAN AF ram access register + pub const MASK_469 = mmio(Address + 0x00000754, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1880 CAN AF ram access register + pub const MASK_470 = mmio(Address + 0x00000758, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1884 CAN AF ram access register + pub const MASK_471 = mmio(Address + 0x0000075c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1888 CAN AF ram access register + pub const MASK_472 = mmio(Address + 0x00000760, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1892 CAN AF ram access register + pub const MASK_473 = mmio(Address + 0x00000764, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1896 CAN AF ram access register + pub const MASK_474 = mmio(Address + 0x00000768, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1900 CAN AF ram access register + pub const MASK_475 = mmio(Address + 0x0000076c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1904 CAN AF ram access register + pub const MASK_476 = mmio(Address + 0x00000770, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1908 CAN AF ram access register + pub const MASK_477 = mmio(Address + 0x00000774, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1912 CAN AF ram access register + pub const MASK_478 = mmio(Address + 0x00000778, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1916 CAN AF ram access register + pub const MASK_479 = mmio(Address + 0x0000077c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1920 CAN AF ram access register + pub const MASK_480 = mmio(Address + 0x00000780, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1924 CAN AF ram access register + pub const MASK_481 = mmio(Address + 0x00000784, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1928 CAN AF ram access register + pub const MASK_482 = mmio(Address + 0x00000788, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1932 CAN AF ram access register + pub const MASK_483 = mmio(Address + 0x0000078c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1936 CAN AF ram access register + pub const MASK_484 = mmio(Address + 0x00000790, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1940 CAN AF ram access register + pub const MASK_485 = mmio(Address + 0x00000794, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1944 CAN AF ram access register + pub const MASK_486 = mmio(Address + 0x00000798, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1948 CAN AF ram access register + pub const MASK_487 = mmio(Address + 0x0000079c, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1952 CAN AF ram access register + pub const MASK_488 = mmio(Address + 0x000007a0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1956 CAN AF ram access register + pub const MASK_489 = mmio(Address + 0x000007a4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1960 CAN AF ram access register + pub const MASK_490 = mmio(Address + 0x000007a8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1964 CAN AF ram access register + pub const MASK_491 = mmio(Address + 0x000007ac, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1968 CAN AF ram access register + pub const MASK_492 = mmio(Address + 0x000007b0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1972 CAN AF ram access register + pub const MASK_493 = mmio(Address + 0x000007b4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1976 CAN AF ram access register + pub const MASK_494 = mmio(Address + 0x000007b8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1980 CAN AF ram access register + pub const MASK_495 = mmio(Address + 0x000007bc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1984 CAN AF ram access register + pub const MASK_496 = mmio(Address + 0x000007c0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1988 CAN AF ram access register + pub const MASK_497 = mmio(Address + 0x000007c4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1992 CAN AF ram access register + pub const MASK_498 = mmio(Address + 0x000007c8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 1996 CAN AF ram access register + pub const MASK_499 = mmio(Address + 0x000007cc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2000 CAN AF ram access register + pub const MASK_500 = mmio(Address + 0x000007d0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2004 CAN AF ram access register + pub const MASK_501 = mmio(Address + 0x000007d4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2008 CAN AF ram access register + pub const MASK_502 = mmio(Address + 0x000007d8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2012 CAN AF ram access register + pub const MASK_503 = mmio(Address + 0x000007dc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2016 CAN AF ram access register + pub const MASK_504 = mmio(Address + 0x000007e0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2020 CAN AF ram access register + pub const MASK_505 = mmio(Address + 0x000007e4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2024 CAN AF ram access register + pub const MASK_506 = mmio(Address + 0x000007e8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2028 CAN AF ram access register + pub const MASK_507 = mmio(Address + 0x000007ec, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2032 CAN AF ram access register + pub const MASK_508 = mmio(Address + 0x000007f0, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2036 CAN AF ram access register + pub const MASK_509 = mmio(Address + 0x000007f4, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2040 CAN AF ram access register + pub const MASK_510 = mmio(Address + 0x000007f8, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); + // byte offset: 2044 CAN AF ram access register + pub const MASK_511 = mmio(Address + 0x000007fc, 32, packed struct { + MASK: u32, // bit offset: 0 desc: CAN AF RAM mask + }); +}; +pub const CANAF = extern struct { + pub const Address: u32 = 0x4003c000; + // byte offset: 0 Acceptance Filter Register + pub const AFMR = mmio(Address + 0x00000000, 32, packed struct { + ACCOFF: bool, // bit offset: 0 desc: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. + ACCBP: bool, // bit offset: 1 desc: All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. + EFCAN: bool, // bit offset: 2 desc: FullCAN mode + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Standard Frame Individual Start Address Register + pub const SFF_SA = mmio(Address + 0x00000004, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + SFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Standard Frame Group Start Address Register + pub const SFF_GRP_SA = mmio(Address + 0x00000008, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + SFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Extended Frame Start Address Register + pub const EFF_SA = mmio(Address + 0x0000000c, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + EFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Extended Frame Group Start Address Register + pub const EFF_GRP_SA = mmio(Address + 0x00000010, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + EFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 End of AF Tables register + pub const ENDOFTABLE = mmio(Address + 0x00000014, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + ENDOFTABLE: u10, // bit offset: 2 desc: The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 LUT Error Address register + pub const LUTERRAD = mmio(Address + 0x00000018, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LUTERRAD: u9, // bit offset: 2 desc: It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 LUT Error Register + pub const LUTERR = mmio(Address + 0x0000001c, 32, packed struct { + LUTERR: bool, // bit offset: 0 desc: This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 FullCAN interrupt enable register + pub const FCANIE = mmio(Address + 0x00000020, 32, packed struct { + FCANIE: bool, // bit offset: 0 desc: Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 FullCAN interrupt and capture register0 + pub const FCANIC0 = mmio(Address + 0x00000024, 32, packed struct { + INTPND: u32, // bit offset: 0 desc: FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. + }); + // byte offset: 40 FullCAN interrupt and capture register1 + pub const FCANIC1 = mmio(Address + 0x00000028, 32, packed struct { + IntPnd32: u32, // bit offset: 0 desc: FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. + }); +}; +pub const CCAN = extern struct { + pub const Address: u32 = 0x40040000; + // byte offset: 0 CAN Central Transmit Status Register + pub const TXSR = mmio(Address + 0x00000000, 32, packed struct { + TS1: bool, // bit offset: 0 desc: When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). + TS2: bool, // bit offset: 1 desc: When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TBS1: bool, // bit offset: 8 desc: When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). + TBS2: bool, // bit offset: 9 desc: When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TCS1: bool, // bit offset: 16 desc: When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). + TCS2: bool, // bit offset: 17 desc: When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 CAN Central Receive Status Register + pub const RXSR = mmio(Address + 0x00000004, 32, packed struct { + RS1: bool, // bit offset: 0 desc: When 1, CAN1 is receiving a message (same as RS in CAN1GSR). + RS2: bool, // bit offset: 1 desc: When 1, CAN2 is receiving a message (same as RS in CAN2GSR). + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RB1: bool, // bit offset: 8 desc: When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). + RB2: bool, // bit offset: 9 desc: When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + DOS1: bool, // bit offset: 16 desc: When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). + DOS2: bool, // bit offset: 17 desc: When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 CAN Central Miscellaneous Register + pub const MSR = mmio(Address + 0x00000008, 32, packed struct { + E1: bool, // bit offset: 0 desc: When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) + E2: bool, // bit offset: 1 desc: When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + BS1: bool, // bit offset: 8 desc: When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). + BS2: bool, // bit offset: 9 desc: When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CAN1 = extern struct { + pub const Address: u32 = 0x40044000; + // byte offset: 0 Controls the operating mode of the CAN Controller. + pub const MOD = mmio(Address + 0x00000000, 32, packed struct { + RM: bool, // bit offset: 0 desc: Reset Mode. + LOM: bool, // bit offset: 1 desc: Listen Only Mode. + STM: bool, // bit offset: 2 desc: Self Test Mode. + TPM: bool, // bit offset: 3 desc: Transmit Priority Mode. + SM: bool, // bit offset: 4 desc: Sleep Mode. + RPM: bool, // bit offset: 5 desc: Receive Polarity Mode. + reserved1: u1 = 0, + TM: bool, // bit offset: 7 desc: Test Mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Command bits that affect the state of the CAN Controller + pub const CMR = mmio(Address + 0x00000004, 32, packed struct { + TR: bool, // bit offset: 0 desc: Transmission Request. + AT: bool, // bit offset: 1 desc: Abort Transmission. + RRB: bool, // bit offset: 2 desc: Release Receive Buffer. + CDO: bool, // bit offset: 3 desc: Clear Data Overrun. + SRR: bool, // bit offset: 4 desc: Self Reception Request. + STB1: bool, // bit offset: 5 desc: Select Tx Buffer 1. + STB2: bool, // bit offset: 6 desc: Select Tx Buffer 2. + STB3: bool, // bit offset: 7 desc: Select Tx Buffer 3. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. + pub const GSR = mmio(Address + 0x00000008, 32, packed struct { + RBS: bool, // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. + DOS: bool, // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. + TBS: bool, // bit offset: 2 desc: Transmit Buffer Status. + TCS: bool, // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. + RS: bool, // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + TS: bool, // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + ES: bool, // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). + BS: bool, // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). + TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). + }); + // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { + RI: bool, // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. + TI1: bool, // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. + EI: bool, // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. + DOI: bool, // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. + WUI: bool, // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. + EPI: bool, // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. + ALI: bool, // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. + BEI: bool, // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. + IDI: bool, // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. + TI2: bool, // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. + TI3: bool, // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. + ERRDIR: bool, // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. + ERRC1_0: u2, // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. + }); + // byte offset: 16 Interrupt Enable + pub const IER = mmio(Address + 0x00000010, 32, packed struct { + RIE: bool, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. + TIE1: bool, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + EIE: bool, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. + DOIE: bool, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. + WUIE: bool, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. + EPIE: bool, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. + ALIE: bool, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. + BEIE: bool, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. + IDIE: bool, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. + TIE2: bool, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + TIE3: bool, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = mmio(Address + 0x00000014, 32, packed struct { + BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. + TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. + TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. + SAM: bool, // bit offset: 23 desc: Sampling + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = mmio(Address + 0x00000018, 32, packed struct { + EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Status Register + pub const SR = mmio(Address + 0x0000001c, 32, packed struct { + RBS_1: bool, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_1: bool, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS1_1: bool, // bit offset: 2 desc: Transmit Buffer Status 1. + TCS1_1: bool, // bit offset: 3 desc: Transmission Complete Status. + RS_1: bool, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS1_1: bool, // bit offset: 5 desc: Transmit Status 1. + ES_1: bool, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_1: bool, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_2: bool, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_2: bool, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS2_2: bool, // bit offset: 10 desc: Transmit Buffer Status 2. + TCS2_2: bool, // bit offset: 11 desc: Transmission Complete Status. + RS_2: bool, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS2_2: bool, // bit offset: 13 desc: Transmit Status 2. + ES_2: bool, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_2: bool, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_3: bool, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_3: bool, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS3_3: bool, // bit offset: 18 desc: Transmit Buffer Status 3. + TCS3_3: bool, // bit offset: 19 desc: Transmission Complete Status. + RS_3: bool, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS3_3: bool, // bit offset: 21 desc: Transmit Status 3. + ES_3: bool, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_3: bool, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = mmio(Address + 0x00000020, 32, packed struct { + IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. + BP: bool, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. + FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. + }); + // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = mmio(Address + 0x00000024, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = mmio(Address + 0x00000028, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. + DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. + DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. + DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. + }); + // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. + DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. + DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. + DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. + }); + // byte offset: 48 Transmit frame info (Tx Buffer ) + pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 52 Transmit Identifier (Tx Buffer) + pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 64 Transmit frame info (Tx Buffer ) + pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 68 Transmit Identifier (Tx Buffer) + pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 80 Transmit frame info (Tx Buffer ) + pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 84 Transmit Identifier (Tx Buffer) + pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); +}; +pub const CAN2 = extern struct { + pub const Address: u32 = 0x40048000; + // byte offset: 0 Controls the operating mode of the CAN Controller. + pub const MOD = mmio(Address + 0x00000000, 32, packed struct { + RM: bool, // bit offset: 0 desc: Reset Mode. + LOM: bool, // bit offset: 1 desc: Listen Only Mode. + STM: bool, // bit offset: 2 desc: Self Test Mode. + TPM: bool, // bit offset: 3 desc: Transmit Priority Mode. + SM: bool, // bit offset: 4 desc: Sleep Mode. + RPM: bool, // bit offset: 5 desc: Receive Polarity Mode. + reserved1: u1 = 0, + TM: bool, // bit offset: 7 desc: Test Mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Command bits that affect the state of the CAN Controller + pub const CMR = mmio(Address + 0x00000004, 32, packed struct { + TR: bool, // bit offset: 0 desc: Transmission Request. + AT: bool, // bit offset: 1 desc: Abort Transmission. + RRB: bool, // bit offset: 2 desc: Release Receive Buffer. + CDO: bool, // bit offset: 3 desc: Clear Data Overrun. + SRR: bool, // bit offset: 4 desc: Self Reception Request. + STB1: bool, // bit offset: 5 desc: Select Tx Buffer 1. + STB2: bool, // bit offset: 6 desc: Select Tx Buffer 2. + STB3: bool, // bit offset: 7 desc: Select Tx Buffer 3. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. + pub const GSR = mmio(Address + 0x00000008, 32, packed struct { + RBS: bool, // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. + DOS: bool, // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. + TBS: bool, // bit offset: 2 desc: Transmit Buffer Status. + TCS: bool, // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. + RS: bool, // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + TS: bool, // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + ES: bool, // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). + BS: bool, // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). + TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). + }); + // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { + RI: bool, // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. + TI1: bool, // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. + EI: bool, // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. + DOI: bool, // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. + WUI: bool, // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. + EPI: bool, // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. + ALI: bool, // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. + BEI: bool, // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. + IDI: bool, // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. + TI2: bool, // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. + TI3: bool, // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. + ERRDIR: bool, // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. + ERRC1_0: u2, // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. + }); + // byte offset: 16 Interrupt Enable + pub const IER = mmio(Address + 0x00000010, 32, packed struct { + RIE: bool, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. + TIE1: bool, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + EIE: bool, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. + DOIE: bool, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. + WUIE: bool, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. + EPIE: bool, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. + ALIE: bool, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. + BEIE: bool, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. + IDIE: bool, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. + TIE2: bool, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + TIE3: bool, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = mmio(Address + 0x00000014, 32, packed struct { + BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. + TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. + TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. + SAM: bool, // bit offset: 23 desc: Sampling + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = mmio(Address + 0x00000018, 32, packed struct { + EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Status Register + pub const SR = mmio(Address + 0x0000001c, 32, packed struct { + RBS_1: bool, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_1: bool, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS1_1: bool, // bit offset: 2 desc: Transmit Buffer Status 1. + TCS1_1: bool, // bit offset: 3 desc: Transmission Complete Status. + RS_1: bool, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS1_1: bool, // bit offset: 5 desc: Transmit Status 1. + ES_1: bool, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_1: bool, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_2: bool, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_2: bool, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS2_2: bool, // bit offset: 10 desc: Transmit Buffer Status 2. + TCS2_2: bool, // bit offset: 11 desc: Transmission Complete Status. + RS_2: bool, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS2_2: bool, // bit offset: 13 desc: Transmit Status 2. + ES_2: bool, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_2: bool, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_3: bool, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_3: bool, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS3_3: bool, // bit offset: 18 desc: Transmit Buffer Status 3. + TCS3_3: bool, // bit offset: 19 desc: Transmission Complete Status. + RS_3: bool, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS3_3: bool, // bit offset: 21 desc: Transmit Status 3. + ES_3: bool, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_3: bool, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = mmio(Address + 0x00000020, 32, packed struct { + IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. + BP: bool, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. + FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. + }); + // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = mmio(Address + 0x00000024, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = mmio(Address + 0x00000028, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. + DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. + DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. + DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. + }); + // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. + DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. + DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. + DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. + }); + // byte offset: 48 Transmit frame info (Tx Buffer ) + pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 48 Transmit frame info (Tx Buffer ) + pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 52 Transmit Identifier (Tx Buffer) + pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 52 Transmit Identifier (Tx Buffer) + pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 64 Transmit frame info (Tx Buffer ) + pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 64 Transmit frame info (Tx Buffer ) + pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 68 Transmit Identifier (Tx Buffer) + pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 68 Transmit Identifier (Tx Buffer) + pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 80 Transmit frame info (Tx Buffer ) + pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 80 Transmit frame info (Tx Buffer ) + pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + }); + // byte offset: 84 Transmit Identifier (Tx Buffer) + pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 84 Transmit Identifier (Tx Buffer) + pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { + ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + }); + // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); +}; +pub const I2C1 = extern struct { + pub const Address: u32 = 0x4005c000; + // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AA: bool, // bit offset: 2 desc: Assert acknowledge flag. + SI: bool, // bit offset: 3 desc: I2C interrupt flag. + STO: bool, // bit offset: 4 desc: STOP flag. + STA: bool, // bit offset: 5 desc: START flag. + I2EN: bool, // bit offset: 6 desc: I2C interface enable. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. + pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. + pub const DAT = mmio(Address + 0x00000008, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. + pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { + SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. + pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { + SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. + reserved2: u1 = 0, + STAC: bool, // bit offset: 5 desc: START flag Clear bit. + I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Monitor mode control register. + pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { + MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. + ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. + MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); +}; +pub const SSP0 = extern struct { + pub const Address: u32 = 0x40088000; + // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { + DSS: u4, // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + FRF: u2, // bit offset: 4 desc: Frame Format. + CPOL: bool, // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. + CPHA: bool, // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control Register 1. Selects master/slave and other modes. + pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { + LBM: bool, // bit offset: 0 desc: Loop Back Mode. + SSE: bool, // bit offset: 1 desc: SSP Enable. + MS: bool, // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. + SOD: bool, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = mmio(Address + 0x00000008, 32, packed struct { + DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Status Register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + TFE: bool, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TNF: bool, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + RNE: bool, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RFF: bool, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + BSY: bool, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Clock Prescale Register + pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { + CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Interrupt Mask Set and Clear Register + pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { + RORIM: bool, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTIM: bool, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXIM: bool, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + TXIM: bool, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Raw Interrupt Status Register + pub const RIS = mmio(Address + 0x00000018, 32, packed struct { + RORRIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTRIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXRIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. + TXRIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Masked Interrupt Status Register + pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { + RORMIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + RTMIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXMIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + TXMIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 SSPICR Interrupt Clear Register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + RORIC: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + RTIC: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 SSP0 DMA control register + pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { + RXDMAE: bool, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. + TXDMAE: bool, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DAC = extern struct { + pub const Address: u32 = 0x4008c000; + // byte offset: 0 D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + VALUE: u10, // bit offset: 6 desc: After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN. + BIAS: bool, // bit offset: 16 desc: Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DAC Control register. This register controls DMA and timer operation. + pub const CTRL = mmio(Address + 0x00000004, 32, packed struct { + INT_DMA_REQ: bool, // bit offset: 0 desc: DMA interrupt request + DBLBUF_ENA: bool, // bit offset: 1 desc: Double buffering + CNT_ENA: bool, // bit offset: 2 desc: Time-out counter operation + DMA_ENA: bool, // bit offset: 3 desc: DMA access + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. + pub const CNTVAL = mmio(Address + 0x00000008, 32, packed struct { + VALUE: u16, // bit offset: 0 desc: 16-bit reload value for the DAC interrupt/DMA timer. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIMER2 = extern struct { + pub const Address: u32 = 0x40090000; + // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + pub const IR = mmio(Address + 0x00000000, 32, packed struct { + MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + pub const TCR = mmio(Address + 0x00000004, 32, packed struct { + CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + pub const TC = mmio(Address + 0x00000008, 32, packed struct { + TC: u32, // bit offset: 0 desc: Timer counter value. + }); + // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. + pub const PR = mmio(Address + 0x0000000c, 32, packed struct { + PM: u32, // bit offset: 0 desc: Prescale counter maximum value. + }); + // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + pub const PC = mmio(Address + 0x00000010, 32, packed struct { + PC: u32, // bit offset: 0 desc: Prescale counter value. + }); + // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + pub const MCR = mmio(Address + 0x00000014, 32, packed struct { + MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 + MR0R: bool, // bit offset: 1 desc: Reset on MR0 + MR0S: bool, // bit offset: 2 desc: Stop on MR0 + MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 + MR1R: bool, // bit offset: 4 desc: Reset on MR1 + MR1S: bool, // bit offset: 5 desc: Stop on MR1 + MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 + MR2R: bool, // bit offset: 7 desc: Reset on MR2 + MR2S: bool, // bit offset: 8 desc: Stop on MR2. + MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 + MR3R: bool, // bit offset: 10 desc: Reset on MR3 + MR3S: bool, // bit offset: 11 desc: Stop on MR3 + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + pub const CCR = mmio(Address + 0x00000028, 32, packed struct { + CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge + CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge + CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event + CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge + CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge + CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 60 External Match Register. The EMR controls the external match pins. + pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { + EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { + CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIMER3 = extern struct { + pub const Address: u32 = 0x40094000; + // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + pub const IR = mmio(Address + 0x00000000, 32, packed struct { + MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + pub const TCR = mmio(Address + 0x00000004, 32, packed struct { + CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + pub const TC = mmio(Address + 0x00000008, 32, packed struct { + TC: u32, // bit offset: 0 desc: Timer counter value. + }); + // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. + pub const PR = mmio(Address + 0x0000000c, 32, packed struct { + PM: u32, // bit offset: 0 desc: Prescale counter maximum value. + }); + // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + pub const PC = mmio(Address + 0x00000010, 32, packed struct { + PC: u32, // bit offset: 0 desc: Prescale counter value. + }); + // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + pub const MCR = mmio(Address + 0x00000014, 32, packed struct { + MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 + MR0R: bool, // bit offset: 1 desc: Reset on MR0 + MR0S: bool, // bit offset: 2 desc: Stop on MR0 + MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 + MR1R: bool, // bit offset: 4 desc: Reset on MR1 + MR1S: bool, // bit offset: 5 desc: Stop on MR1 + MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 + MR2R: bool, // bit offset: 7 desc: Reset on MR2 + MR2S: bool, // bit offset: 8 desc: Stop on MR2. + MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 + MR3R: bool, // bit offset: 10 desc: Reset on MR3 + MR3S: bool, // bit offset: 11 desc: Stop on MR3 + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { + MATCH: u32, // bit offset: 0 desc: Timer counter match value. + }); + // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + pub const CCR = mmio(Address + 0x00000028, 32, packed struct { + CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge + CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge + CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event + CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge + CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge + CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. + pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Timer counter capture value. + }); + // byte offset: 60 External Match Register. The EMR controls the external match pins. + pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { + EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { + CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART2 = extern struct { + pub const Address: u32 = 0x40098000; + // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). + pub const RBR = mmio(Address + 0x00000000, 32, packed struct { + RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). + pub const THR = mmio(Address + 0x00000000, 32, packed struct { + THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLL = mmio(Address + 0x00000000, 32, packed struct { + DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLM = mmio(Address + 0x00000004, 32, packed struct { + DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. + ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = mmio(Address + 0x00000008, 32, packed struct { + INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + reserved2: u1 = 0, + reserved1: u1 = 0, + FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. + ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = mmio(Address + 0x00000008, 32, packed struct { + FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. + RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. + TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. + DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + reserved2: u1 = 0, + reserved1: u1 = 0, + RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. + pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { + WLS: u2, // bit offset: 0 desc: Word Length Select. + SBS: bool, // bit offset: 2 desc: Stop Bit Select + PE: bool, // bit offset: 3 desc: Parity Enable. + PS: u2, // bit offset: 4 desc: Parity Select + BC: bool, // bit offset: 6 desc: Break Control + DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. + pub const LSR = mmio(Address + 0x00000014, 32, packed struct { + RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { + PAD: u8, // bit offset: 0 desc: A readable, writable byte. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = mmio(Address + 0x00000020, 32, packed struct { + START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. + AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = mmio(Address + 0x00000028, 32, packed struct { + DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. + MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. + pub const TER = mmio(Address + 0x00000030, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. + pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { + NMMEN: bool, // bit offset: 0 desc: NMM enable. + RXDIS: bool, // bit offset: 1 desc: Receiver enable. + AADEN: bool, // bit offset: 2 desc: AAD enable. + reserved1: u1 = 0, + DCTRL: bool, // bit offset: 4 desc: Direction control enable. + OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. + pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { + ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 RS-485/EIA-485 direction control delay. + pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { + DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART3 = extern struct { + pub const Address: u32 = 0x4009c000; + // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). + pub const RBR = mmio(Address + 0x00000000, 32, packed struct { + RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). + pub const THR = mmio(Address + 0x00000000, 32, packed struct { + THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLL = mmio(Address + 0x00000000, 32, packed struct { + DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). + pub const DLM = mmio(Address + 0x00000004, 32, packed struct { + DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. + ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = mmio(Address + 0x00000008, 32, packed struct { + INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + reserved2: u1 = 0, + reserved1: u1 = 0, + FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. + ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = mmio(Address + 0x00000008, 32, packed struct { + FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. + RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. + TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. + DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + reserved2: u1 = 0, + reserved1: u1 = 0, + RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. + pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { + WLS: u2, // bit offset: 0 desc: Word Length Select. + SBS: bool, // bit offset: 2 desc: Stop Bit Select + PE: bool, // bit offset: 3 desc: Parity Enable. + PS: u2, // bit offset: 4 desc: Parity Select + BC: bool, // bit offset: 6 desc: Break Control + DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. + pub const LSR = mmio(Address + 0x00000014, 32, packed struct { + RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { + PAD: u8, // bit offset: 0 desc: A readable, writable byte. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = mmio(Address + 0x00000020, 32, packed struct { + START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. + AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = mmio(Address + 0x00000028, 32, packed struct { + DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. + MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. + pub const TER = mmio(Address + 0x00000030, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. + pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { + NMMEN: bool, // bit offset: 0 desc: NMM enable. + RXDIS: bool, // bit offset: 1 desc: Receiver enable. + AADEN: bool, // bit offset: 2 desc: AAD enable. + reserved1: u1 = 0, + DCTRL: bool, // bit offset: 4 desc: Direction control enable. + OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. + pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { + ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 RS-485/EIA-485 direction control delay. + pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { + DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C2 = extern struct { + pub const Address: u32 = 0x400a0000; + // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AA: bool, // bit offset: 2 desc: Assert acknowledge flag. + SI: bool, // bit offset: 3 desc: I2C interrupt flag. + STO: bool, // bit offset: 4 desc: STOP flag. + STA: bool, // bit offset: 5 desc: START flag. + I2EN: bool, // bit offset: 6 desc: I2C interface enable. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. + pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. + pub const DAT = mmio(Address + 0x00000008, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. + pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { + SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. + pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { + SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. + reserved2: u1 = 0, + STAC: bool, // bit offset: 5 desc: START flag Clear bit. + I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Monitor mode control register. + pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { + MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. + ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. + MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: bool, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + }); + // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + }); +}; +pub const I2S = extern struct { + pub const Address: u32 = 0x400a8000; + // byte offset: 0 I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. + pub const DAO = mmio(Address + 0x00000000, 32, packed struct { + WORDWIDTH: u2, // bit offset: 0 desc: Selects the number of bytes in data as follows: + MONO: bool, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. + STOP: bool, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + RESET: bool, // bit offset: 4 desc: When 1, asynchronously resets the transmit channel and FIFO. + WS_SEL: bool, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. + WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + MUTE: bool, // bit offset: 15 desc: When 1, the transmit channel sends only zeroes. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. + pub const DAI = mmio(Address + 0x00000004, 32, packed struct { + WORDWIDTH: u2, // bit offset: 0 desc: Selects the number of bytes in data as follows: + MONO: bool, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. + STOP: bool, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + RESET: bool, // bit offset: 4 desc: When 1, asynchronously reset the transmit channel and FIFO. + WS_SEL: bool, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. + WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. + pub const TXFIFO = mmio(Address + 0x00000008, 32, packed struct { + I2STXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. + }); + // byte offset: 12 I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. + pub const RXFIFO = mmio(Address + 0x0000000c, 32, packed struct { + I2SRXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. + }); + // byte offset: 16 I2S Status Feedback Register. Contains status information about the I2S interface. + pub const STATE = mmio(Address + 0x00000010, 32, packed struct { + IRQ: bool, // bit offset: 0 desc: This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. + DMAREQ1: bool, // bit offset: 1 desc: This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. + DMAREQ2: bool, // bit offset: 2 desc: This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 I2S DMA Configuration Register 1. Contains control information for DMA request 1. + pub const DMA1 = mmio(Address + 0x00000014, 32, packed struct { + RX_DMA1_ENABLE: bool, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. + TX_DMA1_ENABLE: bool, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 I2S DMA Configuration Register 2. Contains control information for DMA request 2. + pub const DMA2 = mmio(Address + 0x00000018, 32, packed struct { + RX_DMA2_ENABLE: bool, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. + TX_DMA2_ENABLE: bool, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. + pub const IRQ = mmio(Address + 0x0000001c, 32, packed struct { + RX_IRQ_ENABLE: bool, // bit offset: 0 desc: When 1, enables I2S receive interrupt. + TX_IRQ_ENABLE: bool, // bit offset: 1 desc: When 1, enables I2S transmit interrupt. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. + pub const TXRATE = mmio(Address + 0x00000020, 32, packed struct { + Y_DIVIDER: u8, // bit offset: 0 desc: I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. + X_DIVIDER: u8, // bit offset: 8 desc: I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. + pub const RXRATE = mmio(Address + 0x00000024, 32, packed struct { + Y_DIVIDER: u8, // bit offset: 0 desc: I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. + X_DIVIDER: u8, // bit offset: 8 desc: I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. + pub const TXBITRATE = mmio(Address + 0x00000028, 32, packed struct { + TX_BITRATE: u6, // bit offset: 0 desc: I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. + pub const RXBITRATE = mmio(Address + 0x0000002c, 32, packed struct { + RX_BITRATE: u6, // bit offset: 0 desc: I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 I2S Transmit mode control. + pub const TXMODE = mmio(Address + 0x00000030, 32, packed struct { + TXCLKSEL: u2, // bit offset: 0 desc: Clock source selection for the transmit bit clock divider. + TX4PIN: bool, // bit offset: 2 desc: Transmit 4-pin mode selection. When 1, enables 4-pin mode. + TXMCENA: bool, // bit offset: 3 desc: Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 I2S Receive mode control. + pub const RXMODE = mmio(Address + 0x00000034, 32, packed struct { + RXCLKSEL: u2, // bit offset: 0 desc: Clock source selection for the receive bit clock divider. + RX4PIN: bool, // bit offset: 2 desc: Receive 4-pin mode selection. When 1, enables 4-pin mode. + RXMCENA: bool, // bit offset: 3 desc: Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const RITIMER = extern struct { + pub const Address: u32 = 0x400b0000; + // byte offset: 0 Compare register + pub const COMPVAL = mmio(Address + 0x00000000, 32, packed struct { + RICOMP: u32, // bit offset: 0 desc: Compare register. Holds the compare value which is compared to the counter. + }); + // byte offset: 4 Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. + pub const MASK = mmio(Address + 0x00000004, 32, packed struct { + RIMASK: u32, // bit offset: 0 desc: Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). + }); + // byte offset: 8 Control register. + pub const CTRL = mmio(Address + 0x00000008, 32, packed struct { + RITINT: bool, // bit offset: 0 desc: Interrupt flag + RITENCLR: bool, // bit offset: 1 desc: Timer enable clear + RITENBR: bool, // bit offset: 2 desc: Timer enable for debug + RITEN: bool, // bit offset: 3 desc: Timer enable. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 32-bit counter + pub const COUNTER = mmio(Address + 0x0000000c, 32, packed struct { + RICOUNTER: u32, // bit offset: 0 desc: 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. + }); +}; +pub const MCPWM = extern struct { + pub const Address: u32 = 0x400b8000; + // byte offset: 0 PWM Control read address + pub const CON = mmio(Address + 0x00000000, 32, packed struct { + RUN0: bool, // bit offset: 0 desc: Stops/starts timer channel 0. + CENTER0: bool, // bit offset: 1 desc: Edge/center aligned operation for channel 0. + POLA0: bool, // bit offset: 2 desc: Selects polarity of the MCOA0 and MCOB0 pins. + DTE0: bool, // bit offset: 3 desc: Controls the dead-time feature for channel 0. + DISUP0: bool, // bit offset: 4 desc: Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RUN1: bool, // bit offset: 8 desc: Stops/starts timer channel 1. + CENTER1: bool, // bit offset: 9 desc: Edge/center aligned operation for channel 1. + POLA1: bool, // bit offset: 10 desc: Selects polarity of the MCOA1 and MCOB1 pins. + DTE1: bool, // bit offset: 11 desc: Controls the dead-time feature for channel 1. + DISUP1: bool, // bit offset: 12 desc: Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RUN2: bool, // bit offset: 16 desc: Stops/starts timer channel 2. + CENTER2: bool, // bit offset: 17 desc: Edge/center aligned operation for channel 2. + POLA2: bool, // bit offset: 18 desc: Selects polarity of the MCOA2 and MCOB2 pins. + DTE2: bool, // bit offset: 19 desc: Controls the dead-time feature for channel 1. + DISUP2: bool, // bit offset: 20 desc: Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + INVBDC: bool, // bit offset: 29 desc: Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. + ACMODE: bool, // bit offset: 30 desc: 3-phase AC mode select (see Section 24.8.7). + DCMODE: bool, // bit offset: 31 desc: 3-phase DC mode select (see Section 24.8.6). + }); + // byte offset: 4 PWM Control set address + pub const CON_SET = mmio(Address + 0x00000004, 32, packed struct { + RUN0_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CON register. + CENTER0_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CON register. + POLA0_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CON register. + DTE0_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CON register. + DISUP0_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CON register. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RUN1_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CON register. + CENTER1_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CON register. + POLA1_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CON register. + DTE1_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CON register. + DISUP1_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CON register. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RUN2_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CON register. + CENTER2_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CON register. + POLA2_SET: bool, // bit offset: 18 desc: Writing a one sets the corresponding bit in the CON register. + DTE2_SET: bool, // bit offset: 19 desc: Writing a one sets the corresponding bit in the CON register. + DISUP2_SET: bool, // bit offset: 20 desc: Writing a one sets the corresponding bit in the CON register. + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + INVBDC_SET: bool, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CON register. + ACMODE_SET: bool, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CON register. + DCMODE_SET: bool, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CON register. + }); + // byte offset: 8 PWM Control clear address + pub const CON_CLR = mmio(Address + 0x00000008, 32, packed struct { + RUN0_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CON register. + CENTER0_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CON register. + POLA0_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CON register. + DTE0_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CON register. + DISUP0_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CON register. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RUN1_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CON register. + CENTER1_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CON register. + POLA1_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CON register. + DTE1_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CON register. + DISUP1_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CON register. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + RUN2_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CON register. + CENTER2_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CON register. + POLA2_CLR: bool, // bit offset: 18 desc: Writing a one clears the corresponding bit in the CON register. + DTE2_CLR: bool, // bit offset: 19 desc: Writing a one clears the corresponding bit in the CON register. + DISUP2_CLR: bool, // bit offset: 20 desc: Writing a one clears the corresponding bit in the CON register. + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + INVBDC_CLR: bool, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CON register. + ACMOD_CLR: bool, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CON register. + DCMODE_CLR: bool, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CON register. + }); + // byte offset: 12 Capture Control read address + pub const CAPCON = mmio(Address + 0x0000000c, 32, packed struct { + CAP0MCI0_RE: bool, // bit offset: 0 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. + CAP0MCI0_FE: bool, // bit offset: 1 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. + CAP0MCI1_RE: bool, // bit offset: 2 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. + CAP0MCI1_FE: bool, // bit offset: 3 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. + CAP0MCI2_RE: bool, // bit offset: 4 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. + CAP0MCI2_FE: bool, // bit offset: 5 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. + CAP1MCI0_RE: bool, // bit offset: 6 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. + CAP1MCI0_FE: bool, // bit offset: 7 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. + CAP1MCI1_RE: bool, // bit offset: 8 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. + CAP1MCI1_FE: bool, // bit offset: 9 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. + CAP1MCI2_RE: bool, // bit offset: 10 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. + CAP1MCI2_FE: bool, // bit offset: 11 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. + CAP2MCI0_RE: bool, // bit offset: 12 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. + CAP2MCI0_FE: bool, // bit offset: 13 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. + CAP2MCI1_RE: bool, // bit offset: 14 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. + CAP2MCI1_FE: bool, // bit offset: 15 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. + CAP2MCI2_RE: bool, // bit offset: 16 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. + CAP2MCI2_FE: bool, // bit offset: 17 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. + RT0: bool, // bit offset: 18 desc: If this bit is 1, TC0 is reset by a channel 0 capture event. + RT1: bool, // bit offset: 19 desc: If this bit is 1, TC1 is reset by a channel 1 capture event. + RT2: bool, // bit offset: 20 desc: If this bit is 1, TC2 is reset by a channel 2 capture event. + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Capture Control set address + pub const CAPCON_SET = mmio(Address + 0x00000010, 32, packed struct { + CAP0MCI0_RE_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_FE_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_RE_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_FE_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_RE_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_FE_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_RE_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_FE_SET: bool, // bit offset: 7 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_RE_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_FE_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_RE_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_FE_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_RE_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_FE_SET: bool, // bit offset: 13 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_RE_SET: bool, // bit offset: 14 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_FE_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_RE_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_FE_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT0_SET: bool, // bit offset: 18 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT1_SET: bool, // bit offset: 19 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT2_SET: bool, // bit offset: 20 desc: Writing a one sets the corresponding bits in the CAPCON register. + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Event Control clear address + pub const CAPCON_CLR = mmio(Address + 0x00000014, 32, packed struct { + CAP0MCI0_RE_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_FE_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_RE_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_FE_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_RE_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_FE_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_RE_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_FE_CLR: bool, // bit offset: 7 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_RE_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_FE_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_RE_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_FE_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_RE_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_FE_CLR: bool, // bit offset: 13 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_RE_CLR: bool, // bit offset: 14 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_FE_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_RE_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_FE_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT0_CLR: bool, // bit offset: 18 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT1_CLR: bool, // bit offset: 19 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT2_CLR: bool, // bit offset: 20 desc: Writing a one clears the corresponding bits in the CAPCON register. + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Timer Counter register + pub const TC_0 = mmio(Address + 0x00000018, 32, packed struct { + MCTC: u32, // bit offset: 0 desc: Timer/Counter value. + }); + // byte offset: 28 Timer Counter register + pub const TC_1 = mmio(Address + 0x0000001c, 32, packed struct { + MCTC: u32, // bit offset: 0 desc: Timer/Counter value. + }); + // byte offset: 32 Timer Counter register + pub const TC_2 = mmio(Address + 0x00000020, 32, packed struct { + MCTC: u32, // bit offset: 0 desc: Timer/Counter value. + }); + // byte offset: 36 Limit register + pub const LIM_0 = mmio(Address + 0x00000024, 32, packed struct { + MCLIM: u32, // bit offset: 0 desc: Limit value. + }); + // byte offset: 40 Limit register + pub const LIM_1 = mmio(Address + 0x00000028, 32, packed struct { + MCLIM: u32, // bit offset: 0 desc: Limit value. + }); + // byte offset: 44 Limit register + pub const LIM_2 = mmio(Address + 0x0000002c, 32, packed struct { + MCLIM: u32, // bit offset: 0 desc: Limit value. + }); + // byte offset: 48 Match register + pub const MAT_0 = mmio(Address + 0x00000030, 32, packed struct { + MCMAT: u32, // bit offset: 0 desc: Match value. + }); + // byte offset: 52 Match register + pub const MAT_1 = mmio(Address + 0x00000034, 32, packed struct { + MCMAT: u32, // bit offset: 0 desc: Match value. + }); + // byte offset: 56 Match register + pub const MAT_2 = mmio(Address + 0x00000038, 32, packed struct { + MCMAT: u32, // bit offset: 0 desc: Match value. + }); + // byte offset: 60 Dead time register + pub const DT = mmio(Address + 0x0000003c, 32, packed struct { + DT0: u10, // bit offset: 0 desc: Dead time for channel 0.[1] + DT1: u10, // bit offset: 10 desc: Dead time for channel 1.[2] + DT2: u10, // bit offset: 20 desc: Dead time for channel 2.[2] + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 Communication Pattern register + pub const CP = mmio(Address + 0x00000040, 32, packed struct { + CCPA0: bool, // bit offset: 0 desc: Communication pattern output A, channel 0. + CCPB0: bool, // bit offset: 1 desc: Communication pattern output B, channel 0. + CCPA1: bool, // bit offset: 2 desc: Communication pattern output A, channel 1. + CCPB1: bool, // bit offset: 3 desc: Communication pattern output B, channel 1. + CCPA2: bool, // bit offset: 4 desc: Communication pattern output A, channel 2. + CCPB2: bool, // bit offset: 5 desc: Communication pattern output B, channel 2. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 Capture register + pub const CAP_0 = mmio(Address + 0x00000044, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. + }); + // byte offset: 72 Capture register + pub const CAP_1 = mmio(Address + 0x00000048, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. + }); + // byte offset: 76 Capture register + pub const CAP_2 = mmio(Address + 0x0000004c, 32, packed struct { + CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. + }); + // byte offset: 80 Interrupt Enable read address + pub const INTEN = mmio(Address + 0x00000050, 32, packed struct { + ILIM0: bool, // bit offset: 0 desc: Limit interrupt for channel 0. + IMAT0: bool, // bit offset: 1 desc: Match interrupt for channel 0. + ICAP0: bool, // bit offset: 2 desc: Capture interrupt for channel 0. + reserved1: u1 = 0, + ILIM1: bool, // bit offset: 4 desc: Limit interrupt for channel 1. + IMAT1: bool, // bit offset: 5 desc: Match interrupt for channel 1. + ICAP1: bool, // bit offset: 6 desc: Capture interrupt for channel 1. + reserved2: u1 = 0, + ILIM2: bool, // bit offset: 8 desc: Limit interrupt for channel 2. + IMAT2: bool, // bit offset: 9 desc: Match interrupt for channel 2. + ICAP2: bool, // bit offset: 10 desc: Capture interrupt for channel 2. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT: bool, // bit offset: 15 desc: Fast abort interrupt. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 Interrupt Enable set address + pub const INTEN_SET = mmio(Address + 0x00000054, 32, packed struct { + ILIM0_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT0_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP0_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + reserved1: u1 = 0, + ILIM1_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT1_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP1_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + reserved3: u1 = 0, + reserved2: u1 = 0, + ILIM2_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT2_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP2_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 88 Interrupt Enable clear address + pub const INTEN_CLR = mmio(Address + 0x00000058, 32, packed struct { + ILIM0_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT0_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP0_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved1: u1 = 0, + ILIM1_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT1_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP1_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved2: u1 = 0, + ILIM2_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT2_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP2_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 Count Control read address + pub const CNTCON = mmio(Address + 0x0000005c, 32, packed struct { + TC0MCI0_RE: bool, // bit offset: 0 desc: Counter 0 rising edge mode, channel 0. + TC0MCI0_FE: bool, // bit offset: 1 desc: Counter 0 falling edge mode, channel 0. + TC0MCI1_RE: bool, // bit offset: 2 desc: Counter 0 rising edge mode, channel 1. + TC0MCI1_FE: bool, // bit offset: 3 desc: Counter 0 falling edge mode, channel 1. + TC0MCI2_RE: bool, // bit offset: 4 desc: Counter 0 rising edge mode, channel 2. + TC0MCI2_FE: bool, // bit offset: 5 desc: Counter 0 falling edge mode, channel 2. + TC1MCI0_RE: bool, // bit offset: 6 desc: Counter 1 rising edge mode, channel 0. + TC1MCI0_FE: bool, // bit offset: 7 desc: Counter 1 falling edge mode, channel 0. + TC1MCI1_RE: bool, // bit offset: 8 desc: Counter 1 rising edge mode, channel 1. + TC1MCI1_FE: bool, // bit offset: 9 desc: Counter 1 falling edge mode, channel 1. + TC1MCI2_RE: bool, // bit offset: 10 desc: Counter 1 rising edge mode, channel 2. + TC1MCI2_FE: bool, // bit offset: 11 desc: Counter 1 falling edge mode, channel 2. + TC2MCI0_RE: bool, // bit offset: 12 desc: Counter 2 rising edge mode, channel 0. + TC2MCI0_FE: bool, // bit offset: 13 desc: Counter 2 falling edge mode, channel 0. + TC2MCI1_RE: bool, // bit offset: 14 desc: Counter 2 rising edge mode, channel 1. + TC2MCI1_FE: bool, // bit offset: 15 desc: Counter 2 falling edge mode, channel 1. + TC2MCI2_RE: bool, // bit offset: 16 desc: Counter 2 rising edge mode, channel 2. + TC2MCI2_FE: bool, // bit offset: 17 desc: Counter 2 falling edge mode, channel 2. + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CNTR0: bool, // bit offset: 29 desc: Channel 0 counter/timer mode. + CNTR1: bool, // bit offset: 30 desc: Channel 1 counter/timer mode. + CNTR2: bool, // bit offset: 31 desc: Channel 2 counter/timer mode. + }); + // byte offset: 96 Count Control set address + pub const CNTCON_SET = mmio(Address + 0x00000060, 32, packed struct { + TC0MCI0_RE_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_FE_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_RE_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_FE_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_RE_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_FE_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_RE_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_FE_SET: bool, // bit offset: 7 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_RE_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_FE_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_RE_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_FE_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_RE_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_FE_SET: bool, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_RE_SET: bool, // bit offset: 14 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_FE_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_RE_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_FE_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CNTCON register. + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CNTR0_SET: bool, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CNTCON register. + CNTR1_SET: bool, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CNTCON register. + CNTR2_SET: bool, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CNTCON register. + }); + // byte offset: 100 Count Control clear address + pub const CNTCON_CLR = mmio(Address + 0x00000064, 32, packed struct { + TC0MCI0_RE_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_FE_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_RE_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_FE_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_RE: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_FE_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_RE_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_FE_CLR: bool, // bit offset: 7 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_RE_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_FE_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_RE_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_FE_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_RE_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_FE_CLR: bool, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_RE_CLR: bool, // bit offset: 14 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_FE_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_RE_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_FE_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CNTCON register. + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CNTR0_CLR: bool, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CNTCON register. + CNTR1_CLR: bool, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CNTCON register. + CNTR2_CLR: bool, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CNTCON register. + }); + // byte offset: 104 Interrupt flags read address + pub const INTF = mmio(Address + 0x00000068, 32, packed struct { + ILIM0_F: bool, // bit offset: 0 desc: Limit interrupt flag for channel 0. + IMAT0_F: bool, // bit offset: 1 desc: Match interrupt flag for channel 0. + ICAP0_F: bool, // bit offset: 2 desc: Capture interrupt flag for channel 0. + reserved1: u1 = 0, + ILIM1_F: bool, // bit offset: 4 desc: Limit interrupt flag for channel 1. + IMAT1_F: bool, // bit offset: 5 desc: Match interrupt flag for channel 1. + ICAP1_F: bool, // bit offset: 6 desc: Capture interrupt flag for channel 1. + reserved2: u1 = 0, + ILIM2_F: bool, // bit offset: 8 desc: Limit interrupt flag for channel 2. + IMAT2_F: bool, // bit offset: 9 desc: Match interrupt flag for channel 2. + ICAP2_F: bool, // bit offset: 10 desc: Capture interrupt flag for channel 2. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT_F: bool, // bit offset: 15 desc: Fast abort interrupt flag. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 108 Interrupt flags set address + pub const INTF_SET = mmio(Address + 0x0000006c, 32, packed struct { + ILIM0_F_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT0_F_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP0_F_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + reserved1: u1 = 0, + ILIM1_F_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT1_F_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP1_F_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + reserved2: u1 = 0, + ILIM2_F_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT2_F_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP2_F_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT_F_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Interrupt flags clear address + pub const INTF_CLR = mmio(Address + 0x00000070, 32, packed struct { + ILIM0_F_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. + IMAT0_F_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP0_F_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved1: u1 = 0, + ILIM1_F_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT1_F_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP1_F_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved2: u1 = 0, + ILIM2_F_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT2_F_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP2_F_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + ABORT_F_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 Capture clear address + pub const CAP_CLR = mmio(Address + 0x00000074, 32, packed struct { + CAP_CLR0: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the CAP0 register. + CAP_CLR1: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the CAP1 register. + CAP_CLR2: bool, // bit offset: 2 desc: Writing a 1 to this bit clears the CAP2 register. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const QEI = extern struct { + pub const Address: u32 = 0x400bc000; + // byte offset: 0 Control register + pub const CON = mmio(Address + 0x00000000, 32, packed struct { + RESP: bool, // bit offset: 0 desc: Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. + RESPI: bool, // bit offset: 1 desc: Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. + RESV: bool, // bit offset: 2 desc: Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. + RESI: bool, // bit offset: 3 desc: Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Status register + pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + DIR: bool, // bit offset: 0 desc: Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Configuration register + pub const CONF = mmio(Address + 0x00000008, 32, packed struct { + DIRINV: bool, // bit offset: 0 desc: Direction invert. When 1, complements the DIR bit. + SIGMODE: bool, // bit offset: 1 desc: Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. + CAPMODE: bool, // bit offset: 2 desc: Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. + INVINX: bool, // bit offset: 3 desc: Invert Index. When 1, inverts the sense of the index input. + CRESPI: bool, // bit offset: 4 desc: Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + INXGATE: u4, // bit offset: 16 desc: Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Position register + pub const POS = mmio(Address + 0x0000000c, 32, packed struct { + POS: u32, // bit offset: 0 desc: Current position value. + }); + // byte offset: 16 Maximum position register + pub const MAXPOS = mmio(Address + 0x00000010, 32, packed struct { + MAXPOS: u32, // bit offset: 0 desc: Current maximum position value. + }); + // byte offset: 20 Position compare register 0 + pub const CMPOS0 = mmio(Address + 0x00000014, 32, packed struct { + PCMP0: u32, // bit offset: 0 desc: Position compare value 0. + }); + // byte offset: 24 Position compare register 1 + pub const CMPOS1 = mmio(Address + 0x00000018, 32, packed struct { + PCMP1: u32, // bit offset: 0 desc: Position compare value 1. + }); + // byte offset: 28 Position compare register 2 + pub const CMPOS2 = mmio(Address + 0x0000001c, 32, packed struct { + PCMP2: u32, // bit offset: 0 desc: Position compare value 2. + }); + // byte offset: 32 Index count register 0 + pub const INXCNT = mmio(Address + 0x00000020, 32, packed struct { + ENCPOS: u32, // bit offset: 0 desc: Current index counter value. + }); + // byte offset: 36 Index compare register 0 + pub const INXCMP0 = mmio(Address + 0x00000024, 32, packed struct { + ICMP0: u32, // bit offset: 0 desc: Index compare value 0. + }); + // byte offset: 40 Velocity timer reload register + pub const LOAD = mmio(Address + 0x00000028, 32, packed struct { + VELLOAD: u32, // bit offset: 0 desc: Current velocity timer load value. + }); + // byte offset: 44 Velocity timer register + pub const TIME = mmio(Address + 0x0000002c, 32, packed struct { + VELVAL: u32, // bit offset: 0 desc: Current velocity timer value. + }); + // byte offset: 48 Velocity counter register + pub const VEL = mmio(Address + 0x00000030, 32, packed struct { + VELPC: u32, // bit offset: 0 desc: Current velocity pulse count. + }); + // byte offset: 52 Velocity capture register + pub const CAP = mmio(Address + 0x00000034, 32, packed struct { + VELCAP: u32, // bit offset: 0 desc: Last velocity capture. + }); + // byte offset: 56 Velocity compare register + pub const VELCOMP = mmio(Address + 0x00000038, 32, packed struct { + VELPC: u32, // bit offset: 0 desc: Compare velocity pulse count. + }); + // byte offset: 60 Digital filter register + pub const FILTER = mmio(Address + 0x0000003c, 32, packed struct { + FILTA: u32, // bit offset: 0 desc: Digital filter sampling delay. + }); + // byte offset: 4056 Interrupt enable clear register + pub const IEC = mmio(Address + 0x00000fd8, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: Writing a 1 disables the INX_Int interrupt in the QEIIE register. + TIM_INT: bool, // bit offset: 1 desc: Writing a 1 disables the TIN_Int interrupt in the QEIIE register. + VELC_INT: bool, // bit offset: 2 desc: Writing a 1 disables the VELC_Int interrupt in the QEIIE register. + DIR_INT: bool, // bit offset: 3 desc: Writing a 1 disables the DIR_Int interrupt in the QEIIE register. + ERR_INT: bool, // bit offset: 4 desc: Writing a 1 disables the ERR_Int interrupt in the QEIIE register. + ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. + POS0_INT: bool, // bit offset: 6 desc: Writing a 1 disables the POS0_Int interrupt in the QEIIE register. + POS1_INT: bool, // bit offset: 7 desc: Writing a 1 disables the POS1_Int interrupt in the QEIIE register. + POS2_INT: bool, // bit offset: 8 desc: Writing a 1 disables the POS2_Int interrupt in the QEIIE register. + REV0_INT: bool, // bit offset: 9 desc: Writing a 1 disables the REV0_Int interrupt in the QEIIE register. + POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. + POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. + POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. + REV1_INT: bool, // bit offset: 13 desc: Writing a 1 disables the REV1_Int interrupt in the QEIIE register. + REV2_INT: bool, // bit offset: 14 desc: Writing a 1 disables the REV2_Int interrupt in the QEIIE register. + MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4060 Interrupt enable set register + pub const IES = mmio(Address + 0x00000fdc, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: Writing a 1 enables the INX_Int interrupt in the QEIIE register. + TIM_INT: bool, // bit offset: 1 desc: Writing a 1 enables the TIN_Int interrupt in the QEIIE register. + VELC_INT: bool, // bit offset: 2 desc: Writing a 1 enables the VELC_Int interrupt in the QEIIE register. + DIR_INT: bool, // bit offset: 3 desc: Writing a 1 enables the DIR_Int interrupt in the QEIIE register. + ERR_INT: bool, // bit offset: 4 desc: Writing a 1 enables the ERR_Int interrupt in the QEIIE register. + ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. + POS0_INT: bool, // bit offset: 6 desc: Writing a 1 enables the POS0_Int interrupt in the QEIIE register. + POS1_INT: bool, // bit offset: 7 desc: Writing a 1 enables the POS1_Int interrupt in the QEIIE register. + POS2_INT: bool, // bit offset: 8 desc: Writing a 1 enables the POS2_Int interrupt in the QEIIE register. + REV0_INT: bool, // bit offset: 9 desc: Writing a 1 enables the REV0_Int interrupt in the QEIIE register. + POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. + POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. + POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. + REV1_INT: bool, // bit offset: 13 desc: Writing a 1 enables the REV1_Int interrupt in the QEIIE register. + REV2_INT: bool, // bit offset: 14 desc: Writing a 1 enables the REV2_Int interrupt in the QEIIE register. + MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4064 Interrupt status register + pub const INTSTAT = mmio(Address + 0x00000fe0, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: Indicates that an index pulse was detected. + TIM_INT: bool, // bit offset: 1 desc: Indicates that a velocity timer overflow occurred + VELC_INT: bool, // bit offset: 2 desc: Indicates that captured velocity is less than compare velocity. + DIR_INT: bool, // bit offset: 3 desc: Indicates that a change of direction was detected. + ERR_INT: bool, // bit offset: 4 desc: Indicates that an encoder phase error was detected. + ENCLK_INT: bool, // bit offset: 5 desc: Indicates that and encoder clock pulse was detected. + POS0_INT: bool, // bit offset: 6 desc: Indicates that the position 0 compare value is equal to the current position. + POS1_INT: bool, // bit offset: 7 desc: Indicates that the position 1compare value is equal to the current position. + POS2_INT: bool, // bit offset: 8 desc: Indicates that the position 2 compare value is equal to the current position. + REV0_INT: bool, // bit offset: 9 desc: Indicates that the index compare 0 value is equal to the current index count. + POS0REV_INT: bool, // bit offset: 10 desc: Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. + POS1REV_INT: bool, // bit offset: 11 desc: Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. + POS2REV_INT: bool, // bit offset: 12 desc: Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. + REV1_INT: bool, // bit offset: 13 desc: Indicates that the index compare 1value is equal to the current index count. + REV2_INT: bool, // bit offset: 14 desc: Indicates that the index compare 2 value is equal to the current index count. + MAXPOS_INT: bool, // bit offset: 15 desc: Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4068 Interrupt enable register + pub const IE = mmio(Address + 0x00000fe4, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: When 1, the INX_Int interrupt is enabled. + TIM_INT: bool, // bit offset: 1 desc: When 1, the TIN_Int interrupt is enabled. + VELC_INT: bool, // bit offset: 2 desc: When 1, the VELC_Int interrupt is enabled. + DIR_INT: bool, // bit offset: 3 desc: When 1, the DIR_Int interrupt is enabled. + ERR_INT: bool, // bit offset: 4 desc: When 1, the ERR_Int interrupt is enabled. + ENCLK_INT: bool, // bit offset: 5 desc: When 1, the ENCLK_Int interrupt is enabled. + POS0_INT: bool, // bit offset: 6 desc: When 1, the POS0_Int interrupt is enabled. + POS1_INT: bool, // bit offset: 7 desc: When 1, the POS1_Int interrupt is enabled. + POS2_INT: bool, // bit offset: 8 desc: When 1, the POS2_Int interrupt is enabled. + REV0_INT: bool, // bit offset: 9 desc: When 1, the REV0_Int interrupt is enabled. + POS0REV_INT: bool, // bit offset: 10 desc: When 1, the POS0REV_Int interrupt is enabled. + POS1REV_INT: bool, // bit offset: 11 desc: When 1, the POS1REV_Int interrupt is enabled. + POS2REV_INT: bool, // bit offset: 12 desc: When 1, the POS2REV_Int interrupt is enabled. + REV1_INT: bool, // bit offset: 13 desc: When 1, the REV1_Int interrupt is enabled. + REV2_INT: bool, // bit offset: 14 desc: When 1, the REV2_Int interrupt is enabled. + MAXPOS_INT: bool, // bit offset: 15 desc: When 1, the MAXPOS_Int interrupt is enabled. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4072 Interrupt status clear register + pub const CLR = mmio(Address + 0x00000fe8, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: Writing a 1 clears the INX_Int bit in QEIINTSTAT. + TIM_INT: bool, // bit offset: 1 desc: Writing a 1 clears the TIN_Int bit in QEIINTSTAT. + VELC_INT: bool, // bit offset: 2 desc: Writing a 1 clears the VELC_Int bit in QEIINTSTAT. + DIR_INT: bool, // bit offset: 3 desc: Writing a 1 clears the DIR_Int bit in QEIINTSTAT. + ERR_INT: bool, // bit offset: 4 desc: Writing a 1 clears the ERR_Int bit in QEIINTSTAT. + ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. + POS0_INT: bool, // bit offset: 6 desc: Writing a 1 clears the POS0_Int bit in QEIINTSTAT. + POS1_INT: bool, // bit offset: 7 desc: Writing a 1 clears the POS1_Int bit in QEIINTSTAT. + POS2_INT: bool, // bit offset: 8 desc: Writing a 1 clears the POS2_Int bit in QEIINTSTAT. + REV0_INT: bool, // bit offset: 9 desc: Writing a 1 clears the REV0_Int bit in QEIINTSTAT. + POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. + POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. + POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. + REV1_INT: bool, // bit offset: 13 desc: Writing a 1 clears the REV1_Int bit in QEIINTSTAT. + REV2_INT: bool, // bit offset: 14 desc: Writing a 1 clears the REV2_Int bit in QEIINTSTAT. + MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4076 Interrupt status set register + pub const SET = mmio(Address + 0x00000fec, 32, packed struct { + INX_INT: bool, // bit offset: 0 desc: Writing a 1 sets the INX_Int bit in QEIINTSTAT. + TIM_INT: bool, // bit offset: 1 desc: Writing a 1 sets the TIN_Int bit in QEIINTSTAT. + VELC_INT: bool, // bit offset: 2 desc: Writing a 1 sets the VELC_Int bit in QEIINTSTAT. + DIR_INT: bool, // bit offset: 3 desc: Writing a 1 sets the DIR_Int bit in QEIINTSTAT. + ERR_INT: bool, // bit offset: 4 desc: Writing a 1 sets the ERR_Int bit in QEIINTSTAT. + ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. + POS0_INT: bool, // bit offset: 6 desc: Writing a 1 sets the POS0_Int bit in QEIINTSTAT. + POS1_INT: bool, // bit offset: 7 desc: Writing a 1 sets the POS1_Int bit in QEIINTSTAT. + POS2_INT: bool, // bit offset: 8 desc: Writing a 1 sets the POS2_Int bit in QEIINTSTAT. + REV0_INT: bool, // bit offset: 9 desc: Writing a 1 sets the REV0_Int bit in QEIINTSTAT. + POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. + POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. + POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. + REV1_INT: bool, // bit offset: 13 desc: Writing a 1 sets the REV1_Int bit in QEIINTSTAT. + REV2_INT: bool, // bit offset: 14 desc: Writing a 1 sets the REV2_Int bit in QEIINTSTAT. + MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SYSCON = extern struct { + pub const Address: u32 = 0x400fc000; + // byte offset: 0 Flash Accelerator Configuration Register. Controls flash access timing. + pub const FLASHCFG = mmio(Address + 0x00000000, 32, packed struct { + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FLASHTIM: u4, // bit offset: 12 desc: Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 128 PLL0 Control Register + pub const PLL0CON = mmio(Address + 0x00000080, 32, packed struct { + PLLE0: bool, // bit offset: 0 desc: PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register. + PLLC0: bool, // bit offset: 1 desc: PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 PLL0 Configuration Register + pub const PLL0CFG = mmio(Address + 0x00000084, 32, packed struct { + MSEL0: u15, // bit offset: 0 desc: PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware. + reserved1: u1 = 0, + NSEL0: u8, // bit offset: 16 desc: PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32. + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 PLL0 Status Register + pub const PLL0STAT = mmio(Address + 0x00000088, 32, packed struct { + MSEL0: u15, // bit offset: 0 desc: Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier. + reserved1: u1 = 0, + NSEL0: u8, // bit offset: 16 desc: Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider. + PLLE0_STAT: bool, // bit offset: 24 desc: Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. + PLLC0_STAT: bool, // bit offset: 25 desc: Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. + PLOCK0: bool, // bit offset: 26 desc: Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 PLL0 Feed Register + pub const PLL0FEED = mmio(Address + 0x0000008c, 32, packed struct { + PLL0FEED: u8, // bit offset: 0 desc: The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 PLL1 Control Register + pub const PLL1CON = mmio(Address + 0x000000a0, 32, packed struct { + PLLE1: bool, // bit offset: 0 desc: PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. + PLLC1: bool, // bit offset: 1 desc: PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 PLL1 Configuration Register + pub const PLL1CFG = mmio(Address + 0x000000a4, 32, packed struct { + MSEL1: u5, // bit offset: 0 desc: PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. + PSEL1: u2, // bit offset: 5 desc: PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 168 PLL1 Status Register + pub const PLL1STAT = mmio(Address + 0x000000a8, 32, packed struct { + MSEL1: u5, // bit offset: 0 desc: Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1. + PSEL1: u2, // bit offset: 5 desc: Read-back for the PLL1 Divider value. This is the value currently used by PLL1. + reserved1: u1 = 0, + PLLE1_STAT: bool, // bit offset: 8 desc: Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. + PLLC1_STAT: bool, // bit offset: 9 desc: Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. + PLOCK1: bool, // bit offset: 10 desc: Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 172 PLL1 Feed Register + pub const PLL1FEED = mmio(Address + 0x000000ac, 32, packed struct { + PLL1FEED: u8, // bit offset: 0 desc: The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 192 Power Control Register + pub const PCON = mmio(Address + 0x000000c0, 32, packed struct { + PM0: bool, // bit offset: 0 desc: Power mode control bit 0. This bit controls entry to the Power-down mode. + PM1: bool, // bit offset: 1 desc: Power mode control bit 1. This bit controls entry to the Deep Power-down mode. + BODRPM: bool, // bit offset: 2 desc: Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. + BOGD: bool, // bit offset: 3 desc: Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. + BORD: bool, // bit offset: 4 desc: Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMFLAG: bool, // bit offset: 8 desc: Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. + DSFLAG: bool, // bit offset: 9 desc: Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. + PDFLAG: bool, // bit offset: 10 desc: Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. + DPDFLAG: bool, // bit offset: 11 desc: Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 196 Power Control for Peripherals Register + pub const PCONP = mmio(Address + 0x000000c4, 32, packed struct { + reserved1: u1 = 0, + PCTIM0: bool, // bit offset: 1 desc: Timer/Counter 0 power/clock control bit. + PCTIM1: bool, // bit offset: 2 desc: Timer/Counter 1 power/clock control bit. + PCUART0: bool, // bit offset: 3 desc: UART0 power/clock control bit. + PCUART1: bool, // bit offset: 4 desc: UART1 power/clock control bit. + reserved2: u1 = 0, + PCPWM1: bool, // bit offset: 6 desc: PWM1 power/clock control bit. + PCI2C0: bool, // bit offset: 7 desc: The I2C0 interface power/clock control bit. + PCSPI: bool, // bit offset: 8 desc: The SPI interface power/clock control bit. + PCRTC: bool, // bit offset: 9 desc: The RTC power/clock control bit. + PCSSP1: bool, // bit offset: 10 desc: The SSP 1 interface power/clock control bit. + reserved3: u1 = 0, + PCADC: bool, // bit offset: 12 desc: A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. + PCCAN1: bool, // bit offset: 13 desc: CAN Controller 1 power/clock control bit. + PCCAN2: bool, // bit offset: 14 desc: CAN Controller 2 power/clock control bit. + PCGPIO: bool, // bit offset: 15 desc: Power/clock control bit for IOCON, GPIO, and GPIO interrupts. + PCRIT: bool, // bit offset: 16 desc: Repetitive Interrupt Timer power/clock control bit. + PCMCPWM: bool, // bit offset: 17 desc: Motor Control PWM + PCQEI: bool, // bit offset: 18 desc: Quadrature Encoder Interface power/clock control bit. + PCI2C1: bool, // bit offset: 19 desc: The I2C1 interface power/clock control bit. + reserved4: u1 = 0, + PCSSP0: bool, // bit offset: 21 desc: The SSP0 interface power/clock control bit. + PCTIM2: bool, // bit offset: 22 desc: Timer 2 power/clock control bit. + PCTIM3: bool, // bit offset: 23 desc: Timer 3 power/clock control bit. + PCUART2: bool, // bit offset: 24 desc: UART 2 power/clock control bit. + PCUART3: bool, // bit offset: 25 desc: UART 3 power/clock control bit. + PCI2C2: bool, // bit offset: 26 desc: I2C interface 2 power/clock control bit. + PCI2S: bool, // bit offset: 27 desc: I2S interface power/clock control bit. + reserved5: u1 = 0, + PCGPDMA: bool, // bit offset: 29 desc: GPDMA function power/clock control bit. + PCENET: bool, // bit offset: 30 desc: Ethernet block power/clock control bit. + PCUSB: bool, // bit offset: 31 desc: USB interface power/clock control bit. + }); + // byte offset: 260 CPU Clock Configuration Register + pub const CCLKCFG = mmio(Address + 0x00000104, 32, packed struct { + CCLKSEL: u8, // bit offset: 0 desc: Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 264 USB Clock Configuration Register + pub const USBCLKCFG = mmio(Address + 0x00000108, 32, packed struct { + USBSEL: u4, // bit offset: 0 desc: Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 268 Clock Source Select Register + pub const CLKSRCSEL = mmio(Address + 0x0000010c, 32, packed struct { + CLKSRC: u2, // bit offset: 0 desc: Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 272 Allows clearing the current CAN channel sleep state as well as reading that state. + pub const CANSLEEPCLR = mmio(Address + 0x00000110, 32, packed struct { + reserved1: u1 = 0, + CAN1SLEEP: bool, // bit offset: 1 desc: Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. + CAN2SLEEP: bool, // bit offset: 2 desc: Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 276 Allows reading the wake-up state of the CAN channels. + pub const CANWAKEFLAGS = mmio(Address + 0x00000114, 32, packed struct { + reserved1: u1 = 0, + CAN1WAKE: bool, // bit offset: 1 desc: Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. + CAN2WAKE: bool, // bit offset: 2 desc: Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 320 External Interrupt Flag Register + pub const EXTINT = mmio(Address + 0x00000140, 32, packed struct { + EINT0: bool, // bit offset: 0 desc: In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT1: bool, // bit offset: 1 desc: In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT2: bool, // bit offset: 2 desc: In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT3: bool, // bit offset: 3 desc: In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 328 External Interrupt Mode register + pub const EXTMODE = mmio(Address + 0x00000148, 32, packed struct { + EXTMODE0: bool, // bit offset: 0 desc: External interrupt 0 EINT0 mode. + EXTMODE1: bool, // bit offset: 1 desc: External interrupt 1 EINT1 mode. + EXTMODE2: bool, // bit offset: 2 desc: External interrupt 2 EINT2 mode. + EXTMODE3: bool, // bit offset: 3 desc: External interrupt 3 EINT3 mode. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 332 External Interrupt Polarity Register + pub const EXTPOLAR = mmio(Address + 0x0000014c, 32, packed struct { + EXTPOLAR0: bool, // bit offset: 0 desc: External interrupt 0 EINT0 polarity. + EXTPOLAR1: bool, // bit offset: 1 desc: External interrupt 1 EINT1 polarity. + EXTPOLAR2: bool, // bit offset: 2 desc: External interrupt 2 EINT2 polarity. + EXTPOLAR3: bool, // bit offset: 3 desc: External interrupt 3 EINT3 polarity. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 384 Reset Source Identification Register + pub const RSID = mmio(Address + 0x00000180, 32, packed struct { + POR: bool, // bit offset: 0 desc: Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. + EXTR: bool, // bit offset: 1 desc: Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR. + WDTR: bool, // bit offset: 2 desc: This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. + BODR: bool, // bit offset: 3 desc: This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 416 System control and status + pub const SCS = mmio(Address + 0x000001a0, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OSCRANGE: bool, // bit offset: 4 desc: Main oscillator range select. + OSCEN: bool, // bit offset: 5 desc: Main oscillator enable. + OSCSTAT: bool, // bit offset: 6 desc: Main oscillator status. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 424 Peripheral Clock Selection register 0. + pub const PCLKSEL0 = mmio(Address + 0x000001a8, 32, packed struct { + PCLK_WDT: u2, // bit offset: 0 desc: Peripheral clock selection for WDT. + PCLK_TIMER0: u2, // bit offset: 2 desc: Peripheral clock selection for TIMER0. + PCLK_TIMER1: u2, // bit offset: 4 desc: Peripheral clock selection for TIMER1. + PCLK_UART0: u2, // bit offset: 6 desc: Peripheral clock selection for UART0. + PCLK_UART1: u2, // bit offset: 8 desc: Peripheral clock selection for UART1. + reserved2: u1 = 0, + reserved1: u1 = 0, + PCLK_PWM1: u2, // bit offset: 12 desc: Peripheral clock selection for PWM1. + PCLK_I2C0: u2, // bit offset: 14 desc: Peripheral clock selection for I2C0. + PCLK_SPI: u2, // bit offset: 16 desc: Peripheral clock selection for SPI. + reserved3: u1 = 0, + reserved2: u1 = 0, + PCLK_SSP1: u2, // bit offset: 20 desc: Peripheral clock selection for SSP1. + PCLK_DAC: u2, // bit offset: 22 desc: Peripheral clock selection for DAC. + PCLK_ADC: u2, // bit offset: 24 desc: Peripheral clock selection for ADC. + PCLK_CAN1: u2, // bit offset: 26 desc: Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + PCLK_CAN2: u2, // bit offset: 28 desc: Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + PCLK_ACF: u2, // bit offset: 30 desc: Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + }); + // byte offset: 428 Peripheral Clock Selection register 1. + pub const PCLKSEL1 = mmio(Address + 0x000001ac, 32, packed struct { + PCLK_QEI: u2, // bit offset: 0 desc: Peripheral clock selection for the Quadrature Encoder Interface. + PCLK_GPIOINT: u2, // bit offset: 2 desc: Peripheral clock selection for GPIO interrupts. + PCLK_PCB: u2, // bit offset: 4 desc: Peripheral clock selection for the Pin Connect block. + PCLK_I2C1: u2, // bit offset: 6 desc: Peripheral clock selection for I2C1. + reserved2: u1 = 0, + reserved1: u1 = 0, + PCLK_SSP0: u2, // bit offset: 10 desc: Peripheral clock selection for SSP0. + PCLK_TIMER2: u2, // bit offset: 12 desc: Peripheral clock selection for TIMER2. + PCLK_TIMER3: u2, // bit offset: 14 desc: Peripheral clock selection for TIMER3. + PCLK_UART2: u2, // bit offset: 16 desc: Peripheral clock selection for UART2. + PCLK_UART3: u2, // bit offset: 18 desc: Peripheral clock selection for UART3. + PCLK_I2C2: u2, // bit offset: 20 desc: Peripheral clock selection for I2C2. + PCLK_I2S: u2, // bit offset: 22 desc: Peripheral clock selection for I2S. + reserved3: u1 = 0, + reserved2: u1 = 0, + PCLK_RIT: u2, // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. + PCLK_SYSCON: u2, // bit offset: 28 desc: Peripheral clock selection for the System Control block. + PCLK_MC: u2, // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. + }); + // byte offset: 448 USB Interrupt Status + pub const USBINTST = mmio(Address + 0x000001c0, 32, packed struct { + USB_INT_REQ_LP: bool, // bit offset: 0 desc: Low priority interrupt line status. This bit is read-only. + USB_INT_REQ_HP: bool, // bit offset: 1 desc: High priority interrupt line status. This bit is read-only. + USB_INT_REQ_DMA: bool, // bit offset: 2 desc: DMA interrupt line status. This bit is read-only. + USB_HOST_INT: bool, // bit offset: 3 desc: USB host interrupt line status. This bit is read-only. + USB_ATX_INT: bool, // bit offset: 4 desc: External ATX interrupt line status. This bit is read-only. + USB_OTG_INT: bool, // bit offset: 5 desc: OTG interrupt line status. This bit is read-only. + USB_I2C_INT: bool, // bit offset: 6 desc: I2C module interrupt line status. This bit is read-only. + reserved1: u1 = 0, + USB_NEED_CLK: bool, // bit offset: 8 desc: USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only. + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + EN_USB_INTS: bool, // bit offset: 31 desc: Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. + }); + // byte offset: 452 Selects between alternative requests on DMA channels 0 through 7 and 10 through 15 + pub const DMACREQSEL = mmio(Address + 0x000001c4, 32, packed struct { + DMASEL08: bool, // bit offset: 0 desc: Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected. + DMASEL09: bool, // bit offset: 1 desc: Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected. + DMASEL10: bool, // bit offset: 2 desc: Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected. + DMASEL11: bool, // bit offset: 3 desc: Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected. + DMASEL12: bool, // bit offset: 4 desc: Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected. + DMASEL13: bool, // bit offset: 5 desc: Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected. + DMASEL14: bool, // bit offset: 6 desc: Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected. + DMASEL15: bool, // bit offset: 7 desc: Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 456 Clock Output Configuration Register + pub const CLKOUTCFG = mmio(Address + 0x000001c8, 32, packed struct { + CLKOUTSEL: u4, // bit offset: 0 desc: Selects the clock source for the CLKOUT function. Other values are reserved. Do not use. + CLKOUTDIV: u4, // bit offset: 4 desc: Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16. + CLKOUT_EN: bool, // bit offset: 8 desc: CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. + CLKOUT_ACT: bool, // bit offset: 9 desc: CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const EMAC = extern struct { + pub const Address: u32 = 0x50000000; + // byte offset: 0 MAC configuration register 1. + pub const MAC1 = mmio(Address + 0x00000000, 32, packed struct { + RXENABLE: bool, // bit offset: 0 desc: RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. + PARF: bool, // bit offset: 1 desc: PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. + RXFLOWCTRL: bool, // bit offset: 2 desc: RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. + TXFLOWCTRL: bool, // bit offset: 3 desc: TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. + LOOPBACK: bool, // bit offset: 4 desc: Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESETTX: bool, // bit offset: 8 desc: Setting this bit will put the Transmit Function logic in reset. + RESETMCSTX: bool, // bit offset: 9 desc: Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. + RESETRX: bool, // bit offset: 10 desc: Setting this bit will put the Ethernet receive logic in reset. + RESETMCSRX: bool, // bit offset: 11 desc: Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. + reserved3: u1 = 0, + reserved2: u1 = 0, + SIMRESET: bool, // bit offset: 14 desc: SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. + SOFTRESET: bool, // bit offset: 15 desc: SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 MAC configuration register 2. + pub const MAC2 = mmio(Address + 0x00000004, 32, packed struct { + FULLDUPLEX: bool, // bit offset: 0 desc: When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. + FLC: bool, // bit offset: 1 desc: FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. + HFEN: bool, // bit offset: 2 desc: HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. + DELAYEDCRC: bool, // bit offset: 3 desc: DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. + CRCEN: bool, // bit offset: 4 desc: CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. + PADCRCEN: bool, // bit offset: 5 desc: PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. + VLANPADEN: bool, // bit offset: 6 desc: VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. + AUTODETPADEN: bool, // bit offset: 7 desc: AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. + PPENF: bool, // bit offset: 8 desc: PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. + LPENF: bool, // bit offset: 9 desc: LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. + reserved2: u1 = 0, + reserved1: u1 = 0, + NOBACKOFF: bool, // bit offset: 12 desc: When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. + BP_NOBACKOFF: bool, // bit offset: 13 desc: BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. + EXCESSDEFER: bool, // bit offset: 14 desc: When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Back-to-Back Inter-Packet-Gap register. + pub const IPGT = mmio(Address + 0x00000008, 32, packed struct { + BTOBINTEGAP: u7, // bit offset: 0 desc: BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Non Back-to-Back Inter-Packet-Gap register. + pub const IPGR = mmio(Address + 0x0000000c, 32, packed struct { + NBTOBINTEGAP2: u7, // bit offset: 0 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). + reserved1: u1 = 0, + NBTOBINTEGAP1: u7, // bit offset: 8 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Collision window / Retry register. + pub const CLRT = mmio(Address + 0x00000010, 32, packed struct { + RETRANSMAX: u4, // bit offset: 0 desc: RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COLLWIN: u6, // bit offset: 8 desc: COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Maximum Frame register. + pub const MAXF = mmio(Address + 0x00000014, 32, packed struct { + MAXFLEN: u16, // bit offset: 0 desc: MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 PHY Support register. + pub const SUPP = mmio(Address + 0x00000018, 32, packed struct { + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SPEED: bool, // bit offset: 8 desc: This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Test register. + pub const TEST = mmio(Address + 0x0000001c, 32, packed struct { + SCPQ: bool, // bit offset: 0 desc: SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. + TESTPAUSE: bool, // bit offset: 1 desc: This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. + TESTBP: bool, // bit offset: 2 desc: TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 MII Mgmt Configuration register. + pub const MCFG = mmio(Address + 0x00000020, 32, packed struct { + SCANINC: bool, // bit offset: 0 desc: SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. + SUPPPREAMBLE: bool, // bit offset: 1 desc: SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. + CLOCKSEL: u4, // bit offset: 2 desc: CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field. + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESETMIIMGMT: bool, // bit offset: 15 desc: RESET MII MGMT. This bit resets the MII Management hardware. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 MII Mgmt Command register. + pub const MCMD = mmio(Address + 0x00000024, 32, packed struct { + READ: bool, // bit offset: 0 desc: This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). + SCAN: bool, // bit offset: 1 desc: This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 MII Mgmt Address register. + pub const MADR = mmio(Address + 0x00000028, 32, packed struct { + REGADDR: u5, // bit offset: 0 desc: REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PHYADDR: u5, // bit offset: 8 desc: PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 MII Mgmt Write Data register. + pub const MWTD = mmio(Address + 0x0000002c, 32, packed struct { + WRITEDATA: u16, // bit offset: 0 desc: WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 MII Mgmt Read Data register. + pub const MRDD = mmio(Address + 0x00000030, 32, packed struct { + READDATA: u16, // bit offset: 0 desc: READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 MII Mgmt Indicators register. + pub const MIND = mmio(Address + 0x00000034, 32, packed struct { + BUSY: bool, // bit offset: 0 desc: When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. + SCANNING: bool, // bit offset: 1 desc: When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. + NOTVALID: bool, // bit offset: 2 desc: When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. + MIILINKFAIL: bool, // bit offset: 3 desc: When 1 is returned - indicates that an MII Mgmt link fail has occurred. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 Station Address 0 register. + pub const SA0 = mmio(Address + 0x00000040, 32, packed struct { + SADDR2: u8, // bit offset: 0 desc: STATION ADDRESS, 2nd octet. This field holds the second octet of the station address. + SADDR1: u8, // bit offset: 8 desc: STATION ADDRESS, 1st octet. This field holds the first octet of the station address. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 Station Address 1 register. + pub const SA1 = mmio(Address + 0x00000044, 32, packed struct { + SADDR4: u8, // bit offset: 0 desc: STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address. + SADDR3: u8, // bit offset: 8 desc: STATION ADDRESS, 3rd octet. This field holds the third octet of the station address. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 Station Address 2 register. + pub const SA2 = mmio(Address + 0x00000048, 32, packed struct { + SADDR6: u8, // bit offset: 0 desc: STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address. + SADDR5: u8, // bit offset: 8 desc: STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 256 Command register. + pub const COMMAND = mmio(Address + 0x00000100, 32, packed struct { + RXENABLE: bool, // bit offset: 0 desc: Enable receive. + TXENABLE: bool, // bit offset: 1 desc: Enable transmit. + reserved1: u1 = 0, + REGRESET: bool, // bit offset: 3 desc: When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. + TXRESET: bool, // bit offset: 4 desc: When a 1 is written, the transmit datapath is reset. + RXRESET: bool, // bit offset: 5 desc: When a 1 is written, the receive datapath is reset. + PASSRUNTFRAME: bool, // bit offset: 6 desc: When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. + PASSRXFILTER: bool, // bit offset: 7 desc: When set to 1 , disables receive filtering i.e. all frames received are written to memory. + TXFLOWCONTROL: bool, // bit offset: 8 desc: Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. + RMII: bool, // bit offset: 9 desc: When set to 1 , RMII mode is selected; if 0, MII mode is selected. + FULLDUPLEX: bool, // bit offset: 10 desc: When set to 1 , indicates full duplex operation. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 260 Status register. + pub const STATUS = mmio(Address + 0x00000104, 32, packed struct { + RXSTATUS: bool, // bit offset: 0 desc: If 1, the receive channel is active. If 0, the receive channel is inactive. + TXSTATUS: bool, // bit offset: 1 desc: If 1, the transmit channel is active. If 0, the transmit channel is inactive. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 264 Receive descriptor base address register. + pub const RXDESCRIPTOR = mmio(Address + 0x00000108, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + RXDESCRIPTOR: u30, // bit offset: 2 desc: MSBs of receive descriptor base address. + }); + // byte offset: 268 Receive status base address register. + pub const RXSTATUS = mmio(Address + 0x0000010c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RXSTATUS: u29, // bit offset: 3 desc: MSBs of receive status base address. + }); + // byte offset: 272 Receive number of descriptors register. + pub const RXDESCRIPTORNUMBER = mmio(Address + 0x00000110, 32, packed struct { + RXDESCRIPTORN: u16, // bit offset: 0 desc: RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 276 Receive produce index register. + pub const RXPRODUCEINDEX = mmio(Address + 0x00000114, 32, packed struct { + RXPRODUCEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be filled next by the receive datapath. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 280 Receive consume index register. + pub const RXCONSUMEINDEX = mmio(Address + 0x00000118, 32, packed struct { + RXCONSUMEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be processed next by the receive + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 284 Transmit descriptor base address register. + pub const TXDESCRIPTOR = mmio(Address + 0x0000011c, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + TXD: u30, // bit offset: 2 desc: TxDescriptor. MSBs of transmit descriptor base address. + }); + // byte offset: 288 Transmit status base address register. + pub const TXSTATUS = mmio(Address + 0x00000120, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + TXSTAT: u30, // bit offset: 2 desc: TxStatus. MSBs of transmit status base address. + }); + // byte offset: 292 Transmit number of descriptors register. + pub const TXDESCRIPTORNUMBER = mmio(Address + 0x00000124, 32, packed struct { + TXDN: u16, // bit offset: 0 desc: TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 296 Transmit produce index register. + pub const TXPRODUCEINDEX = mmio(Address + 0x00000128, 32, packed struct { + TXPI: u16, // bit offset: 0 desc: TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 300 Transmit consume index register. + pub const TXCONSUMEINDEX = mmio(Address + 0x0000012c, 32, packed struct { + TXCI: u16, // bit offset: 0 desc: TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 344 Transmit status vector 0 register. + pub const TSV0 = mmio(Address + 0x00000158, 32, packed struct { + CRCERR: bool, // bit offset: 0 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. + LCE: bool, // bit offset: 1 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. + LOR: bool, // bit offset: 2 desc: Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. + DONE: bool, // bit offset: 3 desc: Transmission of packet was completed. + MULTICAST: bool, // bit offset: 4 desc: Packet's destination was a multicast address. + BROADCAST: bool, // bit offset: 5 desc: Packet's destination was a broadcast address. + PACKETDEFER: bool, // bit offset: 6 desc: Packet was deferred for at least one attempt, but less than an excessive defer. + EXDF: bool, // bit offset: 7 desc: Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. + EXCOL: bool, // bit offset: 8 desc: Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. + LCOL: bool, // bit offset: 9 desc: Late Collision. Collision occurred beyond collision window, 512 bit times. + GIANT: bool, // bit offset: 10 desc: Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. + UNDERRUN: bool, // bit offset: 11 desc: Host side caused buffer underrun. + TOTALBYTES: u16, // bit offset: 12 desc: The total number of bytes transferred including collided attempts. + CONTROLFRAME: bool, // bit offset: 28 desc: The frame was a control frame. + PAUSE: bool, // bit offset: 29 desc: The frame was a control frame with a valid PAUSE opcode. + BACKPRESSURE: bool, // bit offset: 30 desc: Carrier-sense method backpressure was previously applied. + VLAN: bool, // bit offset: 31 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. + }); + // byte offset: 348 Transmit status vector 1 register. + pub const TSV1 = mmio(Address + 0x0000015c, 32, packed struct { + TBC: u16, // bit offset: 0 desc: Transmit byte count. The total number of bytes in the frame, not counting the collided bytes. + TCC: u4, // bit offset: 16 desc: Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented. + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 352 Receive status vector register. + pub const RSV = mmio(Address + 0x00000160, 32, packed struct { + RBC: u16, // bit offset: 0 desc: Received byte count. Indicates length of received frame. + PPI: bool, // bit offset: 16 desc: Packet previously ignored. Indicates that a packet was dropped. + RXDVSEEN: bool, // bit offset: 17 desc: RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. + CESEEN: bool, // bit offset: 18 desc: Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. + RCV: bool, // bit offset: 19 desc: Receive code violation. Indicates that received PHY data does not represent a valid receive code. + CRCERR: bool, // bit offset: 20 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. + LCERR: bool, // bit offset: 21 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. + LOR: bool, // bit offset: 22 desc: Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. + ROK: bool, // bit offset: 23 desc: Receive OK. The packet had valid CRC and no symbol errors. + MULTICAST: bool, // bit offset: 24 desc: The packet destination was a multicast address. + BROADCAST: bool, // bit offset: 25 desc: The packet destination was a broadcast address. + DRIBBLENIBBLE: bool, // bit offset: 26 desc: Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. + CONTROLFRAME: bool, // bit offset: 27 desc: The frame was a control frame. + PAUSE: bool, // bit offset: 28 desc: The frame was a control frame with a valid PAUSE opcode. + UO: bool, // bit offset: 29 desc: Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. + VLAN: bool, // bit offset: 30 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. + padding1: u1 = 0, + }); + // byte offset: 368 Flow control counter register. + pub const FLOWCONTROLCOUNTER = mmio(Address + 0x00000170, 32, packed struct { + MC: u16, // bit offset: 0 desc: MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame. + PT: u16, // bit offset: 16 desc: PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. + }); + // byte offset: 372 Flow control status register. + pub const FLOWCONTROLSTATUS = mmio(Address + 0x00000174, 32, packed struct { + MCC: u16, // bit offset: 0 desc: MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 512 Receive filter control register. + pub const RXFILTERCTRL = mmio(Address + 0x00000200, 32, packed struct { + AUE: bool, // bit offset: 0 desc: AcceptUnicastEn. When set to 1, all unicast frames are accepted. + ABE: bool, // bit offset: 1 desc: AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. + AME: bool, // bit offset: 2 desc: AcceptMulticastEn. When set to 1, all multicast frames are accepted. + AUHE: bool, // bit offset: 3 desc: AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. + AMHE: bool, // bit offset: 4 desc: AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. + APE: bool, // bit offset: 5 desc: AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MPEW: bool, // bit offset: 12 desc: MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. + RFEW: bool, // bit offset: 13 desc: RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 516 Receive filter WoL status register. + pub const RXFILTERWOLSTATUS = mmio(Address + 0x00000204, 32, packed struct { + AUW: bool, // bit offset: 0 desc: AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. + ABW: bool, // bit offset: 1 desc: AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. + AMW: bool, // bit offset: 2 desc: AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. + AUHW: bool, // bit offset: 3 desc: AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. + AMHW: bool, // bit offset: 4 desc: AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. + APW: bool, // bit offset: 5 desc: AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. + reserved1: u1 = 0, + RFW: bool, // bit offset: 7 desc: RxFilterWoL. When the value is 1, the receive filter caused WoL. + MPW: bool, // bit offset: 8 desc: MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 520 Receive filter WoL clear register. + pub const RXFILTERWOLCLEAR = mmio(Address + 0x00000208, 32, packed struct { + AUWCLR: bool, // bit offset: 0 desc: AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + ABWCLR: bool, // bit offset: 1 desc: AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AMWCLR: bool, // bit offset: 2 desc: AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AUHWCLR: bool, // bit offset: 3 desc: AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AMHWCLR: bool, // bit offset: 4 desc: AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + APWCLR: bool, // bit offset: 5 desc: AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + reserved1: u1 = 0, + RFWCLR: bool, // bit offset: 7 desc: RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + MPWCLR: bool, // bit offset: 8 desc: MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 528 Hash filter table LSBs register. + pub const HASHFILTERL = mmio(Address + 0x00000210, 32, packed struct { + HFL: u32, // bit offset: 0 desc: HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. + }); + // byte offset: 532 Hash filter table MSBs register. + pub const HASHFILTERH = mmio(Address + 0x00000214, 32, packed struct { + HFH: u32, // bit offset: 0 desc: Bits 63:32 of the imperfect filter hash table for receive filtering. + }); + // byte offset: 4064 Interrupt status register. + pub const INTSTATUS = mmio(Address + 0x00000fe0, 32, packed struct { + RXOVERRUNINT: bool, // bit offset: 0 desc: Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. + RXERRORINT: bool, // bit offset: 1 desc: Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. + RXFINISHEDINT: bool, // bit offset: 2 desc: Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXDONEINT: bool, // bit offset: 3 desc: Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. + TXUNDERRUNINT: bool, // bit offset: 4 desc: Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. + TXERRORINT: bool, // bit offset: 5 desc: Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. + TXFINISHEDINT: bool, // bit offset: 6 desc: Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXDONEINT: bool, // bit offset: 7 desc: Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SOFTINT: bool, // bit offset: 12 desc: Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. + WAKEUPINT: bool, // bit offset: 13 desc: Interrupt triggered by a Wake-up event detected by the receive filter. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4068 Interrupt enable register. + pub const INTENABLE = mmio(Address + 0x00000fe4, 32, packed struct { + RXOVERRUNINTEN: bool, // bit offset: 0 desc: Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. + RXERRORINTEN: bool, // bit offset: 1 desc: Enable for interrupt trigger on receive errors. + RXFINISHEDINTEN: bool, // bit offset: 2 desc: Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXDONEINTEN: bool, // bit offset: 3 desc: Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. + TXUNDERRUNINTEN: bool, // bit offset: 4 desc: Enable for interrupt trigger on transmit buffer or descriptor underrun situations. + TXERRORINTEN: bool, // bit offset: 5 desc: Enable for interrupt trigger on transmit errors. + TXFINISHEDINTEN: bool, // bit offset: 6 desc: Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXDONEINTEN: bool, // bit offset: 7 desc: Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SOFTINTEN: bool, // bit offset: 12 desc: Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. + WAKEUPINTEN: bool, // bit offset: 13 desc: Enable for interrupt triggered by a Wake-up event detected by the receive filter. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4072 Interrupt clear register. + pub const INTCLEAR = mmio(Address + 0x00000fe8, 32, packed struct { + RXOVERRUNINTCLR: bool, // bit offset: 0 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXERRORINTCLR: bool, // bit offset: 1 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXFINISHEDINTCLR: bool, // bit offset: 2 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXDONEINTCLR: bool, // bit offset: 3 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXUNDERRUNINTCLR: bool, // bit offset: 4 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXERRORINTCLR: bool, // bit offset: 5 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXFINISHEDINTCLR: bool, // bit offset: 6 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXDONEINTCLR: bool, // bit offset: 7 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SOFTINTCLR: bool, // bit offset: 12 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + WAKEUPINTCLR: bool, // bit offset: 13 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4076 Interrupt set register. + pub const INTSET = mmio(Address + 0x00000fec, 32, packed struct { + RXOVERRUNINTSET: bool, // bit offset: 0 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXERRORINTSET: bool, // bit offset: 1 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXFINISHEDINTSET: bool, // bit offset: 2 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXDONEINTSET: bool, // bit offset: 3 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXUNDERRUNINTSET: bool, // bit offset: 4 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXERRORINTSET: bool, // bit offset: 5 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXFINISHEDINTSET: bool, // bit offset: 6 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXDONEINTSET: bool, // bit offset: 7 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SOFTINTSET: bool, // bit offset: 12 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + WAKEUPINTSET: bool, // bit offset: 13 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4084 Power-down register. + pub const POWERDOWN = mmio(Address + 0x00000ff4, 32, packed struct { + reserved31: u1 = 0, + reserved30: u1 = 0, + reserved29: u1 = 0, + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PD: bool, // bit offset: 31 desc: PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. + }); +}; +pub const GPDMA = extern struct { + pub const Address: u32 = 0x50004000; + // byte offset: 0 DMA Interrupt Status Register + pub const INTSTAT = mmio(Address + 0x00000000, 32, packed struct { + INTSTAT0: bool, // bit offset: 0 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT1: bool, // bit offset: 1 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT2: bool, // bit offset: 2 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT3: bool, // bit offset: 3 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT4: bool, // bit offset: 4 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT5: bool, // bit offset: 5 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT6: bool, // bit offset: 6 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT7: bool, // bit offset: 7 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA Interrupt Terminal Count Request Status Register + pub const INTTCSTAT = mmio(Address + 0x00000004, 32, packed struct { + INTTCSTAT0: bool, // bit offset: 0 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT1: bool, // bit offset: 1 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT2: bool, // bit offset: 2 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT3: bool, // bit offset: 3 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT4: bool, // bit offset: 4 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT5: bool, // bit offset: 5 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT6: bool, // bit offset: 6 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT7: bool, // bit offset: 7 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA Interrupt Terminal Count Request Clear Register + pub const INTTCCLEAR = mmio(Address + 0x00000008, 32, packed struct { + INTTCCLEAR0: bool, // bit offset: 0 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR1: bool, // bit offset: 1 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR2: bool, // bit offset: 2 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR3: bool, // bit offset: 3 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR4: bool, // bit offset: 4 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR5: bool, // bit offset: 5 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR6: bool, // bit offset: 6 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR7: bool, // bit offset: 7 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA Interrupt Error Status Register + pub const INTERRSTAT = mmio(Address + 0x0000000c, 32, packed struct { + INTERRSTAT0: bool, // bit offset: 0 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT1: bool, // bit offset: 1 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT2: bool, // bit offset: 2 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT3: bool, // bit offset: 3 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT4: bool, // bit offset: 4 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT5: bool, // bit offset: 5 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT6: bool, // bit offset: 6 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT7: bool, // bit offset: 7 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DMA Interrupt Error Clear Register + pub const INTERRCLR = mmio(Address + 0x00000010, 32, packed struct { + INTERRCLR0: bool, // bit offset: 0 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR1: bool, // bit offset: 1 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR2: bool, // bit offset: 2 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR3: bool, // bit offset: 3 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR4: bool, // bit offset: 4 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR5: bool, // bit offset: 5 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR6: bool, // bit offset: 6 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR7: bool, // bit offset: 7 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 DMA Raw Interrupt Terminal Count Status Register + pub const RAWINTTCSTAT = mmio(Address + 0x00000014, 32, packed struct { + RAWINTTCSTAT0: bool, // bit offset: 0 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT1: bool, // bit offset: 1 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT2: bool, // bit offset: 2 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT3: bool, // bit offset: 3 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT4: bool, // bit offset: 4 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT5: bool, // bit offset: 5 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT6: bool, // bit offset: 6 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT7: bool, // bit offset: 7 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 DMA Raw Error Interrupt Status Register + pub const RAWINTERRSTAT = mmio(Address + 0x00000018, 32, packed struct { + RAWINTERRSTAT0: bool, // bit offset: 0 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT1: bool, // bit offset: 1 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT2: bool, // bit offset: 2 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT3: bool, // bit offset: 3 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT4: bool, // bit offset: 4 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT5: bool, // bit offset: 5 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT6: bool, // bit offset: 6 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT7: bool, // bit offset: 7 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 DMA Enabled Channel Register + pub const ENBLDCHNS = mmio(Address + 0x0000001c, 32, packed struct { + ENABLEDCHANNELS0: bool, // bit offset: 0 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS1: bool, // bit offset: 1 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS2: bool, // bit offset: 2 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS3: bool, // bit offset: 3 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS4: bool, // bit offset: 4 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS5: bool, // bit offset: 5 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS6: bool, // bit offset: 6 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS7: bool, // bit offset: 7 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 DMA Software Burst Request Register + pub const SOFTBREQ = mmio(Address + 0x00000020, 32, packed struct { + SOFTBREQ0: bool, // bit offset: 0 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ1: bool, // bit offset: 1 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ2: bool, // bit offset: 2 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ3: bool, // bit offset: 3 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ4: bool, // bit offset: 4 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ5: bool, // bit offset: 5 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ6: bool, // bit offset: 6 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ7: bool, // bit offset: 7 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ8: bool, // bit offset: 8 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ9: bool, // bit offset: 9 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ10: bool, // bit offset: 10 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ11: bool, // bit offset: 11 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ12: bool, // bit offset: 12 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ13: bool, // bit offset: 13 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ14: bool, // bit offset: 14 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ15: bool, // bit offset: 15 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DMA Software Single Request Register + pub const SOFTSREQ = mmio(Address + 0x00000024, 32, packed struct { + SOFTSREQ0: bool, // bit offset: 0 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ1: bool, // bit offset: 1 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ2: bool, // bit offset: 2 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ3: bool, // bit offset: 3 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ4: bool, // bit offset: 4 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ5: bool, // bit offset: 5 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ6: bool, // bit offset: 6 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ7: bool, // bit offset: 7 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ8: bool, // bit offset: 8 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ9: bool, // bit offset: 9 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ10: bool, // bit offset: 10 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ11: bool, // bit offset: 11 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ12: bool, // bit offset: 12 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ13: bool, // bit offset: 13 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ14: bool, // bit offset: 14 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ15: bool, // bit offset: 15 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 DMA Software Last Burst Request Register + pub const SOFTLBREQ = mmio(Address + 0x00000028, 32, packed struct { + SOFTLBREQ0: bool, // bit offset: 0 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ1: bool, // bit offset: 1 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ2: bool, // bit offset: 2 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ3: bool, // bit offset: 3 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ4: bool, // bit offset: 4 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ5: bool, // bit offset: 5 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ6: bool, // bit offset: 6 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ7: bool, // bit offset: 7 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ8: bool, // bit offset: 8 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ9: bool, // bit offset: 9 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ10: bool, // bit offset: 10 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ11: bool, // bit offset: 11 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ12: bool, // bit offset: 12 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ13: bool, // bit offset: 13 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ14: bool, // bit offset: 14 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ15: bool, // bit offset: 15 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 DMA Software Last Single Request Register + pub const SOFTLSREQ = mmio(Address + 0x0000002c, 32, packed struct { + SOFTLSREQ0: bool, // bit offset: 0 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ1: bool, // bit offset: 1 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ2: bool, // bit offset: 2 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ3: bool, // bit offset: 3 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ4: bool, // bit offset: 4 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ5: bool, // bit offset: 5 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ6: bool, // bit offset: 6 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ7: bool, // bit offset: 7 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ8: bool, // bit offset: 8 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ9: bool, // bit offset: 9 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ10: bool, // bit offset: 10 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ11: bool, // bit offset: 11 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ12: bool, // bit offset: 12 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ13: bool, // bit offset: 13 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ14: bool, // bit offset: 14 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ15: bool, // bit offset: 15 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 DMA Configuration Register + pub const CONFIG = mmio(Address + 0x00000030, 32, packed struct { + E: bool, // bit offset: 0 desc: DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. + M: bool, // bit offset: 1 desc: AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 DMA Synchronization Register + pub const SYNC = mmio(Address + 0x00000034, 32, packed struct { + DMACSYNC0: bool, // bit offset: 0 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC1: bool, // bit offset: 1 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC2: bool, // bit offset: 2 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC3: bool, // bit offset: 3 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC4: bool, // bit offset: 4 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC5: bool, // bit offset: 5 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC6: bool, // bit offset: 6 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC7: bool, // bit offset: 7 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC8: bool, // bit offset: 8 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC9: bool, // bit offset: 9 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC10: bool, // bit offset: 10 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC11: bool, // bit offset: 11 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC12: bool, // bit offset: 12 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC13: bool, // bit offset: 13 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC14: bool, // bit offset: 14 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC15: bool, // bit offset: 15 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 256 DMA Channel 0 Source Address Register + pub const SRCADDR0 = mmio(Address + 0x00000100, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 260 DMA Channel 0 Destination Address Register + pub const DESTADDR0 = mmio(Address + 0x00000104, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 264 DMA Channel 0 Linked List Item Register + pub const LLI0 = mmio(Address + 0x00000108, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 268 DMA Channel 0 Control Register + pub const CONTROL0 = mmio(Address + 0x0000010c, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 272 DMA Channel 0 Configuration Register[1] + pub const CONFIG0 = mmio(Address + 0x00000110, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 288 DMA Channel 0 Source Address Register + pub const SRCADDR1 = mmio(Address + 0x00000120, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 292 DMA Channel 0 Destination Address Register + pub const DESTADDR1 = mmio(Address + 0x00000124, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 296 DMA Channel 0 Linked List Item Register + pub const LLI1 = mmio(Address + 0x00000128, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 300 DMA Channel 0 Control Register + pub const CONTROL1 = mmio(Address + 0x0000012c, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 304 DMA Channel 0 Configuration Register[1] + pub const CONFIG1 = mmio(Address + 0x00000130, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 320 DMA Channel 0 Source Address Register + pub const SRCADDR2 = mmio(Address + 0x00000140, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 324 DMA Channel 0 Destination Address Register + pub const DESTADDR2 = mmio(Address + 0x00000144, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 328 DMA Channel 0 Linked List Item Register + pub const LLI2 = mmio(Address + 0x00000148, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 332 DMA Channel 0 Control Register + pub const CONTROL2 = mmio(Address + 0x0000014c, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 336 DMA Channel 0 Configuration Register[1] + pub const CONFIG2 = mmio(Address + 0x00000150, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 352 DMA Channel 0 Source Address Register + pub const SRCADDR3 = mmio(Address + 0x00000160, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 356 DMA Channel 0 Destination Address Register + pub const DESTADDR3 = mmio(Address + 0x00000164, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 360 DMA Channel 0 Linked List Item Register + pub const LLI3 = mmio(Address + 0x00000168, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 364 DMA Channel 0 Control Register + pub const CONTROL3 = mmio(Address + 0x0000016c, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 368 DMA Channel 0 Configuration Register[1] + pub const CONFIG3 = mmio(Address + 0x00000170, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 384 DMA Channel 0 Source Address Register + pub const SRCADDR4 = mmio(Address + 0x00000180, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 388 DMA Channel 0 Destination Address Register + pub const DESTADDR4 = mmio(Address + 0x00000184, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 392 DMA Channel 0 Linked List Item Register + pub const LLI4 = mmio(Address + 0x00000188, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 396 DMA Channel 0 Control Register + pub const CONTROL4 = mmio(Address + 0x0000018c, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 400 DMA Channel 0 Configuration Register[1] + pub const CONFIG4 = mmio(Address + 0x00000190, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 416 DMA Channel 0 Source Address Register + pub const SRCADDR5 = mmio(Address + 0x000001a0, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 420 DMA Channel 0 Destination Address Register + pub const DESTADDR5 = mmio(Address + 0x000001a4, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 424 DMA Channel 0 Linked List Item Register + pub const LLI5 = mmio(Address + 0x000001a8, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 428 DMA Channel 0 Control Register + pub const CONTROL5 = mmio(Address + 0x000001ac, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 432 DMA Channel 0 Configuration Register[1] + pub const CONFIG5 = mmio(Address + 0x000001b0, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 448 DMA Channel 0 Source Address Register + pub const SRCADDR6 = mmio(Address + 0x000001c0, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 452 DMA Channel 0 Destination Address Register + pub const DESTADDR6 = mmio(Address + 0x000001c4, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 456 DMA Channel 0 Linked List Item Register + pub const LLI6 = mmio(Address + 0x000001c8, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 460 DMA Channel 0 Control Register + pub const CONTROL6 = mmio(Address + 0x000001cc, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 464 DMA Channel 0 Configuration Register[1] + pub const CONFIG6 = mmio(Address + 0x000001d0, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); + // byte offset: 480 DMA Channel 0 Source Address Register + pub const SRCADDR7 = mmio(Address + 0x000001e0, 32, packed struct { + SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. + }); + // byte offset: 484 DMA Channel 0 Destination Address Register + pub const DESTADDR7 = mmio(Address + 0x000001e4, 32, packed struct { + DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. + }); + // byte offset: 488 DMA Channel 0 Linked List Item Register + pub const LLI7 = mmio(Address + 0x000001e8, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. + }); + // byte offset: 492 DMA Channel 0 Control Register + pub const CONTROL7 = mmio(Address + 0x000001ec, 32, packed struct { + TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. + SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + reserved2: u1 = 0, + reserved1: u1 = 0, + SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + }); + // byte offset: 496 DMA Channel 0 Configuration Register[1] + pub const CONFIG7 = mmio(Address + 0x000001f0, 32, packed struct { + E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. + TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. + IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + }); +}; +pub const USB = extern struct { + pub const Address: u32 = 0x50008000; + // byte offset: 220 USB Receive Packet Length + pub const RXPLEN = mmio(Address + 0x000000dc, 32, packed struct { + PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. + DV: bool, // bit offset: 10 desc: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. + PKT_RDY: bool, // bit offset: 11 desc: The PKT_LNGTH field is valid and the packet is ready for reading. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 256 OTG Interrupt Status + pub const INTST = mmio(Address + 0x00000100, 32, packed struct { + TMR: bool, // bit offset: 0 desc: Timer time-out. + REMOVE_PU: bool, // bit offset: 1 desc: Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. + HNP_FAILURE: bool, // bit offset: 2 desc: HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. + HNP_SUCCESS: bool, // bit offset: 3 desc: HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 260 OTG Interrupt Enable + pub const INTEN = mmio(Address + 0x00000104, 32, packed struct { + TMR_EN: bool, // bit offset: 0 desc: 1 = enable the corresponding bit in the IntSt register. + REMOVE_PU_EN: bool, // bit offset: 1 desc: 1 = enable the corresponding bit in the IntSt register. + HNP_FAILURE_EN: bool, // bit offset: 2 desc: 1 = enable the corresponding bit in the IntSt register. + HNP_SUCCES_EN: bool, // bit offset: 3 desc: 1 = enable the corresponding bit in the IntSt register. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 264 OTG Interrupt Set + pub const INTSET = mmio(Address + 0x00000108, 32, packed struct { + TMR_SET: bool, // bit offset: 0 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + REMOVE_PU_SET: bool, // bit offset: 1 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_FAILURE_SET: bool, // bit offset: 2 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_SUCCES_SET: bool, // bit offset: 3 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 268 OTG Interrupt Clear + pub const INTCLR = mmio(Address + 0x0000010c, 32, packed struct { + TMR_CLR: bool, // bit offset: 0 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + REMOVE_PU_CLR: bool, // bit offset: 1 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_FAILURE_CLR: bool, // bit offset: 2 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_SUCCES_CLR: bool, // bit offset: 3 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 272 OTG Status and Control and USB port select + pub const STCTRL = mmio(Address + 0x00000110, 32, packed struct { + PORT_FUNC: u2, // bit offset: 0 desc: Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. + TMR_SCALE: u2, // bit offset: 2 desc: Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved + TMR_MODE: bool, // bit offset: 4 desc: Timer mode selection. 0: monoshot 1: free running + TMR_EN: bool, // bit offset: 5 desc: Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. + TMR_RST: bool, // bit offset: 6 desc: Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. + reserved1: u1 = 0, + B_HNP_TRACK: bool, // bit offset: 8 desc: Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + A_HNP_TRACK: bool, // bit offset: 9 desc: Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + PU_REMOVED: bool, // bit offset: 10 desc: When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TMR_CNT: u16, // bit offset: 16 desc: Current timer count value. + }); + // byte offset: 276 OTG Timer + pub const TMR = mmio(Address + 0x00000114, 32, packed struct { + TIMEOUT_CNT: u16, // bit offset: 0 desc: The TMR interrupt is set when TMR_CNT reaches this value. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 512 USB Device Interrupt Status + pub const DEVINTST = mmio(Address + 0x00000200, 32, packed struct { + FRAME: bool, // bit offset: 0 desc: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. + EP_FAST: bool, // bit offset: 1 desc: Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. + EP_SLOW: bool, // bit offset: 2 desc: Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. + DEV_STAT: bool, // bit offset: 3 desc: Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. + CCEMPTY: bool, // bit offset: 4 desc: The command code register (USBCmdCode) is empty (New command can be written). + CDFULL: bool, // bit offset: 5 desc: Command data register (USBCmdData) is full (Data can be read now). + RxENDPKT: bool, // bit offset: 6 desc: The current packet in the endpoint buffer is transferred to the CPU. + TxENDPKT: bool, // bit offset: 7 desc: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). + EP_RLZED: bool, // bit offset: 8 desc: Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. + ERR_INT: bool, // bit offset: 9 desc: Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 516 USB Device Interrupt Enable + pub const DEVINTEN = mmio(Address + 0x00000204, 32, packed struct { + FRAMEEN: bool, // bit offset: 0 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_FASTEN: bool, // bit offset: 1 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_SLOWEN: bool, // bit offset: 2 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + DEV_STATEN: bool, // bit offset: 3 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CCEMPTYEN: bool, // bit offset: 4 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CDFULLEN: bool, // bit offset: 5 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + RxENDPKTEN: bool, // bit offset: 6 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + TxENDPKTEN: bool, // bit offset: 7 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_RLZEDEN: bool, // bit offset: 8 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + ERR_INTEN: bool, // bit offset: 9 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 520 USB Device Interrupt Clear + pub const DEVINTCLR = mmio(Address + 0x00000208, 32, packed struct { + FRAMECLR: bool, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_FASTCLR: bool, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_SLOWCLR: bool, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + DEV_STATCLR: bool, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + CCEMPTYCLR: bool, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + CDFULLCLR: bool, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + RxENDPKTCLR: bool, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + TxENDPKTCLR: bool, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_RLZEDCLR: bool, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + ERR_INTCLR: bool, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 524 USB Device Interrupt Set + pub const DEVINTSET = mmio(Address + 0x0000020c, 32, packed struct { + FRAMESET: bool, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_FASTSET: bool, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_SLOWSET: bool, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + DEV_STATSET: bool, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + CCEMPTYSET: bool, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + CDFULLSET: bool, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + RxENDPKTSET: bool, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + TxENDPKTSET: bool, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_RLZEDSET: bool, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + ERR_INTSET: bool, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 528 USB Command Code + pub const CMDCODE = mmio(Address + 0x00000210, 32, packed struct { + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CMD_PHASE: u8, // bit offset: 8 desc: The command phase: + CMD_CODE_WDATA: u8, // bit offset: 16 desc: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 532 USB Command Data + pub const CMDDATA = mmio(Address + 0x00000214, 32, packed struct { + CMD_RDATA: u8, // bit offset: 0 desc: Command Read Data. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 536 USB Receive Data + pub const RXDATA = mmio(Address + 0x00000218, 32, packed struct { + RX_DATA: u32, // bit offset: 0 desc: Data received. + }); + // byte offset: 540 USB Transmit Data + pub const TXDATA = mmio(Address + 0x0000021c, 32, packed struct { + TX_DATA: u32, // bit offset: 0 desc: Transmit Data. + }); + // byte offset: 548 USB Transmit Packet Length + pub const TXPLEN = mmio(Address + 0x00000224, 32, packed struct { + PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 552 USB Control + pub const CTRL = mmio(Address + 0x00000228, 32, packed struct { + RD_EN: bool, // bit offset: 0 desc: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. + WR_EN: bool, // bit offset: 1 desc: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. + LOG_ENDPOINT: u4, // bit offset: 2 desc: Logical Endpoint number. + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 556 USB Device Interrupt Priority + pub const DEVINTPRI = mmio(Address + 0x0000022c, 32, packed struct { + FRAME: bool, // bit offset: 0 desc: Frame interrupt routing + EP_FAST: bool, // bit offset: 1 desc: Fast endpoint interrupt routing + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 560 USB Endpoint Interrupt Status + pub const EPINTST = mmio(Address + 0x00000230, 32, packed struct { + EPST0: bool, // bit offset: 0 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST1: bool, // bit offset: 1 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST2: bool, // bit offset: 2 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST3: bool, // bit offset: 3 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST4: bool, // bit offset: 4 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST5: bool, // bit offset: 5 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST6: bool, // bit offset: 6 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST7: bool, // bit offset: 7 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST8: bool, // bit offset: 8 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST9: bool, // bit offset: 9 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST10: bool, // bit offset: 10 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST11: bool, // bit offset: 11 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST12: bool, // bit offset: 12 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST13: bool, // bit offset: 13 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST14: bool, // bit offset: 14 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST15: bool, // bit offset: 15 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST16: bool, // bit offset: 16 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST17: bool, // bit offset: 17 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST18: bool, // bit offset: 18 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST19: bool, // bit offset: 19 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST20: bool, // bit offset: 20 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST21: bool, // bit offset: 21 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST22: bool, // bit offset: 22 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST23: bool, // bit offset: 23 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST24: bool, // bit offset: 24 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST25: bool, // bit offset: 25 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST26: bool, // bit offset: 26 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST27: bool, // bit offset: 27 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST28: bool, // bit offset: 28 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST29: bool, // bit offset: 29 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST30: bool, // bit offset: 30 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST31: bool, // bit offset: 31 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + }); + // byte offset: 564 USB Endpoint Interrupt Enable + pub const EPINTEN = mmio(Address + 0x00000234, 32, packed struct { + EPEN0: bool, // bit offset: 0 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN1: bool, // bit offset: 1 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN2: bool, // bit offset: 2 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN3: bool, // bit offset: 3 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN4: bool, // bit offset: 4 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN5: bool, // bit offset: 5 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN6: bool, // bit offset: 6 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN7: bool, // bit offset: 7 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN8: bool, // bit offset: 8 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN9: bool, // bit offset: 9 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN10: bool, // bit offset: 10 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN11: bool, // bit offset: 11 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN12: bool, // bit offset: 12 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN13: bool, // bit offset: 13 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN14: bool, // bit offset: 14 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN15: bool, // bit offset: 15 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN16: bool, // bit offset: 16 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN17: bool, // bit offset: 17 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN18: bool, // bit offset: 18 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN19: bool, // bit offset: 19 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN20: bool, // bit offset: 20 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN21: bool, // bit offset: 21 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN22: bool, // bit offset: 22 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN23: bool, // bit offset: 23 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN24: bool, // bit offset: 24 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN25: bool, // bit offset: 25 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN26: bool, // bit offset: 26 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN27: bool, // bit offset: 27 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN28: bool, // bit offset: 28 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN29: bool, // bit offset: 29 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN30: bool, // bit offset: 30 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN31: bool, // bit offset: 31 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + }); + // byte offset: 568 USB Endpoint Interrupt Clear + pub const EPINTCLR = mmio(Address + 0x00000238, 32, packed struct { + EPCLR0: bool, // bit offset: 0 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR1: bool, // bit offset: 1 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR2: bool, // bit offset: 2 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR3: bool, // bit offset: 3 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR4: bool, // bit offset: 4 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR5: bool, // bit offset: 5 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR6: bool, // bit offset: 6 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR7: bool, // bit offset: 7 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR8: bool, // bit offset: 8 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR9: bool, // bit offset: 9 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR10: bool, // bit offset: 10 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR11: bool, // bit offset: 11 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR12: bool, // bit offset: 12 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR13: bool, // bit offset: 13 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR14: bool, // bit offset: 14 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR15: bool, // bit offset: 15 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR16: bool, // bit offset: 16 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR17: bool, // bit offset: 17 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR18: bool, // bit offset: 18 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR19: bool, // bit offset: 19 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR20: bool, // bit offset: 20 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR21: bool, // bit offset: 21 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR22: bool, // bit offset: 22 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR23: bool, // bit offset: 23 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR24: bool, // bit offset: 24 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR25: bool, // bit offset: 25 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR26: bool, // bit offset: 26 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR27: bool, // bit offset: 27 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR28: bool, // bit offset: 28 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR29: bool, // bit offset: 29 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR30: bool, // bit offset: 30 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR31: bool, // bit offset: 31 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + }); + // byte offset: 572 USB Endpoint Interrupt Set + pub const EPINTSET = mmio(Address + 0x0000023c, 32, packed struct { + EPSET0: bool, // bit offset: 0 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET1: bool, // bit offset: 1 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET2: bool, // bit offset: 2 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET3: bool, // bit offset: 3 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET4: bool, // bit offset: 4 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET5: bool, // bit offset: 5 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET6: bool, // bit offset: 6 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET7: bool, // bit offset: 7 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET8: bool, // bit offset: 8 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET9: bool, // bit offset: 9 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET10: bool, // bit offset: 10 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET11: bool, // bit offset: 11 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET12: bool, // bit offset: 12 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET13: bool, // bit offset: 13 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET14: bool, // bit offset: 14 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET15: bool, // bit offset: 15 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET16: bool, // bit offset: 16 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET17: bool, // bit offset: 17 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET18: bool, // bit offset: 18 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET19: bool, // bit offset: 19 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET20: bool, // bit offset: 20 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET21: bool, // bit offset: 21 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET22: bool, // bit offset: 22 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET23: bool, // bit offset: 23 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET24: bool, // bit offset: 24 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET25: bool, // bit offset: 25 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET26: bool, // bit offset: 26 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET27: bool, // bit offset: 27 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET28: bool, // bit offset: 28 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET29: bool, // bit offset: 29 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET30: bool, // bit offset: 30 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET31: bool, // bit offset: 31 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + }); + // byte offset: 576 USB Endpoint Priority + pub const EPINTPRI = mmio(Address + 0x00000240, 32, packed struct { + EPPRI0: bool, // bit offset: 0 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI1: bool, // bit offset: 1 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI2: bool, // bit offset: 2 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI3: bool, // bit offset: 3 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI4: bool, // bit offset: 4 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI5: bool, // bit offset: 5 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI6: bool, // bit offset: 6 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI7: bool, // bit offset: 7 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI8: bool, // bit offset: 8 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI9: bool, // bit offset: 9 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI10: bool, // bit offset: 10 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI11: bool, // bit offset: 11 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI12: bool, // bit offset: 12 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI13: bool, // bit offset: 13 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI14: bool, // bit offset: 14 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI15: bool, // bit offset: 15 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI16: bool, // bit offset: 16 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI17: bool, // bit offset: 17 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI18: bool, // bit offset: 18 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI19: bool, // bit offset: 19 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI20: bool, // bit offset: 20 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI21: bool, // bit offset: 21 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI22: bool, // bit offset: 22 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI23: bool, // bit offset: 23 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI24: bool, // bit offset: 24 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI25: bool, // bit offset: 25 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI26: bool, // bit offset: 26 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI27: bool, // bit offset: 27 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI28: bool, // bit offset: 28 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI29: bool, // bit offset: 29 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI30: bool, // bit offset: 30 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI31: bool, // bit offset: 31 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + }); + // byte offset: 580 USB Realize Endpoint + pub const REEP = mmio(Address + 0x00000244, 32, packed struct { + EPR0: bool, // bit offset: 0 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR1: bool, // bit offset: 1 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR2: bool, // bit offset: 2 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR3: bool, // bit offset: 3 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR4: bool, // bit offset: 4 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR5: bool, // bit offset: 5 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR6: bool, // bit offset: 6 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR7: bool, // bit offset: 7 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR8: bool, // bit offset: 8 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR9: bool, // bit offset: 9 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR10: bool, // bit offset: 10 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR11: bool, // bit offset: 11 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR12: bool, // bit offset: 12 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR13: bool, // bit offset: 13 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR14: bool, // bit offset: 14 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR15: bool, // bit offset: 15 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR16: bool, // bit offset: 16 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR17: bool, // bit offset: 17 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR18: bool, // bit offset: 18 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR19: bool, // bit offset: 19 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR20: bool, // bit offset: 20 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR21: bool, // bit offset: 21 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR22: bool, // bit offset: 22 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR23: bool, // bit offset: 23 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR24: bool, // bit offset: 24 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR25: bool, // bit offset: 25 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR26: bool, // bit offset: 26 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR27: bool, // bit offset: 27 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR28: bool, // bit offset: 28 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR29: bool, // bit offset: 29 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR30: bool, // bit offset: 30 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR31: bool, // bit offset: 31 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + }); + // byte offset: 584 USB Endpoint Index + pub const EPIND = mmio(Address + 0x00000248, 32, packed struct { + PHY_EP: u5, // bit offset: 0 desc: Physical endpoint number (0-31) + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 588 USB MaxPacketSize + pub const MAXPSIZE = mmio(Address + 0x0000024c, 32, packed struct { + MPS: u10, // bit offset: 0 desc: The maximum packet size value. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 592 USB DMA Request Status + pub const DMARST = mmio(Address + 0x00000250, 32, packed struct { + EPRST0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). + EPRST1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). + EPRST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + }); + // byte offset: 596 USB DMA Request Clear + pub const DMARCLR = mmio(Address + 0x00000254, 32, packed struct { + EPRCLR0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). + EPRCLR1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). + EPRCLR2: bool, // bit offset: 2 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR3: bool, // bit offset: 3 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR4: bool, // bit offset: 4 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR5: bool, // bit offset: 5 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR6: bool, // bit offset: 6 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR7: bool, // bit offset: 7 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR8: bool, // bit offset: 8 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR9: bool, // bit offset: 9 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR10: bool, // bit offset: 10 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR11: bool, // bit offset: 11 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR12: bool, // bit offset: 12 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR13: bool, // bit offset: 13 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR14: bool, // bit offset: 14 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR15: bool, // bit offset: 15 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR16: bool, // bit offset: 16 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR17: bool, // bit offset: 17 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR18: bool, // bit offset: 18 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR19: bool, // bit offset: 19 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR20: bool, // bit offset: 20 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR21: bool, // bit offset: 21 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR22: bool, // bit offset: 22 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR23: bool, // bit offset: 23 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR24: bool, // bit offset: 24 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR25: bool, // bit offset: 25 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR26: bool, // bit offset: 26 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR27: bool, // bit offset: 27 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR28: bool, // bit offset: 28 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR29: bool, // bit offset: 29 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR30: bool, // bit offset: 30 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR31: bool, // bit offset: 31 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + }); + // byte offset: 600 USB DMA Request Set + pub const DMARSET = mmio(Address + 0x00000258, 32, packed struct { + EPRSET0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). + EPRSET1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). + EPRSET2: bool, // bit offset: 2 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET3: bool, // bit offset: 3 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET4: bool, // bit offset: 4 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET5: bool, // bit offset: 5 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET6: bool, // bit offset: 6 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET7: bool, // bit offset: 7 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET8: bool, // bit offset: 8 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET9: bool, // bit offset: 9 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET10: bool, // bit offset: 10 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET11: bool, // bit offset: 11 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET12: bool, // bit offset: 12 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET13: bool, // bit offset: 13 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET14: bool, // bit offset: 14 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET15: bool, // bit offset: 15 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET16: bool, // bit offset: 16 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET17: bool, // bit offset: 17 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET18: bool, // bit offset: 18 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET19: bool, // bit offset: 19 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET20: bool, // bit offset: 20 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET21: bool, // bit offset: 21 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET22: bool, // bit offset: 22 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET23: bool, // bit offset: 23 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET24: bool, // bit offset: 24 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET25: bool, // bit offset: 25 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET26: bool, // bit offset: 26 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET27: bool, // bit offset: 27 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET28: bool, // bit offset: 28 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET29: bool, // bit offset: 29 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET30: bool, // bit offset: 30 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET31: bool, // bit offset: 31 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + }); + // byte offset: 640 USB UDCA Head + pub const UDCAH = mmio(Address + 0x00000280, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UDCA_ADDR: u25, // bit offset: 7 desc: Start address of the UDCA. + }); + // byte offset: 644 USB Endpoint DMA Status + pub const EPDMAST = mmio(Address + 0x00000284, 32, packed struct { + EP_DMA_ST0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). + EP_DMA_ST1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). + EP_DMA_ST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + }); + // byte offset: 648 USB Endpoint DMA Enable + pub const EPDMAEN = mmio(Address + 0x00000288, 32, packed struct { + EP_DMA_EN0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). + EP_DMA_EN1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). + EP_DMA_EN: u30, // bit offset: 2 desc: Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx. + }); + // byte offset: 652 USB Endpoint DMA Disable + pub const EPDMADIS = mmio(Address + 0x0000028c, 32, packed struct { + EP_DMA_DIS0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). + EP_DMA_DIS1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). + EP_DMA_DIS2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + }); + // byte offset: 656 USB DMA Interrupt Status + pub const DMAINTST = mmio(Address + 0x00000290, 32, packed struct { + EOT: bool, // bit offset: 0 desc: End of Transfer Interrupt bit. + NDDR: bool, // bit offset: 1 desc: New DD Request Interrupt bit. + ERR: bool, // bit offset: 2 desc: System Error Interrupt bit. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 660 USB DMA Interrupt Enable + pub const DMAINTEN = mmio(Address + 0x00000294, 32, packed struct { + EOT: bool, // bit offset: 0 desc: End of Transfer Interrupt enable bit. + NDDR: bool, // bit offset: 1 desc: New DD Request Interrupt enable bit. + ERR: bool, // bit offset: 2 desc: System Error Interrupt enable bit. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 672 USB End of Transfer Interrupt Status + pub const EOTINTST = mmio(Address + 0x000002a0, 32, packed struct { + EPTXINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + }); + // byte offset: 676 USB End of Transfer Interrupt Clear + pub const EOTINTCLR = mmio(Address + 0x000002a4, 32, packed struct { + EPTXINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + }); + // byte offset: 680 USB End of Transfer Interrupt Set + pub const EOTINTSET = mmio(Address + 0x000002a8, 32, packed struct { + EPTXINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + }); + // byte offset: 684 USB New DD Request Interrupt Status + pub const NDDRINTST = mmio(Address + 0x000002ac, 32, packed struct { + EPNDDINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + }); + // byte offset: 688 USB New DD Request Interrupt Clear + pub const NDDRINTCLR = mmio(Address + 0x000002b0, 32, packed struct { + EPNDDINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + }); + // byte offset: 692 USB New DD Request Interrupt Set + pub const NDDRINTSET = mmio(Address + 0x000002b4, 32, packed struct { + EPNDDINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + }); + // byte offset: 696 USB System Error Interrupt Status + pub const SYSERRINTST = mmio(Address + 0x000002b8, 32, packed struct { + EPERRINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + }); + // byte offset: 700 USB System Error Interrupt Clear + pub const SYSERRINTCLR = mmio(Address + 0x000002bc, 32, packed struct { + EPERRINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + }); + // byte offset: 704 USB System Error Interrupt Set + pub const SYSERRINTSET = mmio(Address + 0x000002c0, 32, packed struct { + EPERRINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + }); + // byte offset: 768 I2C Receive + pub const I2C_RX = mmio(Address + 0x00000300, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: Receive data. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 768 I2C Transmit + pub const I2C_WO = mmio(Address + 0x00000300, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: Transmit data. + START: bool, // bit offset: 8 desc: When 1, issue a START condition before transmitting this byte. + STOP: bool, // bit offset: 9 desc: When 1, issue a STOP condition after transmitting this byte. + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 772 I2C Status + pub const I2C_STS = mmio(Address + 0x00000304, 32, packed struct { + TDI: bool, // bit offset: 0 desc: Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. + AFI: bool, // bit offset: 1 desc: Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. + NAI: bool, // bit offset: 2 desc: No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. + DRMI: bool, // bit offset: 3 desc: Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. + DRSI: bool, // bit offset: 4 desc: Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. + Active: bool, // bit offset: 5 desc: Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. + SCL: bool, // bit offset: 6 desc: The current value of the SCL signal. + SDA: bool, // bit offset: 7 desc: The current value of the SDA signal. + RFF: bool, // bit offset: 8 desc: Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. + RFE: bool, // bit offset: 9 desc: Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. + TFF: bool, // bit offset: 10 desc: Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. + TFE: bool, // bit offset: 11 desc: Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 776 I2C Control + pub const I2C_CTL = mmio(Address + 0x00000308, 32, packed struct { + TDIE: bool, // bit offset: 0 desc: Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. + AFIE: bool, // bit offset: 1 desc: Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. + NAIE: bool, // bit offset: 2 desc: Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. + DRMIE: bool, // bit offset: 3 desc: Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. + DRSIE: bool, // bit offset: 4 desc: Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. + REFIE: bool, // bit offset: 5 desc: Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. + RFDAIE: bool, // bit offset: 6 desc: Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). + TFFIE: bool, // bit offset: 7 desc: Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. + SRST: bool, // bit offset: 8 desc: Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 780 I2C Clock High + pub const I2C_CLKHI = mmio(Address + 0x0000030c, 32, packed struct { + CDHI: u8, // bit offset: 0 desc: Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 784 I2C Clock Low + pub const I2C_CLKLO = mmio(Address + 0x00000310, 32, packed struct { + CDLO: u8, // bit offset: 0 desc: Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4084 USB Clock Control + pub const USBCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { + reserved1: u1 = 0, + DEV_CLK_EN: bool, // bit offset: 1 desc: Device clock enable. Enables the usbclk input to the device controller + reserved2: u1 = 0, + PORTSEL_CLK_EN: bool, // bit offset: 3 desc: Port select register clock enable. + AHB_CLK_EN: bool, // bit offset: 4 desc: AHB clock enable + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4084 OTG clock controller + pub const OTGCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { + HOST_CLK_EN: bool, // bit offset: 0 desc: Host clock enable + DEV_CLK_EN: bool, // bit offset: 1 desc: Device clock enable + I2C_CLK_EN: bool, // bit offset: 2 desc: I2C clock enable + OTG_CLK_EN: bool, // bit offset: 3 desc: OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. + AHB_CLK_EN: bool, // bit offset: 4 desc: AHB master clock enable + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4088 USB Clock Status + pub const USBCLKST = mmio(Address + 0x00000ff8, 32, packed struct { + reserved1: u1 = 0, + DEV_CLK_ON: bool, // bit offset: 1 desc: Device clock on. The usbclk input to the device controller is active . + reserved2: u1 = 0, + PORTSEL_CLK_ON: bool, // bit offset: 3 desc: Port select register clock on. + AHB_CLK_ON: bool, // bit offset: 4 desc: AHB clock on. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4088 OTG clock status + pub const OTGCLKST = mmio(Address + 0x00000ff8, 32, packed struct { + HOST_CLK_ON: bool, // bit offset: 0 desc: Host clock status. + DEV_CLK_ON: bool, // bit offset: 1 desc: Device clock status. + I2C_CLK_ON: bool, // bit offset: 2 desc: I2C clock status. + OTG_CLK_ON: bool, // bit offset: 3 desc: OTG clock status. + AHB_CLK_ON: bool, // bit offset: 4 desc: AHB master clock status. + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIO = extern struct { + pub const Address: u32 = 0x2009c000; + // byte offset: 0 GPIO Port Direction control register. + pub const DIR0 = mmio(Address + 0x00000000, 32, packed struct { + PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + }); + // byte offset: 16 Mask register for Port. + pub const MASK0 = mmio(Address + 0x00000010, 32, packed struct { + PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + }); + // byte offset: 20 Port Pin value register using FIOMASK. + pub const PIN0 = mmio(Address + 0x00000014, 32, packed struct { + PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 24 Port Output Set register using FIOMASK. + pub const SET0 = mmio(Address + 0x00000018, 32, packed struct { + PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 28 Port Output Clear register using FIOMASK. + pub const CLR0 = mmio(Address + 0x0000001c, 32, packed struct { + PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + }); + // byte offset: 32 GPIO Port Direction control register. + pub const DIR1 = mmio(Address + 0x00000020, 32, packed struct { + PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + }); + // byte offset: 48 Mask register for Port. + pub const MASK1 = mmio(Address + 0x00000030, 32, packed struct { + PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + }); + // byte offset: 52 Port Pin value register using FIOMASK. + pub const PIN1 = mmio(Address + 0x00000034, 32, packed struct { + PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 56 Port Output Set register using FIOMASK. + pub const SET1 = mmio(Address + 0x00000038, 32, packed struct { + PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 60 Port Output Clear register using FIOMASK. + pub const CLR1 = mmio(Address + 0x0000003c, 32, packed struct { + PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + }); + // byte offset: 64 GPIO Port Direction control register. + pub const DIR2 = mmio(Address + 0x00000040, 32, packed struct { + PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + }); + // byte offset: 80 Mask register for Port. + pub const MASK2 = mmio(Address + 0x00000050, 32, packed struct { + PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + }); + // byte offset: 84 Port Pin value register using FIOMASK. + pub const PIN2 = mmio(Address + 0x00000054, 32, packed struct { + PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 88 Port Output Set register using FIOMASK. + pub const SET2 = mmio(Address + 0x00000058, 32, packed struct { + PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 92 Port Output Clear register using FIOMASK. + pub const CLR2 = mmio(Address + 0x0000005c, 32, packed struct { + PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + }); + // byte offset: 96 GPIO Port Direction control register. + pub const DIR3 = mmio(Address + 0x00000060, 32, packed struct { + PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + }); + // byte offset: 112 Mask register for Port. + pub const MASK3 = mmio(Address + 0x00000070, 32, packed struct { + PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + }); + // byte offset: 116 Port Pin value register using FIOMASK. + pub const PIN3 = mmio(Address + 0x00000074, 32, packed struct { + PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 120 Port Output Set register using FIOMASK. + pub const SET3 = mmio(Address + 0x00000078, 32, packed struct { + PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 124 Port Output Clear register using FIOMASK. + pub const CLR3 = mmio(Address + 0x0000007c, 32, packed struct { + PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + }); + // byte offset: 128 GPIO Port Direction control register. + pub const DIR4 = mmio(Address + 0x00000080, 32, packed struct { + PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + }); + // byte offset: 144 Mask register for Port. + pub const MASK4 = mmio(Address + 0x00000090, 32, packed struct { + PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + }); + // byte offset: 148 Port Pin value register using FIOMASK. + pub const PIN4 = mmio(Address + 0x00000094, 32, packed struct { + PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 152 Port Output Set register using FIOMASK. + pub const SET4 = mmio(Address + 0x00000098, 32, packed struct { + PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + }); + // byte offset: 156 Port Output Clear register using FIOMASK. + pub const CLR4 = mmio(Address + 0x0000009c, 32, packed struct { + PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + }); +}; + diff --git a/src/tools/README.md b/src/tools/README.md new file mode 100644 index 0000000..95becbb --- /dev/null +++ b/src/tools/README.md @@ -0,0 +1,10 @@ +# microzig tools + +## `svd2zig.py` + +Converts CMSIS SVD files into zig source code. Requires [cmsis_svd](https://github.com/posborne/cmsis-svd/) installed (can be done with `pip install -U cmsis-svd`). + +## `linkerscript-gen.zig` + +Compiled on-demand by microzig to generate a linkerscript from a board/chip/cpu bundle. + diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py new file mode 100755 index 0000000..5579f8e --- /dev/null +++ b/src/tools/svd2zig.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +import sys +import io +import subprocess +import re + +from cmsis_svd.parser import SVDParser + +def cleanup_description(description): + if description is None: + return '' + + return ' '.join(description.replace('\n', ' ').split()) + +# register names in from Nordic SVDs are using foo[n] for couple of registers +# and also for somereaons there are %s in the reigster names +name_regex = re.compile(r"\[([^\]]+)]") +def cleanup_name(name): + return name_regex.sub(r"_\1", name).replace("%", "_") + +class MMIOFileGenerator: + def __init__(self, f): + self.f = f + + def generate_padding(self, count, name="padding", offset=0): + while count > 0: + self.write_line(f"{name}{offset + count}: u1 = 0,") + count = count - 1 + + def generate_register_field(self, field): + ''' + returns something like: + name: u, // bit offset: 0 desc: foo description + ''' + field.description = cleanup_description(field.description) + field_type = f"u{field.bit_width}" if field.bit_width != 1 else 'bool' + self.write_line(f"{field.name}:{field_type},// bit offset: {field.bit_offset} desc: {field.description}") + return field.bit_offset + field.bit_width + + def generate_register_declaration(self, register): + ''' + + ''' + register.description = cleanup_description(register.description) + self.write_line(f"// byte offset: {register.address_offset} {register.description}") + register.name = cleanup_name(register.name) + + size = register.size + if size == None: + size = 32 # hack for now... + + self.write_line(f" pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") + last_offset = 0 + reserved_index = 0 + for field in sorted(register.fields, key=lambda f: f.bit_offset): + if last_offset != field.bit_offset: + self.generate_padding(field.bit_offset - last_offset, "reserved", reserved_index) + reserved_index = reserved_index + 1 + + last_offset = self.generate_register_field(field) + + if register.size is not None: + self.generate_padding(register.size - last_offset) + + self.write_line("});") + + def generate_peripherial_declaration(self, peripherial): + self.write_line(f"pub const {peripherial.name} = extern struct {{") + self.write_line(f"pub const Address: u32 = 0x{peripherial.base_address:08x};") + + for register in sorted(peripherial.registers, key=lambda f: f.address_offset): + self.generate_register_declaration(register) + + self.write_line("};") + + def generate_file(self, device): + self.write_line("// generated using svd2zig.py\n// DO NOT EDIT") + self.write_line(f"// based on {device.name} version {device.version}") + + self.write_line("const mmio = @import(\"microzig-mmio\").mmio;") + self.write_line(f"const Name = \"{device.name}\";") + for peripherial in device.peripherals: + self.generate_peripherial_declaration(peripherial) + + def write_line(self, line): + self.f.write(line + "\n") + + + +def main(): + parser = SVDParser.for_packaged_svd(sys.argv[1], sys.argv[2] + '.svd') + device = parser.get_device() + + zig_fmt = subprocess.Popen(('zig', 'fmt', '--stdin'), stdin=subprocess.PIPE, + stdout=subprocess.PIPE, encoding='utf8') + + generator = MMIOFileGenerator(zig_fmt.stdin) + generator.generate_file(device) + + zig_fmt.stdin.flush() + zig_fmt.stdin.close() + print(zig_fmt.stdout.read()) + + +if __name__ == "__main__": + main() From deb9c3fe03005ef189f2afc30e45465aaa01f4cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Fri, 30 Apr 2021 01:35:38 +0200 Subject: [PATCH 010/138] Designs the basic uart frontend. --- build.zig | 1 + src/core/clock.zig | 20 ++++++++ src/core/microzig.zig | 8 ++- src/core/mmio.zig | 1 + src/core/uart.zig | 73 +++++++++++++++++++++++++++ src/modules/chips/lpc1768/lpc1768.zig | 11 ---- tests/blinky.zig | 8 +-- tests/uart-sync.zig | 31 ++++++++++++ 8 files changed, 137 insertions(+), 16 deletions(-) create mode 100644 src/core/clock.zig create mode 100644 src/core/uart.zig create mode 100644 tests/uart-sync.zig diff --git a/build.zig b/build.zig index 1c34f1f..32230f7 100644 --- a/build.zig +++ b/build.zig @@ -21,6 +21,7 @@ pub fn build(b: *std.build.Builder) void { const all_tests = [_]Test{ Test{ .name = "minimal", .source = "tests/minimal.zig" }, Test{ .name = "blinky", .source = "tests/blinky.zig" }, + Test{ .name = "uart-sync", .source = "tests/uart-sync.zig" }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); diff --git a/src/core/clock.zig b/src/core/clock.zig new file mode 100644 index 0000000..538e492 --- /dev/null +++ b/src/core/clock.zig @@ -0,0 +1,20 @@ +const std = @import("std"); +const root = @import("root"); + +/// Is `true` when microzig has a clock frequency available. +pub const has_clock = @hasDecl(root, "cpu_frequency"); + +/// Returns `true` when the frequency can change at runtime. +pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&root.cpu_frequency)).Pointer.is_const; + +/// Ensures that microzig has a clock available. This will @compileError when no clock is available, otherwise, it will be a no-op. +pub fn ensure() void { + if (!has_clock) + @compileError("microzig requires the clock frequency to perform this operation. Please export a const or var cpu_frequency from your root file that contains the cpu frequency in hertz!"); +} + +/// Returns the current cpu frequency in hertz. +pub fn get() callconv(.Inline) u32 { + ensure(); + return root.cpu_frequency; +} diff --git a/src/core/microzig.zig b/src/core/microzig.zig index f3d23ad..2ad2514 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -15,12 +15,18 @@ pub const cpu = chip.cpu; /// Module that helps with interrupt handling. pub const interrupts = @import("interrupts.zig"); +/// Module that provides clock related functions +pub const clock = @import("clock.zig"); + const gpio = @import("gpio.zig"); pub const Gpio = gpio.Gpio; const pin = @import("pin.zig"); pub const Pin = pin.Pin; +const uart = @import("uart.zig"); +pub const Uart = uart.Uart; + /// The microzig panic handler. Will disable interrupts and loop endlessly. /// Export this symbol from your main file to enable microzig: /// ``` @@ -72,7 +78,7 @@ export fn microzig_main() noreturn { // - Compute maximum size on the type of "err" // - Do not emit error names when std.builtin.strip is set. var msg: [64]u8 = undefined; - @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@tagName(err)}) catch @panic("main() returned error.")); + @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); }; } else { main(); diff --git a/src/core/mmio.zig b/src/core/mmio.zig index d433007..d779928 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -1,3 +1,4 @@ + const std = @import("std"); pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile MMIO(size, PackedT) { diff --git a/src/core/uart.zig b/src/core/uart.zig new file mode 100644 index 0000000..e400010 --- /dev/null +++ b/src/core/uart.zig @@ -0,0 +1,73 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); +const chip = @import("chip"); + +/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the +/// most common serial format. +pub const Config = struct { + baud_rate: u32, + stop_bits: StopBits = .one, + parity: Parity = .none, + data_bits: DataBits = .@"8", +}; + +const DataBits = enum { + @"5", + @"6", + @"7", + @"8", + @"9", +}; + +const StopBits = enum { one, two }; + +const Parity = enum { + none, + even, + odd, + mark, + space, +}; + +pub fn Uart(comptime index: usize) type { + return struct { + const Self = @This(); + + /// Initializes the UART with the given config and returns a handle to the uart. + pub fn init(config: Config) Self { + micro.clock.ensure(); + return Self{}; + } + + pub fn reader(self: Self) Reader { + return Reader{ .context = self }; + } + + pub fn writer(self: Self) Writer { + return Writer{ .context = self }; + } + + const ReadError = error{ + /// The input buffer received a byte while the receive fifo is already full. + /// Devices with no fifo fill overrun as soon as a second byte arrives. + Overrun, + /// A byte with an invalid parity bit was received. + ParityError, + /// The stop bit of our byte was not valid. + FramingError, + /// The break interrupt error will happen when RXD is logic zero for + /// the duration of a full byte. + BreakInterrupt, + }; + const WriteError = error{}; + pub const Reader = std.io.Reader(Self, ReadError, readSome); + pub const Writer = std.io.Writer(Self, WriteError, writeSome); + + fn readSome(self: Self, buffer: []u8) ReadError!usize { + return 0; + } + fn writeSome(self: Self, buffer: []const u8) WriteError!usize { + return 0; + } + }; +} diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 843979f..dbead2e 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -61,14 +61,3 @@ pub const gpio = struct { } } }; - -// pub const GPIO = extern struct { -// dir: u32, // 0x00 -// pad: [3]u32, -// mask: u32, // 0x10 -// pin: u32, // 0x14, -// set: u32, // 0x18, -// clr: u32, // 0x1C, -// }; - -// pub const gpio_base = 0x2009_C000; diff --git a/tests/blinky.zig b/tests/blinky.zig index 3dece30..d5614c7 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -6,13 +6,13 @@ pub const panic = micro.panic; // Configures the led_pin to a hardware pin const led_pin = switch (@import("builtin").cpu.arch) { .avr => if (micro.config.has_board) - micro.Pin("D13") + micro.Pin("D13") // Use D13 from Arduino Nano else - micro.Pin("PB5"), + micro.Pin("PB5"), // Use PB5 on raw ATmega328p .arm => if (micro.config.has_board) - micro.Pin("LED-1") + micro.Pin("LED-1") // Use LED-1 from mbed LPC1768 else - micro.Pin("P1.18"), + micro.Pin("P1.18"), // Use P1.18 on raw LPC1768 else => @compileError("Unsupported platform!"), }; diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig new file mode 100644 index 0000000..3734e0e --- /dev/null +++ b/tests/uart-sync.zig @@ -0,0 +1,31 @@ +const micro = @import("microzig"); + +// this will instantiate microzig and pull in all dependencies +pub const panic = micro.panic; + +// Configures the led_pin to a hardware pin +const uart_txd_pin = micro.Pin("P0.15"); +const uart_rxd_pin = micro.Pin("P0.16"); + +pub const cpu_frequency: u32 = 10_000_000; // 10 MHz + +pub fn main() !void { + var debug_port = micro.Uart(0).init(.{ + .baud_rate = 9600, + .stop_bits = .one, + .parity = .none, // { none, even, odd, mark, space } + .data_bits = .@"8", // 5, 6, 7, 8, or 9 data bits + }); + + var out = debug_port.writer(); + var in = debug_port.reader(); + + try out.writeAll("Please enter a sentence:\r\n"); + + while (true) { + try out.writeAll("> "); + var line_buffer: [64]u8 = undefined; + const line = (try in.readUntilDelimiterOrEof(&line_buffer, '\r')).?; + try out.writeAll(line); + } +} From 294cfebf7a6fd160d6bab15a8a2dadc4f3c22234 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Fri, 30 Apr 2021 19:23:16 +0200 Subject: [PATCH 011/138] Makes UART compile for LPC1768. --- build.zig | 18 +- src/core/clock.zig | 48 ++- src/core/microzig.zig | 9 +- src/core/mmio.zig | 11 +- src/core/uart.zig | 114 ++++--- .../boards/arduino-nano/arduino-nano.zig | 2 + src/modules/chips/lpc1768/lpc1768.zig | 89 +++++ src/modules/chips/lpc1768/registers.zig | 320 +++++++++--------- src/tools/svd2zig.py | 6 +- tests/uart-sync.zig | 2 +- 10 files changed, 393 insertions(+), 226 deletions(-) diff --git a/build.zig b/build.zig index 32230f7..b395268 100644 --- a/build.zig +++ b/build.zig @@ -48,6 +48,11 @@ pub fn build(b: *std.build.Builder) void { fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) *std.build.LibExeObjStep { const Pkg = std.build.Pkg; + const microzig_base = Pkg{ + .name = "microzig", + .path = "src/core/microzig.zig", + }; + const chip = switch (backing) { .chip => |c| c, .board => |b| b.chip, @@ -59,11 +64,12 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: .name = "chip", .path = chip.path, .dependencies = &[_]Pkg{ + microzig_base, pkgs.mmio, Pkg{ .name = "cpu", .path = chip.cpu.path, - .dependencies = &[_]Pkg{pkgs.mmio}, + .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, }, Pkg{ .name = "microzig-linker", @@ -184,22 +190,22 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: switch (backing) { .chip => { exe.addPackage(Pkg{ - .name = "microzig", - .path = "src/core/microzig.zig", + .name = microzig_base.name, + .path = microzig_base.path, .dependencies = &[_]Pkg{ config_pkg, chip_package }, }); }, .board => |board| { exe.addPackage(Pkg{ - .name = "microzig", - .path = "src/core/microzig.zig", + .name = microzig_base.name, + .path = microzig_base.path, .dependencies = &[_]Pkg{ config_pkg, chip_package, Pkg{ .name = "board", .path = board.path, - .dependencies = &[_]Pkg{ chip_package, pkgs.mmio }, + .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio }, }, }, }); diff --git a/src/core/clock.zig b/src/core/clock.zig index 538e492..11fbbd0 100644 --- a/src/core/clock.zig +++ b/src/core/clock.zig @@ -1,11 +1,32 @@ const std = @import("std"); const root = @import("root"); +const micro = @import("microzig.zig"); + +/// An enumeration of clock sources. +pub const Source = enum { + none, + application, + board, + chip, + cpu, +}; /// Is `true` when microzig has a clock frequency available. -pub const has_clock = @hasDecl(root, "cpu_frequency"); +/// Clock can be provided by several clock sources +pub const has_clock = (clock_source_type != void); /// Returns `true` when the frequency can change at runtime. -pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&root.cpu_frequency)).Pointer.is_const; +pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&@field(clock_source_type, freq_decl_name))).Pointer.is_const; + +/// Contains the source which provides microzig with clock information. +pub const source: Source = switch (clock_source_type) { + root => .application, + micro.board => .board, + micro.chip => .chip, + micro.cpu => .cpu, + no_clock_source_type => .none, + else => unreachable, +}; /// Ensures that microzig has a clock available. This will @compileError when no clock is available, otherwise, it will be a no-op. pub fn ensure() void { @@ -16,5 +37,26 @@ pub fn ensure() void { /// Returns the current cpu frequency in hertz. pub fn get() callconv(.Inline) u32 { ensure(); - return root.cpu_frequency; + return @field(clock_source_type, freq_decl_name); +} + +const freq_decl_name = "cpu_frequency"; + +const no_clock_source_type = opaque {}; +const clock_source_type = if (@hasDecl(root, freq_decl_name)) + root +else if (micro.config.has_board and @hasDecl(micro.board, freq_decl_name)) + micro.board +else if (@hasDecl(micro.chip, freq_decl_name)) + micro.chip +else if (@hasDecl(micro.cpu, freq_decl_name)) + micro.cpu +else + no_clock_source_type; + +comptime { + if (source != .application) { + if (is_dynamic) + @compileError("clock source " ++ @tagName(source) ++ " is not allowed to be dynamic. Only the application (root file) is allowed to provide a dynamic clock frequency!"); + } } diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 2ad2514..44ca0c9 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -9,6 +9,9 @@ pub const config = @import("microzig-config"); /// Provides access to the low level features of the current microchip. pub const chip = @import("chip"); +/// Provides access to board features or is `void` when no board is present. +pub const board = if (config.has_board) @import("board") else void; + /// Provides access to the low level features of the CPU. pub const cpu = chip.cpu; @@ -18,13 +21,13 @@ pub const interrupts = @import("interrupts.zig"); /// Module that provides clock related functions pub const clock = @import("clock.zig"); -const gpio = @import("gpio.zig"); +pub const gpio = @import("gpio.zig"); pub const Gpio = gpio.Gpio; -const pin = @import("pin.zig"); +pub const pin = @import("pin.zig"); pub const Pin = pin.Pin; -const uart = @import("uart.zig"); +pub const uart = @import("uart.zig"); pub const Uart = uart.Uart; /// The microzig panic handler. Will disable interrupts and loop endlessly. diff --git a/src/core/mmio.zig b/src/core/mmio.zig index d779928..d6cdf41 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -1,4 +1,3 @@ - const std = @import("std"); pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile MMIO(size, PackedT) { @@ -32,20 +31,20 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { addr.* = @bitCast(IntT, val); } - pub fn set(addr: *volatile Self, fields: anytype) void { - var val = read(); + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, field.name) = @field(fields, field.name); } - write(val); + write(addr, val); } pub fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(); + var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); } - write(val); + write(addr, val); } }; } diff --git a/src/core/uart.zig b/src/core/uart.zig index e400010..17a5c3c 100644 --- a/src/core/uart.zig +++ b/src/core/uart.zig @@ -2,41 +2,27 @@ const std = @import("std"); const micro = @import("microzig.zig"); const chip = @import("chip"); -/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the -/// most common serial format. -pub const Config = struct { - baud_rate: u32, - stop_bits: StopBits = .one, - parity: Parity = .none, - data_bits: DataBits = .@"8", -}; - -const DataBits = enum { - @"5", - @"6", - @"7", - @"8", - @"9", -}; - -const StopBits = enum { one, two }; - -const Parity = enum { - none, - even, - odd, - mark, - space, -}; - pub fn Uart(comptime index: usize) type { + const SystemUart = chip.Uart(index); return struct { const Self = @This(); + internal: SystemUart, + /// Initializes the UART with the given config and returns a handle to the uart. - pub fn init(config: Config) Self { + pub fn init(config: Config) InitError!Self { micro.clock.ensure(); - return Self{}; + return Self{ + .internal = try SystemUart.init(config), + }; + } + + pub fn canRead(self: Self) bool { + return self.internal.canRead(); + } + + pub fn canWrite(self: Self) bool { + return self.internal.canWrite(); } pub fn reader(self: Self) Reader { @@ -47,27 +33,67 @@ pub fn Uart(comptime index: usize) type { return Writer{ .context = self }; } - const ReadError = error{ - /// The input buffer received a byte while the receive fifo is already full. - /// Devices with no fifo fill overrun as soon as a second byte arrives. - Overrun, - /// A byte with an invalid parity bit was received. - ParityError, - /// The stop bit of our byte was not valid. - FramingError, - /// The break interrupt error will happen when RXD is logic zero for - /// the duration of a full byte. - BreakInterrupt, - }; - const WriteError = error{}; pub const Reader = std.io.Reader(Self, ReadError, readSome); pub const Writer = std.io.Writer(Self, WriteError, writeSome); fn readSome(self: Self, buffer: []u8) ReadError!usize { - return 0; + for (buffer) |*c| { + c.* = self.internal.rx(); + } + return buffer.len; } fn writeSome(self: Self, buffer: []const u8) WriteError!usize { - return 0; + for (buffer) |c| { + self.internal.tx(c); + } + return buffer.len; } }; } + +/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the +/// most common serial format. +pub const Config = struct { + baud_rate: u32, + stop_bits: StopBits = .one, + parity: Parity = .none, + data_bits: DataBits = .@"8", +}; + +pub const DataBits = enum { + @"5", + @"6", + @"7", + @"8", + @"9", +}; + +pub const StopBits = enum { one, two }; + +pub const Parity = enum { + none, + even, + odd, + mark, + space, +}; +pub const InitError = error{ + UnsupportedWordSize, + UnsupportedParity, + UnsupportedStopBitCount, + UnsupportedBaudRate, +}; + +pub const ReadError = error{ + /// The input buffer received a byte while the receive fifo is already full. + /// Devices with no fifo fill overrun as soon as a second byte arrives. + Overrun, + /// A byte with an invalid parity bit was received. + ParityError, + /// The stop bit of our byte was not valid. + FramingError, + /// The break interrupt error will happen when RXD is logic zero for + /// the duration of a full byte. + BreakInterrupt, +}; +pub const WriteError = error{}; diff --git a/src/modules/boards/arduino-nano/arduino-nano.zig b/src/modules/boards/arduino-nano/arduino-nano.zig index c622669..16ade81 100644 --- a/src/modules/boards/arduino-nano/arduino-nano.zig +++ b/src/modules/boards/arduino-nano/arduino-nano.zig @@ -1,5 +1,7 @@ pub const chip = @import("chip"); +pub const cpu_frequency = 16_000_000; + pub const pin_map = .{ // Port A .D0 = "PD0", diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index dbead2e..5d56401 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const micro = @import("microzig"); const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); @@ -61,3 +62,91 @@ pub const gpio = struct { } } }; + +pub fn Uart(comptime index: usize) type { + return struct { + const UARTn = switch (index) { + 0 => registers.UART0, + 1 => registers.UART1, + 2 => registers.UART2, + 3 => registers.UART3, + else => @compileError("LPC1768 has 4 UARTs available."), + }; + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + switch (index) { + 0 => { + registers.SYSCON.PCONP.modify(.{ .PCUART0 = true }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = 0 }); + }, + 1 => { + registers.SYSCON.PCONP.modify(.{ .PCUART1 = true }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = 0 }); + }, + 2 => { + registers.SYSCON.PCONP.modify(.{ .PCUART2 = true }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = 0 }); + }, + 3 => { + registers.SYSCON.PCONP.modify(.{ .PCUART3 = true }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = 0 }); + }, + else => unreachable, + } + + UARTn.LCR.write(.{ + // 8N1 + .WLS = switch (config.data_bits) { + .@"5" => 0b00, + .@"6" => 0b01, + .@"7" => 0b10, + .@"8" => 0b11, + .@"9" => return error.UnsupportedWordSize, + }, + .SBS = switch (config.stop_bits) { + .one => false, + .two => true, + }, + .PE = (config.parity != .none), + .PS = switch (config.parity) { + .none, .odd => @as(u2, 0b00), + .even => 0b01, + .mark => 0b10, + .space => 0b11, + }, + .BC = false, + .DLAB = true, + }); + UARTn.FCR.modify(.{ .FIFOEN = false }); + + const pclk = micro.clock.get() / 4; + const divider = (pclk / (16 * config.baud_rate)); + + const regval = std.math.cast(u16, divider) catch return error.UnsupportedBaudRate; + + UARTn.DLL.write(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); + UARTn.DLM.write(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); + + UARTn.LCR.modify(.{ .DLAB = false }); + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + return UARTn.LSR.read().THRE; + } + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + UARTn.THR.raw = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + return UARTn.LSR.read().RDR; + } + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return UARTn.RBR.read().RBR; // Read received data + } + }; +} diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index b0a6b05..0b2aa99 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -2618,12 +2618,12 @@ pub const RTC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59 - reserved3: u1 = 0, - reserved2: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23 - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6 padding5: u1 = 0, padding4: u1 = 0, @@ -2638,10 +2638,10 @@ pub const RTC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095. padding4: u1 = 0, padding3: u1 = 0, @@ -3699,22 +3699,22 @@ pub const PINCONNECT = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, P1_4: u2, // bit offset: 8 desc: Pin function select P1.4. + reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, P1_8: u2, // bit offset: 16 desc: Pin function select P1.8. P1_9: u2, // bit offset: 18 desc: Pin function select P1.9. P1_10: u2, // bit offset: 20 desc: Pin function select P1.10. P1_14: u2, // bit offset: 22 desc: Pin function select P1.14. + reserved10: u1 = 0, + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, P1_15: u2, // bit offset: 30 desc: Pin function select P1.15. }); // byte offset: 12 Pin function select register 3. @@ -3913,21 +3913,21 @@ pub const PINCONNECT = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, P1_04MODE: u2, // bit offset: 8 desc: Port 1 pin 4 control. + reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, P1_08MODE: u2, // bit offset: 16 desc: Port 1 pin 8 control. P1_09MODE: u2, // bit offset: 18 desc: Port 1 pin 9 control. P1_10MODE: u2, // bit offset: 20 desc: Port 1 pin 10 control. + reserved10: u1 = 0, + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, P1_14MODE: u2, // bit offset: 28 desc: Port 1 pin 14 control. P1_15MODE: u2, // bit offset: 30 desc: Port 1 pin 15 control. }); @@ -4596,18 +4596,18 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. }); @@ -4653,20 +4653,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4677,20 +4677,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4701,20 +4701,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4725,20 +4725,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4749,20 +4749,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4773,20 +4773,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4797,20 +4797,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -4821,20 +4821,20 @@ pub const ADC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); @@ -7581,6 +7581,9 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -7588,9 +7591,6 @@ pub const CAN1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. }); @@ -7645,6 +7645,9 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -7652,9 +7655,6 @@ pub const CAN1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -7688,6 +7688,9 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -7695,9 +7698,6 @@ pub const CAN1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -7731,6 +7731,9 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -7738,9 +7741,6 @@ pub const CAN1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8007,6 +8007,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8014,9 +8017,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. }); @@ -8071,6 +8071,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8078,9 +8081,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8096,6 +8096,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8103,9 +8106,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8157,6 +8157,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8164,9 +8167,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8182,6 +8182,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8189,9 +8192,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8243,6 +8243,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8250,9 +8253,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -8268,6 +8268,9 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -8275,9 +8278,6 @@ pub const CAN2 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); @@ -11001,10 +11001,10 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO. padding12: u1 = 0, padding11: u1 = 0, @@ -11030,10 +11030,10 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1. padding12: u1 = 0, padding11: u1 = 0, @@ -11059,10 +11059,10 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2. padding12: u1 = 0, padding11: u1 = 0, @@ -11088,10 +11088,10 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request. padding12: u1 = 0, padding11: u1 = 0, @@ -13017,8 +13017,8 @@ pub const SYSCON = extern struct { PCLK_PWM1: u2, // bit offset: 12 desc: Peripheral clock selection for PWM1. PCLK_I2C0: u2, // bit offset: 14 desc: Peripheral clock selection for I2C0. PCLK_SPI: u2, // bit offset: 16 desc: Peripheral clock selection for SPI. + reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, PCLK_SSP1: u2, // bit offset: 20 desc: Peripheral clock selection for SSP1. PCLK_DAC: u2, // bit offset: 22 desc: Peripheral clock selection for DAC. PCLK_ADC: u2, // bit offset: 24 desc: Peripheral clock selection for ADC. @@ -13041,8 +13041,8 @@ pub const SYSCON = extern struct { PCLK_UART3: u2, // bit offset: 18 desc: Peripheral clock selection for UART3. PCLK_I2C2: u2, // bit offset: 20 desc: Peripheral clock selection for I2C2. PCLK_I2S: u2, // bit offset: 22 desc: Peripheral clock selection for I2S. + reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, PCLK_RIT: u2, // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. PCLK_SYSCON: u2, // bit offset: 28 desc: Peripheral clock selection for the System Control block. PCLK_MC: u2, // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index 5579f8e..13061e7 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -22,7 +22,7 @@ class MMIOFileGenerator: def __init__(self, f): self.f = f - def generate_padding(self, count, name="padding", offset=0): + def generate_padding(self, count, name, offset): while count > 0: self.write_line(f"{name}{offset + count}: u1 = 0,") count = count - 1 @@ -55,12 +55,12 @@ class MMIOFileGenerator: for field in sorted(register.fields, key=lambda f: f.bit_offset): if last_offset != field.bit_offset: self.generate_padding(field.bit_offset - last_offset, "reserved", reserved_index) - reserved_index = reserved_index + 1 + reserved_index = reserved_index + field.bit_width last_offset = self.generate_register_field(field) if register.size is not None: - self.generate_padding(register.size - last_offset) + self.generate_padding(register.size - last_offset, "padding", 0) self.write_line("});") diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 3734e0e..7b61086 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -10,7 +10,7 @@ const uart_rxd_pin = micro.Pin("P0.16"); pub const cpu_frequency: u32 = 10_000_000; // 10 MHz pub fn main() !void { - var debug_port = micro.Uart(0).init(.{ + var debug_port = try micro.Uart(0).init(.{ .baud_rate = 9600, .stop_bits = .one, .parity = .none, // { none, even, odd, mark, space } From 196c4c4d0522b1a528de3ac312c9859b417e0312 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=28xq=29=20Quei=C3=9Fner?= Date: Fri, 30 Apr 2021 22:11:50 +0200 Subject: [PATCH 012/138] mbed LPC1768 only commit. This introduces a working UART abstraction for LPC1768, currently the uart-sync example has chip-related code in it. --- build.zig | 2 +- src/core/debug.zig | 38 +++++++ src/core/gpio.zig | 4 +- src/core/microzig.zig | 18 ++- src/core/mmio.zig | 7 +- src/core/pin.zig | 2 +- .../boards/mbed-lpc1768/mbed-lpc1768.zig | 31 ++++++ src/modules/chips/lpc1768/lpc1768.zig | 46 ++++++-- src/modules/cpus/cortex-m3/cortex-m3.zig | 47 ++++---- tests/uart-sync.zig | 105 ++++++++++++++++-- 10 files changed, 252 insertions(+), 48 deletions(-) create mode 100644 src/core/debug.zig diff --git a/build.zig b/build.zig index b395268..c9ca6c0 100644 --- a/build.zig +++ b/build.zig @@ -185,7 +185,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.bundle_compiler_rt = false; + // exe.bundle_compiler_rt = false; switch (backing) { .chip => { diff --git a/src/core/debug.zig b/src/core/debug.zig new file mode 100644 index 0000000..eb2474c --- /dev/null +++ b/src/core/debug.zig @@ -0,0 +1,38 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); + +pub fn busySleep(comptime limit: comptime_int) void { + if (limit <= 0) @compileError("limit must be non-negative!"); + + comptime var bits = 0; + inline while ((1 << bits) <= limit) { + bits += 1; + } + + const I = std.meta.Int(.unsigned, bits); + + var i: I = 0; + while (i < limit) : (i += 1) { + @import("std").mem.doNotOptimizeAway(i); + } +} + +const DebugErr = error{}; +fn writerWrite(ctx: void, string: []const u8) DebugErr!usize { + write(string); + return string.len; +} + +const DebugWriter = std.io.Writer(void, DebugErr, writerWrite); + +pub fn write(string: []const u8) void { + if (!micro.config.has_board) + return; + if (!@hasDecl(micro.board, "debugWrite")) + return; + micro.board.debugWrite(string); +} + +pub fn writer() DebugWriter { + return DebugWriter{ .context = {} }; +} diff --git a/src/core/gpio.zig b/src/core/gpio.zig index bbbe57d..325cfed 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -57,12 +57,12 @@ pub fn Gpio(comptime pin: type, config: anytype) type { } fn read() State { - return @intToEnum(State, chip.gpio.read(pin.source_pin)); + return chip.gpio.read(pin.source_pin); } // outputs: fn write(state: State) void { - chip.gpio.write(pin.source_pin, @enumToInt(state)); + chip.gpio.write(pin.source_pin, state); } fn setToHigh() void { diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 44ca0c9..4664fc5 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -30,13 +30,29 @@ pub const Pin = pin.Pin; pub const uart = @import("uart.zig"); pub const Uart = uart.Uart; +pub const debug = @import("debug.zig"); + /// The microzig panic handler. Will disable interrupts and loop endlessly. /// Export this symbol from your main file to enable microzig: /// ``` /// const micro = @import("microzig"); /// pub const panic = micro.panic; /// ``` -pub fn panic(message: []const u8, stack_trace: ?*std.builtin.StackTrace) noreturn { +pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { + var writer = debug.writer(); + writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable; + if (maybe_stack_trace) |stack_trace| { + var frame_index: usize = 0; + var frames_left: usize = std.math.min(stack_trace.index, stack_trace.instruction_addresses.len); + + while (frames_left != 0) : ({ + frames_left -= 1; + frame_index = (frame_index + 1) % stack_trace.instruction_addresses.len; + }) { + const return_address = stack_trace.instruction_addresses[frame_index]; + writer.print("0x{X:0>8}\r\n", .{return_address}) catch unreachable; + } + } hang(); } diff --git a/src/core/mmio.zig b/src/core/mmio.zig index d6cdf41..a46ca0c 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -24,11 +24,14 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { pub const underlying_type = PackedT; pub fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.*); + return @bitCast(PackedT, addr.raw); } pub fn write(addr: *volatile Self, val: PackedT) void { - addr.* = @bitCast(IntT, val); + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; } pub fn modify(addr: *volatile Self, fields: anytype) void { diff --git a/src/core/pin.zig b/src/core/pin.zig index c7c5db4..b46962e 100644 --- a/src/core/pin.zig +++ b/src/core/pin.zig @@ -28,7 +28,7 @@ pub fn Pin(comptime spec: []const u8) type { pub const source_pin = pin; pub fn route(target: pin.Targets) void { - unreachable; + chip.routePin(source_pin, target); } }; } diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig index 4994c7f..95358ff 100644 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig @@ -1,4 +1,35 @@ pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub fn debugWrite(string: []const u8) void { + const clk_pin = micro.Pin("DIP5"); + const dat_pin = micro.Pin("DIP6"); + + const clk = micro.Gpio(clk_pin, .{ .mode = .output, .initial_state = .low }); + const dat = micro.Gpio(dat_pin, .{ .mode = .output, .initial_state = .low }); + + clk.init(); + dat.init(); + + micro.debug.busySleep(1_000); + + for (string) |c| { + comptime var i: usize = 128; + inline while (i > 0) : (i = i >> 1) { + if ((c & i) != 0) { + dat.write(.high); + } else { + dat.write(.low); + } + clk.write(.high); + micro.debug.busySleep(1_000); + clk.write(.low); + micro.debug.busySleep(1_000); + } + } + dat.write(.low); + clk.write(.low); +} pub const pin_map = .{ // Onboard-LEDs diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 5d56401..d03809e 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -11,6 +11,13 @@ pub const memory_regions = [_]micro_linker.MemoryRegion{ micro_linker.MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, }; +pub const PinTarget = enum(u2) { + func00 = 0b00, + func01 = 0b01, + func10 = 0b10, + func11 = 0b11, +}; + pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme."; if (spec[0] != 'P') @@ -18,12 +25,17 @@ pub fn parsePin(comptime spec: []const u8) type { const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg); - const _port: u3 = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); - const _pin: u5 = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); + const _port: comptime_int = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); + const _pin: comptime_int = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); + + const sel_reg_name = std.fmt.comptimePrint("PINSEL{d}", .{(2 * _port + _pin / 16)}); const _regs = struct { const name_suffix = std.fmt.comptimePrint("{d}", .{_port}); + const pinsel_reg = @field(registers.PINCONNECT, sel_reg_name); + const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin }); + const dir = @field(registers.GPIO, "DIR" ++ name_suffix); const pin = @field(registers.GPIO, "PIN" ++ name_suffix); const set = @field(registers.GPIO, "SET" ++ name_suffix); @@ -32,13 +44,21 @@ pub fn parsePin(comptime spec: []const u8) type { }; return struct { - pub const port = _port; - pub const pin = _pin; + pub const port: u3 = _port; + pub const pin: u5 = _pin; pub const regs = _regs; const gpio_mask: u32 = (1 << pin); + + pub const Targets = PinTarget; }; } +pub fn routePin(comptime pin: type, function: PinTarget) void { + var val = pin.regs.pinsel_reg.read(); + @field(val, pin.regs.pinsel_field) = @enumToInt(function); + pin.regs.pinsel_reg.write(val); +} + pub const gpio = struct { pub fn setOutput(comptime pin: type) void { pin.regs.dir.raw |= pin.gpio_mask; @@ -47,15 +67,15 @@ pub const gpio = struct { pin.regs.dir.raw &= ~pin.gpio_mask; } - pub fn read(comptime pin: type) u1 { + pub fn read(comptime pin: type) micro.gpio.State { return if ((pin.regs.pin.raw & pin.gpio_mask) != 0) - @as(u1, 1) + micro.gpio.State.high else - 0; + micro.gpio.State.low; } - pub fn write(comptime pin: type, state: u1) void { - if (state == 1) { + pub fn write(comptime pin: type, state: micro.gpio.State) void { + if (state == .high) { pin.regs.set.raw = pin.gpio_mask; } else { pin.regs.clr.raw = pin.gpio_mask; @@ -75,6 +95,7 @@ pub fn Uart(comptime index: usize) type { const Self = @This(); pub fn init(config: micro.uart.Config) !Self { + micro.debug.write("0"); switch (index) { 0 => { registers.SYSCON.PCONP.modify(.{ .PCUART0 = true }); @@ -94,6 +115,7 @@ pub fn Uart(comptime index: usize) type { }, else => unreachable, } + micro.debug.write("1"); UARTn.LCR.write(.{ // 8N1 @@ -118,8 +140,14 @@ pub fn Uart(comptime index: usize) type { .BC = false, .DLAB = true, }); + micro.debug.write("2"); UARTn.FCR.modify(.{ .FIFOEN = false }); + micro.debug.writer().print("clock: {} baud: {} ", .{ + micro.clock.get(), + config.baud_rate, + }) catch {}; + const pclk = micro.clock.get() / 4; const divider = (pclk / (16 * config.baud_rate)); diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig index 4c82311..29c1414 100644 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ b/src/modules/cpus/cortex-m3/cortex-m3.zig @@ -1,49 +1,42 @@ const std = @import("std"); pub fn sei() void { - __enable_irq(); + asm volatile ("cpsie i"); } pub fn cli() void { - __disable_irq(); -} - -pub fn __enable_irq() void { - asm volatile ("cpsie i"); -} -pub fn __disable_irq() void { asm volatile ("cpsid i"); } -pub fn __enable_fault_irq() void { +pub fn enable_fault_irq() void { asm volatile ("cpsie f"); } -pub fn __disable_fault_irq() void { +pub fn disable_fault_irq() void { asm volatile ("cpsid f"); } -pub fn __NOP() void { +pub fn nop() void { asm volatile ("nop"); } -pub fn __WFI() void { +pub fn wfi() void { asm volatile ("wfi"); } -pub fn __WFE() void { +pub fn wfe() void { asm volatile ("wfe"); } -pub fn __SEV() void { +pub fn sev() void { asm volatile ("sev"); } -pub fn __ISB() void { +pub fn isb() void { asm volatile ("isb"); } -pub fn __DSB() void { +pub fn dsb() void { asm volatile ("dsb"); } -pub fn __DMB() void { +pub fn dmb() void { asm volatile ("dmb"); } -pub fn __CLREX() void { +pub fn clrex() void { asm volatile ("clrex"); } @@ -53,11 +46,11 @@ pub const startup_logic = struct { const VectorTable = extern struct { initial_stack_pointer: u32, reset: InterruptVector, - nmi: InterruptVector = unhandledInterrupt, - hard_fault: InterruptVector = unhandledInterrupt, - mpu_fault: InterruptVector = unhandledInterrupt, - bus_fault: InterruptVector = unhandledInterrupt, - usage_fault: InterruptVector = unhandledInterrupt, + nmi: InterruptVector = makeUnhandledHandler("nmi"), + hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), + mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), + bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), + usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), reserved: u32 = 0, }; @@ -68,8 +61,12 @@ pub const startup_logic = struct { .reset = _start, }; - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt"); + fn makeUnhandledHandler(comptime str: []const u8) fn () callconv(.C) noreturn { + return struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt; } extern fn microzig_main() noreturn; diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 7b61086..7116272 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -7,25 +7,116 @@ pub const panic = micro.panic; const uart_txd_pin = micro.Pin("P0.15"); const uart_rxd_pin = micro.Pin("P0.16"); -pub const cpu_frequency: u32 = 10_000_000; // 10 MHz +const debug_pin = micro.Pin("P0.17"); + +const led1_pin = micro.Pin("P1.18"); +const led2_pin = micro.Pin("P1.20"); +const led3_pin = micro.Pin("P1.21"); +const led4_pin = micro.Pin("P1.23"); + +pub const cpu_frequency: u32 = 100_000_000; // 100 MHz + +const PLL = struct { + fn init() void { + reset_overclocking(); + } + + fn reset_overclocking() void { + overclock_flash(5); // 5 cycles access time + overclock_pll(3); // 100 MHz + } + + fn overclock_flash(timing: u5) void { + micro.chip.registers.SYSCON.FLASHCFG.write(.{ + .FLASHTIM = @intCast(u4, timing - 1), + }); + } + fn feed_pll() callconv(.Inline) void { + micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0xAA }); + micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0x55 }); + } + + fn overclock_pll(divider: u8) void { + // PLL einrichten für RC + micro.chip.registers.SYSCON.PLL0CON.write(.{ + .PLLE0 = false, + .PLLC0 = false, + }); + feed_pll(); + + micro.chip.registers.SYSCON.CLKSRCSEL.write(.{ .CLKSRC = 0 }); // RC-Oszillator als Quelle + micro.chip.registers.SYSCON.PLL0CFG.write(.{ + // SysClk = (4MHz / 2) * (2 * 75) = 300 MHz + .MSEL0 = 74, + .NSEL0 = 1, + }); + // CPU Takt = SysClk / divider + micro.chip.registers.SYSCON.CCLKCFG.write(.{ .CCLKSEL = divider - 1 }); + + feed_pll(); + + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = true }); // PLL einschalten + feed_pll(); + + var i: usize = 0; + while (i < 1_000) : (i += 1) { + micro.cpu.nop(); + } + + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLC0 = true }); + feed_pll(); + } +}; pub fn main() !void { - var debug_port = try micro.Uart(0).init(.{ + const gpio_init = .{ .mode = .output, .initial_state = .low }; + + const led1 = micro.Gpio(led1_pin, gpio_init); + const led2 = micro.Gpio(led2_pin, gpio_init); + const led3 = micro.Gpio(led3_pin, gpio_init); + const led4 = micro.Gpio(led4_pin, gpio_init); + + const status = micro.Gpio(debug_pin, .{ + .mode = .output, + .initial_state = .high, + }); + status.init(); + led1.init(); + led2.init(); + led3.init(); + led4.init(); + + uart_txd_pin.route(.func01); + uart_rxd_pin.route(.func01); + + PLL.init(); + led1.setToHigh(); + + var debug_port = micro.Uart(1).init(.{ .baud_rate = 9600, .stop_bits = .one, .parity = .none, // { none, even, odd, mark, space } .data_bits = .@"8", // 5, 6, 7, 8, or 9 data bits - }); + }) catch |err| { + led1.write(if (err == error.UnsupportedBaudRate) micro.gpio.State.low else .high); + led2.write(if (err == error.UnsupportedParity) micro.gpio.State.low else .high); + led3.write(if (err == error.UnsupportedStopBitCount) micro.gpio.State.low else .high); + led4.write(if (err == error.UnsupportedWordSize) micro.gpio.State.low else .high); + + micro.hang(); + }; + led2.setToHigh(); var out = debug_port.writer(); var in = debug_port.reader(); try out.writeAll("Please enter a sentence:\r\n"); + led3.setToHigh(); + while (true) { - try out.writeAll("> "); - var line_buffer: [64]u8 = undefined; - const line = (try in.readUntilDelimiterOrEof(&line_buffer, '\r')).?; - try out.writeAll(line); + try out.writeAll("."); + led4.toggle(); + micro.debug.busySleep(100_000); } } From a4416fd2b7a740ea6df39a3a3b43d2287bda06b9 Mon Sep 17 00:00:00 2001 From: Vesim Date: Tue, 4 May 2021 14:56:51 +0200 Subject: [PATCH 013/138] [svd2zig] Add enumeration supports and fix bug for registers without fields --- src/tools/svd2zig.py | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index 13061e7..cd41681 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -27,14 +27,32 @@ class MMIOFileGenerator: self.write_line(f"{name}{offset + count}: u1 = 0,") count = count - 1 + def generate_enumerated_field(self, field): + ''' + returns something like: + name: enum(u){ // bit offset: 0 desc: foo description + name = value, // desc: ... + name = value, // desc: + _, // non_exhustive + }, + + ''' + field.description = cleanup_description(field.description) + self.write_line(f"{field.name}:enum(u{field.bit_width}){{// bit offset: {field.bit_offset} desc: {field.description}") + for e in field.enumerated_values: + e.description = cleanup_description(e.description) + self.write_line(f"@\"{e.name}\" = {e.value}, // desc: {e.description}") + self.write_line("_, // non-exhaustive") + self.write_line("},") + return field.bit_offset + field.bit_width + def generate_register_field(self, field): ''' returns something like: name: u, // bit offset: 0 desc: foo description ''' field.description = cleanup_description(field.description) - field_type = f"u{field.bit_width}" if field.bit_width != 1 else 'bool' - self.write_line(f"{field.name}:{field_type},// bit offset: {field.bit_offset} desc: {field.description}") + self.write_line(f"{field.name}:u{field.bit_width},// bit offset: {field.bit_offset} desc: {field.description}") return field.bit_offset + field.bit_width def generate_register_declaration(self, register): @@ -56,15 +74,22 @@ class MMIOFileGenerator: if last_offset != field.bit_offset: self.generate_padding(field.bit_offset - last_offset, "reserved", reserved_index) reserved_index = reserved_index + field.bit_width + if field.is_enumerated_type: + last_offset = self.generate_enumerated_field(field) + else: + last_offset = self.generate_register_field(field) - last_offset = self.generate_register_field(field) + if size is not None: + if len(register.fields) == 0: + self.write_line(f"raw: u{size}, // placeholder field") + else: + self.generate_padding(size - last_offset, "padding", 0) - if register.size is not None: - self.generate_padding(register.size - last_offset, "padding", 0) self.write_line("});") def generate_peripherial_declaration(self, peripherial): + # TODO: write peripherial description self.write_line(f"pub const {peripherial.name} = extern struct {{") self.write_line(f"pub const Address: u32 = 0x{peripherial.base_address:08x};") From 74641abbf0827b6a0d3d5f5074bd3560341bc859 Mon Sep 17 00:00:00 2001 From: Vesim Date: Tue, 4 May 2021 15:19:42 +0200 Subject: [PATCH 014/138] [svd2zig] Fix handling og non-exhaustive enums and resverd fields --- src/tools/svd2zig.py | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index cd41681..f3d98dc 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -1,22 +1,24 @@ #!/usr/bin/env python3 import sys -import io import subprocess import re from cmsis_svd.parser import SVDParser + def cleanup_description(description): if description is None: return '' return ' '.join(description.replace('\n', ' ').split()) -# register names in from Nordic SVDs are using foo[n] for couple of registers -# and also for somereaons there are %s in the reigster names -name_regex = re.compile(r"\[([^\]]+)]") + +# register names in some SVDs are using foo[n] for registers names +# and also for some reaons there are string formatters like %s in the reigster names +NAME_REGEX = re.compile(r"\[([^\]]+)]") def cleanup_name(name): - return name_regex.sub(r"_\1", name).replace("%", "_") + return NAME_REGEX.sub(r"_\1", name).replace("%", "_") + class MMIOFileGenerator: def __init__(self, f): @@ -33,16 +35,27 @@ class MMIOFileGenerator: name: enum(u){ // bit offset: 0 desc: foo description name = value, // desc: ... name = value, // desc: - _, // non_exhustive + _, // non-exhustive }, ''' field.description = cleanup_description(field.description) self.write_line(f"{field.name}:enum(u{field.bit_width}){{// bit offset: {field.bit_offset} desc: {field.description}") + + total_fields_with_values = 0 for e in field.enumerated_values: e.description = cleanup_description(e.description) - self.write_line(f"@\"{e.name}\" = {e.value}, // desc: {e.description}") - self.write_line("_, // non-exhaustive") + if e.value is None: + # reserved fields doesn't have a value so we have to comment them out + self.write_line(f"// @\"{e.name}\", // desc: {e.description}") + else: + total_fields_with_values = total_fields_with_values + 1 + self.write_line(f"@\"{e.name}\" = {e.value}, // desc: {e.description}") + + # if the fields doesn't use all possible values make the enum non-exhaustive + if total_fields_with_values < 2**field.bit_width: + self.write_line("_, // non-exhaustive") + self.write_line("},") return field.bit_offset + field.bit_width @@ -111,7 +124,6 @@ class MMIOFileGenerator: self.f.write(line + "\n") - def main(): parser = SVDParser.for_packaged_svd(sys.argv[1], sys.argv[2] + '.svd') device = parser.get_device() From eedc689738bfb8c70422bbe07998505d9314be6b Mon Sep 17 00:00:00 2001 From: Vesim Date: Tue, 4 May 2021 23:00:13 +0200 Subject: [PATCH 015/138] Move lpc1768 to new generated SVD --- build.zig | 6 +- src/core/uart.zig | 24 +- src/modules/chips/lpc1768/lpc1768.zig | 84 +- src/modules/chips/lpc1768/registers.zig | 12494 ++++++++++++++-------- src/tools/svd2zig.py | 14 +- tests/blinky.zig | 20 +- tests/uart-sync.zig | 16 +- 7 files changed, 8409 insertions(+), 4249 deletions(-) diff --git a/build.zig b/build.zig index c9ca6c0..93fa0a0 100644 --- a/build.zig +++ b/build.zig @@ -145,11 +145,11 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; if (has_board) { - writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; + writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; } - writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; - writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; + writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; } const config_pkg = Pkg{ diff --git a/src/core/uart.zig b/src/core/uart.zig index 17a5c3c..1cf8e41 100644 --- a/src/core/uart.zig +++ b/src/core/uart.zig @@ -56,27 +56,15 @@ pub fn Uart(comptime index: usize) type { pub const Config = struct { baud_rate: u32, stop_bits: StopBits = .one, - parity: Parity = .none, - data_bits: DataBits = .@"8", + parity: ?Parity = null, + data_bits: DataBits = .eight, }; -pub const DataBits = enum { - @"5", - @"6", - @"7", - @"8", - @"9", -}; - -pub const StopBits = enum { one, two }; +// TODO: comptime verify that the enums are valid +pub const DataBits = chip.uart.DataBits; +pub const StopBits = chip.uart.StopBits; +pub const Parity = chip.uart.Parity; -pub const Parity = enum { - none, - even, - odd, - mark, - space, -}; pub const InitError = error{ UnsupportedWordSize, UnsupportedParity, diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index d03809e..4f39fa4 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -55,7 +55,7 @@ pub fn parsePin(comptime spec: []const u8) type { pub fn routePin(comptime pin: type, function: PinTarget) void { var val = pin.regs.pinsel_reg.read(); - @field(val, pin.regs.pinsel_field) = @enumToInt(function); + @field(val, pin.regs.pinsel_field) = @intToEnum(@TypeOf(@field(val, pin.regs.pinsel_field)), @enumToInt(function)); pin.regs.pinsel_reg.write(val); } @@ -83,6 +83,30 @@ pub const gpio = struct { } }; +pub const uart = struct { + const RegisterDataBitsEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .WLS).field_type; + pub const DataBits = enum(u2) { + five = @enumToInt(RegisterDataBitsEnum.@"5_BIT_CHARACTER_LENG"), + six = @enumToInt(RegisterDataBitsEnum.@"6_BIT_CHARACTER_LENG"), + seven = @enumToInt(RegisterDataBitsEnum.@"7_BIT_CHARACTER_LENG"), + eight = @enumToInt(RegisterDataBitsEnum.@"8_BIT_CHARACTER_LENG"), + }; + + const RegisterStopBitEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .SBS).field_type; + pub const StopBits = enum(u1) { + one = @enumToInt(RegisterStopBitEnum.@"1_STOP_BIT_"), + two = @enumToInt(RegisterStopBitEnum.@"2_STOP_BITS_1_5_IF_"), + }; + + const RegisterParityEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .PS).field_type; + pub const Parity = enum(u2) { + odd = @enumToInt(RegisterParityEnum.@"ODD_PARITY_NUMBER_O"), + even = @enumToInt(RegisterParityEnum.@"EVEN_PARITY_NUMBER_"), + mark = @enumToInt(RegisterParityEnum.@"FORCED_1_STICK_PARIT"), + space = @enumToInt(RegisterParityEnum.@"FORCED_0_STICK_PARIT"), + }; +}; + pub fn Uart(comptime index: usize) type { return struct { const UARTn = switch (index) { @@ -98,20 +122,20 @@ pub fn Uart(comptime index: usize) type { micro.debug.write("0"); switch (index) { 0 => { - registers.SYSCON.PCONP.modify(.{ .PCUART0 = true }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = 0 }); + registers.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = .CCLK_DIV_4 }); }, 1 => { - registers.SYSCON.PCONP.modify(.{ .PCUART1 = true }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = 0 }); + registers.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = .CCLK_DIV_4 }); }, 2 => { - registers.SYSCON.PCONP.modify(.{ .PCUART2 = true }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = 0 }); + registers.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = .CCLK_DIV_4 }); }, 3 => { - registers.SYSCON.PCONP.modify(.{ .PCUART3 = true }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = 0 }); + registers.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); + registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = .CCLK_DIV_4 }); }, else => unreachable, } @@ -119,29 +143,17 @@ pub fn Uart(comptime index: usize) type { UARTn.LCR.write(.{ // 8N1 - .WLS = switch (config.data_bits) { - .@"5" => 0b00, - .@"6" => 0b01, - .@"7" => 0b10, - .@"8" => 0b11, - .@"9" => return error.UnsupportedWordSize, - }, - .SBS = switch (config.stop_bits) { - .one => false, - .two => true, - }, - .PE = (config.parity != .none), - .PS = switch (config.parity) { - .none, .odd => @as(u2, 0b00), - .even => 0b01, - .mark => 0b10, - .space => 0b11, - }, - .BC = false, - .DLAB = true, + .WLS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .WLS).field_type, @enumToInt(config.data_bits)), + .SBS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .SBS).field_type, @enumToInt(config.stop_bits)), + .PE = if (config.parity) |_| .ENABLE_PARITY_GENERA else .DISABLE_PARITY_GENER, + .PS = if (config.parity) |p| @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .PS).field_type, @enumToInt(p)) else .ODD_PARITY_NUMBER_O, + .BC = .DISABLE_BREAK_TRANSM, + .DLAB = .ENABLE_ACCESS_TO_DIV, }); micro.debug.write("2"); - UARTn.FCR.modify(.{ .FIFOEN = false }); + + // TODO: UARTN_FIFOS_ARE_DISA is not available in all uarts + //UARTn.FCR.modify(.{ .FIFOEN = .UARTN_FIFOS_ARE_DISA }); micro.debug.writer().print("clock: {} baud: {} ", .{ micro.clock.get(), @@ -156,13 +168,16 @@ pub fn Uart(comptime index: usize) type { UARTn.DLL.write(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); UARTn.DLM.write(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); - UARTn.LCR.modify(.{ .DLAB = false }); + UARTn.LCR.modify(.{ .DLAB = .DISABLE_ACCESS_TO_DI }); return Self{}; } pub fn canWrite(self: Self) bool { - return UARTn.LSR.read().THRE; + return switch (UARTn.LSR.read().THRE) { + .VALID => true, + .THR_IS_EMPTY_ => false, + }; } pub fn tx(self: Self, ch: u8) void { while (!self.canWrite()) {} // Wait for Previous transmission @@ -170,7 +185,10 @@ pub fn Uart(comptime index: usize) type { } pub fn canRead(self: Self) bool { - return UARTn.LSR.read().RDR; + return switch (UARTn.LSR.read().RDR) { + .EMPTY => false, + .NOTEMPTY => true, + }; } pub fn rx(self: Self) u8 { while (!self.canRead()) {} // Wait till the data is received diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 0b2aa99..e950a28 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -7,10 +7,17 @@ pub const WDT = extern struct { pub const Address: u32 = 0x40000000; // byte offset: 0 Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer. pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - WDEN: bool, // bit offset: 0 desc: Watchdog enable bit. This bit is Set Only. - WDRESET: bool, // bit offset: 1 desc: Watchdog reset enable bit. This bit is Set Only. See Table 652. - WDTOF: bool, // bit offset: 2 desc: Watchdog time-out flag. Set when the watchdog timer times out, cleared by software. - WDINT: bool, // bit offset: 3 desc: Watchdog interrupt flag. Cleared by software. + WDEN: enum(u1) { // bit offset: 0 desc: Watchdog enable bit. This bit is Set Only. + @"STOP" = 0, // desc: The watchdog timer is stopped. + @"RUN" = 1, // desc: The watchdog timer is running. + }, + WDRESET: enum(u1) { // bit offset: 1 desc: Watchdog reset enable bit. This bit is Set Only. See Table 652. + @"NORESET" = 0, // desc: A watchdog timeout will not cause a chip reset. + @"RESET" = 1, // desc: A watchdog timeout will cause a chip reset. + }, + WDTOF: u1, // bit offset: 2 desc: Watchdog time-out flag. Set when the watchdog timer times out, cleared by software. + WDINT: u1, // bit offset: 3 desc: Watchdog interrupt flag. Cleared by software. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -78,7 +85,14 @@ pub const WDT = extern struct { }); // byte offset: 16 Watchdog clock select register. pub const CLKSEL = mmio(Address + 0x00000010, 32, packed struct { - CLKSEL: u2, // bit offset: 0 desc: Selects source of WDT clock + CLKSEL: enum(u2) { // bit offset: 0 desc: Selects source of WDT clock + @"IRC" = 0, // desc: IRC + @"PCLK" = 1, // desc: Peripheral clock + @"RTCOSC" = 2, // desc: RTC oscillator + // @"RESERVED", // desc: Reserved. + _, // non-exhaustive + }, + // RESERVED: u30, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved29: u1 = 0, reserved28: u1 = 0, reserved27: u1 = 0, @@ -108,19 +122,23 @@ pub const WDT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - LOCK: bool, // bit offset: 31 desc: If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. + LOCK: enum(u1) { // bit offset: 31 desc: If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. + @"UNLOCKED" = 0, // desc: This bit is set to 0 on any reset. It cannot be cleared by software. + @"LOCKED" = 1, // desc: Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified. + }, }); }; pub const TIMER0 = extern struct { pub const Address: u32 = 0x40004000; // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -150,8 +168,9 @@ pub const TIMER0 = extern struct { }); // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -197,18 +216,55 @@ pub const TIMER0 = extern struct { }); // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 - MR0R: bool, // bit offset: 1 desc: Reset on MR0 - MR0S: bool, // bit offset: 2 desc: Stop on MR0 - MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 - MR1R: bool, // bit offset: 4 desc: Reset on MR1 - MR1S: bool, // bit offset: 5 desc: Stop on MR1 - MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 - MR2R: bool, // bit offset: 7 desc: Reset on MR2 - MR2S: bool, // bit offset: 8 desc: Stop on MR2. - MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 - MR3R: bool, // bit offset: 10 desc: Reset on MR3 - MR3S: bool, // bit offset: 11 desc: Stop on MR3 + MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. + }, + MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. + @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled + }, + MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -248,12 +304,31 @@ pub const TIMER0 = extern struct { }); // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge - CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge - CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event - CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge - CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge - CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event + @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event + @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -291,14 +366,35 @@ pub const TIMER0 = extern struct { }); // byte offset: 60 External Match Register. The EMR controls the external match pins. pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -322,8 +418,18 @@ pub const TIMER0 = extern struct { }); // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge + @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + }, + CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn + @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn + _, // non-exhaustive + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -358,12 +464,13 @@ pub const TIMER1 = extern struct { pub const Address: u32 = 0x40008000; // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -393,8 +500,9 @@ pub const TIMER1 = extern struct { }); // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -440,18 +548,55 @@ pub const TIMER1 = extern struct { }); // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 - MR0R: bool, // bit offset: 1 desc: Reset on MR0 - MR0S: bool, // bit offset: 2 desc: Stop on MR0 - MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 - MR1R: bool, // bit offset: 4 desc: Reset on MR1 - MR1S: bool, // bit offset: 5 desc: Stop on MR1 - MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 - MR2R: bool, // bit offset: 7 desc: Reset on MR2 - MR2S: bool, // bit offset: 8 desc: Stop on MR2. - MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 - MR3R: bool, // bit offset: 10 desc: Reset on MR3 - MR3S: bool, // bit offset: 11 desc: Stop on MR3 + MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. + }, + MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. + @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled + }, + MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -477,14 +622,6 @@ pub const TIMER1 = extern struct { pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. @@ -493,26 +630,37 @@ pub const TIMER1 = extern struct { pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge - CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge - CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event - CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge - CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge - CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event + @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event + @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -544,28 +692,41 @@ pub const TIMER1 = extern struct { pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); // byte offset: 60 External Match Register. The EMR controls the external match pins. pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -589,8 +750,18 @@ pub const TIMER1 = extern struct { }); // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge + @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + }, + CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn + @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn + _, // non-exhaustive + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -626,6 +797,7 @@ pub const UART0 = extern struct { // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). pub const RBR = mmio(Address + 0x00000000, 32, packed struct { RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -654,6 +826,7 @@ pub const UART0 = extern struct { // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). pub const THR = mmio(Address + 0x00000000, 32, packed struct { THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -682,6 +855,7 @@ pub const UART0 = extern struct { // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLL = mmio(Address + 0x00000000, 32, packed struct { DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -710,6 +884,7 @@ pub const UART0 = extern struct { // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLM = mmio(Address + 0x00000004, 32, packed struct { DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -737,16 +912,33 @@ pub const UART0 = extern struct { }); // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. + @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. + }, + THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. + @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. + }, + RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. + @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. - ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. + @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. + @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. + }, + ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. + @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -772,13 +964,24 @@ pub const UART0 = extern struct { }); // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. + @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. + }, + INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). + @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). + @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). + @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt + _, // non-exhaustive + }, + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -804,13 +1007,29 @@ pub const UART0 = extern struct { }); // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. - RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. - TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. - DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. + @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. + @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. + }, + RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. + }, + TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. + }, + DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, - RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). + @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). + @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). + @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -838,12 +1057,35 @@ pub const UART0 = extern struct { }); // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: u2, // bit offset: 0 desc: Word Length Select. - SBS: bool, // bit offset: 2 desc: Stop Bit Select - PE: bool, // bit offset: 3 desc: Parity Enable. - PS: u2, // bit offset: 4 desc: Parity Select - BC: bool, // bit offset: 6 desc: Break Control - DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. + @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length + @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length + @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length + @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length + }, + SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select + @"1_STOP_BIT_" = 0, // desc: 1 stop bit. + @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). + }, + PE: enum(u1) { // bit offset: 3 desc: Parity Enable. + @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. + @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. + }, + PS: enum(u2) { // bit offset: 4 desc: Parity Select + @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. + @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. + @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. + @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. + }, + BC: enum(u1) { // bit offset: 6 desc: Break Control + @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. + @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. + }, + DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit + @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. + @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -871,14 +1113,39 @@ pub const UART0 = extern struct { }); // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. + @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. + }, + OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + @"INACTIVE" = 0, // desc: Overrun error status is inactive. + @"ACTIVE" = 1, // desc: Overrun error status is active. + }, + PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Parity error status is inactive. + @"ACTIVE" = 1, // desc: Parity error status is active. + }, + FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Framing error status is inactive. + @"ACTIVE" = 1, // desc: Framing error status is active. + }, + BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Break interrupt status is inactive. + @"ACTIVE" = 1, // desc: Break interrupt status is active. + }, + THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + @"VALIDDATA" = 0, // desc: UnTHR contains valid data. + @"EMPTY" = 1, // desc: UnTHR is empty. + }, + TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. + @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. + }, + RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. + @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -907,6 +1174,7 @@ pub const UART0 = extern struct { // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { PAD: u8, // bit offset: 0 desc: A readable, writable byte. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -934,16 +1202,33 @@ pub const UART0 = extern struct { }); // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. - AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). + @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. + }, + MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. + @"MODE_0_" = 0, // desc: Mode 0. + @"MODE_1_" = 1, // desc: Mode 1. + }, + AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. + @"NO_RESTART_" = 0, // desc: No restart. + @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -971,6 +1256,7 @@ pub const UART0 = extern struct { pub const FDR = mmio(Address + 0x00000028, 32, packed struct { DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -998,6 +1284,7 @@ pub const UART0 = extern struct { }); // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. pub const TER = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -1005,7 +1292,8 @@ pub const UART0 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1033,12 +1321,29 @@ pub const UART0 = extern struct { }); // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: bool, // bit offset: 0 desc: NMM enable. - RXDIS: bool, // bit offset: 1 desc: Receiver enable. - AADEN: bool, // bit offset: 2 desc: AAD enable. + NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. + @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. + @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. + }, + RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. + @"ENABLED" = 0, // desc: The receiver is enabled. + @"DISABLED" = 1, // desc: The receiver is disabled. + }, + AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. + @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. + @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. + }, + // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - DCTRL: bool, // bit offset: 4 desc: Direction control enable. - OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. + @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. + @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. + }, + OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. + @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -1069,6 +1374,7 @@ pub const UART0 = extern struct { // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1097,6 +1403,7 @@ pub const UART0 = extern struct { // byte offset: 84 RS-485/EIA-485 direction control delay. pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1128,6 +1435,7 @@ pub const UART1 = extern struct { // byte offset: 0 DLAB =0 Receiver Buffer Register. Contains the next received character to be read. pub const RBR = mmio(Address + 0x00000000, 32, packed struct { RBR: u8, // bit offset: 0 desc: The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1156,6 +1464,7 @@ pub const UART1 = extern struct { // byte offset: 0 DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. pub const THR = mmio(Address + 0x00000000, 32, packed struct { THR: u8, // bit offset: 0 desc: Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1184,6 +1493,7 @@ pub const UART1 = extern struct { // byte offset: 0 DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. pub const DLL = mmio(Address + 0x00000000, 32, packed struct { DLLSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1212,6 +1522,7 @@ pub const UART1 = extern struct { // byte offset: 4 DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. pub const DLM = mmio(Address + 0x00000004, 32, packed struct { DLMSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1239,16 +1550,39 @@ pub const UART1 = extern struct { }); // byte offset: 4 DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. - THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. - RXIE: bool, // bit offset: 2 desc: RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. - MSIE: bool, // bit offset: 3 desc: Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. + RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. + @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. + @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. + }, + THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. + @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. + @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. + }, + RXIE: enum(u1) { // bit offset: 2 desc: RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. + @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. + @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. + }, + MSIE: enum(u1) { // bit offset: 3 desc: Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. + @"DISABLE_THE_MODEM_IN" = 0, // desc: Disable the modem interrupt. + @"ENABLE_THE_MODEM_INT" = 1, // desc: Enable the modem interrupt. + }, + // RESERVED: u3, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CTSIE: bool, // bit offset: 7 desc: CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. - ABEOIE: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. - ABTOIE: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + CTSIE: enum(u1) { // bit offset: 7 desc: CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. + @"DISABLE_THE_CTS_INTE" = 0, // desc: Disable the CTS interrupt. + @"ENABLE_THE_CTS_INTER" = 1, // desc: Enable the CTS interrupt. + }, + ABEOIE: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. + @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. + @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. + }, + ABTOIE: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. + @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -1274,13 +1608,25 @@ pub const UART1 = extern struct { }); // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. - INTID: u3, // bit offset: 1 desc: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). + INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. + @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. + @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. + }, + INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). + @"RLS" = 3, // desc: 1 - Receive Line Status (RLS). + @"RDA" = 2, // desc: 2a - Receive Data Available (RDA). + @"CTI" = 6, // desc: 2b - Character Time-out Indicator (CTI). + @"THRE" = 1, // desc: 3 - THRE Interrupt. + @"MODEM" = 0, // desc: 4 - Modem Interrupt. + _, // non-exhaustive + }, + // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, FIFOENABLE: u2, // bit offset: 6 desc: Copies of FCR[0]. - ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -1306,13 +1652,29 @@ pub const UART1 = extern struct { }); // byte offset: 8 FIFO Control Register. Controls UART1 FIFO usage and modes. pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: bool, // bit offset: 0 desc: FIFO enable. - RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. - TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. - DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. + FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO enable. + @"MUST_NOT_BE_USED_IN_" = 0, // desc: Must not be used in the application. + @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. + }, + RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. + }, + TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. + }, + DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. + // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. + RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. + @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). + @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). + @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). + @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1340,12 +1702,35 @@ pub const UART1 = extern struct { }); // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: u2, // bit offset: 0 desc: Word Length Select. - SBS: bool, // bit offset: 2 desc: Stop Bit Select. - PE: bool, // bit offset: 3 desc: Parity Enable. - PS: u2, // bit offset: 4 desc: Parity Select. - BC: bool, // bit offset: 6 desc: Break Control. - DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit (DLAB) + WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. + @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length. + @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length. + @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length. + @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length. + }, + SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select. + @"1_STOP_BIT_" = 0, // desc: 1 stop bit. + @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if LCR[1:0]=00). + }, + PE: enum(u1) { // bit offset: 3 desc: Parity Enable. + @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. + @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. + }, + PS: enum(u2) { // bit offset: 4 desc: Parity Select. + @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. + @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. + @"FORCED1STICK_PAR" = 2, // desc: Forced 1 stick parity. + @"FORCED0STICK_PAR" = 3, // desc: Forced 0 stick parity. + }, + BC: enum(u1) { // bit offset: 6 desc: Break Control. + @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. + @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. + }, + DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit (DLAB) + @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. + @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1373,14 +1758,26 @@ pub const UART1 = extern struct { }); // byte offset: 16 Modem Control Register. Contains controls for flow control handshaking and loopback mode. pub const MCR = mmio(Address + 0x00000010, 32, packed struct { - DTRCTRL: bool, // bit offset: 0 desc: DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. - RTSCTRL: bool, // bit offset: 1 desc: RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. + DTRCTRL: u1, // bit offset: 0 desc: DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. + RTSCTRL: u1, // bit offset: 1 desc: RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. + // RESERVED: u2, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - LMS: bool, // bit offset: 4 desc: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. - reserved2: u1 = 0, - RTSEN: bool, // bit offset: 6 desc: RTS enable. - CTSEN: bool, // bit offset: 7 desc: CTS enable. + LMS: enum(u1) { // bit offset: 4 desc: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. + @"DISABLE_MODEM_LOOPBA" = 0, // desc: Disable modem loopback mode. + @"ENABLE_MODEM_LOOPBAC" = 1, // desc: Enable modem loopback mode. + }, + // RESERVED: u1, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved3: u1 = 0, + RTSEN: enum(u1) { // bit offset: 6 desc: RTS enable. + @"DISABLE_AUTO_RTS_FLO" = 0, // desc: Disable auto-rts flow control. + @"ENABLE_AUTO_RTS_FLOW" = 1, // desc: Enable auto-rts flow control. + }, + CTSEN: enum(u1) { // bit offset: 7 desc: CTS enable. + @"DISABLE_AUTO_CTS_FLO" = 0, // desc: Disable auto-cts flow control. + @"ENABLE_AUTO_CTS_FLOW" = 1, // desc: Enable auto-cts flow control. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1408,14 +1805,39 @@ pub const UART1 = extern struct { }); // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: bool, // bit offset: 0 desc: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. - OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. - PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. - FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. - BI: bool, // bit offset: 4 desc: Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. - THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. - TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. - RXFE: bool, // bit offset: 7 desc: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. + RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. + @"EMPTY" = 0, // desc: The UART1 receiver FIFO is empty. + @"NOTEMPTY" = 1, // desc: The UART1 receiver FIFO is not empty. + }, + OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. + @"INACTIVE" = 0, // desc: Overrun error status is inactive. + @"ACTIVE" = 1, // desc: Overrun error status is active. + }, + PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. + @"INACTIVE" = 0, // desc: Parity error status is inactive. + @"ACTIVE" = 1, // desc: Parity error status is active. + }, + FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. + @"INACTIVE" = 0, // desc: Framing error status is inactive. + @"ACTIVE" = 1, // desc: Framing error status is active. + }, + BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. + @"INACTIVE" = 0, // desc: Break interrupt status is inactive. + @"ACTIVE" = 1, // desc: Break interrupt status is active. + }, + THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. + @"VALID" = 0, // desc: THR contains valid data. + @"THR_IS_EMPTY_" = 1, // desc: THR is empty. + }, + TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. + @"VALID" = 0, // desc: THR and/or the TSR contains valid data. + @"EMPTY" = 1, // desc: THR and the TSR are empty. + }, + RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. + @"NOERROR" = 0, // desc: RBR contains no UART1 RX errors or FCR[0]=0. + @"ERRORS" = 1, // desc: UART1 RBR contains at least one UART1 RX error. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1443,14 +1865,27 @@ pub const UART1 = extern struct { }); // byte offset: 24 Modem Status Register. Contains handshake signal status flags. pub const MSR = mmio(Address + 0x00000018, 32, packed struct { - DCTS: bool, // bit offset: 0 desc: Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. - DDSR: bool, // bit offset: 1 desc: Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. - TERI: bool, // bit offset: 2 desc: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. - DDCD: bool, // bit offset: 3 desc: Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. - CTS: bool, // bit offset: 4 desc: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. - DSR: bool, // bit offset: 5 desc: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. - RI: bool, // bit offset: 6 desc: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. - DCD: bool, // bit offset: 7 desc: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. + DCTS: enum(u1) { // bit offset: 0 desc: Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. + @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, CTS. + @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, CTS. + }, + DDSR: enum(u1) { // bit offset: 1 desc: Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. + @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DSR. + @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DSR. + }, + TERI: enum(u1) { // bit offset: 2 desc: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. + @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, RI. + @"LOW_TO_HIGH_TRANSITI" = 1, // desc: Low-to-high transition detected on RI. + }, + DDCD: enum(u1) { // bit offset: 3 desc: Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. + @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DCD. + @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DCD. + }, + CTS: u1, // bit offset: 4 desc: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. + DSR: u1, // bit offset: 5 desc: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. + RI: u1, // bit offset: 6 desc: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. + DCD: u1, // bit offset: 7 desc: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1479,6 +1914,7 @@ pub const UART1 = extern struct { // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { Pad: u8, // bit offset: 0 desc: A readable, writable byte. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1506,16 +1942,33 @@ pub const UART1 = extern struct { }); // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: bool, // bit offset: 0 desc: Auto-baud start bit. This bit is automatically cleared after auto-baud completion. - MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. - AUTORESTART: bool, // bit offset: 2 desc: Auto-baud restart bit. + START: enum(u1) { // bit offset: 0 desc: Auto-baud start bit. This bit is automatically cleared after auto-baud completion. + @"STOP" = 0, // desc: Auto-baud stop (auto-baud is not running). + @"START" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. + }, + MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. + @"MODE_0_" = 0, // desc: Mode 0. + @"MODE_1_" = 1, // desc: Mode 1. + }, + AUTORESTART: enum(u1) { // bit offset: 2 desc: Auto-baud restart bit. + @"NO_RESTART" = 0, // desc: No restart + @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UART1 Rx falling edge) + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only). - ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only). + ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only). + @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. + @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. + }, + ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only). + @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. + @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -1543,6 +1996,7 @@ pub const UART1 = extern struct { pub const FDR = mmio(Address + 0x00000028, 32, packed struct { DIVADDVAL: u4, // bit offset: 0 desc: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate. MULVAL: u4, // bit offset: 4 desc: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1570,6 +2024,7 @@ pub const UART1 = extern struct { }); // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. pub const TER = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -1577,7 +2032,8 @@ pub const UART1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. + TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1605,12 +2061,31 @@ pub const UART1 = extern struct { }); // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: bool, // bit offset: 0 desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. - RXDIS: bool, // bit offset: 1 desc: Receive enable. - AADEN: bool, // bit offset: 2 desc: Auto Address Detect (AAD) enable. - SEL: bool, // bit offset: 3 desc: Direction control. - DCTRL: bool, // bit offset: 4 desc: Direction control enable. - OINV: bool, // bit offset: 5 desc: Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. + NMMEN: enum(u1) { // bit offset: 0 desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_IN_THIS_MOD" = 1, // desc: Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. + }, + RXDIS: enum(u1) { // bit offset: 1 desc: Receive enable. + @"ENABLED_" = 0, // desc: Enabled. + @"DISABLED_" = 1, // desc: Disabled. + }, + AADEN: enum(u1) { // bit offset: 2 desc: Auto Address Detect (AAD) enable. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, + SEL: enum(u1) { // bit offset: 3 desc: Direction control. + @"RTS_IF_DIRECTION_CO" = 0, // desc: RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. + @"DTR_IF_DIRECTION_CO" = 1, // desc: DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. + }, + DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. + @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. + @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. + }, + OINV: enum(u1) { // bit offset: 5 desc: Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. + @"LOW_THE_DIRECTION_C" = 0, // desc: LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. + @"HIGH_THE_DIRECTION_" = 1, // desc: HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -1641,6 +2116,7 @@ pub const UART1 = extern struct { // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1669,6 +2145,7 @@ pub const UART1 = extern struct { // byte offset: 84 RS-485/EIA-485 direction control delay. pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { DLY: u8, // bit offset: 0 desc: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -1699,17 +2176,19 @@ pub const PWM1 = extern struct { pub const Address: u32 = 0x40018000; // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending. pub const IR = mmio(Address + 0x00000000, 32, packed struct { - PWMMR0INT: bool, // bit offset: 0 desc: Interrupt flag for PWM match channel 0. - PWMMR1INT: bool, // bit offset: 1 desc: Interrupt flag for PWM match channel 1. - PWMMR2INT: bool, // bit offset: 2 desc: Interrupt flag for PWM match channel 2. - PWMMR3INT: bool, // bit offset: 3 desc: Interrupt flag for PWM match channel 3. - PWMCAP0INT: bool, // bit offset: 4 desc: Interrupt flag for capture input 0 - PWMCAP1INT: bool, // bit offset: 5 desc: Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). + PWMMR0INT: u1, // bit offset: 0 desc: Interrupt flag for PWM match channel 0. + PWMMR1INT: u1, // bit offset: 1 desc: Interrupt flag for PWM match channel 1. + PWMMR2INT: u1, // bit offset: 2 desc: Interrupt flag for PWM match channel 2. + PWMMR3INT: u1, // bit offset: 3 desc: Interrupt flag for PWM match channel 3. + PWMCAP0INT: u1, // bit offset: 4 desc: Interrupt flag for capture input 0 + PWMCAP1INT: u1, // bit offset: 5 desc: Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). + // RESERVED: u2, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, - PWMMR4INT: bool, // bit offset: 8 desc: Interrupt flag for PWM match channel 4. - PWMMR5INT: bool, // bit offset: 9 desc: Interrupt flag for PWM match channel 5. - PWMMR6INT: bool, // bit offset: 10 desc: Interrupt flag for PWM match channel 6. + PWMMR4INT: u1, // bit offset: 8 desc: Interrupt flag for PWM match channel 4. + PWMMR5INT: u1, // bit offset: 9 desc: Interrupt flag for PWM match channel 5. + PWMMR6INT: u1, // bit offset: 10 desc: Interrupt flag for PWM match channel 6. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -1734,11 +2213,25 @@ pub const PWM1 = extern struct { }); // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CE: bool, // bit offset: 0 desc: Counter Enable - CR: bool, // bit offset: 1 desc: Counter Reset + CE: enum(u1) { // bit offset: 0 desc: Counter Enable + @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and PWM Prescale Counter are enabled for counting. + @"THE_COUNTERS_ARE_DIS" = 0, // desc: The counters are disabled. + }, + CR: enum(u1) { // bit offset: 1 desc: Counter Reset + @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. + @"CLEAR_RESET_" = 0, // desc: Clear reset. + }, + // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - PWMEN: bool, // bit offset: 3 desc: PWM Enable - MDIS: bool, // bit offset: 4 desc: Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). + PWMEN: enum(u1) { // bit offset: 3 desc: PWM Enable + @"PWM_MODE_IS_ENABLED_" = 1, // desc: PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. + @"TIMER_MODE_IS_ENABLE" = 0, // desc: Timer mode is enabled (counter resets to 0). + }, + MDIS: enum(u1) { // bit offset: 4 desc: Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). + @"MASTER_USE_PWM0_IS_" = 1, // desc: Master use. PWM0 is the master, and both PWMs are enabled for counting. + @"INDIVIDUAL_USE_THE_" = 0, // desc: Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs. + }, + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -1781,27 +2274,91 @@ pub const PWM1 = extern struct { }); // byte offset: 20 Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs. pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - PWMMR0I: bool, // bit offset: 0 desc: Interrupt PWM0 - PWMMR0R: bool, // bit offset: 1 desc: Reset PWM0 - PWMMR0S: bool, // bit offset: 2 desc: Stop PWM0 - PWMMR1I: bool, // bit offset: 3 desc: Interrupt PWM1 - PWMMR1R: bool, // bit offset: 4 desc: Reset PWM1 - PWMMR1S: bool, // bit offset: 5 desc: Stop PWM1 - PWMMR2I: bool, // bit offset: 6 desc: Interrupt PWM0 - PWMMR2R: bool, // bit offset: 7 desc: Reset PWM0 - PWMMR2S: bool, // bit offset: 8 desc: Stop PWM0 - PWMMR3I: bool, // bit offset: 9 desc: Interrupt PWM3 - PWMMR3R: bool, // bit offset: 10 desc: Reset PWM3 - PWMMR3S: bool, // bit offset: 11 desc: Stop PWM0 - PWMMR4I: bool, // bit offset: 12 desc: Interrupt PWM4 - PWMMR4R: bool, // bit offset: 13 desc: Reset PWM4 - PWMMR4S: bool, // bit offset: 14 desc: Stop PWM4 - PWMMR5I: bool, // bit offset: 15 desc: Interrupt PWM5 - PWMMR5R: bool, // bit offset: 16 desc: Reset PWM5 - PWMMR5S: bool, // bit offset: 17 desc: Stop PWM5 - PWMMR6I: bool, // bit offset: 18 desc: Interrupt PWM6 - PWMMR6R: bool, // bit offset: 19 desc: Reset PWM6 - PWMMR6S: bool, // bit offset: 20 desc: Stop PWM6 + PWMMR0I: enum(u1) { // bit offset: 0 desc: Interrupt PWM0 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR0" = 1, // desc: Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC. + }, + PWMMR0R: enum(u1) { // bit offset: 1 desc: Reset PWM0 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR0_THE" = 1, // desc: Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. + }, + PWMMR0S: enum(u1) { // bit offset: 2 desc: Stop PWM0 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR0_THE_" = 1, // desc: Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. + }, + PWMMR1I: enum(u1) { // bit offset: 3 desc: Interrupt PWM1 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR1" = 1, // desc: Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. + }, + PWMMR1R: enum(u1) { // bit offset: 4 desc: Reset PWM1 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR1_THE" = 1, // desc: Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. + }, + PWMMR1S: enum(u1) { // bit offset: 5 desc: Stop PWM1 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR1_THE_" = 1, // desc: Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC. + }, + PWMMR2I: enum(u1) { // bit offset: 6 desc: Interrupt PWM0 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR2" = 1, // desc: Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC. + }, + PWMMR2R: enum(u1) { // bit offset: 7 desc: Reset PWM0 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR2_THE" = 1, // desc: Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. + }, + PWMMR2S: enum(u1) { // bit offset: 8 desc: Stop PWM0 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR2_THE_" = 1, // desc: Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. + }, + PWMMR3I: enum(u1) { // bit offset: 9 desc: Interrupt PWM3 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR3" = 1, // desc: Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC. + }, + PWMMR3R: enum(u1) { // bit offset: 10 desc: Reset PWM3 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR3_THE" = 1, // desc: Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. + }, + PWMMR3S: enum(u1) { // bit offset: 11 desc: Stop PWM0 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR3_THE_" = 1, // desc: Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. + }, + PWMMR4I: enum(u1) { // bit offset: 12 desc: Interrupt PWM4 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR4" = 1, // desc: Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC. + }, + PWMMR4R: enum(u1) { // bit offset: 13 desc: Reset PWM4 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR4_THE" = 1, // desc: Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. + }, + PWMMR4S: enum(u1) { // bit offset: 14 desc: Stop PWM4 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR4_THE_" = 1, // desc: Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC. + }, + PWMMR5I: enum(u1) { // bit offset: 15 desc: Interrupt PWM5 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR5" = 1, // desc: Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC. + }, + PWMMR5R: enum(u1) { // bit offset: 16 desc: Reset PWM5 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR5_THE" = 1, // desc: Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. + }, + PWMMR5S: enum(u1) { // bit offset: 17 desc: Stop PWM5 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR5_THE_" = 1, // desc: Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC. + }, + PWMMR6I: enum(u1) { // bit offset: 18 desc: Interrupt PWM6 + @"DISABLED_" = 0, // desc: Disabled. + @"INTERRUPT_ON_PWMMR6" = 1, // desc: Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC. + }, + PWMMR6R: enum(u1) { // bit offset: 19 desc: Reset PWM6 + @"DISABLED_" = 0, // desc: Disabled. + @"RESET_ON_PWMMR6_THE" = 1, // desc: Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. + }, + PWMMR6S: enum(u1) { // bit offset: 20 desc: Stop PWM6 + @"DISABLED" = 0, // desc: Disabled + @"STOP_ON_PWMMR6_THE_" = 1, // desc: Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC. + }, + // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -1832,12 +2389,31 @@ pub const PWM1 = extern struct { }); // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event. pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0_R: bool, // bit offset: 0 desc: Capture on PWMn_CAP0 rising edge - CAP0_F: bool, // bit offset: 1 desc: Capture on PWMn_CAP0 falling edge - CAP0_I: bool, // bit offset: 2 desc: Interrupt on PWMn_CAP0 event - CAP1_R: bool, // bit offset: 3 desc: Capture on PWMn_CAP1 rising edge. Reserved for PWM0. - CAP1_F: bool, // bit offset: 4 desc: Capture on PWMn_CAP1 falling edge. Reserved for PWM0. - CAP1_I: bool, // bit offset: 5 desc: Interrupt on PWMn_CAP1 event. Reserved for PWM0. + CAP0_R: enum(u1) { // bit offset: 0 desc: Capture on PWMn_CAP0 rising edge + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC. + }, + CAP0_F: enum(u1) { // bit offset: 1 desc: Capture on PWMn_CAP0 falling edge + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC. + }, + CAP0_I: enum(u1) { // bit offset: 2 desc: Interrupt on PWMn_CAP0 event + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"INTERRUPT_A_CR0_LOA" = 1, // desc: Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt. + }, + CAP1_R: enum(u1) { // bit offset: 3 desc: Capture on PWMn_CAP1 rising edge. Reserved for PWM0. + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC. + }, + CAP1_F: enum(u1) { // bit offset: 4 desc: Capture on PWMn_CAP1 falling edge. Reserved for PWM0. + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC. + }, + CAP1_I: enum(u1) { // bit offset: 5 desc: Interrupt on PWMn_CAP1 event. Reserved for PWM0. + @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. + @"INTERRUPT_A_CR1_LOA" = 1, // desc: Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -1867,39 +2443,145 @@ pub const PWM1 = extern struct { }); // byte offset: 44 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. - PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. - PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. - PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. - PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. + reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. - PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. - PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. - PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. - PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. - PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 48 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. - PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. - PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. - PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. - PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. + reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. - PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. - PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. - PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. - PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. - PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 64 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. pub const MR4 = mmio(Address + 0x00000040, 32, packed struct { @@ -1915,21 +2597,57 @@ pub const PWM1 = extern struct { }); // byte offset: 76 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. pub const PCR = mmio(Address + 0x0000004c, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - PWMSEL2: bool, // bit offset: 2 desc: PWM[2] output single/double edge mode control. - PWMSEL3: bool, // bit offset: 3 desc: PWM[3] output edge control. - PWMSEL4: bool, // bit offset: 4 desc: PWM[4] output edge control. - PWMSEL5: bool, // bit offset: 5 desc: PWM[5] output edge control. - PWMSEL6: bool, // bit offset: 6 desc: PWM[6] output edge control. + PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. + @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. + @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. + }, + // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. + reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - PWMENA1: bool, // bit offset: 9 desc: PWM[1] output enable control. - PWMENA2: bool, // bit offset: 10 desc: PWM[2] output enable control. - PWMENA3: bool, // bit offset: 11 desc: PWM[3] output enable control. - PWMENA4: bool, // bit offset: 12 desc: PWM[4] output enable control. - PWMENA5: bool, // bit offset: 13 desc: PWM[5] output enable control. - PWMENA6: bool, // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. + @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. + @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. + }, + // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -1950,13 +2668,14 @@ pub const PWM1 = extern struct { }); // byte offset: 80 Load Enable Register. Enables use of updated PWM match values. pub const LER = mmio(Address + 0x00000050, 32, packed struct { - MAT0LATCHEN: bool, // bit offset: 0 desc: Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. - MAT1LATCHEN: bool, // bit offset: 1 desc: Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. - MAT2LATCHEN: bool, // bit offset: 2 desc: Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. - MAT3LATCHEN: bool, // bit offset: 3 desc: Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. - MAT4LATCHEN: bool, // bit offset: 4 desc: Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. - MAT5LATCHEN: bool, // bit offset: 5 desc: Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. - MAT6LATCHEN: bool, // bit offset: 6 desc: Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. + MAT0LATCHEN: u1, // bit offset: 0 desc: Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. + MAT1LATCHEN: u1, // bit offset: 1 desc: Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. + MAT2LATCHEN: u1, // bit offset: 2 desc: Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. + MAT3LATCHEN: u1, // bit offset: 3 desc: Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. + MAT4LATCHEN: u1, // bit offset: 4 desc: Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. + MAT5LATCHEN: u1, // bit offset: 5 desc: Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. + MAT6LATCHEN: u1, // bit offset: 6 desc: Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. + // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -1985,8 +2704,17 @@ pub const PWM1 = extern struct { }); // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - MOD: u2, // bit offset: 0 desc: Counter/ Timer Mode - CIS: u2, // bit offset: 2 desc: Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. + MOD: enum(u2) { // bit offset: 0 desc: Counter/ Timer Mode + @"TIMER_MODE_THE_TC_I" = 0, // desc: Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register. + @"RISING_EDGE_COUNTER_" = 1, // desc: Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2. + @"FALLING_EDGE_COUNTER" = 2, // desc: Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2. + @"DUAL_EDGE_COUNTER_MO" = 3, // desc: Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2. + }, + CIS: enum(u2) { // bit offset: 2 desc: Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. + @"FOR_PWM0_00_EQ_PWM0_" = 0, // desc: For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved) + _, // non-exhaustive + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -2021,13 +2749,15 @@ pub const I2C0 = extern struct { pub const Address: u32 = 0x4001c000; // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - AA: bool, // bit offset: 2 desc: Assert acknowledge flag. - SI: bool, // bit offset: 3 desc: I2C interrupt flag. - STO: bool, // bit offset: 4 desc: STOP flag. - STA: bool, // bit offset: 5 desc: START flag. - I2EN: bool, // bit offset: 6 desc: I2C interface enable. + AA: u1, // bit offset: 2 desc: Assert acknowledge flag. + SI: u1, // bit offset: 3 desc: I2C interrupt flag. + STO: u1, // bit offset: 4 desc: STOP flag. + STA: u1, // bit offset: 5 desc: START flag. + I2EN: u1, // bit offset: 6 desc: I2C interface enable. + // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -2056,10 +2786,12 @@ pub const I2C0 = extern struct { }); // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2088,6 +2820,7 @@ pub const I2C0 = extern struct { // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. pub const DAT = mmio(Address + 0x00000008, 32, packed struct { Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2115,8 +2848,9 @@ pub const I2C0 = extern struct { }); // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2145,6 +2879,7 @@ pub const I2C0 = extern struct { // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2165,6 +2900,7 @@ pub const I2C0 = extern struct { // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2184,13 +2920,17 @@ pub const I2C0 = extern struct { }); // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. - reserved2: u1 = 0, - STAC: bool, // bit offset: 5 desc: START flag Clear bit. - I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. + AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. + // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved3: u1 = 0, + STAC: u1, // bit offset: 5 desc: START flag Clear bit. + I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. + // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -2219,9 +2959,19 @@ pub const I2C0 = extern struct { }); // byte offset: 28 Monitor mode control register. pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. - ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. - MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. + MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. + @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. + @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. + }, + ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] + }, + MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -2254,22 +3004,98 @@ pub const I2C0 = extern struct { }); // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2297,38 +3123,173 @@ pub const I2C0 = extern struct { }); // byte offset: 48 I2C Slave address mask register pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 52 I2C Slave address mask register pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 56 I2C Slave address mask register pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 60 I2C Slave address mask register pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); }; pub const SPI = extern struct { pub const Address: u32 = 0x40020000; // byte offset: 0 SPI Control Register. This register controls the operation of the SPI. pub const CR = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - BITENABLE: bool, // bit offset: 2 desc: The SPI controller sends and receives 8 bits of data per transfer. - CPHA: bool, // bit offset: 3 desc: Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. - CPOL: bool, // bit offset: 4 desc: Clock polarity control. - MSTR: bool, // bit offset: 5 desc: Master mode select. - LSBF: bool, // bit offset: 6 desc: LSB First controls which direction each byte is shifted when transferred. - SPIE: bool, // bit offset: 7 desc: Serial peripheral interrupt enable. - BITS: u4, // bit offset: 8 desc: When bit 2 of this register is 1, this field controls the number of bits per transfer: + BITENABLE: enum(u1) { // bit offset: 2 desc: The SPI controller sends and receives 8 bits of data per transfer. + @"THE_SPI_CONTROLLER_S" = 1, // desc: The SPI controller sends and receives the number of bits selected by bits 11:8. + _, // non-exhaustive + }, + CPHA: enum(u1) { // bit offset: 3 desc: Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. + @"FIRST_EDGE" = 0, // desc: Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. + @"SECOND_EDGE" = 1, // desc: Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. + }, + CPOL: enum(u1) { // bit offset: 4 desc: Clock polarity control. + @"SCK_IS_ACTIVE_HIGH_" = 0, // desc: SCK is active high. + @"SCK_IS_ACTIVE_LOW_" = 1, // desc: SCK is active low. + }, + MSTR: enum(u1) { // bit offset: 5 desc: Master mode select. + @"SLAVE" = 0, // desc: The SPI operates in Slave mode. + @"MASTER" = 1, // desc: The SPI operates in Master mode. + }, + LSBF: enum(u1) { // bit offset: 6 desc: LSB First controls which direction each byte is shifted when transferred. + @"MSB" = 0, // desc: SPI data is transferred MSB (bit 7) first. + @"LSB" = 1, // desc: SPI data is transferred LSB (bit 0) first. + }, + SPIE: enum(u1) { // bit offset: 7 desc: Serial peripheral interrupt enable. + @"INTBLOCK" = 0, // desc: SPI interrupts are inhibited. + @"HWINT" = 1, // desc: A hardware interrupt is generated each time the SPIF or MODF bits are activated. + }, + BITS: enum(u4) { // bit offset: 8 desc: When bit 2 of this register is 1, this field controls the number of bits per transfer: + @"8_BITS_PER_TRANSFER" = 8, // desc: 8 bits per transfer + @"9_BITS_PER_TRANSFER" = 9, // desc: 9 bits per transfer + @"10_BITS_PER_TRANSFER" = 10, // desc: 10 bits per transfer + @"11_BITS_PER_TRANSFER" = 11, // desc: 11 bits per transfer + @"12_BITS_PER_TRANSFER" = 12, // desc: 12 bits per transfer + @"13_BITS_PER_TRANSFER" = 13, // desc: 13 bits per transfer + @"14_BITS_PER_TRANSFER" = 14, // desc: 14 bits per transfer + @"15_BITS_PER_TRANSFER" = 15, // desc: 15 bits per transfer + @"16_BITS_PER_TRANSFER" = 0, // desc: 16 bits per transfer + _, // non-exhaustive + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -2352,14 +3313,16 @@ pub const SPI = extern struct { }); // byte offset: 4 SPI Status Register. This register shows the status of the SPI. pub const SR = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABRT: bool, // bit offset: 3 desc: Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. - MODF: bool, // bit offset: 4 desc: Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. - ROVR: bool, // bit offset: 5 desc: Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. - WCOL: bool, // bit offset: 6 desc: Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. - SPIF: bool, // bit offset: 7 desc: SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. + ABRT: u1, // bit offset: 3 desc: Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. + MODF: u1, // bit offset: 4 desc: Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. + ROVR: u1, // bit offset: 5 desc: Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. + WCOL: u1, // bit offset: 6 desc: Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. + SPIF: u1, // bit offset: 7 desc: SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2389,6 +3352,7 @@ pub const SPI = extern struct { pub const DR = mmio(Address + 0x00000008, 32, packed struct { DATALOW: u8, // bit offset: 0 desc: SPI Bi-directional data port. DATAHIGH: u8, // bit offset: 8 desc: If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2409,6 +3373,7 @@ pub const SPI = extern struct { // byte offset: 12 SPI Clock Counter Register. This register controls the frequency of a master's SCK0. pub const CCR = mmio(Address + 0x0000000c, 32, packed struct { COUNTER: u8, // bit offset: 0 desc: SPI0 Clock counter setting. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2436,7 +3401,9 @@ pub const SPI = extern struct { }); // byte offset: 28 SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. pub const INT = mmio(Address + 0x0000001c, 32, packed struct { - SPIF: bool, // bit offset: 0 desc: SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. + SPIF: u1, // bit offset: 0 desc: SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. + // RESERVED: u7, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -2474,8 +3441,9 @@ pub const RTC = extern struct { pub const Address: u32 = 0x40024000; // byte offset: 0 Interrupt Location Register pub const ILR = mmio(Address + 0x00000000, 32, packed struct { - RTCCIF: bool, // bit offset: 0 desc: When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. - RTCALF: bool, // bit offset: 1 desc: When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. + RTCCIF: u1, // bit offset: 0 desc: When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. + RTCALF: u1, // bit offset: 1 desc: When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. + // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2509,11 +3477,22 @@ pub const RTC = extern struct { }); // byte offset: 8 Clock Control Register pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - CLKEN: bool, // bit offset: 0 desc: Clock Enable. - CTCRST: bool, // bit offset: 1 desc: CTC Reset. + CLKEN: enum(u1) { // bit offset: 0 desc: Clock Enable. + @"THE_TIME_COUNTERS_AR" = 1, // desc: The time counters are enabled. + @"THE_TIME_COUNTERS_AR" = 0, // desc: The time counters are disabled so that they may be initialized. + }, + CTCRST: enum(u1) { // bit offset: 1 desc: CTC Reset. + @"RESET" = 1, // desc: When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. + @"NO_EFFECT_" = 0, // desc: No effect. + }, + // RESERVED: u2, // bit offset: 2 desc: Internal test mode controls. These bits must be 0 for normal RTC operation. reserved2: u1 = 0, reserved1: u1 = 0, - CCALEN: bool, // bit offset: 4 desc: Calibration counter enable. + CCALEN: enum(u1) { // bit offset: 4 desc: Calibration counter enable. + @"THE_CALIBRATION_COUN" = 1, // desc: The calibration counter is disabled and reset to zero. + @"THE_CALIBRATION_COUN" = 0, // desc: The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5. + }, + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -2544,14 +3523,15 @@ pub const RTC = extern struct { }); // byte offset: 12 Counter Increment Interrupt Register pub const CIIR = mmio(Address + 0x0000000c, 32, packed struct { - IMSEC: bool, // bit offset: 0 desc: When 1, an increment of the Second value generates an interrupt. - IMMIN: bool, // bit offset: 1 desc: When 1, an increment of the Minute value generates an interrupt. - IMHOUR: bool, // bit offset: 2 desc: When 1, an increment of the Hour value generates an interrupt. - IMDOM: bool, // bit offset: 3 desc: When 1, an increment of the Day of Month value generates an interrupt. - IMDOW: bool, // bit offset: 4 desc: When 1, an increment of the Day of Week value generates an interrupt. - IMDOY: bool, // bit offset: 5 desc: When 1, an increment of the Day of Year value generates an interrupt. - IMMON: bool, // bit offset: 6 desc: When 1, an increment of the Month value generates an interrupt. - IMYEAR: bool, // bit offset: 7 desc: When 1, an increment of the Year value generates an interrupt. + IMSEC: u1, // bit offset: 0 desc: When 1, an increment of the Second value generates an interrupt. + IMMIN: u1, // bit offset: 1 desc: When 1, an increment of the Minute value generates an interrupt. + IMHOUR: u1, // bit offset: 2 desc: When 1, an increment of the Hour value generates an interrupt. + IMDOM: u1, // bit offset: 3 desc: When 1, an increment of the Day of Month value generates an interrupt. + IMDOW: u1, // bit offset: 4 desc: When 1, an increment of the Day of Week value generates an interrupt. + IMDOY: u1, // bit offset: 5 desc: When 1, an increment of the Day of Year value generates an interrupt. + IMMON: u1, // bit offset: 6 desc: When 1, an increment of the Month value generates an interrupt. + IMYEAR: u1, // bit offset: 7 desc: When 1, an increment of the Year value generates an interrupt. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2579,14 +3559,15 @@ pub const RTC = extern struct { }); // byte offset: 16 Alarm Mask Register pub const AMR = mmio(Address + 0x00000010, 32, packed struct { - AMRSEC: bool, // bit offset: 0 desc: When 1, the Second value is not compared for the alarm. - AMRMIN: bool, // bit offset: 1 desc: When 1, the Minutes value is not compared for the alarm. - AMRHOUR: bool, // bit offset: 2 desc: When 1, the Hour value is not compared for the alarm. - AMRDOM: bool, // bit offset: 3 desc: When 1, the Day of Month value is not compared for the alarm. - AMRDOW: bool, // bit offset: 4 desc: When 1, the Day of Week value is not compared for the alarm. - AMRDOY: bool, // bit offset: 5 desc: When 1, the Day of Year value is not compared for the alarm. - AMRMON: bool, // bit offset: 6 desc: When 1, the Month value is not compared for the alarm. - AMRYEAR: bool, // bit offset: 7 desc: When 1, the Year value is not compared for the alarm. + AMRSEC: u1, // bit offset: 0 desc: When 1, the Second value is not compared for the alarm. + AMRMIN: u1, // bit offset: 1 desc: When 1, the Minutes value is not compared for the alarm. + AMRHOUR: u1, // bit offset: 2 desc: When 1, the Hour value is not compared for the alarm. + AMRDOM: u1, // bit offset: 3 desc: When 1, the Day of Month value is not compared for the alarm. + AMRDOW: u1, // bit offset: 4 desc: When 1, the Day of Week value is not compared for the alarm. + AMRDOY: u1, // bit offset: 5 desc: When 1, the Day of Year value is not compared for the alarm. + AMRMON: u1, // bit offset: 6 desc: When 1, the Month value is not compared for the alarm. + AMRYEAR: u1, // bit offset: 7 desc: When 1, the Year value is not compared for the alarm. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2615,16 +3596,20 @@ pub const RTC = extern struct { // byte offset: 20 Consolidated Time Register 0 pub const CTIME0 = mmio(Address + 0x00000014, 32, packed struct { SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + // RESERVED: u2, // bit offset: 6 desc: Reserved. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59 - reserved8: u1 = 0, - reserved7: u1 = 0, + // RESERVED: u2, // bit offset: 14 desc: Reserved. The value read from a reserved bit is not defined. + reserved4: u1 = 0, + reserved3: u1 = 0, HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23 - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, + // RESERVED: u3, // bit offset: 21 desc: Reserved. The value read from a reserved bit is not defined. + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6 + // RESERVED: u5, // bit offset: 27 desc: Reserved. The value read from a reserved bit is not defined. padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, @@ -2634,15 +3619,18 @@ pub const RTC = extern struct { // byte offset: 24 Consolidated Time Register 1 pub const CTIME1 = mmio(Address + 0x00000018, 32, packed struct { DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + // RESERVED: u3, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12. - reserved8: u1 = 0, + // RESERVED: u4, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, + reserved4: u1 = 0, YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095. + // RESERVED: u4, // bit offset: 28 desc: Reserved. The value read from a reserved bit is not defined. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -2651,6 +3639,7 @@ pub const RTC = extern struct { // byte offset: 28 Consolidated Time Register 2 pub const CTIME2 = mmio(Address + 0x0000001c, 32, packed struct { DOY: u12, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -2675,6 +3664,7 @@ pub const RTC = extern struct { // byte offset: 32 Seconds Counter pub const SEC = mmio(Address + 0x00000020, 32, packed struct { SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2705,6 +3695,7 @@ pub const RTC = extern struct { // byte offset: 36 Minutes Register pub const MIN = mmio(Address + 0x00000024, 32, packed struct { MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2735,6 +3726,7 @@ pub const RTC = extern struct { // byte offset: 40 Hours Register pub const HRS = mmio(Address + 0x00000028, 32, packed struct { HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -2766,6 +3758,7 @@ pub const RTC = extern struct { // byte offset: 44 Day of Month Register pub const DOM = mmio(Address + 0x0000002c, 32, packed struct { DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -2797,6 +3790,7 @@ pub const RTC = extern struct { // byte offset: 48 Day of Week Register pub const DOW = mmio(Address + 0x00000030, 32, packed struct { DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. + // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -2830,6 +3824,7 @@ pub const RTC = extern struct { // byte offset: 52 Day of Year Register pub const DOY = mmio(Address + 0x00000034, 32, packed struct { DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -2857,6 +3852,7 @@ pub const RTC = extern struct { // byte offset: 56 Months Register pub const MONTH = mmio(Address + 0x00000038, 32, packed struct { MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -2889,6 +3885,7 @@ pub const RTC = extern struct { // byte offset: 60 Years Register pub const YEAR = mmio(Address + 0x0000003c, 32, packed struct { YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -2913,7 +3910,10 @@ pub const RTC = extern struct { // byte offset: 64 Calibration Value Register pub const CALIBRATION = mmio(Address + 0x00000040, 32, packed struct { CALVAL: u17, // bit offset: 0 desc: If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. - CALDIR: bool, // bit offset: 17 desc: Calibration direction + CALDIR: enum(u1) { // bit offset: 17 desc: Calibration direction + @"BACKWARD_CALIBRATION" = 1, // desc: Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. + @"FORWARD_CALIBRATION_" = 0, // desc: Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. + }, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -2951,11 +3951,13 @@ pub const RTC = extern struct { }); // byte offset: 88 RTC Auxiliary Enable register pub const RTC_AUXEN = mmio(Address + 0x00000058, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTC_OSCFEN: bool, // bit offset: 4 desc: Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. + RTC_OSCFEN: u1, // bit offset: 4 desc: Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -2986,13 +3988,16 @@ pub const RTC = extern struct { }); // byte offset: 92 RTC Auxiliary control register pub const RTC_AUX = mmio(Address + 0x0000005c, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTC_OSCF: bool, // bit offset: 4 desc: RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. - reserved2: u1 = 0, - RTC_PDOUT: bool, // bit offset: 6 desc: When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. + RTC_OSCF: u1, // bit offset: 4 desc: RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. + // RESERVED: u1, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. + reserved5: u1 = 0, + RTC_PDOUT: u1, // bit offset: 6 desc: When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. + // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -3022,6 +4027,7 @@ pub const RTC = extern struct { // byte offset: 96 Alarm value for Seconds pub const ASEC = mmio(Address + 0x00000060, 32, packed struct { SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -3052,6 +4058,7 @@ pub const RTC = extern struct { // byte offset: 100 Alarm value for Minutes pub const AMIN = mmio(Address + 0x00000064, 32, packed struct { MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -3082,6 +4089,7 @@ pub const RTC = extern struct { // byte offset: 104 Alarm value for Hours pub const AHRS = mmio(Address + 0x00000068, 32, packed struct { HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -3113,6 +4121,7 @@ pub const RTC = extern struct { // byte offset: 108 Alarm value for Day of Month pub const ADOM = mmio(Address + 0x0000006c, 32, packed struct { DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -3144,6 +4153,7 @@ pub const RTC = extern struct { // byte offset: 112 Alarm value for Day of Week pub const ADOW = mmio(Address + 0x00000070, 32, packed struct { DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. + // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -3177,6 +4187,7 @@ pub const RTC = extern struct { // byte offset: 116 Alarm value for Day of Year pub const ADOY = mmio(Address + 0x00000074, 32, packed struct { DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). + // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -3204,6 +4215,7 @@ pub const RTC = extern struct { // byte offset: 120 Alarm value for Months pub const AMON = mmio(Address + 0x00000078, 32, packed struct { MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -3236,6 +4248,7 @@ pub const RTC = extern struct { // byte offset: 124 Alarm value for Year pub const AYRS = mmio(Address + 0x0000007c, 32, packed struct { YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -3262,9 +4275,17 @@ pub const GPIOINT = extern struct { pub const Address: u32 = 0x40028080; // byte offset: 0 GPIO overall Interrupt Status. pub const STATUS = mmio(Address + 0x00000000, 32, packed struct { - P0INT: bool, // bit offset: 0 desc: Port 0 GPIO interrupt pending. + P0INT: enum(u1) { // bit offset: 0 desc: Port 0 GPIO interrupt pending. + @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 0. + @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 0. + }, + // RESERVED: u1, // bit offset: 1 desc: Reserved. The value read from a reserved bit is not defined. reserved1: u1 = 0, - P2INT: bool, // bit offset: 2 desc: Port 2 GPIO interrupt pending. + P2INT: enum(u1) { // bit offset: 2 desc: Port 2 GPIO interrupt pending. + @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 2. + @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 2. + }, + // RESERVED: u30, // bit offset: 2 desc: Reserved. The value read from a reserved bit is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -3297,195 +4318,201 @@ pub const GPIOINT = extern struct { }); // byte offset: 4 GPIO Interrupt Status for Rising edge for Port 0. pub const STATR0 = mmio(Address + 0x00000004, 32, packed struct { - P0_0REI: bool, // bit offset: 0 desc: Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_1REI: bool, // bit offset: 1 desc: Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_2REI: bool, // bit offset: 2 desc: Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_3REI: bool, // bit offset: 3 desc: Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_4REI: bool, // bit offset: 4 desc: Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_5REI: bool, // bit offset: 5 desc: Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_6REI: bool, // bit offset: 6 desc: Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_7REI: bool, // bit offset: 7 desc: Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_8REI: bool, // bit offset: 8 desc: Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_9REI: bool, // bit offset: 9 desc: Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_10REI: bool, // bit offset: 10 desc: Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_11REI: bool, // bit offset: 11 desc: Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_12REI: bool, // bit offset: 12 desc: Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_13REI: bool, // bit offset: 13 desc: Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_14REI: bool, // bit offset: 14 desc: Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_15REI: bool, // bit offset: 15 desc: Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_16REI: bool, // bit offset: 16 desc: Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_17REI: bool, // bit offset: 17 desc: Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_18REI: bool, // bit offset: 18 desc: Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_19REI: bool, // bit offset: 19 desc: Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_20REI: bool, // bit offset: 20 desc: Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_21REI: bool, // bit offset: 21 desc: Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_22REI: bool, // bit offset: 22 desc: Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_23REI: bool, // bit offset: 23 desc: Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_24REI: bool, // bit offset: 24 desc: Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_25REI: bool, // bit offset: 25 desc: Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_26REI: bool, // bit offset: 26 desc: Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_27REI: bool, // bit offset: 27 desc: Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_28REI: bool, // bit offset: 28 desc: Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_29REI: bool, // bit offset: 29 desc: Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_30REI: bool, // bit offset: 30 desc: Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_14REI: u1, // bit offset: 14 desc: Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_15REI: u1, // bit offset: 15 desc: Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_16REI: u1, // bit offset: 16 desc: Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_17REI: u1, // bit offset: 17 desc: Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_18REI: u1, // bit offset: 18 desc: Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_19REI: u1, // bit offset: 19 desc: Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_20REI: u1, // bit offset: 20 desc: Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_21REI: u1, // bit offset: 21 desc: Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_22REI: u1, // bit offset: 22 desc: Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_23REI: u1, // bit offset: 23 desc: Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_24REI: u1, // bit offset: 24 desc: Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_25REI: u1, // bit offset: 25 desc: Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_26REI: u1, // bit offset: 26 desc: Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_27REI: u1, // bit offset: 27 desc: Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_28REI: u1, // bit offset: 28 desc: Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_29REI: u1, // bit offset: 29 desc: Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P0_30REI: u1, // bit offset: 30 desc: Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 8 GPIO Interrupt Status for Falling edge for Port 0. pub const STATF0 = mmio(Address + 0x00000008, 32, packed struct { - P0_0FEI: bool, // bit offset: 0 desc: Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_1FEI: bool, // bit offset: 1 desc: Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_2FEI: bool, // bit offset: 2 desc: Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_3FEI: bool, // bit offset: 3 desc: Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_4FEI: bool, // bit offset: 4 desc: Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_5FEI: bool, // bit offset: 5 desc: Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_6FEI: bool, // bit offset: 6 desc: Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_7FEI: bool, // bit offset: 7 desc: Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_8FEI: bool, // bit offset: 8 desc: Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_9FEI: bool, // bit offset: 9 desc: Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_10FEI: bool, // bit offset: 10 desc: Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_11FEI: bool, // bit offset: 11 desc: Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_12FEI: bool, // bit offset: 12 desc: Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_13FEI: bool, // bit offset: 13 desc: Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_14FEI: bool, // bit offset: 14 desc: Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_15FEI: bool, // bit offset: 15 desc: Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_16FEI: bool, // bit offset: 16 desc: Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_17FEI: bool, // bit offset: 17 desc: Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_18FEI: bool, // bit offset: 18 desc: Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_19FEI: bool, // bit offset: 19 desc: Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_20FEI: bool, // bit offset: 20 desc: Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_21FEI: bool, // bit offset: 21 desc: Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_22FEI: bool, // bit offset: 22 desc: Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_23FEI: bool, // bit offset: 23 desc: Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_24FEI: bool, // bit offset: 24 desc: Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_25FEI: bool, // bit offset: 25 desc: Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_26FEI: bool, // bit offset: 26 desc: Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_27FEI: bool, // bit offset: 27 desc: Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_28FEI: bool, // bit offset: 28 desc: Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_29FEI: bool, // bit offset: 29 desc: Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_30FEI: bool, // bit offset: 30 desc: Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_14FEI: u1, // bit offset: 14 desc: Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_15FEI: u1, // bit offset: 15 desc: Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_16FEI: u1, // bit offset: 16 desc: Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_17FEI: u1, // bit offset: 17 desc: Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_18FEI: u1, // bit offset: 18 desc: Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_19FEI: u1, // bit offset: 19 desc: Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_20FEI: u1, // bit offset: 20 desc: Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_21FEI: u1, // bit offset: 21 desc: Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_22FEI: u1, // bit offset: 22 desc: Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_23FEI: u1, // bit offset: 23 desc: Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_24FEI: u1, // bit offset: 24 desc: Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_25FEI: u1, // bit offset: 25 desc: Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_26FEI: u1, // bit offset: 26 desc: Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_27FEI: u1, // bit offset: 27 desc: Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_28FEI: u1, // bit offset: 28 desc: Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_29FEI: u1, // bit offset: 29 desc: Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P0_30FEI: u1, // bit offset: 30 desc: Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 12 GPIO Interrupt Clear. pub const CLR0 = mmio(Address + 0x0000000c, 32, packed struct { - P0_0CI: bool, // bit offset: 0 desc: Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_1CI: bool, // bit offset: 1 desc: Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_2CI: bool, // bit offset: 2 desc: Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_3CI: bool, // bit offset: 3 desc: Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_4CI: bool, // bit offset: 4 desc: Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_5CI: bool, // bit offset: 5 desc: Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_6CI: bool, // bit offset: 6 desc: Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_7CI: bool, // bit offset: 7 desc: Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_8CI: bool, // bit offset: 8 desc: Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_9CI: bool, // bit offset: 9 desc: Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_10CI: bool, // bit offset: 10 desc: Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_11CI: bool, // bit offset: 11 desc: Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_12CI: bool, // bit offset: 12 desc: Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_13CI: bool, // bit offset: 13 desc: Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_14CI: bool, // bit offset: 14 desc: Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_15CI: bool, // bit offset: 15 desc: Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_16CI: bool, // bit offset: 16 desc: Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_17CI: bool, // bit offset: 17 desc: Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_18CI: bool, // bit offset: 18 desc: Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_19CI: bool, // bit offset: 19 desc: Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_20CI: bool, // bit offset: 20 desc: Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_21CI: bool, // bit offset: 21 desc: Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_22CI: bool, // bit offset: 22 desc: Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_23CI: bool, // bit offset: 23 desc: Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_24CI: bool, // bit offset: 24 desc: Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_25CI: bool, // bit offset: 25 desc: Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_26CI: bool, // bit offset: 26 desc: Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_27CI: bool, // bit offset: 27 desc: Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_28CI: bool, // bit offset: 28 desc: Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_29CI: bool, // bit offset: 29 desc: Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_30CI: bool, // bit offset: 30 desc: Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_14CI: u1, // bit offset: 14 desc: Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_15CI: u1, // bit offset: 15 desc: Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_16CI: u1, // bit offset: 16 desc: Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_17CI: u1, // bit offset: 17 desc: Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_18CI: u1, // bit offset: 18 desc: Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_19CI: u1, // bit offset: 19 desc: Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_20CI: u1, // bit offset: 20 desc: Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_21CI: u1, // bit offset: 21 desc: Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_22CI: u1, // bit offset: 22 desc: Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_23CI: u1, // bit offset: 23 desc: Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_24CI: u1, // bit offset: 24 desc: Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_25CI: u1, // bit offset: 25 desc: Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_26CI: u1, // bit offset: 26 desc: Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_27CI: u1, // bit offset: 27 desc: Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_28CI: u1, // bit offset: 28 desc: Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_29CI: u1, // bit offset: 29 desc: Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P0_30CI: u1, // bit offset: 30 desc: Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 16 GPIO Interrupt Enable for Rising edge for Port 0. pub const ENR0 = mmio(Address + 0x00000010, 32, packed struct { - P0_0ER: bool, // bit offset: 0 desc: Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_1ER: bool, // bit offset: 1 desc: Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_2ER: bool, // bit offset: 2 desc: Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_3ER: bool, // bit offset: 3 desc: Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_4ER: bool, // bit offset: 4 desc: Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_5ER: bool, // bit offset: 5 desc: Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_6ER: bool, // bit offset: 6 desc: Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_7ER: bool, // bit offset: 7 desc: Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_8ER: bool, // bit offset: 8 desc: Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_9ER: bool, // bit offset: 9 desc: Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_10ER: bool, // bit offset: 10 desc: Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_11ER: bool, // bit offset: 11 desc: Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_12ER: bool, // bit offset: 12 desc: Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_13ER: bool, // bit offset: 13 desc: Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_14ER: bool, // bit offset: 14 desc: Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_15ER: bool, // bit offset: 15 desc: Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_16ER: bool, // bit offset: 16 desc: Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_17ER: bool, // bit offset: 17 desc: Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_18ER: bool, // bit offset: 18 desc: Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_19ER: bool, // bit offset: 19 desc: Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_20ER: bool, // bit offset: 20 desc: Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_21ER: bool, // bit offset: 21 desc: Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_22ER: bool, // bit offset: 22 desc: Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_23ER: bool, // bit offset: 23 desc: Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_24ER: bool, // bit offset: 24 desc: Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_25ER: bool, // bit offset: 25 desc: Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_26ER: bool, // bit offset: 26 desc: Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_27ER: bool, // bit offset: 27 desc: Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_28ER: bool, // bit offset: 28 desc: Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_29ER: bool, // bit offset: 29 desc: Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_30ER: bool, // bit offset: 30 desc: Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_14ER: u1, // bit offset: 14 desc: Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_15ER: u1, // bit offset: 15 desc: Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_16ER: u1, // bit offset: 16 desc: Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_17ER: u1, // bit offset: 17 desc: Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_18ER: u1, // bit offset: 18 desc: Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_19ER: u1, // bit offset: 19 desc: Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_20ER: u1, // bit offset: 20 desc: Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_21ER: u1, // bit offset: 21 desc: Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_22ER: u1, // bit offset: 22 desc: Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_23ER: u1, // bit offset: 23 desc: Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_24ER: u1, // bit offset: 24 desc: Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_25ER: u1, // bit offset: 25 desc: Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_26ER: u1, // bit offset: 26 desc: Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_27ER: u1, // bit offset: 27 desc: Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_28ER: u1, // bit offset: 28 desc: Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_29ER: u1, // bit offset: 29 desc: Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P0_30ER: u1, // bit offset: 30 desc: Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 20 GPIO Interrupt Enable for Falling edge for Port 0. pub const ENF0 = mmio(Address + 0x00000014, 32, packed struct { - P0_0EF: bool, // bit offset: 0 desc: Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_1EF: bool, // bit offset: 1 desc: Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_2EF: bool, // bit offset: 2 desc: Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_3EF: bool, // bit offset: 3 desc: Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_4EF: bool, // bit offset: 4 desc: Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_5EF: bool, // bit offset: 5 desc: Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_6EF: bool, // bit offset: 6 desc: Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_7EF: bool, // bit offset: 7 desc: Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_8EF: bool, // bit offset: 8 desc: Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_9EF: bool, // bit offset: 9 desc: Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_10EF: bool, // bit offset: 10 desc: Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_11EF: bool, // bit offset: 11 desc: Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_12EF: bool, // bit offset: 12 desc: Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_13EF: bool, // bit offset: 13 desc: Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_14EF: bool, // bit offset: 14 desc: Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_15EF: bool, // bit offset: 15 desc: Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_16EF: bool, // bit offset: 16 desc: Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_17EF: bool, // bit offset: 17 desc: Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_18EF: bool, // bit offset: 18 desc: Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_19EF: bool, // bit offset: 19 desc: Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_20EF: bool, // bit offset: 20 desc: Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_21EF: bool, // bit offset: 21 desc: Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_22EF: bool, // bit offset: 22 desc: Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_23EF: bool, // bit offset: 23 desc: Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_24EF: bool, // bit offset: 24 desc: Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_25EF: bool, // bit offset: 25 desc: Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_26EF: bool, // bit offset: 26 desc: Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_27EF: bool, // bit offset: 27 desc: Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_28EF: bool, // bit offset: 28 desc: Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_29EF: bool, // bit offset: 29 desc: Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_30EF: bool, // bit offset: 30 desc: Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_14EF: u1, // bit offset: 14 desc: Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_15EF: u1, // bit offset: 15 desc: Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_16EF: u1, // bit offset: 16 desc: Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_17EF: u1, // bit offset: 17 desc: Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_18EF: u1, // bit offset: 18 desc: Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_19EF: u1, // bit offset: 19 desc: Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_20EF: u1, // bit offset: 20 desc: Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_21EF: u1, // bit offset: 21 desc: Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_22EF: u1, // bit offset: 22 desc: Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_23EF: u1, // bit offset: 23 desc: Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_24EF: u1, // bit offset: 24 desc: Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_25EF: u1, // bit offset: 25 desc: Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_26EF: u1, // bit offset: 26 desc: Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_27EF: u1, // bit offset: 27 desc: Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_28EF: u1, // bit offset: 28 desc: Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_29EF: u1, // bit offset: 29 desc: Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P0_30EF: u1, // bit offset: 30 desc: Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 36 GPIO Interrupt Status for Rising edge for Port 0. pub const STATR2 = mmio(Address + 0x00000024, 32, packed struct { - P2_0REI: bool, // bit offset: 0 desc: Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_1REI: bool, // bit offset: 1 desc: Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_2REI: bool, // bit offset: 2 desc: Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_3REI: bool, // bit offset: 3 desc: Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_4REI: bool, // bit offset: 4 desc: Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_5REI: bool, // bit offset: 5 desc: Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_6REI: bool, // bit offset: 6 desc: Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_7REI: bool, // bit offset: 7 desc: Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_8REI: bool, // bit offset: 8 desc: Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_9REI: bool, // bit offset: 9 desc: Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_10REI: bool, // bit offset: 10 desc: Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_11REI: bool, // bit offset: 11 desc: Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_12REI: bool, // bit offset: 12 desc: Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_13REI: bool, // bit offset: 13 desc: Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + P2_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3507,20 +4534,21 @@ pub const GPIOINT = extern struct { }); // byte offset: 40 GPIO Interrupt Status for Falling edge for Port 0. pub const STATF2 = mmio(Address + 0x00000028, 32, packed struct { - P2_0FEI: bool, // bit offset: 0 desc: Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_1FEI: bool, // bit offset: 1 desc: Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_2FEI: bool, // bit offset: 2 desc: Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_3FEI: bool, // bit offset: 3 desc: Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_4FEI: bool, // bit offset: 4 desc: Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_5FEI: bool, // bit offset: 5 desc: Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_6FEI: bool, // bit offset: 6 desc: Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_7FEI: bool, // bit offset: 7 desc: Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_8FEI: bool, // bit offset: 8 desc: Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_9FEI: bool, // bit offset: 9 desc: Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_10FEI: bool, // bit offset: 10 desc: Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_11FEI: bool, // bit offset: 11 desc: Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_12FEI: bool, // bit offset: 12 desc: Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_13FEI: bool, // bit offset: 13 desc: Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + P2_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3542,20 +4570,21 @@ pub const GPIOINT = extern struct { }); // byte offset: 44 GPIO Interrupt Clear. pub const CLR2 = mmio(Address + 0x0000002c, 32, packed struct { - P2_0CI: bool, // bit offset: 0 desc: Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_1CI: bool, // bit offset: 1 desc: Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_2CI: bool, // bit offset: 2 desc: Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_3CI: bool, // bit offset: 3 desc: Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_4CI: bool, // bit offset: 4 desc: Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_5CI: bool, // bit offset: 5 desc: Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_6CI: bool, // bit offset: 6 desc: Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_7CI: bool, // bit offset: 7 desc: Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_8CI: bool, // bit offset: 8 desc: Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_9CI: bool, // bit offset: 9 desc: Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_10CI: bool, // bit offset: 10 desc: Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_11CI: bool, // bit offset: 11 desc: Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_12CI: bool, // bit offset: 12 desc: Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_13CI: bool, // bit offset: 13 desc: Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + P2_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3577,20 +4606,21 @@ pub const GPIOINT = extern struct { }); // byte offset: 48 GPIO Interrupt Enable for Rising edge for Port 0. pub const ENR2 = mmio(Address + 0x00000030, 32, packed struct { - P2_0ER: bool, // bit offset: 0 desc: Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_1ER: bool, // bit offset: 1 desc: Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_2ER: bool, // bit offset: 2 desc: Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_3ER: bool, // bit offset: 3 desc: Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_4ER: bool, // bit offset: 4 desc: Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_5ER: bool, // bit offset: 5 desc: Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_6ER: bool, // bit offset: 6 desc: Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_7ER: bool, // bit offset: 7 desc: Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_8ER: bool, // bit offset: 8 desc: Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_9ER: bool, // bit offset: 9 desc: Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_10ER: bool, // bit offset: 10 desc: Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_11ER: bool, // bit offset: 11 desc: Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_12ER: bool, // bit offset: 12 desc: Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_13ER: bool, // bit offset: 13 desc: Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + P2_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3612,20 +4642,21 @@ pub const GPIOINT = extern struct { }); // byte offset: 52 GPIO Interrupt Enable for Falling edge for Port 0. pub const ENF2 = mmio(Address + 0x00000034, 32, packed struct { - P2_0EF: bool, // bit offset: 0 desc: Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_1EF: bool, // bit offset: 1 desc: Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_2EF: bool, // bit offset: 2 desc: Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_3EF: bool, // bit offset: 3 desc: Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_4EF: bool, // bit offset: 4 desc: Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_5EF: bool, // bit offset: 5 desc: Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_6EF: bool, // bit offset: 6 desc: Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_7EF: bool, // bit offset: 7 desc: Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_8EF: bool, // bit offset: 8 desc: Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_9EF: bool, // bit offset: 9 desc: Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_10EF: bool, // bit offset: 10 desc: Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_11EF: bool, // bit offset: 11 desc: Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_12EF: bool, // bit offset: 12 desc: Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_13EF: bool, // bit offset: 13 desc: Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + P2_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3650,108 +4681,480 @@ pub const PINCONNECT = extern struct { pub const Address: u32 = 0x4002c000; // byte offset: 0 Pin function select register 0. pub const PINSEL0 = mmio(Address + 0x00000000, 32, packed struct { - P0_0: u2, // bit offset: 0 desc: Pin function select P0.0. - P0_1: u2, // bit offset: 2 desc: Pin function select P0.1. - P0_2: u2, // bit offset: 4 desc: Pin function select P0.2. - P0_3: u2, // bit offset: 6 desc: Pin function select P0.3. - P0_4: u2, // bit offset: 8 desc: Pin function select P0.4. - P0_5: u2, // bit offset: 10 desc: Pin function select P0.5. - P0_6: u2, // bit offset: 12 desc: Pin function select P0.6. - P0_7: u2, // bit offset: 14 desc: Pin function select P0.7. - P0_8: u2, // bit offset: 16 desc: Pin function select P0.8. - P0_9: u2, // bit offset: 18 desc: Pin function select P0.9. - P0_10: u2, // bit offset: 20 desc: Pin function select P0.10. - P0_11: u2, // bit offset: 22 desc: Pin function select P0.11. + P0_0: enum(u2) { // bit offset: 0 desc: Pin function select P0.0. + @"GPIO_P0" = 0, // desc: GPIO P0.0 + @"RD1" = 1, // desc: RD1 + @"TXD3" = 2, // desc: TXD3 + @"SDA1" = 3, // desc: SDA1 + }, + P0_1: enum(u2) { // bit offset: 2 desc: Pin function select P0.1. + @"GPIO_P0" = 0, // desc: GPIO P0.1 + @"TD1" = 1, // desc: TD1 + @"RXD3" = 2, // desc: RXD3 + @"SCL1" = 3, // desc: SCL1 + }, + P0_2: enum(u2) { // bit offset: 4 desc: Pin function select P0.2. + @"GPIO_P0" = 0, // desc: GPIO P0.2 + @"TXD0" = 1, // desc: TXD0 + @"AD0" = 2, // desc: AD0.7 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P0_3: enum(u2) { // bit offset: 6 desc: Pin function select P0.3. + @"GPIO_P0" = 0, // desc: GPIO P0.3. + @"RXD0" = 1, // desc: RXD0 + @"AD0" = 2, // desc: AD0.6 + // @"RESERVED", // desc: Reserved. + _, // non-exhaustive + }, + P0_4: enum(u2) { // bit offset: 8 desc: Pin function select P0.4. + @"GPIO_P0" = 0, // desc: GPIO P0.4. + @"I2SRX_CLK" = 1, // desc: I2SRX_CLK + @"RD2" = 2, // desc: RD2 + @"CAP2" = 3, // desc: CAP2.0 + }, + P0_5: enum(u2) { // bit offset: 10 desc: Pin function select P0.5. + @"GPIO_P0" = 0, // desc: GPIO P0.5. + @"I2SRX_WS" = 1, // desc: I2SRX_WS + @"TD2" = 2, // desc: TD2 + @"CAP2" = 3, // desc: CAP2.1 + }, + P0_6: enum(u2) { // bit offset: 12 desc: Pin function select P0.6. + @"GPIO_P0" = 0, // desc: GPIO P0.6. + @"I2SRX_SDA" = 1, // desc: I2SRX_SDA + @"SSEL1" = 2, // desc: SSEL1 + @"MAT2" = 3, // desc: MAT2.0 + }, + P0_7: enum(u2) { // bit offset: 14 desc: Pin function select P0.7. + @"GPIO_P0" = 0, // desc: GPIO P0.7. + @"I2STX_CLK" = 1, // desc: I2STX_CLK + @"SCK1" = 2, // desc: SCK1 + @"MAT2" = 3, // desc: MAT2.1 + }, + P0_8: enum(u2) { // bit offset: 16 desc: Pin function select P0.8. + @"GPIO_P0" = 0, // desc: GPIO P0.8. + @"I2STX_WS" = 1, // desc: I2STX_WS + @"MISO1" = 2, // desc: MISO1 + @"MAT2" = 3, // desc: MAT2.2 + }, + P0_9: enum(u2) { // bit offset: 18 desc: Pin function select P0.9. + @"GPIO_P0" = 0, // desc: GPIO P0.9 + @"I2STX_SDA" = 1, // desc: I2STX_SDA + @"MOSI1" = 2, // desc: MOSI1 + @"MAT2" = 3, // desc: MAT2.3 + }, + P0_10: enum(u2) { // bit offset: 20 desc: Pin function select P0.10. + @"GPIO_P0" = 0, // desc: GPIO P0.10 + @"TXD2" = 1, // desc: TXD2 + @"SDA2" = 2, // desc: SDA2 + @"MAT3" = 3, // desc: MAT3.0 + }, + P0_11: enum(u2) { // bit offset: 22 desc: Pin function select P0.11. + @"GPIO_P0" = 0, // desc: GPIO P0.11 + @"RXD2" = 1, // desc: RXD2 + @"SCL2" = 2, // desc: SCL2 + @"MAT3" = 3, // desc: MAT3.1 + }, + // RESERVED: u6, // bit offset: 24 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P0_15: u2, // bit offset: 30 desc: Pin function select P0.15. + P0_15: enum(u2) { // bit offset: 30 desc: Pin function select P0.15. + @"GPIO_P0" = 0, // desc: GPIO P0.15 + @"TXD1" = 1, // desc: TXD1 + @"SCK0" = 2, // desc: SCK0 + @"SCK" = 3, // desc: SCK + }, }); // byte offset: 4 Pin function select register 1. pub const PINSEL1 = mmio(Address + 0x00000004, 32, packed struct { - P0_16: u2, // bit offset: 0 desc: Pin function select P0.16. - P0_17: u2, // bit offset: 2 desc: Pin function select P0.17. - P0_18: u2, // bit offset: 4 desc: Pin function select P0.18. - P0_19: u2, // bit offset: 6 desc: Pin function select P019. - P0_20: u2, // bit offset: 8 desc: Pin function select P0.20. - P0_21: u2, // bit offset: 10 desc: Pin function select P0.21. - P0_22: u2, // bit offset: 12 desc: Pin function select P022 - P0_23: u2, // bit offset: 14 desc: Pin function select P023. - P0_24: u2, // bit offset: 16 desc: Pin function select P0.24. - P0_25: u2, // bit offset: 18 desc: Pin function select P0.25. - P0_26: u2, // bit offset: 20 desc: Pin function select P0.26. - P0_27: u2, // bit offset: 22 desc: Pin function select P0.27. - P0_28: u2, // bit offset: 24 desc: Pin function select P0.28. - P0_29: u2, // bit offset: 26 desc: Pin function select P0.29 - P0_30: u2, // bit offset: 28 desc: Pin function select P0.30. + P0_16: enum(u2) { // bit offset: 0 desc: Pin function select P0.16. + @"GPIO_P0" = 0, // desc: GPIO P0.16 + @"RXD1" = 1, // desc: RXD1 + @"SSEL0" = 2, // desc: SSEL0 + @"SSEL" = 3, // desc: SSEL + }, + P0_17: enum(u2) { // bit offset: 2 desc: Pin function select P0.17. + @"GPIO_P0" = 0, // desc: GPIO P0.17 + @"CTS1" = 1, // desc: CTS1 + @"MISO0" = 2, // desc: MISO0 + @"MISO" = 3, // desc: MISO + }, + P0_18: enum(u2) { // bit offset: 4 desc: Pin function select P0.18. + @"GPIO_P0" = 0, // desc: GPIO P0.18 + @"DCD1" = 1, // desc: DCD1 + @"MOSI0" = 2, // desc: MOSI0 + @"MOSI" = 3, // desc: MOSI + }, + P0_19: enum(u2) { // bit offset: 6 desc: Pin function select P019. + @"GPIO_P0" = 0, // desc: GPIO P0.19. + @"DSR1" = 1, // desc: DSR1 + // @"RESERVED", // desc: Reserved + @"SDA1" = 3, // desc: SDA1 + _, // non-exhaustive + }, + P0_20: enum(u2) { // bit offset: 8 desc: Pin function select P0.20. + @"GPIO_P0" = 0, // desc: GPIO P0.20. + @"DTR1" = 1, // desc: DTR1 + // @"RESERVED", // desc: Reserved + @"SCL1" = 3, // desc: SCL1 + _, // non-exhaustive + }, + P0_21: enum(u2) { // bit offset: 10 desc: Pin function select P0.21. + @"GPIO_PORT_0" = 0, // desc: GPIO Port 0.21. + @"RI1" = 1, // desc: RI1 + // @"RESERVED", // desc: Reserved + @"RD1" = 3, // desc: RD1 + _, // non-exhaustive + }, + P0_22: enum(u2) { // bit offset: 12 desc: Pin function select P022 + @"GPIO_P0" = 0, // desc: GPIO P0.22. + @"RTS1" = 1, // desc: RTS1 + // @"RESERVED", // desc: Reserved + @"TD1" = 3, // desc: TD1 + _, // non-exhaustive + }, + P0_23: enum(u2) { // bit offset: 14 desc: Pin function select P023. + @"GPIO_P0" = 0, // desc: GPIO P0.23. + @"AD0" = 1, // desc: AD0.0 + @"I2SRX_CLK" = 2, // desc: I2SRX_CLK + @"CAP3" = 3, // desc: CAP3.0 + }, + P0_24: enum(u2) { // bit offset: 16 desc: Pin function select P0.24. + @"GPIO_P0" = 0, // desc: GPIO P0.24. + @"AD0" = 1, // desc: AD0.1 + @"I2SRX_WS" = 2, // desc: I2SRX_WS + @"CAP3" = 3, // desc: CAP3.1 + }, + P0_25: enum(u2) { // bit offset: 18 desc: Pin function select P0.25. + @"GPIO_P0" = 0, // desc: GPIO P0.25 + @"AD0" = 1, // desc: AD0.2 + @"I2SRX_SDA" = 2, // desc: I2SRX_SDA + @"TXD3" = 3, // desc: TXD3 + }, + P0_26: enum(u2) { // bit offset: 20 desc: Pin function select P0.26. + @"GPIO_P0" = 0, // desc: GPIO P0.26 + @"AD0" = 1, // desc: AD0.3 + @"AOUT" = 2, // desc: AOUT + @"RXD3" = 3, // desc: RXD3 + }, + P0_27: enum(u2) { // bit offset: 22 desc: Pin function select P0.27. + @"GPIO_P0" = 0, // desc: GPIO P0.27 + @"SDA0" = 1, // desc: SDA0 + @"USB_SDA" = 2, // desc: USB_SDA + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P0_28: enum(u2) { // bit offset: 24 desc: Pin function select P0.28. + @"GPIO_P0" = 0, // desc: GPIO P0.28 + @"SCL0" = 1, // desc: SCL0 + @"USB_SCL" = 2, // desc: USB_SCL + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P0_29: enum(u2) { // bit offset: 26 desc: Pin function select P0.29 + @"GPIO_P0" = 0, // desc: GPIO P0.29 + @"USB_DP" = 1, // desc: USB_D+ + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P0_30: enum(u2) { // bit offset: 28 desc: Pin function select P0.30. + @"GPIO_P0" = 0, // desc: GPIO P0.30 + @"USB_DM" = 1, // desc: USB_D- + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + // RESERVED: u2, // bit offset: 30 desc: Reserved padding2: u1 = 0, padding1: u1 = 0, }); // byte offset: 8 Pin function select register 2. pub const PINSEL2 = mmio(Address + 0x00000008, 32, packed struct { - P1_0: u2, // bit offset: 0 desc: Pin function select P1.0. - P1_1: u2, // bit offset: 2 desc: Pin function select P1.1. + P1_0: enum(u2) { // bit offset: 0 desc: Pin function select P1.0. + @"GPIO_P1" = 0, // desc: GPIO P1.0 + @"ENET_TXD0" = 1, // desc: ENET_TXD0 + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_1: enum(u2) { // bit offset: 2 desc: Pin function select P1.1. + @"GPIO_P1" = 0, // desc: GPIO P1.1 + @"ENET_TXD1" = 1, // desc: ENET_TXD1 + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + // RESERVED: u4, // bit offset: 4 desc: Reserved. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P1_4: u2, // bit offset: 8 desc: Pin function select P1.4. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - P1_8: u2, // bit offset: 16 desc: Pin function select P1.8. - P1_9: u2, // bit offset: 18 desc: Pin function select P1.9. - P1_10: u2, // bit offset: 20 desc: Pin function select P1.10. - P1_14: u2, // bit offset: 22 desc: Pin function select P1.14. + P1_4: enum(u2) { // bit offset: 8 desc: Pin function select P1.4. + @"GPIO_P1" = 0, // desc: GPIO P1.4. + @"ENET_TX_EN" = 1, // desc: ENET_TX_EN + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + // RESERVED: u6, // bit offset: 10 desc: Reserved. reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - P1_15: u2, // bit offset: 30 desc: Pin function select P1.15. + P1_8: enum(u2) { // bit offset: 16 desc: Pin function select P1.8. + @"GPIO_P1" = 0, // desc: GPIO P1.8. + @"ENET_CRS" = 1, // desc: ENET_CRS + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_9: enum(u2) { // bit offset: 18 desc: Pin function select P1.9. + @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.9 + @"ENET_RXD0" = 1, // desc: ENET_RXD0 + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_10: enum(u2) { // bit offset: 20 desc: Pin function select P1.10. + @"GPIO_P1" = 0, // desc: GPIO P1.10 + @"ENET_RXD1" = 1, // desc: ENET_RXD1 + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_14: enum(u2) { // bit offset: 22 desc: Pin function select P1.14. + @"GPIO_P1" = 0, // desc: GPIO P1.14 + @"ENET_RX_ER" = 1, // desc: ENET_RX_ER + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + // RESERVED: u6, // bit offset: 24 desc: Reserved. + // RESERVED: u6, // bit offset: 24 desc: Reserved. + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + P1_15: enum(u2) { // bit offset: 30 desc: Pin function select P1.15. + @"GPIO_P1" = 0, // desc: GPIO P1.15 + @"ENET_REF_CLK" = 1, // desc: ENET_REF_CLK + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, }); // byte offset: 12 Pin function select register 3. pub const PINSEL3 = mmio(Address + 0x0000000c, 32, packed struct { - P1_16: u2, // bit offset: 0 desc: Pin function select P1.16. - P1_17: u2, // bit offset: 2 desc: Pin function select P1.17. - P1_18: u2, // bit offset: 4 desc: Pin function select P1.18. - P1_19: u2, // bit offset: 6 desc: Pin function select P1.19. - P1_20: u2, // bit offset: 8 desc: Pin function select P1.20. - P1_21: u2, // bit offset: 10 desc: Pin function select P1.21. - P1_22: u2, // bit offset: 12 desc: Pin function select P1.22 - P1_23: u2, // bit offset: 14 desc: Pin function select P1.23. - P1_24: u2, // bit offset: 16 desc: Pin function select P1.24. - P1_25: u2, // bit offset: 18 desc: Pin function select P1.25. - P1_26: u2, // bit offset: 20 desc: Pin function select P1.26. - P1_27: u2, // bit offset: 22 desc: Pin function select P1.27. - P1_28: u2, // bit offset: 24 desc: Pin function select P1.28. - P1_29: u2, // bit offset: 26 desc: Pin function select P1.29 - P1_30: u2, // bit offset: 28 desc: Pin function select P1.30. - P1_31: u2, // bit offset: 30 desc: Pin function select P1.31. + P1_16: enum(u2) { // bit offset: 0 desc: Pin function select P1.16. + @"GPIO_P1" = 0, // desc: GPIO P1.16 + @"ENET_MDC" = 1, // desc: ENET_MDC + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_17: enum(u2) { // bit offset: 2 desc: Pin function select P1.17. + @"GPIO_P1" = 0, // desc: GPIO P1.17 + @"ENET_MDIO" = 1, // desc: ENET_MDIO + // @"RESERVED", // desc: Reserved + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P1_18: enum(u2) { // bit offset: 4 desc: Pin function select P1.18. + @"GPIO_P1" = 0, // desc: GPIO P1.18 + @"USB_UP_LED" = 1, // desc: USB_UP_LED + @"PWM1" = 2, // desc: PWM1.1 + @"CAP1" = 3, // desc: CAP1.0 + }, + P1_19: enum(u2) { // bit offset: 6 desc: Pin function select P1.19. + @"GPIO_P1" = 0, // desc: GPIO P1.19. + @"MCOA0" = 1, // desc: MCOA0 + @"USB_PPWR" = 2, // desc: USB_PPWR + @"CAP1" = 3, // desc: CAP1.1 + }, + P1_20: enum(u2) { // bit offset: 8 desc: Pin function select P1.20. + @"GPIO_P1" = 0, // desc: GPIO P1.20. + @"MCI0" = 1, // desc: MCI0 + @"PWM1" = 2, // desc: PWM1.2 + @"SCK0" = 3, // desc: SCK0 + }, + P1_21: enum(u2) { // bit offset: 10 desc: Pin function select P1.21. + @"GPIO_P1" = 0, // desc: GPIO P1.21. + @"MCABORT" = 1, // desc: MCABORT + @"PWM1" = 2, // desc: PWM1.3 + @"SSEL0" = 3, // desc: SSEL0 + }, + P1_22: enum(u2) { // bit offset: 12 desc: Pin function select P1.22 + @"GPIO_P1" = 0, // desc: GPIO P1.22. + @"MCOB0" = 1, // desc: MCOB0 + @"USB_PWRD" = 2, // desc: USB_PWRD + @"MAT1" = 3, // desc: MAT1.0 + }, + P1_23: enum(u2) { // bit offset: 14 desc: Pin function select P1.23. + @"GPIO_P1" = 0, // desc: GPIO P1.23. + @"MCI1" = 1, // desc: MCI1 + @"PWM1" = 2, // desc: PWM1.4 + @"MISO0" = 3, // desc: MISO0 + }, + P1_24: enum(u2) { // bit offset: 16 desc: Pin function select P1.24. + @"GPIO_P1" = 0, // desc: GPIO P1.24. + @"MCI2" = 1, // desc: MCI2 + @"PWM1" = 2, // desc: PWM1.5 + @"MOSI0" = 3, // desc: MOSI0 + }, + P1_25: enum(u2) { // bit offset: 18 desc: Pin function select P1.25. + @"GPIO_P1" = 0, // desc: GPIO P1.25 + @"MCOA1" = 1, // desc: MCOA1 + // @"RESERVED", // desc: Reserved + @"MAT1" = 3, // desc: MAT1.1 + _, // non-exhaustive + }, + P1_26: enum(u2) { // bit offset: 20 desc: Pin function select P1.26. + @"GPIO_P1" = 0, // desc: GPIO P1.26 + @"MCOB1" = 1, // desc: MCOB1 + @"PWM1" = 2, // desc: PWM1.6 + @"CAP0" = 3, // desc: CAP0.0 + }, + P1_27: enum(u2) { // bit offset: 22 desc: Pin function select P1.27. + @"GPIO_P1" = 0, // desc: GPIO P1.27 + @"CLKOUT" = 1, // desc: CLKOUT + @"USB_OVRCR" = 2, // desc: USB_OVRCR + @"CAP0" = 3, // desc: CAP0.1 + }, + P1_28: enum(u2) { // bit offset: 24 desc: Pin function select P1.28. + @"GPIO_P1" = 0, // desc: GPIO P1.28 + @"MCOA2" = 1, // desc: MCOA2 + @"PCAP1" = 2, // desc: PCAP1.0 + @"MAT0" = 3, // desc: MAT0.0 + }, + P1_29: enum(u2) { // bit offset: 26 desc: Pin function select P1.29 + @"GPIO_P1" = 0, // desc: GPIO P1.29 + @"MCOB2" = 1, // desc: MCOB2 + @"PCAP1" = 2, // desc: PCAP1.1 + @"MAT0" = 3, // desc: MAT0.1 + }, + P1_30: enum(u2) { // bit offset: 28 desc: Pin function select P1.30. + @"GPIO_P1" = 0, // desc: GPIO P1.30 + // @"RESERVED", // desc: Reserved + @"VBUS" = 2, // desc: VBUS + @"AD0" = 3, // desc: AD0.4 + _, // non-exhaustive + }, + P1_31: enum(u2) { // bit offset: 30 desc: Pin function select P1.31. + @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.31 + // @"RESERVED", // desc: Reserved + @"SCK1" = 2, // desc: SCK1 + @"AD0" = 3, // desc: AD0.5 + _, // non-exhaustive + }, }); // byte offset: 16 Pin function select register 4 pub const PINSEL4 = mmio(Address + 0x00000010, 32, packed struct { - P2_0: u2, // bit offset: 0 desc: Pin function select P2.0. - P2_1: u2, // bit offset: 2 desc: Pin function select P2.1. - P2_2: u2, // bit offset: 4 desc: Pin function select P2.2. - P2_3: u2, // bit offset: 6 desc: Pin function select P2.3. - P2_4: u2, // bit offset: 8 desc: Pin function select P2.4. - P2_5: u2, // bit offset: 10 desc: Pin function select P2.5. - P2_6: u2, // bit offset: 12 desc: Pin function select P2.6. - P2_7: u2, // bit offset: 14 desc: Pin function select P2.7. - P2_8: u2, // bit offset: 16 desc: Pin function select P2.8. - P2_9: u2, // bit offset: 18 desc: Pin function select P2.9. - P2_10: u2, // bit offset: 20 desc: Pin function select P2.10. - P2_11: u2, // bit offset: 22 desc: Pin function select P2.11. - P2_12: u2, // bit offset: 24 desc: Pin function select P2.12. - P2_13: u2, // bit offset: 26 desc: Pin function select P2.13. + P2_0: enum(u2) { // bit offset: 0 desc: Pin function select P2.0. + @"GPIO_P2" = 0, // desc: GPIO P2.0 + @"PWM1" = 1, // desc: PWM1.1 + @"TXD1" = 2, // desc: TXD1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_1: enum(u2) { // bit offset: 2 desc: Pin function select P2.1. + @"GPIO_P2" = 0, // desc: GPIO P2.1 + @"PWM1" = 1, // desc: PWM1.2 + @"RXD1" = 2, // desc: RXD1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_2: enum(u2) { // bit offset: 4 desc: Pin function select P2.2. + @"GPIO_P2" = 0, // desc: GPIO P2.2 + @"PWM1" = 1, // desc: PWM1.3 + @"CTS1" = 2, // desc: CTS1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_3: enum(u2) { // bit offset: 6 desc: Pin function select P2.3. + @"GPIO_P2" = 0, // desc: GPIO P2.3. + @"PWM1" = 1, // desc: PWM1.4 + @"DCD1" = 2, // desc: DCD1 + // @"RESERVED", // desc: Reserved. + _, // non-exhaustive + }, + P2_4: enum(u2) { // bit offset: 8 desc: Pin function select P2.4. + @"GPIO_P2" = 0, // desc: GPIO P2.4. + @"PWM1" = 1, // desc: PWM1.5 + @"DSR1" = 2, // desc: DSR1 + // @"RESERVED", // desc: Reserved. + _, // non-exhaustive + }, + P2_5: enum(u2) { // bit offset: 10 desc: Pin function select P2.5. + @"GPIO_P2" = 0, // desc: GPIO P2.5. + @"PWM1" = 1, // desc: PWM1.6 + @"DTR1" = 2, // desc: DTR1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_6: enum(u2) { // bit offset: 12 desc: Pin function select P2.6. + @"GPIO_P2" = 0, // desc: GPIO P2.6. + @"PCAP1" = 1, // desc: PCAP1.0 + @"RI1" = 2, // desc: RI1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_7: enum(u2) { // bit offset: 14 desc: Pin function select P2.7. + @"GPIO_P2" = 0, // desc: GPIO P2.7. + @"RD2" = 1, // desc: RD2 + @"RTS1" = 2, // desc: RTS1 + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_8: enum(u2) { // bit offset: 16 desc: Pin function select P2.8. + @"GPIO_P2" = 0, // desc: GPIO P2.8. + @"TD2" = 1, // desc: TD2 + @"TXD2" = 2, // desc: TXD2 + @"ENET_MDC" = 3, // desc: ENET_MDC + }, + P2_9: enum(u2) { // bit offset: 18 desc: Pin function select P2.9. + @"GPIO_P2" = 0, // desc: GPIO P2.9 + @"USB_CONNECT" = 1, // desc: USB_CONNECT + @"RXD2" = 2, // desc: RXD2 + @"ENET_MDIO" = 3, // desc: ENET_MDIO + }, + P2_10: enum(u2) { // bit offset: 20 desc: Pin function select P2.10. + @"GPIO_P2" = 0, // desc: GPIO P2.10 + @"EINT0" = 1, // desc: EINT0 + @"NMI" = 2, // desc: NMI + // @"RESERVED", // desc: Reserved + _, // non-exhaustive + }, + P2_11: enum(u2) { // bit offset: 22 desc: Pin function select P2.11. + @"GPIO_P2" = 0, // desc: GPIO P2.11 + @"EINT1" = 1, // desc: EINT1 + // @"RESERVED", // desc: Reserved + @"I2STX_CLK" = 3, // desc: I2STX_CLK + _, // non-exhaustive + }, + P2_12: enum(u2) { // bit offset: 24 desc: Pin function select P2.12. + @"GPIO_P2" = 0, // desc: GPIO P2.12 + @"EINT2" = 1, // desc: EINT2 + // @"RESERVED", // desc: Reserved + @"I2STX_WS" = 3, // desc: I2STX_WS + _, // non-exhaustive + }, + P2_13: enum(u2) { // bit offset: 26 desc: Pin function select P2.13. + @"GPIO_P2" = 0, // desc: GPIO P2.13 + @"EINT3" = 1, // desc: EINT3 + // @"RESERVED", // desc: Reserved + @"I2STX_SDA" = 3, // desc: I2STX_SDA + _, // non-exhaustive + }, + // RESERVED: u4, // bit offset: 28 desc: Reserved. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -3759,6 +5162,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 28 Pin function select register 7 pub const PINSEL7 = mmio(Address + 0x0000001c, 32, packed struct { + // RESERVED: u18, // bit offset: 0 desc: Reserved. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, @@ -3777,8 +5181,20 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P3_25: u2, // bit offset: 18 desc: Pin function select P3.25. - P3_26: u2, // bit offset: 20 desc: Pin function select P3.26. + P3_25: enum(u2) { // bit offset: 18 desc: Pin function select P3.25. + @"GPIO_P3" = 0, // desc: GPIO P3.25 + // @"RESERVED", // desc: Reserved + @"MAT0" = 2, // desc: MAT0.0 + @"PWM1" = 3, // desc: PWM1.2 + _, // non-exhaustive + }, + P3_26: enum(u2) { // bit offset: 20 desc: Pin function select P3.26. + @"GPIO_P3" = 0, // desc: GPIO P3.26 + @"STCLK" = 1, // desc: STCLK + @"MAT0" = 2, // desc: MAT0.1 + @"PWM1" = 3, // desc: PWM1.3 + }, + // RESERVED: u10, // bit offset: 22 desc: Reserved. padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -3792,6 +5208,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 36 Pin function select register 9 pub const PINSEL9 = mmio(Address + 0x00000024, 32, packed struct { + // RESERVED: u24, // bit offset: 0 desc: Reserved. reserved24: u1 = 0, reserved23: u1 = 0, reserved22: u1 = 0, @@ -3816,8 +5233,19 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P4_28: u2, // bit offset: 24 desc: Pin function select P4.28. - P4_29: u2, // bit offset: 26 desc: Pin function select P4.29. + P4_28: enum(u2) { // bit offset: 24 desc: Pin function select P4.28. + @"GPIO_P4" = 0, // desc: GPIO P4.28 + @"RX_MCLK" = 1, // desc: RX_MCLK + @"MAT2" = 2, // desc: MAT2.0 + @"TXD3" = 3, // desc: TXD3 + }, + P4_29: enum(u2) { // bit offset: 26 desc: Pin function select P4.29. + @"GPIO_P4" = 0, // desc: GPIO P4.29 + @"TX_MCLK" = 1, // desc: TX_MCLK + @"MAT2" = 2, // desc: MAT2.1 + @"RXD3" = 3, // desc: RXD3 + }, + // RESERVED: u4, // bit offset: 28 desc: Reserved. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -3825,10 +5253,15 @@ pub const PINCONNECT = extern struct { }); // byte offset: 40 Pin function select register 10 pub const PINSEL10 = mmio(Address + 0x00000028, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: Reserved. Software should not write 1 to these bits. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TPIUCTRL: bool, // bit offset: 3 desc: TPIU interface pins control. + TPIUCTRL: enum(u1) { // bit offset: 3 desc: TPIU interface pins control. + @"DISABLED" = 0, // desc: Disabled. TPIU interface is disabled. + @"ENABLED" = 1, // desc: Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content. + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Software should not write 1 to these bits. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -3860,39 +5293,162 @@ pub const PINCONNECT = extern struct { }); // byte offset: 64 Pin mode select register 0 pub const PINMODE0 = mmio(Address + 0x00000040, 32, packed struct { - P0_00MODE: u2, // bit offset: 0 desc: Port 0 pin 0 on-chip pull-up/down resistor control. - P0_01MODE: u2, // bit offset: 2 desc: Port 0 pin 1 control. - P0_02MODE: u2, // bit offset: 4 desc: Port 0 pin 2 control. - P0_03MODE: u2, // bit offset: 6 desc: Port 0 pin 3 control. - P0_04MODE: u2, // bit offset: 8 desc: Port 0 pin 4 control. - P0_05MODE: u2, // bit offset: 10 desc: Port 0 pin 5 control. - P0_06MODE: u2, // bit offset: 12 desc: Port 0 pin 6 control. - P0_07MODE: u2, // bit offset: 14 desc: Port 0 pin 7 control. - P0_08MODE: u2, // bit offset: 16 desc: Port 0 pin 8 control. - P0_09MODE: u2, // bit offset: 18 desc: Port 0 pin 9 control. - P0_10MODE: u2, // bit offset: 20 desc: Port 0 pin 10 control. - P0_11MODE: u2, // bit offset: 22 desc: Port 0 pin 11 control. + P0_00MODE: enum(u2) { // bit offset: 0 desc: Port 0 pin 0 on-chip pull-up/down resistor control. + @"PULL_UP" = 0, // desc: Pull-up. P0.0 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.0 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.0 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.0 has a pull-down resistor enabled. + }, + P0_01MODE: enum(u2) { // bit offset: 2 desc: Port 0 pin 1 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.1 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.1 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.1 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.1 has a pull-down resistor enabled. + }, + P0_02MODE: enum(u2) { // bit offset: 4 desc: Port 0 pin 2 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.2 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.2 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.2 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.2 has a pull-down resistor enabled. + }, + P0_03MODE: enum(u2) { // bit offset: 6 desc: Port 0 pin 3 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.3 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.3 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.3 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.3 has a pull-down resistor enabled. + }, + P0_04MODE: enum(u2) { // bit offset: 8 desc: Port 0 pin 4 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.4 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.4 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.4 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.4 has a pull-down resistor enabled. + }, + P0_05MODE: enum(u2) { // bit offset: 10 desc: Port 0 pin 5 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.5 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.5 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.5 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.5 has a pull-down resistor enabled. + }, + P0_06MODE: enum(u2) { // bit offset: 12 desc: Port 0 pin 6 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.6 pin has a pull-up resistor enabled. + @"DISABLED" = 1, // desc: Disabled. Repeater. P0.6 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.6 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.6 has a pull-down resistor enabled. + }, + P0_07MODE: enum(u2) { // bit offset: 14 desc: Port 0 pin 7 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.7 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.7 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.7 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.7 has a pull-down resistor enabled. + }, + P0_08MODE: enum(u2) { // bit offset: 16 desc: Port 0 pin 8 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.8 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.8 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.8 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.8 has a pull-down resistor enabled. + }, + P0_09MODE: enum(u2) { // bit offset: 18 desc: Port 0 pin 9 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.9 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.9 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.9 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.9 has a pull-down resistor enabled. + }, + P0_10MODE: enum(u2) { // bit offset: 20 desc: Port 0 pin 10 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.10 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.10 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.10 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.10 has a pull-down resistor enabled. + }, + P0_11MODE: enum(u2) { // bit offset: 22 desc: Port 0 pin 11 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.11 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.11 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.11 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.11 has a pull-down resistor enabled. + }, + // RESERVED: u6, // bit offset: 24 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P0_15MODE: u2, // bit offset: 30 desc: Port 0 pin 15 control. + P0_15MODE: enum(u2) { // bit offset: 30 desc: Port 0 pin 15 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.15 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.15 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.15 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.15 has a pull-down resistor enabled. + }, }); // byte offset: 68 Pin mode select register 1 pub const PINMODE1 = mmio(Address + 0x00000044, 32, packed struct { - P0_16MODE: u2, // bit offset: 0 desc: Port 1 pin 16 control. - P0_17MODE: u2, // bit offset: 2 desc: Port 1 pin 17 control. - P0_18MODE: u2, // bit offset: 4 desc: Port 1 pin 18 control. - P0_19MODE: u2, // bit offset: 6 desc: Port 1 pin 19 control. - P0_20MODE: u2, // bit offset: 8 desc: Port 1 pin 20 control. - P0_21MODE: u2, // bit offset: 10 desc: Port 1 pin 21 control. - P0_22MODE: u2, // bit offset: 12 desc: Port 1 pin 22 control. - P0_23MODE: u2, // bit offset: 14 desc: Port 1 pin 23 control. - P0_24MODE: u2, // bit offset: 16 desc: Port 1 pin 24 control. - P0_25MODE: u2, // bit offset: 18 desc: Port 1 pin 25 control. - P0_26MODE: u2, // bit offset: 20 desc: Port 1 pin 26 control. + P0_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.16 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.16 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.16 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.16 has a pull-down resistor enabled. + }, + P0_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.17 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.17 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.17 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.17 has a pull-down resistor enabled. + }, + P0_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.18 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.18 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.18 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.18 has a pull-down resistor enabled. + }, + P0_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.19 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.19 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.19 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.19 has a pull-down resistor enabled. + }, + P0_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.20 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.20 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.20 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.20 has a pull-down resistor enabled. + }, + P0_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.21 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.21 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.21 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.21 has a pull-down resistor enabled. + }, + P0_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.22 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.22 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.22 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.22 has a pull-down resistor enabled. + }, + P0_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.23 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.23 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.23 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.23 has a pull-down resistor enabled. + }, + P0_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.24 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.24 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.24 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.24 has a pull-down resistor enabled. + }, + P0_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.25 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.25 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.25 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.25 has a pull-down resistor enabled. + }, + P0_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. + @"PULL_UP" = 0, // desc: Pull-up. P0.26 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P0.26 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P0.26 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P0.26 has a pull-down resistor enabled. + }, + // RESERVED: u8, // bit offset: 22 desc: Reserved. + // RESERVED: u2, // bit offset: 30 desc: Reserved. padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -3906,66 +5462,260 @@ pub const PINCONNECT = extern struct { }); // byte offset: 72 Pin mode select register 2 pub const PINMODE2 = mmio(Address + 0x00000048, 32, packed struct { - P1_00MODE: u2, // bit offset: 0 desc: Port 1 pin 0 control. - P1_01MODE: u2, // bit offset: 2 desc: Port 1 pin 1 control. + P1_00MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 0 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.0 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.0 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.0 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.0 has a pull-down resistor enabled. + }, + P1_01MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 1 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.1 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.1 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.1 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.1 has a pull-down resistor enabled. + }, + // RESERVED: u4, // bit offset: 4 desc: Reserved. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P1_04MODE: u2, // bit offset: 8 desc: Port 1 pin 4 control. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - P1_08MODE: u2, // bit offset: 16 desc: Port 1 pin 8 control. - P1_09MODE: u2, // bit offset: 18 desc: Port 1 pin 9 control. - P1_10MODE: u2, // bit offset: 20 desc: Port 1 pin 10 control. + P1_04MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 4 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.4 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.4 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.4 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.4 has a pull-down resistor enabled. + }, + // RESERVED: u6, // bit offset: 10 desc: Reserved. reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - P1_14MODE: u2, // bit offset: 28 desc: Port 1 pin 14 control. - P1_15MODE: u2, // bit offset: 30 desc: Port 1 pin 15 control. + P1_08MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 8 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.8 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.8 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.8 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.8 has a pull-down resistor enabled. + }, + P1_09MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 9 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.9 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.9 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.9 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.9 has a pull-down resistor enabled. + }, + P1_10MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 10 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.10 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.10 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.10 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.10 has a pull-down resistor enabled. + }, + // RESERVED: u6, // bit offset: 22 desc: Reserved. + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + P1_14MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 14 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.14 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.14 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.14 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.14 has a pull-down resistor enabled. + }, + P1_15MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 15 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.15 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.15 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.15 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.15 has a pull-down resistor enabled. + }, }); // byte offset: 76 Pin mode select register 3. pub const PINMODE3 = mmio(Address + 0x0000004c, 32, packed struct { - P1_16MODE: u2, // bit offset: 0 desc: Port 1 pin 16 control. - P1_17MODE: u2, // bit offset: 2 desc: Port 1 pin 17 control. - P1_18MODE: u2, // bit offset: 4 desc: Port 1 pin 18 control. - P1_19MODE: u2, // bit offset: 6 desc: Port 1 pin 19 control. - P1_20MODE: u2, // bit offset: 8 desc: Port 1 pin 20 control. - P1_21MODE: u2, // bit offset: 10 desc: Port 1 pin 21 control. - P1_22MODE: u2, // bit offset: 12 desc: Port 1 pin 22 control. - P1_23MODE: u2, // bit offset: 14 desc: Port 1 pin 23 control. - P1_24MODE: u2, // bit offset: 16 desc: Port 1 pin 24 control. - P1_25MODE: u2, // bit offset: 18 desc: Port 1 pin 25 control. - P1_26MODE: u2, // bit offset: 20 desc: Port 1 pin 26 control. - P1_27MODE: u2, // bit offset: 22 desc: Port 1 pin 27 control. - P1_28MODE: u2, // bit offset: 24 desc: Port 1 pin 28 control. - P1_29MODE: u2, // bit offset: 26 desc: Port 1 pin 29 control. - P1_30MODE: u2, // bit offset: 28 desc: Port 1 pin 30 control. - P1_31MODE: u2, // bit offset: 30 desc: Port 1 pin 31 control. + P1_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.16 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.16 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.16 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.16 has a pull-down resistor enabled. + }, + P1_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.17 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.17 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.17 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.17 has a pull-down resistor enabled. + }, + P1_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.18 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.18 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.18 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.18 has a pull-down resistor enabled. + }, + P1_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.19 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.19 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.19 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.19 has a pull-down resistor enabled. + }, + P1_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.20 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.20 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.20 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.20 has a pull-down resistor enabled. + }, + P1_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.21 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.21 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.21 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.21 has a pull-down resistor enabled. + }, + P1_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.22 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.22 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.22 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.22 has a pull-down resistor enabled. + }, + P1_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.23 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.23 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.23 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.23 has a pull-down resistor enabled. + }, + P1_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.24 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.24 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.24 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.24 has a pull-down resistor enabled. + }, + P1_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.25 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.25 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.25 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.25 has a pull-down resistor enabled. + }, + P1_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.26 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.26 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.26 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.26 has a pull-down resistor enabled. + }, + P1_27MODE: enum(u2) { // bit offset: 22 desc: Port 1 pin 27 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.27 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.27 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.27 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.27 has a pull-down resistor enabled. + }, + P1_28MODE: enum(u2) { // bit offset: 24 desc: Port 1 pin 28 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.28 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.28 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.28 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.28 has a pull-down resistor enabled. + }, + P1_29MODE: enum(u2) { // bit offset: 26 desc: Port 1 pin 29 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.29 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.29 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.29 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.29 has a pull-down resistor enabled. + }, + P1_30MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 30 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.30 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.30 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.30 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.30 has a pull-down resistor enabled. + }, + P1_31MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 31 control. + @"PULL_UP" = 0, // desc: Pull-up. P1.31 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P1.31 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P1.31 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P1.31 has a pull-down resistor enabled. + }, }); // byte offset: 80 Pin mode select register 4 pub const PINMODE4 = mmio(Address + 0x00000050, 32, packed struct { - P2_00MODE: u2, // bit offset: 0 desc: Port 2 pin 0 control. - P2_01MODE: u2, // bit offset: 2 desc: Port 2 pin 1 control. - P2_02MODE: u2, // bit offset: 4 desc: Port 2 pin 2 control. - P2_03MODE: u2, // bit offset: 6 desc: Port 2 pin 3 control. - P2_04MODE: u2, // bit offset: 8 desc: Port 2 pin 4 control. - P2_05MODE: u2, // bit offset: 10 desc: Port 2 pin 5 control. - P2_06MODE: u2, // bit offset: 12 desc: Port 2 pin 6 control. - P2_07MODE: u2, // bit offset: 14 desc: Port 2 pin 7 control. - P2_08MODE: u2, // bit offset: 16 desc: Port 2 pin 8 control. - P2_09MODE: u2, // bit offset: 18 desc: Port 2 pin 9 control. - P2_10MODE: u2, // bit offset: 20 desc: Port 2 pin 10 control. - P2_11MODE: u2, // bit offset: 22 desc: Port 2 pin 11 control. - P2_12MODE: u2, // bit offset: 24 desc: Port 2 pin 12 control. - P2_13MODE: u2, // bit offset: 26 desc: Port 2 pin 13 control. + P2_00MODE: enum(u2) { // bit offset: 0 desc: Port 2 pin 0 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.0 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.0 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.0 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.0 has a pull-down resistor enabled. + }, + P2_01MODE: enum(u2) { // bit offset: 2 desc: Port 2 pin 1 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.1 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.1 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.1 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.1 has a pull-down resistor enabled. + }, + P2_02MODE: enum(u2) { // bit offset: 4 desc: Port 2 pin 2 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.2 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.2 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.2 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.2 has a pull-down resistor enabled. + }, + P2_03MODE: enum(u2) { // bit offset: 6 desc: Port 2 pin 3 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.3 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.3 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.3 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.3 has a pull-down resistor enabled. + }, + P2_04MODE: enum(u2) { // bit offset: 8 desc: Port 2 pin 4 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.4 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.4 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.4 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.4 has a pull-down resistor enabled. + }, + P2_05MODE: enum(u2) { // bit offset: 10 desc: Port 2 pin 5 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.5 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.5 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.5 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.5 has a pull-down resistor enabled. + }, + P2_06MODE: enum(u2) { // bit offset: 12 desc: Port 2 pin 6 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.6 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.6 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.6 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.6 has a pull-down resistor enabled. + }, + P2_07MODE: enum(u2) { // bit offset: 14 desc: Port 2 pin 7 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.7 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.7 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.7 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.7 has a pull-down resistor enabled. + }, + P2_08MODE: enum(u2) { // bit offset: 16 desc: Port 2 pin 8 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.8 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.8 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.8 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.8 has a pull-down resistor enabled. + }, + P2_09MODE: enum(u2) { // bit offset: 18 desc: Port 2 pin 9 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.9 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.9 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.9 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.9 has a pull-down resistor enabled. + }, + P2_10MODE: enum(u2) { // bit offset: 20 desc: Port 2 pin 10 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.10 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.10 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.10 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.10 has a pull-down resistor enabled. + }, + P2_11MODE: enum(u2) { // bit offset: 22 desc: Port 2 pin 11 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.11 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.11 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.11 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.11 has a pull-down resistor enabled. + }, + P2_12MODE: enum(u2) { // bit offset: 24 desc: Port 2 pin 12 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.12 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.12 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.12 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.12 has a pull-down resistor enabled. + }, + P2_13MODE: enum(u2) { // bit offset: 26 desc: Port 2 pin 13 control. + @"PULL_UP" = 0, // desc: Pull-up. P2.13 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P2.13 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P2.13 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P2.13 has a pull-down resistor enabled. + }, + // RESERVED: u4, // bit offset: 28 desc: Reserved. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -3973,6 +5723,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 92 Pin mode select register 7 pub const PINMODE7 = mmio(Address + 0x0000005c, 32, packed struct { + // RESERVED: u18, // bit offset: 0 desc: Reserved reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, @@ -3991,8 +5742,19 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P3_25MODE: u2, // bit offset: 18 desc: Port 3 pin 25 control. - P3_26MODE: u2, // bit offset: 20 desc: Port 3 pin 26 control. + P3_25MODE: enum(u2) { // bit offset: 18 desc: Port 3 pin 25 control. + @"PULL_UP" = 0, // desc: Pull-up. P3.25 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P3.25 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P3.25 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P3.25 has a pull-down resistor enabled. + }, + P3_26MODE: enum(u2) { // bit offset: 20 desc: Port 3 pin 26 control. + @"PULL_UP" = 0, // desc: Pull-up. P3.26 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P3.26 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P3.26 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P3.26 has a pull-down resistor enabled. + }, + // RESERVED: u10, // bit offset: 22 desc: Reserved. padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -4006,6 +5768,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 100 Pin mode select register 9 pub const PINMODE9 = mmio(Address + 0x00000064, 32, packed struct { + // RESERVED: u24, // bit offset: 0 desc: Reserved. reserved24: u1 = 0, reserved23: u1 = 0, reserved22: u1 = 0, @@ -4030,8 +5793,19 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P4_28MODE: u2, // bit offset: 24 desc: Port 4 pin 28 control. - P4_29MODE: u2, // bit offset: 26 desc: Port 4 pin 29 control. + P4_28MODE: enum(u2) { // bit offset: 24 desc: Port 4 pin 28 control. + @"PULL_UP" = 0, // desc: Pull-up. P4.28 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P4.28 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P4.28 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P4.28 has a pull-down resistor enabled. + }, + P4_29MODE: enum(u2) { // bit offset: 26 desc: Port 4 pin 29 control. + @"PULL_UP" = 0, // desc: Pull-up. P4.29 pin has a pull-up resistor enabled. + @"REPEATER" = 1, // desc: Repeater. P4.29 pin has repeater mode enabled. + @"DISABLED" = 2, // desc: Disabled. P4.29 pin has neither pull-up nor pull-down. + @"PULL_DOWN" = 3, // desc: Pull-down. P4.29 has a pull-down resistor enabled. + }, + // RESERVED: u4, // bit offset: 28 desc: Reserved. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -4039,90 +5813,289 @@ pub const PINCONNECT = extern struct { }); // byte offset: 104 Open drain mode control register 0 pub const PINMODE_OD0 = mmio(Address + 0x00000068, 32, packed struct { - P0_00OD: bool, // bit offset: 0 desc: Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - P0_01OD: bool, // bit offset: 1 desc: Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - P0_02OD: bool, // bit offset: 2 desc: Port 0 pin 2 open drain mode control - P0_03OD: bool, // bit offset: 3 desc: Port 0 pin 3 open drain mode control - P0_04OD: bool, // bit offset: 4 desc: Port 0 pin 4 open drain mode control - P0_05OD: bool, // bit offset: 5 desc: Port 0 pin 5 open drain mode control - P0_06OD: bool, // bit offset: 6 desc: Port 0 pin 6 open drain mode control - P0_07OD: bool, // bit offset: 7 desc: Port 0 pin 7 open drain mode control - P0_08OD: bool, // bit offset: 8 desc: Port 0 pin 8 open drain mode control - P0_09OD: bool, // bit offset: 9 desc: Port 0 pin 9 open drain mode control - P0_10OD: bool, // bit offset: 10 desc: Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - P0_11OD: bool, // bit offset: 11 desc: Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + P0_00OD: enum(u1) { // bit offset: 0 desc: Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.0 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.0 pin is in the open drain mode. + }, + P0_01OD: enum(u1) { // bit offset: 1 desc: Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.1 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.1 pin is in the open drain mode. + }, + P0_02OD: enum(u1) { // bit offset: 2 desc: Port 0 pin 2 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.2 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.2 pin is in the open drain mode. + }, + P0_03OD: enum(u1) { // bit offset: 3 desc: Port 0 pin 3 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.3 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.3 pin is in the open drain mode. + }, + P0_04OD: enum(u1) { // bit offset: 4 desc: Port 0 pin 4 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.4 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.4 pin is in the open drain mode. + }, + P0_05OD: enum(u1) { // bit offset: 5 desc: Port 0 pin 5 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.5 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.5 pin is in the open drain mode. + }, + P0_06OD: enum(u1) { // bit offset: 6 desc: Port 0 pin 6 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.6 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.6 pin is in the open drain mode. + }, + P0_07OD: enum(u1) { // bit offset: 7 desc: Port 0 pin 7 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.7 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.7 pin is in the open drain mode. + }, + P0_08OD: enum(u1) { // bit offset: 8 desc: Port 0 pin 8 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.8 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.8 pin is in the open drain mode. + }, + P0_09OD: enum(u1) { // bit offset: 9 desc: Port 0 pin 9 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.9 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.9 pin is in the open drain mode. + }, + P0_10OD: enum(u1) { // bit offset: 10 desc: Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.10 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.10 pin is in the open drain mode. + }, + P0_11OD: enum(u1) { // bit offset: 11 desc: Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.11 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.11 pin is in the open drain mode. + }, + // RESERVED: u3, // bit offset: 12 desc: Reserved. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P0_15OD: bool, // bit offset: 15 desc: Port 0 pin 15 open drain mode control - P0_16OD: bool, // bit offset: 16 desc: Port 0 pin 16 open drain mode control - P0_17OD: bool, // bit offset: 17 desc: Port 0 pin 17 open drain mode control - P0_18OD: bool, // bit offset: 18 desc: Port 0 pin 18 open drain mode control - P0_19OD: bool, // bit offset: 19 desc: Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - P0_20OD: bool, // bit offset: 20 desc: Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - P0_21OD: bool, // bit offset: 21 desc: Port 0 pin 21 open drain mode control - P0_22OD: bool, // bit offset: 22 desc: Port 0 pin 22 open drain mode control - P0_23OD: bool, // bit offset: 23 desc: Port 0 pin 23 open drain mode control - P0_24OD: bool, // bit offset: 24 desc: Port 0 pin 24open drain mode control - P0_25OD: bool, // bit offset: 25 desc: Port 0 pin 25 open drain mode control - P0_26OD: bool, // bit offset: 26 desc: Port 0 pin 26 open drain mode control - reserved3: u1 = 0, - reserved2: u1 = 0, - P0_29OD: bool, // bit offset: 29 desc: Port 0 pin 29 open drain mode control - P0_30OD: bool, // bit offset: 30 desc: Port 0 pin 30 open drain mode control + P0_15OD: enum(u1) { // bit offset: 15 desc: Port 0 pin 15 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.15 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.15 pin is in the open drain mode. + }, + P0_16OD: enum(u1) { // bit offset: 16 desc: Port 0 pin 16 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.16 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.16 pin is in the open drain mode. + }, + P0_17OD: enum(u1) { // bit offset: 17 desc: Port 0 pin 17 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.17 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.17 pin is in the open drain mode. + }, + P0_18OD: enum(u1) { // bit offset: 18 desc: Port 0 pin 18 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.18 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.18 pin is in the open drain mode. + }, + P0_19OD: enum(u1) { // bit offset: 19 desc: Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.19 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.19 pin is in the open drain mode. + }, + P0_20OD: enum(u1) { // bit offset: 20 desc: Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. + @"NORMAL" = 0, // desc: Normal. P0.20 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.20 pin is in the open drain mode. + }, + P0_21OD: enum(u1) { // bit offset: 21 desc: Port 0 pin 21 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.21 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.21 pin is in the open drain mode. + }, + P0_22OD: enum(u1) { // bit offset: 22 desc: Port 0 pin 22 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.22 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.22 pin is in the open drain mode. + }, + P0_23OD: enum(u1) { // bit offset: 23 desc: Port 0 pin 23 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. + }, + P0_24OD: enum(u1) { // bit offset: 24 desc: Port 0 pin 24open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. + }, + P0_25OD: enum(u1) { // bit offset: 25 desc: Port 0 pin 25 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.25 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.25 pin is in the open drain mode. + }, + P0_26OD: enum(u1) { // bit offset: 26 desc: Port 0 pin 26 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.26 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.26 pin is in the open drain mode. + }, + // RESERVED: u2, // bit offset: 27 desc: Reserved. + reserved5: u1 = 0, + reserved4: u1 = 0, + P0_29OD: enum(u1) { // bit offset: 29 desc: Port 0 pin 29 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.29 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.29 pin is in the open drain mode. + }, + P0_30OD: enum(u1) { // bit offset: 30 desc: Port 0 pin 30 open drain mode control + @"NORMAL" = 0, // desc: Normal. P0.30 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.30 pin is in the open drain mode. + }, + // RESERVED: u1, // bit offset: 31 desc: Reserved. padding1: u1 = 0, }); // byte offset: 108 Open drain mode control register 1 pub const PINMODE_OD1 = mmio(Address + 0x0000006c, 32, packed struct { - P1_00OD: bool, // bit offset: 0 desc: Port 1 pin 0 open drain mode control. - P1_01OD: bool, // bit offset: 1 desc: Port 1 pin 1 open drain mode control, see P1.00OD + P1_00OD: enum(u1) { // bit offset: 0 desc: Port 1 pin 0 open drain mode control. + @"NORMAL" = 0, // desc: Normal. P1.0 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.0 pin is in the open drain mode. + }, + P1_01OD: enum(u1) { // bit offset: 1 desc: Port 1 pin 1 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.1 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.1 pin is in the open drain mode. + }, + // RESERVED: u2, // bit offset: 2 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - P1_04OD: bool, // bit offset: 4 desc: Port 1 pin 4 open drain mode control, see P1.00OD - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - P1_08OD: bool, // bit offset: 8 desc: Port 1 pin 8 open drain mode control, see P1.00OD - P1_09OD: bool, // bit offset: 9 desc: Port 1 pin 9 open drain mode control, see P1.00OD - P1_10OD: bool, // bit offset: 10 desc: Port 1 pin 10 open drain mode control, see P1.00OD + P1_04OD: enum(u1) { // bit offset: 4 desc: Port 1 pin 4 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.4 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.4 pin is in the open drain mode. + }, + // RESERVED: u3, // bit offset: 5 desc: Reserved. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - P1_14OD: bool, // bit offset: 14 desc: Port 1 pin 14 open drain mode control, see P1.00OD - P1_15OD: bool, // bit offset: 15 desc: Port 1 pin 15 open drain mode control, see P1.00OD - P1_16OD: bool, // bit offset: 16 desc: Port 1 pin 16 open drain mode control, see P1.00OD - P1_17OD: bool, // bit offset: 17 desc: Port 1 pin 17 open drain mode control, see P1.00OD - P1_18OD: bool, // bit offset: 18 desc: Port 1 pin 18 open drain mode control, see P1.00OD - P1_19OD: bool, // bit offset: 19 desc: Port 1 pin 19 open drain mode control, see P1.00OD - P1_20OD: bool, // bit offset: 20 desc: Port 1 pin 20open drain mode control, see P1.00OD - P1_21OD: bool, // bit offset: 21 desc: Port 1 pin 21 open drain mode control, see P1.00OD - P1_22OD: bool, // bit offset: 22 desc: Port 1 pin 22 open drain mode control, see P1.00OD - P1_23OD: bool, // bit offset: 23 desc: Port 1 pin 23 open drain mode control, see P1.00OD - P1_24OD: bool, // bit offset: 24 desc: Port 1 pin 24open drain mode control, see P1.00OD - P1_25OD: bool, // bit offset: 25 desc: Port 1 pin 25 open drain mode control, see P1.00OD - P1_26OD: bool, // bit offset: 26 desc: Port 1 pin 26 open drain mode control, see P1.00OD - P1_27OD: bool, // bit offset: 27 desc: Port 1 pin 27 open drain mode control, see P1.00OD - P1_28OD: bool, // bit offset: 28 desc: Port 1 pin 28 open drain mode control, see P1.00OD - P1_29OD: bool, // bit offset: 29 desc: Port 1 pin 29 open drain mode control, see P1.00OD - P1_30OD: bool, // bit offset: 30 desc: Port 1 pin 30 open drain mode control, see P1.00OD - P1_31OD: bool, // bit offset: 31 desc: Port 1 pin 31 open drain mode control. + P1_08OD: enum(u1) { // bit offset: 8 desc: Port 1 pin 8 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.8 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.8 pin is in the open drain mode. + }, + P1_09OD: enum(u1) { // bit offset: 9 desc: Port 1 pin 9 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.9 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.9 pin is in the open drain mode. + }, + P1_10OD: enum(u1) { // bit offset: 10 desc: Port 1 pin 10 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.10 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.10 pin is in the open drain mode. + }, + // RESERVED: u3, // bit offset: 11 desc: Reserved. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + P1_14OD: enum(u1) { // bit offset: 14 desc: Port 1 pin 14 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.14 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.14 pin is in the open drain mode. + }, + P1_15OD: enum(u1) { // bit offset: 15 desc: Port 1 pin 15 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.15 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.15 pin is in the open drain mode. + }, + P1_16OD: enum(u1) { // bit offset: 16 desc: Port 1 pin 16 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.16 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.16 pin is in the open drain mode. + }, + P1_17OD: enum(u1) { // bit offset: 17 desc: Port 1 pin 17 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.17 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.17 pin is in the open drain mode. + }, + P1_18OD: enum(u1) { // bit offset: 18 desc: Port 1 pin 18 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.18 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.18 pin is in the open drain mode. + }, + P1_19OD: enum(u1) { // bit offset: 19 desc: Port 1 pin 19 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.19 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.19 pin is in the open drain mode. + }, + P1_20OD: enum(u1) { // bit offset: 20 desc: Port 1 pin 20open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.20 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.20 pin is in the open drain mode. + }, + P1_21OD: enum(u1) { // bit offset: 21 desc: Port 1 pin 21 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.21 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.21 pin is in the open drain mode. + }, + P1_22OD: enum(u1) { // bit offset: 22 desc: Port 1 pin 22 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.22 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.22 pin is in the open drain mode. + }, + P1_23OD: enum(u1) { // bit offset: 23 desc: Port 1 pin 23 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.23 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.23 pin is in the open drain mode. + }, + P1_24OD: enum(u1) { // bit offset: 24 desc: Port 1 pin 24open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.24 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.24 pin is in the open drain mode. + }, + P1_25OD: enum(u1) { // bit offset: 25 desc: Port 1 pin 25 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.25 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.25 pin is in the open drain mode. + }, + P1_26OD: enum(u1) { // bit offset: 26 desc: Port 1 pin 26 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.26 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.26 pin is in the open drain mode. + }, + P1_27OD: enum(u1) { // bit offset: 27 desc: Port 1 pin 27 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.27 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.27 pin is in the open drain mode. + }, + P1_28OD: enum(u1) { // bit offset: 28 desc: Port 1 pin 28 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.28 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.28 pin is in the open drain mode. + }, + P1_29OD: enum(u1) { // bit offset: 29 desc: Port 1 pin 29 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.29 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.29 pin is in the open drain mode. + }, + P1_30OD: enum(u1) { // bit offset: 30 desc: Port 1 pin 30 open drain mode control, see P1.00OD + @"NORMAL" = 0, // desc: Normal. P1.30 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.30 pin is in the open drain mode. + }, + P1_31OD: enum(u1) { // bit offset: 31 desc: Port 1 pin 31 open drain mode control. + @"NORMAL" = 0, // desc: Normal. P1.31 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.31 pin is in the open drain mode. + }, }); // byte offset: 112 Open drain mode control register 2 pub const PINMODE_OD2 = mmio(Address + 0x00000070, 32, packed struct { - P2_00OD: bool, // bit offset: 0 desc: Port 2 pin 0 open drain mode control. - P2_01OD: bool, // bit offset: 1 desc: Port 2 pin 1 open drain mode control, see P2.00OD - P2_02OD: bool, // bit offset: 2 desc: Port 2 pin 2 open drain mode control, see P2.00OD - P2_03OD: bool, // bit offset: 3 desc: Port 2 pin 3 open drain mode control, see P2.00OD - P2_04OD: bool, // bit offset: 4 desc: Port 2 pin 4 open drain mode control, see P2.00OD - P2_05OD: bool, // bit offset: 5 desc: Port 2 pin 5 open drain mode control, see P2.00OD - P2_06OD: bool, // bit offset: 6 desc: Port 2 pin 6 open drain mode control, see P2.00OD - P2_07OD: bool, // bit offset: 7 desc: Port 2 pin 7 open drain mode control, see P2.00OD - P2_08OD: bool, // bit offset: 8 desc: Port 2 pin 8 open drain mode control, see P2.00OD - P2_09OD: bool, // bit offset: 9 desc: Port 2 pin 9 open drain mode control, see P2.00OD - P2_10OD: bool, // bit offset: 10 desc: Port 2 pin 10 open drain mode control, see P2.00OD - P2_11OD: bool, // bit offset: 11 desc: Port 2 pin 11 open drain mode control, see P2.00OD - P2_12OD: bool, // bit offset: 12 desc: Port 2 pin 12 open drain mode control, see P2.00OD - P2_13OD: bool, // bit offset: 13 desc: Port 2 pin 13 open drain mode control, see P2.00OD + P2_00OD: enum(u1) { // bit offset: 0 desc: Port 2 pin 0 open drain mode control. + @"NORMAL" = 0, // desc: Normal. P2.0 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.0 pin is in the open drain mode. + }, + P2_01OD: enum(u1) { // bit offset: 1 desc: Port 2 pin 1 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.1 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.1p in is in the open drain mode. + }, + P2_02OD: enum(u1) { // bit offset: 2 desc: Port 2 pin 2 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.2 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.2 pin is in the open drain mode. + }, + P2_03OD: enum(u1) { // bit offset: 3 desc: Port 2 pin 3 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.3 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.3 pin is in the open drain mode. + }, + P2_04OD: enum(u1) { // bit offset: 4 desc: Port 2 pin 4 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.4 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.4 pin is in the open drain mode. + }, + P2_05OD: enum(u1) { // bit offset: 5 desc: Port 2 pin 5 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.5 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.5 pin is in the open drain mode. + }, + P2_06OD: enum(u1) { // bit offset: 6 desc: Port 2 pin 6 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.6 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.6 pin is in the open drain mode. + }, + P2_07OD: enum(u1) { // bit offset: 7 desc: Port 2 pin 7 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.7 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.7 pin is in the open drain mode. + }, + P2_08OD: enum(u1) { // bit offset: 8 desc: Port 2 pin 8 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.8 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.8 pin is in the open drain mode. + }, + P2_09OD: enum(u1) { // bit offset: 9 desc: Port 2 pin 9 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.9 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.9 pin is in the open drain mode. + }, + P2_10OD: enum(u1) { // bit offset: 10 desc: Port 2 pin 10 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.10 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.10 pin is in the open drain mode. + }, + P2_11OD: enum(u1) { // bit offset: 11 desc: Port 2 pin 11 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.11 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.11 pin is in the open drain mode. + }, + P2_12OD: enum(u1) { // bit offset: 12 desc: Port 2 pin 12 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.12 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.12 pin is in the open drain mode. + }, + P2_13OD: enum(u1) { // bit offset: 13 desc: Port 2 pin 13 open drain mode control, see P2.00OD + @"NORMAL" = 0, // desc: Normal. P2.13 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.13 pin is in the open drain mode. + }, + // RESERVED: u18, // bit offset: 14 desc: Reserved. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -4144,6 +6117,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 116 Open drain mode control register 3 pub const PINMODE_OD3 = mmio(Address + 0x00000074, 32, packed struct { + // RESERVED: u25, // bit offset: 0 desc: Reserved. reserved25: u1 = 0, reserved24: u1 = 0, reserved23: u1 = 0, @@ -4169,8 +6143,12 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P3_25OD: bool, // bit offset: 25 desc: Port 3 pin 25 open drain mode control. - P3_26OD: bool, // bit offset: 26 desc: Port 3 pin 26 open drain mode control, see P3.25OD + P3_25OD: enum(u1) { // bit offset: 25 desc: Port 3 pin 25 open drain mode control. + @"NORMAL" = 0, // desc: Normal. P3.25 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P3.25 pin is in the open drain mode. + }, + P3_26OD: u1, // bit offset: 26 desc: Port 3 pin 26 open drain mode control, see P3.25OD + // RESERVED: u5, // bit offset: 27 desc: Reserved. padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, @@ -4179,6 +6157,7 @@ pub const PINCONNECT = extern struct { }); // byte offset: 120 Open drain mode control register 4 pub const PINMODE_OD4 = mmio(Address + 0x00000078, 32, packed struct { + // RESERVED: u28, // bit offset: 0 desc: Reserved. reserved28: u1 = 0, reserved27: u1 = 0, reserved26: u1 = 0, @@ -4207,17 +6186,34 @@ pub const PINCONNECT = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - P4_28OD: bool, // bit offset: 28 desc: Port 4 pin 28 open drain mode control. - P4_29OD: bool, // bit offset: 29 desc: Port 4 pin 29 open drain mode control, see P4.28OD + P4_28OD: enum(u1) { // bit offset: 28 desc: Port 4 pin 28 open drain mode control. + @"NORMAL" = 0, // desc: Normal. P4.28 pin is in the normal (not open drain) mode. + @"OPEN_DRAIN" = 1, // desc: Open-drain. P4.28 pin is in the open drain mode. + }, + P4_29OD: u1, // bit offset: 29 desc: Port 4 pin 29 open drain mode control, see P4.28OD + // RESERVED: u2, // bit offset: 30 desc: Reserved. padding2: u1 = 0, padding1: u1 = 0, }); // byte offset: 124 I2C Pin Configuration register pub const I2CPADCFG = mmio(Address + 0x0000007c, 32, packed struct { - SDADRV0: bool, // bit offset: 0 desc: Drive mode control for the SDA0 pin, P0.27. - SDAI2C0: bool, // bit offset: 1 desc: I 2C filter mode control for the SDA0 pin, P0.27. - SCLDRV0: bool, // bit offset: 2 desc: Drive mode control for the SCL0 pin, P0.28. - SCLI2C0: bool, // bit offset: 3 desc: I 2C filter mode control for the SCL0 pin, P0.28. + SDADRV0: enum(u1) { // bit offset: 0 desc: Drive mode control for the SDA0 pin, P0.27. + @"STANDARD" = 0, // desc: Standard. The SDA0 pin is in the standard drive mode. + @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode. + }, + SDAI2C0: enum(u1) { // bit offset: 1 desc: I 2C filter mode control for the SDA0 pin, P0.27. + @"ENABLED" = 0, // desc: Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled. + @"DISABLED" = 1, // desc: Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled. + }, + SCLDRV0: enum(u1) { // bit offset: 2 desc: Drive mode control for the SCL0 pin, P0.28. + @"STANDARD" = 0, // desc: Standard. The SCL0 pin is in the standard drive mode. + @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode. + }, + SCLI2C0: enum(u1) { // bit offset: 3 desc: I 2C filter mode control for the SCL0 pin, P0.28. + @"ENABLED" = 0, // desc: Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled. + @"DISABLED" = 1, // desc: Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled. + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4252,11 +6248,38 @@ pub const SSP1 = extern struct { pub const Address: u32 = 0x40030000; // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: u4, // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - FRF: u2, // bit offset: 4 desc: Frame Format. - CPOL: bool, // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - CPHA: bool, // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer + @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer + @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer + @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer + @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer + @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer + @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer + @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer + @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer + @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer + @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer + @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer + @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer + _, // non-exhaustive + }, + FRF: enum(u2) { // bit offset: 4 desc: Frame Format. + @"SPI" = 0, // desc: SPI + @"TI" = 1, // desc: TI + @"MICROWIRE" = 2, // desc: Microwire + @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. + }, + CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. + @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. + @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. + }, + CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. + @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. + }, SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4276,10 +6299,20 @@ pub const SSP1 = extern struct { }); // byte offset: 4 Control Register 1. Selects master/slave and other modes. pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: bool, // bit offset: 0 desc: Loop Back Mode. - SSE: bool, // bit offset: 1 desc: SSP Enable. - MS: bool, // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - SOD: bool, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. + @"NORMAL" = 0, // desc: During normal operation. + @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). + }, + SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. + @"DISABLED" = 0, // desc: The SSP controller is disabled. + @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. + }, + MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. + @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. + @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. + }, + SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4312,6 +6345,7 @@ pub const SSP1 = extern struct { // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. pub const DR = mmio(Address + 0x00000008, 32, packed struct { DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4331,11 +6365,12 @@ pub const SSP1 = extern struct { }); // byte offset: 12 Status Register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: bool, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: bool, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: bool, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: bool, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: bool, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -4367,6 +6402,7 @@ pub const SSP1 = extern struct { // byte offset: 16 Clock Prescale Register pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -4394,10 +6430,11 @@ pub const SSP1 = extern struct { }); // byte offset: 20 Interrupt Mask Set and Clear Register pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: bool, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: bool, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: bool, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: bool, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4429,10 +6466,11 @@ pub const SSP1 = extern struct { }); // byte offset: 24 Raw Interrupt Status Register pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. + TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4464,10 +6502,11 @@ pub const SSP1 = extern struct { }); // byte offset: 28 Masked Interrupt Status Register pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4499,8 +6538,9 @@ pub const SSP1 = extern struct { }); // byte offset: 32 SSPICR Interrupt Clear Register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -4534,8 +6574,9 @@ pub const SSP1 = extern struct { }); // byte offset: 36 SSP0 DMA control register pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: bool, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: bool, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. + TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -4574,16 +6615,37 @@ pub const ADC = extern struct { pub const CR = mmio(Address + 0x00000000, 32, packed struct { SEL: u8, // bit offset: 0 desc: Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. CLKDIV: u8, // bit offset: 8 desc: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. - BURST: bool, // bit offset: 16 desc: Burst mode + BURST: enum(u1) { // bit offset: 16 desc: Burst mode + @"BURST" = 1, // desc: The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start. + @"SW" = 0, // desc: Conversions are software controlled and require 31 clocks. + }, + // RESERVED: u4, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PDN: bool, // bit offset: 21 desc: Power down mode - reserved3: u1 = 0, - reserved2: u1 = 0, - START: u3, // bit offset: 24 desc: When the BURST bit is 0, these bits control whether and when an A/D conversion is started: - EDGE: bool, // bit offset: 27 desc: This bit is significant only when the START field contains 010-111. In these cases: + PDN: enum(u1) { // bit offset: 21 desc: Power down mode + @"POWERED" = 1, // desc: The A/D converter is operational. + @"POWERDOWN" = 0, // desc: The A/D converter is in power-down mode. + }, + // RESERVED: u2, // bit offset: 22 desc: Reserved. Read value is undefined, only zero should be written. + reserved6: u1 = 0, + reserved5: u1 = 0, + START: enum(u3) { // bit offset: 24 desc: When the BURST bit is 0, these bits control whether and when an A/D conversion is started: + @"NO_START_THIS_VALUE" = 0, // desc: No start (this value should be used when clearing PDN to 0). + @"START_CONVERSION_NOW" = 1, // desc: Start conversion now. + @"P2_10" = 2, // desc: Start conversion when the edge selected by bit 27 occurs on the P2[10] pin. + @"P1_27" = 3, // desc: Start conversion when the edge selected by bit 27 occurs on the P1[27] pin. + @"MAT0_1" = 4, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. + @"MAT0_3" = 5, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. + @"MAT1_0" = 6, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. + @"MAT1_1" = 7, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. + }, + EDGE: enum(u1) { // bit offset: 27 desc: This bit is significant only when the START field contains 010-111. In these cases: + @"FALLLING" = 1, // desc: Start conversion on a falling edge on the selected CAP/MAT signal. + @"RISING" = 0, // desc: Start conversion on a rising edge on the selected CAP/MAT signal. + }, + // RESERVED: u4, // bit offset: 28 desc: Reserved. Read value is undefined, only zero should be written. padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, @@ -4591,37 +6653,68 @@ pub const ADC = extern struct { }); // byte offset: 4 A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion. pub const GDR = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, + // RESERVED: u8, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). + // RESERVED: u3, // bit offset: 27 desc: Reserved. Read value is undefined, only zero should be written. reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. }); // byte offset: 12 A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. pub const INTEN = mmio(Address + 0x0000000c, 32, packed struct { - ADINTEN0: bool, // bit offset: 0 desc: Interrupt enable - ADINTEN1: bool, // bit offset: 1 desc: Interrupt enable - ADINTEN2: bool, // bit offset: 2 desc: Interrupt enable - ADINTEN3: bool, // bit offset: 3 desc: Interrupt enable - ADINTEN4: bool, // bit offset: 4 desc: Interrupt enable - ADINTEN5: bool, // bit offset: 5 desc: Interrupt enable - ADINTEN6: bool, // bit offset: 6 desc: Interrupt enable - ADINTEN7: bool, // bit offset: 7 desc: Interrupt enable - ADGINTEN: bool, // bit offset: 8 desc: Interrupt enable + ADINTEN0: enum(u1) { // bit offset: 0 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 0 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 0 will generate an interrupt. + }, + ADINTEN1: enum(u1) { // bit offset: 1 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 1 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 1 will generate an interrupt. + }, + ADINTEN2: enum(u1) { // bit offset: 2 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 2 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 2 will generate an interrupt. + }, + ADINTEN3: enum(u1) { // bit offset: 3 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 3 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 3 will generate an interrupt. + }, + ADINTEN4: enum(u1) { // bit offset: 4 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 4 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 4 will generate an interrupt. + }, + ADINTEN5: enum(u1) { // bit offset: 5 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 5 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 5 will generate an interrupt. + }, + ADINTEN6: enum(u1) { // bit offset: 6 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 6 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 6 will generate an interrupt. + }, + ADINTEN7: enum(u1) { // bit offset: 7 desc: Interrupt enable + @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 7 will not generate an interrupt. + @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 7 will generate an interrupt. + }, + ADGINTEN: enum(u1) { // bit offset: 8 desc: Interrupt enable + @"CHANNELS" = 0, // desc: Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts. + @"GLOBAL" = 1, // desc: The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts. + }, + // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -4648,215 +6741,232 @@ pub const ADC = extern struct { }); // byte offset: 16 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_0 = mmio(Address + 0x00000010, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 20 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_1 = mmio(Address + 0x00000014, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 24 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_2 = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 28 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_3 = mmio(Address + 0x0000001c, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 32 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_4 = mmio(Address + 0x00000020, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 36 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_5 = mmio(Address + 0x00000024, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 40 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_6 = mmio(Address + 0x00000028, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 44 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. pub const DR_7 = mmio(Address + 0x0000002c, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, + // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, - OVERRUN: bool, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: bool, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. + DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. }); // byte offset: 48 A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. pub const STAT = mmio(Address + 0x00000030, 32, packed struct { - DONE0: bool, // bit offset: 0 desc: This bit mirrors the DONE status flag from the result register for A/D channel 0. - DONE1: bool, // bit offset: 1 desc: This bit mirrors the DONE status flag from the result register for A/D channel 1. - DONE2: bool, // bit offset: 2 desc: This bit mirrors the DONE status flag from the result register for A/D channel 2. - DONE3: bool, // bit offset: 3 desc: This bit mirrors the DONE status flag from the result register for A/D channel 3. - DONE4: bool, // bit offset: 4 desc: This bit mirrors the DONE status flag from the result register for A/D channel 4. - DONE5: bool, // bit offset: 5 desc: This bit mirrors the DONE status flag from the result register for A/D channel 5. - DONE6: bool, // bit offset: 6 desc: This bit mirrors the DONE status flag from the result register for A/D channel 6. - DONE7: bool, // bit offset: 7 desc: This bit mirrors the DONE status flag from the result register for A/D channel 7. - OVERRUN0: bool, // bit offset: 8 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. - OVERRUN1: bool, // bit offset: 9 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. - OVERRUN2: bool, // bit offset: 10 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. - OVERRUN3: bool, // bit offset: 11 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. - OVERRUN4: bool, // bit offset: 12 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. - OVERRUN5: bool, // bit offset: 13 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. - OVERRUN6: bool, // bit offset: 14 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. - OVERRUN7: bool, // bit offset: 15 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. - ADINT: bool, // bit offset: 16 desc: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. + DONE0: u1, // bit offset: 0 desc: This bit mirrors the DONE status flag from the result register for A/D channel 0. + DONE1: u1, // bit offset: 1 desc: This bit mirrors the DONE status flag from the result register for A/D channel 1. + DONE2: u1, // bit offset: 2 desc: This bit mirrors the DONE status flag from the result register for A/D channel 2. + DONE3: u1, // bit offset: 3 desc: This bit mirrors the DONE status flag from the result register for A/D channel 3. + DONE4: u1, // bit offset: 4 desc: This bit mirrors the DONE status flag from the result register for A/D channel 4. + DONE5: u1, // bit offset: 5 desc: This bit mirrors the DONE status flag from the result register for A/D channel 5. + DONE6: u1, // bit offset: 6 desc: This bit mirrors the DONE status flag from the result register for A/D channel 6. + DONE7: u1, // bit offset: 7 desc: This bit mirrors the DONE status flag from the result register for A/D channel 7. + OVERRUN0: u1, // bit offset: 8 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. + OVERRUN1: u1, // bit offset: 9 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. + OVERRUN2: u1, // bit offset: 10 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. + OVERRUN3: u1, // bit offset: 11 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. + OVERRUN4: u1, // bit offset: 12 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. + OVERRUN5: u1, // bit offset: 13 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. + OVERRUN6: u1, // bit offset: 14 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. + OVERRUN7: u1, // bit offset: 15 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. + ADINT: u1, // bit offset: 16 desc: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. + // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -4875,12 +6985,14 @@ pub const ADC = extern struct { }); // byte offset: 52 ADC trim register. pub const TRM = mmio(Address + 0x00000034, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, ADCOFFS: u4, // bit offset: 4 desc: Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. TRIM: u4, // bit offset: 8 desc: written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. + // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -6958,9 +9070,13 @@ pub const CANAF = extern struct { pub const Address: u32 = 0x4003c000; // byte offset: 0 Acceptance Filter Register pub const AFMR = mmio(Address + 0x00000000, 32, packed struct { - ACCOFF: bool, // bit offset: 0 desc: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. - ACCBP: bool, // bit offset: 1 desc: All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. - EFCAN: bool, // bit offset: 2 desc: FullCAN mode + ACCOFF: u1, // bit offset: 0 desc: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. + ACCBP: u1, // bit offset: 1 desc: All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. + EFCAN: enum(u1) { // bit offset: 2 desc: FullCAN mode + @"SOFTWARE_MUST_READ_A" = 0, // desc: Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers. + @"THE_ACCEPTANCE_FILTE" = 1, // desc: The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -6993,9 +9109,11 @@ pub const CANAF = extern struct { }); // byte offset: 4 Standard Frame Individual Start Address Register pub const SFF_SA = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, SFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7020,9 +9138,11 @@ pub const CANAF = extern struct { }); // byte offset: 8 Standard Frame Group Start Address Register pub const SFF_GRP_SA = mmio(Address + 0x00000008, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, SFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. + // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -7046,9 +9166,11 @@ pub const CANAF = extern struct { }); // byte offset: 12 Extended Frame Start Address Register pub const EFF_SA = mmio(Address + 0x0000000c, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, EFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7073,9 +9195,11 @@ pub const CANAF = extern struct { }); // byte offset: 16 Extended Frame Group Start Address Register pub const EFF_GRP_SA = mmio(Address + 0x00000010, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, EFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. + // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -7099,9 +9223,11 @@ pub const CANAF = extern struct { }); // byte offset: 20 End of AF Tables register pub const ENDOFTABLE = mmio(Address + 0x00000014, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, ENDOFTABLE: u10, // bit offset: 2 desc: The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. + // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -7125,9 +9251,11 @@ pub const CANAF = extern struct { }); // byte offset: 24 LUT Error Address register pub const LUTERRAD = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, LUTERRAD: u9, // bit offset: 2 desc: It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7152,7 +9280,8 @@ pub const CANAF = extern struct { }); // byte offset: 28 LUT Error Register pub const LUTERR = mmio(Address + 0x0000001c, 32, packed struct { - LUTERR: bool, // bit offset: 0 desc: This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. + LUTERR: u1, // bit offset: 0 desc: This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. + // RESERVED: u31, // bit offset: 1 desc: Reserved, the value read from a reserved bit is not defined. padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -7187,7 +9316,8 @@ pub const CANAF = extern struct { }); // byte offset: 32 FullCAN interrupt enable register pub const FCANIE = mmio(Address + 0x00000020, 32, packed struct { - FCANIE: bool, // bit offset: 0 desc: Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. + FCANIE: u1, // bit offset: 0 desc: Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. + // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -7233,24 +9363,27 @@ pub const CCAN = extern struct { pub const Address: u32 = 0x40040000; // byte offset: 0 CAN Central Transmit Status Register pub const TXSR = mmio(Address + 0x00000000, 32, packed struct { - TS1: bool, // bit offset: 0 desc: When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). - TS2: bool, // bit offset: 1 desc: When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) + TS1: u1, // bit offset: 0 desc: When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). + TS2: u1, // bit offset: 1 desc: When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) + // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TBS1: bool, // bit offset: 8 desc: When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). - TBS2: bool, // bit offset: 9 desc: When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). + TBS1: u1, // bit offset: 8 desc: When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). + TBS2: u1, // bit offset: 9 desc: When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). + // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - TCS1: bool, // bit offset: 16 desc: When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). - TCS2: bool, // bit offset: 17 desc: When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). + TCS1: u1, // bit offset: 16 desc: When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). + TCS2: u1, // bit offset: 17 desc: When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). + // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -7268,24 +9401,27 @@ pub const CCAN = extern struct { }); // byte offset: 4 CAN Central Receive Status Register pub const RXSR = mmio(Address + 0x00000004, 32, packed struct { - RS1: bool, // bit offset: 0 desc: When 1, CAN1 is receiving a message (same as RS in CAN1GSR). - RS2: bool, // bit offset: 1 desc: When 1, CAN2 is receiving a message (same as RS in CAN2GSR). + RS1: u1, // bit offset: 0 desc: When 1, CAN1 is receiving a message (same as RS in CAN1GSR). + RS2: u1, // bit offset: 1 desc: When 1, CAN2 is receiving a message (same as RS in CAN2GSR). + // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RB1: bool, // bit offset: 8 desc: When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). - RB2: bool, // bit offset: 9 desc: When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). + RB1: u1, // bit offset: 8 desc: When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). + RB2: u1, // bit offset: 9 desc: When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). + // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - DOS1: bool, // bit offset: 16 desc: When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). - DOS2: bool, // bit offset: 17 desc: When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). + DOS1: u1, // bit offset: 16 desc: When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). + DOS2: u1, // bit offset: 17 desc: When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). + // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -7303,16 +9439,18 @@ pub const CCAN = extern struct { }); // byte offset: 8 CAN Central Miscellaneous Register pub const MSR = mmio(Address + 0x00000008, 32, packed struct { - E1: bool, // bit offset: 0 desc: When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) - E2: bool, // bit offset: 1 desc: When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) + E1: u1, // bit offset: 0 desc: When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) + E2: u1, // bit offset: 1 desc: When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) + // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BS1: bool, // bit offset: 8 desc: When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). - BS2: bool, // bit offset: 9 desc: When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). + BS1: u1, // bit offset: 8 desc: When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). + BS2: u1, // bit offset: 9 desc: When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). + // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -7341,14 +9479,37 @@ pub const CAN1 = extern struct { pub const Address: u32 = 0x40044000; // byte offset: 0 Controls the operating mode of the CAN Controller. pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: bool, // bit offset: 0 desc: Reset Mode. - LOM: bool, // bit offset: 1 desc: Listen Only Mode. - STM: bool, // bit offset: 2 desc: Self Test Mode. - TPM: bool, // bit offset: 3 desc: Transmit Priority Mode. - SM: bool, // bit offset: 4 desc: Sleep Mode. - RPM: bool, // bit offset: 5 desc: Receive Polarity Mode. + RM: enum(u1) { // bit offset: 0 desc: Reset Mode. + @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. + @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. + }, + LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. + @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. + @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. + }, + STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. + @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. + @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. + }, + TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. + @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. + @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. + }, + SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. + @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. + @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. + }, + RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. + @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). + @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. + }, + // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - TM: bool, // bit offset: 7 desc: Test Mode. + TM: enum(u1) { // bit offset: 7 desc: Test Mode. + @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. + @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7376,14 +9537,39 @@ pub const CAN1 = extern struct { }); // byte offset: 4 Command bits that affect the state of the CAN Controller pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: bool, // bit offset: 0 desc: Transmission Request. - AT: bool, // bit offset: 1 desc: Abort Transmission. - RRB: bool, // bit offset: 2 desc: Release Receive Buffer. - CDO: bool, // bit offset: 3 desc: Clear Data Overrun. - SRR: bool, // bit offset: 4 desc: Self Reception Request. - STB1: bool, // bit offset: 5 desc: Select Tx Buffer 1. - STB2: bool, // bit offset: 6 desc: Select Tx Buffer 2. - STB3: bool, // bit offset: 7 desc: Select Tx Buffer 3. + TR: enum(u1) { // bit offset: 0 desc: Transmission Request. + @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. + @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) + }, + AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. + @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. + @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. + }, + RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. + @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. + @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). + }, + CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. + @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. + @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. + }, + SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. + @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. + @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. + }, + STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. + }, + STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. + }, + STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7411,14 +9597,39 @@ pub const CAN1 = extern struct { }); // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: bool, // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - DOS: bool, // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - TBS: bool, // bit offset: 2 desc: Transmit Buffer Status. - TCS: bool, // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - RS: bool, // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - TS: bool, // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - ES: bool, // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - BS: bool, // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. + @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. + @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. + }, + DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. + @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). + @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). + }, + TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. + @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). + @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. + @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. + @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. + }, + RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. + @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. + }, + TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. + }, + ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). + @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. + @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. + }, + BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities + @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. + }, + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -7432,40 +9643,83 @@ pub const CAN1 = extern struct { }); // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: bool, // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - TI1: bool, // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - EI: bool, // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - DOI: bool, // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - WUI: bool, // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - EPI: bool, // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - ALI: bool, // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - BEI: bool, // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - IDI: bool, // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - TI2: bool, // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - TI3: bool, // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: bool, // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - ERRC1_0: u2, // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. + @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. + @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. + }, + ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + @"BIT_ERROR" = 0, // desc: Bit error + @"FORM_ERROR" = 1, // desc: Form error + @"STUFF_ERROR" = 2, // desc: Stuff error + @"OTHER_ERROR" = 3, // desc: Other error + }, ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. }); // byte offset: 16 Interrupt Enable pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: bool, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: bool, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: bool, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: bool, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: bool, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: bool, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: bool, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: bool, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: bool, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: bool, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: bool, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. + TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. + DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. + WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. + EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. + ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. + BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. + IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. + TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7491,6 +9745,7 @@ pub const CAN1 = extern struct { // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. pub const BTR = mmio(Address + 0x00000014, 32, packed struct { BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. + // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, @@ -7498,7 +9753,11 @@ pub const CAN1 = extern struct { SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: bool, // bit offset: 23 desc: Sampling + SAM: enum(u1) { // bit offset: 23 desc: Sampling + @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) + @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) + }, + // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -7511,6 +9770,7 @@ pub const CAN1 = extern struct { // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. pub const EWL = mmio(Address + 0x00000018, 32, packed struct { EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7538,30 +9798,58 @@ pub const CAN1 = extern struct { }); // byte offset: 28 Status Register pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: bool, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: bool, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: bool, // bit offset: 2 desc: Transmit Buffer Status 1. - TCS1_1: bool, // bit offset: 3 desc: Transmission Complete Status. - RS_1: bool, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: bool, // bit offset: 5 desc: Transmit Status 1. - ES_1: bool, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: bool, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: bool, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: bool, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: bool, // bit offset: 10 desc: Transmit Buffer Status 2. - TCS2_2: bool, // bit offset: 11 desc: Transmission Complete Status. - RS_2: bool, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: bool, // bit offset: 13 desc: Transmit Status 2. - ES_2: bool, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: bool, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: bool, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: bool, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: bool, // bit offset: 18 desc: Transmit Buffer Status 3. - TCS3_3: bool, // bit offset: 19 desc: Transmission Complete Status. - RS_3: bool, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: bool, // bit offset: 21 desc: Transmit Status 3. - ES_3: bool, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: bool, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. + }, + RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. + }, + ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. + }, + RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. + }, + ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. + }, + RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. + }, + ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -7574,13 +9862,16 @@ pub const CAN1 = extern struct { // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. pub const RFS = mmio(Address + 0x00000020, 32, packed struct { IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: bool, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -7590,13 +9881,13 @@ pub const CAN1 = extern struct { reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. + RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. + FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. }); // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. pub const RID = mmio(Address + 0x00000024, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7636,6 +9927,7 @@ pub const CAN1 = extern struct { // byte offset: 48 Transmit frame info (Tx Buffer ) pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -7645,22 +9937,45 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 52 Transmit Identifier (Tx Buffer) pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { @@ -7679,6 +9994,7 @@ pub const CAN1 = extern struct { // byte offset: 64 Transmit frame info (Tx Buffer ) pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -7688,41 +10004,65 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 68 Transmit Identifier (Tx Buffer) pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - reserved8: u1 = 0, + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) + pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { + DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. + DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. + DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. + DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + }); + // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) + pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { + DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. + DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. + DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. + DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. + }); + // byte offset: 80 Transmit frame info (Tx Buffer ) + pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { + PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. + reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -7731,22 +10071,45 @@ pub const CAN1 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 84 Transmit Identifier (Tx Buffer) pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { @@ -7767,14 +10130,37 @@ pub const CAN2 = extern struct { pub const Address: u32 = 0x40048000; // byte offset: 0 Controls the operating mode of the CAN Controller. pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: bool, // bit offset: 0 desc: Reset Mode. - LOM: bool, // bit offset: 1 desc: Listen Only Mode. - STM: bool, // bit offset: 2 desc: Self Test Mode. - TPM: bool, // bit offset: 3 desc: Transmit Priority Mode. - SM: bool, // bit offset: 4 desc: Sleep Mode. - RPM: bool, // bit offset: 5 desc: Receive Polarity Mode. + RM: enum(u1) { // bit offset: 0 desc: Reset Mode. + @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. + @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. + }, + LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. + @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. + @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. + }, + STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. + @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. + @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. + }, + TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. + @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. + @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. + }, + SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. + @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. + @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. + }, + RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. + @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). + @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. + }, + // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - TM: bool, // bit offset: 7 desc: Test Mode. + TM: enum(u1) { // bit offset: 7 desc: Test Mode. + @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. + @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7802,14 +10188,39 @@ pub const CAN2 = extern struct { }); // byte offset: 4 Command bits that affect the state of the CAN Controller pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: bool, // bit offset: 0 desc: Transmission Request. - AT: bool, // bit offset: 1 desc: Abort Transmission. - RRB: bool, // bit offset: 2 desc: Release Receive Buffer. - CDO: bool, // bit offset: 3 desc: Clear Data Overrun. - SRR: bool, // bit offset: 4 desc: Self Reception Request. - STB1: bool, // bit offset: 5 desc: Select Tx Buffer 1. - STB2: bool, // bit offset: 6 desc: Select Tx Buffer 2. - STB3: bool, // bit offset: 7 desc: Select Tx Buffer 3. + TR: enum(u1) { // bit offset: 0 desc: Transmission Request. + @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. + @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) + }, + AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. + @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. + @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. + }, + RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. + @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. + @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). + }, + CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. + @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. + @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. + }, + SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. + @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. + @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. + }, + STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. + }, + STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. + }, + STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. + @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. + @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7837,14 +10248,39 @@ pub const CAN2 = extern struct { }); // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: bool, // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - DOS: bool, // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - TBS: bool, // bit offset: 2 desc: Transmit Buffer Status. - TCS: bool, // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - RS: bool, // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - TS: bool, // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - ES: bool, // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - BS: bool, // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. + @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. + @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. + }, + DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. + @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). + @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). + }, + TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. + @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). + @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. + @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. + @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. + }, + RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. + @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. + }, + TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. + @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. + }, + ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). + @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. + @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. + }, + BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. + @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities + @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. + }, + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -7858,40 +10294,83 @@ pub const CAN2 = extern struct { }); // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: bool, // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - TI1: bool, // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - EI: bool, // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - DOI: bool, // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - WUI: bool, // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - EPI: bool, // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - ALI: bool, // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - BEI: bool, // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - IDI: bool, // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - TI2: bool, // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - TI3: bool, // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. + @"RESET" = 0, // desc: Reset + @"SET" = 1, // desc: Set + }, + // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: bool, // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - ERRC1_0: u2, // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. + @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. + @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. + }, + ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: + @"BIT_ERROR" = 0, // desc: Bit error + @"FORM_ERROR" = 1, // desc: Form error + @"STUFF_ERROR" = 2, // desc: Stuff error + @"OTHER_ERROR" = 3, // desc: Other error + }, ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. }); // byte offset: 16 Interrupt Enable pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: bool, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: bool, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: bool, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: bool, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: bool, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: bool, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: bool, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: bool, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: bool, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: bool, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: bool, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. + TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. + DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. + WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. + EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. + ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. + BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. + IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. + TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -7917,6 +10396,7 @@ pub const CAN2 = extern struct { // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. pub const BTR = mmio(Address + 0x00000014, 32, packed struct { BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. + // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, @@ -7924,7 +10404,11 @@ pub const CAN2 = extern struct { SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: bool, // bit offset: 23 desc: Sampling + SAM: enum(u1) { // bit offset: 23 desc: Sampling + @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) + @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) + }, + // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -7937,6 +10421,7 @@ pub const CAN2 = extern struct { // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. pub const EWL = mmio(Address + 0x00000018, 32, packed struct { EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7964,30 +10449,58 @@ pub const CAN2 = extern struct { }); // byte offset: 28 Status Register pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: bool, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: bool, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: bool, // bit offset: 2 desc: Transmit Buffer Status 1. - TCS1_1: bool, // bit offset: 3 desc: Transmission Complete Status. - RS_1: bool, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: bool, // bit offset: 5 desc: Transmit Status 1. - ES_1: bool, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: bool, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: bool, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: bool, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: bool, // bit offset: 10 desc: Transmit Buffer Status 2. - TCS2_2: bool, // bit offset: 11 desc: Transmission Complete Status. - RS_2: bool, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: bool, // bit offset: 13 desc: Transmit Status 2. - ES_2: bool, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: bool, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: bool, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: bool, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: bool, // bit offset: 18 desc: Transmit Buffer Status 3. - TCS3_3: bool, // bit offset: 19 desc: Transmission Complete Status. - RS_3: bool, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: bool, // bit offset: 21 desc: Transmit Status 3. - ES_3: bool, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: bool, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. + }, + RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. + }, + ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. + }, + RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. + }, + ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. + @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. + @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. + }, + TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. + @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. + @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. + }, + RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. + TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. + @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. + @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. + }, + ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. + BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. + // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -8000,13 +10513,16 @@ pub const CAN2 = extern struct { // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. pub const RFS = mmio(Address + 0x00000020, 32, packed struct { IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: bool, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. + // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -8016,13 +10532,13 @@ pub const CAN2 = extern struct { reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: bool, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. + RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. + FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. }); // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. pub const RID = mmio(Address + 0x00000024, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -8062,6 +10578,7 @@ pub const CAN2 = extern struct { // byte offset: 48 Transmit frame info (Tx Buffer ) pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -8071,58 +10588,45 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 48 Transmit frame info (Tx Buffer ) - pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 52 Transmit Identifier (Tx Buffer) pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 52 Transmit Identifier (Tx Buffer) - pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { @@ -8138,41 +10642,10 @@ pub const CAN2 = extern struct { DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. }); - // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 64 Transmit frame info (Tx Buffer ) - pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); // byte offset: 64 Transmit frame info (Tx Buffer ) pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -8182,33 +10655,45 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 68 Transmit Identifier (Tx Buffer) pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 68 Transmit Identifier (Tx Buffer) - pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { @@ -8224,41 +10709,10 @@ pub const CAN2 = extern struct { DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); // byte offset: 80 Transmit frame info (Tx Buffer ) pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. + // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -8268,33 +10722,45 @@ pub const CAN2 = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes + // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - RTR: bool, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: bool, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). + RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. + FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). }); // byte offset: 84 Transmit Identifier (Tx Buffer) pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 84 Transmit Identifier (Tx Buffer) - pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - }); - // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. + // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { @@ -8310,25 +10776,20 @@ pub const CAN2 = extern struct { DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. }); - // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); }; pub const I2C1 = extern struct { pub const Address: u32 = 0x4005c000; // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - AA: bool, // bit offset: 2 desc: Assert acknowledge flag. - SI: bool, // bit offset: 3 desc: I2C interrupt flag. - STO: bool, // bit offset: 4 desc: STOP flag. - STA: bool, // bit offset: 5 desc: START flag. - I2EN: bool, // bit offset: 6 desc: I2C interface enable. + AA: u1, // bit offset: 2 desc: Assert acknowledge flag. + SI: u1, // bit offset: 3 desc: I2C interrupt flag. + STO: u1, // bit offset: 4 desc: STOP flag. + STA: u1, // bit offset: 5 desc: START flag. + I2EN: u1, // bit offset: 6 desc: I2C interface enable. + // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8357,10 +10818,12 @@ pub const I2C1 = extern struct { }); // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8389,6 +10852,7 @@ pub const I2C1 = extern struct { // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. pub const DAT = mmio(Address + 0x00000008, 32, packed struct { Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8416,8 +10880,9 @@ pub const I2C1 = extern struct { }); // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8446,6 +10911,7 @@ pub const I2C1 = extern struct { // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8466,6 +10932,7 @@ pub const I2C1 = extern struct { // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8485,13 +10952,17 @@ pub const I2C1 = extern struct { }); // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. - reserved2: u1 = 0, - STAC: bool, // bit offset: 5 desc: START flag Clear bit. - I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. + AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. + // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved3: u1 = 0, + STAC: u1, // bit offset: 5 desc: START flag Clear bit. + I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. + // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8520,9 +10991,19 @@ pub const I2C1 = extern struct { }); // byte offset: 28 Monitor mode control register. pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. - ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. - MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. + MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. + @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. + @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. + }, + ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] + }, + MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -8555,37 +11036,98 @@ pub const I2C1 = extern struct { }); // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8613,54 +11155,165 @@ pub const I2C1 = extern struct { }); // byte offset: 48 I2C Slave address mask register pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 52 I2C Slave address mask register pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 56 I2C Slave address mask register pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 60 I2C Slave address mask register pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); }; pub const SSP0 = extern struct { pub const Address: u32 = 0x40088000; // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: u4, // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - FRF: u2, // bit offset: 4 desc: Frame Format. - CPOL: bool, // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - CPHA: bool, // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer + @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer + @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer + @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer + @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer + @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer + @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer + @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer + @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer + @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer + @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer + @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer + @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer + _, // non-exhaustive + }, + FRF: enum(u2) { // bit offset: 4 desc: Frame Format. + @"SPI" = 0, // desc: SPI + @"TI" = 1, // desc: TI + @"MICROWIRE" = 2, // desc: Microwire + @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. + }, + CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. + @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. + @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. + }, + CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. + @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. + @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. + }, SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8680,10 +11333,20 @@ pub const SSP0 = extern struct { }); // byte offset: 4 Control Register 1. Selects master/slave and other modes. pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: bool, // bit offset: 0 desc: Loop Back Mode. - SSE: bool, // bit offset: 1 desc: SSP Enable. - MS: bool, // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - SOD: bool, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. + @"NORMAL" = 0, // desc: During normal operation. + @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). + }, + SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. + @"DISABLED" = 0, // desc: The SSP controller is disabled. + @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. + }, + MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. + @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. + @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. + }, + SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -8716,6 +11379,7 @@ pub const SSP0 = extern struct { // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. pub const DR = mmio(Address + 0x00000008, 32, packed struct { DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8735,11 +11399,12 @@ pub const SSP0 = extern struct { }); // byte offset: 12 Status Register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: bool, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: bool, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: bool, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: bool, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: bool, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -8771,6 +11436,7 @@ pub const SSP0 = extern struct { // byte offset: 16 Clock Prescale Register pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8798,10 +11464,11 @@ pub const SSP0 = extern struct { }); // byte offset: 20 Interrupt Mask Set and Clear Register pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: bool, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: bool, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: bool, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: bool, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -8833,10 +11500,11 @@ pub const SSP0 = extern struct { }); // byte offset: 24 Raw Interrupt Status Register pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. + TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -8868,10 +11536,11 @@ pub const SSP0 = extern struct { }); // byte offset: 28 Masked Interrupt Status Register pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: bool, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: bool, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: bool, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: bool, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -8903,8 +11572,9 @@ pub const SSP0 = extern struct { }); // byte offset: 32 SSPICR Interrupt Clear Register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -8938,8 +11608,9 @@ pub const SSP0 = extern struct { }); // byte offset: 36 SSP0 DMA control register pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: bool, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: bool, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. + TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -8976,6 +11647,7 @@ pub const DAC = extern struct { pub const Address: u32 = 0x4008c000; // byte offset: 0 D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. pub const CR = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u6, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, @@ -8983,7 +11655,11 @@ pub const DAC = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, VALUE: u10, // bit offset: 6 desc: After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN. - BIAS: bool, // bit offset: 16 desc: Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. + BIAS: enum(u1) { // bit offset: 16 desc: Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. + @"FAST" = 0, // desc: The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. + @"SLOW" = 1, // desc: The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. + }, + // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -9002,10 +11678,23 @@ pub const DAC = extern struct { }); // byte offset: 4 DAC Control register. This register controls DMA and timer operation. pub const CTRL = mmio(Address + 0x00000004, 32, packed struct { - INT_DMA_REQ: bool, // bit offset: 0 desc: DMA interrupt request - DBLBUF_ENA: bool, // bit offset: 1 desc: Double buffering - CNT_ENA: bool, // bit offset: 2 desc: Time-out counter operation - DMA_ENA: bool, // bit offset: 3 desc: DMA access + INT_DMA_REQ: enum(u1) { // bit offset: 0 desc: DMA interrupt request + @"CLEAR_ON_ANY_WRITE_T" = 0, // desc: Clear on any write to the DACR register. + @"SET_BY_HARDWARE_WHEN" = 1, // desc: Set by hardware when the timer times out. + }, + DBLBUF_ENA: enum(u1) { // bit offset: 1 desc: Double buffering + @"DISABLE" = 0, // desc: Disable + @"ENABLE_WHEN_THIS_BI" = 1, // desc: Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. + }, + CNT_ENA: enum(u1) { // bit offset: 2 desc: Time-out counter operation + @"DISABLE" = 0, // desc: Disable + @"ENABLE" = 1, // desc: Enable + }, + DMA_ENA: enum(u1) { // bit offset: 3 desc: DMA access + @"DISABLE" = 0, // desc: Disable + @"ENABLE_DMA_BURST_RE" = 1, // desc: Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672). + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -9038,6 +11727,7 @@ pub const DAC = extern struct { // byte offset: 8 DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. pub const CNTVAL = mmio(Address + 0x00000008, 32, packed struct { VALUE: u16, // bit offset: 0 desc: 16-bit reload value for the DAC interrupt/DMA timer. + // RESERVED: u16, // bit offset: 16 desc: Reserved padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9060,12 +11750,13 @@ pub const TIMER2 = extern struct { pub const Address: u32 = 0x40090000; // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -9095,8 +11786,9 @@ pub const TIMER2 = extern struct { }); // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9142,18 +11834,55 @@ pub const TIMER2 = extern struct { }); // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 - MR0R: bool, // bit offset: 1 desc: Reset on MR0 - MR0S: bool, // bit offset: 2 desc: Stop on MR0 - MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 - MR1R: bool, // bit offset: 4 desc: Reset on MR1 - MR1S: bool, // bit offset: 5 desc: Stop on MR1 - MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 - MR2R: bool, // bit offset: 7 desc: Reset on MR2 - MR2S: bool, // bit offset: 8 desc: Stop on MR2. - MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 - MR3R: bool, // bit offset: 10 desc: Reset on MR3 - MR3S: bool, // bit offset: 11 desc: Stop on MR3 + MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. + }, + MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. + @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled + }, + MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9179,14 +11908,6 @@ pub const TIMER2 = extern struct { pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. @@ -9195,26 +11916,37 @@ pub const TIMER2 = extern struct { pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge - CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge - CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event - CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge - CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge - CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event + @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event + @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -9246,28 +11978,41 @@ pub const TIMER2 = extern struct { pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); // byte offset: 60 External Match Register. The EMR controls the external match pins. pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9291,8 +12036,18 @@ pub const TIMER2 = extern struct { }); // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge + @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + }, + CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn + @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn + _, // non-exhaustive + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -9327,12 +12082,13 @@ pub const TIMER3 = extern struct { pub const Address: u32 = 0x40094000; // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: bool, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: bool, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: bool, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: bool, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: bool, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: bool, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. + MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. + MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. + MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. + CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. + CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -9362,8 +12118,9 @@ pub const TIMER3 = extern struct { }); // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: bool, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: bool, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9409,18 +12166,55 @@ pub const TIMER3 = extern struct { }); // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: bool, // bit offset: 0 desc: Interrupt on MR0 - MR0R: bool, // bit offset: 1 desc: Reset on MR0 - MR0S: bool, // bit offset: 2 desc: Stop on MR0 - MR1I: bool, // bit offset: 3 desc: Interrupt on MR1 - MR1R: bool, // bit offset: 4 desc: Reset on MR1 - MR1S: bool, // bit offset: 5 desc: Stop on MR1 - MR2I: bool, // bit offset: 6 desc: Interrupt on MR2 - MR2R: bool, // bit offset: 7 desc: Reset on MR2 - MR2S: bool, // bit offset: 8 desc: Stop on MR2. - MR3I: bool, // bit offset: 9 desc: Interrupt on MR3 - MR3R: bool, // bit offset: 10 desc: Reset on MR3 - MR3S: bool, // bit offset: 11 desc: Stop on MR3 + MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. + }, + MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. + @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled + }, + MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 + @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. + @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled + }, + MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 + @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 + @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9446,14 +12240,6 @@ pub const TIMER3 = extern struct { pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. @@ -9462,26 +12248,37 @@ pub const TIMER3 = extern struct { pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { MATCH: u32, // bit offset: 0 desc: Timer counter match value. }); // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: bool, // bit offset: 0 desc: Capture on CAPn.0 rising edge - CAP0FE: bool, // bit offset: 1 desc: Capture on CAPn.0 falling edge - CAP0I: bool, // bit offset: 2 desc: Interrupt on CAPn.0 event - CAP1RE: bool, // bit offset: 3 desc: Capture on CAPn.1 rising edge - CAP1FE: bool, // bit offset: 4 desc: Capture on CAPn.1 falling edge - CAP1I: bool, // bit offset: 5 desc: Interrupt on CAPn.1 event + CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event + @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge + @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge + @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event + @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. + @"DISABLE" = 0, // desc: This feature is disabled. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -9513,28 +12310,41 @@ pub const TIMER3 = extern struct { pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { CAP: u32, // bit offset: 0 desc: Timer counter capture value. }); // byte offset: 60 External Match Register. The EMR controls the external match pins. pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: bool, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: bool, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: bool, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: bool, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: u2, // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - EMC1: u2, // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - EMC2: u2, // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - EMC3: u2, // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). + EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). + EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. + @"DO_NOTHING_" = 0, // desc: Do Nothing. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). + @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). + @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9558,8 +12368,18 @@ pub const TIMER3 = extern struct { }); // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: u2, // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - CINSEL: u2, // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge + @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + }, + CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn + @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn + _, // non-exhaustive + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -9595,6 +12415,7 @@ pub const UART2 = extern struct { // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). pub const RBR = mmio(Address + 0x00000000, 32, packed struct { RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9623,6 +12444,7 @@ pub const UART2 = extern struct { // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). pub const THR = mmio(Address + 0x00000000, 32, packed struct { THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9651,6 +12473,7 @@ pub const UART2 = extern struct { // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLL = mmio(Address + 0x00000000, 32, packed struct { DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9679,6 +12502,7 @@ pub const UART2 = extern struct { // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLM = mmio(Address + 0x00000004, 32, packed struct { DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9706,16 +12530,33 @@ pub const UART2 = extern struct { }); // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. + @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. + }, + THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. + @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. + }, + RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. + @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. - ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. + @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. + @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. + }, + ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. + @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9741,13 +12582,24 @@ pub const UART2 = extern struct { }); // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. + @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. + }, + INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). + @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). + @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). + @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt + _, // non-exhaustive + }, + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9773,13 +12625,29 @@ pub const UART2 = extern struct { }); // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. - RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. - TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. - DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. + @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. + @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. + }, + RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. + }, + TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. + }, + DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, - RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). + @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). + @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). + @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9807,12 +12675,35 @@ pub const UART2 = extern struct { }); // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: u2, // bit offset: 0 desc: Word Length Select. - SBS: bool, // bit offset: 2 desc: Stop Bit Select - PE: bool, // bit offset: 3 desc: Parity Enable. - PS: u2, // bit offset: 4 desc: Parity Select - BC: bool, // bit offset: 6 desc: Break Control - DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. + @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length + @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length + @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length + @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length + }, + SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select + @"1_STOP_BIT_" = 0, // desc: 1 stop bit. + @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). + }, + PE: enum(u1) { // bit offset: 3 desc: Parity Enable. + @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. + @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. + }, + PS: enum(u2) { // bit offset: 4 desc: Parity Select + @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. + @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. + @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. + @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. + }, + BC: enum(u1) { // bit offset: 6 desc: Break Control + @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. + @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. + }, + DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit + @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. + @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9840,14 +12731,39 @@ pub const UART2 = extern struct { }); // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. + @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. + }, + OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + @"INACTIVE" = 0, // desc: Overrun error status is inactive. + @"ACTIVE" = 1, // desc: Overrun error status is active. + }, + PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Parity error status is inactive. + @"ACTIVE" = 1, // desc: Parity error status is active. + }, + FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Framing error status is inactive. + @"ACTIVE" = 1, // desc: Framing error status is active. + }, + BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Break interrupt status is inactive. + @"ACTIVE" = 1, // desc: Break interrupt status is active. + }, + THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + @"VALIDDATA" = 0, // desc: UnTHR contains valid data. + @"EMPTY" = 1, // desc: UnTHR is empty. + }, + TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. + @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. + }, + RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. + @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9876,6 +12792,7 @@ pub const UART2 = extern struct { // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { PAD: u8, // bit offset: 0 desc: A readable, writable byte. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9903,16 +12820,33 @@ pub const UART2 = extern struct { }); // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. - AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). + @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. + }, + MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. + @"MODE_0_" = 0, // desc: Mode 0. + @"MODE_1_" = 1, // desc: Mode 1. + }, + AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. + @"NO_RESTART_" = 0, // desc: No restart. + @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9940,6 +12874,7 @@ pub const UART2 = extern struct { pub const FDR = mmio(Address + 0x00000028, 32, packed struct { DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9967,6 +12902,7 @@ pub const UART2 = extern struct { }); // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. pub const TER = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -9974,7 +12910,8 @@ pub const UART2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10002,12 +12939,29 @@ pub const UART2 = extern struct { }); // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: bool, // bit offset: 0 desc: NMM enable. - RXDIS: bool, // bit offset: 1 desc: Receiver enable. - AADEN: bool, // bit offset: 2 desc: AAD enable. + NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. + @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. + @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. + }, + RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. + @"ENABLED" = 0, // desc: The receiver is enabled. + @"DISABLED" = 1, // desc: The receiver is disabled. + }, + AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. + @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. + @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. + }, + // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - DCTRL: bool, // bit offset: 4 desc: Direction control enable. - OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. + @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. + @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. + }, + OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. + @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10038,6 +12992,7 @@ pub const UART2 = extern struct { // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10066,6 +13021,7 @@ pub const UART2 = extern struct { // byte offset: 84 RS-485/EIA-485 direction control delay. pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10097,6 +13053,7 @@ pub const UART3 = extern struct { // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). pub const RBR = mmio(Address + 0x00000000, 32, packed struct { RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. + // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10125,6 +13082,7 @@ pub const UART3 = extern struct { // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). pub const THR = mmio(Address + 0x00000000, 32, packed struct { THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10153,6 +13111,7 @@ pub const UART3 = extern struct { // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLL = mmio(Address + 0x00000000, 32, packed struct { DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10181,6 +13140,7 @@ pub const UART3 = extern struct { // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). pub const DLM = mmio(Address + 0x00000004, 32, packed struct { DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10208,16 +13168,33 @@ pub const UART3 = extern struct { }); // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: bool, // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - THREIE: bool, // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - RXIE: bool, // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. + @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. + @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. + }, + THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. + @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. + @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. + }, + RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. + @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. + @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTEN: bool, // bit offset: 8 desc: Enables the end of auto-baud interrupt. - ABTOINTEN: bool, // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. + @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. + @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. + }, + ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. + @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. + @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10243,13 +13220,24 @@ pub const UART3 = extern struct { }); // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: bool, // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - INTID: u3, // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. + @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. + @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. + }, + INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). + @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). + @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). + @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). + @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt + _, // non-exhaustive + }, + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: bool, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: bool, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10275,13 +13263,29 @@ pub const UART3 = extern struct { }); // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: bool, // bit offset: 0 desc: FIFO Enable. - RXFIFORES: bool, // bit offset: 1 desc: RX FIFO Reset. - TXFIFORES: bool, // bit offset: 2 desc: TX FIFO Reset. - DMAMODE: bool, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. + @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. + @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. + }, + RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. + }, + TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. + @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. + @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. + }, + DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. + // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, - RXTRIGLVL: u2, // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. + @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). + @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). + @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). + @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10309,12 +13313,35 @@ pub const UART3 = extern struct { }); // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: u2, // bit offset: 0 desc: Word Length Select. - SBS: bool, // bit offset: 2 desc: Stop Bit Select - PE: bool, // bit offset: 3 desc: Parity Enable. - PS: u2, // bit offset: 4 desc: Parity Select - BC: bool, // bit offset: 6 desc: Break Control - DLAB: bool, // bit offset: 7 desc: Divisor Latch Access Bit + WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. + @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length + @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length + @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length + @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length + }, + SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select + @"1_STOP_BIT_" = 0, // desc: 1 stop bit. + @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). + }, + PE: enum(u1) { // bit offset: 3 desc: Parity Enable. + @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. + @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. + }, + PS: enum(u2) { // bit offset: 4 desc: Parity Select + @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. + @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. + @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. + @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. + }, + BC: enum(u1) { // bit offset: 6 desc: Break Control + @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. + @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. + }, + DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit + @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. + @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10342,14 +13369,39 @@ pub const UART3 = extern struct { }); // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: bool, // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - OE: bool, // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - PE: bool, // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - FE: bool, // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - BI: bool, // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - THRE: bool, // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - TEMT: bool, // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - RXFE: bool, // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. + @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. + @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. + }, + OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. + @"INACTIVE" = 0, // desc: Overrun error status is inactive. + @"ACTIVE" = 1, // desc: Overrun error status is active. + }, + PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Parity error status is inactive. + @"ACTIVE" = 1, // desc: Parity error status is active. + }, + FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Framing error status is inactive. + @"ACTIVE" = 1, // desc: Framing error status is active. + }, + BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. + @"INACTIVE" = 0, // desc: Break interrupt status is inactive. + @"ACTIVE" = 1, // desc: Break interrupt status is active. + }, + THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. + @"VALIDDATA" = 0, // desc: UnTHR contains valid data. + @"EMPTY" = 1, // desc: UnTHR is empty. + }, + TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. + @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. + @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. + }, + RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. + @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. + @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. + }, + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10378,6 +13430,7 @@ pub const UART3 = extern struct { // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { PAD: u8, // bit offset: 0 desc: A readable, writable byte. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10405,16 +13458,33 @@ pub const UART3 = extern struct { }); // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: bool, // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - MODE: bool, // bit offset: 1 desc: Auto-baud mode select bit. - AUTORESTART: bool, // bit offset: 2 desc: Restart bit. + START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. + @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). + @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. + }, + MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. + @"MODE_0_" = 0, // desc: Mode 0. + @"MODE_1_" = 1, // desc: Mode 1. + }, + AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. + @"NO_RESTART_" = 0, // desc: No restart. + @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) + }, + // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABEOINTCLR: bool, // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: bool, // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + @"NO_IMPACT_" = 0, // desc: No impact. + @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. + }, + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10442,6 +13512,7 @@ pub const UART3 = extern struct { pub const FDR = mmio(Address + 0x00000028, 32, packed struct { DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10469,6 +13540,7 @@ pub const UART3 = extern struct { }); // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. pub const TER = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10476,7 +13548,8 @@ pub const UART3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXEN: bool, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10504,12 +13577,29 @@ pub const UART3 = extern struct { }); // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: bool, // bit offset: 0 desc: NMM enable. - RXDIS: bool, // bit offset: 1 desc: Receiver enable. - AADEN: bool, // bit offset: 2 desc: AAD enable. + NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. + @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. + @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. + }, + RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. + @"ENABLED" = 0, // desc: The receiver is enabled. + @"DISABLED" = 1, // desc: The receiver is disabled. + }, + AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. + @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. + @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. + }, + // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - DCTRL: bool, // bit offset: 4 desc: Direction control enable. - OINV: bool, // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. + @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. + @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. + }, + OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. + @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. + @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10540,6 +13630,7 @@ pub const UART3 = extern struct { // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10568,6 +13659,7 @@ pub const UART3 = extern struct { // byte offset: 84 RS-485/EIA-485 direction control delay. pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10598,13 +13690,15 @@ pub const I2C2 = extern struct { pub const Address: u32 = 0x400a0000; // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved2: u1 = 0, reserved1: u1 = 0, - AA: bool, // bit offset: 2 desc: Assert acknowledge flag. - SI: bool, // bit offset: 3 desc: I2C interrupt flag. - STO: bool, // bit offset: 4 desc: STOP flag. - STA: bool, // bit offset: 5 desc: START flag. - I2EN: bool, // bit offset: 6 desc: I2C interface enable. + AA: u1, // bit offset: 2 desc: Assert acknowledge flag. + SI: u1, // bit offset: 3 desc: I2C interrupt flag. + STO: u1, // bit offset: 4 desc: STOP flag. + STA: u1, // bit offset: 5 desc: START flag. + I2EN: u1, // bit offset: 6 desc: I2C interface enable. + // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10633,10 +13727,12 @@ pub const I2C2 = extern struct { }); // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. pub const STAT = mmio(Address + 0x00000004, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10665,6 +13761,7 @@ pub const I2C2 = extern struct { // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. pub const DAT = mmio(Address + 0x00000008, 32, packed struct { Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10692,8 +13789,9 @@ pub const I2C2 = extern struct { }); // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. + GC: u1, // bit offset: 0 desc: General Call enable bit. Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10722,6 +13820,7 @@ pub const I2C2 = extern struct { // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10742,6 +13841,241 @@ pub const I2C2 = extern struct { // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. + pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved2: u1 = 0, + reserved1: u1 = 0, + AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. + SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. + // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved3: u1 = 0, + STAC: u1, // bit offset: 5 desc: START flag Clear bit. + I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. + // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Monitor mode control register. + pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { + MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. + @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. + @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. + }, + ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] + }, + MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. + @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. + @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { + GC: u1, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { + GC: u1, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { + GC: u1, // bit offset: 0 desc: General Call enable bit. + Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { + Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 I2C Slave address mask register + pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10759,16 +14093,12 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - reserved2: u1 = 0, + // byte offset: 52 I2C Slave address mask register + pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. reserved1: u1 = 0, - AAC: bool, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: bool, // bit offset: 3 desc: I2C interrupt Clear bit. - reserved2: u1 = 0, - STAC: bool, // bit offset: 5 desc: START flag Clear bit. - I2ENC: bool, // bit offset: 6 desc: I2C interface Disable bit. - padding25: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10794,16 +14124,12 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: bool, // bit offset: 0 desc: Monitor mode enable. - ENA_SCL: bool, // bit offset: 1 desc: SCL output enable. - MATCH_ALL: bool, // bit offset: 2 desc: Select interrupt register match. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, + // byte offset: 56 I2C Slave address mask register + pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10829,39 +14155,12 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: bool, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. + // byte offset: 60 I2C Slave address mask register + pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. + reserved1: u1 = 0, + MASK: u7, // bit offset: 1 desc: Mask bits. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10887,58 +14186,24 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - }); }; pub const I2S = extern struct { pub const Address: u32 = 0x400a8000; // byte offset: 0 I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. pub const DAO = mmio(Address + 0x00000000, 32, packed struct { - WORDWIDTH: u2, // bit offset: 0 desc: Selects the number of bytes in data as follows: - MONO: bool, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: bool, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: bool, // bit offset: 4 desc: When 1, asynchronously resets the transmit channel and FIFO. - WS_SEL: bool, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. + WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: + @"8_BIT_DATA" = 0, // desc: 8-bit data + @"16_BIT_DATA" = 1, // desc: 16-bit data + @"32_BIT_DATA" = 3, // desc: 32-bit data + _, // non-exhaustive + }, + MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. + STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + RESET: u1, // bit offset: 4 desc: When 1, asynchronously resets the transmit channel and FIFO. + WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - MUTE: bool, // bit offset: 15 desc: When 1, the transmit channel sends only zeroes. + MUTE: u1, // bit offset: 15 desc: When 1, the transmit channel sends only zeroes. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10958,12 +14223,18 @@ pub const I2S = extern struct { }); // byte offset: 4 I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. pub const DAI = mmio(Address + 0x00000004, 32, packed struct { - WORDWIDTH: u2, // bit offset: 0 desc: Selects the number of bytes in data as follows: - MONO: bool, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: bool, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: bool, // bit offset: 4 desc: When 1, asynchronously reset the transmit channel and FIFO. - WS_SEL: bool, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. + WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: + @"8_BIT_DATA" = 0, // desc: 8-bit data + @"16_BIT_DATA" = 1, // desc: 16-bit data + @"32_BIT_DATA" = 3, // desc: 32-bit data + _, // non-exhaustive + }, + MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. + STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + RESET: u1, // bit offset: 4 desc: When 1, asynchronously reset the transmit channel and FIFO. + WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + // RESERVED: u17, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -10992,20 +14263,23 @@ pub const I2S = extern struct { }); // byte offset: 16 I2S Status Feedback Register. Contains status information about the I2S interface. pub const STATE = mmio(Address + 0x00000010, 32, packed struct { - IRQ: bool, // bit offset: 0 desc: This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. - DMAREQ1: bool, // bit offset: 1 desc: This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. - DMAREQ2: bool, // bit offset: 2 desc: This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. + IRQ: u1, // bit offset: 0 desc: This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. + DMAREQ1: u1, // bit offset: 1 desc: This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. + DMAREQ2: u1, // bit offset: 2 desc: This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. + // RESERVED: u5, // bit offset: 3 desc: Reserved. reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO. + // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - reserved5: u1 = 0, TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO. + // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -11021,8 +14295,9 @@ pub const I2S = extern struct { }); // byte offset: 20 I2S DMA Configuration Register 1. Contains control information for DMA request 1. pub const DMA1 = mmio(Address + 0x00000014, 32, packed struct { - RX_DMA1_ENABLE: bool, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA1_ENABLE: bool, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + RX_DMA1_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. + TX_DMA1_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + // RESERVED: u6, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, @@ -11030,11 +14305,13 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1. + // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved10: u1 = 0, + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1. + // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -11050,8 +14327,9 @@ pub const I2S = extern struct { }); // byte offset: 24 I2S DMA Configuration Register 2. Contains control information for DMA request 2. pub const DMA2 = mmio(Address + 0x00000018, 32, packed struct { - RX_DMA2_ENABLE: bool, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA2_ENABLE: bool, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + RX_DMA2_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. + TX_DMA2_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. + // RESERVED: u6, // bit offset: 2 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, @@ -11059,11 +14337,13 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2. + // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved10: u1 = 0, + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2. + // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -11079,8 +14359,9 @@ pub const I2S = extern struct { }); // byte offset: 28 I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. pub const IRQ = mmio(Address + 0x0000001c, 32, packed struct { - RX_IRQ_ENABLE: bool, // bit offset: 0 desc: When 1, enables I2S receive interrupt. - TX_IRQ_ENABLE: bool, // bit offset: 1 desc: When 1, enables I2S transmit interrupt. + RX_IRQ_ENABLE: u1, // bit offset: 0 desc: When 1, enables I2S receive interrupt. + TX_IRQ_ENABLE: u1, // bit offset: 1 desc: When 1, enables I2S transmit interrupt. + // RESERVED: u6, // bit offset: 2 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, @@ -11088,11 +14369,13 @@ pub const I2S = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request. + // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + reserved10: u1 = 0, + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request. + // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -11110,6 +14393,7 @@ pub const I2S = extern struct { pub const TXRATE = mmio(Address + 0x00000020, 32, packed struct { Y_DIVIDER: u8, // bit offset: 0 desc: I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. X_DIVIDER: u8, // bit offset: 8 desc: I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11131,6 +14415,7 @@ pub const I2S = extern struct { pub const RXRATE = mmio(Address + 0x00000024, 32, packed struct { Y_DIVIDER: u8, // bit offset: 0 desc: I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. X_DIVIDER: u8, // bit offset: 8 desc: I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. + // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11151,6 +14436,7 @@ pub const I2S = extern struct { // byte offset: 40 I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. pub const TXBITRATE = mmio(Address + 0x00000028, 32, packed struct { TX_BITRATE: u6, // bit offset: 0 desc: I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -11181,6 +14467,7 @@ pub const I2S = extern struct { // byte offset: 44 I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. pub const RXBITRATE = mmio(Address + 0x0000002c, 32, packed struct { RX_BITRATE: u6, // bit offset: 0 desc: I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. + // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -11210,9 +14497,14 @@ pub const I2S = extern struct { }); // byte offset: 48 I2S Transmit mode control. pub const TXMODE = mmio(Address + 0x00000030, 32, packed struct { - TXCLKSEL: u2, // bit offset: 0 desc: Clock source selection for the transmit bit clock divider. - TX4PIN: bool, // bit offset: 2 desc: Transmit 4-pin mode selection. When 1, enables 4-pin mode. - TXMCENA: bool, // bit offset: 3 desc: Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. + TXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the transmit bit clock divider. + @"SELECT_THE_TX_FRACTI" = 0, // desc: Select the TX fractional rate divider clock output as the source + @"SELECT_THE_RX_MCLK_S" = 2, // desc: Select the RX_MCLK signal as the TX_MCLK clock source + _, // non-exhaustive + }, + TX4PIN: u1, // bit offset: 2 desc: Transmit 4-pin mode selection. When 1, enables 4-pin mode. + TXMCENA: u1, // bit offset: 3 desc: Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -11244,9 +14536,14 @@ pub const I2S = extern struct { }); // byte offset: 52 I2S Receive mode control. pub const RXMODE = mmio(Address + 0x00000034, 32, packed struct { - RXCLKSEL: u2, // bit offset: 0 desc: Clock source selection for the receive bit clock divider. - RX4PIN: bool, // bit offset: 2 desc: Receive 4-pin mode selection. When 1, enables 4-pin mode. - RXMCENA: bool, // bit offset: 3 desc: Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. + RXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the receive bit clock divider. + @"SELECT_THE_RX_FRACTI" = 0, // desc: Select the RX fractional rate divider clock output as the source + @"SELECT_THE_TX_MCLK_S" = 2, // desc: Select the TX_MCLK signal as the RX_MCLK clock source + _, // non-exhaustive + }, + RX4PIN: u1, // bit offset: 2 desc: Receive 4-pin mode selection. When 1, enables 4-pin mode. + RXMCENA: u1, // bit offset: 3 desc: Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -11289,10 +14586,23 @@ pub const RITIMER = extern struct { }); // byte offset: 8 Control register. pub const CTRL = mmio(Address + 0x00000008, 32, packed struct { - RITINT: bool, // bit offset: 0 desc: Interrupt flag - RITENCLR: bool, // bit offset: 1 desc: Timer enable clear - RITENBR: bool, // bit offset: 2 desc: Timer enable for debug - RITEN: bool, // bit offset: 3 desc: Timer enable. + RITINT: enum(u1) { // bit offset: 0 desc: Interrupt flag + @"THIS_BIT_IS_SET_TO_1" = 1, // desc: This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. + @"THE_COUNTER_VALUE_DO" = 0, // desc: The counter value does not equal the masked compare value. + }, + RITENCLR: enum(u1) { // bit offset: 1 desc: Timer enable clear + @"THE_TIMER_WILL_BE_CL" = 1, // desc: The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. + @"THE_TIMER_WILL_NOT_B" = 0, // desc: The timer will not be cleared to 0. + }, + RITENBR: enum(u1) { // bit offset: 2 desc: Timer enable for debug + @"THE_TIMER_IS_HALTED_" = 1, // desc: The timer is halted when the processor is halted for debugging. + @"DEBUG_HAS_NO_EFFECT_" = 0, // desc: Debug has no effect on the timer operation. + }, + RITEN: enum(u1) { // bit offset: 3 desc: Timer enable. + @"TIMER_ENABLED_THIS_" = 1, // desc: Timer enabled. This can be overruled by a debug halt if enabled in bit 2. + @"TIMER_DISABLED_" = 0, // desc: Timer disabled. + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -11331,132 +14641,196 @@ pub const MCPWM = extern struct { pub const Address: u32 = 0x400b8000; // byte offset: 0 PWM Control read address pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RUN0: bool, // bit offset: 0 desc: Stops/starts timer channel 0. - CENTER0: bool, // bit offset: 1 desc: Edge/center aligned operation for channel 0. - POLA0: bool, // bit offset: 2 desc: Selects polarity of the MCOA0 and MCOB0 pins. - DTE0: bool, // bit offset: 3 desc: Controls the dead-time feature for channel 0. - DISUP0: bool, // bit offset: 4 desc: Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). + RUN0: enum(u1) { // bit offset: 0 desc: Stops/starts timer channel 0. + @"STOP_" = 0, // desc: Stop. + @"RUN_" = 1, // desc: Run. + }, + CENTER0: enum(u1) { // bit offset: 1 desc: Edge/center aligned operation for channel 0. + @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. + @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. + }, + POLA0: enum(u1) { // bit offset: 2 desc: Selects polarity of the MCOA0 and MCOB0 pins. + @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. + @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. + }, + DTE0: enum(u1) { // bit offset: 3 desc: Controls the dead-time feature for channel 0. + @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. + @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. + }, + DISUP0: enum(u1) { // bit offset: 4 desc: Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). + @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. + @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. + }, + // RESERVED: u3, // bit offset: 5 desc: Reserved. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RUN1: bool, // bit offset: 8 desc: Stops/starts timer channel 1. - CENTER1: bool, // bit offset: 9 desc: Edge/center aligned operation for channel 1. - POLA1: bool, // bit offset: 10 desc: Selects polarity of the MCOA1 and MCOB1 pins. - DTE1: bool, // bit offset: 11 desc: Controls the dead-time feature for channel 1. - DISUP1: bool, // bit offset: 12 desc: Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). + RUN1: enum(u1) { // bit offset: 8 desc: Stops/starts timer channel 1. + @"STOP_" = 0, // desc: Stop. + @"RUN_" = 1, // desc: Run. + }, + CENTER1: enum(u1) { // bit offset: 9 desc: Edge/center aligned operation for channel 1. + @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. + @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. + }, + POLA1: enum(u1) { // bit offset: 10 desc: Selects polarity of the MCOA1 and MCOB1 pins. + @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. + @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. + }, + DTE1: enum(u1) { // bit offset: 11 desc: Controls the dead-time feature for channel 1. + @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. + @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. + }, + DISUP1: enum(u1) { // bit offset: 12 desc: Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). + @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. + @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. + }, + // RESERVED: u3, // bit offset: 13 desc: Reserved. + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - RUN2: bool, // bit offset: 16 desc: Stops/starts timer channel 2. - CENTER2: bool, // bit offset: 17 desc: Edge/center aligned operation for channel 2. - POLA2: bool, // bit offset: 18 desc: Selects polarity of the MCOA2 and MCOB2 pins. - DTE2: bool, // bit offset: 19 desc: Controls the dead-time feature for channel 1. - DISUP2: bool, // bit offset: 20 desc: Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). + RUN2: enum(u1) { // bit offset: 16 desc: Stops/starts timer channel 2. + @"STOP_" = 0, // desc: Stop. + @"RUN_" = 1, // desc: Run. + }, + CENTER2: enum(u1) { // bit offset: 17 desc: Edge/center aligned operation for channel 2. + @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. + @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. + }, + POLA2: enum(u1) { // bit offset: 18 desc: Selects polarity of the MCOA2 and MCOB2 pins. + @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. + @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. + }, + DTE2: enum(u1) { // bit offset: 19 desc: Controls the dead-time feature for channel 1. + @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. + @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. + }, + DISUP2: enum(u1) { // bit offset: 20 desc: Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). + @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. + @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. + }, + // RESERVED: u8, // bit offset: 21 desc: Reserved. + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - INVBDC: bool, // bit offset: 29 desc: Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. - ACMODE: bool, // bit offset: 30 desc: 3-phase AC mode select (see Section 24.8.7). - DCMODE: bool, // bit offset: 31 desc: 3-phase DC mode select (see Section 24.8.6). + INVBDC: enum(u1) { // bit offset: 29 desc: Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. + @"OPPOSITE" = 0, // desc: The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). + @"SAME" = 1, // desc: The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6) + }, + ACMODE: enum(u1) { // bit offset: 30 desc: 3-phase AC mode select (see Section 24.8.7). + @"3_PHASE_AC_MODE_OFF" = 0, // desc: 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. + @"3_PHASE_AC_MODE_ON_" = 1, // desc: 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. + }, + DCMODE: enum(u1) { // bit offset: 31 desc: 3-phase DC mode select (see Section 24.8.6). + @"3_PHASE_DC_MODE_OFF" = 0, // desc: 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) + @"3_PHASE_DC_MODE_ON_" = 1, // desc: 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. + }, }); // byte offset: 4 PWM Control set address pub const CON_SET = mmio(Address + 0x00000004, 32, packed struct { - RUN0_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CON register. - CENTER0_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CON register. - POLA0_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CON register. - DTE0_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CON register. - DISUP0_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CON register. + RUN0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CON register. + CENTER0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CON register. + POLA0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CON register. + DTE0_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CON register. + DISUP0_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CON register. + // RESERVED: u3, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CON register. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RUN1_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CON register. - CENTER1_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CON register. - POLA1_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CON register. - DTE1_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CON register. - DISUP1_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CON register. + RUN1_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CON register. + CENTER1_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CON register. + POLA1_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CON register. + DTE1_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CON register. + DISUP1_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CON register. + // RESERVED: u3, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CON register. + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - RUN2_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CON register. - CENTER2_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CON register. - POLA2_SET: bool, // bit offset: 18 desc: Writing a one sets the corresponding bit in the CON register. - DTE2_SET: bool, // bit offset: 19 desc: Writing a one sets the corresponding bit in the CON register. - DISUP2_SET: bool, // bit offset: 20 desc: Writing a one sets the corresponding bit in the CON register. + RUN2_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CON register. + CENTER2_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CON register. + POLA2_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bit in the CON register. + DTE2_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bit in the CON register. + DISUP2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bit in the CON register. + // RESERVED: u8, // bit offset: 21 desc: Writing a one sets the corresponding bit in the CON register. + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - INVBDC_SET: bool, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CON register. - ACMODE_SET: bool, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CON register. - DCMODE_SET: bool, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CON register. + INVBDC_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CON register. + ACMODE_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CON register. + DCMODE_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CON register. }); // byte offset: 8 PWM Control clear address pub const CON_CLR = mmio(Address + 0x00000008, 32, packed struct { - RUN0_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CON register. - CENTER0_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CON register. - POLA0_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CON register. - DTE0_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CON register. - DISUP0_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CON register. + RUN0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CON register. + CENTER0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CON register. + POLA0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CON register. + DTE0_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CON register. + DISUP0_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CON register. + // RESERVED: u3, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CON register. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RUN1_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CON register. - CENTER1_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CON register. - POLA1_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CON register. - DTE1_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CON register. - DISUP1_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CON register. + RUN1_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CON register. + CENTER1_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CON register. + POLA1_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CON register. + DTE1_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CON register. + DISUP1_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CON register. + // RESERVED: u3, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CON register. + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - RUN2_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CON register. - CENTER2_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CON register. - POLA2_CLR: bool, // bit offset: 18 desc: Writing a one clears the corresponding bit in the CON register. - DTE2_CLR: bool, // bit offset: 19 desc: Writing a one clears the corresponding bit in the CON register. - DISUP2_CLR: bool, // bit offset: 20 desc: Writing a one clears the corresponding bit in the CON register. + RUN2_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CON register. + CENTER2_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CON register. + POLA2_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bit in the CON register. + DTE2_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bit in the CON register. + DISUP2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bit in the CON register. + // RESERVED: u8, // bit offset: 21 desc: Writing a one clears the corresponding bit in the CON register. + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - INVBDC_CLR: bool, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CON register. - ACMOD_CLR: bool, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CON register. - DCMODE_CLR: bool, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CON register. + INVBDC_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CON register. + ACMOD_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CON register. + DCMODE_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CON register. }); // byte offset: 12 Capture Control read address pub const CAPCON = mmio(Address + 0x0000000c, 32, packed struct { - CAP0MCI0_RE: bool, // bit offset: 0 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. - CAP0MCI0_FE: bool, // bit offset: 1 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. - CAP0MCI1_RE: bool, // bit offset: 2 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. - CAP0MCI1_FE: bool, // bit offset: 3 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. - CAP0MCI2_RE: bool, // bit offset: 4 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. - CAP0MCI2_FE: bool, // bit offset: 5 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. - CAP1MCI0_RE: bool, // bit offset: 6 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. - CAP1MCI0_FE: bool, // bit offset: 7 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. - CAP1MCI1_RE: bool, // bit offset: 8 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. - CAP1MCI1_FE: bool, // bit offset: 9 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. - CAP1MCI2_RE: bool, // bit offset: 10 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. - CAP1MCI2_FE: bool, // bit offset: 11 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. - CAP2MCI0_RE: bool, // bit offset: 12 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. - CAP2MCI0_FE: bool, // bit offset: 13 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. - CAP2MCI1_RE: bool, // bit offset: 14 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. - CAP2MCI1_FE: bool, // bit offset: 15 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. - CAP2MCI2_RE: bool, // bit offset: 16 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. - CAP2MCI2_FE: bool, // bit offset: 17 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. - RT0: bool, // bit offset: 18 desc: If this bit is 1, TC0 is reset by a channel 0 capture event. - RT1: bool, // bit offset: 19 desc: If this bit is 1, TC1 is reset by a channel 1 capture event. - RT2: bool, // bit offset: 20 desc: If this bit is 1, TC2 is reset by a channel 2 capture event. + CAP0MCI0_RE: u1, // bit offset: 0 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. + CAP0MCI0_FE: u1, // bit offset: 1 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. + CAP0MCI1_RE: u1, // bit offset: 2 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. + CAP0MCI1_FE: u1, // bit offset: 3 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. + CAP0MCI2_RE: u1, // bit offset: 4 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. + CAP0MCI2_FE: u1, // bit offset: 5 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. + CAP1MCI0_RE: u1, // bit offset: 6 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. + CAP1MCI0_FE: u1, // bit offset: 7 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. + CAP1MCI1_RE: u1, // bit offset: 8 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. + CAP1MCI1_FE: u1, // bit offset: 9 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. + CAP1MCI2_RE: u1, // bit offset: 10 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. + CAP1MCI2_FE: u1, // bit offset: 11 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. + CAP2MCI0_RE: u1, // bit offset: 12 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. + CAP2MCI0_FE: u1, // bit offset: 13 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. + CAP2MCI1_RE: u1, // bit offset: 14 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. + CAP2MCI1_FE: u1, // bit offset: 15 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. + CAP2MCI2_RE: u1, // bit offset: 16 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. + CAP2MCI2_FE: u1, // bit offset: 17 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. + RT0: u1, // bit offset: 18 desc: If this bit is 1, TC0 is reset by a channel 0 capture event. + RT1: u1, // bit offset: 19 desc: If this bit is 1, TC1 is reset by a channel 1 capture event. + RT2: u1, // bit offset: 20 desc: If this bit is 1, TC2 is reset by a channel 2 capture event. + // RESERVED: u11, // bit offset: 21 desc: Reserved. padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -11471,27 +14845,28 @@ pub const MCPWM = extern struct { }); // byte offset: 16 Capture Control set address pub const CAPCON_SET = mmio(Address + 0x00000010, 32, packed struct { - CAP0MCI0_RE_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI0_FE_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_RE_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_FE_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_RE_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_FE_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_RE_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_FE_SET: bool, // bit offset: 7 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_RE_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_FE_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_RE_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_FE_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_RE_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_FE_SET: bool, // bit offset: 13 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_RE_SET: bool, // bit offset: 14 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_FE_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_RE_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_FE_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT0_SET: bool, // bit offset: 18 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT1_SET: bool, // bit offset: 19 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT2_SET: bool, // bit offset: 20 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT0_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT1_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bits in the CAPCON register. + RT2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bits in the CAPCON register. + // RESERVED: u11, // bit offset: 21 desc: Reserved. padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -11506,27 +14881,28 @@ pub const MCPWM = extern struct { }); // byte offset: 20 Event Control clear address pub const CAPCON_CLR = mmio(Address + 0x00000014, 32, packed struct { - CAP0MCI0_RE_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI0_FE_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_RE_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_FE_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_RE_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_FE_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_RE_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_FE_CLR: bool, // bit offset: 7 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_RE_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_FE_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_RE_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_FE_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_RE_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_FE_CLR: bool, // bit offset: 13 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_RE_CLR: bool, // bit offset: 14 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_FE_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_RE_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_FE_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT0_CLR: bool, // bit offset: 18 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT1_CLR: bool, // bit offset: 19 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT2_CLR: bool, // bit offset: 20 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_RE_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT0_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT1_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bits in the CAPCON register. + RT2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bits in the CAPCON register. + // RESERVED: u11, // bit offset: 21 desc: Reserved. padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -11580,17 +14956,37 @@ pub const MCPWM = extern struct { DT0: u10, // bit offset: 0 desc: Dead time for channel 0.[1] DT1: u10, // bit offset: 10 desc: Dead time for channel 1.[2] DT2: u10, // bit offset: 20 desc: Dead time for channel 2.[2] + // RESERVED: u2, // bit offset: 30 desc: reserved padding2: u1 = 0, padding1: u1 = 0, }); // byte offset: 64 Communication Pattern register pub const CP = mmio(Address + 0x00000040, 32, packed struct { - CCPA0: bool, // bit offset: 0 desc: Communication pattern output A, channel 0. - CCPB0: bool, // bit offset: 1 desc: Communication pattern output B, channel 0. - CCPA1: bool, // bit offset: 2 desc: Communication pattern output A, channel 1. - CCPB1: bool, // bit offset: 3 desc: Communication pattern output B, channel 1. - CCPA2: bool, // bit offset: 4 desc: Communication pattern output A, channel 2. - CCPB2: bool, // bit offset: 5 desc: Communication pattern output B, channel 2. + CCPA0: enum(u1) { // bit offset: 0 desc: Communication pattern output A, channel 0. + @"MCOA0_PASSIVE_" = 0, // desc: MCOA0 passive. + @"INTERNAL_MCOA0_" = 1, // desc: internal MCOA0. + }, + CCPB0: enum(u1) { // bit offset: 1 desc: Communication pattern output B, channel 0. + @"MCOB0_PASSIVE_" = 0, // desc: MCOB0 passive. + @"MCOB0_TRACKS_INTERNA" = 1, // desc: MCOB0 tracks internal MCOA0. + }, + CCPA1: enum(u1) { // bit offset: 2 desc: Communication pattern output A, channel 1. + @"MCOA1_PASSIVE_" = 0, // desc: MCOA1 passive. + @"MCOA1_TRACKS_INTERNA" = 1, // desc: MCOA1 tracks internal MCOA0. + }, + CCPB1: enum(u1) { // bit offset: 3 desc: Communication pattern output B, channel 1. + @"MCOB1_PASSIVE_" = 0, // desc: MCOB1 passive. + @"MCOB1_TRACKS_INTERNA" = 1, // desc: MCOB1 tracks internal MCOA0. + }, + CCPA2: enum(u1) { // bit offset: 4 desc: Communication pattern output A, channel 2. + @"MCOA2_PASSIVE_" = 0, // desc: MCOA2 passive. + @"MCOA2_TRACKS_INTERNA" = 1, // desc: MCOA2 tracks internal MCOA0. + }, + CCPB2: enum(u1) { // bit offset: 5 desc: Communication pattern output B, channel 2. + @"MCOB2_PASSIVE_" = 0, // desc: MCOB2 passive. + @"MCOB2_TRACKS_INTERNA" = 1, // desc: MCOB2 tracks internal MCOA0. + }, + // RESERVED: u26, // bit offset: 6 desc: Reserved. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -11632,22 +15028,56 @@ pub const MCPWM = extern struct { }); // byte offset: 80 Interrupt Enable read address pub const INTEN = mmio(Address + 0x00000050, 32, packed struct { - ILIM0: bool, // bit offset: 0 desc: Limit interrupt for channel 0. - IMAT0: bool, // bit offset: 1 desc: Match interrupt for channel 0. - ICAP0: bool, // bit offset: 2 desc: Capture interrupt for channel 0. + ILIM0: enum(u1) { // bit offset: 0 desc: Limit interrupt for channel 0. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + IMAT0: enum(u1) { // bit offset: 1 desc: Match interrupt for channel 0. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + ICAP0: enum(u1) { // bit offset: 2 desc: Capture interrupt for channel 0. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1: bool, // bit offset: 4 desc: Limit interrupt for channel 1. - IMAT1: bool, // bit offset: 5 desc: Match interrupt for channel 1. - ICAP1: bool, // bit offset: 6 desc: Capture interrupt for channel 1. + ILIM1: enum(u1) { // bit offset: 4 desc: Limit interrupt for channel 1. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + IMAT1: enum(u1) { // bit offset: 5 desc: Match interrupt for channel 1. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + ICAP1: enum(u1) { // bit offset: 6 desc: Capture interrupt for channel 1. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved2: u1 = 0, - ILIM2: bool, // bit offset: 8 desc: Limit interrupt for channel 2. - IMAT2: bool, // bit offset: 9 desc: Match interrupt for channel 2. - ICAP2: bool, // bit offset: 10 desc: Capture interrupt for channel 2. + ILIM2: enum(u1) { // bit offset: 8 desc: Limit interrupt for channel 2. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + IMAT2: enum(u1) { // bit offset: 9 desc: Match interrupt for channel 2. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + ICAP2: enum(u1) { // bit offset: 10 desc: Capture interrupt for channel 2. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + // RESERVED: u4, // bit offset: 11 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ABORT: bool, // bit offset: 15 desc: Fast abort interrupt. + ABORT: enum(u1) { // bit offset: 15 desc: Fast abort interrupt. + @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. + @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. + }, + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11667,22 +15097,26 @@ pub const MCPWM = extern struct { }); // byte offset: 84 Interrupt Enable set address pub const INTEN_SET = mmio(Address + 0x00000054, 32, packed struct { - ILIM0_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT0_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP0_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT1_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP1_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM1_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT1_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP1_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved3: u1 = 0, reserved2: u1 = 0, - ILIM2_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT2_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP2_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM2_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT2_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP2_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + // RESERVED: u3, // bit offset: 12 desc: Reserved. + reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ABORT_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11702,22 +15136,26 @@ pub const MCPWM = extern struct { }); // byte offset: 88 Interrupt Enable clear address pub const INTEN_CLR = mmio(Address + 0x00000058, 32, packed struct { - ILIM0_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT0_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM1_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT1_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP1_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved2: u1 = 0, - ILIM2_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM2_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT2_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP2_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u4, // bit offset: 11 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ABORT_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ABORT_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11737,24 +15175,79 @@ pub const MCPWM = extern struct { }); // byte offset: 92 Count Control read address pub const CNTCON = mmio(Address + 0x0000005c, 32, packed struct { - TC0MCI0_RE: bool, // bit offset: 0 desc: Counter 0 rising edge mode, channel 0. - TC0MCI0_FE: bool, // bit offset: 1 desc: Counter 0 falling edge mode, channel 0. - TC0MCI1_RE: bool, // bit offset: 2 desc: Counter 0 rising edge mode, channel 1. - TC0MCI1_FE: bool, // bit offset: 3 desc: Counter 0 falling edge mode, channel 1. - TC0MCI2_RE: bool, // bit offset: 4 desc: Counter 0 rising edge mode, channel 2. - TC0MCI2_FE: bool, // bit offset: 5 desc: Counter 0 falling edge mode, channel 2. - TC1MCI0_RE: bool, // bit offset: 6 desc: Counter 1 rising edge mode, channel 0. - TC1MCI0_FE: bool, // bit offset: 7 desc: Counter 1 falling edge mode, channel 0. - TC1MCI1_RE: bool, // bit offset: 8 desc: Counter 1 rising edge mode, channel 1. - TC1MCI1_FE: bool, // bit offset: 9 desc: Counter 1 falling edge mode, channel 1. - TC1MCI2_RE: bool, // bit offset: 10 desc: Counter 1 rising edge mode, channel 2. - TC1MCI2_FE: bool, // bit offset: 11 desc: Counter 1 falling edge mode, channel 2. - TC2MCI0_RE: bool, // bit offset: 12 desc: Counter 2 rising edge mode, channel 0. - TC2MCI0_FE: bool, // bit offset: 13 desc: Counter 2 falling edge mode, channel 0. - TC2MCI1_RE: bool, // bit offset: 14 desc: Counter 2 rising edge mode, channel 1. - TC2MCI1_FE: bool, // bit offset: 15 desc: Counter 2 falling edge mode, channel 1. - TC2MCI2_RE: bool, // bit offset: 16 desc: Counter 2 rising edge mode, channel 2. - TC2MCI2_FE: bool, // bit offset: 17 desc: Counter 2 falling edge mode, channel 2. + TC0MCI0_RE: enum(u1) { // bit offset: 0 desc: Counter 0 rising edge mode, channel 0. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. + @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI0. + }, + TC0MCI0_FE: enum(u1) { // bit offset: 1 desc: Counter 0 falling edge mode, channel 0. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. + @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI0. + }, + TC0MCI1_RE: enum(u1) { // bit offset: 2 desc: Counter 0 rising edge mode, channel 1. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 0. + @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI1. + }, + TC0MCI1_FE: enum(u1) { // bit offset: 3 desc: Counter 0 falling edge mode, channel 1. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 0. + @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI1. + }, + TC0MCI2_RE: enum(u1) { // bit offset: 4 desc: Counter 0 rising edge mode, channel 2. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. + @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI2. + }, + TC0MCI2_FE: enum(u1) { // bit offset: 5 desc: Counter 0 falling edge mode, channel 2. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. + @"FALLLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI2. + }, + TC1MCI0_RE: enum(u1) { // bit offset: 6 desc: Counter 1 rising edge mode, channel 0. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 1. + @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI0. + }, + TC1MCI0_FE: enum(u1) { // bit offset: 7 desc: Counter 1 falling edge mode, channel 0. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. + @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI0. + }, + TC1MCI1_RE: enum(u1) { // bit offset: 8 desc: Counter 1 rising edge mode, channel 1. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 1. + @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI1. + }, + TC1MCI1_FE: enum(u1) { // bit offset: 9 desc: Counter 1 falling edge mode, channel 1. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. + @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI1. + }, + TC1MCI2_RE: enum(u1) { // bit offset: 10 desc: Counter 1 rising edge mode, channel 2. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 1. + @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI2. + }, + TC1MCI2_FE: enum(u1) { // bit offset: 11 desc: Counter 1 falling edge mode, channel 2. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 1. + @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI2. + }, + TC2MCI0_RE: enum(u1) { // bit offset: 12 desc: Counter 2 rising edge mode, channel 0. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 2. + @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI0. + }, + TC2MCI0_FE: enum(u1) { // bit offset: 13 desc: Counter 2 falling edge mode, channel 0. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 2. + @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI0. + }, + TC2MCI1_RE: enum(u1) { // bit offset: 14 desc: Counter 2 rising edge mode, channel 1. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 2. + @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI1. + }, + TC2MCI1_FE: enum(u1) { // bit offset: 15 desc: Counter 2 falling edge mode, channel 1. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 2. + @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI1. + }, + TC2MCI2_RE: enum(u1) { // bit offset: 16 desc: Counter 2 rising edge mode, channel 2. + @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 2. + @"RISIING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI2. + }, + TC2MCI2_FE: enum(u1) { // bit offset: 17 desc: Counter 2 falling edge mode, channel 2. + @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 2. + @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI2. + }, + // RESERVED: u11, // bit offset: 18 desc: Reserved. reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -11766,30 +15259,40 @@ pub const MCPWM = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CNTR0: bool, // bit offset: 29 desc: Channel 0 counter/timer mode. - CNTR1: bool, // bit offset: 30 desc: Channel 1 counter/timer mode. - CNTR2: bool, // bit offset: 31 desc: Channel 2 counter/timer mode. + CNTR0: enum(u1) { // bit offset: 29 desc: Channel 0 counter/timer mode. + @"CHANNEL_0_IS_IN_TIME" = 0, // desc: Channel 0 is in timer mode. + @"CHANNEL_0_IS_IN_COUN" = 1, // desc: Channel 0 is in counter mode. + }, + CNTR1: enum(u1) { // bit offset: 30 desc: Channel 1 counter/timer mode. + @"CHANNEL_1_IS_IN_TIME" = 0, // desc: Channel 1 is in timer mode. + @"CHANNEL_1_IS_IN_COUN" = 1, // desc: Channel 1 is in counter mode. + }, + CNTR2: enum(u1) { // bit offset: 31 desc: Channel 2 counter/timer mode. + @"CHANNEL_2_IS_IN_TIME" = 0, // desc: Channel 2 is in timer mode. + @"CHANNEL_2_IS_IN_COUN" = 1, // desc: Channel 2 is in counter mode. + }, }); // byte offset: 96 Count Control set address pub const CNTCON_SET = mmio(Address + 0x00000060, 32, packed struct { - TC0MCI0_RE_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI0_FE_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_RE_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_FE_SET: bool, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_RE_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_FE_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_RE_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_FE_SET: bool, // bit offset: 7 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_RE_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_FE_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_RE_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_FE_SET: bool, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_RE_SET: bool, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_FE_SET: bool, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_RE_SET: bool, // bit offset: 14 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_FE_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_RE_SET: bool, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_FE_SET: bool, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CNTCON register. + // RESERVED: u11, // bit offset: 18 desc: Reserved. reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -11801,30 +15304,31 @@ pub const MCPWM = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CNTR0_SET: bool, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR1_SET: bool, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR2_SET: bool, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CNTCON register. + CNTR0_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CNTCON register. + CNTR1_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CNTCON register. + CNTR2_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CNTCON register. }); // byte offset: 100 Count Control clear address pub const CNTCON_CLR = mmio(Address + 0x00000064, 32, packed struct { - TC0MCI0_RE_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI0_FE_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_RE_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_FE_CLR: bool, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_RE: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_FE_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_RE_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_FE_CLR: bool, // bit offset: 7 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_RE_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_FE_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_RE_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_FE_CLR: bool, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_RE_CLR: bool, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_FE_CLR: bool, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_RE_CLR: bool, // bit offset: 14 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_FE_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_RE_CLR: bool, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_FE_CLR: bool, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_RE: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CNTCON register. + // RESERVED: u11, // bit offset: 18 desc: Reserved. reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -11836,28 +15340,62 @@ pub const MCPWM = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CNTR0_CLR: bool, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR1_CLR: bool, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR2_CLR: bool, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CNTCON register. + CNTR0_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CNTCON register. + CNTR1_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CNTCON register. + CNTR2_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CNTCON register. }); // byte offset: 104 Interrupt flags read address pub const INTF = mmio(Address + 0x00000068, 32, packed struct { - ILIM0_F: bool, // bit offset: 0 desc: Limit interrupt flag for channel 0. - IMAT0_F: bool, // bit offset: 1 desc: Match interrupt flag for channel 0. - ICAP0_F: bool, // bit offset: 2 desc: Capture interrupt flag for channel 0. + ILIM0_F: enum(u1) { // bit offset: 0 desc: Limit interrupt flag for channel 0. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + IMAT0_F: enum(u1) { // bit offset: 1 desc: Match interrupt flag for channel 0. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + ICAP0_F: enum(u1) { // bit offset: 2 desc: Capture interrupt flag for channel 0. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1_F: bool, // bit offset: 4 desc: Limit interrupt flag for channel 1. - IMAT1_F: bool, // bit offset: 5 desc: Match interrupt flag for channel 1. - ICAP1_F: bool, // bit offset: 6 desc: Capture interrupt flag for channel 1. + ILIM1_F: enum(u1) { // bit offset: 4 desc: Limit interrupt flag for channel 1. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + IMAT1_F: enum(u1) { // bit offset: 5 desc: Match interrupt flag for channel 1. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + ICAP1_F: enum(u1) { // bit offset: 6 desc: Capture interrupt flag for channel 1. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved2: u1 = 0, - ILIM2_F: bool, // bit offset: 8 desc: Limit interrupt flag for channel 2. - IMAT2_F: bool, // bit offset: 9 desc: Match interrupt flag for channel 2. - ICAP2_F: bool, // bit offset: 10 desc: Capture interrupt flag for channel 2. + ILIM2_F: enum(u1) { // bit offset: 8 desc: Limit interrupt flag for channel 2. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + IMAT2_F: enum(u1) { // bit offset: 9 desc: Match interrupt flag for channel 2. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + ICAP2_F: enum(u1) { // bit offset: 10 desc: Capture interrupt flag for channel 2. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + // RESERVED: u4, // bit offset: 11 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ABORT_F: bool, // bit offset: 15 desc: Fast abort interrupt flag. + ABORT_F: enum(u1) { // bit offset: 15 desc: Fast abort interrupt flag. + @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. + @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. + }, + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11877,22 +15415,26 @@ pub const MCPWM = extern struct { }); // byte offset: 108 Interrupt flags set address pub const INTF_SET = mmio(Address + 0x0000006c, 32, packed struct { - ILIM0_F_SET: bool, // bit offset: 0 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT0_F_SET: bool, // bit offset: 1 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP0_F_SET: bool, // bit offset: 2 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ILIM0_F_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT0_F_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP0_F_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1_F_SET: bool, // bit offset: 4 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT1_F_SET: bool, // bit offset: 5 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP1_F_SET: bool, // bit offset: 6 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ILIM1_F_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT1_F_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP1_F_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved2: u1 = 0, - ILIM2_F_SET: bool, // bit offset: 8 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT2_F_SET: bool, // bit offset: 9 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP2_F_SET: bool, // bit offset: 10 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ILIM2_F_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + IMAT2_F_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ICAP2_F_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + // RESERVED: u4, // bit offset: 11 desc: Reserved. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ABORT_F_SET: bool, // bit offset: 15 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + ABORT_F_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11912,22 +15454,26 @@ pub const MCPWM = extern struct { }); // byte offset: 112 Interrupt flags clear address pub const INTF_CLR = mmio(Address + 0x00000070, 32, packed struct { - ILIM0_F_CLR: bool, // bit offset: 0 desc: Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. - IMAT0_F_CLR: bool, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_F_CLR: bool, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM0_F_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. + IMAT0_F_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP0_F_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u1, // bit offset: 3 desc: Reserved. reserved1: u1 = 0, - ILIM1_F_CLR: bool, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_F_CLR: bool, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_F_CLR: bool, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM1_F_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT1_F_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP1_F_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u1, // bit offset: 7 desc: Reserved. reserved2: u1 = 0, - ILIM2_F_CLR: bool, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_F_CLR: bool, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_F_CLR: bool, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ILIM2_F_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + IMAT2_F_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ICAP2_F_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u4, // bit offset: 11 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ABORT_F_CLR: bool, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + ABORT_F_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. + // RESERVED: u16, // bit offset: 16 desc: Reserved. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11947,9 +15493,10 @@ pub const MCPWM = extern struct { }); // byte offset: 116 Capture clear address pub const CAP_CLR = mmio(Address + 0x00000074, 32, packed struct { - CAP_CLR0: bool, // bit offset: 0 desc: Writing a 1 to this bit clears the CAP0 register. - CAP_CLR1: bool, // bit offset: 1 desc: Writing a 1 to this bit clears the CAP1 register. - CAP_CLR2: bool, // bit offset: 2 desc: Writing a 1 to this bit clears the CAP2 register. + CAP_CLR0: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the CAP0 register. + CAP_CLR1: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the CAP1 register. + CAP_CLR2: u1, // bit offset: 2 desc: Writing a 1 to this bit clears the CAP2 register. + // RESERVED: u29, // bit offset: 3 desc: Reserved padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -11985,10 +15532,11 @@ pub const QEI = extern struct { pub const Address: u32 = 0x400bc000; // byte offset: 0 Control register pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RESP: bool, // bit offset: 0 desc: Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. - RESPI: bool, // bit offset: 1 desc: Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. - RESV: bool, // bit offset: 2 desc: Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. - RESI: bool, // bit offset: 3 desc: Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. + RESP: u1, // bit offset: 0 desc: Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. + RESPI: u1, // bit offset: 1 desc: Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. + RESV: u1, // bit offset: 2 desc: Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. + RESI: u1, // bit offset: 3 desc: Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12020,7 +15568,8 @@ pub const QEI = extern struct { }); // byte offset: 4 Status register pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - DIR: bool, // bit offset: 0 desc: Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. + DIR: u1, // bit offset: 0 desc: Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. + // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -12055,11 +15604,12 @@ pub const QEI = extern struct { }); // byte offset: 8 Configuration register pub const CONF = mmio(Address + 0x00000008, 32, packed struct { - DIRINV: bool, // bit offset: 0 desc: Direction invert. When 1, complements the DIR bit. - SIGMODE: bool, // bit offset: 1 desc: Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. - CAPMODE: bool, // bit offset: 2 desc: Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. - INVINX: bool, // bit offset: 3 desc: Invert Index. When 1, inverts the sense of the index input. - CRESPI: bool, // bit offset: 4 desc: Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). + DIRINV: u1, // bit offset: 0 desc: Direction invert. When 1, complements the DIR bit. + SIGMODE: u1, // bit offset: 1 desc: Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. + CAPMODE: u1, // bit offset: 2 desc: Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. + INVINX: u1, // bit offset: 3 desc: Invert Index. When 1, inverts the sense of the index input. + CRESPI: u1, // bit offset: 4 desc: Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). + // RESERVED: u11, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -12072,6 +15622,7 @@ pub const QEI = extern struct { reserved2: u1 = 0, reserved1: u1 = 0, INXGATE: u4, // bit offset: 16 desc: Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. + // RESERVED: u12, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -12139,22 +15690,23 @@ pub const QEI = extern struct { }); // byte offset: 4056 Interrupt enable clear register pub const IEC = mmio(Address + 0x00000fd8, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: Writing a 1 disables the INX_Int interrupt in the QEIIE register. - TIM_INT: bool, // bit offset: 1 desc: Writing a 1 disables the TIN_Int interrupt in the QEIIE register. - VELC_INT: bool, // bit offset: 2 desc: Writing a 1 disables the VELC_Int interrupt in the QEIIE register. - DIR_INT: bool, // bit offset: 3 desc: Writing a 1 disables the DIR_Int interrupt in the QEIIE register. - ERR_INT: bool, // bit offset: 4 desc: Writing a 1 disables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: bool, // bit offset: 6 desc: Writing a 1 disables the POS0_Int interrupt in the QEIIE register. - POS1_INT: bool, // bit offset: 7 desc: Writing a 1 disables the POS1_Int interrupt in the QEIIE register. - POS2_INT: bool, // bit offset: 8 desc: Writing a 1 disables the POS2_Int interrupt in the QEIIE register. - REV0_INT: bool, // bit offset: 9 desc: Writing a 1 disables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: bool, // bit offset: 13 desc: Writing a 1 disables the REV1_Int interrupt in the QEIIE register. - REV2_INT: bool, // bit offset: 14 desc: Writing a 1 disables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. + INX_INT: u1, // bit offset: 0 desc: Writing a 1 disables the INX_Int interrupt in the QEIIE register. + TIM_INT: u1, // bit offset: 1 desc: Writing a 1 disables the TIN_Int interrupt in the QEIIE register. + VELC_INT: u1, // bit offset: 2 desc: Writing a 1 disables the VELC_Int interrupt in the QEIIE register. + DIR_INT: u1, // bit offset: 3 desc: Writing a 1 disables the DIR_Int interrupt in the QEIIE register. + ERR_INT: u1, // bit offset: 4 desc: Writing a 1 disables the ERR_Int interrupt in the QEIIE register. + ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. + POS0_INT: u1, // bit offset: 6 desc: Writing a 1 disables the POS0_Int interrupt in the QEIIE register. + POS1_INT: u1, // bit offset: 7 desc: Writing a 1 disables the POS1_Int interrupt in the QEIIE register. + POS2_INT: u1, // bit offset: 8 desc: Writing a 1 disables the POS2_Int interrupt in the QEIIE register. + REV0_INT: u1, // bit offset: 9 desc: Writing a 1 disables the REV0_Int interrupt in the QEIIE register. + POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. + REV1_INT: u1, // bit offset: 13 desc: Writing a 1 disables the REV1_Int interrupt in the QEIIE register. + REV2_INT: u1, // bit offset: 14 desc: Writing a 1 disables the REV2_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12174,22 +15726,23 @@ pub const QEI = extern struct { }); // byte offset: 4060 Interrupt enable set register pub const IES = mmio(Address + 0x00000fdc, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: Writing a 1 enables the INX_Int interrupt in the QEIIE register. - TIM_INT: bool, // bit offset: 1 desc: Writing a 1 enables the TIN_Int interrupt in the QEIIE register. - VELC_INT: bool, // bit offset: 2 desc: Writing a 1 enables the VELC_Int interrupt in the QEIIE register. - DIR_INT: bool, // bit offset: 3 desc: Writing a 1 enables the DIR_Int interrupt in the QEIIE register. - ERR_INT: bool, // bit offset: 4 desc: Writing a 1 enables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: bool, // bit offset: 6 desc: Writing a 1 enables the POS0_Int interrupt in the QEIIE register. - POS1_INT: bool, // bit offset: 7 desc: Writing a 1 enables the POS1_Int interrupt in the QEIIE register. - POS2_INT: bool, // bit offset: 8 desc: Writing a 1 enables the POS2_Int interrupt in the QEIIE register. - REV0_INT: bool, // bit offset: 9 desc: Writing a 1 enables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: bool, // bit offset: 13 desc: Writing a 1 enables the REV1_Int interrupt in the QEIIE register. - REV2_INT: bool, // bit offset: 14 desc: Writing a 1 enables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. + INX_INT: u1, // bit offset: 0 desc: Writing a 1 enables the INX_Int interrupt in the QEIIE register. + TIM_INT: u1, // bit offset: 1 desc: Writing a 1 enables the TIN_Int interrupt in the QEIIE register. + VELC_INT: u1, // bit offset: 2 desc: Writing a 1 enables the VELC_Int interrupt in the QEIIE register. + DIR_INT: u1, // bit offset: 3 desc: Writing a 1 enables the DIR_Int interrupt in the QEIIE register. + ERR_INT: u1, // bit offset: 4 desc: Writing a 1 enables the ERR_Int interrupt in the QEIIE register. + ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. + POS0_INT: u1, // bit offset: 6 desc: Writing a 1 enables the POS0_Int interrupt in the QEIIE register. + POS1_INT: u1, // bit offset: 7 desc: Writing a 1 enables the POS1_Int interrupt in the QEIIE register. + POS2_INT: u1, // bit offset: 8 desc: Writing a 1 enables the POS2_Int interrupt in the QEIIE register. + REV0_INT: u1, // bit offset: 9 desc: Writing a 1 enables the REV0_Int interrupt in the QEIIE register. + POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. + REV1_INT: u1, // bit offset: 13 desc: Writing a 1 enables the REV1_Int interrupt in the QEIIE register. + REV2_INT: u1, // bit offset: 14 desc: Writing a 1 enables the REV2_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12209,22 +15762,23 @@ pub const QEI = extern struct { }); // byte offset: 4064 Interrupt status register pub const INTSTAT = mmio(Address + 0x00000fe0, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: Indicates that an index pulse was detected. - TIM_INT: bool, // bit offset: 1 desc: Indicates that a velocity timer overflow occurred - VELC_INT: bool, // bit offset: 2 desc: Indicates that captured velocity is less than compare velocity. - DIR_INT: bool, // bit offset: 3 desc: Indicates that a change of direction was detected. - ERR_INT: bool, // bit offset: 4 desc: Indicates that an encoder phase error was detected. - ENCLK_INT: bool, // bit offset: 5 desc: Indicates that and encoder clock pulse was detected. - POS0_INT: bool, // bit offset: 6 desc: Indicates that the position 0 compare value is equal to the current position. - POS1_INT: bool, // bit offset: 7 desc: Indicates that the position 1compare value is equal to the current position. - POS2_INT: bool, // bit offset: 8 desc: Indicates that the position 2 compare value is equal to the current position. - REV0_INT: bool, // bit offset: 9 desc: Indicates that the index compare 0 value is equal to the current index count. - POS0REV_INT: bool, // bit offset: 10 desc: Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. - POS1REV_INT: bool, // bit offset: 11 desc: Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. - POS2REV_INT: bool, // bit offset: 12 desc: Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. - REV1_INT: bool, // bit offset: 13 desc: Indicates that the index compare 1value is equal to the current index count. - REV2_INT: bool, // bit offset: 14 desc: Indicates that the index compare 2 value is equal to the current index count. - MAXPOS_INT: bool, // bit offset: 15 desc: Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. + INX_INT: u1, // bit offset: 0 desc: Indicates that an index pulse was detected. + TIM_INT: u1, // bit offset: 1 desc: Indicates that a velocity timer overflow occurred + VELC_INT: u1, // bit offset: 2 desc: Indicates that captured velocity is less than compare velocity. + DIR_INT: u1, // bit offset: 3 desc: Indicates that a change of direction was detected. + ERR_INT: u1, // bit offset: 4 desc: Indicates that an encoder phase error was detected. + ENCLK_INT: u1, // bit offset: 5 desc: Indicates that and encoder clock pulse was detected. + POS0_INT: u1, // bit offset: 6 desc: Indicates that the position 0 compare value is equal to the current position. + POS1_INT: u1, // bit offset: 7 desc: Indicates that the position 1compare value is equal to the current position. + POS2_INT: u1, // bit offset: 8 desc: Indicates that the position 2 compare value is equal to the current position. + REV0_INT: u1, // bit offset: 9 desc: Indicates that the index compare 0 value is equal to the current index count. + POS0REV_INT: u1, // bit offset: 10 desc: Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. + POS1REV_INT: u1, // bit offset: 11 desc: Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. + POS2REV_INT: u1, // bit offset: 12 desc: Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. + REV1_INT: u1, // bit offset: 13 desc: Indicates that the index compare 1value is equal to the current index count. + REV2_INT: u1, // bit offset: 14 desc: Indicates that the index compare 2 value is equal to the current index count. + MAXPOS_INT: u1, // bit offset: 15 desc: Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12244,22 +15798,23 @@ pub const QEI = extern struct { }); // byte offset: 4068 Interrupt enable register pub const IE = mmio(Address + 0x00000fe4, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: When 1, the INX_Int interrupt is enabled. - TIM_INT: bool, // bit offset: 1 desc: When 1, the TIN_Int interrupt is enabled. - VELC_INT: bool, // bit offset: 2 desc: When 1, the VELC_Int interrupt is enabled. - DIR_INT: bool, // bit offset: 3 desc: When 1, the DIR_Int interrupt is enabled. - ERR_INT: bool, // bit offset: 4 desc: When 1, the ERR_Int interrupt is enabled. - ENCLK_INT: bool, // bit offset: 5 desc: When 1, the ENCLK_Int interrupt is enabled. - POS0_INT: bool, // bit offset: 6 desc: When 1, the POS0_Int interrupt is enabled. - POS1_INT: bool, // bit offset: 7 desc: When 1, the POS1_Int interrupt is enabled. - POS2_INT: bool, // bit offset: 8 desc: When 1, the POS2_Int interrupt is enabled. - REV0_INT: bool, // bit offset: 9 desc: When 1, the REV0_Int interrupt is enabled. - POS0REV_INT: bool, // bit offset: 10 desc: When 1, the POS0REV_Int interrupt is enabled. - POS1REV_INT: bool, // bit offset: 11 desc: When 1, the POS1REV_Int interrupt is enabled. - POS2REV_INT: bool, // bit offset: 12 desc: When 1, the POS2REV_Int interrupt is enabled. - REV1_INT: bool, // bit offset: 13 desc: When 1, the REV1_Int interrupt is enabled. - REV2_INT: bool, // bit offset: 14 desc: When 1, the REV2_Int interrupt is enabled. - MAXPOS_INT: bool, // bit offset: 15 desc: When 1, the MAXPOS_Int interrupt is enabled. + INX_INT: u1, // bit offset: 0 desc: When 1, the INX_Int interrupt is enabled. + TIM_INT: u1, // bit offset: 1 desc: When 1, the TIN_Int interrupt is enabled. + VELC_INT: u1, // bit offset: 2 desc: When 1, the VELC_Int interrupt is enabled. + DIR_INT: u1, // bit offset: 3 desc: When 1, the DIR_Int interrupt is enabled. + ERR_INT: u1, // bit offset: 4 desc: When 1, the ERR_Int interrupt is enabled. + ENCLK_INT: u1, // bit offset: 5 desc: When 1, the ENCLK_Int interrupt is enabled. + POS0_INT: u1, // bit offset: 6 desc: When 1, the POS0_Int interrupt is enabled. + POS1_INT: u1, // bit offset: 7 desc: When 1, the POS1_Int interrupt is enabled. + POS2_INT: u1, // bit offset: 8 desc: When 1, the POS2_Int interrupt is enabled. + REV0_INT: u1, // bit offset: 9 desc: When 1, the REV0_Int interrupt is enabled. + POS0REV_INT: u1, // bit offset: 10 desc: When 1, the POS0REV_Int interrupt is enabled. + POS1REV_INT: u1, // bit offset: 11 desc: When 1, the POS1REV_Int interrupt is enabled. + POS2REV_INT: u1, // bit offset: 12 desc: When 1, the POS2REV_Int interrupt is enabled. + REV1_INT: u1, // bit offset: 13 desc: When 1, the REV1_Int interrupt is enabled. + REV2_INT: u1, // bit offset: 14 desc: When 1, the REV2_Int interrupt is enabled. + MAXPOS_INT: u1, // bit offset: 15 desc: When 1, the MAXPOS_Int interrupt is enabled. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12279,22 +15834,23 @@ pub const QEI = extern struct { }); // byte offset: 4072 Interrupt status clear register pub const CLR = mmio(Address + 0x00000fe8, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: Writing a 1 clears the INX_Int bit in QEIINTSTAT. - TIM_INT: bool, // bit offset: 1 desc: Writing a 1 clears the TIN_Int bit in QEIINTSTAT. - VELC_INT: bool, // bit offset: 2 desc: Writing a 1 clears the VELC_Int bit in QEIINTSTAT. - DIR_INT: bool, // bit offset: 3 desc: Writing a 1 clears the DIR_Int bit in QEIINTSTAT. - ERR_INT: bool, // bit offset: 4 desc: Writing a 1 clears the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: bool, // bit offset: 6 desc: Writing a 1 clears the POS0_Int bit in QEIINTSTAT. - POS1_INT: bool, // bit offset: 7 desc: Writing a 1 clears the POS1_Int bit in QEIINTSTAT. - POS2_INT: bool, // bit offset: 8 desc: Writing a 1 clears the POS2_Int bit in QEIINTSTAT. - REV0_INT: bool, // bit offset: 9 desc: Writing a 1 clears the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: bool, // bit offset: 13 desc: Writing a 1 clears the REV1_Int bit in QEIINTSTAT. - REV2_INT: bool, // bit offset: 14 desc: Writing a 1 clears the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. + INX_INT: u1, // bit offset: 0 desc: Writing a 1 clears the INX_Int bit in QEIINTSTAT. + TIM_INT: u1, // bit offset: 1 desc: Writing a 1 clears the TIN_Int bit in QEIINTSTAT. + VELC_INT: u1, // bit offset: 2 desc: Writing a 1 clears the VELC_Int bit in QEIINTSTAT. + DIR_INT: u1, // bit offset: 3 desc: Writing a 1 clears the DIR_Int bit in QEIINTSTAT. + ERR_INT: u1, // bit offset: 4 desc: Writing a 1 clears the ERR_Int bit in QEIINTSTAT. + ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. + POS0_INT: u1, // bit offset: 6 desc: Writing a 1 clears the POS0_Int bit in QEIINTSTAT. + POS1_INT: u1, // bit offset: 7 desc: Writing a 1 clears the POS1_Int bit in QEIINTSTAT. + POS2_INT: u1, // bit offset: 8 desc: Writing a 1 clears the POS2_Int bit in QEIINTSTAT. + REV0_INT: u1, // bit offset: 9 desc: Writing a 1 clears the REV0_Int bit in QEIINTSTAT. + POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. + REV1_INT: u1, // bit offset: 13 desc: Writing a 1 clears the REV1_Int bit in QEIINTSTAT. + REV2_INT: u1, // bit offset: 14 desc: Writing a 1 clears the REV2_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12314,22 +15870,23 @@ pub const QEI = extern struct { }); // byte offset: 4076 Interrupt status set register pub const SET = mmio(Address + 0x00000fec, 32, packed struct { - INX_INT: bool, // bit offset: 0 desc: Writing a 1 sets the INX_Int bit in QEIINTSTAT. - TIM_INT: bool, // bit offset: 1 desc: Writing a 1 sets the TIN_Int bit in QEIINTSTAT. - VELC_INT: bool, // bit offset: 2 desc: Writing a 1 sets the VELC_Int bit in QEIINTSTAT. - DIR_INT: bool, // bit offset: 3 desc: Writing a 1 sets the DIR_Int bit in QEIINTSTAT. - ERR_INT: bool, // bit offset: 4 desc: Writing a 1 sets the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: bool, // bit offset: 5 desc: Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: bool, // bit offset: 6 desc: Writing a 1 sets the POS0_Int bit in QEIINTSTAT. - POS1_INT: bool, // bit offset: 7 desc: Writing a 1 sets the POS1_Int bit in QEIINTSTAT. - POS2_INT: bool, // bit offset: 8 desc: Writing a 1 sets the POS2_Int bit in QEIINTSTAT. - REV0_INT: bool, // bit offset: 9 desc: Writing a 1 sets the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: bool, // bit offset: 10 desc: Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: bool, // bit offset: 11 desc: Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: bool, // bit offset: 12 desc: Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: bool, // bit offset: 13 desc: Writing a 1 sets the REV1_Int bit in QEIINTSTAT. - REV2_INT: bool, // bit offset: 14 desc: Writing a 1 sets the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: bool, // bit offset: 15 desc: Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. + INX_INT: u1, // bit offset: 0 desc: Writing a 1 sets the INX_Int bit in QEIINTSTAT. + TIM_INT: u1, // bit offset: 1 desc: Writing a 1 sets the TIN_Int bit in QEIINTSTAT. + VELC_INT: u1, // bit offset: 2 desc: Writing a 1 sets the VELC_Int bit in QEIINTSTAT. + DIR_INT: u1, // bit offset: 3 desc: Writing a 1 sets the DIR_Int bit in QEIINTSTAT. + ERR_INT: u1, // bit offset: 4 desc: Writing a 1 sets the ERR_Int bit in QEIINTSTAT. + ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. + POS0_INT: u1, // bit offset: 6 desc: Writing a 1 sets the POS0_Int bit in QEIINTSTAT. + POS1_INT: u1, // bit offset: 7 desc: Writing a 1 sets the POS1_Int bit in QEIINTSTAT. + POS2_INT: u1, // bit offset: 8 desc: Writing a 1 sets the POS2_Int bit in QEIINTSTAT. + REV0_INT: u1, // bit offset: 9 desc: Writing a 1 sets the REV0_Int bit in QEIINTSTAT. + POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. + REV1_INT: u1, // bit offset: 13 desc: Writing a 1 sets the REV1_Int bit in QEIINTSTAT. + REV2_INT: u1, // bit offset: 14 desc: Writing a 1 sets the REV2_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12352,6 +15909,7 @@ pub const SYSCON = extern struct { pub const Address: u32 = 0x400fc000; // byte offset: 0 Flash Accelerator Configuration Register. Controls flash access timing. pub const FLASHCFG = mmio(Address + 0x00000000, 32, packed struct { + // RESERVED: u12, // bit offset: 0 desc: Reserved, user software should not change these bits from the reset value. reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, @@ -12364,7 +15922,16 @@ pub const SYSCON = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FLASHTIM: u4, // bit offset: 12 desc: Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. + FLASHTIM: enum(u4) { // bit offset: 12 desc: Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. + @"1CLK" = 0, // desc: Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. + @"2CLK" = 1, // desc: Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. + @"3CLK" = 2, // desc: Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. + @"4CLK" = 3, // desc: Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. + @"5CLK" = 4, // desc: Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. + @"6CLK" = 5, // desc: Flash accesses use 6 CPU clocks. This safe setting will work under any conditions. + _, // non-exhaustive + }, + // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12384,8 +15951,9 @@ pub const SYSCON = extern struct { }); // byte offset: 128 PLL0 Control Register pub const PLL0CON = mmio(Address + 0x00000080, 32, packed struct { - PLLE0: bool, // bit offset: 0 desc: PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register. - PLLC0: bool, // bit offset: 1 desc: PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register. + PLLE0: u1, // bit offset: 0 desc: PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register. + PLLC0: u1, // bit offset: 1 desc: PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register. + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -12420,8 +15988,10 @@ pub const SYSCON = extern struct { // byte offset: 132 PLL0 Configuration Register pub const PLL0CFG = mmio(Address + 0x00000084, 32, packed struct { MSEL0: u15, // bit offset: 0 desc: PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware. + // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved1: u1 = 0, NSEL0: u8, // bit offset: 16 desc: PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32. + // RESERVED: u8, // bit offset: 24 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -12434,11 +16004,13 @@ pub const SYSCON = extern struct { // byte offset: 136 PLL0 Status Register pub const PLL0STAT = mmio(Address + 0x00000088, 32, packed struct { MSEL0: u15, // bit offset: 0 desc: Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier. + // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved1: u1 = 0, NSEL0: u8, // bit offset: 16 desc: Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider. - PLLE0_STAT: bool, // bit offset: 24 desc: Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. - PLLC0_STAT: bool, // bit offset: 25 desc: Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. - PLOCK0: bool, // bit offset: 26 desc: Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. + PLLE0_STAT: u1, // bit offset: 24 desc: Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. + PLLC0_STAT: u1, // bit offset: 25 desc: Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. + PLOCK0: u1, // bit offset: 26 desc: Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. + // RESERVED: u5, // bit offset: 27 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, @@ -12448,6 +16020,7 @@ pub const SYSCON = extern struct { // byte offset: 140 PLL0 Feed Register pub const PLL0FEED = mmio(Address + 0x0000008c, 32, packed struct { PLL0FEED: u8, // bit offset: 0 desc: The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12475,8 +16048,9 @@ pub const SYSCON = extern struct { }); // byte offset: 160 PLL1 Control Register pub const PLL1CON = mmio(Address + 0x000000a0, 32, packed struct { - PLLE1: bool, // bit offset: 0 desc: PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. - PLLC1: bool, // bit offset: 1 desc: PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register. + PLLE1: u1, // bit offset: 0 desc: PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. + PLLC1: u1, // bit offset: 1 desc: PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register. + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -12512,6 +16086,7 @@ pub const SYSCON = extern struct { pub const PLL1CFG = mmio(Address + 0x000000a4, 32, packed struct { MSEL1: u5, // bit offset: 0 desc: PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. PSEL1: u2, // bit offset: 5 desc: PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. + // RESERVED: u25, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -12542,10 +16117,12 @@ pub const SYSCON = extern struct { pub const PLL1STAT = mmio(Address + 0x000000a8, 32, packed struct { MSEL1: u5, // bit offset: 0 desc: Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1. PSEL1: u2, // bit offset: 5 desc: Read-back for the PLL1 Divider value. This is the value currently used by PLL1. + // RESERVED: u1, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved1: u1 = 0, - PLLE1_STAT: bool, // bit offset: 8 desc: Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. - PLLC1_STAT: bool, // bit offset: 9 desc: Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. - PLOCK1: bool, // bit offset: 10 desc: Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. + PLLE1_STAT: u1, // bit offset: 8 desc: Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. + PLLC1_STAT: u1, // bit offset: 9 desc: Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. + PLOCK1: u1, // bit offset: 10 desc: Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. + // RESERVED: u21, // bit offset: 11 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -12571,6 +16148,7 @@ pub const SYSCON = extern struct { // byte offset: 172 PLL1 Feed Register pub const PLL1FEED = mmio(Address + 0x000000ac, 32, packed struct { PLL1FEED: u8, // bit offset: 0 desc: The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12598,18 +16176,20 @@ pub const SYSCON = extern struct { }); // byte offset: 192 Power Control Register pub const PCON = mmio(Address + 0x000000c0, 32, packed struct { - PM0: bool, // bit offset: 0 desc: Power mode control bit 0. This bit controls entry to the Power-down mode. - PM1: bool, // bit offset: 1 desc: Power mode control bit 1. This bit controls entry to the Deep Power-down mode. - BODRPM: bool, // bit offset: 2 desc: Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. - BOGD: bool, // bit offset: 3 desc: Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. - BORD: bool, // bit offset: 4 desc: Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. + PM0: u1, // bit offset: 0 desc: Power mode control bit 0. This bit controls entry to the Power-down mode. + PM1: u1, // bit offset: 1 desc: Power mode control bit 1. This bit controls entry to the Deep Power-down mode. + BODRPM: u1, // bit offset: 2 desc: Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. + BOGD: u1, // bit offset: 3 desc: Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. + // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. + BORD: u1, // bit offset: 4 desc: Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMFLAG: bool, // bit offset: 8 desc: Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. - DSFLAG: bool, // bit offset: 9 desc: Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. - PDFLAG: bool, // bit offset: 10 desc: Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. - DPDFLAG: bool, // bit offset: 11 desc: Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. + SMFLAG: u1, // bit offset: 8 desc: Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. + DSFLAG: u1, // bit offset: 9 desc: Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. + PDFLAG: u1, // bit offset: 10 desc: Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. + DPDFLAG: u1, // bit offset: 11 desc: Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. + // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12633,42 +16213,48 @@ pub const SYSCON = extern struct { }); // byte offset: 196 Power Control for Peripherals Register pub const PCONP = mmio(Address + 0x000000c4, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. reserved1: u1 = 0, - PCTIM0: bool, // bit offset: 1 desc: Timer/Counter 0 power/clock control bit. - PCTIM1: bool, // bit offset: 2 desc: Timer/Counter 1 power/clock control bit. - PCUART0: bool, // bit offset: 3 desc: UART0 power/clock control bit. - PCUART1: bool, // bit offset: 4 desc: UART1 power/clock control bit. + PCTIM0: u1, // bit offset: 1 desc: Timer/Counter 0 power/clock control bit. + PCTIM1: u1, // bit offset: 2 desc: Timer/Counter 1 power/clock control bit. + PCUART0: u1, // bit offset: 3 desc: UART0 power/clock control bit. + PCUART1: u1, // bit offset: 4 desc: UART1 power/clock control bit. + // RESERVED: u1, // bit offset: 5 desc: Reserved. reserved2: u1 = 0, - PCPWM1: bool, // bit offset: 6 desc: PWM1 power/clock control bit. - PCI2C0: bool, // bit offset: 7 desc: The I2C0 interface power/clock control bit. - PCSPI: bool, // bit offset: 8 desc: The SPI interface power/clock control bit. - PCRTC: bool, // bit offset: 9 desc: The RTC power/clock control bit. - PCSSP1: bool, // bit offset: 10 desc: The SSP 1 interface power/clock control bit. + PCPWM1: u1, // bit offset: 6 desc: PWM1 power/clock control bit. + PCI2C0: u1, // bit offset: 7 desc: The I2C0 interface power/clock control bit. + PCSPI: u1, // bit offset: 8 desc: The SPI interface power/clock control bit. + PCRTC: u1, // bit offset: 9 desc: The RTC power/clock control bit. + PCSSP1: u1, // bit offset: 10 desc: The SSP 1 interface power/clock control bit. + // RESERVED: u1, // bit offset: 11 desc: Reserved. reserved3: u1 = 0, - PCADC: bool, // bit offset: 12 desc: A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. - PCCAN1: bool, // bit offset: 13 desc: CAN Controller 1 power/clock control bit. - PCCAN2: bool, // bit offset: 14 desc: CAN Controller 2 power/clock control bit. - PCGPIO: bool, // bit offset: 15 desc: Power/clock control bit for IOCON, GPIO, and GPIO interrupts. - PCRIT: bool, // bit offset: 16 desc: Repetitive Interrupt Timer power/clock control bit. - PCMCPWM: bool, // bit offset: 17 desc: Motor Control PWM - PCQEI: bool, // bit offset: 18 desc: Quadrature Encoder Interface power/clock control bit. - PCI2C1: bool, // bit offset: 19 desc: The I2C1 interface power/clock control bit. + PCADC: u1, // bit offset: 12 desc: A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. + PCCAN1: u1, // bit offset: 13 desc: CAN Controller 1 power/clock control bit. + PCCAN2: u1, // bit offset: 14 desc: CAN Controller 2 power/clock control bit. + PCGPIO: u1, // bit offset: 15 desc: Power/clock control bit for IOCON, GPIO, and GPIO interrupts. + PCRIT: u1, // bit offset: 16 desc: Repetitive Interrupt Timer power/clock control bit. + PCMCPWM: u1, // bit offset: 17 desc: Motor Control PWM + PCQEI: u1, // bit offset: 18 desc: Quadrature Encoder Interface power/clock control bit. + PCI2C1: u1, // bit offset: 19 desc: The I2C1 interface power/clock control bit. + // RESERVED: u1, // bit offset: 20 desc: Reserved. reserved4: u1 = 0, - PCSSP0: bool, // bit offset: 21 desc: The SSP0 interface power/clock control bit. - PCTIM2: bool, // bit offset: 22 desc: Timer 2 power/clock control bit. - PCTIM3: bool, // bit offset: 23 desc: Timer 3 power/clock control bit. - PCUART2: bool, // bit offset: 24 desc: UART 2 power/clock control bit. - PCUART3: bool, // bit offset: 25 desc: UART 3 power/clock control bit. - PCI2C2: bool, // bit offset: 26 desc: I2C interface 2 power/clock control bit. - PCI2S: bool, // bit offset: 27 desc: I2S interface power/clock control bit. + PCSSP0: u1, // bit offset: 21 desc: The SSP0 interface power/clock control bit. + PCTIM2: u1, // bit offset: 22 desc: Timer 2 power/clock control bit. + PCTIM3: u1, // bit offset: 23 desc: Timer 3 power/clock control bit. + PCUART2: u1, // bit offset: 24 desc: UART 2 power/clock control bit. + PCUART3: u1, // bit offset: 25 desc: UART 3 power/clock control bit. + PCI2C2: u1, // bit offset: 26 desc: I2C interface 2 power/clock control bit. + PCI2S: u1, // bit offset: 27 desc: I2S interface power/clock control bit. + // RESERVED: u1, // bit offset: 28 desc: Reserved. reserved5: u1 = 0, - PCGPDMA: bool, // bit offset: 29 desc: GPDMA function power/clock control bit. - PCENET: bool, // bit offset: 30 desc: Ethernet block power/clock control bit. - PCUSB: bool, // bit offset: 31 desc: USB interface power/clock control bit. + PCGPDMA: u1, // bit offset: 29 desc: GPDMA function power/clock control bit. + PCENET: u1, // bit offset: 30 desc: Ethernet block power/clock control bit. + PCUSB: u1, // bit offset: 31 desc: USB interface power/clock control bit. }); // byte offset: 260 CPU Clock Configuration Register pub const CCLKCFG = mmio(Address + 0x00000104, 32, packed struct { CCLKSEL: u8, // bit offset: 0 desc: Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock. + // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12697,6 +16283,7 @@ pub const SYSCON = extern struct { // byte offset: 264 USB Clock Configuration Register pub const USBCLKCFG = mmio(Address + 0x00000108, 32, packed struct { USBSEL: u4, // bit offset: 0 desc: Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12728,7 +16315,14 @@ pub const SYSCON = extern struct { }); // byte offset: 268 Clock Source Select Register pub const CLKSRCSEL = mmio(Address + 0x0000010c, 32, packed struct { - CLKSRC: u2, // bit offset: 0 desc: Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. + CLKSRC: enum(u2) { // bit offset: 0 desc: Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. + @"SELECTS_THE_INTERNAL" = 0, // desc: Selects the Internal RC oscillator as the PLL0 clock source (default). + @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s. + @"SELECTS_THE_RTC_OSCI" = 2, // desc: Selects the RTC oscillator as the PLL0 clock source. + // @"RESERVED", // desc: Reserved, do not use this setting. + _, // non-exhaustive + }, + // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -12762,9 +16356,11 @@ pub const SYSCON = extern struct { }); // byte offset: 272 Allows clearing the current CAN channel sleep state as well as reading that state. pub const CANSLEEPCLR = mmio(Address + 0x00000110, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - CAN1SLEEP: bool, // bit offset: 1 desc: Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. - CAN2SLEEP: bool, // bit offset: 2 desc: Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. + CAN1SLEEP: u1, // bit offset: 1 desc: Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. + CAN2SLEEP: u1, // bit offset: 2 desc: Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. + // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -12797,9 +16393,11 @@ pub const SYSCON = extern struct { }); // byte offset: 276 Allows reading the wake-up state of the CAN channels. pub const CANWAKEFLAGS = mmio(Address + 0x00000114, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - CAN1WAKE: bool, // bit offset: 1 desc: Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. - CAN2WAKE: bool, // bit offset: 2 desc: Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. + CAN1WAKE: u1, // bit offset: 1 desc: Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. + CAN2WAKE: u1, // bit offset: 2 desc: Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. + // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -12832,10 +16430,11 @@ pub const SYSCON = extern struct { }); // byte offset: 320 External Interrupt Flag Register pub const EXTINT = mmio(Address + 0x00000140, 32, packed struct { - EINT0: bool, // bit offset: 0 desc: In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT1: bool, // bit offset: 1 desc: In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT2: bool, // bit offset: 2 desc: In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT3: bool, // bit offset: 3 desc: In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT0: u1, // bit offset: 0 desc: In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT1: u1, // bit offset: 1 desc: In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT2: u1, // bit offset: 2 desc: In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + EINT3: u1, // bit offset: 3 desc: In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12867,10 +16466,23 @@ pub const SYSCON = extern struct { }); // byte offset: 328 External Interrupt Mode register pub const EXTMODE = mmio(Address + 0x00000148, 32, packed struct { - EXTMODE0: bool, // bit offset: 0 desc: External interrupt 0 EINT0 mode. - EXTMODE1: bool, // bit offset: 1 desc: External interrupt 1 EINT1 mode. - EXTMODE2: bool, // bit offset: 2 desc: External interrupt 2 EINT2 mode. - EXTMODE3: bool, // bit offset: 3 desc: External interrupt 3 EINT3 mode. + EXTMODE0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 mode. + @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT0. + @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT0 is edge sensitive. + }, + EXTMODE1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 mode. + @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT1. + @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT1 is edge sensitive. + }, + EXTMODE2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 mode. + @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT2. + @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT2 is edge sensitive. + }, + EXTMODE3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 mode. + @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT3. + @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT3 is edge sensitive. + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12902,10 +16514,23 @@ pub const SYSCON = extern struct { }); // byte offset: 332 External Interrupt Polarity Register pub const EXTPOLAR = mmio(Address + 0x0000014c, 32, packed struct { - EXTPOLAR0: bool, // bit offset: 0 desc: External interrupt 0 EINT0 polarity. - EXTPOLAR1: bool, // bit offset: 1 desc: External interrupt 1 EINT1 polarity. - EXTPOLAR2: bool, // bit offset: 2 desc: External interrupt 2 EINT2 polarity. - EXTPOLAR3: bool, // bit offset: 3 desc: External interrupt 3 EINT3 polarity. + EXTPOLAR0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 polarity. + @"FALLING_EDGE" = 0, // desc: Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). + @"RISING_EDGE" = 1, // desc: Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). + }, + EXTPOLAR1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 polarity. + @"FALLING_EDGE" = 0, // desc: Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1). + @"RISING_EDGE" = 1, // desc: Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). + }, + EXTPOLAR2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 polarity. + @"FALLING_EDGE" = 0, // desc: Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). + @"RISING_EDGE" = 1, // desc: Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). + }, + EXTPOLAR3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 polarity. + @"FALLING_EDGE" = 0, // desc: Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). + @"RISING_EDGE" = 1, // desc: Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). + }, + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12937,10 +16562,11 @@ pub const SYSCON = extern struct { }); // byte offset: 384 Reset Source Identification Register pub const RSID = mmio(Address + 0x00000180, 32, packed struct { - POR: bool, // bit offset: 0 desc: Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. - EXTR: bool, // bit offset: 1 desc: Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR. - WDTR: bool, // bit offset: 2 desc: This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. - BODR: bool, // bit offset: 3 desc: This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. + POR: u1, // bit offset: 0 desc: Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. + EXTR: u1, // bit offset: 1 desc: Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR. + WDTR: u1, // bit offset: 2 desc: This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. + BODR: u1, // bit offset: 3 desc: This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. + // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -12972,13 +16598,24 @@ pub const SYSCON = extern struct { }); // byte offset: 416 System control and status pub const SCS = mmio(Address + 0x000001a0, 32, packed struct { + // RESERVED: u4, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OSCRANGE: bool, // bit offset: 4 desc: Main oscillator range select. - OSCEN: bool, // bit offset: 5 desc: Main oscillator enable. - OSCSTAT: bool, // bit offset: 6 desc: Main oscillator status. + OSCRANGE: enum(u1) { // bit offset: 4 desc: Main oscillator range select. + @"LOW" = 0, // desc: Low. The frequency range of the main oscillator is 1 MHz to 20 MHz. + @"HIGH" = 1, // desc: High. The frequency range of the main oscillator is 15 MHz to 25 MHz. + }, + OSCEN: enum(u1) { // bit offset: 5 desc: Main oscillator enable. + @"DISABLED" = 0, // desc: Disabled. The main oscillator is disabled. + @"ENABLED" = 1, // desc: Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. + }, + OSCSTAT: enum(u1) { // bit offset: 6 desc: Main oscillator status. + @"NOT_READY" = 0, // desc: Not ready. The main oscillator is not ready to be used as a clock source. + @"READY" = 1, // desc: Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. + }, + // RESERVED: u25, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -13007,57 +16644,203 @@ pub const SYSCON = extern struct { }); // byte offset: 424 Peripheral Clock Selection register 0. pub const PCLKSEL0 = mmio(Address + 0x000001a8, 32, packed struct { - PCLK_WDT: u2, // bit offset: 0 desc: Peripheral clock selection for WDT. - PCLK_TIMER0: u2, // bit offset: 2 desc: Peripheral clock selection for TIMER0. - PCLK_TIMER1: u2, // bit offset: 4 desc: Peripheral clock selection for TIMER1. - PCLK_UART0: u2, // bit offset: 6 desc: Peripheral clock selection for UART0. - PCLK_UART1: u2, // bit offset: 8 desc: Peripheral clock selection for UART1. + PCLK_WDT: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for WDT. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_TIMER0: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for TIMER0. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_TIMER1: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for TIMER1. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_UART0: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for UART0. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_UART1: enum(u2) { // bit offset: 8 desc: Peripheral clock selection for UART1. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + // RESERVED: u2, // bit offset: 10 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - PCLK_PWM1: u2, // bit offset: 12 desc: Peripheral clock selection for PWM1. - PCLK_I2C0: u2, // bit offset: 14 desc: Peripheral clock selection for I2C0. - PCLK_SPI: u2, // bit offset: 16 desc: Peripheral clock selection for SPI. + PCLK_PWM1: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for PWM1. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_I2C0: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for I2C0. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_SPI: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for SPI. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + // RESERVED: u2, // bit offset: 18 desc: Reserved. reserved4: u1 = 0, reserved3: u1 = 0, - PCLK_SSP1: u2, // bit offset: 20 desc: Peripheral clock selection for SSP1. - PCLK_DAC: u2, // bit offset: 22 desc: Peripheral clock selection for DAC. - PCLK_ADC: u2, // bit offset: 24 desc: Peripheral clock selection for ADC. - PCLK_CAN1: u2, // bit offset: 26 desc: Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - PCLK_CAN2: u2, // bit offset: 28 desc: Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - PCLK_ACF: u2, // bit offset: 30 desc: Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + PCLK_SSP1: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for SSP1. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_DAC: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for DAC. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_ADC: enum(u2) { // bit offset: 24 desc: Peripheral clock selection for ADC. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_CAN1: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6. + }, + PCLK_CAN2: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6, + }, + PCLK_ACF: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6 + }, }); // byte offset: 428 Peripheral Clock Selection register 1. pub const PCLKSEL1 = mmio(Address + 0x000001ac, 32, packed struct { - PCLK_QEI: u2, // bit offset: 0 desc: Peripheral clock selection for the Quadrature Encoder Interface. - PCLK_GPIOINT: u2, // bit offset: 2 desc: Peripheral clock selection for GPIO interrupts. - PCLK_PCB: u2, // bit offset: 4 desc: Peripheral clock selection for the Pin Connect block. - PCLK_I2C1: u2, // bit offset: 6 desc: Peripheral clock selection for I2C1. + PCLK_QEI: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for the Quadrature Encoder Interface. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_GPIOINT: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for GPIO interrupts. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_PCB: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for the Pin Connect block. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_I2C1: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for I2C1. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + // RESERVED: u2, // bit offset: 8 desc: Reserved. reserved2: u1 = 0, reserved1: u1 = 0, - PCLK_SSP0: u2, // bit offset: 10 desc: Peripheral clock selection for SSP0. - PCLK_TIMER2: u2, // bit offset: 12 desc: Peripheral clock selection for TIMER2. - PCLK_TIMER3: u2, // bit offset: 14 desc: Peripheral clock selection for TIMER3. - PCLK_UART2: u2, // bit offset: 16 desc: Peripheral clock selection for UART2. - PCLK_UART3: u2, // bit offset: 18 desc: Peripheral clock selection for UART3. - PCLK_I2C2: u2, // bit offset: 20 desc: Peripheral clock selection for I2C2. - PCLK_I2S: u2, // bit offset: 22 desc: Peripheral clock selection for I2S. + PCLK_SSP0: enum(u2) { // bit offset: 10 desc: Peripheral clock selection for SSP0. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_TIMER2: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for TIMER2. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_TIMER3: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for TIMER3. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_UART2: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for UART2. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_UART3: enum(u2) { // bit offset: 18 desc: Peripheral clock selection for UART3. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_I2C2: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for I2C2. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_I2S: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for I2S. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + // RESERVED: u2, // bit offset: 24 desc: Reserved. reserved4: u1 = 0, reserved3: u1 = 0, - PCLK_RIT: u2, // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. - PCLK_SYSCON: u2, // bit offset: 28 desc: Peripheral clock selection for the System Control block. - PCLK_MC: u2, // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. + PCLK_RIT: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_SYSCON: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for the System Control block. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, + PCLK_MC: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. + @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 + @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK + @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 + @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 + }, }); // byte offset: 448 USB Interrupt Status pub const USBINTST = mmio(Address + 0x000001c0, 32, packed struct { - USB_INT_REQ_LP: bool, // bit offset: 0 desc: Low priority interrupt line status. This bit is read-only. - USB_INT_REQ_HP: bool, // bit offset: 1 desc: High priority interrupt line status. This bit is read-only. - USB_INT_REQ_DMA: bool, // bit offset: 2 desc: DMA interrupt line status. This bit is read-only. - USB_HOST_INT: bool, // bit offset: 3 desc: USB host interrupt line status. This bit is read-only. - USB_ATX_INT: bool, // bit offset: 4 desc: External ATX interrupt line status. This bit is read-only. - USB_OTG_INT: bool, // bit offset: 5 desc: OTG interrupt line status. This bit is read-only. - USB_I2C_INT: bool, // bit offset: 6 desc: I2C module interrupt line status. This bit is read-only. + USB_INT_REQ_LP: u1, // bit offset: 0 desc: Low priority interrupt line status. This bit is read-only. + USB_INT_REQ_HP: u1, // bit offset: 1 desc: High priority interrupt line status. This bit is read-only. + USB_INT_REQ_DMA: u1, // bit offset: 2 desc: DMA interrupt line status. This bit is read-only. + USB_HOST_INT: u1, // bit offset: 3 desc: USB host interrupt line status. This bit is read-only. + USB_ATX_INT: u1, // bit offset: 4 desc: External ATX interrupt line status. This bit is read-only. + USB_OTG_INT: u1, // bit offset: 5 desc: OTG interrupt line status. This bit is read-only. + USB_I2C_INT: u1, // bit offset: 6 desc: I2C module interrupt line status. This bit is read-only. + // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - USB_NEED_CLK: bool, // bit offset: 8 desc: USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only. + USB_NEED_CLK: u1, // bit offset: 8 desc: USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only. + // RESERVED: u22, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. reserved23: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, @@ -13080,18 +16863,19 @@ pub const SYSCON = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - EN_USB_INTS: bool, // bit offset: 31 desc: Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. + EN_USB_INTS: u1, // bit offset: 31 desc: Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. }); // byte offset: 452 Selects between alternative requests on DMA channels 0 through 7 and 10 through 15 pub const DMACREQSEL = mmio(Address + 0x000001c4, 32, packed struct { - DMASEL08: bool, // bit offset: 0 desc: Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected. - DMASEL09: bool, // bit offset: 1 desc: Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected. - DMASEL10: bool, // bit offset: 2 desc: Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected. - DMASEL11: bool, // bit offset: 3 desc: Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected. - DMASEL12: bool, // bit offset: 4 desc: Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected. - DMASEL13: bool, // bit offset: 5 desc: Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected. - DMASEL14: bool, // bit offset: 6 desc: Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected. - DMASEL15: bool, // bit offset: 7 desc: Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected. + DMASEL08: u1, // bit offset: 0 desc: Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected. + DMASEL09: u1, // bit offset: 1 desc: Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected. + DMASEL10: u1, // bit offset: 2 desc: Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected. + DMASEL11: u1, // bit offset: 3 desc: Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected. + DMASEL12: u1, // bit offset: 4 desc: Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected. + DMASEL13: u1, // bit offset: 5 desc: Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected. + DMASEL14: u1, // bit offset: 6 desc: Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected. + DMASEL15: u1, // bit offset: 7 desc: Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13119,10 +16903,18 @@ pub const SYSCON = extern struct { }); // byte offset: 456 Clock Output Configuration Register pub const CLKOUTCFG = mmio(Address + 0x000001c8, 32, packed struct { - CLKOUTSEL: u4, // bit offset: 0 desc: Selects the clock source for the CLKOUT function. Other values are reserved. Do not use. + CLKOUTSEL: enum(u4) { // bit offset: 0 desc: Selects the clock source for the CLKOUT function. Other values are reserved. Do not use. + @"SELECTS_THE_CPU_CLOC" = 0, // desc: Selects the CPU clock as the CLKOUT source. + @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the CLKOUT source. + @"SELECTS_THE_INTERNAL" = 2, // desc: Selects the Internal RC oscillator as the CLKOUT source. + @"SELECTS_THE_USB_CLOC" = 3, // desc: Selects the USB clock as the CLKOUT source. + @"SELECTS_THE_RTC_OSCI" = 4, // desc: Selects the RTC oscillator as the CLKOUT source. + _, // non-exhaustive + }, CLKOUTDIV: u4, // bit offset: 4 desc: Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16. - CLKOUT_EN: bool, // bit offset: 8 desc: CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. - CLKOUT_ACT: bool, // bit offset: 9 desc: CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. + CLKOUT_EN: u1, // bit offset: 8 desc: CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. + CLKOUT_ACT: u1, // bit offset: 9 desc: CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. + // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -13151,22 +16943,25 @@ pub const EMAC = extern struct { pub const Address: u32 = 0x50000000; // byte offset: 0 MAC configuration register 1. pub const MAC1 = mmio(Address + 0x00000000, 32, packed struct { - RXENABLE: bool, // bit offset: 0 desc: RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. - PARF: bool, // bit offset: 1 desc: PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. - RXFLOWCTRL: bool, // bit offset: 2 desc: RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. - TXFLOWCTRL: bool, // bit offset: 3 desc: TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. - LOOPBACK: bool, // bit offset: 4 desc: Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. + RXENABLE: u1, // bit offset: 0 desc: RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. + PARF: u1, // bit offset: 1 desc: PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. + RXFLOWCTRL: u1, // bit offset: 2 desc: RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. + TXFLOWCTRL: u1, // bit offset: 3 desc: TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. + LOOPBACK: u1, // bit offset: 4 desc: Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. + // RESERVED: u3, // bit offset: 5 desc: Unused reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESETTX: bool, // bit offset: 8 desc: Setting this bit will put the Transmit Function logic in reset. - RESETMCSTX: bool, // bit offset: 9 desc: Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. - RESETRX: bool, // bit offset: 10 desc: Setting this bit will put the Ethernet receive logic in reset. - RESETMCSRX: bool, // bit offset: 11 desc: Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. - reserved3: u1 = 0, - reserved2: u1 = 0, - SIMRESET: bool, // bit offset: 14 desc: SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. - SOFTRESET: bool, // bit offset: 15 desc: SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. + RESETTX: u1, // bit offset: 8 desc: Setting this bit will put the Transmit Function logic in reset. + RESETMCSTX: u1, // bit offset: 9 desc: Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. + RESETRX: u1, // bit offset: 10 desc: Setting this bit will put the Ethernet receive logic in reset. + RESETMCSRX: u1, // bit offset: 11 desc: Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. + // RESERVED: u2, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. + reserved5: u1 = 0, + reserved4: u1 = 0, + SIMRESET: u1, // bit offset: 14 desc: SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. + SOFTRESET: u1, // bit offset: 15 desc: SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13186,21 +16981,23 @@ pub const EMAC = extern struct { }); // byte offset: 4 MAC configuration register 2. pub const MAC2 = mmio(Address + 0x00000004, 32, packed struct { - FULLDUPLEX: bool, // bit offset: 0 desc: When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. - FLC: bool, // bit offset: 1 desc: FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. - HFEN: bool, // bit offset: 2 desc: HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. - DELAYEDCRC: bool, // bit offset: 3 desc: DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. - CRCEN: bool, // bit offset: 4 desc: CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. - PADCRCEN: bool, // bit offset: 5 desc: PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. - VLANPADEN: bool, // bit offset: 6 desc: VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - AUTODETPADEN: bool, // bit offset: 7 desc: AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - PPENF: bool, // bit offset: 8 desc: PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. - LPENF: bool, // bit offset: 9 desc: LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. + FULLDUPLEX: u1, // bit offset: 0 desc: When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. + FLC: u1, // bit offset: 1 desc: FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. + HFEN: u1, // bit offset: 2 desc: HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. + DELAYEDCRC: u1, // bit offset: 3 desc: DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. + CRCEN: u1, // bit offset: 4 desc: CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. + PADCRCEN: u1, // bit offset: 5 desc: PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. + VLANPADEN: u1, // bit offset: 6 desc: VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. + AUTODETPADEN: u1, // bit offset: 7 desc: AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. + PPENF: u1, // bit offset: 8 desc: PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. + LPENF: u1, // bit offset: 9 desc: LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. + // RESERVED: u2, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, reserved1: u1 = 0, - NOBACKOFF: bool, // bit offset: 12 desc: When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. - BP_NOBACKOFF: bool, // bit offset: 13 desc: BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. - EXCESSDEFER: bool, // bit offset: 14 desc: When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. + NOBACKOFF: u1, // bit offset: 12 desc: When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. + BP_NOBACKOFF: u1, // bit offset: 13 desc: BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. + EXCESSDEFER: u1, // bit offset: 14 desc: When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. + // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13222,6 +17019,7 @@ pub const EMAC = extern struct { // byte offset: 8 Back-to-Back Inter-Packet-Gap register. pub const IPGT = mmio(Address + 0x00000008, 32, packed struct { BTOBINTEGAP: u7, // bit offset: 0 desc: BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). + // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -13251,8 +17049,10 @@ pub const EMAC = extern struct { // byte offset: 12 Non Back-to-Back Inter-Packet-Gap register. pub const IPGR = mmio(Address + 0x0000000c, 32, packed struct { NBTOBINTEGAP2: u7, // bit offset: 0 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). + // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, NBTOBINTEGAP1: u7, // bit offset: 8 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) + // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13274,11 +17074,13 @@ pub const EMAC = extern struct { // byte offset: 16 Collision window / Retry register. pub const CLRT = mmio(Address + 0x00000010, 32, packed struct { RETRANSMAX: u4, // bit offset: 0 desc: RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. + // RESERVED: u4, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, COLLWIN: u6, // bit offset: 8 desc: COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. + // RESERVED: u18, // bit offset: 14 desc: Reserved. Read value is undefined, only zero should be written. padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13301,6 +17103,7 @@ pub const EMAC = extern struct { // byte offset: 20 Maximum Frame register. pub const MAXF = mmio(Address + 0x00000014, 32, packed struct { MAXFLEN: u16, // bit offset: 0 desc: MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13320,6 +17123,7 @@ pub const EMAC = extern struct { }); // byte offset: 24 PHY Support register. pub const SUPP = mmio(Address + 0x00000018, 32, packed struct { + // RESERVED: u8, // bit offset: 0 desc: Unused reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -13328,7 +17132,8 @@ pub const EMAC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SPEED: bool, // bit offset: 8 desc: This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. + SPEED: u1, // bit offset: 8 desc: This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. + // RESERVED: u23, // bit offset: 9 desc: Unused padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13355,9 +17160,10 @@ pub const EMAC = extern struct { }); // byte offset: 28 Test register. pub const TEST = mmio(Address + 0x0000001c, 32, packed struct { - SCPQ: bool, // bit offset: 0 desc: SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. - TESTPAUSE: bool, // bit offset: 1 desc: This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. - TESTBP: bool, // bit offset: 2 desc: TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. + SCPQ: u1, // bit offset: 0 desc: SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. + TESTPAUSE: u1, // bit offset: 1 desc: This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. + TESTBP: u1, // bit offset: 2 desc: TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. + // RESERVED: u29, // bit offset: 3 desc: Unused padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -13390,9 +17196,10 @@ pub const EMAC = extern struct { }); // byte offset: 32 MII Mgmt Configuration register. pub const MCFG = mmio(Address + 0x00000020, 32, packed struct { - SCANINC: bool, // bit offset: 0 desc: SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. - SUPPPREAMBLE: bool, // bit offset: 1 desc: SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. + SCANINC: u1, // bit offset: 0 desc: SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. + SUPPPREAMBLE: u1, // bit offset: 1 desc: SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. CLOCKSEL: u4, // bit offset: 2 desc: CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field. + // RESERVED: u9, // bit offset: 6 desc: Unused reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -13402,7 +17209,8 @@ pub const EMAC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESETMIIMGMT: bool, // bit offset: 15 desc: RESET MII MGMT. This bit resets the MII Management hardware. + RESETMIIMGMT: u1, // bit offset: 15 desc: RESET MII MGMT. This bit resets the MII Management hardware. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13422,8 +17230,9 @@ pub const EMAC = extern struct { }); // byte offset: 36 MII Mgmt Command register. pub const MCMD = mmio(Address + 0x00000024, 32, packed struct { - READ: bool, // bit offset: 0 desc: This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). - SCAN: bool, // bit offset: 1 desc: This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. + READ: u1, // bit offset: 0 desc: This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). + SCAN: u1, // bit offset: 1 desc: This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. + // RESERVED: u30, // bit offset: 2 desc: Unused padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -13458,10 +17267,12 @@ pub const EMAC = extern struct { // byte offset: 40 MII Mgmt Address register. pub const MADR = mmio(Address + 0x00000028, 32, packed struct { REGADDR: u5, // bit offset: 0 desc: REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. + // RESERVED: u3, // bit offset: 5 desc: Unused reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, PHYADDR: u5, // bit offset: 8 desc: PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). + // RESERVED: u19, // bit offset: 13 desc: Unused padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -13485,6 +17296,7 @@ pub const EMAC = extern struct { // byte offset: 44 MII Mgmt Write Data register. pub const MWTD = mmio(Address + 0x0000002c, 32, packed struct { WRITEDATA: u16, // bit offset: 0 desc: WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13505,6 +17317,7 @@ pub const EMAC = extern struct { // byte offset: 48 MII Mgmt Read Data register. pub const MRDD = mmio(Address + 0x00000030, 32, packed struct { READDATA: u16, // bit offset: 0 desc: READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13524,10 +17337,11 @@ pub const EMAC = extern struct { }); // byte offset: 52 MII Mgmt Indicators register. pub const MIND = mmio(Address + 0x00000034, 32, packed struct { - BUSY: bool, // bit offset: 0 desc: When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. - SCANNING: bool, // bit offset: 1 desc: When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. - NOTVALID: bool, // bit offset: 2 desc: When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. - MIILINKFAIL: bool, // bit offset: 3 desc: When 1 is returned - indicates that an MII Mgmt link fail has occurred. + BUSY: u1, // bit offset: 0 desc: When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. + SCANNING: u1, // bit offset: 1 desc: When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. + NOTVALID: u1, // bit offset: 2 desc: When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. + MIILINKFAIL: u1, // bit offset: 3 desc: When 1 is returned - indicates that an MII Mgmt link fail has occurred. + // RESERVED: u28, // bit offset: 4 desc: Unused padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -13561,6 +17375,7 @@ pub const EMAC = extern struct { pub const SA0 = mmio(Address + 0x00000040, 32, packed struct { SADDR2: u8, // bit offset: 0 desc: STATION ADDRESS, 2nd octet. This field holds the second octet of the station address. SADDR1: u8, // bit offset: 8 desc: STATION ADDRESS, 1st octet. This field holds the first octet of the station address. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13582,6 +17397,7 @@ pub const EMAC = extern struct { pub const SA1 = mmio(Address + 0x00000044, 32, packed struct { SADDR4: u8, // bit offset: 0 desc: STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address. SADDR3: u8, // bit offset: 8 desc: STATION ADDRESS, 3rd octet. This field holds the third octet of the station address. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13603,6 +17419,7 @@ pub const EMAC = extern struct { pub const SA2 = mmio(Address + 0x00000048, 32, packed struct { SADDR6: u8, // bit offset: 0 desc: STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address. SADDR5: u8, // bit offset: 8 desc: STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13622,17 +17439,19 @@ pub const EMAC = extern struct { }); // byte offset: 256 Command register. pub const COMMAND = mmio(Address + 0x00000100, 32, packed struct { - RXENABLE: bool, // bit offset: 0 desc: Enable receive. - TXENABLE: bool, // bit offset: 1 desc: Enable transmit. + RXENABLE: u1, // bit offset: 0 desc: Enable receive. + TXENABLE: u1, // bit offset: 1 desc: Enable transmit. + // RESERVED: u1, // bit offset: 2 desc: Unused reserved1: u1 = 0, - REGRESET: bool, // bit offset: 3 desc: When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. - TXRESET: bool, // bit offset: 4 desc: When a 1 is written, the transmit datapath is reset. - RXRESET: bool, // bit offset: 5 desc: When a 1 is written, the receive datapath is reset. - PASSRUNTFRAME: bool, // bit offset: 6 desc: When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. - PASSRXFILTER: bool, // bit offset: 7 desc: When set to 1 , disables receive filtering i.e. all frames received are written to memory. - TXFLOWCONTROL: bool, // bit offset: 8 desc: Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. - RMII: bool, // bit offset: 9 desc: When set to 1 , RMII mode is selected; if 0, MII mode is selected. - FULLDUPLEX: bool, // bit offset: 10 desc: When set to 1 , indicates full duplex operation. + REGRESET: u1, // bit offset: 3 desc: When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. + TXRESET: u1, // bit offset: 4 desc: When a 1 is written, the transmit datapath is reset. + RXRESET: u1, // bit offset: 5 desc: When a 1 is written, the receive datapath is reset. + PASSRUNTFRAME: u1, // bit offset: 6 desc: When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. + PASSRXFILTER: u1, // bit offset: 7 desc: When set to 1 , disables receive filtering i.e. all frames received are written to memory. + TXFLOWCONTROL: u1, // bit offset: 8 desc: Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. + RMII: u1, // bit offset: 9 desc: When set to 1 , RMII mode is selected; if 0, MII mode is selected. + FULLDUPLEX: u1, // bit offset: 10 desc: When set to 1 , indicates full duplex operation. + // RESERVED: u21, // bit offset: 11 desc: Unused padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -13657,8 +17476,9 @@ pub const EMAC = extern struct { }); // byte offset: 260 Status register. pub const STATUS = mmio(Address + 0x00000104, 32, packed struct { - RXSTATUS: bool, // bit offset: 0 desc: If 1, the receive channel is active. If 0, the receive channel is inactive. - TXSTATUS: bool, // bit offset: 1 desc: If 1, the transmit channel is active. If 0, the transmit channel is inactive. + RXSTATUS: u1, // bit offset: 0 desc: If 1, the receive channel is active. If 0, the receive channel is inactive. + TXSTATUS: u1, // bit offset: 1 desc: If 1, the transmit channel is active. If 0, the transmit channel is inactive. + // RESERVED: u30, // bit offset: 2 desc: Unused padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -13692,12 +17512,14 @@ pub const EMAC = extern struct { }); // byte offset: 264 Receive descriptor base address register. pub const RXDESCRIPTOR = mmio(Address + 0x00000108, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 reserved2: u1 = 0, reserved1: u1 = 0, RXDESCRIPTOR: u30, // bit offset: 2 desc: MSBs of receive descriptor base address. }); // byte offset: 268 Receive status base address register. pub const RXSTATUS = mmio(Address + 0x0000010c, 32, packed struct { + // RESERVED: u3, // bit offset: 0 desc: Fixed to 000 reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, @@ -13706,6 +17528,7 @@ pub const EMAC = extern struct { // byte offset: 272 Receive number of descriptors register. pub const RXDESCRIPTORNUMBER = mmio(Address + 0x00000110, 32, packed struct { RXDESCRIPTORN: u16, // bit offset: 0 desc: RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13726,6 +17549,7 @@ pub const EMAC = extern struct { // byte offset: 276 Receive produce index register. pub const RXPRODUCEINDEX = mmio(Address + 0x00000114, 32, packed struct { RXPRODUCEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be filled next by the receive datapath. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13746,6 +17570,7 @@ pub const EMAC = extern struct { // byte offset: 280 Receive consume index register. pub const RXCONSUMEINDEX = mmio(Address + 0x00000118, 32, packed struct { RXCONSUMEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be processed next by the receive + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13765,12 +17590,14 @@ pub const EMAC = extern struct { }); // byte offset: 284 Transmit descriptor base address register. pub const TXDESCRIPTOR = mmio(Address + 0x0000011c, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 reserved2: u1 = 0, reserved1: u1 = 0, TXD: u30, // bit offset: 2 desc: TxDescriptor. MSBs of transmit descriptor base address. }); // byte offset: 288 Transmit status base address register. pub const TXSTATUS = mmio(Address + 0x00000120, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 reserved2: u1 = 0, reserved1: u1 = 0, TXSTAT: u30, // bit offset: 2 desc: TxStatus. MSBs of transmit status base address. @@ -13778,6 +17605,7 @@ pub const EMAC = extern struct { // byte offset: 292 Transmit number of descriptors register. pub const TXDESCRIPTORNUMBER = mmio(Address + 0x00000124, 32, packed struct { TXDN: u16, // bit offset: 0 desc: TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13798,6 +17626,7 @@ pub const EMAC = extern struct { // byte offset: 296 Transmit produce index register. pub const TXPRODUCEINDEX = mmio(Address + 0x00000128, 32, packed struct { TXPI: u16, // bit offset: 0 desc: TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13818,6 +17647,7 @@ pub const EMAC = extern struct { // byte offset: 300 Transmit consume index register. pub const TXCONSUMEINDEX = mmio(Address + 0x0000012c, 32, packed struct { TXCI: u16, // bit offset: 0 desc: TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13837,28 +17667,29 @@ pub const EMAC = extern struct { }); // byte offset: 344 Transmit status vector 0 register. pub const TSV0 = mmio(Address + 0x00000158, 32, packed struct { - CRCERR: bool, // bit offset: 0 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCE: bool, // bit offset: 1 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: bool, // bit offset: 2 desc: Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - DONE: bool, // bit offset: 3 desc: Transmission of packet was completed. - MULTICAST: bool, // bit offset: 4 desc: Packet's destination was a multicast address. - BROADCAST: bool, // bit offset: 5 desc: Packet's destination was a broadcast address. - PACKETDEFER: bool, // bit offset: 6 desc: Packet was deferred for at least one attempt, but less than an excessive defer. - EXDF: bool, // bit offset: 7 desc: Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. - EXCOL: bool, // bit offset: 8 desc: Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. - LCOL: bool, // bit offset: 9 desc: Late Collision. Collision occurred beyond collision window, 512 bit times. - GIANT: bool, // bit offset: 10 desc: Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. - UNDERRUN: bool, // bit offset: 11 desc: Host side caused buffer underrun. + CRCERR: u1, // bit offset: 0 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. + LCE: u1, // bit offset: 1 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. + LOR: u1, // bit offset: 2 desc: Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. + DONE: u1, // bit offset: 3 desc: Transmission of packet was completed. + MULTICAST: u1, // bit offset: 4 desc: Packet's destination was a multicast address. + BROADCAST: u1, // bit offset: 5 desc: Packet's destination was a broadcast address. + PACKETDEFER: u1, // bit offset: 6 desc: Packet was deferred for at least one attempt, but less than an excessive defer. + EXDF: u1, // bit offset: 7 desc: Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. + EXCOL: u1, // bit offset: 8 desc: Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. + LCOL: u1, // bit offset: 9 desc: Late Collision. Collision occurred beyond collision window, 512 bit times. + GIANT: u1, // bit offset: 10 desc: Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. + UNDERRUN: u1, // bit offset: 11 desc: Host side caused buffer underrun. TOTALBYTES: u16, // bit offset: 12 desc: The total number of bytes transferred including collided attempts. - CONTROLFRAME: bool, // bit offset: 28 desc: The frame was a control frame. - PAUSE: bool, // bit offset: 29 desc: The frame was a control frame with a valid PAUSE opcode. - BACKPRESSURE: bool, // bit offset: 30 desc: Carrier-sense method backpressure was previously applied. - VLAN: bool, // bit offset: 31 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. + CONTROLFRAME: u1, // bit offset: 28 desc: The frame was a control frame. + PAUSE: u1, // bit offset: 29 desc: The frame was a control frame with a valid PAUSE opcode. + BACKPRESSURE: u1, // bit offset: 30 desc: Carrier-sense method backpressure was previously applied. + VLAN: u1, // bit offset: 31 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. }); // byte offset: 348 Transmit status vector 1 register. pub const TSV1 = mmio(Address + 0x0000015c, 32, packed struct { TBC: u16, // bit offset: 0 desc: Transmit byte count. The total number of bytes in the frame, not counting the collided bytes. TCC: u4, // bit offset: 16 desc: Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented. + // RESERVED: u12, // bit offset: 20 desc: Unused padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -13875,21 +17706,22 @@ pub const EMAC = extern struct { // byte offset: 352 Receive status vector register. pub const RSV = mmio(Address + 0x00000160, 32, packed struct { RBC: u16, // bit offset: 0 desc: Received byte count. Indicates length of received frame. - PPI: bool, // bit offset: 16 desc: Packet previously ignored. Indicates that a packet was dropped. - RXDVSEEN: bool, // bit offset: 17 desc: RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. - CESEEN: bool, // bit offset: 18 desc: Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. - RCV: bool, // bit offset: 19 desc: Receive code violation. Indicates that received PHY data does not represent a valid receive code. - CRCERR: bool, // bit offset: 20 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCERR: bool, // bit offset: 21 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: bool, // bit offset: 22 desc: Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - ROK: bool, // bit offset: 23 desc: Receive OK. The packet had valid CRC and no symbol errors. - MULTICAST: bool, // bit offset: 24 desc: The packet destination was a multicast address. - BROADCAST: bool, // bit offset: 25 desc: The packet destination was a broadcast address. - DRIBBLENIBBLE: bool, // bit offset: 26 desc: Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. - CONTROLFRAME: bool, // bit offset: 27 desc: The frame was a control frame. - PAUSE: bool, // bit offset: 28 desc: The frame was a control frame with a valid PAUSE opcode. - UO: bool, // bit offset: 29 desc: Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. - VLAN: bool, // bit offset: 30 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. + PPI: u1, // bit offset: 16 desc: Packet previously ignored. Indicates that a packet was dropped. + RXDVSEEN: u1, // bit offset: 17 desc: RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. + CESEEN: u1, // bit offset: 18 desc: Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. + RCV: u1, // bit offset: 19 desc: Receive code violation. Indicates that received PHY data does not represent a valid receive code. + CRCERR: u1, // bit offset: 20 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. + LCERR: u1, // bit offset: 21 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. + LOR: u1, // bit offset: 22 desc: Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. + ROK: u1, // bit offset: 23 desc: Receive OK. The packet had valid CRC and no symbol errors. + MULTICAST: u1, // bit offset: 24 desc: The packet destination was a multicast address. + BROADCAST: u1, // bit offset: 25 desc: The packet destination was a broadcast address. + DRIBBLENIBBLE: u1, // bit offset: 26 desc: Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. + CONTROLFRAME: u1, // bit offset: 27 desc: The frame was a control frame. + PAUSE: u1, // bit offset: 28 desc: The frame was a control frame with a valid PAUSE opcode. + UO: u1, // bit offset: 29 desc: Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. + VLAN: u1, // bit offset: 30 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. + // RESERVED: u1, // bit offset: 31 desc: Unused padding1: u1 = 0, }); // byte offset: 368 Flow control counter register. @@ -13900,6 +17732,7 @@ pub const EMAC = extern struct { // byte offset: 372 Flow control status register. pub const FLOWCONTROLSTATUS = mmio(Address + 0x00000174, 32, packed struct { MCC: u16, // bit offset: 0 desc: MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. + // RESERVED: u16, // bit offset: 16 desc: Unused padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13919,20 +17752,22 @@ pub const EMAC = extern struct { }); // byte offset: 512 Receive filter control register. pub const RXFILTERCTRL = mmio(Address + 0x00000200, 32, packed struct { - AUE: bool, // bit offset: 0 desc: AcceptUnicastEn. When set to 1, all unicast frames are accepted. - ABE: bool, // bit offset: 1 desc: AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. - AME: bool, // bit offset: 2 desc: AcceptMulticastEn. When set to 1, all multicast frames are accepted. - AUHE: bool, // bit offset: 3 desc: AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. - AMHE: bool, // bit offset: 4 desc: AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. - APE: bool, // bit offset: 5 desc: AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. + AUE: u1, // bit offset: 0 desc: AcceptUnicastEn. When set to 1, all unicast frames are accepted. + ABE: u1, // bit offset: 1 desc: AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. + AME: u1, // bit offset: 2 desc: AcceptMulticastEn. When set to 1, all multicast frames are accepted. + AUHE: u1, // bit offset: 3 desc: AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. + AMHE: u1, // bit offset: 4 desc: AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. + APE: u1, // bit offset: 5 desc: AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. + // RESERVED: u6, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MPEW: bool, // bit offset: 12 desc: MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. - RFEW: bool, // bit offset: 13 desc: RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. + MPEW: u1, // bit offset: 12 desc: MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. + RFEW: u1, // bit offset: 13 desc: RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. + // RESERVED: u18, // bit offset: 14 desc: Unused padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13954,15 +17789,17 @@ pub const EMAC = extern struct { }); // byte offset: 516 Receive filter WoL status register. pub const RXFILTERWOLSTATUS = mmio(Address + 0x00000204, 32, packed struct { - AUW: bool, // bit offset: 0 desc: AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. - ABW: bool, // bit offset: 1 desc: AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. - AMW: bool, // bit offset: 2 desc: AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. - AUHW: bool, // bit offset: 3 desc: AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. - AMHW: bool, // bit offset: 4 desc: AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. - APW: bool, // bit offset: 5 desc: AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. + AUW: u1, // bit offset: 0 desc: AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. + ABW: u1, // bit offset: 1 desc: AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. + AMW: u1, // bit offset: 2 desc: AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. + AUHW: u1, // bit offset: 3 desc: AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. + AMHW: u1, // bit offset: 4 desc: AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. + APW: u1, // bit offset: 5 desc: AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. + // RESERVED: u1, // bit offset: 6 desc: Unused reserved1: u1 = 0, - RFW: bool, // bit offset: 7 desc: RxFilterWoL. When the value is 1, the receive filter caused WoL. - MPW: bool, // bit offset: 8 desc: MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. + RFW: u1, // bit offset: 7 desc: RxFilterWoL. When the value is 1, the receive filter caused WoL. + MPW: u1, // bit offset: 8 desc: MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. + // RESERVED: u23, // bit offset: 9 desc: Unused padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13989,15 +17826,17 @@ pub const EMAC = extern struct { }); // byte offset: 520 Receive filter WoL clear register. pub const RXFILTERWOLCLEAR = mmio(Address + 0x00000208, 32, packed struct { - AUWCLR: bool, // bit offset: 0 desc: AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - ABWCLR: bool, // bit offset: 1 desc: AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMWCLR: bool, // bit offset: 2 desc: AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AUHWCLR: bool, // bit offset: 3 desc: AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMHWCLR: bool, // bit offset: 4 desc: AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - APWCLR: bool, // bit offset: 5 desc: AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AUWCLR: u1, // bit offset: 0 desc: AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + ABWCLR: u1, // bit offset: 1 desc: AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AMWCLR: u1, // bit offset: 2 desc: AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AUHWCLR: u1, // bit offset: 3 desc: AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + AMHWCLR: u1, // bit offset: 4 desc: AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + APWCLR: u1, // bit offset: 5 desc: AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + // RESERVED: u1, // bit offset: 6 desc: Unused reserved1: u1 = 0, - RFWCLR: bool, // bit offset: 7 desc: RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - MPWCLR: bool, // bit offset: 8 desc: MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + RFWCLR: u1, // bit offset: 7 desc: RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + MPWCLR: u1, // bit offset: 8 desc: MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. + // RESERVED: u23, // bit offset: 9 desc: Unused padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -14032,20 +17871,22 @@ pub const EMAC = extern struct { }); // byte offset: 4064 Interrupt status register. pub const INTSTATUS = mmio(Address + 0x00000fe0, 32, packed struct { - RXOVERRUNINT: bool, // bit offset: 0 desc: Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. - RXERRORINT: bool, // bit offset: 1 desc: Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. - RXFINISHEDINT: bool, // bit offset: 2 desc: Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINT: bool, // bit offset: 3 desc: Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINT: bool, // bit offset: 4 desc: Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. - TXERRORINT: bool, // bit offset: 5 desc: Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. - TXFINISHEDINT: bool, // bit offset: 6 desc: Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINT: bool, // bit offset: 7 desc: Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + RXOVERRUNINT: u1, // bit offset: 0 desc: Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. + RXERRORINT: u1, // bit offset: 1 desc: Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. + RXFINISHEDINT: u1, // bit offset: 2 desc: Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXDONEINT: u1, // bit offset: 3 desc: Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. + TXUNDERRUNINT: u1, // bit offset: 4 desc: Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. + TXERRORINT: u1, // bit offset: 5 desc: Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. + TXFINISHEDINT: u1, // bit offset: 6 desc: Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXDONEINT: u1, // bit offset: 7 desc: Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + // RESERVED: u4, // bit offset: 8 desc: Unused reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SOFTINT: bool, // bit offset: 12 desc: Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINT: bool, // bit offset: 13 desc: Interrupt triggered by a Wake-up event detected by the receive filter. + SOFTINT: u1, // bit offset: 12 desc: Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. + WAKEUPINT: u1, // bit offset: 13 desc: Interrupt triggered by a Wake-up event detected by the receive filter. + // RESERVED: u18, // bit offset: 14 desc: Unused padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14067,20 +17908,22 @@ pub const EMAC = extern struct { }); // byte offset: 4068 Interrupt enable register. pub const INTENABLE = mmio(Address + 0x00000fe4, 32, packed struct { - RXOVERRUNINTEN: bool, // bit offset: 0 desc: Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. - RXERRORINTEN: bool, // bit offset: 1 desc: Enable for interrupt trigger on receive errors. - RXFINISHEDINTEN: bool, // bit offset: 2 desc: Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINTEN: bool, // bit offset: 3 desc: Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINTEN: bool, // bit offset: 4 desc: Enable for interrupt trigger on transmit buffer or descriptor underrun situations. - TXERRORINTEN: bool, // bit offset: 5 desc: Enable for interrupt trigger on transmit errors. - TXFINISHEDINTEN: bool, // bit offset: 6 desc: Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINTEN: bool, // bit offset: 7 desc: Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + RXOVERRUNINTEN: u1, // bit offset: 0 desc: Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. + RXERRORINTEN: u1, // bit offset: 1 desc: Enable for interrupt trigger on receive errors. + RXFINISHEDINTEN: u1, // bit offset: 2 desc: Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXDONEINTEN: u1, // bit offset: 3 desc: Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. + TXUNDERRUNINTEN: u1, // bit offset: 4 desc: Enable for interrupt trigger on transmit buffer or descriptor underrun situations. + TXERRORINTEN: u1, // bit offset: 5 desc: Enable for interrupt trigger on transmit errors. + TXFINISHEDINTEN: u1, // bit offset: 6 desc: Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXDONEINTEN: u1, // bit offset: 7 desc: Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. + // RESERVED: u4, // bit offset: 8 desc: Unused reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SOFTINTEN: bool, // bit offset: 12 desc: Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINTEN: bool, // bit offset: 13 desc: Enable for interrupt triggered by a Wake-up event detected by the receive filter. + SOFTINTEN: u1, // bit offset: 12 desc: Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. + WAKEUPINTEN: u1, // bit offset: 13 desc: Enable for interrupt triggered by a Wake-up event detected by the receive filter. + // RESERVED: u18, // bit offset: 14 desc: Unused padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14102,20 +17945,22 @@ pub const EMAC = extern struct { }); // byte offset: 4072 Interrupt clear register. pub const INTCLEAR = mmio(Address + 0x00000fe8, 32, packed struct { - RXOVERRUNINTCLR: bool, // bit offset: 0 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXERRORINTCLR: bool, // bit offset: 1 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTCLR: bool, // bit offset: 2 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXDONEINTCLR: bool, // bit offset: 3 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTCLR: bool, // bit offset: 4 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXERRORINTCLR: bool, // bit offset: 5 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTCLR: bool, // bit offset: 6 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXDONEINTCLR: bool, // bit offset: 7 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXOVERRUNINTCLR: u1, // bit offset: 0 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXERRORINTCLR: u1, // bit offset: 1 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXFINISHEDINTCLR: u1, // bit offset: 2 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + RXDONEINTCLR: u1, // bit offset: 3 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXUNDERRUNINTCLR: u1, // bit offset: 4 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXERRORINTCLR: u1, // bit offset: 5 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXFINISHEDINTCLR: u1, // bit offset: 6 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + TXDONEINTCLR: u1, // bit offset: 7 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + // RESERVED: u4, // bit offset: 8 desc: Unused reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SOFTINTCLR: bool, // bit offset: 12 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTCLR: bool, // bit offset: 13 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + SOFTINTCLR: u1, // bit offset: 12 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + WAKEUPINTCLR: u1, // bit offset: 13 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. + // RESERVED: u18, // bit offset: 14 desc: Unused padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14137,20 +17982,22 @@ pub const EMAC = extern struct { }); // byte offset: 4076 Interrupt set register. pub const INTSET = mmio(Address + 0x00000fec, 32, packed struct { - RXOVERRUNINTSET: bool, // bit offset: 0 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXERRORINTSET: bool, // bit offset: 1 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTSET: bool, // bit offset: 2 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXDONEINTSET: bool, // bit offset: 3 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTSET: bool, // bit offset: 4 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXERRORINTSET: bool, // bit offset: 5 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTSET: bool, // bit offset: 6 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXDONEINTSET: bool, // bit offset: 7 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXOVERRUNINTSET: u1, // bit offset: 0 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXERRORINTSET: u1, // bit offset: 1 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXFINISHEDINTSET: u1, // bit offset: 2 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + RXDONEINTSET: u1, // bit offset: 3 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXUNDERRUNINTSET: u1, // bit offset: 4 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXERRORINTSET: u1, // bit offset: 5 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXFINISHEDINTSET: u1, // bit offset: 6 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + TXDONEINTSET: u1, // bit offset: 7 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + // RESERVED: u4, // bit offset: 8 desc: Unused reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SOFTINTSET: bool, // bit offset: 12 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTSET: bool, // bit offset: 13 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + SOFTINTSET: u1, // bit offset: 12 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + WAKEUPINTSET: u1, // bit offset: 13 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. + // RESERVED: u18, // bit offset: 14 desc: Unused padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14172,6 +18019,7 @@ pub const EMAC = extern struct { }); // byte offset: 4084 Power-down register. pub const POWERDOWN = mmio(Address + 0x00000ff4, 32, packed struct { + // RESERVED: u31, // bit offset: 0 desc: Unused reserved31: u1 = 0, reserved30: u1 = 0, reserved29: u1 = 0, @@ -14203,21 +18051,22 @@ pub const EMAC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PD: bool, // bit offset: 31 desc: PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. + PD: u1, // bit offset: 31 desc: PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. }); }; pub const GPDMA = extern struct { pub const Address: u32 = 0x50004000; // byte offset: 0 DMA Interrupt Status Register pub const INTSTAT = mmio(Address + 0x00000000, 32, packed struct { - INTSTAT0: bool, // bit offset: 0 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT1: bool, // bit offset: 1 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT2: bool, // bit offset: 2 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT3: bool, // bit offset: 3 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT4: bool, // bit offset: 4 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT5: bool, // bit offset: 5 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT6: bool, // bit offset: 6 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT7: bool, // bit offset: 7 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT0: u1, // bit offset: 0 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT1: u1, // bit offset: 1 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT2: u1, // bit offset: 2 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT3: u1, // bit offset: 3 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT4: u1, // bit offset: 4 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT5: u1, // bit offset: 5 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT6: u1, // bit offset: 6 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + INTSTAT7: u1, // bit offset: 7 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14245,14 +18094,15 @@ pub const GPDMA = extern struct { }); // byte offset: 4 DMA Interrupt Terminal Count Request Status Register pub const INTTCSTAT = mmio(Address + 0x00000004, 32, packed struct { - INTTCSTAT0: bool, // bit offset: 0 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT1: bool, // bit offset: 1 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT2: bool, // bit offset: 2 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT3: bool, // bit offset: 3 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT4: bool, // bit offset: 4 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT5: bool, // bit offset: 5 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT6: bool, // bit offset: 6 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT7: bool, // bit offset: 7 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT0: u1, // bit offset: 0 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT1: u1, // bit offset: 1 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT2: u1, // bit offset: 2 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT3: u1, // bit offset: 3 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT4: u1, // bit offset: 4 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT5: u1, // bit offset: 5 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT6: u1, // bit offset: 6 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + INTTCSTAT7: u1, // bit offset: 7 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14280,14 +18130,15 @@ pub const GPDMA = extern struct { }); // byte offset: 8 DMA Interrupt Terminal Count Request Clear Register pub const INTTCCLEAR = mmio(Address + 0x00000008, 32, packed struct { - INTTCCLEAR0: bool, // bit offset: 0 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR1: bool, // bit offset: 1 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR2: bool, // bit offset: 2 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR3: bool, // bit offset: 3 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR4: bool, // bit offset: 4 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR5: bool, // bit offset: 5 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR6: bool, // bit offset: 6 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR7: bool, // bit offset: 7 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR0: u1, // bit offset: 0 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR1: u1, // bit offset: 1 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR2: u1, // bit offset: 2 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR3: u1, // bit offset: 3 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR4: u1, // bit offset: 4 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR5: u1, // bit offset: 5 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR6: u1, // bit offset: 6 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + INTTCCLEAR7: u1, // bit offset: 7 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14315,14 +18166,15 @@ pub const GPDMA = extern struct { }); // byte offset: 12 DMA Interrupt Error Status Register pub const INTERRSTAT = mmio(Address + 0x0000000c, 32, packed struct { - INTERRSTAT0: bool, // bit offset: 0 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT1: bool, // bit offset: 1 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT2: bool, // bit offset: 2 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT3: bool, // bit offset: 3 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT4: bool, // bit offset: 4 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT5: bool, // bit offset: 5 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT6: bool, // bit offset: 6 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT7: bool, // bit offset: 7 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT0: u1, // bit offset: 0 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT1: u1, // bit offset: 1 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT2: u1, // bit offset: 2 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT3: u1, // bit offset: 3 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT4: u1, // bit offset: 4 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT5: u1, // bit offset: 5 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT6: u1, // bit offset: 6 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + INTERRSTAT7: u1, // bit offset: 7 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14350,14 +18202,15 @@ pub const GPDMA = extern struct { }); // byte offset: 16 DMA Interrupt Error Clear Register pub const INTERRCLR = mmio(Address + 0x00000010, 32, packed struct { - INTERRCLR0: bool, // bit offset: 0 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR1: bool, // bit offset: 1 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR2: bool, // bit offset: 2 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR3: bool, // bit offset: 3 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR4: bool, // bit offset: 4 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR5: bool, // bit offset: 5 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR6: bool, // bit offset: 6 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR7: bool, // bit offset: 7 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR0: u1, // bit offset: 0 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR1: u1, // bit offset: 1 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR2: u1, // bit offset: 2 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR3: u1, // bit offset: 3 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR4: u1, // bit offset: 4 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR5: u1, // bit offset: 5 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR6: u1, // bit offset: 6 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + INTERRCLR7: u1, // bit offset: 7 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14385,14 +18238,15 @@ pub const GPDMA = extern struct { }); // byte offset: 20 DMA Raw Interrupt Terminal Count Status Register pub const RAWINTTCSTAT = mmio(Address + 0x00000014, 32, packed struct { - RAWINTTCSTAT0: bool, // bit offset: 0 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT1: bool, // bit offset: 1 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT2: bool, // bit offset: 2 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT3: bool, // bit offset: 3 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT4: bool, // bit offset: 4 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT5: bool, // bit offset: 5 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT6: bool, // bit offset: 6 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT7: bool, // bit offset: 7 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT0: u1, // bit offset: 0 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT1: u1, // bit offset: 1 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT2: u1, // bit offset: 2 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT3: u1, // bit offset: 3 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT4: u1, // bit offset: 4 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT5: u1, // bit offset: 5 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT6: u1, // bit offset: 6 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + RAWINTTCSTAT7: u1, // bit offset: 7 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14420,14 +18274,15 @@ pub const GPDMA = extern struct { }); // byte offset: 24 DMA Raw Error Interrupt Status Register pub const RAWINTERRSTAT = mmio(Address + 0x00000018, 32, packed struct { - RAWINTERRSTAT0: bool, // bit offset: 0 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT1: bool, // bit offset: 1 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT2: bool, // bit offset: 2 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT3: bool, // bit offset: 3 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT4: bool, // bit offset: 4 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT5: bool, // bit offset: 5 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT6: bool, // bit offset: 6 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT7: bool, // bit offset: 7 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT0: u1, // bit offset: 0 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT1: u1, // bit offset: 1 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT2: u1, // bit offset: 2 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT3: u1, // bit offset: 3 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT4: u1, // bit offset: 4 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT5: u1, // bit offset: 5 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT6: u1, // bit offset: 6 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + RAWINTERRSTAT7: u1, // bit offset: 7 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14455,14 +18310,15 @@ pub const GPDMA = extern struct { }); // byte offset: 28 DMA Enabled Channel Register pub const ENBLDCHNS = mmio(Address + 0x0000001c, 32, packed struct { - ENABLEDCHANNELS0: bool, // bit offset: 0 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS1: bool, // bit offset: 1 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS2: bool, // bit offset: 2 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS3: bool, // bit offset: 3 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS4: bool, // bit offset: 4 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS5: bool, // bit offset: 5 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS6: bool, // bit offset: 6 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS7: bool, // bit offset: 7 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS0: u1, // bit offset: 0 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS1: u1, // bit offset: 1 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS2: u1, // bit offset: 2 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS3: u1, // bit offset: 3 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS4: u1, // bit offset: 4 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS5: u1, // bit offset: 5 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS6: u1, // bit offset: 6 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS7: u1, // bit offset: 7 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14490,22 +18346,23 @@ pub const GPDMA = extern struct { }); // byte offset: 32 DMA Software Burst Request Register pub const SOFTBREQ = mmio(Address + 0x00000020, 32, packed struct { - SOFTBREQ0: bool, // bit offset: 0 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ1: bool, // bit offset: 1 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ2: bool, // bit offset: 2 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ3: bool, // bit offset: 3 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ4: bool, // bit offset: 4 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ5: bool, // bit offset: 5 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ6: bool, // bit offset: 6 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ7: bool, // bit offset: 7 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ8: bool, // bit offset: 8 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ9: bool, // bit offset: 9 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ10: bool, // bit offset: 10 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ11: bool, // bit offset: 11 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ12: bool, // bit offset: 12 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ13: bool, // bit offset: 13 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ14: bool, // bit offset: 14 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ15: bool, // bit offset: 15 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ0: u1, // bit offset: 0 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ1: u1, // bit offset: 1 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ2: u1, // bit offset: 2 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ3: u1, // bit offset: 3 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ4: u1, // bit offset: 4 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ5: u1, // bit offset: 5 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ6: u1, // bit offset: 6 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ7: u1, // bit offset: 7 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ8: u1, // bit offset: 8 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ9: u1, // bit offset: 9 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ10: u1, // bit offset: 10 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ11: u1, // bit offset: 11 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ12: u1, // bit offset: 12 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ13: u1, // bit offset: 13 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ14: u1, // bit offset: 14 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + SOFTBREQ15: u1, // bit offset: 15 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14525,22 +18382,23 @@ pub const GPDMA = extern struct { }); // byte offset: 36 DMA Software Single Request Register pub const SOFTSREQ = mmio(Address + 0x00000024, 32, packed struct { - SOFTSREQ0: bool, // bit offset: 0 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ1: bool, // bit offset: 1 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ2: bool, // bit offset: 2 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ3: bool, // bit offset: 3 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ4: bool, // bit offset: 4 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ5: bool, // bit offset: 5 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ6: bool, // bit offset: 6 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ7: bool, // bit offset: 7 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ8: bool, // bit offset: 8 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ9: bool, // bit offset: 9 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ10: bool, // bit offset: 10 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ11: bool, // bit offset: 11 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ12: bool, // bit offset: 12 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ13: bool, // bit offset: 13 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ14: bool, // bit offset: 14 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ15: bool, // bit offset: 15 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ0: u1, // bit offset: 0 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ1: u1, // bit offset: 1 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ2: u1, // bit offset: 2 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ3: u1, // bit offset: 3 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ4: u1, // bit offset: 4 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ5: u1, // bit offset: 5 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ6: u1, // bit offset: 6 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ7: u1, // bit offset: 7 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ8: u1, // bit offset: 8 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ9: u1, // bit offset: 9 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ10: u1, // bit offset: 10 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ11: u1, // bit offset: 11 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ12: u1, // bit offset: 12 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ13: u1, // bit offset: 13 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ14: u1, // bit offset: 14 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + SOFTSREQ15: u1, // bit offset: 15 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read undefined. Write reserved bits as zero. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14560,22 +18418,23 @@ pub const GPDMA = extern struct { }); // byte offset: 40 DMA Software Last Burst Request Register pub const SOFTLBREQ = mmio(Address + 0x00000028, 32, packed struct { - SOFTLBREQ0: bool, // bit offset: 0 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ1: bool, // bit offset: 1 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ2: bool, // bit offset: 2 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ3: bool, // bit offset: 3 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ4: bool, // bit offset: 4 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ5: bool, // bit offset: 5 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ6: bool, // bit offset: 6 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ7: bool, // bit offset: 7 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ8: bool, // bit offset: 8 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ9: bool, // bit offset: 9 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ10: bool, // bit offset: 10 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ11: bool, // bit offset: 11 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ12: bool, // bit offset: 12 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ13: bool, // bit offset: 13 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ14: bool, // bit offset: 14 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ15: bool, // bit offset: 15 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ0: u1, // bit offset: 0 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ1: u1, // bit offset: 1 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ2: u1, // bit offset: 2 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ3: u1, // bit offset: 3 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ4: u1, // bit offset: 4 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ5: u1, // bit offset: 5 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ6: u1, // bit offset: 6 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ7: u1, // bit offset: 7 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ8: u1, // bit offset: 8 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ9: u1, // bit offset: 9 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ10: u1, // bit offset: 10 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ11: u1, // bit offset: 11 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ12: u1, // bit offset: 12 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ13: u1, // bit offset: 13 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ14: u1, // bit offset: 14 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + SOFTLBREQ15: u1, // bit offset: 15 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14595,22 +18454,23 @@ pub const GPDMA = extern struct { }); // byte offset: 44 DMA Software Last Single Request Register pub const SOFTLSREQ = mmio(Address + 0x0000002c, 32, packed struct { - SOFTLSREQ0: bool, // bit offset: 0 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ1: bool, // bit offset: 1 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ2: bool, // bit offset: 2 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ3: bool, // bit offset: 3 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ4: bool, // bit offset: 4 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ5: bool, // bit offset: 5 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ6: bool, // bit offset: 6 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ7: bool, // bit offset: 7 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ8: bool, // bit offset: 8 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ9: bool, // bit offset: 9 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ10: bool, // bit offset: 10 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ11: bool, // bit offset: 11 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ12: bool, // bit offset: 12 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ13: bool, // bit offset: 13 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ14: bool, // bit offset: 14 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ15: bool, // bit offset: 15 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ0: u1, // bit offset: 0 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ1: u1, // bit offset: 1 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ2: u1, // bit offset: 2 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ3: u1, // bit offset: 3 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ4: u1, // bit offset: 4 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ5: u1, // bit offset: 5 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ6: u1, // bit offset: 6 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ7: u1, // bit offset: 7 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ8: u1, // bit offset: 8 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ9: u1, // bit offset: 9 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ10: u1, // bit offset: 10 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ11: u1, // bit offset: 11 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ12: u1, // bit offset: 12 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ13: u1, // bit offset: 13 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ14: u1, // bit offset: 14 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + SOFTLSREQ15: u1, // bit offset: 15 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14630,8 +18490,9 @@ pub const GPDMA = extern struct { }); // byte offset: 48 DMA Configuration Register pub const CONFIG = mmio(Address + 0x00000030, 32, packed struct { - E: bool, // bit offset: 0 desc: DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. - M: bool, // bit offset: 1 desc: AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. + E: u1, // bit offset: 0 desc: DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. + M: u1, // bit offset: 1 desc: AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -14665,22 +18526,23 @@ pub const GPDMA = extern struct { }); // byte offset: 52 DMA Synchronization Register pub const SYNC = mmio(Address + 0x00000034, 32, packed struct { - DMACSYNC0: bool, // bit offset: 0 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC1: bool, // bit offset: 1 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC2: bool, // bit offset: 2 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC3: bool, // bit offset: 3 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC4: bool, // bit offset: 4 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC5: bool, // bit offset: 5 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC6: bool, // bit offset: 6 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC7: bool, // bit offset: 7 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC8: bool, // bit offset: 8 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC9: bool, // bit offset: 9 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC10: bool, // bit offset: 10 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC11: bool, // bit offset: 11 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC12: bool, // bit offset: 12 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC13: bool, // bit offset: 13 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC14: bool, // bit offset: 14 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC15: bool, // bit offset: 15 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC0: u1, // bit offset: 0 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC1: u1, // bit offset: 1 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC2: u1, // bit offset: 2 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC3: u1, // bit offset: 3 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC4: u1, // bit offset: 4 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC5: u1, // bit offset: 5 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC6: u1, // bit offset: 6 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC7: u1, // bit offset: 7 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC8: u1, // bit offset: 8 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC9: u1, // bit offset: 9 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC10: u1, // bit offset: 10 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC11: u1, // bit offset: 11 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC12: u1, // bit offset: 12 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC13: u1, // bit offset: 13 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC14: u1, // bit offset: 14 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC15: u1, // bit offset: 15 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14708,6 +18570,7 @@ pub const GPDMA = extern struct { }); // byte offset: 264 DMA Channel 0 Linked List Item Register pub const LLI0 = mmio(Address + 0x00000108, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14719,26 +18582,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 272 DMA Channel 0 Configuration Register[1] pub const CONFIG0 = mmio(Address + 0x00000110, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 288 DMA Channel 0 Source Address Register pub const SRCADDR1 = mmio(Address + 0x00000120, 32, packed struct { @@ -14750,6 +18628,7 @@ pub const GPDMA = extern struct { }); // byte offset: 296 DMA Channel 0 Linked List Item Register pub const LLI1 = mmio(Address + 0x00000128, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14761,26 +18640,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 304 DMA Channel 0 Configuration Register[1] pub const CONFIG1 = mmio(Address + 0x00000130, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 320 DMA Channel 0 Source Address Register pub const SRCADDR2 = mmio(Address + 0x00000140, 32, packed struct { @@ -14792,6 +18686,7 @@ pub const GPDMA = extern struct { }); // byte offset: 328 DMA Channel 0 Linked List Item Register pub const LLI2 = mmio(Address + 0x00000148, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14803,26 +18698,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 336 DMA Channel 0 Configuration Register[1] pub const CONFIG2 = mmio(Address + 0x00000150, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 352 DMA Channel 0 Source Address Register pub const SRCADDR3 = mmio(Address + 0x00000160, 32, packed struct { @@ -14834,6 +18744,7 @@ pub const GPDMA = extern struct { }); // byte offset: 360 DMA Channel 0 Linked List Item Register pub const LLI3 = mmio(Address + 0x00000168, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14845,26 +18756,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 368 DMA Channel 0 Configuration Register[1] pub const CONFIG3 = mmio(Address + 0x00000170, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 384 DMA Channel 0 Source Address Register pub const SRCADDR4 = mmio(Address + 0x00000180, 32, packed struct { @@ -14876,6 +18802,7 @@ pub const GPDMA = extern struct { }); // byte offset: 392 DMA Channel 0 Linked List Item Register pub const LLI4 = mmio(Address + 0x00000188, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14887,26 +18814,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 400 DMA Channel 0 Configuration Register[1] pub const CONFIG4 = mmio(Address + 0x00000190, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 416 DMA Channel 0 Source Address Register pub const SRCADDR5 = mmio(Address + 0x000001a0, 32, packed struct { @@ -14918,6 +18860,7 @@ pub const GPDMA = extern struct { }); // byte offset: 424 DMA Channel 0 Linked List Item Register pub const LLI5 = mmio(Address + 0x000001a8, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14929,26 +18872,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 432 DMA Channel 0 Configuration Register[1] pub const CONFIG5 = mmio(Address + 0x000001b0, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 448 DMA Channel 0 Source Address Register pub const SRCADDR6 = mmio(Address + 0x000001c0, 32, packed struct { @@ -14960,6 +18918,7 @@ pub const GPDMA = extern struct { }); // byte offset: 456 DMA Channel 0 Linked List Item Register pub const LLI6 = mmio(Address + 0x000001c8, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -14971,26 +18930,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 464 DMA Channel 0 Configuration Register[1] pub const CONFIG6 = mmio(Address + 0x000001d0, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); // byte offset: 480 DMA Channel 0 Source Address Register pub const SRCADDR7 = mmio(Address + 0x000001e0, 32, packed struct { @@ -15002,6 +18976,7 @@ pub const GPDMA = extern struct { }); // byte offset: 488 DMA Channel 0 Linked List Item Register pub const LLI7 = mmio(Address + 0x000001e8, 32, packed struct { + // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. @@ -15013,26 +18988,41 @@ pub const GPDMA = extern struct { DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved + // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. reserved2: u1 = 0, reserved1: u1 = 0, - SI: bool, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: bool, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: bool, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: bool, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: bool, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: bool, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. + SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. + DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. + PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. + PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. + I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. }); // byte offset: 496 DMA Channel 0 Configuration Register[1] pub const CONFIG7 = mmio(Address + 0x000001f0, 32, packed struct { - E: bool, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. + E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: bool, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: bool, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: bool, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: bool, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: bool, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. + ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. + L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. + A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. + H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. + // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); }; pub const USB = extern struct { @@ -15040,8 +19030,12 @@ pub const USB = extern struct { // byte offset: 220 USB Receive Packet Length pub const RXPLEN = mmio(Address + 0x000000dc, 32, packed struct { PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. - DV: bool, // bit offset: 10 desc: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. - PKT_RDY: bool, // bit offset: 11 desc: The PKT_LNGTH field is valid and the packet is ready for reading. + DV: enum(u1) { // bit offset: 10 desc: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. + @"DATA_IS_INVALID_" = 0, // desc: Data is invalid. + @"DATA_IS_VALID_" = 1, // desc: Data is valid. + }, + PKT_RDY: u1, // bit offset: 11 desc: The PKT_LNGTH field is valid and the packet is ready for reading. + // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15065,10 +19059,11 @@ pub const USB = extern struct { }); // byte offset: 256 OTG Interrupt Status pub const INTST = mmio(Address + 0x00000100, 32, packed struct { - TMR: bool, // bit offset: 0 desc: Timer time-out. - REMOVE_PU: bool, // bit offset: 1 desc: Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. - HNP_FAILURE: bool, // bit offset: 2 desc: HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. - HNP_SUCCESS: bool, // bit offset: 3 desc: HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. + TMR: u1, // bit offset: 0 desc: Timer time-out. + REMOVE_PU: u1, // bit offset: 1 desc: Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. + HNP_FAILURE: u1, // bit offset: 2 desc: HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. + HNP_SUCCESS: u1, // bit offset: 3 desc: HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -15100,10 +19095,11 @@ pub const USB = extern struct { }); // byte offset: 260 OTG Interrupt Enable pub const INTEN = mmio(Address + 0x00000104, 32, packed struct { - TMR_EN: bool, // bit offset: 0 desc: 1 = enable the corresponding bit in the IntSt register. - REMOVE_PU_EN: bool, // bit offset: 1 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_FAILURE_EN: bool, // bit offset: 2 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_SUCCES_EN: bool, // bit offset: 3 desc: 1 = enable the corresponding bit in the IntSt register. + TMR_EN: u1, // bit offset: 0 desc: 1 = enable the corresponding bit in the IntSt register. + REMOVE_PU_EN: u1, // bit offset: 1 desc: 1 = enable the corresponding bit in the IntSt register. + HNP_FAILURE_EN: u1, // bit offset: 2 desc: 1 = enable the corresponding bit in the IntSt register. + HNP_SUCCES_EN: u1, // bit offset: 3 desc: 1 = enable the corresponding bit in the IntSt register. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -15135,10 +19131,11 @@ pub const USB = extern struct { }); // byte offset: 264 OTG Interrupt Set pub const INTSET = mmio(Address + 0x00000108, 32, packed struct { - TMR_SET: bool, // bit offset: 0 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - REMOVE_PU_SET: bool, // bit offset: 1 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_FAILURE_SET: bool, // bit offset: 2 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_SUCCES_SET: bool, // bit offset: 3 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + TMR_SET: u1, // bit offset: 0 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + REMOVE_PU_SET: u1, // bit offset: 1 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_FAILURE_SET: u1, // bit offset: 2 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_SUCCES_SET: u1, // bit offset: 3 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -15170,10 +19167,11 @@ pub const USB = extern struct { }); // byte offset: 268 OTG Interrupt Clear pub const INTCLR = mmio(Address + 0x0000010c, 32, packed struct { - TMR_CLR: bool, // bit offset: 0 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - REMOVE_PU_CLR: bool, // bit offset: 1 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_FAILURE_CLR: bool, // bit offset: 2 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_SUCCES_CLR: bool, // bit offset: 3 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + TMR_CLR: u1, // bit offset: 0 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + REMOVE_PU_CLR: u1, // bit offset: 1 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_FAILURE_CLR: u1, // bit offset: 2 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_SUCCES_CLR: u1, // bit offset: 3 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -15207,13 +19205,15 @@ pub const USB = extern struct { pub const STCTRL = mmio(Address + 0x00000110, 32, packed struct { PORT_FUNC: u2, // bit offset: 0 desc: Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. TMR_SCALE: u2, // bit offset: 2 desc: Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved - TMR_MODE: bool, // bit offset: 4 desc: Timer mode selection. 0: monoshot 1: free running - TMR_EN: bool, // bit offset: 5 desc: Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. - TMR_RST: bool, // bit offset: 6 desc: Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. + TMR_MODE: u1, // bit offset: 4 desc: Timer mode selection. 0: monoshot 1: free running + TMR_EN: u1, // bit offset: 5 desc: Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. + TMR_RST: u1, // bit offset: 6 desc: Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. + // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - B_HNP_TRACK: bool, // bit offset: 8 desc: Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - A_HNP_TRACK: bool, // bit offset: 9 desc: Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - PU_REMOVED: bool, // bit offset: 10 desc: When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + B_HNP_TRACK: u1, // bit offset: 8 desc: Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + A_HNP_TRACK: u1, // bit offset: 9 desc: Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + PU_REMOVED: u1, // bit offset: 10 desc: When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. + // RESERVED: u5, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, @@ -15224,6 +19224,7 @@ pub const USB = extern struct { // byte offset: 276 OTG Timer pub const TMR = mmio(Address + 0x00000114, 32, packed struct { TIMEOUT_CNT: u16, // bit offset: 0 desc: The TMR interrupt is set when TMR_CNT reaches this value. + // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15243,16 +19244,17 @@ pub const USB = extern struct { }); // byte offset: 512 USB Device Interrupt Status pub const DEVINTST = mmio(Address + 0x00000200, 32, packed struct { - FRAME: bool, // bit offset: 0 desc: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. - EP_FAST: bool, // bit offset: 1 desc: Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. - EP_SLOW: bool, // bit offset: 2 desc: Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. - DEV_STAT: bool, // bit offset: 3 desc: Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. - CCEMPTY: bool, // bit offset: 4 desc: The command code register (USBCmdCode) is empty (New command can be written). - CDFULL: bool, // bit offset: 5 desc: Command data register (USBCmdData) is full (Data can be read now). - RxENDPKT: bool, // bit offset: 6 desc: The current packet in the endpoint buffer is transferred to the CPU. - TxENDPKT: bool, // bit offset: 7 desc: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). - EP_RLZED: bool, // bit offset: 8 desc: Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. - ERR_INT: bool, // bit offset: 9 desc: Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 + FRAME: u1, // bit offset: 0 desc: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. + EP_FAST: u1, // bit offset: 1 desc: Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. + EP_SLOW: u1, // bit offset: 2 desc: Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. + DEV_STAT: u1, // bit offset: 3 desc: Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. + CCEMPTY: u1, // bit offset: 4 desc: The command code register (USBCmdCode) is empty (New command can be written). + CDFULL: u1, // bit offset: 5 desc: Command data register (USBCmdData) is full (Data can be read now). + RxENDPKT: u1, // bit offset: 6 desc: The current packet in the endpoint buffer is transferred to the CPU. + TxENDPKT: u1, // bit offset: 7 desc: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). + EP_RLZED: u1, // bit offset: 8 desc: Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. + ERR_INT: u1, // bit offset: 9 desc: Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 + // RESERVED: u22, // bit offset: 10 desc: Reserved. The value read from a reserved bit is not defined. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15278,16 +19280,17 @@ pub const USB = extern struct { }); // byte offset: 516 USB Device Interrupt Enable pub const DEVINTEN = mmio(Address + 0x00000204, 32, packed struct { - FRAMEEN: bool, // bit offset: 0 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_FASTEN: bool, // bit offset: 1 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_SLOWEN: bool, // bit offset: 2 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - DEV_STATEN: bool, // bit offset: 3 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CCEMPTYEN: bool, // bit offset: 4 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CDFULLEN: bool, // bit offset: 5 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - RxENDPKTEN: bool, // bit offset: 6 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - TxENDPKTEN: bool, // bit offset: 7 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_RLZEDEN: bool, // bit offset: 8 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - ERR_INTEN: bool, // bit offset: 9 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + FRAMEEN: u1, // bit offset: 0 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_FASTEN: u1, // bit offset: 1 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_SLOWEN: u1, // bit offset: 2 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + DEV_STATEN: u1, // bit offset: 3 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CCEMPTYEN: u1, // bit offset: 4 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CDFULLEN: u1, // bit offset: 5 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + RxENDPKTEN: u1, // bit offset: 6 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + TxENDPKTEN: u1, // bit offset: 7 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_RLZEDEN: u1, // bit offset: 8 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + ERR_INTEN: u1, // bit offset: 9 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + // RESERVED: u22, // bit offset: 10 desc: Reserved padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15313,16 +19316,17 @@ pub const USB = extern struct { }); // byte offset: 520 USB Device Interrupt Clear pub const DEVINTCLR = mmio(Address + 0x00000208, 32, packed struct { - FRAMECLR: bool, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_FASTCLR: bool, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_SLOWCLR: bool, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - DEV_STATCLR: bool, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CCEMPTYCLR: bool, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CDFULLCLR: bool, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - RxENDPKTCLR: bool, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - TxENDPKTCLR: bool, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_RLZEDCLR: bool, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - ERR_INTCLR: bool, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + FRAMECLR: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_FASTCLR: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_SLOWCLR: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + DEV_STATCLR: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + CCEMPTYCLR: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + CDFULLCLR: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + RxENDPKTCLR: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + TxENDPKTCLR: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + EP_RLZEDCLR: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + ERR_INTCLR: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. + // RESERVED: u22, // bit offset: 10 desc: Reserved padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15348,16 +19352,17 @@ pub const USB = extern struct { }); // byte offset: 524 USB Device Interrupt Set pub const DEVINTSET = mmio(Address + 0x0000020c, 32, packed struct { - FRAMESET: bool, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_FASTSET: bool, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_SLOWSET: bool, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - DEV_STATSET: bool, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CCEMPTYSET: bool, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CDFULLSET: bool, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - RxENDPKTSET: bool, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - TxENDPKTSET: bool, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_RLZEDSET: bool, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - ERR_INTSET: bool, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + FRAMESET: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_FASTSET: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_SLOWSET: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + DEV_STATSET: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + CCEMPTYSET: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + CDFULLSET: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + RxENDPKTSET: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + TxENDPKTSET: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + EP_RLZEDSET: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + ERR_INTSET: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. + // RESERVED: u22, // bit offset: 10 desc: Reserved padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15383,6 +19388,7 @@ pub const USB = extern struct { }); // byte offset: 528 USB Command Code pub const CMDCODE = mmio(Address + 0x00000210, 32, packed struct { + // RESERVED: u8, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -15391,8 +19397,14 @@ pub const USB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CMD_PHASE: u8, // bit offset: 8 desc: The command phase: + CMD_PHASE: enum(u8) { // bit offset: 8 desc: The command phase: + @"READ" = 2, // desc: Read + @"WRITE" = 1, // desc: Write + @"COMMAND" = 5, // desc: Command + _, // non-exhaustive + }, CMD_CODE_WDATA: u8, // bit offset: 16 desc: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). + // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -15405,6 +19417,7 @@ pub const USB = extern struct { // byte offset: 532 USB Command Data pub const CMDDATA = mmio(Address + 0x00000214, 32, packed struct { CMD_RDATA: u8, // bit offset: 0 desc: Command Read Data. + // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -15441,6 +19454,7 @@ pub const USB = extern struct { // byte offset: 548 USB Transmit Packet Length pub const TXPLEN = mmio(Address + 0x00000224, 32, packed struct { PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15466,9 +19480,16 @@ pub const USB = extern struct { }); // byte offset: 552 USB Control pub const CTRL = mmio(Address + 0x00000228, 32, packed struct { - RD_EN: bool, // bit offset: 0 desc: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. - WR_EN: bool, // bit offset: 1 desc: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. + RD_EN: enum(u1) { // bit offset: 0 desc: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, + WR_EN: enum(u1) { // bit offset: 1 desc: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, LOG_ENDPOINT: u4, // bit offset: 2 desc: Logical Endpoint number. + // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -15498,8 +19519,15 @@ pub const USB = extern struct { }); // byte offset: 556 USB Device Interrupt Priority pub const DEVINTPRI = mmio(Address + 0x0000022c, 32, packed struct { - FRAME: bool, // bit offset: 0 desc: Frame interrupt routing - EP_FAST: bool, // bit offset: 1 desc: Fast endpoint interrupt routing + FRAME: enum(u1) { // bit offset: 0 desc: Frame interrupt routing + @"LP" = 0, // desc: FRAME interrupt is routed to USB_INT_REQ_LP. + @"HP" = 1, // desc: FRAME interrupt is routed to USB_INT_REQ_HP. + }, + EP_FAST: enum(u1) { // bit offset: 1 desc: Fast endpoint interrupt routing + @"LP" = 0, // desc: EP_FAST interrupt is routed to USB_INT_REQ_LP. + @"HP" = 1, // desc: EP_FAST interrupt is routed to USB_INT_REQ_HP. + }, + // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -15533,217 +19561,218 @@ pub const USB = extern struct { }); // byte offset: 560 USB Endpoint Interrupt Status pub const EPINTST = mmio(Address + 0x00000230, 32, packed struct { - EPST0: bool, // bit offset: 0 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST1: bool, // bit offset: 1 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST2: bool, // bit offset: 2 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST3: bool, // bit offset: 3 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST4: bool, // bit offset: 4 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST5: bool, // bit offset: 5 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST6: bool, // bit offset: 6 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST7: bool, // bit offset: 7 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST8: bool, // bit offset: 8 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST9: bool, // bit offset: 9 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST10: bool, // bit offset: 10 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST11: bool, // bit offset: 11 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST12: bool, // bit offset: 12 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST13: bool, // bit offset: 13 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST14: bool, // bit offset: 14 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST15: bool, // bit offset: 15 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST16: bool, // bit offset: 16 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST17: bool, // bit offset: 17 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST18: bool, // bit offset: 18 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST19: bool, // bit offset: 19 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST20: bool, // bit offset: 20 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST21: bool, // bit offset: 21 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST22: bool, // bit offset: 22 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST23: bool, // bit offset: 23 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST24: bool, // bit offset: 24 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST25: bool, // bit offset: 25 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST26: bool, // bit offset: 26 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST27: bool, // bit offset: 27 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST28: bool, // bit offset: 28 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST29: bool, // bit offset: 29 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST30: bool, // bit offset: 30 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST31: bool, // bit offset: 31 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST0: u1, // bit offset: 0 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST1: u1, // bit offset: 1 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST2: u1, // bit offset: 2 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST3: u1, // bit offset: 3 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST4: u1, // bit offset: 4 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST5: u1, // bit offset: 5 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST6: u1, // bit offset: 6 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST7: u1, // bit offset: 7 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST8: u1, // bit offset: 8 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST9: u1, // bit offset: 9 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST10: u1, // bit offset: 10 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST11: u1, // bit offset: 11 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST12: u1, // bit offset: 12 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST13: u1, // bit offset: 13 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST14: u1, // bit offset: 14 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST15: u1, // bit offset: 15 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST16: u1, // bit offset: 16 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST17: u1, // bit offset: 17 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST18: u1, // bit offset: 18 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST19: u1, // bit offset: 19 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST20: u1, // bit offset: 20 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST21: u1, // bit offset: 21 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST22: u1, // bit offset: 22 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST23: u1, // bit offset: 23 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST24: u1, // bit offset: 24 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST25: u1, // bit offset: 25 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST26: u1, // bit offset: 26 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST27: u1, // bit offset: 27 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST28: u1, // bit offset: 28 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST29: u1, // bit offset: 29 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST30: u1, // bit offset: 30 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. + EPST31: u1, // bit offset: 31 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. }); // byte offset: 564 USB Endpoint Interrupt Enable pub const EPINTEN = mmio(Address + 0x00000234, 32, packed struct { - EPEN0: bool, // bit offset: 0 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN1: bool, // bit offset: 1 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN2: bool, // bit offset: 2 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN3: bool, // bit offset: 3 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN4: bool, // bit offset: 4 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN5: bool, // bit offset: 5 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN6: bool, // bit offset: 6 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN7: bool, // bit offset: 7 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN8: bool, // bit offset: 8 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN9: bool, // bit offset: 9 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN10: bool, // bit offset: 10 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN11: bool, // bit offset: 11 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN12: bool, // bit offset: 12 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN13: bool, // bit offset: 13 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN14: bool, // bit offset: 14 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN15: bool, // bit offset: 15 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN16: bool, // bit offset: 16 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN17: bool, // bit offset: 17 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN18: bool, // bit offset: 18 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN19: bool, // bit offset: 19 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN20: bool, // bit offset: 20 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN21: bool, // bit offset: 21 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN22: bool, // bit offset: 22 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN23: bool, // bit offset: 23 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN24: bool, // bit offset: 24 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN25: bool, // bit offset: 25 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN26: bool, // bit offset: 26 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN27: bool, // bit offset: 27 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN28: bool, // bit offset: 28 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN29: bool, // bit offset: 29 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN30: bool, // bit offset: 30 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN31: bool, // bit offset: 31 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN0: u1, // bit offset: 0 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN1: u1, // bit offset: 1 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN2: u1, // bit offset: 2 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN3: u1, // bit offset: 3 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN4: u1, // bit offset: 4 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN5: u1, // bit offset: 5 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN6: u1, // bit offset: 6 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN7: u1, // bit offset: 7 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN8: u1, // bit offset: 8 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN9: u1, // bit offset: 9 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN10: u1, // bit offset: 10 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN11: u1, // bit offset: 11 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN12: u1, // bit offset: 12 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN13: u1, // bit offset: 13 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN14: u1, // bit offset: 14 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN15: u1, // bit offset: 15 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN16: u1, // bit offset: 16 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN17: u1, // bit offset: 17 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN18: u1, // bit offset: 18 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN19: u1, // bit offset: 19 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN20: u1, // bit offset: 20 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN21: u1, // bit offset: 21 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN22: u1, // bit offset: 22 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN23: u1, // bit offset: 23 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN24: u1, // bit offset: 24 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN25: u1, // bit offset: 25 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN26: u1, // bit offset: 26 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN27: u1, // bit offset: 27 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN28: u1, // bit offset: 28 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN29: u1, // bit offset: 29 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN30: u1, // bit offset: 30 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN31: u1, // bit offset: 31 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. }); // byte offset: 568 USB Endpoint Interrupt Clear pub const EPINTCLR = mmio(Address + 0x00000238, 32, packed struct { - EPCLR0: bool, // bit offset: 0 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR1: bool, // bit offset: 1 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR2: bool, // bit offset: 2 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR3: bool, // bit offset: 3 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR4: bool, // bit offset: 4 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR5: bool, // bit offset: 5 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR6: bool, // bit offset: 6 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR7: bool, // bit offset: 7 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR8: bool, // bit offset: 8 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR9: bool, // bit offset: 9 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR10: bool, // bit offset: 10 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR11: bool, // bit offset: 11 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR12: bool, // bit offset: 12 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR13: bool, // bit offset: 13 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR14: bool, // bit offset: 14 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR15: bool, // bit offset: 15 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR16: bool, // bit offset: 16 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR17: bool, // bit offset: 17 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR18: bool, // bit offset: 18 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR19: bool, // bit offset: 19 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR20: bool, // bit offset: 20 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR21: bool, // bit offset: 21 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR22: bool, // bit offset: 22 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR23: bool, // bit offset: 23 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR24: bool, // bit offset: 24 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR25: bool, // bit offset: 25 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR26: bool, // bit offset: 26 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR27: bool, // bit offset: 27 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR28: bool, // bit offset: 28 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR29: bool, // bit offset: 29 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR30: bool, // bit offset: 30 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR31: bool, // bit offset: 31 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. }); // byte offset: 572 USB Endpoint Interrupt Set pub const EPINTSET = mmio(Address + 0x0000023c, 32, packed struct { - EPSET0: bool, // bit offset: 0 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET1: bool, // bit offset: 1 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET2: bool, // bit offset: 2 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET3: bool, // bit offset: 3 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET4: bool, // bit offset: 4 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET5: bool, // bit offset: 5 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET6: bool, // bit offset: 6 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET7: bool, // bit offset: 7 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET8: bool, // bit offset: 8 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET9: bool, // bit offset: 9 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET10: bool, // bit offset: 10 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET11: bool, // bit offset: 11 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET12: bool, // bit offset: 12 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET13: bool, // bit offset: 13 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET14: bool, // bit offset: 14 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET15: bool, // bit offset: 15 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET16: bool, // bit offset: 16 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET17: bool, // bit offset: 17 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET18: bool, // bit offset: 18 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET19: bool, // bit offset: 19 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET20: bool, // bit offset: 20 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET21: bool, // bit offset: 21 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET22: bool, // bit offset: 22 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET23: bool, // bit offset: 23 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET24: bool, // bit offset: 24 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET25: bool, // bit offset: 25 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET26: bool, // bit offset: 26 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET27: bool, // bit offset: 27 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET28: bool, // bit offset: 28 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET29: bool, // bit offset: 29 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET30: bool, // bit offset: 30 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET31: bool, // bit offset: 31 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. }); // byte offset: 576 USB Endpoint Priority pub const EPINTPRI = mmio(Address + 0x00000240, 32, packed struct { - EPPRI0: bool, // bit offset: 0 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI1: bool, // bit offset: 1 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI2: bool, // bit offset: 2 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI3: bool, // bit offset: 3 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI4: bool, // bit offset: 4 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI5: bool, // bit offset: 5 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI6: bool, // bit offset: 6 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI7: bool, // bit offset: 7 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI8: bool, // bit offset: 8 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI9: bool, // bit offset: 9 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI10: bool, // bit offset: 10 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI11: bool, // bit offset: 11 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI12: bool, // bit offset: 12 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI13: bool, // bit offset: 13 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI14: bool, // bit offset: 14 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI15: bool, // bit offset: 15 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI16: bool, // bit offset: 16 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI17: bool, // bit offset: 17 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI18: bool, // bit offset: 18 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI19: bool, // bit offset: 19 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI20: bool, // bit offset: 20 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI21: bool, // bit offset: 21 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI22: bool, // bit offset: 22 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI23: bool, // bit offset: 23 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI24: bool, // bit offset: 24 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI25: bool, // bit offset: 25 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI26: bool, // bit offset: 26 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI27: bool, // bit offset: 27 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI28: bool, // bit offset: 28 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI29: bool, // bit offset: 29 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI30: bool, // bit offset: 30 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI31: bool, // bit offset: 31 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI0: u1, // bit offset: 0 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI1: u1, // bit offset: 1 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI2: u1, // bit offset: 2 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI3: u1, // bit offset: 3 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI4: u1, // bit offset: 4 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI5: u1, // bit offset: 5 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI6: u1, // bit offset: 6 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI7: u1, // bit offset: 7 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI8: u1, // bit offset: 8 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI9: u1, // bit offset: 9 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI10: u1, // bit offset: 10 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI11: u1, // bit offset: 11 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI12: u1, // bit offset: 12 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI13: u1, // bit offset: 13 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI14: u1, // bit offset: 14 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI15: u1, // bit offset: 15 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI16: u1, // bit offset: 16 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI17: u1, // bit offset: 17 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI18: u1, // bit offset: 18 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI19: u1, // bit offset: 19 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI20: u1, // bit offset: 20 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI21: u1, // bit offset: 21 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI22: u1, // bit offset: 22 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI23: u1, // bit offset: 23 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI24: u1, // bit offset: 24 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI25: u1, // bit offset: 25 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI26: u1, // bit offset: 26 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI27: u1, // bit offset: 27 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI28: u1, // bit offset: 28 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI29: u1, // bit offset: 29 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI30: u1, // bit offset: 30 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI31: u1, // bit offset: 31 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt }); // byte offset: 580 USB Realize Endpoint pub const REEP = mmio(Address + 0x00000244, 32, packed struct { - EPR0: bool, // bit offset: 0 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR1: bool, // bit offset: 1 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR2: bool, // bit offset: 2 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR3: bool, // bit offset: 3 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR4: bool, // bit offset: 4 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR5: bool, // bit offset: 5 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR6: bool, // bit offset: 6 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR7: bool, // bit offset: 7 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR8: bool, // bit offset: 8 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR9: bool, // bit offset: 9 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR10: bool, // bit offset: 10 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR11: bool, // bit offset: 11 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR12: bool, // bit offset: 12 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR13: bool, // bit offset: 13 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR14: bool, // bit offset: 14 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR15: bool, // bit offset: 15 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR16: bool, // bit offset: 16 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR17: bool, // bit offset: 17 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR18: bool, // bit offset: 18 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR19: bool, // bit offset: 19 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR20: bool, // bit offset: 20 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR21: bool, // bit offset: 21 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR22: bool, // bit offset: 22 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR23: bool, // bit offset: 23 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR24: bool, // bit offset: 24 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR25: bool, // bit offset: 25 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR26: bool, // bit offset: 26 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR27: bool, // bit offset: 27 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR28: bool, // bit offset: 28 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR29: bool, // bit offset: 29 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR30: bool, // bit offset: 30 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR31: bool, // bit offset: 31 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR0: u1, // bit offset: 0 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR1: u1, // bit offset: 1 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR2: u1, // bit offset: 2 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR3: u1, // bit offset: 3 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR4: u1, // bit offset: 4 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR5: u1, // bit offset: 5 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR6: u1, // bit offset: 6 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR7: u1, // bit offset: 7 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR8: u1, // bit offset: 8 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR9: u1, // bit offset: 9 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR10: u1, // bit offset: 10 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR11: u1, // bit offset: 11 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR12: u1, // bit offset: 12 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR13: u1, // bit offset: 13 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR14: u1, // bit offset: 14 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR15: u1, // bit offset: 15 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR16: u1, // bit offset: 16 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR17: u1, // bit offset: 17 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR18: u1, // bit offset: 18 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR19: u1, // bit offset: 19 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR20: u1, // bit offset: 20 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR21: u1, // bit offset: 21 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR22: u1, // bit offset: 22 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR23: u1, // bit offset: 23 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR24: u1, // bit offset: 24 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR25: u1, // bit offset: 25 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR26: u1, // bit offset: 26 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR27: u1, // bit offset: 27 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR28: u1, // bit offset: 28 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR29: u1, // bit offset: 29 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR30: u1, // bit offset: 30 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR31: u1, // bit offset: 31 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. }); // byte offset: 584 USB Endpoint Index pub const EPIND = mmio(Address + 0x00000248, 32, packed struct { PHY_EP: u5, // bit offset: 0 desc: Physical endpoint number (0-31) + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -15775,6 +19804,7 @@ pub const USB = extern struct { // byte offset: 588 USB MaxPacketSize pub const MAXPSIZE = mmio(Address + 0x0000024c, 32, packed struct { MPS: u10, // bit offset: 0 desc: The maximum packet size value. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -15800,111 +19830,112 @@ pub const USB = extern struct { }); // byte offset: 592 USB DMA Request Status pub const DMARST = mmio(Address + 0x00000250, 32, packed struct { - EPRST0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). - EPRST1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). - EPRST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). + EPRST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). + EPRST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. + EPRST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. }); // byte offset: 596 USB DMA Request Clear pub const DMARCLR = mmio(Address + 0x00000254, 32, packed struct { - EPRCLR0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRCLR1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRCLR2: bool, // bit offset: 2 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR3: bool, // bit offset: 3 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR4: bool, // bit offset: 4 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR5: bool, // bit offset: 5 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR6: bool, // bit offset: 6 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR7: bool, // bit offset: 7 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR8: bool, // bit offset: 8 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR9: bool, // bit offset: 9 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR10: bool, // bit offset: 10 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR11: bool, // bit offset: 11 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR12: bool, // bit offset: 12 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR13: bool, // bit offset: 13 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR14: bool, // bit offset: 14 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR15: bool, // bit offset: 15 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR16: bool, // bit offset: 16 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR17: bool, // bit offset: 17 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR18: bool, // bit offset: 18 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR19: bool, // bit offset: 19 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR20: bool, // bit offset: 20 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR21: bool, // bit offset: 21 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR22: bool, // bit offset: 22 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR23: bool, // bit offset: 23 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR24: bool, // bit offset: 24 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR25: bool, // bit offset: 25 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR26: bool, // bit offset: 26 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR27: bool, // bit offset: 27 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR28: bool, // bit offset: 28 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR29: bool, // bit offset: 29 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR30: bool, // bit offset: 30 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR31: bool, // bit offset: 31 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). + EPRCLR1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). + EPRCLR2: u1, // bit offset: 2 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR3: u1, // bit offset: 3 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR4: u1, // bit offset: 4 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR5: u1, // bit offset: 5 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR6: u1, // bit offset: 6 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR7: u1, // bit offset: 7 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR8: u1, // bit offset: 8 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR9: u1, // bit offset: 9 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR10: u1, // bit offset: 10 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR11: u1, // bit offset: 11 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR12: u1, // bit offset: 12 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR13: u1, // bit offset: 13 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR14: u1, // bit offset: 14 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR15: u1, // bit offset: 15 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR16: u1, // bit offset: 16 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR17: u1, // bit offset: 17 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR18: u1, // bit offset: 18 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR19: u1, // bit offset: 19 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR20: u1, // bit offset: 20 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR21: u1, // bit offset: 21 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR22: u1, // bit offset: 22 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR23: u1, // bit offset: 23 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR24: u1, // bit offset: 24 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR25: u1, // bit offset: 25 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR26: u1, // bit offset: 26 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR27: u1, // bit offset: 27 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR28: u1, // bit offset: 28 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR29: u1, // bit offset: 29 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR30: u1, // bit offset: 30 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. + EPRCLR31: u1, // bit offset: 31 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. }); // byte offset: 600 USB DMA Request Set pub const DMARSET = mmio(Address + 0x00000258, 32, packed struct { - EPRSET0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRSET1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRSET2: bool, // bit offset: 2 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET3: bool, // bit offset: 3 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET4: bool, // bit offset: 4 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET5: bool, // bit offset: 5 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET6: bool, // bit offset: 6 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET7: bool, // bit offset: 7 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET8: bool, // bit offset: 8 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET9: bool, // bit offset: 9 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET10: bool, // bit offset: 10 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET11: bool, // bit offset: 11 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET12: bool, // bit offset: 12 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET13: bool, // bit offset: 13 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET14: bool, // bit offset: 14 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET15: bool, // bit offset: 15 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET16: bool, // bit offset: 16 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET17: bool, // bit offset: 17 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET18: bool, // bit offset: 18 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET19: bool, // bit offset: 19 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET20: bool, // bit offset: 20 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET21: bool, // bit offset: 21 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET22: bool, // bit offset: 22 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET23: bool, // bit offset: 23 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET24: bool, // bit offset: 24 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET25: bool, // bit offset: 25 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET26: bool, // bit offset: 26 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET27: bool, // bit offset: 27 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET28: bool, // bit offset: 28 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET29: bool, // bit offset: 29 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET30: bool, // bit offset: 30 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET31: bool, // bit offset: 31 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). + EPRSET1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). + EPRSET2: u1, // bit offset: 2 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET3: u1, // bit offset: 3 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET4: u1, // bit offset: 4 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET5: u1, // bit offset: 5 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET6: u1, // bit offset: 6 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET7: u1, // bit offset: 7 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET8: u1, // bit offset: 8 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET9: u1, // bit offset: 9 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET10: u1, // bit offset: 10 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET11: u1, // bit offset: 11 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET12: u1, // bit offset: 12 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET13: u1, // bit offset: 13 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET14: u1, // bit offset: 14 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET15: u1, // bit offset: 15 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET16: u1, // bit offset: 16 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET17: u1, // bit offset: 17 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET18: u1, // bit offset: 18 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET19: u1, // bit offset: 19 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET20: u1, // bit offset: 20 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET21: u1, // bit offset: 21 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET22: u1, // bit offset: 22 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET23: u1, // bit offset: 23 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET24: u1, // bit offset: 24 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET25: u1, // bit offset: 25 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET26: u1, // bit offset: 26 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET27: u1, // bit offset: 27 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET28: u1, // bit offset: 28 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET29: u1, // bit offset: 29 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET30: u1, // bit offset: 30 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. + EPRSET31: u1, // bit offset: 31 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. }); // byte offset: 640 USB UDCA Head pub const UDCAH = mmio(Address + 0x00000280, 32, packed struct { + // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries. reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -15916,85 +19947,95 @@ pub const USB = extern struct { }); // byte offset: 644 USB Endpoint DMA Status pub const EPDMAST = mmio(Address + 0x00000284, 32, packed struct { - EP_DMA_ST0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). - EP_DMA_ST1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). - EP_DMA_ST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). + EP_DMA_ST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). + EP_DMA_ST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. }); // byte offset: 648 USB Endpoint DMA Enable pub const EPDMAEN = mmio(Address + 0x00000288, 32, packed struct { - EP_DMA_EN0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). - EP_DMA_EN1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). + EP_DMA_EN0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). + EP_DMA_EN1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). EP_DMA_EN: u30, // bit offset: 2 desc: Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx. }); // byte offset: 652 USB Endpoint DMA Disable pub const EPDMADIS = mmio(Address + 0x0000028c, 32, packed struct { - EP_DMA_DIS0: bool, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). - EP_DMA_DIS1: bool, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). - EP_DMA_DIS2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). + EP_DMA_DIS1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). + EP_DMA_DIS2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. + EP_DMA_DIS31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. }); // byte offset: 656 USB DMA Interrupt Status pub const DMAINTST = mmio(Address + 0x00000290, 32, packed struct { - EOT: bool, // bit offset: 0 desc: End of Transfer Interrupt bit. - NDDR: bool, // bit offset: 1 desc: New DD Request Interrupt bit. - ERR: bool, // bit offset: 2 desc: System Error Interrupt bit. + EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt bit. + @"ALL_BITS_IN_THE_USBE" = 0, // desc: All bits in the USBEoTIntSt register are 0. + @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBEoTIntSt is set. + }, + NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt bit. + @"ALL_BITS_IN_THE_USBN" = 0, // desc: All bits in the USBNDDRIntSt register are 0. + @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBNDDRIntSt is set. + }, + ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt bit. + @"ALL_BITS_IN_THE_USBS" = 0, // desc: All bits in the USBSysErrIntSt register are 0. + @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBSysErrIntSt is set. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from a reserved bit is not defined. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -16027,9 +20068,19 @@ pub const USB = extern struct { }); // byte offset: 660 USB DMA Interrupt Enable pub const DMAINTEN = mmio(Address + 0x00000294, 32, packed struct { - EOT: bool, // bit offset: 0 desc: End of Transfer Interrupt enable bit. - NDDR: bool, // bit offset: 1 desc: New DD Request Interrupt enable bit. - ERR: bool, // bit offset: 2 desc: System Error Interrupt enable bit. + EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt enable bit. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, + NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt enable bit. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, + ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt enable bit. + @"DISABLED_" = 0, // desc: Disabled. + @"ENABLED_" = 1, // desc: Enabled. + }, + // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -16062,318 +20113,318 @@ pub const USB = extern struct { }); // byte offset: 672 USB End of Transfer Interrupt Status pub const EOTINTST = mmio(Address + 0x000002a0, 32, packed struct { - EPTXINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. + EPTXINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. }); // byte offset: 676 USB End of Transfer Interrupt Clear pub const EOTINTCLR = mmio(Address + 0x000002a4, 32, packed struct { - EPTXINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. }); // byte offset: 680 USB End of Transfer Interrupt Set pub const EOTINTSET = mmio(Address + 0x000002a8, 32, packed struct { - EPTXINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. + EPTXINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. }); // byte offset: 684 USB New DD Request Interrupt Status pub const NDDRINTST = mmio(Address + 0x000002ac, 32, packed struct { - EPNDDINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. + EPNDDINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. }); // byte offset: 688 USB New DD Request Interrupt Clear pub const NDDRINTCLR = mmio(Address + 0x000002b0, 32, packed struct { - EPNDDINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. }); // byte offset: 692 USB New DD Request Interrupt Set pub const NDDRINTSET = mmio(Address + 0x000002b4, 32, packed struct { - EPNDDINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. }); // byte offset: 696 USB System Error Interrupt Status pub const SYSERRINTST = mmio(Address + 0x000002b8, 32, packed struct { - EPERRINTST0: bool, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST1: bool, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST2: bool, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST3: bool, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST4: bool, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST5: bool, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST6: bool, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST7: bool, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST8: bool, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST9: bool, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST10: bool, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST11: bool, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST12: bool, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST13: bool, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST14: bool, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST15: bool, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST16: bool, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST17: bool, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST18: bool, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST19: bool, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST20: bool, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST21: bool, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST22: bool, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST23: bool, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST24: bool, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST25: bool, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST26: bool, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST27: bool, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST28: bool, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST29: bool, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST30: bool, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST31: bool, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. + EPERRINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. }); // byte offset: 700 USB System Error Interrupt Clear pub const SYSERRINTCLR = mmio(Address + 0x000002bc, 32, packed struct { - EPERRINTCLR0: bool, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR1: bool, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR2: bool, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR3: bool, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR4: bool, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR5: bool, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR6: bool, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR7: bool, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR8: bool, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR9: bool, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR10: bool, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR11: bool, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR12: bool, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR13: bool, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR14: bool, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR15: bool, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR16: bool, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR17: bool, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR18: bool, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR19: bool, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR20: bool, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR21: bool, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR22: bool, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR23: bool, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR24: bool, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR25: bool, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR26: bool, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR27: bool, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR28: bool, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR29: bool, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR30: bool, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR31: bool, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. }); // byte offset: 704 USB System Error Interrupt Set pub const SYSERRINTSET = mmio(Address + 0x000002c0, 32, packed struct { - EPERRINTSET0: bool, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET1: bool, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET2: bool, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET3: bool, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET4: bool, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET5: bool, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET6: bool, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET7: bool, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET8: bool, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET9: bool, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET10: bool, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET11: bool, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET12: bool, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET13: bool, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET14: bool, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET15: bool, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET16: bool, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET17: bool, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET18: bool, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET19: bool, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET20: bool, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET21: bool, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET22: bool, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET23: bool, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET24: bool, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET25: bool, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET26: bool, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET27: bool, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET28: bool, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET29: bool, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET30: bool, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET31: bool, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. }); // byte offset: 768 I2C Receive pub const I2C_RX = mmio(Address + 0x00000300, 32, packed struct { @@ -16406,8 +20457,9 @@ pub const USB = extern struct { // byte offset: 768 I2C Transmit pub const I2C_WO = mmio(Address + 0x00000300, 32, packed struct { TXDATA: u8, // bit offset: 0 desc: Transmit data. - START: bool, // bit offset: 8 desc: When 1, issue a START condition before transmitting this byte. - STOP: bool, // bit offset: 9 desc: When 1, issue a STOP condition after transmitting this byte. + START: u1, // bit offset: 8 desc: When 1, issue a START condition before transmitting this byte. + STOP: u1, // bit offset: 9 desc: When 1, issue a STOP condition after transmitting this byte. + // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -16433,18 +20485,46 @@ pub const USB = extern struct { }); // byte offset: 772 I2C Status pub const I2C_STS = mmio(Address + 0x00000304, 32, packed struct { - TDI: bool, // bit offset: 0 desc: Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. - AFI: bool, // bit offset: 1 desc: Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. - NAI: bool, // bit offset: 2 desc: No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. - DRMI: bool, // bit offset: 3 desc: Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. - DRSI: bool, // bit offset: 4 desc: Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. - Active: bool, // bit offset: 5 desc: Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. - SCL: bool, // bit offset: 6 desc: The current value of the SCL signal. - SDA: bool, // bit offset: 7 desc: The current value of the SDA signal. - RFF: bool, // bit offset: 8 desc: Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. - RFE: bool, // bit offset: 9 desc: Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. - TFF: bool, // bit offset: 10 desc: Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. - TFE: bool, // bit offset: 11 desc: Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. + TDI: enum(u1) { // bit offset: 0 desc: Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. + @"NOT_COMPLETE" = 0, // desc: Transaction has not completed. + @"COMPLETE" = 1, // desc: Transaction completed. + }, + AFI: enum(u1) { // bit offset: 1 desc: Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. + @"NO_ARBITRATION_FAILU" = 0, // desc: No arbitration failure on last transmission. + @"ARBITRATION_FAILURE_" = 1, // desc: Arbitration failure occurred on last transmission. + }, + NAI: enum(u1) { // bit offset: 2 desc: No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. + @"ACKNOWLEDGE_RCVD" = 0, // desc: Last transmission received an acknowledge. + @"NO_ACKNOWLEDGE_RCVD" = 1, // desc: Last transmission did not receive an acknowledge. + }, + DRMI: enum(u1) { // bit offset: 3 desc: Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. + @"BUSY" = 0, // desc: Master transmitter does not need data. + @"NEED_DATA" = 1, // desc: Master transmitter needs data. + }, + DRSI: enum(u1) { // bit offset: 4 desc: Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. + @"BUSY" = 0, // desc: Slave transmitter does not need data. + @"NEED_DATA" = 1, // desc: Slave transmitter needs data. + }, + Active: u1, // bit offset: 5 desc: Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. + SCL: u1, // bit offset: 6 desc: The current value of the SCL signal. + SDA: u1, // bit offset: 7 desc: The current value of the SDA signal. + RFF: enum(u1) { // bit offset: 8 desc: Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. + @"RX_FIFO_IS_NOT_FULL" = 0, // desc: RX FIFO is not full + @"RX_FIFO_IS_FULL" = 1, // desc: RX FIFO is full + }, + RFE: enum(u1) { // bit offset: 9 desc: Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. + @"DATA" = 0, // desc: RX FIFO contains data. + @"EMPTY" = 1, // desc: RX FIFO is empty + }, + TFF: enum(u1) { // bit offset: 10 desc: Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. + @"TX_FIFO_IS_NOT_FULL_" = 0, // desc: TX FIFO is not full. + @"TX_FIFO_IS_FULL" = 1, // desc: TX FIFO is full + }, + TFE: enum(u1) { // bit offset: 11 desc: Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. + @"VALID_DATA" = 0, // desc: TX FIFO contains valid data. + @"EMPTY" = 1, // desc: TX FIFO is empty + }, + // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16468,15 +20548,43 @@ pub const USB = extern struct { }); // byte offset: 776 I2C Control pub const I2C_CTL = mmio(Address + 0x00000308, 32, packed struct { - TDIE: bool, // bit offset: 0 desc: Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. - AFIE: bool, // bit offset: 1 desc: Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. - NAIE: bool, // bit offset: 2 desc: Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. - DRMIE: bool, // bit offset: 3 desc: Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. - DRSIE: bool, // bit offset: 4 desc: Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. - REFIE: bool, // bit offset: 5 desc: Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. - RFDAIE: bool, // bit offset: 6 desc: Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). - TFFIE: bool, // bit offset: 7 desc: Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. - SRST: bool, // bit offset: 8 desc: Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. + TDIE: enum(u1) { // bit offset: 0 desc: Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. + @"DISABLE_THE_TDI_INTE" = 0, // desc: Disable the TDI interrupt. + @"ENABLE_THE_TDI_INTER" = 1, // desc: Enable the TDI interrupt. + }, + AFIE: enum(u1) { // bit offset: 1 desc: Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. + @"DISABLE_THE_AFI_" = 0, // desc: Disable the AFI. + @"ENABLE_THE_AFI_" = 1, // desc: Enable the AFI. + }, + NAIE: enum(u1) { // bit offset: 2 desc: Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. + @"DISABLE_THE_NAI_" = 0, // desc: Disable the NAI. + @"ENABLE_THE_NAI_" = 1, // desc: Enable the NAI. + }, + DRMIE: enum(u1) { // bit offset: 3 desc: Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. + @"DISABLE_THE_DRMI_INT" = 0, // desc: Disable the DRMI interrupt. + @"ENABLE_THE_DRMI_INTE" = 1, // desc: Enable the DRMI interrupt. + }, + DRSIE: enum(u1) { // bit offset: 4 desc: Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. + @"DISABLE_THE_DRSI_INT" = 0, // desc: Disable the DRSI interrupt. + @"ENABLE_THE_DRSI_INTE" = 1, // desc: Enable the DRSI interrupt. + }, + REFIE: enum(u1) { // bit offset: 5 desc: Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. + @"DISABLE_THE_RFFI_" = 0, // desc: Disable the RFFI. + @"ENABLE_THE_RFFI_" = 1, // desc: Enable the RFFI. + }, + RFDAIE: enum(u1) { // bit offset: 6 desc: Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). + @"DISABLE_THE_DAI_" = 0, // desc: Disable the DAI. + @"ENABLE_THE_DAI_" = 1, // desc: Enable the DAI. + }, + TFFIE: enum(u1) { // bit offset: 7 desc: Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. + @"DISABLE_THE_TFFI_" = 0, // desc: Disable the TFFI. + @"ENABLE_THE_TFFI_" = 1, // desc: Enable the TFFI. + }, + SRST: enum(u1) { // bit offset: 8 desc: Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. + @"NO_RESET" = 0, // desc: No reset. + @"RESET" = 1, // desc: Reset the I2C to idle state. Self clearing. + }, + // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16504,6 +20612,7 @@ pub const USB = extern struct { // byte offset: 780 I2C Clock High pub const I2C_CLKHI = mmio(Address + 0x0000030c, 32, packed struct { CDHI: u8, // bit offset: 0 desc: Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16532,6 +20641,7 @@ pub const USB = extern struct { // byte offset: 784 I2C Clock Low pub const I2C_CLKLO = mmio(Address + 0x00000310, 32, packed struct { CDLO: u8, // bit offset: 0 desc: Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. + // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16559,11 +20669,14 @@ pub const USB = extern struct { }); // byte offset: 4084 USB Clock Control pub const USBCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - DEV_CLK_EN: bool, // bit offset: 1 desc: Device clock enable. Enables the usbclk input to the device controller + DEV_CLK_EN: u1, // bit offset: 1 desc: Device clock enable. Enables the usbclk input to the device controller + // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, - PORTSEL_CLK_EN: bool, // bit offset: 3 desc: Port select register clock enable. - AHB_CLK_EN: bool, // bit offset: 4 desc: AHB clock enable + PORTSEL_CLK_EN: u1, // bit offset: 3 desc: Port select register clock enable. + AHB_CLK_EN: u1, // bit offset: 4 desc: AHB clock enable + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -16594,11 +20707,27 @@ pub const USB = extern struct { }); // byte offset: 4084 OTG clock controller pub const OTGCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { - HOST_CLK_EN: bool, // bit offset: 0 desc: Host clock enable - DEV_CLK_EN: bool, // bit offset: 1 desc: Device clock enable - I2C_CLK_EN: bool, // bit offset: 2 desc: I2C clock enable - OTG_CLK_EN: bool, // bit offset: 3 desc: OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. - AHB_CLK_EN: bool, // bit offset: 4 desc: AHB master clock enable + HOST_CLK_EN: enum(u1) { // bit offset: 0 desc: Host clock enable + @"DISABLE_THE_HOST_CLO" = 0, // desc: Disable the Host clock. + @"ENABLE_THE_HOST_CLOC" = 1, // desc: Enable the Host clock. + }, + DEV_CLK_EN: enum(u1) { // bit offset: 1 desc: Device clock enable + @"DISABLE_THE_DEVICE_C" = 0, // desc: Disable the Device clock. + @"ENABLE_THE_DEVICE_CL" = 1, // desc: Enable the Device clock. + }, + I2C_CLK_EN: enum(u1) { // bit offset: 2 desc: I2C clock enable + @"DISABLE_THE_I2C_CLOC" = 0, // desc: Disable the I2C clock. + @"ENABLE_THE_I2C_CLOCK" = 1, // desc: Enable the I2C clock. + }, + OTG_CLK_EN: enum(u1) { // bit offset: 3 desc: OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. + @"DISABLE_THE_OTG_CLOC" = 0, // desc: Disable the OTG clock. + @"ENABLE_THE_OTG_CLOCK" = 1, // desc: Enable the OTG clock. + }, + AHB_CLK_EN: enum(u1) { // bit offset: 4 desc: AHB master clock enable + @"DISABLE_THE_AHB_CLOC" = 0, // desc: Disable the AHB clock. + @"ENABLE_THE_AHB_CLOCK" = 1, // desc: Enable the AHB clock. + }, + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -16629,11 +20758,14 @@ pub const USB = extern struct { }); // byte offset: 4088 USB Clock Status pub const USBCLKST = mmio(Address + 0x00000ff8, 32, packed struct { + // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. reserved1: u1 = 0, - DEV_CLK_ON: bool, // bit offset: 1 desc: Device clock on. The usbclk input to the device controller is active . + DEV_CLK_ON: u1, // bit offset: 1 desc: Device clock on. The usbclk input to the device controller is active . + // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. reserved2: u1 = 0, - PORTSEL_CLK_ON: bool, // bit offset: 3 desc: Port select register clock on. - AHB_CLK_ON: bool, // bit offset: 4 desc: AHB clock on. + PORTSEL_CLK_ON: u1, // bit offset: 3 desc: Port select register clock on. + AHB_CLK_ON: u1, // bit offset: 4 desc: AHB clock on. + // RESERVED: u27, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -16664,11 +20796,27 @@ pub const USB = extern struct { }); // byte offset: 4088 OTG clock status pub const OTGCLKST = mmio(Address + 0x00000ff8, 32, packed struct { - HOST_CLK_ON: bool, // bit offset: 0 desc: Host clock status. - DEV_CLK_ON: bool, // bit offset: 1 desc: Device clock status. - I2C_CLK_ON: bool, // bit offset: 2 desc: I2C clock status. - OTG_CLK_ON: bool, // bit offset: 3 desc: OTG clock status. - AHB_CLK_ON: bool, // bit offset: 4 desc: AHB master clock status. + HOST_CLK_ON: enum(u1) { // bit offset: 0 desc: Host clock status. + @"HOST_CLOCK_IS_NOT_AV" = 0, // desc: Host clock is not available. + @"HOST_CLOCK_IS_AVAILA" = 1, // desc: Host clock is available. + }, + DEV_CLK_ON: enum(u1) { // bit offset: 1 desc: Device clock status. + @"DEVICE_CLOCK_IS_NOT_" = 0, // desc: Device clock is not available. + @"DEVICE_CLOCK_IS_AVAI" = 1, // desc: Device clock is available. + }, + I2C_CLK_ON: enum(u1) { // bit offset: 2 desc: I2C clock status. + @"I2C_CLOCK_IS_NOT_AVA" = 0, // desc: I2C clock is not available. + @"I2C_CLOCK_IS_AVAILAB" = 1, // desc: I2C clock is available. + }, + OTG_CLK_ON: enum(u1) { // bit offset: 3 desc: OTG clock status. + @"OTG_CLOCK_IS_NOT_AVA" = 0, // desc: OTG clock is not available. + @"OTG_CLOCK_IS_AVAILAB" = 1, // desc: OTG clock is available. + }, + AHB_CLK_ON: enum(u1) { // bit offset: 4 desc: AHB master clock status. + @"AHB_CLOCK_IS_NOT_AVA" = 0, // desc: AHB clock is not available. + @"AHB_CLOCK_IS_AVAILAB" = 1, // desc: AHB clock is available. + }, + // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -16702,878 +20850,878 @@ pub const GPIO = extern struct { pub const Address: u32 = 0x2009c000; // byte offset: 0 GPIO Port Direction control register. pub const DIR0 = mmio(Address + 0x00000000, 32, packed struct { - PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. }); // byte offset: 16 Mask register for Port. pub const MASK0 = mmio(Address + 0x00000010, 32, packed struct { - PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. }); // byte offset: 20 Port Pin value register using FIOMASK. pub const PIN0 = mmio(Address + 0x00000014, 32, packed struct { - PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. }); // byte offset: 24 Port Output Set register using FIOMASK. pub const SET0 = mmio(Address + 0x00000018, 32, packed struct { - PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. }); // byte offset: 28 Port Output Clear register using FIOMASK. pub const CLR0 = mmio(Address + 0x0000001c, 32, packed struct { - PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); // byte offset: 32 GPIO Port Direction control register. pub const DIR1 = mmio(Address + 0x00000020, 32, packed struct { - PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. }); // byte offset: 48 Mask register for Port. pub const MASK1 = mmio(Address + 0x00000030, 32, packed struct { - PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. }); // byte offset: 52 Port Pin value register using FIOMASK. pub const PIN1 = mmio(Address + 0x00000034, 32, packed struct { - PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. }); // byte offset: 56 Port Output Set register using FIOMASK. pub const SET1 = mmio(Address + 0x00000038, 32, packed struct { - PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. }); // byte offset: 60 Port Output Clear register using FIOMASK. pub const CLR1 = mmio(Address + 0x0000003c, 32, packed struct { - PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); // byte offset: 64 GPIO Port Direction control register. pub const DIR2 = mmio(Address + 0x00000040, 32, packed struct { - PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. }); // byte offset: 80 Mask register for Port. pub const MASK2 = mmio(Address + 0x00000050, 32, packed struct { - PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. }); // byte offset: 84 Port Pin value register using FIOMASK. pub const PIN2 = mmio(Address + 0x00000054, 32, packed struct { - PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. }); // byte offset: 88 Port Output Set register using FIOMASK. pub const SET2 = mmio(Address + 0x00000058, 32, packed struct { - PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. }); // byte offset: 92 Port Output Clear register using FIOMASK. pub const CLR2 = mmio(Address + 0x0000005c, 32, packed struct { - PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); // byte offset: 96 GPIO Port Direction control register. pub const DIR3 = mmio(Address + 0x00000060, 32, packed struct { - PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. }); // byte offset: 112 Mask register for Port. pub const MASK3 = mmio(Address + 0x00000070, 32, packed struct { - PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. }); // byte offset: 116 Port Pin value register using FIOMASK. pub const PIN3 = mmio(Address + 0x00000074, 32, packed struct { - PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. }); // byte offset: 120 Port Output Set register using FIOMASK. pub const SET3 = mmio(Address + 0x00000078, 32, packed struct { - PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. }); // byte offset: 124 Port Output Clear register using FIOMASK. pub const CLR3 = mmio(Address + 0x0000007c, 32, packed struct { - PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); // byte offset: 128 GPIO Port Direction control register. pub const DIR4 = mmio(Address + 0x00000080, 32, packed struct { - PINDIR0: bool, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: bool, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: bool, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: bool, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: bool, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: bool, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: bool, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: bool, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: bool, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: bool, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: bool, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: bool, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: bool, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: bool, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: bool, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: bool, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: bool, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: bool, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: bool, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: bool, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: bool, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: bool, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: bool, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: bool, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: bool, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: bool, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: bool, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: bool, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: bool, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: bool, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: bool, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: bool, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. + PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. }); // byte offset: 144 Mask register for Port. pub const MASK4 = mmio(Address + 0x00000090, 32, packed struct { - PINMASK0: bool, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: bool, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: bool, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: bool, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: bool, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: bool, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: bool, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: bool, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: bool, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: bool, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: bool, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: bool, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: bool, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: bool, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: bool, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: bool, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: bool, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: bool, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: bool, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: bool, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: bool, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: bool, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: bool, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: bool, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: bool, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: bool, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: bool, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: bool, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: bool, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: bool, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: bool, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: bool, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. + PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. }); // byte offset: 148 Port Pin value register using FIOMASK. pub const PIN4 = mmio(Address + 0x00000094, 32, packed struct { - PINVAL0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. + PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. }); // byte offset: 152 Port Output Set register using FIOMASK. pub const SET4 = mmio(Address + 0x00000098, 32, packed struct { - PINSET0: bool, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: bool, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: bool, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: bool, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: bool, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: bool, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: bool, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: bool, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: bool, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: bool, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: bool, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: bool, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: bool, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: bool, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: bool, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: bool, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: bool, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: bool, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: bool, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: bool, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: bool, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: bool, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: bool, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: bool, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: bool, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: bool, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: bool, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: bool, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: bool, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: bool, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: bool, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: bool, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. + PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. }); // byte offset: 156 Port Output Clear register using FIOMASK. pub const CLR4 = mmio(Address + 0x0000009c, 32, packed struct { - PINCLR0: bool, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: bool, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: bool, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: bool, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: bool, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: bool, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: bool, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: bool, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: bool, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: bool, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: bool, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: bool, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: bool, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: bool, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: bool, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: bool, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: bool, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: bool, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: bool, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: bool, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: bool, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: bool, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: bool, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: bool, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: bool, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: bool, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: bool, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: bool, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: bool, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: bool, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: bool, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: bool, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. + PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); }; diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index f3d98dc..c31bb92 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -45,7 +45,7 @@ class MMIOFileGenerator: total_fields_with_values = 0 for e in field.enumerated_values: e.description = cleanup_description(e.description) - if e.value is None: + if e.value is None or e.name == "RESERVED": # reserved fields doesn't have a value so we have to comment them out self.write_line(f"// @\"{e.name}\", // desc: {e.description}") else: @@ -84,9 +84,16 @@ class MMIOFileGenerator: last_offset = 0 reserved_index = 0 for field in sorted(register.fields, key=lambda f: f.bit_offset): + # workaround for NXP SVD which has overleaping reserved fields + if field.name == "RESERVED": + self.write_line(f"// RESERVED: u{field.bit_width}, // bit offset: {field.bit_offset} desc: {field.description}") + continue + if last_offset != field.bit_offset: - self.generate_padding(field.bit_offset - last_offset, "reserved", reserved_index) - reserved_index = reserved_index + field.bit_width + reserved_size = field.bit_offset - last_offset + self.generate_padding(reserved_size, "reserved", reserved_index) + reserved_index = reserved_index + reserved_size + if field.is_enumerated_type: last_offset = self.generate_enumerated_field(field) else: @@ -98,7 +105,6 @@ class MMIOFileGenerator: else: self.generate_padding(size - last_offset, "padding", 0) - self.write_line("});") def generate_peripherial_declaration(self, peripherial): diff --git a/tests/blinky.zig b/tests/blinky.zig index d5614c7..b7068be 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -4,16 +4,16 @@ const micro = @import("microzig"); pub const panic = micro.panic; // Configures the led_pin to a hardware pin -const led_pin = switch (@import("builtin").cpu.arch) { - .avr => if (micro.config.has_board) - micro.Pin("D13") // Use D13 from Arduino Nano - else - micro.Pin("PB5"), // Use PB5 on raw ATmega328p - .arm => if (micro.config.has_board) - micro.Pin("LED-1") // Use LED-1 from mbed LPC1768 - else - micro.Pin("P1.18"), // Use P1.18 on raw LPC1768 - else => @compileError("Unsupported platform!"), +const led_pin = if (micro.config.has_board) + switch (micro.config.board_name) { + .@"Arduino Nano" => micro.Pin("D13"), + .@"mbed LPC1768" => micro.Pin("LED-1"), + else => @compileError("unknown board"), + } +else switch (micro.config.chip_name) { + .@"ATmega328p" => micro.Pin("PB5"), + .@"NXP LPC1768" => micro.Pin("P1.18"), + else => @compileError("unknown chip"), }; pub fn main() void { diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 7116272..335fda2 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -28,7 +28,7 @@ const PLL = struct { fn overclock_flash(timing: u5) void { micro.chip.registers.SYSCON.FLASHCFG.write(.{ - .FLASHTIM = @intCast(u4, timing - 1), + .FLASHTIM = @intToEnum(@TypeOf(micro.chip.registers.SYSCON.FLASHCFG.read().FLASHTIM), @intCast(u4, timing - 1)), }); } fn feed_pll() callconv(.Inline) void { @@ -39,12 +39,12 @@ const PLL = struct { fn overclock_pll(divider: u8) void { // PLL einrichten für RC micro.chip.registers.SYSCON.PLL0CON.write(.{ - .PLLE0 = false, - .PLLC0 = false, + .PLLE0 = 0, + .PLLC0 = 0, }); feed_pll(); - micro.chip.registers.SYSCON.CLKSRCSEL.write(.{ .CLKSRC = 0 }); // RC-Oszillator als Quelle + micro.chip.registers.SYSCON.CLKSRCSEL.write(.{ .CLKSRC = .SELECTS_THE_INTERNAL }); // RC-Oszillator als Quelle micro.chip.registers.SYSCON.PLL0CFG.write(.{ // SysClk = (4MHz / 2) * (2 * 75) = 300 MHz .MSEL0 = 74, @@ -55,7 +55,7 @@ const PLL = struct { feed_pll(); - micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = true }); // PLL einschalten + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = 1 }); // PLL einschalten feed_pll(); var i: usize = 0; @@ -63,7 +63,7 @@ const PLL = struct { micro.cpu.nop(); } - micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLC0 = true }); + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLC0 = 1 }); feed_pll(); } }; @@ -95,8 +95,8 @@ pub fn main() !void { var debug_port = micro.Uart(1).init(.{ .baud_rate = 9600, .stop_bits = .one, - .parity = .none, // { none, even, odd, mark, space } - .data_bits = .@"8", // 5, 6, 7, 8, or 9 data bits + .parity = null, + .data_bits = .eight, }) catch |err| { led1.write(if (err == error.UnsupportedBaudRate) micro.gpio.State.low else .high); led2.write(if (err == error.UnsupportedParity) micro.gpio.State.low else .high); From 2a6bedfccace243f1141d312864cd99de0c4bd3a Mon Sep 17 00:00:00 2001 From: Vesim Date: Mon, 7 Jun 2021 19:22:13 +0200 Subject: [PATCH 016/138] Update README.md --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index e69de29..1f130a9 100644 --- a/README.md +++ b/README.md @@ -0,0 +1 @@ +# NOTHING IS STABLE IN THIS REPO From af7aa777f9bc17b18f80615010896ba4f1562799 Mon Sep 17 00:00:00 2001 From: Matthew Knight Date: Mon, 18 Oct 2021 18:22:13 -0700 Subject: [PATCH 017/138] Freshen things up (#6) * catch up to some of master's changes, getting prepped to anchor to 0.9.0 * found fix for lpc board --- .github/workflows/build.yml | 28 ++++++++++++ build.zig | 66 ++++++++++++++------------- src/core/debug.zig | 6 +-- src/core/gpio.zig | 1 + src/core/interrupts.zig | 3 ++ src/modules/chips/lpc1768/lpc1768.zig | 2 + tests/uart-sync.zig | 3 +- 7 files changed, 73 insertions(+), 36 deletions(-) create mode 100644 .github/workflows/build.yml diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 0000000..35a13f4 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,28 @@ +name: Build +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + schedule: + - cron: "0 7 * * *" + +jobs: + build: + runs-on: ubuntu-latest + + steps: + - name: Checkout + uses: actions/checkout@v2 + with: + submodules: recursive + fetch-depth: 0 + + # only using master until 0.9.0 is released + - name: Setup Zig + uses: goto-bus-stop/setup-zig@v1.3.0 + with: + version: master + + - name: Build tests + run: zig build -Drelease-small diff --git a/build.zig b/build.zig index 93fa0a0..6543c41 100644 --- a/build.zig +++ b/build.zig @@ -4,17 +4,17 @@ const std = @import("std"); -pub fn build(b: *std.build.Builder) void { +pub fn build(b: *std.build.Builder) !void { const mode = b.standardReleaseOptions(); const test_step = b.step("test", "Builds and runs the library test suite"); const BuildConfig = struct { name: []const u8, backing: Backing }; const all_backings = [_]BuildConfig{ - BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, + //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = pkgs.boards.mbed_lpc1768 } }, - BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, - BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, + //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, + //BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, }; const Test = struct { name: []const u8, source: []const u8 }; @@ -28,7 +28,7 @@ pub fn build(b: *std.build.Builder) void { inline for (all_backings) |cfg| { inline for (all_tests) |tst| { - const exe = addEmbeddedExecutable( + const exe = try addEmbeddedExecutable( b, "test-" ++ tst.name ++ "-" ++ cfg.name, tst.source, @@ -45,12 +45,12 @@ pub fn build(b: *std.build.Builder) void { } } -fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) *std.build.LibExeObjStep { +fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) !*std.build.LibExeObjStep { const Pkg = std.build.Pkg; const microzig_base = Pkg{ .name = "microzig", - .path = "src/core/microzig.zig", + .path = .{ .path = "src/core/microzig.zig" }, }; const chip = switch (backing) { @@ -62,18 +62,18 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: const chip_package = Pkg{ .name = "chip", - .path = chip.path, + .path = .{ .path = chip.path }, .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio, Pkg{ .name = "cpu", - .path = chip.cpu.path, + .path = .{ .path = chip.cpu.path }, .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, }, Pkg{ .name = "microzig-linker", - .path = "src/modules/linker/linker.zig", + .path = .{ .path = "src/modules/linker/linker.zig" }, }, }, }; @@ -96,11 +96,11 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: const file_suffix = ".ld"; var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ file_prefix, std.fmt.fmtSliceHexLower(&hash), file_suffix, - }) catch unreachable; + }); break :blk builder.dupe(filename); }; @@ -128,44 +128,46 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: const file_suffix = ".zig"; var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ file_prefix, std.fmt.fmtSliceHexLower(&hash), file_suffix, - }) catch unreachable; + }); break :blk builder.dupe(filename); }; { - var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; + std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; + var config_file = try std.fs.cwd().createFile(config_file_name, .{}); defer config_file.close(); var writer = config_file.writer(); + try writer.print("pub const has_board = {};\n", .{has_board}); + if (has_board) + try writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}); - writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; - if (has_board) { - writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; - } - - writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; - writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + try writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}); + try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); } const config_pkg = Pkg{ .name = "microzig-config", - .path = config_file_name, + .path = .{ .path = config_file_name }, }; + const build_options = builder.addOptions(); + build_options.addOption([]const u8, "microzig_chip_name", chip.name); + build_options.addOption([]const u8, "microzig_cpu_name", chip.cpu.name); + build_options.addOption([]const u8, "microzig_target_triple", try chip.cpu.target.zigTriple(builder.allocator)); + const linkerscript_gen = builder.addExecutable("linkerscript-gen", "src/tools/linkerscript-gen.zig"); linkerscript_gen.addPackage(chip_package); linkerscript_gen.addPackage(Pkg{ .name = "microzig-linker", - .path = "src/modules/linker/linker.zig", + .path = .{ .path = "src/modules/linker/linker.zig" }, }); - linkerscript_gen.addBuildOption([]const u8, "microzig_chip_name", chip.name); - linkerscript_gen.addBuildOption([]const u8, "microzig_cpu_name", chip.cpu.name); - linkerscript_gen.addBuildOption([]const u8, "microzig_target_triple", chip.cpu.target.zigTriple(builder.allocator) catch unreachable); + linkerscript_gen.addOptions("build_options", build_options); const linkerscript_invocation = linkerscript_gen.run(); linkerscript_invocation.addArg(linker_script_name); @@ -177,7 +179,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: exe.single_threaded = true; exe.setTarget(chip.cpu.target); - exe.setLinkerScriptPath(linker_script_name); + exe.setLinkerScriptPath(.{ .path = linker_script_name }); exe.step.dependOn(&linkerscript_invocation.step); // TODO: @@ -185,7 +187,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - // exe.bundle_compiler_rt = false; + exe.bundle_compiler_rt = false; switch (backing) { .chip => { @@ -204,7 +206,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: chip_package, Pkg{ .name = "board", - .path = board.path, + .path = .{ .path = board.path }, .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio }, }, }, @@ -241,7 +243,7 @@ pub const Backing = union(enum) { const pkgs = struct { const mmio = std.build.Pkg{ .name = "microzig-mmio", - .path = "src/core/mmio.zig", + .path = .{ .path = "src/core/mmio.zig" }, }; const cpus = struct { @@ -264,7 +266,7 @@ const pkgs = struct { .cpu_arch = .arm, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, .os_tag = .freestanding, - .abi = .eabi, + .abi = .none, }, }; }; diff --git a/src/core/debug.zig b/src/core/debug.zig index eb2474c..88d0f7a 100644 --- a/src/core/debug.zig +++ b/src/core/debug.zig @@ -19,6 +19,7 @@ pub fn busySleep(comptime limit: comptime_int) void { const DebugErr = error{}; fn writerWrite(ctx: void, string: []const u8) DebugErr!usize { + _ = ctx; write(string); return string.len; } @@ -26,10 +27,9 @@ fn writerWrite(ctx: void, string: []const u8) DebugErr!usize { const DebugWriter = std.io.Writer(void, DebugErr, writerWrite); pub fn write(string: []const u8) void { - if (!micro.config.has_board) - return; - if (!@hasDecl(micro.board, "debugWrite")) + if (!micro.config.has_board and !@hasDecl(micro.board, "debugWrite")) return; + micro.board.debugWrite(string); } diff --git a/src/core/gpio.zig b/src/core/gpio.zig index 325cfed..4008b89 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -102,6 +102,7 @@ pub fn Gpio(comptime pin: type, config: anytype) type { // open drain fn setDrive(drive: Drive) void { + _ = drive; @compileError("open drain not implemented yet!"); } fn getDrive() Drive { diff --git a/src/core/interrupts.zig b/src/core/interrupts.zig index 10013c4..79f297f 100644 --- a/src/core/interrupts.zig +++ b/src/core/interrupts.zig @@ -4,16 +4,19 @@ const micro = @import("microzig.zig"); /// Unmasks the given interrupt and enables its execution. /// Note that interrupts must be globally enabled with `sei()` as well. pub fn enable(comptime interrupt: anytype) void { + _ = interrupt; @compileError("not implemented yet!"); } /// Masks the given interrupt and disables its execution. pub fn disable(comptime interrupt: anytype) void { + _ = interrupt; @compileError("not implemented yet!"); } /// Returns true when the given interrupt is unmasked. pub fn isEnabled(comptime interrupt: anytype) bool { + _ = interrupt; @compileError("not implemented yet!"); } diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 4f39fa4..b4a8e05 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -174,6 +174,7 @@ pub fn Uart(comptime index: usize) type { } pub fn canWrite(self: Self) bool { + _ = self; return switch (UARTn.LSR.read().THRE) { .VALID => true, .THR_IS_EMPTY_ => false, @@ -185,6 +186,7 @@ pub fn Uart(comptime index: usize) type { } pub fn canRead(self: Self) bool { + _ = self; return switch (UARTn.LSR.read().RDR) { .EMPTY => false, .NOTEMPTY => true, diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 335fda2..8c97d4f 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -31,7 +31,7 @@ const PLL = struct { .FLASHTIM = @intToEnum(@TypeOf(micro.chip.registers.SYSCON.FLASHCFG.read().FLASHTIM), @intCast(u4, timing - 1)), }); } - fn feed_pll() callconv(.Inline) void { + inline fn feed_pll() void { micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0xAA }); micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0x55 }); } @@ -109,6 +109,7 @@ pub fn main() !void { var out = debug_port.writer(); var in = debug_port.reader(); + _ = in; try out.writeAll("Please enter a sentence:\r\n"); From 5a1e72f380f23fa4e550ed577c9c754013cb8998 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 5 Jan 2022 19:12:55 -0800 Subject: [PATCH 018/138] Create LinkerscriptStep (#7) * create linkerscript step * catch up to master, do some cleanup * remove references to micro_linker * commas * remove package * use root path trick for cpus and chips * remove duped file --- .github/workflows/build.yml | 10 +- .gitignore | 3 +- build.zig | 139 +++--------------- src/core/debug.zig | 4 +- .../LinkerScriptStep.zig} | 107 ++++++++------ src/modules/MemoryRegion.zig | 18 +++ src/modules/boards.zig | 20 +++ src/modules/chips.zig | 37 +++++ src/modules/chips/atmega328p/atmega328p.zig | 7 - src/modules/chips/lpc1768/lpc1768.zig | 7 - src/modules/cpus.zig | 35 +++++ src/modules/cpus/cortex-m3/cortex-m3.zig | 10 +- src/modules/linker/linker.zig | 20 --- 13 files changed, 211 insertions(+), 206 deletions(-) rename src/{tools/linkerscript-gen.zig => modules/LinkerScriptStep.zig} (61%) create mode 100644 src/modules/MemoryRegion.zig create mode 100644 src/modules/boards.zig create mode 100644 src/modules/chips.zig create mode 100644 src/modules/cpus.zig delete mode 100644 src/modules/linker/linker.zig diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 35a13f4..9135476 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -9,8 +9,14 @@ on: jobs: build: - runs-on: ubuntu-latest - + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ + ubuntu-latest, + windows-latest, + macos-latest, + ] steps: - name: Checkout uses: actions/checkout@v2 diff --git a/.gitignore b/.gitignore index ac2eddc..eacd52b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ zig-cache/ -dev-scripts/ \ No newline at end of file +dev-scripts/ +zig-out diff --git a/build.zig b/build.zig index 6543c41..eb478e8 100644 --- a/build.zig +++ b/build.zig @@ -3,6 +3,13 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); +const boards = @import("src/modules/boards.zig"); +const chips = @import("src/modules/chips.zig"); +const LinkerscriptStep = @import("src/modules/LinkerScriptStep.zig"); + +const Board = boards.Board; +const Chip = chips.Chip; +const Cpu = chips.Cpu; pub fn build(b: *std.build.Builder) !void { const mode = b.standardReleaseOptions(); @@ -12,9 +19,9 @@ pub fn build(b: *std.build.Builder) !void { const BuildConfig = struct { name: []const u8, backing: Backing }; const all_backings = [_]BuildConfig{ //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, - BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = pkgs.boards.mbed_lpc1768 } }, + BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, - //BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = pkgs.chips.lpc1768 } }, + BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, }; const Test = struct { name: []const u8, source: []const u8 }; @@ -45,7 +52,12 @@ pub fn build(b: *std.build.Builder) !void { } } -fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing) !*std.build.LibExeObjStep { +fn addEmbeddedExecutable( + builder: *std.build.Builder, + name: []const u8, + source: []const u8, + backing: Backing, +) !*std.build.LibExeObjStep { const Pkg = std.build.Pkg; const microzig_base = Pkg{ @@ -71,40 +83,9 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: .path = .{ .path = chip.cpu.path }, .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, }, - Pkg{ - .name = "microzig-linker", - .path = .{ .path = "src/modules/linker/linker.zig" }, - }, }, }; - const linker_script_name = blk: { - const hash = hash_blk: { - var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); - - hasher.update(chip.name); - hasher.update(chip.path); - hasher.update(chip.cpu.name); - hasher.update(chip.cpu.path); - - var mac: [16]u8 = undefined; - hasher.final(&mac); - break :hash_blk mac; - }; - - const file_prefix = "zig-cache/microzig/"; - const file_suffix = ".ld"; - - var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ - file_prefix, - std.fmt.fmtSliceHexLower(&hash), - file_suffix, - }); - - break :blk builder.dupe(filename); - }; - const config_file_name = blk: { const hash = hash_blk: { var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); @@ -156,22 +137,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: .path = .{ .path = config_file_name }, }; - const build_options = builder.addOptions(); - build_options.addOption([]const u8, "microzig_chip_name", chip.name); - build_options.addOption([]const u8, "microzig_cpu_name", chip.cpu.name); - build_options.addOption([]const u8, "microzig_target_triple", try chip.cpu.target.zigTriple(builder.allocator)); - - const linkerscript_gen = builder.addExecutable("linkerscript-gen", "src/tools/linkerscript-gen.zig"); - linkerscript_gen.addPackage(chip_package); - linkerscript_gen.addPackage(Pkg{ - .name = "microzig-linker", - .path = .{ .path = "src/modules/linker/linker.zig" }, - }); - linkerscript_gen.addOptions("build_options", build_options); - - const linkerscript_invocation = linkerscript_gen.run(); - linkerscript_invocation.addArg(linker_script_name); - + const linkerscript = try LinkerscriptStep.create(builder, chip); const exe = builder.addExecutable(name, source); // might not be true for all machines (Pi Pico), but @@ -179,8 +145,7 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: exe.single_threaded = true; exe.setTarget(chip.cpu.target); - exe.setLinkerScriptPath(.{ .path = linker_script_name }); - exe.step.dependOn(&linkerscript_invocation.step); + exe.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); // TODO: // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. @@ -216,25 +181,6 @@ fn addEmbeddedExecutable(builder: *std.build.Builder, name: []const u8, source: return exe; } -const Board = struct { - name: []const u8, - path: []const u8, - chip: Chip, -}; - -const Chip = struct { - name: []const u8, - path: []const u8, - cpu: Cpu, -}; - -const Cpu = struct { - name: []const u8, - path: []const u8, - target: std.zig.CrossTarget, - linker_script: []const u8, -}; - pub const Backing = union(enum) { board: Board, chip: Chip, @@ -245,55 +191,4 @@ const pkgs = struct { .name = "microzig-mmio", .path = .{ .path = "src/core/mmio.zig" }, }; - - const cpus = struct { - const avr5 = Cpu{ - .name = "AVR5", - .path = "src/modules/cpus/avr/avr5.zig", - .linker_script = "src/modules/cpus/avr/linker.ld", - .target = std.zig.CrossTarget{ - .cpu_arch = .avr, - .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, - .os_tag = .freestanding, - .abi = .eabi, - }, - }; - const cortex_m3 = Cpu{ - .name = "ARM Cortex-M3", - .path = "src/modules/cpus/cortex-m3/cortex-m3.zig", - .linker_script = "src/modules/cpus/cortex-m3/linker.ld", - .target = std.zig.CrossTarget{ - .cpu_arch = .arm, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, - .os_tag = .freestanding, - .abi = .none, - }, - }; - }; - - const chips = struct { - const atmega328p = Chip{ - .name = "ATmega328p", - .path = "src/modules/chips/atmega328p/atmega328p.zig", - .cpu = cpus.avr5, - }; - const lpc1768 = Chip{ - .name = "NXP LPC1768", - .path = "src/modules/chips/lpc1768/lpc1768.zig", - .cpu = cpus.cortex_m3, - }; - }; - - const boards = struct { - const arduino_nano = Board{ - .name = "Arduino Nano", - .path = "src/modules/boards/arduino-nano/arduino-nano.zig", - .chip = chips.atmega328p, - }; - const mbed_lpc1768 = Board{ - .name = "mbed LPC1768", - .path = "src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig", - .chip = chips.lpc1768, - }; - }; }; diff --git a/src/core/debug.zig b/src/core/debug.zig index 88d0f7a..8f27bb3 100644 --- a/src/core/debug.zig +++ b/src/core/debug.zig @@ -27,7 +27,9 @@ fn writerWrite(ctx: void, string: []const u8) DebugErr!usize { const DebugWriter = std.io.Writer(void, DebugErr, writerWrite); pub fn write(string: []const u8) void { - if (!micro.config.has_board and !@hasDecl(micro.board, "debugWrite")) + if (!micro.config.has_board) + return; + if (!@hasDecl(micro.board, "debugWrite")) return; micro.board.debugWrite(string); diff --git a/src/tools/linkerscript-gen.zig b/src/modules/LinkerScriptStep.zig similarity index 61% rename from src/tools/linkerscript-gen.zig rename to src/modules/LinkerScriptStep.zig index a23c272..92f42f7 100644 --- a/src/tools/linkerscript-gen.zig +++ b/src/modules/LinkerScriptStep.zig @@ -1,46 +1,72 @@ const std = @import("std"); -const build_options = @import("build_options"); -const chip = @import("chip"); -const micro_linker = @import("microzig-linker"); - -const target = blk: { - @setEvalBranchQuota(20_000); - - const t = std.zig.CrossTarget.parse(std.zig.CrossTarget.ParseOptions{ - .arch_os_abi = build_options.microzig_target_triple, - }) catch unreachable; - std.debug.assert(t.cpu_arch != null); - break :blk t; -}; - -pub fn main() !u8 { - var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator); - defer arena.deinit(); - - const allocator = &arena.allocator; - - const args = try std.process.argsAlloc(allocator); +const MemoryRegion = @import("MemoryRegion.zig"); +const Chip = @import("chips.zig").Chip; +const Step = std.build.Step; +const Builder = std.build.Builder; +const GeneratedFile = std.build.GeneratedFile; + +const LinkerscriptStep = @This(); + +step: Step, +generated_file: std.build.GeneratedFile, +builder: *Builder, +chip: Chip, + +pub fn create(builder: *Builder, chip: Chip) !*LinkerscriptStep { + var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); + + hasher.update(chip.name); + hasher.update(chip.path); + hasher.update(chip.cpu.name); + hasher.update(chip.cpu.path); + + var mac: [16]u8 = undefined; + hasher.final(&mac); + + const filename = try std.fmt.allocPrint(builder.allocator, "{}{s}", .{ + std.fmt.fmtSliceHexLower(&mac), + ".ld", + }); + + const path = try std.fs.path.join(builder.allocator, &.{ + "zig-cache", + "microzig", + filename, + }); + try std.fs.cwd().makePath(std.fs.path.dirname(path).?); + + var ret = try builder.allocator.create(LinkerscriptStep); + ret.* = LinkerscriptStep{ + .step = Step.init(.custom, "linkerscript", builder.allocator, make), + .generated_file = .{ + .step = &ret.step, + .path = path, + }, + .builder = builder, + .chip = chip, + }; + return ret; +} - if (args.len < 2) { - std.log.err("Missing CLI argument. Give the output file name!", .{}); - return 1; - } +fn make(step: *Step) !void { + const linkerscript = @fieldParentPtr(LinkerscriptStep, "step", step); + const file = try std.fs.cwd().createFile(linkerscript.generated_file.path.?, .{}); + defer file.close(); - if (std.fs.path.dirname(args[1])) |dir| { - try std.fs.cwd().makePath(dir); + const target = linkerscript.chip.cpu.target; + if (target.cpu_arch == null) { + std.log.err("target does not have 'cpu_arch'", .{}); + return error.NoCpuArch; } - var dest_file = try std.fs.cwd().createFile(args[1], .{}); - defer dest_file.close(); - - var writer = dest_file.writer(); - - try writer.writeAll("/*\n * This file was auto-generated by microzig\n *\n"); - try writer.print(" * Target CPU: {s}\n", .{build_options.microzig_cpu_name}); - try writer.print(" * Target Chip: {s}\n", .{build_options.microzig_chip_name}); - try writer.writeAll(" */\n\n"); - - try writer.writeAll( + const writer = file.writer(); + try writer.print( + \\/* + \\ * This file was auto-generated by microzig + \\ * + \\ * Target CPU: {s} + \\ * Target Chip: {s} + \\ */ \\ // This is not the "true" entry point, but there's no such thing on embedded platforms // anyways. This is the logical entrypoint that should be invoked when @@ -48,12 +74,12 @@ pub fn main() !u8 { \\ENTRY(microzig_main); \\ \\ - ); + , .{ linkerscript.chip.cpu.name, linkerscript.chip.name }); try writer.writeAll("MEMORY\n{\n"); { var counters = [2]usize{ 0, 0 }; - for (chip.memory_regions) |region| { + for (linkerscript.chip.memory_regions) |region| { // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k switch (region.kind) { @@ -134,5 +160,4 @@ pub fn main() !u8 { // \\ ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" ); // \\ // ); - return 0; } diff --git a/src/modules/MemoryRegion.zig b/src/modules/MemoryRegion.zig new file mode 100644 index 0000000..048b2b5 --- /dev/null +++ b/src/modules/MemoryRegion.zig @@ -0,0 +1,18 @@ +//! This module is meant to be used to define linking apis + +kind: Kind, +offset: u64, +length: u64, + +pub const Kind = union(enum) { + flash, + ram, + custom: RegionSpec, +}; + +pub const RegionSpec = struct { + name: []const u8, + executable: bool, + readable: bool, + writeable: bool, +}; diff --git a/src/modules/boards.zig b/src/modules/boards.zig new file mode 100644 index 0000000..c435044 --- /dev/null +++ b/src/modules/boards.zig @@ -0,0 +1,20 @@ +const chips = @import("chips.zig"); + +const Chip = chips.Chip; +pub const Board = struct { + name: []const u8, + path: []const u8, + chip: Chip, +}; + +pub const arduino_nano = Board{ + .name = "Arduino Nano", + .path = "src/modules/boards/arduino-nano/arduino-nano.zig", + .chip = chips.atmega328p, +}; + +pub const mbed_lpc1768 = Board{ + .name = "mbed LPC1768", + .path = "src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig", + .chip = chips.lpc1768, +}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig new file mode 100644 index 0000000..c736d38 --- /dev/null +++ b/src/modules/chips.zig @@ -0,0 +1,37 @@ +const std = @import("std"); +const cpus = @import("cpus.zig"); +const MemoryRegion = @import("MemoryRegion.zig"); + +fn root() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +const root_path = root() ++ "/"; + +pub const Chip = struct { + name: []const u8, + path: []const u8, + cpu: cpus.Cpu, + memory_regions: []const MemoryRegion, +}; + +pub const atmega328p = Chip{ + .name = "ATmega328p", + .path = root_path ++ "chips/atmega328p/atmega328p.zig", + .cpu = cpus.avr5, + .memory_regions = &[_]MemoryRegion{ + MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, + }, +}; + +pub const lpc1768 = Chip{ + .name = "NXP LPC1768", + .path = root_path ++ "chips/lpc1768/lpc1768.zig", + .cpu = cpus.cortex_m3, + .memory_regions = &[_]MemoryRegion{ + MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, + MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, + }, +}; diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index da30901..1d6f83d 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,13 +1,6 @@ const std = @import("std"); -const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); - -pub const memory_regions = [_]micro_linker.MemoryRegion{ - micro_linker.MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, - micro_linker.MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, -}; - const Port = enum(u8) { B = 1, C = 2, diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index b4a8e05..9341851 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -1,16 +1,9 @@ const std = @import("std"); const micro = @import("microzig"); -const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); -pub const memory_regions = [_]micro_linker.MemoryRegion{ - micro_linker.MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, - micro_linker.MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, - micro_linker.MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, -}; - pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig new file mode 100644 index 0000000..a58f472 --- /dev/null +++ b/src/modules/cpus.zig @@ -0,0 +1,35 @@ +const std = @import("std"); + +fn root() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +const root_path = root() ++ "/"; + +pub const Cpu = struct { + name: []const u8, + path: []const u8, + target: std.zig.CrossTarget, +}; + +pub const avr5 = Cpu{ + .name = "AVR5", + .path = root_path ++ "cpus/avr/avr5.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .avr, + .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, + .os_tag = .freestanding, + .abi = .eabi, + }, +}; + +pub const cortex_m3 = Cpu{ + .name = "ARM Cortex-M3", + .path = root_path ++ "cpus/cortex-m3/cortex-m3.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .arm, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .none, + }, +}; diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig index 29c1414..4f24e7d 100644 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ b/src/modules/cpus/cortex-m3/cortex-m3.zig @@ -71,11 +71,11 @@ pub const startup_logic = struct { extern fn microzig_main() noreturn; - extern var microzig_data_start: c_void; - extern var microzig_data_end: c_void; - extern var microzig_bss_start: c_void; - extern var microzig_bss_end: c_void; - extern const microzig_data_load_start: c_void; + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; fn _start() callconv(.C) noreturn { diff --git a/src/modules/linker/linker.zig b/src/modules/linker/linker.zig deleted file mode 100644 index f6508b2..0000000 --- a/src/modules/linker/linker.zig +++ /dev/null @@ -1,20 +0,0 @@ -//! This module is meant to be used to define linking apis - -pub const MemoryRegion = struct { - kind: Kind, - offset: u64, - length: u64, - - pub const Kind = union(enum) { - flash, - ram, - custom: RegionSpec, - }; - - pub const RegionSpec = struct { - name: []const u8, - executable: bool, - readable: bool, - writeable: bool, - }; -}; From 46a924234e60bdb5c65af4cb85d994eca7da59e8 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 5 Jan 2022 22:36:06 -0800 Subject: [PATCH 019/138] add stm32f103 registers and reorganize so that microzig can be used as a package (#9) --- build.zig | 154 +- src/main.zig | 154 + src/modules/Board.zig | 5 + src/modules/Chip.zig | 7 + src/modules/Cpu.zig | 5 + src/modules/LinkerScriptStep.zig | 2 +- src/modules/boards.zig | 17 +- src/modules/chips.zig | 22 +- src/modules/chips/stm32f103/registers.zig | 17773 ++++++++++++++++++++ src/modules/chips/stm32f103/stm32f103.zig | 11 + src/modules/cpus.zig | 7 +- tests/blinky.zig | 1 + 12 files changed, 17986 insertions(+), 172 deletions(-) create mode 100644 src/main.zig create mode 100644 src/modules/Board.zig create mode 100644 src/modules/Chip.zig create mode 100644 src/modules/Cpu.zig create mode 100644 src/modules/chips/stm32f103/registers.zig create mode 100644 src/modules/chips/stm32f103/stm32f103.zig diff --git a/build.zig b/build.zig index eb478e8..0006e71 100644 --- a/build.zig +++ b/build.zig @@ -3,13 +3,11 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); -const boards = @import("src/modules/boards.zig"); -const chips = @import("src/modules/chips.zig"); -const LinkerscriptStep = @import("src/modules/LinkerScriptStep.zig"); +const microzig = @import("src/main.zig"); -const Board = boards.Board; -const Chip = chips.Chip; -const Cpu = chips.Cpu; +const boards = microzig.boards; +const chips = microzig.chips; +const Backing = microzig.Backing; pub fn build(b: *std.build.Builder) !void { const mode = b.standardReleaseOptions(); @@ -22,6 +20,7 @@ pub fn build(b: *std.build.Builder) !void { BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, + //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, }; const Test = struct { name: []const u8, source: []const u8 }; @@ -35,7 +34,7 @@ pub fn build(b: *std.build.Builder) !void { inline for (all_backings) |cfg| { inline for (all_tests) |tst| { - const exe = try addEmbeddedExecutable( + const exe = try microzig.addEmbeddedExecutable( b, "test-" ++ tst.name ++ "-" ++ cfg.name, tst.source, @@ -51,144 +50,3 @@ pub fn build(b: *std.build.Builder) !void { } } } - -fn addEmbeddedExecutable( - builder: *std.build.Builder, - name: []const u8, - source: []const u8, - backing: Backing, -) !*std.build.LibExeObjStep { - const Pkg = std.build.Pkg; - - const microzig_base = Pkg{ - .name = "microzig", - .path = .{ .path = "src/core/microzig.zig" }, - }; - - const chip = switch (backing) { - .chip => |c| c, - .board => |b| b.chip, - }; - - const has_board = (backing == .board); - - const chip_package = Pkg{ - .name = "chip", - .path = .{ .path = chip.path }, - .dependencies = &[_]Pkg{ - microzig_base, - pkgs.mmio, - Pkg{ - .name = "cpu", - .path = .{ .path = chip.cpu.path }, - .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, - }, - }, - }; - - const config_file_name = blk: { - const hash = hash_blk: { - var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); - - hasher.update(chip.name); - hasher.update(chip.path); - hasher.update(chip.cpu.name); - hasher.update(chip.cpu.path); - - if (backing == .board) { - hasher.update(backing.board.name); - hasher.update(backing.board.path); - } - - var mac: [16]u8 = undefined; - hasher.final(&mac); - break :hash_blk mac; - }; - - const file_prefix = "zig-cache/microzig/config-"; - const file_suffix = ".zig"; - - var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ - file_prefix, - std.fmt.fmtSliceHexLower(&hash), - file_suffix, - }); - - break :blk builder.dupe(filename); - }; - - { - std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; - var config_file = try std.fs.cwd().createFile(config_file_name, .{}); - defer config_file.close(); - - var writer = config_file.writer(); - try writer.print("pub const has_board = {};\n", .{has_board}); - if (has_board) - try writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}); - - try writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}); - try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); - } - - const config_pkg = Pkg{ - .name = "microzig-config", - .path = .{ .path = config_file_name }, - }; - - const linkerscript = try LinkerscriptStep.create(builder, chip); - const exe = builder.addExecutable(name, source); - - // might not be true for all machines (Pi Pico), but - // for the HAL it's true (it doesn't know the concept of threading) - exe.single_threaded = true; - exe.setTarget(chip.cpu.target); - - exe.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); - - // TODO: - // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. - // - This requires building another tool that runs on the host that compiles those files and emits the linker script. - // - src/tools/linkerscript-gen.zig is the source file for this - - exe.bundle_compiler_rt = false; - - switch (backing) { - .chip => { - exe.addPackage(Pkg{ - .name = microzig_base.name, - .path = microzig_base.path, - .dependencies = &[_]Pkg{ config_pkg, chip_package }, - }); - }, - .board => |board| { - exe.addPackage(Pkg{ - .name = microzig_base.name, - .path = microzig_base.path, - .dependencies = &[_]Pkg{ - config_pkg, - chip_package, - Pkg{ - .name = "board", - .path = .{ .path = board.path }, - .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio }, - }, - }, - }); - }, - } - return exe; -} - -pub const Backing = union(enum) { - board: Board, - chip: Chip, -}; - -const pkgs = struct { - const mmio = std.build.Pkg{ - .name = "microzig-mmio", - .path = .{ .path = "src/core/mmio.zig" }, - }; -}; diff --git a/src/main.zig b/src/main.zig new file mode 100644 index 0000000..7a0ee96 --- /dev/null +++ b/src/main.zig @@ -0,0 +1,154 @@ +const std = @import("std"); + +pub const LinkerScriptStep = @import("modules/LinkerScriptStep.zig"); +pub const boards = @import("modules/boards.zig"); +pub const chips = @import("modules/chips.zig"); +pub const cpus = @import("modules/cpus.zig"); +pub const Board = @import("modules/Board.zig"); +pub const Chip = @import("modules/Chip.zig"); +pub const Cpu = @import("modules/Cpu.zig"); +pub const Backing = union(enum) { + board: Board, + chip: Chip, +}; + +const root_path = root() ++ "/"; +fn root() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +pub fn addEmbeddedExecutable( + builder: *std.build.Builder, + name: []const u8, + source: []const u8, + backing: Backing, +) !*std.build.LibExeObjStep { + const Pkg = std.build.Pkg; + + const microzig_base = Pkg{ + .name = "microzig", + .path = .{ .path = root_path ++ "core/microzig.zig" }, + }; + + const chip = switch (backing) { + .chip => |c| c, + .board => |b| b.chip, + }; + + const has_board = (backing == .board); + + const chip_package = Pkg{ + .name = "chip", + .path = .{ .path = chip.path }, + .dependencies = &[_]Pkg{ + microzig_base, + pkgs.mmio, + Pkg{ + .name = "cpu", + .path = .{ .path = chip.cpu.path }, + .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, + }, + }, + }; + + const config_file_name = blk: { + const hash = hash_blk: { + var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); + + hasher.update(chip.name); + hasher.update(chip.path); + hasher.update(chip.cpu.name); + hasher.update(chip.cpu.path); + + if (backing == .board) { + hasher.update(backing.board.name); + hasher.update(backing.board.path); + } + + var mac: [16]u8 = undefined; + hasher.final(&mac); + break :hash_blk mac; + }; + + const file_prefix = "zig-cache/microzig/config-"; + const file_suffix = ".zig"; + + var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; + const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + file_prefix, + std.fmt.fmtSliceHexLower(&hash), + file_suffix, + }); + + break :blk builder.dupe(filename); + }; + + { + std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; + var config_file = try std.fs.cwd().createFile(config_file_name, .{}); + defer config_file.close(); + + var writer = config_file.writer(); + try writer.print("pub const has_board = {};\n", .{has_board}); + if (has_board) + try writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}); + + try writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}); + try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); + } + + const config_pkg = Pkg{ + .name = "microzig-config", + .path = .{ .path = config_file_name }, + }; + + const linkerscript = try LinkerScriptStep.create(builder, chip); + const exe = builder.addExecutable(name, source); + + // might not be true for all machines (Pi Pico), but + // for the HAL it's true (it doesn't know the concept of threading) + exe.single_threaded = true; + exe.setTarget(chip.cpu.target); + + exe.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + + // TODO: + // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. + // - This requires building another tool that runs on the host that compiles those files and emits the linker script. + // - src/tools/linkerscript-gen.zig is the source file for this + + exe.bundle_compiler_rt = false; + + switch (backing) { + .chip => { + exe.addPackage(Pkg{ + .name = microzig_base.name, + .path = microzig_base.path, + .dependencies = &[_]Pkg{ config_pkg, chip_package }, + }); + }, + .board => |board| { + exe.addPackage(Pkg{ + .name = microzig_base.name, + .path = microzig_base.path, + .dependencies = &[_]Pkg{ + config_pkg, + chip_package, + Pkg{ + .name = "board", + .path = .{ .path = board.path }, + .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio }, + }, + }, + }); + }, + } + return exe; +} + +const pkgs = struct { + const mmio = std.build.Pkg{ + .name = "microzig-mmio", + .path = .{ .path = root_path ++ "core/mmio.zig" }, + }; +}; diff --git a/src/modules/Board.zig b/src/modules/Board.zig new file mode 100644 index 0000000..8074bb6 --- /dev/null +++ b/src/modules/Board.zig @@ -0,0 +1,5 @@ +const Chip = @import("Chip.zig"); + +name: []const u8, +path: []const u8, +chip: Chip, diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig new file mode 100644 index 0000000..1df23e9 --- /dev/null +++ b/src/modules/Chip.zig @@ -0,0 +1,7 @@ +const MemoryRegion = @import("MemoryRegion.zig"); +const Cpu = @import("Cpu.zig"); + +name: []const u8, +path: []const u8, +cpu: Cpu, +memory_regions: []const MemoryRegion, diff --git a/src/modules/Cpu.zig b/src/modules/Cpu.zig new file mode 100644 index 0000000..0f06a77 --- /dev/null +++ b/src/modules/Cpu.zig @@ -0,0 +1,5 @@ +const std = @import("std"); + +name: []const u8, +path: []const u8, +target: std.zig.CrossTarget, diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig index 92f42f7..9357af6 100644 --- a/src/modules/LinkerScriptStep.zig +++ b/src/modules/LinkerScriptStep.zig @@ -1,6 +1,6 @@ const std = @import("std"); const MemoryRegion = @import("MemoryRegion.zig"); -const Chip = @import("chips.zig").Chip; +const Chip = @import("Chip.zig"); const Step = std.build.Step; const Builder = std.build.Builder; const GeneratedFile = std.build.GeneratedFile; diff --git a/src/modules/boards.zig b/src/modules/boards.zig index c435044..f68ce1c 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -1,20 +1,21 @@ +const std = @import("std"); const chips = @import("chips.zig"); +const Board = @import("Board.zig"); -const Chip = chips.Chip; -pub const Board = struct { - name: []const u8, - path: []const u8, - chip: Chip, -}; +fn root() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +const root_path = root() ++ "/"; pub const arduino_nano = Board{ .name = "Arduino Nano", - .path = "src/modules/boards/arduino-nano/arduino-nano.zig", + .path = root_path ++ "boards/arduino-nano/arduino-nano.zig", .chip = chips.atmega328p, }; pub const mbed_lpc1768 = Board{ .name = "mbed LPC1768", - .path = "src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig", + .path = root_path ++ "boards/mbed-lpc1768/mbed-lpc1768.zig", .chip = chips.lpc1768, }; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index c736d38..d4baf93 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -1,5 +1,6 @@ const std = @import("std"); const cpus = @import("cpus.zig"); +const Chip = @import("Chip.zig"); const MemoryRegion = @import("MemoryRegion.zig"); fn root() []const u8 { @@ -8,18 +9,11 @@ fn root() []const u8 { const root_path = root() ++ "/"; -pub const Chip = struct { - name: []const u8, - path: []const u8, - cpu: cpus.Cpu, - memory_regions: []const MemoryRegion, -}; - pub const atmega328p = Chip{ .name = "ATmega328p", .path = root_path ++ "chips/atmega328p/atmega328p.zig", .cpu = cpus.avr5, - .memory_regions = &[_]MemoryRegion{ + .memory_regions = &.{ MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, }, @@ -29,9 +23,19 @@ pub const lpc1768 = Chip{ .name = "NXP LPC1768", .path = root_path ++ "chips/lpc1768/lpc1768.zig", .cpu = cpus.cortex_m3, - .memory_regions = &[_]MemoryRegion{ + .memory_regions = &.{ MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, }, }; + +pub const stm32f103x8 = Chip{ + .name = "STM32F103x8", + .path = root_path ++ "chips/stm32f103/stm32f103.zig", + .cpu = cpus.cortex_m3, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x10000000, .length = 20 * 1024, .kind = .ram }, + }, +}; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig new file mode 100644 index 0000000..2fb9d71 --- /dev/null +++ b/src/modules/chips/stm32f103/registers.zig @@ -0,0 +1,17773 @@ +// generated using svd2zig.py +// DO NOT EDIT +// based on STM32F103xx version 1.3 +const mmio = @import("microzig-mmio").mmio; +const Name = "STM32F103xx"; +pub const FSMC = extern struct { + pub const Address: u32 = 0xa0000000; + // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + reserved2: u1 = 0, + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 PC Card/NAND Flash control register 2 + pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { + reserved1: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN + reserved3: u1 = 0, + reserved2: u1 = 0, + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 100 FIFO status and interrupt register 2 + pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 104 Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx + }); + // byte offset: 108 Attribute memory space timing register 2 + pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: Attribute memory x setup time + ATTWAITx: u8, // bit offset: 8 desc: Attribute memory x wait time + ATTHOLDx: u8, // bit offset: 16 desc: Attribute memory x hold time + ATTHIZx: u8, // bit offset: 24 desc: Attribute memory x databus HiZ time + }); + // byte offset: 116 ECC result register 2 + pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { + ECCx: u32, // bit offset: 0 desc: ECC result + }); + // byte offset: 128 PC Card/NAND Flash control register 3 + pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { + reserved1: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN + reserved3: u1 = 0, + reserved2: u1 = 0, + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 FIFO status and interrupt register 3 + pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx + }); + // byte offset: 140 Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: ATTSETx + ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx + ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx + ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx + }); + // byte offset: 148 ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { + ECCx: u32, // bit offset: 0 desc: ECCx + }); + // byte offset: 160 PC Card/NAND Flash control register 4 + pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN + reserved3: u1 = 0, + reserved2: u1 = 0, + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 FIFO status and interrupt register 4 + pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 168 Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx + }); + // byte offset: 172 Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: ATTSETx + ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx + ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx + ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx + }); + // byte offset: 176 I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { + IOSETx: u8, // bit offset: 0 desc: IOSETx + IOWAITx: u8, // bit offset: 8 desc: IOWAITx + IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx + IOHIZx: u8, // bit offset: 24 desc: IOHIZx + }); + // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const PWR = extern struct { + pub const Address: u32 = 0x40007000; + // byte offset: 0 Power control register (PWR_CR) + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + LPDS: u1, // bit offset: 0 desc: Low Power Deep Sleep + PDDS: u1, // bit offset: 1 desc: Power Down Deep Sleep + CWUF: u1, // bit offset: 2 desc: Clear Wake-up Flag + CSBF: u1, // bit offset: 3 desc: Clear STANDBY Flag + PVDE: u1, // bit offset: 4 desc: Power Voltage Detector Enable + PLS: u3, // bit offset: 5 desc: PVD Level Selection + DBP: u1, // bit offset: 8 desc: Disable Backup Domain write protection + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Power control register (PWR_CR) + pub const CSR = mmio(Address + 0x00000004, 32, packed struct { + WUF: u1, // bit offset: 0 desc: Wake-Up Flag + SBF: u1, // bit offset: 1 desc: STANDBY Flag + PVDO: u1, // bit offset: 2 desc: PVD Output + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + EWUP: u1, // bit offset: 8 desc: Enable WKUP pin + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const RCC = extern struct { + pub const Address: u32 = 0x40021000; + // byte offset: 0 Clock control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable + HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag + reserved1: u1 = 0, + HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming + HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration + HSEON: u1, // bit offset: 16 desc: External High Speed clock enable + HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag + HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass + CSSON: u1, // bit offset: 19 desc: Clock Security System enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + PLLON: u1, // bit offset: 24 desc: PLL enable + PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Clock configuration register (RCC_CFGR) + pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { + SW: u2, // bit offset: 0 desc: System clock Switch + SWS: u2, // bit offset: 2 desc: System Clock Switch Status + HPRE: u4, // bit offset: 4 desc: AHB prescaler + PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) + PPRE2: u3, // bit offset: 11 desc: APB High speed prescaler (APB2) + ADCPRE: u2, // bit offset: 14 desc: ADC prescaler + PLLSRC: u1, // bit offset: 16 desc: PLL entry clock source + PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry + PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor + OTGFSPRE: u1, // bit offset: 22 desc: USB OTG FS prescaler + reserved1: u1 = 0, + MCO: u3, // bit offset: 24 desc: Microcontroller clock output + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Clock interrupt register (RCC_CIR) + pub const CIR = mmio(Address + 0x00000008, 32, packed struct { + LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag + LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag + HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag + HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag + PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag + reserved2: u1 = 0, + reserved1: u1 = 0, + CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag + LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable + LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable + HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable + HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable + PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear + LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear + HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear + HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear + PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + reserved7: u1 = 0, + reserved6: u1 = 0, + CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { + AFIORST: u1, // bit offset: 0 desc: Alternate function I/O reset + reserved1: u1 = 0, + IOPARST: u1, // bit offset: 2 desc: IO port A reset + IOPBRST: u1, // bit offset: 3 desc: IO port B reset + IOPCRST: u1, // bit offset: 4 desc: IO port C reset + IOPDRST: u1, // bit offset: 5 desc: IO port D reset + IOPERST: u1, // bit offset: 6 desc: IO port E reset + IOPFRST: u1, // bit offset: 7 desc: IO port F reset + IOPGRST: u1, // bit offset: 8 desc: IO port G reset + ADC1RST: u1, // bit offset: 9 desc: ADC 1 interface reset + ADC2RST: u1, // bit offset: 10 desc: ADC 2 interface reset + TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset + SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset + TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset + USART1RST: u1, // bit offset: 14 desc: USART1 reset + ADC3RST: u1, // bit offset: 15 desc: ADC 3 interface reset + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TIM9RST: u1, // bit offset: 19 desc: TIM9 timer reset + TIM10RST: u1, // bit offset: 20 desc: TIM10 timer reset + TIM11RST: u1, // bit offset: 21 desc: TIM11 timer reset + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { + TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset + TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset + TIM4RST: u1, // bit offset: 2 desc: Timer 4 reset + TIM5RST: u1, // bit offset: 3 desc: Timer 5 reset + TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset + TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset + TIM12RST: u1, // bit offset: 6 desc: Timer 12 reset + TIM13RST: u1, // bit offset: 7 desc: Timer 13 reset + TIM14RST: u1, // bit offset: 8 desc: Timer 14 reset + reserved2: u1 = 0, + reserved1: u1 = 0, + WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + reserved4: u1 = 0, + reserved3: u1 = 0, + SPI2RST: u1, // bit offset: 14 desc: SPI2 reset + SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + reserved5: u1 = 0, + USART2RST: u1, // bit offset: 17 desc: USART 2 reset + USART3RST: u1, // bit offset: 18 desc: USART 3 reset + UART4RST: u1, // bit offset: 19 desc: UART 4 reset + UART5RST: u1, // bit offset: 20 desc: UART 5 reset + I2C1RST: u1, // bit offset: 21 desc: I2C1 reset + I2C2RST: u1, // bit offset: 22 desc: I2C2 reset + USBRST: u1, // bit offset: 23 desc: USB reset + reserved6: u1 = 0, + CANRST: u1, // bit offset: 25 desc: CAN reset + reserved7: u1 = 0, + BKPRST: u1, // bit offset: 27 desc: Backup interface reset + PWRRST: u1, // bit offset: 28 desc: Power interface reset + DACRST: u1, // bit offset: 29 desc: DAC interface reset + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { + DMA1EN: u1, // bit offset: 0 desc: DMA1 clock enable + DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable + SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable + reserved1: u1 = 0, + FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable + reserved2: u1 = 0, + CRCEN: u1, // bit offset: 6 desc: CRC clock enable + reserved3: u1 = 0, + FSMCEN: u1, // bit offset: 8 desc: FSMC clock enable + reserved4: u1 = 0, + SDIOEN: u1, // bit offset: 10 desc: SDIO clock enable + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { + AFIOEN: u1, // bit offset: 0 desc: Alternate function I/O clock enable + reserved1: u1 = 0, + IOPAEN: u1, // bit offset: 2 desc: I/O port A clock enable + IOPBEN: u1, // bit offset: 3 desc: I/O port B clock enable + IOPCEN: u1, // bit offset: 4 desc: I/O port C clock enable + IOPDEN: u1, // bit offset: 5 desc: I/O port D clock enable + IOPEEN: u1, // bit offset: 6 desc: I/O port E clock enable + IOPFEN: u1, // bit offset: 7 desc: I/O port F clock enable + IOPGEN: u1, // bit offset: 8 desc: I/O port G clock enable + ADC1EN: u1, // bit offset: 9 desc: ADC 1 interface clock enable + ADC2EN: u1, // bit offset: 10 desc: ADC 2 interface clock enable + TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable + SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable + TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable + USART1EN: u1, // bit offset: 14 desc: USART1 clock enable + ADC3EN: u1, // bit offset: 15 desc: ADC3 interface clock enable + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TIM9EN: u1, // bit offset: 19 desc: TIM9 Timer clock enable + TIM10EN: u1, // bit offset: 20 desc: TIM10 Timer clock enable + TIM11EN: u1, // bit offset: 21 desc: TIM11 Timer clock enable + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { + TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable + TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable + TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable + TIM5EN: u1, // bit offset: 3 desc: Timer 5 clock enable + TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable + TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable + TIM12EN: u1, // bit offset: 6 desc: Timer 12 clock enable + TIM13EN: u1, // bit offset: 7 desc: Timer 13 clock enable + TIM14EN: u1, // bit offset: 8 desc: Timer 14 clock enable + reserved2: u1 = 0, + reserved1: u1 = 0, + WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + reserved4: u1 = 0, + reserved3: u1 = 0, + SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable + SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + reserved5: u1 = 0, + USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable + USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable + UART4EN: u1, // bit offset: 19 desc: UART 4 clock enable + UART5EN: u1, // bit offset: 20 desc: UART 5 clock enable + I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable + I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable + USBEN: u1, // bit offset: 23 desc: USB clock enable + reserved6: u1 = 0, + CANEN: u1, // bit offset: 25 desc: CAN clock enable + reserved7: u1 = 0, + BKPEN: u1, // bit offset: 27 desc: Backup interface clock enable + PWREN: u1, // bit offset: 28 desc: Power interface clock enable + DACEN: u1, // bit offset: 29 desc: DAC interface clock enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Backup domain control register (RCC_BDCR) + pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { + LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable + LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready + LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + RTCEN: u1, // bit offset: 15 desc: RTC clock enable + BDRST: u1, // bit offset: 16 desc: Backup domain software reset + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Control/status register (RCC_CSR) + pub const CSR = mmio(Address + 0x00000024, 32, packed struct { + LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable + LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RMVF: u1, // bit offset: 24 desc: Remove reset flag + reserved23: u1 = 0, + PINRSTF: u1, // bit offset: 26 desc: PIN reset flag + PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag + SFTRSTF: u1, // bit offset: 28 desc: Software reset flag + IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag + WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag + LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + }); +}; +pub const GPIOA = extern struct { + pub const Address: u32 = 0x40010800; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOB = extern struct { + pub const Address: u32 = 0x40010c00; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOC = extern struct { + pub const Address: u32 = 0x40011000; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOD = extern struct { + pub const Address: u32 = 0x40011400; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOE = extern struct { + pub const Address: u32 = 0x40011800; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOF = extern struct { + pub const Address: u32 = 0x40011c00; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOG = extern struct { + pub const Address: u32 = 0x40012000; + // byte offset: 0 Port configuration register low (GPIOn_CRL) + pub const CRL = mmio(Address + 0x00000000, 32, packed struct { + MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits + CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits + MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits + CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits + MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits + CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits + MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits + CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits + MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits + CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits + MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits + CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits + MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits + CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits + MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits + CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits + }); + // byte offset: 4 Port configuration register high (GPIOn_CRL) + pub const CRH = mmio(Address + 0x00000004, 32, packed struct { + MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits + CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits + MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits + CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits + MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits + CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits + MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits + CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits + MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits + CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits + MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits + CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits + MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits + CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits + MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits + CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits + }); + // byte offset: 8 Port input data register (GPIOn_IDR) + pub const IDR = mmio(Address + 0x00000008, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data + IDR1: u1, // bit offset: 1 desc: Port input data + IDR2: u1, // bit offset: 2 desc: Port input data + IDR3: u1, // bit offset: 3 desc: Port input data + IDR4: u1, // bit offset: 4 desc: Port input data + IDR5: u1, // bit offset: 5 desc: Port input data + IDR6: u1, // bit offset: 6 desc: Port input data + IDR7: u1, // bit offset: 7 desc: Port input data + IDR8: u1, // bit offset: 8 desc: Port input data + IDR9: u1, // bit offset: 9 desc: Port input data + IDR10: u1, // bit offset: 10 desc: Port input data + IDR11: u1, // bit offset: 11 desc: Port input data + IDR12: u1, // bit offset: 12 desc: Port input data + IDR13: u1, // bit offset: 13 desc: Port input data + IDR14: u1, // bit offset: 14 desc: Port input data + IDR15: u1, // bit offset: 15 desc: Port input data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Port output data register (GPIOn_ODR) + pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data + ODR1: u1, // bit offset: 1 desc: Port output data + ODR2: u1, // bit offset: 2 desc: Port output data + ODR3: u1, // bit offset: 3 desc: Port output data + ODR4: u1, // bit offset: 4 desc: Port output data + ODR5: u1, // bit offset: 5 desc: Port output data + ODR6: u1, // bit offset: 6 desc: Port output data + ODR7: u1, // bit offset: 7 desc: Port output data + ODR8: u1, // bit offset: 8 desc: Port output data + ODR9: u1, // bit offset: 9 desc: Port output data + ODR10: u1, // bit offset: 10 desc: Port output data + ODR11: u1, // bit offset: 11 desc: Port output data + ODR12: u1, // bit offset: 12 desc: Port output data + ODR13: u1, // bit offset: 13 desc: Port output data + ODR14: u1, // bit offset: 14 desc: Port output data + ODR15: u1, // bit offset: 15 desc: Port output data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Set bit 0 + BS1: u1, // bit offset: 1 desc: Set bit 1 + BS2: u1, // bit offset: 2 desc: Set bit 1 + BS3: u1, // bit offset: 3 desc: Set bit 3 + BS4: u1, // bit offset: 4 desc: Set bit 4 + BS5: u1, // bit offset: 5 desc: Set bit 5 + BS6: u1, // bit offset: 6 desc: Set bit 6 + BS7: u1, // bit offset: 7 desc: Set bit 7 + BS8: u1, // bit offset: 8 desc: Set bit 8 + BS9: u1, // bit offset: 9 desc: Set bit 9 + BS10: u1, // bit offset: 10 desc: Set bit 10 + BS11: u1, // bit offset: 11 desc: Set bit 11 + BS12: u1, // bit offset: 12 desc: Set bit 12 + BS13: u1, // bit offset: 13 desc: Set bit 13 + BS14: u1, // bit offset: 14 desc: Set bit 14 + BS15: u1, // bit offset: 15 desc: Set bit 15 + BR0: u1, // bit offset: 16 desc: Reset bit 0 + BR1: u1, // bit offset: 17 desc: Reset bit 1 + BR2: u1, // bit offset: 18 desc: Reset bit 2 + BR3: u1, // bit offset: 19 desc: Reset bit 3 + BR4: u1, // bit offset: 20 desc: Reset bit 4 + BR5: u1, // bit offset: 21 desc: Reset bit 5 + BR6: u1, // bit offset: 22 desc: Reset bit 6 + BR7: u1, // bit offset: 23 desc: Reset bit 7 + BR8: u1, // bit offset: 24 desc: Reset bit 8 + BR9: u1, // bit offset: 25 desc: Reset bit 9 + BR10: u1, // bit offset: 26 desc: Reset bit 10 + BR11: u1, // bit offset: 27 desc: Reset bit 11 + BR12: u1, // bit offset: 28 desc: Reset bit 12 + BR13: u1, // bit offset: 29 desc: Reset bit 13 + BR14: u1, // bit offset: 30 desc: Reset bit 14 + BR15: u1, // bit offset: 31 desc: Reset bit 15 + }); + // byte offset: 20 Port bit reset register (GPIOn_BRR) + pub const BRR = mmio(Address + 0x00000014, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Reset bit 0 + BR1: u1, // bit offset: 1 desc: Reset bit 1 + BR2: u1, // bit offset: 2 desc: Reset bit 1 + BR3: u1, // bit offset: 3 desc: Reset bit 3 + BR4: u1, // bit offset: 4 desc: Reset bit 4 + BR5: u1, // bit offset: 5 desc: Reset bit 5 + BR6: u1, // bit offset: 6 desc: Reset bit 6 + BR7: u1, // bit offset: 7 desc: Reset bit 7 + BR8: u1, // bit offset: 8 desc: Reset bit 8 + BR9: u1, // bit offset: 9 desc: Reset bit 9 + BR10: u1, // bit offset: 10 desc: Reset bit 10 + BR11: u1, // bit offset: 11 desc: Reset bit 11 + BR12: u1, // bit offset: 12 desc: Reset bit 12 + BR13: u1, // bit offset: 13 desc: Reset bit 13 + BR14: u1, // bit offset: 14 desc: Reset bit 14 + BR15: u1, // bit offset: 15 desc: Reset bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Port configuration lock register + pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 + LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 + LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 + LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 + LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 + LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 + LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 + LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 + LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 + LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 + LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 + LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 + LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 + LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 + LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 + LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 + LCKK: u1, // bit offset: 16 desc: Lock key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const AFIO = extern struct { + pub const Address: u32 = 0x40010000; + // byte offset: 0 Event Control Register (AFIO_EVCR) + pub const EVCR = mmio(Address + 0x00000000, 32, packed struct { + PIN: u4, // bit offset: 0 desc: Pin selection + PORT: u3, // bit offset: 4 desc: Port selection + EVOE: u1, // bit offset: 7 desc: Event Output Enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 AF remap and debug I/O configuration register (AFIO_MAPR) + pub const MAPR = mmio(Address + 0x00000004, 32, packed struct { + SPI1_REMAP: u1, // bit offset: 0 desc: SPI1 remapping + I2C1_REMAP: u1, // bit offset: 1 desc: I2C1 remapping + USART1_REMAP: u1, // bit offset: 2 desc: USART1 remapping + USART2_REMAP: u1, // bit offset: 3 desc: USART2 remapping + USART3_REMAP: u2, // bit offset: 4 desc: USART3 remapping + TIM1_REMAP: u2, // bit offset: 6 desc: TIM1 remapping + TIM2_REMAP: u2, // bit offset: 8 desc: TIM2 remapping + TIM3_REMAP: u2, // bit offset: 10 desc: TIM3 remapping + TIM4_REMAP: u1, // bit offset: 12 desc: TIM4 remapping + CAN_REMAP: u2, // bit offset: 13 desc: CAN1 remapping + PD01_REMAP: u1, // bit offset: 15 desc: Port D0/Port D1 mapping on OSCIN/OSCOUT + TIM5CH4_IREMAP: u1, // bit offset: 16 desc: Set and cleared by software + ADC1_ETRGINJ_REMAP: u1, // bit offset: 17 desc: ADC 1 External trigger injected conversion remapping + ADC1_ETRGREG_REMAP: u1, // bit offset: 18 desc: ADC 1 external trigger regular conversion remapping + ADC2_ETRGINJ_REMAP: u1, // bit offset: 19 desc: ADC 2 external trigger injected conversion remapping + ADC2_ETRGREG_REMAP: u1, // bit offset: 20 desc: ADC 2 external trigger regular conversion remapping + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SWJ_CFG: u3, // bit offset: 24 desc: Serial wire JTAG configuration + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 External interrupt configuration register 1 (AFIO_EXTICR1) + pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { + EXTI0: u4, // bit offset: 0 desc: EXTI0 configuration + EXTI1: u4, // bit offset: 4 desc: EXTI1 configuration + EXTI2: u4, // bit offset: 8 desc: EXTI2 configuration + EXTI3: u4, // bit offset: 12 desc: EXTI3 configuration + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 External interrupt configuration register 2 (AFIO_EXTICR2) + pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { + EXTI4: u4, // bit offset: 0 desc: EXTI4 configuration + EXTI5: u4, // bit offset: 4 desc: EXTI5 configuration + EXTI6: u4, // bit offset: 8 desc: EXTI6 configuration + EXTI7: u4, // bit offset: 12 desc: EXTI7 configuration + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 External interrupt configuration register 3 (AFIO_EXTICR3) + pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { + EXTI8: u4, // bit offset: 0 desc: EXTI8 configuration + EXTI9: u4, // bit offset: 4 desc: EXTI9 configuration + EXTI10: u4, // bit offset: 8 desc: EXTI10 configuration + EXTI11: u4, // bit offset: 12 desc: EXTI11 configuration + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 External interrupt configuration register 4 (AFIO_EXTICR4) + pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { + EXTI12: u4, // bit offset: 0 desc: EXTI12 configuration + EXTI13: u4, // bit offset: 4 desc: EXTI13 configuration + EXTI14: u4, // bit offset: 8 desc: EXTI14 configuration + EXTI15: u4, // bit offset: 12 desc: EXTI15 configuration + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 AF remap and debug I/O configuration register + pub const MAPR2 = mmio(Address + 0x0000001c, 32, packed struct { + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIM9_REMAP: u1, // bit offset: 5 desc: TIM9 remapping + TIM10_REMAP: u1, // bit offset: 6 desc: TIM10 remapping + TIM11_REMAP: u1, // bit offset: 7 desc: TIM11 remapping + TIM13_REMAP: u1, // bit offset: 8 desc: TIM13 remapping + TIM14_REMAP: u1, // bit offset: 9 desc: TIM14 remapping + FSMC_NADV: u1, // bit offset: 10 desc: NADV connect/disconnect + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const EXTI = extern struct { + pub const Address: u32 = 0x40010400; + // byte offset: 0 Interrupt mask register (EXTI_IMR) + pub const IMR = mmio(Address + 0x00000000, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 + MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 + MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 + MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 + MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 + MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 + MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 + MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 + MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 + MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 + MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 + MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 + MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 + MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 + MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 + MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 + MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 + MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 + MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Event mask register (EXTI_EMR) + pub const EMR = mmio(Address + 0x00000004, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Event Mask on line 0 + MR1: u1, // bit offset: 1 desc: Event Mask on line 1 + MR2: u1, // bit offset: 2 desc: Event Mask on line 2 + MR3: u1, // bit offset: 3 desc: Event Mask on line 3 + MR4: u1, // bit offset: 4 desc: Event Mask on line 4 + MR5: u1, // bit offset: 5 desc: Event Mask on line 5 + MR6: u1, // bit offset: 6 desc: Event Mask on line 6 + MR7: u1, // bit offset: 7 desc: Event Mask on line 7 + MR8: u1, // bit offset: 8 desc: Event Mask on line 8 + MR9: u1, // bit offset: 9 desc: Event Mask on line 9 + MR10: u1, // bit offset: 10 desc: Event Mask on line 10 + MR11: u1, // bit offset: 11 desc: Event Mask on line 11 + MR12: u1, // bit offset: 12 desc: Event Mask on line 12 + MR13: u1, // bit offset: 13 desc: Event Mask on line 13 + MR14: u1, // bit offset: 14 desc: Event Mask on line 14 + MR15: u1, // bit offset: 15 desc: Event Mask on line 15 + MR16: u1, // bit offset: 16 desc: Event Mask on line 16 + MR17: u1, // bit offset: 17 desc: Event Mask on line 17 + MR18: u1, // bit offset: 18 desc: Event Mask on line 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Rising Trigger selection register (EXTI_RTSR) + pub const RTSR = mmio(Address + 0x00000008, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Falling Trigger selection register (EXTI_FTSR) + pub const FTSR = mmio(Address + 0x0000000c, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Software interrupt event register (EXTI_SWIER) + pub const SWIER = mmio(Address + 0x00000010, 32, packed struct { + SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 + SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 + SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 + SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 + SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 + SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 + SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 + SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 + SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 + SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 + SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 + SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 + SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 + SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 + SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 + SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 + SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 + SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 + SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Pending register (EXTI_PR) + pub const PR = mmio(Address + 0x00000014, 32, packed struct { + PR0: u1, // bit offset: 0 desc: Pending bit 0 + PR1: u1, // bit offset: 1 desc: Pending bit 1 + PR2: u1, // bit offset: 2 desc: Pending bit 2 + PR3: u1, // bit offset: 3 desc: Pending bit 3 + PR4: u1, // bit offset: 4 desc: Pending bit 4 + PR5: u1, // bit offset: 5 desc: Pending bit 5 + PR6: u1, // bit offset: 6 desc: Pending bit 6 + PR7: u1, // bit offset: 7 desc: Pending bit 7 + PR8: u1, // bit offset: 8 desc: Pending bit 8 + PR9: u1, // bit offset: 9 desc: Pending bit 9 + PR10: u1, // bit offset: 10 desc: Pending bit 10 + PR11: u1, // bit offset: 11 desc: Pending bit 11 + PR12: u1, // bit offset: 12 desc: Pending bit 12 + PR13: u1, // bit offset: 13 desc: Pending bit 13 + PR14: u1, // bit offset: 14 desc: Pending bit 14 + PR15: u1, // bit offset: 15 desc: Pending bit 15 + PR16: u1, // bit offset: 16 desc: Pending bit 16 + PR17: u1, // bit offset: 17 desc: Pending bit 17 + PR18: u1, // bit offset: 18 desc: Pending bit 18 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DMA1 = extern struct { + pub const Address: u32 = 0x40020000; + // byte offset: 0 DMA interrupt status register (DMA_ISR) + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag + TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag + HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag + TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag + GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag + TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag + HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag + TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag + GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag + TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag + HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag + TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag + GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag + TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag + HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag + TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag + GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag + TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag + HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag + TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag + GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag + TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag + HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag + TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag + GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag + TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag + HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag + TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { + CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear + CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear + CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear + CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear + CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear + CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear + CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear + CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear + CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear + CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear + CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear + CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear + CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear + CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear + CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear + CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear + CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear + CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear + CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear + CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear + CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear + CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear + CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear + CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear + CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear + CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear + CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear + CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA channel 1 number of data register + pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DMA channel 1 peripheral address register + pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 20 DMA channel 1 memory address register + pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 28 DMA channel configuration register (DMA_CCR) + pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 DMA channel 2 number of data register + pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DMA channel 2 peripheral address register + pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 40 DMA channel 2 memory address register + pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 48 DMA channel configuration register (DMA_CCR) + pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 DMA channel 3 number of data register + pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 DMA channel 3 peripheral address register + pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 60 DMA channel 3 memory address register + pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 68 DMA channel configuration register (DMA_CCR) + pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA channel 4 number of data register + pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA channel 4 peripheral address register + pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 80 DMA channel 4 memory address register + pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 88 DMA channel configuration register (DMA_CCR) + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 DMA channel 5 number of data register + pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 DMA channel 5 peripheral address register + pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 100 DMA channel 5 memory address register + pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 108 DMA channel configuration register (DMA_CCR) + pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 DMA channel 6 number of data register + pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 DMA channel 6 peripheral address register + pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 120 DMA channel 6 memory address register + pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 128 DMA channel configuration register (DMA_CCR) + pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 DMA channel 7 number of data register + pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 DMA channel 7 peripheral address register + pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 140 DMA channel 7 memory address register + pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); +}; +pub const DMA2 = extern struct { + pub const Address: u32 = 0x40020400; + // byte offset: 0 DMA interrupt status register (DMA_ISR) + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag + TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag + HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag + TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag + GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag + TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag + HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag + TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag + GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag + TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag + HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag + TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag + GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag + TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag + HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag + TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag + GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag + TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag + HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag + TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag + GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag + TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag + HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag + TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag + GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag + TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag + HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag + TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { + CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear + CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear + CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear + CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear + CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear + CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear + CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear + CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear + CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear + CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear + CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear + CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear + CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear + CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear + CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear + CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear + CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear + CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear + CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear + CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear + CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear + CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear + CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear + CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear + CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear + CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear + CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear + CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA channel 1 number of data register + pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DMA channel 1 peripheral address register + pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 20 DMA channel 1 memory address register + pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 28 DMA channel configuration register (DMA_CCR) + pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 DMA channel 2 number of data register + pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DMA channel 2 peripheral address register + pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 40 DMA channel 2 memory address register + pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 48 DMA channel configuration register (DMA_CCR) + pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 DMA channel 3 number of data register + pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 DMA channel 3 peripheral address register + pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 60 DMA channel 3 memory address register + pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 68 DMA channel configuration register (DMA_CCR) + pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA channel 4 number of data register + pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA channel 4 peripheral address register + pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 80 DMA channel 4 memory address register + pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 88 DMA channel configuration register (DMA_CCR) + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 DMA channel 5 number of data register + pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 DMA channel 5 peripheral address register + pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 100 DMA channel 5 memory address register + pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 108 DMA channel configuration register (DMA_CCR) + pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 DMA channel 6 number of data register + pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 DMA channel 6 peripheral address register + pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 120 DMA channel 6 memory address register + pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 128 DMA channel configuration register (DMA_CCR) + pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 DMA channel 7 number of data register + pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 DMA channel 7 peripheral address register + pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 140 DMA channel 7 memory address register + pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); +}; +pub const SDIO = extern struct { + pub const Address: u32 = 0x40018000; + // byte offset: 0 Bits 1:0 = PWRCTRL: Power supply control bits + pub const POWER = mmio(Address + 0x00000000, 32, packed struct { + PWRCTRL: u2, // bit offset: 0 desc: PWRCTRL + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 SDI clock control register (SDIO_CLKCR) + pub const CLKCR = mmio(Address + 0x00000004, 32, packed struct { + CLKDIV: u8, // bit offset: 0 desc: Clock divide factor + CLKEN: u1, // bit offset: 8 desc: Clock enable bit + PWRSAV: u1, // bit offset: 9 desc: Power saving configuration bit + BYPASS: u1, // bit offset: 10 desc: Clock divider bypass enable bit + WIDBUS: u2, // bit offset: 11 desc: Wide bus mode enable bit + NEGEDGE: u1, // bit offset: 13 desc: SDIO_CK dephasing selection bit + HWFC_EN: u1, // bit offset: 14 desc: HW Flow Control enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Bits 31:0 = : Command argument + pub const ARG = mmio(Address + 0x00000008, 32, packed struct { + CMDARG: u32, // bit offset: 0 desc: Command argument + }); + // byte offset: 12 SDIO command register (SDIO_CMD) + pub const CMD = mmio(Address + 0x0000000c, 32, packed struct { + CMDINDEX: u6, // bit offset: 0 desc: CMDINDEX + WAITRESP: u2, // bit offset: 6 desc: WAITRESP + WAITINT: u1, // bit offset: 8 desc: WAITINT + WAITPEND: u1, // bit offset: 9 desc: WAITPEND + CPSMEN: u1, // bit offset: 10 desc: CPSMEN + SDIOSuspend: u1, // bit offset: 11 desc: SDIOSuspend + ENCMDcompl: u1, // bit offset: 12 desc: ENCMDcompl + nIEN: u1, // bit offset: 13 desc: nIEN + CE_ATACMD: u1, // bit offset: 14 desc: CE_ATACMD + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SDIO command register + pub const RESPCMD = mmio(Address + 0x00000010, 32, packed struct { + RESPCMD: u6, // bit offset: 0 desc: RESPCMD + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Bits 31:0 = CARDSTATUS1 + pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct { + CARDSTATUS1: u32, // bit offset: 0 desc: CARDSTATUS1 + }); + // byte offset: 24 Bits 31:0 = CARDSTATUS2 + pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct { + CARDSTATUS2: u32, // bit offset: 0 desc: CARDSTATUS2 + }); + // byte offset: 28 Bits 31:0 = CARDSTATUS3 + pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct { + CARDSTATUS3: u32, // bit offset: 0 desc: CARDSTATUS3 + }); + // byte offset: 32 Bits 31:0 = CARDSTATUS4 + pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct { + CARDSTATUS4: u32, // bit offset: 0 desc: CARDSTATUS4 + }); + // byte offset: 36 Bits 31:0 = DATATIME: Data timeout period + pub const DTIMER = mmio(Address + 0x00000024, 32, packed struct { + DATATIME: u32, // bit offset: 0 desc: Data timeout period + }); + // byte offset: 40 Bits 24:0 = DATALENGTH: Data length value + pub const DLEN = mmio(Address + 0x00000028, 32, packed struct { + DATALENGTH: u25, // bit offset: 0 desc: Data length value + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 SDIO data control register (SDIO_DCTRL) + pub const DCTRL = mmio(Address + 0x0000002c, 32, packed struct { + DTEN: u1, // bit offset: 0 desc: DTEN + DTDIR: u1, // bit offset: 1 desc: DTDIR + DTMODE: u1, // bit offset: 2 desc: DTMODE + DMAEN: u1, // bit offset: 3 desc: DMAEN + DBLOCKSIZE: u4, // bit offset: 4 desc: DBLOCKSIZE + PWSTART: u1, // bit offset: 8 desc: PWSTART + PWSTOP: u1, // bit offset: 9 desc: PWSTOP + RWMOD: u1, // bit offset: 10 desc: RWMOD + SDIOEN: u1, // bit offset: 11 desc: SDIOEN + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Bits 24:0 = DATACOUNT: Data count value + pub const DCOUNT = mmio(Address + 0x00000030, 32, packed struct { + DATACOUNT: u25, // bit offset: 0 desc: Data count value + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 SDIO status register (SDIO_STA) + pub const STA = mmio(Address + 0x00000034, 32, packed struct { + CCRCFAIL: u1, // bit offset: 0 desc: CCRCFAIL + DCRCFAIL: u1, // bit offset: 1 desc: DCRCFAIL + CTIMEOUT: u1, // bit offset: 2 desc: CTIMEOUT + DTIMEOUT: u1, // bit offset: 3 desc: DTIMEOUT + TXUNDERR: u1, // bit offset: 4 desc: TXUNDERR + RXOVERR: u1, // bit offset: 5 desc: RXOVERR + CMDREND: u1, // bit offset: 6 desc: CMDREND + CMDSENT: u1, // bit offset: 7 desc: CMDSENT + DATAEND: u1, // bit offset: 8 desc: DATAEND + STBITERR: u1, // bit offset: 9 desc: STBITERR + DBCKEND: u1, // bit offset: 10 desc: DBCKEND + CMDACT: u1, // bit offset: 11 desc: CMDACT + TXACT: u1, // bit offset: 12 desc: TXACT + RXACT: u1, // bit offset: 13 desc: RXACT + TXFIFOHE: u1, // bit offset: 14 desc: TXFIFOHE + RXFIFOHF: u1, // bit offset: 15 desc: RXFIFOHF + TXFIFOF: u1, // bit offset: 16 desc: TXFIFOF + RXFIFOF: u1, // bit offset: 17 desc: RXFIFOF + TXFIFOE: u1, // bit offset: 18 desc: TXFIFOE + RXFIFOE: u1, // bit offset: 19 desc: RXFIFOE + TXDAVL: u1, // bit offset: 20 desc: TXDAVL + RXDAVL: u1, // bit offset: 21 desc: RXDAVL + SDIOIT: u1, // bit offset: 22 desc: SDIOIT + CEATAEND: u1, // bit offset: 23 desc: CEATAEND + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 SDIO interrupt clear register (SDIO_ICR) + pub const ICR = mmio(Address + 0x00000038, 32, packed struct { + CCRCFAILC: u1, // bit offset: 0 desc: CCRCFAILC + DCRCFAILC: u1, // bit offset: 1 desc: DCRCFAILC + CTIMEOUTC: u1, // bit offset: 2 desc: CTIMEOUTC + DTIMEOUTC: u1, // bit offset: 3 desc: DTIMEOUTC + TXUNDERRC: u1, // bit offset: 4 desc: TXUNDERRC + RXOVERRC: u1, // bit offset: 5 desc: RXOVERRC + CMDRENDC: u1, // bit offset: 6 desc: CMDRENDC + CMDSENTC: u1, // bit offset: 7 desc: CMDSENTC + DATAENDC: u1, // bit offset: 8 desc: DATAENDC + STBITERRC: u1, // bit offset: 9 desc: STBITERRC + DBCKENDC: u1, // bit offset: 10 desc: DBCKENDC + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SDIOITC: u1, // bit offset: 22 desc: SDIOITC + CEATAENDC: u1, // bit offset: 23 desc: CEATAENDC + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 SDIO mask register (SDIO_MASK) + pub const MASK = mmio(Address + 0x0000003c, 32, packed struct { + CCRCFAILIE: u1, // bit offset: 0 desc: CCRCFAILIE + DCRCFAILIE: u1, // bit offset: 1 desc: DCRCFAILIE + CTIMEOUTIE: u1, // bit offset: 2 desc: CTIMEOUTIE + DTIMEOUTIE: u1, // bit offset: 3 desc: DTIMEOUTIE + TXUNDERRIE: u1, // bit offset: 4 desc: TXUNDERRIE + RXOVERRIE: u1, // bit offset: 5 desc: RXOVERRIE + CMDRENDIE: u1, // bit offset: 6 desc: CMDRENDIE + CMDSENTIE: u1, // bit offset: 7 desc: CMDSENTIE + DATAENDIE: u1, // bit offset: 8 desc: DATAENDIE + STBITERRIE: u1, // bit offset: 9 desc: STBITERRIE + DBACKENDIE: u1, // bit offset: 10 desc: DBACKENDIE + CMDACTIE: u1, // bit offset: 11 desc: CMDACTIE + TXACTIE: u1, // bit offset: 12 desc: TXACTIE + RXACTIE: u1, // bit offset: 13 desc: RXACTIE + TXFIFOHEIE: u1, // bit offset: 14 desc: TXFIFOHEIE + RXFIFOHFIE: u1, // bit offset: 15 desc: RXFIFOHFIE + TXFIFOFIE: u1, // bit offset: 16 desc: TXFIFOFIE + RXFIFOFIE: u1, // bit offset: 17 desc: RXFIFOFIE + TXFIFOEIE: u1, // bit offset: 18 desc: TXFIFOEIE + RXFIFOEIE: u1, // bit offset: 19 desc: RXFIFOEIE + TXDAVLIE: u1, // bit offset: 20 desc: TXDAVLIE + RXDAVLIE: u1, // bit offset: 21 desc: RXDAVLIE + SDIOITIE: u1, // bit offset: 22 desc: SDIOITIE + CEATENDIE: u1, // bit offset: 23 desc: CEATENDIE + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO + pub const FIFOCNT = mmio(Address + 0x00000048, 32, packed struct { + FIF0COUNT: u24, // bit offset: 0 desc: FIF0COUNT + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 128 bits 31:0 = FIFOData: Receive and transmit FIFO data + pub const FIFO = mmio(Address + 0x00000080, 32, packed struct { + FIFOData: u32, // bit offset: 0 desc: FIFOData + }); +}; +pub const RTC = extern struct { + pub const Address: u32 = 0x40002800; + // byte offset: 0 RTC Control Register High + pub const CRH = mmio(Address + 0x00000000, 32, packed struct { + SECIE: u1, // bit offset: 0 desc: Second interrupt Enable + ALRIE: u1, // bit offset: 1 desc: Alarm interrupt Enable + OWIE: u1, // bit offset: 2 desc: Overflow interrupt Enable + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 RTC Control Register Low + pub const CRL = mmio(Address + 0x00000004, 32, packed struct { + SECF: u1, // bit offset: 0 desc: Second Flag + ALRF: u1, // bit offset: 1 desc: Alarm Flag + OWF: u1, // bit offset: 2 desc: Overflow Flag + RSF: u1, // bit offset: 3 desc: Registers Synchronized Flag + CNF: u1, // bit offset: 4 desc: Configuration Flag + RTOFF: u1, // bit offset: 5 desc: RTC operation OFF + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 RTC Prescaler Load Register High + pub const PRLH = mmio(Address + 0x00000008, 32, packed struct { + PRLH: u4, // bit offset: 0 desc: RTC Prescaler Load Register High + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 RTC Prescaler Load Register Low + pub const PRLL = mmio(Address + 0x0000000c, 32, packed struct { + PRLL: u16, // bit offset: 0 desc: RTC Prescaler Divider Register Low + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 RTC Prescaler Divider Register High + pub const DIVH = mmio(Address + 0x00000010, 32, packed struct { + DIVH: u4, // bit offset: 0 desc: RTC prescaler divider register high + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RTC Prescaler Divider Register Low + pub const DIVL = mmio(Address + 0x00000014, 32, packed struct { + DIVL: u16, // bit offset: 0 desc: RTC prescaler divider register Low + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 RTC Counter Register High + pub const CNTH = mmio(Address + 0x00000018, 32, packed struct { + CNTH: u16, // bit offset: 0 desc: RTC counter register high + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 RTC Counter Register Low + pub const CNTL = mmio(Address + 0x0000001c, 32, packed struct { + CNTL: u16, // bit offset: 0 desc: RTC counter register Low + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 RTC Alarm Register High + pub const ALRH = mmio(Address + 0x00000020, 32, packed struct { + ALRH: u16, // bit offset: 0 desc: RTC alarm register high + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 RTC Alarm Register Low + pub const ALRL = mmio(Address + 0x00000024, 32, packed struct { + ALRL: u16, // bit offset: 0 desc: RTC alarm register low + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const BKP = extern struct { + pub const Address: u32 = 0x40006c04; + // byte offset: 0 Backup data register (BKP_DR) + pub const DR1 = mmio(Address + 0x00000000, 32, packed struct { + D1: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Backup data register (BKP_DR) + pub const DR2 = mmio(Address + 0x00000004, 32, packed struct { + D2: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Backup data register (BKP_DR) + pub const DR3 = mmio(Address + 0x00000008, 32, packed struct { + D3: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Backup data register (BKP_DR) + pub const DR4 = mmio(Address + 0x0000000c, 32, packed struct { + D4: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Backup data register (BKP_DR) + pub const DR5 = mmio(Address + 0x00000010, 32, packed struct { + D5: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Backup data register (BKP_DR) + pub const DR6 = mmio(Address + 0x00000014, 32, packed struct { + D6: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Backup data register (BKP_DR) + pub const DR7 = mmio(Address + 0x00000018, 32, packed struct { + D7: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Backup data register (BKP_DR) + pub const DR8 = mmio(Address + 0x0000001c, 32, packed struct { + D8: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Backup data register (BKP_DR) + pub const DR9 = mmio(Address + 0x00000020, 32, packed struct { + D9: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Backup data register (BKP_DR) + pub const DR10 = mmio(Address + 0x00000024, 32, packed struct { + D10: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 RTC clock calibration register (BKP_RTCCR) + pub const RTCCR = mmio(Address + 0x00000028, 32, packed struct { + CAL: u7, // bit offset: 0 desc: Calibration value + CCO: u1, // bit offset: 7 desc: Calibration Clock Output + ASOE: u1, // bit offset: 8 desc: Alarm or second output enable + ASOS: u1, // bit offset: 9 desc: Alarm or second output selection + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Backup control register (BKP_CR) + pub const CR = mmio(Address + 0x0000002c, 32, packed struct { + TPE: u1, // bit offset: 0 desc: Tamper pin enable + TPAL: u1, // bit offset: 1 desc: Tamper pin active level + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 BKP_CSR control/status register (BKP_CSR) + pub const CSR = mmio(Address + 0x00000030, 32, packed struct { + CTE: u1, // bit offset: 0 desc: Clear Tamper event + CTI: u1, // bit offset: 1 desc: Clear Tamper Interrupt + TPIE: u1, // bit offset: 2 desc: Tamper Pin interrupt enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TEF: u1, // bit offset: 8 desc: Tamper Event Flag + TIF: u1, // bit offset: 9 desc: Tamper Interrupt Flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 Backup data register (BKP_DR) + pub const DR11 = mmio(Address + 0x0000003c, 32, packed struct { + DR11: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 Backup data register (BKP_DR) + pub const DR12 = mmio(Address + 0x00000040, 32, packed struct { + DR12: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 Backup data register (BKP_DR) + pub const DR13 = mmio(Address + 0x00000044, 32, packed struct { + DR13: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 Backup data register (BKP_DR) + pub const DR14 = mmio(Address + 0x00000048, 32, packed struct { + D14: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 Backup data register (BKP_DR) + pub const DR15 = mmio(Address + 0x0000004c, 32, packed struct { + D15: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 Backup data register (BKP_DR) + pub const DR16 = mmio(Address + 0x00000050, 32, packed struct { + D16: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 Backup data register (BKP_DR) + pub const DR17 = mmio(Address + 0x00000054, 32, packed struct { + D17: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 88 Backup data register (BKP_DR) + pub const DR18 = mmio(Address + 0x00000058, 32, packed struct { + D18: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 Backup data register (BKP_DR) + pub const DR19 = mmio(Address + 0x0000005c, 32, packed struct { + D19: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 Backup data register (BKP_DR) + pub const DR20 = mmio(Address + 0x00000060, 32, packed struct { + D20: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 100 Backup data register (BKP_DR) + pub const DR21 = mmio(Address + 0x00000064, 32, packed struct { + D21: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 104 Backup data register (BKP_DR) + pub const DR22 = mmio(Address + 0x00000068, 32, packed struct { + D22: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 108 Backup data register (BKP_DR) + pub const DR23 = mmio(Address + 0x0000006c, 32, packed struct { + D23: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 Backup data register (BKP_DR) + pub const DR24 = mmio(Address + 0x00000070, 32, packed struct { + D24: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 Backup data register (BKP_DR) + pub const DR25 = mmio(Address + 0x00000074, 32, packed struct { + D25: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 120 Backup data register (BKP_DR) + pub const DR26 = mmio(Address + 0x00000078, 32, packed struct { + D26: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 124 Backup data register (BKP_DR) + pub const DR27 = mmio(Address + 0x0000007c, 32, packed struct { + D27: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 128 Backup data register (BKP_DR) + pub const DR28 = mmio(Address + 0x00000080, 32, packed struct { + D28: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 Backup data register (BKP_DR) + pub const DR29 = mmio(Address + 0x00000084, 32, packed struct { + D29: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 Backup data register (BKP_DR) + pub const DR30 = mmio(Address + 0x00000088, 32, packed struct { + D30: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 Backup data register (BKP_DR) + pub const DR31 = mmio(Address + 0x0000008c, 32, packed struct { + D31: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 144 Backup data register (BKP_DR) + pub const DR32 = mmio(Address + 0x00000090, 32, packed struct { + D32: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 148 Backup data register (BKP_DR) + pub const DR33 = mmio(Address + 0x00000094, 32, packed struct { + D33: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 152 Backup data register (BKP_DR) + pub const DR34 = mmio(Address + 0x00000098, 32, packed struct { + D34: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 156 Backup data register (BKP_DR) + pub const DR35 = mmio(Address + 0x0000009c, 32, packed struct { + D35: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Backup data register (BKP_DR) + pub const DR36 = mmio(Address + 0x000000a0, 32, packed struct { + D36: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 Backup data register (BKP_DR) + pub const DR37 = mmio(Address + 0x000000a4, 32, packed struct { + D37: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 168 Backup data register (BKP_DR) + pub const DR38 = mmio(Address + 0x000000a8, 32, packed struct { + D38: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 172 Backup data register (BKP_DR) + pub const DR39 = mmio(Address + 0x000000ac, 32, packed struct { + D39: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 176 Backup data register (BKP_DR) + pub const DR40 = mmio(Address + 0x000000b0, 32, packed struct { + D40: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 180 Backup data register (BKP_DR) + pub const DR41 = mmio(Address + 0x000000b4, 32, packed struct { + D41: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 184 Backup data register (BKP_DR) + pub const DR42 = mmio(Address + 0x000000b8, 32, packed struct { + D42: u16, // bit offset: 0 desc: Backup data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const IWDG = extern struct { + pub const Address: u32 = 0x40003000; + // byte offset: 0 Key register (IWDG_KR) + pub const KR = mmio(Address + 0x00000000, 32, packed struct { + KEY: u16, // bit offset: 0 desc: Key value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Prescaler register (IWDG_PR) + pub const PR = mmio(Address + 0x00000004, 32, packed struct { + PR: u3, // bit offset: 0 desc: Prescaler divider + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Reload register (IWDG_RLR) + pub const RLR = mmio(Address + 0x00000008, 32, packed struct { + RL: u12, // bit offset: 0 desc: Watchdog counter reload value + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Status register (IWDG_SR) + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update + RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const WWDG = extern struct { + pub const Address: u32 = 0x40002c00; + // byte offset: 0 Control register (WWDG_CR) + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + T: u7, // bit offset: 0 desc: 7-bit counter (MSB to LSB) + WDGA: u1, // bit offset: 7 desc: Activation bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Configuration register (WWDG_CFR) + pub const CFR = mmio(Address + 0x00000004, 32, packed struct { + W: u7, // bit offset: 0 desc: 7-bit window value + WDGTB: u2, // bit offset: 7 desc: Timer Base + EWI: u1, // bit offset: 9 desc: Early Wakeup Interrupt + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Status register (WWDG_SR) + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + EWI: u1, // bit offset: 0 desc: Early Wakeup Interrupt + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM1 = extern struct { + pub const Address: u32 = 0x40012c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM8 = extern struct { + pub const Address: u32 = 0x40013400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM2 = extern struct { + pub const Address: u32 = 0x40000000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved2: u1 = 0, + reserved1: u1 = 0, + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved4: u1 = 0, + reserved3: u1 = 0, + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved6: u1 = 0, + reserved5: u1 = 0, + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM3 = extern struct { + pub const Address: u32 = 0x40000400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved2: u1 = 0, + reserved1: u1 = 0, + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved4: u1 = 0, + reserved3: u1 = 0, + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved6: u1 = 0, + reserved5: u1 = 0, + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM4 = extern struct { + pub const Address: u32 = 0x40000800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved2: u1 = 0, + reserved1: u1 = 0, + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved4: u1 = 0, + reserved3: u1 = 0, + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved6: u1 = 0, + reserved5: u1 = 0, + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM5 = extern struct { + pub const Address: u32 = 0x40000c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved2: u1 = 0, + reserved1: u1 = 0, + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved4: u1 = 0, + reserved3: u1 = 0, + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved6: u1 = 0, + reserved5: u1 = 0, + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM9 = extern struct { + pub const Address: u32 = 0x40014c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved5: u1 = 0, + reserved4: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved1: u1 = 0, + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM12 = extern struct { + pub const Address: u32 = 0x40001800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved5: u1 = 0, + reserved4: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved1: u1 = 0, + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM10 = extern struct { + pub const Address: u32 = 0x40015000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + reserved1: u1 = 0, + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM11 = extern struct { + pub const Address: u32 = 0x40015400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + reserved1: u1 = 0, + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM13 = extern struct { + pub const Address: u32 = 0x40001c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + reserved1: u1 = 0, + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM14 = extern struct { + pub const Address: u32 = 0x40002000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + reserved1: u1 = 0, + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM6 = extern struct { + pub const Address: u32 = 0x40001000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM7 = extern struct { + pub const Address: u32 = 0x40001400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C1 = extern struct { + pub const Address: u32 = 0x40005400; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + SMBUS: u1, // bit offset: 1 desc: SMBus mode + reserved1: u1 = 0, + SMBTYPE: u1, // bit offset: 3 desc: SMBus type + ENARP: u1, // bit offset: 4 desc: ARP enable + ENPEC: u1, // bit offset: 5 desc: PEC enable + ENGC: u1, // bit offset: 6 desc: General call enable + NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) + START: u1, // bit offset: 8 desc: Start generation + STOP: u1, // bit offset: 9 desc: Stop generation + ACK: u1, // bit offset: 10 desc: Acknowledge enable + POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) + PEC: u1, // bit offset: 12 desc: Packet error checking + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved2: u1 = 0, + SWRST: u1, // bit offset: 15 desc: Software reset + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + reserved2: u1 = 0, + reserved1: u1 = 0, + ITERREN: u1, // bit offset: 8 desc: Error interrupt enable + ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable + ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable + DMAEN: u1, // bit offset: 11 desc: DMA requests enable + LAST: u1, // bit offset: 12 desc: DMA last transfer + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + ADD0: u1, // bit offset: 0 desc: Interface address + ADD7: u7, // bit offset: 1 desc: Interface address + ADD10: u2, // bit offset: 8 desc: Interface address + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable + ADD2: u7, // bit offset: 1 desc: Interface address + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Data register + pub const DR = mmio(Address + 0x00000010, 32, packed struct { + DR: u8, // bit offset: 0 desc: 8-bit data register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Status register 1 + pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { + SB: u1, // bit offset: 0 desc: Start bit (Master mode) + ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) + BTF: u1, // bit offset: 2 desc: Byte transfer finished + ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) + STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + reserved1: u1 = 0, + RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) + TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) + AF: u1, // bit offset: 10 desc: Acknowledge failure + OVR: u1, // bit offset: 11 desc: Overrun/Underrun + PECERR: u1, // bit offset: 12 desc: PEC Error in reception + reserved2: u1 = 0, + TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error + SMBALERT: u1, // bit offset: 15 desc: SMBus alert + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Status register 2 + pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { + MSL: u1, // bit offset: 0 desc: Master/slave + BUSY: u1, // bit offset: 1 desc: Bus busy + TRA: u1, // bit offset: 2 desc: Transmitter/receiver + reserved1: u1 = 0, + GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) + SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) + SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) + DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) + PEC: u8, // bit offset: 8 desc: acket error checking register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Clock control register + pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { + CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + reserved2: u1 = 0, + reserved1: u1 = 0, + DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle + F_S: u1, // bit offset: 15 desc: I2C master mode selection + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 TRISE register + pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { + TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C2 = extern struct { + pub const Address: u32 = 0x40005800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + SMBUS: u1, // bit offset: 1 desc: SMBus mode + reserved1: u1 = 0, + SMBTYPE: u1, // bit offset: 3 desc: SMBus type + ENARP: u1, // bit offset: 4 desc: ARP enable + ENPEC: u1, // bit offset: 5 desc: PEC enable + ENGC: u1, // bit offset: 6 desc: General call enable + NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) + START: u1, // bit offset: 8 desc: Start generation + STOP: u1, // bit offset: 9 desc: Stop generation + ACK: u1, // bit offset: 10 desc: Acknowledge enable + POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) + PEC: u1, // bit offset: 12 desc: Packet error checking + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved2: u1 = 0, + SWRST: u1, // bit offset: 15 desc: Software reset + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + reserved2: u1 = 0, + reserved1: u1 = 0, + ITERREN: u1, // bit offset: 8 desc: Error interrupt enable + ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable + ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable + DMAEN: u1, // bit offset: 11 desc: DMA requests enable + LAST: u1, // bit offset: 12 desc: DMA last transfer + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + ADD0: u1, // bit offset: 0 desc: Interface address + ADD7: u7, // bit offset: 1 desc: Interface address + ADD10: u2, // bit offset: 8 desc: Interface address + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable + ADD2: u7, // bit offset: 1 desc: Interface address + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Data register + pub const DR = mmio(Address + 0x00000010, 32, packed struct { + DR: u8, // bit offset: 0 desc: 8-bit data register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Status register 1 + pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { + SB: u1, // bit offset: 0 desc: Start bit (Master mode) + ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) + BTF: u1, // bit offset: 2 desc: Byte transfer finished + ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) + STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + reserved1: u1 = 0, + RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) + TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) + AF: u1, // bit offset: 10 desc: Acknowledge failure + OVR: u1, // bit offset: 11 desc: Overrun/Underrun + PECERR: u1, // bit offset: 12 desc: PEC Error in reception + reserved2: u1 = 0, + TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error + SMBALERT: u1, // bit offset: 15 desc: SMBus alert + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Status register 2 + pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { + MSL: u1, // bit offset: 0 desc: Master/slave + BUSY: u1, // bit offset: 1 desc: Bus busy + TRA: u1, // bit offset: 2 desc: Transmitter/receiver + reserved1: u1 = 0, + GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) + SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) + SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) + DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) + PEC: u8, // bit offset: 8 desc: acket error checking register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Clock control register + pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { + CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + reserved2: u1 = 0, + reserved1: u1 = 0, + DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle + F_S: u1, // bit offset: 15 desc: I2C master mode selection + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 TRISE register + pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { + TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI1 = extern struct { + pub const Address: u32 = 0x40013000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + reserved2: u1 = 0, + reserved1: u1 = 0, + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI2 = extern struct { + pub const Address: u32 = 0x40003800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + reserved2: u1 = 0, + reserved1: u1 = 0, + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI3 = extern struct { + pub const Address: u32 = 0x40003c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + reserved2: u1 = 0, + reserved1: u1 = 0, + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART1 = extern struct { + pub const Address: u32 = 0x40013800; + // byte offset: 0 Status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NE: u1, // bit offset: 2 desc: Noise error flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: IDLE line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBD: u1, // bit offset: 8 desc: LIN break detection flag + CTS: u1, // bit offset: 9 desc: CTS flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Data register + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DR: u9, // bit offset: 0 desc: Data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Baud rate register + pub const BRR = mmio(Address + 0x00000008, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Control register 1 + pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { + SBK: u1, // bit offset: 0 desc: Send break + RWU: u1, // bit offset: 1 desc: Receiver wakeup + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Wakeup method + M: u1, // bit offset: 12 desc: Word length + UE: u1, // bit offset: 13 desc: USART enable + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Control register 2 + pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { + ADD: u4, // bit offset: 0 desc: Address of the USART node + reserved1: u1 = 0, + LBDL: u1, // bit offset: 5 desc: lin break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved2: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Control register 3 + pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART2 = extern struct { + pub const Address: u32 = 0x40004400; + // byte offset: 0 Status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NE: u1, // bit offset: 2 desc: Noise error flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: IDLE line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBD: u1, // bit offset: 8 desc: LIN break detection flag + CTS: u1, // bit offset: 9 desc: CTS flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Data register + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DR: u9, // bit offset: 0 desc: Data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Baud rate register + pub const BRR = mmio(Address + 0x00000008, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Control register 1 + pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { + SBK: u1, // bit offset: 0 desc: Send break + RWU: u1, // bit offset: 1 desc: Receiver wakeup + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Wakeup method + M: u1, // bit offset: 12 desc: Word length + UE: u1, // bit offset: 13 desc: USART enable + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Control register 2 + pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { + ADD: u4, // bit offset: 0 desc: Address of the USART node + reserved1: u1 = 0, + LBDL: u1, // bit offset: 5 desc: lin break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved2: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Control register 3 + pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART3 = extern struct { + pub const Address: u32 = 0x40004800; + // byte offset: 0 Status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NE: u1, // bit offset: 2 desc: Noise error flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: IDLE line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBD: u1, // bit offset: 8 desc: LIN break detection flag + CTS: u1, // bit offset: 9 desc: CTS flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Data register + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DR: u9, // bit offset: 0 desc: Data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Baud rate register + pub const BRR = mmio(Address + 0x00000008, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Control register 1 + pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { + SBK: u1, // bit offset: 0 desc: Send break + RWU: u1, // bit offset: 1 desc: Receiver wakeup + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Wakeup method + M: u1, // bit offset: 12 desc: Word length + UE: u1, // bit offset: 13 desc: USART enable + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Control register 2 + pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { + ADD: u4, // bit offset: 0 desc: Address of the USART node + reserved1: u1 = 0, + LBDL: u1, // bit offset: 5 desc: lin break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved2: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Control register 3 + pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC1 = extern struct { + pub const Address: u32 = 0x40012400; + // byte offset: 0 status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + AWD: u1, // bit offset: 0 desc: Analog watchdog flag + EOC: u1, // bit offset: 1 desc: Regular channel end of conversion + JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion + JSTRT: u1, // bit offset: 3 desc: Injected channel start flag + STRT: u1, // bit offset: 4 desc: Regular channel start flag + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 1 + pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { + AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits + EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC + AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable + JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels + SCAN: u1, // bit offset: 8 desc: Scan mode + AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode + JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion + DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels + JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels + DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + DUALMOD: u4, // bit offset: 16 desc: Dual mode selection + reserved2: u1 = 0, + reserved1: u1 = 0, + JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels + AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register 2 + pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { + ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF + CONT: u1, // bit offset: 1 desc: Continuous conversion + CAL: u1, // bit offset: 2 desc: A/D calibration + RSTCAL: u1, // bit offset: 3 desc: Reset calibration + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMA: u1, // bit offset: 8 desc: Direct memory access mode + reserved6: u1 = 0, + reserved5: u1 = 0, + ALIGN: u1, // bit offset: 11 desc: Data alignment + JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group + JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + reserved7: u1 = 0, + EXTSEL: u3, // bit offset: 17 desc: External event select for regular group + EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels + JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels + SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels + TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 sample time register 1 + pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection + SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection + SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection + SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection + SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection + SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection + SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection + SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { + SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection + SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection + SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection + SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection + SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection + SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection + SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection + SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection + SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection + SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 injected channel data offset register x + pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { + JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 injected channel data offset register x + pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { + JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 injected channel data offset register x + pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { + JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 injected channel data offset register x + pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { + JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog higher threshold register + pub const HTR = mmio(Address + 0x00000024, 32, packed struct { + HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog lower threshold register + pub const LTR = mmio(Address + 0x00000028, 32, packed struct { + LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { + SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence + SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence + SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence + SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence + L: u4, // bit offset: 20 desc: Regular channel sequence length + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { + SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence + SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence + SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence + SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence + SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence + SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { + SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence + SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence + SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence + SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence + SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence + SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 injected sequence register + pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { + JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence + JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence + JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence + JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence + JL: u2, // bit offset: 20 desc: Injected sequence length + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 injected data register x + pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 injected data register x + pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 injected data register x + pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 injected data register x + pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 regular data register + pub const DR = mmio(Address + 0x0000004c, 32, packed struct { + DATA: u16, // bit offset: 0 desc: Regular data + ADC2DATA: u16, // bit offset: 16 desc: ADC2 data + }); +}; +pub const ADC2 = extern struct { + pub const Address: u32 = 0x40012800; + // byte offset: 0 status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + AWD: u1, // bit offset: 0 desc: Analog watchdog flag + EOC: u1, // bit offset: 1 desc: Regular channel end of conversion + JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion + JSTRT: u1, // bit offset: 3 desc: Injected channel start flag + STRT: u1, // bit offset: 4 desc: Regular channel start flag + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 1 + pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { + AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits + EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC + AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable + JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels + SCAN: u1, // bit offset: 8 desc: Scan mode + AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode + JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion + DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels + JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels + DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels + AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register 2 + pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { + ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF + CONT: u1, // bit offset: 1 desc: Continuous conversion + CAL: u1, // bit offset: 2 desc: A/D calibration + RSTCAL: u1, // bit offset: 3 desc: Reset calibration + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMA: u1, // bit offset: 8 desc: Direct memory access mode + reserved6: u1 = 0, + reserved5: u1 = 0, + ALIGN: u1, // bit offset: 11 desc: Data alignment + JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group + JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + reserved7: u1 = 0, + EXTSEL: u3, // bit offset: 17 desc: External event select for regular group + EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels + JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels + SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels + TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 sample time register 1 + pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection + SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection + SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection + SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection + SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection + SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection + SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection + SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { + SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection + SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection + SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection + SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection + SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection + SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection + SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection + SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection + SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection + SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 injected channel data offset register x + pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { + JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 injected channel data offset register x + pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { + JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 injected channel data offset register x + pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { + JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 injected channel data offset register x + pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { + JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog higher threshold register + pub const HTR = mmio(Address + 0x00000024, 32, packed struct { + HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog lower threshold register + pub const LTR = mmio(Address + 0x00000028, 32, packed struct { + LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { + SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence + SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence + SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence + SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence + L: u4, // bit offset: 20 desc: Regular channel sequence length + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { + SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence + SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence + SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence + SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence + SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence + SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { + SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence + SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence + SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence + SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence + SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence + SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 injected sequence register + pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { + JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence + JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence + JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence + JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence + JL: u2, // bit offset: 20 desc: Injected sequence length + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 injected data register x + pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 injected data register x + pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 injected data register x + pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 injected data register x + pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 regular data register + pub const DR = mmio(Address + 0x0000004c, 32, packed struct { + DATA: u16, // bit offset: 0 desc: Regular data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC3 = extern struct { + pub const Address: u32 = 0x40013c00; + // byte offset: 0 status register + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + AWD: u1, // bit offset: 0 desc: Analog watchdog flag + EOC: u1, // bit offset: 1 desc: Regular channel end of conversion + JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion + JSTRT: u1, // bit offset: 3 desc: Injected channel start flag + STRT: u1, // bit offset: 4 desc: Regular channel start flag + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 1 + pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { + AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits + EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC + AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable + JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels + SCAN: u1, // bit offset: 8 desc: Scan mode + AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode + JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion + DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels + JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels + DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels + AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register 2 + pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { + ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF + CONT: u1, // bit offset: 1 desc: Continuous conversion + CAL: u1, // bit offset: 2 desc: A/D calibration + RSTCAL: u1, // bit offset: 3 desc: Reset calibration + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMA: u1, // bit offset: 8 desc: Direct memory access mode + reserved6: u1 = 0, + reserved5: u1 = 0, + ALIGN: u1, // bit offset: 11 desc: Data alignment + JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group + JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + reserved7: u1 = 0, + EXTSEL: u3, // bit offset: 17 desc: External event select for regular group + EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels + JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels + SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels + TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 sample time register 1 + pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection + SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection + SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection + SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection + SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection + SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection + SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection + SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { + SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection + SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection + SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection + SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection + SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection + SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection + SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection + SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection + SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection + SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 injected channel data offset register x + pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { + JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 injected channel data offset register x + pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { + JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 injected channel data offset register x + pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { + JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 injected channel data offset register x + pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { + JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog higher threshold register + pub const HTR = mmio(Address + 0x00000024, 32, packed struct { + HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog lower threshold register + pub const LTR = mmio(Address + 0x00000028, 32, packed struct { + LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { + SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence + SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence + SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence + SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence + L: u4, // bit offset: 20 desc: Regular channel sequence length + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { + SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence + SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence + SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence + SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence + SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence + SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { + SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence + SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence + SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence + SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence + SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence + SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 injected sequence register + pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { + JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence + JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence + JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence + JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence + JL: u2, // bit offset: 20 desc: Injected sequence length + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 injected data register x + pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 injected data register x + pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 injected data register x + pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 injected data register x + pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { + JDATA: u16, // bit offset: 0 desc: Injected data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 regular data register + pub const DR = mmio(Address + 0x0000004c, 32, packed struct { + DATA: u16, // bit offset: 0 desc: Regular data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CAN = extern struct { + pub const Address: u32 = 0x40006400; + // byte offset: 0 CAN_MCR + pub const CAN_MCR = mmio(Address + 0x00000000, 32, packed struct { + INRQ: u1, // bit offset: 0 desc: INRQ + SLEEP: u1, // bit offset: 1 desc: SLEEP + TXFP: u1, // bit offset: 2 desc: TXFP + RFLM: u1, // bit offset: 3 desc: RFLM + NART: u1, // bit offset: 4 desc: NART + AWUM: u1, // bit offset: 5 desc: AWUM + ABOM: u1, // bit offset: 6 desc: ABOM + TTCM: u1, // bit offset: 7 desc: TTCM + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESET: u1, // bit offset: 15 desc: RESET + DBF: u1, // bit offset: 16 desc: DBF + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 CAN_MSR + pub const CAN_MSR = mmio(Address + 0x00000004, 32, packed struct { + INAK: u1, // bit offset: 0 desc: INAK + SLAK: u1, // bit offset: 1 desc: SLAK + ERRI: u1, // bit offset: 2 desc: ERRI + WKUI: u1, // bit offset: 3 desc: WKUI + SLAKI: u1, // bit offset: 4 desc: SLAKI + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXM: u1, // bit offset: 8 desc: TXM + RXM: u1, // bit offset: 9 desc: RXM + SAMP: u1, // bit offset: 10 desc: SAMP + RX: u1, // bit offset: 11 desc: RX + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 CAN_TSR + pub const CAN_TSR = mmio(Address + 0x00000008, 32, packed struct { + RQCP0: u1, // bit offset: 0 desc: RQCP0 + TXOK0: u1, // bit offset: 1 desc: TXOK0 + ALST0: u1, // bit offset: 2 desc: ALST0 + TERR0: u1, // bit offset: 3 desc: TERR0 + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABRQ0: u1, // bit offset: 7 desc: ABRQ0 + RQCP1: u1, // bit offset: 8 desc: RQCP1 + TXOK1: u1, // bit offset: 9 desc: TXOK1 + ALST1: u1, // bit offset: 10 desc: ALST1 + TERR1: u1, // bit offset: 11 desc: TERR1 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + ABRQ1: u1, // bit offset: 15 desc: ABRQ1 + RQCP2: u1, // bit offset: 16 desc: RQCP2 + TXOK2: u1, // bit offset: 17 desc: TXOK2 + ALST2: u1, // bit offset: 18 desc: ALST2 + TERR2: u1, // bit offset: 19 desc: TERR2 + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + ABRQ2: u1, // bit offset: 23 desc: ABRQ2 + CODE: u2, // bit offset: 24 desc: CODE + TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 + TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 + TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 + LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 + LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 + LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 + }); + // byte offset: 12 CAN_RF0R + pub const CAN_RF0R = mmio(Address + 0x0000000c, 32, packed struct { + FMP0: u2, // bit offset: 0 desc: FMP0 + reserved1: u1 = 0, + FULL0: u1, // bit offset: 3 desc: FULL0 + FOVR0: u1, // bit offset: 4 desc: FOVR0 + RFOM0: u1, // bit offset: 5 desc: RFOM0 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CAN_RF1R + pub const CAN_RF1R = mmio(Address + 0x00000010, 32, packed struct { + FMP1: u2, // bit offset: 0 desc: FMP1 + reserved1: u1 = 0, + FULL1: u1, // bit offset: 3 desc: FULL1 + FOVR1: u1, // bit offset: 4 desc: FOVR1 + RFOM1: u1, // bit offset: 5 desc: RFOM1 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 CAN_IER + pub const CAN_IER = mmio(Address + 0x00000014, 32, packed struct { + TMEIE: u1, // bit offset: 0 desc: TMEIE + FMPIE0: u1, // bit offset: 1 desc: FMPIE0 + FFIE0: u1, // bit offset: 2 desc: FFIE0 + FOVIE0: u1, // bit offset: 3 desc: FOVIE0 + FMPIE1: u1, // bit offset: 4 desc: FMPIE1 + FFIE1: u1, // bit offset: 5 desc: FFIE1 + FOVIE1: u1, // bit offset: 6 desc: FOVIE1 + reserved1: u1 = 0, + EWGIE: u1, // bit offset: 8 desc: EWGIE + EPVIE: u1, // bit offset: 9 desc: EPVIE + BOFIE: u1, // bit offset: 10 desc: BOFIE + LECIE: u1, // bit offset: 11 desc: LECIE + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + ERRIE: u1, // bit offset: 15 desc: ERRIE + WKUIE: u1, // bit offset: 16 desc: WKUIE + SLKIE: u1, // bit offset: 17 desc: SLKIE + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 CAN_ESR + pub const CAN_ESR = mmio(Address + 0x00000018, 32, packed struct { + EWGF: u1, // bit offset: 0 desc: EWGF + EPVF: u1, // bit offset: 1 desc: EPVF + BOFF: u1, // bit offset: 2 desc: BOFF + reserved1: u1 = 0, + LEC: u3, // bit offset: 4 desc: LEC + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TEC: u8, // bit offset: 16 desc: TEC + REC: u8, // bit offset: 24 desc: REC + }); + // byte offset: 28 CAN_BTR + pub const CAN_BTR = mmio(Address + 0x0000001c, 32, packed struct { + BRP: u10, // bit offset: 0 desc: BRP + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TS1: u4, // bit offset: 16 desc: TS1 + TS2: u3, // bit offset: 20 desc: TS2 + reserved7: u1 = 0, + SJW: u2, // bit offset: 24 desc: SJW + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + LBKM: u1, // bit offset: 30 desc: LBKM + SILM: u1, // bit offset: 31 desc: SILM + }); + // byte offset: 384 CAN_TI0R + pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 388 CAN_TDT0R + pub const CAN_TDT0R = mmio(Address + 0x00000184, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 392 CAN_TDL0R + pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 396 CAN_TDH0R + pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 400 CAN_TI1R + pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 404 CAN_TDT1R + pub const CAN_TDT1R = mmio(Address + 0x00000194, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 408 CAN_TDL1R + pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 412 CAN_TDH1R + pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 416 CAN_TI2R + pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 420 CAN_TDT2R + pub const CAN_TDT2R = mmio(Address + 0x000001a4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 424 CAN_TDL2R + pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 428 CAN_TDH2R + pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 432 CAN_RI0R + pub const CAN_RI0R = mmio(Address + 0x000001b0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 436 CAN_RDT0R + pub const CAN_RDT0R = mmio(Address + 0x000001b4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 440 CAN_RDL0R + pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 444 CAN_RDH0R + pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 448 CAN_RI1R + pub const CAN_RI1R = mmio(Address + 0x000001c0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 452 CAN_RDT1R + pub const CAN_RDT1R = mmio(Address + 0x000001c4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 456 CAN_RDL1R + pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 460 CAN_RDH1R + pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 512 CAN_FMR + pub const CAN_FMR = mmio(Address + 0x00000200, 32, packed struct { + FINIT: u1, // bit offset: 0 desc: FINIT + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 516 CAN_FM1R + pub const CAN_FM1R = mmio(Address + 0x00000204, 32, packed struct { + FBM0: u1, // bit offset: 0 desc: Filter mode + FBM1: u1, // bit offset: 1 desc: Filter mode + FBM2: u1, // bit offset: 2 desc: Filter mode + FBM3: u1, // bit offset: 3 desc: Filter mode + FBM4: u1, // bit offset: 4 desc: Filter mode + FBM5: u1, // bit offset: 5 desc: Filter mode + FBM6: u1, // bit offset: 6 desc: Filter mode + FBM7: u1, // bit offset: 7 desc: Filter mode + FBM8: u1, // bit offset: 8 desc: Filter mode + FBM9: u1, // bit offset: 9 desc: Filter mode + FBM10: u1, // bit offset: 10 desc: Filter mode + FBM11: u1, // bit offset: 11 desc: Filter mode + FBM12: u1, // bit offset: 12 desc: Filter mode + FBM13: u1, // bit offset: 13 desc: Filter mode + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 524 CAN_FS1R + pub const CAN_FS1R = mmio(Address + 0x0000020c, 32, packed struct { + FSC0: u1, // bit offset: 0 desc: Filter scale configuration + FSC1: u1, // bit offset: 1 desc: Filter scale configuration + FSC2: u1, // bit offset: 2 desc: Filter scale configuration + FSC3: u1, // bit offset: 3 desc: Filter scale configuration + FSC4: u1, // bit offset: 4 desc: Filter scale configuration + FSC5: u1, // bit offset: 5 desc: Filter scale configuration + FSC6: u1, // bit offset: 6 desc: Filter scale configuration + FSC7: u1, // bit offset: 7 desc: Filter scale configuration + FSC8: u1, // bit offset: 8 desc: Filter scale configuration + FSC9: u1, // bit offset: 9 desc: Filter scale configuration + FSC10: u1, // bit offset: 10 desc: Filter scale configuration + FSC11: u1, // bit offset: 11 desc: Filter scale configuration + FSC12: u1, // bit offset: 12 desc: Filter scale configuration + FSC13: u1, // bit offset: 13 desc: Filter scale configuration + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 532 CAN_FFA1R + pub const CAN_FFA1R = mmio(Address + 0x00000214, 32, packed struct { + FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 + FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 + FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 + FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 + FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 + FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 + FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 + FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 + FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 + FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 + FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 + FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 + FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 + FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 540 CAN_FA1R + pub const CAN_FA1R = mmio(Address + 0x0000021c, 32, packed struct { + FACT0: u1, // bit offset: 0 desc: Filter active + FACT1: u1, // bit offset: 1 desc: Filter active + FACT2: u1, // bit offset: 2 desc: Filter active + FACT3: u1, // bit offset: 3 desc: Filter active + FACT4: u1, // bit offset: 4 desc: Filter active + FACT5: u1, // bit offset: 5 desc: Filter active + FACT6: u1, // bit offset: 6 desc: Filter active + FACT7: u1, // bit offset: 7 desc: Filter active + FACT8: u1, // bit offset: 8 desc: Filter active + FACT9: u1, // bit offset: 9 desc: Filter active + FACT10: u1, // bit offset: 10 desc: Filter active + FACT11: u1, // bit offset: 11 desc: Filter active + FACT12: u1, // bit offset: 12 desc: Filter active + FACT13: u1, // bit offset: 13 desc: Filter active + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 576 Filter bank 0 register 1 + pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 580 Filter bank 0 register 2 + pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 584 Filter bank 1 register 1 + pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 588 Filter bank 1 register 2 + pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 592 Filter bank 2 register 1 + pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 596 Filter bank 2 register 2 + pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 600 Filter bank 3 register 1 + pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 604 Filter bank 3 register 2 + pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 608 Filter bank 4 register 1 + pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 612 Filter bank 4 register 2 + pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 616 Filter bank 5 register 1 + pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 620 Filter bank 5 register 2 + pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 624 Filter bank 6 register 1 + pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 628 Filter bank 6 register 2 + pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 632 Filter bank 7 register 1 + pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 636 Filter bank 7 register 2 + pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 640 Filter bank 8 register 1 + pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 644 Filter bank 8 register 2 + pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 648 Filter bank 9 register 1 + pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 652 Filter bank 9 register 2 + pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 656 Filter bank 10 register 1 + pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 660 Filter bank 10 register 2 + pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 664 Filter bank 11 register 1 + pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 668 Filter bank 11 register 2 + pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 672 Filter bank 4 register 1 + pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 676 Filter bank 12 register 2 + pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 680 Filter bank 13 register 1 + pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 684 Filter bank 13 register 2 + pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); +}; +pub const DAC = extern struct { + pub const Address: u32 = 0x40007400; + // byte offset: 0 Control register (DAC_CR) + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + EN1: u1, // bit offset: 0 desc: DAC channel1 enable + BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable + TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable + TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection + WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable + MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector + DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + EN2: u1, // bit offset: 16 desc: DAC channel2 enable + BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable + TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable + TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection + WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable + MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector + DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DAC software trigger register (DAC_SWTRIGR) + pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { + SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger + SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) + pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) + pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) + pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) + pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { + DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) + pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) + pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { + DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved + pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved + pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit right-aligned data + }); + // byte offset: 40 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved + pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 DAC channel1 data output register (DAC_DOR1) + pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { + DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 DAC channel2 data output register (DAC_DOR2) + pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { + DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DBG = extern struct { + pub const Address: u32 = 0xe0042000; + // byte offset: 0 DBGMCU_IDCODE + pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { + DEV_ID: u12, // bit offset: 0 desc: DEV_ID + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + REV_ID: u16, // bit offset: 16 desc: REV_ID + }); + // byte offset: 4 DBGMCU_CR + pub const CR = mmio(Address + 0x00000004, 32, packed struct { + DBG_SLEEP: u1, // bit offset: 0 desc: DBG_SLEEP + DBG_STOP: u1, // bit offset: 1 desc: DBG_STOP + DBG_STANDBY: u1, // bit offset: 2 desc: DBG_STANDBY + reserved2: u1 = 0, + reserved1: u1 = 0, + TRACE_IOEN: u1, // bit offset: 5 desc: TRACE_IOEN + TRACE_MODE: u2, // bit offset: 6 desc: TRACE_MODE + DBG_IWDG_STOP: u1, // bit offset: 8 desc: DBG_IWDG_STOP + DBG_WWDG_STOP: u1, // bit offset: 9 desc: DBG_WWDG_STOP + DBG_TIM1_STOP: u1, // bit offset: 10 desc: DBG_TIM1_STOP + DBG_TIM2_STOP: u1, // bit offset: 11 desc: DBG_TIM2_STOP + DBG_TIM3_STOP: u1, // bit offset: 12 desc: DBG_TIM3_STOP + DBG_TIM4_STOP: u1, // bit offset: 13 desc: DBG_TIM4_STOP + DBG_CAN1_STOP: u1, // bit offset: 14 desc: DBG_CAN1_STOP + DBG_I2C1_SMBUS_TIMEOUT: u1, // bit offset: 15 desc: DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, // bit offset: 16 desc: DBG_I2C2_SMBUS_TIMEOUT + DBG_TIM8_STOP: u1, // bit offset: 17 desc: DBG_TIM8_STOP + DBG_TIM5_STOP: u1, // bit offset: 18 desc: DBG_TIM5_STOP + DBG_TIM6_STOP: u1, // bit offset: 19 desc: DBG_TIM6_STOP + DBG_TIM7_STOP: u1, // bit offset: 20 desc: DBG_TIM7_STOP + DBG_CAN2_STOP: u1, // bit offset: 21 desc: DBG_CAN2_STOP + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART4 = extern struct { + pub const Address: u32 = 0x40004c00; + // byte offset: 0 UART4_SR + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NE: u1, // bit offset: 2 desc: Noise error flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: IDLE line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBD: u1, // bit offset: 8 desc: LIN break detection flag + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 UART4_DR + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DR: u9, // bit offset: 0 desc: DR + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 UART4_BRR + pub const BRR = mmio(Address + 0x00000008, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction + DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 UART4_CR1 + pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { + SBK: u1, // bit offset: 0 desc: Send break + RWU: u1, // bit offset: 1 desc: Receiver wakeup + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Wakeup method + M: u1, // bit offset: 12 desc: Word length + UE: u1, // bit offset: 13 desc: USART enable + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 UART4_CR2 + pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { + ADD: u4, // bit offset: 0 desc: Address of the USART node + reserved1: u1 = 0, + LBDL: u1, // bit offset: 5 desc: lin break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 UART4_CR3 + pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + reserved2: u1 = 0, + reserved1: u1 = 0, + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART5 = extern struct { + pub const Address: u32 = 0x40005000; + // byte offset: 0 UART4_SR + pub const SR = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: PE + FE: u1, // bit offset: 1 desc: FE + NE: u1, // bit offset: 2 desc: NE + ORE: u1, // bit offset: 3 desc: ORE + IDLE: u1, // bit offset: 4 desc: IDLE + RXNE: u1, // bit offset: 5 desc: RXNE + TC: u1, // bit offset: 6 desc: TC + TXE: u1, // bit offset: 7 desc: TXE + LBD: u1, // bit offset: 8 desc: LBD + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 UART4_DR + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DR: u9, // bit offset: 0 desc: DR + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 UART4_BRR + pub const BRR = mmio(Address + 0x00000008, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction + DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 UART4_CR1 + pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { + SBK: u1, // bit offset: 0 desc: SBK + RWU: u1, // bit offset: 1 desc: RWU + RE: u1, // bit offset: 2 desc: RE + TE: u1, // bit offset: 3 desc: TE + IDLEIE: u1, // bit offset: 4 desc: IDLEIE + RXNEIE: u1, // bit offset: 5 desc: RXNEIE + TCIE: u1, // bit offset: 6 desc: TCIE + TXEIE: u1, // bit offset: 7 desc: TXEIE + PEIE: u1, // bit offset: 8 desc: PEIE + PS: u1, // bit offset: 9 desc: PS + PCE: u1, // bit offset: 10 desc: PCE + WAKE: u1, // bit offset: 11 desc: WAKE + M: u1, // bit offset: 12 desc: M + UE: u1, // bit offset: 13 desc: UE + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 UART4_CR2 + pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { + ADD: u4, // bit offset: 0 desc: ADD + reserved1: u1 = 0, + LBDL: u1, // bit offset: 5 desc: LBDL + LBDIE: u1, // bit offset: 6 desc: LBDIE + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + STOP: u2, // bit offset: 12 desc: STOP + LINEN: u1, // bit offset: 14 desc: LINEN + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 UART4_CR3 + pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CRC = extern struct { + pub const Address: u32 = 0x40023000; + // byte offset: 0 Data register + pub const DR = mmio(Address + 0x00000000, 32, packed struct { + DR: u32, // bit offset: 0 desc: Data Register + }); + // byte offset: 4 Independent Data register + pub const IDR = mmio(Address + 0x00000004, 32, packed struct { + IDR: u8, // bit offset: 0 desc: Independent Data register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + RESET: u1, // bit offset: 0 desc: Reset bit + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const FLASH = extern struct { + pub const Address: u32 = 0x40022000; + // byte offset: 0 Flash access control register + pub const ACR = mmio(Address + 0x00000000, 32, packed struct { + LATENCY: u3, // bit offset: 0 desc: Latency + HLFCYA: u1, // bit offset: 3 desc: Flash half cycle access enable + PRFTBE: u1, // bit offset: 4 desc: Prefetch buffer enable + PRFTBS: u1, // bit offset: 5 desc: Prefetch buffer status + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Flash key register + pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { + KEY: u32, // bit offset: 0 desc: FPEC key + }); + // byte offset: 8 Flash option key register + pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { + OPTKEY: u32, // bit offset: 0 desc: Option byte key + }); + // byte offset: 12 Status register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + BSY: u1, // bit offset: 0 desc: Busy + reserved1: u1 = 0, + PGERR: u1, // bit offset: 2 desc: Programming error + reserved2: u1 = 0, + WRPRTERR: u1, // bit offset: 4 desc: Write protection error + EOP: u1, // bit offset: 5 desc: End of operation + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Control register + pub const CR = mmio(Address + 0x00000010, 32, packed struct { + PG: u1, // bit offset: 0 desc: Programming + PER: u1, // bit offset: 1 desc: Page Erase + MER: u1, // bit offset: 2 desc: Mass Erase + reserved1: u1 = 0, + OPTPG: u1, // bit offset: 4 desc: Option byte programming + OPTER: u1, // bit offset: 5 desc: Option byte erase + STRT: u1, // bit offset: 6 desc: Start + LOCK: u1, // bit offset: 7 desc: Lock + reserved2: u1 = 0, + OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable + ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + reserved3: u1 = 0, + EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Flash address register + pub const AR = mmio(Address + 0x00000014, 32, packed struct { + FAR: u32, // bit offset: 0 desc: Flash Address + }); + // byte offset: 28 Option byte register + pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { + OPTERR: u1, // bit offset: 0 desc: Option byte error + RDPRT: u1, // bit offset: 1 desc: Read protection + WDG_SW: u1, // bit offset: 2 desc: WDG_SW + nRST_STOP: u1, // bit offset: 3 desc: nRST_STOP + nRST_STDBY: u1, // bit offset: 4 desc: nRST_STDBY + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + Data0: u8, // bit offset: 10 desc: Data0 + Data1: u8, // bit offset: 18 desc: Data1 + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Write protection register + pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { + WRP: u32, // bit offset: 0 desc: Write protect + }); +}; +pub const NVIC = extern struct { + pub const Address: u32 = 0xe000e000; + // byte offset: 4 Interrupt Controller Type Register + pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { + INTLINESNUM: u4, // bit offset: 0 desc: Total number of interrupt lines in groups + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 256 Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 260 Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 384 Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 388 Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 512 Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 516 Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 640 Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 644 Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 768 Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 772 Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 1024 Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1028 Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1032 Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1036 Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1040 Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1044 Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1048 Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1052 Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1056 Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1060 Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1064 Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1068 Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1072 Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1076 Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1080 Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 3840 Software Triggered Interrupt Register + pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { + INTID: u9, // bit offset: 0 desc: interrupt to be triggered + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USB = extern struct { + pub const Address: u32 = 0x40005c00; + // byte offset: 0 endpoint 0 register + pub const EP0R = mmio(Address + 0x00000000, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 endpoint 1 register + pub const EP1R = mmio(Address + 0x00000004, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 endpoint 2 register + pub const EP2R = mmio(Address + 0x00000008, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 endpoint 3 register + pub const EP3R = mmio(Address + 0x0000000c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 endpoint 4 register + pub const EP4R = mmio(Address + 0x00000010, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 endpoint 5 register + pub const EP5R = mmio(Address + 0x00000014, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 endpoint 6 register + pub const EP6R = mmio(Address + 0x00000018, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 endpoint 7 register + pub const EP7R = mmio(Address + 0x0000001c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 control register + pub const CNTR = mmio(Address + 0x00000040, 32, packed struct { + FRES: u1, // bit offset: 0 desc: Force USB Reset + PDWN: u1, // bit offset: 1 desc: Power down + LPMODE: u1, // bit offset: 2 desc: Low-power mode + FSUSP: u1, // bit offset: 3 desc: Force suspend + RESUME: u1, // bit offset: 4 desc: Resume request + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask + SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask + RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask + SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask + WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask + ERRM: u1, // bit offset: 13 desc: Error interrupt mask + PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask + CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 interrupt status register + pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { + EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier + DIR: u1, // bit offset: 4 desc: Direction of transaction + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOF: u1, // bit offset: 8 desc: Expected start frame + SOF: u1, // bit offset: 9 desc: start of frame + RESET: u1, // bit offset: 10 desc: reset request + SUSP: u1, // bit offset: 11 desc: Suspend mode request + WKUP: u1, // bit offset: 12 desc: Wakeup + ERR: u1, // bit offset: 13 desc: Error + PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun + CTR: u1, // bit offset: 15 desc: Correct transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 frame number register + pub const FNR = mmio(Address + 0x00000048, 32, packed struct { + FN: u11, // bit offset: 0 desc: Frame number + LSOF: u2, // bit offset: 11 desc: Lost SOF + LCK: u1, // bit offset: 13 desc: Locked + RXDM: u1, // bit offset: 14 desc: Receive data - line status + RXDP: u1, // bit offset: 15 desc: Receive data + line status + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 device address + pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { + ADD: u7, // bit offset: 0 desc: Device address + EF: u1, // bit offset: 7 desc: Enable function + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 Buffer table address + pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + BTABLE: u13, // bit offset: 3 desc: Buffer table + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig new file mode 100644 index 0000000..7f6e072 --- /dev/null +++ b/src/modules/chips/stm32f103/stm32f103.zig @@ -0,0 +1,11 @@ +const std = @import("std"); +const micro = @import("microzig"); +const micro_linker = @import("microzig-linker"); + +pub const cpu = @import("cpu"); +pub const registers = @import("registers.zig"); + +pub const memory_regions = [_]micro_linker.MemoryRegion{ + micro_linker.MemoryRegion{ .offset = 0x00000000, .length = 64 * 1024, .kind = .flash }, + micro_linker.MemoryRegion{ .offset = 0x10000000, .length = 20 * 1024, .kind = .ram }, +}; diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index a58f472..3f4c648 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const Cpu = @import("Cpu.zig"); fn root() []const u8 { return std.fs.path.dirname(@src().file) orelse unreachable; @@ -6,12 +7,6 @@ fn root() []const u8 { const root_path = root() ++ "/"; -pub const Cpu = struct { - name: []const u8, - path: []const u8, - target: std.zig.CrossTarget, -}; - pub const avr5 = Cpu{ .name = "AVR5", .path = root_path ++ "cpus/avr/avr5.zig", diff --git a/tests/blinky.zig b/tests/blinky.zig index b7068be..1ef09bc 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -13,6 +13,7 @@ const led_pin = if (micro.config.has_board) else switch (micro.config.chip_name) { .@"ATmega328p" => micro.Pin("PB5"), .@"NXP LPC1768" => micro.Pin("P1.18"), + .@"STM32F103x8" => micro.Pin("PC13"), else => @compileError("unknown chip"), }; From f46c2e4ea9a3594a8f2c699611f3251bb676a8b1 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 8 Jan 2022 12:48:20 -0800 Subject: [PATCH 020/138] Microzig as pkg (#10) * works as a package * run zig fmt on all files --- src/core/clock.zig | 2 +- src/core/microzig.zig | 41 ---------- src/core/start.zig | 46 +++++++++++ src/main.zig | 95 +++++++++++++++-------- src/modules/chips/lpc1768/registers.zig | 1 - src/modules/chips/stm32f103/registers.zig | 1 - src/modules/chips/stm32f103/stm32f103.zig | 7 -- src/modules/cpus/avr/avr5.zig | 12 +-- 8 files changed, 114 insertions(+), 91 deletions(-) create mode 100644 src/core/start.zig diff --git a/src/core/clock.zig b/src/core/clock.zig index 11fbbd0..ee7b408 100644 --- a/src/core/clock.zig +++ b/src/core/clock.zig @@ -35,7 +35,7 @@ pub fn ensure() void { } /// Returns the current cpu frequency in hertz. -pub fn get() callconv(.Inline) u32 { +pub inline fn get() u32 { ensure(); return @field(clock_source_type, freq_decl_name); } diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 4664fc5..893a8ab 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -66,47 +66,6 @@ pub fn hang() noreturn { } } -/// This is the logical entry point for microzig. -/// It will invoke the main function from the root source file -/// and provides error return handling as well as a event loop if requested. -/// -/// Why is this function exported? -/// This is due to the modular design of microzig to allow the "chip" dependency of microzig -/// to call into our main function here. If we would use a normal function call, we'd have a -/// circular dependency between the `microzig` and `chip` package. This function is also likely -/// to be invoked from assembly, so it's also convenient in that regard. -export fn microzig_main() noreturn { - if (!@hasDecl(root, "main")) - @compileError("The root source file must provide a public function main!"); - - const main = @field(root, "main"); - const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); - - const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; - if (info != .Fn or info.Fn.args.len > 0) - @compileError(invalid_main_msg); - - const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); - - if (info.Fn.calling_convention == .Async) - @compileError("TODO: Embedded event loop not supported yet. Please try again later."); - - if (@typeInfo(return_type) == .ErrorUnion) { - main() catch |err| { - // TODO: - // - Compute maximum size on the type of "err" - // - Do not emit error names when std.builtin.strip is set. - var msg: [64]u8 = undefined; - @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); - }; - } else { - main(); - } - - // main returned, just hang around here a bit - hang(); -} - comptime { _ = cpu.startup_logic; } diff --git a/src/core/start.zig b/src/core/start.zig new file mode 100644 index 0000000..b84c395 --- /dev/null +++ b/src/core/start.zig @@ -0,0 +1,46 @@ +const std = @import("std"); +const app = @import("app"); +const microzig = @import("microzig"); + +pub usingnamespace app; + +/// This is the logical entry point for microzig. +/// It will invoke the main function from the root source file +/// and provides error return handling as well as a event loop if requested. +/// +/// Why is this function exported? +/// This is due to the modular design of microzig to allow the "chip" dependency of microzig +/// to call into our main function here. If we would use a normal function call, we'd have a +/// circular dependency between the `microzig` and `chip` package. This function is also likely +/// to be invoked from assembly, so it's also convenient in that regard. +export fn microzig_main() noreturn { + if (!@hasDecl(app, "main")) + @compileError("The root source file must provide a public function main!"); + + const main = @field(app, "main"); + const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); + + const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; + if (info != .Fn or info.Fn.args.len > 0) + @compileError(invalid_main_msg); + + const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); + + if (info.Fn.calling_convention == .Async) + @compileError("TODO: Embedded event loop not supported yet. Please try again later."); + + if (@typeInfo(return_type) == .ErrorUnion) { + main() catch |err| { + // TODO: + // - Compute maximum size on the type of "err" + // - Do not emit error names when std.builtin.strip is set. + var msg: [64]u8 = undefined; + @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); + }; + } else { + main(); + } + + // main returned, just hang around here a bit + microzig.hang(); +} diff --git a/src/main.zig b/src/main.zig index 7a0ee96..0141522 100644 --- a/src/main.zig +++ b/src/main.zig @@ -12,6 +12,7 @@ pub const Backing = union(enum) { chip: Chip, }; +const Pkg = std.build.Pkg; const root_path = root() ++ "/"; fn root() []const u8 { return std.fs.path.dirname(@src().file) orelse unreachable; @@ -23,34 +24,12 @@ pub fn addEmbeddedExecutable( source: []const u8, backing: Backing, ) !*std.build.LibExeObjStep { - const Pkg = std.build.Pkg; - - const microzig_base = Pkg{ - .name = "microzig", - .path = .{ .path = root_path ++ "core/microzig.zig" }, - }; - + const has_board = (backing == .board); const chip = switch (backing) { .chip => |c| c, .board => |b| b.chip, }; - const has_board = (backing == .board); - - const chip_package = Pkg{ - .name = "chip", - .path = .{ .path = chip.path }, - .dependencies = &[_]Pkg{ - microzig_base, - pkgs.mmio, - Pkg{ - .name = "cpu", - .path = .{ .path = chip.cpu.path }, - .dependencies = &[_]Pkg{ microzig_base, pkgs.mmio }, - }, - }, - }; - const config_file_name = blk: { const hash = hash_blk: { var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); @@ -97,47 +76,95 @@ pub fn addEmbeddedExecutable( try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); } + const microzig_pkg = Pkg{ + .name = "microzig", + .path = .{ .path = root_path ++ "core/microzig.zig" }, + }; + + const chip_pkg = Pkg{ + .name = "chip", + .path = .{ .path = chip.path }, + .dependencies = &[_]Pkg{ + microzig_pkg, + pkgs.mmio, + Pkg{ + .name = "cpu", + .path = .{ .path = chip.cpu.path }, + .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio }, + }, + }, + }; + const config_pkg = Pkg{ .name = "microzig-config", .path = .{ .path = config_file_name }, }; - const linkerscript = try LinkerScriptStep.create(builder, chip); - const exe = builder.addExecutable(name, source); + const exe = builder.addExecutable(name, root_path ++ "core/start.zig"); // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) exe.single_threaded = true; exe.setTarget(chip.cpu.target); + const linkerscript = try LinkerScriptStep.create(builder, chip); exe.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); // TODO: // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.bundle_compiler_rt = false; - switch (backing) { .chip => { exe.addPackage(Pkg{ - .name = microzig_base.name, - .path = microzig_base.path, - .dependencies = &[_]Pkg{ config_pkg, chip_package }, + .name = "app", + .path = .{ .path = source }, + .dependencies = &[_]Pkg{ + Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, + .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, + }, + }, + }); + exe.addPackage(Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, + .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, }); }, .board => |board| { exe.addPackage(Pkg{ - .name = microzig_base.name, - .path = microzig_base.path, + .name = "app", + .path = .{ .path = source }, + .dependencies = &[_]Pkg{ + Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, + .dependencies = &[_]Pkg{ + config_pkg, + chip_pkg, + Pkg{ + .name = "board", + .path = .{ .path = board.path }, + .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, + }, + }, + }, + }, + }); + + exe.addPackage(Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, .dependencies = &[_]Pkg{ config_pkg, - chip_package, + chip_pkg, Pkg{ .name = "board", .path = .{ .path = board.path }, - .dependencies = &[_]Pkg{ microzig_base, chip_package, pkgs.mmio }, + .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, }, }, }); diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index e950a28..807b7a4 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -21724,4 +21724,3 @@ pub const GPIO = extern struct { PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); }; - diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 2fb9d71..8f26813 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -17770,4 +17770,3 @@ pub const USB = extern struct { padding1: u1 = 0, }); }; - diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig index 7f6e072..6ede441 100644 --- a/src/modules/chips/stm32f103/stm32f103.zig +++ b/src/modules/chips/stm32f103/stm32f103.zig @@ -1,11 +1,4 @@ const std = @import("std"); -const micro = @import("microzig"); -const micro_linker = @import("microzig-linker"); pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); - -pub const memory_regions = [_]micro_linker.MemoryRegion{ - micro_linker.MemoryRegion{ .offset = 0x00000000, .length = 64 * 1024, .kind = .flash }, - micro_linker.MemoryRegion{ .offset = 0x10000000, .length = 20 * 1024, .kind = .ram }, -}; diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index baa0093..d53fd3a 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -1,26 +1,26 @@ const std = @import("std"); -pub fn sei() callconv(.Inline) void { +pub inline fn sei() void { asm volatile ("sei"); } -pub fn cli() callconv(.Inline) void { +pub inline fn cli() void { asm volatile ("cli"); } -pub fn sbi(comptime reg: u5, comptime bit: u3) callconv(.Inline) void { +pub inline fn sbi(comptime reg: u5, comptime bit: u3) void { asm volatile ("sbi %[reg], %[bit]" : : [reg] "I" (reg), - [bit] "I" (bit) + [bit] "I" (bit), ); } -pub fn cbi(comptime reg: u5, comptime bit: u3) callconv(.Inline) void { +pub inline fn cbi(comptime reg: u5, comptime bit: u3) void { asm volatile ("cbi %[reg], %[bit]" : : [reg] "I" (reg), - [bit] "I" (bit) + [bit] "I" (bit), ); } From 1b5cc2ad1fb93212e3265915e0adafc5bc16116f Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Thu, 27 Jan 2022 20:43:47 +0100 Subject: [PATCH 021/138] Support STM32F3DISCOVERY board (#11) * Support disabling UART test configs * `zig build [install]` also builds .bin files * Support one blinking LD3 on STM32F3DISCOVERY board These changes were mostly copied from the stm32f103 already there. But this is far from complete, many shortcuts were taken: - Most importantly, only a single LED on the board, and its port/pin, is supported, viz. the 'north' LD3 on bit 9 of GPIOE. - Setting RCC_AHBENR bit IOPEEN ("I/O port E clock enable") is done at the same as setting the mode (input or output) on one of its pins. No idea if that is the right place to do this. - In cortex-m4.zig, using 'max ram' as the initial stack pointer. The rest is completely copied from cortex-m3.zig. - UART test is disabled. (It seems to assume mbed-lpc1768 pin numbers.) * Nicer initial stack pointer: exactly after RAM * Fix build error (How was this code working earlier?!?) * stm32f30x: Allow all 16 pins, all GPIOx registers * STM32F3DISCOVERY: map all LED pins --- build.zig | 18 +- src/modules/boards.zig | 6 + .../stm32f3discovery/stm32f3discovery.zig | 24 + src/modules/chips.zig | 10 + src/modules/chips/stm32f30x/registers.zig | 19599 ++++++++++++++++ src/modules/chips/stm32f30x/stm32f30x.zig | 55 + src/modules/cpus.zig | 11 + src/modules/cpus/cortex-m4/cortex-m4.zig | 103 + tests/blinky.zig | 1 + 9 files changed, 19823 insertions(+), 4 deletions(-) create mode 100644 src/modules/boards/stm32f3discovery/stm32f3discovery.zig create mode 100644 src/modules/chips/stm32f30x/registers.zig create mode 100644 src/modules/chips/stm32f30x/stm32f30x.zig create mode 100644 src/modules/cpus/cortex-m4/cortex-m4.zig diff --git a/build.zig b/build.zig index 0006e71..62771e2 100644 --- a/build.zig +++ b/build.zig @@ -14,29 +14,32 @@ pub fn build(b: *std.build.Builder) !void { const test_step = b.step("test", "Builds and runs the library test suite"); - const BuildConfig = struct { name: []const u8, backing: Backing }; + const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart: bool = true }; const all_backings = [_]BuildConfig{ //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, + BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart = false }, }; - const Test = struct { name: []const u8, source: []const u8 }; + const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false }; const all_tests = [_]Test{ Test{ .name = "minimal", .source = "tests/minimal.zig" }, Test{ .name = "blinky", .source = "tests/blinky.zig" }, - Test{ .name = "uart-sync", .source = "tests/uart-sync.zig" }, + Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); inline for (all_backings) |cfg| { inline for (all_tests) |tst| { + if (tst.uses_uart and !cfg.supports_uart) continue; + const exe = try microzig.addEmbeddedExecutable( b, - "test-" ++ tst.name ++ "-" ++ cfg.name, + "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".elf", tst.source, cfg.backing, ); @@ -46,6 +49,13 @@ pub fn build(b: *std.build.Builder) !void { exe.install(); test_step.dependOn(&exe.step); + + const bin = b.addInstallRaw( + exe, + "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".bin", + .{}, + ); + b.getInstallStep().dependOn(&bin.step); } } } diff --git a/src/modules/boards.zig b/src/modules/boards.zig index f68ce1c..6c03b51 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -19,3 +19,9 @@ pub const mbed_lpc1768 = Board{ .path = root_path ++ "boards/mbed-lpc1768/mbed-lpc1768.zig", .chip = chips.lpc1768, }; + +pub const stm32f3discovery = Board{ + .name = "STM32F3DISCOVERY", + .path = root_path ++ "boards/stm32f3discovery/stm32f3discovery.zig", + .chip = chips.stm32f30x, +}; diff --git a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig new file mode 100644 index 0000000..8f2aa47 --- /dev/null +++ b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig @@ -0,0 +1,24 @@ +pub const chip = @import("chip"); + +pub const cpu_frequency = 8_000_000; + +pub const pin_map = .{ + // circle of LEDs, connected to GPIOE bits 8..15 + + // NW blue + .@"LD4" = "PE8", + // N red + .@"LD3" = "PE9", + // NE orange + .@"LD5" = "PE10", + // E green + .@"LD7" = "PE11", + // SE blue + .@"LD9" = "PE12", + // S red + .@"LD10" = "PE13", + // SW orange + .@"LD8" = "PE14", + // W green + .@"LD6" = "PE15", +}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index d4baf93..13cd9ba 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -39,3 +39,13 @@ pub const stm32f103x8 = Chip{ MemoryRegion{ .offset = 0x10000000, .length = 20 * 1024, .kind = .ram }, }, }; + +pub const stm32f30x = Chip{ + .name = "STM32F30x", + .path = root_path ++ "chips/stm32f30x/stm32f30x.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram }, + }, +}; diff --git a/src/modules/chips/stm32f30x/registers.zig b/src/modules/chips/stm32f30x/registers.zig new file mode 100644 index 0000000..ffea679 --- /dev/null +++ b/src/modules/chips/stm32f30x/registers.zig @@ -0,0 +1,19599 @@ +// generated using svd2zig.py +// DO NOT EDIT +// based on STM32F30x version 1.4 +const mmio = @import("microzig-mmio").mmio; +const Name = "STM32F30x"; +pub const GPIOA = extern struct { + pub const Address: u32 = 0x48000000; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OT1: u1, // bit offset: 1 desc: Port x configuration bits (y = 0..15) + OT2: u1, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OT3: u1, // bit offset: 3 desc: Port x configuration bits (y = 0..15) + OT4: u1, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OT5: u1, // bit offset: 5 desc: Port x configuration bits (y = 0..15) + OT6: u1, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OT7: u1, // bit offset: 7 desc: Port x configuration bits (y = 0..15) + OT8: u1, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OT9: u1, // bit offset: 9 desc: Port x configuration bits (y = 0..15) + OT10: u1, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OT11: u1, // bit offset: 11 desc: Port x configuration bits (y = 0..15) + OT12: u1, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OT13: u1, // bit offset: 13 desc: Port x configuration bits (y = 0..15) + OT14: u1, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OT15: u1, // bit offset: 15 desc: Port x configuration bits (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOB = extern struct { + pub const Address: u32 = 0x48000400; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOC = extern struct { + pub const Address: u32 = 0x48000800; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOD = extern struct { + pub const Address: u32 = 0x48000c00; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOE = extern struct { + pub const Address: u32 = 0x48001000; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const GPIOF = extern struct { + pub const Address: u32 = 0x48001400; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TSC = extern struct { + pub const Address: u32 = 0x40024000; + // byte offset: 0 control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + TSCE: u1, // bit offset: 0 desc: Touch sensing controller enable + START: u1, // bit offset: 1 desc: Start a new acquisition + AM: u1, // bit offset: 2 desc: Acquisition mode + SYNCPOL: u1, // bit offset: 3 desc: Synchronization pin polarity + IODEF: u1, // bit offset: 4 desc: I/O Default mode + MCV: u3, // bit offset: 5 desc: Max count value + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PGPSC: u3, // bit offset: 12 desc: pulse generator prescaler + SSPSC: u1, // bit offset: 15 desc: Spread spectrum prescaler + SSE: u1, // bit offset: 16 desc: Spread spectrum enable + SSD: u7, // bit offset: 17 desc: Spread spectrum deviation + CTPL: u4, // bit offset: 24 desc: Charge transfer pulse low + CTPH: u4, // bit offset: 28 desc: Charge transfer pulse high + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + EOAIE: u1, // bit offset: 0 desc: End of acquisition interrupt enable + MCEIE: u1, // bit offset: 1 desc: Max count error interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 interrupt clear register + pub const ICR = mmio(Address + 0x00000008, 32, packed struct { + EOAIC: u1, // bit offset: 0 desc: End of acquisition interrupt clear + MCEIC: u1, // bit offset: 1 desc: Max count error interrupt clear + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 interrupt status register + pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { + EOAF: u1, // bit offset: 0 desc: End of acquisition flag + MCEF: u1, // bit offset: 1 desc: Max count error flag + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 I/O hysteresis control register + pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 Schmitt trigger hysteresis mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 Schmitt trigger hysteresis mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 Schmitt trigger hysteresis mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 Schmitt trigger hysteresis mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 Schmitt trigger hysteresis mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 Schmitt trigger hysteresis mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 Schmitt trigger hysteresis mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 Schmitt trigger hysteresis mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 Schmitt trigger hysteresis mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 Schmitt trigger hysteresis mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 Schmitt trigger hysteresis mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 Schmitt trigger hysteresis mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 Schmitt trigger hysteresis mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 Schmitt trigger hysteresis mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 Schmitt trigger hysteresis mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 Schmitt trigger hysteresis mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 Schmitt trigger hysteresis mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 Schmitt trigger hysteresis mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 Schmitt trigger hysteresis mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 Schmitt trigger hysteresis mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 Schmitt trigger hysteresis mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 Schmitt trigger hysteresis mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 Schmitt trigger hysteresis mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 Schmitt trigger hysteresis mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 Schmitt trigger hysteresis mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 Schmitt trigger hysteresis mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 Schmitt trigger hysteresis mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 Schmitt trigger hysteresis mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 Schmitt trigger hysteresis mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 Schmitt trigger hysteresis mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 Schmitt trigger hysteresis mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 Schmitt trigger hysteresis mode + }); + // byte offset: 24 I/O analog switch control register + pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 analog switch enable + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 analog switch enable + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 analog switch enable + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 analog switch enable + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 analog switch enable + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 analog switch enable + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 analog switch enable + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 analog switch enable + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 analog switch enable + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 analog switch enable + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 analog switch enable + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 analog switch enable + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 analog switch enable + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 analog switch enable + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 analog switch enable + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 analog switch enable + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 analog switch enable + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 analog switch enable + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 analog switch enable + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 analog switch enable + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 analog switch enable + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 analog switch enable + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 analog switch enable + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 analog switch enable + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 analog switch enable + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 analog switch enable + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 analog switch enable + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 analog switch enable + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 analog switch enable + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 analog switch enable + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 analog switch enable + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 analog switch enable + }); + // byte offset: 32 I/O sampling control register + pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 sampling mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 sampling mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 sampling mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 sampling mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 sampling mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 sampling mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 sampling mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 sampling mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 sampling mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 sampling mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 sampling mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 sampling mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 sampling mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 sampling mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 sampling mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 sampling mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 sampling mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 sampling mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 sampling mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 sampling mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 sampling mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 sampling mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 sampling mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 sampling mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 sampling mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 sampling mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 sampling mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 sampling mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 sampling mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 sampling mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 sampling mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 sampling mode + }); + // byte offset: 40 I/O channel control register + pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 channel mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 channel mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 channel mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 channel mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 channel mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 channel mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 channel mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 channel mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 channel mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 channel mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 channel mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 channel mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 channel mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 channel mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 channel mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 channel mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 channel mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 channel mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 channel mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 channel mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 channel mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 channel mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 channel mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 channel mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 channel mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 channel mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 channel mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 channel mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 channel mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 channel mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 channel mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 channel mode + }); + // byte offset: 48 I/O group control status register + pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { + G1E: u1, // bit offset: 0 desc: Analog I/O group x enable + G2E: u1, // bit offset: 1 desc: Analog I/O group x enable + G3E: u1, // bit offset: 2 desc: Analog I/O group x enable + G4E: u1, // bit offset: 3 desc: Analog I/O group x enable + G5E: u1, // bit offset: 4 desc: Analog I/O group x enable + G6E: u1, // bit offset: 5 desc: Analog I/O group x enable + G7E: u1, // bit offset: 6 desc: Analog I/O group x enable + G8E: u1, // bit offset: 7 desc: Analog I/O group x enable + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + G1S: u1, // bit offset: 16 desc: Analog I/O group x status + G2S: u1, // bit offset: 17 desc: Analog I/O group x status + G3S: u1, // bit offset: 18 desc: Analog I/O group x status + G4S: u1, // bit offset: 19 desc: Analog I/O group x status + G5S: u1, // bit offset: 20 desc: Analog I/O group x status + G6S: u1, // bit offset: 21 desc: Analog I/O group x status + G7S: u1, // bit offset: 22 desc: Analog I/O group x status + G8S: u1, // bit offset: 23 desc: Analog I/O group x status + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 I/O group x counter register + pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 I/O group x counter register + pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 I/O group x counter register + pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 I/O group x counter register + pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 I/O group x counter register + pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 I/O group x counter register + pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 I/O group x counter register + pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 I/O group x counter register + pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CRC = extern struct { + pub const Address: u32 = 0x40023000; + // byte offset: 0 Data register + pub const DR = mmio(Address + 0x00000000, 32, packed struct { + DR: u32, // bit offset: 0 desc: Data register bits + }); + // byte offset: 4 Independent data register + pub const IDR = mmio(Address + 0x00000004, 32, packed struct { + IDR: u8, // bit offset: 0 desc: General-purpose 8-bit data register bits + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + RESET: u1, // bit offset: 0 desc: reset bit + reserved2: u1 = 0, + reserved1: u1 = 0, + POLYSIZE: u2, // bit offset: 3 desc: Polynomial size + REV_IN: u2, // bit offset: 5 desc: Reverse input data + REV_OUT: u1, // bit offset: 7 desc: Reverse output data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Initial CRC value + pub const INIT = mmio(Address + 0x00000010, 32, packed struct { + INIT: u32, // bit offset: 0 desc: Programmable initial CRC value + }); + // byte offset: 20 CRC polynomial + pub const POL = mmio(Address + 0x00000014, 32, packed struct { + POL: u32, // bit offset: 0 desc: Programmable polynomial + }); +}; +pub const Flash = extern struct { + pub const Address: u32 = 0x40022000; + // byte offset: 0 Flash access control register + pub const ACR = mmio(Address + 0x00000000, 32, packed struct { + LATENCY: u3, // bit offset: 0 desc: LATENCY + reserved1: u1 = 0, + PRFTBE: u1, // bit offset: 4 desc: PRFTBE + PRFTBS: u1, // bit offset: 5 desc: PRFTBS + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Flash key register + pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { + FKEYR: u32, // bit offset: 0 desc: Flash Key + }); + // byte offset: 8 Flash option key register + pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { + OPTKEYR: u32, // bit offset: 0 desc: Option byte key + }); + // byte offset: 12 Flash status register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + BSY: u1, // bit offset: 0 desc: Busy + reserved1: u1 = 0, + PGERR: u1, // bit offset: 2 desc: Programming error + reserved2: u1 = 0, + WRPRT: u1, // bit offset: 4 desc: Write protection error + EOP: u1, // bit offset: 5 desc: End of operation + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Flash control register + pub const CR = mmio(Address + 0x00000010, 32, packed struct { + PG: u1, // bit offset: 0 desc: Programming + PER: u1, // bit offset: 1 desc: Page erase + MER: u1, // bit offset: 2 desc: Mass erase + reserved1: u1 = 0, + OPTPG: u1, // bit offset: 4 desc: Option byte programming + OPTER: u1, // bit offset: 5 desc: Option byte erase + STRT: u1, // bit offset: 6 desc: Start + LOCK: u1, // bit offset: 7 desc: Lock + reserved2: u1 = 0, + OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable + ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + reserved3: u1 = 0, + EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable + FORCE_OPTLOAD: u1, // bit offset: 13 desc: Force option byte loading + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Flash address register + pub const AR = mmio(Address + 0x00000014, 32, packed struct { + FAR: u32, // bit offset: 0 desc: Flash address + }); + // byte offset: 28 Option byte register + pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { + OPTERR: u1, // bit offset: 0 desc: Option byte error + LEVEL1_PROT: u1, // bit offset: 1 desc: Level 1 protection status + LEVEL2_PROT: u1, // bit offset: 2 desc: Level 2 protection status + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + WDG_SW: u1, // bit offset: 8 desc: WDG_SW + nRST_STOP: u1, // bit offset: 9 desc: nRST_STOP + nRST_STDBY: u1, // bit offset: 10 desc: nRST_STDBY + reserved6: u1 = 0, + BOOT1: u1, // bit offset: 12 desc: BOOT1 + VDDA_MONITOR: u1, // bit offset: 13 desc: VDDA_MONITOR + SRAM_PARITY_CHECK: u1, // bit offset: 14 desc: SRAM_PARITY_CHECK + reserved7: u1 = 0, + Data0: u8, // bit offset: 16 desc: Data0 + Data1: u8, // bit offset: 24 desc: Data1 + }); + // byte offset: 32 Write protection register + pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { + WRP: u32, // bit offset: 0 desc: Write protect + }); +}; +pub const RCC = extern struct { + pub const Address: u32 = 0x40021000; + // byte offset: 0 Clock control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable + HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag + reserved1: u1 = 0, + HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming + HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration + HSEON: u1, // bit offset: 16 desc: External High Speed clock enable + HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag + HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass + CSSON: u1, // bit offset: 19 desc: Clock Security System enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + PLLON: u1, // bit offset: 24 desc: PLL enable + PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Clock configuration register (RCC_CFGR) + pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { + SW: u2, // bit offset: 0 desc: System clock Switch + SWS: u2, // bit offset: 2 desc: System Clock Switch Status + HPRE: u4, // bit offset: 4 desc: AHB prescaler + PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) + PPRE2: u3, // bit offset: 11 desc: APB high speed prescaler (APB2) + reserved2: u1 = 0, + reserved1: u1 = 0, + PLLSRC: u1, // bit offset: 16 desc: PLL entry clock source + PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry + PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor + USBPRES: u1, // bit offset: 22 desc: USB prescaler + I2SSRC: u1, // bit offset: 23 desc: I2S external clock source selection + MCO: u3, // bit offset: 24 desc: Microcontroller clock output + reserved3: u1 = 0, + MCOF: u1, // bit offset: 28 desc: Microcontroller Clock Output Flag + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Clock interrupt register (RCC_CIR) + pub const CIR = mmio(Address + 0x00000008, 32, packed struct { + LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag + LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag + HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag + HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag + PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag + reserved2: u1 = 0, + reserved1: u1 = 0, + CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag + LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable + LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable + HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable + HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable + PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear + LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear + HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear + HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear + PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + reserved7: u1 = 0, + reserved6: u1 = 0, + CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { + SYSCFGRST: u1, // bit offset: 0 desc: SYSCFG and COMP reset + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset + SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset + TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset + USART1RST: u1, // bit offset: 14 desc: USART1 reset + reserved11: u1 = 0, + TIM15RST: u1, // bit offset: 16 desc: TIM15 timer reset + TIM16RST: u1, // bit offset: 17 desc: TIM16 timer reset + TIM17RST: u1, // bit offset: 18 desc: TIM17 timer reset + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { + TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset + TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset + TIM4RST: u1, // bit offset: 2 desc: Timer 14 reset + reserved1: u1 = 0, + TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset + TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + reserved8: u1 = 0, + reserved7: u1 = 0, + SPI2RST: u1, // bit offset: 14 desc: SPI2 reset + SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + reserved9: u1 = 0, + USART2RST: u1, // bit offset: 17 desc: USART 2 reset + USART3RST: u1, // bit offset: 18 desc: USART3 reset + UART4RST: u1, // bit offset: 19 desc: UART 4 reset + UART5RST: u1, // bit offset: 20 desc: UART 5 reset + I2C1RST: u1, // bit offset: 21 desc: I2C1 reset + I2C2RST: u1, // bit offset: 22 desc: I2C2 reset + USBRST: u1, // bit offset: 23 desc: USB reset + reserved10: u1 = 0, + CANRST: u1, // bit offset: 25 desc: CAN reset + reserved12: u1 = 0, + reserved11: u1 = 0, + PWRRST: u1, // bit offset: 28 desc: Power interface reset + DACRST: u1, // bit offset: 29 desc: DAC interface reset + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMA1 clock enable + DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable + SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable + reserved1: u1 = 0, + FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable + reserved2: u1 = 0, + CRCEN: u1, // bit offset: 6 desc: CRC clock enable + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + IOPAEN: u1, // bit offset: 17 desc: I/O port A clock enable + IOPBEN: u1, // bit offset: 18 desc: I/O port B clock enable + IOPCEN: u1, // bit offset: 19 desc: I/O port C clock enable + IOPDEN: u1, // bit offset: 20 desc: I/O port D clock enable + IOPEEN: u1, // bit offset: 21 desc: I/O port E clock enable + IOPFEN: u1, // bit offset: 22 desc: I/O port F clock enable + reserved13: u1 = 0, + TSCEN: u1, // bit offset: 24 desc: Touch sensing controller clock enable + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + ADC12EN: u1, // bit offset: 28 desc: ADC1 and ADC2 clock enable + ADC34EN: u1, // bit offset: 29 desc: ADC3 and ADC4 clock enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { + SYSCFGEN: u1, // bit offset: 0 desc: SYSCFG clock enable + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable + SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable + TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable + USART1EN: u1, // bit offset: 14 desc: USART1 clock enable + reserved11: u1 = 0, + TIM15EN: u1, // bit offset: 16 desc: TIM15 timer clock enable + TIM16EN: u1, // bit offset: 17 desc: TIM16 timer clock enable + TIM17EN: u1, // bit offset: 18 desc: TIM17 timer clock enable + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { + TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable + TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable + TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable + reserved1: u1 = 0, + TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable + TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + reserved8: u1 = 0, + reserved7: u1 = 0, + SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable + SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + reserved9: u1 = 0, + USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable + I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable + USBEN: u1, // bit offset: 23 desc: USB clock enable + reserved13: u1 = 0, + CANEN: u1, // bit offset: 25 desc: CAN clock enable + reserved15: u1 = 0, + reserved14: u1 = 0, + PWREN: u1, // bit offset: 28 desc: Power interface clock enable + DACEN: u1, // bit offset: 29 desc: DAC interface clock enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Backup domain control register (RCC_BDCR) + pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { + LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable + LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready + LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass + LSEDRV: u2, // bit offset: 3 desc: LSE oscillator drive capability + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + RTCEN: u1, // bit offset: 15 desc: RTC clock enable + BDRST: u1, // bit offset: 16 desc: Backup domain software reset + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Control/status register (RCC_CSR) + pub const CSR = mmio(Address + 0x00000024, 32, packed struct { + LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable + LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RMVF: u1, // bit offset: 24 desc: Remove reset flag + OBLRSTF: u1, // bit offset: 25 desc: Option byte loader reset flag + PINRSTF: u1, // bit offset: 26 desc: PIN reset flag + PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag + SFTRSTF: u1, // bit offset: 28 desc: Software reset flag + IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag + WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag + LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + }); + // byte offset: 40 AHB peripheral reset register + pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + IOPARST: u1, // bit offset: 17 desc: I/O port A reset + IOPBRST: u1, // bit offset: 18 desc: I/O port B reset + IOPCRST: u1, // bit offset: 19 desc: I/O port C reset + IOPDRST: u1, // bit offset: 20 desc: I/O port D reset + IOPERST: u1, // bit offset: 21 desc: I/O port E reset + IOPFRST: u1, // bit offset: 22 desc: I/O port F reset + reserved18: u1 = 0, + TSCRST: u1, // bit offset: 24 desc: Touch sensing controller reset + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + ADC12RST: u1, // bit offset: 28 desc: ADC1 and ADC2 reset + ADC34RST: u1, // bit offset: 29 desc: ADC3 and ADC4 reset + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Clock configuration register 2 + pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { + PREDIV: u4, // bit offset: 0 desc: PREDIV division factor + ADC12PRES: u5, // bit offset: 4 desc: ADC1 and ADC2 prescaler + ADC34PRES: u5, // bit offset: 9 desc: ADC3 and ADC4 prescaler + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 Clock configuration register 3 + pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { + USART1SW: u2, // bit offset: 0 desc: USART1 clock source selection + reserved2: u1 = 0, + reserved1: u1 = 0, + I2C1SW: u1, // bit offset: 4 desc: I2C1 clock source selection + I2C2SW: u1, // bit offset: 5 desc: I2C2 clock source selection + reserved4: u1 = 0, + reserved3: u1 = 0, + TIM1SW: u1, // bit offset: 8 desc: Timer1 clock source selection + TIM8SW: u1, // bit offset: 9 desc: Timer8 clock source selection + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + USART2SW: u2, // bit offset: 16 desc: USART2 clock source selection + USART3SW: u2, // bit offset: 18 desc: USART3 clock source selection + UART4SW: u2, // bit offset: 20 desc: UART4 clock source selection + UART5SW: u2, // bit offset: 22 desc: UART5 clock source selection + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DMA1 = extern struct { + pub const Address: u32 = 0x40020000; + // byte offset: 0 DMA interrupt status register (DMA_ISR) + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag + TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag + HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag + TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag + GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag + TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag + HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag + TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag + GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag + TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag + HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag + TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag + GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag + TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag + HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag + TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag + GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag + TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag + HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag + TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag + GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag + TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag + HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag + TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag + GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag + TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag + HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag + TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { + CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear + CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear + CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear + CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear + CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear + CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear + CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear + CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear + CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear + CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear + CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear + CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear + CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear + CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear + CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear + CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear + CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear + CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear + CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear + CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear + CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear + CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear + CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear + CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear + CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear + CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear + CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear + CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA channel 1 number of data register + pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DMA channel 1 peripheral address register + pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 20 DMA channel 1 memory address register + pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 28 DMA channel configuration register (DMA_CCR) + pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 DMA channel 2 number of data register + pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DMA channel 2 peripheral address register + pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 40 DMA channel 2 memory address register + pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 48 DMA channel configuration register (DMA_CCR) + pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 DMA channel 3 number of data register + pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 DMA channel 3 peripheral address register + pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 60 DMA channel 3 memory address register + pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 68 DMA channel configuration register (DMA_CCR) + pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA channel 4 number of data register + pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA channel 4 peripheral address register + pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 80 DMA channel 4 memory address register + pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 88 DMA channel configuration register (DMA_CCR) + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 DMA channel 5 number of data register + pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 DMA channel 5 peripheral address register + pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 100 DMA channel 5 memory address register + pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 108 DMA channel configuration register (DMA_CCR) + pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 DMA channel 6 number of data register + pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 DMA channel 6 peripheral address register + pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 120 DMA channel 6 memory address register + pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 128 DMA channel configuration register (DMA_CCR) + pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 DMA channel 7 number of data register + pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 DMA channel 7 peripheral address register + pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 140 DMA channel 7 memory address register + pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); +}; +pub const DMA2 = extern struct { + pub const Address: u32 = 0x40020400; + // byte offset: 0 DMA interrupt status register (DMA_ISR) + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag + TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag + HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag + TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag + GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag + TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag + HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag + TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag + GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag + TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag + HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag + TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag + GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag + TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag + HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag + TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag + GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag + TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag + HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag + TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag + GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag + TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag + HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag + TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag + GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag + TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag + HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag + TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { + CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear + CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear + CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear + CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear + CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear + CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear + CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear + CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear + CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear + CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear + CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear + CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear + CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear + CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear + CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear + CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear + CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear + CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear + CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear + CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear + CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear + CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear + CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear + CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear + CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear + CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear + CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear + CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA channel 1 number of data register + pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 DMA channel 1 peripheral address register + pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 20 DMA channel 1 memory address register + pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 28 DMA channel configuration register (DMA_CCR) + pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 DMA channel 2 number of data register + pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DMA channel 2 peripheral address register + pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 40 DMA channel 2 memory address register + pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 48 DMA channel configuration register (DMA_CCR) + pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 DMA channel 3 number of data register + pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 DMA channel 3 peripheral address register + pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 60 DMA channel 3 memory address register + pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 68 DMA channel configuration register (DMA_CCR) + pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA channel 4 number of data register + pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA channel 4 peripheral address register + pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 80 DMA channel 4 memory address register + pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 88 DMA channel configuration register (DMA_CCR) + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 92 DMA channel 5 number of data register + pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 DMA channel 5 peripheral address register + pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 100 DMA channel 5 memory address register + pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 108 DMA channel configuration register (DMA_CCR) + pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 112 DMA channel 6 number of data register + pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 116 DMA channel 6 peripheral address register + pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 120 DMA channel 6 memory address register + pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 128 DMA channel configuration register (DMA_CCR) + pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 DMA channel 7 number of data register + pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 DMA channel 7 peripheral address register + pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 140 DMA channel 7 memory address register + pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); +}; +pub const TIM2 = extern struct { + pub const Address: u32 = 0x40000000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved3: u1 = 0, + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved4: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNTL: u16, // bit offset: 0 desc: Low counter value + CNTH: u15, // bit offset: 16 desc: High counter value + CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARRL: u16, // bit offset: 0 desc: Low Auto-reload value + ARRH: u16, // bit offset: 16 desc: High Auto-reload value + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value + CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value + CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM3 = extern struct { + pub const Address: u32 = 0x40000400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved3: u1 = 0, + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved4: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNTL: u16, // bit offset: 0 desc: Low counter value + CNTH: u15, // bit offset: 16 desc: High counter value + CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARRL: u16, // bit offset: 0 desc: Low Auto-reload value + ARRH: u16, // bit offset: 16 desc: High Auto-reload value + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value + CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value + CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM4 = extern struct { + pub const Address: u32 = 0x40000800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + reserved1: u1 = 0, + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + reserved2: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + reserved3: u1 = 0, + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + reserved1: u1 = 0, + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + reserved1: u1 = 0, + TG: u1, // bit offset: 6 desc: Trigger generation + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved3: u1 = 0, + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved4: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNTL: u16, // bit offset: 0 desc: Low counter value + CNTH: u15, // bit offset: 16 desc: High counter value + CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARRL: u16, // bit offset: 0 desc: Low Auto-reload value + ARRH: u16, // bit offset: 16 desc: High Auto-reload value + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value + CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value + CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM15 = extern struct { + pub const Address: u32 = 0x40014000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + reserved4: u1 = 0, + reserved3: u1 = 0, + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + reserved3: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + reserved2: u1 = 0, + reserved1: u1 = 0, + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved1: u1 = 0, + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + reserved2: u1 = 0, + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved1: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM16 = extern struct { + pub const Address: u32 = 0x40014400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + reserved4: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 option register + pub const OR = mmio(Address + 0x00000050, 32, packed struct { + raw: u32, // placeholder field + }); +}; +pub const TIM17 = extern struct { + pub const Address: u32 = 0x40014800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + reserved4: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART1 = extern struct { + pub const Address: u32 = 0x40013800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART2 = extern struct { + pub const Address: u32 = 0x40004400; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const USART3 = extern struct { + pub const Address: u32 = 0x40004800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART4 = extern struct { + pub const Address: u32 = 0x40004c00; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const UART5 = extern struct { + pub const Address: u32 = 0x40005000; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI1 = extern struct { + pub const Address: u32 = 0x40013000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI2 = extern struct { + pub const Address: u32 = 0x40003800; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const SPI3 = extern struct { + pub const Address: u32 = 0x40003c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2S2ext = extern struct { + pub const Address: u32 = 0x40003400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2S3ext = extern struct { + pub const Address: u32 = 0x40004000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + DFF: u1, // bit offset: 11 desc: Data frame format + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const EXTI = extern struct { + pub const Address: u32 = 0x40010400; + // byte offset: 0 Interrupt mask register + pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 + MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 + MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 + MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 + MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 + MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 + MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 + MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 + MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 + MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 + MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 + MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 + MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 + MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 + MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 + MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 + MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 + MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 + MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 + MR19: u1, // bit offset: 19 desc: Interrupt Mask on line 19 + MR20: u1, // bit offset: 20 desc: Interrupt Mask on line 20 + MR21: u1, // bit offset: 21 desc: Interrupt Mask on line 21 + MR22: u1, // bit offset: 22 desc: Interrupt Mask on line 22 + MR23: u1, // bit offset: 23 desc: Interrupt Mask on line 23 + MR24: u1, // bit offset: 24 desc: Interrupt Mask on line 24 + MR25: u1, // bit offset: 25 desc: Interrupt Mask on line 25 + MR26: u1, // bit offset: 26 desc: Interrupt Mask on line 26 + MR27: u1, // bit offset: 27 desc: Interrupt Mask on line 27 + MR28: u1, // bit offset: 28 desc: Interrupt Mask on line 28 + MR29: u1, // bit offset: 29 desc: Interrupt Mask on line 29 + MR30: u1, // bit offset: 30 desc: Interrupt Mask on line 30 + MR31: u1, // bit offset: 31 desc: Interrupt Mask on line 31 + }); + // byte offset: 4 Event mask register + pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Event Mask on line 0 + MR1: u1, // bit offset: 1 desc: Event Mask on line 1 + MR2: u1, // bit offset: 2 desc: Event Mask on line 2 + MR3: u1, // bit offset: 3 desc: Event Mask on line 3 + MR4: u1, // bit offset: 4 desc: Event Mask on line 4 + MR5: u1, // bit offset: 5 desc: Event Mask on line 5 + MR6: u1, // bit offset: 6 desc: Event Mask on line 6 + MR7: u1, // bit offset: 7 desc: Event Mask on line 7 + MR8: u1, // bit offset: 8 desc: Event Mask on line 8 + MR9: u1, // bit offset: 9 desc: Event Mask on line 9 + MR10: u1, // bit offset: 10 desc: Event Mask on line 10 + MR11: u1, // bit offset: 11 desc: Event Mask on line 11 + MR12: u1, // bit offset: 12 desc: Event Mask on line 12 + MR13: u1, // bit offset: 13 desc: Event Mask on line 13 + MR14: u1, // bit offset: 14 desc: Event Mask on line 14 + MR15: u1, // bit offset: 15 desc: Event Mask on line 15 + MR16: u1, // bit offset: 16 desc: Event Mask on line 16 + MR17: u1, // bit offset: 17 desc: Event Mask on line 17 + MR18: u1, // bit offset: 18 desc: Event Mask on line 18 + MR19: u1, // bit offset: 19 desc: Event Mask on line 19 + MR20: u1, // bit offset: 20 desc: Event Mask on line 20 + MR21: u1, // bit offset: 21 desc: Event Mask on line 21 + MR22: u1, // bit offset: 22 desc: Event Mask on line 22 + MR23: u1, // bit offset: 23 desc: Event Mask on line 23 + MR24: u1, // bit offset: 24 desc: Event Mask on line 24 + MR25: u1, // bit offset: 25 desc: Event Mask on line 25 + MR26: u1, // bit offset: 26 desc: Event Mask on line 26 + MR27: u1, // bit offset: 27 desc: Event Mask on line 27 + MR28: u1, // bit offset: 28 desc: Event Mask on line 28 + MR29: u1, // bit offset: 29 desc: Event Mask on line 29 + MR30: u1, // bit offset: 30 desc: Event Mask on line 30 + MR31: u1, // bit offset: 31 desc: Event Mask on line 31 + }); + // byte offset: 8 Rising Trigger selection register + pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 + TR19: u1, // bit offset: 19 desc: Rising trigger event configuration of line 19 + TR20: u1, // bit offset: 20 desc: Rising trigger event configuration of line 20 + TR21: u1, // bit offset: 21 desc: Rising trigger event configuration of line 21 + TR22: u1, // bit offset: 22 desc: Rising trigger event configuration of line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TR29: u1, // bit offset: 29 desc: Rising trigger event configuration of line 29 + TR30: u1, // bit offset: 30 desc: Rising trigger event configuration of line 30 + TR31: u1, // bit offset: 31 desc: Rising trigger event configuration of line 31 + }); + // byte offset: 12 Falling Trigger selection register + pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 + TR19: u1, // bit offset: 19 desc: Falling trigger event configuration of line 19 + TR20: u1, // bit offset: 20 desc: Falling trigger event configuration of line 20 + TR21: u1, // bit offset: 21 desc: Falling trigger event configuration of line 21 + TR22: u1, // bit offset: 22 desc: Falling trigger event configuration of line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TR29: u1, // bit offset: 29 desc: Falling trigger event configuration of line 29 + TR30: u1, // bit offset: 30 desc: Falling trigger event configuration of line 30. + TR31: u1, // bit offset: 31 desc: Falling trigger event configuration of line 31 + }); + // byte offset: 16 Software interrupt event register + pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { + SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 + SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 + SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 + SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 + SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 + SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 + SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 + SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 + SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 + SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 + SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 + SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 + SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 + SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 + SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 + SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 + SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 + SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 + SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 + SWIER19: u1, // bit offset: 19 desc: Software Interrupt on line 19 + SWIER20: u1, // bit offset: 20 desc: Software Interrupt on line 20 + SWIER21: u1, // bit offset: 21 desc: Software Interrupt on line 21 + SWIER22: u1, // bit offset: 22 desc: Software Interrupt on line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SWIER29: u1, // bit offset: 29 desc: Software Interrupt on line 29 + SWIER30: u1, // bit offset: 30 desc: Software Interrupt on line 309 + SWIER31: u1, // bit offset: 31 desc: Software Interrupt on line 319 + }); + // byte offset: 20 Pending register + pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { + PR0: u1, // bit offset: 0 desc: Pending bit 0 + PR1: u1, // bit offset: 1 desc: Pending bit 1 + PR2: u1, // bit offset: 2 desc: Pending bit 2 + PR3: u1, // bit offset: 3 desc: Pending bit 3 + PR4: u1, // bit offset: 4 desc: Pending bit 4 + PR5: u1, // bit offset: 5 desc: Pending bit 5 + PR6: u1, // bit offset: 6 desc: Pending bit 6 + PR7: u1, // bit offset: 7 desc: Pending bit 7 + PR8: u1, // bit offset: 8 desc: Pending bit 8 + PR9: u1, // bit offset: 9 desc: Pending bit 9 + PR10: u1, // bit offset: 10 desc: Pending bit 10 + PR11: u1, // bit offset: 11 desc: Pending bit 11 + PR12: u1, // bit offset: 12 desc: Pending bit 12 + PR13: u1, // bit offset: 13 desc: Pending bit 13 + PR14: u1, // bit offset: 14 desc: Pending bit 14 + PR15: u1, // bit offset: 15 desc: Pending bit 15 + PR16: u1, // bit offset: 16 desc: Pending bit 16 + PR17: u1, // bit offset: 17 desc: Pending bit 17 + PR18: u1, // bit offset: 18 desc: Pending bit 18 + PR19: u1, // bit offset: 19 desc: Pending bit 19 + PR20: u1, // bit offset: 20 desc: Pending bit 20 + PR21: u1, // bit offset: 21 desc: Pending bit 21 + PR22: u1, // bit offset: 22 desc: Pending bit 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PR29: u1, // bit offset: 29 desc: Pending bit 29 + PR30: u1, // bit offset: 30 desc: Pending bit 30 + PR31: u1, // bit offset: 31 desc: Pending bit 31 + }); + // byte offset: 24 Interrupt mask register + pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { + MR32: u1, // bit offset: 0 desc: Interrupt Mask on external/internal line 32 + MR33: u1, // bit offset: 1 desc: Interrupt Mask on external/internal line 33 + MR34: u1, // bit offset: 2 desc: Interrupt Mask on external/internal line 34 + MR35: u1, // bit offset: 3 desc: Interrupt Mask on external/internal line 35 + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Event mask register + pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { + MR32: u1, // bit offset: 0 desc: Event mask on external/internal line 32 + MR33: u1, // bit offset: 1 desc: Event mask on external/internal line 33 + MR34: u1, // bit offset: 2 desc: Event mask on external/internal line 34 + MR35: u1, // bit offset: 3 desc: Event mask on external/internal line 35 + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Rising Trigger selection register + pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { + TR32: u1, // bit offset: 0 desc: Rising trigger event configuration bit of line 32 + TR33: u1, // bit offset: 1 desc: Rising trigger event configuration bit of line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Falling Trigger selection register + pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { + TR32: u1, // bit offset: 0 desc: Falling trigger event configuration bit of line 32 + TR33: u1, // bit offset: 1 desc: Falling trigger event configuration bit of line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Software interrupt event register + pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { + SWIER32: u1, // bit offset: 0 desc: Software interrupt on line 32 + SWIER33: u1, // bit offset: 1 desc: Software interrupt on line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Pending register + pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { + PR32: u1, // bit offset: 0 desc: Pending bit on line 32 + PR33: u1, // bit offset: 1 desc: Pending bit on line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const COMP = extern struct { + pub const Address: u32 = 0x4001001c; + // byte offset: 0 control and status register + pub const COMP1_CSR = mmio(Address + 0x00000000, 32, packed struct { + COMP1EN: u1, // bit offset: 0 desc: Comparator 1 enable + COMP1_INP_DAC: u1, // bit offset: 1 desc: COMP1_INP_DAC + COMP1MODE: u2, // bit offset: 2 desc: Comparator 1 mode + COMP1INSEL: u3, // bit offset: 4 desc: Comparator 1 inverting input selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMP1_OUT_SEL: u4, // bit offset: 10 desc: Comparator 1 output selection + reserved4: u1 = 0, + COMP1POL: u1, // bit offset: 15 desc: Comparator 1 output polarity + COMP1HYST: u2, // bit offset: 16 desc: Comparator 1 hysteresis + COMP1_BLANKING: u3, // bit offset: 18 desc: Comparator 1 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP1OUT: u1, // bit offset: 30 desc: Comparator 1 output + COMP1LOCK: u1, // bit offset: 31 desc: Comparator 1 lock + }); + // byte offset: 4 control and status register + pub const COMP2_CSR = mmio(Address + 0x00000004, 32, packed struct { + COMP2EN: u1, // bit offset: 0 desc: Comparator 2 enable + reserved1: u1 = 0, + COMP2MODE: u2, // bit offset: 2 desc: Comparator 2 mode + COMP2INSEL: u3, // bit offset: 4 desc: Comparator 2 inverting input selection + COMP2INPSEL: u1, // bit offset: 7 desc: Comparator 2 non inverted input selection + reserved2: u1 = 0, + COMP2INMSEL: u1, // bit offset: 9 desc: Comparator 1inverting input selection + COMP2_OUT_SEL: u4, // bit offset: 10 desc: Comparator 2 output selection + reserved3: u1 = 0, + COMP2POL: u1, // bit offset: 15 desc: Comparator 2 output polarity + COMP2HYST: u2, // bit offset: 16 desc: Comparator 2 hysteresis + COMP2_BLANKING: u3, // bit offset: 18 desc: Comparator 2 blanking source + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMP2OUT: u1, // bit offset: 30 desc: Comparator 2 output + COMP2LOCK: u1, // bit offset: 31 desc: Comparator 2 lock + }); + // byte offset: 8 control and status register + pub const COMP3_CSR = mmio(Address + 0x00000008, 32, packed struct { + COMP3EN: u1, // bit offset: 0 desc: Comparator 3 enable + reserved1: u1 = 0, + COMP3MODE: u2, // bit offset: 2 desc: Comparator 3 mode + COMP3INSEL: u3, // bit offset: 4 desc: Comparator 3 inverting input selection + COMP3INPSEL: u1, // bit offset: 7 desc: Comparator 3 non inverted input selection + reserved3: u1 = 0, + reserved2: u1 = 0, + COMP3_OUT_SEL: u4, // bit offset: 10 desc: Comparator 3 output selection + reserved4: u1 = 0, + COMP3POL: u1, // bit offset: 15 desc: Comparator 3 output polarity + COMP3HYST: u2, // bit offset: 16 desc: Comparator 3 hysteresis + COMP3_BLANKING: u3, // bit offset: 18 desc: Comparator 3 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP3OUT: u1, // bit offset: 30 desc: Comparator 3 output + COMP3LOCK: u1, // bit offset: 31 desc: Comparator 3 lock + }); + // byte offset: 12 control and status register + pub const COMP4_CSR = mmio(Address + 0x0000000c, 32, packed struct { + COMP4EN: u1, // bit offset: 0 desc: Comparator 4 enable + reserved1: u1 = 0, + COMP4MODE: u2, // bit offset: 2 desc: Comparator 4 mode + COMP4INSEL: u3, // bit offset: 4 desc: Comparator 4 inverting input selection + COMP4INPSEL: u1, // bit offset: 7 desc: Comparator 4 non inverted input selection + reserved2: u1 = 0, + COM4WINMODE: u1, // bit offset: 9 desc: Comparator 4 window mode + COMP4_OUT_SEL: u4, // bit offset: 10 desc: Comparator 4 output selection + reserved3: u1 = 0, + COMP4POL: u1, // bit offset: 15 desc: Comparator 4 output polarity + COMP4HYST: u2, // bit offset: 16 desc: Comparator 4 hysteresis + COMP4_BLANKING: u3, // bit offset: 18 desc: Comparator 4 blanking source + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMP4OUT: u1, // bit offset: 30 desc: Comparator 4 output + COMP4LOCK: u1, // bit offset: 31 desc: Comparator 4 lock + }); + // byte offset: 16 control and status register + pub const COMP5_CSR = mmio(Address + 0x00000010, 32, packed struct { + COMP5EN: u1, // bit offset: 0 desc: Comparator 5 enable + reserved1: u1 = 0, + COMP5MODE: u2, // bit offset: 2 desc: Comparator 5 mode + COMP5INSEL: u3, // bit offset: 4 desc: Comparator 5 inverting input selection + COMP5INPSEL: u1, // bit offset: 7 desc: Comparator 5 non inverted input selection + reserved3: u1 = 0, + reserved2: u1 = 0, + COMP5_OUT_SEL: u4, // bit offset: 10 desc: Comparator 5 output selection + reserved4: u1 = 0, + COMP5POL: u1, // bit offset: 15 desc: Comparator 5 output polarity + COMP5HYST: u2, // bit offset: 16 desc: Comparator 5 hysteresis + COMP5_BLANKING: u3, // bit offset: 18 desc: Comparator 5 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP5OUT: u1, // bit offset: 30 desc: Comparator51 output + COMP5LOCK: u1, // bit offset: 31 desc: Comparator 5 lock + }); + // byte offset: 20 control and status register + pub const COMP6_CSR = mmio(Address + 0x00000014, 32, packed struct { + COMP6EN: u1, // bit offset: 0 desc: Comparator 6 enable + reserved1: u1 = 0, + COMP6MODE: u2, // bit offset: 2 desc: Comparator 6 mode + COMP6INSEL: u3, // bit offset: 4 desc: Comparator 6 inverting input selection + COMP6INPSEL: u1, // bit offset: 7 desc: Comparator 6 non inverted input selection + reserved2: u1 = 0, + COM6WINMODE: u1, // bit offset: 9 desc: Comparator 6 window mode + COMP6_OUT_SEL: u4, // bit offset: 10 desc: Comparator 6 output selection + reserved3: u1 = 0, + COMP6POL: u1, // bit offset: 15 desc: Comparator 6 output polarity + COMP6HYST: u2, // bit offset: 16 desc: Comparator 6 hysteresis + COMP6_BLANKING: u3, // bit offset: 18 desc: Comparator 6 blanking source + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMP6OUT: u1, // bit offset: 30 desc: Comparator 6 output + COMP6LOCK: u1, // bit offset: 31 desc: Comparator 6 lock + }); + // byte offset: 24 control and status register + pub const COMP7_CSR = mmio(Address + 0x00000018, 32, packed struct { + COMP7EN: u1, // bit offset: 0 desc: Comparator 7 enable + reserved1: u1 = 0, + COMP7MODE: u2, // bit offset: 2 desc: Comparator 7 mode + COMP7INSEL: u3, // bit offset: 4 desc: Comparator 7 inverting input selection + COMP7INPSEL: u1, // bit offset: 7 desc: Comparator 7 non inverted input selection + reserved3: u1 = 0, + reserved2: u1 = 0, + COMP7_OUT_SEL: u4, // bit offset: 10 desc: Comparator 7 output selection + reserved4: u1 = 0, + COMP7POL: u1, // bit offset: 15 desc: Comparator 7 output polarity + COMP7HYST: u2, // bit offset: 16 desc: Comparator 7 hysteresis + COMP7_BLANKING: u3, // bit offset: 18 desc: Comparator 7 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP7OUT: u1, // bit offset: 30 desc: Comparator 7 output + COMP7LOCK: u1, // bit offset: 31 desc: Comparator 7 lock + }); +}; +pub const PWR = extern struct { + pub const Address: u32 = 0x40007000; + // byte offset: 0 power control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + LPDS: u1, // bit offset: 0 desc: Low-power deep sleep + PDDS: u1, // bit offset: 1 desc: Power down deepsleep + CWUF: u1, // bit offset: 2 desc: Clear wakeup flag + CSBF: u1, // bit offset: 3 desc: Clear standby flag + PVDE: u1, // bit offset: 4 desc: Power voltage detector enable + PLS: u3, // bit offset: 5 desc: PVD level selection + DBP: u1, // bit offset: 8 desc: Disable backup domain write protection + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 power control/status register + pub const CSR = mmio(Address + 0x00000004, 32, packed struct { + WUF: u1, // bit offset: 0 desc: Wakeup flag + SBF: u1, // bit offset: 1 desc: Standby flag + PVDO: u1, // bit offset: 2 desc: PVD output + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + EWUP1: u1, // bit offset: 8 desc: Enable WKUP1 pin + EWUP2: u1, // bit offset: 9 desc: Enable WKUP2 pin + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CAN = extern struct { + pub const Address: u32 = 0x40006400; + // byte offset: 0 master control register + pub const MCR = mmio(Address + 0x00000000, 32, packed struct { + INRQ: u1, // bit offset: 0 desc: INRQ + SLEEP: u1, // bit offset: 1 desc: SLEEP + TXFP: u1, // bit offset: 2 desc: TXFP + RFLM: u1, // bit offset: 3 desc: RFLM + NART: u1, // bit offset: 4 desc: NART + AWUM: u1, // bit offset: 5 desc: AWUM + ABOM: u1, // bit offset: 6 desc: ABOM + TTCM: u1, // bit offset: 7 desc: TTCM + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESET: u1, // bit offset: 15 desc: RESET + DBF: u1, // bit offset: 16 desc: DBF + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 master status register + pub const MSR = mmio(Address + 0x00000004, 32, packed struct { + INAK: u1, // bit offset: 0 desc: INAK + SLAK: u1, // bit offset: 1 desc: SLAK + ERRI: u1, // bit offset: 2 desc: ERRI + WKUI: u1, // bit offset: 3 desc: WKUI + SLAKI: u1, // bit offset: 4 desc: SLAKI + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXM: u1, // bit offset: 8 desc: TXM + RXM: u1, // bit offset: 9 desc: RXM + SAMP: u1, // bit offset: 10 desc: SAMP + RX: u1, // bit offset: 11 desc: RX + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 transmit status register + pub const TSR = mmio(Address + 0x00000008, 32, packed struct { + RQCP0: u1, // bit offset: 0 desc: RQCP0 + TXOK0: u1, // bit offset: 1 desc: TXOK0 + ALST0: u1, // bit offset: 2 desc: ALST0 + TERR0: u1, // bit offset: 3 desc: TERR0 + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABRQ0: u1, // bit offset: 7 desc: ABRQ0 + RQCP1: u1, // bit offset: 8 desc: RQCP1 + TXOK1: u1, // bit offset: 9 desc: TXOK1 + ALST1: u1, // bit offset: 10 desc: ALST1 + TERR1: u1, // bit offset: 11 desc: TERR1 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + ABRQ1: u1, // bit offset: 15 desc: ABRQ1 + RQCP2: u1, // bit offset: 16 desc: RQCP2 + TXOK2: u1, // bit offset: 17 desc: TXOK2 + ALST2: u1, // bit offset: 18 desc: ALST2 + TERR2: u1, // bit offset: 19 desc: TERR2 + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + ABRQ2: u1, // bit offset: 23 desc: ABRQ2 + CODE: u2, // bit offset: 24 desc: CODE + TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 + TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 + TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 + LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 + LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 + LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 + }); + // byte offset: 12 receive FIFO 0 register + pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { + FMP0: u2, // bit offset: 0 desc: FMP0 + reserved1: u1 = 0, + FULL0: u1, // bit offset: 3 desc: FULL0 + FOVR0: u1, // bit offset: 4 desc: FOVR0 + RFOM0: u1, // bit offset: 5 desc: RFOM0 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 receive FIFO 1 register + pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { + FMP1: u2, // bit offset: 0 desc: FMP1 + reserved1: u1 = 0, + FULL1: u1, // bit offset: 3 desc: FULL1 + FOVR1: u1, // bit offset: 4 desc: FOVR1 + RFOM1: u1, // bit offset: 5 desc: RFOM1 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 interrupt enable register + pub const IER = mmio(Address + 0x00000014, 32, packed struct { + TMEIE: u1, // bit offset: 0 desc: TMEIE + FMPIE0: u1, // bit offset: 1 desc: FMPIE0 + FFIE0: u1, // bit offset: 2 desc: FFIE0 + FOVIE0: u1, // bit offset: 3 desc: FOVIE0 + FMPIE1: u1, // bit offset: 4 desc: FMPIE1 + FFIE1: u1, // bit offset: 5 desc: FFIE1 + FOVIE1: u1, // bit offset: 6 desc: FOVIE1 + reserved1: u1 = 0, + EWGIE: u1, // bit offset: 8 desc: EWGIE + EPVIE: u1, // bit offset: 9 desc: EPVIE + BOFIE: u1, // bit offset: 10 desc: BOFIE + LECIE: u1, // bit offset: 11 desc: LECIE + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + ERRIE: u1, // bit offset: 15 desc: ERRIE + WKUIE: u1, // bit offset: 16 desc: WKUIE + SLKIE: u1, // bit offset: 17 desc: SLKIE + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 error status register + pub const ESR = mmio(Address + 0x00000018, 32, packed struct { + EWGF: u1, // bit offset: 0 desc: EWGF + EPVF: u1, // bit offset: 1 desc: EPVF + BOFF: u1, // bit offset: 2 desc: BOFF + reserved1: u1 = 0, + LEC: u3, // bit offset: 4 desc: LEC + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TEC: u8, // bit offset: 16 desc: TEC + REC: u8, // bit offset: 24 desc: REC + }); + // byte offset: 28 bit timing register + pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { + BRP: u10, // bit offset: 0 desc: BRP + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TS1: u4, // bit offset: 16 desc: TS1 + TS2: u3, // bit offset: 20 desc: TS2 + reserved7: u1 = 0, + SJW: u2, // bit offset: 24 desc: SJW + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + LBKM: u1, // bit offset: 30 desc: LBKM + SILM: u1, // bit offset: 31 desc: SILM + }); + // byte offset: 384 TX mailbox identifier register + pub const TI0R = mmio(Address + 0x00000180, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 388 mailbox data length control and time stamp register + pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 392 mailbox data low register + pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 396 mailbox data high register + pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 400 TX mailbox identifier register + pub const TI1R = mmio(Address + 0x00000190, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 404 mailbox data length control and time stamp register + pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 408 mailbox data low register + pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 412 mailbox data high register + pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 416 TX mailbox identifier register + pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 420 mailbox data length control and time stamp register + pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 424 mailbox data low register + pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 428 mailbox data high register + pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 432 receive FIFO mailbox identifier register + pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 436 receive FIFO mailbox data length control and time stamp register + pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 440 receive FIFO mailbox data low register + pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 444 receive FIFO mailbox data high register + pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 448 receive FIFO mailbox identifier register + pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 452 receive FIFO mailbox data length control and time stamp register + pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 456 receive FIFO mailbox data low register + pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 460 receive FIFO mailbox data high register + pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 512 filter master register + pub const FMR = mmio(Address + 0x00000200, 32, packed struct { + FINIT: u1, // bit offset: 0 desc: Filter init mode + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CAN2SB: u6, // bit offset: 8 desc: CAN2 start bank + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 516 filter mode register + pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { + FBM0: u1, // bit offset: 0 desc: Filter mode + FBM1: u1, // bit offset: 1 desc: Filter mode + FBM2: u1, // bit offset: 2 desc: Filter mode + FBM3: u1, // bit offset: 3 desc: Filter mode + FBM4: u1, // bit offset: 4 desc: Filter mode + FBM5: u1, // bit offset: 5 desc: Filter mode + FBM6: u1, // bit offset: 6 desc: Filter mode + FBM7: u1, // bit offset: 7 desc: Filter mode + FBM8: u1, // bit offset: 8 desc: Filter mode + FBM9: u1, // bit offset: 9 desc: Filter mode + FBM10: u1, // bit offset: 10 desc: Filter mode + FBM11: u1, // bit offset: 11 desc: Filter mode + FBM12: u1, // bit offset: 12 desc: Filter mode + FBM13: u1, // bit offset: 13 desc: Filter mode + FBM14: u1, // bit offset: 14 desc: Filter mode + FBM15: u1, // bit offset: 15 desc: Filter mode + FBM16: u1, // bit offset: 16 desc: Filter mode + FBM17: u1, // bit offset: 17 desc: Filter mode + FBM18: u1, // bit offset: 18 desc: Filter mode + FBM19: u1, // bit offset: 19 desc: Filter mode + FBM20: u1, // bit offset: 20 desc: Filter mode + FBM21: u1, // bit offset: 21 desc: Filter mode + FBM22: u1, // bit offset: 22 desc: Filter mode + FBM23: u1, // bit offset: 23 desc: Filter mode + FBM24: u1, // bit offset: 24 desc: Filter mode + FBM25: u1, // bit offset: 25 desc: Filter mode + FBM26: u1, // bit offset: 26 desc: Filter mode + FBM27: u1, // bit offset: 27 desc: Filter mode + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 524 filter scale register + pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { + FSC0: u1, // bit offset: 0 desc: Filter scale configuration + FSC1: u1, // bit offset: 1 desc: Filter scale configuration + FSC2: u1, // bit offset: 2 desc: Filter scale configuration + FSC3: u1, // bit offset: 3 desc: Filter scale configuration + FSC4: u1, // bit offset: 4 desc: Filter scale configuration + FSC5: u1, // bit offset: 5 desc: Filter scale configuration + FSC6: u1, // bit offset: 6 desc: Filter scale configuration + FSC7: u1, // bit offset: 7 desc: Filter scale configuration + FSC8: u1, // bit offset: 8 desc: Filter scale configuration + FSC9: u1, // bit offset: 9 desc: Filter scale configuration + FSC10: u1, // bit offset: 10 desc: Filter scale configuration + FSC11: u1, // bit offset: 11 desc: Filter scale configuration + FSC12: u1, // bit offset: 12 desc: Filter scale configuration + FSC13: u1, // bit offset: 13 desc: Filter scale configuration + FSC14: u1, // bit offset: 14 desc: Filter scale configuration + FSC15: u1, // bit offset: 15 desc: Filter scale configuration + FSC16: u1, // bit offset: 16 desc: Filter scale configuration + FSC17: u1, // bit offset: 17 desc: Filter scale configuration + FSC18: u1, // bit offset: 18 desc: Filter scale configuration + FSC19: u1, // bit offset: 19 desc: Filter scale configuration + FSC20: u1, // bit offset: 20 desc: Filter scale configuration + FSC21: u1, // bit offset: 21 desc: Filter scale configuration + FSC22: u1, // bit offset: 22 desc: Filter scale configuration + FSC23: u1, // bit offset: 23 desc: Filter scale configuration + FSC24: u1, // bit offset: 24 desc: Filter scale configuration + FSC25: u1, // bit offset: 25 desc: Filter scale configuration + FSC26: u1, // bit offset: 26 desc: Filter scale configuration + FSC27: u1, // bit offset: 27 desc: Filter scale configuration + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 532 filter FIFO assignment register + pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { + FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 + FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 + FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 + FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 + FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 + FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 + FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 + FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 + FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 + FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 + FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 + FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 + FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 + FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 + FFA14: u1, // bit offset: 14 desc: Filter FIFO assignment for filter 14 + FFA15: u1, // bit offset: 15 desc: Filter FIFO assignment for filter 15 + FFA16: u1, // bit offset: 16 desc: Filter FIFO assignment for filter 16 + FFA17: u1, // bit offset: 17 desc: Filter FIFO assignment for filter 17 + FFA18: u1, // bit offset: 18 desc: Filter FIFO assignment for filter 18 + FFA19: u1, // bit offset: 19 desc: Filter FIFO assignment for filter 19 + FFA20: u1, // bit offset: 20 desc: Filter FIFO assignment for filter 20 + FFA21: u1, // bit offset: 21 desc: Filter FIFO assignment for filter 21 + FFA22: u1, // bit offset: 22 desc: Filter FIFO assignment for filter 22 + FFA23: u1, // bit offset: 23 desc: Filter FIFO assignment for filter 23 + FFA24: u1, // bit offset: 24 desc: Filter FIFO assignment for filter 24 + FFA25: u1, // bit offset: 25 desc: Filter FIFO assignment for filter 25 + FFA26: u1, // bit offset: 26 desc: Filter FIFO assignment for filter 26 + FFA27: u1, // bit offset: 27 desc: Filter FIFO assignment for filter 27 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 540 CAN filter activation register + pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { + FACT0: u1, // bit offset: 0 desc: Filter active + FACT1: u1, // bit offset: 1 desc: Filter active + FACT2: u1, // bit offset: 2 desc: Filter active + FACT3: u1, // bit offset: 3 desc: Filter active + FACT4: u1, // bit offset: 4 desc: Filter active + FACT5: u1, // bit offset: 5 desc: Filter active + FACT6: u1, // bit offset: 6 desc: Filter active + FACT7: u1, // bit offset: 7 desc: Filter active + FACT8: u1, // bit offset: 8 desc: Filter active + FACT9: u1, // bit offset: 9 desc: Filter active + FACT10: u1, // bit offset: 10 desc: Filter active + FACT11: u1, // bit offset: 11 desc: Filter active + FACT12: u1, // bit offset: 12 desc: Filter active + FACT13: u1, // bit offset: 13 desc: Filter active + FACT14: u1, // bit offset: 14 desc: Filter active + FACT15: u1, // bit offset: 15 desc: Filter active + FACT16: u1, // bit offset: 16 desc: Filter active + FACT17: u1, // bit offset: 17 desc: Filter active + FACT18: u1, // bit offset: 18 desc: Filter active + FACT19: u1, // bit offset: 19 desc: Filter active + FACT20: u1, // bit offset: 20 desc: Filter active + FACT21: u1, // bit offset: 21 desc: Filter active + FACT22: u1, // bit offset: 22 desc: Filter active + FACT23: u1, // bit offset: 23 desc: Filter active + FACT24: u1, // bit offset: 24 desc: Filter active + FACT25: u1, // bit offset: 25 desc: Filter active + FACT26: u1, // bit offset: 26 desc: Filter active + FACT27: u1, // bit offset: 27 desc: Filter active + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 576 Filter bank 0 register 1 + pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 580 Filter bank 0 register 2 + pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 584 Filter bank 1 register 1 + pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 588 Filter bank 1 register 2 + pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 592 Filter bank 2 register 1 + pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 596 Filter bank 2 register 2 + pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 600 Filter bank 3 register 1 + pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 604 Filter bank 3 register 2 + pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 608 Filter bank 4 register 1 + pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 612 Filter bank 4 register 2 + pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 616 Filter bank 5 register 1 + pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 620 Filter bank 5 register 2 + pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 624 Filter bank 6 register 1 + pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 628 Filter bank 6 register 2 + pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 632 Filter bank 7 register 1 + pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 636 Filter bank 7 register 2 + pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 640 Filter bank 8 register 1 + pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 644 Filter bank 8 register 2 + pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 648 Filter bank 9 register 1 + pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 652 Filter bank 9 register 2 + pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 656 Filter bank 10 register 1 + pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 660 Filter bank 10 register 2 + pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 664 Filter bank 11 register 1 + pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 668 Filter bank 11 register 2 + pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 672 Filter bank 4 register 1 + pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 676 Filter bank 12 register 2 + pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 680 Filter bank 13 register 1 + pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 684 Filter bank 13 register 2 + pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 688 Filter bank 14 register 1 + pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 692 Filter bank 14 register 2 + pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 696 Filter bank 15 register 1 + pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 700 Filter bank 15 register 2 + pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 704 Filter bank 16 register 1 + pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 708 Filter bank 16 register 2 + pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 712 Filter bank 17 register 1 + pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 716 Filter bank 17 register 2 + pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 720 Filter bank 18 register 1 + pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 724 Filter bank 18 register 2 + pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 728 Filter bank 19 register 1 + pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 732 Filter bank 19 register 2 + pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 736 Filter bank 20 register 1 + pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 740 Filter bank 20 register 2 + pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 744 Filter bank 21 register 1 + pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 748 Filter bank 21 register 2 + pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 752 Filter bank 22 register 1 + pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 756 Filter bank 22 register 2 + pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 760 Filter bank 23 register 1 + pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 764 Filter bank 23 register 2 + pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 768 Filter bank 24 register 1 + pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 772 Filter bank 24 register 2 + pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 776 Filter bank 25 register 1 + pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 780 Filter bank 25 register 2 + pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 784 Filter bank 26 register 1 + pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 788 Filter bank 26 register 2 + pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 792 Filter bank 27 register 1 + pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 796 Filter bank 27 register 2 + pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); +}; +pub const USB_FS = extern struct { + pub const Address: u32 = 0x40005c00; + // byte offset: 0 endpoint 0 register + pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 endpoint 1 register + pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 endpoint 2 register + pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 endpoint 3 register + pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 endpoint 4 register + pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 endpoint 5 register + pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 endpoint 6 register + pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 endpoint 7 register + pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 control register + pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { + FRES: u1, // bit offset: 0 desc: Force USB Reset + PDWN: u1, // bit offset: 1 desc: Power down + LPMODE: u1, // bit offset: 2 desc: Low-power mode + FSUSP: u1, // bit offset: 3 desc: Force suspend + RESUME: u1, // bit offset: 4 desc: Resume request + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask + SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask + RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask + SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask + WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask + ERRM: u1, // bit offset: 13 desc: Error interrupt mask + PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask + CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 interrupt status register + pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { + EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier + DIR: u1, // bit offset: 4 desc: Direction of transaction + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOF: u1, // bit offset: 8 desc: Expected start frame + SOF: u1, // bit offset: 9 desc: start of frame + RESET: u1, // bit offset: 10 desc: reset request + SUSP: u1, // bit offset: 11 desc: Suspend mode request + WKUP: u1, // bit offset: 12 desc: Wakeup + ERR: u1, // bit offset: 13 desc: Error + PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun + CTR: u1, // bit offset: 15 desc: Correct transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 frame number register + pub const FNR = mmio(Address + 0x00000048, 32, packed struct { + FN: u11, // bit offset: 0 desc: Frame number + LSOF: u2, // bit offset: 11 desc: Lost SOF + LCK: u1, // bit offset: 13 desc: Locked + RXDM: u1, // bit offset: 14 desc: Receive data - line status + RXDP: u1, // bit offset: 15 desc: Receive data + line status + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 device address + pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { + ADD: u1, // bit offset: 0 desc: Device address + ADD1: u1, // bit offset: 1 desc: Device address + ADD2: u1, // bit offset: 2 desc: Device address + ADD3: u1, // bit offset: 3 desc: Device address + ADD4: u1, // bit offset: 4 desc: Device address + ADD5: u1, // bit offset: 5 desc: Device address + ADD6: u1, // bit offset: 6 desc: Device address + EF: u1, // bit offset: 7 desc: Enable function + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 Buffer table address + pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + BTABLE: u13, // bit offset: 3 desc: Buffer table + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C1 = extern struct { + pub const Address: u32 = 0x40005400; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + TXIE: u1, // bit offset: 1 desc: TX Interrupt enable + RXIE: u1, // bit offset: 2 desc: RX Interrupt enable + ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) + NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable + STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable + TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable + ERRIE: u1, // bit offset: 7 desc: Error interrupts enable + DNF: u4, // bit offset: 8 desc: Digital noise filter + ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF + SWRST: u1, // bit offset: 13 desc: Software reset + TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable + RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable + SBC: u1, // bit offset: 16 desc: Slave byte control + NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable + WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable + GCEN: u1, // bit offset: 19 desc: General call enable + SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable + SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable + ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable + PECEN: u1, // bit offset: 23 desc: PEC enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) + SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) + SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) + RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) + ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) + HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) + START: u1, // bit offset: 13 desc: Start generation + STOP: u1, // bit offset: 14 desc: Stop generation (master mode) + NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) + NBYTES: u8, // bit offset: 16 desc: Number of bytes + RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode + AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) + PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + OA1_0: u1, // bit offset: 0 desc: Interface address + OA1_1: u7, // bit offset: 1 desc: Interface address + OA1_8: u2, // bit offset: 8 desc: Interface address + OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + reserved1: u1 = 0, + OA2: u7, // bit offset: 1 desc: Interface address + OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Timing register + pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { + SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) + SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) + SDADEL: u4, // bit offset: 16 desc: Data hold time + SCLDEL: u4, // bit offset: 20 desc: Data setup time + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRESC: u4, // bit offset: 28 desc: Timing prescaler + }); + // byte offset: 20 Status register 1 + pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { + TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A + TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + reserved2: u1 = 0, + reserved1: u1 = 0, + TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable + TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + }); + // byte offset: 24 Interrupt and Status register + pub const ISR = mmio(Address + 0x00000018, 32, packed struct { + TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) + TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) + RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) + ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) + NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag + STOPF: u1, // bit offset: 5 desc: Stop detection flag + TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) + TCR: u1, // bit offset: 7 desc: Transfer Complete Reload + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost + OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) + PECERR: u1, // bit offset: 11 desc: PEC Error in reception + TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved1: u1 = 0, + BUSY: u1, // bit offset: 15 desc: Bus busy + DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) + ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt clear register + pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear + NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear + STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + reserved5: u1 = 0, + reserved4: u1 = 0, + BERRCF: u1, // bit offset: 8 desc: Bus error flag clear + ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear + OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear + PECCF: u1, // bit offset: 11 desc: PEC Error flag clear + TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear + ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 PEC register + pub const PECR = mmio(Address + 0x00000020, 32, packed struct { + PEC: u8, // bit offset: 0 desc: Packet error checking register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const I2C2 = extern struct { + pub const Address: u32 = 0x40005800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + TXIE: u1, // bit offset: 1 desc: TX Interrupt enable + RXIE: u1, // bit offset: 2 desc: RX Interrupt enable + ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) + NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable + STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable + TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable + ERRIE: u1, // bit offset: 7 desc: Error interrupts enable + DNF: u4, // bit offset: 8 desc: Digital noise filter + ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF + SWRST: u1, // bit offset: 13 desc: Software reset + TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable + RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable + SBC: u1, // bit offset: 16 desc: Slave byte control + NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable + WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable + GCEN: u1, // bit offset: 19 desc: General call enable + SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable + SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable + ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable + PECEN: u1, // bit offset: 23 desc: PEC enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) + SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) + SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) + RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) + ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) + HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) + START: u1, // bit offset: 13 desc: Start generation + STOP: u1, // bit offset: 14 desc: Stop generation (master mode) + NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) + NBYTES: u8, // bit offset: 16 desc: Number of bytes + RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode + AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) + PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + OA1_0: u1, // bit offset: 0 desc: Interface address + OA1_1: u7, // bit offset: 1 desc: Interface address + OA1_8: u2, // bit offset: 8 desc: Interface address + OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + reserved1: u1 = 0, + OA2: u7, // bit offset: 1 desc: Interface address + OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Timing register + pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { + SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) + SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) + SDADEL: u4, // bit offset: 16 desc: Data hold time + SCLDEL: u4, // bit offset: 20 desc: Data setup time + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRESC: u4, // bit offset: 28 desc: Timing prescaler + }); + // byte offset: 20 Status register 1 + pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { + TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A + TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + reserved2: u1 = 0, + reserved1: u1 = 0, + TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable + TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + }); + // byte offset: 24 Interrupt and Status register + pub const ISR = mmio(Address + 0x00000018, 32, packed struct { + TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) + TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) + RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) + ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) + NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag + STOPF: u1, // bit offset: 5 desc: Stop detection flag + TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) + TCR: u1, // bit offset: 7 desc: Transfer Complete Reload + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost + OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) + PECERR: u1, // bit offset: 11 desc: PEC Error in reception + TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved1: u1 = 0, + BUSY: u1, // bit offset: 15 desc: Bus busy + DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) + ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Interrupt clear register + pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear + NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear + STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + reserved5: u1 = 0, + reserved4: u1 = 0, + BERRCF: u1, // bit offset: 8 desc: Bus error flag clear + ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear + OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear + PECCF: u1, // bit offset: 11 desc: PEC Error flag clear + TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear + ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 PEC register + pub const PECR = mmio(Address + 0x00000020, 32, packed struct { + PEC: u8, // bit offset: 0 desc: Packet error checking register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Receive data register + pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Transmit data register + pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const IWDG = extern struct { + pub const Address: u32 = 0x40003000; + // byte offset: 0 Key register + pub const KR = mmio(Address + 0x00000000, 32, packed struct { + KEY: u16, // bit offset: 0 desc: Key value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Prescaler register + pub const PR = mmio(Address + 0x00000004, 32, packed struct { + PR: u3, // bit offset: 0 desc: Prescaler divider + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Reload register + pub const RLR = mmio(Address + 0x00000008, 32, packed struct { + RL: u12, // bit offset: 0 desc: Watchdog counter reload value + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Status register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update + RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update + WVU: u1, // bit offset: 2 desc: Watchdog counter window value update + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 Window register + pub const WINR = mmio(Address + 0x00000010, 32, packed struct { + WIN: u12, // bit offset: 0 desc: Watchdog counter window value + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const WWDG = extern struct { + pub const Address: u32 = 0x40002c00; + // byte offset: 0 Control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + T: u7, // bit offset: 0 desc: 7-bit counter + WDGA: u1, // bit offset: 7 desc: Activation bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Configuration register + pub const CFR = mmio(Address + 0x00000004, 32, packed struct { + W: u7, // bit offset: 0 desc: 7-bit window value + WDGTB: u2, // bit offset: 7 desc: Timer base + EWI: u1, // bit offset: 9 desc: Early wakeup interrupt + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + EWIF: u1, // bit offset: 0 desc: Early wakeup interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const RTC = extern struct { + pub const Address: u32 = 0x40002800; + // byte offset: 0 time register + pub const TR = mmio(Address + 0x00000000, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + reserved1: u1 = 0, + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + reserved2: u1 = 0, + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 date register + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DU: u4, // bit offset: 0 desc: Date units in BCD format + DT: u2, // bit offset: 4 desc: Date tens in BCD format + reserved2: u1 = 0, + reserved1: u1 = 0, + MU: u4, // bit offset: 8 desc: Month units in BCD format + MT: u1, // bit offset: 12 desc: Month tens in BCD format + WDU: u3, // bit offset: 13 desc: Week day units + YU: u4, // bit offset: 16 desc: Year units in BCD format + YT: u4, // bit offset: 20 desc: Year tens in BCD format + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + WCKSEL: u3, // bit offset: 0 desc: Wakeup clock selection + TSEDGE: u1, // bit offset: 3 desc: Time-stamp event active edge + REFCKON: u1, // bit offset: 4 desc: Reference clock detection enable (50 or 60 Hz) + BYPSHAD: u1, // bit offset: 5 desc: Bypass the shadow registers + FMT: u1, // bit offset: 6 desc: Hour format + reserved1: u1 = 0, + ALRAE: u1, // bit offset: 8 desc: Alarm A enable + ALRBE: u1, // bit offset: 9 desc: Alarm B enable + WUTE: u1, // bit offset: 10 desc: Wakeup timer enable + TSE: u1, // bit offset: 11 desc: Time stamp enable + ALRAIE: u1, // bit offset: 12 desc: Alarm A interrupt enable + ALRBIE: u1, // bit offset: 13 desc: Alarm B interrupt enable + WUTIE: u1, // bit offset: 14 desc: Wakeup timer interrupt enable + TSIE: u1, // bit offset: 15 desc: Time-stamp interrupt enable + ADD1H: u1, // bit offset: 16 desc: Add 1 hour (summer time change) + SUB1H: u1, // bit offset: 17 desc: Subtract 1 hour (winter time change) + BKP: u1, // bit offset: 18 desc: Backup + COSEL: u1, // bit offset: 19 desc: Calibration output selection + POL: u1, // bit offset: 20 desc: Output polarity + OSEL: u2, // bit offset: 21 desc: Output selection + COE: u1, // bit offset: 23 desc: Calibration output enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 initialization and status register + pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { + ALRAWF: u1, // bit offset: 0 desc: Alarm A write flag + ALRBWF: u1, // bit offset: 1 desc: Alarm B write flag + WUTWF: u1, // bit offset: 2 desc: Wakeup timer write flag + SHPF: u1, // bit offset: 3 desc: Shift operation pending + INITS: u1, // bit offset: 4 desc: Initialization status flag + RSF: u1, // bit offset: 5 desc: Registers synchronization flag + INITF: u1, // bit offset: 6 desc: Initialization flag + INIT: u1, // bit offset: 7 desc: Initialization mode + ALRAF: u1, // bit offset: 8 desc: Alarm A flag + ALRBF: u1, // bit offset: 9 desc: Alarm B flag + WUTF: u1, // bit offset: 10 desc: Wakeup timer flag + TSF: u1, // bit offset: 11 desc: Time-stamp flag + TSOVF: u1, // bit offset: 12 desc: Time-stamp overflow flag + TAMP1F: u1, // bit offset: 13 desc: Tamper detection flag + TAMP2F: u1, // bit offset: 14 desc: RTC_TAMP2 detection flag + TAMP3F: u1, // bit offset: 15 desc: RTC_TAMP3 detection flag + RECALPF: u1, // bit offset: 16 desc: Recalibration pending Flag + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 prescaler register + pub const PRER = mmio(Address + 0x00000010, 32, packed struct { + PREDIV_S: u15, // bit offset: 0 desc: Synchronous prescaler factor + reserved1: u1 = 0, + PREDIV_A: u7, // bit offset: 16 desc: Asynchronous prescaler factor + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 wakeup timer register + pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { + WUT: u16, // bit offset: 0 desc: Wakeup auto-reload value bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 alarm A register + pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + MSK1: u1, // bit offset: 7 desc: Alarm A seconds mask + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + MSK2: u1, // bit offset: 15 desc: Alarm A minutes mask + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + MSK3: u1, // bit offset: 23 desc: Alarm A hours mask + DU: u4, // bit offset: 24 desc: Date units or day in BCD format + DT: u2, // bit offset: 28 desc: Date tens in BCD format + WDSEL: u1, // bit offset: 30 desc: Week day selection + MSK4: u1, // bit offset: 31 desc: Alarm A date mask + }); + // byte offset: 32 alarm B register + pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + MSK1: u1, // bit offset: 7 desc: Alarm B seconds mask + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + MSK2: u1, // bit offset: 15 desc: Alarm B minutes mask + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + MSK3: u1, // bit offset: 23 desc: Alarm B hours mask + DU: u4, // bit offset: 24 desc: Date units or day in BCD format + DT: u2, // bit offset: 28 desc: Date tens in BCD format + WDSEL: u1, // bit offset: 30 desc: Week day selection + MSK4: u1, // bit offset: 31 desc: Alarm B date mask + }); + // byte offset: 36 write protection register + pub const WPR = mmio(Address + 0x00000024, 32, packed struct { + KEY: u8, // bit offset: 0 desc: Write protection key + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 sub second register + pub const SSR = mmio(Address + 0x00000028, 32, packed struct { + SS: u16, // bit offset: 0 desc: Sub second value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 shift control register + pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { + SUBFS: u15, // bit offset: 0 desc: Subtract a fraction of a second + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADD1S: u1, // bit offset: 31 desc: Add one second + }); + // byte offset: 48 time stamp time register + pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + reserved1: u1 = 0, + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + reserved2: u1 = 0, + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 time stamp date register + pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { + DU: u4, // bit offset: 0 desc: Date units in BCD format + DT: u2, // bit offset: 4 desc: Date tens in BCD format + reserved2: u1 = 0, + reserved1: u1 = 0, + MU: u4, // bit offset: 8 desc: Month units in BCD format + MT: u1, // bit offset: 12 desc: Month tens in BCD format + WDU: u3, // bit offset: 13 desc: Week day units + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 timestamp sub second register + pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { + SS: u16, // bit offset: 0 desc: Sub second value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 calibration register + pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { + CALM: u9, // bit offset: 0 desc: Calibration minus + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALW16: u1, // bit offset: 13 desc: Use a 16-second calibration cycle period + CALW8: u1, // bit offset: 14 desc: Use an 8-second calibration cycle period + CALP: u1, // bit offset: 15 desc: Increase frequency of RTC by 488.5 ppm + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 tamper and alternate function configuration register + pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { + TAMP1E: u1, // bit offset: 0 desc: Tamper 1 detection enable + TAMP1TRG: u1, // bit offset: 1 desc: Active level for tamper 1 + TAMPIE: u1, // bit offset: 2 desc: Tamper interrupt enable + TAMP2E: u1, // bit offset: 3 desc: Tamper 2 detection enable + TAMP2TRG: u1, // bit offset: 4 desc: Active level for tamper 2 + TAMP3E: u1, // bit offset: 5 desc: Tamper 3 detection enable + TAMP3TRG: u1, // bit offset: 6 desc: Active level for tamper 3 + TAMPTS: u1, // bit offset: 7 desc: Activate timestamp on tamper detection event + TAMPFREQ: u3, // bit offset: 8 desc: Tamper sampling frequency + TAMPFLT: u2, // bit offset: 11 desc: Tamper filter count + TAMPPRCH: u2, // bit offset: 13 desc: Tamper precharge duration + TAMPPUDIS: u1, // bit offset: 15 desc: TAMPER pull-up disable + reserved2: u1 = 0, + reserved1: u1 = 0, + PC13VALUE: u1, // bit offset: 18 desc: PC13 value + PC13MODE: u1, // bit offset: 19 desc: PC13 mode + PC14VALUE: u1, // bit offset: 20 desc: PC14 value + PC14MODE: u1, // bit offset: 21 desc: PC 14 mode + PC15VALUE: u1, // bit offset: 22 desc: PC15 value + PC15MODE: u1, // bit offset: 23 desc: PC15 mode + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 alarm A sub second register + pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { + SS: u15, // bit offset: 0 desc: Sub seconds value + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 alarm B sub second register + pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { + SS: u15, // bit offset: 0 desc: Sub seconds value + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 backup register + pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 84 backup register + pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 88 backup register + pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 92 backup register + pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 96 backup register + pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 100 backup register + pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 104 backup register + pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 108 backup register + pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 112 backup register + pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 116 backup register + pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 120 backup register + pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 124 backup register + pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 128 backup register + pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 132 backup register + pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 136 backup register + pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 140 backup register + pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 144 backup register + pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 148 backup register + pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 152 backup register + pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 156 backup register + pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 160 backup register + pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 164 backup register + pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 168 backup register + pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 172 backup register + pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 176 backup register + pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 180 backup register + pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 184 backup register + pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 188 backup register + pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 192 backup register + pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 196 backup register + pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 200 backup register + pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 204 backup register + pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); +}; +pub const TIM6 = extern struct { + pub const Address: u32 = 0x40001000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM7 = extern struct { + pub const Address: u32 = 0x40001400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DAC = extern struct { + pub const Address: u32 = 0x40007400; + // byte offset: 0 control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + EN1: u1, // bit offset: 0 desc: DAC channel1 enable + BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable + TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable + TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection + WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable + MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector + DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable + DMAUDRIE1: u1, // bit offset: 13 desc: DAC channel1 DMA Underrun Interrupt enable + reserved2: u1 = 0, + reserved1: u1 = 0, + EN2: u1, // bit offset: 16 desc: DAC channel2 enable + BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable + TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable + TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection + WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable + MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector + DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable + DMAUDRIE2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun interrupt enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 software trigger register + pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { + SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger + SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 channel1 12-bit right-aligned data holding register + pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 channel1 12-bit left aligned data holding register + pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 channel1 8-bit right aligned data holding register + pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 channel2 12-bit right aligned data holding register + pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { + DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 channel2 12-bit left aligned data holding register + pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 channel2 8-bit right-aligned data holding register + pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { + DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Dual DAC 12-bit right-aligned data holding register + pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 DUAL DAC 12-bit left aligned data holding register + pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit left-aligned data + }); + // byte offset: 40 DUAL DAC 8-bit right aligned data holding register + pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 channel1 data output register + pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { + DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 channel2 data output register + pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { + DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 status register + pub const SR = mmio(Address + 0x00000034, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMAUDR1: u1, // bit offset: 13 desc: DAC channel1 DMA underrun flag + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + DMAUDR2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun flag + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const NVIC = extern struct { + pub const Address: u32 = 0xe000e000; + // byte offset: 4 Interrupt Controller Type Register + pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { + INTLINESNUM: u4, // bit offset: 0 desc: Total number of interrupt lines in groups + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 256 Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 260 Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 264 Interrupt Set-Enable Register + pub const ISER2 = mmio(Address + 0x00000108, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 384 Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 388 Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 392 Interrupt Clear-Enable Register + pub const ICER2 = mmio(Address + 0x00000188, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 512 Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 516 Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 520 Interrupt Set-Pending Register + pub const ISPR2 = mmio(Address + 0x00000208, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 640 Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 644 Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 648 Interrupt Clear-Pending Register + pub const ICPR2 = mmio(Address + 0x00000288, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 768 Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 772 Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 776 Interrupt Active Bit Register + pub const IABR2 = mmio(Address + 0x00000308, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 1024 Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1028 Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1032 Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1036 Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1040 Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1044 Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1048 Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1052 Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1056 Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1060 Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1064 Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1068 Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1072 Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1076 Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1080 Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1084 Interrupt Priority Register + pub const IPR15 = mmio(Address + 0x0000043c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1088 Interrupt Priority Register + pub const IPR16 = mmio(Address + 0x00000440, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1092 Interrupt Priority Register + pub const IPR17 = mmio(Address + 0x00000444, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1096 Interrupt Priority Register + pub const IPR18 = mmio(Address + 0x00000448, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1100 Interrupt Priority Register + pub const IPR19 = mmio(Address + 0x0000044c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 1104 Interrupt Priority Register + pub const IPR20 = mmio(Address + 0x00000450, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 3840 Software Triggered Interrupt Register + pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { + INTID: u9, // bit offset: 0 desc: interrupt to be triggered + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const FPU = extern struct { + pub const Address: u32 = 0xe000ed88; + // byte offset: 0 Coprocessor Access Control Register + pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { + CP0: u1, // bit offset: 0 desc: Access privileges for coprocessor 0 + reserved1: u1 = 0, + CP1: u1, // bit offset: 2 desc: Access privileges for coprocessor 1 + reserved2: u1 = 0, + CP2: u1, // bit offset: 4 desc: Access privileges for coprocessor 2 + reserved3: u1 = 0, + CP3: u1, // bit offset: 6 desc: Access privileges for coprocessor 3 + reserved4: u1 = 0, + CP4: u1, // bit offset: 8 desc: Access privileges for coprocessor 4 + reserved5: u1 = 0, + CP5: u1, // bit offset: 10 desc: Access privileges for coprocessor 5 + reserved6: u1 = 0, + CP6: u2, // bit offset: 12 desc: Access privileges for coprocessor 6 + CP7: u1, // bit offset: 14 desc: Access privileges for coprocessor 7 + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + CP10: u1, // bit offset: 20 desc: Access privileges for coprocessor 10 + reserved12: u1 = 0, + CP11: u1, // bit offset: 22 desc: Access privileges for coprocessor 11 + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 428 FP Context Control Register + pub const FPCCR = mmio(Address + 0x000001ac, 32, packed struct { + LSPACT: u1, // bit offset: 0 desc: LSPACT + USER: u1, // bit offset: 1 desc: USER + reserved1: u1 = 0, + THREAD: u1, // bit offset: 3 desc: THREAD + HFRDY: u1, // bit offset: 4 desc: HFRDY + MMRDY: u1, // bit offset: 5 desc: MMRDY + BFRDY: u1, // bit offset: 6 desc: BFRDY + reserved2: u1 = 0, + MONRDY: u1, // bit offset: 8 desc: MONRDY + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + LSPEN: u1, // bit offset: 30 desc: LSPEN + ASPEN: u1, // bit offset: 31 desc: ASPEN + }); + // byte offset: 432 FP Context Address Register + pub const FPCAR = mmio(Address + 0x000001b0, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRESS: u29, // bit offset: 3 desc: ADDRESS + }); + // byte offset: 436 FP Default Status Control Register + pub const FPDSCR = mmio(Address + 0x000001b4, 32, packed struct { + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RMode: u2, // bit offset: 22 desc: RMode + FZ: u1, // bit offset: 24 desc: FZ + DN: u1, // bit offset: 25 desc: DN + AHP: u1, // bit offset: 26 desc: AHP + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 440 Media and VFP Feature Register 0 + pub const MVFR0 = mmio(Address + 0x000001b8, 32, packed struct { + A_SIMD: u4, // bit offset: 0 desc: A_SIMD registers + Single_precision: u4, // bit offset: 4 desc: Single_precision + Double_precision: u4, // bit offset: 8 desc: Double_precision + FP_exception_trapping: u4, // bit offset: 12 desc: FP exception trapping + Divide: u4, // bit offset: 16 desc: Divide + Square_root: u4, // bit offset: 20 desc: Square root + Short_vectors: u4, // bit offset: 24 desc: Short vectors + FP_rounding_modes: u4, // bit offset: 28 desc: FP rounding modes + }); + // byte offset: 444 Media and VFP Feature Register 1 + pub const MVFR1 = mmio(Address + 0x000001bc, 32, packed struct { + FtZ_mode: u4, // bit offset: 0 desc: FtZ mode + D_NaN_mode: u4, // bit offset: 4 desc: D_NaN mode + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FP_HPFP: u4, // bit offset: 24 desc: FP HPFP + FP_fused_MAC: u4, // bit offset: 28 desc: FP fused MAC + }); +}; +pub const DBGMCU = extern struct { + pub const Address: u32 = 0xe0042000; + // byte offset: 0 MCU Device ID Code Register + pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { + DEV_ID: u12, // bit offset: 0 desc: Device Identifier + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + REV_ID: u16, // bit offset: 16 desc: Revision Identifier + }); + // byte offset: 4 Debug MCU Configuration Register + pub const CR = mmio(Address + 0x00000004, 32, packed struct { + DBG_SLEEP: u1, // bit offset: 0 desc: Debug Sleep mode + DBG_STOP: u1, // bit offset: 1 desc: Debug Stop Mode + DBG_STANDBY: u1, // bit offset: 2 desc: Debug Standby Mode + reserved2: u1 = 0, + reserved1: u1 = 0, + TRACE_IOEN: u1, // bit offset: 5 desc: Trace pin assignment control + TRACE_MODE: u2, // bit offset: 6 desc: Trace pin assignment control + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 APB Low Freeze Register + pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { + DBG_TIM2_STOP: u1, // bit offset: 0 desc: Debug Timer 2 stopped when Core is halted + DBG_TIM3_STOP: u1, // bit offset: 1 desc: Debug Timer 3 stopped when Core is halted + DBG_TIM4_STOP: u1, // bit offset: 2 desc: Debug Timer 4 stopped when Core is halted + DBG_TIM5_STOP: u1, // bit offset: 3 desc: Debug Timer 5 stopped when Core is halted + DBG_TIM6_STOP: u1, // bit offset: 4 desc: Debug Timer 6 stopped when Core is halted + DBG_TIM7_STOP: u1, // bit offset: 5 desc: Debug Timer 7 stopped when Core is halted + DBG_TIM12_STOP: u1, // bit offset: 6 desc: Debug Timer 12 stopped when Core is halted + DBG_TIM13_STOP: u1, // bit offset: 7 desc: Debug Timer 13 stopped when Core is halted + DBG_TIMER14_STOP: u1, // bit offset: 8 desc: Debug Timer 14 stopped when Core is halted + DBG_TIM18_STOP: u1, // bit offset: 9 desc: Debug Timer 18 stopped when Core is halted + DBG_RTC_STOP: u1, // bit offset: 10 desc: Debug RTC stopped when Core is halted + DBG_WWDG_STOP: u1, // bit offset: 11 desc: Debug Window Wachdog stopped when Core is halted + DBG_IWDG_STOP: u1, // bit offset: 12 desc: Debug Independent Wachdog stopped when Core is halted + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + I2C1_SMBUS_TIMEOUT: u1, // bit offset: 21 desc: SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1, // bit offset: 22 desc: SMBUS timeout mode stopped when Core is halted + reserved10: u1 = 0, + reserved9: u1 = 0, + DBG_CAN_STOP: u1, // bit offset: 25 desc: Debug CAN stopped when core is halted + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 APB High Freeze Register + pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + DBG_TIM15_STOP: u1, // bit offset: 2 desc: Debug Timer 15 stopped when Core is halted + DBG_TIM16_STOP: u1, // bit offset: 3 desc: Debug Timer 16 stopped when Core is halted + DBG_TIM17_STO: u1, // bit offset: 4 desc: Debug Timer 17 stopped when Core is halted + DBG_TIM19_STOP: u1, // bit offset: 5 desc: Debug Timer 19 stopped when Core is halted + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM1 = extern struct { + pub const Address: u32 = 0x40012c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + reserved2: u1 = 0, + OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + reserved3: u1 = 0, + OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + reserved4: u1 = 0, + MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: Reserved + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag + C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + B2G: u1, // bit offset: 8 desc: Break 2 generation + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved1: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity + CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable + CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + reserved3: u1 = 0, + reserved2: u1 = 0, + CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable + CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u16, // bit offset: 0 desc: Repetition counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + BK2F: u4, // bit offset: 20 desc: Break 2 filter + BK2E: u1, // bit offset: 24 desc: Break 2 enable + BK2P: u1, // bit offset: 25 desc: Break 2 polarity + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 capture/compare mode register 3 (output mode) + pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable + OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable + OC5M: u3, // bit offset: 4 desc: Output compare 5 mode + OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + reserved4: u1 = 0, + reserved3: u1 = 0, + OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable + OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable + OC6M: u3, // bit offset: 12 desc: Output compare 6 mode + OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable + OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 88 capture/compare register 5 + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 + GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 + GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + }); + // byte offset: 92 capture/compare register 6 + pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { + CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 option registers + pub const OR = mmio(Address + 0x00000060, 32, packed struct { + TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM8 = extern struct { + pub const Address: u32 = 0x40013400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + reserved2: u1 = 0, + OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + reserved3: u1 = 0, + OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + reserved4: u1 = 0, + MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: Reserved + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag + C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + B2G: u1, // bit offset: 8 desc: Break 2 generation + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved1: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity + CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable + CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + reserved3: u1 = 0, + reserved2: u1 = 0, + CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable + CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u16, // bit offset: 0 desc: Repetition counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + BK2F: u4, // bit offset: 20 desc: Break 2 filter + BK2E: u1, // bit offset: 24 desc: Break 2 enable + BK2P: u1, // bit offset: 25 desc: Break 2 polarity + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 capture/compare mode register 3 (output mode) + pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable + OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable + OC5M: u3, // bit offset: 4 desc: Output compare 5 mode + OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + reserved4: u1 = 0, + reserved3: u1 = 0, + OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable + OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable + OC6M: u3, // bit offset: 12 desc: Output compare 6 mode + OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable + OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 88 capture/compare register 5 + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 + GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 + GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + }); + // byte offset: 92 capture/compare register 6 + pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { + CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 option registers + pub const OR = mmio(Address + 0x00000060, 32, packed struct { + TIM8_ETR_ADC2_RMP: u2, // bit offset: 0 desc: TIM8_ETR_ADC2 remapping capability + TIM8_ETR_ADC3_RMP: u2, // bit offset: 2 desc: TIM8_ETR_ADC3 remapping capability + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC1 = extern struct { + pub const Address: u32 = 0x50000000; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT2: u8, // bit offset: 16 desc: HT2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, + reserved1: u1 = 0, + SQ1: u5, // bit offset: 6 desc: SQ1 + reserved3: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 + reserved1: u1 = 0, + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 + reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 + reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 + reserved1: u1 = 0, + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + }); + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN + }); + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + AWD2CH: u18, // bit offset: 1 desc: AWD2CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { + reserved1: u1 = 0, + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC2 = extern struct { + pub const Address: u32 = 0x50000100; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT2: u8, // bit offset: 16 desc: HT2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, + reserved1: u1 = 0, + SQ1: u5, // bit offset: 6 desc: SQ1 + reserved3: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 + reserved1: u1 = 0, + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 + reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 + reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 + reserved1: u1 = 0, + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + }); + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN + }); + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + AWD2CH: u18, // bit offset: 1 desc: AWD2CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { + reserved1: u1 = 0, + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC3 = extern struct { + pub const Address: u32 = 0x50000400; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT2: u8, // bit offset: 16 desc: HT2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, + reserved1: u1 = 0, + SQ1: u5, // bit offset: 6 desc: SQ1 + reserved3: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 + reserved1: u1 = 0, + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 + reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 + reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 + reserved1: u1 = 0, + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + }); + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN + }); + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + AWD2CH: u18, // bit offset: 1 desc: AWD2CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { + reserved1: u1 = 0, + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC4 = extern struct { + pub const Address: u32 = 0x50000500; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT2: u8, // bit offset: 16 desc: HT2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, + reserved1: u1 = 0, + SQ1: u5, // bit offset: 6 desc: SQ1 + reserved3: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 + reserved1: u1 = 0, + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 + reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 + reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 + reserved1: u1 = 0, + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + }); + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN + }); + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + AWD2CH: u18, // bit offset: 1 desc: AWD2CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { + reserved1: u1 = 0, + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC1_2 = extern struct { + pub const Address: u32 = 0x50000300; + // byte offset: 0 ADC Common status register + pub const CSR = mmio(Address + 0x00000000, 32, packed struct { + ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST + EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST + EOC_MST: u1, // bit offset: 2 desc: EOC_MST + EOS_MST: u1, // bit offset: 3 desc: EOS_MST + OVR_MST: u1, // bit offset: 4 desc: OVR_MST + JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST + JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST + AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST + AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST + AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST + JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV + EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV + EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC + EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC + OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC + JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC + JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC + AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC + AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC + AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC + JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 ADC common control register + pub const CCR = mmio(Address + 0x00000008, 32, packed struct { + MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + reserved4: u1 = 0, + DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) + MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode + CKMODE: u2, // bit offset: 16 desc: ADC clock mode + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + VREFEN: u1, // bit offset: 22 desc: VREFINT enable + TSEN: u1, // bit offset: 23 desc: Temperature sensor enable + VBATEN: u1, // bit offset: 24 desc: VBAT enable + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 ADC common regular data register for dual and triple modes + pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { + RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC + RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + }); +}; +pub const ADC3_4 = extern struct { + pub const Address: u32 = 0x50000700; + // byte offset: 0 ADC Common status register + pub const CSR = mmio(Address + 0x00000000, 32, packed struct { + ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST + EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST + EOC_MST: u1, // bit offset: 2 desc: EOC_MST + EOS_MST: u1, // bit offset: 3 desc: EOS_MST + OVR_MST: u1, // bit offset: 4 desc: OVR_MST + JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST + JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST + AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST + AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST + AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST + JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV + EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV + EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC + EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC + OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC + JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC + JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC + AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC + AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC + AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC + JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 ADC common control register + pub const CCR = mmio(Address + 0x00000008, 32, packed struct { + MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + reserved4: u1 = 0, + DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) + MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode + CKMODE: u2, // bit offset: 16 desc: ADC clock mode + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + VREFEN: u1, // bit offset: 22 desc: VREFINT enable + TSEN: u1, // bit offset: 23 desc: Temperature sensor enable + VBATEN: u1, // bit offset: 24 desc: VBAT enable + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 ADC common regular data register for dual and triple modes + pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { + RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC + RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + }); +}; +pub const SYSCFG = extern struct { + pub const Address: u32 = 0x40010000; + // byte offset: 0 configuration register 1 + pub const CFGR1 = mmio(Address + 0x00000000, 32, packed struct { + MEM_MODE: u2, // bit offset: 0 desc: Memory mapping selection bits + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + USB_IT_RMP: u1, // bit offset: 5 desc: USB interrupt remap + TIM1_ITR_RMP: u1, // bit offset: 6 desc: Timer 1 ITR3 selection + DAC_TRIG_RMP: u1, // bit offset: 7 desc: DAC trigger remap (when TSEL = 001) + ADC24_DMA_RMP: u1, // bit offset: 8 desc: ADC24 DMA remapping bit + reserved5: u1 = 0, + reserved4: u1 = 0, + TIM16_DMA_RMP: u1, // bit offset: 11 desc: TIM16 DMA request remapping bit + TIM17_DMA_RMP: u1, // bit offset: 12 desc: TIM17 DMA request remapping bit + TIM6_DAC1_DMA_RMP: u1, // bit offset: 13 desc: TIM6 and DAC1 DMA request remapping bit + TIM7_DAC2_DMA_RMP: u1, // bit offset: 14 desc: TIM7 and DAC2 DMA request remapping bit + reserved6: u1 = 0, + I2C_PB6_FM: u1, // bit offset: 16 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB7_FM: u1, // bit offset: 17 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB8_FM: u1, // bit offset: 18 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB9_FM: u1, // bit offset: 19 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C1_FM: u1, // bit offset: 20 desc: I2C1 Fast Mode Plus + I2C2_FM: u1, // bit offset: 21 desc: I2C2 Fast Mode Plus + ENCODER_MODE: u2, // bit offset: 22 desc: Encoder mode + reserved8: u1 = 0, + reserved7: u1 = 0, + FPU_IT: u6, // bit offset: 26 desc: Interrupt enable bits from FPU + }); + // byte offset: 4 CCM SRAM protection register + pub const RCR = mmio(Address + 0x00000004, 32, packed struct { + PAGE0_WP: u1, // bit offset: 0 desc: CCM SRAM page write protection bit + PAGE1_WP: u1, // bit offset: 1 desc: CCM SRAM page write protection bit + PAGE2_WP: u1, // bit offset: 2 desc: CCM SRAM page write protection bit + PAGE3_WP: u1, // bit offset: 3 desc: CCM SRAM page write protection bit + PAGE4_WP: u1, // bit offset: 4 desc: CCM SRAM page write protection bit + PAGE5_WP: u1, // bit offset: 5 desc: CCM SRAM page write protection bit + PAGE6_WP: u1, // bit offset: 6 desc: CCM SRAM page write protection bit + PAGE7_WP: u1, // bit offset: 7 desc: CCM SRAM page write protection bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 external interrupt configuration register 1 + pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { + EXTI0: u4, // bit offset: 0 desc: EXTI 0 configuration bits + EXTI1: u4, // bit offset: 4 desc: EXTI 1 configuration bits + EXTI2: u4, // bit offset: 8 desc: EXTI 2 configuration bits + EXTI3: u4, // bit offset: 12 desc: EXTI 3 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 external interrupt configuration register 2 + pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { + EXTI4: u4, // bit offset: 0 desc: EXTI 4 configuration bits + EXTI5: u4, // bit offset: 4 desc: EXTI 5 configuration bits + EXTI6: u4, // bit offset: 8 desc: EXTI 6 configuration bits + EXTI7: u4, // bit offset: 12 desc: EXTI 7 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 external interrupt configuration register 3 + pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { + EXTI8: u4, // bit offset: 0 desc: EXTI 8 configuration bits + EXTI9: u4, // bit offset: 4 desc: EXTI 9 configuration bits + EXTI10: u4, // bit offset: 8 desc: EXTI 10 configuration bits + EXTI11: u4, // bit offset: 12 desc: EXTI 11 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 external interrupt configuration register 4 + pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { + EXTI12: u4, // bit offset: 0 desc: EXTI 12 configuration bits + EXTI13: u4, // bit offset: 4 desc: EXTI 13 configuration bits + EXTI14: u4, // bit offset: 8 desc: EXTI 14 configuration bits + EXTI15: u4, // bit offset: 12 desc: EXTI 15 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 configuration register 2 + pub const CFGR2 = mmio(Address + 0x00000018, 32, packed struct { + LOCUP_LOCK: u1, // bit offset: 0 desc: Cortex-M0 LOCKUP bit enable bit + SRAM_PARITY_LOCK: u1, // bit offset: 1 desc: SRAM parity lock bit + PVD_LOCK: u1, // bit offset: 2 desc: PVD lock enable bit + reserved1: u1 = 0, + BYP_ADD_PAR: u1, // bit offset: 4 desc: Bypass address bit 29 in parity calculation + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + SRAM_PEF: u1, // bit offset: 8 desc: SRAM parity flag + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const OPAMP = extern struct { + pub const Address: u32 = 0x40010038; + // byte offset: 0 OPAMP1 control register + pub const OPAMP1_CR = mmio(Address + 0x00000000, 32, packed struct { + OPAMP1_EN: u1, // bit offset: 0 desc: OPAMP1 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP1 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP1 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP1 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP1 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 1 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 1 lock + }); + // byte offset: 4 OPAMP2 control register + pub const OPAMP2_CR = mmio(Address + 0x00000004, 32, packed struct { + OPAMP2EN: u1, // bit offset: 0 desc: OPAMP2 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP2 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP2 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP2 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP2 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CAL_SEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 2 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 2 lock + }); + // byte offset: 8 OPAMP3 control register + pub const OPAMP3_CR = mmio(Address + 0x00000008, 32, packed struct { + OPAMP3EN: u1, // bit offset: 0 desc: OPAMP3 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP3 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP3 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP3 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP3 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 3 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 3 lock + }); + // byte offset: 12 OPAMP4 control register + pub const OPAMP4_CR = mmio(Address + 0x0000000c, 32, packed struct { + OPAMP4EN: u1, // bit offset: 0 desc: OPAMP4 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP4 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP4 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP4 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP4 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 4 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 4 lock + }); +}; diff --git a/src/modules/chips/stm32f30x/stm32f30x.zig b/src/modules/chips/stm32f30x/stm32f30x.zig new file mode 100644 index 0000000..9c13c60 --- /dev/null +++ b/src/modules/chips/stm32f30x/stm32f30x.zig @@ -0,0 +1,55 @@ +const std = @import("std"); +const micro = @import("microzig"); + +pub const cpu = @import("cpu"); +pub const registers = @import("registers.zig"); + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'H') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'H' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(registers, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn setInput(comptime pin: type) void { + setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + switch (state) { + .low => setRegField(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1), + .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 3f4c648..7c1ff7d 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -28,3 +28,14 @@ pub const cortex_m3 = Cpu{ .abi = .none, }, }; + +pub const cortex_m4 = Cpu{ + .name = "ARM Cortex-M4", + .path = root_path ++ "cpus/cortex-m4/cortex-m4.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .none, + }, +}; diff --git a/src/modules/cpus/cortex-m4/cortex-m4.zig b/src/modules/cpus/cortex-m4/cortex-m4.zig new file mode 100644 index 0000000..832279e --- /dev/null +++ b/src/modules/cpus/cortex-m4/cortex-m4.zig @@ -0,0 +1,103 @@ +const std = @import("std"); + +pub fn sei() void { + asm volatile ("cpsie i"); +} + +pub fn cli() void { + asm volatile ("cpsid i"); +} + +pub fn enable_fault_irq() void { + asm volatile ("cpsie f"); +} +pub fn disable_fault_irq() void { + asm volatile ("cpsid f"); +} + +pub fn nop() void { + asm volatile ("nop"); +} +pub fn wfi() void { + asm volatile ("wfi"); +} +pub fn wfe() void { + asm volatile ("wfe"); +} +pub fn sev() void { + asm volatile ("sev"); +} +pub fn isb() void { + asm volatile ("isb"); +} +pub fn dsb() void { + asm volatile ("dsb"); +} +pub fn dmb() void { + asm volatile ("dmb"); +} +pub fn clrex() void { + asm volatile ("clrex"); +} + +pub const startup_logic = struct { + const InterruptVector = fn () callconv(.C) void; + + const VectorTable = extern struct { + initial_stack_pointer: u32, + reset: InterruptVector, + nmi: InterruptVector = makeUnhandledHandler("nmi"), + hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), + mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), + bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), + usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), + + reserved: u32 = 0, + }; + + export const vectors linksection("microzig_flash_start") = VectorTable{ + // TODO: How to compute/get the initial stack pointer? + .initial_stack_pointer = 0x2000_A000, // HACK: hardcoded, do not keep! + .reset = _start, + }; + + fn makeUnhandledHandler(comptime str: []const u8) fn () callconv(.C) noreturn { + return struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt; + } + + extern fn microzig_main() noreturn; + + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; + + fn _start() callconv(.C) noreturn { + + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, µzig_bss_start); + const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, µzig_data_start); + const data_end = @ptrCast([*]u8, µzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, µzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } + + microzig_main(); + } +}; diff --git a/tests/blinky.zig b/tests/blinky.zig index 1ef09bc..7a24275 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -8,6 +8,7 @@ const led_pin = if (micro.config.has_board) switch (micro.config.board_name) { .@"Arduino Nano" => micro.Pin("D13"), .@"mbed LPC1768" => micro.Pin("LED-1"), + .@"STM32F3DISCOVERY" => micro.Pin("LD3"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) { From 38110fb3bddc314787d2b0b057d026e546ba3c9b Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 11 Feb 2022 23:29:09 -0800 Subject: [PATCH 022/138] calculate end-of-stack value from chip configs (#12) --- build.zig | 2 +- src/main.zig | 25 ++++++++++++++++++------ src/modules/cpus/cortex-m3/cortex-m3.zig | 4 ++-- src/modules/cpus/cortex-m4/cortex-m4.zig | 4 ++-- 4 files changed, 24 insertions(+), 11 deletions(-) diff --git a/build.zig b/build.zig index 62771e2..eaa0192 100644 --- a/build.zig +++ b/build.zig @@ -16,7 +16,7 @@ pub fn build(b: *std.build.Builder) !void { const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart: bool = true }; const all_backings = [_]BuildConfig{ - //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = pkgs.boards.arduino_nano } }, + //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, diff --git a/src/main.zig b/src/main.zig index 0141522..aa43c73 100644 --- a/src/main.zig +++ b/src/main.zig @@ -63,6 +63,18 @@ pub fn addEmbeddedExecutable( }; { + // TODO: let the user override which ram section to use the stack on, + // for now just using the first ram section in the memory region list + const first_ram = blk: { + for (chip.memory_regions) |region| { + if (region.kind == .ram) + break :blk region; + } else { + std.log.err("no ram memory region found for setting the end-of-stack address", .{}); + return error.NoRam; + } + }; + std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; var config_file = try std.fs.cwd().createFile(config_file_name, .{}); defer config_file.close(); @@ -74,6 +86,7 @@ pub fn addEmbeddedExecutable( try writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}); try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); + try writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}); } const microzig_pkg = Pkg{ @@ -81,6 +94,11 @@ pub fn addEmbeddedExecutable( .path = .{ .path = root_path ++ "core/microzig.zig" }, }; + const config_pkg = Pkg{ + .name = "microzig-config", + .path = .{ .path = config_file_name }, + }; + const chip_pkg = Pkg{ .name = "chip", .path = .{ .path = chip.path }, @@ -90,16 +108,11 @@ pub fn addEmbeddedExecutable( Pkg{ .name = "cpu", .path = .{ .path = chip.cpu.path }, - .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio }, + .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio, config_pkg }, }, }, }; - const config_pkg = Pkg{ - .name = "microzig-config", - .path = .{ .path = config_file_name }, - }; - const exe = builder.addExecutable(name, root_path ++ "core/start.zig"); // might not be true for all machines (Pi Pico), but diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig index 4f24e7d..8512f26 100644 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ b/src/modules/cpus/cortex-m3/cortex-m3.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const config = @import("microzig-config"); pub fn sei() void { asm volatile ("cpsie i"); @@ -56,8 +57,7 @@ pub const startup_logic = struct { }; export const vectors linksection("microzig_flash_start") = VectorTable{ - // TODO: How to compute/get the initial stack pointer? - .initial_stack_pointer = 0x1000_7FFC, // HACK: hardcoded, do not keep! + .initial_stack_pointer = config.end_of_stack, .reset = _start, }; diff --git a/src/modules/cpus/cortex-m4/cortex-m4.zig b/src/modules/cpus/cortex-m4/cortex-m4.zig index 832279e..8512f26 100644 --- a/src/modules/cpus/cortex-m4/cortex-m4.zig +++ b/src/modules/cpus/cortex-m4/cortex-m4.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const config = @import("microzig-config"); pub fn sei() void { asm volatile ("cpsie i"); @@ -56,8 +57,7 @@ pub const startup_logic = struct { }; export const vectors linksection("microzig_flash_start") = VectorTable{ - // TODO: How to compute/get the initial stack pointer? - .initial_stack_pointer = 0x2000_A000, // HACK: hardcoded, do not keep! + .initial_stack_pointer = config.end_of_stack, .reset = _start, }; From 23eb8d5658deba05e6885d4fd37e9fc8d2f4f3e5 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 12 Feb 2022 10:30:58 -0800 Subject: [PATCH 023/138] add packages to your embedded app (#13) --- build.zig | 1 + src/main.zig | 60 +++++++++++++++++++++++++++++++++------------------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/build.zig b/build.zig index eaa0192..8633891 100644 --- a/build.zig +++ b/build.zig @@ -42,6 +42,7 @@ pub fn build(b: *std.build.Builder) !void { "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".elf", tst.source, cfg.backing, + .{}, ); if (filter == null or exe.target.cpu_arch.? == filter.?) { diff --git a/src/main.zig b/src/main.zig index aa43c73..451f84a 100644 --- a/src/main.zig +++ b/src/main.zig @@ -18,11 +18,16 @@ fn root() []const u8 { return std.fs.path.dirname(@src().file) orelse unreachable; } +pub const BuildOptions = struct { + packages: ?[]const Pkg = null, +}; + pub fn addEmbeddedExecutable( builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing, + options: BuildOptions, ) !*std.build.LibExeObjStep { const has_board = (backing == .board); const chip = switch (backing) { @@ -130,17 +135,22 @@ pub fn addEmbeddedExecutable( exe.bundle_compiler_rt = false; switch (backing) { .chip => { + var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); + try app_pkgs.append(Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, + .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, + }); + + if (options.packages) |packages| + try app_pkgs.appendSlice(packages); + exe.addPackage(Pkg{ .name = "app", .path = .{ .path = source }, - .dependencies = &[_]Pkg{ - Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, - }, - }, + .dependencies = app_pkgs.items, }); + exe.addPackage(Pkg{ .name = microzig_pkg.name, .path = microzig_pkg.path, @@ -148,24 +158,30 @@ pub fn addEmbeddedExecutable( }); }, .board => |board| { - exe.addPackage(Pkg{ - .name = "app", - .path = .{ .path = source }, - .dependencies = &[_]Pkg{ - Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ - config_pkg, - chip_pkg, - Pkg{ - .name = "board", - .path = .{ .path = board.path }, - .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, - }, + var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); + try app_pkgs.append( + Pkg{ + .name = microzig_pkg.name, + .path = microzig_pkg.path, + .dependencies = &[_]Pkg{ + config_pkg, + chip_pkg, + Pkg{ + .name = "board", + .path = .{ .path = board.path }, + .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, }, }, }, + ); + + if (options.packages) |packages| + try app_pkgs.appendSlice(packages); + + exe.addPackage(Pkg{ + .name = "app", + .path = .{ .path = source }, + .dependencies = app_pkgs.items, }); exe.addPackage(Pkg{ From 0124a1477320ed3dcd12302ecc824ca8477c5f28 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 12 Feb 2022 12:34:36 -0800 Subject: [PATCH 024/138] Add interrupt declaration to cortex-m microcontrollers (#14) Co-authored-by: Vesim --- build.zig | 3 + src/modules/cpus.zig | 4 +- src/modules/cpus/cortex-m/cortex-m.zig | 163 +++++++++++++++++++++++ src/modules/cpus/cortex-m3/cortex-m3.zig | 103 -------------- src/modules/cpus/cortex-m4/cortex-m4.zig | 103 -------------- tests/interrupt.zig | 18 +++ 6 files changed, 186 insertions(+), 208 deletions(-) create mode 100644 src/modules/cpus/cortex-m/cortex-m.zig delete mode 100644 src/modules/cpus/cortex-m3/cortex-m3.zig delete mode 100644 src/modules/cpus/cortex-m4/cortex-m4.zig create mode 100644 tests/interrupt.zig diff --git a/build.zig b/build.zig index 8633891..bb380ae 100644 --- a/build.zig +++ b/build.zig @@ -29,6 +29,9 @@ pub fn build(b: *std.build.Builder) !void { Test{ .name = "minimal", .source = "tests/minimal.zig" }, Test{ .name = "blinky", .source = "tests/blinky.zig" }, Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true }, + + // Note: this example uses the systick interrupt and therefore only for arm microcontrollers + Test{ .name = "interrupt", .source = "tests/interrupt.zig" }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 7c1ff7d..7fd8f30 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -20,7 +20,7 @@ pub const avr5 = Cpu{ pub const cortex_m3 = Cpu{ .name = "ARM Cortex-M3", - .path = root_path ++ "cpus/cortex-m3/cortex-m3.zig", + .path = root_path ++ "cpus/cortex-m/cortex-m.zig", .target = std.zig.CrossTarget{ .cpu_arch = .arm, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, @@ -31,7 +31,7 @@ pub const cortex_m3 = Cpu{ pub const cortex_m4 = Cpu{ .name = "ARM Cortex-M4", - .path = root_path ++ "cpus/cortex-m4/cortex-m4.zig", + .path = root_path ++ "cpus/cortex-m/cortex-m.zig", .target = std.zig.CrossTarget{ .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig new file mode 100644 index 0000000..f5f4d1f --- /dev/null +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -0,0 +1,163 @@ +const std = @import("std"); +const root = @import("root"); +const config = @import("microzig-config"); + +pub fn sei() void { + asm volatile ("cpsie i"); +} + +pub fn cli() void { + asm volatile ("cpsid i"); +} + +pub fn enable_fault_irq() void { + asm volatile ("cpsie f"); +} +pub fn disable_fault_irq() void { + asm volatile ("cpsid f"); +} + +pub fn nop() void { + asm volatile ("nop"); +} +pub fn wfi() void { + asm volatile ("wfi"); +} +pub fn wfe() void { + asm volatile ("wfe"); +} +pub fn sev() void { + asm volatile ("sev"); +} +pub fn isb() void { + asm volatile ("isb"); +} +pub fn dsb() void { + asm volatile ("dsb"); +} +pub fn dmb() void { + asm volatile ("dmb"); +} +pub fn clrex() void { + asm volatile ("clrex"); +} + +pub const startup_logic = struct { + const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm + }; + + const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + reset: InterruptVector = InterruptVector{ .C = _start }, + nmi: InterruptVector = makeUnhandledHandler("nmi"), + hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), + mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), + bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), + usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), + secure_fault: InterruptVector = makeUnhandledHandler("secure_fault"), + + reserved: [3]u32 = .{ 0, 0, 0 }, + svc: InterruptVector = makeUnhandledHandler("svc"), + debugmon: InterruptVector = makeUnhandledHandler("debugmon"), + reserved1: u32 = 0, + + pendsv: InterruptVector = makeUnhandledHandler("pendsv"), + systick: InterruptVector = makeUnhandledHandler("systick"), + }; + + fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); + } + + export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "' declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; + }; + + fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; + } + + extern fn microzig_main() noreturn; + + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; + + fn _start() callconv(.C) noreturn { + + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, µzig_bss_start); + const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, µzig_data_start); + const data_end = @ptrCast([*]u8, µzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, µzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } + + microzig_main(); + } +}; diff --git a/src/modules/cpus/cortex-m3/cortex-m3.zig b/src/modules/cpus/cortex-m3/cortex-m3.zig deleted file mode 100644 index 8512f26..0000000 --- a/src/modules/cpus/cortex-m3/cortex-m3.zig +++ /dev/null @@ -1,103 +0,0 @@ -const std = @import("std"); -const config = @import("microzig-config"); - -pub fn sei() void { - asm volatile ("cpsie i"); -} - -pub fn cli() void { - asm volatile ("cpsid i"); -} - -pub fn enable_fault_irq() void { - asm volatile ("cpsie f"); -} -pub fn disable_fault_irq() void { - asm volatile ("cpsid f"); -} - -pub fn nop() void { - asm volatile ("nop"); -} -pub fn wfi() void { - asm volatile ("wfi"); -} -pub fn wfe() void { - asm volatile ("wfe"); -} -pub fn sev() void { - asm volatile ("sev"); -} -pub fn isb() void { - asm volatile ("isb"); -} -pub fn dsb() void { - asm volatile ("dsb"); -} -pub fn dmb() void { - asm volatile ("dmb"); -} -pub fn clrex() void { - asm volatile ("clrex"); -} - -pub const startup_logic = struct { - const InterruptVector = fn () callconv(.C) void; - - const VectorTable = extern struct { - initial_stack_pointer: u32, - reset: InterruptVector, - nmi: InterruptVector = makeUnhandledHandler("nmi"), - hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), - mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), - bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), - usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), - - reserved: u32 = 0, - }; - - export const vectors linksection("microzig_flash_start") = VectorTable{ - .initial_stack_pointer = config.end_of_stack, - .reset = _start, - }; - - fn makeUnhandledHandler(comptime str: []const u8) fn () callconv(.C) noreturn { - return struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt; - } - - extern fn microzig_main() noreturn; - - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; - - fn _start() callconv(.C) noreturn { - - // fill .bss with zeroes - { - const bss_start = @ptrCast([*]u8, µzig_bss_start); - const bss_end = @ptrCast([*]u8, µzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - - std.mem.set(u8, bss_start[0..bss_len], 0); - } - - // load .data from flash - { - const data_start = @ptrCast([*]u8, µzig_data_start); - const data_end = @ptrCast([*]u8, µzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); - const data_src = @ptrCast([*]const u8, µzig_data_load_start); - - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); - } - - microzig_main(); - } -}; diff --git a/src/modules/cpus/cortex-m4/cortex-m4.zig b/src/modules/cpus/cortex-m4/cortex-m4.zig deleted file mode 100644 index 8512f26..0000000 --- a/src/modules/cpus/cortex-m4/cortex-m4.zig +++ /dev/null @@ -1,103 +0,0 @@ -const std = @import("std"); -const config = @import("microzig-config"); - -pub fn sei() void { - asm volatile ("cpsie i"); -} - -pub fn cli() void { - asm volatile ("cpsid i"); -} - -pub fn enable_fault_irq() void { - asm volatile ("cpsie f"); -} -pub fn disable_fault_irq() void { - asm volatile ("cpsid f"); -} - -pub fn nop() void { - asm volatile ("nop"); -} -pub fn wfi() void { - asm volatile ("wfi"); -} -pub fn wfe() void { - asm volatile ("wfe"); -} -pub fn sev() void { - asm volatile ("sev"); -} -pub fn isb() void { - asm volatile ("isb"); -} -pub fn dsb() void { - asm volatile ("dsb"); -} -pub fn dmb() void { - asm volatile ("dmb"); -} -pub fn clrex() void { - asm volatile ("clrex"); -} - -pub const startup_logic = struct { - const InterruptVector = fn () callconv(.C) void; - - const VectorTable = extern struct { - initial_stack_pointer: u32, - reset: InterruptVector, - nmi: InterruptVector = makeUnhandledHandler("nmi"), - hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), - mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), - bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), - usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), - - reserved: u32 = 0, - }; - - export const vectors linksection("microzig_flash_start") = VectorTable{ - .initial_stack_pointer = config.end_of_stack, - .reset = _start, - }; - - fn makeUnhandledHandler(comptime str: []const u8) fn () callconv(.C) noreturn { - return struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt; - } - - extern fn microzig_main() noreturn; - - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; - - fn _start() callconv(.C) noreturn { - - // fill .bss with zeroes - { - const bss_start = @ptrCast([*]u8, µzig_bss_start); - const bss_end = @ptrCast([*]u8, µzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - - std.mem.set(u8, bss_start[0..bss_len], 0); - } - - // load .data from flash - { - const data_start = @ptrCast([*]u8, µzig_data_start); - const data_end = @ptrCast([*]u8, µzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); - const data_src = @ptrCast([*]const u8, µzig_data_load_start); - - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); - } - - microzig_main(); - } -}; diff --git a/tests/interrupt.zig b/tests/interrupt.zig new file mode 100644 index 0000000..33a3e63 --- /dev/null +++ b/tests/interrupt.zig @@ -0,0 +1,18 @@ +const micro = @import("microzig"); + +// this program will only work on arm microcontrollers, and it might not +// actually run correctly at first, it's just a test for declaring interrupts +// right now. + +pub const panic = micro.panic; +pub const vector_table = struct { + pub fn systick() callconv(.Naked) void { + @panic("hit systick!"); + } +}; + +pub fn main() void { + while (true) { + micro.cpu.wfi(); + } +} From 152db2ae5fb548c6563f62993041f01496a2eb92 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 12 Feb 2022 14:06:34 -0800 Subject: [PATCH 025/138] no need to make the interrupt the .Naked calling convention (#15) --- tests/interrupt.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/interrupt.zig b/tests/interrupt.zig index 33a3e63..9406a8e 100644 --- a/tests/interrupt.zig +++ b/tests/interrupt.zig @@ -6,7 +6,7 @@ const micro = @import("microzig"); pub const panic = micro.panic; pub const vector_table = struct { - pub fn systick() callconv(.Naked) void { + pub fn systick() void { @panic("hit systick!"); } }; From c34d8b73d5491344f762fbfe924c5f50ddca31ea Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 13 Feb 2022 10:33:13 -0800 Subject: [PATCH 026/138] interrupt generation for chips (#16) --- src/main.zig | 3 +- src/modules/boards.zig | 2 +- src/modules/chips.zig | 6 +- src/modules/chips/lpc1768/registers.zig | 126 + src/modules/chips/stm32f103/registers.zig | 270 + .../{stm32f30x => stm32f303}/registers.zig | 18577 +++++++++------- .../stm32f30x.zig => stm32f303/stm32f303.zig} | 0 src/modules/cpus/cortex-m/cortex-m.zig | 89 +- src/tools/svd2zig.py | 132 +- tests/interrupt.zig | 2 +- 10 files changed, 11346 insertions(+), 7861 deletions(-) rename src/modules/chips/{stm32f30x => stm32f303}/registers.zig (85%) rename src/modules/chips/{stm32f30x/stm32f30x.zig => stm32f303/stm32f303.zig} (100%) diff --git a/src/main.zig b/src/main.zig index 451f84a..66f5c48 100644 --- a/src/main.zig +++ b/src/main.zig @@ -110,10 +110,11 @@ pub fn addEmbeddedExecutable( .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio, + config_pkg, Pkg{ .name = "cpu", .path = .{ .path = chip.cpu.path }, - .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio, config_pkg }, + .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio }, }, }, }; diff --git a/src/modules/boards.zig b/src/modules/boards.zig index 6c03b51..e0ce389 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -23,5 +23,5 @@ pub const mbed_lpc1768 = Board{ pub const stm32f3discovery = Board{ .name = "STM32F3DISCOVERY", .path = root_path ++ "boards/stm32f3discovery/stm32f3discovery.zig", - .chip = chips.stm32f30x, + .chip = chips.stm32f303vc, }; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 13cd9ba..25c6cf2 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -40,9 +40,9 @@ pub const stm32f103x8 = Chip{ }, }; -pub const stm32f30x = Chip{ - .name = "STM32F30x", - .path = root_path ++ "chips/stm32f30x/stm32f30x.zig", +pub const stm32f303vc = Chip{ + .name = "STM32F303VC", + .path = root_path ++ "chips/stm32f303/stm32f303.zig", .cpu = cpus.cortex_m4, .memory_regions = &.{ MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash }, diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 807b7a4..436e99e 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -21724,3 +21724,129 @@ pub const GPIO = extern struct { PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. }); }; + +const std = @import("std"); +const root = @import("root"); +const cpu = @import("cpu"); +const config = @import("microzig-config"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler("NMI"), + HardFault: InterruptVector = makeUnhandledHandler("HardFault"), + MemManage: InterruptVector = makeUnhandledHandler("MemManage"), + BusFault: InterruptVector = makeUnhandledHandler("BusFault"), + UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler("SVCall"), + DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler("PendSV"), + SysTick: InterruptVector = makeUnhandledHandler("SysTick"), + + WDT: InterruptVector = makeUnhandledHandler("WDT"), + TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), + TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), + TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), + TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), + UART0: InterruptVector = makeUnhandledHandler("UART0"), + UART1: InterruptVector = makeUnhandledHandler("UART1"), + UART2: InterruptVector = makeUnhandledHandler("UART2"), + UART3: InterruptVector = makeUnhandledHandler("UART3"), + PWM1: InterruptVector = makeUnhandledHandler("PWM1"), + I2C0: InterruptVector = makeUnhandledHandler("I2C0"), + I2C1: InterruptVector = makeUnhandledHandler("I2C1"), + I2C2: InterruptVector = makeUnhandledHandler("I2C2"), + SPI: InterruptVector = makeUnhandledHandler("SPI"), + SSP0: InterruptVector = makeUnhandledHandler("SSP0"), + SSP1: InterruptVector = makeUnhandledHandler("SSP1"), + PLL0: InterruptVector = makeUnhandledHandler("PLL0"), + RTC: InterruptVector = makeUnhandledHandler("RTC"), + EINT0: InterruptVector = makeUnhandledHandler("EINT0"), + EINT1: InterruptVector = makeUnhandledHandler("EINT1"), + EINT2: InterruptVector = makeUnhandledHandler("EINT2"), + EINT3: InterruptVector = makeUnhandledHandler("EINT3"), + ADC: InterruptVector = makeUnhandledHandler("ADC"), + BOD: InterruptVector = makeUnhandledHandler("BOD"), + USB: InterruptVector = makeUnhandledHandler("USB"), + CAN: InterruptVector = makeUnhandledHandler("CAN"), + DMA: InterruptVector = makeUnhandledHandler("DMA"), + I2S: InterruptVector = makeUnhandledHandler("I2S"), + ENET: InterruptVector = makeUnhandledHandler("ENET"), + RIT: InterruptVector = makeUnhandledHandler("RIT"), + MCPWM: InterruptVector = makeUnhandledHandler("MCPWM"), + QEI: InterruptVector = makeUnhandledHandler("QEI"), + PLL1: InterruptVector = makeUnhandledHandler("PLL1"), + USBActivity: InterruptVector = makeUnhandledHandler("USBActivity"), + CANActivity: InterruptVector = makeUnhandledHandler("CANActivity"), +}; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; +}; + diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 8f26813..4cbe4cd 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -17770,3 +17770,273 @@ pub const USB = extern struct { padding1: u1 = 0, }); }; + +const std = @import("std"); +const root = @import("root"); +const cpu = @import("cpu"); +const config = @import("microzig-config"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler("NMI"), + HardFault: InterruptVector = makeUnhandledHandler("HardFault"), + MemManage: InterruptVector = makeUnhandledHandler("MemManage"), + BusFault: InterruptVector = makeUnhandledHandler("BusFault"), + UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler("SVCall"), + DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler("PendSV"), + SysTick: InterruptVector = makeUnhandledHandler("SysTick"), + + /// Window Watchdog interrupt + WWDG: InterruptVector = makeUnhandledHandler("WWDG"), + + /// PVD through EXTI line detection interrupt + PVD: InterruptVector = makeUnhandledHandler("PVD"), + + /// Tamper interrupt + TAMPER: InterruptVector = makeUnhandledHandler("TAMPER"), + + /// RTC global interrupt + RTC: InterruptVector = makeUnhandledHandler("RTC"), + + /// Flash global interrupt + FLASH: InterruptVector = makeUnhandledHandler("FLASH"), + + /// RCC global interrupt + RCC: InterruptVector = makeUnhandledHandler("RCC"), + + /// EXTI Line0 interrupt + EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), + + /// EXTI Line1 interrupt + EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), + + /// EXTI Line2 interrupt + EXTI2: InterruptVector = makeUnhandledHandler("EXTI2"), + + /// EXTI Line3 interrupt + EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), + + /// EXTI Line4 interrupt + EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), + + /// DMA1 Channel1 global interrupt + DMA1_Channel1: InterruptVector = makeUnhandledHandler("DMA1_Channel1"), + + /// DMA1 Channel2 global interrupt + DMA1_Channel2: InterruptVector = makeUnhandledHandler("DMA1_Channel2"), + + /// DMA1 Channel3 global interrupt + DMA1_Channel3: InterruptVector = makeUnhandledHandler("DMA1_Channel3"), + + /// DMA1 Channel4 global interrupt + DMA1_Channel4: InterruptVector = makeUnhandledHandler("DMA1_Channel4"), + + /// DMA1 Channel5 global interrupt + DMA1_Channel5: InterruptVector = makeUnhandledHandler("DMA1_Channel5"), + + /// DMA1 Channel6 global interrupt + DMA1_Channel6: InterruptVector = makeUnhandledHandler("DMA1_Channel6"), + + /// DMA1 Channel7 global interrupt + DMA1_Channel7: InterruptVector = makeUnhandledHandler("DMA1_Channel7"), + + /// ADC1 global interrupt; ADC2 global interrupt + ADC: InterruptVector = makeUnhandledHandler("ADC"), + + /// CAN1 TX interrupts + CAN1_TX: InterruptVector = makeUnhandledHandler("CAN1_TX"), + + /// CAN1 RX0 interrupts + CAN1_RX0: InterruptVector = makeUnhandledHandler("CAN1_RX0"), + + /// CAN1 RX1 interrupt + CAN1_RX1: InterruptVector = makeUnhandledHandler("CAN1_RX1"), + + /// CAN1 SCE interrupt + CAN1_SCE: InterruptVector = makeUnhandledHandler("CAN1_SCE"), + + /// EXTI Line[9:5] interrupts + EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), + + /// TIM1 Break interrupt and TIM9 global interrupt + TIM1_BRK_TIM9: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM9"), + + /// TIM1 Update interrupt and TIM10 global interrupt + TIM1_UP_TIM10: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM10"), + + /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt + TIM1_TRG_COM_TIM11: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM11"), + + /// TIM1 Capture Compare interrupt + TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), + + /// TIM2 global interrupt + TIM2: InterruptVector = makeUnhandledHandler("TIM2"), + + /// TIM3 global interrupt + TIM3: InterruptVector = makeUnhandledHandler("TIM3"), + + /// TIM4 global interrupt + TIM4: InterruptVector = makeUnhandledHandler("TIM4"), + + /// I2C1 event interrupt + I2C1_EV: InterruptVector = makeUnhandledHandler("I2C1_EV"), + + /// I2C1 error interrupt + I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), + + /// I2C2 event interrupt + I2C2_EV: InterruptVector = makeUnhandledHandler("I2C2_EV"), + + /// I2C2 error interrupt + I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), + + /// SPI1 global interrupt + SPI1: InterruptVector = makeUnhandledHandler("SPI1"), + + /// SPI2 global interrupt + SPI2: InterruptVector = makeUnhandledHandler("SPI2"), + + /// USART1 global interrupt + USART1: InterruptVector = makeUnhandledHandler("USART1"), + + /// USART2 global interrupt + USART2: InterruptVector = makeUnhandledHandler("USART2"), + + /// USART3 global interrupt + USART3: InterruptVector = makeUnhandledHandler("USART3"), + + /// EXTI Line[15:10] interrupts + EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), + + /// RTC Alarms through EXTI line interrupt + RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), + + /// USB Device FS Wakeup through EXTI line interrupt + USB_FS_WKUP: InterruptVector = makeUnhandledHandler("USB_FS_WKUP"), + + /// TIM8 Break interrupt and TIM12 global interrupt + TIM8_BRK_TIM12: InterruptVector = makeUnhandledHandler("TIM8_BRK_TIM12"), + + /// TIM8 Update interrupt and TIM13 global interrupt + TIM8_UP_TIM13: InterruptVector = makeUnhandledHandler("TIM8_UP_TIM13"), + + /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt + TIM8_TRG_COM_TIM14: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM_TIM14"), + + /// TIM8 Capture Compare interrupt + TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), + + /// ADC3 global interrupt + ADC3: InterruptVector = makeUnhandledHandler("ADC3"), + + /// FSMC global interrupt + FSMC: InterruptVector = makeUnhandledHandler("FSMC"), + + /// SDIO global interrupt + SDIO: InterruptVector = makeUnhandledHandler("SDIO"), + + /// TIM5 global interrupt + TIM5: InterruptVector = makeUnhandledHandler("TIM5"), + + /// SPI3 global interrupt + SPI3: InterruptVector = makeUnhandledHandler("SPI3"), + + /// UART4 global interrupt + UART4: InterruptVector = makeUnhandledHandler("UART4"), + + /// UART5 global interrupt + UART5: InterruptVector = makeUnhandledHandler("UART5"), + + /// TIM6 global interrupt + TIM6: InterruptVector = makeUnhandledHandler("TIM6"), + + /// TIM7 global interrupt + TIM7: InterruptVector = makeUnhandledHandler("TIM7"), + + /// DMA2 Channel1 global interrupt + DMA2_Channel1: InterruptVector = makeUnhandledHandler("DMA2_Channel1"), + + /// DMA2 Channel2 global interrupt + DMA2_Channel2: InterruptVector = makeUnhandledHandler("DMA2_Channel2"), + + /// DMA2 Channel3 global interrupt + DMA2_Channel3: InterruptVector = makeUnhandledHandler("DMA2_Channel3"), + + /// DMA2 Channel4 and DMA2 Channel5 global interrupt + DMA2_Channel4_5: InterruptVector = makeUnhandledHandler("DMA2_Channel4_5"), +}; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; +}; + diff --git a/src/modules/chips/stm32f30x/registers.zig b/src/modules/chips/stm32f303/registers.zig similarity index 85% rename from src/modules/chips/stm32f30x/registers.zig rename to src/modules/chips/stm32f303/registers.zig index ffea679..fb286b3 100644 --- a/src/modules/chips/stm32f30x/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -1,8 +1,8 @@ // generated using svd2zig.py // DO NOT EDIT -// based on STM32F30x version 1.4 +// based on STM32F303 version 1.4 const mmio = @import("microzig-mmio").mmio; -const Name = "STM32F30x"; +const Name = "STM32F303"; pub const GPIOA = extern struct { pub const Address: u32 = 0x48000000; // byte offset: 0 GPIO port mode register @@ -1755,45 +1755,45 @@ pub const GPIOF = extern struct { padding1: u1 = 0, }); }; -pub const TSC = extern struct { - pub const Address: u32 = 0x40024000; - // byte offset: 0 control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - TSCE: u1, // bit offset: 0 desc: Touch sensing controller enable - START: u1, // bit offset: 1 desc: Start a new acquisition - AM: u1, // bit offset: 2 desc: Acquisition mode - SYNCPOL: u1, // bit offset: 3 desc: Synchronization pin polarity - IODEF: u1, // bit offset: 4 desc: I/O Default mode - MCV: u3, // bit offset: 5 desc: Max count value - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PGPSC: u3, // bit offset: 12 desc: pulse generator prescaler - SSPSC: u1, // bit offset: 15 desc: Spread spectrum prescaler - SSE: u1, // bit offset: 16 desc: Spread spectrum enable - SSD: u7, // bit offset: 17 desc: Spread spectrum deviation - CTPL: u4, // bit offset: 24 desc: Charge transfer pulse low - CTPH: u4, // bit offset: 28 desc: Charge transfer pulse high +pub const GPIOG = extern struct { + pub const Address: u32 = 0x48001800; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) }); - // byte offset: 4 interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - EOAIE: u1, // bit offset: 0 desc: End of acquisition interrupt enable - MCEIE: u1, // bit offset: 1 desc: Max count error interrupt enable - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1811,24 +1811,62 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 interrupt clear register - pub const ICR = mmio(Address + 0x00000008, 32, packed struct { - EOAIC: u1, // bit offset: 0 desc: End of acquisition interrupt clear - MCEIC: u1, // bit offset: 1 desc: Max count error interrupt clear - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1846,24 +1884,24 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 interrupt status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - EOAF: u1, // bit offset: 0 desc: End of acquisition flag - MCEF: u1, // bit offset: 1 desc: Max count error flag - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1881,187 +1919,60 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 I/O hysteresis control register - pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 Schmitt trigger hysteresis mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 Schmitt trigger hysteresis mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 Schmitt trigger hysteresis mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 Schmitt trigger hysteresis mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 Schmitt trigger hysteresis mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 Schmitt trigger hysteresis mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 Schmitt trigger hysteresis mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 Schmitt trigger hysteresis mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 Schmitt trigger hysteresis mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 Schmitt trigger hysteresis mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 Schmitt trigger hysteresis mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 Schmitt trigger hysteresis mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 Schmitt trigger hysteresis mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 Schmitt trigger hysteresis mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 Schmitt trigger hysteresis mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 Schmitt trigger hysteresis mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 Schmitt trigger hysteresis mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 Schmitt trigger hysteresis mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 Schmitt trigger hysteresis mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 Schmitt trigger hysteresis mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 Schmitt trigger hysteresis mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 Schmitt trigger hysteresis mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 Schmitt trigger hysteresis mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 Schmitt trigger hysteresis mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 Schmitt trigger hysteresis mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 Schmitt trigger hysteresis mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 Schmitt trigger hysteresis mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 Schmitt trigger hysteresis mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 Schmitt trigger hysteresis mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 Schmitt trigger hysteresis mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 Schmitt trigger hysteresis mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 Schmitt trigger hysteresis mode + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) }); - // byte offset: 24 I/O analog switch control register - pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 analog switch enable - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 analog switch enable - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 analog switch enable - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 analog switch enable - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 analog switch enable - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 analog switch enable - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 analog switch enable - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 analog switch enable - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 analog switch enable - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 analog switch enable - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 analog switch enable - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 analog switch enable - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 analog switch enable - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 analog switch enable - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 analog switch enable - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 analog switch enable - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 analog switch enable - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 analog switch enable - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 analog switch enable - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 analog switch enable - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 analog switch enable - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 analog switch enable - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 analog switch enable - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 analog switch enable - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 analog switch enable - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 analog switch enable - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 analog switch enable - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 analog switch enable - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 analog switch enable - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 analog switch enable - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 analog switch enable - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 analog switch enable - }); - // byte offset: 32 I/O sampling control register - pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 sampling mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 sampling mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 sampling mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 sampling mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 sampling mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 sampling mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 sampling mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 sampling mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 sampling mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 sampling mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 sampling mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 sampling mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 sampling mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 sampling mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 sampling mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 sampling mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 sampling mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 sampling mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 sampling mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 sampling mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 sampling mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 sampling mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 sampling mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 sampling mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 sampling mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 sampling mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 sampling mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 sampling mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 sampling mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 sampling mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 sampling mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 sampling mode - }); - // byte offset: 40 I/O channel control register - pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 channel mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 channel mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 channel mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 channel mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 channel mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 channel mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 channel mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 channel mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 channel mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 channel mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 channel mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 channel mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 channel mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 channel mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 channel mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 channel mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 channel mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 channel mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 channel mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 channel mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 channel mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 channel mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 channel mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 channel mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 channel mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 channel mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 channel mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 channel mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 channel mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 channel mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 channel mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 channel mode - }); - // byte offset: 48 I/O group control status register - pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { - G1E: u1, // bit offset: 0 desc: Analog I/O group x enable - G2E: u1, // bit offset: 1 desc: Analog I/O group x enable - G3E: u1, // bit offset: 2 desc: Analog I/O group x enable - G4E: u1, // bit offset: 3 desc: Analog I/O group x enable - G5E: u1, // bit offset: 4 desc: Analog I/O group x enable - G6E: u1, // bit offset: 5 desc: Analog I/O group x enable - G7E: u1, // bit offset: 6 desc: Analog I/O group x enable - G8E: u1, // bit offset: 7 desc: Analog I/O group x enable - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - G1S: u1, // bit offset: 16 desc: Analog I/O group x status - G2S: u1, // bit offset: 17 desc: Analog I/O group x status - G3S: u1, // bit offset: 18 desc: Analog I/O group x status - G4S: u1, // bit offset: 19 desc: Analog I/O group x status - G5S: u1, // bit offset: 20 desc: Analog I/O group x status - G6S: u1, // bit offset: 21 desc: Analog I/O group x status - G7S: u1, // bit offset: 22 desc: Analog I/O group x status - G8S: u1, // bit offset: 23 desc: Analog I/O group x status - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I/O group x counter register - pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2078,11 +1989,46 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 I/O group x counter register - pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2100,11 +2046,46 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 I/O group x counter register - pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, +}; +pub const GPIOH = extern struct { + pub const Address: u32 = 0x48001c00; + // byte offset: 0 GPIO port mode register + pub const MODER = mmio(Address + 0x00000000, 32, packed struct { + MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 4 GPIO port output type register + pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { + OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 + OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 + OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 + OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 + OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 + OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 + OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 + OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 + OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 + OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 + OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 + OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 + OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 + OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 + OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 + OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2122,13 +2103,64 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 I/O group x counter register - pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, + // byte offset: 8 GPIO port output speed register + pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { + OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 12 GPIO port pull-up/pull-down register + pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { + PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) + PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) + PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) + PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) + PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) + PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) + PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) + PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) + PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) + PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) + PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) + PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) + PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) + PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) + PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) + PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) + }); + // byte offset: 16 GPIO port input data register + pub const IDR = mmio(Address + 0x00000010, 32, packed struct { + IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) + IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) + IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) + IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) + IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) + IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) + IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) + IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) + IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) + IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) + IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) + IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) + IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) + IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) + IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) + IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + padding16: u1 = 0, + padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -2144,11 +2176,24 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 I/O group x counter register - pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 20 GPIO port output data register + pub const ODR = mmio(Address + 0x00000014, 32, packed struct { + ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) + ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) + ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) + ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) + ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) + ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) + ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) + ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) + ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) + ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) + ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) + ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) + ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) + ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) + ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) + ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2166,12 +2211,60 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 I/O group x counter register - pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, + // byte offset: 24 GPIO port bit set/reset register + pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { + BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) + BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) + BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) + BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) + BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) + BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) + BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) + BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) + BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) + BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) + BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) + BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) + BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) + BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) + BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) + BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) + BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) + BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) + BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) + BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) + BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) + BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) + BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) + BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) + BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) + BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) + BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) + BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) + BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) + BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) + BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) + BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) + }); + // byte offset: 28 GPIO port configuration lock register + pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { + LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) + LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) + LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) + LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) + LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) + LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) + LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) + LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) + LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) + LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) + LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) + LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) + LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) + LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) + LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) + LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) + LCKK: u1, // bit offset: 16 desc: Lok Key padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2188,11 +2281,46 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 I/O group x counter register - pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 32 GPIO alternate function low register + pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { + AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) + }); + // byte offset: 36 GPIO alternate function high register + pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { + AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) + }); + // byte offset: 40 Port bit reset register + pub const BRR = mmio(Address + 0x00000028, 32, packed struct { + BR0: u1, // bit offset: 0 desc: Port x Reset bit y + BR1: u1, // bit offset: 1 desc: Port x Reset bit y + BR2: u1, // bit offset: 2 desc: Port x Reset bit y + BR3: u1, // bit offset: 3 desc: Port x Reset bit y + BR4: u1, // bit offset: 4 desc: Port x Reset bit y + BR5: u1, // bit offset: 5 desc: Port x Reset bit y + BR6: u1, // bit offset: 6 desc: Port x Reset bit y + BR7: u1, // bit offset: 7 desc: Port x Reset bit y + BR8: u1, // bit offset: 8 desc: Port x Reset bit y + BR9: u1, // bit offset: 9 desc: Port x Reset bit y + BR10: u1, // bit offset: 10 desc: Port x Reset bit y + BR11: u1, // bit offset: 11 desc: Port x Reset bit y + BR12: u1, // bit offset: 12 desc: Port x Reset bit y + BR13: u1, // bit offset: 13 desc: Port x Reset bit y + BR14: u1, // bit offset: 14 desc: Port x Reset bit y + BR15: u1, // bit offset: 15 desc: Port x Reset bit y padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2210,9 +2338,44 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 I/O group x counter register - pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value +}; +pub const TSC = extern struct { + pub const Address: u32 = 0x40024000; + // byte offset: 0 control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + TSCE: u1, // bit offset: 0 desc: Touch sensing controller enable + START: u1, // bit offset: 1 desc: Start a new acquisition + AM: u1, // bit offset: 2 desc: Acquisition mode + SYNCPOL: u1, // bit offset: 3 desc: Synchronization pin polarity + IODEF: u1, // bit offset: 4 desc: I/O Default mode + MCV: u3, // bit offset: 5 desc: Max count value + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PGPSC: u3, // bit offset: 12 desc: pulse generator prescaler + SSPSC: u1, // bit offset: 15 desc: Spread spectrum prescaler + SSE: u1, // bit offset: 16 desc: Spread spectrum enable + SSD: u7, // bit offset: 17 desc: Spread spectrum deviation + CTPL: u4, // bit offset: 24 desc: Charge transfer pulse low + CTPH: u4, // bit offset: 28 desc: Charge transfer pulse high + }); + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + EOAIE: u1, // bit offset: 0 desc: End of acquisition interrupt enable + MCEIE: u1, // bit offset: 1 desc: Max count error interrupt enable + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2232,16 +2395,16 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const CRC = extern struct { - pub const Address: u32 = 0x40023000; - // byte offset: 0 Data register - pub const DR = mmio(Address + 0x00000000, 32, packed struct { - DR: u32, // bit offset: 0 desc: Data register bits - }); - // byte offset: 4 Independent data register - pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - IDR: u8, // bit offset: 0 desc: General-purpose 8-bit data register bits + // byte offset: 8 interrupt clear register + pub const ICR = mmio(Address + 0x00000008, 32, packed struct { + EOAIC: u1, // bit offset: 0 desc: End of acquisition interrupt clear + MCEIC: u1, // bit offset: 1 desc: Max count error interrupt clear + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2267,15 +2430,17 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - RESET: u1, // bit offset: 0 desc: reset bit - reserved2: u1 = 0, - reserved1: u1 = 0, - POLYSIZE: u2, // bit offset: 3 desc: Polynomial size - REV_IN: u2, // bit offset: 5 desc: Reverse input data - REV_OUT: u1, // bit offset: 7 desc: Reverse output data - padding24: u1 = 0, + // byte offset: 12 interrupt status register + pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { + EOAF: u1, // bit offset: 0 desc: End of acquisition flag + MCEF: u1, // bit offset: 1 desc: Max count error flag + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -2300,31 +2465,184 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Initial CRC value - pub const INIT = mmio(Address + 0x00000010, 32, packed struct { - INIT: u32, // bit offset: 0 desc: Programmable initial CRC value + // byte offset: 16 I/O hysteresis control register + pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 Schmitt trigger hysteresis mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 Schmitt trigger hysteresis mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 Schmitt trigger hysteresis mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 Schmitt trigger hysteresis mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 Schmitt trigger hysteresis mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 Schmitt trigger hysteresis mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 Schmitt trigger hysteresis mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 Schmitt trigger hysteresis mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 Schmitt trigger hysteresis mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 Schmitt trigger hysteresis mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 Schmitt trigger hysteresis mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 Schmitt trigger hysteresis mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 Schmitt trigger hysteresis mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 Schmitt trigger hysteresis mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 Schmitt trigger hysteresis mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 Schmitt trigger hysteresis mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 Schmitt trigger hysteresis mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 Schmitt trigger hysteresis mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 Schmitt trigger hysteresis mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 Schmitt trigger hysteresis mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 Schmitt trigger hysteresis mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 Schmitt trigger hysteresis mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 Schmitt trigger hysteresis mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 Schmitt trigger hysteresis mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 Schmitt trigger hysteresis mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 Schmitt trigger hysteresis mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 Schmitt trigger hysteresis mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 Schmitt trigger hysteresis mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 Schmitt trigger hysteresis mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 Schmitt trigger hysteresis mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 Schmitt trigger hysteresis mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 Schmitt trigger hysteresis mode }); - // byte offset: 20 CRC polynomial - pub const POL = mmio(Address + 0x00000014, 32, packed struct { - POL: u32, // bit offset: 0 desc: Programmable polynomial + // byte offset: 24 I/O analog switch control register + pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 analog switch enable + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 analog switch enable + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 analog switch enable + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 analog switch enable + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 analog switch enable + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 analog switch enable + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 analog switch enable + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 analog switch enable + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 analog switch enable + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 analog switch enable + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 analog switch enable + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 analog switch enable + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 analog switch enable + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 analog switch enable + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 analog switch enable + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 analog switch enable + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 analog switch enable + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 analog switch enable + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 analog switch enable + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 analog switch enable + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 analog switch enable + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 analog switch enable + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 analog switch enable + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 analog switch enable + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 analog switch enable + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 analog switch enable + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 analog switch enable + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 analog switch enable + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 analog switch enable + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 analog switch enable + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 analog switch enable + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 analog switch enable }); -}; -pub const Flash = extern struct { - pub const Address: u32 = 0x40022000; - // byte offset: 0 Flash access control register - pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - LATENCY: u3, // bit offset: 0 desc: LATENCY + // byte offset: 32 I/O sampling control register + pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 sampling mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 sampling mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 sampling mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 sampling mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 sampling mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 sampling mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 sampling mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 sampling mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 sampling mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 sampling mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 sampling mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 sampling mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 sampling mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 sampling mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 sampling mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 sampling mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 sampling mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 sampling mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 sampling mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 sampling mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 sampling mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 sampling mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 sampling mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 sampling mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 sampling mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 sampling mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 sampling mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 sampling mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 sampling mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 sampling mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 sampling mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 sampling mode + }); + // byte offset: 40 I/O channel control register + pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { + G1_IO1: u1, // bit offset: 0 desc: G1_IO1 channel mode + G1_IO2: u1, // bit offset: 1 desc: G1_IO2 channel mode + G1_IO3: u1, // bit offset: 2 desc: G1_IO3 channel mode + G1_IO4: u1, // bit offset: 3 desc: G1_IO4 channel mode + G2_IO1: u1, // bit offset: 4 desc: G2_IO1 channel mode + G2_IO2: u1, // bit offset: 5 desc: G2_IO2 channel mode + G2_IO3: u1, // bit offset: 6 desc: G2_IO3 channel mode + G2_IO4: u1, // bit offset: 7 desc: G2_IO4 channel mode + G3_IO1: u1, // bit offset: 8 desc: G3_IO1 channel mode + G3_IO2: u1, // bit offset: 9 desc: G3_IO2 channel mode + G3_IO3: u1, // bit offset: 10 desc: G3_IO3 channel mode + G3_IO4: u1, // bit offset: 11 desc: G3_IO4 channel mode + G4_IO1: u1, // bit offset: 12 desc: G4_IO1 channel mode + G4_IO2: u1, // bit offset: 13 desc: G4_IO2 channel mode + G4_IO3: u1, // bit offset: 14 desc: G4_IO3 channel mode + G4_IO4: u1, // bit offset: 15 desc: G4_IO4 channel mode + G5_IO1: u1, // bit offset: 16 desc: G5_IO1 channel mode + G5_IO2: u1, // bit offset: 17 desc: G5_IO2 channel mode + G5_IO3: u1, // bit offset: 18 desc: G5_IO3 channel mode + G5_IO4: u1, // bit offset: 19 desc: G5_IO4 channel mode + G6_IO1: u1, // bit offset: 20 desc: G6_IO1 channel mode + G6_IO2: u1, // bit offset: 21 desc: G6_IO2 channel mode + G6_IO3: u1, // bit offset: 22 desc: G6_IO3 channel mode + G6_IO4: u1, // bit offset: 23 desc: G6_IO4 channel mode + G7_IO1: u1, // bit offset: 24 desc: G7_IO1 channel mode + G7_IO2: u1, // bit offset: 25 desc: G7_IO2 channel mode + G7_IO3: u1, // bit offset: 26 desc: G7_IO3 channel mode + G7_IO4: u1, // bit offset: 27 desc: G7_IO4 channel mode + G8_IO1: u1, // bit offset: 28 desc: G8_IO1 channel mode + G8_IO2: u1, // bit offset: 29 desc: G8_IO2 channel mode + G8_IO3: u1, // bit offset: 30 desc: G8_IO3 channel mode + G8_IO4: u1, // bit offset: 31 desc: G8_IO4 channel mode + }); + // byte offset: 48 I/O group control status register + pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { + G1E: u1, // bit offset: 0 desc: Analog I/O group x enable + G2E: u1, // bit offset: 1 desc: Analog I/O group x enable + G3E: u1, // bit offset: 2 desc: Analog I/O group x enable + G4E: u1, // bit offset: 3 desc: Analog I/O group x enable + G5E: u1, // bit offset: 4 desc: Analog I/O group x enable + G6E: u1, // bit offset: 5 desc: Analog I/O group x enable + G7E: u1, // bit offset: 6 desc: Analog I/O group x enable + G8E: u1, // bit offset: 7 desc: Analog I/O group x enable + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - PRFTBE: u1, // bit offset: 4 desc: PRFTBE - PRFTBS: u1, // bit offset: 5 desc: PRFTBS - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, + G1S: u1, // bit offset: 16 desc: Analog I/O group x status + G2S: u1, // bit offset: 17 desc: Analog I/O group x status + G3S: u1, // bit offset: 18 desc: Analog I/O group x status + G4S: u1, // bit offset: 19 desc: Analog I/O group x status + G5S: u1, // bit offset: 20 desc: Analog I/O group x status + G6S: u1, // bit offset: 21 desc: Analog I/O group x status + G7S: u1, // bit offset: 22 desc: Analog I/O group x status + G8S: u1, // bit offset: 23 desc: Analog I/O group x status + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 I/O group x counter register + pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2344,30 +2662,9 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Flash key register - pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - FKEYR: u32, // bit offset: 0 desc: Flash Key - }); - // byte offset: 8 Flash option key register - pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - OPTKEYR: u32, // bit offset: 0 desc: Option byte key - }); - // byte offset: 12 Flash status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - BSY: u1, // bit offset: 0 desc: Busy - reserved1: u1 = 0, - PGERR: u1, // bit offset: 2 desc: Programming error - reserved2: u1 = 0, - WRPRT: u1, // bit offset: 4 desc: Write protection error - EOP: u1, // bit offset: 5 desc: End of operation - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, + // byte offset: 56 I/O group x counter register + pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2387,22 +2684,9 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Flash control register - pub const CR = mmio(Address + 0x00000010, 32, packed struct { - PG: u1, // bit offset: 0 desc: Programming - PER: u1, // bit offset: 1 desc: Page erase - MER: u1, // bit offset: 2 desc: Mass erase - reserved1: u1 = 0, - OPTPG: u1, // bit offset: 4 desc: Option byte programming - OPTER: u1, // bit offset: 5 desc: Option byte erase - STRT: u1, // bit offset: 6 desc: Start - LOCK: u1, // bit offset: 7 desc: Lock - reserved2: u1 = 0, - OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable - ERRIE: u1, // bit offset: 10 desc: Error interrupt enable - reserved3: u1 = 0, - EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable - FORCE_OPTLOAD: u1, // bit offset: 13 desc: Force option byte loading + // byte offset: 60 I/O group x counter register + pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2422,55 +2706,21 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Flash address register - pub const AR = mmio(Address + 0x00000014, 32, packed struct { - FAR: u32, // bit offset: 0 desc: Flash address - }); - // byte offset: 28 Option byte register - pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - OPTERR: u1, // bit offset: 0 desc: Option byte error - LEVEL1_PROT: u1, // bit offset: 1 desc: Level 1 protection status - LEVEL2_PROT: u1, // bit offset: 2 desc: Level 2 protection status - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - WDG_SW: u1, // bit offset: 8 desc: WDG_SW - nRST_STOP: u1, // bit offset: 9 desc: nRST_STOP - nRST_STDBY: u1, // bit offset: 10 desc: nRST_STDBY - reserved6: u1 = 0, - BOOT1: u1, // bit offset: 12 desc: BOOT1 - VDDA_MONITOR: u1, // bit offset: 13 desc: VDDA_MONITOR - SRAM_PARITY_CHECK: u1, // bit offset: 14 desc: SRAM_PARITY_CHECK - reserved7: u1 = 0, - Data0: u8, // bit offset: 16 desc: Data0 - Data1: u8, // bit offset: 24 desc: Data1 - }); - // byte offset: 32 Write protection register - pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - WRP: u32, // bit offset: 0 desc: Write protect - }); -}; -pub const RCC = extern struct { - pub const Address: u32 = 0x40021000; - // byte offset: 0 Clock control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable - HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag - reserved1: u1 = 0, - HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming - HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration - HSEON: u1, // bit offset: 16 desc: External High Speed clock enable - HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag - HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass - CSSON: u1, // bit offset: 19 desc: Clock Security System enable - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - PLLON: u1, // bit offset: 24 desc: PLL enable - PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + // byte offset: 64 I/O group x counter register + pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -2478,53 +2728,19 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Clock configuration register (RCC_CFGR) - pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - SW: u2, // bit offset: 0 desc: System clock Switch - SWS: u2, // bit offset: 2 desc: System Clock Switch Status - HPRE: u4, // bit offset: 4 desc: AHB prescaler - PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) - PPRE2: u3, // bit offset: 11 desc: APB high speed prescaler (APB2) - reserved2: u1 = 0, - reserved1: u1 = 0, - PLLSRC: u1, // bit offset: 16 desc: PLL entry clock source - PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry - PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor - USBPRES: u1, // bit offset: 22 desc: USB prescaler - I2SSRC: u1, // bit offset: 23 desc: I2S external clock source selection - MCO: u3, // bit offset: 24 desc: Microcontroller clock output - reserved3: u1 = 0, - MCOF: u1, // bit offset: 28 desc: Microcontroller Clock Output Flag - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Clock interrupt register (RCC_CIR) - pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag - LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag - HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag - HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag - PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag - reserved2: u1 = 0, - reserved1: u1 = 0, - CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag - LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable - LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable - HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable - HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable - PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear - LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear - HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear - HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear - PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear - reserved7: u1 = 0, - reserved6: u1 = 0, - CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + // byte offset: 68 I/O group x counter register + pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -2534,27 +2750,14 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) - pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - SYSCFGRST: u1, // bit offset: 0 desc: SYSCFG and COMP reset - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset - SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset - TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset - USART1RST: u1, // bit offset: 14 desc: USART1 reset - reserved11: u1 = 0, - TIM15RST: u1, // bit offset: 16 desc: TIM15 timer reset - TIM16RST: u1, // bit offset: 17 desc: TIM16 timer reset - TIM17RST: u1, // bit offset: 18 desc: TIM17 timer reset + // byte offset: 72 I/O group x counter register + pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2569,97 +2772,14 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) - pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset - TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset - TIM4RST: u1, // bit offset: 2 desc: Timer 14 reset - reserved1: u1 = 0, - TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset - TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset - reserved8: u1 = 0, - reserved7: u1 = 0, - SPI2RST: u1, // bit offset: 14 desc: SPI2 reset - SPI3RST: u1, // bit offset: 15 desc: SPI3 reset - reserved9: u1 = 0, - USART2RST: u1, // bit offset: 17 desc: USART 2 reset - USART3RST: u1, // bit offset: 18 desc: USART3 reset - UART4RST: u1, // bit offset: 19 desc: UART 4 reset - UART5RST: u1, // bit offset: 20 desc: UART 5 reset - I2C1RST: u1, // bit offset: 21 desc: I2C1 reset - I2C2RST: u1, // bit offset: 22 desc: I2C2 reset - USBRST: u1, // bit offset: 23 desc: USB reset - reserved10: u1 = 0, - CANRST: u1, // bit offset: 25 desc: CAN reset - reserved12: u1 = 0, - reserved11: u1 = 0, - PWRRST: u1, // bit offset: 28 desc: Power interface reset - DACRST: u1, // bit offset: 29 desc: DAC interface reset - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) - pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMA1 clock enable - DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable - SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable - reserved1: u1 = 0, - FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable - reserved2: u1 = 0, - CRCEN: u1, // bit offset: 6 desc: CRC clock enable - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - IOPAEN: u1, // bit offset: 17 desc: I/O port A clock enable - IOPBEN: u1, // bit offset: 18 desc: I/O port B clock enable - IOPCEN: u1, // bit offset: 19 desc: I/O port C clock enable - IOPDEN: u1, // bit offset: 20 desc: I/O port D clock enable - IOPEEN: u1, // bit offset: 21 desc: I/O port E clock enable - IOPFEN: u1, // bit offset: 22 desc: I/O port F clock enable - reserved13: u1 = 0, - TSCEN: u1, // bit offset: 24 desc: Touch sensing controller clock enable - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - ADC12EN: u1, // bit offset: 28 desc: ADC1 and ADC2 clock enable - ADC34EN: u1, // bit offset: 29 desc: ADC3 and ADC4 clock enable - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) - pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - SYSCFGEN: u1, // bit offset: 0 desc: SYSCFG clock enable - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable - SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable - TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable - USART1EN: u1, // bit offset: 14 desc: USART1 clock enable - reserved11: u1 = 0, - TIM15EN: u1, // bit offset: 16 desc: TIM15 timer clock enable - TIM16EN: u1, // bit offset: 17 desc: TIM16 timer clock enable - TIM17EN: u1, // bit offset: 18 desc: TIM17 timer clock enable + // byte offset: 76 I/O group x counter register + pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2674,58 +2794,12 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) - pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable - TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable - TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable - reserved1: u1 = 0, - TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable - TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable - reserved8: u1 = 0, - reserved7: u1 = 0, - SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable - SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable - reserved9: u1 = 0, - USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable - I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable - USBEN: u1, // bit offset: 23 desc: USB clock enable - reserved13: u1 = 0, - CANEN: u1, // bit offset: 25 desc: CAN clock enable - reserved15: u1 = 0, - reserved14: u1 = 0, - PWREN: u1, // bit offset: 28 desc: Power interface clock enable - DACEN: u1, // bit offset: 29 desc: DAC interface clock enable - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Backup domain control register (RCC_BDCR) - pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable - LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready - LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass - LSEDRV: u2, // bit offset: 3 desc: LSE oscillator drive capability - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RTCEN: u1, // bit offset: 15 desc: RTC clock enable - BDRST: u1, // bit offset: 16 desc: Backup domain software reset + // byte offset: 80 I/O group x counter register + pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { + CNT: u14, // bit offset: 0 desc: Counter value + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2742,81 +2816,22 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Control/status register (RCC_CSR) - pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable - LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RMVF: u1, // bit offset: 24 desc: Remove reset flag - OBLRSTF: u1, // bit offset: 25 desc: Option byte loader reset flag - PINRSTF: u1, // bit offset: 26 desc: PIN reset flag - PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag - SFTRSTF: u1, // bit offset: 28 desc: Software reset flag - IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag - WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag - LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag - }); - // byte offset: 40 AHB peripheral reset register - pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - IOPARST: u1, // bit offset: 17 desc: I/O port A reset - IOPBRST: u1, // bit offset: 18 desc: I/O port B reset - IOPCRST: u1, // bit offset: 19 desc: I/O port C reset - IOPDRST: u1, // bit offset: 20 desc: I/O port D reset - IOPERST: u1, // bit offset: 21 desc: I/O port E reset - IOPFRST: u1, // bit offset: 22 desc: I/O port F reset - reserved18: u1 = 0, - TSCRST: u1, // bit offset: 24 desc: Touch sensing controller reset - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - ADC12RST: u1, // bit offset: 28 desc: ADC1 and ADC2 reset - ADC34RST: u1, // bit offset: 29 desc: ADC3 and ADC4 reset - padding2: u1 = 0, - padding1: u1 = 0, +}; +pub const CRC = extern struct { + pub const Address: u32 = 0x40023000; + // byte offset: 0 Data register + pub const DR = mmio(Address + 0x00000000, 32, packed struct { + DR: u32, // bit offset: 0 desc: Data register bits }); - // byte offset: 44 Clock configuration register 2 - pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { - PREDIV: u4, // bit offset: 0 desc: PREDIV division factor - ADC12PRES: u5, // bit offset: 4 desc: ADC1 and ADC2 prescaler - ADC34PRES: u5, // bit offset: 9 desc: ADC3 and ADC4 prescaler + // byte offset: 4 Independent data register + pub const IDR = mmio(Address + 0x00000004, 32, packed struct { + IDR: u8, // bit offset: 0 desc: General-purpose 8-bit data register bits + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2836,27 +2851,30 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 Clock configuration register 3 - pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { - USART1SW: u2, // bit offset: 0 desc: USART1 clock source selection + // byte offset: 8 Control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + RESET: u1, // bit offset: 0 desc: reset bit reserved2: u1 = 0, reserved1: u1 = 0, - I2C1SW: u1, // bit offset: 4 desc: I2C1 clock source selection - I2C2SW: u1, // bit offset: 5 desc: I2C2 clock source selection - reserved4: u1 = 0, - reserved3: u1 = 0, - TIM1SW: u1, // bit offset: 8 desc: Timer1 clock source selection - TIM8SW: u1, // bit offset: 9 desc: Timer8 clock source selection - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - USART2SW: u2, // bit offset: 16 desc: USART2 clock source selection - USART3SW: u2, // bit offset: 18 desc: USART3 clock source selection - UART4SW: u2, // bit offset: 20 desc: UART4 clock source selection - UART5SW: u2, // bit offset: 22 desc: UART5 clock source selection + POLYSIZE: u2, // bit offset: 3 desc: Polynomial size + REV_IN: u2, // bit offset: 5 desc: Reverse input data + REV_OUT: u1, // bit offset: 7 desc: Reverse output data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -2866,93 +2884,75 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 16 Initial CRC value + pub const INIT = mmio(Address + 0x00000010, 32, packed struct { + INIT: u32, // bit offset: 0 desc: Programmable initial CRC value + }); + // byte offset: 20 CRC polynomial + pub const POL = mmio(Address + 0x00000014, 32, packed struct { + POL: u32, // bit offset: 0 desc: Programmable polynomial + }); }; -pub const DMA1 = extern struct { - pub const Address: u32 = 0x40020000; - // byte offset: 0 DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag +pub const Flash = extern struct { + pub const Address: u32 = 0x40022000; + // byte offset: 0 Flash access control register + pub const ACR = mmio(Address + 0x00000000, 32, packed struct { + LATENCY: u3, // bit offset: 0 desc: LATENCY + reserved1: u1 = 0, + PRFTBE: u1, // bit offset: 4 desc: PRFTBE + PRFTBS: u1, // bit offset: 5 desc: PRFTBS + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 4 Flash key register + pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { + FKEYR: u32, // bit offset: 0 desc: Flash Key }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + // byte offset: 8 Flash option key register + pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { + OPTKEYR: u32, // bit offset: 0 desc: Option byte key + }); + // byte offset: 12 Flash status register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + BSY: u1, // bit offset: 0 desc: Busy + reserved1: u1 = 0, + PGERR: u1, // bit offset: 2 desc: Programming error + reserved2: u1 = 0, + WRPRT: u1, // bit offset: 4 desc: Write protection error + EOP: u1, // bit offset: 5 desc: End of operation + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -2971,9 +2971,24 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + // byte offset: 16 Flash control register + pub const CR = mmio(Address + 0x00000010, 32, packed struct { + PG: u1, // bit offset: 0 desc: Programming + PER: u1, // bit offset: 1 desc: Page erase + MER: u1, // bit offset: 2 desc: Mass erase + reserved1: u1 = 0, + OPTPG: u1, // bit offset: 4 desc: Option byte programming + OPTER: u1, // bit offset: 5 desc: Option byte erase + STRT: u1, // bit offset: 6 desc: Start + LOCK: u1, // bit offset: 7 desc: Lock + reserved2: u1 = 0, + OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable + ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + reserved3: u1 = 0, + EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable + FORCE_OPTLOAD: u1, // bit offset: 13 desc: Force option byte loading + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2991,37 +3006,108 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + // byte offset: 20 Flash address register + pub const AR = mmio(Address + 0x00000014, 32, packed struct { + FAR: u32, // bit offset: 0 desc: Flash address }); - // byte offset: 20 DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + // byte offset: 28 Option byte register + pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { + OPTERR: u1, // bit offset: 0 desc: Option byte error + LEVEL1_PROT: u1, // bit offset: 1 desc: Level 1 protection status + LEVEL2_PROT: u1, // bit offset: 2 desc: Level 2 protection status + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + WDG_SW: u1, // bit offset: 8 desc: WDG_SW + nRST_STOP: u1, // bit offset: 9 desc: nRST_STOP + nRST_STDBY: u1, // bit offset: 10 desc: nRST_STDBY + reserved6: u1 = 0, + BOOT1: u1, // bit offset: 12 desc: BOOT1 + VDDA_MONITOR: u1, // bit offset: 13 desc: VDDA_MONITOR + SRAM_PARITY_CHECK: u1, // bit offset: 14 desc: SRAM_PARITY_CHECK + reserved7: u1 = 0, + Data0: u8, // bit offset: 16 desc: Data0 + Data1: u8, // bit offset: 24 desc: Data1 }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 32 Write protection register + pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { + WRP: u32, // bit offset: 0 desc: Write protect + }); +}; +pub const RCC = extern struct { + pub const Address: u32 = 0x40021000; + // byte offset: 0 Clock control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable + HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag + reserved1: u1 = 0, + HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming + HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration + HSEON: u1, // bit offset: 16 desc: External High Speed clock enable + HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag + HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass + CSSON: u1, // bit offset: 19 desc: Clock Security System enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + PLLON: u1, // bit offset: 24 desc: PLL enable + PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Clock configuration register (RCC_CFGR) + pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { + SW: u2, // bit offset: 0 desc: System clock Switch + SWS: u2, // bit offset: 2 desc: System Clock Switch Status + HPRE: u4, // bit offset: 4 desc: AHB prescaler + PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) + PPRE2: u3, // bit offset: 11 desc: APB high speed prescaler (APB2) + reserved1: u1 = 0, + PLLSRC: u2, // bit offset: 15 desc: PLL entry clock source + PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry + PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor + USBPRES: u1, // bit offset: 22 desc: USB prescaler + I2SSRC: u1, // bit offset: 23 desc: I2S external clock source selection + MCO: u3, // bit offset: 24 desc: Microcontroller clock output + reserved2: u1 = 0, + MCOF: u1, // bit offset: 28 desc: Microcontroller Clock Output Flag + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Clock interrupt register (RCC_CIR) + pub const CIR = mmio(Address + 0x00000008, 32, packed struct { + LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag + LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag + HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag + HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag + PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag + reserved2: u1 = 0, + reserved1: u1 = 0, + CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag + LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable + LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable + HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable + HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable + PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear + LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear + HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear + HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear + PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + reserved7: u1 = 0, + reserved6: u1 = 0, + CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3031,12 +3117,27 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { + SYSCFGRST: u1, // bit offset: 0 desc: SYSCFG and COMP reset + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset + SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset + TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset + USART1RST: u1, // bit offset: 14 desc: USART1 reset + reserved11: u1 = 0, + TIM15RST: u1, // bit offset: 16 desc: TIM15 timer reset + TIM16RST: u1, // bit offset: 17 desc: TIM16 timer reset + TIM17RST: u1, // bit offset: 18 desc: TIM17 timer reset padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3051,32 +3152,97 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address - }); - // byte offset: 40 DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address - }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { + TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset + TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset + TIM4RST: u1, // bit offset: 2 desc: Timer 14 reset + reserved1: u1 = 0, + TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset + TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + reserved8: u1 = 0, + reserved7: u1 = 0, + SPI2RST: u1, // bit offset: 14 desc: SPI2 reset + SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + reserved9: u1 = 0, + USART2RST: u1, // bit offset: 17 desc: USART 2 reset + USART3RST: u1, // bit offset: 18 desc: USART3 reset + UART4RST: u1, // bit offset: 19 desc: UART 4 reset + UART5RST: u1, // bit offset: 20 desc: UART 5 reset + I2C1RST: u1, // bit offset: 21 desc: I2C1 reset + I2C2RST: u1, // bit offset: 22 desc: I2C2 reset + USBRST: u1, // bit offset: 23 desc: USB reset + reserved10: u1 = 0, + CANRST: u1, // bit offset: 25 desc: CAN reset + reserved12: u1 = 0, + reserved11: u1 = 0, + PWRRST: u1, // bit offset: 28 desc: Power interface reset + DACRST: u1, // bit offset: 29 desc: DAC interface reset + I2C3RST: u1, // bit offset: 30 desc: I2C3 reset + padding1: u1 = 0, + }); + // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMA1 clock enable + DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable + SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable + reserved1: u1 = 0, + FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable + FMCEN: u1, // bit offset: 5 desc: FMC clock enable + CRCEN: u1, // bit offset: 6 desc: CRC clock enable + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + IOPHEN: u1, // bit offset: 16 desc: IO port H clock enable + IOPAEN: u1, // bit offset: 17 desc: I/O port A clock enable + IOPBEN: u1, // bit offset: 18 desc: I/O port B clock enable + IOPCEN: u1, // bit offset: 19 desc: I/O port C clock enable + IOPDEN: u1, // bit offset: 20 desc: I/O port D clock enable + IOPEEN: u1, // bit offset: 21 desc: I/O port E clock enable + IOPFEN: u1, // bit offset: 22 desc: I/O port F clock enable + IOPGEN: u1, // bit offset: 23 desc: I/O port G clock enable + TSCEN: u1, // bit offset: 24 desc: Touch sensing controller clock enable + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + ADC12EN: u1, // bit offset: 28 desc: ADC1 and ADC2 clock enable + ADC34EN: u1, // bit offset: 29 desc: ADC3 and ADC4 clock enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { + SYSCFGEN: u1, // bit offset: 0 desc: SYSCFG clock enable + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable + SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable + TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable + USART1EN: u1, // bit offset: 14 desc: USART1 clock enable + reserved11: u1 = 0, + TIM15EN: u1, // bit offset: 16 desc: TIM15 timer clock enable + TIM16EN: u1, // bit offset: 17 desc: TIM16 timer clock enable + TIM17EN: u1, // bit offset: 18 desc: TIM17 timer clock enable padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3091,10 +3257,58 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, + // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { + TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable + TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable + TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable + reserved1: u1 = 0, + TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable + TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + reserved8: u1 = 0, + reserved7: u1 = 0, + SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable + SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + reserved9: u1 = 0, + USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable + USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable + USART4EN: u1, // bit offset: 19 desc: USART 4 clock enable + USART5EN: u1, // bit offset: 20 desc: USART 5 clock enable + I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable + I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable + USBEN: u1, // bit offset: 23 desc: USB clock enable + reserved10: u1 = 0, + CANEN: u1, // bit offset: 25 desc: CAN clock enable + DAC2EN: u1, // bit offset: 26 desc: DAC2 interface clock enable + reserved11: u1 = 0, + PWREN: u1, // bit offset: 28 desc: Power interface clock enable + DACEN: u1, // bit offset: 29 desc: DAC interface clock enable + I2C3EN: u1, // bit offset: 30 desc: I2C3 clock enable + padding1: u1 = 0, + }); + // byte offset: 32 Backup domain control register (RCC_BDCR) + pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { + LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable + LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready + LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass + LSEDRV: u2, // bit offset: 3 desc: LSE oscillator drive capability + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + RTCEN: u1, // bit offset: 15 desc: RTC clock enable + BDRST: u1, // bit offset: 16 desc: Backup domain software reset padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -3111,28 +3325,82 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + // byte offset: 36 Control/status register (RCC_CSR) + pub const CSR = mmio(Address + 0x00000024, 32, packed struct { + LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable + LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RMVF: u1, // bit offset: 24 desc: Remove reset flag + OBLRSTF: u1, // bit offset: 25 desc: Option byte loader reset flag + PINRSTF: u1, // bit offset: 26 desc: PIN reset flag + PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag + SFTRSTF: u1, // bit offset: 28 desc: Software reset flag + IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag + WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag + LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag }); - // byte offset: 60 DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + // byte offset: 40 AHB peripheral reset register + pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMCRST: u1, // bit offset: 5 desc: FMC reset + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + IOPHRST: u1, // bit offset: 16 desc: I/O port H reset + IOPARST: u1, // bit offset: 17 desc: I/O port A reset + IOPBRST: u1, // bit offset: 18 desc: I/O port B reset + IOPCRST: u1, // bit offset: 19 desc: I/O port C reset + IOPDRST: u1, // bit offset: 20 desc: I/O port D reset + IOPERST: u1, // bit offset: 21 desc: I/O port E reset + IOPFRST: u1, // bit offset: 22 desc: I/O port F reset + IOPGRST: u1, // bit offset: 23 desc: Touch sensing controller reset + TSCRST: u1, // bit offset: 24 desc: Touch sensing controller reset + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + ADC12RST: u1, // bit offset: 28 desc: ADC1 and ADC2 reset + ADC34RST: u1, // bit offset: 29 desc: ADC3 and ADC4 reset + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + // byte offset: 44 Clock configuration register 2 + pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { + PREDIV: u4, // bit offset: 0 desc: PREDIV division factor + ADC12PRES: u5, // bit offset: 4 desc: ADC1 and ADC2 prescaler + ADC34PRES: u5, // bit offset: 9 desc: ADC3 and ADC4 prescaler + padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3151,197 +3419,27 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address - }); - // byte offset: 80 DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address - }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 96 DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address - }); - // byte offset: 100 DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address - }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address - }); - // byte offset: 120 DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address - }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 132 DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 48 Clock configuration register 3 + pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { + USART1SW: u2, // bit offset: 0 desc: USART1 clock source selection + reserved2: u1 = 0, + reserved1: u1 = 0, + I2C1SW: u1, // bit offset: 4 desc: I2C1 clock source selection + I2C2SW: u1, // bit offset: 5 desc: I2C2 clock source selection + I2C3SW: u1, // bit offset: 6 desc: I2C3 clock source selection + reserved3: u1 = 0, + TIM1SW: u1, // bit offset: 8 desc: Timer1 clock source selection + TIM8SW: u1, // bit offset: 9 desc: Timer8 clock source selection + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + USART2SW: u2, // bit offset: 16 desc: USART2 clock source selection + USART3SW: u2, // bit offset: 18 desc: USART3 clock source selection + UART4SW: u2, // bit offset: 20 desc: UART4 clock source selection + UART5SW: u2, // bit offset: 22 desc: UART5 clock source selection padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3351,17 +3449,9 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address - }); - // byte offset: 140 DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address - }); }; -pub const DMA2 = extern struct { - pub const Address: u32 = 0x40020400; +pub const DMA1 = extern struct { + pub const Address: u32 = 0x40020000; // byte offset: 0 DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag @@ -3853,56 +3943,92 @@ pub const DMA2 = extern struct { MA: u32, // bit offset: 0 desc: Memory address }); }; -pub const TIM2 = extern struct { - pub const Address: u32 = 0x40000000; - // byte offset: 0 control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, +pub const DMA2 = extern struct { + pub const Address: u32 = 0x40020400; + // byte offset: 0 DMA interrupt status register (DMA_ISR) + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag + TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag + HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag + TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag + GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag + TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag + HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag + TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag + GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag + TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag + HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag + TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag + GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag + TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag + HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag + TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag + GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag + TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag + HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag + TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag + GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag + TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag + HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag + TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag + GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag + TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag + HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag + TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { + CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear + CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear + CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear + CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear + CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear + CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear + CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear + CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear + CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear + CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear + CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear + CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear + CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear + CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear + CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear + CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear + CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear + CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear + CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear + CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear + CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear + CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear + CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear + CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear + CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear + CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear + CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear + CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3921,17 +4047,10 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + // byte offset: 12 DMA channel 1 number of data register + pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -3948,23 +4067,28 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + // byte offset: 16 DMA channel 1 peripheral address register + pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 20 DMA channel 1 memory address register + pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 28 DMA channel configuration register (DMA_CCR) + pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3983,24 +4107,9 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - reserved3: u1 = 0, - reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 32 DMA channel 2 number of data register + pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4018,23 +4127,28 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, + // byte offset: 36 DMA channel 2 peripheral address register + pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 40 DMA channel 2 memory address register + pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 48 DMA channel configuration register (DMA_CCR) + pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4053,43 +4167,9 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + // byte offset: 52 DMA channel 3 number of data register + pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4107,27 +4187,38 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + // byte offset: 56 DMA channel 3 peripheral address register + pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 60 DMA channel 3 memory address register + pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 68 DMA channel configuration register (DMA_CCR) + pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -4136,14 +4227,9 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + // byte offset: 72 DMA channel 4 number of data register + pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4161,24 +4247,29 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + // byte offset: 76 DMA channel 4 peripheral address register + pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 80 DMA channel 4 memory address register + pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 88 DMA channel configuration register (DMA_CCR) + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4196,15 +4287,9 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access - }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + // byte offset: 92 DMA channel 5 number of data register + pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4222,40 +4307,88 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + // byte offset: 96 DMA channel 5 peripheral address register + pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address }); - // byte offset: 52 capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + // byte offset: 100 DMA channel 5 memory address register + pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address }); - // byte offset: 56 capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + // byte offset: 108 DMA channel configuration register (DMA_CCR) + pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + // byte offset: 112 DMA channel 6 number of data register + pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + // byte offset: 116 DMA channel 6 peripheral address register + pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address }); - // byte offset: 72 DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length - padding19: u1 = 0, - padding18: u1 = 0, + // byte offset: 120 DMA channel 6 memory address register + pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); + // byte offset: 128 DMA channel configuration register (DMA_CCR) + pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { + EN: u1, // bit offset: 0 desc: Channel enable + TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable + HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable + TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable + DIR: u1, // bit offset: 4 desc: Data transfer direction + CIRC: u1, // bit offset: 5 desc: Circular mode + PINC: u1, // bit offset: 6 desc: Peripheral increment mode + MINC: u1, // bit offset: 7 desc: Memory increment mode + PSIZE: u2, // bit offset: 8 desc: Peripheral size + MSIZE: u2, // bit offset: 10 desc: Memory size + PL: u2, // bit offset: 12 desc: Channel Priority level + MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4274,9 +4407,9 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + // byte offset: 132 DMA channel 7 number of data register + pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { + NDT: u16, // bit offset: 0 desc: Number of data to transfer padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4294,9 +4427,17 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 136 DMA channel 7 peripheral address register + pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { + PA: u32, // bit offset: 0 desc: Peripheral address + }); + // byte offset: 140 DMA channel 7 memory address register + pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { + MA: u32, // bit offset: 0 desc: Memory address + }); }; -pub const TIM3 = extern struct { - pub const Address: u32 = 0x40000400; +pub const TIM2 = extern struct { + pub const Address: u32 = 0x40000000; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable @@ -4737,8 +4878,8 @@ pub const TIM3 = extern struct { padding1: u1 = 0, }); }; -pub const TIM4 = extern struct { - pub const Address: u32 = 0x40000800; +pub const TIM3 = extern struct { + pub const Address: u32 = 0x40000400; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable @@ -5179,20 +5320,19 @@ pub const TIM4 = extern struct { padding1: u1 = 0, }); }; -pub const TIM15 = extern struct { - pub const Address: u32 = 0x40014000; +pub const TIM4 = extern struct { + pub const Address: u32 = 0x40000800; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable UDIS: u1, // bit offset: 1 desc: Update disable URS: u1, // bit offset: 2 desc: Update request source OPM: u1, // bit offset: 3 desc: One-pulse mode - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable CKD: u2, // bit offset: 8 desc: Clock division - reserved4: u1 = 0, + reserved1: u1 = 0, UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping padding20: u1 = 0, padding19: u1 = 0, @@ -5217,15 +5357,15 @@ pub const TIM15 = extern struct { }); // byte offset: 4 control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection MMS: u3, // bit offset: 4 desc: Master mode selection TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5251,18 +5391,14 @@ pub const TIM15 = extern struct { // byte offset: 8 slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { SMS: u3, // bit offset: 0 desc: Slave mode selection - reserved1: u1 = 0, + OCCS: u1, // bit offset: 3 desc: OCREF clear selection TS: u3, // bit offset: 4 desc: Trigger selection MSM: u1, // bit offset: 7 desc: Master/Slave mode - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -5284,17 +5420,17 @@ pub const TIM15 = extern struct { UIE: u1, // bit offset: 0 desc: Update interrupt enable CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - reserved2: u1 = 0, + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable + reserved2: u1 = 0, UDE: u1, // bit offset: 8 desc: Update DMA request enable CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - reserved4: u1 = 0, + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable reserved3: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable TDE: u1, // bit offset: 14 desc: Trigger DMA request enable padding17: u1 = 0, padding16: u1 = 0, @@ -5319,16 +5455,16 @@ pub const TIM15 = extern struct { UIF: u1, // bit offset: 0 desc: Update interrupt flag CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - reserved2: u1 = 0, + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag reserved3: u1 = 0, + reserved2: u1 = 0, CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - padding21: u1 = 0, - padding20: u1 = 0, + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5354,11 +5490,11 @@ pub const TIM15 = extern struct { UG: u1, // bit offset: 0 desc: Update generation CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - reserved2: u1 = 0, + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5384,27 +5520,27 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + // byte offset: 24 capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - reserved1: u1 = 0, + OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - reserved2: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 - reserved9: u1 = 0, - reserved8: u1 = 0, + OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5418,7 +5554,7 @@ pub const TIM15 = extern struct { CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler IC2F: u4, // bit offset: 12 desc: Input capture 2 filter padding16: u1 = 0, @@ -5438,52 +5574,19 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved1: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, + // byte offset: 28 capture/compare mode register 2 (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5491,20 +5594,7 @@ pub const TIM15 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy - }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5513,9 +5603,14 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5533,17 +5628,24 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + reserved1: u1 = 0, + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved2: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + reserved3: u1 = 0, + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved4: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5561,9 +5663,15 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNTL: u16, // bit offset: 0 desc: Low counter value + CNTH: u15, // bit offset: 16 desc: High counter value + CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5581,49 +5689,30 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARRL: u16, // bit offset: 0 desc: Low Auto-reload value + ARRH: u16, // bit offset: 16 desc: High Auto-reload value + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value + CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + }); // byte offset: 56 capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value + CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) }); - // byte offset: 68 break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value + CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) }); // byte offset: 72 DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { @@ -5673,8 +5762,8 @@ pub const TIM15 = extern struct { padding1: u1 = 0, }); }; -pub const TIM16 = extern struct { - pub const Address: u32 = 0x40014400; +pub const TIM15 = extern struct { + pub const Address: u32 = 0x40014000; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable @@ -5715,13 +5804,11 @@ pub const TIM16 = extern struct { reserved1: u1 = 0, CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection OIS1: u1, // bit offset: 8 desc: Output Idle state 1 OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - padding22: u1 = 0, + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5744,11 +5831,42 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + reserved1: u1 = 0, + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); // byte offset: 12 DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { UIE: u1, // bit offset: 0 desc: Update interrupt enable CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - reserved3: u1 = 0, + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable reserved2: u1 = 0, reserved1: u1 = 0, COMIE: u1, // bit offset: 5 desc: COM interrupt enable @@ -5756,9 +5874,9 @@ pub const TIM16 = extern struct { BIE: u1, // bit offset: 7 desc: Break interrupt enable UDE: u1, // bit offset: 8 desc: Update DMA request enable CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - reserved6: u1 = 0, - reserved5: u1 = 0, + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable reserved4: u1 = 0, + reserved3: u1 = 0, COMDE: u1, // bit offset: 13 desc: COM DMA request enable TDE: u1, // bit offset: 14 desc: Trigger DMA request enable padding17: u1 = 0, @@ -5783,15 +5901,15 @@ pub const TIM16 = extern struct { pub const SR = mmio(Address + 0x00000010, 32, packed struct { UIF: u1, // bit offset: 0 desc: Update interrupt flag CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - reserved3: u1 = 0, + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag reserved2: u1 = 0, reserved1: u1 = 0, COMIF: u1, // bit offset: 5 desc: COM interrupt flag TIF: u1, // bit offset: 6 desc: Trigger interrupt flag BIF: u1, // bit offset: 7 desc: Break interrupt flag - reserved4: u1 = 0, + reserved3: u1 = 0, CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - padding22: u1 = 0, + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5818,7 +5936,7 @@ pub const TIM16 = extern struct { pub const EGR = mmio(Address + 0x00000014, 32, packed struct { UG: u1, // bit offset: 0 desc: Update generation CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - reserved3: u1 = 0, + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation reserved2: u1 = 0, reserved1: u1 = 0, COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation @@ -5855,6 +5973,13 @@ pub const TIM16 = extern struct { OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved1: u1 = 0, + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + reserved2: u1 = 0, + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -5862,17 +5987,7 @@ pub const TIM16 = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5886,14 +6001,9 @@ pub const TIM16 = extern struct { CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5917,10 +6027,10 @@ pub const TIM16 = extern struct { CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + reserved1: u1 = 0, + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5964,7 +6074,7 @@ pub const TIM16 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + UIFCPY: u1, // bit offset: 31 desc: UIF copy }); // byte offset: 40 prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { @@ -6054,6 +6164,26 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); // byte offset: 68 break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { DTG: u8, // bit offset: 0 desc: Dead-time generator setup @@ -6125,13 +6255,9 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 option register - pub const OR = mmio(Address + 0x00000050, 32, packed struct { - raw: u32, // placeholder field - }); }; -pub const TIM17 = extern struct { - pub const Address: u32 = 0x40014800; +pub const TIM16 = extern struct { + pub const Address: u32 = 0x40014400; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable @@ -6582,99 +6708,30 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 80 option register + pub const OR = mmio(Address + 0x00000050, 32, packed struct { + raw: u32, // placeholder field + }); }; -pub const USART1 = extern struct { - pub const Address: u32 = 0x40013800; - // byte offset: 0 Control register 1 +pub const TIM17 = extern struct { + pub const Address: u32 = 0x40014800; + // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable - reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6692,10 +6749,24 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6713,28 +6784,23 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length - }); - // byte offset: 24 Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6753,80 +6819,18 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag - reserved9: u1 = 0, - reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value - padding23: u1 = 0, + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6850,9 +6854,17 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -6877,100 +6889,22 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const USART2 = extern struct { - pub const Address: u32 = 0x40004400; - // byte offset: 0 Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable - reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV - padding16: u1 = 0, + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -6987,10 +6921,19 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7008,18 +6951,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length - }); - // byte offset: 24 Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7048,31 +6986,36 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7083,29 +7026,14 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag - reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag - reserved9: u1 = 0, - reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7118,9 +7046,10 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u8, // bit offset: 0 desc: Repetition counter value + padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7145,13 +7074,57 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7172,9 +7145,29 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); }; -pub const USART3 = extern struct { - pub const Address: u32 = 0x40004800; +pub const USART1 = extern struct { + pub const Address: u32 = 0x40013800; // byte offset: 0 Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { UE: u1, // bit offset: 0 desc: USART enable @@ -7468,8 +7461,8 @@ pub const USART3 = extern struct { padding1: u1 = 0, }); }; -pub const UART4 = extern struct { - pub const Address: u32 = 0x40004c00; +pub const USART2 = extern struct { + pub const Address: u32 = 0x40004400; // byte offset: 0 Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { UE: u1, // bit offset: 0 desc: USART enable @@ -7763,8 +7756,8 @@ pub const UART4 = extern struct { padding1: u1 = 0, }); }; -pub const UART5 = extern struct { - pub const Address: u32 = 0x40005000; +pub const USART3 = extern struct { + pub const Address: u32 = 0x40004800; // byte offset: 0 Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { UE: u1, // bit offset: 0 desc: USART enable @@ -8058,63 +8051,84 @@ pub const UART5 = extern struct { padding1: u1 = 0, }); }; -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40013000; - // byte offset: 0 control register 1 +pub const UART4 = extern struct { + pub const Address: u32 = 0x40004c00; + // byte offset: 0 Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + // byte offset: 4 Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8125,22 +8139,10 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8158,9 +8160,10 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8178,9 +8181,29 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8198,16 +8221,31 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8218,14 +8256,29 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8238,17 +8291,12 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -8270,11 +8318,10 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8299,63 +8346,84 @@ pub const SPI1 = extern struct { padding1: u1 = 0, }); }; -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40003800; - // byte offset: 0 control register 1 +pub const UART5 = extern struct { + pub const Address: u32 = 0x40005000; + // byte offset: 0 Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, + UE: u1, // bit offset: 0 desc: USART enable + UESM: u1, // bit offset: 1 desc: USART enable in Stop mode + RE: u1, // bit offset: 2 desc: Receiver enable + TE: u1, // bit offset: 3 desc: Transmitter enable + IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable + RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable + TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable + TXEIE: u1, // bit offset: 7 desc: interrupt enable + PEIE: u1, // bit offset: 8 desc: PE interrupt enable + PS: u1, // bit offset: 9 desc: Parity selection + PCE: u1, // bit offset: 10 desc: Parity control enable + WAKE: u1, // bit offset: 11 desc: Receiver wakeup method + M: u1, // bit offset: 12 desc: Word length + MME: u1, // bit offset: 13 desc: Mute mode enable + CMIE: u1, // bit offset: 14 desc: Character match interrupt enable + OVER8: u1, // bit offset: 15 desc: Oversampling mode + DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time + DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time + RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable + EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + // byte offset: 4 Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection + LBDL: u1, // bit offset: 5 desc: LIN break detection length + LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + reserved5: u1 = 0, + LBCL: u1, // bit offset: 8 desc: Last bit clock pulse + CPHA: u1, // bit offset: 9 desc: Clock phase + CPOL: u1, // bit offset: 10 desc: Clock polarity + CLKEN: u1, // bit offset: 11 desc: Clock enable + STOP: u2, // bit offset: 12 desc: STOP bits + LINEN: u1, // bit offset: 14 desc: LIN mode enable + SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins + RXINV: u1, // bit offset: 16 desc: RX pin active level inversion + TXINV: u1, // bit offset: 17 desc: TX pin active level inversion + DATAINV: u1, // bit offset: 18 desc: Binary data inversion + MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first + ABREN: u1, // bit offset: 20 desc: Auto baud rate enable + ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode + RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable + ADD0: u4, // bit offset: 24 desc: Address of the USART node + ADD4: u4, // bit offset: 28 desc: Address of the USART node + }); + // byte offset: 8 Control register 3 + pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { + EIE: u1, // bit offset: 0 desc: Error interrupt enable + IREN: u1, // bit offset: 1 desc: IrDA mode enable + IRLP: u1, // bit offset: 2 desc: IrDA low-power + HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + NACK: u1, // bit offset: 4 desc: Smartcard NACK enable + SCEN: u1, // bit offset: 5 desc: Smartcard mode enable + DMAR: u1, // bit offset: 6 desc: DMA enable receiver + DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + RTSE: u1, // bit offset: 8 desc: RTS enable + CTSE: u1, // bit offset: 9 desc: CTS enable + CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable + OVRDIS: u1, // bit offset: 12 desc: Overrun Disable + DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error + DEM: u1, // bit offset: 14 desc: Driver enable mode + DEP: u1, // bit offset: 15 desc: Driver enable polarity selection + reserved1: u1 = 0, + SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count + WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection + WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8366,22 +8434,10 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 12 Baud rate register + pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { + DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV + DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8399,9 +8455,10 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + // byte offset: 16 Guard time and prescaler register + pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { + PSC: u8, // bit offset: 0 desc: Prescaler value + GT: u8, // bit offset: 8 desc: Guard time value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8419,9 +8476,29 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + // byte offset: 20 Receiver timeout register + pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { + RTO: u24, // bit offset: 0 desc: Receiver timeout value + BLEN: u8, // bit offset: 24 desc: Block Length + }); + // byte offset: 24 Request register + pub const RQR = mmio(Address + 0x00000018, 32, packed struct { + ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request + SBKRQ: u1, // bit offset: 1 desc: Send break request + MMRQ: u1, // bit offset: 2 desc: Mute mode request + RXFRQ: u1, // bit offset: 3 desc: Receive data flush request + TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8439,16 +8516,31 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + // byte offset: 28 Interrupt & status register + pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { + PE: u1, // bit offset: 0 desc: Parity error + FE: u1, // bit offset: 1 desc: Framing error + NF: u1, // bit offset: 2 desc: Noise detected flag + ORE: u1, // bit offset: 3 desc: Overrun error + IDLE: u1, // bit offset: 4 desc: Idle line detected + RXNE: u1, // bit offset: 5 desc: Read data register not empty + TC: u1, // bit offset: 6 desc: Transmission complete + TXE: u1, // bit offset: 7 desc: Transmit data register empty + LBDF: u1, // bit offset: 8 desc: LIN break detection flag + CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag + CTS: u1, // bit offset: 10 desc: CTS flag + RTOF: u1, // bit offset: 11 desc: Receiver timeout + EOBF: u1, // bit offset: 12 desc: End of block flag + reserved1: u1 = 0, + ABRE: u1, // bit offset: 14 desc: Auto baud rate error + ABRF: u1, // bit offset: 15 desc: Auto baud rate flag + BUSY: u1, // bit offset: 16 desc: Busy flag + CMF: u1, // bit offset: 17 desc: character match flag + SBKF: u1, // bit offset: 18 desc: Send break flag + RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode + WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag + TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag + REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8459,14 +8551,29 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, + // byte offset: 32 Interrupt flag clear register + pub const ICR = mmio(Address + 0x00000020, 32, packed struct { + PECF: u1, // bit offset: 0 desc: Parity error clear flag + FECF: u1, // bit offset: 1 desc: Framing error clear flag + NCF: u1, // bit offset: 2 desc: Noise detected clear flag + ORECF: u1, // bit offset: 3 desc: Overrun error clear flag + IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag + reserved1: u1 = 0, + TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag + reserved2: u1 = 0, + LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag + CTSCF: u1, // bit offset: 9 desc: CTS clear flag + reserved3: u1 = 0, + RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag + EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + CMCF: u1, // bit offset: 17 desc: Character match clear flag + reserved9: u1 = 0, + reserved8: u1 = 0, + WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8479,17 +8586,12 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + // byte offset: 36 Receive data register + pub const RDR = mmio(Address + 0x00000024, 32, packed struct { + RDR: u9, // bit offset: 0 desc: Receive data value + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -8511,11 +8613,10 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + // byte offset: 40 Transmit data register + pub const TDR = mmio(Address + 0x00000028, 32, packed struct { + TDR: u9, // bit offset: 0 desc: Transmit data value + padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8540,8 +8641,8 @@ pub const SPI2 = extern struct { padding1: u1 = 0, }); }; -pub const SPI3 = extern struct { - pub const Address: u32 = 0x40003c00; +pub const SPI1 = extern struct { + pub const Address: u32 = 0x40013000; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CPHA: u1, // bit offset: 0 desc: Clock phase @@ -8553,7 +8654,7 @@ pub const SPI3 = extern struct { SSI: u1, // bit offset: 8 desc: Internal slave select SSM: u1, // bit offset: 9 desc: Software slave management RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format + CRCL: u1, // bit offset: 11 desc: CRC length CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode @@ -8781,8 +8882,8 @@ pub const SPI3 = extern struct { padding1: u1 = 0, }); }; -pub const I2S2ext = extern struct { - pub const Address: u32 = 0x40003400; +pub const SPI2 = extern struct { + pub const Address: u32 = 0x40003800; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CPHA: u1, // bit offset: 0 desc: Clock phase @@ -8794,7 +8895,7 @@ pub const I2S2ext = extern struct { SSI: u1, // bit offset: 8 desc: Internal slave select SSM: u1, // bit offset: 9 desc: Software slave management RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format + CRCL: u1, // bit offset: 11 desc: CRC length CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode @@ -9022,8 +9123,8 @@ pub const I2S2ext = extern struct { padding1: u1 = 0, }); }; -pub const I2S3ext = extern struct { - pub const Address: u32 = 0x40004000; +pub const SPI3 = extern struct { + pub const Address: u32 = 0x40003c00; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CPHA: u1, // bit offset: 0 desc: Clock phase @@ -9035,7 +9136,7 @@ pub const I2S3ext = extern struct { SSI: u1, // bit offset: 8 desc: Internal slave select SSM: u1, // bit offset: 9 desc: Software slave management RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format + CRCL: u1, // bit offset: 11 desc: CRC length CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode @@ -9263,236 +9364,24 @@ pub const I2S3ext = extern struct { padding1: u1 = 0, }); }; -pub const EXTI = extern struct { - pub const Address: u32 = 0x40010400; - // byte offset: 0 Interrupt mask register - pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 - MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 - MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 - MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 - MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 - MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 - MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 - MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 - MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 - MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 - MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 - MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 - MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 - MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 - MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 - MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 - MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 - MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 - MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 - MR19: u1, // bit offset: 19 desc: Interrupt Mask on line 19 - MR20: u1, // bit offset: 20 desc: Interrupt Mask on line 20 - MR21: u1, // bit offset: 21 desc: Interrupt Mask on line 21 - MR22: u1, // bit offset: 22 desc: Interrupt Mask on line 22 - MR23: u1, // bit offset: 23 desc: Interrupt Mask on line 23 - MR24: u1, // bit offset: 24 desc: Interrupt Mask on line 24 - MR25: u1, // bit offset: 25 desc: Interrupt Mask on line 25 - MR26: u1, // bit offset: 26 desc: Interrupt Mask on line 26 - MR27: u1, // bit offset: 27 desc: Interrupt Mask on line 27 - MR28: u1, // bit offset: 28 desc: Interrupt Mask on line 28 - MR29: u1, // bit offset: 29 desc: Interrupt Mask on line 29 - MR30: u1, // bit offset: 30 desc: Interrupt Mask on line 30 - MR31: u1, // bit offset: 31 desc: Interrupt Mask on line 31 - }); - // byte offset: 4 Event mask register - pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Event Mask on line 0 - MR1: u1, // bit offset: 1 desc: Event Mask on line 1 - MR2: u1, // bit offset: 2 desc: Event Mask on line 2 - MR3: u1, // bit offset: 3 desc: Event Mask on line 3 - MR4: u1, // bit offset: 4 desc: Event Mask on line 4 - MR5: u1, // bit offset: 5 desc: Event Mask on line 5 - MR6: u1, // bit offset: 6 desc: Event Mask on line 6 - MR7: u1, // bit offset: 7 desc: Event Mask on line 7 - MR8: u1, // bit offset: 8 desc: Event Mask on line 8 - MR9: u1, // bit offset: 9 desc: Event Mask on line 9 - MR10: u1, // bit offset: 10 desc: Event Mask on line 10 - MR11: u1, // bit offset: 11 desc: Event Mask on line 11 - MR12: u1, // bit offset: 12 desc: Event Mask on line 12 - MR13: u1, // bit offset: 13 desc: Event Mask on line 13 - MR14: u1, // bit offset: 14 desc: Event Mask on line 14 - MR15: u1, // bit offset: 15 desc: Event Mask on line 15 - MR16: u1, // bit offset: 16 desc: Event Mask on line 16 - MR17: u1, // bit offset: 17 desc: Event Mask on line 17 - MR18: u1, // bit offset: 18 desc: Event Mask on line 18 - MR19: u1, // bit offset: 19 desc: Event Mask on line 19 - MR20: u1, // bit offset: 20 desc: Event Mask on line 20 - MR21: u1, // bit offset: 21 desc: Event Mask on line 21 - MR22: u1, // bit offset: 22 desc: Event Mask on line 22 - MR23: u1, // bit offset: 23 desc: Event Mask on line 23 - MR24: u1, // bit offset: 24 desc: Event Mask on line 24 - MR25: u1, // bit offset: 25 desc: Event Mask on line 25 - MR26: u1, // bit offset: 26 desc: Event Mask on line 26 - MR27: u1, // bit offset: 27 desc: Event Mask on line 27 - MR28: u1, // bit offset: 28 desc: Event Mask on line 28 - MR29: u1, // bit offset: 29 desc: Event Mask on line 29 - MR30: u1, // bit offset: 30 desc: Event Mask on line 30 - MR31: u1, // bit offset: 31 desc: Event Mask on line 31 - }); - // byte offset: 8 Rising Trigger selection register - pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Rising trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Rising trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Rising trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Rising trigger event configuration of line 22 - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Rising trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Rising trigger event configuration of line 30 - TR31: u1, // bit offset: 31 desc: Rising trigger event configuration of line 31 - }); - // byte offset: 12 Falling Trigger selection register - pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Falling trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Falling trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Falling trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Falling trigger event configuration of line 22 - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Falling trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Falling trigger event configuration of line 30. - TR31: u1, // bit offset: 31 desc: Falling trigger event configuration of line 31 - }); - // byte offset: 16 Software interrupt event register - pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { - SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 - SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 - SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 - SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 - SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 - SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 - SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 - SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 - SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 - SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 - SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 - SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 - SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 - SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 - SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 - SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 - SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 - SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 - SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 - SWIER19: u1, // bit offset: 19 desc: Software Interrupt on line 19 - SWIER20: u1, // bit offset: 20 desc: Software Interrupt on line 20 - SWIER21: u1, // bit offset: 21 desc: Software Interrupt on line 21 - SWIER22: u1, // bit offset: 22 desc: Software Interrupt on line 22 - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SWIER29: u1, // bit offset: 29 desc: Software Interrupt on line 29 - SWIER30: u1, // bit offset: 30 desc: Software Interrupt on line 309 - SWIER31: u1, // bit offset: 31 desc: Software Interrupt on line 319 - }); - // byte offset: 20 Pending register - pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { - PR0: u1, // bit offset: 0 desc: Pending bit 0 - PR1: u1, // bit offset: 1 desc: Pending bit 1 - PR2: u1, // bit offset: 2 desc: Pending bit 2 - PR3: u1, // bit offset: 3 desc: Pending bit 3 - PR4: u1, // bit offset: 4 desc: Pending bit 4 - PR5: u1, // bit offset: 5 desc: Pending bit 5 - PR6: u1, // bit offset: 6 desc: Pending bit 6 - PR7: u1, // bit offset: 7 desc: Pending bit 7 - PR8: u1, // bit offset: 8 desc: Pending bit 8 - PR9: u1, // bit offset: 9 desc: Pending bit 9 - PR10: u1, // bit offset: 10 desc: Pending bit 10 - PR11: u1, // bit offset: 11 desc: Pending bit 11 - PR12: u1, // bit offset: 12 desc: Pending bit 12 - PR13: u1, // bit offset: 13 desc: Pending bit 13 - PR14: u1, // bit offset: 14 desc: Pending bit 14 - PR15: u1, // bit offset: 15 desc: Pending bit 15 - PR16: u1, // bit offset: 16 desc: Pending bit 16 - PR17: u1, // bit offset: 17 desc: Pending bit 17 - PR18: u1, // bit offset: 18 desc: Pending bit 18 - PR19: u1, // bit offset: 19 desc: Pending bit 19 - PR20: u1, // bit offset: 20 desc: Pending bit 20 - PR21: u1, // bit offset: 21 desc: Pending bit 21 - PR22: u1, // bit offset: 22 desc: Pending bit 22 - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PR29: u1, // bit offset: 29 desc: Pending bit 29 - PR30: u1, // bit offset: 30 desc: Pending bit 30 - PR31: u1, // bit offset: 31 desc: Pending bit 31 - }); - // byte offset: 24 Interrupt mask register - pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Interrupt Mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Interrupt Mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Interrupt Mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Interrupt Mask on external/internal line 35 - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, +pub const I2S2ext = extern struct { + pub const Address: u32 = 0x40003400; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + CRCL: u1, // bit offset: 11 desc: CRC length + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9510,23 +9399,20 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Event mask register - pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Event mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Event mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Event mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Event mask on external/internal line 35 - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9545,21 +9431,19 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Rising Trigger selection register - pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Rising trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Rising trigger event configuration bit of line 33 - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9580,24 +9464,9 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Falling Trigger selection register - pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Falling trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Falling trigger event configuration bit of line 33 - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9615,20 +9484,77 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Software interrupt event register - pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { - SWIER32: u1, // bit offset: 0 desc: Software interrupt on line 32 - SWIER33: u1, // bit offset: 1 desc: Software interrupt on line 33 - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9650,18 +9576,11 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Pending register - pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { - PR32: u1, // bit offset: 0 desc: Pending bit on line 32 - PR33: u1, // bit offset: 1 desc: Pending bit on line 33 - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9686,206 +9605,86 @@ pub const EXTI = extern struct { padding1: u1 = 0, }); }; -pub const COMP = extern struct { - pub const Address: u32 = 0x4001001c; - // byte offset: 0 control and status register - pub const COMP1_CSR = mmio(Address + 0x00000000, 32, packed struct { - COMP1EN: u1, // bit offset: 0 desc: Comparator 1 enable - COMP1_INP_DAC: u1, // bit offset: 1 desc: COMP1_INP_DAC - COMP1MODE: u2, // bit offset: 2 desc: Comparator 1 mode - COMP1INSEL: u3, // bit offset: 4 desc: Comparator 1 inverting input selection - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - COMP1_OUT_SEL: u4, // bit offset: 10 desc: Comparator 1 output selection - reserved4: u1 = 0, - COMP1POL: u1, // bit offset: 15 desc: Comparator 1 output polarity - COMP1HYST: u2, // bit offset: 16 desc: Comparator 1 hysteresis - COMP1_BLANKING: u3, // bit offset: 18 desc: Comparator 1 blanking source - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - COMP1OUT: u1, // bit offset: 30 desc: Comparator 1 output - COMP1LOCK: u1, // bit offset: 31 desc: Comparator 1 lock +pub const I2S3ext = extern struct { + pub const Address: u32 = 0x40004000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + CRCL: u1, // bit offset: 11 desc: CRC length + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 4 control and status register - pub const COMP2_CSR = mmio(Address + 0x00000004, 32, packed struct { - COMP2EN: u1, // bit offset: 0 desc: Comparator 2 enable - reserved1: u1 = 0, - COMP2MODE: u2, // bit offset: 2 desc: Comparator 2 mode - COMP2INSEL: u3, // bit offset: 4 desc: Comparator 2 inverting input selection - COMP2INPSEL: u1, // bit offset: 7 desc: Comparator 2 non inverted input selection - reserved2: u1 = 0, - COMP2INMSEL: u1, // bit offset: 9 desc: Comparator 1inverting input selection - COMP2_OUT_SEL: u4, // bit offset: 10 desc: Comparator 2 output selection - reserved3: u1 = 0, - COMP2POL: u1, // bit offset: 15 desc: Comparator 2 output polarity - COMP2HYST: u2, // bit offset: 16 desc: Comparator 2 hysteresis - COMP2_BLANKING: u3, // bit offset: 18 desc: Comparator 2 blanking source - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - COMP2OUT: u1, // bit offset: 30 desc: Comparator 2 output - COMP2LOCK: u1, // bit offset: 31 desc: Comparator 2 lock + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 8 control and status register - pub const COMP3_CSR = mmio(Address + 0x00000008, 32, packed struct { - COMP3EN: u1, // bit offset: 0 desc: Comparator 3 enable - reserved1: u1 = 0, - COMP3MODE: u2, // bit offset: 2 desc: Comparator 3 mode - COMP3INSEL: u3, // bit offset: 4 desc: Comparator 3 inverting input selection - COMP3INPSEL: u1, // bit offset: 7 desc: Comparator 3 non inverted input selection - reserved3: u1 = 0, - reserved2: u1 = 0, - COMP3_OUT_SEL: u4, // bit offset: 10 desc: Comparator 3 output selection - reserved4: u1 = 0, - COMP3POL: u1, // bit offset: 15 desc: Comparator 3 output polarity - COMP3HYST: u2, // bit offset: 16 desc: Comparator 3 hysteresis - COMP3_BLANKING: u3, // bit offset: 18 desc: Comparator 3 blanking source - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - COMP3OUT: u1, // bit offset: 30 desc: Comparator 3 output - COMP3LOCK: u1, // bit offset: 31 desc: Comparator 3 lock - }); - // byte offset: 12 control and status register - pub const COMP4_CSR = mmio(Address + 0x0000000c, 32, packed struct { - COMP4EN: u1, // bit offset: 0 desc: Comparator 4 enable - reserved1: u1 = 0, - COMP4MODE: u2, // bit offset: 2 desc: Comparator 4 mode - COMP4INSEL: u3, // bit offset: 4 desc: Comparator 4 inverting input selection - COMP4INPSEL: u1, // bit offset: 7 desc: Comparator 4 non inverted input selection - reserved2: u1 = 0, - COM4WINMODE: u1, // bit offset: 9 desc: Comparator 4 window mode - COMP4_OUT_SEL: u4, // bit offset: 10 desc: Comparator 4 output selection - reserved3: u1 = 0, - COMP4POL: u1, // bit offset: 15 desc: Comparator 4 output polarity - COMP4HYST: u2, // bit offset: 16 desc: Comparator 4 hysteresis - COMP4_BLANKING: u3, // bit offset: 18 desc: Comparator 4 blanking source - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - COMP4OUT: u1, // bit offset: 30 desc: Comparator 4 output - COMP4LOCK: u1, // bit offset: 31 desc: Comparator 4 lock - }); - // byte offset: 16 control and status register - pub const COMP5_CSR = mmio(Address + 0x00000010, 32, packed struct { - COMP5EN: u1, // bit offset: 0 desc: Comparator 5 enable - reserved1: u1 = 0, - COMP5MODE: u2, // bit offset: 2 desc: Comparator 5 mode - COMP5INSEL: u3, // bit offset: 4 desc: Comparator 5 inverting input selection - COMP5INPSEL: u1, // bit offset: 7 desc: Comparator 5 non inverted input selection - reserved3: u1 = 0, - reserved2: u1 = 0, - COMP5_OUT_SEL: u4, // bit offset: 10 desc: Comparator 5 output selection - reserved4: u1 = 0, - COMP5POL: u1, // bit offset: 15 desc: Comparator 5 output polarity - COMP5HYST: u2, // bit offset: 16 desc: Comparator 5 hysteresis - COMP5_BLANKING: u3, // bit offset: 18 desc: Comparator 5 blanking source - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - COMP5OUT: u1, // bit offset: 30 desc: Comparator51 output - COMP5LOCK: u1, // bit offset: 31 desc: Comparator 5 lock - }); - // byte offset: 20 control and status register - pub const COMP6_CSR = mmio(Address + 0x00000014, 32, packed struct { - COMP6EN: u1, // bit offset: 0 desc: Comparator 6 enable - reserved1: u1 = 0, - COMP6MODE: u2, // bit offset: 2 desc: Comparator 6 mode - COMP6INSEL: u3, // bit offset: 4 desc: Comparator 6 inverting input selection - COMP6INPSEL: u1, // bit offset: 7 desc: Comparator 6 non inverted input selection - reserved2: u1 = 0, - COM6WINMODE: u1, // bit offset: 9 desc: Comparator 6 window mode - COMP6_OUT_SEL: u4, // bit offset: 10 desc: Comparator 6 output selection - reserved3: u1 = 0, - COMP6POL: u1, // bit offset: 15 desc: Comparator 6 output polarity - COMP6HYST: u2, // bit offset: 16 desc: Comparator 6 hysteresis - COMP6_BLANKING: u3, // bit offset: 18 desc: Comparator 6 blanking source - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - COMP6OUT: u1, // bit offset: 30 desc: Comparator 6 output - COMP6LOCK: u1, // bit offset: 31 desc: Comparator 6 lock - }); - // byte offset: 24 control and status register - pub const COMP7_CSR = mmio(Address + 0x00000018, 32, packed struct { - COMP7EN: u1, // bit offset: 0 desc: Comparator 7 enable - reserved1: u1 = 0, - COMP7MODE: u2, // bit offset: 2 desc: Comparator 7 mode - COMP7INSEL: u3, // bit offset: 4 desc: Comparator 7 inverting input selection - COMP7INPSEL: u1, // bit offset: 7 desc: Comparator 7 non inverted input selection - reserved3: u1 = 0, - reserved2: u1 = 0, - COMP7_OUT_SEL: u4, // bit offset: 10 desc: Comparator 7 output selection - reserved4: u1 = 0, - COMP7POL: u1, // bit offset: 15 desc: Comparator 7 output polarity - COMP7HYST: u2, // bit offset: 16 desc: Comparator 7 hysteresis - COMP7_BLANKING: u3, // bit offset: 18 desc: Comparator 7 blanking source - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - COMP7OUT: u1, // bit offset: 30 desc: Comparator 7 output - COMP7LOCK: u1, // bit offset: 31 desc: Comparator 7 lock - }); -}; -pub const PWR = extern struct { - pub const Address: u32 = 0x40007000; - // byte offset: 0 power control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - LPDS: u1, // bit offset: 0 desc: Low-power deep sleep - PDDS: u1, // bit offset: 1 desc: Power down deepsleep - CWUF: u1, // bit offset: 2 desc: Clear wakeup flag - CSBF: u1, // bit offset: 3 desc: Clear standby flag - PVDE: u1, // bit offset: 4 desc: Power voltage detector enable - PLS: u3, // bit offset: 5 desc: PVD level selection - DBP: u1, // bit offset: 8 desc: Disable backup domain write protection - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9906,24 +9705,9 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 power control/status register - pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - WUF: u1, // bit offset: 0 desc: Wakeup flag - SBF: u1, // bit offset: 1 desc: Standby flag - PVDO: u1, // bit offset: 2 desc: PVD output - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - EWUP1: u1, // bit offset: 8 desc: Enable WKUP1 pin - EWUP2: u1, // bit offset: 9 desc: Enable WKUP2 pin - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9941,28 +9725,10 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const CAN = extern struct { - pub const Address: u32 = 0x40006400; - // byte offset: 0 master control register - pub const MCR = mmio(Address + 0x00000000, 32, packed struct { - INRQ: u1, // bit offset: 0 desc: INRQ - SLEEP: u1, // bit offset: 1 desc: SLEEP - TXFP: u1, // bit offset: 2 desc: TXFP - RFLM: u1, // bit offset: 3 desc: RFLM - NART: u1, // bit offset: 4 desc: NART - AWUM: u1, // bit offset: 5 desc: AWUM - ABOM: u1, // bit offset: 6 desc: ABOM - TTCM: u1, // bit offset: 7 desc: TTCM - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESET: u1, // bit offset: 15 desc: RESET - DBF: u1, // bit offset: 16 desc: DBF + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -9979,20 +9745,57 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 master status register - pub const MSR = mmio(Address + 0x00000004, 32, packed struct { - INAK: u1, // bit offset: 0 desc: INAK - SLAK: u1, // bit offset: 1 desc: SLAK - ERRI: u1, // bit offset: 2 desc: ERRI - WKUI: u1, // bit offset: 3 desc: WKUI - SLAKI: u1, // bit offset: 4 desc: SLAKI - reserved3: u1 = 0, - reserved2: u1 = 0, + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection reserved1: u1 = 0, - TXM: u1, // bit offset: 8 desc: TXM - RXM: u1, // bit offset: 9 desc: RXM - SAMP: u1, // bit offset: 10 desc: SAMP - RX: u1, // bit offset: 11 desc: RX + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -10014,51 +9817,11 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 transmit status register - pub const TSR = mmio(Address + 0x00000008, 32, packed struct { - RQCP0: u1, // bit offset: 0 desc: RQCP0 - TXOK0: u1, // bit offset: 1 desc: TXOK0 - ALST0: u1, // bit offset: 2 desc: ALST0 - TERR0: u1, // bit offset: 3 desc: TERR0 - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABRQ0: u1, // bit offset: 7 desc: ABRQ0 - RQCP1: u1, // bit offset: 8 desc: RQCP1 - TXOK1: u1, // bit offset: 9 desc: TXOK1 - ALST1: u1, // bit offset: 10 desc: ALST1 - TERR1: u1, // bit offset: 11 desc: TERR1 - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - ABRQ1: u1, // bit offset: 15 desc: ABRQ1 - RQCP2: u1, // bit offset: 16 desc: RQCP2 - TXOK2: u1, // bit offset: 17 desc: TXOK2 - ALST2: u1, // bit offset: 18 desc: ALST2 - TERR2: u1, // bit offset: 19 desc: TERR2 - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - ABRQ2: u1, // bit offset: 23 desc: ABRQ2 - CODE: u2, // bit offset: 24 desc: CODE - TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 - TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 - TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 - LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 - LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 - LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 - }); - // byte offset: 12 receive FIFO 0 register - pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { - FMP0: u2, // bit offset: 0 desc: FMP0 - reserved1: u1 = 0, - FULL0: u1, // bit offset: 3 desc: FULL0 - FOVR0: u1, // bit offset: 4 desc: FOVR0 - RFOM0: u1, // bit offset: 5 desc: RFOM0 - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10082,20 +9845,87 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 receive FIFO 1 register - pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { - FMP1: u2, // bit offset: 0 desc: FMP1 - reserved1: u1 = 0, - FULL1: u1, // bit offset: 3 desc: FULL1 - FOVR1: u1, // bit offset: 4 desc: FOVR1 - RFOM1: u1, // bit offset: 5 desc: RFOM1 - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, +}; +pub const SPI4 = extern struct { + pub const Address: u32 = 0x40013c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CPHA: u1, // bit offset: 0 desc: Clock phase + CPOL: u1, // bit offset: 1 desc: Clock polarity + MSTR: u1, // bit offset: 2 desc: Master selection + BR: u3, // bit offset: 3 desc: Baud rate control + SPE: u1, // bit offset: 6 desc: SPI enable + LSBFIRST: u1, // bit offset: 7 desc: Frame format + SSI: u1, // bit offset: 8 desc: Internal slave select + SSM: u1, // bit offset: 9 desc: Software slave management + RXONLY: u1, // bit offset: 10 desc: Receive only + CRCL: u1, // bit offset: 11 desc: CRC length + CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next + CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable + BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode + BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable + TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable + SSOE: u1, // bit offset: 2 desc: SS output enable + NSSP: u1, // bit offset: 3 desc: NSS pulse management + FRF: u1, // bit offset: 4 desc: Frame format + ERRIE: u1, // bit offset: 5 desc: Error interrupt enable + RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable + TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + DS: u4, // bit offset: 8 desc: Data size + FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold + LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception + LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + RXNE: u1, // bit offset: 0 desc: Receive buffer not empty + TXE: u1, // bit offset: 1 desc: Transmit buffer empty + CHSIDE: u1, // bit offset: 2 desc: Channel side + UDR: u1, // bit offset: 3 desc: Underrun flag + CRCERR: u1, // bit offset: 4 desc: CRC error flag + MODF: u1, // bit offset: 5 desc: Mode fault + OVR: u1, // bit offset: 6 desc: Overrun flag + BSY: u1, // bit offset: 7 desc: Busy flag + TIFRFE: u1, // bit offset: 8 desc: TI frame format error + FRLVL: u2, // bit offset: 9 desc: FIFO reception level + FTLVL: u2, // bit offset: 11 desc: FIFO transmission level padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -10116,26 +9946,11 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 interrupt enable register - pub const IER = mmio(Address + 0x00000014, 32, packed struct { - TMEIE: u1, // bit offset: 0 desc: TMEIE - FMPIE0: u1, // bit offset: 1 desc: FMPIE0 - FFIE0: u1, // bit offset: 2 desc: FFIE0 - FOVIE0: u1, // bit offset: 3 desc: FOVIE0 - FMPIE1: u1, // bit offset: 4 desc: FMPIE1 - FFIE1: u1, // bit offset: 5 desc: FFIE1 - FOVIE1: u1, // bit offset: 6 desc: FOVIE1 - reserved1: u1 = 0, - EWGIE: u1, // bit offset: 8 desc: EWGIE - EPVIE: u1, // bit offset: 9 desc: EPVIE - BOFIE: u1, // bit offset: 10 desc: BOFIE - LECIE: u1, // bit offset: 11 desc: LECIE - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - ERRIE: u1, // bit offset: 15 desc: ERRIE - WKUIE: u1, // bit offset: 16 desc: WKUIE - SLKIE: u1, // bit offset: 17 desc: SLKIE + // byte offset: 12 data register + pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + DR: u16, // bit offset: 0 desc: Data register + padding16: u1 = 0, + padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -10151,239 +9966,49 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 error status register - pub const ESR = mmio(Address + 0x00000018, 32, packed struct { - EWGF: u1, // bit offset: 0 desc: EWGF - EPVF: u1, // bit offset: 1 desc: EPVF - BOFF: u1, // bit offset: 2 desc: BOFF - reserved1: u1 = 0, - LEC: u3, // bit offset: 4 desc: LEC - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - TEC: u8, // bit offset: 16 desc: TEC - REC: u8, // bit offset: 24 desc: REC - }); - // byte offset: 28 bit timing register - pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { - BRP: u10, // bit offset: 0 desc: BRP - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TS1: u4, // bit offset: 16 desc: TS1 - TS2: u3, // bit offset: 20 desc: TS2 - reserved7: u1 = 0, - SJW: u2, // bit offset: 24 desc: SJW - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - LBKM: u1, // bit offset: 30 desc: LBKM - SILM: u1, // bit offset: 31 desc: SILM + // byte offset: 16 CRC polynomial register + pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 384 TX mailbox identifier register - pub const TI0R = mmio(Address + 0x00000180, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID + // byte offset: 20 RX CRC register + pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { + RxCRC: u16, // bit offset: 0 desc: Rx CRC register + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 388 mailbox data length control and time stamp register - pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 392 mailbox data low register - pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 396 mailbox data high register - pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 400 TX mailbox identifier register - pub const TI1R = mmio(Address + 0x00000190, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 404 mailbox data length control and time stamp register - pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 408 mailbox data low register - pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 412 mailbox data high register - pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 416 TX mailbox identifier register - pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 420 mailbox data length control and time stamp register - pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 424 mailbox data low register - pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 428 mailbox data high register - pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 432 receive FIFO mailbox identifier register - pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { - reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 436 receive FIFO mailbox data length control and time stamp register - pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 440 receive FIFO mailbox data low register - pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 444 receive FIFO mailbox data high register - pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 448 receive FIFO mailbox identifier register - pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { - reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 452 receive FIFO mailbox data length control and time stamp register - pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 456 receive FIFO mailbox data low register - pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 460 receive FIFO mailbox data high register - pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 512 filter master register - pub const FMR = mmio(Address + 0x00000200, 32, packed struct { - FINIT: u1, // bit offset: 0 desc: Filter init mode - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CAN2SB: u6, // bit offset: 8 desc: CAN2 start bank - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 24 TX CRC register + pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { + TxCRC: u16, // bit offset: 0 desc: Tx CRC register padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10401,196 +10026,2365 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 516 filter mode register - pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { - FBM0: u1, // bit offset: 0 desc: Filter mode - FBM1: u1, // bit offset: 1 desc: Filter mode - FBM2: u1, // bit offset: 2 desc: Filter mode - FBM3: u1, // bit offset: 3 desc: Filter mode - FBM4: u1, // bit offset: 4 desc: Filter mode - FBM5: u1, // bit offset: 5 desc: Filter mode - FBM6: u1, // bit offset: 6 desc: Filter mode - FBM7: u1, // bit offset: 7 desc: Filter mode - FBM8: u1, // bit offset: 8 desc: Filter mode - FBM9: u1, // bit offset: 9 desc: Filter mode - FBM10: u1, // bit offset: 10 desc: Filter mode - FBM11: u1, // bit offset: 11 desc: Filter mode - FBM12: u1, // bit offset: 12 desc: Filter mode - FBM13: u1, // bit offset: 13 desc: Filter mode - FBM14: u1, // bit offset: 14 desc: Filter mode - FBM15: u1, // bit offset: 15 desc: Filter mode - FBM16: u1, // bit offset: 16 desc: Filter mode - FBM17: u1, // bit offset: 17 desc: Filter mode - FBM18: u1, // bit offset: 18 desc: Filter mode - FBM19: u1, // bit offset: 19 desc: Filter mode - FBM20: u1, // bit offset: 20 desc: Filter mode - FBM21: u1, // bit offset: 21 desc: Filter mode - FBM22: u1, // bit offset: 22 desc: Filter mode - FBM23: u1, // bit offset: 23 desc: Filter mode - FBM24: u1, // bit offset: 24 desc: Filter mode - FBM25: u1, // bit offset: 25 desc: Filter mode - FBM26: u1, // bit offset: 26 desc: Filter mode - FBM27: u1, // bit offset: 27 desc: Filter mode + // byte offset: 28 I2S configuration register + pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { + CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) + DATLEN: u2, // bit offset: 1 desc: Data length to be transferred + CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity + I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + reserved1: u1 = 0, + PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization + I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode + I2SE: u1, // bit offset: 10 desc: I2S Enable + I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 524 filter scale register - pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { - FSC0: u1, // bit offset: 0 desc: Filter scale configuration - FSC1: u1, // bit offset: 1 desc: Filter scale configuration - FSC2: u1, // bit offset: 2 desc: Filter scale configuration - FSC3: u1, // bit offset: 3 desc: Filter scale configuration - FSC4: u1, // bit offset: 4 desc: Filter scale configuration - FSC5: u1, // bit offset: 5 desc: Filter scale configuration - FSC6: u1, // bit offset: 6 desc: Filter scale configuration - FSC7: u1, // bit offset: 7 desc: Filter scale configuration - FSC8: u1, // bit offset: 8 desc: Filter scale configuration - FSC9: u1, // bit offset: 9 desc: Filter scale configuration - FSC10: u1, // bit offset: 10 desc: Filter scale configuration - FSC11: u1, // bit offset: 11 desc: Filter scale configuration - FSC12: u1, // bit offset: 12 desc: Filter scale configuration - FSC13: u1, // bit offset: 13 desc: Filter scale configuration - FSC14: u1, // bit offset: 14 desc: Filter scale configuration - FSC15: u1, // bit offset: 15 desc: Filter scale configuration - FSC16: u1, // bit offset: 16 desc: Filter scale configuration - FSC17: u1, // bit offset: 17 desc: Filter scale configuration - FSC18: u1, // bit offset: 18 desc: Filter scale configuration - FSC19: u1, // bit offset: 19 desc: Filter scale configuration - FSC20: u1, // bit offset: 20 desc: Filter scale configuration - FSC21: u1, // bit offset: 21 desc: Filter scale configuration - FSC22: u1, // bit offset: 22 desc: Filter scale configuration - FSC23: u1, // bit offset: 23 desc: Filter scale configuration - FSC24: u1, // bit offset: 24 desc: Filter scale configuration - FSC25: u1, // bit offset: 25 desc: Filter scale configuration - FSC26: u1, // bit offset: 26 desc: Filter scale configuration - FSC27: u1, // bit offset: 27 desc: Filter scale configuration + // byte offset: 32 I2S prescaler register + pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { + I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler + ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler + MCKOE: u1, // bit offset: 9 desc: Master clock output enable + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 532 filter FIFO assignment register - pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { - FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 - FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 - FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 - FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 - FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 - FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 - FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 - FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 - FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 - FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 - FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 - FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 - FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 - FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 - FFA14: u1, // bit offset: 14 desc: Filter FIFO assignment for filter 14 - FFA15: u1, // bit offset: 15 desc: Filter FIFO assignment for filter 15 - FFA16: u1, // bit offset: 16 desc: Filter FIFO assignment for filter 16 - FFA17: u1, // bit offset: 17 desc: Filter FIFO assignment for filter 17 - FFA18: u1, // bit offset: 18 desc: Filter FIFO assignment for filter 18 - FFA19: u1, // bit offset: 19 desc: Filter FIFO assignment for filter 19 - FFA20: u1, // bit offset: 20 desc: Filter FIFO assignment for filter 20 - FFA21: u1, // bit offset: 21 desc: Filter FIFO assignment for filter 21 - FFA22: u1, // bit offset: 22 desc: Filter FIFO assignment for filter 22 - FFA23: u1, // bit offset: 23 desc: Filter FIFO assignment for filter 23 - FFA24: u1, // bit offset: 24 desc: Filter FIFO assignment for filter 24 - FFA25: u1, // bit offset: 25 desc: Filter FIFO assignment for filter 25 - FFA26: u1, // bit offset: 26 desc: Filter FIFO assignment for filter 26 - FFA27: u1, // bit offset: 27 desc: Filter FIFO assignment for filter 27 - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, +}; +pub const EXTI = extern struct { + pub const Address: u32 = 0x40010400; + // byte offset: 0 Interrupt mask register + pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 + MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 + MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 + MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 + MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 + MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 + MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 + MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 + MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 + MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 + MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 + MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 + MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 + MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 + MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 + MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 + MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 + MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 + MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 + MR19: u1, // bit offset: 19 desc: Interrupt Mask on line 19 + MR20: u1, // bit offset: 20 desc: Interrupt Mask on line 20 + MR21: u1, // bit offset: 21 desc: Interrupt Mask on line 21 + MR22: u1, // bit offset: 22 desc: Interrupt Mask on line 22 + MR23: u1, // bit offset: 23 desc: Interrupt Mask on line 23 + MR24: u1, // bit offset: 24 desc: Interrupt Mask on line 24 + MR25: u1, // bit offset: 25 desc: Interrupt Mask on line 25 + MR26: u1, // bit offset: 26 desc: Interrupt Mask on line 26 + MR27: u1, // bit offset: 27 desc: Interrupt Mask on line 27 + MR28: u1, // bit offset: 28 desc: Interrupt Mask on line 28 + MR29: u1, // bit offset: 29 desc: Interrupt Mask on line 29 + MR30: u1, // bit offset: 30 desc: Interrupt Mask on line 30 + MR31: u1, // bit offset: 31 desc: Interrupt Mask on line 31 }); - // byte offset: 540 CAN filter activation register - pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { - FACT0: u1, // bit offset: 0 desc: Filter active - FACT1: u1, // bit offset: 1 desc: Filter active - FACT2: u1, // bit offset: 2 desc: Filter active - FACT3: u1, // bit offset: 3 desc: Filter active - FACT4: u1, // bit offset: 4 desc: Filter active - FACT5: u1, // bit offset: 5 desc: Filter active - FACT6: u1, // bit offset: 6 desc: Filter active - FACT7: u1, // bit offset: 7 desc: Filter active - FACT8: u1, // bit offset: 8 desc: Filter active - FACT9: u1, // bit offset: 9 desc: Filter active - FACT10: u1, // bit offset: 10 desc: Filter active - FACT11: u1, // bit offset: 11 desc: Filter active - FACT12: u1, // bit offset: 12 desc: Filter active - FACT13: u1, // bit offset: 13 desc: Filter active - FACT14: u1, // bit offset: 14 desc: Filter active - FACT15: u1, // bit offset: 15 desc: Filter active - FACT16: u1, // bit offset: 16 desc: Filter active - FACT17: u1, // bit offset: 17 desc: Filter active - FACT18: u1, // bit offset: 18 desc: Filter active - FACT19: u1, // bit offset: 19 desc: Filter active - FACT20: u1, // bit offset: 20 desc: Filter active - FACT21: u1, // bit offset: 21 desc: Filter active - FACT22: u1, // bit offset: 22 desc: Filter active - FACT23: u1, // bit offset: 23 desc: Filter active - FACT24: u1, // bit offset: 24 desc: Filter active - FACT25: u1, // bit offset: 25 desc: Filter active - FACT26: u1, // bit offset: 26 desc: Filter active - FACT27: u1, // bit offset: 27 desc: Filter active - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 4 Event mask register + pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { + MR0: u1, // bit offset: 0 desc: Event Mask on line 0 + MR1: u1, // bit offset: 1 desc: Event Mask on line 1 + MR2: u1, // bit offset: 2 desc: Event Mask on line 2 + MR3: u1, // bit offset: 3 desc: Event Mask on line 3 + MR4: u1, // bit offset: 4 desc: Event Mask on line 4 + MR5: u1, // bit offset: 5 desc: Event Mask on line 5 + MR6: u1, // bit offset: 6 desc: Event Mask on line 6 + MR7: u1, // bit offset: 7 desc: Event Mask on line 7 + MR8: u1, // bit offset: 8 desc: Event Mask on line 8 + MR9: u1, // bit offset: 9 desc: Event Mask on line 9 + MR10: u1, // bit offset: 10 desc: Event Mask on line 10 + MR11: u1, // bit offset: 11 desc: Event Mask on line 11 + MR12: u1, // bit offset: 12 desc: Event Mask on line 12 + MR13: u1, // bit offset: 13 desc: Event Mask on line 13 + MR14: u1, // bit offset: 14 desc: Event Mask on line 14 + MR15: u1, // bit offset: 15 desc: Event Mask on line 15 + MR16: u1, // bit offset: 16 desc: Event Mask on line 16 + MR17: u1, // bit offset: 17 desc: Event Mask on line 17 + MR18: u1, // bit offset: 18 desc: Event Mask on line 18 + MR19: u1, // bit offset: 19 desc: Event Mask on line 19 + MR20: u1, // bit offset: 20 desc: Event Mask on line 20 + MR21: u1, // bit offset: 21 desc: Event Mask on line 21 + MR22: u1, // bit offset: 22 desc: Event Mask on line 22 + MR23: u1, // bit offset: 23 desc: Event Mask on line 23 + MR24: u1, // bit offset: 24 desc: Event Mask on line 24 + MR25: u1, // bit offset: 25 desc: Event Mask on line 25 + MR26: u1, // bit offset: 26 desc: Event Mask on line 26 + MR27: u1, // bit offset: 27 desc: Event Mask on line 27 + MR28: u1, // bit offset: 28 desc: Event Mask on line 28 + MR29: u1, // bit offset: 29 desc: Event Mask on line 29 + MR30: u1, // bit offset: 30 desc: Event Mask on line 30 + MR31: u1, // bit offset: 31 desc: Event Mask on line 31 }); - // byte offset: 576 Filter bank 0 register 1 - pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 8 Rising Trigger selection register + pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 + TR19: u1, // bit offset: 19 desc: Rising trigger event configuration of line 19 + TR20: u1, // bit offset: 20 desc: Rising trigger event configuration of line 20 + TR21: u1, // bit offset: 21 desc: Rising trigger event configuration of line 21 + TR22: u1, // bit offset: 22 desc: Rising trigger event configuration of line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TR29: u1, // bit offset: 29 desc: Rising trigger event configuration of line 29 + TR30: u1, // bit offset: 30 desc: Rising trigger event configuration of line 30 + TR31: u1, // bit offset: 31 desc: Rising trigger event configuration of line 31 }); - // byte offset: 580 Filter bank 0 register 2 - pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits + // byte offset: 12 Falling Trigger selection register + pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { + TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 + TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 + TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 + TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 + TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 + TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 + TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 + TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 + TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 + TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 + TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 + TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 + TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 + TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 + TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 + TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 + TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 + TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 + TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 + TR19: u1, // bit offset: 19 desc: Falling trigger event configuration of line 19 + TR20: u1, // bit offset: 20 desc: Falling trigger event configuration of line 20 + TR21: u1, // bit offset: 21 desc: Falling trigger event configuration of line 21 + TR22: u1, // bit offset: 22 desc: Falling trigger event configuration of line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TR29: u1, // bit offset: 29 desc: Falling trigger event configuration of line 29 + TR30: u1, // bit offset: 30 desc: Falling trigger event configuration of line 30. + TR31: u1, // bit offset: 31 desc: Falling trigger event configuration of line 31 + }); + // byte offset: 16 Software interrupt event register + pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { + SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 + SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 + SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 + SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 + SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 + SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 + SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 + SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 + SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 + SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 + SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 + SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 + SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 + SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 + SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 + SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 + SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 + SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 + SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 + SWIER19: u1, // bit offset: 19 desc: Software Interrupt on line 19 + SWIER20: u1, // bit offset: 20 desc: Software Interrupt on line 20 + SWIER21: u1, // bit offset: 21 desc: Software Interrupt on line 21 + SWIER22: u1, // bit offset: 22 desc: Software Interrupt on line 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SWIER29: u1, // bit offset: 29 desc: Software Interrupt on line 29 + SWIER30: u1, // bit offset: 30 desc: Software Interrupt on line 309 + SWIER31: u1, // bit offset: 31 desc: Software Interrupt on line 319 + }); + // byte offset: 20 Pending register + pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { + PR0: u1, // bit offset: 0 desc: Pending bit 0 + PR1: u1, // bit offset: 1 desc: Pending bit 1 + PR2: u1, // bit offset: 2 desc: Pending bit 2 + PR3: u1, // bit offset: 3 desc: Pending bit 3 + PR4: u1, // bit offset: 4 desc: Pending bit 4 + PR5: u1, // bit offset: 5 desc: Pending bit 5 + PR6: u1, // bit offset: 6 desc: Pending bit 6 + PR7: u1, // bit offset: 7 desc: Pending bit 7 + PR8: u1, // bit offset: 8 desc: Pending bit 8 + PR9: u1, // bit offset: 9 desc: Pending bit 9 + PR10: u1, // bit offset: 10 desc: Pending bit 10 + PR11: u1, // bit offset: 11 desc: Pending bit 11 + PR12: u1, // bit offset: 12 desc: Pending bit 12 + PR13: u1, // bit offset: 13 desc: Pending bit 13 + PR14: u1, // bit offset: 14 desc: Pending bit 14 + PR15: u1, // bit offset: 15 desc: Pending bit 15 + PR16: u1, // bit offset: 16 desc: Pending bit 16 + PR17: u1, // bit offset: 17 desc: Pending bit 17 + PR18: u1, // bit offset: 18 desc: Pending bit 18 + PR19: u1, // bit offset: 19 desc: Pending bit 19 + PR20: u1, // bit offset: 20 desc: Pending bit 20 + PR21: u1, // bit offset: 21 desc: Pending bit 21 + PR22: u1, // bit offset: 22 desc: Pending bit 22 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PR29: u1, // bit offset: 29 desc: Pending bit 29 + PR30: u1, // bit offset: 30 desc: Pending bit 30 + PR31: u1, // bit offset: 31 desc: Pending bit 31 + }); + // byte offset: 24 Interrupt mask register + pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { + MR32: u1, // bit offset: 0 desc: Interrupt Mask on external/internal line 32 + MR33: u1, // bit offset: 1 desc: Interrupt Mask on external/internal line 33 + MR34: u1, // bit offset: 2 desc: Interrupt Mask on external/internal line 34 + MR35: u1, // bit offset: 3 desc: Interrupt Mask on external/internal line 35 + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 Event mask register + pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { + MR32: u1, // bit offset: 0 desc: Event mask on external/internal line 32 + MR33: u1, // bit offset: 1 desc: Event mask on external/internal line 33 + MR34: u1, // bit offset: 2 desc: Event mask on external/internal line 34 + MR35: u1, // bit offset: 3 desc: Event mask on external/internal line 35 + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 Rising Trigger selection register + pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { + TR32: u1, // bit offset: 0 desc: Rising trigger event configuration bit of line 32 + TR33: u1, // bit offset: 1 desc: Rising trigger event configuration bit of line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 Falling Trigger selection register + pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { + TR32: u1, // bit offset: 0 desc: Falling trigger event configuration bit of line 32 + TR33: u1, // bit offset: 1 desc: Falling trigger event configuration bit of line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 40 Software interrupt event register + pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { + SWIER32: u1, // bit offset: 0 desc: Software interrupt on line 32 + SWIER33: u1, // bit offset: 1 desc: Software interrupt on line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Pending register + pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { + PR32: u1, // bit offset: 0 desc: Pending bit on line 32 + PR33: u1, // bit offset: 1 desc: Pending bit on line 33 + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const PWR = extern struct { + pub const Address: u32 = 0x40007000; + // byte offset: 0 power control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + LPDS: u1, // bit offset: 0 desc: Low-power deep sleep + PDDS: u1, // bit offset: 1 desc: Power down deepsleep + CWUF: u1, // bit offset: 2 desc: Clear wakeup flag + CSBF: u1, // bit offset: 3 desc: Clear standby flag + PVDE: u1, // bit offset: 4 desc: Power voltage detector enable + PLS: u3, // bit offset: 5 desc: PVD level selection + DBP: u1, // bit offset: 8 desc: Disable backup domain write protection + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 power control/status register + pub const CSR = mmio(Address + 0x00000004, 32, packed struct { + WUF: u1, // bit offset: 0 desc: Wakeup flag + SBF: u1, // bit offset: 1 desc: Standby flag + PVDO: u1, // bit offset: 2 desc: PVD output + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + EWUP1: u1, // bit offset: 8 desc: Enable WKUP1 pin + EWUP2: u1, // bit offset: 9 desc: Enable WKUP2 pin + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const CAN = extern struct { + pub const Address: u32 = 0x40006400; + // byte offset: 0 master control register + pub const MCR = mmio(Address + 0x00000000, 32, packed struct { + INRQ: u1, // bit offset: 0 desc: INRQ + SLEEP: u1, // bit offset: 1 desc: SLEEP + TXFP: u1, // bit offset: 2 desc: TXFP + RFLM: u1, // bit offset: 3 desc: RFLM + NART: u1, // bit offset: 4 desc: NART + AWUM: u1, // bit offset: 5 desc: AWUM + ABOM: u1, // bit offset: 6 desc: ABOM + TTCM: u1, // bit offset: 7 desc: TTCM + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + RESET: u1, // bit offset: 15 desc: RESET + DBF: u1, // bit offset: 16 desc: DBF + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 master status register + pub const MSR = mmio(Address + 0x00000004, 32, packed struct { + INAK: u1, // bit offset: 0 desc: INAK + SLAK: u1, // bit offset: 1 desc: SLAK + ERRI: u1, // bit offset: 2 desc: ERRI + WKUI: u1, // bit offset: 3 desc: WKUI + SLAKI: u1, // bit offset: 4 desc: SLAKI + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TXM: u1, // bit offset: 8 desc: TXM + RXM: u1, // bit offset: 9 desc: RXM + SAMP: u1, // bit offset: 10 desc: SAMP + RX: u1, // bit offset: 11 desc: RX + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 transmit status register + pub const TSR = mmio(Address + 0x00000008, 32, packed struct { + RQCP0: u1, // bit offset: 0 desc: RQCP0 + TXOK0: u1, // bit offset: 1 desc: TXOK0 + ALST0: u1, // bit offset: 2 desc: ALST0 + TERR0: u1, // bit offset: 3 desc: TERR0 + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ABRQ0: u1, // bit offset: 7 desc: ABRQ0 + RQCP1: u1, // bit offset: 8 desc: RQCP1 + TXOK1: u1, // bit offset: 9 desc: TXOK1 + ALST1: u1, // bit offset: 10 desc: ALST1 + TERR1: u1, // bit offset: 11 desc: TERR1 + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + ABRQ1: u1, // bit offset: 15 desc: ABRQ1 + RQCP2: u1, // bit offset: 16 desc: RQCP2 + TXOK2: u1, // bit offset: 17 desc: TXOK2 + ALST2: u1, // bit offset: 18 desc: ALST2 + TERR2: u1, // bit offset: 19 desc: TERR2 + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + ABRQ2: u1, // bit offset: 23 desc: ABRQ2 + CODE: u2, // bit offset: 24 desc: CODE + TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 + TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 + TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 + LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 + LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 + LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 + }); + // byte offset: 12 receive FIFO 0 register + pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { + FMP0: u2, // bit offset: 0 desc: FMP0 + reserved1: u1 = 0, + FULL0: u1, // bit offset: 3 desc: FULL0 + FOVR0: u1, // bit offset: 4 desc: FOVR0 + RFOM0: u1, // bit offset: 5 desc: RFOM0 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 receive FIFO 1 register + pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { + FMP1: u2, // bit offset: 0 desc: FMP1 + reserved1: u1 = 0, + FULL1: u1, // bit offset: 3 desc: FULL1 + FOVR1: u1, // bit offset: 4 desc: FOVR1 + RFOM1: u1, // bit offset: 5 desc: RFOM1 + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 interrupt enable register + pub const IER = mmio(Address + 0x00000014, 32, packed struct { + TMEIE: u1, // bit offset: 0 desc: TMEIE + FMPIE0: u1, // bit offset: 1 desc: FMPIE0 + FFIE0: u1, // bit offset: 2 desc: FFIE0 + FOVIE0: u1, // bit offset: 3 desc: FOVIE0 + FMPIE1: u1, // bit offset: 4 desc: FMPIE1 + FFIE1: u1, // bit offset: 5 desc: FFIE1 + FOVIE1: u1, // bit offset: 6 desc: FOVIE1 + reserved1: u1 = 0, + EWGIE: u1, // bit offset: 8 desc: EWGIE + EPVIE: u1, // bit offset: 9 desc: EPVIE + BOFIE: u1, // bit offset: 10 desc: BOFIE + LECIE: u1, // bit offset: 11 desc: LECIE + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + ERRIE: u1, // bit offset: 15 desc: ERRIE + WKUIE: u1, // bit offset: 16 desc: WKUIE + SLKIE: u1, // bit offset: 17 desc: SLKIE + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 error status register + pub const ESR = mmio(Address + 0x00000018, 32, packed struct { + EWGF: u1, // bit offset: 0 desc: EWGF + EPVF: u1, // bit offset: 1 desc: EPVF + BOFF: u1, // bit offset: 2 desc: BOFF + reserved1: u1 = 0, + LEC: u3, // bit offset: 4 desc: LEC + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + TEC: u8, // bit offset: 16 desc: TEC + REC: u8, // bit offset: 24 desc: REC + }); + // byte offset: 28 bit timing register + pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { + BRP: u10, // bit offset: 0 desc: BRP + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TS1: u4, // bit offset: 16 desc: TS1 + TS2: u3, // bit offset: 20 desc: TS2 + reserved7: u1 = 0, + SJW: u2, // bit offset: 24 desc: SJW + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + LBKM: u1, // bit offset: 30 desc: LBKM + SILM: u1, // bit offset: 31 desc: SILM + }); + // byte offset: 384 TX mailbox identifier register + pub const TI0R = mmio(Address + 0x00000180, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 388 mailbox data length control and time stamp register + pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 392 mailbox data low register + pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 396 mailbox data high register + pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 400 TX mailbox identifier register + pub const TI1R = mmio(Address + 0x00000190, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 404 mailbox data length control and time stamp register + pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 408 mailbox data low register + pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 412 mailbox data high register + pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 416 TX mailbox identifier register + pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct { + TXRQ: u1, // bit offset: 0 desc: TXRQ + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 420 mailbox data length control and time stamp register + pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + TGT: u1, // bit offset: 8 desc: TGT + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 424 mailbox data low register + pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 428 mailbox data high register + pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 432 receive FIFO mailbox identifier register + pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 436 receive FIFO mailbox data length control and time stamp register + pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 440 receive FIFO mailbox data low register + pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 444 receive FIFO mailbox data high register + pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 448 receive FIFO mailbox identifier register + pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { + reserved1: u1 = 0, + RTR: u1, // bit offset: 1 desc: RTR + IDE: u1, // bit offset: 2 desc: IDE + EXID: u18, // bit offset: 3 desc: EXID + STID: u11, // bit offset: 21 desc: STID + }); + // byte offset: 452 receive FIFO mailbox data length control and time stamp register + pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { + DLC: u4, // bit offset: 0 desc: DLC + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + FMI: u8, // bit offset: 8 desc: FMI + TIME: u16, // bit offset: 16 desc: TIME + }); + // byte offset: 456 receive FIFO mailbox data low register + pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct { + DATA0: u8, // bit offset: 0 desc: DATA0 + DATA1: u8, // bit offset: 8 desc: DATA1 + DATA2: u8, // bit offset: 16 desc: DATA2 + DATA3: u8, // bit offset: 24 desc: DATA3 + }); + // byte offset: 460 receive FIFO mailbox data high register + pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct { + DATA4: u8, // bit offset: 0 desc: DATA4 + DATA5: u8, // bit offset: 8 desc: DATA5 + DATA6: u8, // bit offset: 16 desc: DATA6 + DATA7: u8, // bit offset: 24 desc: DATA7 + }); + // byte offset: 512 filter master register + pub const FMR = mmio(Address + 0x00000200, 32, packed struct { + FINIT: u1, // bit offset: 0 desc: Filter init mode + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CAN2SB: u6, // bit offset: 8 desc: CAN2 start bank + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 516 filter mode register + pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { + FBM0: u1, // bit offset: 0 desc: Filter mode + FBM1: u1, // bit offset: 1 desc: Filter mode + FBM2: u1, // bit offset: 2 desc: Filter mode + FBM3: u1, // bit offset: 3 desc: Filter mode + FBM4: u1, // bit offset: 4 desc: Filter mode + FBM5: u1, // bit offset: 5 desc: Filter mode + FBM6: u1, // bit offset: 6 desc: Filter mode + FBM7: u1, // bit offset: 7 desc: Filter mode + FBM8: u1, // bit offset: 8 desc: Filter mode + FBM9: u1, // bit offset: 9 desc: Filter mode + FBM10: u1, // bit offset: 10 desc: Filter mode + FBM11: u1, // bit offset: 11 desc: Filter mode + FBM12: u1, // bit offset: 12 desc: Filter mode + FBM13: u1, // bit offset: 13 desc: Filter mode + FBM14: u1, // bit offset: 14 desc: Filter mode + FBM15: u1, // bit offset: 15 desc: Filter mode + FBM16: u1, // bit offset: 16 desc: Filter mode + FBM17: u1, // bit offset: 17 desc: Filter mode + FBM18: u1, // bit offset: 18 desc: Filter mode + FBM19: u1, // bit offset: 19 desc: Filter mode + FBM20: u1, // bit offset: 20 desc: Filter mode + FBM21: u1, // bit offset: 21 desc: Filter mode + FBM22: u1, // bit offset: 22 desc: Filter mode + FBM23: u1, // bit offset: 23 desc: Filter mode + FBM24: u1, // bit offset: 24 desc: Filter mode + FBM25: u1, // bit offset: 25 desc: Filter mode + FBM26: u1, // bit offset: 26 desc: Filter mode + FBM27: u1, // bit offset: 27 desc: Filter mode + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 524 filter scale register + pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { + FSC0: u1, // bit offset: 0 desc: Filter scale configuration + FSC1: u1, // bit offset: 1 desc: Filter scale configuration + FSC2: u1, // bit offset: 2 desc: Filter scale configuration + FSC3: u1, // bit offset: 3 desc: Filter scale configuration + FSC4: u1, // bit offset: 4 desc: Filter scale configuration + FSC5: u1, // bit offset: 5 desc: Filter scale configuration + FSC6: u1, // bit offset: 6 desc: Filter scale configuration + FSC7: u1, // bit offset: 7 desc: Filter scale configuration + FSC8: u1, // bit offset: 8 desc: Filter scale configuration + FSC9: u1, // bit offset: 9 desc: Filter scale configuration + FSC10: u1, // bit offset: 10 desc: Filter scale configuration + FSC11: u1, // bit offset: 11 desc: Filter scale configuration + FSC12: u1, // bit offset: 12 desc: Filter scale configuration + FSC13: u1, // bit offset: 13 desc: Filter scale configuration + FSC14: u1, // bit offset: 14 desc: Filter scale configuration + FSC15: u1, // bit offset: 15 desc: Filter scale configuration + FSC16: u1, // bit offset: 16 desc: Filter scale configuration + FSC17: u1, // bit offset: 17 desc: Filter scale configuration + FSC18: u1, // bit offset: 18 desc: Filter scale configuration + FSC19: u1, // bit offset: 19 desc: Filter scale configuration + FSC20: u1, // bit offset: 20 desc: Filter scale configuration + FSC21: u1, // bit offset: 21 desc: Filter scale configuration + FSC22: u1, // bit offset: 22 desc: Filter scale configuration + FSC23: u1, // bit offset: 23 desc: Filter scale configuration + FSC24: u1, // bit offset: 24 desc: Filter scale configuration + FSC25: u1, // bit offset: 25 desc: Filter scale configuration + FSC26: u1, // bit offset: 26 desc: Filter scale configuration + FSC27: u1, // bit offset: 27 desc: Filter scale configuration + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 532 filter FIFO assignment register + pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { + FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 + FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 + FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 + FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 + FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 + FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 + FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 + FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 + FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 + FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 + FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 + FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 + FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 + FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 + FFA14: u1, // bit offset: 14 desc: Filter FIFO assignment for filter 14 + FFA15: u1, // bit offset: 15 desc: Filter FIFO assignment for filter 15 + FFA16: u1, // bit offset: 16 desc: Filter FIFO assignment for filter 16 + FFA17: u1, // bit offset: 17 desc: Filter FIFO assignment for filter 17 + FFA18: u1, // bit offset: 18 desc: Filter FIFO assignment for filter 18 + FFA19: u1, // bit offset: 19 desc: Filter FIFO assignment for filter 19 + FFA20: u1, // bit offset: 20 desc: Filter FIFO assignment for filter 20 + FFA21: u1, // bit offset: 21 desc: Filter FIFO assignment for filter 21 + FFA22: u1, // bit offset: 22 desc: Filter FIFO assignment for filter 22 + FFA23: u1, // bit offset: 23 desc: Filter FIFO assignment for filter 23 + FFA24: u1, // bit offset: 24 desc: Filter FIFO assignment for filter 24 + FFA25: u1, // bit offset: 25 desc: Filter FIFO assignment for filter 25 + FFA26: u1, // bit offset: 26 desc: Filter FIFO assignment for filter 26 + FFA27: u1, // bit offset: 27 desc: Filter FIFO assignment for filter 27 + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 540 CAN filter activation register + pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { + FACT0: u1, // bit offset: 0 desc: Filter active + FACT1: u1, // bit offset: 1 desc: Filter active + FACT2: u1, // bit offset: 2 desc: Filter active + FACT3: u1, // bit offset: 3 desc: Filter active + FACT4: u1, // bit offset: 4 desc: Filter active + FACT5: u1, // bit offset: 5 desc: Filter active + FACT6: u1, // bit offset: 6 desc: Filter active + FACT7: u1, // bit offset: 7 desc: Filter active + FACT8: u1, // bit offset: 8 desc: Filter active + FACT9: u1, // bit offset: 9 desc: Filter active + FACT10: u1, // bit offset: 10 desc: Filter active + FACT11: u1, // bit offset: 11 desc: Filter active + FACT12: u1, // bit offset: 12 desc: Filter active + FACT13: u1, // bit offset: 13 desc: Filter active + FACT14: u1, // bit offset: 14 desc: Filter active + FACT15: u1, // bit offset: 15 desc: Filter active + FACT16: u1, // bit offset: 16 desc: Filter active + FACT17: u1, // bit offset: 17 desc: Filter active + FACT18: u1, // bit offset: 18 desc: Filter active + FACT19: u1, // bit offset: 19 desc: Filter active + FACT20: u1, // bit offset: 20 desc: Filter active + FACT21: u1, // bit offset: 21 desc: Filter active + FACT22: u1, // bit offset: 22 desc: Filter active + FACT23: u1, // bit offset: 23 desc: Filter active + FACT24: u1, // bit offset: 24 desc: Filter active + FACT25: u1, // bit offset: 25 desc: Filter active + FACT26: u1, // bit offset: 26 desc: Filter active + FACT27: u1, // bit offset: 27 desc: Filter active + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 576 Filter bank 0 register 1 + pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 580 Filter bank 0 register 2 + pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 584 Filter bank 1 register 1 + pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 588 Filter bank 1 register 2 + pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 592 Filter bank 2 register 1 + pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 596 Filter bank 2 register 2 + pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 600 Filter bank 3 register 1 + pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 604 Filter bank 3 register 2 + pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 608 Filter bank 4 register 1 + pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 612 Filter bank 4 register 2 + pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 616 Filter bank 5 register 1 + pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 620 Filter bank 5 register 2 + pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 624 Filter bank 6 register 1 + pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 628 Filter bank 6 register 2 + pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 632 Filter bank 7 register 1 + pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 636 Filter bank 7 register 2 + pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 640 Filter bank 8 register 1 + pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 644 Filter bank 8 register 2 + pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 648 Filter bank 9 register 1 + pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 652 Filter bank 9 register 2 + pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 656 Filter bank 10 register 1 + pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 660 Filter bank 10 register 2 + pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 664 Filter bank 11 register 1 + pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 668 Filter bank 11 register 2 + pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 672 Filter bank 4 register 1 + pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 676 Filter bank 12 register 2 + pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 680 Filter bank 13 register 1 + pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 684 Filter bank 13 register 2 + pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 688 Filter bank 14 register 1 + pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 692 Filter bank 14 register 2 + pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 696 Filter bank 15 register 1 + pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 700 Filter bank 15 register 2 + pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 704 Filter bank 16 register 1 + pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 708 Filter bank 16 register 2 + pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 712 Filter bank 17 register 1 + pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits FB13: u1, // bit offset: 13 desc: Filter bits FB14: u1, // bit offset: 14 desc: Filter bits FB15: u1, // bit offset: 15 desc: Filter bits @@ -10611,8 +12405,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 584 Filter bank 1 register 1 - pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { + // byte offset: 716 Filter bank 17 register 2 + pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10646,8 +12440,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 588 Filter bank 1 register 2 - pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { + // byte offset: 720 Filter bank 18 register 1 + pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10681,8 +12475,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 592 Filter bank 2 register 1 - pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { + // byte offset: 724 Filter bank 18 register 2 + pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10716,8 +12510,218 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 596 Filter bank 2 register 2 - pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { + // byte offset: 728 Filter bank 19 register 1 + pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 732 Filter bank 19 register 2 + pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 736 Filter bank 20 register 1 + pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 740 Filter bank 20 register 2 + pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 744 Filter bank 21 register 1 + pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 748 Filter bank 21 register 2 + pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { + FB0: u1, // bit offset: 0 desc: Filter bits + FB1: u1, // bit offset: 1 desc: Filter bits + FB2: u1, // bit offset: 2 desc: Filter bits + FB3: u1, // bit offset: 3 desc: Filter bits + FB4: u1, // bit offset: 4 desc: Filter bits + FB5: u1, // bit offset: 5 desc: Filter bits + FB6: u1, // bit offset: 6 desc: Filter bits + FB7: u1, // bit offset: 7 desc: Filter bits + FB8: u1, // bit offset: 8 desc: Filter bits + FB9: u1, // bit offset: 9 desc: Filter bits + FB10: u1, // bit offset: 10 desc: Filter bits + FB11: u1, // bit offset: 11 desc: Filter bits + FB12: u1, // bit offset: 12 desc: Filter bits + FB13: u1, // bit offset: 13 desc: Filter bits + FB14: u1, // bit offset: 14 desc: Filter bits + FB15: u1, // bit offset: 15 desc: Filter bits + FB16: u1, // bit offset: 16 desc: Filter bits + FB17: u1, // bit offset: 17 desc: Filter bits + FB18: u1, // bit offset: 18 desc: Filter bits + FB19: u1, // bit offset: 19 desc: Filter bits + FB20: u1, // bit offset: 20 desc: Filter bits + FB21: u1, // bit offset: 21 desc: Filter bits + FB22: u1, // bit offset: 22 desc: Filter bits + FB23: u1, // bit offset: 23 desc: Filter bits + FB24: u1, // bit offset: 24 desc: Filter bits + FB25: u1, // bit offset: 25 desc: Filter bits + FB26: u1, // bit offset: 26 desc: Filter bits + FB27: u1, // bit offset: 27 desc: Filter bits + FB28: u1, // bit offset: 28 desc: Filter bits + FB29: u1, // bit offset: 29 desc: Filter bits + FB30: u1, // bit offset: 30 desc: Filter bits + FB31: u1, // bit offset: 31 desc: Filter bits + }); + // byte offset: 752 Filter bank 22 register 1 + pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10751,8 +12755,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 600 Filter bank 3 register 1 - pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { + // byte offset: 756 Filter bank 22 register 2 + pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10786,8 +12790,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 604 Filter bank 3 register 2 - pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { + // byte offset: 760 Filter bank 23 register 1 + pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10821,8 +12825,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 608 Filter bank 4 register 1 - pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { + // byte offset: 764 Filter bank 23 register 2 + pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10856,8 +12860,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 612 Filter bank 4 register 2 - pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { + // byte offset: 768 Filter bank 24 register 1 + pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10891,8 +12895,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 616 Filter bank 5 register 1 - pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { + // byte offset: 772 Filter bank 24 register 2 + pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10926,8 +12930,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 620 Filter bank 5 register 2 - pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { + // byte offset: 776 Filter bank 25 register 1 + pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10961,8 +12965,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 624 Filter bank 6 register 1 - pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { + // byte offset: 780 Filter bank 25 register 2 + pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -10996,8 +13000,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 628 Filter bank 6 register 2 - pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { + // byte offset: 784 Filter bank 26 register 1 + pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -11031,8 +13035,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 632 Filter bank 7 register 1 - pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { + // byte offset: 788 Filter bank 26 register 2 + pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -11066,8 +13070,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 636 Filter bank 7 register 2 - pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { + // byte offset: 792 Filter bank 27 register 1 + pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -11101,8 +13105,8 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 640 Filter bank 8 register 1 - pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { + // byte offset: 796 Filter bank 27 register 2 + pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { FB0: u1, // bit offset: 0 desc: Filter bits FB1: u1, // bit offset: 1 desc: Filter bits FB2: u1, // bit offset: 2 desc: Filter bits @@ -11136,1386 +13140,1459 @@ pub const CAN = extern struct { FB30: u1, // bit offset: 30 desc: Filter bits FB31: u1, // bit offset: 31 desc: Filter bits }); - // byte offset: 644 Filter bank 8 register 2 - pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits +}; +pub const USB_FS = extern struct { + pub const Address: u32 = 0x40005c00; + // byte offset: 0 endpoint 0 register + pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 endpoint 1 register + pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 endpoint 2 register + pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 endpoint 3 register + pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 endpoint 4 register + pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 endpoint 5 register + pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 endpoint 6 register + pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 endpoint 7 register + pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { + EA: u4, // bit offset: 0 desc: Endpoint address + STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers + DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers + CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission + EP_KIND: u1, // bit offset: 8 desc: Endpoint kind + EP_TYPE: u2, // bit offset: 9 desc: Endpoint type + SETUP: u1, // bit offset: 11 desc: Setup transaction completed + STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers + DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers + CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 control register + pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { + FRES: u1, // bit offset: 0 desc: Force USB Reset + PDWN: u1, // bit offset: 1 desc: Power down + LPMODE: u1, // bit offset: 2 desc: Low-power mode + FSUSP: u1, // bit offset: 3 desc: Force suspend + RESUME: u1, // bit offset: 4 desc: Resume request + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask + SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask + RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask + SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask + WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask + ERRM: u1, // bit offset: 13 desc: Error interrupt mask + PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask + CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 648 Filter bank 9 register 1 - pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 68 interrupt status register + pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { + EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier + DIR: u1, // bit offset: 4 desc: Direction of transaction + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ESOF: u1, // bit offset: 8 desc: Expected start frame + SOF: u1, // bit offset: 9 desc: start of frame + RESET: u1, // bit offset: 10 desc: reset request + SUSP: u1, // bit offset: 11 desc: Suspend mode request + WKUP: u1, // bit offset: 12 desc: Wakeup + ERR: u1, // bit offset: 13 desc: Error + PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun + CTR: u1, // bit offset: 15 desc: Correct transfer + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 652 Filter bank 9 register 2 - pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 72 frame number register + pub const FNR = mmio(Address + 0x00000048, 32, packed struct { + FN: u11, // bit offset: 0 desc: Frame number + LSOF: u2, // bit offset: 11 desc: Lost SOF + LCK: u1, // bit offset: 13 desc: Locked + RXDM: u1, // bit offset: 14 desc: Receive data - line status + RXDP: u1, // bit offset: 15 desc: Receive data + line status + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 656 Filter bank 10 register 1 - pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 76 device address + pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { + ADD: u1, // bit offset: 0 desc: Device address + ADD1: u1, // bit offset: 1 desc: Device address + ADD2: u1, // bit offset: 2 desc: Device address + ADD3: u1, // bit offset: 3 desc: Device address + ADD4: u1, // bit offset: 4 desc: Device address + ADD5: u1, // bit offset: 5 desc: Device address + ADD6: u1, // bit offset: 6 desc: Device address + EF: u1, // bit offset: 7 desc: Enable function + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 660 Filter bank 10 register 2 - pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 80 Buffer table address + pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + BTABLE: u13, // bit offset: 3 desc: Buffer table + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 664 Filter bank 11 register 1 - pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits +}; +pub const I2C1 = extern struct { + pub const Address: u32 = 0x40005400; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + TXIE: u1, // bit offset: 1 desc: TX Interrupt enable + RXIE: u1, // bit offset: 2 desc: RX Interrupt enable + ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) + NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable + STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable + TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable + ERRIE: u1, // bit offset: 7 desc: Error interrupts enable + DNF: u4, // bit offset: 8 desc: Digital noise filter + ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF + SWRST: u1, // bit offset: 13 desc: Software reset + TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable + RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable + SBC: u1, // bit offset: 16 desc: Slave byte control + NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable + WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable + GCEN: u1, // bit offset: 19 desc: General call enable + SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable + SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable + ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable + PECEN: u1, // bit offset: 23 desc: PEC enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 668 Filter bank 11 register 2 - pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) + SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) + SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) + RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) + ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) + HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) + START: u1, // bit offset: 13 desc: Start generation + STOP: u1, // bit offset: 14 desc: Stop generation (master mode) + NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) + NBYTES: u8, // bit offset: 16 desc: Number of bytes + RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode + AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) + PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 672 Filter bank 4 register 1 - pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + OA1_0: u1, // bit offset: 0 desc: Interface address + OA1_1: u7, // bit offset: 1 desc: Interface address + OA1_8: u2, // bit offset: 8 desc: Interface address + OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 676 Filter bank 12 register 2 - pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + reserved1: u1 = 0, + OA2: u7, // bit offset: 1 desc: Interface address + OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 680 Filter bank 13 register 1 - pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 16 Timing register + pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { + SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) + SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) + SDADEL: u4, // bit offset: 16 desc: Data hold time + SCLDEL: u4, // bit offset: 20 desc: Data setup time + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRESC: u4, // bit offset: 28 desc: Timing prescaler }); - // byte offset: 684 Filter bank 13 register 2 - pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 20 Status register 1 + pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { + TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A + TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + reserved2: u1 = 0, + reserved1: u1 = 0, + TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable + TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable }); - // byte offset: 688 Filter bank 14 register 1 - pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 24 Interrupt and Status register + pub const ISR = mmio(Address + 0x00000018, 32, packed struct { + TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) + TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) + RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) + ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) + NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag + STOPF: u1, // bit offset: 5 desc: Stop detection flag + TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) + TCR: u1, // bit offset: 7 desc: Transfer Complete Reload + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost + OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) + PECERR: u1, // bit offset: 11 desc: PEC Error in reception + TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved1: u1 = 0, + BUSY: u1, // bit offset: 15 desc: Bus busy + DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) + ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 692 Filter bank 14 register 2 - pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 28 Interrupt clear register + pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear + NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear + STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + reserved5: u1 = 0, + reserved4: u1 = 0, + BERRCF: u1, // bit offset: 8 desc: Bus error flag clear + ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear + OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear + PECCF: u1, // bit offset: 11 desc: PEC Error flag clear + TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear + ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 696 Filter bank 15 register 1 - pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 32 PEC register + pub const PECR = mmio(Address + 0x00000020, 32, packed struct { + PEC: u8, // bit offset: 0 desc: Packet error checking register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 700 Filter bank 15 register 2 - pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 36 Receive data register + pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 704 Filter bank 16 register 1 - pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 40 Transmit data register + pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 708 Filter bank 16 register 2 - pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits +}; +pub const I2C2 = extern struct { + pub const Address: u32 = 0x40005800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + TXIE: u1, // bit offset: 1 desc: TX Interrupt enable + RXIE: u1, // bit offset: 2 desc: RX Interrupt enable + ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) + NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable + STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable + TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable + ERRIE: u1, // bit offset: 7 desc: Error interrupts enable + DNF: u4, // bit offset: 8 desc: Digital noise filter + ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF + SWRST: u1, // bit offset: 13 desc: Software reset + TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable + RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable + SBC: u1, // bit offset: 16 desc: Slave byte control + NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable + WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable + GCEN: u1, // bit offset: 19 desc: General call enable + SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable + SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable + ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable + PECEN: u1, // bit offset: 23 desc: PEC enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 712 Filter bank 17 register 1 - pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) + SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) + SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) + RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) + ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) + HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) + START: u1, // bit offset: 13 desc: Start generation + STOP: u1, // bit offset: 14 desc: Stop generation (master mode) + NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) + NBYTES: u8, // bit offset: 16 desc: Number of bytes + RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode + AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) + PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 716 Filter bank 17 register 2 - pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + OA1_0: u1, // bit offset: 0 desc: Interface address + OA1_1: u7, // bit offset: 1 desc: Interface address + OA1_8: u2, // bit offset: 8 desc: Interface address + OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 720 Filter bank 18 register 1 - pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + reserved1: u1 = 0, + OA2: u7, // bit offset: 1 desc: Interface address + OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 724 Filter bank 18 register 2 - pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 16 Timing register + pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { + SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) + SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) + SDADEL: u4, // bit offset: 16 desc: Data hold time + SCLDEL: u4, // bit offset: 20 desc: Data setup time + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRESC: u4, // bit offset: 28 desc: Timing prescaler + }); + // byte offset: 20 Status register 1 + pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { + TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A + TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + reserved2: u1 = 0, + reserved1: u1 = 0, + TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable + TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable }); - // byte offset: 728 Filter bank 19 register 1 - pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 24 Interrupt and Status register + pub const ISR = mmio(Address + 0x00000018, 32, packed struct { + TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) + TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) + RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) + ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) + NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag + STOPF: u1, // bit offset: 5 desc: Stop detection flag + TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) + TCR: u1, // bit offset: 7 desc: Transfer Complete Reload + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost + OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) + PECERR: u1, // bit offset: 11 desc: PEC Error in reception + TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved1: u1 = 0, + BUSY: u1, // bit offset: 15 desc: Bus busy + DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) + ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 732 Filter bank 19 register 2 - pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 28 Interrupt clear register + pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear + NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear + STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + reserved5: u1 = 0, + reserved4: u1 = 0, + BERRCF: u1, // bit offset: 8 desc: Bus error flag clear + ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear + OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear + PECCF: u1, // bit offset: 11 desc: PEC Error flag clear + TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear + ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 736 Filter bank 20 register 1 - pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 32 PEC register + pub const PECR = mmio(Address + 0x00000020, 32, packed struct { + PEC: u8, // bit offset: 0 desc: Packet error checking register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 740 Filter bank 20 register 2 - pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 36 Receive data register + pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 744 Filter bank 21 register 1 - pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 40 Transmit data register + pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 748 Filter bank 21 register 2 - pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits +}; +pub const I2C3 = extern struct { + pub const Address: u32 = 0x40007800; + // byte offset: 0 Control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + PE: u1, // bit offset: 0 desc: Peripheral enable + TXIE: u1, // bit offset: 1 desc: TX Interrupt enable + RXIE: u1, // bit offset: 2 desc: RX Interrupt enable + ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) + NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable + STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable + TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable + ERRIE: u1, // bit offset: 7 desc: Error interrupts enable + DNF: u4, // bit offset: 8 desc: Digital noise filter + ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF + SWRST: u1, // bit offset: 13 desc: Software reset + TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable + RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable + SBC: u1, // bit offset: 16 desc: Slave byte control + NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable + WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable + GCEN: u1, // bit offset: 19 desc: General call enable + SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable + SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable + ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable + PECEN: u1, // bit offset: 23 desc: PEC enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 752 Filter bank 22 register 1 - pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 4 Control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) + SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) + SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) + RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) + ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) + HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) + START: u1, // bit offset: 13 desc: Start generation + STOP: u1, // bit offset: 14 desc: Stop generation (master mode) + NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) + NBYTES: u8, // bit offset: 16 desc: Number of bytes + RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode + AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) + PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 756 Filter bank 22 register 2 - pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 8 Own address register 1 + pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { + OA1_0: u1, // bit offset: 0 desc: Interface address + OA1_1: u7, // bit offset: 1 desc: Interface address + OA1_8: u2, // bit offset: 8 desc: Interface address + OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 Own address register 2 + pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { + reserved1: u1 = 0, + OA2: u7, // bit offset: 1 desc: Interface address + OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 760 Filter bank 23 register 1 - pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 16 Timing register + pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { + SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) + SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) + SDADEL: u4, // bit offset: 16 desc: Data hold time + SCLDEL: u4, // bit offset: 20 desc: Data setup time + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRESC: u4, // bit offset: 28 desc: Timing prescaler }); - // byte offset: 764 Filter bank 23 register 2 - pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 20 Status register 1 + pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { + TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A + TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + reserved2: u1 = 0, + reserved1: u1 = 0, + TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable + TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable }); - // byte offset: 768 Filter bank 24 register 1 - pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 24 Interrupt and Status register + pub const ISR = mmio(Address + 0x00000018, 32, packed struct { + TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) + TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) + RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) + ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) + NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag + STOPF: u1, // bit offset: 5 desc: Stop detection flag + TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) + TCR: u1, // bit offset: 7 desc: Transfer Complete Reload + BERR: u1, // bit offset: 8 desc: Bus error + ARLO: u1, // bit offset: 9 desc: Arbitration lost + OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) + PECERR: u1, // bit offset: 11 desc: PEC Error in reception + TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag + ALERT: u1, // bit offset: 13 desc: SMBus alert + reserved1: u1 = 0, + BUSY: u1, // bit offset: 15 desc: Bus busy + DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) + ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 772 Filter bank 24 register 2 - pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 28 Interrupt clear register + pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear + NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear + STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + reserved5: u1 = 0, + reserved4: u1 = 0, + BERRCF: u1, // bit offset: 8 desc: Bus error flag clear + ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear + OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear + PECCF: u1, // bit offset: 11 desc: PEC Error flag clear + TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear + ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 32 PEC register + pub const PECR = mmio(Address + 0x00000020, 32, packed struct { + PEC: u8, // bit offset: 0 desc: Packet error checking register + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 776 Filter bank 25 register 1 - pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 36 Receive data register + pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { + RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 780 Filter bank 25 register 2 - pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 40 Transmit data register + pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { + TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 784 Filter bank 26 register 1 - pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits +}; +pub const IWDG = extern struct { + pub const Address: u32 = 0x40003000; + // byte offset: 0 Key register + pub const KR = mmio(Address + 0x00000000, 32, packed struct { + KEY: u16, // bit offset: 0 desc: Key value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 788 Filter bank 26 register 2 - pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 4 Prescaler register + pub const PR = mmio(Address + 0x00000004, 32, packed struct { + PR: u3, // bit offset: 0 desc: Prescaler divider + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Reload register + pub const RLR = mmio(Address + 0x00000008, 32, packed struct { + RL: u12, // bit offset: 0 desc: Watchdog counter reload value + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 792 Filter bank 27 register 1 - pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 12 Status register + pub const SR = mmio(Address + 0x0000000c, 32, packed struct { + PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update + RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update + WVU: u1, // bit offset: 2 desc: Watchdog counter window value update + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 796 Filter bank 27 register 2 - pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + // byte offset: 16 Window register + pub const WINR = mmio(Address + 0x00000010, 32, packed struct { + WIN: u12, // bit offset: 0 desc: Watchdog counter window value + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); }; -pub const USB_FS = extern struct { - pub const Address: u32 = 0x40005c00; - // byte offset: 0 endpoint 0 register - pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception +pub const WWDG = extern struct { + pub const Address: u32 = 0x40002c00; + // byte offset: 0 Control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + T: u7, // bit offset: 0 desc: 7-bit counter + WDGA: u1, // bit offset: 7 desc: Activation bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 Configuration register + pub const CFR = mmio(Address + 0x00000004, 32, packed struct { + W: u7, // bit offset: 0 desc: 7-bit window value + WDGTB: u2, // bit offset: 7 desc: Timer base + EWI: u1, // bit offset: 9 desc: Early wakeup interrupt + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 Status register + pub const SR = mmio(Address + 0x00000008, 32, packed struct { + EWIF: u1, // bit offset: 0 desc: Early wakeup interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12533,26 +14610,41 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 endpoint 1 register - pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, +}; +pub const RTC = extern struct { + pub const Address: u32 = 0x40002800; + // byte offset: 0 time register + pub const TR = mmio(Address + 0x00000000, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + reserved1: u1 = 0, + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + reserved2: u1 = 0, + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 date register + pub const DR = mmio(Address + 0x00000004, 32, packed struct { + DU: u4, // bit offset: 0 desc: Date units in BCD format + DT: u2, // bit offset: 4 desc: Date tens in BCD format + reserved2: u1 = 0, + reserved1: u1 = 0, + MU: u4, // bit offset: 8 desc: Month units in BCD format + MT: u1, // bit offset: 12 desc: Month tens in BCD format + WDU: u3, // bit offset: 13 desc: Week day units + YU: u4, // bit offset: 16 desc: Year units in BCD format + YT: u4, // bit offset: 20 desc: Year tens in BCD format padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -12562,19 +14654,57 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 endpoint 2 register - pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception - padding16: u1 = 0, + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + WCKSEL: u3, // bit offset: 0 desc: Wakeup clock selection + TSEDGE: u1, // bit offset: 3 desc: Time-stamp event active edge + REFCKON: u1, // bit offset: 4 desc: Reference clock detection enable (50 or 60 Hz) + BYPSHAD: u1, // bit offset: 5 desc: Bypass the shadow registers + FMT: u1, // bit offset: 6 desc: Hour format + reserved1: u1 = 0, + ALRAE: u1, // bit offset: 8 desc: Alarm A enable + ALRBE: u1, // bit offset: 9 desc: Alarm B enable + WUTE: u1, // bit offset: 10 desc: Wakeup timer enable + TSE: u1, // bit offset: 11 desc: Time stamp enable + ALRAIE: u1, // bit offset: 12 desc: Alarm A interrupt enable + ALRBIE: u1, // bit offset: 13 desc: Alarm B interrupt enable + WUTIE: u1, // bit offset: 14 desc: Wakeup timer interrupt enable + TSIE: u1, // bit offset: 15 desc: Time-stamp interrupt enable + ADD1H: u1, // bit offset: 16 desc: Add 1 hour (summer time change) + SUB1H: u1, // bit offset: 17 desc: Subtract 1 hour (winter time change) + BKP: u1, // bit offset: 18 desc: Backup + COSEL: u1, // bit offset: 19 desc: Calibration output selection + POL: u1, // bit offset: 20 desc: Output polarity + OSEL: u2, // bit offset: 21 desc: Output selection + COE: u1, // bit offset: 23 desc: Calibration output enable + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 initialization and status register + pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { + ALRAWF: u1, // bit offset: 0 desc: Alarm A write flag + ALRBWF: u1, // bit offset: 1 desc: Alarm B write flag + WUTWF: u1, // bit offset: 2 desc: Wakeup timer write flag + SHPF: u1, // bit offset: 3 desc: Shift operation pending + INITS: u1, // bit offset: 4 desc: Initialization status flag + RSF: u1, // bit offset: 5 desc: Registers synchronization flag + INITF: u1, // bit offset: 6 desc: Initialization flag + INIT: u1, // bit offset: 7 desc: Initialization mode + ALRAF: u1, // bit offset: 8 desc: Alarm A flag + ALRBF: u1, // bit offset: 9 desc: Alarm B flag + WUTF: u1, // bit offset: 10 desc: Wakeup timer flag + TSF: u1, // bit offset: 11 desc: Time-stamp flag + TSOVF: u1, // bit offset: 12 desc: Time-stamp overflow flag + TAMP1F: u1, // bit offset: 13 desc: Tamper detection flag + TAMP2F: u1, // bit offset: 14 desc: RTC_TAMP2 detection flag + TAMP3F: u1, // bit offset: 15 desc: RTC_TAMP3 detection flag + RECALPF: u1, // bit offset: 16 desc: Recalibration pending Flag padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -12591,25 +14721,11 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 endpoint 3 register - pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + // byte offset: 16 prescaler register + pub const PRER = mmio(Address + 0x00000010, 32, packed struct { + PREDIV_S: u15, // bit offset: 0 desc: Synchronous prescaler factor + reserved1: u1 = 0, + PREDIV_A: u7, // bit offset: 16 desc: Asynchronous prescaler factor padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -12620,18 +14736,9 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 endpoint 4 register - pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + // byte offset: 20 wakeup timer register + pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { + WUT: u16, // bit offset: 0 desc: Wakeup auto-reload value bits padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12649,18 +14756,51 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 endpoint 5 register - pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + // byte offset: 28 alarm A register + pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + MSK1: u1, // bit offset: 7 desc: Alarm A seconds mask + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + MSK2: u1, // bit offset: 15 desc: Alarm A minutes mask + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + MSK3: u1, // bit offset: 23 desc: Alarm A hours mask + DU: u4, // bit offset: 24 desc: Date units or day in BCD format + DT: u2, // bit offset: 28 desc: Date tens in BCD format + WDSEL: u1, // bit offset: 30 desc: Week day selection + MSK4: u1, // bit offset: 31 desc: Alarm A date mask + }); + // byte offset: 32 alarm B register + pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + MSK1: u1, // bit offset: 7 desc: Alarm B seconds mask + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + MSK2: u1, // bit offset: 15 desc: Alarm B minutes mask + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation + MSK3: u1, // bit offset: 23 desc: Alarm B hours mask + DU: u4, // bit offset: 24 desc: Date units or day in BCD format + DT: u2, // bit offset: 28 desc: Date tens in BCD format + WDSEL: u1, // bit offset: 30 desc: Week day selection + MSK4: u1, // bit offset: 31 desc: Alarm B date mask + }); + // byte offset: 36 write protection register + pub const WPR = mmio(Address + 0x00000024, 32, packed struct { + KEY: u8, // bit offset: 0 desc: Write protection key + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12678,18 +14818,9 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 endpoint 6 register - pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + // byte offset: 40 sub second register + pub const SSR = mmio(Address + 0x00000028, 32, packed struct { + SS: u16, // bit offset: 0 desc: Sub second value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12707,25 +14838,38 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 endpoint 7 register - pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + // byte offset: 44 shift control register + pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { + SUBFS: u15, // bit offset: 0 desc: Subtract a fraction of a second + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADD1S: u1, // bit offset: 31 desc: Add one second + }); + // byte offset: 48 time stamp time register + pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { + SU: u4, // bit offset: 0 desc: Second units in BCD format + ST: u3, // bit offset: 4 desc: Second tens in BCD format + reserved1: u1 = 0, + MNU: u4, // bit offset: 8 desc: Minute units in BCD format + MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + reserved2: u1 = 0, + HU: u4, // bit offset: 16 desc: Hour units in BCD format + HT: u2, // bit offset: 20 desc: Hour tens in BCD format + PM: u1, // bit offset: 22 desc: AM/PM notation padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -12736,24 +14880,15 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 control register - pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { - FRES: u1, // bit offset: 0 desc: Force USB Reset - PDWN: u1, // bit offset: 1 desc: Power down - LPMODE: u1, // bit offset: 2 desc: Low-power mode - FSUSP: u1, // bit offset: 3 desc: Force suspend - RESUME: u1, // bit offset: 4 desc: Resume request - reserved3: u1 = 0, + // byte offset: 52 time stamp date register + pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { + DU: u4, // bit offset: 0 desc: Date units in BCD format + DT: u2, // bit offset: 4 desc: Date tens in BCD format reserved2: u1 = 0, reserved1: u1 = 0, - ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask - SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask - RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask - SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask - WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask - ERRM: u1, // bit offset: 13 desc: Error interrupt mask - PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask - CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + MU: u4, // bit offset: 8 desc: Month units in BCD format + MT: u1, // bit offset: 12 desc: Month tens in BCD format + WDU: u3, // bit offset: 13 desc: Week day units padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12771,21 +14906,9 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 interrupt status register - pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier - DIR: u1, // bit offset: 4 desc: Direction of transaction - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ESOF: u1, // bit offset: 8 desc: Expected start frame - SOF: u1, // bit offset: 9 desc: start of frame - RESET: u1, // bit offset: 10 desc: reset request - SUSP: u1, // bit offset: 11 desc: Suspend mode request - WKUP: u1, // bit offset: 12 desc: Wakeup - ERR: u1, // bit offset: 13 desc: Error - PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun - CTR: u1, // bit offset: 15 desc: Correct transfer + // byte offset: 56 timestamp sub second register + pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { + SS: u16, // bit offset: 0 desc: Sub second value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12803,13 +14926,16 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 frame number register - pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - FN: u11, // bit offset: 0 desc: Frame number - LSOF: u2, // bit offset: 11 desc: Lost SOF - LCK: u1, // bit offset: 13 desc: Locked - RXDM: u1, // bit offset: 14 desc: Receive data - line status - RXDP: u1, // bit offset: 15 desc: Receive data + line status + // byte offset: 60 calibration register + pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { + CALM: u9, // bit offset: 0 desc: Calibration minus + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALW16: u1, // bit offset: 13 desc: Use a 16-second calibration cycle period + CALW8: u1, // bit offset: 14 desc: Use an 8-second calibration cycle period + CALP: u1, // bit offset: 15 desc: Increase frequency of RTC by 488.5 ppm padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12827,32 +14953,28 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 device address - pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - ADD: u1, // bit offset: 0 desc: Device address - ADD1: u1, // bit offset: 1 desc: Device address - ADD2: u1, // bit offset: 2 desc: Device address - ADD3: u1, // bit offset: 3 desc: Device address - ADD4: u1, // bit offset: 4 desc: Device address - ADD5: u1, // bit offset: 5 desc: Device address - ADD6: u1, // bit offset: 6 desc: Device address - EF: u1, // bit offset: 7 desc: Enable function - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 64 tamper and alternate function configuration register + pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { + TAMP1E: u1, // bit offset: 0 desc: Tamper 1 detection enable + TAMP1TRG: u1, // bit offset: 1 desc: Active level for tamper 1 + TAMPIE: u1, // bit offset: 2 desc: Tamper interrupt enable + TAMP2E: u1, // bit offset: 3 desc: Tamper 2 detection enable + TAMP2TRG: u1, // bit offset: 4 desc: Active level for tamper 2 + TAMP3E: u1, // bit offset: 5 desc: Tamper 3 detection enable + TAMP3TRG: u1, // bit offset: 6 desc: Active level for tamper 3 + TAMPTS: u1, // bit offset: 7 desc: Activate timestamp on tamper detection event + TAMPFREQ: u3, // bit offset: 8 desc: Tamper sampling frequency + TAMPFLT: u2, // bit offset: 11 desc: Tamper filter count + TAMPPRCH: u2, // bit offset: 13 desc: Tamper precharge duration + TAMPPUDIS: u1, // bit offset: 15 desc: TAMPER pull-up disable + reserved2: u1 = 0, + reserved1: u1 = 0, + PC13VALUE: u1, // bit offset: 18 desc: PC13 value + PC13MODE: u1, // bit offset: 19 desc: PC13 mode + PC14VALUE: u1, // bit offset: 20 desc: PC14 value + PC14MODE: u1, // bit offset: 21 desc: PC 14 mode + PC15VALUE: u1, // bit offset: 22 desc: PC15 value + PC15MODE: u1, // bit offset: 23 desc: PC15 mode padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -12862,12 +14984,191 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Buffer table address - pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { + // byte offset: 68 alarm A sub second register + pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { + SS: u15, // bit offset: 0 desc: Sub seconds value + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 alarm B sub second register + pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { + SS: u15, // bit offset: 0 desc: Sub seconds value + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 80 backup register + pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 84 backup register + pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 88 backup register + pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 92 backup register + pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 96 backup register + pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 100 backup register + pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 104 backup register + pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 108 backup register + pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 112 backup register + pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 116 backup register + pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 120 backup register + pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 124 backup register + pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 128 backup register + pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 132 backup register + pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 136 backup register + pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 140 backup register + pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 144 backup register + pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 148 backup register + pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 152 backup register + pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 156 backup register + pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 160 backup register + pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 164 backup register + pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 168 backup register + pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 172 backup register + pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 176 backup register + pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 180 backup register + pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 184 backup register + pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 188 backup register + pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 192 backup register + pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 196 backup register + pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 200 backup register + pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); + // byte offset: 204 backup register + pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct { + BKP: u32, // bit offset: 0 desc: BKP + }); +}; +pub const TIM6 = extern struct { + pub const Address: u32 = 0x40001000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BTABLE: u13, // bit offset: 3 desc: Buffer table + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12885,73 +15186,22 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const I2C1 = extern struct { - pub const Address: u32 = 0x40005400; - // byte offset: 0 Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + // byte offset: 4 control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12969,16 +15219,24 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + reserved1: u1 = 0, + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12996,76 +15254,22 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler - }); - // byte offset: 20 Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection - reserved2: u1 = 0, - reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable - }); - // byte offset: 24 Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear - reserved5: u1 = 0, - reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13085,9 +15289,16 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13113,17 +15324,29 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13141,17 +15364,9 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13170,72 +15385,26 @@ pub const I2C1 = extern struct { padding1: u1 = 0, }); }; -pub const I2C2 = extern struct { - pub const Address: u32 = 0x40005800; - // byte offset: 0 Control register 1 +pub const TIM7 = extern struct { + pub const Address: u32 = 0x40001400; + // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode - reserved4: u1 = 0, + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13253,16 +15422,22 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks - reserved5: u1 = 0, + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + reserved1: u1 = 0, + MMS: u3, // bit offset: 4 desc: Master mode selection + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13280,76 +15455,22 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler - }); - // byte offset: 20 Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection - reserved2: u1 = 0, - reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable - }); - // byte offset: 24 Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear - reserved5: u1 = 0, - reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + UDE: u1, // bit offset: 8 desc: Update DMA request enable + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13369,9 +15490,16 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13397,9 +15525,16 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13425,17 +15560,29 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: Low counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF Copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13453,12 +15600,9 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const IWDG = extern struct { - pub const Address: u32 = 0x40003000; - // byte offset: 0 Key register - pub const KR = mmio(Address + 0x00000000, 32, packed struct { - KEY: u16, // bit offset: 0 desc: Key value + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Low Auto-reload value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13476,9 +15620,37 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Prescaler register - pub const PR = mmio(Address + 0x00000004, 32, packed struct { - PR: u3, // bit offset: 0 desc: Prescaler divider +}; +pub const DAC = extern struct { + pub const Address: u32 = 0x40007400; + // byte offset: 0 control register + pub const CR = mmio(Address + 0x00000000, 32, packed struct { + EN1: u1, // bit offset: 0 desc: DAC channel1 enable + BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable + TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable + TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection + WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable + MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector + DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable + DMAUDRIE1: u1, // bit offset: 13 desc: DAC channel1 DMA Underrun Interrupt enable + reserved2: u1 = 0, + reserved1: u1 = 0, + EN2: u1, // bit offset: 16 desc: DAC channel2 enable + BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable + TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable + TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection + WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable + MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector + DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable + DMAUDRIE2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun interrupt enable + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 4 software trigger register + pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { + SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger + SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -13509,9 +15681,9 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Reload register - pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - RL: u12, // bit offset: 0 desc: Watchdog counter reload value + // byte offset: 8 channel1 12-bit right-aligned data holding register + pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13533,24 +15705,13 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update - RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update - WVU: u1, // bit offset: 2 desc: Watchdog counter window value update - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 12 channel1 12-bit left aligned data holding register + pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13568,9 +15729,13 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Window register - pub const WINR = mmio(Address + 0x00000010, 32, packed struct { - WIN: u12, // bit offset: 0 desc: Watchdog counter window value + // byte offset: 16 channel1 8-bit right aligned data holding register + pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13592,17 +15757,9 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const WWDG = extern struct { - pub const Address: u32 = 0x40002c00; - // byte offset: 0 Control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - T: u7, // bit offset: 0 desc: 7-bit counter - WDGA: u1, // bit offset: 7 desc: Activation bit - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, + // byte offset: 20 channel2 12-bit right aligned data holding register + pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { + DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13624,17 +15781,13 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Configuration register - pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - W: u7, // bit offset: 0 desc: 7-bit window value - WDGTB: u2, // bit offset: 7 desc: Timer base - EWI: u1, // bit offset: 9 desc: Early wakeup interrupt - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 24 channel2 12-bit left aligned data holding register + pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13652,16 +15805,9 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - EWIF: u1, // bit offset: 0 desc: Early wakeup interrupt flag - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, + // byte offset: 28 channel2 8-bit right-aligned data holding register + pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { + DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13687,122 +15833,43 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const RTC = extern struct { - pub const Address: u32 = 0x40002800; - // byte offset: 0 time register - pub const TR = mmio(Address + 0x00000000, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 date register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format + // byte offset: 32 Dual DAC 12-bit right-aligned data holding register + pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { + DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + reserved4: u1 = 0, + reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units - YU: u4, // bit offset: 16 desc: Year units in BCD format - YT: u4, // bit offset: 20 desc: Year tens in BCD format - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - WCKSEL: u3, // bit offset: 0 desc: Wakeup clock selection - TSEDGE: u1, // bit offset: 3 desc: Time-stamp event active edge - REFCKON: u1, // bit offset: 4 desc: Reference clock detection enable (50 or 60 Hz) - BYPSHAD: u1, // bit offset: 5 desc: Bypass the shadow registers - FMT: u1, // bit offset: 6 desc: Hour format - reserved1: u1 = 0, - ALRAE: u1, // bit offset: 8 desc: Alarm A enable - ALRBE: u1, // bit offset: 9 desc: Alarm B enable - WUTE: u1, // bit offset: 10 desc: Wakeup timer enable - TSE: u1, // bit offset: 11 desc: Time stamp enable - ALRAIE: u1, // bit offset: 12 desc: Alarm A interrupt enable - ALRBIE: u1, // bit offset: 13 desc: Alarm B interrupt enable - WUTIE: u1, // bit offset: 14 desc: Wakeup timer interrupt enable - TSIE: u1, // bit offset: 15 desc: Time-stamp interrupt enable - ADD1H: u1, // bit offset: 16 desc: Add 1 hour (summer time change) - SUB1H: u1, // bit offset: 17 desc: Subtract 1 hour (winter time change) - BKP: u1, // bit offset: 18 desc: Backup - COSEL: u1, // bit offset: 19 desc: Calibration output selection - POL: u1, // bit offset: 20 desc: Output polarity - OSEL: u2, // bit offset: 21 desc: Output selection - COE: u1, // bit offset: 23 desc: Calibration output enable - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 initialization and status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - ALRAWF: u1, // bit offset: 0 desc: Alarm A write flag - ALRBWF: u1, // bit offset: 1 desc: Alarm B write flag - WUTWF: u1, // bit offset: 2 desc: Wakeup timer write flag - SHPF: u1, // bit offset: 3 desc: Shift operation pending - INITS: u1, // bit offset: 4 desc: Initialization status flag - RSF: u1, // bit offset: 5 desc: Registers synchronization flag - INITF: u1, // bit offset: 6 desc: Initialization flag - INIT: u1, // bit offset: 7 desc: Initialization mode - ALRAF: u1, // bit offset: 8 desc: Alarm A flag - ALRBF: u1, // bit offset: 9 desc: Alarm B flag - WUTF: u1, // bit offset: 10 desc: Wakeup timer flag - TSF: u1, // bit offset: 11 desc: Time-stamp flag - TSOVF: u1, // bit offset: 12 desc: Time-stamp overflow flag - TAMP1F: u1, // bit offset: 13 desc: Tamper detection flag - TAMP2F: u1, // bit offset: 14 desc: RTC_TAMP2 detection flag - TAMP3F: u1, // bit offset: 15 desc: RTC_TAMP3 detection flag - RECALPF: u1, // bit offset: 16 desc: Recalibration pending Flag - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, + DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 prescaler register - pub const PRER = mmio(Address + 0x00000010, 32, packed struct { - PREDIV_S: u15, // bit offset: 0 desc: Synchronous prescaler factor + // byte offset: 36 DUAL DAC 12-bit left aligned data holding register + pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - PREDIV_A: u7, // bit offset: 16 desc: Asynchronous prescaler factor + DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit left-aligned data + }); + // byte offset: 40 DUAL DAC 8-bit right aligned data holding register + pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { + DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -13813,9 +15880,13 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 wakeup timer register - pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { - WUT: u16, // bit offset: 0 desc: Wakeup auto-reload value bits + // byte offset: 44 channel1 data output register + pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { + DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13833,47 +15904,9 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 alarm A register - pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm A seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm A minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm A hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm A date mask - }); - // byte offset: 32 alarm B register - pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm B seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm B minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm B hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm B date mask - }); - // byte offset: 36 write protection register - pub const WPR = mmio(Address + 0x00000024, 32, packed struct { - KEY: u8, // bit offset: 0 desc: Write protection key - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, + // byte offset: 48 channel2 data output register + pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { + DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13895,9 +15928,70 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 sub second register - pub const SSR = mmio(Address + 0x00000028, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value + // byte offset: 52 status register + pub const SR = mmio(Address + 0x00000034, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DMAUDR1: u1, // bit offset: 13 desc: DAC channel1 DMA underrun flag + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + DMAUDR2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun flag + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const DBGMCU = extern struct { + pub const Address: u32 = 0xe0042000; + // byte offset: 0 MCU Device ID Code Register + pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { + DEV_ID: u12, // bit offset: 0 desc: Device Identifier + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + REV_ID: u16, // bit offset: 16 desc: Revision Identifier + }); + // byte offset: 4 Debug MCU Configuration Register + pub const CR = mmio(Address + 0x00000004, 32, packed struct { + DBG_SLEEP: u1, // bit offset: 0 desc: Debug Sleep mode + DBG_STOP: u1, // bit offset: 1 desc: Debug Stop Mode + DBG_STANDBY: u1, // bit offset: 2 desc: Debug Standby Mode + reserved2: u1 = 0, + reserved1: u1 = 0, + TRACE_IOEN: u1, // bit offset: 5 desc: Trace pin assignment control + TRACE_MODE: u2, // bit offset: 6 desc: Trace pin assignment control + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13915,17 +16009,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 shift control register - pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { - SUBFS: u15, // bit offset: 0 desc: Subtract a fraction of a second - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, + // byte offset: 8 APB Low Freeze Register + pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { + DBG_TIM2_STOP: u1, // bit offset: 0 desc: Debug Timer 2 stopped when Core is halted + DBG_TIM3_STOP: u1, // bit offset: 1 desc: Debug Timer 3 stopped when Core is halted + DBG_TIM4_STOP: u1, // bit offset: 2 desc: Debug Timer 4 stopped when Core is halted + DBG_TIM5_STOP: u1, // bit offset: 3 desc: Debug Timer 5 stopped when Core is halted + DBG_TIM6_STOP: u1, // bit offset: 4 desc: Debug Timer 6 stopped when Core is halted + DBG_TIM7_STOP: u1, // bit offset: 5 desc: Debug Timer 7 stopped when Core is halted + DBG_TIM12_STOP: u1, // bit offset: 6 desc: Debug Timer 12 stopped when Core is halted + DBG_TIM13_STOP: u1, // bit offset: 7 desc: Debug Timer 13 stopped when Core is halted + DBG_TIMER14_STOP: u1, // bit offset: 8 desc: Debug Timer 14 stopped when Core is halted + DBG_TIM18_STOP: u1, // bit offset: 9 desc: Debug Timer 18 stopped when Core is halted + DBG_RTC_STOP: u1, // bit offset: 10 desc: Debug RTC stopped when Core is halted + DBG_WWDG_STOP: u1, // bit offset: 11 desc: Debug Window Wachdog stopped when Core is halted + DBG_IWDG_STOP: u1, // bit offset: 12 desc: Debug Independent Wachdog stopped when Core is halted reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -13934,19 +16032,43 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADD1S: u1, // bit offset: 31 desc: Add one second + I2C1_SMBUS_TIMEOUT: u1, // bit offset: 21 desc: SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1, // bit offset: 22 desc: SMBUS timeout mode stopped when Core is halted + reserved10: u1 = 0, + reserved9: u1 = 0, + DBG_CAN_STOP: u1, // bit offset: 25 desc: Debug CAN stopped when core is halted + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 48 time stamp time register - pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + // byte offset: 12 APB High Freeze Register + pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation + reserved1: u1 = 0, + DBG_TIM15_STOP: u1, // bit offset: 2 desc: Debug Timer 15 stopped when Core is halted + DBG_TIM16_STOP: u1, // bit offset: 3 desc: Debug Timer 16 stopped when Core is halted + DBG_TIM17_STO: u1, // bit offset: 4 desc: Debug Timer 17 stopped when Core is halted + DBG_TIM19_STOP: u1, // bit offset: 5 desc: Debug Timer 19 stopped when Core is halted + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -13957,15 +16079,25 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 time stamp date register - pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format - reserved2: u1 = 0, +}; +pub const TIM1 = extern struct { + pub const Address: u32 = 0x40012c00; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13983,10 +16115,47 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 timestamp sub second register - pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value - padding16: u1 = 0, + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + reserved1: u1 = 0, + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + reserved2: u1 = 0, + OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + reserved3: u1 = 0, + OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + reserved4: u1 = 0, + MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14003,16 +16172,24 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 calibration register - pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { - CALM: u9, // bit offset: 0 desc: Calibration minus - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CALW16: u1, // bit offset: 13 desc: Use a 16-second calibration cycle period - CALW8: u1, // bit offset: 14 desc: Use an 8-second calibration cycle period - CALP: u1, // bit offset: 15 desc: Increase frequency of RTC by 488.5 ppm + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14026,222 +16203,59 @@ pub const RTC = extern struct { padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 tamper and alternate function configuration register - pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { - TAMP1E: u1, // bit offset: 0 desc: Tamper 1 detection enable - TAMP1TRG: u1, // bit offset: 1 desc: Active level for tamper 1 - TAMPIE: u1, // bit offset: 2 desc: Tamper interrupt enable - TAMP2E: u1, // bit offset: 3 desc: Tamper 2 detection enable - TAMP2TRG: u1, // bit offset: 4 desc: Active level for tamper 2 - TAMP3E: u1, // bit offset: 5 desc: Tamper 3 detection enable - TAMP3TRG: u1, // bit offset: 6 desc: Active level for tamper 3 - TAMPTS: u1, // bit offset: 7 desc: Activate timestamp on tamper detection event - TAMPFREQ: u3, // bit offset: 8 desc: Tamper sampling frequency - TAMPFLT: u2, // bit offset: 11 desc: Tamper filter count - TAMPPRCH: u2, // bit offset: 13 desc: Tamper precharge duration - TAMPPUDIS: u1, // bit offset: 15 desc: TAMPER pull-up disable - reserved2: u1 = 0, - reserved1: u1 = 0, - PC13VALUE: u1, // bit offset: 18 desc: PC13 value - PC13MODE: u1, // bit offset: 19 desc: PC13 mode - PC14VALUE: u1, // bit offset: 20 desc: PC14 value - PC14MODE: u1, // bit offset: 21 desc: PC 14 mode - PC15VALUE: u1, // bit offset: 22 desc: PC15 value - PC15MODE: u1, // bit offset: 23 desc: PC15 mode - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 alarm A sub second register - pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 alarm B sub second register - pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 backup register - pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 84 backup register - pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 88 backup register - pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 92 backup register - pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 96 backup register - pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 100 backup register - pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 104 backup register - pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 108 backup register - pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 112 backup register - pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 116 backup register - pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 120 backup register - pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 124 backup register - pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 128 backup register - pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 132 backup register - pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 136 backup register - pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 140 backup register - pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 144 backup register - pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 148 backup register - pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 152 backup register - pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 156 backup register - pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 160 backup register - pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 164 backup register - pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 168 backup register - pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 172 backup register - pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 176 backup register - pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 180 backup register - pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 184 backup register - pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 188 backup register - pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 192 backup register - pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 196 backup register - pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 200 backup register - pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 204 backup register - pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); -}; -pub const TIM6 = extern struct { - pub const Address: u32 = 0x40001000; - // byte offset: 0 control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag + C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + B2G: u1, // bit offset: 8 desc: Break 2 generation + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14263,22 +16277,43 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14296,9 +16331,19 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -14306,14 +16351,23 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14331,24 +16385,64 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved1: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity + CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable + CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + reserved3: u1 = 0, + reserved2: u1 = 0, + CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable + CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14366,24 +16460,29 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u16, // bit offset: 0 desc: Repetition counter value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14401,29 +16500,9 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy - }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14441,9 +16520,9 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14461,27 +16540,9 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const TIM7 = extern struct { - pub const Address: u32 = 0x40001400; - // byte offset: 0 control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14499,22 +16560,9 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14532,21 +16580,34 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + BK2F: u4, // bit offset: 20 desc: Break 2 filter + BK2E: u1, // bit offset: 24 desc: Break 2 enable + BK2P: u1, // bit offset: 25 desc: Break 2 polarity + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -14567,24 +16628,9 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14602,33 +16648,29 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, + // byte offset: 84 capture/compare mode register 3 (output mode) + pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable + OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable + OC5M: u3, // bit offset: 4 desc: Output compare 5 mode + OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + reserved4: u1 = 0, + reserved3: u1 = 0, + OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable + OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable + OC6M: u3, // bit offset: 12 desc: Output compare 6 mode + OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable + OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -14637,11 +16679,9 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value - reserved15: u1 = 0, - reserved14: u1 = 0, + // byte offset: 88 capture/compare register 5 + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -14655,11 +16695,13 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 + GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 + GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + // byte offset: 92 capture/compare register 6 + pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { + CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14677,9 +16719,58 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + // byte offset: 96 option registers + pub const OR = mmio(Address + 0x00000060, 32, packed struct { + TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const TIM20 = extern struct { + pub const Address: u32 = 0x40015000; + // byte offset: 0 control register 1 + pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { + CEN: u1, // bit offset: 0 desc: Counter enable + UDIS: u1, // bit offset: 1 desc: Update disable + URS: u1, // bit offset: 2 desc: Update request source + OPM: u1, // bit offset: 3 desc: One-pulse mode + DIR: u1, // bit offset: 4 desc: Direction + CMS: u2, // bit offset: 5 desc: Center-aligned mode selection + ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + CKD: u2, // bit offset: 8 desc: Clock division + reserved1: u1 = 0, + UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14697,51 +16788,47 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const DAC = extern struct { - pub const Address: u32 = 0x40007400; - // byte offset: 0 control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - EN1: u1, // bit offset: 0 desc: DAC channel1 enable - BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable - TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable - TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection - WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable - MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector - DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable - DMAUDRIE1: u1, // bit offset: 13 desc: DAC channel1 DMA Underrun Interrupt enable - reserved2: u1 = 0, + // byte offset: 4 control register 2 + pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { + CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control reserved1: u1 = 0, - EN2: u1, // bit offset: 16 desc: DAC channel2 enable - BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable - TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable - TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection - WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable - MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector - DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable - DMAUDRIE2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun interrupt enable + CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection + CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + MMS: u3, // bit offset: 4 desc: Master mode selection + TI1S: u1, // bit offset: 7 desc: TI1 selection + OIS1: u1, // bit offset: 8 desc: Output Idle state 1 + OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 + OIS3: u1, // bit offset: 12 desc: Output Idle state 3 + OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 + OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + reserved2: u1 = 0, + OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + reserved3: u1 = 0, + OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + reserved4: u1 = 0, + MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 software trigger register - pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger - SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, + // byte offset: 8 slave mode control register + pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { + SMS: u3, // bit offset: 0 desc: Slave mode selection + OCCS: u1, // bit offset: 3 desc: OCREF clear selection + TS: u3, // bit offset: 4 desc: Trigger selection + MSM: u1, // bit offset: 7 desc: Master/Slave mode + ETF: u4, // bit offset: 8 desc: External trigger filter + ETPS: u2, // bit offset: 12 desc: External trigger prescaler + ECE: u1, // bit offset: 14 desc: External clock enable + ETP: u1, // bit offset: 15 desc: External trigger polarity + SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14758,12 +16845,23 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 channel1 12-bit right-aligned data holding register - pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, + // byte offset: 12 DMA/Interrupt enable register + pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { + UIE: u1, // bit offset: 0 desc: Update interrupt enable + CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable + CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + COMIE: u1, // bit offset: 5 desc: COM interrupt enable + TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + BIE: u1, // bit offset: 7 desc: Break interrupt enable + UDE: u1, // bit offset: 8 desc: Update DMA request enable + CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable + CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + COMDE: u1, // bit offset: 13 desc: COM DMA request enable + TDE: u1, // bit offset: 14 desc: Trigger DMA request enable padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -14782,15 +16880,26 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 channel1 12-bit left aligned data holding register - pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { - reserved4: u1 = 0, + // byte offset: 16 status register + pub const SR = mmio(Address + 0x00000010, 32, packed struct { + UIF: u1, // bit offset: 0 desc: Update interrupt flag + CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag + CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + COMIF: u1, // bit offset: 5 desc: COM interrupt flag + TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + BIF: u1, // bit offset: 7 desc: Break interrupt flag + B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag + CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag + CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data - padding16: u1 = 0, - padding15: u1 = 0, + C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag + C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -14806,10 +16915,17 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 channel1 8-bit right aligned data holding register - pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - padding24: u1 = 0, + // byte offset: 20 event generation register + pub const EGR = mmio(Address + 0x00000014, 32, packed struct { + UG: u1, // bit offset: 0 desc: Update generation + CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation + CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation + TG: u1, // bit offset: 6 desc: Trigger generation + BG: u1, // bit offset: 7 desc: Break generation + B2G: u1, // bit offset: 8 desc: Break 2 generation padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -14834,13 +16950,43 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 channel2 12-bit right aligned data holding register - pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 24 capture/compare mode register (output mode) + pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable + OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable + OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable + OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable + OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 capture/compare mode register 1 (input mode) + pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { + CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler + IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection + IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler + IC2F: u4, // bit offset: 12 desc: Input capture 2 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14858,13 +17004,43 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 channel2 12-bit left aligned data holding register - pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { + // byte offset: 28 capture/compare mode register (output mode) + pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection + OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable + OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable + OC3M: u3, // bit offset: 4 desc: Output compare 3 mode + OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable + OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable + OC4M: u3, // bit offset: 12 desc: Output compare 4 mode + OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 28 capture/compare mode register 2 (input mode) + pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { + CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection + IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler + IC3F: u4, // bit offset: 4 desc: Input capture 3 filter + CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection + IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler + IC4F: u4, // bit offset: 12 desc: Input capture 4 filter padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14882,23 +17058,30 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 channel2 8-bit right-aligned data holding register - pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, + // byte offset: 32 capture/compare enable register + pub const CCER = mmio(Address + 0x00000020, 32, packed struct { + CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable + CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable + CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable + CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable + CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable + CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable + CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity + CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable + CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + reserved1: u1 = 0, + CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity + CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable + CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + reserved3: u1 = 0, + reserved2: u1 = 0, + CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable + CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -14910,36 +17093,49 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Dual DAC 12-bit right-aligned data holding register - pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DUAL DAC 12-bit left aligned data holding register - pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit left-aligned data - }); - // byte offset: 40 DUAL DAC 8-bit right aligned data holding register - pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14957,13 +17153,9 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 channel1 data output register - pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u16, // bit offset: 0 desc: Repetition counter value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14981,13 +17173,9 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 channel2 data output register - pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15005,59 +17193,9 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 status register - pub const SR = mmio(Address + 0x00000034, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DMAUDR1: u1, // bit offset: 13 desc: DAC channel1 DMA underrun flag - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - DMAUDR2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun flag - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const NVIC = extern struct { - pub const Address: u32 = 0xe000e000; - // byte offset: 4 Interrupt Controller Type Register - pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { - INTLINESNUM: u4, // bit offset: 0 desc: Total number of interrupt lines in groups - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15075,220 +17213,74 @@ pub const NVIC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 256 Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 260 Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 264 Interrupt Set-Enable Register - pub const ISER2 = mmio(Address + 0x00000108, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 384 Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 388 Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 392 Interrupt Clear-Enable Register - pub const ICER2 = mmio(Address + 0x00000188, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 512 Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 516 Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 520 Interrupt Set-Pending Register - pub const ISPR2 = mmio(Address + 0x00000208, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 640 Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 644 Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 648 Interrupt Clear-Pending Register - pub const ICPR2 = mmio(Address + 0x00000288, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 768 Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 772 Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 776 Interrupt Active Bit Register - pub const IABR2 = mmio(Address + 0x00000308, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 1024 Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1028 Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1032 Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1036 Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1040 Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1044 Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1048 Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1052 Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1056 Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1060 Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1064 Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1068 Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1072 Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1076 Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1080 Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1084 Interrupt Priority Register - pub const IPR15 = mmio(Address + 0x0000043c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1088 Interrupt Priority Register - pub const IPR16 = mmio(Address + 0x00000440, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1092 Interrupt Priority Register - pub const IPR17 = mmio(Address + 0x00000444, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1096 Interrupt Priority Register - pub const IPR18 = mmio(Address + 0x00000448, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1100 Interrupt Priority Register - pub const IPR19 = mmio(Address + 0x0000044c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 1104 Interrupt Priority Register - pub const IPR20 = mmio(Address + 0x00000450, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 3840 Software Triggered Interrupt Register - pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { - INTID: u9, // bit offset: 0 desc: interrupt to be triggered - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + BK2F: u4, // bit offset: 20 desc: Break 2 filter + BK2E: u1, // bit offset: 24 desc: Break 2 enable + BK2P: u1, // bit offset: 25 desc: Break 2 polarity + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -15309,33 +17301,16 @@ pub const NVIC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const FPU = extern struct { - pub const Address: u32 = 0xe000ed88; - // byte offset: 0 Coprocessor Access Control Register - pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { - CP0: u1, // bit offset: 0 desc: Access privileges for coprocessor 0 - reserved1: u1 = 0, - CP1: u1, // bit offset: 2 desc: Access privileges for coprocessor 1 - reserved2: u1 = 0, - CP2: u1, // bit offset: 4 desc: Access privileges for coprocessor 2 - reserved3: u1 = 0, - CP3: u1, // bit offset: 6 desc: Access privileges for coprocessor 3 - reserved4: u1 = 0, - CP4: u1, // bit offset: 8 desc: Access privileges for coprocessor 4 - reserved5: u1 = 0, - CP5: u1, // bit offset: 10 desc: Access privileges for coprocessor 5 - reserved6: u1 = 0, - CP6: u2, // bit offset: 12 desc: Access privileges for coprocessor 6 - CP7: u1, // bit offset: 14 desc: Access privileges for coprocessor 7 - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - CP10: u1, // bit offset: 20 desc: Access privileges for coprocessor 10 - reserved12: u1 = 0, - CP11: u1, // bit offset: 22 desc: Access privileges for coprocessor 11 + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -15346,61 +17321,21 @@ pub const FPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 428 FP Context Control Register - pub const FPCCR = mmio(Address + 0x000001ac, 32, packed struct { - LSPACT: u1, // bit offset: 0 desc: LSPACT - USER: u1, // bit offset: 1 desc: USER - reserved1: u1 = 0, - THREAD: u1, // bit offset: 3 desc: THREAD - HFRDY: u1, // bit offset: 4 desc: HFRDY - MMRDY: u1, // bit offset: 5 desc: MMRDY - BFRDY: u1, // bit offset: 6 desc: BFRDY + // byte offset: 84 capture/compare mode register 3 (output mode) + pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, - MONRDY: u1, // bit offset: 8 desc: MONRDY - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, + reserved1: u1 = 0, + OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable + OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable + OC5M: u3, // bit offset: 4 desc: Output compare 5 mode + OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable reserved4: u1 = 0, reserved3: u1 = 0, - LSPEN: u1, // bit offset: 30 desc: LSPEN - ASPEN: u1, // bit offset: 31 desc: ASPEN - }); - // byte offset: 432 FP Context Address Register - pub const FPCAR = mmio(Address + 0x000001b0, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADDRESS: u29, // bit offset: 3 desc: ADDRESS - }); - // byte offset: 436 FP Default Status Control Register - pub const FPDSCR = mmio(Address + 0x000001b4, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, + OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable + OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable + OC6M: u3, // bit offset: 12 desc: Output compare 6 mode + OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable + OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -15408,38 +17343,18 @@ pub const FPU = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RMode: u2, // bit offset: 22 desc: RMode - FZ: u1, // bit offset: 24 desc: FZ - DN: u1, // bit offset: 25 desc: DN - AHP: u1, // bit offset: 26 desc: AHP + OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 440 Media and VFP Feature Register 0 - pub const MVFR0 = mmio(Address + 0x000001b8, 32, packed struct { - A_SIMD: u4, // bit offset: 0 desc: A_SIMD registers - Single_precision: u4, // bit offset: 4 desc: Single_precision - Double_precision: u4, // bit offset: 8 desc: Double_precision - FP_exception_trapping: u4, // bit offset: 12 desc: FP exception trapping - Divide: u4, // bit offset: 16 desc: Divide - Square_root: u4, // bit offset: 20 desc: Square root - Short_vectors: u4, // bit offset: 24 desc: Short vectors - FP_rounding_modes: u4, // bit offset: 28 desc: FP rounding modes - }); - // byte offset: 444 Media and VFP Feature Register 1 - pub const MVFR1 = mmio(Address + 0x000001bc, 32, packed struct { - FtZ_mode: u4, // bit offset: 0 desc: FtZ mode - D_NaN_mode: u4, // bit offset: 4 desc: D_NaN mode - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, + // byte offset: 88 capture/compare register 5 + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -15453,38 +17368,13 @@ pub const FPU = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FP_HPFP: u4, // bit offset: 24 desc: FP HPFP - FP_fused_MAC: u4, // bit offset: 28 desc: FP fused MAC - }); -}; -pub const DBGMCU = extern struct { - pub const Address: u32 = 0xe0042000; - // byte offset: 0 MCU Device ID Code Register - pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - DEV_ID: u12, // bit offset: 0 desc: Device Identifier - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - REV_ID: u16, // bit offset: 16 desc: Revision Identifier + GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 + GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 + GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 }); - // byte offset: 4 Debug MCU Configuration Register - pub const CR = mmio(Address + 0x00000004, 32, packed struct { - DBG_SLEEP: u1, // bit offset: 0 desc: Debug Sleep mode - DBG_STOP: u1, // bit offset: 1 desc: Debug Stop Mode - DBG_STANDBY: u1, // bit offset: 2 desc: Debug Standby Mode - reserved2: u1 = 0, - reserved1: u1 = 0, - TRACE_IOEN: u1, // bit offset: 5 desc: Trace pin assignment control - TRACE_MODE: u2, // bit offset: 6 desc: Trace pin assignment control - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 92 capture/compare register 6 + pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { + CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15502,49 +17392,12 @@ pub const DBGMCU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 APB Low Freeze Register - pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { - DBG_TIM2_STOP: u1, // bit offset: 0 desc: Debug Timer 2 stopped when Core is halted - DBG_TIM3_STOP: u1, // bit offset: 1 desc: Debug Timer 3 stopped when Core is halted - DBG_TIM4_STOP: u1, // bit offset: 2 desc: Debug Timer 4 stopped when Core is halted - DBG_TIM5_STOP: u1, // bit offset: 3 desc: Debug Timer 5 stopped when Core is halted - DBG_TIM6_STOP: u1, // bit offset: 4 desc: Debug Timer 6 stopped when Core is halted - DBG_TIM7_STOP: u1, // bit offset: 5 desc: Debug Timer 7 stopped when Core is halted - DBG_TIM12_STOP: u1, // bit offset: 6 desc: Debug Timer 12 stopped when Core is halted - DBG_TIM13_STOP: u1, // bit offset: 7 desc: Debug Timer 13 stopped when Core is halted - DBG_TIMER14_STOP: u1, // bit offset: 8 desc: Debug Timer 14 stopped when Core is halted - DBG_TIM18_STOP: u1, // bit offset: 9 desc: Debug Timer 18 stopped when Core is halted - DBG_RTC_STOP: u1, // bit offset: 10 desc: Debug RTC stopped when Core is halted - DBG_WWDG_STOP: u1, // bit offset: 11 desc: Debug Window Wachdog stopped when Core is halted - DBG_IWDG_STOP: u1, // bit offset: 12 desc: Debug Independent Wachdog stopped when Core is halted - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - I2C1_SMBUS_TIMEOUT: u1, // bit offset: 21 desc: SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1, // bit offset: 22 desc: SMBUS timeout mode stopped when Core is halted - reserved10: u1 = 0, - reserved9: u1 = 0, - DBG_CAN_STOP: u1, // bit offset: 25 desc: Debug CAN stopped when core is halted - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 APB High Freeze Register - pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - DBG_TIM15_STOP: u1, // bit offset: 2 desc: Debug Timer 15 stopped when Core is halted - DBG_TIM16_STOP: u1, // bit offset: 3 desc: Debug Timer 16 stopped when Core is halted - DBG_TIM17_STO: u1, // bit offset: 4 desc: Debug Timer 17 stopped when Core is halted - DBG_TIM19_STOP: u1, // bit offset: 5 desc: Debug Timer 19 stopped when Core is halted + // byte offset: 96 option registers + pub const OR = mmio(Address + 0x00000060, 32, packed struct { + TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + padding28: u1 = 0, + padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -15573,8 +17426,8 @@ pub const DBGMCU = extern struct { padding1: u1 = 0, }); }; -pub const TIM1 = extern struct { - pub const Address: u32 = 0x40012c00; +pub const TIM8 = extern struct { + pub const Address: u32 = 0x40013400; // byte offset: 0 control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { CEN: u1, // bit offset: 0 desc: Counter enable @@ -15680,7 +17533,7 @@ pub const TIM1 = extern struct { CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: Reserved + COMDE: u1, // bit offset: 13 desc: COM DMA request enable TDE: u1, // bit offset: 14 desc: Trigger DMA request enable padding17: u1 = 0, padding16: u1 = 0, @@ -15913,11 +17766,268 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value - reserved15: u1 = 0, - reserved14: u1 = 0, + // byte offset: 36 counter + pub const CNT = mmio(Address + 0x00000024, 32, packed struct { + CNT: u16, // bit offset: 0 desc: counter value + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + UIFCPY: u1, // bit offset: 31 desc: UIF copy + }); + // byte offset: 40 prescaler + pub const PSC = mmio(Address + 0x00000028, 32, packed struct { + PSC: u16, // bit offset: 0 desc: Prescaler value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 auto-reload register + pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { + ARR: u16, // bit offset: 0 desc: Auto-reload value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 48 repetition counter register + pub const RCR = mmio(Address + 0x00000030, 32, packed struct { + REP: u16, // bit offset: 0 desc: Repetition counter value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 capture/compare register 1 + pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { + CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 capture/compare register 2 + pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { + CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 capture/compare register 3 + pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { + CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 64 capture/compare register 4 + pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { + CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 68 break and dead-time register + pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { + DTG: u8, // bit offset: 0 desc: Dead-time generator setup + LOCK: u2, // bit offset: 8 desc: Lock configuration + OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode + OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode + BKE: u1, // bit offset: 12 desc: Break enable + BKP: u1, // bit offset: 13 desc: Break polarity + AOE: u1, // bit offset: 14 desc: Automatic output enable + MOE: u1, // bit offset: 15 desc: Main output enable + BKF: u4, // bit offset: 16 desc: Break filter + BK2F: u4, // bit offset: 20 desc: Break 2 filter + BK2E: u1, // bit offset: 24 desc: Break 2 enable + BK2P: u1, // bit offset: 25 desc: Break 2 polarity + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 72 DMA control register + pub const DCR = mmio(Address + 0x00000048, 32, packed struct { + DBA: u5, // bit offset: 0 desc: DMA base address + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DBL: u5, // bit offset: 8 desc: DMA burst length + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 76 DMA address for full transfer + pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { + DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 84 capture/compare mode register 3 (output mode) + pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable + OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable + OC5M: u3, // bit offset: 4 desc: Output compare 5 mode + OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + reserved4: u1 = 0, + reserved3: u1 = 0, + OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable + OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable + OC6M: u3, // bit offset: 12 desc: Output compare 6 mode + OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable + OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 88 capture/compare register 5 + pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { + CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -15931,11 +18041,13 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 + GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 + GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + // byte offset: 92 capture/compare register 6 + pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { + CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15953,9 +18065,22 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + // byte offset: 96 option registers + pub const OR = mmio(Address + 0x00000060, 32, packed struct { + TIM8_ETR_ADC2_RMP: u2, // bit offset: 0 desc: TIM8_ETR_ADC2 remapping capability + TIM8_ETR_ADC3_RMP: u2, // bit offset: 2 desc: TIM8_ETR_ADC3 remapping capability + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15973,9 +18098,27 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value +}; +pub const ADC1 = extern struct { + pub const Address: u32 = 0x50000000; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15993,9 +18136,24 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16013,57 +18171,124 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16073,20 +18298,20 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 + padding8: u1 = 0, + padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -16094,13 +18319,59 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, + reserved1: u1 = 0, + SQ1: u5, // bit offset: 6 desc: SQ1 + reserved3: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 + reserved1: u1 = 0, + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -16121,9 +18392,9 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16141,21 +18412,66 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -16163,18 +18479,17 @@ pub const TIM1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 88 capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -16188,13 +18503,12 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 92 capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16212,22 +18526,9 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16245,25 +18546,9 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const TIM8 = extern struct { - pub const Address: u32 = 0x40013400; - // byte offset: 0 control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16281,27 +18566,35 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 - reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 - reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + AWD2CH: u18, // bit offset: 1 desc: AWD2CH + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16311,19 +18604,10 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -16338,27 +18622,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: Reserved - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { + reserved1: u1 = 0, + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -16373,26 +18641,52 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC2 = extern struct { + pub const Address: u32 = 0x50000100; + // byte offset: 0 interrupt and status register + pub const ISR = mmio(Address + 0x00000000, 32, packed struct { + ADRDY: u1, // bit offset: 0 desc: ADRDY + EOSMP: u1, // bit offset: 1 desc: EOSMP + EOC: u1, // bit offset: 2 desc: EOC + EOS: u1, // bit offset: 3 desc: EOS + OVR: u1, // bit offset: 4 desc: OVR + JEOC: u1, // bit offset: 5 desc: JEOC + JEOS: u1, // bit offset: 6 desc: JEOS + AWD1: u1, // bit offset: 7 desc: AWD1 + AWD2: u1, // bit offset: 8 desc: AWD2 + AWD3: u1, // bit offset: 9 desc: AWD3 + JQOVF: u1, // bit offset: 10 desc: JQOVF + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -16408,19 +18702,19 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation - padding23: u1 = 0, - padding22: u1 = 0, + // byte offset: 4 interrupt enable register + pub const IER = mmio(Address + 0x00000004, 32, packed struct { + ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE + EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE + EOCIE: u1, // bit offset: 2 desc: EOCIE + EOSIE: u1, // bit offset: 3 desc: EOSIE + OVRIE: u1, // bit offset: 4 desc: OVRIE + JEOCIE: u1, // bit offset: 5 desc: JEOCIE + JEOSIE: u1, // bit offset: 6 desc: JEOSIE + AWD1IE: u1, // bit offset: 7 desc: AWD1IE + AWD2IE: u1, // bit offset: 8 desc: AWD2IE + AWD3IE: u1, // bit offset: 9 desc: AWD3IE + JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -16443,19 +18737,29 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + // byte offset: 8 control register + pub const CR = mmio(Address + 0x00000008, 32, packed struct { + ADEN: u1, // bit offset: 0 desc: ADEN + ADDIS: u1, // bit offset: 1 desc: ADDIS + ADSTART: u1, // bit offset: 2 desc: ADSTART + JADSTART: u1, // bit offset: 3 desc: JADSTART + ADSTP: u1, // bit offset: 4 desc: ADSTP + JADSTP: u1, // bit offset: 5 desc: JADSTP + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16463,53 +18767,86 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 - padding7: u1 = 0, - padding6: u1 = 0, + ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN + DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD + ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF + ADCAL: u1, // bit offset: 31 desc: ADCAL + }); + // byte offset: 12 configuration register + pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { + DMAEN: u1, // bit offset: 0 desc: DMAEN + DMACFG: u1, // bit offset: 1 desc: DMACFG + reserved1: u1 = 0, + RES: u2, // bit offset: 3 desc: RES + ALIGN: u1, // bit offset: 5 desc: ALIGN + EXTSEL: u4, // bit offset: 6 desc: EXTSEL + EXTEN: u2, // bit offset: 10 desc: EXTEN + OVRMOD: u1, // bit offset: 12 desc: OVRMOD + CONT: u1, // bit offset: 13 desc: CONT + AUTDLY: u1, // bit offset: 14 desc: AUTDLY + AUTOFF: u1, // bit offset: 15 desc: AUTOFF + DISCEN: u1, // bit offset: 16 desc: DISCEN + DISCNUM: u3, // bit offset: 17 desc: DISCNUM + JDISCEN: u1, // bit offset: 20 desc: JDISCEN + JQM: u1, // bit offset: 21 desc: JQM + AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL + AWD1EN: u1, // bit offset: 23 desc: AWD1EN + JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN + JAUTO: u1, // bit offset: 25 desc: JAUTO + AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH + padding1: u1 = 0, + }); + // byte offset: 20 sample time register 1 + pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + SMP1: u3, // bit offset: 3 desc: SMP1 + SMP2: u3, // bit offset: 6 desc: SMP2 + SMP3: u3, // bit offset: 9 desc: SMP3 + SMP4: u3, // bit offset: 12 desc: SMP4 + SMP5: u3, // bit offset: 15 desc: SMP5 + SMP6: u3, // bit offset: 18 desc: SMP6 + SMP7: u3, // bit offset: 21 desc: SMP7 + SMP8: u3, // bit offset: 24 desc: SMP8 + SMP9: u3, // bit offset: 27 desc: SMP9 + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 sample time register 2 + pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { + SMP10: u3, // bit offset: 0 desc: SMP10 + SMP11: u3, // bit offset: 3 desc: SMP11 + SMP12: u3, // bit offset: 6 desc: SMP12 + SMP13: u3, // bit offset: 9 desc: SMP13 + SMP14: u3, // bit offset: 12 desc: SMP14 + SMP15: u3, // bit offset: 15 desc: SMP15 + SMP16: u3, // bit offset: 18 desc: SMP16 + SMP17: u3, // bit offset: 21 desc: SMP17 + SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, + // byte offset: 32 watchdog threshold register 1 + pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { + LT1: u12, // bit offset: 0 desc: LT1 + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + // byte offset: 36 watchdog threshold register + pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { + LT2: u8, // bit offset: 0 desc: LT2 + reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16517,7 +18854,8 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + HT2: u8, // bit offset: 16 desc: HT2 + padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16526,22 +18864,18 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 40 watchdog threshold register 3 + pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { + LT3: u8, // bit offset: 0 desc: LT3 + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16551,84 +18885,62 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + // byte offset: 48 regular sequence register 1 + pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { + L3: u4, // bit offset: 0 desc: L3 + reserved2: u1 = 0, reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, + SQ2: u5, // bit offset: 12 desc: SQ2 + reserved4: u1 = 0, + SQ3: u5, // bit offset: 18 desc: SQ3 + reserved5: u1 = 0, + SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, + // byte offset: 52 regular sequence register 2 + pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { + SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + SQ6: u5, // bit offset: 6 desc: SQ6 + reserved2: u1 = 0, + SQ7: u5, // bit offset: 12 desc: SQ7 + reserved3: u1 = 0, + SQ8: u5, // bit offset: 18 desc: SQ8 + reserved4: u1 = 0, + SQ9: u5, // bit offset: 24 desc: SQ9 + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, }); - // byte offset: 40 prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, + // byte offset: 56 regular sequence register 3 + pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { + SQ10: u5, // bit offset: 0 desc: SQ10 + reserved1: u1 = 0, + SQ11: u5, // bit offset: 6 desc: SQ11 + reserved2: u1 = 0, + SQ12: u5, // bit offset: 12 desc: SQ12 + reserved3: u1 = 0, + SQ13: u5, // bit offset: 18 desc: SQ13 + reserved4: u1 = 0, + SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + // byte offset: 60 regular sequence register 4 + pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { + SQ15: u5, // bit offset: 0 desc: SQ15 + reserved1: u1 = 0, + SQ16: u5, // bit offset: 6 desc: SQ16 + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16646,9 +18958,9 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + // byte offset: 64 regular Data Register + pub const DR = mmio(Address + 0x00000040, 32, packed struct { + regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16666,9 +18978,103 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + // byte offset: 76 injected sequence register + pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { + JL: u2, // bit offset: 0 desc: JL + JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL + JEXTEN: u2, // bit offset: 6 desc: JEXTEN + JSQ1: u5, // bit offset: 8 desc: JSQ1 + reserved1: u1 = 0, + JSQ2: u5, // bit offset: 14 desc: JSQ2 + reserved2: u1 = 0, + JSQ3: u5, // bit offset: 20 desc: JSQ3 + reserved3: u1 = 0, + JSQ4: u5, // bit offset: 26 desc: JSQ4 + padding1: u1 = 0, + }); + // byte offset: 96 offset register 1 + pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { + OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH + OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + }); + // byte offset: 100 offset register 2 + pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { + OFFSET2: u12, // bit offset: 0 desc: OFFSET2 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH + OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + }); + // byte offset: 104 offset register 3 + pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { + OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH + OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + }); + // byte offset: 108 offset register 4 + pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { + OFFSET4: u12, // bit offset: 0 desc: OFFSET4 + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH + OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN + }); + // byte offset: 128 injected data register 1 + pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { + JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16686,9 +19092,9 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + // byte offset: 132 injected data register 2 + pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { + JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16706,9 +19112,9 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + // byte offset: 136 injected data register 3 + pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { + JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16726,9 +19132,9 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + // byte offset: 140 injected data register 4 + pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { + JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16746,40 +19152,10 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address - reserved3: u1 = 0, - reserved2: u1 = 0, + // byte offset: 160 Analog Watchdog 2 Configuration Register + pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -16794,12 +19170,10 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 164 Analog Watchdog 3 Configuration Register + pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + reserved1: u1 = 0, + AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -16814,29 +19188,17 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, + // byte offset: 176 Differential Mode Selection Register 2 + pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable - reserved4: u1 = 0, - reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 + DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16845,13 +19207,9 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -16861,53 +19219,7 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 - }); - // byte offset: 92 capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 96 option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM8_ETR_ADC2_RMP: u2, // bit offset: 0 desc: TIM8_ETR_ADC2 remapping capability - TIM8_ETR_ADC3_RMP: u2, // bit offset: 2 desc: TIM8_ETR_ADC3 remapping capability - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -16919,8 +19231,8 @@ pub const TIM8 = extern struct { padding1: u1 = 0, }); }; -pub const ADC1 = extern struct { - pub const Address: u32 = 0x50000000; +pub const ADC3 = extern struct { + pub const Address: u32 = 0x50000400; // byte offset: 0 interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { ADRDY: u1, // bit offset: 0 desc: ADRDY @@ -17485,8 +19797,8 @@ pub const ADC1 = extern struct { padding1: u1 = 0, }); }; -pub const ADC2 = extern struct { - pub const Address: u32 = 0x50000100; +pub const ADC4 = extern struct { + pub const Address: u32 = 0x50000500; // byte offset: 0 interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { ADRDY: u1, // bit offset: 0 desc: ADRDY @@ -18027,21 +20339,154 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, + // byte offset: 180 Calibration Factors + pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { + CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; +pub const ADC1_2 = extern struct { + pub const Address: u32 = 0x50000300; + // byte offset: 0 ADC Common status register + pub const CSR = mmio(Address + 0x00000000, 32, packed struct { + ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST + EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST + EOC_MST: u1, // bit offset: 2 desc: EOC_MST + EOS_MST: u1, // bit offset: 3 desc: EOS_MST + OVR_MST: u1, // bit offset: 4 desc: OVR_MST + JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST + JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST + AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST + AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST + AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST + JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV + EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV + EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC + EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC + OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC + JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC + JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC + AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC + AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC + AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC + JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 ADC common control register + pub const CCR = mmio(Address + 0x00000008, 32, packed struct { + MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + reserved4: u1 = 0, + DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) + MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode + CKMODE: u2, // bit offset: 16 desc: ADC clock mode + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + VREFEN: u1, // bit offset: 22 desc: VREFINT enable + TSEN: u1, // bit offset: 23 desc: Temperature sensor enable + VBATEN: u1, // bit offset: 24 desc: VBAT enable + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 12 ADC common regular data register for dual and triple modes + pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { + RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC + RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + }); +}; +pub const ADC3_4 = extern struct { + pub const Address: u32 = 0x50000700; + // byte offset: 0 ADC Common status register + pub const CSR = mmio(Address + 0x00000000, 32, packed struct { + ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST + EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST + EOC_MST: u1, // bit offset: 2 desc: EOC_MST + EOS_MST: u1, // bit offset: 3 desc: EOS_MST + OVR_MST: u1, // bit offset: 4 desc: OVR_MST + JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST + JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST + AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST + AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST + AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST + JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D - padding9: u1 = 0, - padding8: u1 = 0, + ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV + EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV + EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC + EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC + OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC + JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC + JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC + AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC + AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC + AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC + JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 8 ADC common control register + pub const CCR = mmio(Address + 0x00000008, 32, packed struct { + MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + reserved4: u1 = 0, + DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) + MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode + CKMODE: u2, // bit offset: 16 desc: ADC clock mode + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + VREFEN: u1, // bit offset: 22 desc: VREFINT enable + TSEN: u1, // bit offset: 23 desc: Temperature sensor enable + VBATEN: u1, // bit offset: 24 desc: VBAT enable padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -18050,22 +20495,55 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); + // byte offset: 12 ADC common regular data register for dual and triple modes + pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { + RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC + RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + }); }; -pub const ADC3 = extern struct { - pub const Address: u32 = 0x50000400; - // byte offset: 0 interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF +pub const SYSCFG_COMP_OPAMP = extern struct { + pub const Address: u32 = 0x40010000; + // byte offset: 0 configuration register 1 + pub const SYSCFG_CFGR1 = mmio(Address + 0x00000000, 32, packed struct { + MEM_MODE: u2, // bit offset: 0 desc: Memory mapping selection bits + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + USB_IT_RMP: u1, // bit offset: 5 desc: USB interrupt remap + TIM1_ITR_RMP: u1, // bit offset: 6 desc: Timer 1 ITR3 selection + DAC_TRIG_RMP: u1, // bit offset: 7 desc: DAC trigger remap (when TSEL = 001) + ADC24_DMA_RMP: u1, // bit offset: 8 desc: ADC24 DMA remapping bit + reserved5: u1 = 0, + reserved4: u1 = 0, + TIM16_DMA_RMP: u1, // bit offset: 11 desc: TIM16 DMA request remapping bit + TIM17_DMA_RMP: u1, // bit offset: 12 desc: TIM17 DMA request remapping bit + TIM6_DAC1_DMA_RMP: u1, // bit offset: 13 desc: TIM6 and DAC1 DMA request remapping bit + TIM7_DAC2_DMA_RMP: u1, // bit offset: 14 desc: TIM7 and DAC2 DMA request remapping bit + reserved6: u1 = 0, + I2C_PB6_FM: u1, // bit offset: 16 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB7_FM: u1, // bit offset: 17 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB8_FM: u1, // bit offset: 18 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB9_FM: u1, // bit offset: 19 desc: Fast Mode Plus (FM+) driving capability activation bits. + I2C1_FM: u1, // bit offset: 20 desc: I2C1 Fast Mode Plus + I2C2_FM: u1, // bit offset: 21 desc: I2C2 Fast Mode Plus + ENCODER_MODE: u2, // bit offset: 22 desc: Encoder mode + reserved8: u1 = 0, + reserved7: u1 = 0, + FPU_IT: u6, // bit offset: 26 desc: Interrupt enable bits from FPU + }); + // byte offset: 4 CCM SRAM protection register + pub const SYSCFG_RCR = mmio(Address + 0x00000004, 32, packed struct { + PAGE0_WP: u1, // bit offset: 0 desc: CCM SRAM page write protection bit + PAGE1_WP: u1, // bit offset: 1 desc: CCM SRAM page write protection bit + PAGE2_WP: u1, // bit offset: 2 desc: CCM SRAM page write protection bit + PAGE3_WP: u1, // bit offset: 3 desc: CCM SRAM page write protection bit + PAGE4_WP: u1, // bit offset: 4 desc: CCM SRAM page write protection bit + PAGE5_WP: u1, // bit offset: 5 desc: CCM SRAM page write protection bit + PAGE6_WP: u1, // bit offset: 6 desc: CCM SRAM page write protection bit + PAGE7_WP: u1, // bit offset: 7 desc: CCM SRAM page write protection bit + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18088,24 +20566,12 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 8 external interrupt configuration register 1 + pub const SYSCFG_EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { + EXTI0: u4, // bit offset: 0 desc: EXTI 0 configuration bits + EXTI1: u4, // bit offset: 4 desc: EXTI 1 configuration bits + EXTI2: u4, // bit offset: 8 desc: EXTI 2 configuration bits + EXTI3: u4, // bit offset: 12 desc: EXTI 3 configuration bits padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18123,124 +20589,20 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL - }); - // byte offset: 12 configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 + // byte offset: 12 external interrupt configuration register 2 + pub const SYSCFG_EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { + EXTI4: u4, // bit offset: 0 desc: EXTI 4 configuration bits + EXTI5: u4, // bit offset: 4 desc: EXTI 5 configuration bits + EXTI6: u4, // bit offset: 8 desc: EXTI 6 configuration bits + EXTI7: u4, // bit offset: 12 desc: EXTI 7 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18250,18 +20612,20 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 + // byte offset: 16 external interrupt configuration register 3 + pub const SYSCFG_EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { + EXTI8: u4, // bit offset: 0 desc: EXTI 8 configuration bits + EXTI9: u4, // bit offset: 4 desc: EXTI 9 configuration bits + EXTI10: u4, // bit offset: 8 desc: EXTI 10 configuration bits + EXTI11: u4, // bit offset: 12 desc: EXTI 11 configuration bits + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18271,62 +20635,12 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 - reserved2: u1 = 0, - reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 - reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 - reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 - reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 - reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 - reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 - reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 - reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 - reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 - reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 - reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 - reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 - reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, + // byte offset: 20 external interrupt configuration register 4 + pub const SYSCFG_EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { + EXTI12: u4, // bit offset: 0 desc: EXTI 12 configuration bits + EXTI13: u4, // bit offset: 4 desc: EXTI 13 configuration bits + EXTI14: u4, // bit offset: 8 desc: EXTI 14 configuration bits + EXTI15: u4, // bit offset: 12 desc: EXTI 15 configuration bits padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18344,9 +20658,24 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA + // byte offset: 24 configuration register 2 + pub const SYSCFG_CFGR2 = mmio(Address + 0x00000018, 32, packed struct { + LOCUP_LOCK: u1, // bit offset: 0 desc: Cortex-M0 LOCKUP bit enable bit + SRAM_PARITY_LOCK: u1, // bit offset: 1 desc: SRAM parity lock bit + PVD_LOCK: u1, // bit offset: 2 desc: PVD lock enable bit + reserved1: u1 = 0, + BYP_ADD_PAR: u1, // bit offset: 4 desc: Bypass address bit 29 in parity calculation + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + SRAM_PEF: u1, // bit offset: 8 desc: SRAM parity flag + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18364,24 +20693,46 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 + // byte offset: 28 control and status register + pub const COMP1_CSR = mmio(Address + 0x0000001c, 32, packed struct { + COMP1EN: u1, // bit offset: 0 desc: Comparator 1 enable + COMP1_INP_DAC: u1, // bit offset: 1 desc: COMP1_INP_DAC + COMP1MODE: u2, // bit offset: 2 desc: Comparator 1 mode + COMP1INSEL: u3, // bit offset: 4 desc: Comparator 1 inverting input selection + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 + COMP1_OUT_SEL: u4, // bit offset: 10 desc: Comparator 1 output selection + reserved4: u1 = 0, + COMP1POL: u1, // bit offset: 15 desc: Comparator 1 output polarity + COMP1HYST: u2, // bit offset: 16 desc: Comparator 1 hysteresis + COMP1_BLANKING: u3, // bit offset: 18 desc: Comparator 1 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP1OUT: u1, // bit offset: 30 desc: Comparator 1 output + COMP1LOCK: u1, // bit offset: 31 desc: Comparator 1 lock + }); + // byte offset: 32 control and status register + pub const COMP2_CSR = mmio(Address + 0x00000020, 32, packed struct { + COMP2EN: u1, // bit offset: 0 desc: Comparator 2 enable + reserved1: u1 = 0, + COMP2MODE: u2, // bit offset: 2 desc: Comparator 2 mode + COMP2INSEL: u3, // bit offset: 4 desc: Comparator 2 inverting input selection + COMP2INPSEL: u1, // bit offset: 7 desc: Comparator 2 non inverted input selection reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 + COMP2INMSEL: u1, // bit offset: 9 desc: Comparator 1inverting input selection + COMP2_OUT_SEL: u4, // bit offset: 10 desc: Comparator 2 output selection reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 - padding1: u1 = 0, - }); - // byte offset: 96 offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 - reserved14: u1 = 0, + COMP2POL: u1, // bit offset: 15 desc: Comparator 2 output polarity + COMP2HYST: u2, // bit offset: 16 desc: Comparator 2 hysteresis + COMP2_BLANKING: u3, // bit offset: 18 desc: Comparator 2 blanking source reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -18392,16 +20743,74 @@ pub const ADC3 = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, + COMP2LOCK: u1, // bit offset: 31 desc: Comparator 2 lock + }); + // byte offset: 36 control and status register + pub const COMP3_CSR = mmio(Address + 0x00000024, 32, packed struct { + COMP3EN: u1, // bit offset: 0 desc: Comparator 3 enable + reserved1: u1 = 0, + COMP3MODE: u2, // bit offset: 2 desc: Comparator 3 mode + COMP3INSEL: u3, // bit offset: 4 desc: Comparator 3 inverting input selection + COMP3INPSEL: u1, // bit offset: 7 desc: Comparator 3 non inverted input selection reserved3: u1 = 0, reserved2: u1 = 0, + COMP3_OUT_SEL: u4, // bit offset: 10 desc: Comparator 3 output selection + reserved4: u1 = 0, + COMP3POL: u1, // bit offset: 15 desc: Comparator 3 output polarity + COMP3HYST: u2, // bit offset: 16 desc: Comparator 3 hysteresis + COMP3_BLANKING: u3, // bit offset: 18 desc: Comparator 3 blanking source + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + COMP3OUT: u1, // bit offset: 30 desc: Comparator 3 output + COMP3LOCK: u1, // bit offset: 31 desc: Comparator 3 lock + }); + // byte offset: 40 control and status register + pub const COMP4_CSR = mmio(Address + 0x00000028, 32, packed struct { + COMP4EN: u1, // bit offset: 0 desc: Comparator 4 enable reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + COMP4MODE: u2, // bit offset: 2 desc: Comparator 4 mode + COMP4INSEL: u3, // bit offset: 4 desc: Comparator 4 inverting input selection + COMP4INPSEL: u1, // bit offset: 7 desc: Comparator 4 non inverted input selection + reserved2: u1 = 0, + COM4WINMODE: u1, // bit offset: 9 desc: Comparator 4 window mode + COMP4_OUT_SEL: u4, // bit offset: 10 desc: Comparator 4 output selection + reserved3: u1 = 0, + COMP4POL: u1, // bit offset: 15 desc: Comparator 4 output polarity + COMP4HYST: u2, // bit offset: 16 desc: Comparator 4 hysteresis + COMP4_BLANKING: u3, // bit offset: 18 desc: Comparator 4 blanking source + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + COMP4OUT: u1, // bit offset: 30 desc: Comparator 4 output + COMP4LOCK: u1, // bit offset: 31 desc: Comparator 4 lock }); - // byte offset: 100 offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 - reserved14: u1 = 0, + // byte offset: 44 control and status register + pub const COMP5_CSR = mmio(Address + 0x0000002c, 32, packed struct { + COMP5EN: u1, // bit offset: 0 desc: Comparator 5 enable + reserved1: u1 = 0, + COMP5MODE: u2, // bit offset: 2 desc: Comparator 5 mode + COMP5INSEL: u3, // bit offset: 4 desc: Comparator 5 inverting input selection + COMP5INPSEL: u1, // bit offset: 7 desc: Comparator 5 non inverted input selection + reserved3: u1 = 0, + reserved2: u1 = 0, + COMP5_OUT_SEL: u4, // bit offset: 10 desc: Comparator 5 output selection + reserved4: u1 = 0, + COMP5POL: u1, // bit offset: 15 desc: Comparator 5 output polarity + COMP5HYST: u2, // bit offset: 16 desc: Comparator 5 hysteresis + COMP5_BLANKING: u3, // bit offset: 18 desc: Comparator 5 blanking source reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -18411,17 +20820,49 @@ pub const ADC3 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, + COMP5OUT: u1, // bit offset: 30 desc: Comparator51 output + COMP5LOCK: u1, // bit offset: 31 desc: Comparator 5 lock + }); + // byte offset: 48 control and status register + pub const COMP6_CSR = mmio(Address + 0x00000030, 32, packed struct { + COMP6EN: u1, // bit offset: 0 desc: Comparator 6 enable + reserved1: u1 = 0, + COMP6MODE: u2, // bit offset: 2 desc: Comparator 6 mode + COMP6INSEL: u3, // bit offset: 4 desc: Comparator 6 inverting input selection + COMP6INPSEL: u1, // bit offset: 7 desc: Comparator 6 non inverted input selection + reserved2: u1 = 0, + COM6WINMODE: u1, // bit offset: 9 desc: Comparator 6 window mode + COMP6_OUT_SEL: u4, // bit offset: 10 desc: Comparator 6 output selection + reserved3: u1 = 0, + COMP6POL: u1, // bit offset: 15 desc: Comparator 6 output polarity + COMP6HYST: u2, // bit offset: 16 desc: Comparator 6 hysteresis + COMP6_BLANKING: u3, // bit offset: 18 desc: Comparator 6 blanking source + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, reserved4: u1 = 0, + COMP6OUT: u1, // bit offset: 30 desc: Comparator 6 output + COMP6LOCK: u1, // bit offset: 31 desc: Comparator 6 lock + }); + // byte offset: 52 control and status register + pub const COMP7_CSR = mmio(Address + 0x00000034, 32, packed struct { + COMP7EN: u1, // bit offset: 0 desc: Comparator 7 enable + reserved1: u1 = 0, + COMP7MODE: u2, // bit offset: 2 desc: Comparator 7 mode + COMP7INSEL: u3, // bit offset: 4 desc: Comparator 7 inverting input selection + COMP7INPSEL: u1, // bit offset: 7 desc: Comparator 7 non inverted input selection reserved3: u1 = 0, reserved2: u1 = 0, - reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN - }); - // byte offset: 104 offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 - reserved14: u1 = 0, + COMP7_OUT_SEL: u4, // bit offset: 10 desc: Comparator 7 output selection + reserved4: u1 = 0, + COMP7POL: u1, // bit offset: 15 desc: Comparator 7 output polarity + COMP7HYST: u2, // bit offset: 16 desc: Comparator 7 hysteresis + COMP7_BLANKING: u3, // bit offset: 18 desc: Comparator 7 blanking source reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -18431,41 +20872,113 @@ pub const ADC3 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, + COMP7OUT: u1, // bit offset: 30 desc: Comparator 7 output + COMP7LOCK: u1, // bit offset: 31 desc: Comparator 7 lock + }); + // byte offset: 56 control register + pub const OPAMP1_CSR = mmio(Address + 0x00000038, 32, packed struct { + OPAMP1_EN: u1, // bit offset: 0 desc: OPAMP1 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP1 Non inverting input selection reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + VM_SEL: u2, // bit offset: 5 desc: OPAMP1 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP1 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP1 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 1 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 1 lock }); - // byte offset: 108 offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, + // byte offset: 60 control register + pub const OPAMP2_CSR = mmio(Address + 0x0000003c, 32, packed struct { + OPAMP2EN: u1, // bit offset: 0 desc: OPAMP2 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP2 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP2 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP2 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP2 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CAL_SEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 2 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 2 lock + }); + // byte offset: 64 control register + pub const OPAMP3_CSR = mmio(Address + 0x00000040, 32, packed struct { + OPAMP3EN: u1, // bit offset: 0 desc: OPAMP3 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP3 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP3 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP3 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP3 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 3 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 3 lock + }); + // byte offset: 68 control register + pub const OPAMP4_CSR = mmio(Address + 0x00000044, 32, packed struct { + OPAMP4EN: u1, // bit offset: 0 desc: OPAMP4 enable + FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP + VP_SEL: u2, // bit offset: 2 desc: OPAMP4 Non inverting input selection + reserved1: u1 = 0, + VM_SEL: u2, // bit offset: 5 desc: OPAMP4 inverting input selection + TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable + VMS_SEL: u1, // bit offset: 8 desc: OPAMP4 inverting input secondary selection + VPS_SEL: u2, // bit offset: 9 desc: OPAMP4 Non inverting input secondary selection + CALON: u1, // bit offset: 11 desc: Calibration mode enable + CALSEL: u2, // bit offset: 12 desc: Calibration selection + PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode + USER_TRIM: u1, // bit offset: 18 desc: User trimming enable + TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) + TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) + TSTREF: u1, // bit offset: 29 desc: TSTREF + OUTCAL: u1, // bit offset: 30 desc: OPAMP 4 ouput status flag + LOCK: u1, // bit offset: 31 desc: OPAMP 4 lock + }); +}; +pub const FMC = extern struct { + pub const Address: u32 = 0xa0000400; + // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + reserved2: u1 = 0, + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN - }); - // byte offset: 128 injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW + CCLKEN: u1, // bit offset: 20 desc: CCLKEN padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -18478,33 +20991,38 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, + // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, + // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -18518,13 +21036,38 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, + // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN + reserved1: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -18538,11 +21081,38 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { + MBKEN: u1, // bit offset: 0 desc: MBKEN + MUXEN: u1, // bit offset: 1 desc: MUXEN + MTYP: u2, // bit offset: 2 desc: MTYP + MWID: u2, // bit offset: 4 desc: MWID + FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH - padding13: u1 = 0, + BURSTEN: u1, // bit offset: 8 desc: BURSTEN + WAITPOL: u1, // bit offset: 9 desc: WAITPOL + WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD + WAITCFG: u1, // bit offset: 11 desc: WAITCFG + WREN: u1, // bit offset: 12 desc: WREN + WAITEN: u1, // bit offset: 13 desc: WAITEN + EXTMOD: u1, // bit offset: 14 desc: EXTMOD + ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -18556,11 +21126,31 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { + // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: BUSTURN + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 96 PC Card/NAND Flash control register 2 + pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH - padding13: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN + reserved3: u1 = 0, + reserved2: u1 = 0, + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -18574,11 +21164,27 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + // byte offset: 100 FIFO status and interrupt register 2 + pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18593,19 +21199,40 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, + // byte offset: 104 Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx + }); + // byte offset: 108 Attribute memory space timing register 2 + pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: ATTSETx + ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx + ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx + ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx + }); + // byte offset: 116 ECC result register 2 + pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { + ECCx: u32, // bit offset: 0 desc: ECCx + }); + // byte offset: 128 PC Card/NAND Flash control register 3 + pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { + reserved1: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -18616,22 +21243,19 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const ADC4 = extern struct { - pub const Address: u32 = 0x50000500; - // byte offset: 0 interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF + // byte offset: 132 FIFO status and interrupt register 3 + pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18654,19 +21278,63 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE + // byte offset: 136 Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx + }); + // byte offset: 140 Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: ATTSETx + ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx + ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx + ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx + }); + // byte offset: 148 ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { + ECCx: u32, // bit offset: 0 desc: ECCx + }); + // byte offset: 160 PC Card/NAND Flash control register 4 + pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { + reserved1: u1 = 0, + PWAITEN: u1, // bit offset: 1 desc: PWAITEN + PBKEN: u1, // bit offset: 2 desc: PBKEN + PTYP: u1, // bit offset: 3 desc: PTYP + PWID: u2, // bit offset: 4 desc: PWID + ECCEN: u1, // bit offset: 6 desc: ECCEN + reserved3: u1 = 0, + reserved2: u1 = 0, + TCLR: u4, // bit offset: 9 desc: TCLR + TAR: u4, // bit offset: 13 desc: TAR + ECCPS: u3, // bit offset: 17 desc: ECCPS + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 164 FIFO status and interrupt register 4 + pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { + IRS: u1, // bit offset: 0 desc: IRS + ILS: u1, // bit offset: 1 desc: ILS + IFS: u1, // bit offset: 2 desc: IFS + IREN: u1, // bit offset: 3 desc: IREN + ILEN: u1, // bit offset: 4 desc: ILEN + IFEN: u1, // bit offset: 5 desc: IFEN + FEMPT: u1, // bit offset: 6 desc: FEMPT + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18689,264 +21357,308 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL + // byte offset: 168 Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { + MEMSETx: u8, // bit offset: 0 desc: MEMSETx + MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx + MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx + MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx }); - // byte offset: 12 configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, + // byte offset: 172 Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { + ATTSETx: u8, // bit offset: 0 desc: ATTSETx + ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx + ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx + ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx }); - // byte offset: 20 sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 176 I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { + IOSETx: u8, // bit offset: 0 desc: IOSETx + IOWAITx: u8, // bit offset: 8 desc: IOWAITx + IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx + IOHIZx: u8, // bit offset: 24 desc: IOHIZx }); - // byte offset: 24 sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, + // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 - padding4: u1 = 0, - padding3: u1 = 0, + // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, + // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, + // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { + ADDSET: u4, // bit offset: 0 desc: ADDSET + ADDHLD: u4, // bit offset: 4 desc: ADDHLD + DATAST: u8, // bit offset: 8 desc: DATAST + BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration + CLKDIV: u4, // bit offset: 20 desc: CLKDIV + DATLAT: u4, // bit offset: 24 desc: DATLAT + ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 - reserved2: u1 = 0, - reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 - reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 - reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 - reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, +}; +pub const NVIC = extern struct { + pub const Address: u32 = 0xe000e100; + // byte offset: 0 Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 4 Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 8 Interrupt Set-Enable Register + pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct { + SETENA: u32, // bit offset: 0 desc: SETENA + }); + // byte offset: 128 Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 132 Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 136 Interrupt Clear-Enable Register + pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct { + CLRENA: u32, // bit offset: 0 desc: CLRENA + }); + // byte offset: 256 Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 260 Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 264 Interrupt Set-Pending Register + pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct { + SETPEND: u32, // bit offset: 0 desc: SETPEND + }); + // byte offset: 384 Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 388 Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 392 Interrupt Clear-Pending Register + pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct { + CLRPEND: u32, // bit offset: 0 desc: CLRPEND + }); + // byte offset: 512 Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 516 Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 520 Interrupt Active Bit Register + pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct { + ACTIVE: u32, // bit offset: 0 desc: ACTIVE + }); + // byte offset: 768 Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 772 Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 776 Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 780 Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 784 Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 788 Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 792 Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 796 Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 800 Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 804 Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 808 Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 812 Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 816 Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 }); - // byte offset: 52 regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 - reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 - reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 - reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 - reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 820 Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 }); - // byte offset: 56 regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 - reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 - reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 - reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 - reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 824 Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 }); - // byte offset: 60 regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 - reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 828 Interrupt Priority Register + pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 }); - // byte offset: 64 regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + // byte offset: 832 Interrupt Priority Register + pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 }); - // byte offset: 76 injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 + // byte offset: 836 Interrupt Priority Register + pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 840 Interrupt Priority Register + pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 844 Interrupt Priority Register + pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); + // byte offset: 848 Interrupt Priority Register + pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct { + IPR_N0: u8, // bit offset: 0 desc: IPR_N0 + IPR_N1: u8, // bit offset: 8 desc: IPR_N1 + IPR_N2: u8, // bit offset: 16 desc: IPR_N2 + IPR_N3: u8, // bit offset: 24 desc: IPR_N3 + }); +}; +pub const FPU = extern struct { + pub const Address: u32 = 0xe000ef34; + // byte offset: 0 Floating-point context control register + pub const FPCCR = mmio(Address + 0x00000000, 32, packed struct { + LSPACT: u1, // bit offset: 0 desc: LSPACT + USER: u1, // bit offset: 1 desc: USER reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 + THREAD: u1, // bit offset: 3 desc: THREAD + HFRDY: u1, // bit offset: 4 desc: HFRDY + MMRDY: u1, // bit offset: 5 desc: MMRDY + BFRDY: u1, // bit offset: 6 desc: BFRDY reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 - reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 - padding1: u1 = 0, - }); - // byte offset: 96 offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 + MONRDY: u1, // bit offset: 8 desc: MONRDY + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18959,34 +21671,28 @@ pub const ADC4 = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN + LSPEN: u1, // bit offset: 30 desc: LSPEN + ASPEN: u1, // bit offset: 31 desc: ASPEN }); - // byte offset: 100 offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, + // byte offset: 4 Floating-point context address register + pub const FPCAR = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN + ADDRESS: u29, // bit offset: 3 desc: Location of unpopulated floating-point }); - // byte offset: 104 offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 + // byte offset: 8 Floating-point status control register + pub const FPSCR = mmio(Address + 0x00000008, 32, packed struct { + IOC: u1, // bit offset: 0 desc: Invalid operation cumulative exception bit + DZC: u1, // bit offset: 1 desc: Division by zero cumulative exception bit. + OFC: u1, // bit offset: 2 desc: Overflow cumulative exception bit + UFC: u1, // bit offset: 3 desc: Underflow cumulative exception bit + IXC: u1, // bit offset: 4 desc: Inexact cumulative exception bit + reserved2: u1 = 0, + reserved1: u1 = 0, + IDC: u1, // bit offset: 7 desc: Input denormal cumulative exception bit. + reserved16: u1 = 0, + reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18999,21 +21705,22 @@ pub const ADC4 = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN + RMode: u2, // bit offset: 22 desc: Rounding Mode control field + FZ: u1, // bit offset: 24 desc: Flush-to-zero mode control bit: + DN: u1, // bit offset: 25 desc: Default NaN mode control bit + AHP: u1, // bit offset: 26 desc: Alternative half-precision control bit + reserved17: u1 = 0, + V: u1, // bit offset: 28 desc: Overflow condition code flag + C: u1, // bit offset: 29 desc: Carry condition code flag + Z: u1, // bit offset: 30 desc: Zero condition code flag + N: u1, // bit offset: 31 desc: Negative condition code flag }); - // byte offset: 108 offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, +}; +pub const MPU = extern struct { + pub const Address: u32 = 0xe000ed90; + // byte offset: 0 MPU type register + pub const MPU_TYPER = mmio(Address + 0x00000000, 32, packed struct { + SEPARATE: u1, // bit offset: 0 desc: Separate flag reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -19021,40 +21728,8 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN - }); - // byte offset: 128 injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 132 injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + DREGION: u8, // bit offset: 8 desc: Number of MPU data regions + IREGION: u8, // bit offset: 16 desc: Number of MPU instruction regions padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19064,9 +21739,24 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 + // byte offset: 4 MPU control register + pub const MPU_CTRL = mmio(Address + 0x00000004, 32, packed struct { + ENABLE: u1, // bit offset: 0 desc: Enables the MPU + HFNMIENA: u1, // bit offset: 1 desc: Enables the operation of MPU during hard fault + PRIVDEFENA: u1, // bit offset: 2 desc: Enable priviliged software access to default memory map + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19084,9 +21774,17 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 + // byte offset: 8 MPU region number register + pub const MPU_RNR = mmio(Address + 0x00000008, 32, packed struct { + REGION: u8, // bit offset: 0 desc: MPU region + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19104,28 +21802,56 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { + // byte offset: 12 MPU region base address register + pub const MPU_RBAR = mmio(Address + 0x0000000c, 32, packed struct { + REGION: u4, // bit offset: 0 desc: MPU region field + VALID: u1, // bit offset: 4 desc: MPU region number valid + ADDR: u27, // bit offset: 5 desc: Region base address field + }); + // byte offset: 16 MPU region attribute and size register + pub const MPU_RASR = mmio(Address + 0x00000010, 32, packed struct { + ENABLE: u1, // bit offset: 0 desc: Region enable bit. + SIZE: u5, // bit offset: 1 desc: Size of the MPU protection region + reserved2: u1 = 0, reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, + SRD: u8, // bit offset: 8 desc: Subregion disable bits + B: u1, // bit offset: 16 desc: memory attribute + C: u1, // bit offset: 17 desc: memory attribute + S: u1, // bit offset: 18 desc: Shareable memory attribute + TEX: u3, // bit offset: 19 desc: memory attribute + reserved4: u1 = 0, + reserved3: u1 = 0, + AP: u3, // bit offset: 24 desc: Access permission + reserved5: u1 = 0, + XN: u1, // bit offset: 28 desc: Instruction access disable bit padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { +}; +pub const STK = extern struct { + pub const Address: u32 = 0xe000e010; + // byte offset: 0 SysTick control and status register + pub const CTRL = mmio(Address + 0x00000000, 32, packed struct { + ENABLE: u1, // bit offset: 0 desc: Counter enable + TICKINT: u1, // bit offset: 1 desc: SysTick exception request enable + CLKSOURCE: u1, // bit offset: 2 desc: Clock source selection + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH + COUNTFLAG: u1, // bit offset: 16 desc: COUNTFLAG + padding15: u1 = 0, + padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19140,16 +21866,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 4 SysTick reload value register + pub const LOAD = mmio(Address + 0x00000004, 32, packed struct { + RELOAD: u24, // bit offset: 0 desc: RELOAD value padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19159,20 +21878,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D - padding9: u1 = 0, + // byte offset: 8 SysTick current value register + pub const VAL = mmio(Address + 0x00000008, 32, packed struct { + CURRENT: u24, // bit offset: 0 desc: Current counter value padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19182,187 +21890,130 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); -}; -pub const ADC1_2 = extern struct { - pub const Address: u32 = 0x50000300; - // byte offset: 0 ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST + // byte offset: 12 SysTick calibration value register + pub const CALIB = mmio(Address + 0x0000000c, 32, packed struct { + TENMS: u24, // bit offset: 0 desc: Calibration value + reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, + SKEW: u1, // bit offset: 30 desc: SKEW flag: Indicates whether the TENMS value is exact + NOREF: u1, // bit offset: 31 desc: NOREF flag. Reads as zero }); - // byte offset: 8 ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection - reserved3: u1 = 0, +}; +pub const SCB = extern struct { + pub const Address: u32 = 0xe000ed00; + // byte offset: 0 CPUID base register + pub const CPUID = mmio(Address + 0x00000000, 32, packed struct { + Revision: u4, // bit offset: 0 desc: Revision number + PartNo: u12, // bit offset: 4 desc: Part number of the processor + Constant: u4, // bit offset: 16 desc: Reads as 0xF + Variant: u4, // bit offset: 20 desc: Variant number + Implementer: u8, // bit offset: 24 desc: Implementer code + }); + // byte offset: 4 Interrupt control and state register + pub const ICSR = mmio(Address + 0x00000004, 32, packed struct { + VECTACTIVE: u9, // bit offset: 0 desc: Active vector reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + RETTOBASE: u1, // bit offset: 11 desc: Return to base level + VECTPENDING: u7, // bit offset: 12 desc: Pending vector + reserved5: u1 = 0, reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode - reserved8: u1 = 0, + reserved3: u1 = 0, + ISRPENDING: u1, // bit offset: 22 desc: Interrupt pending flag reserved7: u1 = 0, reserved6: u1 = 0, - reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + PENDSTCLR: u1, // bit offset: 25 desc: SysTick exception clear-pending bit + PENDSTSET: u1, // bit offset: 26 desc: SysTick exception set-pending bit + PENDSVCLR: u1, // bit offset: 27 desc: PendSV clear-pending bit + PENDSVSET: u1, // bit offset: 28 desc: PendSV set-pending bit + reserved9: u1 = 0, + reserved8: u1 = 0, + NMIPENDSET: u1, // bit offset: 31 desc: NMI set-pending bit. }); -}; -pub const ADC3_4 = extern struct { - pub const Address: u32 = 0x50000700; - // byte offset: 0 ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST + // byte offset: 8 Vector table offset register + pub const VTOR = mmio(Address + 0x00000008, 32, packed struct { + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, + TBLOFF: u21, // bit offset: 9 desc: Vector table base offset field padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + // byte offset: 12 Application interrupt and reset control register + pub const AIRCR = mmio(Address + 0x0000000c, 32, packed struct { + VECTRESET: u1, // bit offset: 0 desc: VECTRESET + VECTCLRACTIVE: u1, // bit offset: 1 desc: VECTCLRACTIVE + SYSRESETREQ: u1, // bit offset: 2 desc: SYSRESETREQ + reserved5: u1 = 0, + reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases - reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode + PRIGROUP: u3, // bit offset: 8 desc: PRIGROUP + reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable + ENDIANESS: u1, // bit offset: 15 desc: ENDIANESS + VECTKEYSTAT: u16, // bit offset: 16 desc: Register key + }); + // byte offset: 16 System control register + pub const SCR = mmio(Address + 0x00000010, 32, packed struct { + reserved1: u1 = 0, + SLEEPONEXIT: u1, // bit offset: 1 desc: SLEEPONEXIT + SLEEPDEEP: u1, // bit offset: 2 desc: SLEEPDEEP + reserved2: u1 = 0, + SEVEONPEND: u1, // bit offset: 4 desc: Send Event on Pending bit + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC - }); -}; -pub const SYSCFG = extern struct { - pub const Address: u32 = 0x40010000; - // byte offset: 0 configuration register 1 - pub const CFGR1 = mmio(Address + 0x00000000, 32, packed struct { - MEM_MODE: u2, // bit offset: 0 desc: Memory mapping selection bits - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - USB_IT_RMP: u1, // bit offset: 5 desc: USB interrupt remap - TIM1_ITR_RMP: u1, // bit offset: 6 desc: Timer 1 ITR3 selection - DAC_TRIG_RMP: u1, // bit offset: 7 desc: DAC trigger remap (when TSEL = 001) - ADC24_DMA_RMP: u1, // bit offset: 8 desc: ADC24 DMA remapping bit - reserved5: u1 = 0, - reserved4: u1 = 0, - TIM16_DMA_RMP: u1, // bit offset: 11 desc: TIM16 DMA request remapping bit - TIM17_DMA_RMP: u1, // bit offset: 12 desc: TIM17 DMA request remapping bit - TIM6_DAC1_DMA_RMP: u1, // bit offset: 13 desc: TIM6 and DAC1 DMA request remapping bit - TIM7_DAC2_DMA_RMP: u1, // bit offset: 14 desc: TIM7 and DAC2 DMA request remapping bit - reserved6: u1 = 0, - I2C_PB6_FM: u1, // bit offset: 16 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB7_FM: u1, // bit offset: 17 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB8_FM: u1, // bit offset: 18 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB9_FM: u1, // bit offset: 19 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C1_FM: u1, // bit offset: 20 desc: I2C1 Fast Mode Plus - I2C2_FM: u1, // bit offset: 21 desc: I2C2 Fast Mode Plus - ENCODER_MODE: u2, // bit offset: 22 desc: Encoder mode - reserved8: u1 = 0, - reserved7: u1 = 0, - FPU_IT: u6, // bit offset: 26 desc: Interrupt enable bits from FPU - }); - // byte offset: 4 CCM SRAM protection register - pub const RCR = mmio(Address + 0x00000004, 32, packed struct { - PAGE0_WP: u1, // bit offset: 0 desc: CCM SRAM page write protection bit - PAGE1_WP: u1, // bit offset: 1 desc: CCM SRAM page write protection bit - PAGE2_WP: u1, // bit offset: 2 desc: CCM SRAM page write protection bit - PAGE3_WP: u1, // bit offset: 3 desc: CCM SRAM page write protection bit - PAGE4_WP: u1, // bit offset: 4 desc: CCM SRAM page write protection bit - PAGE5_WP: u1, // bit offset: 5 desc: CCM SRAM page write protection bit - PAGE6_WP: u1, // bit offset: 6 desc: CCM SRAM page write protection bit - PAGE7_WP: u1, // bit offset: 7 desc: CCM SRAM page write protection bit - padding24: u1 = 0, - padding23: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 20 Configuration and control register + pub const CCR = mmio(Address + 0x00000014, 32, packed struct { + NONBASETHRDENA: u1, // bit offset: 0 desc: Configures how the processor enters Thread mode + USERSETMPEND: u1, // bit offset: 1 desc: USERSETMPEND + reserved1: u1 = 0, + UNALIGN__TRP: u1, // bit offset: 3 desc: UNALIGN_ TRP + DIV_0_TRP: u1, // bit offset: 4 desc: DIV_0_TRP + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + BFHFNMIGN: u1, // bit offset: 8 desc: BFHFNMIGN + STKALIGN: u1, // bit offset: 9 desc: STKALIGN padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -19386,20 +22037,11 @@ pub const SYSCFG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 external interrupt configuration register 1 - pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - EXTI0: u4, // bit offset: 0 desc: EXTI 0 configuration bits - EXTI1: u4, // bit offset: 4 desc: EXTI 1 configuration bits - EXTI2: u4, // bit offset: 8 desc: EXTI 2 configuration bits - EXTI3: u4, // bit offset: 12 desc: EXTI 3 configuration bits - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, + // byte offset: 24 System handler priority registers + pub const SHPR1 = mmio(Address + 0x00000018, 32, packed struct { + PRI_4: u8, // bit offset: 0 desc: Priority of system handler 4 + PRI_5: u8, // bit offset: 8 desc: Priority of system handler 5 + PRI_6: u8, // bit offset: 16 desc: Priority of system handler 6 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19409,15 +22051,76 @@ pub const SYSCFG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 external interrupt configuration register 2 - pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - EXTI4: u4, // bit offset: 0 desc: EXTI 4 configuration bits - EXTI5: u4, // bit offset: 4 desc: EXTI 5 configuration bits - EXTI6: u4, // bit offset: 8 desc: EXTI 6 configuration bits - EXTI7: u4, // bit offset: 12 desc: EXTI 7 configuration bits - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, + // byte offset: 28 System handler priority registers + pub const SHPR2 = mmio(Address + 0x0000001c, 32, packed struct { + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRI_11: u8, // bit offset: 24 desc: Priority of system handler 11 + }); + // byte offset: 32 System handler priority registers + pub const SHPR3 = mmio(Address + 0x00000020, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + PRI_14: u8, // bit offset: 16 desc: Priority of system handler 14 + PRI_15: u8, // bit offset: 24 desc: Priority of system handler 15 + }); + // byte offset: 36 System handler control and state register + pub const SHCRS = mmio(Address + 0x00000024, 32, packed struct { + MEMFAULTACT: u1, // bit offset: 0 desc: Memory management fault exception active bit + BUSFAULTACT: u1, // bit offset: 1 desc: Bus fault exception active bit + reserved1: u1 = 0, + USGFAULTACT: u1, // bit offset: 3 desc: Usage fault exception active bit + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + SVCALLACT: u1, // bit offset: 7 desc: SVC call active bit + MONITORACT: u1, // bit offset: 8 desc: Debug monitor active bit + reserved5: u1 = 0, + PENDSVACT: u1, // bit offset: 10 desc: PendSV exception active bit + SYSTICKACT: u1, // bit offset: 11 desc: SysTick exception active bit + USGFAULTPENDED: u1, // bit offset: 12 desc: Usage fault exception pending bit + MEMFAULTPENDED: u1, // bit offset: 13 desc: Memory management fault exception pending bit + BUSFAULTPENDED: u1, // bit offset: 14 desc: Bus fault exception pending bit + SVCALLPENDED: u1, // bit offset: 15 desc: SVC call pending bit + MEMFAULTENA: u1, // bit offset: 16 desc: Memory management fault enable bit + BUSFAULTENA: u1, // bit offset: 17 desc: Bus fault enable bit + USGFAULTENA: u1, // bit offset: 18 desc: Usage fault enable bit padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19432,12 +22135,101 @@ pub const SYSCFG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 external interrupt configuration register 3 - pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - EXTI8: u4, // bit offset: 0 desc: EXTI 8 configuration bits - EXTI9: u4, // bit offset: 4 desc: EXTI 9 configuration bits - EXTI10: u4, // bit offset: 8 desc: EXTI 10 configuration bits - EXTI11: u4, // bit offset: 12 desc: EXTI 11 configuration bits + // byte offset: 40 Configurable fault status register + pub const CFSR_UFSR_BFSR_MMFSR = mmio(Address + 0x00000028, 32, packed struct { + reserved1: u1 = 0, + IACCVIOL: u1, // bit offset: 1 desc: Instruction access violation flag + reserved2: u1 = 0, + MUNSTKERR: u1, // bit offset: 3 desc: Memory manager fault on unstacking for a return from exception + MSTKERR: u1, // bit offset: 4 desc: Memory manager fault on stacking for exception entry. + MLSPERR: u1, // bit offset: 5 desc: MLSPERR + reserved3: u1 = 0, + MMARVALID: u1, // bit offset: 7 desc: Memory Management Fault Address Register (MMAR) valid flag + IBUSERR: u1, // bit offset: 8 desc: Instruction bus error + PRECISERR: u1, // bit offset: 9 desc: Precise data bus error + IMPRECISERR: u1, // bit offset: 10 desc: Imprecise data bus error + UNSTKERR: u1, // bit offset: 11 desc: Bus fault on unstacking for a return from exception + STKERR: u1, // bit offset: 12 desc: Bus fault on stacking for exception entry + LSPERR: u1, // bit offset: 13 desc: Bus fault on floating-point lazy state preservation + reserved4: u1 = 0, + BFARVALID: u1, // bit offset: 15 desc: Bus Fault Address Register (BFAR) valid flag + UNDEFINSTR: u1, // bit offset: 16 desc: Undefined instruction usage fault + INVSTATE: u1, // bit offset: 17 desc: Invalid state usage fault + INVPC: u1, // bit offset: 18 desc: Invalid PC load usage fault + NOCP: u1, // bit offset: 19 desc: No coprocessor usage fault. + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + UNALIGNED: u1, // bit offset: 24 desc: Unaligned access usage fault + DIVBYZERO: u1, // bit offset: 25 desc: Divide by zero usage fault + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + // byte offset: 44 Hard fault status register + pub const HFSR = mmio(Address + 0x0000002c, 32, packed struct { + reserved1: u1 = 0, + VECTTBL: u1, // bit offset: 1 desc: Vector table hard fault + reserved29: u1 = 0, + reserved28: u1 = 0, + reserved27: u1 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + FORCED: u1, // bit offset: 30 desc: Forced hard fault + DEBUG_VT: u1, // bit offset: 31 desc: Reserved for Debug use + }); + // byte offset: 52 Memory management fault address register + pub const MMFAR = mmio(Address + 0x00000034, 32, packed struct { + MMFAR: u32, // bit offset: 0 desc: Memory management fault address + }); + // byte offset: 56 Bus fault address register + pub const BFAR = mmio(Address + 0x00000038, 32, packed struct { + BFAR: u32, // bit offset: 0 desc: Bus fault address + }); + // byte offset: 60 Auxiliary fault status register + pub const AFSR = mmio(Address + 0x0000003c, 32, packed struct { + IMPDEF: u32, // bit offset: 0 desc: Implementation defined + }); +}; +pub const NVIC_STIR = extern struct { + pub const Address: u32 = 0xe000ef00; + // byte offset: 0 Software trigger interrupt register + pub const STIR = mmio(Address + 0x00000000, 32, packed struct { + INTID: u9, // bit offset: 0 desc: Software generated interrupt ID + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19455,20 +22247,32 @@ pub const SYSCFG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 external interrupt configuration register 4 - pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - EXTI12: u4, // bit offset: 0 desc: EXTI 12 configuration bits - EXTI13: u4, // bit offset: 4 desc: EXTI 13 configuration bits - EXTI14: u4, // bit offset: 8 desc: EXTI 14 configuration bits - EXTI15: u4, // bit offset: 12 desc: EXTI 15 configuration bits - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, +}; +pub const FPU_CPACR = extern struct { + pub const Address: u32 = 0xe000ed88; + // byte offset: 0 Coprocessor access control register + pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + CP: u4, // bit offset: 20 desc: CP padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19478,18 +22282,21 @@ pub const SYSCFG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 configuration register 2 - pub const CFGR2 = mmio(Address + 0x00000018, 32, packed struct { - LOCUP_LOCK: u1, // bit offset: 0 desc: Cortex-M0 LOCKUP bit enable bit - SRAM_PARITY_LOCK: u1, // bit offset: 1 desc: SRAM parity lock bit - PVD_LOCK: u1, // bit offset: 2 desc: PVD lock enable bit - reserved1: u1 = 0, - BYP_ADD_PAR: u1, // bit offset: 4 desc: Bypass address bit 29 in parity calculation +}; +pub const SCB_ACTRL = extern struct { + pub const Address: u32 = 0xe000e008; + // byte offset: 0 Auxiliary control register + pub const ACTRL = mmio(Address + 0x00000000, 32, packed struct { + DISMCYCINT: u1, // bit offset: 0 desc: DISMCYCINT + DISDEFWBUF: u1, // bit offset: 1 desc: DISDEFWBUF + DISFOLD: u1, // bit offset: 2 desc: DISFOLD + reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SRAM_PEF: u1, // bit offset: 8 desc: SRAM parity flag - padding23: u1 = 0, + reserved1: u1 = 0, + DISFPCA: u1, // bit offset: 8 desc: DISFPCA + DISOOFP: u1, // bit offset: 9 desc: DISOOFP padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -19514,86 +22321,326 @@ pub const SYSCFG = extern struct { padding1: u1 = 0, }); }; -pub const OPAMP = extern struct { - pub const Address: u32 = 0x40010038; - // byte offset: 0 OPAMP1 control register - pub const OPAMP1_CR = mmio(Address + 0x00000000, 32, packed struct { - OPAMP1_EN: u1, // bit offset: 0 desc: OPAMP1 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP1 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP1 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP1 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP1 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 1 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 1 lock - }); - // byte offset: 4 OPAMP2 control register - pub const OPAMP2_CR = mmio(Address + 0x00000004, 32, packed struct { - OPAMP2EN: u1, // bit offset: 0 desc: OPAMP2 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP2 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP2 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP2 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP2 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CAL_SEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 2 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 2 lock - }); - // byte offset: 8 OPAMP3 control register - pub const OPAMP3_CR = mmio(Address + 0x00000008, 32, packed struct { - OPAMP3EN: u1, // bit offset: 0 desc: OPAMP3 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP3 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP3 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP3 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP3 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 3 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 3 lock - }); - // byte offset: 12 OPAMP4 control register - pub const OPAMP4_CR = mmio(Address + 0x0000000c, 32, packed struct { - OPAMP4EN: u1, // bit offset: 0 desc: OPAMP4 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP4 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP4 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP4 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP4 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 4 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 4 lock - }); + +const std = @import("std"); +const root = @import("root"); +const cpu = @import("cpu"); +const config = @import("microzig-config"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler("NMI"), + HardFault: InterruptVector = makeUnhandledHandler("HardFault"), + MemManage: InterruptVector = makeUnhandledHandler("MemManage"), + BusFault: InterruptVector = makeUnhandledHandler("BusFault"), + UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler("SVCall"), + DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler("PendSV"), + SysTick: InterruptVector = makeUnhandledHandler("SysTick"), + + /// Window Watchdog interrupt + WWDG: InterruptVector = makeUnhandledHandler("WWDG"), + + /// PVD through EXTI line detection interrupt + PVD: InterruptVector = makeUnhandledHandler("PVD"), + + /// Tamper and TimeStamp interrupts + TAMP_STAMP: InterruptVector = makeUnhandledHandler("TAMP_STAMP"), + + /// RTC Wakeup interrupt through the EXTI line + RTC_WKUP: InterruptVector = makeUnhandledHandler("RTC_WKUP"), + + /// Flash global interrupt + FLASH: InterruptVector = makeUnhandledHandler("FLASH"), + + /// RCC global interrupt + RCC: InterruptVector = makeUnhandledHandler("RCC"), + + /// EXTI Line0 interrupt + EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), + + /// EXTI Line3 interrupt + EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), + + /// EXTI Line2 and Touch sensing interrupts + EXTI2_TSC: InterruptVector = makeUnhandledHandler("EXTI2_TSC"), + + /// EXTI Line3 interrupt + EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), + + /// EXTI Line4 interrupt + EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), + + /// DMA1 channel 1 interrupt + DMA1_CH1: InterruptVector = makeUnhandledHandler("DMA1_CH1"), + + /// DMA1 channel 2 interrupt + DMA1_CH2: InterruptVector = makeUnhandledHandler("DMA1_CH2"), + + /// DMA1 channel 3 interrupt + DMA1_CH3: InterruptVector = makeUnhandledHandler("DMA1_CH3"), + + /// DMA1 channel 4 interrupt + DMA1_CH4: InterruptVector = makeUnhandledHandler("DMA1_CH4"), + + /// DMA1 channel 5 interrupt + DMA1_CH5: InterruptVector = makeUnhandledHandler("DMA1_CH5"), + + /// DMA1 channel 6 interrupt + DMA1_CH6: InterruptVector = makeUnhandledHandler("DMA1_CH6"), + + /// DMA1 channel 7interrupt + DMA1_CH7: InterruptVector = makeUnhandledHandler("DMA1_CH7"), + + /// ADC1 and ADC2 global interrupt + ADC1_2: InterruptVector = makeUnhandledHandler("ADC1_2"), + + /// USB High Priority/CAN_TX interrupts + USB_HP_CAN_TX: InterruptVector = makeUnhandledHandler("USB_HP_CAN_TX"), + + /// USB Low Priority/CAN_RX0 interrupts + USB_LP_CAN_RX0: InterruptVector = makeUnhandledHandler("USB_LP_CAN_RX0"), + + /// CAN_RX1 interrupt + CAN_RX1: InterruptVector = makeUnhandledHandler("CAN_RX1"), + + /// CAN_SCE interrupt + CAN_SCE: InterruptVector = makeUnhandledHandler("CAN_SCE"), + + /// EXTI Line5 to Line9 interrupts + EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), + + /// TIM1 Break/TIM15 global interruts + TIM1_BRK_TIM15: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM15"), + + /// TIM1 Update/TIM16 global interrupts + TIM1_UP_TIM16: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM16"), + + /// TIM1 trigger and commutation/TIM17 interrupts + TIM1_TRG_COM_TIM17: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM17"), + + /// TIM1 capture compare interrupt + TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), + + /// TIM2 global interrupt + TIM2: InterruptVector = makeUnhandledHandler("TIM2"), + + /// TIM3 global interrupt + TIM3: InterruptVector = makeUnhandledHandler("TIM3"), + + /// TIM4 global interrupt + TIM4: InterruptVector = makeUnhandledHandler("TIM4"), + + /// I2C1 event interrupt and EXTI Line23 interrupt + I2C1_EV_EXTI23: InterruptVector = makeUnhandledHandler("I2C1_EV_EXTI23"), + + /// I2C1 error interrupt + I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), + + /// I2C2 event interrupt & EXTI Line24 interrupt + I2C2_EV_EXTI24: InterruptVector = makeUnhandledHandler("I2C2_EV_EXTI24"), + + /// I2C2 error interrupt + I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), + + /// SPI1 global interrupt + SPI1: InterruptVector = makeUnhandledHandler("SPI1"), + + /// SPI2 global interrupt + SPI2: InterruptVector = makeUnhandledHandler("SPI2"), + + /// USART1 global interrupt and EXTI Line 25 interrupt + USART1_EXTI25: InterruptVector = makeUnhandledHandler("USART1_EXTI25"), + + /// USART2 global interrupt and EXTI Line 26 interrupt + USART2_EXTI26: InterruptVector = makeUnhandledHandler("USART2_EXTI26"), + + /// USART3 global interrupt and EXTI Line 28 interrupt + USART3_EXTI28: InterruptVector = makeUnhandledHandler("USART3_EXTI28"), + + /// EXTI Line15 to Line10 interrupts + EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), + + /// RTC alarm interrupt + RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), + + /// USB wakeup from Suspend + USB_WKUP: InterruptVector = makeUnhandledHandler("USB_WKUP"), + + /// TIM8 break interrupt + TIM8_BRK: InterruptVector = makeUnhandledHandler("TIM8_BRK"), + + /// TIM8 update interrupt + TIM8_UP: InterruptVector = makeUnhandledHandler("TIM8_UP"), + + /// TIM8 Trigger and commutation interrupts + TIM8_TRG_COM: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM"), + + /// TIM8 capture compare interrupt + TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), + + /// ADC3 global interrupt + ADC3: InterruptVector = makeUnhandledHandler("ADC3"), + + /// FSMC global interrupt + FMC: InterruptVector = makeUnhandledHandler("FMC"), + reserved2: u32 = 0, + reserved3: u32 = 0, + + /// SPI3 global interrupt + SPI3: InterruptVector = makeUnhandledHandler("SPI3"), + + /// UART4 global and EXTI Line 34 interrupts + UART4_EXTI34: InterruptVector = makeUnhandledHandler("UART4_EXTI34"), + + /// UART5 global and EXTI Line 35 interrupts + UART5_EXTI35: InterruptVector = makeUnhandledHandler("UART5_EXTI35"), + + /// TIM6 global and DAC12 underrun interrupts + TIM6_DACUNDER: InterruptVector = makeUnhandledHandler("TIM6_DACUNDER"), + + /// TIM7 global interrupt + TIM7: InterruptVector = makeUnhandledHandler("TIM7"), + + /// DMA2 channel1 global interrupt + DMA2_CH1: InterruptVector = makeUnhandledHandler("DMA2_CH1"), + + /// DMA2 channel2 global interrupt + DMA2_CH2: InterruptVector = makeUnhandledHandler("DMA2_CH2"), + + /// DMA2 channel3 global interrupt + DMA2_CH3: InterruptVector = makeUnhandledHandler("DMA2_CH3"), + + /// DMA2 channel4 global interrupt + DMA2_CH4: InterruptVector = makeUnhandledHandler("DMA2_CH4"), + + /// DMA2 channel5 global interrupt + DMA2_CH5: InterruptVector = makeUnhandledHandler("DMA2_CH5"), + + /// ADC4 global interrupt + ADC4: InterruptVector = makeUnhandledHandler("ADC4"), + reserved4: u32 = 0, + reserved5: u32 = 0, + + /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts + COMP123: InterruptVector = makeUnhandledHandler("COMP123"), + + /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 interrupts + COMP456: InterruptVector = makeUnhandledHandler("COMP456"), + + /// COMP7 interrupt combined with EXTI Line 33 interrupt + COMP7: InterruptVector = makeUnhandledHandler("COMP7"), + reserved6: u32 = 0, + reserved7: u32 = 0, + reserved8: u32 = 0, + reserved9: u32 = 0, + reserved10: u32 = 0, + + /// I2C3 Event interrupt + I2C3_EV: InterruptVector = makeUnhandledHandler("I2C3_EV"), + + /// I2C3 Error interrupt + I2C3_ER: InterruptVector = makeUnhandledHandler("I2C3_ER"), + + /// USB High priority interrupt + USB_HP: InterruptVector = makeUnhandledHandler("USB_HP"), + + /// USB Low priority interrupt + USB_LP: InterruptVector = makeUnhandledHandler("USB_LP"), + + /// USB wakeup from Suspend and EXTI Line 18 + USB_WKUP_EXTI: InterruptVector = makeUnhandledHandler("USB_WKUP_EXTI"), + + /// TIM20 Break interrupt + TIM20_BRK: InterruptVector = makeUnhandledHandler("TIM20_BRK"), + + /// TIM20 Upgrade interrupt + TIM20_UP: InterruptVector = makeUnhandledHandler("TIM20_UP"), + + /// TIM20 Trigger and Commutation interrupt + TIM20_TRG_COM: InterruptVector = makeUnhandledHandler("TIM20_TRG_COM"), + + /// TIM20 Capture Compare interrupt + TIM20_CC: InterruptVector = makeUnhandledHandler("TIM20_CC"), + + /// Floating point unit interrupt; Floating point interrupt + FPU: InterruptVector = makeUnhandledHandler("FPU"), + reserved11: u32 = 0, + reserved12: u32 = 0, + + /// SPI4 Global interrupt + SPI4: InterruptVector = makeUnhandledHandler("SPI4"), +}; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; }; + diff --git a/src/modules/chips/stm32f30x/stm32f30x.zig b/src/modules/chips/stm32f303/stm32f303.zig similarity index 100% rename from src/modules/chips/stm32f30x/stm32f30x.zig rename to src/modules/chips/stm32f303/stm32f303.zig diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig index f5f4d1f..7d0d489 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -1,6 +1,5 @@ const std = @import("std"); const root = @import("root"); -const config = @import("microzig-config"); pub fn sei() void { asm volatile ("cpsie i"); @@ -43,92 +42,6 @@ pub fn clrex() void { } pub const startup_logic = struct { - const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm - }; - - const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - reset: InterruptVector = InterruptVector{ .C = _start }, - nmi: InterruptVector = makeUnhandledHandler("nmi"), - hard_fault: InterruptVector = makeUnhandledHandler("hard_fault"), - mpu_fault: InterruptVector = makeUnhandledHandler("mpu_fault"), - bus_fault: InterruptVector = makeUnhandledHandler("bus_fault"), - usage_fault: InterruptVector = makeUnhandledHandler("usage_fault"), - secure_fault: InterruptVector = makeUnhandledHandler("secure_fault"), - - reserved: [3]u32 = .{ 0, 0, 0 }, - svc: InterruptVector = makeUnhandledHandler("svc"), - debugmon: InterruptVector = makeUnhandledHandler("debugmon"), - reserved1: u32 = 0, - - pendsv: InterruptVector = makeUnhandledHandler("pendsv"), - systick: InterruptVector = makeUnhandledHandler("systick"), - }; - - fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); - } - - export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "' declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; - } - } - break :blk temp; - }; - - fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; - } - extern fn microzig_main() noreturn; extern var microzig_data_start: anyopaque; @@ -137,7 +50,7 @@ pub const startup_logic = struct { extern var microzig_bss_end: anyopaque; extern const microzig_data_load_start: anyopaque; - fn _start() callconv(.C) noreturn { + pub fn _start() callconv(.C) noreturn { // fill .bss with zeroes { diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index c31bb92..e7cf163 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -117,14 +117,142 @@ class MMIOFileGenerator: self.write_line("};") + # TODO: descriptions on system interrupts/exceptions, turn on system interrupts/exceptions + def generate_startup_and_interrupts(self, interrupts): + self.write_line("") + self.write_line( + """ +const std = @import(\"std\"); +const root = @import(\"root\"); +const cpu = @import(\"cpu\"); +const config = @import(\"microzig-config\"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic(\"unhandled interrupt: \" ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler(\"NMI\"), + HardFault: InterruptVector = makeUnhandledHandler(\"HardFault\"), + MemManage: InterruptVector = makeUnhandledHandler(\"MemManage\"), + BusFault: InterruptVector = makeUnhandledHandler(\"BusFault\"), + UsageFault: InterruptVector = makeUnhandledHandler(\"UsageFault\"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler(\"SVCall\"), + DebugMonitor: InterruptVector = makeUnhandledHandler(\"DebugMonitor\"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler(\"PendSV\"), + SysTick: InterruptVector = makeUnhandledHandler(\"SysTick\"),\n +""") + + reserved_count = 2 + expected_next_value = 0 + for interrupt in interrupts: + if expected_next_value > interrupt.value: + raise Exception("out of order interrupt list") + + while expected_next_value < interrupt.value: + self.write_line(f" reserved{reserved_count}: u32 = 0,") + expected_next_value += 1 + reserved_count += 1 + + if interrupt.description is not None: + self.write_line(f"\n /// {interrupt.description}") + self.write_line(f" {interrupt.name}: InterruptVector = makeUnhandledHandler(\"{interrupt.name}\"),") + expected_next_value += 1 + self.write_line("};") + + self.write_line( + """ +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection(\"microzig_flash_start\") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, \"vector_table\")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog(\"root.vector_table must be a struct\"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = \"There is no such interrupt as '\" ++ decl.name ++ \"', declarations in 'root.vector_table' must be one of:\\n\"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ \" \" ++ field.name ++ \"\\n\"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError(\"You are not allowed to specify \'\" ++ decl.name ++ \"\' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang\"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError(\"unsupported calling convention for function \" ++ decl.name), + }; + } + } + break :blk temp; +}; +""") + def generate_file(self, device): self.write_line("// generated using svd2zig.py\n// DO NOT EDIT") self.write_line(f"// based on {device.name} version {device.version}") self.write_line("const mmio = @import(\"microzig-mmio\").mmio;") self.write_line(f"const Name = \"{device.name}\";") - for peripherial in device.peripherals: - self.generate_peripherial_declaration(peripherial) + interrupts = {} + for peripheral in device.peripherals: + self.generate_peripherial_declaration(peripheral) + if peripheral.interrupts != None: + for interrupt in peripheral.interrupts: + if interrupt.value in interrupts and interrupts[interrupt.value].description != interrupt.description: + interrupts[interrupt.value].description += "; " + interrupt.description + else: + interrupts[interrupt.value] = interrupt + + interrupts = list(map(lambda i: i[1], sorted(interrupts.items()))) + for interrupt in interrupts: + if interrupt.description is not None: + interrupt.description = ' '.join(interrupt.description.split()) + + self.generate_startup_and_interrupts(interrupts) def write_line(self, line): self.f.write(line + "\n") diff --git a/tests/interrupt.zig b/tests/interrupt.zig index 9406a8e..73dd4ea 100644 --- a/tests/interrupt.zig +++ b/tests/interrupt.zig @@ -6,7 +6,7 @@ const micro = @import("microzig"); pub const panic = micro.panic; pub const vector_table = struct { - pub fn systick() void { + pub fn SysTick() void { @panic("hit systick!"); } }; From 6b85ecfdcf15afa04d34cf1d0766dd310931406a Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 13 Feb 2022 10:55:00 -0800 Subject: [PATCH 027/138] cortex-m3 set to thumb isa (#17) --- src/main.zig | 2 +- src/modules/cpus.zig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main.zig b/src/main.zig index 66f5c48..275ea18 100644 --- a/src/main.zig +++ b/src/main.zig @@ -133,7 +133,7 @@ pub fn addEmbeddedExecutable( // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.bundle_compiler_rt = false; + exe.bundle_compiler_rt = true; switch (backing) { .chip => { var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 7fd8f30..95f37e4 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -22,7 +22,7 @@ pub const cortex_m3 = Cpu{ .name = "ARM Cortex-M3", .path = root_path ++ "cpus/cortex-m/cortex-m.zig", .target = std.zig.CrossTarget{ - .cpu_arch = .arm, + .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, .os_tag = .freestanding, .abi = .none, From 8a5ee675885b6d50ff8e0a70d0d459ee8705aec9 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 15 Feb 2022 18:02:20 -0800 Subject: [PATCH 028/138] register arrays and clusters, nrf52 as well (#19) * register arrays and clusters, nrf52 as well * remove TODO comment --- src/core/mmio.zig | 2 +- src/modules/chips.zig | 10 + src/modules/chips/nrf52/nrf52.zig | 2 + src/modules/chips/nrf52/registers.zig | 21145 ++++++++++++++++ src/modules/chips/stm32f103/registers.zig | 16056 +++++++----- src/modules/chips/stm32f303/registers.zig | 26030 +++++++++++++------- src/tools/svd2zig.py | 281 +- 7 files changed, 48093 insertions(+), 15433 deletions(-) create mode 100644 src/modules/chips/nrf52/nrf52.zig create mode 100644 src/modules/chips/nrf52/registers.zig diff --git a/src/core/mmio.zig b/src/core/mmio.zig index a46ca0c..4df5ef4 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -14,7 +14,7 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { const IntT = std.meta.Int(.unsigned, size); if (@sizeOf(PackedT) != (size / 8)) - @compileError("IntT and PackedT must have the same size!"); + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); return extern struct { const Self = @This(); diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 25c6cf2..7058431 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -49,3 +49,13 @@ pub const stm32f303vc = Chip{ MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram }, }, }; + +pub const nrf52832 = Chip{ + .name = "nRF52832", + .path = root_path ++ "chips/nrf52/nrf52.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, +}; diff --git a/src/modules/chips/nrf52/nrf52.zig b/src/modules/chips/nrf52/nrf52.zig new file mode 100644 index 0000000..5ae1cd3 --- /dev/null +++ b/src/modules/chips/nrf52/nrf52.zig @@ -0,0 +1,2 @@ +pub const cpu = @import("cpu"); +pub const registers = @import("registers.zig"); diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig new file mode 100644 index 0000000..97e4fec --- /dev/null +++ b/src/modules/chips/nrf52/registers.zig @@ -0,0 +1,21145 @@ +// generated using svd2zig.py +// DO NOT EDIT +// based on nrf52 version 1 +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; +const Name = "nrf52"; + +/// Factory Information Configuration Registers +pub const FICR = extern struct { + pub const Address: u32 = 0x10000000; + + /// Code memory page size + pub const CODEPAGESIZE = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Code memory size + pub const CODESIZE = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Device address type + pub const DEVICEADDRTYPE = mmio(Address + 0x000000a0, 32, packed struct { + /// Device address type + DEVICEADDRTYPE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Device identifier + pub const DEVICEID = @intToPtr(*volatile [2]u32, Address + 0x00000060); + /// Description collection[0]: Encryption Root, word 0 + pub const ER = @intToPtr(*volatile [4]u32, Address + 0x00000080); + /// Description collection[0]: Identity Root, word 0 + pub const IR = @intToPtr(*volatile [4]u32, Address + 0x00000090); + /// Description collection[0]: Device address 0 + pub const DEVICEADDR = @intToPtr(*volatile [2]u32, Address + 0x000000a4); + + pub const INFO = struct { + + /// Part code + pub const PART = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Part Variant, Hardware version and Production configuration + pub const VARIANT = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Package option + pub const PACKAGE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// RAM variant + pub const RAM = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Flash variant + pub const FLASH = @intToPtr(*volatile u32, Address + 0x00000010); + /// Description collection[0]: Unspecified + pub const UNUSED0 = @intToPtr(*volatile [3]u32, Address + 0x00000014); + }; + + pub const TEMP = struct { + + /// Slope definition A0. + pub const A0 = mmio(Address + 0x00000000, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A1. + pub const A1 = mmio(Address + 0x00000004, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A2. + pub const A2 = mmio(Address + 0x00000008, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A3. + pub const A3 = mmio(Address + 0x0000000c, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A4. + pub const A4 = mmio(Address + 0x00000010, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope definition A5. + pub const A5 = mmio(Address + 0x00000014, 32, packed struct { + /// A (slope definition) register. + A: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B0. + pub const B0 = mmio(Address + 0x00000018, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B1. + pub const B1 = mmio(Address + 0x0000001c, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B2. + pub const B2 = mmio(Address + 0x00000020, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B3. + pub const B3 = mmio(Address + 0x00000024, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B4. + pub const B4 = mmio(Address + 0x00000028, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept B5. + pub const B5 = mmio(Address + 0x0000002c, 32, packed struct { + /// B (y-intercept) + B: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T0. + pub const T0 = mmio(Address + 0x00000030, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T1. + pub const T1 = mmio(Address + 0x00000034, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T2. + pub const T2 = mmio(Address + 0x00000038, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T3. + pub const T3 = mmio(Address + 0x0000003c, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Segment end T4. + pub const T4 = mmio(Address + 0x00000040, 32, packed struct { + /// T (segment end)register. + T: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const NFC = struct { + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER0 = mmio(Address + 0x00000000, 32, packed struct { + /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + MFGID: u8 = 0, + /// Unique identifier byte 1 + UD1: u8 = 0, + /// Unique identifier byte 2 + UD2: u8 = 0, + /// Unique identifier byte 3 + UD3: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER1 = mmio(Address + 0x00000004, 32, packed struct { + /// Unique identifier byte 4 + UD4: u8 = 0, + /// Unique identifier byte 5 + UD5: u8 = 0, + /// Unique identifier byte 6 + UD6: u8 = 0, + /// Unique identifier byte 7 + UD7: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER2 = mmio(Address + 0x00000008, 32, packed struct { + /// Unique identifier byte 8 + UD8: u8 = 0, + /// Unique identifier byte 9 + UD9: u8 = 0, + /// Unique identifier byte 10 + UD10: u8 = 0, + /// Unique identifier byte 11 + UD11: u8 = 0, + }); + + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER3 = mmio(Address + 0x0000000c, 32, packed struct { + /// Unique identifier byte 12 + UD12: u8 = 0, + /// Unique identifier byte 13 + UD13: u8 = 0, + /// Unique identifier byte 14 + UD14: u8 = 0, + /// Unique identifier byte 15 + UD15: u8 = 0, + }); + }; +}; + +/// User Information Configuration Registers +pub const UICR = extern struct { + pub const Address: u32 = 0x10001000; + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Unspecified + pub const UNUSED1 = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Unspecified + pub const UNUSED2 = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Unspecified + pub const UNUSED3 = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Access Port protection + pub const APPROTECT = mmio(Address + 0x00000208, 32, packed struct { + /// Enable or disable Access Port protection. Any other value than 0xFF being + /// written to this field will enable protection. + PALL: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + pub const NFCPINS = mmio(Address + 0x0000020c, 32, packed struct { + /// Setting of pins dedicated to NFC functionality + PROTECT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Reserved for Nordic firmware design + pub const NRFFW = @intToPtr(*volatile [15]u32, Address + 0x00000014); + /// Description collection[0]: Reserved for Nordic hardware design + pub const NRFHW = @intToPtr(*volatile [12]u32, Address + 0x00000050); + /// Description collection[0]: Reserved for customer + pub const CUSTOMER = @intToPtr(*volatile [32]u32, Address + 0x00000080); + /// Description collection[0]: Mapping of the nRESET function (see POWER chapter + /// for details) + pub const PSELRESET = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// GPIO number P0.n onto which Reset is exposed + PIN: u6 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }), Address + 0x00000200); +}; + +/// Block Protect +pub const BPROT = extern struct { + pub const Address: u32 = 0x40000000; + + /// Block protect configuration register 0 + pub const CONFIG0 = mmio(Address + 0x00000600, 32, packed struct { + /// Enable protection for region 0. Write '0' has no effect. + REGION0: u1 = 0, + /// Enable protection for region 1. Write '0' has no effect. + REGION1: u1 = 0, + /// Enable protection for region 2. Write '0' has no effect. + REGION2: u1 = 0, + /// Enable protection for region 3. Write '0' has no effect. + REGION3: u1 = 0, + /// Enable protection for region 4. Write '0' has no effect. + REGION4: u1 = 0, + /// Enable protection for region 5. Write '0' has no effect. + REGION5: u1 = 0, + /// Enable protection for region 6. Write '0' has no effect. + REGION6: u1 = 0, + /// Enable protection for region 7. Write '0' has no effect. + REGION7: u1 = 0, + /// Enable protection for region 8. Write '0' has no effect. + REGION8: u1 = 0, + /// Enable protection for region 9. Write '0' has no effect. + REGION9: u1 = 0, + /// Enable protection for region 10. Write '0' has no effect. + REGION10: u1 = 0, + /// Enable protection for region 11. Write '0' has no effect. + REGION11: u1 = 0, + /// Enable protection for region 12. Write '0' has no effect. + REGION12: u1 = 0, + /// Enable protection for region 13. Write '0' has no effect. + REGION13: u1 = 0, + /// Enable protection for region 14. Write '0' has no effect. + REGION14: u1 = 0, + /// Enable protection for region 15. Write '0' has no effect. + REGION15: u1 = 0, + /// Enable protection for region 16. Write '0' has no effect. + REGION16: u1 = 0, + /// Enable protection for region 17. Write '0' has no effect. + REGION17: u1 = 0, + /// Enable protection for region 18. Write '0' has no effect. + REGION18: u1 = 0, + /// Enable protection for region 19. Write '0' has no effect. + REGION19: u1 = 0, + /// Enable protection for region 20. Write '0' has no effect. + REGION20: u1 = 0, + /// Enable protection for region 21. Write '0' has no effect. + REGION21: u1 = 0, + /// Enable protection for region 22. Write '0' has no effect. + REGION22: u1 = 0, + /// Enable protection for region 23. Write '0' has no effect. + REGION23: u1 = 0, + /// Enable protection for region 24. Write '0' has no effect. + REGION24: u1 = 0, + /// Enable protection for region 25. Write '0' has no effect. + REGION25: u1 = 0, + /// Enable protection for region 26. Write '0' has no effect. + REGION26: u1 = 0, + /// Enable protection for region 27. Write '0' has no effect. + REGION27: u1 = 0, + /// Enable protection for region 28. Write '0' has no effect. + REGION28: u1 = 0, + /// Enable protection for region 29. Write '0' has no effect. + REGION29: u1 = 0, + /// Enable protection for region 30. Write '0' has no effect. + REGION30: u1 = 0, + /// Enable protection for region 31. Write '0' has no effect. + REGION31: u1 = 0, + }); + + /// Block protect configuration register 1 + pub const CONFIG1 = mmio(Address + 0x00000604, 32, packed struct { + /// Enable protection for region 32. Write '0' has no effect. + REGION32: u1 = 0, + /// Enable protection for region 33. Write '0' has no effect. + REGION33: u1 = 0, + /// Enable protection for region 34. Write '0' has no effect. + REGION34: u1 = 0, + /// Enable protection for region 35. Write '0' has no effect. + REGION35: u1 = 0, + /// Enable protection for region 36. Write '0' has no effect. + REGION36: u1 = 0, + /// Enable protection for region 37. Write '0' has no effect. + REGION37: u1 = 0, + /// Enable protection for region 38. Write '0' has no effect. + REGION38: u1 = 0, + /// Enable protection for region 39. Write '0' has no effect. + REGION39: u1 = 0, + /// Enable protection for region 40. Write '0' has no effect. + REGION40: u1 = 0, + /// Enable protection for region 41. Write '0' has no effect. + REGION41: u1 = 0, + /// Enable protection for region 42. Write '0' has no effect. + REGION42: u1 = 0, + /// Enable protection for region 43. Write '0' has no effect. + REGION43: u1 = 0, + /// Enable protection for region 44. Write '0' has no effect. + REGION44: u1 = 0, + /// Enable protection for region 45. Write '0' has no effect. + REGION45: u1 = 0, + /// Enable protection for region 46. Write '0' has no effect. + REGION46: u1 = 0, + /// Enable protection for region 47. Write '0' has no effect. + REGION47: u1 = 0, + /// Enable protection for region 48. Write '0' has no effect. + REGION48: u1 = 0, + /// Enable protection for region 49. Write '0' has no effect. + REGION49: u1 = 0, + /// Enable protection for region 50. Write '0' has no effect. + REGION50: u1 = 0, + /// Enable protection for region 51. Write '0' has no effect. + REGION51: u1 = 0, + /// Enable protection for region 52. Write '0' has no effect. + REGION52: u1 = 0, + /// Enable protection for region 53. Write '0' has no effect. + REGION53: u1 = 0, + /// Enable protection for region 54. Write '0' has no effect. + REGION54: u1 = 0, + /// Enable protection for region 55. Write '0' has no effect. + REGION55: u1 = 0, + /// Enable protection for region 56. Write '0' has no effect. + REGION56: u1 = 0, + /// Enable protection for region 57. Write '0' has no effect. + REGION57: u1 = 0, + /// Enable protection for region 58. Write '0' has no effect. + REGION58: u1 = 0, + /// Enable protection for region 59. Write '0' has no effect. + REGION59: u1 = 0, + /// Enable protection for region 60. Write '0' has no effect. + REGION60: u1 = 0, + /// Enable protection for region 61. Write '0' has no effect. + REGION61: u1 = 0, + /// Enable protection for region 62. Write '0' has no effect. + REGION62: u1 = 0, + /// Enable protection for region 63. Write '0' has no effect. + REGION63: u1 = 0, + }); + + /// Disable protection mechanism in debug interface mode + pub const DISABLEINDEBUG = mmio(Address + 0x00000608, 32, packed struct { + /// Disable the protection mechanism for NVM regions while in debug interface + /// mode. This register will only disable the protection mechanism if the device + /// is in debug interface mode. + DISABLEINDEBUG: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x0000060c); + + /// Block protect configuration register 2 + pub const CONFIG2 = mmio(Address + 0x00000610, 32, packed struct { + /// Enable protection for region 64. Write '0' has no effect. + REGION64: u1 = 0, + /// Enable protection for region 65. Write '0' has no effect. + REGION65: u1 = 0, + /// Enable protection for region 66. Write '0' has no effect. + REGION66: u1 = 0, + /// Enable protection for region 67. Write '0' has no effect. + REGION67: u1 = 0, + /// Enable protection for region 68. Write '0' has no effect. + REGION68: u1 = 0, + /// Enable protection for region 69. Write '0' has no effect. + REGION69: u1 = 0, + /// Enable protection for region 70. Write '0' has no effect. + REGION70: u1 = 0, + /// Enable protection for region 71. Write '0' has no effect. + REGION71: u1 = 0, + /// Enable protection for region 72. Write '0' has no effect. + REGION72: u1 = 0, + /// Enable protection for region 73. Write '0' has no effect. + REGION73: u1 = 0, + /// Enable protection for region 74. Write '0' has no effect. + REGION74: u1 = 0, + /// Enable protection for region 75. Write '0' has no effect. + REGION75: u1 = 0, + /// Enable protection for region 76. Write '0' has no effect. + REGION76: u1 = 0, + /// Enable protection for region 77. Write '0' has no effect. + REGION77: u1 = 0, + /// Enable protection for region 78. Write '0' has no effect. + REGION78: u1 = 0, + /// Enable protection for region 79. Write '0' has no effect. + REGION79: u1 = 0, + /// Enable protection for region 80. Write '0' has no effect. + REGION80: u1 = 0, + /// Enable protection for region 81. Write '0' has no effect. + REGION81: u1 = 0, + /// Enable protection for region 82. Write '0' has no effect. + REGION82: u1 = 0, + /// Enable protection for region 83. Write '0' has no effect. + REGION83: u1 = 0, + /// Enable protection for region 84. Write '0' has no effect. + REGION84: u1 = 0, + /// Enable protection for region 85. Write '0' has no effect. + REGION85: u1 = 0, + /// Enable protection for region 86. Write '0' has no effect. + REGION86: u1 = 0, + /// Enable protection for region 87. Write '0' has no effect. + REGION87: u1 = 0, + /// Enable protection for region 88. Write '0' has no effect. + REGION88: u1 = 0, + /// Enable protection for region 89. Write '0' has no effect. + REGION89: u1 = 0, + /// Enable protection for region 90. Write '0' has no effect. + REGION90: u1 = 0, + /// Enable protection for region 91. Write '0' has no effect. + REGION91: u1 = 0, + /// Enable protection for region 92. Write '0' has no effect. + REGION92: u1 = 0, + /// Enable protection for region 93. Write '0' has no effect. + REGION93: u1 = 0, + /// Enable protection for region 94. Write '0' has no effect. + REGION94: u1 = 0, + /// Enable protection for region 95. Write '0' has no effect. + REGION95: u1 = 0, + }); + + /// Block protect configuration register 3 + pub const CONFIG3 = mmio(Address + 0x00000614, 32, packed struct { + /// Enable protection for region 96. Write '0' has no effect. + REGION96: u1 = 0, + /// Enable protection for region 97. Write '0' has no effect. + REGION97: u1 = 0, + /// Enable protection for region 98. Write '0' has no effect. + REGION98: u1 = 0, + /// Enable protection for region 99. Write '0' has no effect. + REGION99: u1 = 0, + /// Enable protection for region 100. Write '0' has no effect. + REGION100: u1 = 0, + /// Enable protection for region 101. Write '0' has no effect. + REGION101: u1 = 0, + /// Enable protection for region 102. Write '0' has no effect. + REGION102: u1 = 0, + /// Enable protection for region 103. Write '0' has no effect. + REGION103: u1 = 0, + /// Enable protection for region 104. Write '0' has no effect. + REGION104: u1 = 0, + /// Enable protection for region 105. Write '0' has no effect. + REGION105: u1 = 0, + /// Enable protection for region 106. Write '0' has no effect. + REGION106: u1 = 0, + /// Enable protection for region 107. Write '0' has no effect. + REGION107: u1 = 0, + /// Enable protection for region 108. Write '0' has no effect. + REGION108: u1 = 0, + /// Enable protection for region 109. Write '0' has no effect. + REGION109: u1 = 0, + /// Enable protection for region 110. Write '0' has no effect. + REGION110: u1 = 0, + /// Enable protection for region 111. Write '0' has no effect. + REGION111: u1 = 0, + /// Enable protection for region 112. Write '0' has no effect. + REGION112: u1 = 0, + /// Enable protection for region 113. Write '0' has no effect. + REGION113: u1 = 0, + /// Enable protection for region 114. Write '0' has no effect. + REGION114: u1 = 0, + /// Enable protection for region 115. Write '0' has no effect. + REGION115: u1 = 0, + /// Enable protection for region 116. Write '0' has no effect. + REGION116: u1 = 0, + /// Enable protection for region 117. Write '0' has no effect. + REGION117: u1 = 0, + /// Enable protection for region 118. Write '0' has no effect. + REGION118: u1 = 0, + /// Enable protection for region 119. Write '0' has no effect. + REGION119: u1 = 0, + /// Enable protection for region 120. Write '0' has no effect. + REGION120: u1 = 0, + /// Enable protection for region 121. Write '0' has no effect. + REGION121: u1 = 0, + /// Enable protection for region 122. Write '0' has no effect. + REGION122: u1 = 0, + /// Enable protection for region 123. Write '0' has no effect. + REGION123: u1 = 0, + /// Enable protection for region 124. Write '0' has no effect. + REGION124: u1 = 0, + /// Enable protection for region 125. Write '0' has no effect. + REGION125: u1 = 0, + /// Enable protection for region 126. Write '0' has no effect. + REGION126: u1 = 0, + /// Enable protection for region 127. Write '0' has no effect. + REGION127: u1 = 0, + }); +}; + +/// Power control +pub const POWER = extern struct { + pub const Address: u32 = 0x40000000; + + /// Enable constant latency mode + pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, Address + 0x00000078); + + /// Enable low power mode (variable latency) + pub const TASKS_LOWPWR = @intToPtr(*volatile u32, Address + 0x0000007c); + + /// Power failure warning + pub const EVENTS_POFWARN = @intToPtr(*volatile u32, Address + 0x00000108); + + /// CPU entered WFI/WFE sleep + pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, Address + 0x00000114); + + /// CPU exited WFI/WFE sleep + pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for POFWARN event + POFWARN: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER: u1 = 0, + /// Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for POFWARN event + POFWARN: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER: u1 = 0, + /// Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reset reason + pub const RESETREAS = mmio(Address + 0x00000400, 32, packed struct { + /// Reset from pin-reset detected + RESETPIN: u1 = 0, + /// Reset from watchdog detected + DOG: u1 = 0, + /// Reset from soft reset detected + SREQ: u1 = 0, + /// Reset from CPU lock-up detected + LOCKUP: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// DETECT signal from GPIO + OFF: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// ANADETECT signal from LPCOMP + LPCOMP: u1 = 0, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// entering into debug interface mode + DIF: u1 = 0, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM status register + pub const RAMSTATUS = mmio(Address + 0x00000428, 32, packed struct { + /// RAM block 0 is on or off/powering up + RAMBLOCK0: u1 = 0, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: u1 = 0, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: u1 = 0, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// System OFF register + pub const SYSTEMOFF = mmio(Address + 0x00000500, 32, packed struct { + /// Enable System OFF mode + SYSTEMOFF: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Power failure comparator configuration + pub const POFCON = mmio(Address + 0x00000510, 32, packed struct { + /// Enable or disable power failure comparator + POF: u1 = 0, + /// Power failure comparator threshold setting + THRESHOLD: u4 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// General purpose retention register + pub const GPREGRET = mmio(Address + 0x0000051c, 32, packed struct { + /// General purpose retention register + GPREGRET: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// General purpose retention register + pub const GPREGRET2 = mmio(Address + 0x00000520, 32, packed struct { + /// General purpose retention register + GPREGRET: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMON = mmio(Address + 0x00000524, 32, packed struct { + /// Keep RAM block 0 on or off in system ON Mode + ONRAM0: u1 = 0, + /// Keep RAM block 1 on or off in system ON Mode + ONRAM1: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0: u1 = 0, + /// Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMONB = mmio(Address + 0x00000554, 32, packed struct { + /// Keep RAM block 2 on or off in system ON Mode + ONRAM2: u1 = 0, + /// Keep RAM block 3 on or off in system ON Mode + ONRAM3: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2: u1 = 0, + /// Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DC/DC enable register + pub const DCDCEN = mmio(Address + 0x00000578, 32, packed struct { + /// Enable or disable DC/DC converter + DCDCEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Clock control +pub const CLOCK = extern struct { + pub const Address: u32 = 0x40000000; + + /// Start HFCLK crystal oscillator + pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop HFCLK crystal oscillator + pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start LFCLK source + pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop LFCLK source + pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Start calibration of LFRC oscillator + pub const TASKS_CAL = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Start calibration timer + pub const TASKS_CTSTART = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Stop calibration timer + pub const TASKS_CTSTOP = @intToPtr(*volatile u32, Address + 0x00000018); + + /// HFCLK oscillator started + pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// LFCLK started + pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Calibration of LFCLK RC oscillator complete event + pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Calibration timer timeout + pub const EVENTS_CTTO = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Enable interrupt for CTTO event + CTTO: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Disable interrupt for CTTO event + CTTO: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status indicating that HFCLKSTART task has been triggered + pub const HFCLKRUN = mmio(Address + 0x00000408, 32, packed struct { + /// HFCLKSTART task triggered or not + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// HFCLK status + pub const HFCLKSTAT = mmio(Address + 0x0000040c, 32, packed struct { + /// Source of HFCLK + SRC: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// HFCLK state + STATE: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status indicating that LFCLKSTART task has been triggered + pub const LFCLKRUN = mmio(Address + 0x00000414, 32, packed struct { + /// LFCLKSTART task triggered or not + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// LFCLK status + pub const LFCLKSTAT = mmio(Address + 0x00000418, 32, packed struct { + /// Source of LFCLK + SRC: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// LFCLK state + STATE: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + pub const LFCLKSRCCOPY = mmio(Address + 0x0000041c, 32, packed struct { + /// Clock source + SRC: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Clock source for the LFCLK + pub const LFCLKSRC = mmio(Address + 0x00000518, 32, packed struct { + /// Clock source + SRC: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock + /// source + BYPASS: u1 = 0, + /// Enable or disable external source for LFCLK + EXTERNAL: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Calibration timer interval + pub const CTIV = mmio(Address + 0x00000538, 32, packed struct { + /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds + /// to 31.75 seconds. + CTIV: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Clocking options for the Trace Port debug interface + pub const TRACECONFIG = mmio(Address + 0x0000055c, 32, packed struct { + /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock + /// divided by two. + TRACEPORTSPEED: u2 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Pin multiplexing of trace signals. + TRACEMUX: u2 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// 2.4 GHz Radio +pub const RADIO = extern struct { + pub const Address: u32 = 0x40001000; + + /// Enable RADIO in TX mode + pub const TASKS_TXEN = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Enable RADIO in RX mode + pub const TASKS_RXEN = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start RADIO + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop RADIO + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Disable RADIO + pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Start the RSSI and take one single sample of the receive signal strength. + pub const TASKS_RSSISTART = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Stop the RSSI measurement + pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, Address + 0x00000018); + + /// Start the bit counter + pub const TASKS_BCSTART = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Stop the bit counter + pub const TASKS_BCSTOP = @intToPtr(*volatile u32, Address + 0x00000020); + + /// RADIO has ramped up and is ready to be started + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Address sent or received + pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Packet payload sent or received + pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Packet sent or received + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// RADIO has been disabled + pub const EVENTS_DISABLED = @intToPtr(*volatile u32, Address + 0x00000110); + + /// A device address match occurred on the last received packet + pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, Address + 0x00000114); + + /// No device address match occurred on the last received packet + pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Sampling of receive signal strength complete. + pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Bit counter reached bit count value. + pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Packet received with CRC ok + pub const EVENTS_CRCOK = @intToPtr(*volatile u32, Address + 0x00000130); + + /// Packet received with CRC error + pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, Address + 0x00000134); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and START task + READY_START: u1 = 0, + /// Shortcut between END event and DISABLE task + END_DISABLE: u1 = 0, + /// Shortcut between DISABLED event and TXEN task + DISABLED_TXEN: u1 = 0, + /// Shortcut between DISABLED event and RXEN task + DISABLED_RXEN: u1 = 0, + /// Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + /// Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for ADDRESS event + ADDRESS: u1 = 0, + /// Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for DISABLED event + DISABLED: u1 = 0, + /// Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH: u1 = 0, + /// Write '1' to Enable interrupt for DEVMISS event + DEVMISS: u1 = 0, + /// Write '1' to Enable interrupt for RSSIEND event + RSSIEND: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for BCMATCH event + BCMATCH: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for CRCOK event + CRCOK: u1 = 0, + /// Write '1' to Enable interrupt for CRCERROR event + CRCERROR: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for ADDRESS event + ADDRESS: u1 = 0, + /// Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for DISABLED event + DISABLED: u1 = 0, + /// Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH: u1 = 0, + /// Write '1' to Disable interrupt for DEVMISS event + DEVMISS: u1 = 0, + /// Write '1' to Disable interrupt for RSSIEND event + RSSIEND: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for BCMATCH event + BCMATCH: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for CRCOK event + CRCOK: u1 = 0, + /// Write '1' to Disable interrupt for CRCERROR event + CRCERROR: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC status + pub const CRCSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// CRC status of packet received + CRCSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Received address + pub const RXMATCH = mmio(Address + 0x00000408, 32, packed struct { + /// Received address + RXMATCH: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC field of previously received packet + pub const RXCRC = mmio(Address + 0x0000040c, 32, packed struct { + /// CRC field of previously received packet + RXCRC: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Device address match index + pub const DAI = mmio(Address + 0x00000410, 32, packed struct { + /// Device address match index + DAI: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet pointer + pub const PACKETPTR = @intToPtr(*volatile u32, Address + 0x00000504); + + /// Frequency + pub const FREQUENCY = mmio(Address + 0x00000508, 32, packed struct { + /// Radio channel frequency + FREQUENCY: u7 = 0, + reserved1: u1 = 0, + /// Channel map selection. + MAP: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Output power + pub const TXPOWER = mmio(Address + 0x0000050c, 32, packed struct { + /// RADIO output power. + TXPOWER: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Data rate and modulation + pub const MODE = mmio(Address + 0x00000510, 32, packed struct { + /// Radio data rate and modulation setting. The radio supports Frequency-shift + /// Keying (FSK) modulation. + MODE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet configuration register 0 + pub const PCNF0 = mmio(Address + 0x00000514, 32, packed struct { + /// Length on air of LENGTH field in number of bits. + LFLEN: u4 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Length on air of S0 field in number of bytes. + S0LEN: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + /// Length on air of S1 field in number of bits. + S1LEN: u4 = 0, + /// Include or exclude S1 field in RAM + S1INCL: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet configuration register 1 + pub const PCNF1 = mmio(Address + 0x00000518, 32, packed struct { + /// Maximum length of packet payload. If the packet payload is larger than + /// MAXLEN, the radio will truncate the payload to MAXLEN. + MAXLEN: u8 = 0, + /// Static length in number of bytes + STATLEN: u8 = 0, + /// Base address length in number of bytes + BALEN: u3 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the + /// PAYLOAD fields. + ENDIAN: u1 = 0, + /// Enable or disable packet whitening + WHITEEN: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Base address 0 + pub const BASE0 = @intToPtr(*volatile u32, Address + 0x0000051c); + + /// Base address 1 + pub const BASE1 = @intToPtr(*volatile u32, Address + 0x00000520); + + /// Prefixes bytes for logical addresses 0-3 + pub const PREFIX0 = mmio(Address + 0x00000524, 32, packed struct { + /// Address prefix 0. + AP0: u8 = 0, + /// Address prefix 1. + AP1: u8 = 0, + /// Address prefix 2. + AP2: u8 = 0, + /// Address prefix 3. + AP3: u8 = 0, + }); + + /// Prefixes bytes for logical addresses 4-7 + pub const PREFIX1 = mmio(Address + 0x00000528, 32, packed struct { + /// Address prefix 4. + AP4: u8 = 0, + /// Address prefix 5. + AP5: u8 = 0, + /// Address prefix 6. + AP6: u8 = 0, + /// Address prefix 7. + AP7: u8 = 0, + }); + + /// Transmit address select + pub const TXADDRESS = mmio(Address + 0x0000052c, 32, packed struct { + /// Transmit address select + TXADDRESS: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Receive address select + pub const RXADDRESSES = mmio(Address + 0x00000530, 32, packed struct { + /// Enable or disable reception on logical address 0. + ADDR0: u1 = 0, + /// Enable or disable reception on logical address 1. + ADDR1: u1 = 0, + /// Enable or disable reception on logical address 2. + ADDR2: u1 = 0, + /// Enable or disable reception on logical address 3. + ADDR3: u1 = 0, + /// Enable or disable reception on logical address 4. + ADDR4: u1 = 0, + /// Enable or disable reception on logical address 5. + ADDR5: u1 = 0, + /// Enable or disable reception on logical address 6. + ADDR6: u1 = 0, + /// Enable or disable reception on logical address 7. + ADDR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC configuration + pub const CRCCNF = mmio(Address + 0x00000534, 32, packed struct { + /// CRC length in number of bytes. + LEN: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC polynomial + pub const CRCPOLY = mmio(Address + 0x00000538, 32, packed struct { + /// CRC polynomial + CRCPOLY: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CRC initial value + pub const CRCINIT = mmio(Address + 0x0000053c, 32, packed struct { + /// CRC initial value + CRCINIT: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000540); + + /// Inter Frame Spacing in us + pub const TIFS = mmio(Address + 0x00000544, 32, packed struct { + /// Inter Frame Spacing in us + TIFS: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RSSI sample + pub const RSSISAMPLE = mmio(Address + 0x00000548, 32, packed struct { + /// RSSI sample + RSSISAMPLE: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current radio state + pub const STATE = mmio(Address + 0x00000550, 32, packed struct { + /// Current radio state + STATE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Data whitening initial value + pub const DATAWHITEIV = mmio(Address + 0x00000554, 32, packed struct { + /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it + /// has no effect, and it will always be read back and used by the device as + /// '1'. + DATAWHITEIV: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Bit counter compare + pub const BCC = @intToPtr(*volatile u32, Address + 0x00000560); + + /// Device address match configuration + pub const DACNF = mmio(Address + 0x00000640, 32, packed struct { + /// Enable or disable device address matching using device address 0 + ENA0: u1 = 0, + /// Enable or disable device address matching using device address 1 + ENA1: u1 = 0, + /// Enable or disable device address matching using device address 2 + ENA2: u1 = 0, + /// Enable or disable device address matching using device address 3 + ENA3: u1 = 0, + /// Enable or disable device address matching using device address 4 + ENA4: u1 = 0, + /// Enable or disable device address matching using device address 5 + ENA5: u1 = 0, + /// Enable or disable device address matching using device address 6 + ENA6: u1 = 0, + /// Enable or disable device address matching using device address 7 + ENA7: u1 = 0, + /// TxAdd for device address 0 + TXADD0: u1 = 0, + /// TxAdd for device address 1 + TXADD1: u1 = 0, + /// TxAdd for device address 2 + TXADD2: u1 = 0, + /// TxAdd for device address 3 + TXADD3: u1 = 0, + /// TxAdd for device address 4 + TXADD4: u1 = 0, + /// TxAdd for device address 5 + TXADD5: u1 = 0, + /// TxAdd for device address 6 + TXADD6: u1 = 0, + /// TxAdd for device address 7 + TXADD7: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Radio mode configuration register 0 + pub const MODECNF0 = mmio(Address + 0x00000650, 32, packed struct { + /// Radio ramp-up time + RU: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Default TX value + DTX: u2 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Peripheral power control + pub const POWER = mmio(Address + 0x00000ffc, 32, packed struct { + /// Peripheral power control. The peripheral and its registers will be reset to + /// its initial state by switching the peripheral off and then back on again. + POWER: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Device address base segment 0 + pub const DAB = @intToPtr(*volatile [8]u32, Address + 0x00000600); + /// Description collection[0]: Device address prefix 0 + pub const DAP = @intToPtr(*volatile [8]MMIO(32, packed struct { + /// Device address prefix 0 + DAP: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000620); +}; + +/// UART with EasyDMA +pub const UARTE0 = extern struct { + pub const Address: u32 = 0x40002000; + + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Flush RX FIFO into RX buffer + pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, Address + 0x0000002c); + + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); + + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Data received in RXD (but potentially not yet transferred to Data RAM) + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Receive buffer is filled up + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Last TX byte transmitted + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); + + /// UART receiver has started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// UART transmitter has started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Transmitter stopped + pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, Address + 0x00000158); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX: u1 = 0, + /// Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for CTS event + CTS: u1 = 0, + /// Enable or disable interrupt for NCTS event + NCTS: u1 = 0, + /// Enable or disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Enable or disable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Enable or disable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved12: u1 = 0, + /// Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// Parity error + PARITY: u1 = 0, + /// Framing error occurred + FRAMING: u1 = 0, + /// Break condition + BREAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable UART + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable UARTE + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Baud rate. Accuracy depends on the HFCLK source selected. + pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration of parity and hardware flow control + pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { + /// Hardware flow control + HWFC: u1 = 0, + /// Parity + PARITY: u3 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for RTS signal + pub const RTS = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for TXD signal + pub const TXD = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for CTS signal + pub const CTS = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for RXD signal + pub const RXD = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Universal Asynchronous Receiver/Transmitter +pub const UART0 = extern struct { + pub const Address: u32 = 0x40002000; + + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Suspend UART + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); + + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Data received in RXD + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between CTS event and STARTRX task + CTS_STARTRX: u1 = 0, + /// Shortcut between NCTS event and STOPRX task + NCTS_STOPRX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for CTS event + CTS: u1 = 0, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1 = 0, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// Parity error + PARITY: u1 = 0, + /// Framing error occurred + FRAMING: u1 = 0, + /// Break condition + BREAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable UART + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable UART + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for RTS + pub const PSELRTS = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for TXD + pub const PSELTXD = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Pin select for CTS + pub const PSELCTS = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pin select for RXD + pub const PSELRXD = @intToPtr(*volatile u32, Address + 0x00000514); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received in previous transfers, double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to be transferred + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Baud rate + pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration of parity and hardware flow control + pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { + /// Hardware flow control + HWFC: u1 = 0, + /// Parity + PARITY: u3 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface Master with EasyDMA 0 +pub const SPIM0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MOSI signal + pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MISO signal + pub const MISO = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// SPI Slave 0 +pub const SPIS0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MISO signal + pub const MISO = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for MOSI signal + pub const MOSI = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for CSN signal + pub const CSN = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// RXD data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes received in last granted transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes received in the last granted transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// TXD data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transmitted in last granted transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transmitted in last granted transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Master Interface with EasyDMA 0 +pub const TWIM0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Last byte has been sent out after the SUSPEND task has been issued, TWI + /// traffic is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); + + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1 = 0, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1 = 0, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1 = 0, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1 = 0, + reserved8: u1 = 0, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCL signal + pub const SCL = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDA signal + pub const SDA = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in receive buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in receive buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction. In case of NACK error, + /// includes the NACK'ed byte. + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in transmit buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last transaction. In case of NACK error, + /// includes the NACK'ed byte. + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// EasyDMA list type + pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { + /// List type + LIST: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Slave Interface with EasyDMA 0 +pub const TWIS0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); + + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); + + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1 = 0, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Enable or disable interrupt for WRITE event + WRITE: u1 = 0, + /// Enable or disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Enable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + reserved1: u1 = 0, + /// NACK sent after receiving a data byte + DNACK: u1 = 0, + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status register indicating which address had a match + pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIS + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIS + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the address match mechanism + pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1 = 0, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// TWI slave address + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000588); + + pub const PSEL = struct { + + /// Pin select for SCL signal + pub const SCL = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDA signal + pub const SDA = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// RXD Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in RXD buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in RXD buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last RXD transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last RXD transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// TXD Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of bytes in TXD buffer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of bytes in TXD buffer + MAXCNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of bytes transferred in the last TXD transaction + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of bytes transferred in the last TXD transaction + AMOUNT: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Serial Peripheral Interface 0 +pub const SPI0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for SCK + pub const SCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number configuration for SPI SCK signal + PSELSCK: u32 = 0, + }); + + /// Pin select for MOSI + pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number configuration for SPI MOSI signal + PSELMOSI: u32 = 0, + }); + + /// Pin select for MISO + pub const MISO = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number configuration for SPI MISO signal + PSELMISO: u32 = 0, + }); + }; +}; + +/// I2C compatible Two-Wire Interface 0 +pub const TWI0 = extern struct { + pub const Address: u32 = 0x40003000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); + + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1 = 0, + /// Shortcut between BB event and STOP task + BB_STOP: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Enable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Disable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RXD register + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TXD register + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface Master with EasyDMA 1 +pub const SPIM1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// SPI Slave 1 +pub const SPIS1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Master Interface with EasyDMA 1 +pub const TWIM1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Last byte has been sent out after the SUSPEND task has been issued, TWI + /// traffic is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); + + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1 = 0, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1 = 0, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1 = 0, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1 = 0, + reserved8: u1 = 0, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1 = 0, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Slave Interface with EasyDMA 1 +pub const TWIS1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); + + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); + + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1 = 0, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Enable or disable interrupt for WRITE event + WRITE: u1 = 0, + /// Enable or disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Enable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1 = 0, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1 = 0, + /// Write '1' to Disable interrupt for READ event + READ: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + reserved1: u1 = 0, + /// NACK sent after receiving a data byte + DNACK: u1 = 0, + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status register indicating which address had a match + pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { + /// Which of the addresses in {ADDRESS} matched the incoming address + MATCH: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWIS + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWIS + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the address match mechanism + pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1 = 0, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character sent out in case of an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { + /// TWI slave address + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000588); +}; + +/// Serial Peripheral Interface 1 +pub const SPI1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// I2C compatible Two-Wire Interface 1 +pub const TWI1 = extern struct { + pub const Address: u32 = 0x40004000; + + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); + + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); + + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1 = 0, + /// Shortcut between BB event and STOP task + BB_STOP: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Enable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// Write '1' to Disable interrupt for BB event + BB: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Error source + pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { + /// Overrun error + OVERRUN: u1 = 0, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1 = 0, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable TWI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable TWI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RXD register + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TXD register + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Address used in the TWI transfer + pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// Address used in the TWI transfer + ADDRESS: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// NFC-A compatible radio +pub const NFCT = extern struct { + pub const Address: u32 = 0x40005000; + + /// Activate NFC peripheral for incoming and outgoing frames, change state to + /// activated + pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Disable NFC peripheral + pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Enable NFC sense field mode, change state to sense mode + pub const TASKS_SENSE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Start transmission of a outgoing frame, change state to transmit + pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Initializes the EasyDMA for receive. + pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Force state machine to IDLE state + pub const TASKS_GOIDLE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Force state machine to SLEEP_A state + pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, Address + 0x00000028); + + /// The NFC peripheral is ready to receive and send frames + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Remote NFC field detected + pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Remote NFC field lost + pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Marks the start of the first symbol of a transmitted frame + pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Marks the end of the last transmitted on-air symbol of a frame + pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Marks the end of the first symbol of a received frame + pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Received data have been checked (CRC, parity) and transferred to RAM, and + /// EasyDMA has ended accessing the RX buffer + pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// NFC error reported. The ERRORSTATUS register contains details on the source + /// of the error. + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on + /// the source of the error. + pub const EVENTS_RXERROR = @intToPtr(*volatile u32, Address + 0x00000128); + + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x0000012c); + + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the + /// TX buffer + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000130); + + /// Auto collision resolution process has started + pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, Address + 0x00000138); + + /// NFC Auto collision resolution error reported. + pub const EVENTS_COLLISION = @intToPtr(*volatile u32, Address + 0x00000148); + + /// NFC Auto collision resolution successfully completed + pub const EVENTS_SELECTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// EasyDMA is ready to receive or send frames. + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000150); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE: u1 = 0, + /// Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for READY event + READY: u1 = 0, + /// Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Enable or disable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Enable or disable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Enable or disable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Enable or disable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Write '1' to Enable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1 = 0, + /// Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST: u1 = 0, + /// Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1 = 0, + /// Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1 = 0, + /// Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1 = 0, + /// Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for RXERROR event + RXERROR: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved3: u1 = 0, + /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for COLLISION event + COLLISION: u1 = 0, + /// Write '1' to Disable interrupt for SELECTED event + SELECTED: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC Error Status register + pub const ERRORSTATUS = mmio(Address + 0x00000404, 32, packed struct { + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1 = 0, + reserved1: u1 = 0, + /// Field level is too high at max load resistance + NFCFIELDTOOSTRONG: u1 = 0, + /// Field level is too low at min load resistance + NFCFIELDTOOWEAK: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current value driven to the NFC Load Control + pub const CURRENTLOADCTRL = mmio(Address + 0x00000430, 32, packed struct { + /// Current value driven to the NFC Load Control + CURRENTLOADCTRL: u6 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Indicates the presence or not of a valid field + pub const FIELDPRESENT = mmio(Address + 0x0000043c, 32, packed struct { + /// Indicates the presence or not of a valid field. Available only in the + /// activated state. + FIELDPRESENT: u1 = 0, + /// Indicates if the low level has locked to the field + LOCKDETECT: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Minimum frame delay + pub const FRAMEDELAYMIN = mmio(Address + 0x00000504, 32, packed struct { + /// Minimum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMIN: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Maximum frame delay + pub const FRAMEDELAYMAX = mmio(Address + 0x00000508, 32, packed struct { + /// Maximum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMAX: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register for the Frame Delay Timer + pub const FRAMEDELAYMODE = mmio(Address + 0x0000050c, 32, packed struct { + /// Configuration register for the Frame Delay Timer + FRAMEDELAYMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Packet pointer for TXD and RXD data storage in Data RAM + pub const PACKETPTR = mmio(Address + 0x00000510, 32, packed struct { + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a + /// byte aligned RAM address. + PTR: u32 = 0, + }); + + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + pub const MAXLEN = mmio(Address + 0x00000514, 32, packed struct { + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN: u9 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Last NFCID1 part (4, 7 or 10 bytes ID) + pub const NFCID1_LAST = mmio(Address + 0x00000590, 32, packed struct { + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8 = 0, + /// NFCID1 byte Y + NFCID1_Y: u8 = 0, + /// NFCID1 byte X + NFCID1_X: u8 = 0, + /// NFCID1 byte W + NFCID1_W: u8 = 0, + }); + + /// Second last NFCID1 part (7 or 10 bytes ID) + pub const NFCID1_2ND_LAST = mmio(Address + 0x00000594, 32, packed struct { + /// NFCID1 byte V + NFCID1_V: u8 = 0, + /// NFCID1 byte U + NFCID1_U: u8 = 0, + /// NFCID1 byte T + NFCID1_T: u8 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Third last NFCID1 part (10 bytes ID) + pub const NFCID1_3RD_LAST = mmio(Address + 0x00000598, 32, packed struct { + /// NFCID1 byte S + NFCID1_S: u8 = 0, + /// NFCID1 byte R + NFCID1_R: u8 = 0, + /// NFCID1 byte Q + NFCID1_Q: u8 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC-A SENS_RES auto-response settings + pub const SENSRES = mmio(Address + 0x000005a0, 32, packed struct { + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the + /// NFC Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: u5 = 0, + /// Reserved for future use. Shall be 0. + RFU5: u1 = 0, + /// NFCID1 size. This value is used by the Auto collision resolution engine. + NFCIDSIZE: u2 = 0, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES + /// response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4 = 0, + /// Reserved for future use. Shall be 0. + RFU74: u4 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// NFC-A SEL_RES auto-response settings + pub const SELRES = mmio(Address + 0x000005a4, 32, packed struct { + /// Reserved for future use. Shall be 0. + RFU10: u2 = 0, + /// Cascade bit (controlled by hardware, write has no effect) + CASCADE: u1 = 0, + /// Reserved for future use. Shall be 0. + RFU43: u2 = 0, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC + /// Digital Protocol Technical Specification + PROTOCOL: u2 = 0, + /// Reserved for future use. Shall be 0. + RFU7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const FRAMESTATUS = struct { + + /// Result of last incoming frames + pub const RX = mmio(Address + 0x00000000, 32, packed struct { + /// No valid End of Frame detected + CRCERROR: u1 = 0, + reserved1: u1 = 0, + /// Parity status of received frame + PARITYSTATUS: u1 = 0, + /// Overrun detected + OVERRUN: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const TXD = struct { + + /// Configuration of outgoing frames + pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { + /// Adding parity or not in the frame + PARITY: u1 = 0, + /// Discarding unused bits in start or at end of a Frame + DISCARDMODE: u1 = 0, + /// Adding SoF or not in TX frames + SOF: u1 = 0, + reserved1: u1 = 0, + /// CRC mode for outgoing frames + CRCMODETX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Size of outgoing frame + pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { + /// Number of bits in the last or first byte read from RAM that shall be + /// included in the frame (excluding parity bit). + TXDATABITS: u3 = 0, + /// Number of complete bytes that shall be included in the frame, excluding CRC, + /// parity and framing + TXDATABYTES: u9 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Configuration of incoming frames + pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { + /// Parity expected or not in RX frame + PARITY: u1 = 0, + reserved1: u1 = 0, + /// SoF expected or not in RX frames + SOF: u1 = 0, + reserved2: u1 = 0, + /// CRC mode for incoming frames + CRCMODERX: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Size of last incoming frame + pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { + /// Number of bits in the last byte in the frame, if less than 8 (including CRC, + /// but excluding parity and SoF/EoF framing). + RXDATABITS: u3 = 0, + /// Number of complete bytes received in the frame (including CRC, but excluding + /// parity and SoF/EoF framing) + RXDATABYTES: u9 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// GPIO Tasks and Events +pub const GPIOTE = extern struct { + pub const Address: u32 = 0x40006000; + + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + pub const EVENTS_PORT = @intToPtr(*volatile u32, Address + 0x0000017c); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for IN[0] event + IN0: u1 = 0, + /// Write '1' to Enable interrupt for IN[1] event + IN1: u1 = 0, + /// Write '1' to Enable interrupt for IN[2] event + IN2: u1 = 0, + /// Write '1' to Enable interrupt for IN[3] event + IN3: u1 = 0, + /// Write '1' to Enable interrupt for IN[4] event + IN4: u1 = 0, + /// Write '1' to Enable interrupt for IN[5] event + IN5: u1 = 0, + /// Write '1' to Enable interrupt for IN[6] event + IN6: u1 = 0, + /// Write '1' to Enable interrupt for IN[7] event + IN7: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for PORT event + PORT: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for IN[0] event + IN0: u1 = 0, + /// Write '1' to Disable interrupt for IN[1] event + IN1: u1 = 0, + /// Write '1' to Disable interrupt for IN[2] event + IN2: u1 = 0, + /// Write '1' to Disable interrupt for IN[3] event + IN3: u1 = 0, + /// Write '1' to Disable interrupt for IN[4] event + IN4: u1 = 0, + /// Write '1' to Disable interrupt for IN[5] event + IN5: u1 = 0, + /// Write '1' to Disable interrupt for IN[6] event + IN6: u1 = 0, + /// Write '1' to Disable interrupt for IN[7] event + IN7: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for PORT event + PORT: u1 = 0, + }); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + pub const TASKS_OUT = @intToPtr(*volatile [8]u32, Address + 0x00000000); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is to set it high. + pub const TASKS_SET = @intToPtr(*volatile [8]u32, Address + 0x00000030); + /// Description collection[0]: Task for writing to pin specified in + /// CONFIG[0].PSEL. Action on pin is to set it low. + pub const TASKS_CLR = @intToPtr(*volatile [8]u32, Address + 0x00000060); + /// Description collection[0]: Event generated from pin specified in + /// CONFIG[0].PSEL + pub const EVENTS_IN = @intToPtr(*volatile [8]u32, Address + 0x00000100); + /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks + /// and IN[n] event + pub const CONFIG = @intToPtr(*volatile [8]MMIO(32, packed struct { + /// Mode + MODE: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + /// When In task mode: Operation to be performed on output when OUT[n] task is + /// triggered. When In event mode: Operation on input that shall trigger IN[n] + /// event. + POLARITY: u2 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + /// When in task mode: Initial value of the output when the GPIOTE channel is + /// configured. When in event mode: No effect. + OUTINIT: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000510); +}; + +/// Analog to Digital Converter +pub const SAADC = extern struct { + pub const Address: u32 = 0x40007000; + + /// Start the ADC and prepare the result buffer in RAM + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Take one ADC sample, if scan is enabled all channels are sampled + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Stop the ADC and terminate any on-going conversion + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Starts offset auto-calibration + pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// The ADC has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// The ADC has filled up the Result buffer + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// A conversion task has been completed. Depending on the mode, multiple + /// conversions might be needed for a result to be transferred to RAM. + pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x00000108); + + /// A result is ready to get transferred to RAM. + pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Calibration is complete + pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, Address + 0x00000110); + + /// The ADC has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + /// Enable or disable interrupt for END event + END: u1 = 0, + /// Enable or disable interrupt for DONE event + DONE: u1 = 0, + /// Enable or disable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for DONE event + DONE: u1 = 0, + /// Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE: u1 = 0, + /// Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1 = 0, + /// Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1 = 0, + /// Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status + pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// Status + STATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable ADC + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable ADC + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Resolution configuration + pub const RESOLUTION = mmio(Address + 0x000005f0, 32, packed struct { + /// Set the resolution + VAL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The + /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher + /// RESOLUTION should be used. + pub const OVERSAMPLE = mmio(Address + 0x000005f4, 32, packed struct { + /// Oversample control + OVERSAMPLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Controls normal or continuous sample rate + pub const SAMPLERATE = mmio(Address + 0x000005f8, 32, packed struct { + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11 = 0, + reserved1: u1 = 0, + /// Select mode for sample rate control + MODE: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const RESULT = struct { + + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Maximum number of buffer words to transfer + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Maximum number of buffer words to transfer + MAXCNT: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of buffer words transferred since last START + pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + /// Number of buffer words transferred since last START. This register can be + /// read after an END or STOPPED event. + AMOUNT: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Timer/Counter 0 +pub const TIMER0 = extern struct { + pub const Address: u32 = 0x40008000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 1 +pub const TIMER1 = extern struct { + pub const Address: u32 = 0x40009000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 2 +pub const TIMER2 = extern struct { + pub const Address: u32 = 0x4000a000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Real time counter 0 +pub const RTC0 = extern struct { + pub const Address: u32 = 0x4000b000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Temperature Sensor +pub const TEMP = extern struct { + pub const Address: u32 = 0x4000c000; + + /// Start temperature measurement + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop temperature measurement + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Temperature measurement complete, data ready + pub const EVENTS_DATARDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for DATARDY event + DATARDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for DATARDY event + DATARDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Temperature in degC (0.25deg steps) + pub const TEMP = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Slope of 1st piece wise linear function + pub const A0 = mmio(Address + 0x00000520, 32, packed struct { + /// Slope of 1st piece wise linear function + A0: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 2nd piece wise linear function + pub const A1 = mmio(Address + 0x00000524, 32, packed struct { + /// Slope of 2nd piece wise linear function + A1: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 3rd piece wise linear function + pub const A2 = mmio(Address + 0x00000528, 32, packed struct { + /// Slope of 3rd piece wise linear function + A2: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 4th piece wise linear function + pub const A3 = mmio(Address + 0x0000052c, 32, packed struct { + /// Slope of 4th piece wise linear function + A3: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 5th piece wise linear function + pub const A4 = mmio(Address + 0x00000530, 32, packed struct { + /// Slope of 5th piece wise linear function + A4: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Slope of 6th piece wise linear function + pub const A5 = mmio(Address + 0x00000534, 32, packed struct { + /// Slope of 6th piece wise linear function + A5: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 1st piece wise linear function + pub const B0 = mmio(Address + 0x00000540, 32, packed struct { + /// y-intercept of 1st piece wise linear function + B0: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 2nd piece wise linear function + pub const B1 = mmio(Address + 0x00000544, 32, packed struct { + /// y-intercept of 2nd piece wise linear function + B1: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 3rd piece wise linear function + pub const B2 = mmio(Address + 0x00000548, 32, packed struct { + /// y-intercept of 3rd piece wise linear function + B2: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 4th piece wise linear function + pub const B3 = mmio(Address + 0x0000054c, 32, packed struct { + /// y-intercept of 4th piece wise linear function + B3: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 5th piece wise linear function + pub const B4 = mmio(Address + 0x00000550, 32, packed struct { + /// y-intercept of 5th piece wise linear function + B4: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// y-intercept of 6th piece wise linear function + pub const B5 = mmio(Address + 0x00000554, 32, packed struct { + /// y-intercept of 6th piece wise linear function + B5: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 1st piece wise linear function + pub const T0 = mmio(Address + 0x00000560, 32, packed struct { + /// End point of 1st piece wise linear function + T0: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 2nd piece wise linear function + pub const T1 = mmio(Address + 0x00000564, 32, packed struct { + /// End point of 2nd piece wise linear function + T1: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 3rd piece wise linear function + pub const T2 = mmio(Address + 0x00000568, 32, packed struct { + /// End point of 3rd piece wise linear function + T2: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 4th piece wise linear function + pub const T3 = mmio(Address + 0x0000056c, 32, packed struct { + /// End point of 4th piece wise linear function + T3: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// End point of 5th piece wise linear function + pub const T4 = mmio(Address + 0x00000570, 32, packed struct { + /// End point of 5th piece wise linear function + T4: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Random Number Generator +pub const RNG = extern struct { + pub const Address: u32 = 0x4000d000; + + /// Task starting the random number generator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Task stopping the random number generator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Event being generated for every new random number written to the VALUE + /// register + pub const EVENTS_VALRDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between VALRDY event and STOP task + VALRDY_STOP: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for VALRDY event + VALRDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for VALRDY event + VALRDY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { + /// Bias correction + DERCEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Output random number + pub const VALUE = mmio(Address + 0x00000508, 32, packed struct { + /// Generated random number + VALUE: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// AES ECB Mode Encryption +pub const ECB = extern struct { + pub const Address: u32 = 0x4000e000; + + /// Start ECB block encrypt + pub const TASKS_STARTECB = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Abort a possible executing ECB operation + pub const TASKS_STOPECB = @intToPtr(*volatile u32, Address + 0x00000004); + + /// ECB block encrypt complete + pub const EVENTS_ENDECB = @intToPtr(*volatile u32, Address + 0x00000100); + + /// ECB block encrypt aborted because of a STOPECB task or due to an error + pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for ENDECB event + ENDECB: u1 = 0, + /// Write '1' to Enable interrupt for ERRORECB event + ERRORECB: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for ENDECB event + ENDECB: u1 = 0, + /// Write '1' to Disable interrupt for ERRORECB event + ERRORECB: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// ECB block encrypt memory pointers + pub const ECBDATAPTR = @intToPtr(*volatile u32, Address + 0x00000504); +}; + +/// AES CCM Mode Encryption +pub const CCM = extern struct { + pub const Address: u32 = 0x4000f000; + + /// Start generation of key-stream. This operation will stop by itself when + /// completed. + pub const TASKS_KSGEN = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Start encryption/decryption. This operation will stop by itself when + /// completed. + pub const TASKS_CRYPT = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Stop encryption/decryption + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Key-stream generation complete + pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Encrypt/decrypt complete + pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, Address + 0x00000104); + + /// CCM error event + pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN: u1 = 0, + /// Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT: u1 = 0, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN: u1 = 0, + /// Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT: u1 = 0, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// MIC check result + pub const MICSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// The result of the MIC check performed during the previous decryption + /// operation + MICSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable CCM + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Operation mode + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// The mode of operation to be used + MODE: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Data rate that the CCM shall run in synch with + DATARATE: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + /// Packet length configuration + LENGTH: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pointer to data structure holding AES key and NONCE vector + pub const CNFPTR = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Input pointer + pub const INPTR = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Output pointer + pub const OUTPTR = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); +}; + +/// Accelerated Address Resolver +pub const AAR = extern struct { + pub const Address: u32 = 0x4000f000; + + /// Start resolving addresses based on IRKs specified in the IRK data structure + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop resolving addresses + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Address resolution procedure complete + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Address resolved + pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Address not resolved + pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + /// Write '1' to Enable interrupt for RESOLVED event + RESOLVED: u1 = 0, + /// Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + /// Write '1' to Disable interrupt for RESOLVED event + RESOLVED: u1 = 0, + /// Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Resolution status + pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// The IRK that was used last time an address was resolved + STATUS: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable AAR + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable AAR + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Number of IRKs + pub const NIRK = mmio(Address + 0x00000504, 32, packed struct { + /// Number of Identity root keys available in the IRK data structure + NIRK: u5 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pointer to IRK data structure + pub const IRKPTR = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Pointer to the resolvable address + pub const ADDRPTR = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); +}; + +/// Watchdog Timer +pub const WDT = extern struct { + pub const Address: u32 = 0x40010000; + + /// Start the watchdog + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Watchdog timeout + pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Run status + pub const RUNSTATUS = mmio(Address + 0x00000400, 32, packed struct { + /// Indicates whether or not the watchdog is running + RUNSTATUS: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Request status + pub const REQSTATUS = mmio(Address + 0x00000404, 32, packed struct { + /// Request status for RR[0] register + RR0: u1 = 0, + /// Request status for RR[1] register + RR1: u1 = 0, + /// Request status for RR[2] register + RR2: u1 = 0, + /// Request status for RR[3] register + RR3: u1 = 0, + /// Request status for RR[4] register + RR4: u1 = 0, + /// Request status for RR[5] register + RR5: u1 = 0, + /// Request status for RR[6] register + RR6: u1 = 0, + /// Request status for RR[7] register + RR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Counter reload value + pub const CRV = @intToPtr(*volatile u32, Address + 0x00000504); + + /// Enable register for reload request registers + pub const RREN = mmio(Address + 0x00000508, 32, packed struct { + /// Enable or disable RR[0] register + RR0: u1 = 0, + /// Enable or disable RR[1] register + RR1: u1 = 0, + /// Enable or disable RR[2] register + RR2: u1 = 0, + /// Enable or disable RR[3] register + RR3: u1 = 0, + /// Enable or disable RR[4] register + RR4: u1 = 0, + /// Enable or disable RR[5] register + RR5: u1 = 0, + /// Enable or disable RR[6] register + RR6: u1 = 0, + /// Enable or disable RR[7] register + RR7: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x0000050c, 32, packed struct { + /// Configure the watchdog to either be paused, or kept running, while the CPU + /// is sleeping + SLEEP: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Configure the watchdog to either be paused, or kept running, while the CPU + /// is halted by the debugger + HALT: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Reload request 0 + pub const RR = @intToPtr(*volatile [8]u32, Address + 0x00000600); +}; + +/// Real time counter 1 +pub const RTC1 = extern struct { + pub const Address: u32 = 0x40011000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Quadrature Decoder +pub const QDEC = extern struct { + pub const Address: u32 = 0x40012000; + + /// Task starting the quadrature decoder + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Task stopping the quadrature decoder + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Read and clear ACC and ACCDBL + pub const TASKS_READCLRACC = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Read and clear ACC + pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Read and clear ACCDBL + pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Event being generated for every new sample value written to the SAMPLE + /// register + pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Non-null report ready + pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, Address + 0x00000104); + + /// ACC or ACCDBL register overflow + pub const EVENTS_ACCOF = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Double displacement(s) detected + pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// QDEC has been stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC: u1 = 0, + /// Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP: u1 = 0, + /// Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC: u1 = 0, + /// Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP: u1 = 0, + /// Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL: u1 = 0, + /// Shortcut between DBLRDY event and STOP task + DBLRDY_STOP: u1 = 0, + /// Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY: u1 = 0, + /// Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY: u1 = 0, + /// Write '1' to Enable interrupt for ACCOF event + ACCOF: u1 = 0, + /// Write '1' to Enable interrupt for DBLRDY event + DBLRDY: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY: u1 = 0, + /// Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY: u1 = 0, + /// Write '1' to Disable interrupt for ACCOF event + ACCOF: u1 = 0, + /// Write '1' to Disable interrupt for DBLRDY event + DBLRDY: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable the quadrature decoder + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable the quadrature decoder + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// LED output pin polarity + pub const LEDPOL = mmio(Address + 0x00000504, 32, packed struct { + /// LED output pin polarity + LEDPOL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Sample period + pub const SAMPLEPER = mmio(Address + 0x00000508, 32, packed struct { + /// Sample period. The SAMPLE register will be updated for every new sample + SAMPLEPER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Motion sample value + pub const SAMPLE = @intToPtr(*volatile u32, Address + 0x0000050c); + + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be + /// generated + pub const REPORTPER = mmio(Address + 0x00000510, 32, packed struct { + /// Specifies the number of samples to be accumulated in the ACC register before + /// the REPORTRDY and DBLRDY events can be generated + REPORTPER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register accumulating the valid transitions + pub const ACC = @intToPtr(*volatile u32, Address + 0x00000514); + + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + pub const ACCREAD = @intToPtr(*volatile u32, Address + 0x00000518); + + /// Enable input debounce filters + pub const DBFEN = mmio(Address + 0x00000528, 32, packed struct { + /// Enable input debounce filters + DBFEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Time period the LED is switched ON prior to sampling + pub const LEDPRE = mmio(Address + 0x00000540, 32, packed struct { + /// Period in us the LED is switched on prior to sampling + LEDPRE: u9 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register accumulating the number of detected double transitions + pub const ACCDBL = mmio(Address + 0x00000544, 32, packed struct { + /// Register accumulating the number of detected double or illegal transitions. + /// ( SAMPLE = 2 ). + ACCDBL: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + pub const ACCDBLREAD = mmio(Address + 0x00000548, 32, packed struct { + /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC + /// or RDCLRDBL task is triggered. + ACCDBLREAD: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin select for LED signal + pub const LED = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for A signal + pub const A = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for B signal + pub const B = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; +}; + +/// Comparator +pub const COMP = extern struct { + pub const Address: u32 = 0x40013000; + + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// COMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1 = 0, + /// Shortcut between READY event and STOP task + READY_STOP: u1 = 0, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1 = 0, + /// Shortcut between UP event and STOP task + UP_STOP: u1 = 0, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for READY event + READY: u1 = 0, + /// Enable or disable interrupt for DOWN event + DOWN: u1 = 0, + /// Enable or disable interrupt for UP event + UP: u1 = 0, + /// Enable or disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Enable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Disable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Compare result + pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { + /// Result of last compare. Decision point SAMPLE task. + RESULT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// COMP enable + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable COMP + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Pin select + pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { + /// Analog pin select + PSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reference source select for single-ended mode + pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// Reference select + REFSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// External reference select + pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { + /// External analog reference select + EXTREFSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Threshold configuration for hysteresis unit + pub const TH = mmio(Address + 0x00000530, 32, packed struct { + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// VUP = (THUP+1)/64*VREF + THUP: u6 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Mode configuration + pub const MODE = mmio(Address + 0x00000534, 32, packed struct { + /// Speed and power modes + SP: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Main operation modes + MAIN: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Comparator hysteresis enable + pub const HYST = mmio(Address + 0x00000538, 32, packed struct { + /// Comparator hysteresis + HYST: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current source select on analog input + pub const ISOURCE = mmio(Address + 0x0000053c, 32, packed struct { + /// Comparator hysteresis + ISOURCE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Low Power Comparator +pub const LPCOMP = extern struct { + pub const Address: u32 = 0x40013000; + + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); + + /// LPCOMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1 = 0, + /// Shortcut between READY event and STOP task + READY_STOP: u1 = 0, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1 = 0, + /// Shortcut between UP event and STOP task + UP_STOP: u1 = 0, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Enable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1 = 0, + /// Write '1' to Disable interrupt for UP event + UP: u1 = 0, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Compare result + pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { + /// Result of last compare. Decision point SAMPLE task. + RESULT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable LPCOMP + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable LPCOMP + ENABLE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Input pin select + pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { + /// Analog pin select + PSEL: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reference select + pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// Reference select + REFSEL: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// External reference select + pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { + /// External analog reference select + EXTREFSEL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Analog detect configuration + pub const ANADETECT = mmio(Address + 0x00000520, 32, packed struct { + /// Analog detect configuration + ANADETECT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Comparator hysteresis enable + pub const HYST = mmio(Address + 0x00000538, 32, packed struct { + /// Comparator hysteresis enable + HYST: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Software interrupt 0 +pub const SWI0 = extern struct { + pub const Address: u32 = 0x40014000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 0 +pub const EGU0 = extern struct { + pub const Address: u32 = 0x40014000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 1 +pub const SWI1 = extern struct { + pub const Address: u32 = 0x40015000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 1 +pub const EGU1 = extern struct { + pub const Address: u32 = 0x40015000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 2 +pub const SWI2 = extern struct { + pub const Address: u32 = 0x40016000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 2 +pub const EGU2 = extern struct { + pub const Address: u32 = 0x40016000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 3 +pub const SWI3 = extern struct { + pub const Address: u32 = 0x40017000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 3 +pub const EGU3 = extern struct { + pub const Address: u32 = 0x40017000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 4 +pub const SWI4 = extern struct { + pub const Address: u32 = 0x40018000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 4 +pub const EGU4 = extern struct { + pub const Address: u32 = 0x40018000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Software interrupt 5 +pub const SWI5 = extern struct { + pub const Address: u32 = 0x40019000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// Event Generator Unit 5 +pub const EGU5 = extern struct { + pub const Address: u32 = 0x40019000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1 = 0, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); +}; + +/// Timer/Counter 3 +pub const TIMER3 = extern struct { + pub const Address: u32 = 0x4001a000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Timer/Counter 4 +pub const TIMER4 = extern struct { + pub const Address: u32 = 0x4001b000; + + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1 = 0, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1 = 0, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1 = 0, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1 = 0, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1 = 0, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1 = 0, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1 = 0, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1 = 0, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1 = 0, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1 = 0, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer mode selection + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Timer mode + MODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configure the number of bits used by the TIMER + pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { + /// Timer bit width + BITMODE: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Timer prescaler register + pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { + /// Prescaler value + PRESCALER: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); +}; + +/// Pulse Width Modulation Unit 0 +pub const PWM0 = extern struct { + pub const Address: u32 = 0x4001c000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); + + pub const PSEL = struct { + /// Description collection[0]: Output pin select for PWM channel 0 + pub const OUT = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }), Address + 0x00000000); + }; +}; + +/// Pulse Density Modulation (Digital Microphone) Interface +pub const PDM = extern struct { + pub const Address: u32 = 0x4001d000; + + /// Starts continuous PDM transfer + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stops PDM transfer + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// PDM transfer has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); + + /// PDM transfer has finished + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last + /// sample after a STOP task has been received) to Data RAM + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for STARTED event + STARTED: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PDM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PDM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PDM clock generator control + pub const PDMCLKCTRL = mmio(Address + 0x00000504, 32, packed struct { + /// PDM_CLK frequency + FREQ: u32 = 0, + }); + + /// Defines the routing of the connected PDM microphones' signals + pub const MODE = mmio(Address + 0x00000508, 32, packed struct { + /// Mono or stereo operation + OPERATION: u1 = 0, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Left output gain adjustment + pub const GAINL = mmio(Address + 0x00000518, 32, packed struct { + /// Left output gain adjustment, in 0.5 dB steps, around the default module gain + /// (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain + /// adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB + /// gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + GAINL: u7 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Right output gain adjustment + pub const GAINR = mmio(Address + 0x0000051c, 32, packed struct { + /// Right output gain adjustment, in 0.5 dB steps, around the default module + /// gain (see electrical parameters) + GAINR: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const PSEL = struct { + + /// Pin number configuration for PDM CLK signal + pub const CLK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin number configuration for PDM DIN signal + pub const DIN = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; + + pub const SAMPLE = struct { + + /// RAM address pointer to write samples to with EasyDMA + pub const PTR = mmio(Address + 0x00000000, 32, packed struct { + /// Address to write PDM samples to over DMA + SAMPLEPTR: u32 = 0, + }); + + /// Number of samples to allocate memory for in EasyDMA mode + pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// Length of DMA RAM allocation in number of samples + BUFFSIZE: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; +}; + +/// Non Volatile Memory Controller +pub const NVMC = extern struct { + pub const Address: u32 = 0x4001e000; + + /// Ready flag + pub const READY = mmio(Address + 0x00000400, 32, packed struct { + /// NVMC is ready or busy + READY: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { + /// Program memory access mode. It is strongly recommended to only activate + /// erase and write modes when they are actively used. Enabling write or erase + /// will invalidate the cache and keep it invalidated. + WEN: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Register for erasing a page in Code area + pub const ERASEPAGE = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Deprecated register - Register for erasing a page in Code area. Equivalent + /// to ERASEPAGE. + pub const ERASEPCR1 = @intToPtr(*volatile u32, Address + 0x00000508); + + /// Register for erasing all non-volatile user memory + pub const ERASEALL = mmio(Address + 0x0000050c, 32, packed struct { + /// Erase all non-volatile memory including UICR registers. Note that code erase + /// has to be enabled by CONFIG.EEN before the UICR can be erased. + ERASEALL: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Deprecated register - Register for erasing a page in Code area. Equivalent + /// to ERASEPAGE. + pub const ERASEPCR0 = @intToPtr(*volatile u32, Address + 0x00000510); + + /// Register for erasing User Information Configuration Registers + pub const ERASEUICR = mmio(Address + 0x00000514, 32, packed struct { + /// Register starting erase of all User Information Configuration Registers. + /// Note that code erase has to be enabled by CONFIG.EEN before the UICR can be + /// erased. + ERASEUICR: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// I-Code cache configuration register. + pub const ICACHECNF = mmio(Address + 0x00000540, 32, packed struct { + /// Cache enable + CACHEEN: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Cache profiling enable + CACHEPROFEN: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// I-Code cache hit counter. + pub const IHIT = mmio(Address + 0x00000548, 32, packed struct { + /// Number of cache hits + HITS: u32 = 0, + }); + + /// I-Code cache miss counter. + pub const IMISS = mmio(Address + 0x0000054c, 32, packed struct { + /// Number of cache misses + MISSES: u32 = 0, + }); +}; + +/// Programmable Peripheral Interconnect +pub const PPI = extern struct { + pub const Address: u32 = 0x4001f000; + + /// Channel enable register + pub const CHEN = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable channel 0 + CH0: u1 = 0, + /// Enable or disable channel 1 + CH1: u1 = 0, + /// Enable or disable channel 2 + CH2: u1 = 0, + /// Enable or disable channel 3 + CH3: u1 = 0, + /// Enable or disable channel 4 + CH4: u1 = 0, + /// Enable or disable channel 5 + CH5: u1 = 0, + /// Enable or disable channel 6 + CH6: u1 = 0, + /// Enable or disable channel 7 + CH7: u1 = 0, + /// Enable or disable channel 8 + CH8: u1 = 0, + /// Enable or disable channel 9 + CH9: u1 = 0, + /// Enable or disable channel 10 + CH10: u1 = 0, + /// Enable or disable channel 11 + CH11: u1 = 0, + /// Enable or disable channel 12 + CH12: u1 = 0, + /// Enable or disable channel 13 + CH13: u1 = 0, + /// Enable or disable channel 14 + CH14: u1 = 0, + /// Enable or disable channel 15 + CH15: u1 = 0, + /// Enable or disable channel 16 + CH16: u1 = 0, + /// Enable or disable channel 17 + CH17: u1 = 0, + /// Enable or disable channel 18 + CH18: u1 = 0, + /// Enable or disable channel 19 + CH19: u1 = 0, + /// Enable or disable channel 20 + CH20: u1 = 0, + /// Enable or disable channel 21 + CH21: u1 = 0, + /// Enable or disable channel 22 + CH22: u1 = 0, + /// Enable or disable channel 23 + CH23: u1 = 0, + /// Enable or disable channel 24 + CH24: u1 = 0, + /// Enable or disable channel 25 + CH25: u1 = 0, + /// Enable or disable channel 26 + CH26: u1 = 0, + /// Enable or disable channel 27 + CH27: u1 = 0, + /// Enable or disable channel 28 + CH28: u1 = 0, + /// Enable or disable channel 29 + CH29: u1 = 0, + /// Enable or disable channel 30 + CH30: u1 = 0, + /// Enable or disable channel 31 + CH31: u1 = 0, + }); + + /// Channel enable set register + pub const CHENSET = mmio(Address + 0x00000504, 32, packed struct { + /// Channel 0 enable set register. Writing '0' has no effect + CH0: u1 = 0, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: u1 = 0, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: u1 = 0, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: u1 = 0, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: u1 = 0, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: u1 = 0, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: u1 = 0, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: u1 = 0, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: u1 = 0, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: u1 = 0, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: u1 = 0, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: u1 = 0, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: u1 = 0, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: u1 = 0, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: u1 = 0, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: u1 = 0, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: u1 = 0, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: u1 = 0, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: u1 = 0, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: u1 = 0, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: u1 = 0, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: u1 = 0, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: u1 = 0, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: u1 = 0, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: u1 = 0, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: u1 = 0, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: u1 = 0, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: u1 = 0, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: u1 = 0, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: u1 = 0, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: u1 = 0, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: u1 = 0, + }); + + /// Channel enable clear register + pub const CHENCLR = mmio(Address + 0x00000508, 32, packed struct { + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: u1 = 0, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: u1 = 0, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: u1 = 0, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: u1 = 0, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: u1 = 0, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: u1 = 0, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: u1 = 0, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: u1 = 0, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: u1 = 0, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: u1 = 0, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: u1 = 0, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: u1 = 0, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: u1 = 0, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: u1 = 0, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: u1 = 0, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: u1 = 0, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: u1 = 0, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: u1 = 0, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: u1 = 0, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: u1 = 0, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: u1 = 0, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: u1 = 0, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: u1 = 0, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: u1 = 0, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: u1 = 0, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: u1 = 0, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: u1 = 0, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: u1 = 0, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: u1 = 0, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: u1 = 0, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: u1 = 0, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: u1 = 0, + }); + /// Description collection[0]: Channel group 0 + pub const CHG = @intToPtr(*volatile [6]MMIO(32, packed struct { + /// Include or exclude channel 0 + CH0: u1 = 0, + /// Include or exclude channel 1 + CH1: u1 = 0, + /// Include or exclude channel 2 + CH2: u1 = 0, + /// Include or exclude channel 3 + CH3: u1 = 0, + /// Include or exclude channel 4 + CH4: u1 = 0, + /// Include or exclude channel 5 + CH5: u1 = 0, + /// Include or exclude channel 6 + CH6: u1 = 0, + /// Include or exclude channel 7 + CH7: u1 = 0, + /// Include or exclude channel 8 + CH8: u1 = 0, + /// Include or exclude channel 9 + CH9: u1 = 0, + /// Include or exclude channel 10 + CH10: u1 = 0, + /// Include or exclude channel 11 + CH11: u1 = 0, + /// Include or exclude channel 12 + CH12: u1 = 0, + /// Include or exclude channel 13 + CH13: u1 = 0, + /// Include or exclude channel 14 + CH14: u1 = 0, + /// Include or exclude channel 15 + CH15: u1 = 0, + /// Include or exclude channel 16 + CH16: u1 = 0, + /// Include or exclude channel 17 + CH17: u1 = 0, + /// Include or exclude channel 18 + CH18: u1 = 0, + /// Include or exclude channel 19 + CH19: u1 = 0, + /// Include or exclude channel 20 + CH20: u1 = 0, + /// Include or exclude channel 21 + CH21: u1 = 0, + /// Include or exclude channel 22 + CH22: u1 = 0, + /// Include or exclude channel 23 + CH23: u1 = 0, + /// Include or exclude channel 24 + CH24: u1 = 0, + /// Include or exclude channel 25 + CH25: u1 = 0, + /// Include or exclude channel 26 + CH26: u1 = 0, + /// Include or exclude channel 27 + CH27: u1 = 0, + /// Include or exclude channel 28 + CH28: u1 = 0, + /// Include or exclude channel 29 + CH29: u1 = 0, + /// Include or exclude channel 30 + CH30: u1 = 0, + /// Include or exclude channel 31 + CH31: u1 = 0, + }), Address + 0x00000800); +}; + +/// Memory Watch Unit +pub const MWU = extern struct { + pub const Address: u32 = 0x40020000; + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + /// Enable or disable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Enable or disable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Enable or disable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Enable or disable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Enable or disable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Enable or disable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Enable or disable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Enable or disable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Enable or disable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Enable or disable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Enable or disable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable non-maskable interrupt + pub const NMIEN = mmio(Address + 0x00000320, 32, packed struct { + /// Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable non-maskable interrupt + pub const NMIENSET = mmio(Address + 0x00000324, 32, packed struct { + /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable non-maskable interrupt + pub const NMIENCLR = mmio(Address + 0x00000328, 32, packed struct { + /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1 = 0, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable/disable regions watch + pub const REGIONEN = mmio(Address + 0x00000510, 32, packed struct { + /// Enable/disable write access watch in region[0] + RGN0WA: u1 = 0, + /// Enable/disable read access watch in region[0] + RGN0RA: u1 = 0, + /// Enable/disable write access watch in region[1] + RGN1WA: u1 = 0, + /// Enable/disable read access watch in region[1] + RGN1RA: u1 = 0, + /// Enable/disable write access watch in region[2] + RGN2WA: u1 = 0, + /// Enable/disable read access watch in region[2] + RGN2RA: u1 = 0, + /// Enable/disable write access watch in region[3] + RGN3WA: u1 = 0, + /// Enable/disable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable regions watch + pub const REGIONENSET = mmio(Address + 0x00000514, 32, packed struct { + /// Enable write access watch in region[0] + RGN0WA: u1 = 0, + /// Enable read access watch in region[0] + RGN0RA: u1 = 0, + /// Enable write access watch in region[1] + RGN1WA: u1 = 0, + /// Enable read access watch in region[1] + RGN1RA: u1 = 0, + /// Enable write access watch in region[2] + RGN2WA: u1 = 0, + /// Enable read access watch in region[2] + RGN2RA: u1 = 0, + /// Enable write access watch in region[3] + RGN3WA: u1 = 0, + /// Enable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Enable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Enable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Enable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable regions watch + pub const REGIONENCLR = mmio(Address + 0x00000518, 32, packed struct { + /// Disable write access watch in region[0] + RGN0WA: u1 = 0, + /// Disable read access watch in region[0] + RGN0RA: u1 = 0, + /// Disable write access watch in region[1] + RGN1WA: u1 = 0, + /// Disable read access watch in region[1] + RGN1RA: u1 = 0, + /// Disable write access watch in region[2] + RGN2WA: u1 = 0, + /// Disable read access watch in region[2] + RGN2RA: u1 = 0, + /// Disable write access watch in region[3] + RGN3WA: u1 = 0, + /// Disable read access watch in region[3] + RGN3RA: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Disable write access watch in PREGION[0] + PRGN0WA: u1 = 0, + /// Disable read access watch in PREGION[0] + PRGN0RA: u1 = 0, + /// Disable write access watch in PREGION[1] + PRGN1WA: u1 = 0, + /// Disable read access watch in PREGION[1] + PRGN1RA: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Pulse Width Modulation Unit 1 +pub const PWM1 = extern struct { + pub const Address: u32 = 0x40021000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); +}; + +/// Pulse Width Modulation Unit 2 +pub const PWM2 = extern struct { + pub const Address: u32 = 0x40022000; + + /// Stops PWM pulse generation on all channels at the end of current PWM period, + /// and stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); + + /// Concatenated sequences have been played the amount of times defined in + /// LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1 = 0, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1 = 0, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1 = 0, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1 = 0, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1 = 0, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1 = 0, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1 = 0, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// PWM module enable register + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable PWM module + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Selects operating mode of the wave counter + pub const MODE = mmio(Address + 0x00000504, 32, packed struct { + /// Selects up or up and down as wave counter mode + UPDOWN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { + /// Value up to which the pulse generator counter counts. This register is + /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + COUNTERTOP: u15 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration for PWM_CLK + pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { + /// Pre-scaler of PWM_CLK + PRESCALER: u3 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration of the decoder + pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Selects source for advancing the active sequence + MODE: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Amount of playback of a loop + pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { + /// Amount of playback of pattern cycles + CNT: u16 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); + /// Description collection[0]: Emitted at end of every sequence 0, when last + /// value from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); +}; + +/// Serial Peripheral Interface Master with EasyDMA 2 +pub const SPIM2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); + + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); + + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); + + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); + + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); + + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); + + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and START task + END_START: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved5: u1 = 0, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPIM + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPIM + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// SPI Slave 2 +pub const SPIS2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); + + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); + + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); + + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); + + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); + + /// Shortcut register + pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for END event + END: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Semaphore status register + pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { + /// Semaphore status + SEMSTAT: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Status from last transaction + pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { + /// TX buffer over-read detected, and prevented + OVERREAD: u1 = 0, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI slave + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI slave + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + /// Default character. Character clocked out in case of an ignored transaction. + DEF: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Over-read character + pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// Over-read character. Character clocked out after an over-read of the + /// transmit buffer. + ORC: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Serial Peripheral Interface 2 +pub const SPI2 = extern struct { + pub const Address: u32 = 0x40023000; + + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for READY event + READY: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable SPI + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable or disable SPI + ENABLE: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// RXD register + pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// RX data received. Double buffered + RXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// TXD register + pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + /// TX data to send. Double buffered + TXD: u8 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); + + /// Configuration register + pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { + /// Bit order + ORDER: u1 = 0, + /// Serial clock (SCK) phase + CPHA: u1 = 0, + /// Serial clock (SCK) polarity + CPOL: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); +}; + +/// Real time counter 2 +pub const RTC2 = extern struct { + pub const Address: u32 = 0x40024000; + + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); + + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); + + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + /// Write '1' to Enable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + /// Write '1' to Disable interrupt for TICK event + TICK: u1 = 0, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable or disable event routing + pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { + /// Enable or disable event routing for TICK event + TICK: u1 = 0, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable event routing + pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { + /// Write '1' to Enable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable event routing + pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { + /// Write '1' to Disable event routing for TICK event + TICK: u1 = 0, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1 = 0, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Current COUNTER value + pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { + /// Counter value + COUNTER: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { + /// Prescaler value + PRESCALER: u12 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { + /// Compare value + COMPARE: u24 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000540); +}; + +/// Inter-IC Sound +pub const I2S = extern struct { + pub const Address: u32 = 0x40025000; + + /// Starts continuous I2S transfer. Also starts MCK generator when this is + /// enabled. + pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will + /// cause the {event:STOPPED} event to be generated. + pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); + + /// The RXD.PTR register has been copied to internal double-buffers. When the + /// I2S module is started and RX is enabled, this event will be generated for + /// every RXTXD.MAXCNT words that are received on the SDIN pin. + pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000104); + + /// I2S transfer stopped. + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000108); + + /// The TDX.PTR register has been copied to internal double-buffers. When the + /// I2S module is started and TX is enabled, this event will be generated for + /// every RXTXD.MAXCNT words that are sent on the SDOUT pin. + pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000114); + + /// Enable or disable interrupt + pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { + reserved1: u1 = 0, + /// Enable or disable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Enable or disable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable interrupt + pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Disable interrupt + pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { + reserved1: u1 = 0, + /// Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD: u1 = 0, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + /// Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable I2S module. + pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + /// Enable I2S module. + ENABLE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + pub const CONFIG = struct { + + /// I2S mode. + pub const MODE = mmio(Address + 0x00000000, 32, packed struct { + /// I2S mode. + MODE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Reception (RX) enable. + pub const RXEN = mmio(Address + 0x00000004, 32, packed struct { + /// Reception (RX) enable. + RXEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Transmission (TX) enable. + pub const TXEN = mmio(Address + 0x00000008, 32, packed struct { + /// Transmission (TX) enable. + TXEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Master clock generator enable. + pub const MCKEN = mmio(Address + 0x0000000c, 32, packed struct { + /// Master clock generator enable. + MCKEN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Master clock generator frequency. + pub const MCKFREQ = @intToPtr(*volatile u32, Address + 0x00000010); + + /// MCK / LRCK ratio. + pub const RATIO = mmio(Address + 0x00000014, 32, packed struct { + /// MCK / LRCK ratio. + RATIO: u4 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Sample width. + pub const SWIDTH = mmio(Address + 0x00000018, 32, packed struct { + /// Sample width. + SWIDTH: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Alignment of sample within a frame. + pub const ALIGN = mmio(Address + 0x0000001c, 32, packed struct { + /// Alignment of sample within a frame. + ALIGN: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Frame format. + pub const FORMAT = mmio(Address + 0x00000020, 32, packed struct { + /// Frame format. + FORMAT: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Enable channels. + pub const CHANNELS = mmio(Address + 0x00000024, 32, packed struct { + /// Enable channels. + CHANNELS: u2 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const RXD = struct { + + /// Receive buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + }; + + pub const TXD = struct { + + /// Transmit buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + }; + + pub const RXTXD = struct { + + /// Size of RXD and TXD buffers. + pub const MAXCNT = mmio(Address + 0x00000000, 32, packed struct { + /// Size of RXD and TXD buffers in number of 32 bit words. + MAXCNT: u14 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + }; + + pub const PSEL = struct { + + /// Pin select for MCK signal. + pub const MCK = mmio(Address + 0x00000000, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SCK signal. + pub const SCK = mmio(Address + 0x00000004, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for LRCK signal. + pub const LRCK = mmio(Address + 0x00000008, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDIN signal. + pub const SDIN = mmio(Address + 0x0000000c, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + + /// Pin select for SDOUT signal. + pub const SDOUT = mmio(Address + 0x00000010, 32, packed struct { + /// Pin number + PIN: u5 = 0, + reserved26: u1 = 0, + reserved25: u1 = 0, + reserved24: u1 = 0, + reserved23: u1 = 0, + reserved22: u1 = 0, + reserved21: u1 = 0, + reserved20: u1 = 0, + reserved19: u1 = 0, + reserved18: u1 = 0, + reserved17: u1 = 0, + reserved16: u1 = 0, + reserved15: u1 = 0, + reserved14: u1 = 0, + reserved13: u1 = 0, + reserved12: u1 = 0, + reserved11: u1 = 0, + reserved10: u1 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Connection + CONNECT: u1 = 0, + }); + }; +}; + +/// FPU +pub const FPU = extern struct { + pub const Address: u32 = 0x40026000; + + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); +}; + +/// GPIO Port 1 +pub const P0 = extern struct { + pub const Address: u32 = 0x50000000; + + /// Write GPIO port + pub const OUT = mmio(Address + 0x00000504, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Set individual bits in GPIO port + pub const OUTSET = mmio(Address + 0x00000508, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Clear individual bits in GPIO port + pub const OUTCLR = mmio(Address + 0x0000050c, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Read GPIO port + pub const IN = mmio(Address + 0x00000510, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// Direction of GPIO pins + pub const DIR = mmio(Address + 0x00000514, 32, packed struct { + /// Pin 0 + PIN0: u1 = 0, + /// Pin 1 + PIN1: u1 = 0, + /// Pin 2 + PIN2: u1 = 0, + /// Pin 3 + PIN3: u1 = 0, + /// Pin 4 + PIN4: u1 = 0, + /// Pin 5 + PIN5: u1 = 0, + /// Pin 6 + PIN6: u1 = 0, + /// Pin 7 + PIN7: u1 = 0, + /// Pin 8 + PIN8: u1 = 0, + /// Pin 9 + PIN9: u1 = 0, + /// Pin 10 + PIN10: u1 = 0, + /// Pin 11 + PIN11: u1 = 0, + /// Pin 12 + PIN12: u1 = 0, + /// Pin 13 + PIN13: u1 = 0, + /// Pin 14 + PIN14: u1 = 0, + /// Pin 15 + PIN15: u1 = 0, + /// Pin 16 + PIN16: u1 = 0, + /// Pin 17 + PIN17: u1 = 0, + /// Pin 18 + PIN18: u1 = 0, + /// Pin 19 + PIN19: u1 = 0, + /// Pin 20 + PIN20: u1 = 0, + /// Pin 21 + PIN21: u1 = 0, + /// Pin 22 + PIN22: u1 = 0, + /// Pin 23 + PIN23: u1 = 0, + /// Pin 24 + PIN24: u1 = 0, + /// Pin 25 + PIN25: u1 = 0, + /// Pin 26 + PIN26: u1 = 0, + /// Pin 27 + PIN27: u1 = 0, + /// Pin 28 + PIN28: u1 = 0, + /// Pin 29 + PIN29: u1 = 0, + /// Pin 30 + PIN30: u1 = 0, + /// Pin 31 + PIN31: u1 = 0, + }); + + /// DIR set register + pub const DIRSET = mmio(Address + 0x00000518, 32, packed struct { + /// Set as output pin 0 + PIN0: u1 = 0, + /// Set as output pin 1 + PIN1: u1 = 0, + /// Set as output pin 2 + PIN2: u1 = 0, + /// Set as output pin 3 + PIN3: u1 = 0, + /// Set as output pin 4 + PIN4: u1 = 0, + /// Set as output pin 5 + PIN5: u1 = 0, + /// Set as output pin 6 + PIN6: u1 = 0, + /// Set as output pin 7 + PIN7: u1 = 0, + /// Set as output pin 8 + PIN8: u1 = 0, + /// Set as output pin 9 + PIN9: u1 = 0, + /// Set as output pin 10 + PIN10: u1 = 0, + /// Set as output pin 11 + PIN11: u1 = 0, + /// Set as output pin 12 + PIN12: u1 = 0, + /// Set as output pin 13 + PIN13: u1 = 0, + /// Set as output pin 14 + PIN14: u1 = 0, + /// Set as output pin 15 + PIN15: u1 = 0, + /// Set as output pin 16 + PIN16: u1 = 0, + /// Set as output pin 17 + PIN17: u1 = 0, + /// Set as output pin 18 + PIN18: u1 = 0, + /// Set as output pin 19 + PIN19: u1 = 0, + /// Set as output pin 20 + PIN20: u1 = 0, + /// Set as output pin 21 + PIN21: u1 = 0, + /// Set as output pin 22 + PIN22: u1 = 0, + /// Set as output pin 23 + PIN23: u1 = 0, + /// Set as output pin 24 + PIN24: u1 = 0, + /// Set as output pin 25 + PIN25: u1 = 0, + /// Set as output pin 26 + PIN26: u1 = 0, + /// Set as output pin 27 + PIN27: u1 = 0, + /// Set as output pin 28 + PIN28: u1 = 0, + /// Set as output pin 29 + PIN29: u1 = 0, + /// Set as output pin 30 + PIN30: u1 = 0, + /// Set as output pin 31 + PIN31: u1 = 0, + }); + + /// DIR clear register + pub const DIRCLR = mmio(Address + 0x0000051c, 32, packed struct { + /// Set as input pin 0 + PIN0: u1 = 0, + /// Set as input pin 1 + PIN1: u1 = 0, + /// Set as input pin 2 + PIN2: u1 = 0, + /// Set as input pin 3 + PIN3: u1 = 0, + /// Set as input pin 4 + PIN4: u1 = 0, + /// Set as input pin 5 + PIN5: u1 = 0, + /// Set as input pin 6 + PIN6: u1 = 0, + /// Set as input pin 7 + PIN7: u1 = 0, + /// Set as input pin 8 + PIN8: u1 = 0, + /// Set as input pin 9 + PIN9: u1 = 0, + /// Set as input pin 10 + PIN10: u1 = 0, + /// Set as input pin 11 + PIN11: u1 = 0, + /// Set as input pin 12 + PIN12: u1 = 0, + /// Set as input pin 13 + PIN13: u1 = 0, + /// Set as input pin 14 + PIN14: u1 = 0, + /// Set as input pin 15 + PIN15: u1 = 0, + /// Set as input pin 16 + PIN16: u1 = 0, + /// Set as input pin 17 + PIN17: u1 = 0, + /// Set as input pin 18 + PIN18: u1 = 0, + /// Set as input pin 19 + PIN19: u1 = 0, + /// Set as input pin 20 + PIN20: u1 = 0, + /// Set as input pin 21 + PIN21: u1 = 0, + /// Set as input pin 22 + PIN22: u1 = 0, + /// Set as input pin 23 + PIN23: u1 = 0, + /// Set as input pin 24 + PIN24: u1 = 0, + /// Set as input pin 25 + PIN25: u1 = 0, + /// Set as input pin 26 + PIN26: u1 = 0, + /// Set as input pin 27 + PIN27: u1 = 0, + /// Set as input pin 28 + PIN28: u1 = 0, + /// Set as input pin 29 + PIN29: u1 = 0, + /// Set as input pin 30 + PIN30: u1 = 0, + /// Set as input pin 31 + PIN31: u1 = 0, + }); + + /// Latch register indicating what GPIO pins that have met the criteria set in + /// the PIN_CNF[n].SENSE registers + pub const LATCH = mmio(Address + 0x00000520, 32, packed struct { + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. + /// Write '1' to clear. + PIN0: u1 = 0, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. + /// Write '1' to clear. + PIN1: u1 = 0, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. + /// Write '1' to clear. + PIN2: u1 = 0, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. + /// Write '1' to clear. + PIN3: u1 = 0, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. + /// Write '1' to clear. + PIN4: u1 = 0, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. + /// Write '1' to clear. + PIN5: u1 = 0, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. + /// Write '1' to clear. + PIN6: u1 = 0, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. + /// Write '1' to clear. + PIN7: u1 = 0, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. + /// Write '1' to clear. + PIN8: u1 = 0, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. + /// Write '1' to clear. + PIN9: u1 = 0, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. + /// Write '1' to clear. + PIN10: u1 = 0, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. + /// Write '1' to clear. + PIN11: u1 = 0, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. + /// Write '1' to clear. + PIN12: u1 = 0, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. + /// Write '1' to clear. + PIN13: u1 = 0, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. + /// Write '1' to clear. + PIN14: u1 = 0, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. + /// Write '1' to clear. + PIN15: u1 = 0, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. + /// Write '1' to clear. + PIN16: u1 = 0, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. + /// Write '1' to clear. + PIN17: u1 = 0, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. + /// Write '1' to clear. + PIN18: u1 = 0, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. + /// Write '1' to clear. + PIN19: u1 = 0, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. + /// Write '1' to clear. + PIN20: u1 = 0, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. + /// Write '1' to clear. + PIN21: u1 = 0, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. + /// Write '1' to clear. + PIN22: u1 = 0, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. + /// Write '1' to clear. + PIN23: u1 = 0, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. + /// Write '1' to clear. + PIN24: u1 = 0, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. + /// Write '1' to clear. + PIN25: u1 = 0, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. + /// Write '1' to clear. + PIN26: u1 = 0, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. + /// Write '1' to clear. + PIN27: u1 = 0, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. + /// Write '1' to clear. + PIN28: u1 = 0, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. + /// Write '1' to clear. + PIN29: u1 = 0, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. + /// Write '1' to clear. + PIN30: u1 = 0, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. + /// Write '1' to clear. + PIN31: u1 = 0, + }); + + /// Select between default DETECT signal behaviour and LDETECT mode + pub const DETECTMODE = mmio(Address + 0x00000524, 32, packed struct { + /// Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE: u1 = 0, + padding31: u1 = 0, + padding30: u1 = 0, + padding29: u1 = 0, + padding28: u1 = 0, + padding27: u1 = 0, + padding26: u1 = 0, + padding25: u1 = 0, + padding24: u1 = 0, + padding23: u1 = 0, + padding22: u1 = 0, + padding21: u1 = 0, + padding20: u1 = 0, + padding19: u1 = 0, + padding18: u1 = 0, + padding17: u1 = 0, + padding16: u1 = 0, + padding15: u1 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + /// Description collection[0]: Configuration of GPIO pins + pub const PIN_CNF = @intToPtr(*volatile [32]MMIO(32, packed struct { + /// Pin direction. Same physical register as DIR register + DIR: u1 = 0, + /// Connect or disconnect input buffer + INPUT: u1 = 0, + /// Pull configuration + PULL: u2 = 0, + reserved4: u1 = 0, + reserved3: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Drive configuration + DRIVE: u3 = 0, + reserved9: u1 = 0, + reserved8: u1 = 0, + reserved7: u1 = 0, + reserved6: u1 = 0, + reserved5: u1 = 0, + /// Pin sensing mechanism + SENSE: u2 = 0, + padding14: u1 = 0, + padding13: u1 = 0, + padding12: u1 = 0, + padding11: u1 = 0, + padding10: u1 = 0, + padding9: u1 = 0, + padding8: u1 = 0, + padding7: u1 = 0, + padding6: u1 = 0, + padding5: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }), Address + 0x00000700); +}; + +const std = @import("std"); +const root = @import("root"); +const cpu = @import("cpu"); +const config = @import("microzig-config"); +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { + return InterruptVector{ + .C = struct { + fn unhandledInterrupt() callconv(.C) noreturn { + @panic("unhandled interrupt: " ++ str); + } + }.unhandledInterrupt, + }; +} + +pub const VectorTable = extern struct { + initial_stack_pointer: u32 = config.end_of_stack, + Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, + NMI: InterruptVector = makeUnhandledHandler("NMI"), + HardFault: InterruptVector = makeUnhandledHandler("HardFault"), + MemManage: InterruptVector = makeUnhandledHandler("MemManage"), + BusFault: InterruptVector = makeUnhandledHandler("BusFault"), + UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), + + reserved: [4]u32 = .{ 0, 0, 0, 0 }, + SVCall: InterruptVector = makeUnhandledHandler("SVCall"), + DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), + reserved1: u32 = 0, + + PendSV: InterruptVector = makeUnhandledHandler("PendSV"), + SysTick: InterruptVector = makeUnhandledHandler("SysTick"), + + POWER_CLOCK: InterruptVector = makeUnhandledHandler("POWER_CLOCK"), + RADIO: InterruptVector = makeUnhandledHandler("RADIO"), + UARTE0_UART0: InterruptVector = makeUnhandledHandler("UARTE0_UART0"), + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = makeUnhandledHandler("SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0"), + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = makeUnhandledHandler("SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1"), + NFCT: InterruptVector = makeUnhandledHandler("NFCT"), + GPIOTE: InterruptVector = makeUnhandledHandler("GPIOTE"), + SAADC: InterruptVector = makeUnhandledHandler("SAADC"), + TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), + TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), + TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), + RTC0: InterruptVector = makeUnhandledHandler("RTC0"), + TEMP: InterruptVector = makeUnhandledHandler("TEMP"), + RNG: InterruptVector = makeUnhandledHandler("RNG"), + ECB: InterruptVector = makeUnhandledHandler("ECB"), + CCM_AAR: InterruptVector = makeUnhandledHandler("CCM_AAR"), + WDT: InterruptVector = makeUnhandledHandler("WDT"), + RTC1: InterruptVector = makeUnhandledHandler("RTC1"), + QDEC: InterruptVector = makeUnhandledHandler("QDEC"), + COMP_LPCOMP: InterruptVector = makeUnhandledHandler("COMP_LPCOMP"), + SWI0_EGU0: InterruptVector = makeUnhandledHandler("SWI0_EGU0"), + SWI1_EGU1: InterruptVector = makeUnhandledHandler("SWI1_EGU1"), + SWI2_EGU2: InterruptVector = makeUnhandledHandler("SWI2_EGU2"), + SWI3_EGU3: InterruptVector = makeUnhandledHandler("SWI3_EGU3"), + SWI4_EGU4: InterruptVector = makeUnhandledHandler("SWI4_EGU4"), + SWI5_EGU5: InterruptVector = makeUnhandledHandler("SWI5_EGU5"), + TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), + TIMER4: InterruptVector = makeUnhandledHandler("TIMER4"), + PWM0: InterruptVector = makeUnhandledHandler("PWM0"), + PDM: InterruptVector = makeUnhandledHandler("PDM"), + reserved2: u32 = 0, + reserved3: u32 = 0, + MWU: InterruptVector = makeUnhandledHandler("MWU"), + PWM1: InterruptVector = makeUnhandledHandler("PWM1"), + PWM2: InterruptVector = makeUnhandledHandler("PWM2"), + SPIM2_SPIS2_SPI2: InterruptVector = makeUnhandledHandler("SPIM2_SPIS2_SPI2"), + RTC2: InterruptVector = makeUnhandledHandler("RTC2"), + I2S: InterruptVector = makeUnhandledHandler("I2S"), + FPU: InterruptVector = makeUnhandledHandler("FPU"), +}; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +export const vectors: VectorTable linksection("microzig_flash_start") = blk: { + var temp: VectorTable = .{}; + if (@hasDecl(root, "vector_table")) { + const vector_table = root.vector_table; + if (@typeInfo(vector_table) != .Struct) + @compileLog("root.vector_table must be a struct"); + + inline for (@typeInfo(vector_table).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; + const handler = @field(vector_table, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(temp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk temp; +}; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 4cbe4cd..f56973f 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -1,30 +1,22 @@ // generated using svd2zig.py // DO NOT EDIT // based on STM32F103xx version 1.3 -const mmio = @import("microzig-mmio").mmio; +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; const Name = "STM32F103xx"; + +/// Flexible static memory controller pub const FSMC = extern struct { pub const Address: u32 = 0xa0000000; - // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + + /// SRAM/NOR-Flash chip-select control register 1 pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL reserved2: u1 = 0, - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -38,38 +30,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + + /// SRAM/NOR-Flash chip-select timing register 1 pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + + /// SRAM/NOR-Flash chip-select control register 2 pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -83,38 +56,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + + /// SRAM/NOR-Flash chip-select timing register 2 pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + + /// SRAM/NOR-Flash chip-select control register 3 pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -128,38 +82,19 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + + /// SRAM/NOR-Flash chip-select timing register 3 pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + + /// SRAM/NOR-Flash chip-select control register 4 pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -173,31 +108,18 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + + /// SRAM/NOR-Flash chip-select timing register 4 pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 PC Card/NAND Flash control register 2 + + /// PC Card/NAND Flash control register 2 pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -211,15 +133,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 FIFO status and interrupt register 2 + + /// FIFO status and interrupt register 2 pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -246,37 +162,33 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 108 Attribute memory space timing register 2 + + /// Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); + + /// Attribute memory space timing register 2 pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: Attribute memory x setup time - ATTWAITx: u8, // bit offset: 8 desc: Attribute memory x wait time - ATTHOLDx: u8, // bit offset: 16 desc: Attribute memory x hold time - ATTHIZx: u8, // bit offset: 24 desc: Attribute memory x databus HiZ time + /// Attribute memory x setup time + ATTSETx: u8 = 0, + /// Attribute memory x wait time + ATTWAITx: u8 = 0, + /// Attribute memory x hold time + ATTHOLDx: u8 = 0, + /// Attribute memory x databus HiZ time + ATTHIZx: u8 = 0, }); - // byte offset: 116 ECC result register 2 + + /// ECC result register 2 pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECC result + /// ECC result + ECCx: u32 = 0, }); - // byte offset: 128 PC Card/NAND Flash control register 3 + + /// PC Card/NAND Flash control register 3 pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -290,15 +202,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 FIFO status and interrupt register 3 + + /// FIFO status and interrupt register 3 pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -325,37 +231,21 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 140 Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 148 ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 160 PC Card/NAND Flash control register 4 + + /// Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); + + /// PC Card/NAND Flash control register 4 pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -369,15 +259,9 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 FIFO status and interrupt register 4 + + /// FIFO status and interrupt register 4 pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -404,99 +288,77 @@ pub const FSMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 172 Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 176 I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { - IOSETx: u8, // bit offset: 0 desc: IOSETx - IOWAITx: u8, // bit offset: 8 desc: IOWAITx - IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx - IOHIZx: u8, // bit offset: 24 desc: IOHIZx - }); - // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + + /// Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// SRAM/NOR-Flash write timing registers 1 pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + + /// SRAM/NOR-Flash write timing registers 2 pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + + /// SRAM/NOR-Flash write timing registers 3 pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + + /// SRAM/NOR-Flash write timing registers 4 pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Power control pub const PWR = extern struct { pub const Address: u32 = 0x40007000; - // byte offset: 0 Power control register (PWR_CR) + + /// Power control register (PWR_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - LPDS: u1, // bit offset: 0 desc: Low Power Deep Sleep - PDDS: u1, // bit offset: 1 desc: Power Down Deep Sleep - CWUF: u1, // bit offset: 2 desc: Clear Wake-up Flag - CSBF: u1, // bit offset: 3 desc: Clear STANDBY Flag - PVDE: u1, // bit offset: 4 desc: Power Voltage Detector Enable - PLS: u3, // bit offset: 5 desc: PVD Level Selection - DBP: u1, // bit offset: 8 desc: Disable Backup Domain write protection + /// Low Power Deep Sleep + LPDS: u1 = 0, + /// Power Down Deep Sleep + PDDS: u1 = 0, + /// Clear Wake-up Flag + CWUF: u1 = 0, + /// Clear STANDBY Flag + CSBF: u1 = 0, + /// Power Voltage Detector Enable + PVDE: u1 = 0, + /// PVD Level Selection + PLS: u3 = 0, + /// Disable Backup Domain write protection + DBP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -521,17 +383,22 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Power control register (PWR_CR) + + /// Power control register (PWR_CR) pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - WUF: u1, // bit offset: 0 desc: Wake-Up Flag - SBF: u1, // bit offset: 1 desc: STANDBY Flag - PVDO: u1, // bit offset: 2 desc: PVD Output + /// Wake-Up Flag + WUF: u1 = 0, + /// STANDBY Flag + SBF: u1 = 0, + /// PVD Output + PVDO: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EWUP: u1, // bit offset: 8 desc: Enable WKUP pin + /// Enable WKUP pin + EWUP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -557,25 +424,38 @@ pub const PWR = extern struct { padding1: u1 = 0, }); }; + +/// Reset and clock control pub const RCC = extern struct { pub const Address: u32 = 0x40021000; - // byte offset: 0 Clock control register + + /// Clock control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable - HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag + /// Internal High Speed clock enable + HSION: u1 = 0, + /// Internal High Speed clock ready flag + HSIRDY: u1 = 0, reserved1: u1 = 0, - HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming - HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration - HSEON: u1, // bit offset: 16 desc: External High Speed clock enable - HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag - HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass - CSSON: u1, // bit offset: 19 desc: Clock Security System enable + /// Internal High Speed clock trimming + HSITRIM: u5 = 0, + /// Internal High Speed clock Calibration + HSICAL: u8 = 0, + /// External High Speed clock enable + HSEON: u1 = 0, + /// External High Speed clock ready flag + HSERDY: u1 = 0, + /// External High Speed clock Bypass + HSEBYP: u1 = 0, + /// Clock Security System enable + CSSON: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - PLLON: u1, // bit offset: 24 desc: PLL enable - PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + /// PLL enable + PLLON: u1 = 0, + /// PLL clock ready flag + PLLRDY: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -583,52 +463,82 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Clock configuration register (RCC_CFGR) + + /// Clock configuration register (RCC_CFGR) pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - SW: u2, // bit offset: 0 desc: System clock Switch - SWS: u2, // bit offset: 2 desc: System Clock Switch Status - HPRE: u4, // bit offset: 4 desc: AHB prescaler - PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) - PPRE2: u3, // bit offset: 11 desc: APB High speed prescaler (APB2) - ADCPRE: u2, // bit offset: 14 desc: ADC prescaler - PLLSRC: u1, // bit offset: 16 desc: PLL entry clock source - PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry - PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor - OTGFSPRE: u1, // bit offset: 22 desc: USB OTG FS prescaler + /// System clock Switch + SW: u2 = 0, + /// System Clock Switch Status + SWS: u2 = 0, + /// AHB prescaler + HPRE: u4 = 0, + /// APB Low speed prescaler (APB1) + PPRE1: u3 = 0, + /// APB High speed prescaler (APB2) + PPRE2: u3 = 0, + /// ADC prescaler + ADCPRE: u2 = 0, + /// PLL entry clock source + PLLSRC: u1 = 0, + /// HSE divider for PLL entry + PLLXTPRE: u1 = 0, + /// PLL Multiplication Factor + PLLMUL: u4 = 0, + /// USB OTG FS prescaler + OTGFSPRE: u1 = 0, reserved1: u1 = 0, - MCO: u3, // bit offset: 24 desc: Microcontroller clock output + /// Microcontroller clock output + MCO: u3 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Clock interrupt register (RCC_CIR) + + /// Clock interrupt register (RCC_CIR) pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag - LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag - HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag - HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag - PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag + /// LSI Ready Interrupt flag + LSIRDYF: u1 = 0, + /// LSE Ready Interrupt flag + LSERDYF: u1 = 0, + /// HSI Ready Interrupt flag + HSIRDYF: u1 = 0, + /// HSE Ready Interrupt flag + HSERDYF: u1 = 0, + /// PLL Ready Interrupt flag + PLLRDYF: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag - LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable - LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable - HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable - HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable - PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + /// Clock Security System Interrupt flag + CSSF: u1 = 0, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1 = 0, + /// LSE Ready Interrupt Enable + LSERDYIE: u1 = 0, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1 = 0, + /// HSE Ready Interrupt Enable + HSERDYIE: u1 = 0, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear - LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear - HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear - HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear - PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + /// LSI Ready Interrupt Clear + LSIRDYC: u1 = 0, + /// LSE Ready Interrupt Clear + LSERDYC: u1 = 0, + /// HSI Ready Interrupt Clear + HSIRDYC: u1 = 0, + /// HSE Ready Interrupt Clear + HSERDYC: u1 = 0, + /// PLL Ready Interrupt Clear + PLLRDYC: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + /// Clock security system interrupt clear + CSSC: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -638,30 +548,49 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + + /// APB2 peripheral reset register (RCC_APB2RSTR) pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - AFIORST: u1, // bit offset: 0 desc: Alternate function I/O reset + /// Alternate function I/O reset + AFIORST: u1 = 0, reserved1: u1 = 0, - IOPARST: u1, // bit offset: 2 desc: IO port A reset - IOPBRST: u1, // bit offset: 3 desc: IO port B reset - IOPCRST: u1, // bit offset: 4 desc: IO port C reset - IOPDRST: u1, // bit offset: 5 desc: IO port D reset - IOPERST: u1, // bit offset: 6 desc: IO port E reset - IOPFRST: u1, // bit offset: 7 desc: IO port F reset - IOPGRST: u1, // bit offset: 8 desc: IO port G reset - ADC1RST: u1, // bit offset: 9 desc: ADC 1 interface reset - ADC2RST: u1, // bit offset: 10 desc: ADC 2 interface reset - TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset - SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset - TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset - USART1RST: u1, // bit offset: 14 desc: USART1 reset - ADC3RST: u1, // bit offset: 15 desc: ADC 3 interface reset + /// IO port A reset + IOPARST: u1 = 0, + /// IO port B reset + IOPBRST: u1 = 0, + /// IO port C reset + IOPCRST: u1 = 0, + /// IO port D reset + IOPDRST: u1 = 0, + /// IO port E reset + IOPERST: u1 = 0, + /// IO port F reset + IOPFRST: u1 = 0, + /// IO port G reset + IOPGRST: u1 = 0, + /// ADC 1 interface reset + ADC1RST: u1 = 0, + /// ADC 2 interface reset + ADC2RST: u1 = 0, + /// TIM1 timer reset + TIM1RST: u1 = 0, + /// SPI 1 reset + SPI1RST: u1 = 0, + /// TIM8 timer reset + TIM8RST: u1 = 0, + /// USART1 reset + USART1RST: u1 = 0, + /// ADC 3 interface reset + ADC3RST: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TIM9RST: u1, // bit offset: 19 desc: TIM9 timer reset - TIM10RST: u1, // bit offset: 20 desc: TIM10 timer reset - TIM11RST: u1, // bit offset: 21 desc: TIM11 timer reset + /// TIM9 timer reset + TIM9RST: u1 = 0, + /// TIM10 timer reset + TIM10RST: u1 = 0, + /// TIM11 timer reset + TIM11RST: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -673,54 +602,86 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + + /// APB1 peripheral reset register (RCC_APB1RSTR) pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset - TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset - TIM4RST: u1, // bit offset: 2 desc: Timer 4 reset - TIM5RST: u1, // bit offset: 3 desc: Timer 5 reset - TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset - TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset - TIM12RST: u1, // bit offset: 6 desc: Timer 12 reset - TIM13RST: u1, // bit offset: 7 desc: Timer 13 reset - TIM14RST: u1, // bit offset: 8 desc: Timer 14 reset + /// Timer 2 reset + TIM2RST: u1 = 0, + /// Timer 3 reset + TIM3RST: u1 = 0, + /// Timer 4 reset + TIM4RST: u1 = 0, + /// Timer 5 reset + TIM5RST: u1 = 0, + /// Timer 6 reset + TIM6RST: u1 = 0, + /// Timer 7 reset + TIM7RST: u1 = 0, + /// Timer 12 reset + TIM12RST: u1 = 0, + /// Timer 13 reset + TIM13RST: u1 = 0, + /// Timer 14 reset + TIM14RST: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + /// Window watchdog reset + WWDGRST: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - SPI2RST: u1, // bit offset: 14 desc: SPI2 reset - SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + /// SPI2 reset + SPI2RST: u1 = 0, + /// SPI3 reset + SPI3RST: u1 = 0, reserved5: u1 = 0, - USART2RST: u1, // bit offset: 17 desc: USART 2 reset - USART3RST: u1, // bit offset: 18 desc: USART 3 reset - UART4RST: u1, // bit offset: 19 desc: UART 4 reset - UART5RST: u1, // bit offset: 20 desc: UART 5 reset - I2C1RST: u1, // bit offset: 21 desc: I2C1 reset - I2C2RST: u1, // bit offset: 22 desc: I2C2 reset - USBRST: u1, // bit offset: 23 desc: USB reset + /// USART 2 reset + USART2RST: u1 = 0, + /// USART 3 reset + USART3RST: u1 = 0, + /// UART 4 reset + UART4RST: u1 = 0, + /// UART 5 reset + UART5RST: u1 = 0, + /// I2C1 reset + I2C1RST: u1 = 0, + /// I2C2 reset + I2C2RST: u1 = 0, + /// USB reset + USBRST: u1 = 0, reserved6: u1 = 0, - CANRST: u1, // bit offset: 25 desc: CAN reset + /// CAN reset + CANRST: u1 = 0, reserved7: u1 = 0, - BKPRST: u1, // bit offset: 27 desc: Backup interface reset - PWRRST: u1, // bit offset: 28 desc: Power interface reset - DACRST: u1, // bit offset: 29 desc: DAC interface reset + /// Backup interface reset + BKPRST: u1 = 0, + /// Power interface reset + PWRRST: u1 = 0, + /// DAC interface reset + DACRST: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + + /// AHB Peripheral Clock enable register (RCC_AHBENR) pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - DMA1EN: u1, // bit offset: 0 desc: DMA1 clock enable - DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable - SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable + /// DMA1 clock enable + DMA1EN: u1 = 0, + /// DMA2 clock enable + DMA2EN: u1 = 0, + /// SRAM interface clock enable + SRAMEN: u1 = 0, reserved1: u1 = 0, - FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable + /// FLITF clock enable + FLITFEN: u1 = 0, reserved2: u1 = 0, - CRCEN: u1, // bit offset: 6 desc: CRC clock enable + /// CRC clock enable + CRCEN: u1 = 0, reserved3: u1 = 0, - FSMCEN: u1, // bit offset: 8 desc: FSMC clock enable + /// FSMC clock enable + FSMCEN: u1 = 0, reserved4: u1 = 0, - SDIOEN: u1, // bit offset: 10 desc: SDIO clock enable + /// SDIO clock enable + SDIOEN: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -743,30 +704,49 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + + /// APB2 peripheral clock enable register (RCC_APB2ENR) pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - AFIOEN: u1, // bit offset: 0 desc: Alternate function I/O clock enable + /// Alternate function I/O clock enable + AFIOEN: u1 = 0, reserved1: u1 = 0, - IOPAEN: u1, // bit offset: 2 desc: I/O port A clock enable - IOPBEN: u1, // bit offset: 3 desc: I/O port B clock enable - IOPCEN: u1, // bit offset: 4 desc: I/O port C clock enable - IOPDEN: u1, // bit offset: 5 desc: I/O port D clock enable - IOPEEN: u1, // bit offset: 6 desc: I/O port E clock enable - IOPFEN: u1, // bit offset: 7 desc: I/O port F clock enable - IOPGEN: u1, // bit offset: 8 desc: I/O port G clock enable - ADC1EN: u1, // bit offset: 9 desc: ADC 1 interface clock enable - ADC2EN: u1, // bit offset: 10 desc: ADC 2 interface clock enable - TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable - SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable - TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable - USART1EN: u1, // bit offset: 14 desc: USART1 clock enable - ADC3EN: u1, // bit offset: 15 desc: ADC3 interface clock enable + /// I/O port A clock enable + IOPAEN: u1 = 0, + /// I/O port B clock enable + IOPBEN: u1 = 0, + /// I/O port C clock enable + IOPCEN: u1 = 0, + /// I/O port D clock enable + IOPDEN: u1 = 0, + /// I/O port E clock enable + IOPEEN: u1 = 0, + /// I/O port F clock enable + IOPFEN: u1 = 0, + /// I/O port G clock enable + IOPGEN: u1 = 0, + /// ADC 1 interface clock enable + ADC1EN: u1 = 0, + /// ADC 2 interface clock enable + ADC2EN: u1 = 0, + /// TIM1 Timer clock enable + TIM1EN: u1 = 0, + /// SPI 1 clock enable + SPI1EN: u1 = 0, + /// TIM8 Timer clock enable + TIM8EN: u1 = 0, + /// USART1 clock enable + USART1EN: u1 = 0, + /// ADC3 interface clock enable + ADC3EN: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TIM9EN: u1, // bit offset: 19 desc: TIM9 Timer clock enable - TIM10EN: u1, // bit offset: 20 desc: TIM10 Timer clock enable - TIM11EN: u1, // bit offset: 21 desc: TIM11 Timer clock enable + /// TIM9 Timer clock enable + TIM9EN: u1 = 0, + /// TIM10 Timer clock enable + TIM10EN: u1 = 0, + /// TIM11 Timer clock enable + TIM11EN: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -778,59 +758,90 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + + /// APB1 peripheral clock enable register (RCC_APB1ENR) pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable - TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable - TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable - TIM5EN: u1, // bit offset: 3 desc: Timer 5 clock enable - TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable - TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable - TIM12EN: u1, // bit offset: 6 desc: Timer 12 clock enable - TIM13EN: u1, // bit offset: 7 desc: Timer 13 clock enable - TIM14EN: u1, // bit offset: 8 desc: Timer 14 clock enable + /// Timer 2 clock enable + TIM2EN: u1 = 0, + /// Timer 3 clock enable + TIM3EN: u1 = 0, + /// Timer 4 clock enable + TIM4EN: u1 = 0, + /// Timer 5 clock enable + TIM5EN: u1 = 0, + /// Timer 6 clock enable + TIM6EN: u1 = 0, + /// Timer 7 clock enable + TIM7EN: u1 = 0, + /// Timer 12 clock enable + TIM12EN: u1 = 0, + /// Timer 13 clock enable + TIM13EN: u1 = 0, + /// Timer 14 clock enable + TIM14EN: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + /// Window watchdog clock enable + WWDGEN: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable - SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + /// SPI 2 clock enable + SPI2EN: u1 = 0, + /// SPI 3 clock enable + SPI3EN: u1 = 0, reserved5: u1 = 0, - USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable - USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable - UART4EN: u1, // bit offset: 19 desc: UART 4 clock enable - UART5EN: u1, // bit offset: 20 desc: UART 5 clock enable - I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable - I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable - USBEN: u1, // bit offset: 23 desc: USB clock enable + /// USART 2 clock enable + USART2EN: u1 = 0, + /// USART 3 clock enable + USART3EN: u1 = 0, + /// UART 4 clock enable + UART4EN: u1 = 0, + /// UART 5 clock enable + UART5EN: u1 = 0, + /// I2C 1 clock enable + I2C1EN: u1 = 0, + /// I2C 2 clock enable + I2C2EN: u1 = 0, + /// USB clock enable + USBEN: u1 = 0, reserved6: u1 = 0, - CANEN: u1, // bit offset: 25 desc: CAN clock enable + /// CAN clock enable + CANEN: u1 = 0, reserved7: u1 = 0, - BKPEN: u1, // bit offset: 27 desc: Backup interface clock enable - PWREN: u1, // bit offset: 28 desc: Power interface clock enable - DACEN: u1, // bit offset: 29 desc: DAC interface clock enable + /// Backup interface clock enable + BKPEN: u1 = 0, + /// Power interface clock enable + PWREN: u1 = 0, + /// DAC interface clock enable + DACEN: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup domain control register (RCC_BDCR) + + /// Backup domain control register (RCC_BDCR) pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable - LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready - LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass + /// External Low Speed oscillator enable + LSEON: u1 = 0, + /// External Low Speed oscillator ready + LSERDY: u1 = 0, + /// External Low Speed oscillator bypass + LSEBYP: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + /// RTC clock source selection + RTCSEL: u2 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - RTCEN: u1, // bit offset: 15 desc: RTC clock enable - BDRST: u1, // bit offset: 16 desc: Backup domain software reset + /// RTC clock enable + RTCEN: u1 = 0, + /// Backup domain software reset + BDRST: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -847,10 +858,13 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Control/status register (RCC_CSR) + + /// Control/status register (RCC_CSR) pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable - LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + /// Internal low speed oscillator enable + LSION: u1 = 0, + /// Internal low speed oscillator ready + LSIRDY: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -873,74 +887,134 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RMVF: u1, // bit offset: 24 desc: Remove reset flag + /// Remove reset flag + RMVF: u1 = 0, reserved23: u1 = 0, - PINRSTF: u1, // bit offset: 26 desc: PIN reset flag - PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag - SFTRSTF: u1, // bit offset: 28 desc: Software reset flag - IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag - WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag - LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + /// PIN reset flag + PINRSTF: u1 = 0, + /// POR/PDR reset flag + PORRSTF: u1 = 0, + /// Software reset flag + SFTRSTF: u1 = 0, + /// Independent watchdog reset flag + IWDGRSTF: u1 = 0, + /// Window watchdog reset flag + WWDGRSTF: u1 = 0, + /// Low-power reset flag + LPWRRSTF: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOA = extern struct { pub const Address: u32 = 0x40010800; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -958,24 +1032,41 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -993,59 +1084,109 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1063,25 +1204,43 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1099,64 +1258,117 @@ pub const GPIOA = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOB = extern struct { pub const Address: u32 = 0x40010c00; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1174,24 +1386,41 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1209,59 +1438,109 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1279,25 +1558,43 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1315,64 +1612,117 @@ pub const GPIOB = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOC = extern struct { pub const Address: u32 = 0x40011000; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1390,24 +1740,41 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1425,59 +1792,109 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1495,25 +1912,43 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1531,64 +1966,117 @@ pub const GPIOC = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOD = extern struct { pub const Address: u32 = 0x40011400; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1606,24 +2094,41 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1641,59 +2146,109 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1711,25 +2266,43 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1747,64 +2320,117 @@ pub const GPIOD = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOE = extern struct { pub const Address: u32 = 0x40011800; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1822,24 +2448,41 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1857,59 +2500,109 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1927,25 +2620,43 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1963,64 +2674,117 @@ pub const GPIOE = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOF = extern struct { pub const Address: u32 = 0x40011c00; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2038,24 +2802,41 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2073,59 +2854,109 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2143,25 +2974,43 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2179,64 +3028,117 @@ pub const GPIOF = extern struct { padding1: u1 = 0, }); }; + +/// General purpose I/O pub const GPIOG = extern struct { pub const Address: u32 = 0x40012000; - // byte offset: 0 Port configuration register low (GPIOn_CRL) + + /// Port configuration register low (GPIOn_CRL) pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - MODE0: u2, // bit offset: 0 desc: Port n.0 mode bits - CNF0: u2, // bit offset: 2 desc: Port n.0 configuration bits - MODE1: u2, // bit offset: 4 desc: Port n.1 mode bits - CNF1: u2, // bit offset: 6 desc: Port n.1 configuration bits - MODE2: u2, // bit offset: 8 desc: Port n.2 mode bits - CNF2: u2, // bit offset: 10 desc: Port n.2 configuration bits - MODE3: u2, // bit offset: 12 desc: Port n.3 mode bits - CNF3: u2, // bit offset: 14 desc: Port n.3 configuration bits - MODE4: u2, // bit offset: 16 desc: Port n.4 mode bits - CNF4: u2, // bit offset: 18 desc: Port n.4 configuration bits - MODE5: u2, // bit offset: 20 desc: Port n.5 mode bits - CNF5: u2, // bit offset: 22 desc: Port n.5 configuration bits - MODE6: u2, // bit offset: 24 desc: Port n.6 mode bits - CNF6: u2, // bit offset: 26 desc: Port n.6 configuration bits - MODE7: u2, // bit offset: 28 desc: Port n.7 mode bits - CNF7: u2, // bit offset: 30 desc: Port n.7 configuration bits - }); - // byte offset: 4 Port configuration register high (GPIOn_CRL) + /// Port n.0 mode bits + MODE0: u2 = 0, + /// Port n.0 configuration bits + CNF0: u2 = 0, + /// Port n.1 mode bits + MODE1: u2 = 0, + /// Port n.1 configuration bits + CNF1: u2 = 0, + /// Port n.2 mode bits + MODE2: u2 = 0, + /// Port n.2 configuration bits + CNF2: u2 = 0, + /// Port n.3 mode bits + MODE3: u2 = 0, + /// Port n.3 configuration bits + CNF3: u2 = 0, + /// Port n.4 mode bits + MODE4: u2 = 0, + /// Port n.4 configuration bits + CNF4: u2 = 0, + /// Port n.5 mode bits + MODE5: u2 = 0, + /// Port n.5 configuration bits + CNF5: u2 = 0, + /// Port n.6 mode bits + MODE6: u2 = 0, + /// Port n.6 configuration bits + CNF6: u2 = 0, + /// Port n.7 mode bits + MODE7: u2 = 0, + /// Port n.7 configuration bits + CNF7: u2 = 0, + }); + + /// Port configuration register high (GPIOn_CRL) pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - MODE8: u2, // bit offset: 0 desc: Port n.8 mode bits - CNF8: u2, // bit offset: 2 desc: Port n.8 configuration bits - MODE9: u2, // bit offset: 4 desc: Port n.9 mode bits - CNF9: u2, // bit offset: 6 desc: Port n.9 configuration bits - MODE10: u2, // bit offset: 8 desc: Port n.10 mode bits - CNF10: u2, // bit offset: 10 desc: Port n.10 configuration bits - MODE11: u2, // bit offset: 12 desc: Port n.11 mode bits - CNF11: u2, // bit offset: 14 desc: Port n.11 configuration bits - MODE12: u2, // bit offset: 16 desc: Port n.12 mode bits - CNF12: u2, // bit offset: 18 desc: Port n.12 configuration bits - MODE13: u2, // bit offset: 20 desc: Port n.13 mode bits - CNF13: u2, // bit offset: 22 desc: Port n.13 configuration bits - MODE14: u2, // bit offset: 24 desc: Port n.14 mode bits - CNF14: u2, // bit offset: 26 desc: Port n.14 configuration bits - MODE15: u2, // bit offset: 28 desc: Port n.15 mode bits - CNF15: u2, // bit offset: 30 desc: Port n.15 configuration bits - }); - // byte offset: 8 Port input data register (GPIOn_IDR) + /// Port n.8 mode bits + MODE8: u2 = 0, + /// Port n.8 configuration bits + CNF8: u2 = 0, + /// Port n.9 mode bits + MODE9: u2 = 0, + /// Port n.9 configuration bits + CNF9: u2 = 0, + /// Port n.10 mode bits + MODE10: u2 = 0, + /// Port n.10 configuration bits + CNF10: u2 = 0, + /// Port n.11 mode bits + MODE11: u2 = 0, + /// Port n.11 configuration bits + CNF11: u2 = 0, + /// Port n.12 mode bits + MODE12: u2 = 0, + /// Port n.12 configuration bits + CNF12: u2 = 0, + /// Port n.13 mode bits + MODE13: u2 = 0, + /// Port n.13 configuration bits + CNF13: u2 = 0, + /// Port n.14 mode bits + MODE14: u2 = 0, + /// Port n.14 configuration bits + CNF14: u2 = 0, + /// Port n.15 mode bits + MODE15: u2 = 0, + /// Port n.15 configuration bits + CNF15: u2 = 0, + }); + + /// Port input data register (GPIOn_IDR) pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data - IDR1: u1, // bit offset: 1 desc: Port input data - IDR2: u1, // bit offset: 2 desc: Port input data - IDR3: u1, // bit offset: 3 desc: Port input data - IDR4: u1, // bit offset: 4 desc: Port input data - IDR5: u1, // bit offset: 5 desc: Port input data - IDR6: u1, // bit offset: 6 desc: Port input data - IDR7: u1, // bit offset: 7 desc: Port input data - IDR8: u1, // bit offset: 8 desc: Port input data - IDR9: u1, // bit offset: 9 desc: Port input data - IDR10: u1, // bit offset: 10 desc: Port input data - IDR11: u1, // bit offset: 11 desc: Port input data - IDR12: u1, // bit offset: 12 desc: Port input data - IDR13: u1, // bit offset: 13 desc: Port input data - IDR14: u1, // bit offset: 14 desc: Port input data - IDR15: u1, // bit offset: 15 desc: Port input data + /// Port input data + IDR0: u1 = 0, + /// Port input data + IDR1: u1 = 0, + /// Port input data + IDR2: u1 = 0, + /// Port input data + IDR3: u1 = 0, + /// Port input data + IDR4: u1 = 0, + /// Port input data + IDR5: u1 = 0, + /// Port input data + IDR6: u1 = 0, + /// Port input data + IDR7: u1 = 0, + /// Port input data + IDR8: u1 = 0, + /// Port input data + IDR9: u1 = 0, + /// Port input data + IDR10: u1 = 0, + /// Port input data + IDR11: u1 = 0, + /// Port input data + IDR12: u1 = 0, + /// Port input data + IDR13: u1 = 0, + /// Port input data + IDR14: u1 = 0, + /// Port input data + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2254,24 +3156,41 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Port output data register (GPIOn_ODR) + + /// Port output data register (GPIOn_ODR) pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data - ODR1: u1, // bit offset: 1 desc: Port output data - ODR2: u1, // bit offset: 2 desc: Port output data - ODR3: u1, // bit offset: 3 desc: Port output data - ODR4: u1, // bit offset: 4 desc: Port output data - ODR5: u1, // bit offset: 5 desc: Port output data - ODR6: u1, // bit offset: 6 desc: Port output data - ODR7: u1, // bit offset: 7 desc: Port output data - ODR8: u1, // bit offset: 8 desc: Port output data - ODR9: u1, // bit offset: 9 desc: Port output data - ODR10: u1, // bit offset: 10 desc: Port output data - ODR11: u1, // bit offset: 11 desc: Port output data - ODR12: u1, // bit offset: 12 desc: Port output data - ODR13: u1, // bit offset: 13 desc: Port output data - ODR14: u1, // bit offset: 14 desc: Port output data - ODR15: u1, // bit offset: 15 desc: Port output data + /// Port output data + ODR0: u1 = 0, + /// Port output data + ODR1: u1 = 0, + /// Port output data + ODR2: u1 = 0, + /// Port output data + ODR3: u1 = 0, + /// Port output data + ODR4: u1 = 0, + /// Port output data + ODR5: u1 = 0, + /// Port output data + ODR6: u1 = 0, + /// Port output data + ODR7: u1 = 0, + /// Port output data + ODR8: u1 = 0, + /// Port output data + ODR9: u1 = 0, + /// Port output data + ODR10: u1 = 0, + /// Port output data + ODR11: u1 = 0, + /// Port output data + ODR12: u1 = 0, + /// Port output data + ODR13: u1 = 0, + /// Port output data + ODR14: u1 = 0, + /// Port output data + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2289,59 +3208,109 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Port bit set/reset register (GPIOn_BSRR) + + /// Port bit set/reset register (GPIOn_BSRR) pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Set bit 0 - BS1: u1, // bit offset: 1 desc: Set bit 1 - BS2: u1, // bit offset: 2 desc: Set bit 1 - BS3: u1, // bit offset: 3 desc: Set bit 3 - BS4: u1, // bit offset: 4 desc: Set bit 4 - BS5: u1, // bit offset: 5 desc: Set bit 5 - BS6: u1, // bit offset: 6 desc: Set bit 6 - BS7: u1, // bit offset: 7 desc: Set bit 7 - BS8: u1, // bit offset: 8 desc: Set bit 8 - BS9: u1, // bit offset: 9 desc: Set bit 9 - BS10: u1, // bit offset: 10 desc: Set bit 10 - BS11: u1, // bit offset: 11 desc: Set bit 11 - BS12: u1, // bit offset: 12 desc: Set bit 12 - BS13: u1, // bit offset: 13 desc: Set bit 13 - BS14: u1, // bit offset: 14 desc: Set bit 14 - BS15: u1, // bit offset: 15 desc: Set bit 15 - BR0: u1, // bit offset: 16 desc: Reset bit 0 - BR1: u1, // bit offset: 17 desc: Reset bit 1 - BR2: u1, // bit offset: 18 desc: Reset bit 2 - BR3: u1, // bit offset: 19 desc: Reset bit 3 - BR4: u1, // bit offset: 20 desc: Reset bit 4 - BR5: u1, // bit offset: 21 desc: Reset bit 5 - BR6: u1, // bit offset: 22 desc: Reset bit 6 - BR7: u1, // bit offset: 23 desc: Reset bit 7 - BR8: u1, // bit offset: 24 desc: Reset bit 8 - BR9: u1, // bit offset: 25 desc: Reset bit 9 - BR10: u1, // bit offset: 26 desc: Reset bit 10 - BR11: u1, // bit offset: 27 desc: Reset bit 11 - BR12: u1, // bit offset: 28 desc: Reset bit 12 - BR13: u1, // bit offset: 29 desc: Reset bit 13 - BR14: u1, // bit offset: 30 desc: Reset bit 14 - BR15: u1, // bit offset: 31 desc: Reset bit 15 - }); - // byte offset: 20 Port bit reset register (GPIOn_BRR) + /// Set bit 0 + BS0: u1 = 0, + /// Set bit 1 + BS1: u1 = 0, + /// Set bit 1 + BS2: u1 = 0, + /// Set bit 3 + BS3: u1 = 0, + /// Set bit 4 + BS4: u1 = 0, + /// Set bit 5 + BS5: u1 = 0, + /// Set bit 6 + BS6: u1 = 0, + /// Set bit 7 + BS7: u1 = 0, + /// Set bit 8 + BS8: u1 = 0, + /// Set bit 9 + BS9: u1 = 0, + /// Set bit 10 + BS10: u1 = 0, + /// Set bit 11 + BS11: u1 = 0, + /// Set bit 12 + BS12: u1 = 0, + /// Set bit 13 + BS13: u1 = 0, + /// Set bit 14 + BS14: u1 = 0, + /// Set bit 15 + BS15: u1 = 0, + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 2 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, + }); + + /// Port bit reset register (GPIOn_BRR) pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Reset bit 0 - BR1: u1, // bit offset: 1 desc: Reset bit 1 - BR2: u1, // bit offset: 2 desc: Reset bit 1 - BR3: u1, // bit offset: 3 desc: Reset bit 3 - BR4: u1, // bit offset: 4 desc: Reset bit 4 - BR5: u1, // bit offset: 5 desc: Reset bit 5 - BR6: u1, // bit offset: 6 desc: Reset bit 6 - BR7: u1, // bit offset: 7 desc: Reset bit 7 - BR8: u1, // bit offset: 8 desc: Reset bit 8 - BR9: u1, // bit offset: 9 desc: Reset bit 9 - BR10: u1, // bit offset: 10 desc: Reset bit 10 - BR11: u1, // bit offset: 11 desc: Reset bit 11 - BR12: u1, // bit offset: 12 desc: Reset bit 12 - BR13: u1, // bit offset: 13 desc: Reset bit 13 - BR14: u1, // bit offset: 14 desc: Reset bit 14 - BR15: u1, // bit offset: 15 desc: Reset bit 15 + /// Reset bit 0 + BR0: u1 = 0, + /// Reset bit 1 + BR1: u1 = 0, + /// Reset bit 1 + BR2: u1 = 0, + /// Reset bit 3 + BR3: u1 = 0, + /// Reset bit 4 + BR4: u1 = 0, + /// Reset bit 5 + BR5: u1 = 0, + /// Reset bit 6 + BR6: u1 = 0, + /// Reset bit 7 + BR7: u1 = 0, + /// Reset bit 8 + BR8: u1 = 0, + /// Reset bit 9 + BR9: u1 = 0, + /// Reset bit 10 + BR10: u1 = 0, + /// Reset bit 11 + BR11: u1 = 0, + /// Reset bit 12 + BR12: u1 = 0, + /// Reset bit 13 + BR13: u1 = 0, + /// Reset bit 14 + BR14: u1 = 0, + /// Reset bit 15 + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2359,25 +3328,43 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Port configuration lock register + + /// Port configuration lock register pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port A Lock bit 0 - LCK1: u1, // bit offset: 1 desc: Port A Lock bit 1 - LCK2: u1, // bit offset: 2 desc: Port A Lock bit 2 - LCK3: u1, // bit offset: 3 desc: Port A Lock bit 3 - LCK4: u1, // bit offset: 4 desc: Port A Lock bit 4 - LCK5: u1, // bit offset: 5 desc: Port A Lock bit 5 - LCK6: u1, // bit offset: 6 desc: Port A Lock bit 6 - LCK7: u1, // bit offset: 7 desc: Port A Lock bit 7 - LCK8: u1, // bit offset: 8 desc: Port A Lock bit 8 - LCK9: u1, // bit offset: 9 desc: Port A Lock bit 9 - LCK10: u1, // bit offset: 10 desc: Port A Lock bit 10 - LCK11: u1, // bit offset: 11 desc: Port A Lock bit 11 - LCK12: u1, // bit offset: 12 desc: Port A Lock bit 12 - LCK13: u1, // bit offset: 13 desc: Port A Lock bit 13 - LCK14: u1, // bit offset: 14 desc: Port A Lock bit 14 - LCK15: u1, // bit offset: 15 desc: Port A Lock bit 15 - LCKK: u1, // bit offset: 16 desc: Lock key + /// Port A Lock bit 0 + LCK0: u1 = 0, + /// Port A Lock bit 1 + LCK1: u1 = 0, + /// Port A Lock bit 2 + LCK2: u1 = 0, + /// Port A Lock bit 3 + LCK3: u1 = 0, + /// Port A Lock bit 4 + LCK4: u1 = 0, + /// Port A Lock bit 5 + LCK5: u1 = 0, + /// Port A Lock bit 6 + LCK6: u1 = 0, + /// Port A Lock bit 7 + LCK7: u1 = 0, + /// Port A Lock bit 8 + LCK8: u1 = 0, + /// Port A Lock bit 9 + LCK9: u1 = 0, + /// Port A Lock bit 10 + LCK10: u1 = 0, + /// Port A Lock bit 11 + LCK11: u1 = 0, + /// Port A Lock bit 12 + LCK12: u1 = 0, + /// Port A Lock bit 13 + LCK13: u1 = 0, + /// Port A Lock bit 14 + LCK14: u1 = 0, + /// Port A Lock bit 15 + LCK15: u1 = 0, + /// Lock key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2395,13 +3382,19 @@ pub const GPIOG = extern struct { padding1: u1 = 0, }); }; + +/// Alternate function I/O pub const AFIO = extern struct { pub const Address: u32 = 0x40010000; - // byte offset: 0 Event Control Register (AFIO_EVCR) + + /// Event Control Register (AFIO_EVCR) pub const EVCR = mmio(Address + 0x00000000, 32, packed struct { - PIN: u4, // bit offset: 0 desc: Pin selection - PORT: u3, // bit offset: 4 desc: Port selection - EVOE: u1, // bit offset: 7 desc: Event Output Enable + /// Pin selection + PIN: u4 = 0, + /// Port selection + PORT: u3 = 0, + /// Event Output Enable + EVOE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2427,40 +3420,63 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 AF remap and debug I/O configuration register (AFIO_MAPR) + + /// AF remap and debug I/O configuration register (AFIO_MAPR) pub const MAPR = mmio(Address + 0x00000004, 32, packed struct { - SPI1_REMAP: u1, // bit offset: 0 desc: SPI1 remapping - I2C1_REMAP: u1, // bit offset: 1 desc: I2C1 remapping - USART1_REMAP: u1, // bit offset: 2 desc: USART1 remapping - USART2_REMAP: u1, // bit offset: 3 desc: USART2 remapping - USART3_REMAP: u2, // bit offset: 4 desc: USART3 remapping - TIM1_REMAP: u2, // bit offset: 6 desc: TIM1 remapping - TIM2_REMAP: u2, // bit offset: 8 desc: TIM2 remapping - TIM3_REMAP: u2, // bit offset: 10 desc: TIM3 remapping - TIM4_REMAP: u1, // bit offset: 12 desc: TIM4 remapping - CAN_REMAP: u2, // bit offset: 13 desc: CAN1 remapping - PD01_REMAP: u1, // bit offset: 15 desc: Port D0/Port D1 mapping on OSCIN/OSCOUT - TIM5CH4_IREMAP: u1, // bit offset: 16 desc: Set and cleared by software - ADC1_ETRGINJ_REMAP: u1, // bit offset: 17 desc: ADC 1 External trigger injected conversion remapping - ADC1_ETRGREG_REMAP: u1, // bit offset: 18 desc: ADC 1 external trigger regular conversion remapping - ADC2_ETRGINJ_REMAP: u1, // bit offset: 19 desc: ADC 2 external trigger injected conversion remapping - ADC2_ETRGREG_REMAP: u1, // bit offset: 20 desc: ADC 2 external trigger regular conversion remapping + /// SPI1 remapping + SPI1_REMAP: u1 = 0, + /// I2C1 remapping + I2C1_REMAP: u1 = 0, + /// USART1 remapping + USART1_REMAP: u1 = 0, + /// USART2 remapping + USART2_REMAP: u1 = 0, + /// USART3 remapping + USART3_REMAP: u2 = 0, + /// TIM1 remapping + TIM1_REMAP: u2 = 0, + /// TIM2 remapping + TIM2_REMAP: u2 = 0, + /// TIM3 remapping + TIM3_REMAP: u2 = 0, + /// TIM4 remapping + TIM4_REMAP: u1 = 0, + /// CAN1 remapping + CAN_REMAP: u2 = 0, + /// Port D0/Port D1 mapping on OSCIN/OSCOUT + PD01_REMAP: u1 = 0, + /// Set and cleared by software + TIM5CH4_IREMAP: u1 = 0, + /// ADC 1 External trigger injected conversion remapping + ADC1_ETRGINJ_REMAP: u1 = 0, + /// ADC 1 external trigger regular conversion remapping + ADC1_ETRGREG_REMAP: u1 = 0, + /// ADC 2 external trigger injected conversion remapping + ADC2_ETRGINJ_REMAP: u1 = 0, + /// ADC 2 external trigger regular conversion remapping + ADC2_ETRGREG_REMAP: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SWJ_CFG: u3, // bit offset: 24 desc: Serial wire JTAG configuration + /// Serial wire JTAG configuration + SWJ_CFG: u3 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 External interrupt configuration register 1 (AFIO_EXTICR1) + + /// External interrupt configuration register 1 (AFIO_EXTICR1) pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - EXTI0: u4, // bit offset: 0 desc: EXTI0 configuration - EXTI1: u4, // bit offset: 4 desc: EXTI1 configuration - EXTI2: u4, // bit offset: 8 desc: EXTI2 configuration - EXTI3: u4, // bit offset: 12 desc: EXTI3 configuration + /// EXTI0 configuration + EXTI0: u4 = 0, + /// EXTI1 configuration + EXTI1: u4 = 0, + /// EXTI2 configuration + EXTI2: u4 = 0, + /// EXTI3 configuration + EXTI3: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2478,12 +3494,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 External interrupt configuration register 2 (AFIO_EXTICR2) + + /// External interrupt configuration register 2 (AFIO_EXTICR2) pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - EXTI4: u4, // bit offset: 0 desc: EXTI4 configuration - EXTI5: u4, // bit offset: 4 desc: EXTI5 configuration - EXTI6: u4, // bit offset: 8 desc: EXTI6 configuration - EXTI7: u4, // bit offset: 12 desc: EXTI7 configuration + /// EXTI4 configuration + EXTI4: u4 = 0, + /// EXTI5 configuration + EXTI5: u4 = 0, + /// EXTI6 configuration + EXTI6: u4 = 0, + /// EXTI7 configuration + EXTI7: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2501,12 +3522,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 External interrupt configuration register 3 (AFIO_EXTICR3) + + /// External interrupt configuration register 3 (AFIO_EXTICR3) pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - EXTI8: u4, // bit offset: 0 desc: EXTI8 configuration - EXTI9: u4, // bit offset: 4 desc: EXTI9 configuration - EXTI10: u4, // bit offset: 8 desc: EXTI10 configuration - EXTI11: u4, // bit offset: 12 desc: EXTI11 configuration + /// EXTI8 configuration + EXTI8: u4 = 0, + /// EXTI9 configuration + EXTI9: u4 = 0, + /// EXTI10 configuration + EXTI10: u4 = 0, + /// EXTI11 configuration + EXTI11: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2524,12 +3550,17 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 External interrupt configuration register 4 (AFIO_EXTICR4) + + /// External interrupt configuration register 4 (AFIO_EXTICR4) pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - EXTI12: u4, // bit offset: 0 desc: EXTI12 configuration - EXTI13: u4, // bit offset: 4 desc: EXTI13 configuration - EXTI14: u4, // bit offset: 8 desc: EXTI14 configuration - EXTI15: u4, // bit offset: 12 desc: EXTI15 configuration + /// EXTI12 configuration + EXTI12: u4 = 0, + /// EXTI13 configuration + EXTI13: u4 = 0, + /// EXTI14 configuration + EXTI14: u4 = 0, + /// EXTI15 configuration + EXTI15: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2547,19 +3578,26 @@ pub const AFIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 AF remap and debug I/O configuration register + + /// AF remap and debug I/O configuration register pub const MAPR2 = mmio(Address + 0x0000001c, 32, packed struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM9_REMAP: u1, // bit offset: 5 desc: TIM9 remapping - TIM10_REMAP: u1, // bit offset: 6 desc: TIM10 remapping - TIM11_REMAP: u1, // bit offset: 7 desc: TIM11 remapping - TIM13_REMAP: u1, // bit offset: 8 desc: TIM13 remapping - TIM14_REMAP: u1, // bit offset: 9 desc: TIM14 remapping - FSMC_NADV: u1, // bit offset: 10 desc: NADV connect/disconnect + /// TIM9 remapping + TIM9_REMAP: u1 = 0, + /// TIM10 remapping + TIM10_REMAP: u1 = 0, + /// TIM11 remapping + TIM11_REMAP: u1 = 0, + /// TIM13 remapping + TIM13_REMAP: u1 = 0, + /// TIM14 remapping + TIM14_REMAP: u1 = 0, + /// NADV connect/disconnect + FSMC_NADV: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -2583,29 +3621,51 @@ pub const AFIO = extern struct { padding1: u1 = 0, }); }; + +/// EXTI pub const EXTI = extern struct { pub const Address: u32 = 0x40010400; - // byte offset: 0 Interrupt mask register (EXTI_IMR) + + /// Interrupt mask register (EXTI_IMR) pub const IMR = mmio(Address + 0x00000000, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 - MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 - MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 - MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 - MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 - MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 - MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 - MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 - MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 - MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 - MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 - MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 - MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 - MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 - MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 - MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 - MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 - MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 - MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 + /// Interrupt Mask on line 0 + MR0: u1 = 0, + /// Interrupt Mask on line 1 + MR1: u1 = 0, + /// Interrupt Mask on line 2 + MR2: u1 = 0, + /// Interrupt Mask on line 3 + MR3: u1 = 0, + /// Interrupt Mask on line 4 + MR4: u1 = 0, + /// Interrupt Mask on line 5 + MR5: u1 = 0, + /// Interrupt Mask on line 6 + MR6: u1 = 0, + /// Interrupt Mask on line 7 + MR7: u1 = 0, + /// Interrupt Mask on line 8 + MR8: u1 = 0, + /// Interrupt Mask on line 9 + MR9: u1 = 0, + /// Interrupt Mask on line 10 + MR10: u1 = 0, + /// Interrupt Mask on line 11 + MR11: u1 = 0, + /// Interrupt Mask on line 12 + MR12: u1 = 0, + /// Interrupt Mask on line 13 + MR13: u1 = 0, + /// Interrupt Mask on line 14 + MR14: u1 = 0, + /// Interrupt Mask on line 15 + MR15: u1 = 0, + /// Interrupt Mask on line 16 + MR16: u1 = 0, + /// Interrupt Mask on line 17 + MR17: u1 = 0, + /// Interrupt Mask on line 18 + MR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2620,27 +3680,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Event mask register (EXTI_EMR) + + /// Event mask register (EXTI_EMR) pub const EMR = mmio(Address + 0x00000004, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Event Mask on line 0 - MR1: u1, // bit offset: 1 desc: Event Mask on line 1 - MR2: u1, // bit offset: 2 desc: Event Mask on line 2 - MR3: u1, // bit offset: 3 desc: Event Mask on line 3 - MR4: u1, // bit offset: 4 desc: Event Mask on line 4 - MR5: u1, // bit offset: 5 desc: Event Mask on line 5 - MR6: u1, // bit offset: 6 desc: Event Mask on line 6 - MR7: u1, // bit offset: 7 desc: Event Mask on line 7 - MR8: u1, // bit offset: 8 desc: Event Mask on line 8 - MR9: u1, // bit offset: 9 desc: Event Mask on line 9 - MR10: u1, // bit offset: 10 desc: Event Mask on line 10 - MR11: u1, // bit offset: 11 desc: Event Mask on line 11 - MR12: u1, // bit offset: 12 desc: Event Mask on line 12 - MR13: u1, // bit offset: 13 desc: Event Mask on line 13 - MR14: u1, // bit offset: 14 desc: Event Mask on line 14 - MR15: u1, // bit offset: 15 desc: Event Mask on line 15 - MR16: u1, // bit offset: 16 desc: Event Mask on line 16 - MR17: u1, // bit offset: 17 desc: Event Mask on line 17 - MR18: u1, // bit offset: 18 desc: Event Mask on line 18 + /// Event Mask on line 0 + MR0: u1 = 0, + /// Event Mask on line 1 + MR1: u1 = 0, + /// Event Mask on line 2 + MR2: u1 = 0, + /// Event Mask on line 3 + MR3: u1 = 0, + /// Event Mask on line 4 + MR4: u1 = 0, + /// Event Mask on line 5 + MR5: u1 = 0, + /// Event Mask on line 6 + MR6: u1 = 0, + /// Event Mask on line 7 + MR7: u1 = 0, + /// Event Mask on line 8 + MR8: u1 = 0, + /// Event Mask on line 9 + MR9: u1 = 0, + /// Event Mask on line 10 + MR10: u1 = 0, + /// Event Mask on line 11 + MR11: u1 = 0, + /// Event Mask on line 12 + MR12: u1 = 0, + /// Event Mask on line 13 + MR13: u1 = 0, + /// Event Mask on line 14 + MR14: u1 = 0, + /// Event Mask on line 15 + MR15: u1 = 0, + /// Event Mask on line 16 + MR16: u1 = 0, + /// Event Mask on line 17 + MR17: u1 = 0, + /// Event Mask on line 18 + MR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2655,27 +3735,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Rising Trigger selection register (EXTI_RTSR) + + /// Rising Trigger selection register (EXTI_RTSR) pub const RTSR = mmio(Address + 0x00000008, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 + /// Rising trigger event configuration of line 0 + TR0: u1 = 0, + /// Rising trigger event configuration of line 1 + TR1: u1 = 0, + /// Rising trigger event configuration of line 2 + TR2: u1 = 0, + /// Rising trigger event configuration of line 3 + TR3: u1 = 0, + /// Rising trigger event configuration of line 4 + TR4: u1 = 0, + /// Rising trigger event configuration of line 5 + TR5: u1 = 0, + /// Rising trigger event configuration of line 6 + TR6: u1 = 0, + /// Rising trigger event configuration of line 7 + TR7: u1 = 0, + /// Rising trigger event configuration of line 8 + TR8: u1 = 0, + /// Rising trigger event configuration of line 9 + TR9: u1 = 0, + /// Rising trigger event configuration of line 10 + TR10: u1 = 0, + /// Rising trigger event configuration of line 11 + TR11: u1 = 0, + /// Rising trigger event configuration of line 12 + TR12: u1 = 0, + /// Rising trigger event configuration of line 13 + TR13: u1 = 0, + /// Rising trigger event configuration of line 14 + TR14: u1 = 0, + /// Rising trigger event configuration of line 15 + TR15: u1 = 0, + /// Rising trigger event configuration of line 16 + TR16: u1 = 0, + /// Rising trigger event configuration of line 17 + TR17: u1 = 0, + /// Rising trigger event configuration of line 18 + TR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2690,27 +3790,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Falling Trigger selection register (EXTI_FTSR) + + /// Falling Trigger selection register (EXTI_FTSR) pub const FTSR = mmio(Address + 0x0000000c, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 + /// Falling trigger event configuration of line 0 + TR0: u1 = 0, + /// Falling trigger event configuration of line 1 + TR1: u1 = 0, + /// Falling trigger event configuration of line 2 + TR2: u1 = 0, + /// Falling trigger event configuration of line 3 + TR3: u1 = 0, + /// Falling trigger event configuration of line 4 + TR4: u1 = 0, + /// Falling trigger event configuration of line 5 + TR5: u1 = 0, + /// Falling trigger event configuration of line 6 + TR6: u1 = 0, + /// Falling trigger event configuration of line 7 + TR7: u1 = 0, + /// Falling trigger event configuration of line 8 + TR8: u1 = 0, + /// Falling trigger event configuration of line 9 + TR9: u1 = 0, + /// Falling trigger event configuration of line 10 + TR10: u1 = 0, + /// Falling trigger event configuration of line 11 + TR11: u1 = 0, + /// Falling trigger event configuration of line 12 + TR12: u1 = 0, + /// Falling trigger event configuration of line 13 + TR13: u1 = 0, + /// Falling trigger event configuration of line 14 + TR14: u1 = 0, + /// Falling trigger event configuration of line 15 + TR15: u1 = 0, + /// Falling trigger event configuration of line 16 + TR16: u1 = 0, + /// Falling trigger event configuration of line 17 + TR17: u1 = 0, + /// Falling trigger event configuration of line 18 + TR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2725,27 +3845,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Software interrupt event register (EXTI_SWIER) + + /// Software interrupt event register (EXTI_SWIER) pub const SWIER = mmio(Address + 0x00000010, 32, packed struct { - SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 - SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 - SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 - SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 - SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 - SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 - SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 - SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 - SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 - SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 - SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 - SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 - SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 - SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 - SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 - SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 - SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 - SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 - SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 + /// Software Interrupt on line 0 + SWIER0: u1 = 0, + /// Software Interrupt on line 1 + SWIER1: u1 = 0, + /// Software Interrupt on line 2 + SWIER2: u1 = 0, + /// Software Interrupt on line 3 + SWIER3: u1 = 0, + /// Software Interrupt on line 4 + SWIER4: u1 = 0, + /// Software Interrupt on line 5 + SWIER5: u1 = 0, + /// Software Interrupt on line 6 + SWIER6: u1 = 0, + /// Software Interrupt on line 7 + SWIER7: u1 = 0, + /// Software Interrupt on line 8 + SWIER8: u1 = 0, + /// Software Interrupt on line 9 + SWIER9: u1 = 0, + /// Software Interrupt on line 10 + SWIER10: u1 = 0, + /// Software Interrupt on line 11 + SWIER11: u1 = 0, + /// Software Interrupt on line 12 + SWIER12: u1 = 0, + /// Software Interrupt on line 13 + SWIER13: u1 = 0, + /// Software Interrupt on line 14 + SWIER14: u1 = 0, + /// Software Interrupt on line 15 + SWIER15: u1 = 0, + /// Software Interrupt on line 16 + SWIER16: u1 = 0, + /// Software Interrupt on line 17 + SWIER17: u1 = 0, + /// Software Interrupt on line 18 + SWIER18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2760,27 +3900,47 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Pending register (EXTI_PR) + + /// Pending register (EXTI_PR) pub const PR = mmio(Address + 0x00000014, 32, packed struct { - PR0: u1, // bit offset: 0 desc: Pending bit 0 - PR1: u1, // bit offset: 1 desc: Pending bit 1 - PR2: u1, // bit offset: 2 desc: Pending bit 2 - PR3: u1, // bit offset: 3 desc: Pending bit 3 - PR4: u1, // bit offset: 4 desc: Pending bit 4 - PR5: u1, // bit offset: 5 desc: Pending bit 5 - PR6: u1, // bit offset: 6 desc: Pending bit 6 - PR7: u1, // bit offset: 7 desc: Pending bit 7 - PR8: u1, // bit offset: 8 desc: Pending bit 8 - PR9: u1, // bit offset: 9 desc: Pending bit 9 - PR10: u1, // bit offset: 10 desc: Pending bit 10 - PR11: u1, // bit offset: 11 desc: Pending bit 11 - PR12: u1, // bit offset: 12 desc: Pending bit 12 - PR13: u1, // bit offset: 13 desc: Pending bit 13 - PR14: u1, // bit offset: 14 desc: Pending bit 14 - PR15: u1, // bit offset: 15 desc: Pending bit 15 - PR16: u1, // bit offset: 16 desc: Pending bit 16 - PR17: u1, // bit offset: 17 desc: Pending bit 17 - PR18: u1, // bit offset: 18 desc: Pending bit 18 + /// Pending bit 0 + PR0: u1 = 0, + /// Pending bit 1 + PR1: u1 = 0, + /// Pending bit 2 + PR2: u1 = 0, + /// Pending bit 3 + PR3: u1 = 0, + /// Pending bit 4 + PR4: u1 = 0, + /// Pending bit 5 + PR5: u1 = 0, + /// Pending bit 6 + PR6: u1 = 0, + /// Pending bit 7 + PR7: u1 = 0, + /// Pending bit 8 + PR8: u1 = 0, + /// Pending bit 9 + PR9: u1 = 0, + /// Pending bit 10 + PR10: u1 = 0, + /// Pending bit 11 + PR11: u1 = 0, + /// Pending bit 12 + PR12: u1 = 0, + /// Pending bit 13 + PR13: u1 = 0, + /// Pending bit 14 + PR14: u1 = 0, + /// Pending bit 15 + PR15: u1 = 0, + /// Pending bit 16 + PR16: u1 = 0, + /// Pending bit 17 + PR17: u1 = 0, + /// Pending bit 18 + PR18: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -2796,92 +3956,165 @@ pub const EXTI = extern struct { padding1: u1 = 0, }); }; + +/// DMA controller pub const DMA1 = extern struct { pub const Address: u32 = 0x40020000; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -2900,9 +4133,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2920,28 +4155,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -2960,9 +4212,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2980,28 +4234,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3020,9 +4291,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3040,28 +4313,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3080,9 +4370,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3100,28 +4392,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3140,9 +4449,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3160,28 +4471,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3200,9 +4528,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3220,28 +4550,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3260,9 +4607,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3280,101 +4629,178 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// DMA controller pub const DMA2 = extern struct { pub const Address: u32 = 0x40020400; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3393,9 +4819,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3413,28 +4841,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3453,9 +4898,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3473,28 +4920,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3513,9 +4977,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3533,28 +4999,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3573,9 +5056,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3593,28 +5078,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3633,9 +5135,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3653,28 +5157,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3693,9 +5214,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3713,28 +5236,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3753,9 +5293,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3773,20 +5315,26 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// Secure digital input/output interface pub const SDIO = extern struct { pub const Address: u32 = 0x40018000; - // byte offset: 0 Bits 1:0 = PWRCTRL: Power supply control bits + + /// Bits 1:0 = PWRCTRL: Power supply control bits pub const POWER = mmio(Address + 0x00000000, 32, packed struct { - PWRCTRL: u2, // bit offset: 0 desc: PWRCTRL padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -3818,15 +5366,23 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SDI clock control register (SDIO_CLKCR) + + /// SDI clock control register (SDIO_CLKCR) pub const CLKCR = mmio(Address + 0x00000004, 32, packed struct { - CLKDIV: u8, // bit offset: 0 desc: Clock divide factor - CLKEN: u1, // bit offset: 8 desc: Clock enable bit - PWRSAV: u1, // bit offset: 9 desc: Power saving configuration bit - BYPASS: u1, // bit offset: 10 desc: Clock divider bypass enable bit - WIDBUS: u2, // bit offset: 11 desc: Wide bus mode enable bit - NEGEDGE: u1, // bit offset: 13 desc: SDIO_CK dephasing selection bit - HWFC_EN: u1, // bit offset: 14 desc: HW Flow Control enable + /// Clock divide factor + CLKDIV: u8 = 0, + /// Clock enable bit + CLKEN: u1 = 0, + /// Power saving configuration bit + PWRSAV: u1 = 0, + /// Clock divider bypass enable bit + BYPASS: u1 = 0, + /// Wide bus mode enable bit + WIDBUS: u2 = 0, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1 = 0, + /// HW Flow Control enable + HWFC_EN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3845,21 +5401,15 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Bits 31:0 = : Command argument + + /// Bits 31:0 = : Command argument pub const ARG = mmio(Address + 0x00000008, 32, packed struct { - CMDARG: u32, // bit offset: 0 desc: Command argument + /// Command argument + CMDARG: u32 = 0, }); - // byte offset: 12 SDIO command register (SDIO_CMD) + + /// SDIO command register (SDIO_CMD) pub const CMD = mmio(Address + 0x0000000c, 32, packed struct { - CMDINDEX: u6, // bit offset: 0 desc: CMDINDEX - WAITRESP: u2, // bit offset: 6 desc: WAITRESP - WAITINT: u1, // bit offset: 8 desc: WAITINT - WAITPEND: u1, // bit offset: 9 desc: WAITPEND - CPSMEN: u1, // bit offset: 10 desc: CPSMEN - SDIOSuspend: u1, // bit offset: 11 desc: SDIOSuspend - ENCMDcompl: u1, // bit offset: 12 desc: ENCMDcompl - nIEN: u1, // bit offset: 13 desc: nIEN - CE_ATACMD: u1, // bit offset: 14 desc: CE_ATACMD padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3878,9 +5428,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SDIO command register + + /// SDIO command register pub const RESPCMD = mmio(Address + 0x00000010, 32, packed struct { - RESPCMD: u6, // bit offset: 0 desc: RESPCMD padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -3908,29 +5458,29 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct { - CARDSTATUS1: u32, // bit offset: 0 desc: CARDSTATUS1 - }); - // byte offset: 24 Bits 31:0 = CARDSTATUS2 - pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct { - CARDSTATUS2: u32, // bit offset: 0 desc: CARDSTATUS2 - }); - // byte offset: 28 Bits 31:0 = CARDSTATUS3 - pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct { - CARDSTATUS3: u32, // bit offset: 0 desc: CARDSTATUS3 - }); - // byte offset: 32 Bits 31:0 = CARDSTATUS4 - pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct { - CARDSTATUS4: u32, // bit offset: 0 desc: CARDSTATUS4 - }); - // byte offset: 36 Bits 31:0 = DATATIME: Data timeout period + + /// Bits 31:0 = CARDSTATUS1 + pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS2 + pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS3 + pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct {}); + + /// Bits 31:0 = CARDSTATUS4 + pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct {}); + + /// Bits 31:0 = DATATIME: Data timeout period pub const DTIMER = mmio(Address + 0x00000024, 32, packed struct { - DATATIME: u32, // bit offset: 0 desc: Data timeout period + /// Data timeout period + DATATIME: u32 = 0, }); - // byte offset: 40 Bits 24:0 = DATALENGTH: Data length value + + /// Bits 24:0 = DATALENGTH: Data length value pub const DLEN = mmio(Address + 0x00000028, 32, packed struct { - DATALENGTH: u25, // bit offset: 0 desc: Data length value + /// Data length value + DATALENGTH: u25 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -3939,17 +5489,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 SDIO data control register (SDIO_DCTRL) + + /// SDIO data control register (SDIO_DCTRL) pub const DCTRL = mmio(Address + 0x0000002c, 32, packed struct { - DTEN: u1, // bit offset: 0 desc: DTEN - DTDIR: u1, // bit offset: 1 desc: DTDIR - DTMODE: u1, // bit offset: 2 desc: DTMODE - DMAEN: u1, // bit offset: 3 desc: DMAEN - DBLOCKSIZE: u4, // bit offset: 4 desc: DBLOCKSIZE - PWSTART: u1, // bit offset: 8 desc: PWSTART - PWSTOP: u1, // bit offset: 9 desc: PWSTOP - RWMOD: u1, // bit offset: 10 desc: RWMOD - SDIOEN: u1, // bit offset: 11 desc: SDIOEN padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -3971,9 +5513,11 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 Bits 24:0 = DATACOUNT: Data count value + + /// Bits 24:0 = DATACOUNT: Data count value pub const DCOUNT = mmio(Address + 0x00000030, 32, packed struct { - DATACOUNT: u25, // bit offset: 0 desc: Data count value + /// Data count value + DATACOUNT: u25 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -3982,32 +5526,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 SDIO status register (SDIO_STA) + + /// SDIO status register (SDIO_STA) pub const STA = mmio(Address + 0x00000034, 32, packed struct { - CCRCFAIL: u1, // bit offset: 0 desc: CCRCFAIL - DCRCFAIL: u1, // bit offset: 1 desc: DCRCFAIL - CTIMEOUT: u1, // bit offset: 2 desc: CTIMEOUT - DTIMEOUT: u1, // bit offset: 3 desc: DTIMEOUT - TXUNDERR: u1, // bit offset: 4 desc: TXUNDERR - RXOVERR: u1, // bit offset: 5 desc: RXOVERR - CMDREND: u1, // bit offset: 6 desc: CMDREND - CMDSENT: u1, // bit offset: 7 desc: CMDSENT - DATAEND: u1, // bit offset: 8 desc: DATAEND - STBITERR: u1, // bit offset: 9 desc: STBITERR - DBCKEND: u1, // bit offset: 10 desc: DBCKEND - CMDACT: u1, // bit offset: 11 desc: CMDACT - TXACT: u1, // bit offset: 12 desc: TXACT - RXACT: u1, // bit offset: 13 desc: RXACT - TXFIFOHE: u1, // bit offset: 14 desc: TXFIFOHE - RXFIFOHF: u1, // bit offset: 15 desc: RXFIFOHF - TXFIFOF: u1, // bit offset: 16 desc: TXFIFOF - RXFIFOF: u1, // bit offset: 17 desc: RXFIFOF - TXFIFOE: u1, // bit offset: 18 desc: TXFIFOE - RXFIFOE: u1, // bit offset: 19 desc: RXFIFOE - TXDAVL: u1, // bit offset: 20 desc: TXDAVL - RXDAVL: u1, // bit offset: 21 desc: RXDAVL - SDIOIT: u1, // bit offset: 22 desc: SDIOIT - CEATAEND: u1, // bit offset: 23 desc: CEATAEND padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4017,19 +5538,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 SDIO interrupt clear register (SDIO_ICR) + + /// SDIO interrupt clear register (SDIO_ICR) pub const ICR = mmio(Address + 0x00000038, 32, packed struct { - CCRCFAILC: u1, // bit offset: 0 desc: CCRCFAILC - DCRCFAILC: u1, // bit offset: 1 desc: DCRCFAILC - CTIMEOUTC: u1, // bit offset: 2 desc: CTIMEOUTC - DTIMEOUTC: u1, // bit offset: 3 desc: DTIMEOUTC - TXUNDERRC: u1, // bit offset: 4 desc: TXUNDERRC - RXOVERRC: u1, // bit offset: 5 desc: RXOVERRC - CMDRENDC: u1, // bit offset: 6 desc: CMDRENDC - CMDSENTC: u1, // bit offset: 7 desc: CMDSENTC - DATAENDC: u1, // bit offset: 8 desc: DATAENDC - STBITERRC: u1, // bit offset: 9 desc: STBITERRC - DBCKENDC: u1, // bit offset: 10 desc: DBCKENDC reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -4041,8 +5552,6 @@ pub const SDIO = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SDIOITC: u1, // bit offset: 22 desc: SDIOITC - CEATAENDC: u1, // bit offset: 23 desc: CEATAENDC padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4052,32 +5561,9 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 SDIO mask register (SDIO_MASK) + + /// SDIO mask register (SDIO_MASK) pub const MASK = mmio(Address + 0x0000003c, 32, packed struct { - CCRCFAILIE: u1, // bit offset: 0 desc: CCRCFAILIE - DCRCFAILIE: u1, // bit offset: 1 desc: DCRCFAILIE - CTIMEOUTIE: u1, // bit offset: 2 desc: CTIMEOUTIE - DTIMEOUTIE: u1, // bit offset: 3 desc: DTIMEOUTIE - TXUNDERRIE: u1, // bit offset: 4 desc: TXUNDERRIE - RXOVERRIE: u1, // bit offset: 5 desc: RXOVERRIE - CMDRENDIE: u1, // bit offset: 6 desc: CMDRENDIE - CMDSENTIE: u1, // bit offset: 7 desc: CMDSENTIE - DATAENDIE: u1, // bit offset: 8 desc: DATAENDIE - STBITERRIE: u1, // bit offset: 9 desc: STBITERRIE - DBACKENDIE: u1, // bit offset: 10 desc: DBACKENDIE - CMDACTIE: u1, // bit offset: 11 desc: CMDACTIE - TXACTIE: u1, // bit offset: 12 desc: TXACTIE - RXACTIE: u1, // bit offset: 13 desc: RXACTIE - TXFIFOHEIE: u1, // bit offset: 14 desc: TXFIFOHEIE - RXFIFOHFIE: u1, // bit offset: 15 desc: RXFIFOHFIE - TXFIFOFIE: u1, // bit offset: 16 desc: TXFIFOFIE - RXFIFOFIE: u1, // bit offset: 17 desc: RXFIFOFIE - TXFIFOEIE: u1, // bit offset: 18 desc: TXFIFOEIE - RXFIFOEIE: u1, // bit offset: 19 desc: RXFIFOEIE - TXDAVLIE: u1, // bit offset: 20 desc: TXDAVLIE - RXDAVLIE: u1, // bit offset: 21 desc: RXDAVLIE - SDIOITIE: u1, // bit offset: 22 desc: SDIOITIE - CEATENDIE: u1, // bit offset: 23 desc: CEATENDIE padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4087,9 +5573,10 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO + + /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read + /// from the FIFO pub const FIFOCNT = mmio(Address + 0x00000048, 32, packed struct { - FIF0COUNT: u24, // bit offset: 0 desc: FIF0COUNT padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -4099,18 +5586,23 @@ pub const SDIO = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 128 bits 31:0 = FIFOData: Receive and transmit FIFO data - pub const FIFO = mmio(Address + 0x00000080, 32, packed struct { - FIFOData: u32, // bit offset: 0 desc: FIFOData - }); + + /// bits 31:0 = FIFOData: Receive and transmit FIFO data + pub const FIFO = mmio(Address + 0x00000080, 32, packed struct {}); }; + +/// Real time clock pub const RTC = extern struct { pub const Address: u32 = 0x40002800; - // byte offset: 0 RTC Control Register High + + /// RTC Control Register High pub const CRH = mmio(Address + 0x00000000, 32, packed struct { - SECIE: u1, // bit offset: 0 desc: Second interrupt Enable - ALRIE: u1, // bit offset: 1 desc: Alarm interrupt Enable - OWIE: u1, // bit offset: 2 desc: Overflow interrupt Enable + /// Second interrupt Enable + SECIE: u1 = 0, + /// Alarm interrupt Enable + ALRIE: u1 = 0, + /// Overflow interrupt Enable + OWIE: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -4141,14 +5633,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 RTC Control Register Low + + /// RTC Control Register Low pub const CRL = mmio(Address + 0x00000004, 32, packed struct { - SECF: u1, // bit offset: 0 desc: Second Flag - ALRF: u1, // bit offset: 1 desc: Alarm Flag - OWF: u1, // bit offset: 2 desc: Overflow Flag - RSF: u1, // bit offset: 3 desc: Registers Synchronized Flag - CNF: u1, // bit offset: 4 desc: Configuration Flag - RTOFF: u1, // bit offset: 5 desc: RTC operation OFF + /// Second Flag + SECF: u1 = 0, + /// Alarm Flag + ALRF: u1 = 0, + /// Overflow Flag + OWF: u1 = 0, + /// Registers Synchronized Flag + RSF: u1 = 0, + /// Configuration Flag + CNF: u1 = 0, + /// RTC operation OFF + RTOFF: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -4176,9 +5675,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 RTC Prescaler Load Register High + + /// RTC Prescaler Load Register High pub const PRLH = mmio(Address + 0x00000008, 32, packed struct { - PRLH: u4, // bit offset: 0 desc: RTC Prescaler Load Register High + /// RTC Prescaler Load Register High + PRLH: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4208,9 +5709,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 RTC Prescaler Load Register Low + + /// RTC Prescaler Load Register Low pub const PRLL = mmio(Address + 0x0000000c, 32, packed struct { - PRLL: u16, // bit offset: 0 desc: RTC Prescaler Divider Register Low + /// RTC Prescaler Divider Register Low + PRLL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4228,9 +5731,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 RTC Prescaler Divider Register High + + /// RTC Prescaler Divider Register High pub const DIVH = mmio(Address + 0x00000010, 32, packed struct { - DIVH: u4, // bit offset: 0 desc: RTC prescaler divider register high + /// RTC prescaler divider register high + DIVH: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -4260,9 +5765,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RTC Prescaler Divider Register Low + + /// RTC Prescaler Divider Register Low pub const DIVL = mmio(Address + 0x00000014, 32, packed struct { - DIVL: u16, // bit offset: 0 desc: RTC prescaler divider register Low + /// RTC prescaler divider register Low + DIVL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4280,9 +5787,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 RTC Counter Register High + + /// RTC Counter Register High pub const CNTH = mmio(Address + 0x00000018, 32, packed struct { - CNTH: u16, // bit offset: 0 desc: RTC counter register high + /// RTC counter register high + CNTH: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4300,9 +5809,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 RTC Counter Register Low + + /// RTC Counter Register Low pub const CNTL = mmio(Address + 0x0000001c, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: RTC counter register Low + /// RTC counter register Low + CNTL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4320,9 +5831,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 RTC Alarm Register High + + /// RTC Alarm Register High pub const ALRH = mmio(Address + 0x00000020, 32, packed struct { - ALRH: u16, // bit offset: 0 desc: RTC alarm register high + /// RTC alarm register high + ALRH: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4340,9 +5853,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 RTC Alarm Register Low + + /// RTC Alarm Register Low pub const ALRL = mmio(Address + 0x00000024, 32, packed struct { - ALRL: u16, // bit offset: 0 desc: RTC alarm register low + /// RTC alarm register low + ALRL: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4361,11 +5876,15 @@ pub const RTC = extern struct { padding1: u1 = 0, }); }; + +/// Backup registers pub const BKP = extern struct { pub const Address: u32 = 0x40006c04; - // byte offset: 0 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR1 = mmio(Address + 0x00000000, 32, packed struct { - D1: u16, // bit offset: 0 desc: Backup data + /// Backup data + D1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4383,9 +5902,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR2 = mmio(Address + 0x00000004, 32, packed struct { - D2: u16, // bit offset: 0 desc: Backup data + /// Backup data + D2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4403,9 +5924,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR3 = mmio(Address + 0x00000008, 32, packed struct { - D3: u16, // bit offset: 0 desc: Backup data + /// Backup data + D3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4423,9 +5946,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR4 = mmio(Address + 0x0000000c, 32, packed struct { - D4: u16, // bit offset: 0 desc: Backup data + /// Backup data + D4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4443,9 +5968,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR5 = mmio(Address + 0x00000010, 32, packed struct { - D5: u16, // bit offset: 0 desc: Backup data + /// Backup data + D5: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4463,9 +5990,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR6 = mmio(Address + 0x00000014, 32, packed struct { - D6: u16, // bit offset: 0 desc: Backup data + /// Backup data + D6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4483,9 +6012,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR7 = mmio(Address + 0x00000018, 32, packed struct { - D7: u16, // bit offset: 0 desc: Backup data + /// Backup data + D7: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4503,9 +6034,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR8 = mmio(Address + 0x0000001c, 32, packed struct { - D8: u16, // bit offset: 0 desc: Backup data + /// Backup data + D8: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4523,9 +6056,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR9 = mmio(Address + 0x00000020, 32, packed struct { - D9: u16, // bit offset: 0 desc: Backup data + /// Backup data + D9: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4543,9 +6078,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR10 = mmio(Address + 0x00000024, 32, packed struct { - D10: u16, // bit offset: 0 desc: Backup data + /// Backup data + D10: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4563,12 +6100,17 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 RTC clock calibration register (BKP_RTCCR) + + /// RTC clock calibration register (BKP_RTCCR) pub const RTCCR = mmio(Address + 0x00000028, 32, packed struct { - CAL: u7, // bit offset: 0 desc: Calibration value - CCO: u1, // bit offset: 7 desc: Calibration Clock Output - ASOE: u1, // bit offset: 8 desc: Alarm or second output enable - ASOS: u1, // bit offset: 9 desc: Alarm or second output selection + /// Calibration value + CAL: u7 = 0, + /// Calibration Clock Output + CCO: u1 = 0, + /// Alarm or second output enable + ASOE: u1 = 0, + /// Alarm or second output selection + ASOS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -4592,10 +6134,13 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Backup control register (BKP_CR) + + /// Backup control register (BKP_CR) pub const CR = mmio(Address + 0x0000002c, 32, packed struct { - TPE: u1, // bit offset: 0 desc: Tamper pin enable - TPAL: u1, // bit offset: 1 desc: Tamper pin active level + /// Tamper pin enable + TPE: u1 = 0, + /// Tamper pin active level + TPAL: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -4627,18 +6172,24 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 BKP_CSR control/status register (BKP_CSR) + + /// BKP_CSR control/status register (BKP_CSR) pub const CSR = mmio(Address + 0x00000030, 32, packed struct { - CTE: u1, // bit offset: 0 desc: Clear Tamper event - CTI: u1, // bit offset: 1 desc: Clear Tamper Interrupt - TPIE: u1, // bit offset: 2 desc: Tamper Pin interrupt enable + /// Clear Tamper event + CTE: u1 = 0, + /// Clear Tamper Interrupt + CTI: u1 = 0, + /// Tamper Pin interrupt enable + TPIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TEF: u1, // bit offset: 8 desc: Tamper Event Flag - TIF: u1, // bit offset: 9 desc: Tamper Interrupt Flag + /// Tamper Event Flag + TEF: u1 = 0, + /// Tamper Interrupt Flag + TIF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -4662,9 +6213,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR11 = mmio(Address + 0x0000003c, 32, packed struct { - DR11: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR11: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4682,9 +6235,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR12 = mmio(Address + 0x00000040, 32, packed struct { - DR12: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR12: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4702,9 +6257,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR13 = mmio(Address + 0x00000044, 32, packed struct { - DR13: u16, // bit offset: 0 desc: Backup data + /// Backup data + DR13: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4722,9 +6279,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR14 = mmio(Address + 0x00000048, 32, packed struct { - D14: u16, // bit offset: 0 desc: Backup data + /// Backup data + D14: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4742,9 +6301,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR15 = mmio(Address + 0x0000004c, 32, packed struct { - D15: u16, // bit offset: 0 desc: Backup data + /// Backup data + D15: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4762,9 +6323,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR16 = mmio(Address + 0x00000050, 32, packed struct { - D16: u16, // bit offset: 0 desc: Backup data + /// Backup data + D16: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4782,9 +6345,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR17 = mmio(Address + 0x00000054, 32, packed struct { - D17: u16, // bit offset: 0 desc: Backup data + /// Backup data + D17: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4802,9 +6367,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR18 = mmio(Address + 0x00000058, 32, packed struct { - D18: u16, // bit offset: 0 desc: Backup data + /// Backup data + D18: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4822,9 +6389,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR19 = mmio(Address + 0x0000005c, 32, packed struct { - D19: u16, // bit offset: 0 desc: Backup data + /// Backup data + D19: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4842,9 +6411,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR20 = mmio(Address + 0x00000060, 32, packed struct { - D20: u16, // bit offset: 0 desc: Backup data + /// Backup data + D20: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4862,9 +6433,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR21 = mmio(Address + 0x00000064, 32, packed struct { - D21: u16, // bit offset: 0 desc: Backup data + /// Backup data + D21: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4882,9 +6455,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR22 = mmio(Address + 0x00000068, 32, packed struct { - D22: u16, // bit offset: 0 desc: Backup data + /// Backup data + D22: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4902,9 +6477,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 108 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR23 = mmio(Address + 0x0000006c, 32, packed struct { - D23: u16, // bit offset: 0 desc: Backup data + /// Backup data + D23: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4922,9 +6499,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR24 = mmio(Address + 0x00000070, 32, packed struct { - D24: u16, // bit offset: 0 desc: Backup data + /// Backup data + D24: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4942,9 +6521,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR25 = mmio(Address + 0x00000074, 32, packed struct { - D25: u16, // bit offset: 0 desc: Backup data + /// Backup data + D25: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4962,9 +6543,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 120 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR26 = mmio(Address + 0x00000078, 32, packed struct { - D26: u16, // bit offset: 0 desc: Backup data + /// Backup data + D26: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4982,9 +6565,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 124 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR27 = mmio(Address + 0x0000007c, 32, packed struct { - D27: u16, // bit offset: 0 desc: Backup data + /// Backup data + D27: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5002,9 +6587,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 128 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR28 = mmio(Address + 0x00000080, 32, packed struct { - D28: u16, // bit offset: 0 desc: Backup data + /// Backup data + D28: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5022,9 +6609,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR29 = mmio(Address + 0x00000084, 32, packed struct { - D29: u16, // bit offset: 0 desc: Backup data + /// Backup data + D29: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5042,9 +6631,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR30 = mmio(Address + 0x00000088, 32, packed struct { - D30: u16, // bit offset: 0 desc: Backup data + /// Backup data + D30: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5062,9 +6653,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR31 = mmio(Address + 0x0000008c, 32, packed struct { - D31: u16, // bit offset: 0 desc: Backup data + /// Backup data + D31: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5082,9 +6675,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 144 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR32 = mmio(Address + 0x00000090, 32, packed struct { - D32: u16, // bit offset: 0 desc: Backup data + /// Backup data + D32: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5102,9 +6697,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 148 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR33 = mmio(Address + 0x00000094, 32, packed struct { - D33: u16, // bit offset: 0 desc: Backup data + /// Backup data + D33: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5122,9 +6719,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 152 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR34 = mmio(Address + 0x00000098, 32, packed struct { - D34: u16, // bit offset: 0 desc: Backup data + /// Backup data + D34: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5142,9 +6741,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 156 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR35 = mmio(Address + 0x0000009c, 32, packed struct { - D35: u16, // bit offset: 0 desc: Backup data + /// Backup data + D35: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5162,9 +6763,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR36 = mmio(Address + 0x000000a0, 32, packed struct { - D36: u16, // bit offset: 0 desc: Backup data + /// Backup data + D36: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5182,9 +6785,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR37 = mmio(Address + 0x000000a4, 32, packed struct { - D37: u16, // bit offset: 0 desc: Backup data + /// Backup data + D37: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5202,9 +6807,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR38 = mmio(Address + 0x000000a8, 32, packed struct { - D38: u16, // bit offset: 0 desc: Backup data + /// Backup data + D38: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5222,9 +6829,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 172 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR39 = mmio(Address + 0x000000ac, 32, packed struct { - D39: u16, // bit offset: 0 desc: Backup data + /// Backup data + D39: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5242,9 +6851,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR40 = mmio(Address + 0x000000b0, 32, packed struct { - D40: u16, // bit offset: 0 desc: Backup data + /// Backup data + D40: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5262,9 +6873,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR41 = mmio(Address + 0x000000b4, 32, packed struct { - D41: u16, // bit offset: 0 desc: Backup data + /// Backup data + D41: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5282,9 +6895,11 @@ pub const BKP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 184 Backup data register (BKP_DR) + + /// Backup data register (BKP_DR) pub const DR42 = mmio(Address + 0x000000b8, 32, packed struct { - D42: u16, // bit offset: 0 desc: Backup data + /// Backup data + D42: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5303,11 +6918,15 @@ pub const BKP = extern struct { padding1: u1 = 0, }); }; + +/// Independent watchdog pub const IWDG = extern struct { pub const Address: u32 = 0x40003000; - // byte offset: 0 Key register (IWDG_KR) + + /// Key register (IWDG_KR) pub const KR = mmio(Address + 0x00000000, 32, packed struct { - KEY: u16, // bit offset: 0 desc: Key value + /// Key value + KEY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5325,9 +6944,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Prescaler register (IWDG_PR) + + /// Prescaler register (IWDG_PR) pub const PR = mmio(Address + 0x00000004, 32, packed struct { - PR: u3, // bit offset: 0 desc: Prescaler divider + /// Prescaler divider + PR: u3 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -5358,9 +6979,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Reload register (IWDG_RLR) + + /// Reload register (IWDG_RLR) pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - RL: u12, // bit offset: 0 desc: Watchdog counter reload value + /// Watchdog counter reload value + RL: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5382,10 +7005,13 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Status register (IWDG_SR) + + /// Status register (IWDG_SR) pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update - RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update + /// Watchdog prescaler value update + PVU: u1 = 0, + /// Watchdog counter reload value update + RVU: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -5418,12 +7044,17 @@ pub const IWDG = extern struct { padding1: u1 = 0, }); }; + +/// Window watchdog pub const WWDG = extern struct { pub const Address: u32 = 0x40002c00; - // byte offset: 0 Control register (WWDG_CR) + + /// Control register (WWDG_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - T: u7, // bit offset: 0 desc: 7-bit counter (MSB to LSB) - WDGA: u1, // bit offset: 7 desc: Activation bit + /// 7-bit counter (MSB to LSB) + T: u7 = 0, + /// Activation bit + WDGA: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5449,11 +7080,15 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Configuration register (WWDG_CFR) + + /// Configuration register (WWDG_CFR) pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - W: u7, // bit offset: 0 desc: 7-bit window value - WDGTB: u2, // bit offset: 7 desc: Timer Base - EWI: u1, // bit offset: 9 desc: Early Wakeup Interrupt + /// 7-bit window value + W: u7 = 0, + /// Timer Base + WDGTB: u2 = 0, + /// Early Wakeup Interrupt + EWI: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -5477,9 +7112,11 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Status register (WWDG_SR) + + /// Status register (WWDG_SR) pub const SR = mmio(Address + 0x00000008, 32, packed struct { - EWI: u1, // bit offset: 0 desc: Early Wakeup Interrupt + /// Early Wakeup Interrupt + EWI: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -5513,18 +7150,29 @@ pub const WWDG = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM1 = extern struct { pub const Address: u32 = 0x40012c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -5548,21 +7196,34 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5581,16 +7242,24 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5608,23 +7277,39 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5643,21 +7328,34 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5678,16 +7376,25 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5713,18 +7420,29 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5742,14 +7460,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + ICPCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5767,18 +7492,29 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5796,14 +7532,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5821,22 +7564,37 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -5856,9 +7614,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5876,9 +7636,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5896,9 +7658,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5916,9 +7680,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5944,9 +7710,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5964,9 +7732,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5984,9 +7754,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6004,9 +7776,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6024,16 +7798,25 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6051,13 +7834,16 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6078,9 +7864,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6099,18 +7887,29 @@ pub const TIM1 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM8 = extern struct { pub const Address: u32 = 0x40013400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6134,21 +7933,34 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6167,16 +7979,24 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6194,23 +8014,39 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6229,21 +8065,34 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6264,16 +8113,25 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6299,18 +8157,29 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6328,14 +8197,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - ICPCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + ICPCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6353,18 +8229,29 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6382,14 +8269,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6407,22 +8301,37 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -6442,9 +8351,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6462,9 +8373,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6482,9 +8395,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6502,9 +8417,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6530,9 +8447,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6550,9 +8469,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6570,9 +8491,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6590,9 +8513,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6610,16 +8535,25 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6637,13 +8571,16 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6664,9 +8601,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6685,18 +8624,29 @@ pub const TIM8 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM2 = extern struct { pub const Address: u32 = 0x40000000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6720,14 +8670,18 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6753,16 +8707,24 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6780,23 +8742,36 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6815,21 +8790,32 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6850,15 +8836,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -6885,18 +8878,29 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6914,14 +8918,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6939,18 +8950,29 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6968,14 +8990,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6993,22 +9022,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -7028,9 +9066,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7048,9 +9088,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7068,9 +9110,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7088,9 +9132,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7108,9 +9154,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7128,9 +9176,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7148,9 +9198,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7168,13 +9220,16 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7195,9 +9250,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7216,18 +9273,29 @@ pub const TIM2 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM3 = extern struct { pub const Address: u32 = 0x40000400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -7251,14 +9319,18 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7284,16 +9356,24 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7311,23 +9391,36 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -7346,21 +9439,32 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7381,15 +9485,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -7416,18 +9527,29 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7445,14 +9567,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7470,18 +9599,29 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7499,14 +9639,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7524,22 +9671,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -7559,9 +9715,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7579,9 +9737,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7599,9 +9759,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7619,9 +9781,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7639,9 +9803,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7659,9 +9825,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7679,9 +9847,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7699,13 +9869,16 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7726,9 +9899,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7747,18 +9922,29 @@ pub const TIM3 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM4 = extern struct { pub const Address: u32 = 0x40000800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -7782,14 +9968,18 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7815,16 +10005,24 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7842,23 +10040,36 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -7877,21 +10088,32 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7912,15 +10134,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -7947,18 +10176,29 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7976,14 +10216,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8001,18 +10248,29 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8030,14 +10288,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8055,22 +10320,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -8090,9 +10364,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8110,9 +10386,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8130,9 +10408,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8150,9 +10430,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8170,9 +10452,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8190,9 +10474,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8210,9 +10496,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8230,13 +10518,16 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8257,9 +10548,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8278,18 +10571,29 @@ pub const TIM4 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM5 = extern struct { pub const Address: u32 = 0x40000c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8313,14 +10617,18 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8346,16 +10654,24 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8373,23 +10689,36 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8408,21 +10737,32 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8443,15 +10783,22 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8478,18 +10825,29 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8507,14 +10865,21 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8532,18 +10897,29 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8561,14 +10937,21 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8586,22 +10969,31 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -8621,9 +11013,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8641,9 +11035,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8661,9 +11057,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8681,9 +11079,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8701,9 +11101,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8721,9 +11123,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8741,9 +11145,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare value + /// Capture/Compare value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8761,13 +11167,16 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8788,9 +11197,11 @@ pub const TIM5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8809,19 +11220,28 @@ pub const TIM5 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM9 = extern struct { pub const Address: u32 = 0x40014c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8845,13 +11265,15 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8878,12 +11300,16 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -8909,15 +11335,20 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -8944,19 +11375,26 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -8979,15 +11417,20 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9014,17 +11457,26 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9043,14 +11495,21 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9068,16 +11527,23 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9103,9 +11569,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9123,9 +11591,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9143,9 +11613,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9163,9 +11635,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9183,9 +11657,11 @@ pub const TIM9 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9204,19 +11680,28 @@ pub const TIM9 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM12 = extern struct { pub const Address: u32 = 0x40001800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9240,13 +11725,15 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9273,12 +11760,16 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9304,15 +11795,20 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable + /// Trigger interrupt enable + TIE: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9339,19 +11835,26 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Trigger interrupt flag + TIF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -9374,15 +11877,20 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9409,17 +11917,26 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9438,14 +11955,21 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9463,16 +11987,23 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9498,9 +12029,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9518,9 +12051,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9538,9 +12073,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9558,9 +12095,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9578,9 +12117,11 @@ pub const TIM12 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9599,19 +12140,27 @@ pub const TIM12 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM10 = extern struct { pub const Address: u32 = 0x40015000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9635,13 +12184,15 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9668,10 +12219,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9703,10 +12257,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -9714,7 +12271,8 @@ pub const TIM10 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9738,10 +12296,13 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -9773,12 +12334,16 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -9805,11 +12370,15 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -9835,12 +12404,16 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -9870,9 +12443,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9890,9 +12465,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9910,9 +12487,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9930,9 +12509,11 @@ pub const TIM10 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9951,19 +12532,27 @@ pub const TIM10 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM11 = extern struct { pub const Address: u32 = 0x40015400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9987,13 +12576,15 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10020,10 +12611,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10055,10 +12649,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10066,7 +12663,8 @@ pub const TIM11 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10090,10 +12688,13 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10125,12 +12726,16 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10157,11 +12762,15 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10187,12 +12796,16 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10222,9 +12835,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10242,9 +12857,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10262,9 +12879,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10282,9 +12901,11 @@ pub const TIM11 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10303,19 +12924,27 @@ pub const TIM11 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM13 = extern struct { pub const Address: u32 = 0x40001c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10339,13 +12968,15 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10372,10 +13003,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10407,10 +13041,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10418,7 +13055,8 @@ pub const TIM13 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10442,10 +13080,13 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10477,12 +13118,16 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10509,11 +13154,15 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10539,12 +13188,16 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10574,9 +13227,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10594,9 +13249,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10614,9 +13271,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10634,9 +13293,11 @@ pub const TIM13 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10655,19 +13316,27 @@ pub const TIM13 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM14 = extern struct { pub const Address: u32 = 0x40002000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10691,13 +13360,15 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10724,10 +13395,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10759,10 +13433,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10770,7 +13447,8 @@ pub const TIM14 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10794,10 +13472,13 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10829,12 +13510,16 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection + /// Capture/Compare 1 selection + CC1S: u2 = 0, reserved1: u1 = 0, - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -10861,11 +13546,15 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (input mode) + + /// capture/compare mode register (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -10891,12 +13580,16 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10926,9 +13619,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10946,9 +13641,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10966,9 +13663,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10986,9 +13685,11 @@ pub const TIM14 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11007,18 +13708,26 @@ pub const TIM14 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timer pub const TIM6 = extern struct { pub const Address: u32 = 0x40001000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11044,13 +13753,15 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -11077,9 +13788,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11087,7 +13800,8 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -11112,9 +13826,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11147,9 +13863,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11182,9 +13900,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11202,9 +13922,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11222,9 +13944,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11243,18 +13967,26 @@ pub const TIM6 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timer pub const TIM7 = extern struct { pub const Address: u32 = 0x40001400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11280,13 +14012,15 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -11313,9 +14047,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11323,7 +14059,8 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -11348,9 +14085,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11383,9 +14122,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -11418,9 +14159,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11438,9 +14181,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11458,9 +14203,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11479,26 +14226,43 @@ pub const TIM7 = extern struct { padding1: u1 = 0, }); }; + +/// Inter integrated circuit pub const I2C1 = extern struct { pub const Address: u32 = 0x40005400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - SMBUS: u1, // bit offset: 1 desc: SMBus mode + /// Peripheral enable + PE: u1 = 0, + /// SMBus mode + SMBUS: u1 = 0, reserved1: u1 = 0, - SMBTYPE: u1, // bit offset: 3 desc: SMBus type - ENARP: u1, // bit offset: 4 desc: ARP enable - ENPEC: u1, // bit offset: 5 desc: PEC enable - ENGC: u1, // bit offset: 6 desc: General call enable - NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) - START: u1, // bit offset: 8 desc: Start generation - STOP: u1, // bit offset: 9 desc: Stop generation - ACK: u1, // bit offset: 10 desc: Acknowledge enable - POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) - PEC: u1, // bit offset: 12 desc: Packet error checking - ALERT: u1, // bit offset: 13 desc: SMBus alert + /// SMBus type + SMBTYPE: u1 = 0, + /// ARP enable + ENARP: u1 = 0, + /// PEC enable + ENPEC: u1 = 0, + /// General call enable + ENGC: u1 = 0, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation + STOP: u1 = 0, + /// Acknowledge enable + ACK: u1 = 0, + /// Acknowledge/PEC Position (for data reception) + POS: u1 = 0, + /// Packet error checking + PEC: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, reserved2: u1 = 0, - SWRST: u1, // bit offset: 15 desc: Software reset + /// Software reset + SWRST: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11516,16 +14280,23 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + /// Peripheral clock frequency + FREQ: u6 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ITERREN: u1, // bit offset: 8 desc: Error interrupt enable - ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable - ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable - DMAEN: u1, // bit offset: 11 desc: DMA requests enable - LAST: u1, // bit offset: 12 desc: DMA last transfer + /// Error interrupt enable + ITERREN: u1 = 0, + /// Event interrupt enable + ITEVTEN: u1 = 0, + /// Buffer interrupt enable + ITBUFEN: u1 = 0, + /// DMA requests enable + DMAEN: u1 = 0, + /// DMA last transfer + LAST: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -11546,17 +14317,22 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - ADD0: u1, // bit offset: 0 desc: Interface address - ADD7: u7, // bit offset: 1 desc: Interface address - ADD10: u2, // bit offset: 8 desc: Interface address + /// Interface address + ADD0: u1 = 0, + /// Interface address + ADD7: u7 = 0, + /// Interface address + ADD10: u2 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + /// Addressing mode (slave mode) + ADDMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11574,10 +14350,13 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable - ADD2: u7, // bit offset: 1 desc: Interface address + /// Dual addressing mode enable + ENDUAL: u1 = 0, + /// Interface address + ADD2: u7 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11603,9 +14382,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Data register + + /// Data register pub const DR = mmio(Address + 0x00000010, 32, packed struct { - DR: u8, // bit offset: 0 desc: 8-bit data register + /// 8-bit data register + DR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11631,24 +14412,39 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - SB: u1, // bit offset: 0 desc: Start bit (Master mode) - ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) - BTF: u1, // bit offset: 2 desc: Byte transfer finished - ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) - STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + /// Start bit (Master mode) + SB: u1 = 0, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1 = 0, + /// Byte transfer finished + BTF: u1 = 0, + /// 10-bit header sent (Master mode) + ADD10: u1 = 0, + /// Stop detection (slave mode) + STOPF: u1 = 0, reserved1: u1 = 0, - RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) - TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) - AF: u1, // bit offset: 10 desc: Acknowledge failure - OVR: u1, // bit offset: 11 desc: Overrun/Underrun - PECERR: u1, // bit offset: 12 desc: PEC Error in reception + /// Data register not empty (receivers) + RxNE: u1 = 0, + /// Data register empty (transmitters) + TxE: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost (master mode) + ARLO: u1 = 0, + /// Acknowledge failure + AF: u1 = 0, + /// Overrun/Underrun + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, reserved2: u1 = 0, - TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error - SMBALERT: u1, // bit offset: 15 desc: SMBus alert + /// Timeout or Tlow error + TIMEOUT: u1 = 0, + /// SMBus alert + SMBALERT: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11666,17 +14462,26 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Status register 2 + + /// Status register 2 pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - MSL: u1, // bit offset: 0 desc: Master/slave - BUSY: u1, // bit offset: 1 desc: Bus busy - TRA: u1, // bit offset: 2 desc: Transmitter/receiver + /// Master/slave + MSL: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transmitter/receiver + TRA: u1 = 0, reserved1: u1 = 0, - GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) - SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) - SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) - DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) - PEC: u8, // bit offset: 8 desc: acket error checking register + /// General call address (Slave mode) + GENCALL: u1 = 0, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1 = 0, + /// SMBus host header (Slave mode) + SMBHOST: u1 = 0, + /// Dual flag (Slave mode) + DUALF: u1 = 0, + /// acket error checking register + PEC: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11694,13 +14499,17 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Clock control register + + /// Clock control register pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle - F_S: u1, // bit offset: 15 desc: I2C master mode selection + /// Fast mode duty cycle + DUTY: u1 = 0, + /// I2C master mode selection + F_S: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11718,9 +14527,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 TRISE register + + /// TRISE register pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -11749,26 +14560,43 @@ pub const I2C1 = extern struct { padding1: u1 = 0, }); }; + +/// Inter integrated circuit pub const I2C2 = extern struct { pub const Address: u32 = 0x40005800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - SMBUS: u1, // bit offset: 1 desc: SMBus mode + /// Peripheral enable + PE: u1 = 0, + /// SMBus mode + SMBUS: u1 = 0, reserved1: u1 = 0, - SMBTYPE: u1, // bit offset: 3 desc: SMBus type - ENARP: u1, // bit offset: 4 desc: ARP enable - ENPEC: u1, // bit offset: 5 desc: PEC enable - ENGC: u1, // bit offset: 6 desc: General call enable - NOSTRETCH: u1, // bit offset: 7 desc: Clock stretching disable (Slave mode) - START: u1, // bit offset: 8 desc: Start generation - STOP: u1, // bit offset: 9 desc: Stop generation - ACK: u1, // bit offset: 10 desc: Acknowledge enable - POS: u1, // bit offset: 11 desc: Acknowledge/PEC Position (for data reception) - PEC: u1, // bit offset: 12 desc: Packet error checking - ALERT: u1, // bit offset: 13 desc: SMBus alert + /// SMBus type + SMBTYPE: u1 = 0, + /// ARP enable + ENARP: u1 = 0, + /// PEC enable + ENPEC: u1 = 0, + /// General call enable + ENGC: u1 = 0, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation + STOP: u1 = 0, + /// Acknowledge enable + ACK: u1 = 0, + /// Acknowledge/PEC Position (for data reception) + POS: u1 = 0, + /// Packet error checking + PEC: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, reserved2: u1 = 0, - SWRST: u1, // bit offset: 15 desc: Software reset + /// Software reset + SWRST: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11786,16 +14614,23 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - FREQ: u6, // bit offset: 0 desc: Peripheral clock frequency + /// Peripheral clock frequency + FREQ: u6 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ITERREN: u1, // bit offset: 8 desc: Error interrupt enable - ITEVTEN: u1, // bit offset: 9 desc: Event interrupt enable - ITBUFEN: u1, // bit offset: 10 desc: Buffer interrupt enable - DMAEN: u1, // bit offset: 11 desc: DMA requests enable - LAST: u1, // bit offset: 12 desc: DMA last transfer + /// Error interrupt enable + ITERREN: u1 = 0, + /// Event interrupt enable + ITEVTEN: u1 = 0, + /// Buffer interrupt enable + ITBUFEN: u1 = 0, + /// DMA requests enable + DMAEN: u1 = 0, + /// DMA last transfer + LAST: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -11816,17 +14651,22 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - ADD0: u1, // bit offset: 0 desc: Interface address - ADD7: u7, // bit offset: 1 desc: Interface address - ADD10: u2, // bit offset: 8 desc: Interface address + /// Interface address + ADD0: u1 = 0, + /// Interface address + ADD7: u7 = 0, + /// Interface address + ADD10: u2 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDMODE: u1, // bit offset: 15 desc: Addressing mode (slave mode) + /// Addressing mode (slave mode) + ADDMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11844,10 +14684,13 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - ENDUAL: u1, // bit offset: 0 desc: Dual addressing mode enable - ADD2: u7, // bit offset: 1 desc: Interface address + /// Dual addressing mode enable + ENDUAL: u1 = 0, + /// Interface address + ADD2: u7 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11873,9 +14716,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Data register + + /// Data register pub const DR = mmio(Address + 0x00000010, 32, packed struct { - DR: u8, // bit offset: 0 desc: 8-bit data register + /// 8-bit data register + DR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -11901,24 +14746,39 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - SB: u1, // bit offset: 0 desc: Start bit (Master mode) - ADDR: u1, // bit offset: 1 desc: Address sent (master mode)/matched (slave mode) - BTF: u1, // bit offset: 2 desc: Byte transfer finished - ADD10: u1, // bit offset: 3 desc: 10-bit header sent (Master mode) - STOPF: u1, // bit offset: 4 desc: Stop detection (slave mode) + /// Start bit (Master mode) + SB: u1 = 0, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1 = 0, + /// Byte transfer finished + BTF: u1 = 0, + /// 10-bit header sent (Master mode) + ADD10: u1 = 0, + /// Stop detection (slave mode) + STOPF: u1 = 0, reserved1: u1 = 0, - RxNE: u1, // bit offset: 6 desc: Data register not empty (receivers) - TxE: u1, // bit offset: 7 desc: Data register empty (transmitters) - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost (master mode) - AF: u1, // bit offset: 10 desc: Acknowledge failure - OVR: u1, // bit offset: 11 desc: Overrun/Underrun - PECERR: u1, // bit offset: 12 desc: PEC Error in reception + /// Data register not empty (receivers) + RxNE: u1 = 0, + /// Data register empty (transmitters) + TxE: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost (master mode) + ARLO: u1 = 0, + /// Acknowledge failure + AF: u1 = 0, + /// Overrun/Underrun + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, reserved2: u1 = 0, - TIMEOUT: u1, // bit offset: 14 desc: Timeout or Tlow error - SMBALERT: u1, // bit offset: 15 desc: SMBus alert + /// Timeout or Tlow error + TIMEOUT: u1 = 0, + /// SMBus alert + SMBALERT: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11936,17 +14796,26 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Status register 2 + + /// Status register 2 pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - MSL: u1, // bit offset: 0 desc: Master/slave - BUSY: u1, // bit offset: 1 desc: Bus busy - TRA: u1, // bit offset: 2 desc: Transmitter/receiver + /// Master/slave + MSL: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transmitter/receiver + TRA: u1 = 0, reserved1: u1 = 0, - GENCALL: u1, // bit offset: 4 desc: General call address (Slave mode) - SMBDEFAULT: u1, // bit offset: 5 desc: SMBus device default address (Slave mode) - SMBHOST: u1, // bit offset: 6 desc: SMBus host header (Slave mode) - DUALF: u1, // bit offset: 7 desc: Dual flag (Slave mode) - PEC: u8, // bit offset: 8 desc: acket error checking register + /// General call address (Slave mode) + GENCALL: u1 = 0, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1 = 0, + /// SMBus host header (Slave mode) + SMBHOST: u1 = 0, + /// Dual flag (Slave mode) + DUALF: u1 = 0, + /// acket error checking register + PEC: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11964,13 +14833,17 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Clock control register + + /// Clock control register pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - CCR: u12, // bit offset: 0 desc: Clock control register in Fast/Standard mode (Master mode) + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DUTY: u1, // bit offset: 14 desc: Fast mode duty cycle - F_S: u1, // bit offset: 15 desc: I2C master mode selection + /// Fast mode duty cycle + DUTY: u1 = 0, + /// I2C master mode selection + F_S: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -11988,9 +14861,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 TRISE register + + /// TRISE register pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - TRISE: u6, // bit offset: 0 desc: Maximum rise time in Fast/Standard mode (Master mode) + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -12019,24 +14894,41 @@ pub const I2C2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI1 = extern struct { pub const Address: u32 = 0x40013000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12054,16 +14946,23 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12089,16 +14988,25 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12124,9 +15032,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12144,9 +15054,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12164,9 +15076,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12184,9 +15098,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12204,17 +15120,26 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12236,11 +15161,15 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12265,24 +15194,41 @@ pub const SPI1 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI2 = extern struct { pub const Address: u32 = 0x40003800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12300,16 +15246,23 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12335,16 +15288,25 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12370,9 +15332,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12390,9 +15354,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12410,9 +15376,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12430,9 +15398,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12450,17 +15420,26 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12482,11 +15461,15 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12511,24 +15494,41 @@ pub const SPI2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface pub const SPI3 = extern struct { pub const Address: u32 = 0x40003c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - DFF: u1, // bit offset: 11 desc: Data frame format - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// Data frame format + DFF: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12546,16 +15546,23 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12581,16 +15588,25 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -12616,9 +15632,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12636,9 +15654,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12656,9 +15676,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12676,9 +15698,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12696,17 +15720,26 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -12728,11 +15761,15 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12757,20 +15794,33 @@ pub const SPI3 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART1 = extern struct { pub const Address: u32 = 0x40013800; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -12794,9 +15844,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -12821,10 +15873,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12842,22 +15897,37 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -12877,19 +15947,29 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -12908,19 +15988,31 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -12943,10 +16035,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -12965,20 +16060,33 @@ pub const USART1 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART2 = extern struct { pub const Address: u32 = 0x40004400; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -13002,9 +16110,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13029,10 +16139,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13050,22 +16163,37 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13085,19 +16213,29 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13116,19 +16254,31 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -13151,10 +16301,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13173,20 +16326,33 @@ pub const USART2 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART3 = extern struct { pub const Address: u32 = 0x40004800; - // byte offset: 0 Status register + + /// Status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag - CTS: u1, // bit offset: 9 desc: CTS flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, + /// CTS flag + CTS: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -13210,9 +16376,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Data register + + /// Data register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: Data value + /// Data value + DR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -13237,10 +16405,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13258,22 +16429,37 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13293,19 +16479,29 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved2: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -13324,19 +16520,31 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Control register 3 + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -13359,10 +16567,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13381,15 +16592,23 @@ pub const USART3 = extern struct { padding1: u1 = 0, }); }; + +/// Analog to digital converter pub const ADC1 = extern struct { pub const Address: u32 = 0x40012400; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -13418,23 +16637,37 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count - DUALMOD: u4, // bit offset: 16 desc: Dual mode selection + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, + /// Dual mode selection + DUALMOD: u4 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13444,28 +16677,42 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13475,16 +16722,25 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13494,24 +16750,37 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13533,9 +16802,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13557,9 +16828,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13581,9 +16854,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13605,9 +16880,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13629,9 +16906,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13653,13 +16932,19 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13669,35 +16954,55 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -13709,9 +17014,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13729,9 +17036,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13749,9 +17058,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13769,9 +17080,11 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13789,21 +17102,32 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data - ADC2DATA: u16, // bit offset: 16 desc: ADC2 data + /// Regular data + DATA: u16 = 0, + /// ADC2 data + ADC2DATA: u16 = 0, }); }; + +/// Analog to digital converter pub const ADC2 = extern struct { pub const Address: u32 = 0x40012800; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -13832,26 +17156,39 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13861,28 +17198,42 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13892,16 +17243,25 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13911,24 +17271,37 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13950,9 +17323,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13974,9 +17349,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -13998,9 +17375,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14022,9 +17401,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14046,9 +17427,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14070,13 +17453,19 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14086,35 +17475,55 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -14126,9 +17535,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14146,9 +17557,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14166,9 +17579,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14186,9 +17601,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14206,9 +17623,11 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data + /// Regular data + DATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14227,15 +17646,23 @@ pub const ADC2 = extern struct { padding1: u1 = 0, }); }; + +/// Analog to digital converter pub const ADC3 = extern struct { pub const Address: u32 = 0x40013c00; - // byte offset: 0 status register + + /// status register pub const SR = mmio(Address + 0x00000000, 32, packed struct { - AWD: u1, // bit offset: 0 desc: Analog watchdog flag - EOC: u1, // bit offset: 1 desc: Regular channel end of conversion - JEOC: u1, // bit offset: 2 desc: Injected channel end of conversion - JSTRT: u1, // bit offset: 3 desc: Injected channel start flag - STRT: u1, // bit offset: 4 desc: Regular channel start flag + /// Analog watchdog flag + AWD: u1 = 0, + /// Regular channel end of conversion + EOC: u1 = 0, + /// Injected channel end of conversion + JEOC: u1 = 0, + /// Injected channel start flag + JSTRT: u1 = 0, + /// Regular channel start flag + STRT: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -14264,26 +17691,39 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - AWDCH: u5, // bit offset: 0 desc: Analog watchdog channel select bits - EOCIE: u1, // bit offset: 5 desc: Interrupt enable for EOC - AWDIE: u1, // bit offset: 6 desc: Analog watchdog interrupt enable - JEOCIE: u1, // bit offset: 7 desc: Interrupt enable for injected channels - SCAN: u1, // bit offset: 8 desc: Scan mode - AWDSGL: u1, // bit offset: 9 desc: Enable the watchdog on a single channel in scan mode - JAUTO: u1, // bit offset: 10 desc: Automatic injected group conversion - DISCEN: u1, // bit offset: 11 desc: Discontinuous mode on regular channels - JDISCEN: u1, // bit offset: 12 desc: Discontinuous mode on injected channels - DISCNUM: u3, // bit offset: 13 desc: Discontinuous mode channel count + /// Analog watchdog channel select bits + AWDCH: u5 = 0, + /// Interrupt enable for EOC + EOCIE: u1 = 0, + /// Analog watchdog interrupt enable + AWDIE: u1 = 0, + /// Interrupt enable for injected channels + JEOCIE: u1 = 0, + /// Scan mode + SCAN: u1 = 0, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1 = 0, + /// Automatic injected group conversion + JAUTO: u1 = 0, + /// Discontinuous mode on regular channels + DISCEN: u1 = 0, + /// Discontinuous mode on injected channels + JDISCEN: u1 = 0, + /// Discontinuous mode channel count + DISCNUM: u3 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - JAWDEN: u1, // bit offset: 22 desc: Analog watchdog enable on injected channels - AWDEN: u1, // bit offset: 23 desc: Analog watchdog enable on regular channels + /// Analog watchdog enable on injected channels + JAWDEN: u1 = 0, + /// Analog watchdog enable on regular channels + AWDEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14293,28 +17733,42 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - ADON: u1, // bit offset: 0 desc: A/D converter ON / OFF - CONT: u1, // bit offset: 1 desc: Continuous conversion - CAL: u1, // bit offset: 2 desc: A/D calibration - RSTCAL: u1, // bit offset: 3 desc: Reset calibration + /// A/D converter ON / OFF + ADON: u1 = 0, + /// Continuous conversion + CONT: u1 = 0, + /// A/D calibration + CAL: u1 = 0, + /// Reset calibration + RSTCAL: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMA: u1, // bit offset: 8 desc: Direct memory access mode + /// Direct memory access mode + DMA: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - ALIGN: u1, // bit offset: 11 desc: Data alignment - JEXTSEL: u3, // bit offset: 12 desc: External event select for injected group - JEXTTRIG: u1, // bit offset: 15 desc: External trigger conversion mode for injected channels + /// Data alignment + ALIGN: u1 = 0, + /// External event select for injected group + JEXTSEL: u3 = 0, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1 = 0, reserved7: u1 = 0, - EXTSEL: u3, // bit offset: 17 desc: External event select for regular group - EXTTRIG: u1, // bit offset: 20 desc: External trigger conversion mode for regular channels - JSWSTART: u1, // bit offset: 21 desc: Start conversion of injected channels - SWSTART: u1, // bit offset: 22 desc: Start conversion of regular channels - TSVREFE: u1, // bit offset: 23 desc: Temperature sensor and VREFINT enable + /// External event select for regular group + EXTSEL: u3 = 0, + /// External trigger conversion mode for regular channels + EXTTRIG: u1 = 0, + /// Start conversion of injected channels + JSWSTART: u1 = 0, + /// Start conversion of regular channels + SWSTART: u1 = 0, + /// Temperature sensor and VREFINT enable + TSVREFE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14324,16 +17778,25 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 sample time register 1 + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: Channel 10 sample time selection - SMP11: u3, // bit offset: 3 desc: Channel 11 sample time selection - SMP12: u3, // bit offset: 6 desc: Channel 12 sample time selection - SMP13: u3, // bit offset: 9 desc: Channel 13 sample time selection - SMP14: u3, // bit offset: 12 desc: Channel 14 sample time selection - SMP15: u3, // bit offset: 15 desc: Channel 15 sample time selection - SMP16: u3, // bit offset: 18 desc: Channel 16 sample time selection - SMP17: u3, // bit offset: 21 desc: Channel 17 sample time selection + /// Channel 10 sample time selection + SMP10: u3 = 0, + /// Channel 11 sample time selection + SMP11: u3 = 0, + /// Channel 12 sample time selection + SMP12: u3 = 0, + /// Channel 13 sample time selection + SMP13: u3 = 0, + /// Channel 14 sample time selection + SMP14: u3 = 0, + /// Channel 15 sample time selection + SMP15: u3 = 0, + /// Channel 16 sample time selection + SMP16: u3 = 0, + /// Channel 17 sample time selection + SMP17: u3 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14343,24 +17806,37 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - SMP0: u3, // bit offset: 0 desc: Channel 0 sample time selection - SMP1: u3, // bit offset: 3 desc: Channel 1 sample time selection - SMP2: u3, // bit offset: 6 desc: Channel 2 sample time selection - SMP3: u3, // bit offset: 9 desc: Channel 3 sample time selection - SMP4: u3, // bit offset: 12 desc: Channel 4 sample time selection - SMP5: u3, // bit offset: 15 desc: Channel 5 sample time selection - SMP6: u3, // bit offset: 18 desc: Channel 6 sample time selection - SMP7: u3, // bit offset: 21 desc: Channel 7 sample time selection - SMP8: u3, // bit offset: 24 desc: Channel 8 sample time selection - SMP9: u3, // bit offset: 27 desc: Channel 9 sample time selection + /// Channel 0 sample time selection + SMP0: u3 = 0, + /// Channel 1 sample time selection + SMP1: u3 = 0, + /// Channel 2 sample time selection + SMP2: u3 = 0, + /// Channel 3 sample time selection + SMP3: u3 = 0, + /// Channel 4 sample time selection + SMP4: u3 = 0, + /// Channel 5 sample time selection + SMP5: u3 = 0, + /// Channel 6 sample time selection + SMP6: u3 = 0, + /// Channel 7 sample time selection + SMP7: u3 = 0, + /// Channel 8 sample time selection + SMP8: u3 = 0, + /// Channel 9 sample time selection + SMP9: u3 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - JOFFSET1: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET1: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14382,9 +17858,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - JOFFSET2: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET2: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14406,9 +17884,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - JOFFSET3: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET3: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14430,9 +17910,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 injected channel data offset register x + + /// injected channel data offset register x pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - JOFFSET4: u12, // bit offset: 0 desc: Data offset for injected channel x + /// Data offset for injected channel x + JOFFSET4: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14454,9 +17936,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog higher threshold register + + /// watchdog higher threshold register pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - HT: u12, // bit offset: 0 desc: Analog watchdog higher threshold + /// Analog watchdog higher threshold + HT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14478,9 +17962,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog lower threshold register + + /// watchdog lower threshold register pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - LT: u12, // bit offset: 0 desc: Analog watchdog lower threshold + /// Analog watchdog lower threshold + LT: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14502,13 +17988,19 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - SQ13: u5, // bit offset: 0 desc: 13th conversion in regular sequence - SQ14: u5, // bit offset: 5 desc: 14th conversion in regular sequence - SQ15: u5, // bit offset: 10 desc: 15th conversion in regular sequence - SQ16: u5, // bit offset: 15 desc: 16th conversion in regular sequence - L: u4, // bit offset: 20 desc: Regular channel sequence length + /// 13th conversion in regular sequence + SQ13: u5 = 0, + /// 14th conversion in regular sequence + SQ14: u5 = 0, + /// 15th conversion in regular sequence + SQ15: u5 = 0, + /// 16th conversion in regular sequence + SQ16: u5 = 0, + /// Regular channel sequence length + L: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14518,35 +18010,55 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - SQ7: u5, // bit offset: 0 desc: 7th conversion in regular sequence - SQ8: u5, // bit offset: 5 desc: 8th conversion in regular sequence - SQ9: u5, // bit offset: 10 desc: 9th conversion in regular sequence - SQ10: u5, // bit offset: 15 desc: 10th conversion in regular sequence - SQ11: u5, // bit offset: 20 desc: 11th conversion in regular sequence - SQ12: u5, // bit offset: 25 desc: 12th conversion in regular sequence + /// 7th conversion in regular sequence + SQ7: u5 = 0, + /// 8th conversion in regular sequence + SQ8: u5 = 0, + /// 9th conversion in regular sequence + SQ9: u5 = 0, + /// 10th conversion in regular sequence + SQ10: u5 = 0, + /// 11th conversion in regular sequence + SQ11: u5 = 0, + /// 12th conversion in regular sequence + SQ12: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - SQ1: u5, // bit offset: 0 desc: 1st conversion in regular sequence - SQ2: u5, // bit offset: 5 desc: 2nd conversion in regular sequence - SQ3: u5, // bit offset: 10 desc: 3rd conversion in regular sequence - SQ4: u5, // bit offset: 15 desc: 4th conversion in regular sequence - SQ5: u5, // bit offset: 20 desc: 5th conversion in regular sequence - SQ6: u5, // bit offset: 25 desc: 6th conversion in regular sequence + /// 1st conversion in regular sequence + SQ1: u5 = 0, + /// 2nd conversion in regular sequence + SQ2: u5 = 0, + /// 3rd conversion in regular sequence + SQ3: u5 = 0, + /// 4th conversion in regular sequence + SQ4: u5 = 0, + /// 5th conversion in regular sequence + SQ5: u5 = 0, + /// 6th conversion in regular sequence + SQ6: u5 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - JSQ1: u5, // bit offset: 0 desc: 1st conversion in injected sequence - JSQ2: u5, // bit offset: 5 desc: 2nd conversion in injected sequence - JSQ3: u5, // bit offset: 10 desc: 3rd conversion in injected sequence - JSQ4: u5, // bit offset: 15 desc: 4th conversion in injected sequence - JL: u2, // bit offset: 20 desc: Injected sequence length + /// 1st conversion in injected sequence + JSQ1: u5 = 0, + /// 2nd conversion in injected sequence + JSQ2: u5 = 0, + /// 3rd conversion in injected sequence + JSQ3: u5 = 0, + /// 4th conversion in injected sequence + JSQ4: u5 = 0, + /// Injected sequence length + JL: u2 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -14558,9 +18070,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 injected data register x + + /// injected data register x pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14578,9 +18092,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 injected data register x + + /// injected data register x pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14598,9 +18114,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 injected data register x + + /// injected data register x pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14618,9 +18136,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 injected data register x + + /// injected data register x pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - JDATA: u16, // bit offset: 0 desc: Injected data + /// Injected data + JDATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14638,9 +18158,11 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 regular data register + + /// regular data register pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Regular data + /// Regular data + DATA: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14659,18 +18181,13 @@ pub const ADC3 = extern struct { padding1: u1 = 0, }); }; + +/// Controller area network pub const CAN = extern struct { pub const Address: u32 = 0x40006400; - // byte offset: 0 CAN_MCR + + /// CAN_MCR pub const CAN_MCR = mmio(Address + 0x00000000, 32, packed struct { - INRQ: u1, // bit offset: 0 desc: INRQ - SLEEP: u1, // bit offset: 1 desc: SLEEP - TXFP: u1, // bit offset: 2 desc: TXFP - RFLM: u1, // bit offset: 3 desc: RFLM - NART: u1, // bit offset: 4 desc: NART - AWUM: u1, // bit offset: 5 desc: AWUM - ABOM: u1, // bit offset: 6 desc: ABOM - TTCM: u1, // bit offset: 7 desc: TTCM reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -14678,8 +18195,6 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESET: u1, // bit offset: 15 desc: RESET - DBF: u1, // bit offset: 16 desc: DBF padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14696,20 +18211,12 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 CAN_MSR + + /// CAN_MSR pub const CAN_MSR = mmio(Address + 0x00000004, 32, packed struct { - INAK: u1, // bit offset: 0 desc: INAK - SLAK: u1, // bit offset: 1 desc: SLAK - ERRI: u1, // bit offset: 2 desc: ERRI - WKUI: u1, // bit offset: 3 desc: WKUI - SLAKI: u1, // bit offset: 4 desc: SLAKI reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXM: u1, // bit offset: 8 desc: TXM - RXM: u1, // bit offset: 9 desc: RXM - SAMP: u1, // bit offset: 10 desc: SAMP - RX: u1, // bit offset: 11 desc: RX padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14731,47 +18238,35 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 CAN_TSR + + /// CAN_TSR pub const CAN_TSR = mmio(Address + 0x00000008, 32, packed struct { - RQCP0: u1, // bit offset: 0 desc: RQCP0 - TXOK0: u1, // bit offset: 1 desc: TXOK0 - ALST0: u1, // bit offset: 2 desc: ALST0 - TERR0: u1, // bit offset: 3 desc: TERR0 reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABRQ0: u1, // bit offset: 7 desc: ABRQ0 - RQCP1: u1, // bit offset: 8 desc: RQCP1 - TXOK1: u1, // bit offset: 9 desc: TXOK1 - ALST1: u1, // bit offset: 10 desc: ALST1 - TERR1: u1, // bit offset: 11 desc: TERR1 reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - ABRQ1: u1, // bit offset: 15 desc: ABRQ1 - RQCP2: u1, // bit offset: 16 desc: RQCP2 - TXOK2: u1, // bit offset: 17 desc: TXOK2 - ALST2: u1, // bit offset: 18 desc: ALST2 - TERR2: u1, // bit offset: 19 desc: TERR2 reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - ABRQ2: u1, // bit offset: 23 desc: ABRQ2 - CODE: u2, // bit offset: 24 desc: CODE - TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 - TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 - TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 - LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 - LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 - LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 - }); - // byte offset: 12 CAN_RF0R + /// Lowest priority flag for mailbox 0 + TME0: u1 = 0, + /// Lowest priority flag for mailbox 1 + TME1: u1 = 0, + /// Lowest priority flag for mailbox 2 + TME2: u1 = 0, + /// Lowest priority flag for mailbox 0 + LOW0: u1 = 0, + /// Lowest priority flag for mailbox 1 + LOW1: u1 = 0, + /// Lowest priority flag for mailbox 2 + LOW2: u1 = 0, + }); + + /// CAN_RF0R pub const CAN_RF0R = mmio(Address + 0x0000000c, 32, packed struct { - FMP0: u2, // bit offset: 0 desc: FMP0 reserved1: u1 = 0, - FULL0: u1, // bit offset: 3 desc: FULL0 - FOVR0: u1, // bit offset: 4 desc: FOVR0 - RFOM0: u1, // bit offset: 5 desc: RFOM0 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -14799,13 +18294,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CAN_RF1R + + /// CAN_RF1R pub const CAN_RF1R = mmio(Address + 0x00000010, 32, packed struct { - FMP1: u2, // bit offset: 0 desc: FMP1 reserved1: u1 = 0, - FULL1: u1, // bit offset: 3 desc: FULL1 - FOVR1: u1, // bit offset: 4 desc: FOVR1 - RFOM1: u1, // bit offset: 5 desc: RFOM1 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -14833,26 +18325,13 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 CAN_IER + + /// CAN_IER pub const CAN_IER = mmio(Address + 0x00000014, 32, packed struct { - TMEIE: u1, // bit offset: 0 desc: TMEIE - FMPIE0: u1, // bit offset: 1 desc: FMPIE0 - FFIE0: u1, // bit offset: 2 desc: FFIE0 - FOVIE0: u1, // bit offset: 3 desc: FOVIE0 - FMPIE1: u1, // bit offset: 4 desc: FMPIE1 - FFIE1: u1, // bit offset: 5 desc: FFIE1 - FOVIE1: u1, // bit offset: 6 desc: FOVIE1 reserved1: u1 = 0, - EWGIE: u1, // bit offset: 8 desc: EWGIE - EPVIE: u1, // bit offset: 9 desc: EPVIE - BOFIE: u1, // bit offset: 10 desc: BOFIE - LECIE: u1, // bit offset: 11 desc: LECIE reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - ERRIE: u1, // bit offset: 15 desc: ERRIE - WKUIE: u1, // bit offset: 16 desc: WKUIE - SLKIE: u1, // bit offset: 17 desc: SLKIE padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -14868,13 +18347,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 CAN_ESR + + /// CAN_ESR pub const CAN_ESR = mmio(Address + 0x00000018, 32, packed struct { - EWGF: u1, // bit offset: 0 desc: EWGF - EPVF: u1, // bit offset: 1 desc: EPVF - BOFF: u1, // bit offset: 2 desc: BOFF reserved1: u1 = 0, - LEC: u3, // bit offset: 4 desc: LEC reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -14884,45 +18360,32 @@ pub const CAN = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TEC: u8, // bit offset: 16 desc: TEC - REC: u8, // bit offset: 24 desc: REC }); - // byte offset: 28 CAN_BTR + + /// CAN_BTR pub const CAN_BTR = mmio(Address + 0x0000001c, 32, packed struct { - BRP: u10, // bit offset: 0 desc: BRP reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TS1: u4, // bit offset: 16 desc: TS1 - TS2: u3, // bit offset: 20 desc: TS2 reserved7: u1 = 0, - SJW: u2, // bit offset: 24 desc: SJW reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - LBKM: u1, // bit offset: 30 desc: LBKM - SILM: u1, // bit offset: 31 desc: SILM - }); - // byte offset: 384 CAN_TI0R - pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 388 CAN_TDT0R + }); + + /// CAN_TI0R + pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct {}); + + /// CAN_TDT0R pub const CAN_TDT0R = mmio(Address + 0x00000184, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -14930,38 +18393,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 392 CAN_TDL0R - pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 396 CAN_TDH0R - pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 400 CAN_TI1R - pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 404 CAN_TDT1R + }); + + /// CAN_TDL0R + pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); + + /// CAN_TDH0R + pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); + + /// CAN_TI1R + pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct {}); + + /// CAN_TDT1R pub const CAN_TDT1R = mmio(Address + 0x00000194, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -14969,38 +18417,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 408 CAN_TDL1R - pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 412 CAN_TDH1R - pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 416 CAN_TI2R - pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 420 CAN_TDT2R + }); + + /// CAN_TDL1R + pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); + + /// CAN_TDH1R + pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); + + /// CAN_TI2R + pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); + + /// CAN_TDT2R pub const CAN_TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -15008,89 +18441,54 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 424 CAN_TDL2R - pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 428 CAN_TDH2R - pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 432 CAN_RI0R + }); + + /// CAN_TDL2R + pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); + + /// CAN_TDH2R + pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); + + /// CAN_RI0R pub const CAN_RI0R = mmio(Address + 0x000001b0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 436 CAN_RDT0R + + /// CAN_RDT0R pub const CAN_RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 440 CAN_RDL0R - pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 444 CAN_RDH0R - pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 448 CAN_RI1R + }); + + /// CAN_RDL0R + pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); + + /// CAN_RDH0R + pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); + + /// CAN_RI1R pub const CAN_RI1R = mmio(Address + 0x000001c0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 452 CAN_RDT1R + + /// CAN_RDT1R pub const CAN_RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 456 CAN_RDL1R - pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 460 CAN_RDH1R - pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 512 CAN_FMR + }); + + /// CAN_RDL1R + pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); + + /// CAN_RDH1R + pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); + + /// CAN_FMR pub const CAN_FMR = mmio(Address + 0x00000200, 32, packed struct { - FINIT: u1, // bit offset: 0 desc: FINIT padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15123,22 +18521,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 516 CAN_FM1R + + /// CAN_FM1R pub const CAN_FM1R = mmio(Address + 0x00000204, 32, packed struct { - FBM0: u1, // bit offset: 0 desc: Filter mode - FBM1: u1, // bit offset: 1 desc: Filter mode - FBM2: u1, // bit offset: 2 desc: Filter mode - FBM3: u1, // bit offset: 3 desc: Filter mode - FBM4: u1, // bit offset: 4 desc: Filter mode - FBM5: u1, // bit offset: 5 desc: Filter mode - FBM6: u1, // bit offset: 6 desc: Filter mode - FBM7: u1, // bit offset: 7 desc: Filter mode - FBM8: u1, // bit offset: 8 desc: Filter mode - FBM9: u1, // bit offset: 9 desc: Filter mode - FBM10: u1, // bit offset: 10 desc: Filter mode - FBM11: u1, // bit offset: 11 desc: Filter mode - FBM12: u1, // bit offset: 12 desc: Filter mode - FBM13: u1, // bit offset: 13 desc: Filter mode + /// Filter mode + FBM0: u1 = 0, + /// Filter mode + FBM1: u1 = 0, + /// Filter mode + FBM2: u1 = 0, + /// Filter mode + FBM3: u1 = 0, + /// Filter mode + FBM4: u1 = 0, + /// Filter mode + FBM5: u1 = 0, + /// Filter mode + FBM6: u1 = 0, + /// Filter mode + FBM7: u1 = 0, + /// Filter mode + FBM8: u1 = 0, + /// Filter mode + FBM9: u1 = 0, + /// Filter mode + FBM10: u1 = 0, + /// Filter mode + FBM11: u1 = 0, + /// Filter mode + FBM12: u1 = 0, + /// Filter mode + FBM13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15158,22 +18571,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 524 CAN_FS1R + + /// CAN_FS1R pub const CAN_FS1R = mmio(Address + 0x0000020c, 32, packed struct { - FSC0: u1, // bit offset: 0 desc: Filter scale configuration - FSC1: u1, // bit offset: 1 desc: Filter scale configuration - FSC2: u1, // bit offset: 2 desc: Filter scale configuration - FSC3: u1, // bit offset: 3 desc: Filter scale configuration - FSC4: u1, // bit offset: 4 desc: Filter scale configuration - FSC5: u1, // bit offset: 5 desc: Filter scale configuration - FSC6: u1, // bit offset: 6 desc: Filter scale configuration - FSC7: u1, // bit offset: 7 desc: Filter scale configuration - FSC8: u1, // bit offset: 8 desc: Filter scale configuration - FSC9: u1, // bit offset: 9 desc: Filter scale configuration - FSC10: u1, // bit offset: 10 desc: Filter scale configuration - FSC11: u1, // bit offset: 11 desc: Filter scale configuration - FSC12: u1, // bit offset: 12 desc: Filter scale configuration - FSC13: u1, // bit offset: 13 desc: Filter scale configuration + /// Filter scale configuration + FSC0: u1 = 0, + /// Filter scale configuration + FSC1: u1 = 0, + /// Filter scale configuration + FSC2: u1 = 0, + /// Filter scale configuration + FSC3: u1 = 0, + /// Filter scale configuration + FSC4: u1 = 0, + /// Filter scale configuration + FSC5: u1 = 0, + /// Filter scale configuration + FSC6: u1 = 0, + /// Filter scale configuration + FSC7: u1 = 0, + /// Filter scale configuration + FSC8: u1 = 0, + /// Filter scale configuration + FSC9: u1 = 0, + /// Filter scale configuration + FSC10: u1 = 0, + /// Filter scale configuration + FSC11: u1 = 0, + /// Filter scale configuration + FSC12: u1 = 0, + /// Filter scale configuration + FSC13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15193,22 +18621,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 532 CAN_FFA1R + + /// CAN_FFA1R pub const CAN_FFA1R = mmio(Address + 0x00000214, 32, packed struct { - FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 - FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 - FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 - FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 - FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 - FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 - FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 - FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 - FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 - FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 - FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 - FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 - FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 - FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 + /// Filter FIFO assignment for filter 0 + FFA0: u1 = 0, + /// Filter FIFO assignment for filter 1 + FFA1: u1 = 0, + /// Filter FIFO assignment for filter 2 + FFA2: u1 = 0, + /// Filter FIFO assignment for filter 3 + FFA3: u1 = 0, + /// Filter FIFO assignment for filter 4 + FFA4: u1 = 0, + /// Filter FIFO assignment for filter 5 + FFA5: u1 = 0, + /// Filter FIFO assignment for filter 6 + FFA6: u1 = 0, + /// Filter FIFO assignment for filter 7 + FFA7: u1 = 0, + /// Filter FIFO assignment for filter 8 + FFA8: u1 = 0, + /// Filter FIFO assignment for filter 9 + FFA9: u1 = 0, + /// Filter FIFO assignment for filter 10 + FFA10: u1 = 0, + /// Filter FIFO assignment for filter 11 + FFA11: u1 = 0, + /// Filter FIFO assignment for filter 12 + FFA12: u1 = 0, + /// Filter FIFO assignment for filter 13 + FFA13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15228,22 +18671,37 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 540 CAN_FA1R + + /// CAN_FA1R pub const CAN_FA1R = mmio(Address + 0x0000021c, 32, packed struct { - FACT0: u1, // bit offset: 0 desc: Filter active - FACT1: u1, // bit offset: 1 desc: Filter active - FACT2: u1, // bit offset: 2 desc: Filter active - FACT3: u1, // bit offset: 3 desc: Filter active - FACT4: u1, // bit offset: 4 desc: Filter active - FACT5: u1, // bit offset: 5 desc: Filter active - FACT6: u1, // bit offset: 6 desc: Filter active - FACT7: u1, // bit offset: 7 desc: Filter active - FACT8: u1, // bit offset: 8 desc: Filter active - FACT9: u1, // bit offset: 9 desc: Filter active - FACT10: u1, // bit offset: 10 desc: Filter active - FACT11: u1, // bit offset: 11 desc: Filter active - FACT12: u1, // bit offset: 12 desc: Filter active - FACT13: u1, // bit offset: 13 desc: Filter active + /// Filter active + FACT0: u1 = 0, + /// Filter active + FACT1: u1 = 0, + /// Filter active + FACT2: u1 = 0, + /// Filter active + FACT3: u1 = 0, + /// Filter active + FACT4: u1 = 0, + /// Filter active + FACT5: u1 = 0, + /// Filter active + FACT6: u1 = 0, + /// Filter active + FACT7: u1 = 0, + /// Filter active + FACT8: u1 = 0, + /// Filter active + FACT9: u1 = 0, + /// Filter active + FACT10: u1 = 0, + /// Filter active + FACT11: u1 = 0, + /// Filter active + FACT12: u1 = 0, + /// Filter active + FACT13: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -15263,1016 +18721,1960 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 576 Filter bank 0 register 1 + + /// Filter bank 0 register 1 pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 580 Filter bank 0 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 0 register 2 pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 584 Filter bank 1 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 1 pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 588 Filter bank 1 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 2 pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 592 Filter bank 2 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 1 pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 596 Filter bank 2 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 2 pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 600 Filter bank 3 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 1 pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 604 Filter bank 3 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 2 pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 608 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 612 Filter bank 4 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 2 pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 616 Filter bank 5 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 1 pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 620 Filter bank 5 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 2 pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 624 Filter bank 6 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 1 pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 628 Filter bank 6 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 2 pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 632 Filter bank 7 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 1 pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 636 Filter bank 7 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 2 pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 640 Filter bank 8 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 1 pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 644 Filter bank 8 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 2 pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 648 Filter bank 9 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 1 pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 652 Filter bank 9 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 2 pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 656 Filter bank 10 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 1 pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 660 Filter bank 10 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 2 pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 664 Filter bank 11 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 1 pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 668 Filter bank 11 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 2 pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 672 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 676 Filter bank 12 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 12 register 2 pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 680 Filter bank 13 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 1 pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 684 Filter bank 13 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 2 pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, }); }; + +/// Digital to analog converter pub const DAC = extern struct { pub const Address: u32 = 0x40007400; - // byte offset: 0 Control register (DAC_CR) + + /// Control register (DAC_CR) pub const CR = mmio(Address + 0x00000000, 32, packed struct { - EN1: u1, // bit offset: 0 desc: DAC channel1 enable - BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable - TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable - TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection - WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable - MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector - DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable + /// DAC channel1 enable + EN1: u1 = 0, + /// DAC channel1 output buffer disable + BOFF1: u1 = 0, + /// DAC channel1 trigger enable + TEN1: u1 = 0, + /// DAC channel1 trigger selection + TSEL1: u3 = 0, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2 = 0, + /// DAC channel1 mask/amplitude selector + MAMP1: u4 = 0, + /// DAC channel1 DMA enable + DMAEN1: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EN2: u1, // bit offset: 16 desc: DAC channel2 enable - BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable - TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable - TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection - WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable - MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector - DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable + /// DAC channel2 enable + EN2: u1 = 0, + /// DAC channel2 output buffer disable + BOFF2: u1 = 0, + /// DAC channel2 trigger enable + TEN2: u1 = 0, + /// DAC channel2 trigger selection + TSEL2: u3 = 0, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2 = 0, + /// DAC channel2 mask/amplitude selector + MAMP2: u4 = 0, + /// DAC channel2 DMA enable + DMAEN2: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 DAC software trigger register (DAC_SWTRIGR) + + /// DAC software trigger register (DAC_SWTRIGR) pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger - SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + /// DAC channel1 software trigger + SWTRIG1: u1 = 0, + /// DAC channel2 software trigger + SWTRIG2: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -16304,9 +20706,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) + + /// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16328,13 +20732,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) + + /// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16352,9 +20758,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) + + /// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16380,9 +20788,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) + + /// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16404,13 +20814,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) + + /// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16428,9 +20840,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) + + /// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16456,36 +20870,48 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved + + /// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits + /// 31:28 Reserved, Bits 15:12 Reserved pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved + + /// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 + /// Reserved, Bits 3:0 Reserved pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, }); - // byte offset: 40 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved + + /// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 + /// Reserved pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16503,9 +20929,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 DAC channel1 data output register (DAC_DOR1) + + /// DAC channel1 data output register (DAC_DOR1) pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + /// DAC channel1 data output + DACC1DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16527,9 +20955,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 DAC channel2 data output register (DAC_DOR2) + + /// DAC channel2 data output register (DAC_DOR2) pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + /// DAC channel2 data output + DACC2DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16552,40 +20982,23 @@ pub const DAC = extern struct { padding1: u1 = 0, }); }; + +/// Debug support pub const DBG = extern struct { pub const Address: u32 = 0xe0042000; - // byte offset: 0 DBGMCU_IDCODE + + /// DBGMCU_IDCODE pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - DEV_ID: u12, // bit offset: 0 desc: DEV_ID reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - REV_ID: u16, // bit offset: 16 desc: REV_ID }); - // byte offset: 4 DBGMCU_CR + + /// DBGMCU_CR pub const CR = mmio(Address + 0x00000004, 32, packed struct { - DBG_SLEEP: u1, // bit offset: 0 desc: DBG_SLEEP - DBG_STOP: u1, // bit offset: 1 desc: DBG_STOP - DBG_STANDBY: u1, // bit offset: 2 desc: DBG_STANDBY reserved2: u1 = 0, reserved1: u1 = 0, - TRACE_IOEN: u1, // bit offset: 5 desc: TRACE_IOEN - TRACE_MODE: u2, // bit offset: 6 desc: TRACE_MODE - DBG_IWDG_STOP: u1, // bit offset: 8 desc: DBG_IWDG_STOP - DBG_WWDG_STOP: u1, // bit offset: 9 desc: DBG_WWDG_STOP - DBG_TIM1_STOP: u1, // bit offset: 10 desc: DBG_TIM1_STOP - DBG_TIM2_STOP: u1, // bit offset: 11 desc: DBG_TIM2_STOP - DBG_TIM3_STOP: u1, // bit offset: 12 desc: DBG_TIM3_STOP - DBG_TIM4_STOP: u1, // bit offset: 13 desc: DBG_TIM4_STOP - DBG_CAN1_STOP: u1, // bit offset: 14 desc: DBG_CAN1_STOP - DBG_I2C1_SMBUS_TIMEOUT: u1, // bit offset: 15 desc: DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, // bit offset: 16 desc: DBG_I2C2_SMBUS_TIMEOUT - DBG_TIM8_STOP: u1, // bit offset: 17 desc: DBG_TIM8_STOP - DBG_TIM5_STOP: u1, // bit offset: 18 desc: DBG_TIM5_STOP - DBG_TIM6_STOP: u1, // bit offset: 19 desc: DBG_TIM6_STOP - DBG_TIM7_STOP: u1, // bit offset: 20 desc: DBG_TIM7_STOP - DBG_CAN2_STOP: u1, // bit offset: 21 desc: DBG_CAN2_STOP padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -16598,19 +21011,31 @@ pub const DBG = extern struct { padding1: u1 = 0, }); }; + +/// Universal asynchronous receiver transmitter pub const UART4 = extern struct { pub const Address: u32 = 0x40004c00; - // byte offset: 0 UART4_SR + + /// UART4_SR pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NE: u1, // bit offset: 2 desc: Noise error flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: IDLE line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBD: u1, // bit offset: 8 desc: LIN break detection flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise error flag + NE: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// IDLE line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBD: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16635,9 +21060,9 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 UART4_DR + + /// UART4_DR pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: DR padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16662,10 +21087,9 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 UART4_BRR + + /// UART4_BRR pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction - DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16683,22 +21107,37 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 UART4_CR1 + + /// UART4_CR1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: Send break - RWU: u1, // bit offset: 1 desc: Receiver wakeup - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: TXE interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Wakeup method - M: u1, // bit offset: 12 desc: Word length - UE: u1, // bit offset: 13 desc: USART enable + /// Send break + SBK: u1 = 0, + /// Receiver wakeup + RWU: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// TXE interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// USART enable + UE: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -16718,19 +21157,25 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 UART4_CR2 + + /// UART4_CR2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: Address of the USART node + /// Address of the USART node + ADD: u4 = 0, reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: lin break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// lin break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16749,16 +21194,23 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 UART4_CR3 + + /// UART4_CR3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16785,19 +21237,13 @@ pub const UART4 = extern struct { padding1: u1 = 0, }); }; + +/// Universal asynchronous receiver transmitter pub const UART5 = extern struct { pub const Address: u32 = 0x40005000; - // byte offset: 0 UART4_SR + + /// UART4_SR pub const SR = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: PE - FE: u1, // bit offset: 1 desc: FE - NE: u1, // bit offset: 2 desc: NE - ORE: u1, // bit offset: 3 desc: ORE - IDLE: u1, // bit offset: 4 desc: IDLE - RXNE: u1, // bit offset: 5 desc: RXNE - TC: u1, // bit offset: 6 desc: TC - TXE: u1, // bit offset: 7 desc: TXE - LBD: u1, // bit offset: 8 desc: LBD padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16822,9 +21268,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 UART4_DR + + /// UART4_DR pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DR: u9, // bit offset: 0 desc: DR padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16849,10 +21295,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 UART4_BRR + + /// UART4_BRR pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: DIV_Fraction - DIV_Mantissa: u12, // bit offset: 4 desc: DIV_Mantissa padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16870,22 +21315,9 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 UART4_CR1 + + /// UART4_CR1 pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - SBK: u1, // bit offset: 0 desc: SBK - RWU: u1, // bit offset: 1 desc: RWU - RE: u1, // bit offset: 2 desc: RE - TE: u1, // bit offset: 3 desc: TE - IDLEIE: u1, // bit offset: 4 desc: IDLEIE - RXNEIE: u1, // bit offset: 5 desc: RXNEIE - TCIE: u1, // bit offset: 6 desc: TCIE - TXEIE: u1, // bit offset: 7 desc: TXEIE - PEIE: u1, // bit offset: 8 desc: PEIE - PS: u1, // bit offset: 9 desc: PS - PCE: u1, // bit offset: 10 desc: PCE - WAKE: u1, // bit offset: 11 desc: WAKE - M: u1, // bit offset: 12 desc: M - UE: u1, // bit offset: 13 desc: UE padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -16905,19 +21337,15 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 UART4_CR2 + + /// UART4_CR2 pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - ADD: u4, // bit offset: 0 desc: ADD reserved1: u1 = 0, - LBDL: u1, // bit offset: 5 desc: LBDL - LBDIE: u1, // bit offset: 6 desc: LBDIE reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - STOP: u2, // bit offset: 12 desc: STOP - LINEN: u1, // bit offset: 14 desc: LINEN padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16936,16 +21364,22 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 UART4_CR3 + + /// UART4_CR3 pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter + /// DMA enable transmitter + DMAT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16972,15 +21406,18 @@ pub const UART5 = extern struct { padding1: u1 = 0, }); }; + +/// CRC calculation unit pub const CRC = extern struct { pub const Address: u32 = 0x40023000; - // byte offset: 0 Data register - pub const DR = mmio(Address + 0x00000000, 32, packed struct { - DR: u32, // bit offset: 0 desc: Data Register - }); - // byte offset: 4 Independent Data register + + /// Data register + pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Independent Data register pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - IDR: u8, // bit offset: 0 desc: Independent Data register + /// Independent Data register + IDR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -17006,9 +21443,11 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Control register + + /// Control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - RESET: u1, // bit offset: 0 desc: Reset bit + /// Reset bit + RESET: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -17042,14 +21481,21 @@ pub const CRC = extern struct { padding1: u1 = 0, }); }; + +/// FLASH pub const FLASH = extern struct { pub const Address: u32 = 0x40022000; - // byte offset: 0 Flash access control register + + /// Flash access control register pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - LATENCY: u3, // bit offset: 0 desc: Latency - HLFCYA: u1, // bit offset: 3 desc: Flash half cycle access enable - PRFTBE: u1, // bit offset: 4 desc: Prefetch buffer enable - PRFTBS: u1, // bit offset: 5 desc: Prefetch buffer status + /// Latency + LATENCY: u3 = 0, + /// Flash half cycle access enable + HLFCYA: u1 = 0, + /// Prefetch buffer enable + PRFTBE: u1 = 0, + /// Prefetch buffer status + PRFTBS: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -17077,22 +21523,31 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Flash key register + + /// Flash key register pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - KEY: u32, // bit offset: 0 desc: FPEC key + /// FPEC key + KEY: u32 = 0, }); - // byte offset: 8 Flash option key register + + /// Flash option key register pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - OPTKEY: u32, // bit offset: 0 desc: Option byte key + /// Option byte key + OPTKEY: u32 = 0, }); - // byte offset: 12 Status register + + /// Status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - BSY: u1, // bit offset: 0 desc: Busy + /// Busy + BSY: u1 = 0, reserved1: u1 = 0, - PGERR: u1, // bit offset: 2 desc: Programming error + /// Programming error + PGERR: u1 = 0, reserved2: u1 = 0, - WRPRTERR: u1, // bit offset: 4 desc: Write protection error - EOP: u1, // bit offset: 5 desc: End of operation + /// Write protection error + WRPRTERR: u1 = 0, + /// End of operation + EOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -17120,21 +21575,32 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Control register + + /// Control register pub const CR = mmio(Address + 0x00000010, 32, packed struct { - PG: u1, // bit offset: 0 desc: Programming - PER: u1, // bit offset: 1 desc: Page Erase - MER: u1, // bit offset: 2 desc: Mass Erase + /// Programming + PG: u1 = 0, + /// Page Erase + PER: u1 = 0, + /// Mass Erase + MER: u1 = 0, reserved1: u1 = 0, - OPTPG: u1, // bit offset: 4 desc: Option byte programming - OPTER: u1, // bit offset: 5 desc: Option byte erase - STRT: u1, // bit offset: 6 desc: Start - LOCK: u1, // bit offset: 7 desc: Lock + /// Option byte programming + OPTPG: u1 = 0, + /// Option byte erase + OPTER: u1 = 0, + /// Start + STRT: u1 = 0, + /// Lock + LOCK: u1 = 0, reserved2: u1 = 0, - OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable - ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + /// Option bytes write enable + OPTWRE: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, reserved3: u1 = 0, - EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable + /// End of operation interrupt enable + EOPIE: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17155,24 +21621,24 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Flash address register + + /// Flash address register pub const AR = mmio(Address + 0x00000014, 32, packed struct { - FAR: u32, // bit offset: 0 desc: Flash Address + /// Flash Address + FAR: u32 = 0, }); - // byte offset: 28 Option byte register + + /// Option byte register pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - OPTERR: u1, // bit offset: 0 desc: Option byte error - RDPRT: u1, // bit offset: 1 desc: Read protection - WDG_SW: u1, // bit offset: 2 desc: WDG_SW - nRST_STOP: u1, // bit offset: 3 desc: nRST_STOP - nRST_STDBY: u1, // bit offset: 4 desc: nRST_STDBY + /// Option byte error + OPTERR: u1 = 0, + /// Read protection + RDPRT: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - Data0: u8, // bit offset: 10 desc: Data0 - Data1: u8, // bit offset: 18 desc: Data1 padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17180,16 +21646,22 @@ pub const FLASH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Write protection register + + /// Write protection register pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - WRP: u32, // bit offset: 0 desc: Write protect + /// Write protect + WRP: u32 = 0, }); }; + +/// Nested Vectored Interrupt Controller pub const NVIC = extern struct { pub const Address: u32 = 0xe000e000; - // byte offset: 4 Interrupt Controller Type Register + + /// Interrupt Controller Type Register pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { - INTLINESNUM: u4, // bit offset: 0 desc: Total number of interrupt lines in groups + /// Total number of interrupt lines in groups + INTLINESNUM: u4 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -17219,154 +21691,86 @@ pub const NVIC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 256 Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 260 Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 384 Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 388 Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 512 Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 516 Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 640 Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 644 Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 768 Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 772 Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 1024 Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1028 Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1032 Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1036 Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1040 Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1044 Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1048 Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1052 Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1056 Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1060 Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1064 Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1068 Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1072 Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1076 Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 1080 Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 3840 Software Triggered Interrupt Register + + /// Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct {}); + + /// Software Triggered Interrupt Register pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { - INTID: u9, // bit offset: 0 desc: interrupt to be triggered + /// interrupt to be triggered + INTID: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -17392,20 +21796,33 @@ pub const NVIC = extern struct { padding1: u1 = 0, }); }; + +/// Universal serial bus full-speed device interface pub const USB = extern struct { pub const Address: u32 = 0x40005c00; - // byte offset: 0 endpoint 0 register + + /// endpoint 0 register pub const EP0R = mmio(Address + 0x00000000, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17423,18 +21840,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 endpoint 1 register + + /// endpoint 1 register pub const EP1R = mmio(Address + 0x00000004, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17452,18 +21880,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 endpoint 2 register + + /// endpoint 2 register pub const EP2R = mmio(Address + 0x00000008, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17481,18 +21920,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 endpoint 3 register + + /// endpoint 3 register pub const EP3R = mmio(Address + 0x0000000c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17510,18 +21960,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 endpoint 4 register + + /// endpoint 4 register pub const EP4R = mmio(Address + 0x00000010, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17539,18 +22000,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 endpoint 5 register + + /// endpoint 5 register pub const EP5R = mmio(Address + 0x00000014, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17568,18 +22040,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 endpoint 6 register + + /// endpoint 6 register pub const EP6R = mmio(Address + 0x00000018, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17597,18 +22080,29 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 endpoint 7 register + + /// endpoint 7 register pub const EP7R = mmio(Address + 0x0000001c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17626,24 +22120,38 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 control register + + /// control register pub const CNTR = mmio(Address + 0x00000040, 32, packed struct { - FRES: u1, // bit offset: 0 desc: Force USB Reset - PDWN: u1, // bit offset: 1 desc: Power down - LPMODE: u1, // bit offset: 2 desc: Low-power mode - FSUSP: u1, // bit offset: 3 desc: Force suspend - RESUME: u1, // bit offset: 4 desc: Resume request + /// Force USB Reset + FRES: u1 = 0, + /// Power down + PDWN: u1 = 0, + /// Low-power mode + LPMODE: u1 = 0, + /// Force suspend + FSUSP: u1 = 0, + /// Resume request + RESUME: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask - SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask - RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask - SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask - WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask - ERRM: u1, // bit offset: 13 desc: Error interrupt mask - PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask - CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + /// Expected start of frame interrupt mask + ESOFM: u1 = 0, + /// Start of frame interrupt mask + SOFM: u1 = 0, + /// USB reset interrupt mask + RESETM: u1 = 0, + /// Suspend mode interrupt mask + SUSPM: u1 = 0, + /// Wakeup interrupt mask + WKUPM: u1 = 0, + /// Error interrupt mask + ERRM: u1 = 0, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1 = 0, + /// Correct transfer interrupt mask + CTRM: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17661,21 +22169,32 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 interrupt status register + + /// interrupt status register pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier - DIR: u1, // bit offset: 4 desc: Direction of transaction + /// Endpoint Identifier + EP_ID: u4 = 0, + /// Direction of transaction + DIR: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOF: u1, // bit offset: 8 desc: Expected start frame - SOF: u1, // bit offset: 9 desc: start of frame - RESET: u1, // bit offset: 10 desc: reset request - SUSP: u1, // bit offset: 11 desc: Suspend mode request - WKUP: u1, // bit offset: 12 desc: Wakeup - ERR: u1, // bit offset: 13 desc: Error - PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun - CTR: u1, // bit offset: 15 desc: Correct transfer + /// Expected start frame + ESOF: u1 = 0, + /// start of frame + SOF: u1 = 0, + /// reset request + RESET: u1 = 0, + /// Suspend mode request + SUSP: u1 = 0, + /// Wakeup + WKUP: u1 = 0, + /// Error + ERR: u1 = 0, + /// Packet memory area over / underrun + PMAOVR: u1 = 0, + /// Correct transfer + CTR: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17693,13 +22212,19 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 frame number register + + /// frame number register pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - FN: u11, // bit offset: 0 desc: Frame number - LSOF: u2, // bit offset: 11 desc: Lost SOF - LCK: u1, // bit offset: 13 desc: Locked - RXDM: u1, // bit offset: 14 desc: Receive data - line status - RXDP: u1, // bit offset: 15 desc: Receive data + line status + /// Frame number + FN: u11 = 0, + /// Lost SOF + LSOF: u2 = 0, + /// Locked + LCK: u1 = 0, + /// Receive data - line status + RXDM: u1 = 0, + /// Receive data + line status + RXDP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17717,10 +22242,13 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 device address + + /// device address pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - ADD: u7, // bit offset: 0 desc: Device address - EF: u1, // bit offset: 7 desc: Enable function + /// Device address + ADD: u7 = 0, + /// Enable function + EF: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -17746,12 +22274,14 @@ pub const USB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Buffer table address + + /// Buffer table address pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BTABLE: u13, // bit offset: 3 desc: Buffer table + /// Buffer table + BTABLE: u13 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17810,181 +22340,122 @@ pub const VectorTable = extern struct { /// Window Watchdog interrupt WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper interrupt TAMPER: InterruptVector = makeUnhandledHandler("TAMPER"), - /// RTC global interrupt RTC: InterruptVector = makeUnhandledHandler("RTC"), - /// Flash global interrupt FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line1 interrupt EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 interrupt EXTI2: InterruptVector = makeUnhandledHandler("EXTI2"), - /// EXTI Line3 interrupt EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 Channel1 global interrupt DMA1_Channel1: InterruptVector = makeUnhandledHandler("DMA1_Channel1"), - /// DMA1 Channel2 global interrupt DMA1_Channel2: InterruptVector = makeUnhandledHandler("DMA1_Channel2"), - /// DMA1 Channel3 global interrupt DMA1_Channel3: InterruptVector = makeUnhandledHandler("DMA1_Channel3"), - /// DMA1 Channel4 global interrupt DMA1_Channel4: InterruptVector = makeUnhandledHandler("DMA1_Channel4"), - /// DMA1 Channel5 global interrupt DMA1_Channel5: InterruptVector = makeUnhandledHandler("DMA1_Channel5"), - /// DMA1 Channel6 global interrupt DMA1_Channel6: InterruptVector = makeUnhandledHandler("DMA1_Channel6"), - /// DMA1 Channel7 global interrupt DMA1_Channel7: InterruptVector = makeUnhandledHandler("DMA1_Channel7"), - /// ADC1 global interrupt; ADC2 global interrupt ADC: InterruptVector = makeUnhandledHandler("ADC"), - /// CAN1 TX interrupts CAN1_TX: InterruptVector = makeUnhandledHandler("CAN1_TX"), - /// CAN1 RX0 interrupts CAN1_RX0: InterruptVector = makeUnhandledHandler("CAN1_RX0"), - /// CAN1 RX1 interrupt CAN1_RX1: InterruptVector = makeUnhandledHandler("CAN1_RX1"), - /// CAN1 SCE interrupt CAN1_SCE: InterruptVector = makeUnhandledHandler("CAN1_SCE"), - /// EXTI Line[9:5] interrupts EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break interrupt and TIM9 global interrupt TIM1_BRK_TIM9: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM9"), - /// TIM1 Update interrupt and TIM10 global interrupt TIM1_UP_TIM10: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM10"), - /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt TIM1_TRG_COM_TIM11: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM11"), - /// TIM1 Capture Compare interrupt TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt I2C1_EV: InterruptVector = makeUnhandledHandler("I2C1_EV"), - /// I2C1 error interrupt I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt I2C2_EV: InterruptVector = makeUnhandledHandler("I2C2_EV"), - /// I2C2 error interrupt I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt USART1: InterruptVector = makeUnhandledHandler("USART1"), - /// USART2 global interrupt USART2: InterruptVector = makeUnhandledHandler("USART2"), - /// USART3 global interrupt USART3: InterruptVector = makeUnhandledHandler("USART3"), - /// EXTI Line[15:10] interrupts EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC Alarms through EXTI line interrupt RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB Device FS Wakeup through EXTI line interrupt USB_FS_WKUP: InterruptVector = makeUnhandledHandler("USB_FS_WKUP"), - /// TIM8 Break interrupt and TIM12 global interrupt TIM8_BRK_TIM12: InterruptVector = makeUnhandledHandler("TIM8_BRK_TIM12"), - /// TIM8 Update interrupt and TIM13 global interrupt TIM8_UP_TIM13: InterruptVector = makeUnhandledHandler("TIM8_UP_TIM13"), - /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt TIM8_TRG_COM_TIM14: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM_TIM14"), - /// TIM8 Capture Compare interrupt TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt FSMC: InterruptVector = makeUnhandledHandler("FSMC"), - /// SDIO global interrupt SDIO: InterruptVector = makeUnhandledHandler("SDIO"), - /// TIM5 global interrupt TIM5: InterruptVector = makeUnhandledHandler("TIM5"), - /// SPI3 global interrupt SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global interrupt UART4: InterruptVector = makeUnhandledHandler("UART4"), - /// UART5 global interrupt UART5: InterruptVector = makeUnhandledHandler("UART5"), - /// TIM6 global interrupt TIM6: InterruptVector = makeUnhandledHandler("TIM6"), - /// TIM7 global interrupt TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 Channel1 global interrupt DMA2_Channel1: InterruptVector = makeUnhandledHandler("DMA2_Channel1"), - /// DMA2 Channel2 global interrupt DMA2_Channel2: InterruptVector = makeUnhandledHandler("DMA2_Channel2"), - /// DMA2 Channel3 global interrupt DMA2_Channel3: InterruptVector = makeUnhandledHandler("DMA2_Channel3"), - /// DMA2 Channel4 and DMA2 Channel5 global interrupt DMA2_Channel4_5: InterruptVector = makeUnhandledHandler("DMA2_Channel4_5"), }; @@ -18039,4 +22510,3 @@ export const vectors: VectorTable linksection("microzig_flash_start") = blk: { } break :blk temp; }; - diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index fb286b3..88c3635 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -1,47 +1,85 @@ // generated using svd2zig.py // DO NOT EDIT // based on STM32F303 version 1.4 -const mmio = @import("microzig-mmio").mmio; +const microzig_mmio = @import("microzig-mmio"); +const mmio = microzig_mmio.mmio; +const MMIO = microzig_mmio.MMIO; const Name = "STM32F303"; + +/// General-purpose I/Os pub const GPIOA = extern struct { pub const Address: u32 = 0x48000000; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OT1: u1, // bit offset: 1 desc: Port x configuration bits (y = 0..15) - OT2: u1, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OT3: u1, // bit offset: 3 desc: Port x configuration bits (y = 0..15) - OT4: u1, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OT5: u1, // bit offset: 5 desc: Port x configuration bits (y = 0..15) - OT6: u1, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OT7: u1, // bit offset: 7 desc: Port x configuration bits (y = 0..15) - OT8: u1, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OT9: u1, // bit offset: 9 desc: Port x configuration bits (y = 0..15) - OT10: u1, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OT11: u1, // bit offset: 11 desc: Port x configuration bits (y = 0..15) - OT12: u1, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OT13: u1, // bit offset: 13 desc: Port x configuration bits (y = 0..15) - OT14: u1, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OT15: u1, // bit offset: 15 desc: Port x configuration bits (y = 0..15) + /// Port x configuration bits (y = 0..15) + OT0: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT1: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT2: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT3: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT4: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT5: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT6: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT7: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT8: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT9: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT10: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT11: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT12: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT13: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT14: u1 = 0, + /// Port x configuration bits (y = 0..15) + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -59,62 +97,113 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -132,24 +221,41 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -167,60 +273,111 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -237,46 +394,81 @@ pub const GPIOA = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -295,45 +487,81 @@ pub const GPIOA = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOB = extern struct { pub const Address: u32 = 0x48000400; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -351,62 +579,113 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -424,24 +703,41 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -459,60 +755,111 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -529,46 +876,81 @@ pub const GPIOB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -587,45 +969,81 @@ pub const GPIOB = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOC = extern struct { pub const Address: u32 = 0x48000800; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -643,62 +1061,113 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -716,24 +1185,41 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -751,60 +1237,111 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -821,46 +1358,81 @@ pub const GPIOC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -879,45 +1451,81 @@ pub const GPIOC = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOD = extern struct { pub const Address: u32 = 0x48000c00; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -935,62 +1543,113 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1008,24 +1667,41 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1043,60 +1719,111 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1113,46 +1840,81 @@ pub const GPIOD = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1171,45 +1933,81 @@ pub const GPIOD = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOE = extern struct { pub const Address: u32 = 0x48001000; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1227,62 +2025,113 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1300,24 +2149,41 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1335,60 +2201,111 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1405,46 +2322,81 @@ pub const GPIOE = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1463,45 +2415,81 @@ pub const GPIOE = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOF = extern struct { pub const Address: u32 = 0x48001400; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1519,62 +2507,113 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1592,24 +2631,41 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1627,60 +2683,111 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1697,46 +2804,81 @@ pub const GPIOF = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1755,45 +2897,81 @@ pub const GPIOF = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOG = extern struct { pub const Address: u32 = 0x48001800; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1811,62 +2989,113 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1884,24 +3113,41 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -1919,60 +3165,111 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -1989,46 +3286,81 @@ pub const GPIOG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2047,45 +3379,81 @@ pub const GPIOG = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose I/Os pub const GPIOH = extern struct { pub const Address: u32 = 0x48001c00; - // byte offset: 0 GPIO port mode register + + /// GPIO port mode register pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - MODER0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - MODER1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - MODER2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - MODER3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - MODER4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - MODER5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - MODER6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - MODER7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - MODER8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - MODER9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - MODER10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - MODER11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - MODER12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - MODER13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - MODER14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - MODER15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 4 GPIO port output type register + /// Port x configuration bits (y = 0..15) + MODER0: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER1: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER2: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER3: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER4: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER5: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER6: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER7: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER8: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER9: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER10: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER11: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER12: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER13: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER14: u2 = 0, + /// Port x configuration bits (y = 0..15) + MODER15: u2 = 0, + }); + + /// GPIO port output type register pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - OT0: u1, // bit offset: 0 desc: Port x configuration bit 0 - OT1: u1, // bit offset: 1 desc: Port x configuration bit 1 - OT2: u1, // bit offset: 2 desc: Port x configuration bit 2 - OT3: u1, // bit offset: 3 desc: Port x configuration bit 3 - OT4: u1, // bit offset: 4 desc: Port x configuration bit 4 - OT5: u1, // bit offset: 5 desc: Port x configuration bit 5 - OT6: u1, // bit offset: 6 desc: Port x configuration bit 6 - OT7: u1, // bit offset: 7 desc: Port x configuration bit 7 - OT8: u1, // bit offset: 8 desc: Port x configuration bit 8 - OT9: u1, // bit offset: 9 desc: Port x configuration bit 9 - OT10: u1, // bit offset: 10 desc: Port x configuration bit 10 - OT11: u1, // bit offset: 11 desc: Port x configuration bit 11 - OT12: u1, // bit offset: 12 desc: Port x configuration bit 12 - OT13: u1, // bit offset: 13 desc: Port x configuration bit 13 - OT14: u1, // bit offset: 14 desc: Port x configuration bit 14 - OT15: u1, // bit offset: 15 desc: Port x configuration bit 15 + /// Port x configuration bit 0 + OT0: u1 = 0, + /// Port x configuration bit 1 + OT1: u1 = 0, + /// Port x configuration bit 2 + OT2: u1 = 0, + /// Port x configuration bit 3 + OT3: u1 = 0, + /// Port x configuration bit 4 + OT4: u1 = 0, + /// Port x configuration bit 5 + OT5: u1 = 0, + /// Port x configuration bit 6 + OT6: u1 = 0, + /// Port x configuration bit 7 + OT7: u1 = 0, + /// Port x configuration bit 8 + OT8: u1 = 0, + /// Port x configuration bit 9 + OT9: u1 = 0, + /// Port x configuration bit 10 + OT10: u1 = 0, + /// Port x configuration bit 11 + OT11: u1 = 0, + /// Port x configuration bit 12 + OT12: u1 = 0, + /// Port x configuration bit 13 + OT13: u1 = 0, + /// Port x configuration bit 14 + OT14: u1 = 0, + /// Port x configuration bit 15 + OT15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2103,62 +3471,113 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 GPIO port output speed register + + /// GPIO port output speed register pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - OSPEEDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - OSPEEDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - OSPEEDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - OSPEEDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - OSPEEDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - OSPEEDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - OSPEEDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - OSPEEDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - OSPEEDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - OSPEEDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - OSPEEDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - OSPEEDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - OSPEEDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - OSPEEDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - OSPEEDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - OSPEEDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 12 GPIO port pull-up/pull-down register + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2 = 0, + }); + + /// GPIO port pull-up/pull-down register pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - PUPDR0: u2, // bit offset: 0 desc: Port x configuration bits (y = 0..15) - PUPDR1: u2, // bit offset: 2 desc: Port x configuration bits (y = 0..15) - PUPDR2: u2, // bit offset: 4 desc: Port x configuration bits (y = 0..15) - PUPDR3: u2, // bit offset: 6 desc: Port x configuration bits (y = 0..15) - PUPDR4: u2, // bit offset: 8 desc: Port x configuration bits (y = 0..15) - PUPDR5: u2, // bit offset: 10 desc: Port x configuration bits (y = 0..15) - PUPDR6: u2, // bit offset: 12 desc: Port x configuration bits (y = 0..15) - PUPDR7: u2, // bit offset: 14 desc: Port x configuration bits (y = 0..15) - PUPDR8: u2, // bit offset: 16 desc: Port x configuration bits (y = 0..15) - PUPDR9: u2, // bit offset: 18 desc: Port x configuration bits (y = 0..15) - PUPDR10: u2, // bit offset: 20 desc: Port x configuration bits (y = 0..15) - PUPDR11: u2, // bit offset: 22 desc: Port x configuration bits (y = 0..15) - PUPDR12: u2, // bit offset: 24 desc: Port x configuration bits (y = 0..15) - PUPDR13: u2, // bit offset: 26 desc: Port x configuration bits (y = 0..15) - PUPDR14: u2, // bit offset: 28 desc: Port x configuration bits (y = 0..15) - PUPDR15: u2, // bit offset: 30 desc: Port x configuration bits (y = 0..15) - }); - // byte offset: 16 GPIO port input data register + /// Port x configuration bits (y = 0..15) + PUPDR0: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2 = 0, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2 = 0, + }); + + /// GPIO port input data register pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - IDR0: u1, // bit offset: 0 desc: Port input data (y = 0..15) - IDR1: u1, // bit offset: 1 desc: Port input data (y = 0..15) - IDR2: u1, // bit offset: 2 desc: Port input data (y = 0..15) - IDR3: u1, // bit offset: 3 desc: Port input data (y = 0..15) - IDR4: u1, // bit offset: 4 desc: Port input data (y = 0..15) - IDR5: u1, // bit offset: 5 desc: Port input data (y = 0..15) - IDR6: u1, // bit offset: 6 desc: Port input data (y = 0..15) - IDR7: u1, // bit offset: 7 desc: Port input data (y = 0..15) - IDR8: u1, // bit offset: 8 desc: Port input data (y = 0..15) - IDR9: u1, // bit offset: 9 desc: Port input data (y = 0..15) - IDR10: u1, // bit offset: 10 desc: Port input data (y = 0..15) - IDR11: u1, // bit offset: 11 desc: Port input data (y = 0..15) - IDR12: u1, // bit offset: 12 desc: Port input data (y = 0..15) - IDR13: u1, // bit offset: 13 desc: Port input data (y = 0..15) - IDR14: u1, // bit offset: 14 desc: Port input data (y = 0..15) - IDR15: u1, // bit offset: 15 desc: Port input data (y = 0..15) + /// Port input data (y = 0..15) + IDR0: u1 = 0, + /// Port input data (y = 0..15) + IDR1: u1 = 0, + /// Port input data (y = 0..15) + IDR2: u1 = 0, + /// Port input data (y = 0..15) + IDR3: u1 = 0, + /// Port input data (y = 0..15) + IDR4: u1 = 0, + /// Port input data (y = 0..15) + IDR5: u1 = 0, + /// Port input data (y = 0..15) + IDR6: u1 = 0, + /// Port input data (y = 0..15) + IDR7: u1 = 0, + /// Port input data (y = 0..15) + IDR8: u1 = 0, + /// Port input data (y = 0..15) + IDR9: u1 = 0, + /// Port input data (y = 0..15) + IDR10: u1 = 0, + /// Port input data (y = 0..15) + IDR11: u1 = 0, + /// Port input data (y = 0..15) + IDR12: u1 = 0, + /// Port input data (y = 0..15) + IDR13: u1 = 0, + /// Port input data (y = 0..15) + IDR14: u1 = 0, + /// Port input data (y = 0..15) + IDR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2176,24 +3595,41 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 GPIO port output data register + + /// GPIO port output data register pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - ODR0: u1, // bit offset: 0 desc: Port output data (y = 0..15) - ODR1: u1, // bit offset: 1 desc: Port output data (y = 0..15) - ODR2: u1, // bit offset: 2 desc: Port output data (y = 0..15) - ODR3: u1, // bit offset: 3 desc: Port output data (y = 0..15) - ODR4: u1, // bit offset: 4 desc: Port output data (y = 0..15) - ODR5: u1, // bit offset: 5 desc: Port output data (y = 0..15) - ODR6: u1, // bit offset: 6 desc: Port output data (y = 0..15) - ODR7: u1, // bit offset: 7 desc: Port output data (y = 0..15) - ODR8: u1, // bit offset: 8 desc: Port output data (y = 0..15) - ODR9: u1, // bit offset: 9 desc: Port output data (y = 0..15) - ODR10: u1, // bit offset: 10 desc: Port output data (y = 0..15) - ODR11: u1, // bit offset: 11 desc: Port output data (y = 0..15) - ODR12: u1, // bit offset: 12 desc: Port output data (y = 0..15) - ODR13: u1, // bit offset: 13 desc: Port output data (y = 0..15) - ODR14: u1, // bit offset: 14 desc: Port output data (y = 0..15) - ODR15: u1, // bit offset: 15 desc: Port output data (y = 0..15) + /// Port output data (y = 0..15) + ODR0: u1 = 0, + /// Port output data (y = 0..15) + ODR1: u1 = 0, + /// Port output data (y = 0..15) + ODR2: u1 = 0, + /// Port output data (y = 0..15) + ODR3: u1 = 0, + /// Port output data (y = 0..15) + ODR4: u1 = 0, + /// Port output data (y = 0..15) + ODR5: u1 = 0, + /// Port output data (y = 0..15) + ODR6: u1 = 0, + /// Port output data (y = 0..15) + ODR7: u1 = 0, + /// Port output data (y = 0..15) + ODR8: u1 = 0, + /// Port output data (y = 0..15) + ODR9: u1 = 0, + /// Port output data (y = 0..15) + ODR10: u1 = 0, + /// Port output data (y = 0..15) + ODR11: u1 = 0, + /// Port output data (y = 0..15) + ODR12: u1 = 0, + /// Port output data (y = 0..15) + ODR13: u1 = 0, + /// Port output data (y = 0..15) + ODR14: u1 = 0, + /// Port output data (y = 0..15) + ODR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2211,60 +3647,111 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 GPIO port bit set/reset register + + /// GPIO port bit set/reset register pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - BS0: u1, // bit offset: 0 desc: Port x set bit y (y= 0..15) - BS1: u1, // bit offset: 1 desc: Port x set bit y (y= 0..15) - BS2: u1, // bit offset: 2 desc: Port x set bit y (y= 0..15) - BS3: u1, // bit offset: 3 desc: Port x set bit y (y= 0..15) - BS4: u1, // bit offset: 4 desc: Port x set bit y (y= 0..15) - BS5: u1, // bit offset: 5 desc: Port x set bit y (y= 0..15) - BS6: u1, // bit offset: 6 desc: Port x set bit y (y= 0..15) - BS7: u1, // bit offset: 7 desc: Port x set bit y (y= 0..15) - BS8: u1, // bit offset: 8 desc: Port x set bit y (y= 0..15) - BS9: u1, // bit offset: 9 desc: Port x set bit y (y= 0..15) - BS10: u1, // bit offset: 10 desc: Port x set bit y (y= 0..15) - BS11: u1, // bit offset: 11 desc: Port x set bit y (y= 0..15) - BS12: u1, // bit offset: 12 desc: Port x set bit y (y= 0..15) - BS13: u1, // bit offset: 13 desc: Port x set bit y (y= 0..15) - BS14: u1, // bit offset: 14 desc: Port x set bit y (y= 0..15) - BS15: u1, // bit offset: 15 desc: Port x set bit y (y= 0..15) - BR0: u1, // bit offset: 16 desc: Port x set bit y (y= 0..15) - BR1: u1, // bit offset: 17 desc: Port x reset bit y (y = 0..15) - BR2: u1, // bit offset: 18 desc: Port x reset bit y (y = 0..15) - BR3: u1, // bit offset: 19 desc: Port x reset bit y (y = 0..15) - BR4: u1, // bit offset: 20 desc: Port x reset bit y (y = 0..15) - BR5: u1, // bit offset: 21 desc: Port x reset bit y (y = 0..15) - BR6: u1, // bit offset: 22 desc: Port x reset bit y (y = 0..15) - BR7: u1, // bit offset: 23 desc: Port x reset bit y (y = 0..15) - BR8: u1, // bit offset: 24 desc: Port x reset bit y (y = 0..15) - BR9: u1, // bit offset: 25 desc: Port x reset bit y (y = 0..15) - BR10: u1, // bit offset: 26 desc: Port x reset bit y (y = 0..15) - BR11: u1, // bit offset: 27 desc: Port x reset bit y (y = 0..15) - BR12: u1, // bit offset: 28 desc: Port x reset bit y (y = 0..15) - BR13: u1, // bit offset: 29 desc: Port x reset bit y (y = 0..15) - BR14: u1, // bit offset: 30 desc: Port x reset bit y (y = 0..15) - BR15: u1, // bit offset: 31 desc: Port x reset bit y (y = 0..15) - }); - // byte offset: 28 GPIO port configuration lock register + /// Port x set bit y (y= 0..15) + BS0: u1 = 0, + /// Port x set bit y (y= 0..15) + BS1: u1 = 0, + /// Port x set bit y (y= 0..15) + BS2: u1 = 0, + /// Port x set bit y (y= 0..15) + BS3: u1 = 0, + /// Port x set bit y (y= 0..15) + BS4: u1 = 0, + /// Port x set bit y (y= 0..15) + BS5: u1 = 0, + /// Port x set bit y (y= 0..15) + BS6: u1 = 0, + /// Port x set bit y (y= 0..15) + BS7: u1 = 0, + /// Port x set bit y (y= 0..15) + BS8: u1 = 0, + /// Port x set bit y (y= 0..15) + BS9: u1 = 0, + /// Port x set bit y (y= 0..15) + BS10: u1 = 0, + /// Port x set bit y (y= 0..15) + BS11: u1 = 0, + /// Port x set bit y (y= 0..15) + BS12: u1 = 0, + /// Port x set bit y (y= 0..15) + BS13: u1 = 0, + /// Port x set bit y (y= 0..15) + BS14: u1 = 0, + /// Port x set bit y (y= 0..15) + BS15: u1 = 0, + /// Port x set bit y (y= 0..15) + BR0: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR1: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR2: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR3: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR4: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR5: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR6: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR7: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR8: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR9: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR10: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR11: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR12: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR13: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR14: u1 = 0, + /// Port x reset bit y (y = 0..15) + BR15: u1 = 0, + }); + + /// GPIO port configuration lock register pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - LCK0: u1, // bit offset: 0 desc: Port x lock bit y (y= 0..15) - LCK1: u1, // bit offset: 1 desc: Port x lock bit y (y= 0..15) - LCK2: u1, // bit offset: 2 desc: Port x lock bit y (y= 0..15) - LCK3: u1, // bit offset: 3 desc: Port x lock bit y (y= 0..15) - LCK4: u1, // bit offset: 4 desc: Port x lock bit y (y= 0..15) - LCK5: u1, // bit offset: 5 desc: Port x lock bit y (y= 0..15) - LCK6: u1, // bit offset: 6 desc: Port x lock bit y (y= 0..15) - LCK7: u1, // bit offset: 7 desc: Port x lock bit y (y= 0..15) - LCK8: u1, // bit offset: 8 desc: Port x lock bit y (y= 0..15) - LCK9: u1, // bit offset: 9 desc: Port x lock bit y (y= 0..15) - LCK10: u1, // bit offset: 10 desc: Port x lock bit y (y= 0..15) - LCK11: u1, // bit offset: 11 desc: Port x lock bit y (y= 0..15) - LCK12: u1, // bit offset: 12 desc: Port x lock bit y (y= 0..15) - LCK13: u1, // bit offset: 13 desc: Port x lock bit y (y= 0..15) - LCK14: u1, // bit offset: 14 desc: Port x lock bit y (y= 0..15) - LCK15: u1, // bit offset: 15 desc: Port x lock bit y (y= 0..15) - LCKK: u1, // bit offset: 16 desc: Lok Key + /// Port x lock bit y (y= 0..15) + LCK0: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK1: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK2: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK3: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK4: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK5: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK6: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK7: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK8: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK9: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK10: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK11: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK12: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK13: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK14: u1 = 0, + /// Port x lock bit y (y= 0..15) + LCK15: u1 = 0, + /// Lok Key + LCKK: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -2281,46 +3768,81 @@ pub const GPIOH = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 GPIO alternate function low register + + /// GPIO alternate function low register pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - AFRL0: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 0..7) - }); - // byte offset: 36 GPIO alternate function high register + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4 = 0, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4 = 0, + }); + + /// GPIO alternate function high register pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - AFRH8: u4, // bit offset: 0 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4, // bit offset: 4 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4, // bit offset: 8 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4, // bit offset: 12 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4, // bit offset: 16 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4, // bit offset: 20 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4, // bit offset: 24 desc: Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4, // bit offset: 28 desc: Alternate function selection for port x bit y (y = 8..15) - }); - // byte offset: 40 Port bit reset register + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4 = 0, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4 = 0, + }); + + /// Port bit reset register pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - BR0: u1, // bit offset: 0 desc: Port x Reset bit y - BR1: u1, // bit offset: 1 desc: Port x Reset bit y - BR2: u1, // bit offset: 2 desc: Port x Reset bit y - BR3: u1, // bit offset: 3 desc: Port x Reset bit y - BR4: u1, // bit offset: 4 desc: Port x Reset bit y - BR5: u1, // bit offset: 5 desc: Port x Reset bit y - BR6: u1, // bit offset: 6 desc: Port x Reset bit y - BR7: u1, // bit offset: 7 desc: Port x Reset bit y - BR8: u1, // bit offset: 8 desc: Port x Reset bit y - BR9: u1, // bit offset: 9 desc: Port x Reset bit y - BR10: u1, // bit offset: 10 desc: Port x Reset bit y - BR11: u1, // bit offset: 11 desc: Port x Reset bit y - BR12: u1, // bit offset: 12 desc: Port x Reset bit y - BR13: u1, // bit offset: 13 desc: Port x Reset bit y - BR14: u1, // bit offset: 14 desc: Port x Reset bit y - BR15: u1, // bit offset: 15 desc: Port x Reset bit y + /// Port x Reset bit y + BR0: u1 = 0, + /// Port x Reset bit y + BR1: u1 = 0, + /// Port x Reset bit y + BR2: u1 = 0, + /// Port x Reset bit y + BR3: u1 = 0, + /// Port x Reset bit y + BR4: u1 = 0, + /// Port x Reset bit y + BR5: u1 = 0, + /// Port x Reset bit y + BR6: u1 = 0, + /// Port x Reset bit y + BR7: u1 = 0, + /// Port x Reset bit y + BR8: u1 = 0, + /// Port x Reset bit y + BR9: u1 = 0, + /// Port x Reset bit y + BR10: u1 = 0, + /// Port x Reset bit y + BR11: u1 = 0, + /// Port x Reset bit y + BR12: u1 = 0, + /// Port x Reset bit y + BR13: u1 = 0, + /// Port x Reset bit y + BR14: u1 = 0, + /// Port x Reset bit y + BR15: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -2339,31 +3861,49 @@ pub const GPIOH = extern struct { padding1: u1 = 0, }); }; + +/// Touch sensing controller pub const TSC = extern struct { pub const Address: u32 = 0x40024000; - // byte offset: 0 control register + + /// control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - TSCE: u1, // bit offset: 0 desc: Touch sensing controller enable - START: u1, // bit offset: 1 desc: Start a new acquisition - AM: u1, // bit offset: 2 desc: Acquisition mode - SYNCPOL: u1, // bit offset: 3 desc: Synchronization pin polarity - IODEF: u1, // bit offset: 4 desc: I/O Default mode - MCV: u3, // bit offset: 5 desc: Max count value + /// Touch sensing controller enable + TSCE: u1 = 0, + /// Start a new acquisition + START: u1 = 0, + /// Acquisition mode + AM: u1 = 0, + /// Synchronization pin polarity + SYNCPOL: u1 = 0, + /// I/O Default mode + IODEF: u1 = 0, + /// Max count value + MCV: u3 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PGPSC: u3, // bit offset: 12 desc: pulse generator prescaler - SSPSC: u1, // bit offset: 15 desc: Spread spectrum prescaler - SSE: u1, // bit offset: 16 desc: Spread spectrum enable - SSD: u7, // bit offset: 17 desc: Spread spectrum deviation - CTPL: u4, // bit offset: 24 desc: Charge transfer pulse low - CTPH: u4, // bit offset: 28 desc: Charge transfer pulse high + /// pulse generator prescaler + PGPSC: u3 = 0, + /// Spread spectrum prescaler + SSPSC: u1 = 0, + /// Spread spectrum enable + SSE: u1 = 0, + /// Spread spectrum deviation + SSD: u7 = 0, + /// Charge transfer pulse low + CTPL: u4 = 0, + /// Charge transfer pulse high + CTPH: u4 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - EOAIE: u1, // bit offset: 0 desc: End of acquisition interrupt enable - MCEIE: u1, // bit offset: 1 desc: Max count error interrupt enable + /// End of acquisition interrupt enable + EOAIE: u1 = 0, + /// Max count error interrupt enable + MCEIE: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2395,10 +3935,13 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 interrupt clear register + + /// interrupt clear register pub const ICR = mmio(Address + 0x00000008, 32, packed struct { - EOAIC: u1, // bit offset: 0 desc: End of acquisition interrupt clear - MCEIC: u1, // bit offset: 1 desc: Max count error interrupt clear + /// End of acquisition interrupt clear + EOAIC: u1 = 0, + /// Max count error interrupt clear + MCEIC: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2430,10 +3973,13 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 interrupt status register + + /// interrupt status register pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - EOAF: u1, // bit offset: 0 desc: End of acquisition flag - MCEF: u1, // bit offset: 1 desc: Max count error flag + /// End of acquisition flag + EOAF: u1 = 0, + /// Max count error flag + MCEF: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -2465,156 +4011,297 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 I/O hysteresis control register + + /// I/O hysteresis control register pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 Schmitt trigger hysteresis mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 Schmitt trigger hysteresis mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 Schmitt trigger hysteresis mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 Schmitt trigger hysteresis mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 Schmitt trigger hysteresis mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 Schmitt trigger hysteresis mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 Schmitt trigger hysteresis mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 Schmitt trigger hysteresis mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 Schmitt trigger hysteresis mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 Schmitt trigger hysteresis mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 Schmitt trigger hysteresis mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 Schmitt trigger hysteresis mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 Schmitt trigger hysteresis mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 Schmitt trigger hysteresis mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 Schmitt trigger hysteresis mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 Schmitt trigger hysteresis mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 Schmitt trigger hysteresis mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 Schmitt trigger hysteresis mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 Schmitt trigger hysteresis mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 Schmitt trigger hysteresis mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 Schmitt trigger hysteresis mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 Schmitt trigger hysteresis mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 Schmitt trigger hysteresis mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 Schmitt trigger hysteresis mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 Schmitt trigger hysteresis mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 Schmitt trigger hysteresis mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 Schmitt trigger hysteresis mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 Schmitt trigger hysteresis mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 Schmitt trigger hysteresis mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 Schmitt trigger hysteresis mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 Schmitt trigger hysteresis mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 Schmitt trigger hysteresis mode - }); - // byte offset: 24 I/O analog switch control register + /// G1_IO1 Schmitt trigger hysteresis mode + G1_IO1: u1 = 0, + /// G1_IO2 Schmitt trigger hysteresis mode + G1_IO2: u1 = 0, + /// G1_IO3 Schmitt trigger hysteresis mode + G1_IO3: u1 = 0, + /// G1_IO4 Schmitt trigger hysteresis mode + G1_IO4: u1 = 0, + /// G2_IO1 Schmitt trigger hysteresis mode + G2_IO1: u1 = 0, + /// G2_IO2 Schmitt trigger hysteresis mode + G2_IO2: u1 = 0, + /// G2_IO3 Schmitt trigger hysteresis mode + G2_IO3: u1 = 0, + /// G2_IO4 Schmitt trigger hysteresis mode + G2_IO4: u1 = 0, + /// G3_IO1 Schmitt trigger hysteresis mode + G3_IO1: u1 = 0, + /// G3_IO2 Schmitt trigger hysteresis mode + G3_IO2: u1 = 0, + /// G3_IO3 Schmitt trigger hysteresis mode + G3_IO3: u1 = 0, + /// G3_IO4 Schmitt trigger hysteresis mode + G3_IO4: u1 = 0, + /// G4_IO1 Schmitt trigger hysteresis mode + G4_IO1: u1 = 0, + /// G4_IO2 Schmitt trigger hysteresis mode + G4_IO2: u1 = 0, + /// G4_IO3 Schmitt trigger hysteresis mode + G4_IO3: u1 = 0, + /// G4_IO4 Schmitt trigger hysteresis mode + G4_IO4: u1 = 0, + /// G5_IO1 Schmitt trigger hysteresis mode + G5_IO1: u1 = 0, + /// G5_IO2 Schmitt trigger hysteresis mode + G5_IO2: u1 = 0, + /// G5_IO3 Schmitt trigger hysteresis mode + G5_IO3: u1 = 0, + /// G5_IO4 Schmitt trigger hysteresis mode + G5_IO4: u1 = 0, + /// G6_IO1 Schmitt trigger hysteresis mode + G6_IO1: u1 = 0, + /// G6_IO2 Schmitt trigger hysteresis mode + G6_IO2: u1 = 0, + /// G6_IO3 Schmitt trigger hysteresis mode + G6_IO3: u1 = 0, + /// G6_IO4 Schmitt trigger hysteresis mode + G6_IO4: u1 = 0, + /// G7_IO1 Schmitt trigger hysteresis mode + G7_IO1: u1 = 0, + /// G7_IO2 Schmitt trigger hysteresis mode + G7_IO2: u1 = 0, + /// G7_IO3 Schmitt trigger hysteresis mode + G7_IO3: u1 = 0, + /// G7_IO4 Schmitt trigger hysteresis mode + G7_IO4: u1 = 0, + /// G8_IO1 Schmitt trigger hysteresis mode + G8_IO1: u1 = 0, + /// G8_IO2 Schmitt trigger hysteresis mode + G8_IO2: u1 = 0, + /// G8_IO3 Schmitt trigger hysteresis mode + G8_IO3: u1 = 0, + /// G8_IO4 Schmitt trigger hysteresis mode + G8_IO4: u1 = 0, + }); + + /// I/O analog switch control register pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 analog switch enable - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 analog switch enable - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 analog switch enable - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 analog switch enable - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 analog switch enable - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 analog switch enable - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 analog switch enable - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 analog switch enable - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 analog switch enable - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 analog switch enable - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 analog switch enable - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 analog switch enable - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 analog switch enable - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 analog switch enable - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 analog switch enable - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 analog switch enable - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 analog switch enable - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 analog switch enable - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 analog switch enable - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 analog switch enable - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 analog switch enable - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 analog switch enable - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 analog switch enable - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 analog switch enable - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 analog switch enable - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 analog switch enable - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 analog switch enable - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 analog switch enable - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 analog switch enable - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 analog switch enable - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 analog switch enable - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 analog switch enable - }); - // byte offset: 32 I/O sampling control register + /// G1_IO1 analog switch enable + G1_IO1: u1 = 0, + /// G1_IO2 analog switch enable + G1_IO2: u1 = 0, + /// G1_IO3 analog switch enable + G1_IO3: u1 = 0, + /// G1_IO4 analog switch enable + G1_IO4: u1 = 0, + /// G2_IO1 analog switch enable + G2_IO1: u1 = 0, + /// G2_IO2 analog switch enable + G2_IO2: u1 = 0, + /// G2_IO3 analog switch enable + G2_IO3: u1 = 0, + /// G2_IO4 analog switch enable + G2_IO4: u1 = 0, + /// G3_IO1 analog switch enable + G3_IO1: u1 = 0, + /// G3_IO2 analog switch enable + G3_IO2: u1 = 0, + /// G3_IO3 analog switch enable + G3_IO3: u1 = 0, + /// G3_IO4 analog switch enable + G3_IO4: u1 = 0, + /// G4_IO1 analog switch enable + G4_IO1: u1 = 0, + /// G4_IO2 analog switch enable + G4_IO2: u1 = 0, + /// G4_IO3 analog switch enable + G4_IO3: u1 = 0, + /// G4_IO4 analog switch enable + G4_IO4: u1 = 0, + /// G5_IO1 analog switch enable + G5_IO1: u1 = 0, + /// G5_IO2 analog switch enable + G5_IO2: u1 = 0, + /// G5_IO3 analog switch enable + G5_IO3: u1 = 0, + /// G5_IO4 analog switch enable + G5_IO4: u1 = 0, + /// G6_IO1 analog switch enable + G6_IO1: u1 = 0, + /// G6_IO2 analog switch enable + G6_IO2: u1 = 0, + /// G6_IO3 analog switch enable + G6_IO3: u1 = 0, + /// G6_IO4 analog switch enable + G6_IO4: u1 = 0, + /// G7_IO1 analog switch enable + G7_IO1: u1 = 0, + /// G7_IO2 analog switch enable + G7_IO2: u1 = 0, + /// G7_IO3 analog switch enable + G7_IO3: u1 = 0, + /// G7_IO4 analog switch enable + G7_IO4: u1 = 0, + /// G8_IO1 analog switch enable + G8_IO1: u1 = 0, + /// G8_IO2 analog switch enable + G8_IO2: u1 = 0, + /// G8_IO3 analog switch enable + G8_IO3: u1 = 0, + /// G8_IO4 analog switch enable + G8_IO4: u1 = 0, + }); + + /// I/O sampling control register pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 sampling mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 sampling mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 sampling mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 sampling mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 sampling mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 sampling mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 sampling mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 sampling mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 sampling mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 sampling mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 sampling mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 sampling mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 sampling mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 sampling mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 sampling mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 sampling mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 sampling mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 sampling mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 sampling mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 sampling mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 sampling mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 sampling mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 sampling mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 sampling mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 sampling mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 sampling mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 sampling mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 sampling mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 sampling mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 sampling mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 sampling mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 sampling mode - }); - // byte offset: 40 I/O channel control register + /// G1_IO1 sampling mode + G1_IO1: u1 = 0, + /// G1_IO2 sampling mode + G1_IO2: u1 = 0, + /// G1_IO3 sampling mode + G1_IO3: u1 = 0, + /// G1_IO4 sampling mode + G1_IO4: u1 = 0, + /// G2_IO1 sampling mode + G2_IO1: u1 = 0, + /// G2_IO2 sampling mode + G2_IO2: u1 = 0, + /// G2_IO3 sampling mode + G2_IO3: u1 = 0, + /// G2_IO4 sampling mode + G2_IO4: u1 = 0, + /// G3_IO1 sampling mode + G3_IO1: u1 = 0, + /// G3_IO2 sampling mode + G3_IO2: u1 = 0, + /// G3_IO3 sampling mode + G3_IO3: u1 = 0, + /// G3_IO4 sampling mode + G3_IO4: u1 = 0, + /// G4_IO1 sampling mode + G4_IO1: u1 = 0, + /// G4_IO2 sampling mode + G4_IO2: u1 = 0, + /// G4_IO3 sampling mode + G4_IO3: u1 = 0, + /// G4_IO4 sampling mode + G4_IO4: u1 = 0, + /// G5_IO1 sampling mode + G5_IO1: u1 = 0, + /// G5_IO2 sampling mode + G5_IO2: u1 = 0, + /// G5_IO3 sampling mode + G5_IO3: u1 = 0, + /// G5_IO4 sampling mode + G5_IO4: u1 = 0, + /// G6_IO1 sampling mode + G6_IO1: u1 = 0, + /// G6_IO2 sampling mode + G6_IO2: u1 = 0, + /// G6_IO3 sampling mode + G6_IO3: u1 = 0, + /// G6_IO4 sampling mode + G6_IO4: u1 = 0, + /// G7_IO1 sampling mode + G7_IO1: u1 = 0, + /// G7_IO2 sampling mode + G7_IO2: u1 = 0, + /// G7_IO3 sampling mode + G7_IO3: u1 = 0, + /// G7_IO4 sampling mode + G7_IO4: u1 = 0, + /// G8_IO1 sampling mode + G8_IO1: u1 = 0, + /// G8_IO2 sampling mode + G8_IO2: u1 = 0, + /// G8_IO3 sampling mode + G8_IO3: u1 = 0, + /// G8_IO4 sampling mode + G8_IO4: u1 = 0, + }); + + /// I/O channel control register pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { - G1_IO1: u1, // bit offset: 0 desc: G1_IO1 channel mode - G1_IO2: u1, // bit offset: 1 desc: G1_IO2 channel mode - G1_IO3: u1, // bit offset: 2 desc: G1_IO3 channel mode - G1_IO4: u1, // bit offset: 3 desc: G1_IO4 channel mode - G2_IO1: u1, // bit offset: 4 desc: G2_IO1 channel mode - G2_IO2: u1, // bit offset: 5 desc: G2_IO2 channel mode - G2_IO3: u1, // bit offset: 6 desc: G2_IO3 channel mode - G2_IO4: u1, // bit offset: 7 desc: G2_IO4 channel mode - G3_IO1: u1, // bit offset: 8 desc: G3_IO1 channel mode - G3_IO2: u1, // bit offset: 9 desc: G3_IO2 channel mode - G3_IO3: u1, // bit offset: 10 desc: G3_IO3 channel mode - G3_IO4: u1, // bit offset: 11 desc: G3_IO4 channel mode - G4_IO1: u1, // bit offset: 12 desc: G4_IO1 channel mode - G4_IO2: u1, // bit offset: 13 desc: G4_IO2 channel mode - G4_IO3: u1, // bit offset: 14 desc: G4_IO3 channel mode - G4_IO4: u1, // bit offset: 15 desc: G4_IO4 channel mode - G5_IO1: u1, // bit offset: 16 desc: G5_IO1 channel mode - G5_IO2: u1, // bit offset: 17 desc: G5_IO2 channel mode - G5_IO3: u1, // bit offset: 18 desc: G5_IO3 channel mode - G5_IO4: u1, // bit offset: 19 desc: G5_IO4 channel mode - G6_IO1: u1, // bit offset: 20 desc: G6_IO1 channel mode - G6_IO2: u1, // bit offset: 21 desc: G6_IO2 channel mode - G6_IO3: u1, // bit offset: 22 desc: G6_IO3 channel mode - G6_IO4: u1, // bit offset: 23 desc: G6_IO4 channel mode - G7_IO1: u1, // bit offset: 24 desc: G7_IO1 channel mode - G7_IO2: u1, // bit offset: 25 desc: G7_IO2 channel mode - G7_IO3: u1, // bit offset: 26 desc: G7_IO3 channel mode - G7_IO4: u1, // bit offset: 27 desc: G7_IO4 channel mode - G8_IO1: u1, // bit offset: 28 desc: G8_IO1 channel mode - G8_IO2: u1, // bit offset: 29 desc: G8_IO2 channel mode - G8_IO3: u1, // bit offset: 30 desc: G8_IO3 channel mode - G8_IO4: u1, // bit offset: 31 desc: G8_IO4 channel mode - }); - // byte offset: 48 I/O group control status register + /// G1_IO1 channel mode + G1_IO1: u1 = 0, + /// G1_IO2 channel mode + G1_IO2: u1 = 0, + /// G1_IO3 channel mode + G1_IO3: u1 = 0, + /// G1_IO4 channel mode + G1_IO4: u1 = 0, + /// G2_IO1 channel mode + G2_IO1: u1 = 0, + /// G2_IO2 channel mode + G2_IO2: u1 = 0, + /// G2_IO3 channel mode + G2_IO3: u1 = 0, + /// G2_IO4 channel mode + G2_IO4: u1 = 0, + /// G3_IO1 channel mode + G3_IO1: u1 = 0, + /// G3_IO2 channel mode + G3_IO2: u1 = 0, + /// G3_IO3 channel mode + G3_IO3: u1 = 0, + /// G3_IO4 channel mode + G3_IO4: u1 = 0, + /// G4_IO1 channel mode + G4_IO1: u1 = 0, + /// G4_IO2 channel mode + G4_IO2: u1 = 0, + /// G4_IO3 channel mode + G4_IO3: u1 = 0, + /// G4_IO4 channel mode + G4_IO4: u1 = 0, + /// G5_IO1 channel mode + G5_IO1: u1 = 0, + /// G5_IO2 channel mode + G5_IO2: u1 = 0, + /// G5_IO3 channel mode + G5_IO3: u1 = 0, + /// G5_IO4 channel mode + G5_IO4: u1 = 0, + /// G6_IO1 channel mode + G6_IO1: u1 = 0, + /// G6_IO2 channel mode + G6_IO2: u1 = 0, + /// G6_IO3 channel mode + G6_IO3: u1 = 0, + /// G6_IO4 channel mode + G6_IO4: u1 = 0, + /// G7_IO1 channel mode + G7_IO1: u1 = 0, + /// G7_IO2 channel mode + G7_IO2: u1 = 0, + /// G7_IO3 channel mode + G7_IO3: u1 = 0, + /// G7_IO4 channel mode + G7_IO4: u1 = 0, + /// G8_IO1 channel mode + G8_IO1: u1 = 0, + /// G8_IO2 channel mode + G8_IO2: u1 = 0, + /// G8_IO3 channel mode + G8_IO3: u1 = 0, + /// G8_IO4 channel mode + G8_IO4: u1 = 0, + }); + + /// I/O group control status register pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { - G1E: u1, // bit offset: 0 desc: Analog I/O group x enable - G2E: u1, // bit offset: 1 desc: Analog I/O group x enable - G3E: u1, // bit offset: 2 desc: Analog I/O group x enable - G4E: u1, // bit offset: 3 desc: Analog I/O group x enable - G5E: u1, // bit offset: 4 desc: Analog I/O group x enable - G6E: u1, // bit offset: 5 desc: Analog I/O group x enable - G7E: u1, // bit offset: 6 desc: Analog I/O group x enable - G8E: u1, // bit offset: 7 desc: Analog I/O group x enable + /// Analog I/O group x enable + G1E: u1 = 0, + /// Analog I/O group x enable + G2E: u1 = 0, + /// Analog I/O group x enable + G3E: u1 = 0, + /// Analog I/O group x enable + G4E: u1 = 0, + /// Analog I/O group x enable + G5E: u1 = 0, + /// Analog I/O group x enable + G6E: u1 = 0, + /// Analog I/O group x enable + G7E: u1 = 0, + /// Analog I/O group x enable + G8E: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -2623,14 +4310,22 @@ pub const TSC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - G1S: u1, // bit offset: 16 desc: Analog I/O group x status - G2S: u1, // bit offset: 17 desc: Analog I/O group x status - G3S: u1, // bit offset: 18 desc: Analog I/O group x status - G4S: u1, // bit offset: 19 desc: Analog I/O group x status - G5S: u1, // bit offset: 20 desc: Analog I/O group x status - G6S: u1, // bit offset: 21 desc: Analog I/O group x status - G7S: u1, // bit offset: 22 desc: Analog I/O group x status - G8S: u1, // bit offset: 23 desc: Analog I/O group x status + /// Analog I/O group x status + G1S: u1 = 0, + /// Analog I/O group x status + G2S: u1 = 0, + /// Analog I/O group x status + G3S: u1 = 0, + /// Analog I/O group x status + G4S: u1 = 0, + /// Analog I/O group x status + G5S: u1 = 0, + /// Analog I/O group x status + G6S: u1 = 0, + /// Analog I/O group x status + G7S: u1 = 0, + /// Analog I/O group x status + G8S: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -2640,9 +4335,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 I/O group x counter register + + /// I/O group x counter register pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2662,9 +4359,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 I/O group x counter register + + /// I/O group x counter register pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2684,9 +4383,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 I/O group x counter register + + /// I/O group x counter register pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2706,9 +4407,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 I/O group x counter register + + /// I/O group x counter register pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2728,9 +4431,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 I/O group x counter register + + /// I/O group x counter register pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2750,9 +4455,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 I/O group x counter register + + /// I/O group x counter register pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2772,9 +4479,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 I/O group x counter register + + /// I/O group x counter register pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2794,9 +4503,11 @@ pub const TSC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 I/O group x counter register + + /// I/O group x counter register pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { - CNT: u14, // bit offset: 0 desc: Counter value + /// Counter value + CNT: u14 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -2817,15 +4528,18 @@ pub const TSC = extern struct { padding1: u1 = 0, }); }; + +/// cyclic redundancy check calculation unit pub const CRC = extern struct { pub const Address: u32 = 0x40023000; - // byte offset: 0 Data register - pub const DR = mmio(Address + 0x00000000, 32, packed struct { - DR: u32, // bit offset: 0 desc: Data register bits - }); - // byte offset: 4 Independent data register + + /// Data register + pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + + /// Independent data register pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - IDR: u8, // bit offset: 0 desc: General-purpose 8-bit data register bits + /// General-purpose 8-bit data register bits + IDR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2851,14 +4565,19 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Control register + + /// Control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - RESET: u1, // bit offset: 0 desc: reset bit + /// reset bit + RESET: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - POLYSIZE: u2, // bit offset: 3 desc: Polynomial size - REV_IN: u2, // bit offset: 5 desc: Reverse input data - REV_OUT: u1, // bit offset: 7 desc: Reverse output data + /// Polynomial size + POLYSIZE: u2 = 0, + /// Reverse input data + REV_IN: u2 = 0, + /// Reverse output data + REV_OUT: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -2884,23 +4603,21 @@ pub const CRC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Initial CRC value - pub const INIT = mmio(Address + 0x00000010, 32, packed struct { - INIT: u32, // bit offset: 0 desc: Programmable initial CRC value - }); - // byte offset: 20 CRC polynomial - pub const POL = mmio(Address + 0x00000014, 32, packed struct { - POL: u32, // bit offset: 0 desc: Programmable polynomial - }); + + /// Initial CRC value + pub const INIT = @intToPtr(*volatile u32, Address + 0x00000010); + + /// CRC polynomial + pub const POL = @intToPtr(*volatile u32, Address + 0x00000014); }; + +/// Flash pub const Flash = extern struct { pub const Address: u32 = 0x40022000; - // byte offset: 0 Flash access control register + + /// Flash access control register pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - LATENCY: u3, // bit offset: 0 desc: LATENCY reserved1: u1 = 0, - PRFTBE: u1, // bit offset: 4 desc: PRFTBE - PRFTBS: u1, // bit offset: 5 desc: PRFTBS padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2928,22 +4645,28 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Flash key register + + /// Flash key register pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - FKEYR: u32, // bit offset: 0 desc: Flash Key + /// Flash Key + FKEYR: u32 = 0, }); - // byte offset: 8 Flash option key register - pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - OPTKEYR: u32, // bit offset: 0 desc: Option byte key - }); - // byte offset: 12 Flash status register + + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile u32, Address + 0x00000008); + + /// Flash status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - BSY: u1, // bit offset: 0 desc: Busy + /// Busy + BSY: u1 = 0, reserved1: u1 = 0, - PGERR: u1, // bit offset: 2 desc: Programming error + /// Programming error + PGERR: u1 = 0, reserved2: u1 = 0, - WRPRT: u1, // bit offset: 4 desc: Write protection error - EOP: u1, // bit offset: 5 desc: End of operation + /// Write protection error + WRPRT: u1 = 0, + /// End of operation + EOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -2971,22 +4694,34 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Flash control register + + /// Flash control register pub const CR = mmio(Address + 0x00000010, 32, packed struct { - PG: u1, // bit offset: 0 desc: Programming - PER: u1, // bit offset: 1 desc: Page erase - MER: u1, // bit offset: 2 desc: Mass erase - reserved1: u1 = 0, - OPTPG: u1, // bit offset: 4 desc: Option byte programming - OPTER: u1, // bit offset: 5 desc: Option byte erase - STRT: u1, // bit offset: 6 desc: Start - LOCK: u1, // bit offset: 7 desc: Lock - reserved2: u1 = 0, - OPTWRE: u1, // bit offset: 9 desc: Option bytes write enable - ERRIE: u1, // bit offset: 10 desc: Error interrupt enable + /// Programming + PG: u1 = 0, + /// Page erase + PER: u1 = 0, + /// Mass erase + MER: u1 = 0, + reserved1: u1 = 0, + /// Option byte programming + OPTPG: u1 = 0, + /// Option byte erase + OPTER: u1 = 0, + /// Start + STRT: u1 = 0, + /// Lock + LOCK: u1 = 0, + reserved2: u1 = 0, + /// Option bytes write enable + OPTWRE: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, reserved3: u1 = 0, - EOPIE: u1, // bit offset: 12 desc: End of operation interrupt enable - FORCE_OPTLOAD: u1, // bit offset: 13 desc: Force option byte loading + /// End of operation interrupt enable + EOPIE: u1 = 0, + /// Force option byte loading + FORCE_OPTLOAD: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3006,55 +4741,68 @@ pub const Flash = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Flash address register + + /// Flash address register pub const AR = mmio(Address + 0x00000014, 32, packed struct { - FAR: u32, // bit offset: 0 desc: Flash address + /// Flash address + FAR: u32 = 0, }); - // byte offset: 28 Option byte register + + /// Option byte register pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - OPTERR: u1, // bit offset: 0 desc: Option byte error - LEVEL1_PROT: u1, // bit offset: 1 desc: Level 1 protection status - LEVEL2_PROT: u1, // bit offset: 2 desc: Level 2 protection status + /// Option byte error + OPTERR: u1 = 0, + /// Level 1 protection status + LEVEL1_PROT: u1 = 0, + /// Level 2 protection status + LEVEL2_PROT: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - WDG_SW: u1, // bit offset: 8 desc: WDG_SW - nRST_STOP: u1, // bit offset: 9 desc: nRST_STOP - nRST_STDBY: u1, // bit offset: 10 desc: nRST_STDBY reserved6: u1 = 0, - BOOT1: u1, // bit offset: 12 desc: BOOT1 - VDDA_MONITOR: u1, // bit offset: 13 desc: VDDA_MONITOR - SRAM_PARITY_CHECK: u1, // bit offset: 14 desc: SRAM_PARITY_CHECK reserved7: u1 = 0, - Data0: u8, // bit offset: 16 desc: Data0 - Data1: u8, // bit offset: 24 desc: Data1 }); - // byte offset: 32 Write protection register + + /// Write protection register pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - WRP: u32, // bit offset: 0 desc: Write protect + /// Write protect + WRP: u32 = 0, }); }; + +/// Reset and clock control pub const RCC = extern struct { pub const Address: u32 = 0x40021000; - // byte offset: 0 Clock control register + + /// Clock control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - HSION: u1, // bit offset: 0 desc: Internal High Speed clock enable - HSIRDY: u1, // bit offset: 1 desc: Internal High Speed clock ready flag - reserved1: u1 = 0, - HSITRIM: u5, // bit offset: 3 desc: Internal High Speed clock trimming - HSICAL: u8, // bit offset: 8 desc: Internal High Speed clock Calibration - HSEON: u1, // bit offset: 16 desc: External High Speed clock enable - HSERDY: u1, // bit offset: 17 desc: External High Speed clock ready flag - HSEBYP: u1, // bit offset: 18 desc: External High Speed clock Bypass - CSSON: u1, // bit offset: 19 desc: Clock Security System enable + /// Internal High Speed clock enable + HSION: u1 = 0, + /// Internal High Speed clock ready flag + HSIRDY: u1 = 0, + reserved1: u1 = 0, + /// Internal High Speed clock trimming + HSITRIM: u5 = 0, + /// Internal High Speed clock Calibration + HSICAL: u8 = 0, + /// External High Speed clock enable + HSEON: u1 = 0, + /// External High Speed clock ready flag + HSERDY: u1 = 0, + /// External High Speed clock Bypass + HSEBYP: u1 = 0, + /// Clock Security System enable + CSSON: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - PLLON: u1, // bit offset: 24 desc: PLL enable - PLLRDY: u1, // bit offset: 25 desc: PLL clock ready flag + /// PLL enable + PLLON: u1 = 0, + /// PLL clock ready flag + PLLRDY: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -3062,52 +4810,83 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Clock configuration register (RCC_CFGR) + + /// Clock configuration register (RCC_CFGR) pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - SW: u2, // bit offset: 0 desc: System clock Switch - SWS: u2, // bit offset: 2 desc: System Clock Switch Status - HPRE: u4, // bit offset: 4 desc: AHB prescaler - PPRE1: u3, // bit offset: 8 desc: APB Low speed prescaler (APB1) - PPRE2: u3, // bit offset: 11 desc: APB high speed prescaler (APB2) - reserved1: u1 = 0, - PLLSRC: u2, // bit offset: 15 desc: PLL entry clock source - PLLXTPRE: u1, // bit offset: 17 desc: HSE divider for PLL entry - PLLMUL: u4, // bit offset: 18 desc: PLL Multiplication Factor - USBPRES: u1, // bit offset: 22 desc: USB prescaler - I2SSRC: u1, // bit offset: 23 desc: I2S external clock source selection - MCO: u3, // bit offset: 24 desc: Microcontroller clock output - reserved2: u1 = 0, - MCOF: u1, // bit offset: 28 desc: Microcontroller Clock Output Flag + /// System clock Switch + SW: u2 = 0, + /// System Clock Switch Status + SWS: u2 = 0, + /// AHB prescaler + HPRE: u4 = 0, + /// APB Low speed prescaler (APB1) + PPRE1: u3 = 0, + /// APB high speed prescaler (APB2) + PPRE2: u3 = 0, + reserved1: u1 = 0, + /// PLL entry clock source + PLLSRC: u2 = 0, + /// HSE divider for PLL entry + PLLXTPRE: u1 = 0, + /// PLL Multiplication Factor + PLLMUL: u4 = 0, + /// USB prescaler + USBPRES: u1 = 0, + /// I2S external clock source selection + I2SSRC: u1 = 0, + /// Microcontroller clock output + MCO: u3 = 0, + reserved2: u1 = 0, + /// Microcontroller Clock Output Flag + MCOF: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Clock interrupt register (RCC_CIR) + + /// Clock interrupt register (RCC_CIR) pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - LSIRDYF: u1, // bit offset: 0 desc: LSI Ready Interrupt flag - LSERDYF: u1, // bit offset: 1 desc: LSE Ready Interrupt flag - HSIRDYF: u1, // bit offset: 2 desc: HSI Ready Interrupt flag - HSERDYF: u1, // bit offset: 3 desc: HSE Ready Interrupt flag - PLLRDYF: u1, // bit offset: 4 desc: PLL Ready Interrupt flag - reserved2: u1 = 0, - reserved1: u1 = 0, - CSSF: u1, // bit offset: 7 desc: Clock Security System Interrupt flag - LSIRDYIE: u1, // bit offset: 8 desc: LSI Ready Interrupt Enable - LSERDYIE: u1, // bit offset: 9 desc: LSE Ready Interrupt Enable - HSIRDYIE: u1, // bit offset: 10 desc: HSI Ready Interrupt Enable - HSERDYIE: u1, // bit offset: 11 desc: HSE Ready Interrupt Enable - PLLRDYIE: u1, // bit offset: 12 desc: PLL Ready Interrupt Enable + /// LSI Ready Interrupt flag + LSIRDYF: u1 = 0, + /// LSE Ready Interrupt flag + LSERDYF: u1 = 0, + /// HSI Ready Interrupt flag + HSIRDYF: u1 = 0, + /// HSE Ready Interrupt flag + HSERDYF: u1 = 0, + /// PLL Ready Interrupt flag + PLLRDYF: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Clock Security System Interrupt flag + CSSF: u1 = 0, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1 = 0, + /// LSE Ready Interrupt Enable + LSERDYIE: u1 = 0, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1 = 0, + /// HSE Ready Interrupt Enable + HSERDYIE: u1 = 0, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSIRDYC: u1, // bit offset: 16 desc: LSI Ready Interrupt Clear - LSERDYC: u1, // bit offset: 17 desc: LSE Ready Interrupt Clear - HSIRDYC: u1, // bit offset: 18 desc: HSI Ready Interrupt Clear - HSERDYC: u1, // bit offset: 19 desc: HSE Ready Interrupt Clear - PLLRDYC: u1, // bit offset: 20 desc: PLL Ready Interrupt Clear + /// LSI Ready Interrupt Clear + LSIRDYC: u1 = 0, + /// LSE Ready Interrupt Clear + LSERDYC: u1 = 0, + /// HSI Ready Interrupt Clear + HSIRDYC: u1 = 0, + /// HSE Ready Interrupt Clear + HSERDYC: u1 = 0, + /// PLL Ready Interrupt Clear + PLLRDYC: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - CSSC: u1, // bit offset: 23 desc: Clock security system interrupt clear + /// Clock security system interrupt clear + CSSC: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3117,9 +4896,11 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB2 peripheral reset register (RCC_APB2RSTR) + + /// APB2 peripheral reset register (RCC_APB2RSTR) pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - SYSCFGRST: u1, // bit offset: 0 desc: SYSCFG and COMP reset + /// SYSCFG and COMP reset + SYSCFGRST: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3130,14 +4911,21 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM1RST: u1, // bit offset: 11 desc: TIM1 timer reset - SPI1RST: u1, // bit offset: 12 desc: SPI 1 reset - TIM8RST: u1, // bit offset: 13 desc: TIM8 timer reset - USART1RST: u1, // bit offset: 14 desc: USART1 reset + /// TIM1 timer reset + TIM1RST: u1 = 0, + /// SPI 1 reset + SPI1RST: u1 = 0, + /// TIM8 timer reset + TIM8RST: u1 = 0, + /// USART1 reset + USART1RST: u1 = 0, reserved11: u1 = 0, - TIM15RST: u1, // bit offset: 16 desc: TIM15 timer reset - TIM16RST: u1, // bit offset: 17 desc: TIM16 timer reset - TIM17RST: u1, // bit offset: 18 desc: TIM17 timer reset + /// TIM15 timer reset + TIM15RST: u1 = 0, + /// TIM16 timer reset + TIM16RST: u1 = 0, + /// TIM17 timer reset + TIM17RST: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3152,50 +4940,77 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 APB1 peripheral reset register (RCC_APB1RSTR) + + /// APB1 peripheral reset register (RCC_APB1RSTR) pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - TIM2RST: u1, // bit offset: 0 desc: Timer 2 reset - TIM3RST: u1, // bit offset: 1 desc: Timer 3 reset - TIM4RST: u1, // bit offset: 2 desc: Timer 14 reset - reserved1: u1 = 0, - TIM6RST: u1, // bit offset: 4 desc: Timer 6 reset - TIM7RST: u1, // bit offset: 5 desc: Timer 7 reset + /// Timer 2 reset + TIM2RST: u1 = 0, + /// Timer 3 reset + TIM3RST: u1 = 0, + /// Timer 14 reset + TIM4RST: u1 = 0, + reserved1: u1 = 0, + /// Timer 6 reset + TIM6RST: u1 = 0, + /// Timer 7 reset + TIM7RST: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - WWDGRST: u1, // bit offset: 11 desc: Window watchdog reset + /// Window watchdog reset + WWDGRST: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - SPI2RST: u1, // bit offset: 14 desc: SPI2 reset - SPI3RST: u1, // bit offset: 15 desc: SPI3 reset + /// SPI2 reset + SPI2RST: u1 = 0, + /// SPI3 reset + SPI3RST: u1 = 0, reserved9: u1 = 0, - USART2RST: u1, // bit offset: 17 desc: USART 2 reset - USART3RST: u1, // bit offset: 18 desc: USART3 reset - UART4RST: u1, // bit offset: 19 desc: UART 4 reset - UART5RST: u1, // bit offset: 20 desc: UART 5 reset - I2C1RST: u1, // bit offset: 21 desc: I2C1 reset - I2C2RST: u1, // bit offset: 22 desc: I2C2 reset - USBRST: u1, // bit offset: 23 desc: USB reset + /// USART 2 reset + USART2RST: u1 = 0, + /// USART3 reset + USART3RST: u1 = 0, + /// UART 4 reset + UART4RST: u1 = 0, + /// UART 5 reset + UART5RST: u1 = 0, + /// I2C1 reset + I2C1RST: u1 = 0, + /// I2C2 reset + I2C2RST: u1 = 0, + /// USB reset + USBRST: u1 = 0, reserved10: u1 = 0, - CANRST: u1, // bit offset: 25 desc: CAN reset + /// CAN reset + CANRST: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, - PWRRST: u1, // bit offset: 28 desc: Power interface reset - DACRST: u1, // bit offset: 29 desc: DAC interface reset - I2C3RST: u1, // bit offset: 30 desc: I2C3 reset + /// Power interface reset + PWRRST: u1 = 0, + /// DAC interface reset + DACRST: u1 = 0, + /// I2C3 reset + I2C3RST: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 AHB Peripheral Clock enable register (RCC_AHBENR) + + /// AHB Peripheral Clock enable register (RCC_AHBENR) pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMA1 clock enable - DMA2EN: u1, // bit offset: 1 desc: DMA2 clock enable - SRAMEN: u1, // bit offset: 2 desc: SRAM interface clock enable - reserved1: u1 = 0, - FLITFEN: u1, // bit offset: 4 desc: FLITF clock enable - FMCEN: u1, // bit offset: 5 desc: FMC clock enable - CRCEN: u1, // bit offset: 6 desc: CRC clock enable + /// DMA1 clock enable + DMAEN: u1 = 0, + /// DMA2 clock enable + DMA2EN: u1 = 0, + /// SRAM interface clock enable + SRAMEN: u1 = 0, + reserved1: u1 = 0, + /// FLITF clock enable + FLITFEN: u1 = 0, + /// FMC clock enable + FMCEN: u1 = 0, + /// CRC clock enable + CRCEN: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3205,26 +5020,39 @@ pub const RCC = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - IOPHEN: u1, // bit offset: 16 desc: IO port H clock enable - IOPAEN: u1, // bit offset: 17 desc: I/O port A clock enable - IOPBEN: u1, // bit offset: 18 desc: I/O port B clock enable - IOPCEN: u1, // bit offset: 19 desc: I/O port C clock enable - IOPDEN: u1, // bit offset: 20 desc: I/O port D clock enable - IOPEEN: u1, // bit offset: 21 desc: I/O port E clock enable - IOPFEN: u1, // bit offset: 22 desc: I/O port F clock enable - IOPGEN: u1, // bit offset: 23 desc: I/O port G clock enable - TSCEN: u1, // bit offset: 24 desc: Touch sensing controller clock enable + /// IO port H clock enable + IOPHEN: u1 = 0, + /// I/O port A clock enable + IOPAEN: u1 = 0, + /// I/O port B clock enable + IOPBEN: u1 = 0, + /// I/O port C clock enable + IOPCEN: u1 = 0, + /// I/O port D clock enable + IOPDEN: u1 = 0, + /// I/O port E clock enable + IOPEEN: u1 = 0, + /// I/O port F clock enable + IOPFEN: u1 = 0, + /// I/O port G clock enable + IOPGEN: u1 = 0, + /// Touch sensing controller clock enable + TSCEN: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, - ADC12EN: u1, // bit offset: 28 desc: ADC1 and ADC2 clock enable - ADC34EN: u1, // bit offset: 29 desc: ADC3 and ADC4 clock enable + /// ADC1 and ADC2 clock enable + ADC12EN: u1 = 0, + /// ADC3 and ADC4 clock enable + ADC34EN: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 APB2 peripheral clock enable register (RCC_APB2ENR) + + /// APB2 peripheral clock enable register (RCC_APB2ENR) pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - SYSCFGEN: u1, // bit offset: 0 desc: SYSCFG clock enable + /// SYSCFG clock enable + SYSCFGEN: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -3235,14 +5063,21 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIM1EN: u1, // bit offset: 11 desc: TIM1 Timer clock enable - SPI1EN: u1, // bit offset: 12 desc: SPI 1 clock enable - TIM8EN: u1, // bit offset: 13 desc: TIM8 Timer clock enable - USART1EN: u1, // bit offset: 14 desc: USART1 clock enable + /// TIM1 Timer clock enable + TIM1EN: u1 = 0, + /// SPI 1 clock enable + SPI1EN: u1 = 0, + /// TIM8 Timer clock enable + TIM8EN: u1 = 0, + /// USART1 clock enable + USART1EN: u1 = 0, reserved11: u1 = 0, - TIM15EN: u1, // bit offset: 16 desc: TIM15 timer clock enable - TIM16EN: u1, // bit offset: 17 desc: TIM16 timer clock enable - TIM17EN: u1, // bit offset: 18 desc: TIM17 timer clock enable + /// TIM15 timer clock enable + TIM15EN: u1 = 0, + /// TIM16 timer clock enable + TIM16EN: u1 = 0, + /// TIM17 timer clock enable + TIM17EN: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -3257,58 +5092,87 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 APB1 peripheral clock enable register (RCC_APB1ENR) + + /// APB1 peripheral clock enable register (RCC_APB1ENR) pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - TIM2EN: u1, // bit offset: 0 desc: Timer 2 clock enable - TIM3EN: u1, // bit offset: 1 desc: Timer 3 clock enable - TIM4EN: u1, // bit offset: 2 desc: Timer 4 clock enable - reserved1: u1 = 0, - TIM6EN: u1, // bit offset: 4 desc: Timer 6 clock enable - TIM7EN: u1, // bit offset: 5 desc: Timer 7 clock enable + /// Timer 2 clock enable + TIM2EN: u1 = 0, + /// Timer 3 clock enable + TIM3EN: u1 = 0, + /// Timer 4 clock enable + TIM4EN: u1 = 0, + reserved1: u1 = 0, + /// Timer 6 clock enable + TIM6EN: u1 = 0, + /// Timer 7 clock enable + TIM7EN: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - WWDGEN: u1, // bit offset: 11 desc: Window watchdog clock enable + /// Window watchdog clock enable + WWDGEN: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - SPI2EN: u1, // bit offset: 14 desc: SPI 2 clock enable - SPI3EN: u1, // bit offset: 15 desc: SPI 3 clock enable + /// SPI 2 clock enable + SPI2EN: u1 = 0, + /// SPI 3 clock enable + SPI3EN: u1 = 0, reserved9: u1 = 0, - USART2EN: u1, // bit offset: 17 desc: USART 2 clock enable - USART3EN: u1, // bit offset: 18 desc: USART 3 clock enable - USART4EN: u1, // bit offset: 19 desc: USART 4 clock enable - USART5EN: u1, // bit offset: 20 desc: USART 5 clock enable - I2C1EN: u1, // bit offset: 21 desc: I2C 1 clock enable - I2C2EN: u1, // bit offset: 22 desc: I2C 2 clock enable - USBEN: u1, // bit offset: 23 desc: USB clock enable + /// USART 2 clock enable + USART2EN: u1 = 0, + /// USART 3 clock enable + USART3EN: u1 = 0, + /// USART 4 clock enable + USART4EN: u1 = 0, + /// USART 5 clock enable + USART5EN: u1 = 0, + /// I2C 1 clock enable + I2C1EN: u1 = 0, + /// I2C 2 clock enable + I2C2EN: u1 = 0, + /// USB clock enable + USBEN: u1 = 0, reserved10: u1 = 0, - CANEN: u1, // bit offset: 25 desc: CAN clock enable - DAC2EN: u1, // bit offset: 26 desc: DAC2 interface clock enable + /// CAN clock enable + CANEN: u1 = 0, + /// DAC2 interface clock enable + DAC2EN: u1 = 0, reserved11: u1 = 0, - PWREN: u1, // bit offset: 28 desc: Power interface clock enable - DACEN: u1, // bit offset: 29 desc: DAC interface clock enable - I2C3EN: u1, // bit offset: 30 desc: I2C3 clock enable + /// Power interface clock enable + PWREN: u1 = 0, + /// DAC interface clock enable + DACEN: u1 = 0, + /// I2C3 clock enable + I2C3EN: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Backup domain control register (RCC_BDCR) + + /// Backup domain control register (RCC_BDCR) pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - LSEON: u1, // bit offset: 0 desc: External Low Speed oscillator enable - LSERDY: u1, // bit offset: 1 desc: External Low Speed oscillator ready - LSEBYP: u1, // bit offset: 2 desc: External Low Speed oscillator bypass - LSEDRV: u2, // bit offset: 3 desc: LSE oscillator drive capability + /// External Low Speed oscillator enable + LSEON: u1 = 0, + /// External Low Speed oscillator ready + LSERDY: u1 = 0, + /// External Low Speed oscillator bypass + LSEBYP: u1 = 0, + /// LSE oscillator drive capability + LSEDRV: u2 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RTCSEL: u2, // bit offset: 8 desc: RTC clock source selection + /// RTC clock source selection + RTCSEL: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - RTCEN: u1, // bit offset: 15 desc: RTC clock enable - BDRST: u1, // bit offset: 16 desc: Backup domain software reset + /// RTC clock enable + RTCEN: u1 = 0, + /// Backup domain software reset + BDRST: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -3325,10 +5189,13 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Control/status register (RCC_CSR) + + /// Control/status register (RCC_CSR) pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - LSION: u1, // bit offset: 0 desc: Internal low speed oscillator enable - LSIRDY: u1, // bit offset: 1 desc: Internal low speed oscillator ready + /// Internal low speed oscillator enable + LSION: u1 = 0, + /// Internal low speed oscillator ready + LSIRDY: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -3351,23 +5218,33 @@ pub const RCC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RMVF: u1, // bit offset: 24 desc: Remove reset flag - OBLRSTF: u1, // bit offset: 25 desc: Option byte loader reset flag - PINRSTF: u1, // bit offset: 26 desc: PIN reset flag - PORRSTF: u1, // bit offset: 27 desc: POR/PDR reset flag - SFTRSTF: u1, // bit offset: 28 desc: Software reset flag - IWDGRSTF: u1, // bit offset: 29 desc: Independent watchdog reset flag - WWDGRSTF: u1, // bit offset: 30 desc: Window watchdog reset flag - LPWRRSTF: u1, // bit offset: 31 desc: Low-power reset flag + /// Remove reset flag + RMVF: u1 = 0, + /// Option byte loader reset flag + OBLRSTF: u1 = 0, + /// PIN reset flag + PINRSTF: u1 = 0, + /// POR/PDR reset flag + PORRSTF: u1 = 0, + /// Software reset flag + SFTRSTF: u1 = 0, + /// Independent watchdog reset flag + IWDGRSTF: u1 = 0, + /// Window watchdog reset flag + WWDGRSTF: u1 = 0, + /// Low-power reset flag + LPWRRSTF: u1 = 0, }); - // byte offset: 40 AHB peripheral reset register + + /// AHB peripheral reset register pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMCRST: u1, // bit offset: 5 desc: FMC reset + /// FMC reset + FMCRST: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -3378,28 +5255,43 @@ pub const RCC = extern struct { reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - IOPHRST: u1, // bit offset: 16 desc: I/O port H reset - IOPARST: u1, // bit offset: 17 desc: I/O port A reset - IOPBRST: u1, // bit offset: 18 desc: I/O port B reset - IOPCRST: u1, // bit offset: 19 desc: I/O port C reset - IOPDRST: u1, // bit offset: 20 desc: I/O port D reset - IOPERST: u1, // bit offset: 21 desc: I/O port E reset - IOPFRST: u1, // bit offset: 22 desc: I/O port F reset - IOPGRST: u1, // bit offset: 23 desc: Touch sensing controller reset - TSCRST: u1, // bit offset: 24 desc: Touch sensing controller reset + /// I/O port H reset + IOPHRST: u1 = 0, + /// I/O port A reset + IOPARST: u1 = 0, + /// I/O port B reset + IOPBRST: u1 = 0, + /// I/O port C reset + IOPCRST: u1 = 0, + /// I/O port D reset + IOPDRST: u1 = 0, + /// I/O port E reset + IOPERST: u1 = 0, + /// I/O port F reset + IOPFRST: u1 = 0, + /// Touch sensing controller reset + IOPGRST: u1 = 0, + /// Touch sensing controller reset + TSCRST: u1 = 0, reserved18: u1 = 0, reserved17: u1 = 0, reserved16: u1 = 0, - ADC12RST: u1, // bit offset: 28 desc: ADC1 and ADC2 reset - ADC34RST: u1, // bit offset: 29 desc: ADC3 and ADC4 reset + /// ADC1 and ADC2 reset + ADC12RST: u1 = 0, + /// ADC3 and ADC4 reset + ADC34RST: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Clock configuration register 2 + + /// Clock configuration register 2 pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { - PREDIV: u4, // bit offset: 0 desc: PREDIV division factor - ADC12PRES: u5, // bit offset: 4 desc: ADC1 and ADC2 prescaler - ADC34PRES: u5, // bit offset: 9 desc: ADC3 and ADC4 prescaler + /// PREDIV division factor + PREDIV: u4 = 0, + /// ADC1 and ADC2 prescaler + ADC12PRES: u5 = 0, + /// ADC3 and ADC4 prescaler + ADC34PRES: u5 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -3419,27 +5311,38 @@ pub const RCC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 Clock configuration register 3 + + /// Clock configuration register 3 pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { - USART1SW: u2, // bit offset: 0 desc: USART1 clock source selection + /// USART1 clock source selection + USART1SW: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - I2C1SW: u1, // bit offset: 4 desc: I2C1 clock source selection - I2C2SW: u1, // bit offset: 5 desc: I2C2 clock source selection - I2C3SW: u1, // bit offset: 6 desc: I2C3 clock source selection + /// I2C1 clock source selection + I2C1SW: u1 = 0, + /// I2C2 clock source selection + I2C2SW: u1 = 0, + /// I2C3 clock source selection + I2C3SW: u1 = 0, reserved3: u1 = 0, - TIM1SW: u1, // bit offset: 8 desc: Timer1 clock source selection - TIM8SW: u1, // bit offset: 9 desc: Timer8 clock source selection + /// Timer1 clock source selection + TIM1SW: u1 = 0, + /// Timer8 clock source selection + TIM8SW: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - USART2SW: u2, // bit offset: 16 desc: USART2 clock source selection - USART3SW: u2, // bit offset: 18 desc: USART3 clock source selection - UART4SW: u2, // bit offset: 20 desc: UART4 clock source selection - UART5SW: u2, // bit offset: 22 desc: UART5 clock source selection + /// USART2 clock source selection + USART2SW: u2 = 0, + /// USART3 clock source selection + USART3SW: u2 = 0, + /// UART4 clock source selection + UART4SW: u2 = 0, + /// UART5 clock source selection + UART5SW: u2 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -3450,92 +5353,165 @@ pub const RCC = extern struct { padding1: u1 = 0, }); }; + +/// DMA controller 1 pub const DMA1 = extern struct { pub const Address: u32 = 0x40020000; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3554,9 +5530,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3574,28 +5552,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3614,9 +5609,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3634,28 +5631,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3674,9 +5688,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3694,28 +5710,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3734,9 +5767,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3754,28 +5789,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3794,9 +5846,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3814,28 +5868,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3854,9 +5925,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3874,28 +5947,45 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -3914,9 +6004,11 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -3934,101 +6026,178 @@ pub const DMA1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// DMA controller 1 pub const DMA2 = extern struct { pub const Address: u32 = 0x40020400; - // byte offset: 0 DMA interrupt status register (DMA_ISR) + + /// DMA interrupt status register (DMA_ISR) pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - GIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt flag - TCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete flag - HTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer Complete flag - TEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error flag - GIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt flag - TCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete flag - HTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer Complete flag - TEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error flag - GIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt flag - TCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete flag - HTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer Complete flag - TEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error flag - GIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt flag - TCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete flag - HTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer Complete flag - TEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error flag - GIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt flag - TCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete flag - HTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer Complete flag - TEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error flag - GIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt flag - TCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete flag - HTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer Complete flag - TEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error flag - GIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt flag - TCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete flag - HTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer Complete flag - TEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error flag - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA interrupt flag clear register (DMA_IFCR) + /// Channel 1 Global interrupt flag + GIF1: u1 = 0, + /// Channel 1 Transfer Complete flag + TCIF1: u1 = 0, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1 = 0, + /// Channel 1 Transfer Error flag + TEIF1: u1 = 0, + /// Channel 2 Global interrupt flag + GIF2: u1 = 0, + /// Channel 2 Transfer Complete flag + TCIF2: u1 = 0, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1 = 0, + /// Channel 2 Transfer Error flag + TEIF2: u1 = 0, + /// Channel 3 Global interrupt flag + GIF3: u1 = 0, + /// Channel 3 Transfer Complete flag + TCIF3: u1 = 0, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1 = 0, + /// Channel 3 Transfer Error flag + TEIF3: u1 = 0, + /// Channel 4 Global interrupt flag + GIF4: u1 = 0, + /// Channel 4 Transfer Complete flag + TCIF4: u1 = 0, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1 = 0, + /// Channel 4 Transfer Error flag + TEIF4: u1 = 0, + /// Channel 5 Global interrupt flag + GIF5: u1 = 0, + /// Channel 5 Transfer Complete flag + TCIF5: u1 = 0, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1 = 0, + /// Channel 5 Transfer Error flag + TEIF5: u1 = 0, + /// Channel 6 Global interrupt flag + GIF6: u1 = 0, + /// Channel 6 Transfer Complete flag + TCIF6: u1 = 0, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1 = 0, + /// Channel 6 Transfer Error flag + TEIF6: u1 = 0, + /// Channel 7 Global interrupt flag + GIF7: u1 = 0, + /// Channel 7 Transfer Complete flag + TCIF7: u1 = 0, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1 = 0, + /// Channel 7 Transfer Error flag + TEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA interrupt flag clear register (DMA_IFCR) pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - CGIF1: u1, // bit offset: 0 desc: Channel 1 Global interrupt clear - CTCIF1: u1, // bit offset: 1 desc: Channel 1 Transfer Complete clear - CHTIF1: u1, // bit offset: 2 desc: Channel 1 Half Transfer clear - CTEIF1: u1, // bit offset: 3 desc: Channel 1 Transfer Error clear - CGIF2: u1, // bit offset: 4 desc: Channel 2 Global interrupt clear - CTCIF2: u1, // bit offset: 5 desc: Channel 2 Transfer Complete clear - CHTIF2: u1, // bit offset: 6 desc: Channel 2 Half Transfer clear - CTEIF2: u1, // bit offset: 7 desc: Channel 2 Transfer Error clear - CGIF3: u1, // bit offset: 8 desc: Channel 3 Global interrupt clear - CTCIF3: u1, // bit offset: 9 desc: Channel 3 Transfer Complete clear - CHTIF3: u1, // bit offset: 10 desc: Channel 3 Half Transfer clear - CTEIF3: u1, // bit offset: 11 desc: Channel 3 Transfer Error clear - CGIF4: u1, // bit offset: 12 desc: Channel 4 Global interrupt clear - CTCIF4: u1, // bit offset: 13 desc: Channel 4 Transfer Complete clear - CHTIF4: u1, // bit offset: 14 desc: Channel 4 Half Transfer clear - CTEIF4: u1, // bit offset: 15 desc: Channel 4 Transfer Error clear - CGIF5: u1, // bit offset: 16 desc: Channel 5 Global interrupt clear - CTCIF5: u1, // bit offset: 17 desc: Channel 5 Transfer Complete clear - CHTIF5: u1, // bit offset: 18 desc: Channel 5 Half Transfer clear - CTEIF5: u1, // bit offset: 19 desc: Channel 5 Transfer Error clear - CGIF6: u1, // bit offset: 20 desc: Channel 6 Global interrupt clear - CTCIF6: u1, // bit offset: 21 desc: Channel 6 Transfer Complete clear - CHTIF6: u1, // bit offset: 22 desc: Channel 6 Half Transfer clear - CTEIF6: u1, // bit offset: 23 desc: Channel 6 Transfer Error clear - CGIF7: u1, // bit offset: 24 desc: Channel 7 Global interrupt clear - CTCIF7: u1, // bit offset: 25 desc: Channel 7 Transfer Complete clear - CHTIF7: u1, // bit offset: 26 desc: Channel 7 Half Transfer clear - CTEIF7: u1, // bit offset: 27 desc: Channel 7 Transfer Error clear - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel 1 Global interrupt clear + CGIF1: u1 = 0, + /// Channel 1 Transfer Complete clear + CTCIF1: u1 = 0, + /// Channel 1 Half Transfer clear + CHTIF1: u1 = 0, + /// Channel 1 Transfer Error clear + CTEIF1: u1 = 0, + /// Channel 2 Global interrupt clear + CGIF2: u1 = 0, + /// Channel 2 Transfer Complete clear + CTCIF2: u1 = 0, + /// Channel 2 Half Transfer clear + CHTIF2: u1 = 0, + /// Channel 2 Transfer Error clear + CTEIF2: u1 = 0, + /// Channel 3 Global interrupt clear + CGIF3: u1 = 0, + /// Channel 3 Transfer Complete clear + CTCIF3: u1 = 0, + /// Channel 3 Half Transfer clear + CHTIF3: u1 = 0, + /// Channel 3 Transfer Error clear + CTEIF3: u1 = 0, + /// Channel 4 Global interrupt clear + CGIF4: u1 = 0, + /// Channel 4 Transfer Complete clear + CTCIF4: u1 = 0, + /// Channel 4 Half Transfer clear + CHTIF4: u1 = 0, + /// Channel 4 Transfer Error clear + CTEIF4: u1 = 0, + /// Channel 5 Global interrupt clear + CGIF5: u1 = 0, + /// Channel 5 Transfer Complete clear + CTCIF5: u1 = 0, + /// Channel 5 Half Transfer clear + CHTIF5: u1 = 0, + /// Channel 5 Transfer Error clear + CTEIF5: u1 = 0, + /// Channel 6 Global interrupt clear + CGIF6: u1 = 0, + /// Channel 6 Transfer Complete clear + CTCIF6: u1 = 0, + /// Channel 6 Half Transfer clear + CHTIF6: u1 = 0, + /// Channel 6 Transfer Error clear + CTEIF6: u1 = 0, + /// Channel 7 Global interrupt clear + CGIF7: u1 = 0, + /// Channel 7 Transfer Complete clear + CTCIF7: u1 = 0, + /// Channel 7 Half Transfer clear + CHTIF7: u1 = 0, + /// Channel 7 Transfer Error clear + CTEIF7: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// DMA channel configuration register (DMA_CCR) + pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4047,9 +6216,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA channel 1 number of data register + + /// DMA channel 1 number of data register pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4067,28 +6238,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 DMA channel 1 peripheral address register + + /// DMA channel 1 peripheral address register pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 20 DMA channel 1 memory address register + + /// DMA channel 1 memory address register pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 28 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4107,9 +6295,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 DMA channel 2 number of data register + + /// DMA channel 2 number of data register pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4127,28 +6317,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DMA channel 2 peripheral address register + + /// DMA channel 2 peripheral address register pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 40 DMA channel 2 memory address register + + /// DMA channel 2 memory address register pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 48 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4167,9 +6374,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 DMA channel 3 number of data register + + /// DMA channel 3 number of data register pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4187,28 +6396,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 DMA channel 3 peripheral address register + + /// DMA channel 3 peripheral address register pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 60 DMA channel 3 memory address register + + /// DMA channel 3 memory address register pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 68 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4227,9 +6453,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA channel 4 number of data register + + /// DMA channel 4 number of data register pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4247,28 +6475,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA channel 4 peripheral address register + + /// DMA channel 4 peripheral address register pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 80 DMA channel 4 memory address register + + /// DMA channel 4 memory address register pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 88 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4287,9 +6532,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 92 DMA channel 5 number of data register + + /// DMA channel 5 number of data register pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4307,28 +6554,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 DMA channel 5 peripheral address register + + /// DMA channel 5 peripheral address register pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 100 DMA channel 5 memory address register + + /// DMA channel 5 memory address register pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 108 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4347,9 +6611,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 112 DMA channel 6 number of data register + + /// DMA channel 6 number of data register pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4367,28 +6633,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 116 DMA channel 6 peripheral address register + + /// DMA channel 6 peripheral address register pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 120 DMA channel 6 memory address register + + /// DMA channel 6 memory address register pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); - // byte offset: 128 DMA channel configuration register (DMA_CCR) + + /// DMA channel configuration register (DMA_CCR) pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - EN: u1, // bit offset: 0 desc: Channel enable - TCIE: u1, // bit offset: 1 desc: Transfer complete interrupt enable - HTIE: u1, // bit offset: 2 desc: Half Transfer interrupt enable - TEIE: u1, // bit offset: 3 desc: Transfer error interrupt enable - DIR: u1, // bit offset: 4 desc: Data transfer direction - CIRC: u1, // bit offset: 5 desc: Circular mode - PINC: u1, // bit offset: 6 desc: Peripheral increment mode - MINC: u1, // bit offset: 7 desc: Memory increment mode - PSIZE: u2, // bit offset: 8 desc: Peripheral size - MSIZE: u2, // bit offset: 10 desc: Memory size - PL: u2, // bit offset: 12 desc: Channel Priority level - MEM2MEM: u1, // bit offset: 14 desc: Memory to memory mode + /// Channel enable + EN: u1 = 0, + /// Transfer complete interrupt enable + TCIE: u1 = 0, + /// Half Transfer interrupt enable + HTIE: u1 = 0, + /// Transfer error interrupt enable + TEIE: u1 = 0, + /// Data transfer direction + DIR: u1 = 0, + /// Circular mode + CIRC: u1 = 0, + /// Peripheral increment mode + PINC: u1 = 0, + /// Memory increment mode + MINC: u1 = 0, + /// Peripheral size + PSIZE: u2 = 0, + /// Memory size + MSIZE: u2 = 0, + /// Channel Priority level + PL: u2 = 0, + /// Memory to memory mode + MEM2MEM: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4407,9 +6690,11 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 DMA channel 7 number of data register + + /// DMA channel 7 number of data register pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - NDT: u16, // bit offset: 0 desc: Number of data to transfer + /// Number of data to transfer + NDT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4427,29 +6712,45 @@ pub const DMA2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 DMA channel 7 peripheral address register + + /// DMA channel 7 peripheral address register pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - PA: u32, // bit offset: 0 desc: Peripheral address + /// Peripheral address + PA: u32 = 0, }); - // byte offset: 140 DMA channel 7 memory address register + + /// DMA channel 7 memory address register pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - MA: u32, // bit offset: 0 desc: Memory address + /// Memory address + MA: u32 = 0, }); }; + +/// General purpose timer pub const TIM2 = extern struct { pub const Address: u32 = 0x40000000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -4471,14 +6772,18 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -4504,17 +6809,27 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -4531,23 +6846,36 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -4566,21 +6894,32 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -4601,15 +6940,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -4636,19 +6982,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -4656,7 +7014,8 @@ pub const TIM2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -4665,14 +7024,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4690,19 +7056,31 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -4710,7 +7088,8 @@ pub const TIM2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -4719,14 +7098,21 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4744,24 +7130,37 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4779,15 +7178,22 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4805,38 +7211,56 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -4857,9 +7281,11 @@ pub const TIM2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -4878,20 +7304,32 @@ pub const TIM2 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM3 = extern struct { pub const Address: u32 = 0x40000400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -4913,14 +7351,18 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -4946,17 +7388,27 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -4973,23 +7425,36 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5008,21 +7473,32 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5043,15 +7519,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -5078,19 +7561,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5098,7 +7593,8 @@ pub const TIM3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5107,14 +7603,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5132,19 +7635,31 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5152,7 +7667,8 @@ pub const TIM3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5161,14 +7677,21 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5186,24 +7709,37 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5221,15 +7757,22 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5247,38 +7790,56 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5299,9 +7860,11 @@ pub const TIM3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5320,20 +7883,32 @@ pub const TIM3 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timer pub const TIM4 = extern struct { pub const Address: u32 = 0x40000800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5355,14 +7930,18 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5388,17 +7967,27 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -5415,23 +8004,36 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - reserved1: u1 = 0, - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - reserved2: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + reserved2: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, reserved3: u1 = 0, - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5450,21 +8052,32 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - reserved1: u1 = 0, - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + reserved1: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5485,15 +8098,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - reserved1: u1 = 0, - TG: u1, // bit offset: 6 desc: Trigger generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + reserved1: u1 = 0, + /// Trigger generation + TG: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -5520,19 +8140,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (output mode) + + /// capture/compare mode register 1 (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output compare 1 fast enable + OC1FE: u1 = 0, + /// Output compare 1 preload enable + OC1PE: u1 = 0, + /// Output compare 1 mode + OC1M: u3 = 0, + /// Output compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output compare 2 fast enable + OC2FE: u1 = 0, + /// Output compare 2 preload enable + OC2PE: u1 = 0, + /// Output compare 2 mode + OC2M: u3 = 0, + /// Output compare 2 clear enable + OC2CE: u1 = 0, + /// Output compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5540,7 +8172,8 @@ pub const TIM4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output compare 2 mode bit 3 + /// Output compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5549,14 +8182,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5574,19 +8214,31 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (output mode) + + /// capture/compare mode register 2 (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - O24CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output compare 3 mode bit3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + O24CE: u1 = 0, + /// Output compare 3 mode bit3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -5594,7 +8246,8 @@ pub const TIM4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output compare 4 mode bit3 + /// Output compare 4 mode bit3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5603,14 +8256,21 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5628,24 +8288,37 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - reserved1: u1 = 0, - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved2: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved2: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, reserved3: u1 = 0, - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, reserved4: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 3 output Polarity + /// Capture/Compare 3 output Polarity + CC4NP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5663,15 +8336,22 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNTL: u16, // bit offset: 0 desc: Low counter value - CNTH: u15, // bit offset: 16 desc: High counter value - CNT_or_UIFCPY: u1, // bit offset: 31 desc: if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + /// Low counter value + CNTL: u16 = 0, + /// High counter value + CNTH: u15 = 0, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5689,38 +8369,56 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARRL: u16, // bit offset: 0 desc: Low Auto-reload value - ARRH: u16, // bit offset: 16 desc: High Auto-reload value + /// Low Auto-reload value + ARRL: u16 = 0, + /// High Auto-reload value + ARRH: u16 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1L: u16, // bit offset: 0 desc: Low Capture/Compare 1 value - CCR1H: u16, // bit offset: 16 desc: High Capture/Compare 1 value (on TIM2) + /// Low Capture/Compare 1 value + CCR1L: u16 = 0, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2L: u16, // bit offset: 0 desc: Low Capture/Compare 2 value - CCR2H: u16, // bit offset: 16 desc: High Capture/Compare 2 value (on TIM2) + /// Low Capture/Compare 2 value + CCR2L: u16 = 0, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR3H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR3L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR3H: u16 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4L: u16, // bit offset: 0 desc: Low Capture/Compare value - CCR4H: u16, // bit offset: 16 desc: High Capture/Compare value (on TIM2) + /// Low Capture/Compare value + CCR4L: u16 = 0, + /// High Capture/Compare value (on TIM2) + CCR4H: u16 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -5741,9 +8439,11 @@ pub const TIM4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -5762,21 +8462,31 @@ pub const TIM4 = extern struct { padding1: u1 = 0, }); }; + +/// General purpose timers pub const TIM15 = extern struct { pub const Address: u32 = 0x40014000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -5798,17 +8508,26 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5831,12 +8550,16 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection + /// Slave mode selection + SMS: u3 = 0, reserved1: u1 = 0, - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -5845,7 +8568,8 @@ pub const TIM15 = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SMS_3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection bit 3 + SMS_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -5862,23 +8586,35 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - reserved2: u1 = 0, - reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -5897,19 +8633,28 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - reserved2: u1 = 0, - reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved3: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -5932,16 +8677,23 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - reserved2: u1 = 0, - reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -5967,19 +8719,29 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - reserved1: u1 = 0, - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - reserved2: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + reserved1: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + reserved2: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -5987,7 +8749,8 @@ pub const TIM15 = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -5996,14 +8759,21 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PSC: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PSC: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6021,16 +8791,24 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - reserved1: u1 = 0, - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6056,9 +8834,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -6074,11 +8854,14 @@ pub const TIM15 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6096,9 +8879,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6116,9 +8901,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6144,9 +8931,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6164,9 +8953,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6184,17 +8975,27 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -6208,13 +9009,16 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6235,9 +9039,11 @@ pub const TIM15 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6256,21 +9062,31 @@ pub const TIM15 = extern struct { padding1: u1 = 0, }); }; + +/// General-purpose-timers pub const TIM16 = extern struct { pub const Address: u32 = 0x40014400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -6292,18 +9108,24 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6327,23 +9149,33 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6362,18 +9194,25 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6397,16 +9236,22 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6432,12 +9277,17 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -6447,7 +9297,8 @@ pub const TIM16 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + /// Output Compare 1 mode + OC1M_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -6464,11 +9315,15 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6494,12 +9349,17 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -6529,9 +9389,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -6547,11 +9409,14 @@ pub const TIM16 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6569,9 +9434,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6589,9 +9456,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6617,9 +9486,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6637,17 +9508,27 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -6661,13 +9542,16 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -6688,9 +9572,11 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -6708,26 +9594,35 @@ pub const TIM16 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 option register - pub const OR = mmio(Address + 0x00000050, 32, packed struct { - raw: u32, // placeholder field - }); + + /// option register + pub const OR = @intToPtr(*volatile u32, Address + 0x00000050); }; + +/// General purpose timer pub const TIM17 = extern struct { pub const Address: u32 = 0x40014800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -6749,18 +9644,24 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control + /// Capture/compare preloaded control + CCPC: u1 = 0, reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6784,23 +9685,33 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -6819,18 +9730,25 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, reserved4: u1 = 0, - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -6854,16 +9772,22 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6889,12 +9813,17 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -6904,7 +9833,8 @@ pub const TIM17 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode + /// Output Compare 1 mode + OC1M_3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -6921,11 +9851,15 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PSC: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PSC: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -6951,12 +9885,17 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -6986,9 +9925,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -7004,11 +9945,14 @@ pub const TIM17 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7026,9 +9970,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7046,9 +9992,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u8, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -7074,9 +10022,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7094,17 +10044,27 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -7118,13 +10078,16 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -7145,9 +10108,11 @@ pub const TIM17 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7166,84 +10131,147 @@ pub const TIM17 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART1 = extern struct { pub const Address: u32 = 0x40013800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7254,10 +10282,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7275,10 +10306,13 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7296,18 +10330,27 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7336,31 +10379,54 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7371,29 +10437,42 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7406,9 +10485,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7433,9 +10514,11 @@ pub const USART1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7461,84 +10544,147 @@ pub const USART1 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART2 = extern struct { pub const Address: u32 = 0x40004400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7549,10 +10695,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7570,10 +10719,13 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7591,18 +10743,27 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7631,31 +10792,54 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7666,29 +10850,42 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7701,9 +10898,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7728,9 +10927,11 @@ pub const USART2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -7756,84 +10957,147 @@ pub const USART2 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const USART3 = extern struct { pub const Address: u32 = 0x40004800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7844,10 +11108,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7865,10 +11132,13 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -7886,18 +11156,27 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -7926,31 +11205,54 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -7961,29 +11263,42 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -7996,9 +11311,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8023,9 +11340,11 @@ pub const USART3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8051,84 +11370,147 @@ pub const USART3 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const UART4 = extern struct { pub const Address: u32 = 0x40004c00; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8139,10 +11521,13 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8160,10 +11545,13 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8181,18 +11569,27 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -8221,31 +11618,54 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8256,29 +11676,42 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8291,9 +11724,11 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8318,9 +11753,11 @@ pub const UART4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8346,84 +11783,147 @@ pub const UART4 = extern struct { padding1: u1 = 0, }); }; + +/// Universal synchronous asynchronous receiver transmitter pub const UART5 = extern struct { pub const Address: u32 = 0x40005000; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - UE: u1, // bit offset: 0 desc: USART enable - UESM: u1, // bit offset: 1 desc: USART enable in Stop mode - RE: u1, // bit offset: 2 desc: Receiver enable - TE: u1, // bit offset: 3 desc: Transmitter enable - IDLEIE: u1, // bit offset: 4 desc: IDLE interrupt enable - RXNEIE: u1, // bit offset: 5 desc: RXNE interrupt enable - TCIE: u1, // bit offset: 6 desc: Transmission complete interrupt enable - TXEIE: u1, // bit offset: 7 desc: interrupt enable - PEIE: u1, // bit offset: 8 desc: PE interrupt enable - PS: u1, // bit offset: 9 desc: Parity selection - PCE: u1, // bit offset: 10 desc: Parity control enable - WAKE: u1, // bit offset: 11 desc: Receiver wakeup method - M: u1, // bit offset: 12 desc: Word length - MME: u1, // bit offset: 13 desc: Mute mode enable - CMIE: u1, // bit offset: 14 desc: Character match interrupt enable - OVER8: u1, // bit offset: 15 desc: Oversampling mode - DEDT: u5, // bit offset: 16 desc: Driver Enable deassertion time - DEAT: u5, // bit offset: 21 desc: Driver Enable assertion time - RTOIE: u1, // bit offset: 26 desc: Receiver timeout interrupt enable - EOBIE: u1, // bit offset: 27 desc: End of Block interrupt enable - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control register 2 + /// USART enable + UE: u1 = 0, + /// USART enable in Stop mode + UESM: u1 = 0, + /// Receiver enable + RE: u1 = 0, + /// Transmitter enable + TE: u1 = 0, + /// IDLE interrupt enable + IDLEIE: u1 = 0, + /// RXNE interrupt enable + RXNEIE: u1 = 0, + /// Transmission complete interrupt enable + TCIE: u1 = 0, + /// interrupt enable + TXEIE: u1 = 0, + /// PE interrupt enable + PEIE: u1 = 0, + /// Parity selection + PS: u1 = 0, + /// Parity control enable + PCE: u1 = 0, + /// Receiver wakeup method + WAKE: u1 = 0, + /// Word length + M: u1 = 0, + /// Mute mode enable + MME: u1 = 0, + /// Character match interrupt enable + CMIE: u1 = 0, + /// Oversampling mode + OVER8: u1 = 0, + /// Driver Enable deassertion time + DEDT: u5 = 0, + /// Driver Enable assertion time + DEAT: u5 = 0, + /// Receiver timeout interrupt enable + RTOIE: u1 = 0, + /// End of Block interrupt enable + EOBIE: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDM7: u1, // bit offset: 4 desc: 7-bit Address Detection/4-bit Address Detection - LBDL: u1, // bit offset: 5 desc: LIN break detection length - LBDIE: u1, // bit offset: 6 desc: LIN break detection interrupt enable + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1 = 0, + /// LIN break detection length + LBDL: u1 = 0, + /// LIN break detection interrupt enable + LBDIE: u1 = 0, reserved5: u1 = 0, - LBCL: u1, // bit offset: 8 desc: Last bit clock pulse - CPHA: u1, // bit offset: 9 desc: Clock phase - CPOL: u1, // bit offset: 10 desc: Clock polarity - CLKEN: u1, // bit offset: 11 desc: Clock enable - STOP: u2, // bit offset: 12 desc: STOP bits - LINEN: u1, // bit offset: 14 desc: LIN mode enable - SWAP: u1, // bit offset: 15 desc: Swap TX/RX pins - RXINV: u1, // bit offset: 16 desc: RX pin active level inversion - TXINV: u1, // bit offset: 17 desc: TX pin active level inversion - DATAINV: u1, // bit offset: 18 desc: Binary data inversion - MSBFIRST: u1, // bit offset: 19 desc: Most significant bit first - ABREN: u1, // bit offset: 20 desc: Auto baud rate enable - ABRMOD: u2, // bit offset: 21 desc: Auto baud rate mode - RTOEN: u1, // bit offset: 23 desc: Receiver timeout enable - ADD0: u4, // bit offset: 24 desc: Address of the USART node - ADD4: u4, // bit offset: 28 desc: Address of the USART node - }); - // byte offset: 8 Control register 3 + /// Last bit clock pulse + LBCL: u1 = 0, + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Clock enable + CLKEN: u1 = 0, + /// STOP bits + STOP: u2 = 0, + /// LIN mode enable + LINEN: u1 = 0, + /// Swap TX/RX pins + SWAP: u1 = 0, + /// RX pin active level inversion + RXINV: u1 = 0, + /// TX pin active level inversion + TXINV: u1 = 0, + /// Binary data inversion + DATAINV: u1 = 0, + /// Most significant bit first + MSBFIRST: u1 = 0, + /// Auto baud rate enable + ABREN: u1 = 0, + /// Auto baud rate mode + ABRMOD: u2 = 0, + /// Receiver timeout enable + RTOEN: u1 = 0, + /// Address of the USART node + ADD0: u4 = 0, + /// Address of the USART node + ADD4: u4 = 0, + }); + + /// Control register 3 pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - EIE: u1, // bit offset: 0 desc: Error interrupt enable - IREN: u1, // bit offset: 1 desc: IrDA mode enable - IRLP: u1, // bit offset: 2 desc: IrDA low-power - HDSEL: u1, // bit offset: 3 desc: Half-duplex selection - NACK: u1, // bit offset: 4 desc: Smartcard NACK enable - SCEN: u1, // bit offset: 5 desc: Smartcard mode enable - DMAR: u1, // bit offset: 6 desc: DMA enable receiver - DMAT: u1, // bit offset: 7 desc: DMA enable transmitter - RTSE: u1, // bit offset: 8 desc: RTS enable - CTSE: u1, // bit offset: 9 desc: CTS enable - CTSIE: u1, // bit offset: 10 desc: CTS interrupt enable - ONEBIT: u1, // bit offset: 11 desc: One sample bit method enable - OVRDIS: u1, // bit offset: 12 desc: Overrun Disable - DDRE: u1, // bit offset: 13 desc: DMA Disable on Reception Error - DEM: u1, // bit offset: 14 desc: Driver enable mode - DEP: u1, // bit offset: 15 desc: Driver enable polarity selection - reserved1: u1 = 0, - SCARCNT: u3, // bit offset: 17 desc: Smartcard auto-retry count - WUS: u2, // bit offset: 20 desc: Wakeup from Stop mode interrupt flag selection - WUFIE: u1, // bit offset: 22 desc: Wakeup from Stop mode interrupt enable + /// Error interrupt enable + EIE: u1 = 0, + /// IrDA mode enable + IREN: u1 = 0, + /// IrDA low-power + IRLP: u1 = 0, + /// Half-duplex selection + HDSEL: u1 = 0, + /// Smartcard NACK enable + NACK: u1 = 0, + /// Smartcard mode enable + SCEN: u1 = 0, + /// DMA enable receiver + DMAR: u1 = 0, + /// DMA enable transmitter + DMAT: u1 = 0, + /// RTS enable + RTSE: u1 = 0, + /// CTS enable + CTSE: u1 = 0, + /// CTS interrupt enable + CTSIE: u1 = 0, + /// One sample bit method enable + ONEBIT: u1 = 0, + /// Overrun Disable + OVRDIS: u1 = 0, + /// DMA Disable on Reception Error + DDRE: u1 = 0, + /// Driver enable mode + DEM: u1 = 0, + /// Driver enable polarity selection + DEP: u1 = 0, + reserved1: u1 = 0, + /// Smartcard auto-retry count + SCARCNT: u3 = 0, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2 = 0, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8434,10 +11934,13 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Baud rate register + + /// Baud rate register pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - DIV_Fraction: u4, // bit offset: 0 desc: fraction of USARTDIV - DIV_Mantissa: u12, // bit offset: 4 desc: mantissa of USARTDIV + /// fraction of USARTDIV + DIV_Fraction: u4 = 0, + /// mantissa of USARTDIV + DIV_Mantissa: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8455,10 +11958,13 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Guard time and prescaler register + + /// Guard time and prescaler register pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - PSC: u8, // bit offset: 0 desc: Prescaler value - GT: u8, // bit offset: 8 desc: Guard time value + /// Prescaler value + PSC: u8 = 0, + /// Guard time value + GT: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8476,18 +11982,27 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Receiver timeout register + + /// Receiver timeout register pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - RTO: u24, // bit offset: 0 desc: Receiver timeout value - BLEN: u8, // bit offset: 24 desc: Block Length + /// Receiver timeout value + RTO: u24 = 0, + /// Block Length + BLEN: u8 = 0, }); - // byte offset: 24 Request register + + /// Request register pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - ABRRQ: u1, // bit offset: 0 desc: Auto baud rate request - SBKRQ: u1, // bit offset: 1 desc: Send break request - MMRQ: u1, // bit offset: 2 desc: Mute mode request - RXFRQ: u1, // bit offset: 3 desc: Receive data flush request - TXFRQ: u1, // bit offset: 4 desc: Transmit data flush request + /// Auto baud rate request + ABRRQ: u1 = 0, + /// Send break request + SBKRQ: u1 = 0, + /// Mute mode request + MMRQ: u1 = 0, + /// Receive data flush request + RXFRQ: u1 = 0, + /// Transmit data flush request + TXFRQ: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -8516,31 +12031,54 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt & status register + + /// Interrupt & status register pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - PE: u1, // bit offset: 0 desc: Parity error - FE: u1, // bit offset: 1 desc: Framing error - NF: u1, // bit offset: 2 desc: Noise detected flag - ORE: u1, // bit offset: 3 desc: Overrun error - IDLE: u1, // bit offset: 4 desc: Idle line detected - RXNE: u1, // bit offset: 5 desc: Read data register not empty - TC: u1, // bit offset: 6 desc: Transmission complete - TXE: u1, // bit offset: 7 desc: Transmit data register empty - LBDF: u1, // bit offset: 8 desc: LIN break detection flag - CTSIF: u1, // bit offset: 9 desc: CTS interrupt flag - CTS: u1, // bit offset: 10 desc: CTS flag - RTOF: u1, // bit offset: 11 desc: Receiver timeout - EOBF: u1, // bit offset: 12 desc: End of block flag - reserved1: u1 = 0, - ABRE: u1, // bit offset: 14 desc: Auto baud rate error - ABRF: u1, // bit offset: 15 desc: Auto baud rate flag - BUSY: u1, // bit offset: 16 desc: Busy flag - CMF: u1, // bit offset: 17 desc: character match flag - SBKF: u1, // bit offset: 18 desc: Send break flag - RWU: u1, // bit offset: 19 desc: Receiver wakeup from Mute mode - WUF: u1, // bit offset: 20 desc: Wakeup from Stop mode flag - TEACK: u1, // bit offset: 21 desc: Transmit enable acknowledge flag - REACK: u1, // bit offset: 22 desc: Receive enable acknowledge flag + /// Parity error + PE: u1 = 0, + /// Framing error + FE: u1 = 0, + /// Noise detected flag + NF: u1 = 0, + /// Overrun error + ORE: u1 = 0, + /// Idle line detected + IDLE: u1 = 0, + /// Read data register not empty + RXNE: u1 = 0, + /// Transmission complete + TC: u1 = 0, + /// Transmit data register empty + TXE: u1 = 0, + /// LIN break detection flag + LBDF: u1 = 0, + /// CTS interrupt flag + CTSIF: u1 = 0, + /// CTS flag + CTS: u1 = 0, + /// Receiver timeout + RTOF: u1 = 0, + /// End of block flag + EOBF: u1 = 0, + reserved1: u1 = 0, + /// Auto baud rate error + ABRE: u1 = 0, + /// Auto baud rate flag + ABRF: u1 = 0, + /// Busy flag + BUSY: u1 = 0, + /// character match flag + CMF: u1 = 0, + /// Send break flag + SBKF: u1 = 0, + /// Receiver wakeup from Mute mode + RWU: u1 = 0, + /// Wakeup from Stop mode flag + WUF: u1 = 0, + /// Transmit enable acknowledge flag + TEACK: u1 = 0, + /// Receive enable acknowledge flag + REACK: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -8551,29 +12089,42 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Interrupt flag clear register + + /// Interrupt flag clear register pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - PECF: u1, // bit offset: 0 desc: Parity error clear flag - FECF: u1, // bit offset: 1 desc: Framing error clear flag - NCF: u1, // bit offset: 2 desc: Noise detected clear flag - ORECF: u1, // bit offset: 3 desc: Overrun error clear flag - IDLECF: u1, // bit offset: 4 desc: Idle line detected clear flag - reserved1: u1 = 0, - TCCF: u1, // bit offset: 6 desc: Transmission complete clear flag - reserved2: u1 = 0, - LBDCF: u1, // bit offset: 8 desc: LIN break detection clear flag - CTSCF: u1, // bit offset: 9 desc: CTS clear flag + /// Parity error clear flag + PECF: u1 = 0, + /// Framing error clear flag + FECF: u1 = 0, + /// Noise detected clear flag + NCF: u1 = 0, + /// Overrun error clear flag + ORECF: u1 = 0, + /// Idle line detected clear flag + IDLECF: u1 = 0, + reserved1: u1 = 0, + /// Transmission complete clear flag + TCCF: u1 = 0, + reserved2: u1 = 0, + /// LIN break detection clear flag + LBDCF: u1 = 0, + /// CTS clear flag + CTSCF: u1 = 0, reserved3: u1 = 0, - RTOCF: u1, // bit offset: 11 desc: Receiver timeout clear flag - EOBCF: u1, // bit offset: 12 desc: End of timeout clear flag + /// Receiver timeout clear flag + RTOCF: u1 = 0, + /// End of timeout clear flag + EOBCF: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - CMCF: u1, // bit offset: 17 desc: Character match clear flag + /// Character match clear flag + CMCF: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - WUCF: u1, // bit offset: 20 desc: Wakeup from Stop mode clear flag + /// Wakeup from Stop mode clear flag + WUCF: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -8586,9 +12137,11 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - RDR: u9, // bit offset: 0 desc: Receive data value + /// Receive data value + RDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8613,9 +12166,11 @@ pub const UART5 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - TDR: u9, // bit offset: 0 desc: Transmit data value + /// Transmit data value + TDR: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -8641,24 +12196,41 @@ pub const UART5 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI1 = extern struct { pub const Address: u32 = 0x40013000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8676,20 +12248,33 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8708,19 +12293,31 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8741,9 +12338,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8761,9 +12360,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8781,9 +12382,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8801,9 +12404,11 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8821,17 +12426,26 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -8853,11 +12467,15 @@ pub const SPI1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -8882,24 +12500,41 @@ pub const SPI1 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI2 = extern struct { pub const Address: u32 = 0x40003800; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -8917,20 +12552,33 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -8949,19 +12597,31 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -8982,9 +12642,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9002,9 +12664,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9022,9 +12686,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9042,9 +12708,11 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9062,17 +12730,26 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9094,11 +12771,15 @@ pub const SPI2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9123,24 +12804,41 @@ pub const SPI2 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI3 = extern struct { pub const Address: u32 = 0x40003c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9158,20 +12856,33 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9190,19 +12901,31 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9223,9 +12946,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9243,9 +12968,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9263,9 +12990,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9283,9 +13012,11 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9303,17 +13034,26 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9335,11 +13075,15 @@ pub const SPI3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9364,24 +13108,41 @@ pub const SPI3 = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const I2S2ext = extern struct { pub const Address: u32 = 0x40003400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9399,20 +13160,33 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9431,19 +13205,31 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9464,9 +13250,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9484,9 +13272,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9504,9 +13294,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9524,9 +13316,11 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9544,17 +13338,26 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9576,11 +13379,15 @@ pub const I2S2ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9605,24 +13412,41 @@ pub const I2S2ext = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const I2S3ext = extern struct { pub const Address: u32 = 0x40004000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9640,20 +13464,33 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9672,19 +13509,31 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9705,9 +13554,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9725,9 +13576,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9745,9 +13598,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9765,9 +13620,11 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9785,17 +13642,26 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -9817,11 +13683,15 @@ pub const I2S3ext = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -9846,24 +13716,41 @@ pub const I2S3ext = extern struct { padding1: u1 = 0, }); }; + +/// Serial peripheral interface/Inter-IC sound pub const SPI4 = extern struct { pub const Address: u32 = 0x40013c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CPHA: u1, // bit offset: 0 desc: Clock phase - CPOL: u1, // bit offset: 1 desc: Clock polarity - MSTR: u1, // bit offset: 2 desc: Master selection - BR: u3, // bit offset: 3 desc: Baud rate control - SPE: u1, // bit offset: 6 desc: SPI enable - LSBFIRST: u1, // bit offset: 7 desc: Frame format - SSI: u1, // bit offset: 8 desc: Internal slave select - SSM: u1, // bit offset: 9 desc: Software slave management - RXONLY: u1, // bit offset: 10 desc: Receive only - CRCL: u1, // bit offset: 11 desc: CRC length - CRCNEXT: u1, // bit offset: 12 desc: CRC transfer next - CRCEN: u1, // bit offset: 13 desc: Hardware CRC calculation enable - BIDIOE: u1, // bit offset: 14 desc: Output enable in bidirectional mode - BIDIMODE: u1, // bit offset: 15 desc: Bidirectional data mode enable + /// Clock phase + CPHA: u1 = 0, + /// Clock polarity + CPOL: u1 = 0, + /// Master selection + MSTR: u1 = 0, + /// Baud rate control + BR: u3 = 0, + /// SPI enable + SPE: u1 = 0, + /// Frame format + LSBFIRST: u1 = 0, + /// Internal slave select + SSI: u1 = 0, + /// Software slave management + SSM: u1 = 0, + /// Receive only + RXONLY: u1 = 0, + /// CRC length + CRCL: u1 = 0, + /// CRC transfer next + CRCNEXT: u1 = 0, + /// Hardware CRC calculation enable + CRCEN: u1 = 0, + /// Output enable in bidirectional mode + BIDIOE: u1 = 0, + /// Bidirectional data mode enable + BIDIMODE: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9881,20 +13768,33 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - RXDMAEN: u1, // bit offset: 0 desc: Rx buffer DMA enable - TXDMAEN: u1, // bit offset: 1 desc: Tx buffer DMA enable - SSOE: u1, // bit offset: 2 desc: SS output enable - NSSP: u1, // bit offset: 3 desc: NSS pulse management - FRF: u1, // bit offset: 4 desc: Frame format - ERRIE: u1, // bit offset: 5 desc: Error interrupt enable - RXNEIE: u1, // bit offset: 6 desc: RX buffer not empty interrupt enable - TXEIE: u1, // bit offset: 7 desc: Tx buffer empty interrupt enable - DS: u4, // bit offset: 8 desc: Data size - FRXTH: u1, // bit offset: 12 desc: FIFO reception threshold - LDMA_RX: u1, // bit offset: 13 desc: Last DMA transfer for reception - LDMA_TX: u1, // bit offset: 14 desc: Last DMA transfer for transmission + /// Rx buffer DMA enable + RXDMAEN: u1 = 0, + /// Tx buffer DMA enable + TXDMAEN: u1 = 0, + /// SS output enable + SSOE: u1 = 0, + /// NSS pulse management + NSSP: u1 = 0, + /// Frame format + FRF: u1 = 0, + /// Error interrupt enable + ERRIE: u1 = 0, + /// RX buffer not empty interrupt enable + RXNEIE: u1 = 0, + /// Tx buffer empty interrupt enable + TXEIE: u1 = 0, + /// Data size + DS: u4 = 0, + /// FIFO reception threshold + FRXTH: u1 = 0, + /// Last DMA transfer for reception + LDMA_RX: u1 = 0, + /// Last DMA transfer for transmission + LDMA_TX: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -9913,19 +13813,31 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 status register + + /// status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - RXNE: u1, // bit offset: 0 desc: Receive buffer not empty - TXE: u1, // bit offset: 1 desc: Transmit buffer empty - CHSIDE: u1, // bit offset: 2 desc: Channel side - UDR: u1, // bit offset: 3 desc: Underrun flag - CRCERR: u1, // bit offset: 4 desc: CRC error flag - MODF: u1, // bit offset: 5 desc: Mode fault - OVR: u1, // bit offset: 6 desc: Overrun flag - BSY: u1, // bit offset: 7 desc: Busy flag - TIFRFE: u1, // bit offset: 8 desc: TI frame format error - FRLVL: u2, // bit offset: 9 desc: FIFO reception level - FTLVL: u2, // bit offset: 11 desc: FIFO transmission level + /// Receive buffer not empty + RXNE: u1 = 0, + /// Transmit buffer empty + TXE: u1 = 0, + /// Channel side + CHSIDE: u1 = 0, + /// Underrun flag + UDR: u1 = 0, + /// CRC error flag + CRCERR: u1 = 0, + /// Mode fault + MODF: u1 = 0, + /// Overrun flag + OVR: u1 = 0, + /// Busy flag + BSY: u1 = 0, + /// TI frame format error + TIFRFE: u1 = 0, + /// FIFO reception level + FRLVL: u2 = 0, + /// FIFO transmission level + FTLVL: u2 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -9946,9 +13858,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 data register + + /// data register pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - DR: u16, // bit offset: 0 desc: Data register + /// Data register + DR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9966,9 +13880,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 CRC polynomial register + + /// CRC polynomial register pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - CRCPOLY: u16, // bit offset: 0 desc: CRC polynomial register + /// CRC polynomial register + CRCPOLY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -9986,9 +13902,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 RX CRC register + + /// RX CRC register pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - RxCRC: u16, // bit offset: 0 desc: Rx CRC register + /// Rx CRC register + RxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10006,9 +13924,11 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 TX CRC register + + /// TX CRC register pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - TxCRC: u16, // bit offset: 0 desc: Tx CRC register + /// Tx CRC register + TxCRC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -10026,17 +13946,26 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 I2S configuration register + + /// I2S configuration register pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - CHLEN: u1, // bit offset: 0 desc: Channel length (number of bits per audio channel) - DATLEN: u2, // bit offset: 1 desc: Data length to be transferred - CKPOL: u1, // bit offset: 3 desc: Steady state clock polarity - I2SSTD: u2, // bit offset: 4 desc: I2S standard selection - reserved1: u1 = 0, - PCMSYNC: u1, // bit offset: 7 desc: PCM frame synchronization - I2SCFG: u2, // bit offset: 8 desc: I2S configuration mode - I2SE: u1, // bit offset: 10 desc: I2S Enable - I2SMOD: u1, // bit offset: 11 desc: I2S mode selection + /// Channel length (number of bits per audio channel) + CHLEN: u1 = 0, + /// Data length to be transferred + DATLEN: u2 = 0, + /// Steady state clock polarity + CKPOL: u1 = 0, + /// I2S standard selection + I2SSTD: u2 = 0, + reserved1: u1 = 0, + /// PCM frame synchronization + PCMSYNC: u1 = 0, + /// I2S configuration mode + I2SCFG: u2 = 0, + /// I2S Enable + I2SE: u1 = 0, + /// I2S mode selection + I2SMOD: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -10058,11 +13987,15 @@ pub const SPI4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 I2S prescaler register + + /// I2S prescaler register pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - I2SDIV: u8, // bit offset: 0 desc: I2S Linear prescaler - ODD: u1, // bit offset: 8 desc: Odd factor for the prescaler - MCKOE: u1, // bit offset: 9 desc: Master clock output enable + /// I2S Linear prescaler + I2SDIV: u8 = 0, + /// Odd factor for the prescaler + ODD: u1 = 0, + /// Master clock output enable + MCKOE: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10087,224 +14020,405 @@ pub const SPI4 = extern struct { padding1: u1 = 0, }); }; + +/// External interrupt/event controller pub const EXTI = extern struct { pub const Address: u32 = 0x40010400; - // byte offset: 0 Interrupt mask register + + /// Interrupt mask register pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Interrupt Mask on line 0 - MR1: u1, // bit offset: 1 desc: Interrupt Mask on line 1 - MR2: u1, // bit offset: 2 desc: Interrupt Mask on line 2 - MR3: u1, // bit offset: 3 desc: Interrupt Mask on line 3 - MR4: u1, // bit offset: 4 desc: Interrupt Mask on line 4 - MR5: u1, // bit offset: 5 desc: Interrupt Mask on line 5 - MR6: u1, // bit offset: 6 desc: Interrupt Mask on line 6 - MR7: u1, // bit offset: 7 desc: Interrupt Mask on line 7 - MR8: u1, // bit offset: 8 desc: Interrupt Mask on line 8 - MR9: u1, // bit offset: 9 desc: Interrupt Mask on line 9 - MR10: u1, // bit offset: 10 desc: Interrupt Mask on line 10 - MR11: u1, // bit offset: 11 desc: Interrupt Mask on line 11 - MR12: u1, // bit offset: 12 desc: Interrupt Mask on line 12 - MR13: u1, // bit offset: 13 desc: Interrupt Mask on line 13 - MR14: u1, // bit offset: 14 desc: Interrupt Mask on line 14 - MR15: u1, // bit offset: 15 desc: Interrupt Mask on line 15 - MR16: u1, // bit offset: 16 desc: Interrupt Mask on line 16 - MR17: u1, // bit offset: 17 desc: Interrupt Mask on line 17 - MR18: u1, // bit offset: 18 desc: Interrupt Mask on line 18 - MR19: u1, // bit offset: 19 desc: Interrupt Mask on line 19 - MR20: u1, // bit offset: 20 desc: Interrupt Mask on line 20 - MR21: u1, // bit offset: 21 desc: Interrupt Mask on line 21 - MR22: u1, // bit offset: 22 desc: Interrupt Mask on line 22 - MR23: u1, // bit offset: 23 desc: Interrupt Mask on line 23 - MR24: u1, // bit offset: 24 desc: Interrupt Mask on line 24 - MR25: u1, // bit offset: 25 desc: Interrupt Mask on line 25 - MR26: u1, // bit offset: 26 desc: Interrupt Mask on line 26 - MR27: u1, // bit offset: 27 desc: Interrupt Mask on line 27 - MR28: u1, // bit offset: 28 desc: Interrupt Mask on line 28 - MR29: u1, // bit offset: 29 desc: Interrupt Mask on line 29 - MR30: u1, // bit offset: 30 desc: Interrupt Mask on line 30 - MR31: u1, // bit offset: 31 desc: Interrupt Mask on line 31 - }); - // byte offset: 4 Event mask register + /// Interrupt Mask on line 0 + MR0: u1 = 0, + /// Interrupt Mask on line 1 + MR1: u1 = 0, + /// Interrupt Mask on line 2 + MR2: u1 = 0, + /// Interrupt Mask on line 3 + MR3: u1 = 0, + /// Interrupt Mask on line 4 + MR4: u1 = 0, + /// Interrupt Mask on line 5 + MR5: u1 = 0, + /// Interrupt Mask on line 6 + MR6: u1 = 0, + /// Interrupt Mask on line 7 + MR7: u1 = 0, + /// Interrupt Mask on line 8 + MR8: u1 = 0, + /// Interrupt Mask on line 9 + MR9: u1 = 0, + /// Interrupt Mask on line 10 + MR10: u1 = 0, + /// Interrupt Mask on line 11 + MR11: u1 = 0, + /// Interrupt Mask on line 12 + MR12: u1 = 0, + /// Interrupt Mask on line 13 + MR13: u1 = 0, + /// Interrupt Mask on line 14 + MR14: u1 = 0, + /// Interrupt Mask on line 15 + MR15: u1 = 0, + /// Interrupt Mask on line 16 + MR16: u1 = 0, + /// Interrupt Mask on line 17 + MR17: u1 = 0, + /// Interrupt Mask on line 18 + MR18: u1 = 0, + /// Interrupt Mask on line 19 + MR19: u1 = 0, + /// Interrupt Mask on line 20 + MR20: u1 = 0, + /// Interrupt Mask on line 21 + MR21: u1 = 0, + /// Interrupt Mask on line 22 + MR22: u1 = 0, + /// Interrupt Mask on line 23 + MR23: u1 = 0, + /// Interrupt Mask on line 24 + MR24: u1 = 0, + /// Interrupt Mask on line 25 + MR25: u1 = 0, + /// Interrupt Mask on line 26 + MR26: u1 = 0, + /// Interrupt Mask on line 27 + MR27: u1 = 0, + /// Interrupt Mask on line 28 + MR28: u1 = 0, + /// Interrupt Mask on line 29 + MR29: u1 = 0, + /// Interrupt Mask on line 30 + MR30: u1 = 0, + /// Interrupt Mask on line 31 + MR31: u1 = 0, + }); + + /// Event mask register pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { - MR0: u1, // bit offset: 0 desc: Event Mask on line 0 - MR1: u1, // bit offset: 1 desc: Event Mask on line 1 - MR2: u1, // bit offset: 2 desc: Event Mask on line 2 - MR3: u1, // bit offset: 3 desc: Event Mask on line 3 - MR4: u1, // bit offset: 4 desc: Event Mask on line 4 - MR5: u1, // bit offset: 5 desc: Event Mask on line 5 - MR6: u1, // bit offset: 6 desc: Event Mask on line 6 - MR7: u1, // bit offset: 7 desc: Event Mask on line 7 - MR8: u1, // bit offset: 8 desc: Event Mask on line 8 - MR9: u1, // bit offset: 9 desc: Event Mask on line 9 - MR10: u1, // bit offset: 10 desc: Event Mask on line 10 - MR11: u1, // bit offset: 11 desc: Event Mask on line 11 - MR12: u1, // bit offset: 12 desc: Event Mask on line 12 - MR13: u1, // bit offset: 13 desc: Event Mask on line 13 - MR14: u1, // bit offset: 14 desc: Event Mask on line 14 - MR15: u1, // bit offset: 15 desc: Event Mask on line 15 - MR16: u1, // bit offset: 16 desc: Event Mask on line 16 - MR17: u1, // bit offset: 17 desc: Event Mask on line 17 - MR18: u1, // bit offset: 18 desc: Event Mask on line 18 - MR19: u1, // bit offset: 19 desc: Event Mask on line 19 - MR20: u1, // bit offset: 20 desc: Event Mask on line 20 - MR21: u1, // bit offset: 21 desc: Event Mask on line 21 - MR22: u1, // bit offset: 22 desc: Event Mask on line 22 - MR23: u1, // bit offset: 23 desc: Event Mask on line 23 - MR24: u1, // bit offset: 24 desc: Event Mask on line 24 - MR25: u1, // bit offset: 25 desc: Event Mask on line 25 - MR26: u1, // bit offset: 26 desc: Event Mask on line 26 - MR27: u1, // bit offset: 27 desc: Event Mask on line 27 - MR28: u1, // bit offset: 28 desc: Event Mask on line 28 - MR29: u1, // bit offset: 29 desc: Event Mask on line 29 - MR30: u1, // bit offset: 30 desc: Event Mask on line 30 - MR31: u1, // bit offset: 31 desc: Event Mask on line 31 - }); - // byte offset: 8 Rising Trigger selection register + /// Event Mask on line 0 + MR0: u1 = 0, + /// Event Mask on line 1 + MR1: u1 = 0, + /// Event Mask on line 2 + MR2: u1 = 0, + /// Event Mask on line 3 + MR3: u1 = 0, + /// Event Mask on line 4 + MR4: u1 = 0, + /// Event Mask on line 5 + MR5: u1 = 0, + /// Event Mask on line 6 + MR6: u1 = 0, + /// Event Mask on line 7 + MR7: u1 = 0, + /// Event Mask on line 8 + MR8: u1 = 0, + /// Event Mask on line 9 + MR9: u1 = 0, + /// Event Mask on line 10 + MR10: u1 = 0, + /// Event Mask on line 11 + MR11: u1 = 0, + /// Event Mask on line 12 + MR12: u1 = 0, + /// Event Mask on line 13 + MR13: u1 = 0, + /// Event Mask on line 14 + MR14: u1 = 0, + /// Event Mask on line 15 + MR15: u1 = 0, + /// Event Mask on line 16 + MR16: u1 = 0, + /// Event Mask on line 17 + MR17: u1 = 0, + /// Event Mask on line 18 + MR18: u1 = 0, + /// Event Mask on line 19 + MR19: u1 = 0, + /// Event Mask on line 20 + MR20: u1 = 0, + /// Event Mask on line 21 + MR21: u1 = 0, + /// Event Mask on line 22 + MR22: u1 = 0, + /// Event Mask on line 23 + MR23: u1 = 0, + /// Event Mask on line 24 + MR24: u1 = 0, + /// Event Mask on line 25 + MR25: u1 = 0, + /// Event Mask on line 26 + MR26: u1 = 0, + /// Event Mask on line 27 + MR27: u1 = 0, + /// Event Mask on line 28 + MR28: u1 = 0, + /// Event Mask on line 29 + MR29: u1 = 0, + /// Event Mask on line 30 + MR30: u1 = 0, + /// Event Mask on line 31 + MR31: u1 = 0, + }); + + /// Rising Trigger selection register pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Rising trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Rising trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Rising trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Rising trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Rising trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Rising trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Rising trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Rising trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Rising trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Rising trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Rising trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Rising trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Rising trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Rising trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Rising trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Rising trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Rising trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Rising trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Rising trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Rising trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Rising trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Rising trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Rising trigger event configuration of line 22 + /// Rising trigger event configuration of line 0 + TR0: u1 = 0, + /// Rising trigger event configuration of line 1 + TR1: u1 = 0, + /// Rising trigger event configuration of line 2 + TR2: u1 = 0, + /// Rising trigger event configuration of line 3 + TR3: u1 = 0, + /// Rising trigger event configuration of line 4 + TR4: u1 = 0, + /// Rising trigger event configuration of line 5 + TR5: u1 = 0, + /// Rising trigger event configuration of line 6 + TR6: u1 = 0, + /// Rising trigger event configuration of line 7 + TR7: u1 = 0, + /// Rising trigger event configuration of line 8 + TR8: u1 = 0, + /// Rising trigger event configuration of line 9 + TR9: u1 = 0, + /// Rising trigger event configuration of line 10 + TR10: u1 = 0, + /// Rising trigger event configuration of line 11 + TR11: u1 = 0, + /// Rising trigger event configuration of line 12 + TR12: u1 = 0, + /// Rising trigger event configuration of line 13 + TR13: u1 = 0, + /// Rising trigger event configuration of line 14 + TR14: u1 = 0, + /// Rising trigger event configuration of line 15 + TR15: u1 = 0, + /// Rising trigger event configuration of line 16 + TR16: u1 = 0, + /// Rising trigger event configuration of line 17 + TR17: u1 = 0, + /// Rising trigger event configuration of line 18 + TR18: u1 = 0, + /// Rising trigger event configuration of line 19 + TR19: u1 = 0, + /// Rising trigger event configuration of line 20 + TR20: u1 = 0, + /// Rising trigger event configuration of line 21 + TR21: u1 = 0, + /// Rising trigger event configuration of line 22 + TR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Rising trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Rising trigger event configuration of line 30 - TR31: u1, // bit offset: 31 desc: Rising trigger event configuration of line 31 + /// Rising trigger event configuration of line 29 + TR29: u1 = 0, + /// Rising trigger event configuration of line 30 + TR30: u1 = 0, + /// Rising trigger event configuration of line 31 + TR31: u1 = 0, }); - // byte offset: 12 Falling Trigger selection register + + /// Falling Trigger selection register pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { - TR0: u1, // bit offset: 0 desc: Falling trigger event configuration of line 0 - TR1: u1, // bit offset: 1 desc: Falling trigger event configuration of line 1 - TR2: u1, // bit offset: 2 desc: Falling trigger event configuration of line 2 - TR3: u1, // bit offset: 3 desc: Falling trigger event configuration of line 3 - TR4: u1, // bit offset: 4 desc: Falling trigger event configuration of line 4 - TR5: u1, // bit offset: 5 desc: Falling trigger event configuration of line 5 - TR6: u1, // bit offset: 6 desc: Falling trigger event configuration of line 6 - TR7: u1, // bit offset: 7 desc: Falling trigger event configuration of line 7 - TR8: u1, // bit offset: 8 desc: Falling trigger event configuration of line 8 - TR9: u1, // bit offset: 9 desc: Falling trigger event configuration of line 9 - TR10: u1, // bit offset: 10 desc: Falling trigger event configuration of line 10 - TR11: u1, // bit offset: 11 desc: Falling trigger event configuration of line 11 - TR12: u1, // bit offset: 12 desc: Falling trigger event configuration of line 12 - TR13: u1, // bit offset: 13 desc: Falling trigger event configuration of line 13 - TR14: u1, // bit offset: 14 desc: Falling trigger event configuration of line 14 - TR15: u1, // bit offset: 15 desc: Falling trigger event configuration of line 15 - TR16: u1, // bit offset: 16 desc: Falling trigger event configuration of line 16 - TR17: u1, // bit offset: 17 desc: Falling trigger event configuration of line 17 - TR18: u1, // bit offset: 18 desc: Falling trigger event configuration of line 18 - TR19: u1, // bit offset: 19 desc: Falling trigger event configuration of line 19 - TR20: u1, // bit offset: 20 desc: Falling trigger event configuration of line 20 - TR21: u1, // bit offset: 21 desc: Falling trigger event configuration of line 21 - TR22: u1, // bit offset: 22 desc: Falling trigger event configuration of line 22 + /// Falling trigger event configuration of line 0 + TR0: u1 = 0, + /// Falling trigger event configuration of line 1 + TR1: u1 = 0, + /// Falling trigger event configuration of line 2 + TR2: u1 = 0, + /// Falling trigger event configuration of line 3 + TR3: u1 = 0, + /// Falling trigger event configuration of line 4 + TR4: u1 = 0, + /// Falling trigger event configuration of line 5 + TR5: u1 = 0, + /// Falling trigger event configuration of line 6 + TR6: u1 = 0, + /// Falling trigger event configuration of line 7 + TR7: u1 = 0, + /// Falling trigger event configuration of line 8 + TR8: u1 = 0, + /// Falling trigger event configuration of line 9 + TR9: u1 = 0, + /// Falling trigger event configuration of line 10 + TR10: u1 = 0, + /// Falling trigger event configuration of line 11 + TR11: u1 = 0, + /// Falling trigger event configuration of line 12 + TR12: u1 = 0, + /// Falling trigger event configuration of line 13 + TR13: u1 = 0, + /// Falling trigger event configuration of line 14 + TR14: u1 = 0, + /// Falling trigger event configuration of line 15 + TR15: u1 = 0, + /// Falling trigger event configuration of line 16 + TR16: u1 = 0, + /// Falling trigger event configuration of line 17 + TR17: u1 = 0, + /// Falling trigger event configuration of line 18 + TR18: u1 = 0, + /// Falling trigger event configuration of line 19 + TR19: u1 = 0, + /// Falling trigger event configuration of line 20 + TR20: u1 = 0, + /// Falling trigger event configuration of line 21 + TR21: u1 = 0, + /// Falling trigger event configuration of line 22 + TR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TR29: u1, // bit offset: 29 desc: Falling trigger event configuration of line 29 - TR30: u1, // bit offset: 30 desc: Falling trigger event configuration of line 30. - TR31: u1, // bit offset: 31 desc: Falling trigger event configuration of line 31 + /// Falling trigger event configuration of line 29 + TR29: u1 = 0, + /// Falling trigger event configuration of line 30. + TR30: u1 = 0, + /// Falling trigger event configuration of line 31 + TR31: u1 = 0, }); - // byte offset: 16 Software interrupt event register + + /// Software interrupt event register pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { - SWIER0: u1, // bit offset: 0 desc: Software Interrupt on line 0 - SWIER1: u1, // bit offset: 1 desc: Software Interrupt on line 1 - SWIER2: u1, // bit offset: 2 desc: Software Interrupt on line 2 - SWIER3: u1, // bit offset: 3 desc: Software Interrupt on line 3 - SWIER4: u1, // bit offset: 4 desc: Software Interrupt on line 4 - SWIER5: u1, // bit offset: 5 desc: Software Interrupt on line 5 - SWIER6: u1, // bit offset: 6 desc: Software Interrupt on line 6 - SWIER7: u1, // bit offset: 7 desc: Software Interrupt on line 7 - SWIER8: u1, // bit offset: 8 desc: Software Interrupt on line 8 - SWIER9: u1, // bit offset: 9 desc: Software Interrupt on line 9 - SWIER10: u1, // bit offset: 10 desc: Software Interrupt on line 10 - SWIER11: u1, // bit offset: 11 desc: Software Interrupt on line 11 - SWIER12: u1, // bit offset: 12 desc: Software Interrupt on line 12 - SWIER13: u1, // bit offset: 13 desc: Software Interrupt on line 13 - SWIER14: u1, // bit offset: 14 desc: Software Interrupt on line 14 - SWIER15: u1, // bit offset: 15 desc: Software Interrupt on line 15 - SWIER16: u1, // bit offset: 16 desc: Software Interrupt on line 16 - SWIER17: u1, // bit offset: 17 desc: Software Interrupt on line 17 - SWIER18: u1, // bit offset: 18 desc: Software Interrupt on line 18 - SWIER19: u1, // bit offset: 19 desc: Software Interrupt on line 19 - SWIER20: u1, // bit offset: 20 desc: Software Interrupt on line 20 - SWIER21: u1, // bit offset: 21 desc: Software Interrupt on line 21 - SWIER22: u1, // bit offset: 22 desc: Software Interrupt on line 22 + /// Software Interrupt on line 0 + SWIER0: u1 = 0, + /// Software Interrupt on line 1 + SWIER1: u1 = 0, + /// Software Interrupt on line 2 + SWIER2: u1 = 0, + /// Software Interrupt on line 3 + SWIER3: u1 = 0, + /// Software Interrupt on line 4 + SWIER4: u1 = 0, + /// Software Interrupt on line 5 + SWIER5: u1 = 0, + /// Software Interrupt on line 6 + SWIER6: u1 = 0, + /// Software Interrupt on line 7 + SWIER7: u1 = 0, + /// Software Interrupt on line 8 + SWIER8: u1 = 0, + /// Software Interrupt on line 9 + SWIER9: u1 = 0, + /// Software Interrupt on line 10 + SWIER10: u1 = 0, + /// Software Interrupt on line 11 + SWIER11: u1 = 0, + /// Software Interrupt on line 12 + SWIER12: u1 = 0, + /// Software Interrupt on line 13 + SWIER13: u1 = 0, + /// Software Interrupt on line 14 + SWIER14: u1 = 0, + /// Software Interrupt on line 15 + SWIER15: u1 = 0, + /// Software Interrupt on line 16 + SWIER16: u1 = 0, + /// Software Interrupt on line 17 + SWIER17: u1 = 0, + /// Software Interrupt on line 18 + SWIER18: u1 = 0, + /// Software Interrupt on line 19 + SWIER19: u1 = 0, + /// Software Interrupt on line 20 + SWIER20: u1 = 0, + /// Software Interrupt on line 21 + SWIER21: u1 = 0, + /// Software Interrupt on line 22 + SWIER22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SWIER29: u1, // bit offset: 29 desc: Software Interrupt on line 29 - SWIER30: u1, // bit offset: 30 desc: Software Interrupt on line 309 - SWIER31: u1, // bit offset: 31 desc: Software Interrupt on line 319 + /// Software Interrupt on line 29 + SWIER29: u1 = 0, + /// Software Interrupt on line 309 + SWIER30: u1 = 0, + /// Software Interrupt on line 319 + SWIER31: u1 = 0, }); - // byte offset: 20 Pending register + + /// Pending register pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { - PR0: u1, // bit offset: 0 desc: Pending bit 0 - PR1: u1, // bit offset: 1 desc: Pending bit 1 - PR2: u1, // bit offset: 2 desc: Pending bit 2 - PR3: u1, // bit offset: 3 desc: Pending bit 3 - PR4: u1, // bit offset: 4 desc: Pending bit 4 - PR5: u1, // bit offset: 5 desc: Pending bit 5 - PR6: u1, // bit offset: 6 desc: Pending bit 6 - PR7: u1, // bit offset: 7 desc: Pending bit 7 - PR8: u1, // bit offset: 8 desc: Pending bit 8 - PR9: u1, // bit offset: 9 desc: Pending bit 9 - PR10: u1, // bit offset: 10 desc: Pending bit 10 - PR11: u1, // bit offset: 11 desc: Pending bit 11 - PR12: u1, // bit offset: 12 desc: Pending bit 12 - PR13: u1, // bit offset: 13 desc: Pending bit 13 - PR14: u1, // bit offset: 14 desc: Pending bit 14 - PR15: u1, // bit offset: 15 desc: Pending bit 15 - PR16: u1, // bit offset: 16 desc: Pending bit 16 - PR17: u1, // bit offset: 17 desc: Pending bit 17 - PR18: u1, // bit offset: 18 desc: Pending bit 18 - PR19: u1, // bit offset: 19 desc: Pending bit 19 - PR20: u1, // bit offset: 20 desc: Pending bit 20 - PR21: u1, // bit offset: 21 desc: Pending bit 21 - PR22: u1, // bit offset: 22 desc: Pending bit 22 + /// Pending bit 0 + PR0: u1 = 0, + /// Pending bit 1 + PR1: u1 = 0, + /// Pending bit 2 + PR2: u1 = 0, + /// Pending bit 3 + PR3: u1 = 0, + /// Pending bit 4 + PR4: u1 = 0, + /// Pending bit 5 + PR5: u1 = 0, + /// Pending bit 6 + PR6: u1 = 0, + /// Pending bit 7 + PR7: u1 = 0, + /// Pending bit 8 + PR8: u1 = 0, + /// Pending bit 9 + PR9: u1 = 0, + /// Pending bit 10 + PR10: u1 = 0, + /// Pending bit 11 + PR11: u1 = 0, + /// Pending bit 12 + PR12: u1 = 0, + /// Pending bit 13 + PR13: u1 = 0, + /// Pending bit 14 + PR14: u1 = 0, + /// Pending bit 15 + PR15: u1 = 0, + /// Pending bit 16 + PR16: u1 = 0, + /// Pending bit 17 + PR17: u1 = 0, + /// Pending bit 18 + PR18: u1 = 0, + /// Pending bit 19 + PR19: u1 = 0, + /// Pending bit 20 + PR20: u1 = 0, + /// Pending bit 21 + PR21: u1 = 0, + /// Pending bit 22 + PR22: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PR29: u1, // bit offset: 29 desc: Pending bit 29 - PR30: u1, // bit offset: 30 desc: Pending bit 30 - PR31: u1, // bit offset: 31 desc: Pending bit 31 + /// Pending bit 29 + PR29: u1 = 0, + /// Pending bit 30 + PR30: u1 = 0, + /// Pending bit 31 + PR31: u1 = 0, }); - // byte offset: 24 Interrupt mask register + + /// Interrupt mask register pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Interrupt Mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Interrupt Mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Interrupt Mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Interrupt Mask on external/internal line 35 + /// Interrupt Mask on external/internal line 32 + MR32: u1 = 0, + /// Interrupt Mask on external/internal line 33 + MR33: u1 = 0, + /// Interrupt Mask on external/internal line 34 + MR34: u1 = 0, + /// Interrupt Mask on external/internal line 35 + MR35: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10334,12 +14448,17 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Event mask register + + /// Event mask register pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { - MR32: u1, // bit offset: 0 desc: Event mask on external/internal line 32 - MR33: u1, // bit offset: 1 desc: Event mask on external/internal line 33 - MR34: u1, // bit offset: 2 desc: Event mask on external/internal line 34 - MR35: u1, // bit offset: 3 desc: Event mask on external/internal line 35 + /// Event mask on external/internal line 32 + MR32: u1 = 0, + /// Event mask on external/internal line 33 + MR33: u1 = 0, + /// Event mask on external/internal line 34 + MR34: u1 = 0, + /// Event mask on external/internal line 35 + MR35: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -10369,10 +14488,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Rising Trigger selection register + + /// Rising Trigger selection register pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Rising trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Rising trigger event configuration bit of line 33 + /// Rising trigger event configuration bit of line 32 + TR32: u1 = 0, + /// Rising trigger event configuration bit of line 33 + TR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10404,10 +14526,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Falling Trigger selection register + + /// Falling Trigger selection register pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { - TR32: u1, // bit offset: 0 desc: Falling trigger event configuration bit of line 32 - TR33: u1, // bit offset: 1 desc: Falling trigger event configuration bit of line 33 + /// Falling trigger event configuration bit of line 32 + TR32: u1 = 0, + /// Falling trigger event configuration bit of line 33 + TR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10439,10 +14564,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Software interrupt event register + + /// Software interrupt event register pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { - SWIER32: u1, // bit offset: 0 desc: Software interrupt on line 32 - SWIER33: u1, // bit offset: 1 desc: Software interrupt on line 33 + /// Software interrupt on line 32 + SWIER32: u1 = 0, + /// Software interrupt on line 33 + SWIER33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10474,10 +14602,13 @@ pub const EXTI = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Pending register + + /// Pending register pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { - PR32: u1, // bit offset: 0 desc: Pending bit on line 32 - PR33: u1, // bit offset: 1 desc: Pending bit on line 33 + /// Pending bit on line 32 + PR32: u1 = 0, + /// Pending bit on line 33 + PR33: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -10510,17 +14641,27 @@ pub const EXTI = extern struct { padding1: u1 = 0, }); }; + +/// Power control pub const PWR = extern struct { pub const Address: u32 = 0x40007000; - // byte offset: 0 power control register + + /// power control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - LPDS: u1, // bit offset: 0 desc: Low-power deep sleep - PDDS: u1, // bit offset: 1 desc: Power down deepsleep - CWUF: u1, // bit offset: 2 desc: Clear wakeup flag - CSBF: u1, // bit offset: 3 desc: Clear standby flag - PVDE: u1, // bit offset: 4 desc: Power voltage detector enable - PLS: u3, // bit offset: 5 desc: PVD level selection - DBP: u1, // bit offset: 8 desc: Disable backup domain write protection + /// Low-power deep sleep + LPDS: u1 = 0, + /// Power down deepsleep + PDDS: u1 = 0, + /// Clear wakeup flag + CWUF: u1 = 0, + /// Clear standby flag + CSBF: u1 = 0, + /// Power voltage detector enable + PVDE: u1 = 0, + /// PVD level selection + PLS: u3 = 0, + /// Disable backup domain write protection + DBP: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -10545,18 +14686,24 @@ pub const PWR = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 power control/status register + + /// power control/status register pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - WUF: u1, // bit offset: 0 desc: Wakeup flag - SBF: u1, // bit offset: 1 desc: Standby flag - PVDO: u1, // bit offset: 2 desc: PVD output + /// Wakeup flag + WUF: u1 = 0, + /// Standby flag + SBF: u1 = 0, + /// PVD output + PVDO: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - EWUP1: u1, // bit offset: 8 desc: Enable WKUP1 pin - EWUP2: u1, // bit offset: 9 desc: Enable WKUP2 pin + /// Enable WKUP1 pin + EWUP1: u1 = 0, + /// Enable WKUP2 pin + EWUP2: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -10581,18 +14728,13 @@ pub const PWR = extern struct { padding1: u1 = 0, }); }; + +/// Controller area network pub const CAN = extern struct { pub const Address: u32 = 0x40006400; - // byte offset: 0 master control register + + /// master control register pub const MCR = mmio(Address + 0x00000000, 32, packed struct { - INRQ: u1, // bit offset: 0 desc: INRQ - SLEEP: u1, // bit offset: 1 desc: SLEEP - TXFP: u1, // bit offset: 2 desc: TXFP - RFLM: u1, // bit offset: 3 desc: RFLM - NART: u1, // bit offset: 4 desc: NART - AWUM: u1, // bit offset: 5 desc: AWUM - ABOM: u1, // bit offset: 6 desc: ABOM - TTCM: u1, // bit offset: 7 desc: TTCM reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -10600,8 +14742,6 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RESET: u1, // bit offset: 15 desc: RESET - DBF: u1, // bit offset: 16 desc: DBF padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -10618,20 +14758,12 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 master status register + + /// master status register pub const MSR = mmio(Address + 0x00000004, 32, packed struct { - INAK: u1, // bit offset: 0 desc: INAK - SLAK: u1, // bit offset: 1 desc: SLAK - ERRI: u1, // bit offset: 2 desc: ERRI - WKUI: u1, // bit offset: 3 desc: WKUI - SLAKI: u1, // bit offset: 4 desc: SLAKI reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TXM: u1, // bit offset: 8 desc: TXM - RXM: u1, // bit offset: 9 desc: RXM - SAMP: u1, // bit offset: 10 desc: SAMP - RX: u1, // bit offset: 11 desc: RX padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -10653,47 +14785,35 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 transmit status register + + /// transmit status register pub const TSR = mmio(Address + 0x00000008, 32, packed struct { - RQCP0: u1, // bit offset: 0 desc: RQCP0 - TXOK0: u1, // bit offset: 1 desc: TXOK0 - ALST0: u1, // bit offset: 2 desc: ALST0 - TERR0: u1, // bit offset: 3 desc: TERR0 reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ABRQ0: u1, // bit offset: 7 desc: ABRQ0 - RQCP1: u1, // bit offset: 8 desc: RQCP1 - TXOK1: u1, // bit offset: 9 desc: TXOK1 - ALST1: u1, // bit offset: 10 desc: ALST1 - TERR1: u1, // bit offset: 11 desc: TERR1 reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - ABRQ1: u1, // bit offset: 15 desc: ABRQ1 - RQCP2: u1, // bit offset: 16 desc: RQCP2 - TXOK2: u1, // bit offset: 17 desc: TXOK2 - ALST2: u1, // bit offset: 18 desc: ALST2 - TERR2: u1, // bit offset: 19 desc: TERR2 reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - ABRQ2: u1, // bit offset: 23 desc: ABRQ2 - CODE: u2, // bit offset: 24 desc: CODE - TME0: u1, // bit offset: 26 desc: Lowest priority flag for mailbox 0 - TME1: u1, // bit offset: 27 desc: Lowest priority flag for mailbox 1 - TME2: u1, // bit offset: 28 desc: Lowest priority flag for mailbox 2 - LOW0: u1, // bit offset: 29 desc: Lowest priority flag for mailbox 0 - LOW1: u1, // bit offset: 30 desc: Lowest priority flag for mailbox 1 - LOW2: u1, // bit offset: 31 desc: Lowest priority flag for mailbox 2 - }); - // byte offset: 12 receive FIFO 0 register + /// Lowest priority flag for mailbox 0 + TME0: u1 = 0, + /// Lowest priority flag for mailbox 1 + TME1: u1 = 0, + /// Lowest priority flag for mailbox 2 + TME2: u1 = 0, + /// Lowest priority flag for mailbox 0 + LOW0: u1 = 0, + /// Lowest priority flag for mailbox 1 + LOW1: u1 = 0, + /// Lowest priority flag for mailbox 2 + LOW2: u1 = 0, + }); + + /// receive FIFO 0 register pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { - FMP0: u2, // bit offset: 0 desc: FMP0 reserved1: u1 = 0, - FULL0: u1, // bit offset: 3 desc: FULL0 - FOVR0: u1, // bit offset: 4 desc: FOVR0 - RFOM0: u1, // bit offset: 5 desc: RFOM0 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10721,13 +14841,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 receive FIFO 1 register + + /// receive FIFO 1 register pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { - FMP1: u2, // bit offset: 0 desc: FMP1 reserved1: u1 = 0, - FULL1: u1, // bit offset: 3 desc: FULL1 - FOVR1: u1, // bit offset: 4 desc: FOVR1 - RFOM1: u1, // bit offset: 5 desc: RFOM1 padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -10755,26 +14872,13 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000014, 32, packed struct { - TMEIE: u1, // bit offset: 0 desc: TMEIE - FMPIE0: u1, // bit offset: 1 desc: FMPIE0 - FFIE0: u1, // bit offset: 2 desc: FFIE0 - FOVIE0: u1, // bit offset: 3 desc: FOVIE0 - FMPIE1: u1, // bit offset: 4 desc: FMPIE1 - FFIE1: u1, // bit offset: 5 desc: FFIE1 - FOVIE1: u1, // bit offset: 6 desc: FOVIE1 - reserved1: u1 = 0, - EWGIE: u1, // bit offset: 8 desc: EWGIE - EPVIE: u1, // bit offset: 9 desc: EPVIE - BOFIE: u1, // bit offset: 10 desc: BOFIE - LECIE: u1, // bit offset: 11 desc: LECIE + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - ERRIE: u1, // bit offset: 15 desc: ERRIE - WKUIE: u1, // bit offset: 16 desc: WKUIE - SLKIE: u1, // bit offset: 17 desc: SLKIE padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -10790,13 +14894,10 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 error status register + + /// error status register pub const ESR = mmio(Address + 0x00000018, 32, packed struct { - EWGF: u1, // bit offset: 0 desc: EWGF - EPVF: u1, // bit offset: 1 desc: EPVF - BOFF: u1, // bit offset: 2 desc: BOFF reserved1: u1 = 0, - LEC: u3, // bit offset: 4 desc: LEC reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, @@ -10806,45 +14907,32 @@ pub const CAN = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - TEC: u8, // bit offset: 16 desc: TEC - REC: u8, // bit offset: 24 desc: REC }); - // byte offset: 28 bit timing register + + /// bit timing register pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { - BRP: u10, // bit offset: 0 desc: BRP reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TS1: u4, // bit offset: 16 desc: TS1 - TS2: u3, // bit offset: 20 desc: TS2 reserved7: u1 = 0, - SJW: u2, // bit offset: 24 desc: SJW reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - LBKM: u1, // bit offset: 30 desc: LBKM - SILM: u1, // bit offset: 31 desc: SILM - }); - // byte offset: 384 TX mailbox identifier register - pub const TI0R = mmio(Address + 0x00000180, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 388 mailbox data length control and time stamp register + }); + + /// TX mailbox identifier register + pub const TI0R = mmio(Address + 0x00000180, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10852,38 +14940,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 392 mailbox data low register - pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 396 mailbox data high register - pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 400 TX mailbox identifier register - pub const TI1R = mmio(Address + 0x00000190, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 404 mailbox data length control and time stamp register + }); + + /// mailbox data low register + pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); + + /// mailbox data high register + pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); + + /// TX mailbox identifier register + pub const TI1R = mmio(Address + 0x00000190, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10891,38 +14964,23 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 408 mailbox data low register - pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 412 mailbox data high register - pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 416 TX mailbox identifier register - pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct { - TXRQ: u1, // bit offset: 0 desc: TXRQ - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID - }); - // byte offset: 420 mailbox data length control and time stamp register + }); + + /// mailbox data low register + pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); + + /// mailbox data high register + pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); + + /// TX mailbox identifier register + pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); + + /// mailbox data length control and time stamp register pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TGT: u1, // bit offset: 8 desc: TGT reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -10930,89 +14988,56 @@ pub const CAN = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 424 mailbox data low register - pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 - }); - // byte offset: 428 mailbox data high register - pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 432 receive FIFO mailbox identifier register + }); + + /// mailbox data low register + pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); + + /// mailbox data high register + pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); + + /// receive FIFO mailbox identifier register pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 436 receive FIFO mailbox data length control and time stamp register + + /// receive FIFO mailbox data length control and time stamp register pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 440 receive FIFO mailbox data low register - pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 }); - // byte offset: 444 receive FIFO mailbox data high register - pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 448 receive FIFO mailbox identifier register + + /// receive FIFO mailbox data low register + pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); + + /// receive FIFO mailbox data high register + pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); + + /// receive FIFO mailbox identifier register pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { reserved1: u1 = 0, - RTR: u1, // bit offset: 1 desc: RTR - IDE: u1, // bit offset: 2 desc: IDE - EXID: u18, // bit offset: 3 desc: EXID - STID: u11, // bit offset: 21 desc: STID }); - // byte offset: 452 receive FIFO mailbox data length control and time stamp register + + /// receive FIFO mailbox data length control and time stamp register pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - DLC: u4, // bit offset: 0 desc: DLC reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - FMI: u8, // bit offset: 8 desc: FMI - TIME: u16, // bit offset: 16 desc: TIME - }); - // byte offset: 456 receive FIFO mailbox data low register - pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct { - DATA0: u8, // bit offset: 0 desc: DATA0 - DATA1: u8, // bit offset: 8 desc: DATA1 - DATA2: u8, // bit offset: 16 desc: DATA2 - DATA3: u8, // bit offset: 24 desc: DATA3 }); - // byte offset: 460 receive FIFO mailbox data high register - pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct { - DATA4: u8, // bit offset: 0 desc: DATA4 - DATA5: u8, // bit offset: 8 desc: DATA5 - DATA6: u8, // bit offset: 16 desc: DATA6 - DATA7: u8, // bit offset: 24 desc: DATA7 - }); - // byte offset: 512 filter master register + + /// receive FIFO mailbox data low register + pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); + + /// receive FIFO mailbox data high register + pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); + + /// filter master register pub const FMR = mmio(Address + 0x00000200, 32, packed struct { - FINIT: u1, // bit offset: 0 desc: Filter init mode + /// Filter init mode + FINIT: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -11020,7 +15045,8 @@ pub const CAN = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CAN2SB: u6, // bit offset: 8 desc: CAN2 start bank + /// CAN2 start bank + CAN2SB: u6 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -11040,2121 +15066,4098 @@ pub const CAN = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 516 filter mode register + + /// filter mode register pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { - FBM0: u1, // bit offset: 0 desc: Filter mode - FBM1: u1, // bit offset: 1 desc: Filter mode - FBM2: u1, // bit offset: 2 desc: Filter mode - FBM3: u1, // bit offset: 3 desc: Filter mode - FBM4: u1, // bit offset: 4 desc: Filter mode - FBM5: u1, // bit offset: 5 desc: Filter mode - FBM6: u1, // bit offset: 6 desc: Filter mode - FBM7: u1, // bit offset: 7 desc: Filter mode - FBM8: u1, // bit offset: 8 desc: Filter mode - FBM9: u1, // bit offset: 9 desc: Filter mode - FBM10: u1, // bit offset: 10 desc: Filter mode - FBM11: u1, // bit offset: 11 desc: Filter mode - FBM12: u1, // bit offset: 12 desc: Filter mode - FBM13: u1, // bit offset: 13 desc: Filter mode - FBM14: u1, // bit offset: 14 desc: Filter mode - FBM15: u1, // bit offset: 15 desc: Filter mode - FBM16: u1, // bit offset: 16 desc: Filter mode - FBM17: u1, // bit offset: 17 desc: Filter mode - FBM18: u1, // bit offset: 18 desc: Filter mode - FBM19: u1, // bit offset: 19 desc: Filter mode - FBM20: u1, // bit offset: 20 desc: Filter mode - FBM21: u1, // bit offset: 21 desc: Filter mode - FBM22: u1, // bit offset: 22 desc: Filter mode - FBM23: u1, // bit offset: 23 desc: Filter mode - FBM24: u1, // bit offset: 24 desc: Filter mode - FBM25: u1, // bit offset: 25 desc: Filter mode - FBM26: u1, // bit offset: 26 desc: Filter mode - FBM27: u1, // bit offset: 27 desc: Filter mode - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 524 filter scale register + /// Filter mode + FBM0: u1 = 0, + /// Filter mode + FBM1: u1 = 0, + /// Filter mode + FBM2: u1 = 0, + /// Filter mode + FBM3: u1 = 0, + /// Filter mode + FBM4: u1 = 0, + /// Filter mode + FBM5: u1 = 0, + /// Filter mode + FBM6: u1 = 0, + /// Filter mode + FBM7: u1 = 0, + /// Filter mode + FBM8: u1 = 0, + /// Filter mode + FBM9: u1 = 0, + /// Filter mode + FBM10: u1 = 0, + /// Filter mode + FBM11: u1 = 0, + /// Filter mode + FBM12: u1 = 0, + /// Filter mode + FBM13: u1 = 0, + /// Filter mode + FBM14: u1 = 0, + /// Filter mode + FBM15: u1 = 0, + /// Filter mode + FBM16: u1 = 0, + /// Filter mode + FBM17: u1 = 0, + /// Filter mode + FBM18: u1 = 0, + /// Filter mode + FBM19: u1 = 0, + /// Filter mode + FBM20: u1 = 0, + /// Filter mode + FBM21: u1 = 0, + /// Filter mode + FBM22: u1 = 0, + /// Filter mode + FBM23: u1 = 0, + /// Filter mode + FBM24: u1 = 0, + /// Filter mode + FBM25: u1 = 0, + /// Filter mode + FBM26: u1 = 0, + /// Filter mode + FBM27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// filter scale register pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { - FSC0: u1, // bit offset: 0 desc: Filter scale configuration - FSC1: u1, // bit offset: 1 desc: Filter scale configuration - FSC2: u1, // bit offset: 2 desc: Filter scale configuration - FSC3: u1, // bit offset: 3 desc: Filter scale configuration - FSC4: u1, // bit offset: 4 desc: Filter scale configuration - FSC5: u1, // bit offset: 5 desc: Filter scale configuration - FSC6: u1, // bit offset: 6 desc: Filter scale configuration - FSC7: u1, // bit offset: 7 desc: Filter scale configuration - FSC8: u1, // bit offset: 8 desc: Filter scale configuration - FSC9: u1, // bit offset: 9 desc: Filter scale configuration - FSC10: u1, // bit offset: 10 desc: Filter scale configuration - FSC11: u1, // bit offset: 11 desc: Filter scale configuration - FSC12: u1, // bit offset: 12 desc: Filter scale configuration - FSC13: u1, // bit offset: 13 desc: Filter scale configuration - FSC14: u1, // bit offset: 14 desc: Filter scale configuration - FSC15: u1, // bit offset: 15 desc: Filter scale configuration - FSC16: u1, // bit offset: 16 desc: Filter scale configuration - FSC17: u1, // bit offset: 17 desc: Filter scale configuration - FSC18: u1, // bit offset: 18 desc: Filter scale configuration - FSC19: u1, // bit offset: 19 desc: Filter scale configuration - FSC20: u1, // bit offset: 20 desc: Filter scale configuration - FSC21: u1, // bit offset: 21 desc: Filter scale configuration - FSC22: u1, // bit offset: 22 desc: Filter scale configuration - FSC23: u1, // bit offset: 23 desc: Filter scale configuration - FSC24: u1, // bit offset: 24 desc: Filter scale configuration - FSC25: u1, // bit offset: 25 desc: Filter scale configuration - FSC26: u1, // bit offset: 26 desc: Filter scale configuration - FSC27: u1, // bit offset: 27 desc: Filter scale configuration - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 532 filter FIFO assignment register + /// Filter scale configuration + FSC0: u1 = 0, + /// Filter scale configuration + FSC1: u1 = 0, + /// Filter scale configuration + FSC2: u1 = 0, + /// Filter scale configuration + FSC3: u1 = 0, + /// Filter scale configuration + FSC4: u1 = 0, + /// Filter scale configuration + FSC5: u1 = 0, + /// Filter scale configuration + FSC6: u1 = 0, + /// Filter scale configuration + FSC7: u1 = 0, + /// Filter scale configuration + FSC8: u1 = 0, + /// Filter scale configuration + FSC9: u1 = 0, + /// Filter scale configuration + FSC10: u1 = 0, + /// Filter scale configuration + FSC11: u1 = 0, + /// Filter scale configuration + FSC12: u1 = 0, + /// Filter scale configuration + FSC13: u1 = 0, + /// Filter scale configuration + FSC14: u1 = 0, + /// Filter scale configuration + FSC15: u1 = 0, + /// Filter scale configuration + FSC16: u1 = 0, + /// Filter scale configuration + FSC17: u1 = 0, + /// Filter scale configuration + FSC18: u1 = 0, + /// Filter scale configuration + FSC19: u1 = 0, + /// Filter scale configuration + FSC20: u1 = 0, + /// Filter scale configuration + FSC21: u1 = 0, + /// Filter scale configuration + FSC22: u1 = 0, + /// Filter scale configuration + FSC23: u1 = 0, + /// Filter scale configuration + FSC24: u1 = 0, + /// Filter scale configuration + FSC25: u1 = 0, + /// Filter scale configuration + FSC26: u1 = 0, + /// Filter scale configuration + FSC27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// filter FIFO assignment register pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { - FFA0: u1, // bit offset: 0 desc: Filter FIFO assignment for filter 0 - FFA1: u1, // bit offset: 1 desc: Filter FIFO assignment for filter 1 - FFA2: u1, // bit offset: 2 desc: Filter FIFO assignment for filter 2 - FFA3: u1, // bit offset: 3 desc: Filter FIFO assignment for filter 3 - FFA4: u1, // bit offset: 4 desc: Filter FIFO assignment for filter 4 - FFA5: u1, // bit offset: 5 desc: Filter FIFO assignment for filter 5 - FFA6: u1, // bit offset: 6 desc: Filter FIFO assignment for filter 6 - FFA7: u1, // bit offset: 7 desc: Filter FIFO assignment for filter 7 - FFA8: u1, // bit offset: 8 desc: Filter FIFO assignment for filter 8 - FFA9: u1, // bit offset: 9 desc: Filter FIFO assignment for filter 9 - FFA10: u1, // bit offset: 10 desc: Filter FIFO assignment for filter 10 - FFA11: u1, // bit offset: 11 desc: Filter FIFO assignment for filter 11 - FFA12: u1, // bit offset: 12 desc: Filter FIFO assignment for filter 12 - FFA13: u1, // bit offset: 13 desc: Filter FIFO assignment for filter 13 - FFA14: u1, // bit offset: 14 desc: Filter FIFO assignment for filter 14 - FFA15: u1, // bit offset: 15 desc: Filter FIFO assignment for filter 15 - FFA16: u1, // bit offset: 16 desc: Filter FIFO assignment for filter 16 - FFA17: u1, // bit offset: 17 desc: Filter FIFO assignment for filter 17 - FFA18: u1, // bit offset: 18 desc: Filter FIFO assignment for filter 18 - FFA19: u1, // bit offset: 19 desc: Filter FIFO assignment for filter 19 - FFA20: u1, // bit offset: 20 desc: Filter FIFO assignment for filter 20 - FFA21: u1, // bit offset: 21 desc: Filter FIFO assignment for filter 21 - FFA22: u1, // bit offset: 22 desc: Filter FIFO assignment for filter 22 - FFA23: u1, // bit offset: 23 desc: Filter FIFO assignment for filter 23 - FFA24: u1, // bit offset: 24 desc: Filter FIFO assignment for filter 24 - FFA25: u1, // bit offset: 25 desc: Filter FIFO assignment for filter 25 - FFA26: u1, // bit offset: 26 desc: Filter FIFO assignment for filter 26 - FFA27: u1, // bit offset: 27 desc: Filter FIFO assignment for filter 27 - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 540 CAN filter activation register + /// Filter FIFO assignment for filter 0 + FFA0: u1 = 0, + /// Filter FIFO assignment for filter 1 + FFA1: u1 = 0, + /// Filter FIFO assignment for filter 2 + FFA2: u1 = 0, + /// Filter FIFO assignment for filter 3 + FFA3: u1 = 0, + /// Filter FIFO assignment for filter 4 + FFA4: u1 = 0, + /// Filter FIFO assignment for filter 5 + FFA5: u1 = 0, + /// Filter FIFO assignment for filter 6 + FFA6: u1 = 0, + /// Filter FIFO assignment for filter 7 + FFA7: u1 = 0, + /// Filter FIFO assignment for filter 8 + FFA8: u1 = 0, + /// Filter FIFO assignment for filter 9 + FFA9: u1 = 0, + /// Filter FIFO assignment for filter 10 + FFA10: u1 = 0, + /// Filter FIFO assignment for filter 11 + FFA11: u1 = 0, + /// Filter FIFO assignment for filter 12 + FFA12: u1 = 0, + /// Filter FIFO assignment for filter 13 + FFA13: u1 = 0, + /// Filter FIFO assignment for filter 14 + FFA14: u1 = 0, + /// Filter FIFO assignment for filter 15 + FFA15: u1 = 0, + /// Filter FIFO assignment for filter 16 + FFA16: u1 = 0, + /// Filter FIFO assignment for filter 17 + FFA17: u1 = 0, + /// Filter FIFO assignment for filter 18 + FFA18: u1 = 0, + /// Filter FIFO assignment for filter 19 + FFA19: u1 = 0, + /// Filter FIFO assignment for filter 20 + FFA20: u1 = 0, + /// Filter FIFO assignment for filter 21 + FFA21: u1 = 0, + /// Filter FIFO assignment for filter 22 + FFA22: u1 = 0, + /// Filter FIFO assignment for filter 23 + FFA23: u1 = 0, + /// Filter FIFO assignment for filter 24 + FFA24: u1 = 0, + /// Filter FIFO assignment for filter 25 + FFA25: u1 = 0, + /// Filter FIFO assignment for filter 26 + FFA26: u1 = 0, + /// Filter FIFO assignment for filter 27 + FFA27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// CAN filter activation register pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { - FACT0: u1, // bit offset: 0 desc: Filter active - FACT1: u1, // bit offset: 1 desc: Filter active - FACT2: u1, // bit offset: 2 desc: Filter active - FACT3: u1, // bit offset: 3 desc: Filter active - FACT4: u1, // bit offset: 4 desc: Filter active - FACT5: u1, // bit offset: 5 desc: Filter active - FACT6: u1, // bit offset: 6 desc: Filter active - FACT7: u1, // bit offset: 7 desc: Filter active - FACT8: u1, // bit offset: 8 desc: Filter active - FACT9: u1, // bit offset: 9 desc: Filter active - FACT10: u1, // bit offset: 10 desc: Filter active - FACT11: u1, // bit offset: 11 desc: Filter active - FACT12: u1, // bit offset: 12 desc: Filter active - FACT13: u1, // bit offset: 13 desc: Filter active - FACT14: u1, // bit offset: 14 desc: Filter active - FACT15: u1, // bit offset: 15 desc: Filter active - FACT16: u1, // bit offset: 16 desc: Filter active - FACT17: u1, // bit offset: 17 desc: Filter active - FACT18: u1, // bit offset: 18 desc: Filter active - FACT19: u1, // bit offset: 19 desc: Filter active - FACT20: u1, // bit offset: 20 desc: Filter active - FACT21: u1, // bit offset: 21 desc: Filter active - FACT22: u1, // bit offset: 22 desc: Filter active - FACT23: u1, // bit offset: 23 desc: Filter active - FACT24: u1, // bit offset: 24 desc: Filter active - FACT25: u1, // bit offset: 25 desc: Filter active - FACT26: u1, // bit offset: 26 desc: Filter active - FACT27: u1, // bit offset: 27 desc: Filter active - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 576 Filter bank 0 register 1 + /// Filter active + FACT0: u1 = 0, + /// Filter active + FACT1: u1 = 0, + /// Filter active + FACT2: u1 = 0, + /// Filter active + FACT3: u1 = 0, + /// Filter active + FACT4: u1 = 0, + /// Filter active + FACT5: u1 = 0, + /// Filter active + FACT6: u1 = 0, + /// Filter active + FACT7: u1 = 0, + /// Filter active + FACT8: u1 = 0, + /// Filter active + FACT9: u1 = 0, + /// Filter active + FACT10: u1 = 0, + /// Filter active + FACT11: u1 = 0, + /// Filter active + FACT12: u1 = 0, + /// Filter active + FACT13: u1 = 0, + /// Filter active + FACT14: u1 = 0, + /// Filter active + FACT15: u1 = 0, + /// Filter active + FACT16: u1 = 0, + /// Filter active + FACT17: u1 = 0, + /// Filter active + FACT18: u1 = 0, + /// Filter active + FACT19: u1 = 0, + /// Filter active + FACT20: u1 = 0, + /// Filter active + FACT21: u1 = 0, + /// Filter active + FACT22: u1 = 0, + /// Filter active + FACT23: u1 = 0, + /// Filter active + FACT24: u1 = 0, + /// Filter active + FACT25: u1 = 0, + /// Filter active + FACT26: u1 = 0, + /// Filter active + FACT27: u1 = 0, + padding4: u1 = 0, + padding3: u1 = 0, + padding2: u1 = 0, + padding1: u1 = 0, + }); + + /// Filter bank 0 register 1 pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 580 Filter bank 0 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 0 register 2 pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 584 Filter bank 1 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 1 pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 588 Filter bank 1 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 1 register 2 pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 592 Filter bank 2 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 1 pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 596 Filter bank 2 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 2 register 2 pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 600 Filter bank 3 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 1 pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 604 Filter bank 3 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 3 register 2 pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 608 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 612 Filter bank 4 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 2 pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 616 Filter bank 5 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 1 pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 620 Filter bank 5 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 5 register 2 pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 624 Filter bank 6 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 1 pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 628 Filter bank 6 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 6 register 2 pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 632 Filter bank 7 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 1 pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 636 Filter bank 7 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 7 register 2 pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 640 Filter bank 8 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 1 pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 644 Filter bank 8 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 8 register 2 pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 648 Filter bank 9 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 1 pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 652 Filter bank 9 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 9 register 2 pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 656 Filter bank 10 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 1 pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 660 Filter bank 10 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 10 register 2 pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 664 Filter bank 11 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 1 pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 668 Filter bank 11 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 11 register 2 pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 672 Filter bank 4 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 4 register 1 pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 676 Filter bank 12 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 12 register 2 pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 680 Filter bank 13 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 1 pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 684 Filter bank 13 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 13 register 2 pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 688 Filter bank 14 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 14 register 1 pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 692 Filter bank 14 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 14 register 2 pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 696 Filter bank 15 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 15 register 1 pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 700 Filter bank 15 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 15 register 2 pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 704 Filter bank 16 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 16 register 1 pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 708 Filter bank 16 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 16 register 2 pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 712 Filter bank 17 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 17 register 1 pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 716 Filter bank 17 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 17 register 2 pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 720 Filter bank 18 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 18 register 1 pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 724 Filter bank 18 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 18 register 2 pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 728 Filter bank 19 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 19 register 1 pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 732 Filter bank 19 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 19 register 2 pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 736 Filter bank 20 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 20 register 1 pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 740 Filter bank 20 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 20 register 2 pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 744 Filter bank 21 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 21 register 1 pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 748 Filter bank 21 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 21 register 2 pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 752 Filter bank 22 register 1 - pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 756 Filter bank 22 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 22 register 1 + pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 22 register 2 pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 760 Filter bank 23 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 23 register 1 pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 764 Filter bank 23 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 23 register 2 pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 768 Filter bank 24 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 24 register 1 pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 772 Filter bank 24 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 24 register 2 pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 776 Filter bank 25 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 25 register 1 pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 780 Filter bank 25 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 25 register 2 pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 784 Filter bank 26 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 26 register 1 pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 788 Filter bank 26 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 26 register 2 pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 792 Filter bank 27 register 1 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 27 register 1 pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits - }); - // byte offset: 796 Filter bank 27 register 2 + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, + }); + + /// Filter bank 27 register 2 pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { - FB0: u1, // bit offset: 0 desc: Filter bits - FB1: u1, // bit offset: 1 desc: Filter bits - FB2: u1, // bit offset: 2 desc: Filter bits - FB3: u1, // bit offset: 3 desc: Filter bits - FB4: u1, // bit offset: 4 desc: Filter bits - FB5: u1, // bit offset: 5 desc: Filter bits - FB6: u1, // bit offset: 6 desc: Filter bits - FB7: u1, // bit offset: 7 desc: Filter bits - FB8: u1, // bit offset: 8 desc: Filter bits - FB9: u1, // bit offset: 9 desc: Filter bits - FB10: u1, // bit offset: 10 desc: Filter bits - FB11: u1, // bit offset: 11 desc: Filter bits - FB12: u1, // bit offset: 12 desc: Filter bits - FB13: u1, // bit offset: 13 desc: Filter bits - FB14: u1, // bit offset: 14 desc: Filter bits - FB15: u1, // bit offset: 15 desc: Filter bits - FB16: u1, // bit offset: 16 desc: Filter bits - FB17: u1, // bit offset: 17 desc: Filter bits - FB18: u1, // bit offset: 18 desc: Filter bits - FB19: u1, // bit offset: 19 desc: Filter bits - FB20: u1, // bit offset: 20 desc: Filter bits - FB21: u1, // bit offset: 21 desc: Filter bits - FB22: u1, // bit offset: 22 desc: Filter bits - FB23: u1, // bit offset: 23 desc: Filter bits - FB24: u1, // bit offset: 24 desc: Filter bits - FB25: u1, // bit offset: 25 desc: Filter bits - FB26: u1, // bit offset: 26 desc: Filter bits - FB27: u1, // bit offset: 27 desc: Filter bits - FB28: u1, // bit offset: 28 desc: Filter bits - FB29: u1, // bit offset: 29 desc: Filter bits - FB30: u1, // bit offset: 30 desc: Filter bits - FB31: u1, // bit offset: 31 desc: Filter bits + /// Filter bits + FB0: u1 = 0, + /// Filter bits + FB1: u1 = 0, + /// Filter bits + FB2: u1 = 0, + /// Filter bits + FB3: u1 = 0, + /// Filter bits + FB4: u1 = 0, + /// Filter bits + FB5: u1 = 0, + /// Filter bits + FB6: u1 = 0, + /// Filter bits + FB7: u1 = 0, + /// Filter bits + FB8: u1 = 0, + /// Filter bits + FB9: u1 = 0, + /// Filter bits + FB10: u1 = 0, + /// Filter bits + FB11: u1 = 0, + /// Filter bits + FB12: u1 = 0, + /// Filter bits + FB13: u1 = 0, + /// Filter bits + FB14: u1 = 0, + /// Filter bits + FB15: u1 = 0, + /// Filter bits + FB16: u1 = 0, + /// Filter bits + FB17: u1 = 0, + /// Filter bits + FB18: u1 = 0, + /// Filter bits + FB19: u1 = 0, + /// Filter bits + FB20: u1 = 0, + /// Filter bits + FB21: u1 = 0, + /// Filter bits + FB22: u1 = 0, + /// Filter bits + FB23: u1 = 0, + /// Filter bits + FB24: u1 = 0, + /// Filter bits + FB25: u1 = 0, + /// Filter bits + FB26: u1 = 0, + /// Filter bits + FB27: u1 = 0, + /// Filter bits + FB28: u1 = 0, + /// Filter bits + FB29: u1 = 0, + /// Filter bits + FB30: u1 = 0, + /// Filter bits + FB31: u1 = 0, }); }; + +/// Universal serial bus full-speed device interface pub const USB_FS = extern struct { pub const Address: u32 = 0x40005c00; - // byte offset: 0 endpoint 0 register + + /// endpoint 0 register pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13172,18 +19175,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 endpoint 1 register + + /// endpoint 1 register pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13201,18 +19215,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 endpoint 2 register + + /// endpoint 2 register pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13230,18 +19255,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 endpoint 3 register + + /// endpoint 3 register pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13259,18 +19295,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 endpoint 4 register + + /// endpoint 4 register pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13288,18 +19335,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 endpoint 5 register + + /// endpoint 5 register pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13317,18 +19375,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 endpoint 6 register + + /// endpoint 6 register pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13346,18 +19415,29 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 endpoint 7 register + + /// endpoint 7 register pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { - EA: u4, // bit offset: 0 desc: Endpoint address - STAT_TX: u2, // bit offset: 4 desc: Status bits, for transmission transfers - DTOG_TX: u1, // bit offset: 6 desc: Data Toggle, for transmission transfers - CTR_TX: u1, // bit offset: 7 desc: Correct Transfer for transmission - EP_KIND: u1, // bit offset: 8 desc: Endpoint kind - EP_TYPE: u2, // bit offset: 9 desc: Endpoint type - SETUP: u1, // bit offset: 11 desc: Setup transaction completed - STAT_RX: u2, // bit offset: 12 desc: Status bits, for reception transfers - DTOG_RX: u1, // bit offset: 14 desc: Data Toggle, for reception transfers - CTR_RX: u1, // bit offset: 15 desc: Correct transfer for reception + /// Endpoint address + EA: u4 = 0, + /// Status bits, for transmission transfers + STAT_TX: u2 = 0, + /// Data Toggle, for transmission transfers + DTOG_TX: u1 = 0, + /// Correct Transfer for transmission + CTR_TX: u1 = 0, + /// Endpoint kind + EP_KIND: u1 = 0, + /// Endpoint type + EP_TYPE: u2 = 0, + /// Setup transaction completed + SETUP: u1 = 0, + /// Status bits, for reception transfers + STAT_RX: u2 = 0, + /// Data Toggle, for reception transfers + DTOG_RX: u1 = 0, + /// Correct transfer for reception + CTR_RX: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13375,24 +19455,38 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 control register + + /// control register pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { - FRES: u1, // bit offset: 0 desc: Force USB Reset - PDWN: u1, // bit offset: 1 desc: Power down - LPMODE: u1, // bit offset: 2 desc: Low-power mode - FSUSP: u1, // bit offset: 3 desc: Force suspend - RESUME: u1, // bit offset: 4 desc: Resume request + /// Force USB Reset + FRES: u1 = 0, + /// Power down + PDWN: u1 = 0, + /// Low-power mode + LPMODE: u1 = 0, + /// Force suspend + FSUSP: u1 = 0, + /// Resume request + RESUME: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOFM: u1, // bit offset: 8 desc: Expected start of frame interrupt mask - SOFM: u1, // bit offset: 9 desc: Start of frame interrupt mask - RESETM: u1, // bit offset: 10 desc: USB reset interrupt mask - SUSPM: u1, // bit offset: 11 desc: Suspend mode interrupt mask - WKUPM: u1, // bit offset: 12 desc: Wakeup interrupt mask - ERRM: u1, // bit offset: 13 desc: Error interrupt mask - PMAOVRM: u1, // bit offset: 14 desc: Packet memory area over / underrun interrupt mask - CTRM: u1, // bit offset: 15 desc: Correct transfer interrupt mask + /// Expected start of frame interrupt mask + ESOFM: u1 = 0, + /// Start of frame interrupt mask + SOFM: u1 = 0, + /// USB reset interrupt mask + RESETM: u1 = 0, + /// Suspend mode interrupt mask + SUSPM: u1 = 0, + /// Wakeup interrupt mask + WKUPM: u1 = 0, + /// Error interrupt mask + ERRM: u1 = 0, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1 = 0, + /// Correct transfer interrupt mask + CTRM: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13410,21 +19504,32 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 interrupt status register + + /// interrupt status register pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - EP_ID: u4, // bit offset: 0 desc: Endpoint Identifier - DIR: u1, // bit offset: 4 desc: Direction of transaction + /// Endpoint Identifier + EP_ID: u4 = 0, + /// Direction of transaction + DIR: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ESOF: u1, // bit offset: 8 desc: Expected start frame - SOF: u1, // bit offset: 9 desc: start of frame - RESET: u1, // bit offset: 10 desc: reset request - SUSP: u1, // bit offset: 11 desc: Suspend mode request - WKUP: u1, // bit offset: 12 desc: Wakeup - ERR: u1, // bit offset: 13 desc: Error - PMAOVR: u1, // bit offset: 14 desc: Packet memory area over / underrun - CTR: u1, // bit offset: 15 desc: Correct transfer + /// Expected start frame + ESOF: u1 = 0, + /// start of frame + SOF: u1 = 0, + /// reset request + RESET: u1 = 0, + /// Suspend mode request + SUSP: u1 = 0, + /// Wakeup + WKUP: u1 = 0, + /// Error + ERR: u1 = 0, + /// Packet memory area over / underrun + PMAOVR: u1 = 0, + /// Correct transfer + CTR: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13442,13 +19547,19 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 frame number register + + /// frame number register pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - FN: u11, // bit offset: 0 desc: Frame number - LSOF: u2, // bit offset: 11 desc: Lost SOF - LCK: u1, // bit offset: 13 desc: Locked - RXDM: u1, // bit offset: 14 desc: Receive data - line status - RXDP: u1, // bit offset: 15 desc: Receive data + line status + /// Frame number + FN: u11 = 0, + /// Lost SOF + LSOF: u2 = 0, + /// Locked + LCK: u1 = 0, + /// Receive data - line status + RXDM: u1 = 0, + /// Receive data + line status + RXDP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13466,16 +19577,25 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 device address + + /// device address pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - ADD: u1, // bit offset: 0 desc: Device address - ADD1: u1, // bit offset: 1 desc: Device address - ADD2: u1, // bit offset: 2 desc: Device address - ADD3: u1, // bit offset: 3 desc: Device address - ADD4: u1, // bit offset: 4 desc: Device address - ADD5: u1, // bit offset: 5 desc: Device address - ADD6: u1, // bit offset: 6 desc: Device address - EF: u1, // bit offset: 7 desc: Enable function + /// Device address + ADD: u1 = 0, + /// Device address + ADD1: u1 = 0, + /// Device address + ADD2: u1 = 0, + /// Device address + ADD3: u1 = 0, + /// Device address + ADD4: u1 = 0, + /// Device address + ADD5: u1 = 0, + /// Device address + ADD6: u1 = 0, + /// Enable function + EF: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13501,12 +19621,14 @@ pub const USB_FS = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 Buffer table address + + /// Buffer table address pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - BTABLE: u13, // bit offset: 3 desc: Buffer table + /// Buffer table + BTABLE: u13 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13525,31 +19647,55 @@ pub const USB_FS = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C1 = extern struct { pub const Address: u32 = 0x40005400; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13559,38 +19705,58 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13608,16 +19774,20 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13635,51 +19805,81 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13689,22 +19889,32 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -13724,9 +19934,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13752,9 +19964,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13780,9 +19994,11 @@ pub const I2C1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -13809,31 +20025,55 @@ pub const I2C1 = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C2 = extern struct { pub const Address: u32 = 0x40005800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13843,38 +20083,58 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13892,16 +20152,20 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -13919,51 +20183,81 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -13973,22 +20267,32 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14008,9 +20312,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14036,9 +20342,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14064,9 +20372,11 @@ pub const I2C2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14093,31 +20403,55 @@ pub const I2C2 = extern struct { padding1: u1 = 0, }); }; + +/// Inter-integrated circuit pub const I2C3 = extern struct { pub const Address: u32 = 0x40007800; - // byte offset: 0 Control register 1 + + /// Control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - PE: u1, // bit offset: 0 desc: Peripheral enable - TXIE: u1, // bit offset: 1 desc: TX Interrupt enable - RXIE: u1, // bit offset: 2 desc: RX Interrupt enable - ADDRIE: u1, // bit offset: 3 desc: Address match interrupt enable (slave only) - NACKIE: u1, // bit offset: 4 desc: Not acknowledge received interrupt enable - STOPIE: u1, // bit offset: 5 desc: STOP detection Interrupt enable - TCIE: u1, // bit offset: 6 desc: Transfer Complete interrupt enable - ERRIE: u1, // bit offset: 7 desc: Error interrupts enable - DNF: u4, // bit offset: 8 desc: Digital noise filter - ANFOFF: u1, // bit offset: 12 desc: Analog noise filter OFF - SWRST: u1, // bit offset: 13 desc: Software reset - TXDMAEN: u1, // bit offset: 14 desc: DMA transmission requests enable - RXDMAEN: u1, // bit offset: 15 desc: DMA reception requests enable - SBC: u1, // bit offset: 16 desc: Slave byte control - NOSTRETCH: u1, // bit offset: 17 desc: Clock stretching disable - WUPEN: u1, // bit offset: 18 desc: Wakeup from STOP enable - GCEN: u1, // bit offset: 19 desc: General call enable - SMBHEN: u1, // bit offset: 20 desc: SMBus Host address enable - SMBDEN: u1, // bit offset: 21 desc: SMBus Device Default address enable - ALERTEN: u1, // bit offset: 22 desc: SMBUS alert enable - PECEN: u1, // bit offset: 23 desc: PEC enable + /// Peripheral enable + PE: u1 = 0, + /// TX Interrupt enable + TXIE: u1 = 0, + /// RX Interrupt enable + RXIE: u1 = 0, + /// Address match interrupt enable (slave only) + ADDRIE: u1 = 0, + /// Not acknowledge received interrupt enable + NACKIE: u1 = 0, + /// STOP detection Interrupt enable + STOPIE: u1 = 0, + /// Transfer Complete interrupt enable + TCIE: u1 = 0, + /// Error interrupts enable + ERRIE: u1 = 0, + /// Digital noise filter + DNF: u4 = 0, + /// Analog noise filter OFF + ANFOFF: u1 = 0, + /// Software reset + SWRST: u1 = 0, + /// DMA transmission requests enable + TXDMAEN: u1 = 0, + /// DMA reception requests enable + RXDMAEN: u1 = 0, + /// Slave byte control + SBC: u1 = 0, + /// Clock stretching disable + NOSTRETCH: u1 = 0, + /// Wakeup from STOP enable + WUPEN: u1 = 0, + /// General call enable + GCEN: u1 = 0, + /// SMBus Host address enable + SMBHEN: u1 = 0, + /// SMBus Device Default address enable + SMBDEN: u1 = 0, + /// SMBUS alert enable + ALERTEN: u1 = 0, + /// PEC enable + PECEN: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14127,38 +20461,58 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Control register 2 + + /// Control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - SADD0: u1, // bit offset: 0 desc: Slave address bit 0 (master mode) - SADD1: u7, // bit offset: 1 desc: Slave address bit 7:1 (master mode) - SADD8: u2, // bit offset: 8 desc: Slave address bit 9:8 (master mode) - RD_WRN: u1, // bit offset: 10 desc: Transfer direction (master mode) - ADD10: u1, // bit offset: 11 desc: 10-bit addressing mode (master mode) - HEAD10R: u1, // bit offset: 12 desc: 10-bit address header only read direction (master receiver mode) - START: u1, // bit offset: 13 desc: Start generation - STOP: u1, // bit offset: 14 desc: Stop generation (master mode) - NACK: u1, // bit offset: 15 desc: NACK generation (slave mode) - NBYTES: u8, // bit offset: 16 desc: Number of bytes - RELOAD: u1, // bit offset: 24 desc: NBYTES reload mode - AUTOEND: u1, // bit offset: 25 desc: Automatic end mode (master mode) - PECBYTE: u1, // bit offset: 26 desc: Packet error checking byte + /// Slave address bit 0 (master mode) + SADD0: u1 = 0, + /// Slave address bit 7:1 (master mode) + SADD1: u7 = 0, + /// Slave address bit 9:8 (master mode) + SADD8: u2 = 0, + /// Transfer direction (master mode) + RD_WRN: u1 = 0, + /// 10-bit addressing mode (master mode) + ADD10: u1 = 0, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1 = 0, + /// Start generation + START: u1 = 0, + /// Stop generation (master mode) + STOP: u1 = 0, + /// NACK generation (slave mode) + NACK: u1 = 0, + /// Number of bytes + NBYTES: u8 = 0, + /// NBYTES reload mode + RELOAD: u1 = 0, + /// Automatic end mode (master mode) + AUTOEND: u1 = 0, + /// Packet error checking byte + PECBYTE: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Own address register 1 + + /// Own address register 1 pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - OA1_0: u1, // bit offset: 0 desc: Interface address - OA1_1: u7, // bit offset: 1 desc: Interface address - OA1_8: u2, // bit offset: 8 desc: Interface address - OA1MODE: u1, // bit offset: 10 desc: Own Address 1 10-bit mode + /// Interface address + OA1_0: u1 = 0, + /// Interface address + OA1_1: u7 = 0, + /// Interface address + OA1_8: u2 = 0, + /// Own Address 1 10-bit mode + OA1MODE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OA1EN: u1, // bit offset: 15 desc: Own Address 1 enable + /// Own Address 1 enable + OA1EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14176,16 +20530,20 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Own address register 2 + + /// Own address register 2 pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { reserved1: u1 = 0, - OA2: u7, // bit offset: 1 desc: Interface address - OA2MSK: u3, // bit offset: 8 desc: Own Address 2 masks + /// Interface address + OA2: u7 = 0, + /// Own Address 2 masks + OA2MSK: u3 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - OA2EN: u1, // bit offset: 15 desc: Own Address 2 enable + /// Own Address 2 enable + OA2EN: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14203,51 +20561,81 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Timing register + + /// Timing register pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - SCLL: u8, // bit offset: 0 desc: SCL low period (master mode) - SCLH: u8, // bit offset: 8 desc: SCL high period (master mode) - SDADEL: u4, // bit offset: 16 desc: Data hold time - SCLDEL: u4, // bit offset: 20 desc: Data setup time + /// SCL low period (master mode) + SCLL: u8 = 0, + /// SCL high period (master mode) + SCLH: u8 = 0, + /// Data hold time + SDADEL: u4 = 0, + /// Data setup time + SCLDEL: u4 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRESC: u4, // bit offset: 28 desc: Timing prescaler + /// Timing prescaler + PRESC: u4 = 0, }); - // byte offset: 20 Status register 1 + + /// Status register 1 pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - TIMEOUTA: u12, // bit offset: 0 desc: Bus timeout A - TIDLE: u1, // bit offset: 12 desc: Idle clock timeout detection + /// Bus timeout A + TIMEOUTA: u12 = 0, + /// Idle clock timeout detection + TIDLE: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TIMOUTEN: u1, // bit offset: 15 desc: Clock timeout enable - TIMEOUTB: u12, // bit offset: 16 desc: Bus timeout B + /// Clock timeout enable + TIMOUTEN: u1 = 0, + /// Bus timeout B + TIMEOUTB: u12 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - TEXTEN: u1, // bit offset: 31 desc: Extended clock timeout enable + /// Extended clock timeout enable + TEXTEN: u1 = 0, }); - // byte offset: 24 Interrupt and Status register + + /// Interrupt and Status register pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - TXE: u1, // bit offset: 0 desc: Transmit data register empty (transmitters) - TXIS: u1, // bit offset: 1 desc: Transmit interrupt status (transmitters) - RXNE: u1, // bit offset: 2 desc: Receive data register not empty (receivers) - ADDR: u1, // bit offset: 3 desc: Address matched (slave mode) - NACKF: u1, // bit offset: 4 desc: Not acknowledge received flag - STOPF: u1, // bit offset: 5 desc: Stop detection flag - TC: u1, // bit offset: 6 desc: Transfer Complete (master mode) - TCR: u1, // bit offset: 7 desc: Transfer Complete Reload - BERR: u1, // bit offset: 8 desc: Bus error - ARLO: u1, // bit offset: 9 desc: Arbitration lost - OVR: u1, // bit offset: 10 desc: Overrun/Underrun (slave mode) - PECERR: u1, // bit offset: 11 desc: PEC Error in reception - TIMEOUT: u1, // bit offset: 12 desc: Timeout or t_low detection flag - ALERT: u1, // bit offset: 13 desc: SMBus alert - reserved1: u1 = 0, - BUSY: u1, // bit offset: 15 desc: Bus busy - DIR: u1, // bit offset: 16 desc: Transfer direction (Slave mode) - ADDCODE: u7, // bit offset: 17 desc: Address match code (Slave mode) + /// Transmit data register empty (transmitters) + TXE: u1 = 0, + /// Transmit interrupt status (transmitters) + TXIS: u1 = 0, + /// Receive data register not empty (receivers) + RXNE: u1 = 0, + /// Address matched (slave mode) + ADDR: u1 = 0, + /// Not acknowledge received flag + NACKF: u1 = 0, + /// Stop detection flag + STOPF: u1 = 0, + /// Transfer Complete (master mode) + TC: u1 = 0, + /// Transfer Complete Reload + TCR: u1 = 0, + /// Bus error + BERR: u1 = 0, + /// Arbitration lost + ARLO: u1 = 0, + /// Overrun/Underrun (slave mode) + OVR: u1 = 0, + /// PEC Error in reception + PECERR: u1 = 0, + /// Timeout or t_low detection flag + TIMEOUT: u1 = 0, + /// SMBus alert + ALERT: u1 = 0, + reserved1: u1 = 0, + /// Bus busy + BUSY: u1 = 0, + /// Transfer direction (Slave mode) + DIR: u1 = 0, + /// Address match code (Slave mode) + ADDCODE: u7 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14257,22 +20645,32 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 Interrupt clear register + + /// Interrupt clear register pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRCF: u1, // bit offset: 3 desc: Address Matched flag clear - NACKCF: u1, // bit offset: 4 desc: Not Acknowledge flag clear - STOPCF: u1, // bit offset: 5 desc: Stop detection flag clear + /// Address Matched flag clear + ADDRCF: u1 = 0, + /// Not Acknowledge flag clear + NACKCF: u1 = 0, + /// Stop detection flag clear + STOPCF: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - BERRCF: u1, // bit offset: 8 desc: Bus error flag clear - ARLOCF: u1, // bit offset: 9 desc: Arbitration lost flag clear - OVRCF: u1, // bit offset: 10 desc: Overrun/Underrun flag clear - PECCF: u1, // bit offset: 11 desc: PEC Error flag clear - TIMOUTCF: u1, // bit offset: 12 desc: Timeout detection flag clear - ALERTCF: u1, // bit offset: 13 desc: Alert flag clear + /// Bus error flag clear + BERRCF: u1 = 0, + /// Arbitration lost flag clear + ARLOCF: u1 = 0, + /// Overrun/Underrun flag clear + OVRCF: u1 = 0, + /// PEC Error flag clear + PECCF: u1 = 0, + /// Timeout detection flag clear + TIMOUTCF: u1 = 0, + /// Alert flag clear + ALERTCF: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, @@ -14292,9 +20690,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 PEC register + + /// PEC register pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - PEC: u8, // bit offset: 0 desc: Packet error checking register + /// Packet error checking register + PEC: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14320,9 +20720,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 Receive data register + + /// Receive data register pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: 8-bit receive data + /// 8-bit receive data + RXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14348,9 +20750,11 @@ pub const I2C3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Transmit data register + + /// Transmit data register pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: 8-bit transmit data + /// 8-bit transmit data + TXDATA: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14377,11 +20781,15 @@ pub const I2C3 = extern struct { padding1: u1 = 0, }); }; + +/// Independent watchdog pub const IWDG = extern struct { pub const Address: u32 = 0x40003000; - // byte offset: 0 Key register + + /// Key register pub const KR = mmio(Address + 0x00000000, 32, packed struct { - KEY: u16, // bit offset: 0 desc: Key value + /// Key value + KEY: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14399,9 +20807,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Prescaler register + + /// Prescaler register pub const PR = mmio(Address + 0x00000004, 32, packed struct { - PR: u3, // bit offset: 0 desc: Prescaler divider + /// Prescaler divider + PR: u3 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -14432,9 +20842,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Reload register + + /// Reload register pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - RL: u12, // bit offset: 0 desc: Watchdog counter reload value + /// Watchdog counter reload value + RL: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14456,11 +20868,15 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Status register + + /// Status register pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - PVU: u1, // bit offset: 0 desc: Watchdog prescaler value update - RVU: u1, // bit offset: 1 desc: Watchdog counter reload value update - WVU: u1, // bit offset: 2 desc: Watchdog counter window value update + /// Watchdog prescaler value update + PVU: u1 = 0, + /// Watchdog counter reload value update + RVU: u1 = 0, + /// Watchdog counter window value update + WVU: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -14491,9 +20907,11 @@ pub const IWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 Window register + + /// Window register pub const WINR = mmio(Address + 0x00000010, 32, packed struct { - WIN: u12, // bit offset: 0 desc: Watchdog counter window value + /// Watchdog counter window value + WIN: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -14516,12 +20934,17 @@ pub const IWDG = extern struct { padding1: u1 = 0, }); }; + +/// Window watchdog pub const WWDG = extern struct { pub const Address: u32 = 0x40002c00; - // byte offset: 0 Control register + + /// Control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - T: u7, // bit offset: 0 desc: 7-bit counter - WDGA: u1, // bit offset: 7 desc: Activation bit + /// 7-bit counter + T: u7 = 0, + /// Activation bit + WDGA: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14547,11 +20970,15 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 Configuration register + + /// Configuration register pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - W: u7, // bit offset: 0 desc: 7-bit window value - WDGTB: u2, // bit offset: 7 desc: Timer base - EWI: u1, // bit offset: 9 desc: Early wakeup interrupt + /// 7-bit window value + W: u7 = 0, + /// Timer base + WDGTB: u2 = 0, + /// Early wakeup interrupt + EWI: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -14575,9 +21002,11 @@ pub const WWDG = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 Status register + + /// Status register pub const SR = mmio(Address + 0x00000008, 32, packed struct { - EWIF: u1, // bit offset: 0 desc: Early wakeup interrupt flag + /// Early wakeup interrupt flag + EWIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -14611,19 +21040,29 @@ pub const WWDG = extern struct { padding1: u1 = 0, }); }; + +/// Real-time clock pub const RTC = extern struct { pub const Address: u32 = 0x40002800; - // byte offset: 0 time register + + /// time register pub const TR = mmio(Address + 0x00000000, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14634,17 +21073,25 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 date register + + /// date register pub const DR = mmio(Address + 0x00000004, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format + /// Date units in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units - YU: u4, // bit offset: 16 desc: Year units in BCD format - YT: u4, // bit offset: 20 desc: Year tens in BCD format + /// Month units in BCD format + MU: u4 = 0, + /// Month tens in BCD format + MT: u1 = 0, + /// Week day units + WDU: u3 = 0, + /// Year units in BCD format + YU: u4 = 0, + /// Year tens in BCD format + YT: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14654,29 +21101,50 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - WCKSEL: u3, // bit offset: 0 desc: Wakeup clock selection - TSEDGE: u1, // bit offset: 3 desc: Time-stamp event active edge - REFCKON: u1, // bit offset: 4 desc: Reference clock detection enable (50 or 60 Hz) - BYPSHAD: u1, // bit offset: 5 desc: Bypass the shadow registers - FMT: u1, // bit offset: 6 desc: Hour format - reserved1: u1 = 0, - ALRAE: u1, // bit offset: 8 desc: Alarm A enable - ALRBE: u1, // bit offset: 9 desc: Alarm B enable - WUTE: u1, // bit offset: 10 desc: Wakeup timer enable - TSE: u1, // bit offset: 11 desc: Time stamp enable - ALRAIE: u1, // bit offset: 12 desc: Alarm A interrupt enable - ALRBIE: u1, // bit offset: 13 desc: Alarm B interrupt enable - WUTIE: u1, // bit offset: 14 desc: Wakeup timer interrupt enable - TSIE: u1, // bit offset: 15 desc: Time-stamp interrupt enable - ADD1H: u1, // bit offset: 16 desc: Add 1 hour (summer time change) - SUB1H: u1, // bit offset: 17 desc: Subtract 1 hour (winter time change) - BKP: u1, // bit offset: 18 desc: Backup - COSEL: u1, // bit offset: 19 desc: Calibration output selection - POL: u1, // bit offset: 20 desc: Output polarity - OSEL: u2, // bit offset: 21 desc: Output selection - COE: u1, // bit offset: 23 desc: Calibration output enable + /// Wakeup clock selection + WCKSEL: u3 = 0, + /// Time-stamp event active edge + TSEDGE: u1 = 0, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1 = 0, + /// Bypass the shadow registers + BYPSHAD: u1 = 0, + /// Hour format + FMT: u1 = 0, + reserved1: u1 = 0, + /// Alarm A enable + ALRAE: u1 = 0, + /// Alarm B enable + ALRBE: u1 = 0, + /// Wakeup timer enable + WUTE: u1 = 0, + /// Time stamp enable + TSE: u1 = 0, + /// Alarm A interrupt enable + ALRAIE: u1 = 0, + /// Alarm B interrupt enable + ALRBIE: u1 = 0, + /// Wakeup timer interrupt enable + WUTIE: u1 = 0, + /// Time-stamp interrupt enable + TSIE: u1 = 0, + /// Add 1 hour (summer time change) + ADD1H: u1 = 0, + /// Subtract 1 hour (winter time change) + SUB1H: u1 = 0, + /// Backup + BKP: u1 = 0, + /// Calibration output selection + COSEL: u1 = 0, + /// Output polarity + POL: u1 = 0, + /// Output selection + OSEL: u2 = 0, + /// Calibration output enable + COE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14686,25 +21154,43 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 initialization and status register + + /// initialization and status register pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - ALRAWF: u1, // bit offset: 0 desc: Alarm A write flag - ALRBWF: u1, // bit offset: 1 desc: Alarm B write flag - WUTWF: u1, // bit offset: 2 desc: Wakeup timer write flag - SHPF: u1, // bit offset: 3 desc: Shift operation pending - INITS: u1, // bit offset: 4 desc: Initialization status flag - RSF: u1, // bit offset: 5 desc: Registers synchronization flag - INITF: u1, // bit offset: 6 desc: Initialization flag - INIT: u1, // bit offset: 7 desc: Initialization mode - ALRAF: u1, // bit offset: 8 desc: Alarm A flag - ALRBF: u1, // bit offset: 9 desc: Alarm B flag - WUTF: u1, // bit offset: 10 desc: Wakeup timer flag - TSF: u1, // bit offset: 11 desc: Time-stamp flag - TSOVF: u1, // bit offset: 12 desc: Time-stamp overflow flag - TAMP1F: u1, // bit offset: 13 desc: Tamper detection flag - TAMP2F: u1, // bit offset: 14 desc: RTC_TAMP2 detection flag - TAMP3F: u1, // bit offset: 15 desc: RTC_TAMP3 detection flag - RECALPF: u1, // bit offset: 16 desc: Recalibration pending Flag + /// Alarm A write flag + ALRAWF: u1 = 0, + /// Alarm B write flag + ALRBWF: u1 = 0, + /// Wakeup timer write flag + WUTWF: u1 = 0, + /// Shift operation pending + SHPF: u1 = 0, + /// Initialization status flag + INITS: u1 = 0, + /// Registers synchronization flag + RSF: u1 = 0, + /// Initialization flag + INITF: u1 = 0, + /// Initialization mode + INIT: u1 = 0, + /// Alarm A flag + ALRAF: u1 = 0, + /// Alarm B flag + ALRBF: u1 = 0, + /// Wakeup timer flag + WUTF: u1 = 0, + /// Time-stamp flag + TSF: u1 = 0, + /// Time-stamp overflow flag + TSOVF: u1 = 0, + /// Tamper detection flag + TAMP1F: u1 = 0, + /// RTC_TAMP2 detection flag + TAMP2F: u1 = 0, + /// RTC_TAMP3 detection flag + TAMP3F: u1 = 0, + /// Recalibration pending Flag + RECALPF: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -14721,11 +21207,14 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 prescaler register + + /// prescaler register pub const PRER = mmio(Address + 0x00000010, 32, packed struct { - PREDIV_S: u15, // bit offset: 0 desc: Synchronous prescaler factor + /// Synchronous prescaler factor + PREDIV_S: u15 = 0, reserved1: u1 = 0, - PREDIV_A: u7, // bit offset: 16 desc: Asynchronous prescaler factor + /// Asynchronous prescaler factor + PREDIV_A: u7 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14736,9 +21225,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 wakeup timer register + + /// wakeup timer register pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { - WUT: u16, // bit offset: 0 desc: Wakeup auto-reload value bits + /// Wakeup auto-reload value bits + WUT: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14756,43 +21247,75 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 alarm A register + + /// alarm A register pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm A seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm A minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm A hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm A date mask - }); - // byte offset: 32 alarm B register + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, + /// Alarm A seconds mask + MSK1: u1 = 0, + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, + /// Alarm A minutes mask + MSK2: u1 = 0, + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, + /// Alarm A hours mask + MSK3: u1 = 0, + /// Date units or day in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, + /// Week day selection + WDSEL: u1 = 0, + /// Alarm A date mask + MSK4: u1 = 0, + }); + + /// alarm B register pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format - MSK1: u1, // bit offset: 7 desc: Alarm B seconds mask - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format - MSK2: u1, // bit offset: 15 desc: Alarm B minutes mask - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation - MSK3: u1, // bit offset: 23 desc: Alarm B hours mask - DU: u4, // bit offset: 24 desc: Date units or day in BCD format - DT: u2, // bit offset: 28 desc: Date tens in BCD format - WDSEL: u1, // bit offset: 30 desc: Week day selection - MSK4: u1, // bit offset: 31 desc: Alarm B date mask - }); - // byte offset: 36 write protection register + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, + /// Alarm B seconds mask + MSK1: u1 = 0, + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, + /// Alarm B minutes mask + MSK2: u1 = 0, + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, + /// Alarm B hours mask + MSK3: u1 = 0, + /// Date units or day in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, + /// Week day selection + WDSEL: u1 = 0, + /// Alarm B date mask + MSK4: u1 = 0, + }); + + /// write protection register pub const WPR = mmio(Address + 0x00000024, 32, packed struct { - KEY: u8, // bit offset: 0 desc: Write protection key + /// Write protection key + KEY: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -14818,9 +21341,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 sub second register + + /// sub second register pub const SSR = mmio(Address + 0x00000028, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value + /// Sub second value + SS: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14838,9 +21363,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 shift control register + + /// shift control register pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { - SUBFS: u15, // bit offset: 0 desc: Subtract a fraction of a second + /// Subtract a fraction of a second + SUBFS: u15 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, @@ -14857,19 +21384,28 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADD1S: u1, // bit offset: 31 desc: Add one second + /// Add one second + ADD1S: u1 = 0, }); - // byte offset: 48 time stamp time register + + /// time stamp time register pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { - SU: u4, // bit offset: 0 desc: Second units in BCD format - ST: u3, // bit offset: 4 desc: Second tens in BCD format + /// Second units in BCD format + SU: u4 = 0, + /// Second tens in BCD format + ST: u3 = 0, reserved1: u1 = 0, - MNU: u4, // bit offset: 8 desc: Minute units in BCD format - MNT: u3, // bit offset: 12 desc: Minute tens in BCD format + /// Minute units in BCD format + MNU: u4 = 0, + /// Minute tens in BCD format + MNT: u3 = 0, reserved2: u1 = 0, - HU: u4, // bit offset: 16 desc: Hour units in BCD format - HT: u2, // bit offset: 20 desc: Hour tens in BCD format - PM: u1, // bit offset: 22 desc: AM/PM notation + /// Hour units in BCD format + HU: u4 = 0, + /// Hour tens in BCD format + HT: u2 = 0, + /// AM/PM notation + PM: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -14880,15 +21416,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 time stamp date register + + /// time stamp date register pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { - DU: u4, // bit offset: 0 desc: Date units in BCD format - DT: u2, // bit offset: 4 desc: Date tens in BCD format + /// Date units in BCD format + DU: u4 = 0, + /// Date tens in BCD format + DT: u2 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MU: u4, // bit offset: 8 desc: Month units in BCD format - MT: u1, // bit offset: 12 desc: Month tens in BCD format - WDU: u3, // bit offset: 13 desc: Week day units + /// Month units in BCD format + MU: u4 = 0, + /// Month tens in BCD format + MT: u1 = 0, + /// Week day units + WDU: u3 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14906,9 +21448,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 timestamp sub second register + + /// timestamp sub second register pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { - SS: u16, // bit offset: 0 desc: Sub second value + /// Sub second value + SS: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14926,16 +21470,21 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 calibration register + + /// calibration register pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { - CALM: u9, // bit offset: 0 desc: Calibration minus + /// Calibration minus + CALM: u9 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALW16: u1, // bit offset: 13 desc: Use a 16-second calibration cycle period - CALW8: u1, // bit offset: 14 desc: Use an 8-second calibration cycle period - CALP: u1, // bit offset: 15 desc: Increase frequency of RTC by 488.5 ppm + /// Use a 16-second calibration cycle period + CALW16: u1 = 0, + /// Use an 8-second calibration cycle period + CALW8: u1 = 0, + /// Increase frequency of RTC by 488.5 ppm + CALP: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -14953,28 +21502,47 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 tamper and alternate function configuration register + + /// tamper and alternate function configuration register pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { - TAMP1E: u1, // bit offset: 0 desc: Tamper 1 detection enable - TAMP1TRG: u1, // bit offset: 1 desc: Active level for tamper 1 - TAMPIE: u1, // bit offset: 2 desc: Tamper interrupt enable - TAMP2E: u1, // bit offset: 3 desc: Tamper 2 detection enable - TAMP2TRG: u1, // bit offset: 4 desc: Active level for tamper 2 - TAMP3E: u1, // bit offset: 5 desc: Tamper 3 detection enable - TAMP3TRG: u1, // bit offset: 6 desc: Active level for tamper 3 - TAMPTS: u1, // bit offset: 7 desc: Activate timestamp on tamper detection event - TAMPFREQ: u3, // bit offset: 8 desc: Tamper sampling frequency - TAMPFLT: u2, // bit offset: 11 desc: Tamper filter count - TAMPPRCH: u2, // bit offset: 13 desc: Tamper precharge duration - TAMPPUDIS: u1, // bit offset: 15 desc: TAMPER pull-up disable + /// Tamper 1 detection enable + TAMP1E: u1 = 0, + /// Active level for tamper 1 + TAMP1TRG: u1 = 0, + /// Tamper interrupt enable + TAMPIE: u1 = 0, + /// Tamper 2 detection enable + TAMP2E: u1 = 0, + /// Active level for tamper 2 + TAMP2TRG: u1 = 0, + /// Tamper 3 detection enable + TAMP3E: u1 = 0, + /// Active level for tamper 3 + TAMP3TRG: u1 = 0, + /// Activate timestamp on tamper detection event + TAMPTS: u1 = 0, + /// Tamper sampling frequency + TAMPFREQ: u3 = 0, + /// Tamper filter count + TAMPFLT: u2 = 0, + /// Tamper precharge duration + TAMPPRCH: u2 = 0, + /// TAMPER pull-up disable + TAMPPUDIS: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PC13VALUE: u1, // bit offset: 18 desc: PC13 value - PC13MODE: u1, // bit offset: 19 desc: PC13 mode - PC14VALUE: u1, // bit offset: 20 desc: PC14 value - PC14MODE: u1, // bit offset: 21 desc: PC 14 mode - PC15VALUE: u1, // bit offset: 22 desc: PC15 value - PC15MODE: u1, // bit offset: 23 desc: PC15 mode + /// PC13 value + PC13VALUE: u1 = 0, + /// PC13 mode + PC13MODE: u1 = 0, + /// PC14 value + PC14VALUE: u1 = 0, + /// PC 14 mode + PC14MODE: u1 = 0, + /// PC15 value + PC15VALUE: u1 = 0, + /// PC15 mode + PC15MODE: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -14984,9 +21552,11 @@ pub const RTC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 alarm A sub second register + + /// alarm A sub second register pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value + /// Sub seconds value + SS: u15 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -14996,15 +21566,18 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + /// Mask the most-significant bits starting at this bit + MASKSS: u4 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 alarm B sub second register + + /// alarm B sub second register pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { - SS: u15, // bit offset: 0 desc: Sub seconds value + /// Sub seconds value + SS: u15 = 0, reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -15014,157 +21587,135 @@ pub const RTC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MASKSS: u4, // bit offset: 24 desc: Mask the most-significant bits starting at this bit + /// Mask the most-significant bits starting at this bit + MASKSS: u4 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 80 backup register - pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 84 backup register - pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 88 backup register - pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 92 backup register - pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 96 backup register - pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 100 backup register - pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 104 backup register - pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 108 backup register - pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 112 backup register - pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 116 backup register - pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 120 backup register - pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 124 backup register - pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 128 backup register - pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 132 backup register - pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 136 backup register - pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 140 backup register - pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 144 backup register - pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 148 backup register - pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 152 backup register - pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 156 backup register - pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 160 backup register - pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 164 backup register - pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 168 backup register - pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 172 backup register - pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 176 backup register - pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 180 backup register - pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 184 backup register - pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 188 backup register - pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 192 backup register - pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 196 backup register - pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 200 backup register - pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); - // byte offset: 204 backup register - pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct { - BKP: u32, // bit offset: 0 desc: BKP - }); + + /// backup register + pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct {}); + + /// backup register + pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct {}); + + /// backup register + pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct {}); + + /// backup register + pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct {}); + + /// backup register + pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct {}); + + /// backup register + pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct {}); + + /// backup register + pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct {}); + + /// backup register + pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct {}); + + /// backup register + pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct {}); + + /// backup register + pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct {}); + + /// backup register + pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct {}); + + /// backup register + pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct {}); + + /// backup register + pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct {}); + + /// backup register + pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct {}); + + /// backup register + pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct {}); + + /// backup register + pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// backup register + pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct {}); + + /// backup register + pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct {}); + + /// backup register + pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct {}); + + /// backup register + pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct {}); + + /// backup register + pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct {}); + + /// backup register + pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct {}); + + /// backup register + pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// backup register + pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// backup register + pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// backup register + pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct {}); + + /// backup register + pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct {}); + + /// backup register + pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct {}); + + /// backup register + pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct {}); + + /// backup register + pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct {}); + + /// backup register + pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct {}); + + /// backup register + pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct {}); }; + +/// Basic timers pub const TIM6 = extern struct { pub const Address: u32 = 0x40001000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15186,13 +21737,15 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -15219,9 +21772,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -15229,7 +21784,8 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -15254,9 +21810,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15289,9 +21847,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15324,9 +21884,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -15342,11 +21904,14 @@ pub const TIM6 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15364,9 +21929,11 @@ pub const TIM6 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15385,22 +21952,31 @@ pub const TIM6 = extern struct { padding1: u1 = 0, }); }; + +/// Basic timers pub const TIM7 = extern struct { pub const Address: u32 = 0x40001400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable + /// Auto-reload preload enable + ARPE: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15422,13 +21998,15 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - MMS: u3, // bit offset: 4 desc: Master mode selection + /// Master mode selection + MMS: u3 = 0, padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -15455,9 +22033,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable + /// Update interrupt enable + UIE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -15465,7 +22045,8 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UDE: u1, // bit offset: 8 desc: Update DMA request enable + /// Update DMA request enable + UDE: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -15490,9 +22071,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag + /// Update interrupt flag + UIF: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15525,9 +22108,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation + /// Update generation + UG: u1 = 0, padding31: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, @@ -15560,9 +22145,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: Low counter value + /// Low counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -15578,11 +22165,14 @@ pub const TIM7 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF Copy + /// UIF Copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15600,9 +22190,11 @@ pub const TIM7 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Low Auto-reload value + /// Low Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15621,35 +22213,57 @@ pub const TIM7 = extern struct { padding1: u1 = 0, }); }; + +/// Digital-to-analog converter pub const DAC = extern struct { pub const Address: u32 = 0x40007400; - // byte offset: 0 control register + + /// control register pub const CR = mmio(Address + 0x00000000, 32, packed struct { - EN1: u1, // bit offset: 0 desc: DAC channel1 enable - BOFF1: u1, // bit offset: 1 desc: DAC channel1 output buffer disable - TEN1: u1, // bit offset: 2 desc: DAC channel1 trigger enable - TSEL1: u3, // bit offset: 3 desc: DAC channel1 trigger selection - WAVE1: u2, // bit offset: 6 desc: DAC channel1 noise/triangle wave generation enable - MAMP1: u4, // bit offset: 8 desc: DAC channel1 mask/amplitude selector - DMAEN1: u1, // bit offset: 12 desc: DAC channel1 DMA enable - DMAUDRIE1: u1, // bit offset: 13 desc: DAC channel1 DMA Underrun Interrupt enable - reserved2: u1 = 0, - reserved1: u1 = 0, - EN2: u1, // bit offset: 16 desc: DAC channel2 enable - BOFF2: u1, // bit offset: 17 desc: DAC channel2 output buffer disable - TEN2: u1, // bit offset: 18 desc: DAC channel2 trigger enable - TSEL2: u3, // bit offset: 19 desc: DAC channel2 trigger selection - WAVE2: u2, // bit offset: 22 desc: DAC channel2 noise/triangle wave generation enable - MAMP2: u4, // bit offset: 24 desc: DAC channel2 mask/amplitude selector - DMAEN2: u1, // bit offset: 28 desc: DAC channel2 DMA enable - DMAUDRIE2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun interrupt enable + /// DAC channel1 enable + EN1: u1 = 0, + /// DAC channel1 output buffer disable + BOFF1: u1 = 0, + /// DAC channel1 trigger enable + TEN1: u1 = 0, + /// DAC channel1 trigger selection + TSEL1: u3 = 0, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2 = 0, + /// DAC channel1 mask/amplitude selector + MAMP1: u4 = 0, + /// DAC channel1 DMA enable + DMAEN1: u1 = 0, + /// DAC channel1 DMA Underrun Interrupt enable + DMAUDRIE1: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// DAC channel2 enable + EN2: u1 = 0, + /// DAC channel2 output buffer disable + BOFF2: u1 = 0, + /// DAC channel2 trigger enable + TEN2: u1 = 0, + /// DAC channel2 trigger selection + TSEL2: u3 = 0, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2 = 0, + /// DAC channel2 mask/amplitude selector + MAMP2: u4 = 0, + /// DAC channel2 DMA enable + DMAEN2: u1 = 0, + /// DAC channel2 DMA underrun interrupt enable + DMAUDRIE2: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 software trigger register + + /// software trigger register pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - SWTRIG1: u1, // bit offset: 0 desc: DAC channel1 software trigger - SWTRIG2: u1, // bit offset: 1 desc: DAC channel2 software trigger + /// DAC channel1 software trigger + SWTRIG1: u1 = 0, + /// DAC channel2 software trigger + SWTRIG2: u1 = 0, padding30: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, @@ -15681,9 +22295,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 channel1 12-bit right-aligned data holding register + + /// channel1 12-bit right-aligned data holding register pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15705,13 +22321,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 channel1 12-bit left aligned data holding register + + /// channel1 12-bit left aligned data holding register pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15729,9 +22347,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 channel1 8-bit right aligned data holding register + + /// channel1 8-bit right aligned data holding register pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -15757,9 +22377,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 channel2 12-bit right aligned data holding register + + /// channel2 12-bit right aligned data holding register pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - DACC2DHR: u12, // bit offset: 0 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15781,13 +22403,15 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 channel2 12-bit left aligned data holding register + + /// channel2 12-bit left aligned data holding register pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 4 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15805,9 +22429,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 channel2 8-bit right-aligned data holding register + + /// channel2 8-bit right-aligned data holding register pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - DACC2DHR: u8, // bit offset: 0 desc: DAC channel2 8-bit right-aligned data + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -15833,36 +22459,45 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 Dual DAC 12-bit right-aligned data holding register + + /// Dual DAC 12-bit right-aligned data holding register pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - DACC1DHR: u12, // bit offset: 0 desc: DAC channel1 12-bit right-aligned data + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC2DHR: u12, // bit offset: 16 desc: DAC channel2 12-bit right-aligned data + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 DUAL DAC 12-bit left aligned data holding register + + /// DUAL DAC 12-bit left aligned data holding register pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DACC1DHR: u12, // bit offset: 4 desc: DAC channel1 12-bit left-aligned data + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - DACC2DHR: u12, // bit offset: 20 desc: DAC channel2 12-bit left-aligned data + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12 = 0, }); - // byte offset: 40 DUAL DAC 8-bit right aligned data holding register + + /// DUAL DAC 8-bit right aligned data holding register pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - DACC1DHR: u8, // bit offset: 0 desc: DAC channel1 8-bit right-aligned data - DACC2DHR: u8, // bit offset: 8 desc: DAC channel2 8-bit right-aligned data + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8 = 0, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -15880,9 +22515,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 channel1 data output register + + /// channel1 data output register pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - DACC1DOR: u12, // bit offset: 0 desc: DAC channel1 data output + /// DAC channel1 data output + DACC1DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15904,9 +22541,11 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 channel2 data output register + + /// channel2 data output register pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - DACC2DOR: u12, // bit offset: 0 desc: DAC channel2 data output + /// DAC channel2 data output + DACC2DOR: u12 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -15928,7 +22567,8 @@ pub const DAC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 status register + + /// status register pub const SR = mmio(Address + 0x00000034, 32, packed struct { reserved13: u1 = 0, reserved12: u1 = 0, @@ -15943,7 +22583,8 @@ pub const DAC = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DMAUDR1: u1, // bit offset: 13 desc: DAC channel1 DMA underrun flag + /// DAC channel1 DMA underrun flag + DMAUDR1: u1 = 0, reserved28: u1 = 0, reserved27: u1 = 0, reserved26: u1 = 0, @@ -15959,31 +22600,43 @@ pub const DAC = extern struct { reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, - DMAUDR2: u1, // bit offset: 29 desc: DAC channel2 DMA underrun flag + /// DAC channel2 DMA underrun flag + DMAUDR2: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Debug support pub const DBGMCU = extern struct { pub const Address: u32 = 0xe0042000; - // byte offset: 0 MCU Device ID Code Register + + /// MCU Device ID Code Register pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - DEV_ID: u12, // bit offset: 0 desc: Device Identifier + /// Device Identifier + DEV_ID: u12 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - REV_ID: u16, // bit offset: 16 desc: Revision Identifier + /// Revision Identifier + REV_ID: u16 = 0, }); - // byte offset: 4 Debug MCU Configuration Register + + /// Debug MCU Configuration Register pub const CR = mmio(Address + 0x00000004, 32, packed struct { - DBG_SLEEP: u1, // bit offset: 0 desc: Debug Sleep mode - DBG_STOP: u1, // bit offset: 1 desc: Debug Stop Mode - DBG_STANDBY: u1, // bit offset: 2 desc: Debug Standby Mode - reserved2: u1 = 0, - reserved1: u1 = 0, - TRACE_IOEN: u1, // bit offset: 5 desc: Trace pin assignment control - TRACE_MODE: u2, // bit offset: 6 desc: Trace pin assignment control + /// Debug Sleep mode + DBG_SLEEP: u1 = 0, + /// Debug Stop Mode + DBG_STOP: u1 = 0, + /// Debug Standby Mode + DBG_STANDBY: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Trace pin assignment control + TRACE_IOEN: u1 = 0, + /// Trace pin assignment control + TRACE_MODE: u2 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -16009,21 +22662,35 @@ pub const DBGMCU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 APB Low Freeze Register + + /// APB Low Freeze Register pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { - DBG_TIM2_STOP: u1, // bit offset: 0 desc: Debug Timer 2 stopped when Core is halted - DBG_TIM3_STOP: u1, // bit offset: 1 desc: Debug Timer 3 stopped when Core is halted - DBG_TIM4_STOP: u1, // bit offset: 2 desc: Debug Timer 4 stopped when Core is halted - DBG_TIM5_STOP: u1, // bit offset: 3 desc: Debug Timer 5 stopped when Core is halted - DBG_TIM6_STOP: u1, // bit offset: 4 desc: Debug Timer 6 stopped when Core is halted - DBG_TIM7_STOP: u1, // bit offset: 5 desc: Debug Timer 7 stopped when Core is halted - DBG_TIM12_STOP: u1, // bit offset: 6 desc: Debug Timer 12 stopped when Core is halted - DBG_TIM13_STOP: u1, // bit offset: 7 desc: Debug Timer 13 stopped when Core is halted - DBG_TIMER14_STOP: u1, // bit offset: 8 desc: Debug Timer 14 stopped when Core is halted - DBG_TIM18_STOP: u1, // bit offset: 9 desc: Debug Timer 18 stopped when Core is halted - DBG_RTC_STOP: u1, // bit offset: 10 desc: Debug RTC stopped when Core is halted - DBG_WWDG_STOP: u1, // bit offset: 11 desc: Debug Window Wachdog stopped when Core is halted - DBG_IWDG_STOP: u1, // bit offset: 12 desc: Debug Independent Wachdog stopped when Core is halted + /// Debug Timer 2 stopped when Core is halted + DBG_TIM2_STOP: u1 = 0, + /// Debug Timer 3 stopped when Core is halted + DBG_TIM3_STOP: u1 = 0, + /// Debug Timer 4 stopped when Core is halted + DBG_TIM4_STOP: u1 = 0, + /// Debug Timer 5 stopped when Core is halted + DBG_TIM5_STOP: u1 = 0, + /// Debug Timer 6 stopped when Core is halted + DBG_TIM6_STOP: u1 = 0, + /// Debug Timer 7 stopped when Core is halted + DBG_TIM7_STOP: u1 = 0, + /// Debug Timer 12 stopped when Core is halted + DBG_TIM12_STOP: u1 = 0, + /// Debug Timer 13 stopped when Core is halted + DBG_TIM13_STOP: u1 = 0, + /// Debug Timer 14 stopped when Core is halted + DBG_TIMER14_STOP: u1 = 0, + /// Debug Timer 18 stopped when Core is halted + DBG_TIM18_STOP: u1 = 0, + /// Debug RTC stopped when Core is halted + DBG_RTC_STOP: u1 = 0, + /// Debug Window Wachdog stopped when Core is halted + DBG_WWDG_STOP: u1 = 0, + /// Debug Independent Wachdog stopped when Core is halted + DBG_IWDG_STOP: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -16032,11 +22699,14 @@ pub const DBGMCU = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - I2C1_SMBUS_TIMEOUT: u1, // bit offset: 21 desc: SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1, // bit offset: 22 desc: SMBUS timeout mode stopped when Core is halted + /// SMBUS timeout mode stopped when Core is halted + I2C1_SMBUS_TIMEOUT: u1 = 0, + /// SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, - DBG_CAN_STOP: u1, // bit offset: 25 desc: Debug CAN stopped when core is halted + /// Debug CAN stopped when core is halted + DBG_CAN_STOP: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -16044,14 +22714,19 @@ pub const DBGMCU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 APB High Freeze Register + + /// APB High Freeze Register pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - DBG_TIM15_STOP: u1, // bit offset: 2 desc: Debug Timer 15 stopped when Core is halted - DBG_TIM16_STOP: u1, // bit offset: 3 desc: Debug Timer 16 stopped when Core is halted - DBG_TIM17_STO: u1, // bit offset: 4 desc: Debug Timer 17 stopped when Core is halted - DBG_TIM19_STOP: u1, // bit offset: 5 desc: Debug Timer 19 stopped when Core is halted + /// Debug Timer 15 stopped when Core is halted + DBG_TIM15_STOP: u1 = 0, + /// Debug Timer 16 stopped when Core is halted + DBG_TIM16_STOP: u1 = 0, + /// Debug Timer 17 stopped when Core is halted + DBG_TIM17_STO: u1 = 0, + /// Debug Timer 19 stopped when Core is halted + DBG_TIM19_STOP: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, padding24: u1 = 0, @@ -16080,20 +22755,32 @@ pub const DBGMCU = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM1 = extern struct { pub const Address: u32 = 0x40012c00; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16115,27 +22802,43 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16145,17 +22848,27 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -16172,23 +22885,39 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16207,26 +22936,42 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -16242,17 +22987,27 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16277,19 +23032,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16297,7 +23064,8 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16306,14 +23074,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16331,19 +23106,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16351,7 +23138,8 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16360,14 +23148,21 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16385,30 +23180,50 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -16420,9 +23235,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -16438,11 +23255,14 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16460,9 +23280,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16480,9 +23302,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16500,9 +23324,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16520,9 +23346,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16540,9 +23368,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16560,9 +23390,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16580,20 +23412,33 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -16601,13 +23446,16 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -16628,9 +23476,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16648,21 +23498,31 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -16670,7 +23530,8 @@ pub const TIM1 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16679,9 +23540,11 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -16695,13 +23558,18 @@ pub const TIM1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -16719,10 +23587,13 @@ pub const TIM1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + /// TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC1_RMP: u2 = 0, + /// TIM1_ETR_ADC4 remapping capability + TIM1_ETR_ADC4_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -16753,20 +23624,32 @@ pub const TIM1 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced timer pub const TIM20 = extern struct { pub const Address: u32 = 0x40015000; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -16788,27 +23671,43 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -16818,17 +23717,27 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -16845,23 +23754,39 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -16880,26 +23805,42 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -16915,17 +23856,27 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -16950,19 +23901,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -16970,7 +23933,8 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -16979,14 +23943,21 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17004,19 +23975,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17024,7 +24007,8 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17033,14 +24017,21 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17058,30 +24049,50 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -17093,9 +24104,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -17111,11 +24124,14 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17133,9 +24149,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17153,9 +24171,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17173,9 +24193,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17193,9 +24215,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17213,9 +24237,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17233,9 +24259,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17253,20 +24281,33 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17274,13 +24315,16 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17301,9 +24345,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17321,21 +24367,31 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -17343,7 +24399,8 @@ pub const TIM20 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17352,9 +24409,11 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -17368,13 +24427,18 @@ pub const TIM20 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17392,10 +24456,13 @@ pub const TIM20 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM1_ETR_ADC1_RMP: u2, // bit offset: 0 desc: TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC4_RMP: u2, // bit offset: 2 desc: TIM1_ETR_ADC4 remapping capability + /// TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC1_RMP: u2 = 0, + /// TIM1_ETR_ADC4 remapping capability + TIM1_ETR_ADC4_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -17426,20 +24493,32 @@ pub const TIM20 = extern struct { padding1: u1 = 0, }); }; + +/// Advanced-timers pub const TIM8 = extern struct { pub const Address: u32 = 0x40013400; - // byte offset: 0 control register 1 + + /// control register 1 pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - CEN: u1, // bit offset: 0 desc: Counter enable - UDIS: u1, // bit offset: 1 desc: Update disable - URS: u1, // bit offset: 2 desc: Update request source - OPM: u1, // bit offset: 3 desc: One-pulse mode - DIR: u1, // bit offset: 4 desc: Direction - CMS: u2, // bit offset: 5 desc: Center-aligned mode selection - ARPE: u1, // bit offset: 7 desc: Auto-reload preload enable - CKD: u2, // bit offset: 8 desc: Clock division - reserved1: u1 = 0, - UIFREMAP: u1, // bit offset: 11 desc: UIF status bit remapping + /// Counter enable + CEN: u1 = 0, + /// Update disable + UDIS: u1 = 0, + /// Update request source + URS: u1 = 0, + /// One-pulse mode + OPM: u1 = 0, + /// Direction + DIR: u1 = 0, + /// Center-aligned mode selection + CMS: u2 = 0, + /// Auto-reload preload enable + ARPE: u1 = 0, + /// Clock division + CKD: u2 = 0, + reserved1: u1 = 0, + /// UIF status bit remapping + UIFREMAP: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, padding18: u1 = 0, @@ -17461,27 +24540,43 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 control register 2 + + /// control register 2 pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - CCPC: u1, // bit offset: 0 desc: Capture/compare preloaded control - reserved1: u1 = 0, - CCUS: u1, // bit offset: 2 desc: Capture/compare control update selection - CCDS: u1, // bit offset: 3 desc: Capture/compare DMA selection - MMS: u3, // bit offset: 4 desc: Master mode selection - TI1S: u1, // bit offset: 7 desc: TI1 selection - OIS1: u1, // bit offset: 8 desc: Output Idle state 1 - OIS1N: u1, // bit offset: 9 desc: Output Idle state 1 - OIS2: u1, // bit offset: 10 desc: Output Idle state 2 - OIS2N: u1, // bit offset: 11 desc: Output Idle state 2 - OIS3: u1, // bit offset: 12 desc: Output Idle state 3 - OIS3N: u1, // bit offset: 13 desc: Output Idle state 3 - OIS4: u1, // bit offset: 14 desc: Output Idle state 4 - reserved2: u1 = 0, - OIS5: u1, // bit offset: 16 desc: Output Idle state 5 + /// Capture/compare preloaded control + CCPC: u1 = 0, + reserved1: u1 = 0, + /// Capture/compare control update selection + CCUS: u1 = 0, + /// Capture/compare DMA selection + CCDS: u1 = 0, + /// Master mode selection + MMS: u3 = 0, + /// TI1 selection + TI1S: u1 = 0, + /// Output Idle state 1 + OIS1: u1 = 0, + /// Output Idle state 1 + OIS1N: u1 = 0, + /// Output Idle state 2 + OIS2: u1 = 0, + /// Output Idle state 2 + OIS2N: u1 = 0, + /// Output Idle state 3 + OIS3: u1 = 0, + /// Output Idle state 3 + OIS3N: u1 = 0, + /// Output Idle state 4 + OIS4: u1 = 0, + reserved2: u1 = 0, + /// Output Idle state 5 + OIS5: u1 = 0, reserved3: u1 = 0, - OIS6: u1, // bit offset: 18 desc: Output Idle state 6 + /// Output Idle state 6 + OIS6: u1 = 0, reserved4: u1 = 0, - MMS2: u4, // bit offset: 20 desc: Master mode selection 2 + /// Master mode selection 2 + MMS2: u4 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -17491,17 +24586,27 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 slave mode control register + + /// slave mode control register pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - SMS: u3, // bit offset: 0 desc: Slave mode selection - OCCS: u1, // bit offset: 3 desc: OCREF clear selection - TS: u3, // bit offset: 4 desc: Trigger selection - MSM: u1, // bit offset: 7 desc: Master/Slave mode - ETF: u4, // bit offset: 8 desc: External trigger filter - ETPS: u2, // bit offset: 12 desc: External trigger prescaler - ECE: u1, // bit offset: 14 desc: External clock enable - ETP: u1, // bit offset: 15 desc: External trigger polarity - SMS3: u1, // bit offset: 16 desc: Slave mode selection bit 3 + /// Slave mode selection + SMS: u3 = 0, + /// OCREF clear selection + OCCS: u1 = 0, + /// Trigger selection + TS: u3 = 0, + /// Master/Slave mode + MSM: u1 = 0, + /// External trigger filter + ETF: u4 = 0, + /// External trigger prescaler + ETPS: u2 = 0, + /// External clock enable + ECE: u1 = 0, + /// External trigger polarity + ETP: u1 = 0, + /// Slave mode selection bit 3 + SMS3: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -17518,23 +24623,39 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 DMA/Interrupt enable register + + /// DMA/Interrupt enable register pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - UIE: u1, // bit offset: 0 desc: Update interrupt enable - CC1IE: u1, // bit offset: 1 desc: Capture/Compare 1 interrupt enable - CC2IE: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt enable - CC3IE: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt enable - CC4IE: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt enable - COMIE: u1, // bit offset: 5 desc: COM interrupt enable - TIE: u1, // bit offset: 6 desc: Trigger interrupt enable - BIE: u1, // bit offset: 7 desc: Break interrupt enable - UDE: u1, // bit offset: 8 desc: Update DMA request enable - CC1DE: u1, // bit offset: 9 desc: Capture/Compare 1 DMA request enable - CC2DE: u1, // bit offset: 10 desc: Capture/Compare 2 DMA request enable - CC3DE: u1, // bit offset: 11 desc: Capture/Compare 3 DMA request enable - CC4DE: u1, // bit offset: 12 desc: Capture/Compare 4 DMA request enable - COMDE: u1, // bit offset: 13 desc: COM DMA request enable - TDE: u1, // bit offset: 14 desc: Trigger DMA request enable + /// Update interrupt enable + UIE: u1 = 0, + /// Capture/Compare 1 interrupt enable + CC1IE: u1 = 0, + /// Capture/Compare 2 interrupt enable + CC2IE: u1 = 0, + /// Capture/Compare 3 interrupt enable + CC3IE: u1 = 0, + /// Capture/Compare 4 interrupt enable + CC4IE: u1 = 0, + /// COM interrupt enable + COMIE: u1 = 0, + /// Trigger interrupt enable + TIE: u1 = 0, + /// Break interrupt enable + BIE: u1 = 0, + /// Update DMA request enable + UDE: u1 = 0, + /// Capture/Compare 1 DMA request enable + CC1DE: u1 = 0, + /// Capture/Compare 2 DMA request enable + CC2DE: u1 = 0, + /// Capture/Compare 3 DMA request enable + CC3DE: u1 = 0, + /// Capture/Compare 4 DMA request enable + CC4DE: u1 = 0, + /// COM DMA request enable + COMDE: u1 = 0, + /// Trigger DMA request enable + TDE: u1 = 0, padding17: u1 = 0, padding16: u1 = 0, padding15: u1 = 0, @@ -17553,26 +24674,42 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 status register + + /// status register pub const SR = mmio(Address + 0x00000010, 32, packed struct { - UIF: u1, // bit offset: 0 desc: Update interrupt flag - CC1IF: u1, // bit offset: 1 desc: Capture/compare 1 interrupt flag - CC2IF: u1, // bit offset: 2 desc: Capture/Compare 2 interrupt flag - CC3IF: u1, // bit offset: 3 desc: Capture/Compare 3 interrupt flag - CC4IF: u1, // bit offset: 4 desc: Capture/Compare 4 interrupt flag - COMIF: u1, // bit offset: 5 desc: COM interrupt flag - TIF: u1, // bit offset: 6 desc: Trigger interrupt flag - BIF: u1, // bit offset: 7 desc: Break interrupt flag - B2IF: u1, // bit offset: 8 desc: Break 2 interrupt flag - CC1OF: u1, // bit offset: 9 desc: Capture/Compare 1 overcapture flag - CC2OF: u1, // bit offset: 10 desc: Capture/compare 2 overcapture flag - CC3OF: u1, // bit offset: 11 desc: Capture/Compare 3 overcapture flag - CC4OF: u1, // bit offset: 12 desc: Capture/Compare 4 overcapture flag + /// Update interrupt flag + UIF: u1 = 0, + /// Capture/compare 1 interrupt flag + CC1IF: u1 = 0, + /// Capture/Compare 2 interrupt flag + CC2IF: u1 = 0, + /// Capture/Compare 3 interrupt flag + CC3IF: u1 = 0, + /// Capture/Compare 4 interrupt flag + CC4IF: u1 = 0, + /// COM interrupt flag + COMIF: u1 = 0, + /// Trigger interrupt flag + TIF: u1 = 0, + /// Break interrupt flag + BIF: u1 = 0, + /// Break 2 interrupt flag + B2IF: u1 = 0, + /// Capture/Compare 1 overcapture flag + CC1OF: u1 = 0, + /// Capture/compare 2 overcapture flag + CC2OF: u1 = 0, + /// Capture/Compare 3 overcapture flag + CC3OF: u1 = 0, + /// Capture/Compare 4 overcapture flag + CC4OF: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - C5IF: u1, // bit offset: 16 desc: Capture/Compare 5 interrupt flag - C6IF: u1, // bit offset: 17 desc: Capture/Compare 6 interrupt flag + /// Capture/Compare 5 interrupt flag + C5IF: u1 = 0, + /// Capture/Compare 6 interrupt flag + C6IF: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, @@ -17588,17 +24725,27 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 event generation register + + /// event generation register pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - UG: u1, // bit offset: 0 desc: Update generation - CC1G: u1, // bit offset: 1 desc: Capture/compare 1 generation - CC2G: u1, // bit offset: 2 desc: Capture/compare 2 generation - CC3G: u1, // bit offset: 3 desc: Capture/compare 3 generation - CC4G: u1, // bit offset: 4 desc: Capture/compare 4 generation - COMG: u1, // bit offset: 5 desc: Capture/Compare control update generation - TG: u1, // bit offset: 6 desc: Trigger generation - BG: u1, // bit offset: 7 desc: Break generation - B2G: u1, // bit offset: 8 desc: Break 2 generation + /// Update generation + UG: u1 = 0, + /// Capture/compare 1 generation + CC1G: u1 = 0, + /// Capture/compare 2 generation + CC2G: u1 = 0, + /// Capture/compare 3 generation + CC3G: u1 = 0, + /// Capture/compare 4 generation + CC4G: u1 = 0, + /// Capture/Compare control update generation + COMG: u1 = 0, + /// Trigger generation + TG: u1 = 0, + /// Break generation + BG: u1 = 0, + /// Break 2 generation + B2G: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -17623,19 +24770,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - OC1FE: u1, // bit offset: 2 desc: Output Compare 1 fast enable - OC1PE: u1, // bit offset: 3 desc: Output Compare 1 preload enable - OC1M: u3, // bit offset: 4 desc: Output Compare 1 mode - OC1CE: u1, // bit offset: 7 desc: Output Compare 1 clear enable - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - OC2FE: u1, // bit offset: 10 desc: Output Compare 2 fast enable - OC2PE: u1, // bit offset: 11 desc: Output Compare 2 preload enable - OC2M: u3, // bit offset: 12 desc: Output Compare 2 mode - OC2CE: u1, // bit offset: 15 desc: Output Compare 2 clear enable - OC1M_3: u1, // bit offset: 16 desc: Output Compare 1 mode bit 3 + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Output Compare 1 fast enable + OC1FE: u1 = 0, + /// Output Compare 1 preload enable + OC1PE: u1 = 0, + /// Output Compare 1 mode + OC1M: u3 = 0, + /// Output Compare 1 clear enable + OC1CE: u1 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Output Compare 2 fast enable + OC2FE: u1 = 0, + /// Output Compare 2 preload enable + OC2PE: u1 = 0, + /// Output Compare 2 mode + OC2M: u3 = 0, + /// Output Compare 2 clear enable + OC2CE: u1 = 0, + /// Output Compare 1 mode bit 3 + OC1M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17643,7 +24802,8 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC2M_3: u1, // bit offset: 24 desc: Output Compare 2 mode bit 3 + /// Output Compare 2 mode bit 3 + OC2M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17652,14 +24812,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 capture/compare mode register 1 (input mode) + + /// capture/compare mode register 1 (input mode) pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - CC1S: u2, // bit offset: 0 desc: Capture/Compare 1 selection - IC1PCS: u2, // bit offset: 2 desc: Input capture 1 prescaler - IC1F: u4, // bit offset: 4 desc: Input capture 1 filter - CC2S: u2, // bit offset: 8 desc: Capture/Compare 2 selection - IC2PCS: u2, // bit offset: 10 desc: Input capture 2 prescaler - IC2F: u4, // bit offset: 12 desc: Input capture 2 filter + /// Capture/Compare 1 selection + CC1S: u2 = 0, + /// Input capture 1 prescaler + IC1PCS: u2 = 0, + /// Input capture 1 filter + IC1F: u4 = 0, + /// Capture/Compare 2 selection + CC2S: u2 = 0, + /// Input capture 2 prescaler + IC2PCS: u2 = 0, + /// Input capture 2 filter + IC2F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17677,19 +24844,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register (output mode) + + /// capture/compare mode register (output mode) pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/Compare 3 selection - OC3FE: u1, // bit offset: 2 desc: Output compare 3 fast enable - OC3PE: u1, // bit offset: 3 desc: Output compare 3 preload enable - OC3M: u3, // bit offset: 4 desc: Output compare 3 mode - OC3CE: u1, // bit offset: 7 desc: Output compare 3 clear enable - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - OC4FE: u1, // bit offset: 10 desc: Output compare 4 fast enable - OC4PE: u1, // bit offset: 11 desc: Output compare 4 preload enable - OC4M: u3, // bit offset: 12 desc: Output compare 4 mode - OC4CE: u1, // bit offset: 15 desc: Output compare 4 clear enable - OC3M_3: u1, // bit offset: 16 desc: Output Compare 3 mode bit 3 + /// Capture/Compare 3 selection + CC3S: u2 = 0, + /// Output compare 3 fast enable + OC3FE: u1 = 0, + /// Output compare 3 preload enable + OC3PE: u1 = 0, + /// Output compare 3 mode + OC3M: u3 = 0, + /// Output compare 3 clear enable + OC3CE: u1 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Output compare 4 fast enable + OC4FE: u1 = 0, + /// Output compare 4 preload enable + OC4PE: u1 = 0, + /// Output compare 4 mode + OC4M: u3 = 0, + /// Output compare 4 clear enable + OC4CE: u1 = 0, + /// Output Compare 3 mode bit 3 + OC3M_3: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -17697,7 +24876,8 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OC4M_3: u1, // bit offset: 24 desc: Output Compare 4 mode bit 3 + /// Output Compare 4 mode bit 3 + OC4M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -17706,14 +24886,21 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 capture/compare mode register 2 (input mode) + + /// capture/compare mode register 2 (input mode) pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - CC3S: u2, // bit offset: 0 desc: Capture/compare 3 selection - IC3PSC: u2, // bit offset: 2 desc: Input capture 3 prescaler - IC3F: u4, // bit offset: 4 desc: Input capture 3 filter - CC4S: u2, // bit offset: 8 desc: Capture/Compare 4 selection - IC4PSC: u2, // bit offset: 10 desc: Input capture 4 prescaler - IC4F: u4, // bit offset: 12 desc: Input capture 4 filter + /// Capture/compare 3 selection + CC3S: u2 = 0, + /// Input capture 3 prescaler + IC3PSC: u2 = 0, + /// Input capture 3 filter + IC3F: u4 = 0, + /// Capture/Compare 4 selection + CC4S: u2 = 0, + /// Input capture 4 prescaler + IC4PSC: u2 = 0, + /// Input capture 4 filter + IC4F: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17731,30 +24918,50 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 capture/compare enable register + + /// capture/compare enable register pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - CC1E: u1, // bit offset: 0 desc: Capture/Compare 1 output enable - CC1P: u1, // bit offset: 1 desc: Capture/Compare 1 output Polarity - CC1NE: u1, // bit offset: 2 desc: Capture/Compare 1 complementary output enable - CC1NP: u1, // bit offset: 3 desc: Capture/Compare 1 output Polarity - CC2E: u1, // bit offset: 4 desc: Capture/Compare 2 output enable - CC2P: u1, // bit offset: 5 desc: Capture/Compare 2 output Polarity - CC2NE: u1, // bit offset: 6 desc: Capture/Compare 2 complementary output enable - CC2NP: u1, // bit offset: 7 desc: Capture/Compare 2 output Polarity - CC3E: u1, // bit offset: 8 desc: Capture/Compare 3 output enable - CC3P: u1, // bit offset: 9 desc: Capture/Compare 3 output Polarity - CC3NE: u1, // bit offset: 10 desc: Capture/Compare 3 complementary output enable - CC3NP: u1, // bit offset: 11 desc: Capture/Compare 3 output Polarity - CC4E: u1, // bit offset: 12 desc: Capture/Compare 4 output enable - CC4P: u1, // bit offset: 13 desc: Capture/Compare 3 output Polarity - reserved1: u1 = 0, - CC4NP: u1, // bit offset: 15 desc: Capture/Compare 4 output Polarity - CC5E: u1, // bit offset: 16 desc: Capture/Compare 5 output enable - CC5P: u1, // bit offset: 17 desc: Capture/Compare 5 output Polarity + /// Capture/Compare 1 output enable + CC1E: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1P: u1 = 0, + /// Capture/Compare 1 complementary output enable + CC1NE: u1 = 0, + /// Capture/Compare 1 output Polarity + CC1NP: u1 = 0, + /// Capture/Compare 2 output enable + CC2E: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2P: u1 = 0, + /// Capture/Compare 2 complementary output enable + CC2NE: u1 = 0, + /// Capture/Compare 2 output Polarity + CC2NP: u1 = 0, + /// Capture/Compare 3 output enable + CC3E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3P: u1 = 0, + /// Capture/Compare 3 complementary output enable + CC3NE: u1 = 0, + /// Capture/Compare 3 output Polarity + CC3NP: u1 = 0, + /// Capture/Compare 4 output enable + CC4E: u1 = 0, + /// Capture/Compare 3 output Polarity + CC4P: u1 = 0, + reserved1: u1 = 0, + /// Capture/Compare 4 output Polarity + CC4NP: u1 = 0, + /// Capture/Compare 5 output enable + CC5E: u1 = 0, + /// Capture/Compare 5 output Polarity + CC5P: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CC6E: u1, // bit offset: 20 desc: Capture/Compare 6 output enable - CC6P: u1, // bit offset: 21 desc: Capture/Compare 6 output Polarity + /// Capture/Compare 6 output enable + CC6E: u1 = 0, + /// Capture/Compare 6 output Polarity + CC6P: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, padding8: u1 = 0, @@ -17766,9 +24973,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 counter + + /// counter pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - CNT: u16, // bit offset: 0 desc: counter value + /// counter value + CNT: u16 = 0, reserved15: u1 = 0, reserved14: u1 = 0, reserved13: u1 = 0, @@ -17784,11 +24993,14 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - UIFCPY: u1, // bit offset: 31 desc: UIF copy + /// UIF copy + UIFCPY: u1 = 0, }); - // byte offset: 40 prescaler + + /// prescaler pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - PSC: u16, // bit offset: 0 desc: Prescaler value + /// Prescaler value + PSC: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17806,9 +25018,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 auto-reload register + + /// auto-reload register pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - ARR: u16, // bit offset: 0 desc: Auto-reload value + /// Auto-reload value + ARR: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17826,9 +25040,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 repetition counter register + + /// repetition counter register pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - REP: u16, // bit offset: 0 desc: Repetition counter value + /// Repetition counter value + REP: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17846,9 +25062,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 capture/compare register 1 + + /// capture/compare register 1 pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - CCR1: u16, // bit offset: 0 desc: Capture/Compare 1 value + /// Capture/Compare 1 value + CCR1: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17866,9 +25084,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 capture/compare register 2 + + /// capture/compare register 2 pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - CCR2: u16, // bit offset: 0 desc: Capture/Compare 2 value + /// Capture/Compare 2 value + CCR2: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17886,9 +25106,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 capture/compare register 3 + + /// capture/compare register 3 pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - CCR3: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR3: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17906,9 +25128,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 capture/compare register 4 + + /// capture/compare register 4 pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - CCR4: u16, // bit offset: 0 desc: Capture/Compare 3 value + /// Capture/Compare 3 value + CCR4: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17926,20 +25150,33 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 68 break and dead-time register + + /// break and dead-time register pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - DTG: u8, // bit offset: 0 desc: Dead-time generator setup - LOCK: u2, // bit offset: 8 desc: Lock configuration - OSSI: u1, // bit offset: 10 desc: Off-state selection for Idle mode - OSSR: u1, // bit offset: 11 desc: Off-state selection for Run mode - BKE: u1, // bit offset: 12 desc: Break enable - BKP: u1, // bit offset: 13 desc: Break polarity - AOE: u1, // bit offset: 14 desc: Automatic output enable - MOE: u1, // bit offset: 15 desc: Main output enable - BKF: u4, // bit offset: 16 desc: Break filter - BK2F: u4, // bit offset: 20 desc: Break 2 filter - BK2E: u1, // bit offset: 24 desc: Break 2 enable - BK2P: u1, // bit offset: 25 desc: Break 2 polarity + /// Dead-time generator setup + DTG: u8 = 0, + /// Lock configuration + LOCK: u2 = 0, + /// Off-state selection for Idle mode + OSSI: u1 = 0, + /// Off-state selection for Run mode + OSSR: u1 = 0, + /// Break enable + BKE: u1 = 0, + /// Break polarity + BKP: u1 = 0, + /// Automatic output enable + AOE: u1 = 0, + /// Main output enable + MOE: u1 = 0, + /// Break filter + BKF: u4 = 0, + /// Break 2 filter + BK2F: u4 = 0, + /// Break 2 enable + BK2E: u1 = 0, + /// Break 2 polarity + BK2P: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -17947,13 +25184,16 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 72 DMA control register + + /// DMA control register pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - DBA: u5, // bit offset: 0 desc: DMA base address + /// DMA base address + DBA: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DBL: u5, // bit offset: 8 desc: DMA burst length + /// DMA burst length + DBL: u5 = 0, padding19: u1 = 0, padding18: u1 = 0, padding17: u1 = 0, @@ -17974,9 +25214,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 DMA address for full transfer + + /// DMA address for full transfer pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - DMAB: u16, // bit offset: 0 desc: DMA register for burst accesses + /// DMA register for burst accesses + DMAB: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -17994,21 +25236,31 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 84 capture/compare mode register 3 (output mode) + + /// capture/compare mode register 3 (output mode) pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { reserved2: u1 = 0, reserved1: u1 = 0, - OC5FE: u1, // bit offset: 2 desc: Output compare 5 fast enable - OC5PE: u1, // bit offset: 3 desc: Output compare 5 preload enable - OC5M: u3, // bit offset: 4 desc: Output compare 5 mode - OC5CE: u1, // bit offset: 7 desc: Output compare 5 clear enable + /// Output compare 5 fast enable + OC5FE: u1 = 0, + /// Output compare 5 preload enable + OC5PE: u1 = 0, + /// Output compare 5 mode + OC5M: u3 = 0, + /// Output compare 5 clear enable + OC5CE: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - OC6FE: u1, // bit offset: 10 desc: Output compare 6 fast enable - OC6PE: u1, // bit offset: 11 desc: Output compare 6 preload enable - OC6M: u3, // bit offset: 12 desc: Output compare 6 mode - OC6CE: u1, // bit offset: 15 desc: Output compare 6 clear enable - OC5M_3: u1, // bit offset: 16 desc: Outout Compare 5 mode bit 3 + /// Output compare 6 fast enable + OC6FE: u1 = 0, + /// Output compare 6 preload enable + OC6PE: u1 = 0, + /// Output compare 6 mode + OC6M: u3 = 0, + /// Output compare 6 clear enable + OC6CE: u1 = 0, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, reserved9: u1 = 0, @@ -18016,7 +25268,8 @@ pub const TIM8 = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - OC6M_3: u1, // bit offset: 24 desc: Outout Compare 6 mode bit 3 + /// Outout Compare 6 mode bit 3 + OC6M_3: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -18025,9 +25278,11 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 88 capture/compare register 5 + + /// capture/compare register 5 pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - CCR5: u16, // bit offset: 0 desc: Capture/Compare 5 value + /// Capture/Compare 5 value + CCR5: u16 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -18041,13 +25296,18 @@ pub const TIM8 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - GC5C1: u1, // bit offset: 29 desc: Group Channel 5 and Channel 1 - GC5C2: u1, // bit offset: 30 desc: Group Channel 5 and Channel 2 - GC5C3: u1, // bit offset: 31 desc: Group Channel 5 and Channel 3 + /// Group Channel 5 and Channel 1 + GC5C1: u1 = 0, + /// Group Channel 5 and Channel 2 + GC5C2: u1 = 0, + /// Group Channel 5 and Channel 3 + GC5C3: u1 = 0, }); - // byte offset: 92 capture/compare register 6 + + /// capture/compare register 6 pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - CCR6: u16, // bit offset: 0 desc: Capture/Compare 6 value + /// Capture/Compare 6 value + CCR6: u16 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18065,10 +25325,13 @@ pub const TIM8 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 option registers + + /// option registers pub const OR = mmio(Address + 0x00000060, 32, packed struct { - TIM8_ETR_ADC2_RMP: u2, // bit offset: 0 desc: TIM8_ETR_ADC2 remapping capability - TIM8_ETR_ADC3_RMP: u2, // bit offset: 2 desc: TIM8_ETR_ADC3 remapping capability + /// TIM8_ETR_ADC2 remapping capability + TIM8_ETR_ADC2_RMP: u2 = 0, + /// TIM8_ETR_ADC3 remapping capability + TIM8_ETR_ADC3_RMP: u2 = 0, padding28: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, @@ -18099,21 +25362,13 @@ pub const TIM8 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC1 = extern struct { pub const Address: u32 = 0x50000000; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18136,19 +25391,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18171,14 +25416,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -18201,85 +25441,46 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18288,7 +25489,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18298,9 +25498,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18309,7 +25509,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18319,57 +25518,44 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18392,9 +25578,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18412,23 +25598,17 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18443,12 +25623,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18463,12 +25641,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18483,12 +25659,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -18503,12 +25677,10 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18526,9 +25698,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18546,9 +25718,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18566,9 +25738,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18586,10 +25758,10 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18604,10 +25776,10 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18622,11 +25794,14 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -18641,9 +25816,9 @@ pub const ADC1 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -18653,7 +25828,6 @@ pub const ADC1 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -18665,21 +25839,13 @@ pub const ADC1 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC2 = extern struct { pub const Address: u32 = 0x50000100; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18702,19 +25868,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18737,14 +25893,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -18767,85 +25918,46 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18854,7 +25966,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18864,9 +25975,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -18875,7 +25986,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -18885,57 +25995,44 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -18958,9 +26055,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -18978,23 +26075,17 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19009,12 +26100,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19029,12 +26118,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19049,12 +26136,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19069,12 +26154,10 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19092,9 +26175,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19112,9 +26195,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19132,9 +26215,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19152,10 +26235,10 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19170,10 +26253,10 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19188,11 +26271,14 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19207,9 +26293,9 @@ pub const ADC2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -19219,7 +26305,6 @@ pub const ADC2 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -19231,21 +26316,13 @@ pub const ADC2 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC3 = extern struct { pub const Address: u32 = 0x50000400; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19268,19 +26345,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19303,14 +26370,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -19333,85 +26395,46 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19420,7 +26443,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19430,9 +26452,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19441,7 +26463,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19451,57 +26472,44 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19524,9 +26532,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19544,23 +26552,17 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19575,12 +26577,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19595,12 +26595,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19615,12 +26613,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -19635,12 +26631,10 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19658,9 +26652,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19678,9 +26672,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19698,9 +26692,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -19718,10 +26712,10 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19736,10 +26730,10 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19754,11 +26748,14 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -19773,9 +26770,9 @@ pub const ADC3 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -19785,7 +26782,6 @@ pub const ADC3 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -19797,21 +26793,13 @@ pub const ADC3 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC4 = extern struct { pub const Address: u32 = 0x50000500; - // byte offset: 0 interrupt and status register + + /// interrupt and status register pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - ADRDY: u1, // bit offset: 0 desc: ADRDY - EOSMP: u1, // bit offset: 1 desc: EOSMP - EOC: u1, // bit offset: 2 desc: EOC - EOS: u1, // bit offset: 3 desc: EOS - OVR: u1, // bit offset: 4 desc: OVR - JEOC: u1, // bit offset: 5 desc: JEOC - JEOS: u1, // bit offset: 6 desc: JEOS - AWD1: u1, // bit offset: 7 desc: AWD1 - AWD2: u1, // bit offset: 8 desc: AWD2 - AWD3: u1, // bit offset: 9 desc: AWD3 - JQOVF: u1, // bit offset: 10 desc: JQOVF padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19834,19 +26822,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 interrupt enable register + + /// interrupt enable register pub const IER = mmio(Address + 0x00000004, 32, packed struct { - ADRDYIE: u1, // bit offset: 0 desc: ADRDYIE - EOSMPIE: u1, // bit offset: 1 desc: EOSMPIE - EOCIE: u1, // bit offset: 2 desc: EOCIE - EOSIE: u1, // bit offset: 3 desc: EOSIE - OVRIE: u1, // bit offset: 4 desc: OVRIE - JEOCIE: u1, // bit offset: 5 desc: JEOCIE - JEOSIE: u1, // bit offset: 6 desc: JEOSIE - AWD1IE: u1, // bit offset: 7 desc: AWD1IE - AWD2IE: u1, // bit offset: 8 desc: AWD2IE - AWD3IE: u1, // bit offset: 9 desc: AWD3IE - JQOVFIE: u1, // bit offset: 10 desc: JQOVFIE padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -19869,14 +26847,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 control register + + /// control register pub const CR = mmio(Address + 0x00000008, 32, packed struct { - ADEN: u1, // bit offset: 0 desc: ADEN - ADDIS: u1, // bit offset: 1 desc: ADDIS - ADSTART: u1, // bit offset: 2 desc: ADSTART - JADSTART: u1, // bit offset: 3 desc: JADSTART - ADSTP: u1, // bit offset: 4 desc: ADSTP - JADSTP: u1, // bit offset: 5 desc: JADSTP reserved22: u1 = 0, reserved21: u1 = 0, reserved20: u1 = 0, @@ -19899,85 +26872,46 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADVREGEN: u1, // bit offset: 28 desc: ADVREGEN - DEEPPWD: u1, // bit offset: 29 desc: DEEPPWD - ADCALDIF: u1, // bit offset: 30 desc: ADCALDIF - ADCAL: u1, // bit offset: 31 desc: ADCAL }); - // byte offset: 12 configuration register + + /// configuration register pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - DMAEN: u1, // bit offset: 0 desc: DMAEN - DMACFG: u1, // bit offset: 1 desc: DMACFG - reserved1: u1 = 0, - RES: u2, // bit offset: 3 desc: RES - ALIGN: u1, // bit offset: 5 desc: ALIGN - EXTSEL: u4, // bit offset: 6 desc: EXTSEL - EXTEN: u2, // bit offset: 10 desc: EXTEN - OVRMOD: u1, // bit offset: 12 desc: OVRMOD - CONT: u1, // bit offset: 13 desc: CONT - AUTDLY: u1, // bit offset: 14 desc: AUTDLY - AUTOFF: u1, // bit offset: 15 desc: AUTOFF - DISCEN: u1, // bit offset: 16 desc: DISCEN - DISCNUM: u3, // bit offset: 17 desc: DISCNUM - JDISCEN: u1, // bit offset: 20 desc: JDISCEN - JQM: u1, // bit offset: 21 desc: JQM - AWD1SGL: u1, // bit offset: 22 desc: AWD1SGL - AWD1EN: u1, // bit offset: 23 desc: AWD1EN - JAWD1EN: u1, // bit offset: 24 desc: JAWD1EN - JAUTO: u1, // bit offset: 25 desc: JAUTO - AWDCH1CH: u5, // bit offset: 26 desc: AWDCH1CH - padding1: u1 = 0, - }); - // byte offset: 20 sample time register 1 + reserved1: u1 = 0, + padding1: u1 = 0, + }); + + /// sample time register 1 pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SMP1: u3, // bit offset: 3 desc: SMP1 - SMP2: u3, // bit offset: 6 desc: SMP2 - SMP3: u3, // bit offset: 9 desc: SMP3 - SMP4: u3, // bit offset: 12 desc: SMP4 - SMP5: u3, // bit offset: 15 desc: SMP5 - SMP6: u3, // bit offset: 18 desc: SMP6 - SMP7: u3, // bit offset: 21 desc: SMP7 - SMP8: u3, // bit offset: 24 desc: SMP8 - SMP9: u3, // bit offset: 27 desc: SMP9 padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 sample time register 2 + + /// sample time register 2 pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - SMP10: u3, // bit offset: 0 desc: SMP10 - SMP11: u3, // bit offset: 3 desc: SMP11 - SMP12: u3, // bit offset: 6 desc: SMP12 - SMP13: u3, // bit offset: 9 desc: SMP13 - SMP14: u3, // bit offset: 12 desc: SMP14 - SMP15: u3, // bit offset: 15 desc: SMP15 - SMP16: u3, // bit offset: 18 desc: SMP16 - SMP17: u3, // bit offset: 21 desc: SMP17 - SMP18: u3, // bit offset: 24 desc: SMP18 padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 32 watchdog threshold register 1 + + /// watchdog threshold register 1 pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - LT1: u12, // bit offset: 0 desc: LT1 reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT1: u12, // bit offset: 16 desc: HT1 padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 36 watchdog threshold register + + /// watchdog threshold register pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - LT2: u8, // bit offset: 0 desc: LT2 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -19986,7 +26920,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT2: u8, // bit offset: 16 desc: HT2 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -19996,9 +26929,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 watchdog threshold register 3 + + /// watchdog threshold register 3 pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - LT3: u8, // bit offset: 0 desc: LT3 reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, @@ -20007,7 +26940,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - HT3: u8, // bit offset: 16 desc: HT3 padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -20017,57 +26949,44 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 48 regular sequence register 1 + + /// regular sequence register 1 pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - L3: u4, // bit offset: 0 desc: L3 reserved2: u1 = 0, reserved1: u1 = 0, - SQ1: u5, // bit offset: 6 desc: SQ1 reserved3: u1 = 0, - SQ2: u5, // bit offset: 12 desc: SQ2 reserved4: u1 = 0, - SQ3: u5, // bit offset: 18 desc: SQ3 reserved5: u1 = 0, - SQ4: u5, // bit offset: 24 desc: SQ4 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 52 regular sequence register 2 + + /// regular sequence register 2 pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - SQ5: u5, // bit offset: 0 desc: SQ5 reserved1: u1 = 0, - SQ6: u5, // bit offset: 6 desc: SQ6 reserved2: u1 = 0, - SQ7: u5, // bit offset: 12 desc: SQ7 reserved3: u1 = 0, - SQ8: u5, // bit offset: 18 desc: SQ8 reserved4: u1 = 0, - SQ9: u5, // bit offset: 24 desc: SQ9 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 56 regular sequence register 3 + + /// regular sequence register 3 pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - SQ10: u5, // bit offset: 0 desc: SQ10 reserved1: u1 = 0, - SQ11: u5, // bit offset: 6 desc: SQ11 reserved2: u1 = 0, - SQ12: u5, // bit offset: 12 desc: SQ12 reserved3: u1 = 0, - SQ13: u5, // bit offset: 18 desc: SQ13 reserved4: u1 = 0, - SQ14: u5, // bit offset: 24 desc: SQ14 padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 60 regular sequence register 4 + + /// regular sequence register 4 pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - SQ15: u5, // bit offset: 0 desc: SQ15 reserved1: u1 = 0, - SQ16: u5, // bit offset: 6 desc: SQ16 padding21: u1 = 0, padding20: u1 = 0, padding19: u1 = 0, @@ -20090,9 +27009,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 64 regular Data Register + + /// regular Data Register pub const DR = mmio(Address + 0x00000040, 32, packed struct { - regularDATA: u16, // bit offset: 0 desc: regularDATA padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20110,23 +27029,17 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 76 injected sequence register + + /// injected sequence register pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - JL: u2, // bit offset: 0 desc: JL - JEXTSEL: u4, // bit offset: 2 desc: JEXTSEL - JEXTEN: u2, // bit offset: 6 desc: JEXTEN - JSQ1: u5, // bit offset: 8 desc: JSQ1 reserved1: u1 = 0, - JSQ2: u5, // bit offset: 14 desc: JSQ2 reserved2: u1 = 0, - JSQ3: u5, // bit offset: 20 desc: JSQ3 reserved3: u1 = 0, - JSQ4: u5, // bit offset: 26 desc: JSQ4 padding1: u1 = 0, }); - // byte offset: 96 offset register 1 + + /// offset register 1 pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - OFFSET1: u12, // bit offset: 0 desc: OFFSET1 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20141,12 +27054,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET1_CH: u5, // bit offset: 26 desc: OFFSET1_CH - OFFSET1_EN: u1, // bit offset: 31 desc: OFFSET1_EN }); - // byte offset: 100 offset register 2 + + /// offset register 2 pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - OFFSET2: u12, // bit offset: 0 desc: OFFSET2 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20161,12 +27072,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET2_CH: u5, // bit offset: 26 desc: OFFSET2_CH - OFFSET2_EN: u1, // bit offset: 31 desc: OFFSET2_EN }); - // byte offset: 104 offset register 3 + + /// offset register 3 pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - OFFSET3: u12, // bit offset: 0 desc: OFFSET3 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20181,12 +27090,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET3_CH: u5, // bit offset: 26 desc: OFFSET3_CH - OFFSET3_EN: u1, // bit offset: 31 desc: OFFSET3_EN }); - // byte offset: 108 offset register 4 + + /// offset register 4 pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - OFFSET4: u12, // bit offset: 0 desc: OFFSET4 reserved14: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, @@ -20201,12 +27108,10 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - OFFSET4_CH: u5, // bit offset: 26 desc: OFFSET4_CH - OFFSET4_EN: u1, // bit offset: 31 desc: OFFSET4_EN }); - // byte offset: 128 injected data register 1 + + /// injected data register 1 pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - JDATA1: u16, // bit offset: 0 desc: JDATA1 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20224,9 +27129,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 injected data register 2 + + /// injected data register 2 pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - JDATA2: u16, // bit offset: 0 desc: JDATA2 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20244,9 +27149,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 injected data register 3 + + /// injected data register 3 pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - JDATA3: u16, // bit offset: 0 desc: JDATA3 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20264,9 +27169,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 140 injected data register 4 + + /// injected data register 4 pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - JDATA4: u16, // bit offset: 0 desc: JDATA4 padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20284,10 +27189,10 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 160 Analog Watchdog 2 Configuration Register + + /// Analog Watchdog 2 Configuration Register pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - AWD2CH: u18, // bit offset: 1 desc: AWD2CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20302,10 +27207,10 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 Analog Watchdog 3 Configuration Register + + /// Analog Watchdog 3 Configuration Register pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { reserved1: u1 = 0, - AWD3CH: u18, // bit offset: 1 desc: AWD3CH padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20320,11 +27225,14 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 176 Differential Mode Selection Register 2 + + /// Differential Mode Selection Register 2 pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { reserved1: u1 = 0, - DIFSEL_1_15: u15, // bit offset: 1 desc: Differential mode for channels 15 to 1 - DIFSEL_16_18: u3, // bit offset: 16 desc: Differential mode for channels 18 to 16 + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15 = 0, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -20339,9 +27247,9 @@ pub const ADC4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 180 Calibration Factors + + /// Calibration Factors pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - CALFACT_S: u7, // bit offset: 0 desc: CALFACT_S reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, @@ -20351,7 +27259,6 @@ pub const ADC4 = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CALFACT_D: u7, // bit offset: 16 desc: CALFACT_D padding9: u1 = 0, padding8: u1 = 0, padding7: u1 = 0, @@ -20363,61 +27270,69 @@ pub const ADC4 = extern struct { padding1: u1 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC1_2 = extern struct { pub const Address: u32 = 0x50000300; - // byte offset: 0 ADC Common status register + + /// ADC Common status register pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + /// End of regular conversion of the slave ADC + EOC_SLV: u1 = 0, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1 = 0, + /// Overrun flag of the slave ADC + OVR_SLV: u1 = 0, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1 = 0, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1 = 0, + /// Analog watchdog 1 flag of the slave ADC + AWD1_SLV: u1 = 0, + /// Analog watchdog 2 flag of the slave ADC + AWD2_SLV: u1 = 0, + /// Analog watchdog 3 flag of the slave ADC + AWD3_SLV: u1 = 0, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 ADC common control register + + /// ADC common control register pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + /// Multi ADC mode selection + MULT: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + /// Delay between 2 sampling phases + DELAY: u4 = 0, reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode + /// DMA configuration (for multi-ADC mode) + DMACFG: u1 = 0, + /// Direct memory access mode for multi ADC mode + MDMA: u2 = 0, + /// ADC clock mode + CKMODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable + /// VREFINT enable + VREFEN: u1 = 0, + /// Temperature sensor enable + TSEN: u1 = 0, + /// VBAT enable + VBATEN: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -20426,67 +27341,78 @@ pub const ADC1_2 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 ADC common regular data register for dual and triple modes + + /// ADC common regular data register for dual and triple modes pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + /// Regular data of the master ADC + RDATA_MST: u16 = 0, + /// Regular data of the slave ADC + RDATA_SLV: u16 = 0, }); }; + +/// Analog-to-Digital Converter pub const ADC3_4 = extern struct { pub const Address: u32 = 0x50000700; - // byte offset: 0 ADC Common status register + + /// ADC Common status register pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - ADDRDY_MST: u1, // bit offset: 0 desc: ADDRDY_MST - EOSMP_MST: u1, // bit offset: 1 desc: EOSMP_MST - EOC_MST: u1, // bit offset: 2 desc: EOC_MST - EOS_MST: u1, // bit offset: 3 desc: EOS_MST - OVR_MST: u1, // bit offset: 4 desc: OVR_MST - JEOC_MST: u1, // bit offset: 5 desc: JEOC_MST - JEOS_MST: u1, // bit offset: 6 desc: JEOS_MST - AWD1_MST: u1, // bit offset: 7 desc: AWD1_MST - AWD2_MST: u1, // bit offset: 8 desc: AWD2_MST - AWD3_MST: u1, // bit offset: 9 desc: AWD3_MST - JQOVF_MST: u1, // bit offset: 10 desc: JQOVF_MST reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADRDY_SLV: u1, // bit offset: 16 desc: ADRDY_SLV - EOSMP_SLV: u1, // bit offset: 17 desc: EOSMP_SLV - EOC_SLV: u1, // bit offset: 18 desc: End of regular conversion of the slave ADC - EOS_SLV: u1, // bit offset: 19 desc: End of regular sequence flag of the slave ADC - OVR_SLV: u1, // bit offset: 20 desc: Overrun flag of the slave ADC - JEOC_SLV: u1, // bit offset: 21 desc: End of injected conversion flag of the slave ADC - JEOS_SLV: u1, // bit offset: 22 desc: End of injected sequence flag of the slave ADC - AWD1_SLV: u1, // bit offset: 23 desc: Analog watchdog 1 flag of the slave ADC - AWD2_SLV: u1, // bit offset: 24 desc: Analog watchdog 2 flag of the slave ADC - AWD3_SLV: u1, // bit offset: 25 desc: Analog watchdog 3 flag of the slave ADC - JQOVF_SLV: u1, // bit offset: 26 desc: Injected Context Queue Overflow flag of the slave ADC + /// End of regular conversion of the slave ADC + EOC_SLV: u1 = 0, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1 = 0, + /// Overrun flag of the slave ADC + OVR_SLV: u1 = 0, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1 = 0, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1 = 0, + /// Analog watchdog 1 flag of the slave ADC + AWD1_SLV: u1 = 0, + /// Analog watchdog 2 flag of the slave ADC + AWD2_SLV: u1 = 0, + /// Analog watchdog 3 flag of the slave ADC + AWD3_SLV: u1 = 0, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 ADC common control register + + /// ADC common control register pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - MULT: u5, // bit offset: 0 desc: Multi ADC mode selection + /// Multi ADC mode selection + MULT: u5 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DELAY: u4, // bit offset: 8 desc: Delay between 2 sampling phases + /// Delay between 2 sampling phases + DELAY: u4 = 0, reserved4: u1 = 0, - DMACFG: u1, // bit offset: 13 desc: DMA configuration (for multi-ADC mode) - MDMA: u2, // bit offset: 14 desc: Direct memory access mode for multi ADC mode - CKMODE: u2, // bit offset: 16 desc: ADC clock mode + /// DMA configuration (for multi-ADC mode) + DMACFG: u1 = 0, + /// Direct memory access mode for multi ADC mode + MDMA: u2 = 0, + /// ADC clock mode + CKMODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - VREFEN: u1, // bit offset: 22 desc: VREFINT enable - TSEN: u1, // bit offset: 23 desc: Temperature sensor enable - VBATEN: u1, // bit offset: 24 desc: VBAT enable + /// VREFINT enable + VREFEN: u1 = 0, + /// Temperature sensor enable + TSEN: u1 = 0, + /// VBAT enable + VBATEN: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, @@ -20495,52 +27421,84 @@ pub const ADC3_4 = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 ADC common regular data register for dual and triple modes + + /// ADC common regular data register for dual and triple modes pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - RDATA_MST: u16, // bit offset: 0 desc: Regular data of the master ADC - RDATA_SLV: u16, // bit offset: 16 desc: Regular data of the slave ADC + /// Regular data of the master ADC + RDATA_MST: u16 = 0, + /// Regular data of the slave ADC + RDATA_SLV: u16 = 0, }); }; + +/// System configuration controller _Comparator and Operational amplifier pub const SYSCFG_COMP_OPAMP = extern struct { pub const Address: u32 = 0x40010000; - // byte offset: 0 configuration register 1 + + /// configuration register 1 pub const SYSCFG_CFGR1 = mmio(Address + 0x00000000, 32, packed struct { - MEM_MODE: u2, // bit offset: 0 desc: Memory mapping selection bits + /// Memory mapping selection bits + MEM_MODE: u2 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - USB_IT_RMP: u1, // bit offset: 5 desc: USB interrupt remap - TIM1_ITR_RMP: u1, // bit offset: 6 desc: Timer 1 ITR3 selection - DAC_TRIG_RMP: u1, // bit offset: 7 desc: DAC trigger remap (when TSEL = 001) - ADC24_DMA_RMP: u1, // bit offset: 8 desc: ADC24 DMA remapping bit + /// USB interrupt remap + USB_IT_RMP: u1 = 0, + /// Timer 1 ITR3 selection + TIM1_ITR_RMP: u1 = 0, + /// DAC trigger remap (when TSEL = 001) + DAC_TRIG_RMP: u1 = 0, + /// ADC24 DMA remapping bit + ADC24_DMA_RMP: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - TIM16_DMA_RMP: u1, // bit offset: 11 desc: TIM16 DMA request remapping bit - TIM17_DMA_RMP: u1, // bit offset: 12 desc: TIM17 DMA request remapping bit - TIM6_DAC1_DMA_RMP: u1, // bit offset: 13 desc: TIM6 and DAC1 DMA request remapping bit - TIM7_DAC2_DMA_RMP: u1, // bit offset: 14 desc: TIM7 and DAC2 DMA request remapping bit + /// TIM16 DMA request remapping bit + TIM16_DMA_RMP: u1 = 0, + /// TIM17 DMA request remapping bit + TIM17_DMA_RMP: u1 = 0, + /// TIM6 and DAC1 DMA request remapping bit + TIM6_DAC1_DMA_RMP: u1 = 0, + /// TIM7 and DAC2 DMA request remapping bit + TIM7_DAC2_DMA_RMP: u1 = 0, reserved6: u1 = 0, - I2C_PB6_FM: u1, // bit offset: 16 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB7_FM: u1, // bit offset: 17 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB8_FM: u1, // bit offset: 18 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB9_FM: u1, // bit offset: 19 desc: Fast Mode Plus (FM+) driving capability activation bits. - I2C1_FM: u1, // bit offset: 20 desc: I2C1 Fast Mode Plus - I2C2_FM: u1, // bit offset: 21 desc: I2C2 Fast Mode Plus - ENCODER_MODE: u2, // bit offset: 22 desc: Encoder mode + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB6_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB7_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB8_FM: u1 = 0, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB9_FM: u1 = 0, + /// I2C1 Fast Mode Plus + I2C1_FM: u1 = 0, + /// I2C2 Fast Mode Plus + I2C2_FM: u1 = 0, + /// Encoder mode + ENCODER_MODE: u2 = 0, reserved8: u1 = 0, reserved7: u1 = 0, - FPU_IT: u6, // bit offset: 26 desc: Interrupt enable bits from FPU + /// Interrupt enable bits from FPU + FPU_IT: u6 = 0, }); - // byte offset: 4 CCM SRAM protection register + + /// CCM SRAM protection register pub const SYSCFG_RCR = mmio(Address + 0x00000004, 32, packed struct { - PAGE0_WP: u1, // bit offset: 0 desc: CCM SRAM page write protection bit - PAGE1_WP: u1, // bit offset: 1 desc: CCM SRAM page write protection bit - PAGE2_WP: u1, // bit offset: 2 desc: CCM SRAM page write protection bit - PAGE3_WP: u1, // bit offset: 3 desc: CCM SRAM page write protection bit - PAGE4_WP: u1, // bit offset: 4 desc: CCM SRAM page write protection bit - PAGE5_WP: u1, // bit offset: 5 desc: CCM SRAM page write protection bit - PAGE6_WP: u1, // bit offset: 6 desc: CCM SRAM page write protection bit - PAGE7_WP: u1, // bit offset: 7 desc: CCM SRAM page write protection bit + /// CCM SRAM page write protection bit + PAGE0_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE1_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE2_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE3_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE4_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE5_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE6_WP: u1 = 0, + /// CCM SRAM page write protection bit + PAGE7_WP: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -20566,12 +27524,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 external interrupt configuration register 1 + + /// external interrupt configuration register 1 pub const SYSCFG_EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - EXTI0: u4, // bit offset: 0 desc: EXTI 0 configuration bits - EXTI1: u4, // bit offset: 4 desc: EXTI 1 configuration bits - EXTI2: u4, // bit offset: 8 desc: EXTI 2 configuration bits - EXTI3: u4, // bit offset: 12 desc: EXTI 3 configuration bits + /// EXTI 0 configuration bits + EXTI0: u4 = 0, + /// EXTI 1 configuration bits + EXTI1: u4 = 0, + /// EXTI 2 configuration bits + EXTI2: u4 = 0, + /// EXTI 3 configuration bits + EXTI3: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20589,12 +27552,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 external interrupt configuration register 2 + + /// external interrupt configuration register 2 pub const SYSCFG_EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - EXTI4: u4, // bit offset: 0 desc: EXTI 4 configuration bits - EXTI5: u4, // bit offset: 4 desc: EXTI 5 configuration bits - EXTI6: u4, // bit offset: 8 desc: EXTI 6 configuration bits - EXTI7: u4, // bit offset: 12 desc: EXTI 7 configuration bits + /// EXTI 4 configuration bits + EXTI4: u4 = 0, + /// EXTI 5 configuration bits + EXTI5: u4 = 0, + /// EXTI 6 configuration bits + EXTI6: u4 = 0, + /// EXTI 7 configuration bits + EXTI7: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20612,12 +27580,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 external interrupt configuration register 3 + + /// external interrupt configuration register 3 pub const SYSCFG_EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - EXTI8: u4, // bit offset: 0 desc: EXTI 8 configuration bits - EXTI9: u4, // bit offset: 4 desc: EXTI 9 configuration bits - EXTI10: u4, // bit offset: 8 desc: EXTI 10 configuration bits - EXTI11: u4, // bit offset: 12 desc: EXTI 11 configuration bits + /// EXTI 8 configuration bits + EXTI8: u4 = 0, + /// EXTI 9 configuration bits + EXTI9: u4 = 0, + /// EXTI 10 configuration bits + EXTI10: u4 = 0, + /// EXTI 11 configuration bits + EXTI11: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20635,12 +27608,17 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 external interrupt configuration register 4 + + /// external interrupt configuration register 4 pub const SYSCFG_EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - EXTI12: u4, // bit offset: 0 desc: EXTI 12 configuration bits - EXTI13: u4, // bit offset: 4 desc: EXTI 13 configuration bits - EXTI14: u4, // bit offset: 8 desc: EXTI 14 configuration bits - EXTI15: u4, // bit offset: 12 desc: EXTI 15 configuration bits + /// EXTI 12 configuration bits + EXTI12: u4 = 0, + /// EXTI 13 configuration bits + EXTI13: u4 = 0, + /// EXTI 14 configuration bits + EXTI14: u4 = 0, + /// EXTI 15 configuration bits + EXTI15: u4 = 0, padding16: u1 = 0, padding15: u1 = 0, padding14: u1 = 0, @@ -20658,17 +27636,23 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 configuration register 2 + + /// configuration register 2 pub const SYSCFG_CFGR2 = mmio(Address + 0x00000018, 32, packed struct { - LOCUP_LOCK: u1, // bit offset: 0 desc: Cortex-M0 LOCKUP bit enable bit - SRAM_PARITY_LOCK: u1, // bit offset: 1 desc: SRAM parity lock bit - PVD_LOCK: u1, // bit offset: 2 desc: PVD lock enable bit - reserved1: u1 = 0, - BYP_ADD_PAR: u1, // bit offset: 4 desc: Bypass address bit 29 in parity calculation + /// Cortex-M0 LOCKUP bit enable bit + LOCUP_LOCK: u1 = 0, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1 = 0, + /// PVD lock enable bit + PVD_LOCK: u1 = 0, + reserved1: u1 = 0, + /// Bypass address bit 29 in parity calculation + BYP_ADD_PAR: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SRAM_PEF: u1, // bit offset: 8 desc: SRAM parity flag + /// SRAM parity flag + SRAM_PEF: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -20693,20 +27677,27 @@ pub const SYSCFG_COMP_OPAMP = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 control and status register + + /// control and status register pub const COMP1_CSR = mmio(Address + 0x0000001c, 32, packed struct { - COMP1EN: u1, // bit offset: 0 desc: Comparator 1 enable - COMP1_INP_DAC: u1, // bit offset: 1 desc: COMP1_INP_DAC - COMP1MODE: u2, // bit offset: 2 desc: Comparator 1 mode - COMP1INSEL: u3, // bit offset: 4 desc: Comparator 1 inverting input selection + /// Comparator 1 enable + COMP1EN: u1 = 0, + /// Comparator 1 mode + COMP1MODE: u2 = 0, + /// Comparator 1 inverting input selection + COMP1INSEL: u3 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COMP1_OUT_SEL: u4, // bit offset: 10 desc: Comparator 1 output selection + /// Comparator 1 output selection + COMP1_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP1POL: u1, // bit offset: 15 desc: Comparator 1 output polarity - COMP1HYST: u2, // bit offset: 16 desc: Comparator 1 hysteresis - COMP1_BLANKING: u3, // bit offset: 18 desc: Comparator 1 blanking source + /// Comparator 1 output polarity + COMP1POL: u1 = 0, + /// Comparator 1 hysteresis + COMP1HYST: u2 = 0, + /// Comparator 1 blanking source + COMP1_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20716,23 +27707,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP1OUT: u1, // bit offset: 30 desc: Comparator 1 output - COMP1LOCK: u1, // bit offset: 31 desc: Comparator 1 lock + /// Comparator 1 output + COMP1OUT: u1 = 0, + /// Comparator 1 lock + COMP1LOCK: u1 = 0, }); - // byte offset: 32 control and status register + + /// control and status register pub const COMP2_CSR = mmio(Address + 0x00000020, 32, packed struct { - COMP2EN: u1, // bit offset: 0 desc: Comparator 2 enable - reserved1: u1 = 0, - COMP2MODE: u2, // bit offset: 2 desc: Comparator 2 mode - COMP2INSEL: u3, // bit offset: 4 desc: Comparator 2 inverting input selection - COMP2INPSEL: u1, // bit offset: 7 desc: Comparator 2 non inverted input selection - reserved2: u1 = 0, - COMP2INMSEL: u1, // bit offset: 9 desc: Comparator 1inverting input selection - COMP2_OUT_SEL: u4, // bit offset: 10 desc: Comparator 2 output selection + /// Comparator 2 enable + COMP2EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 2 mode + COMP2MODE: u2 = 0, + /// Comparator 2 inverting input selection + COMP2INSEL: u3 = 0, + /// Comparator 2 non inverted input selection + COMP2INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 1inverting input selection + COMP2INMSEL: u1 = 0, + /// Comparator 2 output selection + COMP2_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP2POL: u1, // bit offset: 15 desc: Comparator 2 output polarity - COMP2HYST: u2, // bit offset: 16 desc: Comparator 2 hysteresis - COMP2_BLANKING: u3, // bit offset: 18 desc: Comparator 2 blanking source + /// Comparator 2 output polarity + COMP2POL: u1 = 0, + /// Comparator 2 hysteresis + COMP2HYST: u2 = 0, + /// Comparator 2 blanking source + COMP2_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20743,22 +27746,32 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP2LOCK: u1, // bit offset: 31 desc: Comparator 2 lock + /// Comparator 2 lock + COMP2LOCK: u1 = 0, }); - // byte offset: 36 control and status register + + /// control and status register pub const COMP3_CSR = mmio(Address + 0x00000024, 32, packed struct { - COMP3EN: u1, // bit offset: 0 desc: Comparator 3 enable - reserved1: u1 = 0, - COMP3MODE: u2, // bit offset: 2 desc: Comparator 3 mode - COMP3INSEL: u3, // bit offset: 4 desc: Comparator 3 inverting input selection - COMP3INPSEL: u1, // bit offset: 7 desc: Comparator 3 non inverted input selection + /// Comparator 3 enable + COMP3EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 3 mode + COMP3MODE: u2 = 0, + /// Comparator 3 inverting input selection + COMP3INSEL: u3 = 0, + /// Comparator 3 non inverted input selection + COMP3INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP3_OUT_SEL: u4, // bit offset: 10 desc: Comparator 3 output selection + /// Comparator 3 output selection + COMP3_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP3POL: u1, // bit offset: 15 desc: Comparator 3 output polarity - COMP3HYST: u2, // bit offset: 16 desc: Comparator 3 hysteresis - COMP3_BLANKING: u3, // bit offset: 18 desc: Comparator 3 blanking source + /// Comparator 3 output polarity + COMP3POL: u1 = 0, + /// Comparator 3 hysteresis + COMP3HYST: u2 = 0, + /// Comparator 3 blanking source + COMP3_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20768,23 +27781,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP3OUT: u1, // bit offset: 30 desc: Comparator 3 output - COMP3LOCK: u1, // bit offset: 31 desc: Comparator 3 lock + /// Comparator 3 output + COMP3OUT: u1 = 0, + /// Comparator 3 lock + COMP3LOCK: u1 = 0, }); - // byte offset: 40 control and status register + + /// control and status register pub const COMP4_CSR = mmio(Address + 0x00000028, 32, packed struct { - COMP4EN: u1, // bit offset: 0 desc: Comparator 4 enable - reserved1: u1 = 0, - COMP4MODE: u2, // bit offset: 2 desc: Comparator 4 mode - COMP4INSEL: u3, // bit offset: 4 desc: Comparator 4 inverting input selection - COMP4INPSEL: u1, // bit offset: 7 desc: Comparator 4 non inverted input selection - reserved2: u1 = 0, - COM4WINMODE: u1, // bit offset: 9 desc: Comparator 4 window mode - COMP4_OUT_SEL: u4, // bit offset: 10 desc: Comparator 4 output selection + /// Comparator 4 enable + COMP4EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 4 mode + COMP4MODE: u2 = 0, + /// Comparator 4 inverting input selection + COMP4INSEL: u3 = 0, + /// Comparator 4 non inverted input selection + COMP4INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 4 window mode + COM4WINMODE: u1 = 0, + /// Comparator 4 output selection + COMP4_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP4POL: u1, // bit offset: 15 desc: Comparator 4 output polarity - COMP4HYST: u2, // bit offset: 16 desc: Comparator 4 hysteresis - COMP4_BLANKING: u3, // bit offset: 18 desc: Comparator 4 blanking source + /// Comparator 4 output polarity + COMP4POL: u1 = 0, + /// Comparator 4 hysteresis + COMP4HYST: u2 = 0, + /// Comparator 4 blanking source + COMP4_BLANKING: u3 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, @@ -20794,23 +27819,34 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP4OUT: u1, // bit offset: 30 desc: Comparator 4 output - COMP4LOCK: u1, // bit offset: 31 desc: Comparator 4 lock + /// Comparator 4 output + COMP4OUT: u1 = 0, + /// Comparator 4 lock + COMP4LOCK: u1 = 0, }); - // byte offset: 44 control and status register + + /// control and status register pub const COMP5_CSR = mmio(Address + 0x0000002c, 32, packed struct { - COMP5EN: u1, // bit offset: 0 desc: Comparator 5 enable - reserved1: u1 = 0, - COMP5MODE: u2, // bit offset: 2 desc: Comparator 5 mode - COMP5INSEL: u3, // bit offset: 4 desc: Comparator 5 inverting input selection - COMP5INPSEL: u1, // bit offset: 7 desc: Comparator 5 non inverted input selection + /// Comparator 5 enable + COMP5EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 5 mode + COMP5MODE: u2 = 0, + /// Comparator 5 inverting input selection + COMP5INSEL: u3 = 0, + /// Comparator 5 non inverted input selection + COMP5INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP5_OUT_SEL: u4, // bit offset: 10 desc: Comparator 5 output selection + /// Comparator 5 output selection + COMP5_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP5POL: u1, // bit offset: 15 desc: Comparator 5 output polarity - COMP5HYST: u2, // bit offset: 16 desc: Comparator 5 hysteresis - COMP5_BLANKING: u3, // bit offset: 18 desc: Comparator 5 blanking source + /// Comparator 5 output polarity + COMP5POL: u1 = 0, + /// Comparator 5 hysteresis + COMP5HYST: u2 = 0, + /// Comparator 5 blanking source + COMP5_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20820,23 +27856,35 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP5OUT: u1, // bit offset: 30 desc: Comparator51 output - COMP5LOCK: u1, // bit offset: 31 desc: Comparator 5 lock + /// Comparator51 output + COMP5OUT: u1 = 0, + /// Comparator 5 lock + COMP5LOCK: u1 = 0, }); - // byte offset: 48 control and status register + + /// control and status register pub const COMP6_CSR = mmio(Address + 0x00000030, 32, packed struct { - COMP6EN: u1, // bit offset: 0 desc: Comparator 6 enable - reserved1: u1 = 0, - COMP6MODE: u2, // bit offset: 2 desc: Comparator 6 mode - COMP6INSEL: u3, // bit offset: 4 desc: Comparator 6 inverting input selection - COMP6INPSEL: u1, // bit offset: 7 desc: Comparator 6 non inverted input selection - reserved2: u1 = 0, - COM6WINMODE: u1, // bit offset: 9 desc: Comparator 6 window mode - COMP6_OUT_SEL: u4, // bit offset: 10 desc: Comparator 6 output selection + /// Comparator 6 enable + COMP6EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 6 mode + COMP6MODE: u2 = 0, + /// Comparator 6 inverting input selection + COMP6INSEL: u3 = 0, + /// Comparator 6 non inverted input selection + COMP6INPSEL: u1 = 0, + reserved2: u1 = 0, + /// Comparator 6 window mode + COM6WINMODE: u1 = 0, + /// Comparator 6 output selection + COMP6_OUT_SEL: u4 = 0, reserved3: u1 = 0, - COMP6POL: u1, // bit offset: 15 desc: Comparator 6 output polarity - COMP6HYST: u2, // bit offset: 16 desc: Comparator 6 hysteresis - COMP6_BLANKING: u3, // bit offset: 18 desc: Comparator 6 blanking source + /// Comparator 6 output polarity + COMP6POL: u1 = 0, + /// Comparator 6 hysteresis + COMP6HYST: u2 = 0, + /// Comparator 6 blanking source + COMP6_BLANKING: u3 = 0, reserved12: u1 = 0, reserved11: u1 = 0, reserved10: u1 = 0, @@ -20846,23 +27894,34 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, - COMP6OUT: u1, // bit offset: 30 desc: Comparator 6 output - COMP6LOCK: u1, // bit offset: 31 desc: Comparator 6 lock + /// Comparator 6 output + COMP6OUT: u1 = 0, + /// Comparator 6 lock + COMP6LOCK: u1 = 0, }); - // byte offset: 52 control and status register + + /// control and status register pub const COMP7_CSR = mmio(Address + 0x00000034, 32, packed struct { - COMP7EN: u1, // bit offset: 0 desc: Comparator 7 enable - reserved1: u1 = 0, - COMP7MODE: u2, // bit offset: 2 desc: Comparator 7 mode - COMP7INSEL: u3, // bit offset: 4 desc: Comparator 7 inverting input selection - COMP7INPSEL: u1, // bit offset: 7 desc: Comparator 7 non inverted input selection + /// Comparator 7 enable + COMP7EN: u1 = 0, + reserved1: u1 = 0, + /// Comparator 7 mode + COMP7MODE: u2 = 0, + /// Comparator 7 inverting input selection + COMP7INSEL: u3 = 0, + /// Comparator 7 non inverted input selection + COMP7INPSEL: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - COMP7_OUT_SEL: u4, // bit offset: 10 desc: Comparator 7 output selection + /// Comparator 7 output selection + COMP7_OUT_SEL: u4 = 0, reserved4: u1 = 0, - COMP7POL: u1, // bit offset: 15 desc: Comparator 7 output polarity - COMP7HYST: u2, // bit offset: 16 desc: Comparator 7 hysteresis - COMP7_BLANKING: u3, // bit offset: 18 desc: Comparator 7 blanking source + /// Comparator 7 output polarity + COMP7POL: u1 = 0, + /// Comparator 7 hysteresis + COMP7HYST: u2 = 0, + /// Comparator 7 blanking source + COMP7_BLANKING: u3 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -20872,113 +27931,156 @@ pub const SYSCFG_COMP_OPAMP = extern struct { reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - COMP7OUT: u1, // bit offset: 30 desc: Comparator 7 output - COMP7LOCK: u1, // bit offset: 31 desc: Comparator 7 lock + /// Comparator 7 output + COMP7OUT: u1 = 0, + /// Comparator 7 lock + COMP7LOCK: u1 = 0, }); - // byte offset: 56 control register + + /// control register pub const OPAMP1_CSR = mmio(Address + 0x00000038, 32, packed struct { - OPAMP1_EN: u1, // bit offset: 0 desc: OPAMP1 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP1 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP1 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP1 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP1 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 1 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 1 lock - }); - // byte offset: 60 control register + /// OPAMP1 enable + OPAMP1_EN: u1 = 0, + /// OPAMP1 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP1 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP1 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP1 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 1 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 1 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP2_CSR = mmio(Address + 0x0000003c, 32, packed struct { - OPAMP2EN: u1, // bit offset: 0 desc: OPAMP2 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP2 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP2 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP2 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP2 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CAL_SEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 2 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 2 lock - }); - // byte offset: 64 control register + /// OPAMP2 enable + OPAMP2EN: u1 = 0, + /// OPAMP2 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP2 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP2 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP2 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CAL_SEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 2 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 2 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP3_CSR = mmio(Address + 0x00000040, 32, packed struct { - OPAMP3EN: u1, // bit offset: 0 desc: OPAMP3 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP3 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP3 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP3 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP3 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 3 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 3 lock - }); - // byte offset: 68 control register + /// OPAMP3 enable + OPAMP3EN: u1 = 0, + /// OPAMP3 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP3 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP3 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP3 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 3 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 3 lock + LOCK: u1 = 0, + }); + + /// control register pub const OPAMP4_CSR = mmio(Address + 0x00000044, 32, packed struct { - OPAMP4EN: u1, // bit offset: 0 desc: OPAMP4 enable - FORCE_VP: u1, // bit offset: 1 desc: FORCE_VP - VP_SEL: u2, // bit offset: 2 desc: OPAMP4 Non inverting input selection - reserved1: u1 = 0, - VM_SEL: u2, // bit offset: 5 desc: OPAMP4 inverting input selection - TCM_EN: u1, // bit offset: 7 desc: Timer controlled Mux mode enable - VMS_SEL: u1, // bit offset: 8 desc: OPAMP4 inverting input secondary selection - VPS_SEL: u2, // bit offset: 9 desc: OPAMP4 Non inverting input secondary selection - CALON: u1, // bit offset: 11 desc: Calibration mode enable - CALSEL: u2, // bit offset: 12 desc: Calibration selection - PGA_GAIN: u4, // bit offset: 14 desc: Gain in PGA mode - USER_TRIM: u1, // bit offset: 18 desc: User trimming enable - TRIMOFFSETP: u5, // bit offset: 19 desc: Offset trimming value (PMOS) - TRIMOFFSETN: u5, // bit offset: 24 desc: Offset trimming value (NMOS) - TSTREF: u1, // bit offset: 29 desc: TSTREF - OUTCAL: u1, // bit offset: 30 desc: OPAMP 4 ouput status flag - LOCK: u1, // bit offset: 31 desc: OPAMP 4 lock + /// OPAMP4 enable + OPAMP4EN: u1 = 0, + /// OPAMP4 Non inverting input selection + VP_SEL: u2 = 0, + reserved1: u1 = 0, + /// OPAMP4 inverting input selection + VM_SEL: u2 = 0, + /// Timer controlled Mux mode enable + TCM_EN: u1 = 0, + /// OPAMP4 inverting input secondary selection + VMS_SEL: u1 = 0, + /// OPAMP4 Non inverting input secondary selection + VPS_SEL: u2 = 0, + /// Calibration mode enable + CALON: u1 = 0, + /// Calibration selection + CALSEL: u2 = 0, + /// Gain in PGA mode + PGA_GAIN: u4 = 0, + /// User trimming enable + USER_TRIM: u1 = 0, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5 = 0, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5 = 0, + /// OPAMP 4 ouput status flag + OUTCAL: u1 = 0, + /// OPAMP 4 lock + LOCK: u1 = 0, }); }; + +/// Flexible memory controller pub const FMC = extern struct { pub const Address: u32 = 0xa0000400; - // byte offset: 0 SRAM/NOR-Flash chip-select control register 1 + + /// SRAM/NOR-Flash chip-select control register 1 pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - reserved2: u1 = 0, - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, + reserved2: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW - CCLKEN: u1, // bit offset: 20 desc: CCLKEN padding11: u1 = 0, padding10: u1 = 0, padding9: u1 = 0, @@ -20991,38 +28093,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SRAM/NOR-Flash chip-select timing register 1 + + /// SRAM/NOR-Flash chip-select timing register 1 pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SRAM/NOR-Flash chip-select control register 2 + + /// SRAM/NOR-Flash chip-select control register 2 pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21036,38 +28119,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SRAM/NOR-Flash chip-select timing register 2 + + /// SRAM/NOR-Flash chip-select timing register 2 pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 16 SRAM/NOR-Flash chip-select control register 3 + + /// SRAM/NOR-Flash chip-select control register 3 pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21081,38 +28145,19 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 SRAM/NOR-Flash chip-select timing register 3 + + /// SRAM/NOR-Flash chip-select timing register 3 pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 SRAM/NOR-Flash chip-select control register 4 + + /// SRAM/NOR-Flash chip-select control register 4 pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - MBKEN: u1, // bit offset: 0 desc: MBKEN - MUXEN: u1, // bit offset: 1 desc: MUXEN - MTYP: u2, // bit offset: 2 desc: MTYP - MWID: u2, // bit offset: 4 desc: MWID - FACCEN: u1, // bit offset: 6 desc: FACCEN - reserved1: u1 = 0, - BURSTEN: u1, // bit offset: 8 desc: BURSTEN - WAITPOL: u1, // bit offset: 9 desc: WAITPOL - WRAPMOD: u1, // bit offset: 10 desc: WRAPMOD - WAITCFG: u1, // bit offset: 11 desc: WAITCFG - WREN: u1, // bit offset: 12 desc: WREN - WAITEN: u1, // bit offset: 13 desc: WAITEN - EXTMOD: u1, // bit offset: 14 desc: EXTMOD - ASYNCWAIT: u1, // bit offset: 15 desc: ASYNCWAIT + reserved1: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - CBURSTRW: u1, // bit offset: 19 desc: CBURSTRW padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21126,31 +28171,18 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 SRAM/NOR-Flash chip-select timing register 4 + + /// SRAM/NOR-Flash chip-select timing register 4 pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: BUSTURN - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 96 PC Card/NAND Flash control register 2 + + /// PC Card/NAND Flash control register 2 pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21164,15 +28196,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 100 FIFO status and interrupt register 2 + + /// FIFO status and interrupt register 2 pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21199,37 +28225,21 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 104 Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 108 Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 116 ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 128 PC Card/NAND Flash control register 3 + + /// Common memory space timing register 2 + pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); + + /// Attribute memory space timing register 2 + pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct {}); + + /// ECC result register 2 + pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct {}); + + /// PC Card/NAND Flash control register 3 pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21243,15 +28253,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 132 FIFO status and interrupt register 3 + + /// FIFO status and interrupt register 3 pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21278,37 +28282,21 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 136 Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 140 Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 148 ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct { - ECCx: u32, // bit offset: 0 desc: ECCx - }); - // byte offset: 160 PC Card/NAND Flash control register 4 + + /// Common memory space timing register 3 + pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Attribute memory space timing register 3 + pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); + + /// ECC result register 3 + pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); + + /// PC Card/NAND Flash control register 4 pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { reserved1: u1 = 0, - PWAITEN: u1, // bit offset: 1 desc: PWAITEN - PBKEN: u1, // bit offset: 2 desc: PBKEN - PTYP: u1, // bit offset: 3 desc: PTYP - PWID: u2, // bit offset: 4 desc: PWID - ECCEN: u1, // bit offset: 6 desc: ECCEN reserved3: u1 = 0, reserved2: u1 = 0, - TCLR: u4, // bit offset: 9 desc: TCLR - TAR: u4, // bit offset: 13 desc: TAR - ECCPS: u3, // bit offset: 17 desc: ECCPS padding12: u1 = 0, padding11: u1 = 0, padding10: u1 = 0, @@ -21322,15 +28310,9 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 164 FIFO status and interrupt register 4 + + /// FIFO status and interrupt register 4 pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - IRS: u1, // bit offset: 0 desc: IRS - ILS: u1, // bit offset: 1 desc: ILS - IFS: u1, // bit offset: 2 desc: IFS - IREN: u1, // bit offset: 3 desc: IREN - ILEN: u1, // bit offset: 4 desc: ILEN - IFEN: u1, // bit offset: 5 desc: IFEN - FEMPT: u1, // bit offset: 6 desc: FEMPT padding25: u1 = 0, padding24: u1 = 0, padding23: u1 = 0, @@ -21357,299 +28339,170 @@ pub const FMC = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 168 Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct { - MEMSETx: u8, // bit offset: 0 desc: MEMSETx - MEMWAITx: u8, // bit offset: 8 desc: MEMWAITx - MEMHOLDx: u8, // bit offset: 16 desc: MEMHOLDx - MEMHIZx: u8, // bit offset: 24 desc: MEMHIZx - }); - // byte offset: 172 Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct { - ATTSETx: u8, // bit offset: 0 desc: ATTSETx - ATTWAITx: u8, // bit offset: 8 desc: ATTWAITx - ATTHOLDx: u8, // bit offset: 16 desc: ATTHOLDx - ATTHIZx: u8, // bit offset: 24 desc: ATTHIZx - }); - // byte offset: 176 I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct { - IOSETx: u8, // bit offset: 0 desc: IOSETx - IOWAITx: u8, // bit offset: 8 desc: IOWAITx - IOHOLDx: u8, // bit offset: 16 desc: IOHOLDx - IOHIZx: u8, // bit offset: 24 desc: IOHIZx - }); - // byte offset: 260 SRAM/NOR-Flash write timing registers 1 + + /// Common memory space timing register 4 + pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); + + /// Attribute memory space timing register 4 + pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); + + /// I/O space timing register 4 + pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); + + /// SRAM/NOR-Flash write timing registers 1 pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 268 SRAM/NOR-Flash write timing registers 2 + + /// SRAM/NOR-Flash write timing registers 2 pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 276 SRAM/NOR-Flash write timing registers 3 + + /// SRAM/NOR-Flash write timing registers 3 pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 284 SRAM/NOR-Flash write timing registers 4 + + /// SRAM/NOR-Flash write timing registers 4 pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - ADDSET: u4, // bit offset: 0 desc: ADDSET - ADDHLD: u4, // bit offset: 4 desc: ADDHLD - DATAST: u8, // bit offset: 8 desc: DATAST - BUSTURN: u4, // bit offset: 16 desc: Bus turnaround phase duration - CLKDIV: u4, // bit offset: 20 desc: CLKDIV - DATLAT: u4, // bit offset: 24 desc: DATLAT - ACCMOD: u2, // bit offset: 28 desc: ACCMOD + /// Bus turnaround phase duration + BUSTURN: u4 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// Nested Vectored Interrupt Controller pub const NVIC = extern struct { pub const Address: u32 = 0xe000e100; - // byte offset: 0 Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 4 Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 8 Interrupt Set-Enable Register - pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct { - SETENA: u32, // bit offset: 0 desc: SETENA - }); - // byte offset: 128 Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 132 Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 136 Interrupt Clear-Enable Register - pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct { - CLRENA: u32, // bit offset: 0 desc: CLRENA - }); - // byte offset: 256 Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 260 Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 264 Interrupt Set-Pending Register - pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct { - SETPEND: u32, // bit offset: 0 desc: SETPEND - }); - // byte offset: 384 Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 388 Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 392 Interrupt Clear-Pending Register - pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct { - CLRPEND: u32, // bit offset: 0 desc: CLRPEND - }); - // byte offset: 512 Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 516 Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 520 Interrupt Active Bit Register - pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct { - ACTIVE: u32, // bit offset: 0 desc: ACTIVE - }); - // byte offset: 768 Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 772 Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 776 Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 780 Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 784 Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 788 Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 792 Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 796 Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 800 Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 804 Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 808 Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 812 Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 816 Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 820 Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 824 Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 828 Interrupt Priority Register - pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 832 Interrupt Priority Register - pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 836 Interrupt Priority Register - pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 840 Interrupt Priority Register - pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 844 Interrupt Priority Register - pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); - // byte offset: 848 Interrupt Priority Register - pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct { - IPR_N0: u8, // bit offset: 0 desc: IPR_N0 - IPR_N1: u8, // bit offset: 8 desc: IPR_N1 - IPR_N2: u8, // bit offset: 16 desc: IPR_N2 - IPR_N3: u8, // bit offset: 24 desc: IPR_N3 - }); + + /// Interrupt Set-Enable Register + pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct {}); + + /// Interrupt Set-Enable Register + pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct {}); + + /// Interrupt Clear-Enable Register + pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct {}); + + /// Interrupt Set-Pending Register + pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct {}); + + /// Interrupt Clear-Pending Register + pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct {}); + + /// Interrupt Active Bit Register + pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct {}); + + /// Interrupt Priority Register + pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct {}); }; + +/// Floting point unit pub const FPU = extern struct { pub const Address: u32 = 0xe000ef34; - // byte offset: 0 Floating-point context control register + + /// Floating-point context control register pub const FPCCR = mmio(Address + 0x00000000, 32, packed struct { - LSPACT: u1, // bit offset: 0 desc: LSPACT - USER: u1, // bit offset: 1 desc: USER reserved1: u1 = 0, - THREAD: u1, // bit offset: 3 desc: THREAD - HFRDY: u1, // bit offset: 4 desc: HFRDY - MMRDY: u1, // bit offset: 5 desc: MMRDY - BFRDY: u1, // bit offset: 6 desc: BFRDY reserved2: u1 = 0, - MONRDY: u1, // bit offset: 8 desc: MONRDY reserved23: u1 = 0, reserved22: u1 = 0, reserved21: u1 = 0, @@ -21671,26 +28524,33 @@ pub const FPU = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - LSPEN: u1, // bit offset: 30 desc: LSPEN - ASPEN: u1, // bit offset: 31 desc: ASPEN }); - // byte offset: 4 Floating-point context address register + + /// Floating-point context address register pub const FPCAR = mmio(Address + 0x00000004, 32, packed struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - ADDRESS: u29, // bit offset: 3 desc: Location of unpopulated floating-point + /// Location of unpopulated floating-point + ADDRESS: u29 = 0, }); - // byte offset: 8 Floating-point status control register + + /// Floating-point status control register pub const FPSCR = mmio(Address + 0x00000008, 32, packed struct { - IOC: u1, // bit offset: 0 desc: Invalid operation cumulative exception bit - DZC: u1, // bit offset: 1 desc: Division by zero cumulative exception bit. - OFC: u1, // bit offset: 2 desc: Overflow cumulative exception bit - UFC: u1, // bit offset: 3 desc: Underflow cumulative exception bit - IXC: u1, // bit offset: 4 desc: Inexact cumulative exception bit - reserved2: u1 = 0, - reserved1: u1 = 0, - IDC: u1, // bit offset: 7 desc: Input denormal cumulative exception bit. + /// Invalid operation cumulative exception bit + IOC: u1 = 0, + /// Division by zero cumulative exception bit. + DZC: u1 = 0, + /// Overflow cumulative exception bit + OFC: u1 = 0, + /// Underflow cumulative exception bit + UFC: u1 = 0, + /// Inexact cumulative exception bit + IXC: u1 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Input denormal cumulative exception bit. + IDC: u1 = 0, reserved16: u1 = 0, reserved15: u1 = 0, reserved14: u1 = 0, @@ -21705,22 +28565,34 @@ pub const FPU = extern struct { reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - RMode: u2, // bit offset: 22 desc: Rounding Mode control field - FZ: u1, // bit offset: 24 desc: Flush-to-zero mode control bit: - DN: u1, // bit offset: 25 desc: Default NaN mode control bit - AHP: u1, // bit offset: 26 desc: Alternative half-precision control bit + /// Rounding Mode control field + RMode: u2 = 0, + /// Flush-to-zero mode control bit: + FZ: u1 = 0, + /// Default NaN mode control bit + DN: u1 = 0, + /// Alternative half-precision control bit + AHP: u1 = 0, reserved17: u1 = 0, - V: u1, // bit offset: 28 desc: Overflow condition code flag - C: u1, // bit offset: 29 desc: Carry condition code flag - Z: u1, // bit offset: 30 desc: Zero condition code flag - N: u1, // bit offset: 31 desc: Negative condition code flag + /// Overflow condition code flag + V: u1 = 0, + /// Carry condition code flag + C: u1 = 0, + /// Zero condition code flag + Z: u1 = 0, + /// Negative condition code flag + N: u1 = 0, }); }; + +/// Memory protection unit pub const MPU = extern struct { pub const Address: u32 = 0xe000ed90; - // byte offset: 0 MPU type register + + /// MPU type register pub const MPU_TYPER = mmio(Address + 0x00000000, 32, packed struct { - SEPARATE: u1, // bit offset: 0 desc: Separate flag + /// Separate flag + SEPARATE: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, @@ -21728,8 +28600,10 @@ pub const MPU = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DREGION: u8, // bit offset: 8 desc: Number of MPU data regions - IREGION: u8, // bit offset: 16 desc: Number of MPU instruction regions + /// Number of MPU data regions + DREGION: u8 = 0, + /// Number of MPU instruction regions + IREGION: u8 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21739,11 +28613,15 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 MPU control register + + /// MPU control register pub const MPU_CTRL = mmio(Address + 0x00000004, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Enables the MPU - HFNMIENA: u1, // bit offset: 1 desc: Enables the operation of MPU during hard fault - PRIVDEFENA: u1, // bit offset: 2 desc: Enable priviliged software access to default memory map + /// Enables the MPU + ENABLE: u1 = 0, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1 = 0, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1 = 0, padding29: u1 = 0, padding28: u1 = 0, padding27: u1 = 0, @@ -21774,9 +28652,11 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 MPU region number register + + /// MPU region number register pub const MPU_RNR = mmio(Address + 0x00000008, 32, packed struct { - REGION: u8, // bit offset: 0 desc: MPU region + /// MPU region + REGION: u8 = 0, padding24: u1 = 0, padding23: u1 = 0, padding22: u1 = 0, @@ -21802,40 +28682,60 @@ pub const MPU = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 MPU region base address register + + /// MPU region base address register pub const MPU_RBAR = mmio(Address + 0x0000000c, 32, packed struct { - REGION: u4, // bit offset: 0 desc: MPU region field - VALID: u1, // bit offset: 4 desc: MPU region number valid - ADDR: u27, // bit offset: 5 desc: Region base address field + /// MPU region field + REGION: u4 = 0, + /// MPU region number valid + VALID: u1 = 0, + /// Region base address field + ADDR: u27 = 0, }); - // byte offset: 16 MPU region attribute and size register + + /// MPU region attribute and size register pub const MPU_RASR = mmio(Address + 0x00000010, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Region enable bit. - SIZE: u5, // bit offset: 1 desc: Size of the MPU protection region - reserved2: u1 = 0, - reserved1: u1 = 0, - SRD: u8, // bit offset: 8 desc: Subregion disable bits - B: u1, // bit offset: 16 desc: memory attribute - C: u1, // bit offset: 17 desc: memory attribute - S: u1, // bit offset: 18 desc: Shareable memory attribute - TEX: u3, // bit offset: 19 desc: memory attribute + /// Region enable bit. + ENABLE: u1 = 0, + /// Size of the MPU protection region + SIZE: u5 = 0, + reserved2: u1 = 0, + reserved1: u1 = 0, + /// Subregion disable bits + SRD: u8 = 0, + /// memory attribute + B: u1 = 0, + /// memory attribute + C: u1 = 0, + /// Shareable memory attribute + S: u1 = 0, + /// memory attribute + TEX: u3 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - AP: u3, // bit offset: 24 desc: Access permission + /// Access permission + AP: u3 = 0, reserved5: u1 = 0, - XN: u1, // bit offset: 28 desc: Instruction access disable bit + /// Instruction access disable bit + XN: u1 = 0, padding3: u1 = 0, padding2: u1 = 0, padding1: u1 = 0, }); }; + +/// SysTick timer pub const STK = extern struct { pub const Address: u32 = 0xe000e010; - // byte offset: 0 SysTick control and status register + + /// SysTick control and status register pub const CTRL = mmio(Address + 0x00000000, 32, packed struct { - ENABLE: u1, // bit offset: 0 desc: Counter enable - TICKINT: u1, // bit offset: 1 desc: SysTick exception request enable - CLKSOURCE: u1, // bit offset: 2 desc: Clock source selection + /// Counter enable + ENABLE: u1 = 0, + /// SysTick exception request enable + TICKINT: u1 = 0, + /// Clock source selection + CLKSOURCE: u1 = 0, reserved13: u1 = 0, reserved12: u1 = 0, reserved11: u1 = 0, @@ -21849,7 +28749,6 @@ pub const STK = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - COUNTFLAG: u1, // bit offset: 16 desc: COUNTFLAG padding15: u1 = 0, padding14: u1 = 0, padding13: u1 = 0, @@ -21866,9 +28765,11 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 4 SysTick reload value register + + /// SysTick reload value register pub const LOAD = mmio(Address + 0x00000004, 32, packed struct { - RELOAD: u24, // bit offset: 0 desc: RELOAD value + /// RELOAD value + RELOAD: u24 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21878,9 +28779,11 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 8 SysTick current value register + + /// SysTick current value register pub const VAL = mmio(Address + 0x00000008, 32, packed struct { - CURRENT: u24, // bit offset: 0 desc: Current counter value + /// Current counter value + CURRENT: u24 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -21890,51 +28793,74 @@ pub const STK = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 SysTick calibration value register + + /// SysTick calibration value register pub const CALIB = mmio(Address + 0x0000000c, 32, packed struct { - TENMS: u24, // bit offset: 0 desc: Calibration value + /// Calibration value + TENMS: u24 = 0, reserved6: u1 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - SKEW: u1, // bit offset: 30 desc: SKEW flag: Indicates whether the TENMS value is exact - NOREF: u1, // bit offset: 31 desc: NOREF flag. Reads as zero + /// SKEW flag: Indicates whether the TENMS value is exact + SKEW: u1 = 0, + /// NOREF flag. Reads as zero + NOREF: u1 = 0, }); }; + +/// System control block pub const SCB = extern struct { pub const Address: u32 = 0xe000ed00; - // byte offset: 0 CPUID base register + + /// CPUID base register pub const CPUID = mmio(Address + 0x00000000, 32, packed struct { - Revision: u4, // bit offset: 0 desc: Revision number - PartNo: u12, // bit offset: 4 desc: Part number of the processor - Constant: u4, // bit offset: 16 desc: Reads as 0xF - Variant: u4, // bit offset: 20 desc: Variant number - Implementer: u8, // bit offset: 24 desc: Implementer code + /// Revision number + Revision: u4 = 0, + /// Part number of the processor + PartNo: u12 = 0, + /// Reads as 0xF + Constant: u4 = 0, + /// Variant number + Variant: u4 = 0, + /// Implementer code + Implementer: u8 = 0, }); - // byte offset: 4 Interrupt control and state register + + /// Interrupt control and state register pub const ICSR = mmio(Address + 0x00000004, 32, packed struct { - VECTACTIVE: u9, // bit offset: 0 desc: Active vector + /// Active vector + VECTACTIVE: u9 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - RETTOBASE: u1, // bit offset: 11 desc: Return to base level - VECTPENDING: u7, // bit offset: 12 desc: Pending vector + /// Return to base level + RETTOBASE: u1 = 0, + /// Pending vector + VECTPENDING: u7 = 0, reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, - ISRPENDING: u1, // bit offset: 22 desc: Interrupt pending flag + /// Interrupt pending flag + ISRPENDING: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - PENDSTCLR: u1, // bit offset: 25 desc: SysTick exception clear-pending bit - PENDSTSET: u1, // bit offset: 26 desc: SysTick exception set-pending bit - PENDSVCLR: u1, // bit offset: 27 desc: PendSV clear-pending bit - PENDSVSET: u1, // bit offset: 28 desc: PendSV set-pending bit + /// SysTick exception clear-pending bit + PENDSTCLR: u1 = 0, + /// SysTick exception set-pending bit + PENDSTSET: u1 = 0, + /// PendSV clear-pending bit + PENDSVCLR: u1 = 0, + /// PendSV set-pending bit + PENDSVSET: u1 = 0, reserved9: u1 = 0, reserved8: u1 = 0, - NMIPENDSET: u1, // bit offset: 31 desc: NMI set-pending bit. + /// NMI set-pending bit. + NMIPENDSET: u1 = 0, }); - // byte offset: 8 Vector table offset register + + /// Vector table offset register pub const VTOR = mmio(Address + 0x00000008, 32, packed struct { reserved9: u1 = 0, reserved8: u1 = 0, @@ -21945,35 +28871,33 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - TBLOFF: u21, // bit offset: 9 desc: Vector table base offset field + /// Vector table base offset field + TBLOFF: u21 = 0, padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 12 Application interrupt and reset control register + + /// Application interrupt and reset control register pub const AIRCR = mmio(Address + 0x0000000c, 32, packed struct { - VECTRESET: u1, // bit offset: 0 desc: VECTRESET - VECTCLRACTIVE: u1, // bit offset: 1 desc: VECTCLRACTIVE - SYSRESETREQ: u1, // bit offset: 2 desc: SYSRESETREQ reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRIGROUP: u3, // bit offset: 8 desc: PRIGROUP reserved9: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, - ENDIANESS: u1, // bit offset: 15 desc: ENDIANESS - VECTKEYSTAT: u16, // bit offset: 16 desc: Register key + /// Register key + VECTKEYSTAT: u16 = 0, }); - // byte offset: 16 System control register + + /// System control register pub const SCR = mmio(Address + 0x00000010, 32, packed struct { reserved1: u1 = 0, - SLEEPONEXIT: u1, // bit offset: 1 desc: SLEEPONEXIT - SLEEPDEEP: u1, // bit offset: 2 desc: SLEEPDEEP reserved2: u1 = 0, - SEVEONPEND: u1, // bit offset: 4 desc: Send Event on Pending bit + /// Send Event on Pending bit + SEVEONPEND: u1 = 0, padding27: u1 = 0, padding26: u1 = 0, padding25: u1 = 0, @@ -22002,18 +28926,17 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 20 Configuration and control register + + /// Configuration and control register pub const CCR = mmio(Address + 0x00000014, 32, packed struct { - NONBASETHRDENA: u1, // bit offset: 0 desc: Configures how the processor enters Thread mode - USERSETMPEND: u1, // bit offset: 1 desc: USERSETMPEND + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1 = 0, reserved1: u1 = 0, - UNALIGN__TRP: u1, // bit offset: 3 desc: UNALIGN_ TRP - DIV_0_TRP: u1, // bit offset: 4 desc: DIV_0_TRP + /// UNALIGN_ TRP + UNALIGN__TRP: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - BFHFNMIGN: u1, // bit offset: 8 desc: BFHFNMIGN - STKALIGN: u1, // bit offset: 9 desc: STKALIGN padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -22037,11 +28960,15 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 24 System handler priority registers + + /// System handler priority registers pub const SHPR1 = mmio(Address + 0x00000018, 32, packed struct { - PRI_4: u8, // bit offset: 0 desc: Priority of system handler 4 - PRI_5: u8, // bit offset: 8 desc: Priority of system handler 5 - PRI_6: u8, // bit offset: 16 desc: Priority of system handler 6 + /// Priority of system handler 4 + PRI_4: u8 = 0, + /// Priority of system handler 5 + PRI_5: u8 = 0, + /// Priority of system handler 6 + PRI_6: u8 = 0, padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -22051,7 +28978,8 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 28 System handler priority registers + + /// System handler priority registers pub const SHPR2 = mmio(Address + 0x0000001c, 32, packed struct { reserved24: u1 = 0, reserved23: u1 = 0, @@ -22077,9 +29005,11 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRI_11: u8, // bit offset: 24 desc: Priority of system handler 11 + /// Priority of system handler 11 + PRI_11: u8 = 0, }); - // byte offset: 32 System handler priority registers + + /// System handler priority registers pub const SHPR3 = mmio(Address + 0x00000020, 32, packed struct { reserved16: u1 = 0, reserved15: u1 = 0, @@ -22097,30 +29027,47 @@ pub const SCB = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - PRI_14: u8, // bit offset: 16 desc: Priority of system handler 14 - PRI_15: u8, // bit offset: 24 desc: Priority of system handler 15 + /// Priority of system handler 14 + PRI_14: u8 = 0, + /// Priority of system handler 15 + PRI_15: u8 = 0, }); - // byte offset: 36 System handler control and state register + + /// System handler control and state register pub const SHCRS = mmio(Address + 0x00000024, 32, packed struct { - MEMFAULTACT: u1, // bit offset: 0 desc: Memory management fault exception active bit - BUSFAULTACT: u1, // bit offset: 1 desc: Bus fault exception active bit + /// Memory management fault exception active bit + MEMFAULTACT: u1 = 0, + /// Bus fault exception active bit + BUSFAULTACT: u1 = 0, reserved1: u1 = 0, - USGFAULTACT: u1, // bit offset: 3 desc: Usage fault exception active bit + /// Usage fault exception active bit + USGFAULTACT: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - SVCALLACT: u1, // bit offset: 7 desc: SVC call active bit - MONITORACT: u1, // bit offset: 8 desc: Debug monitor active bit + /// SVC call active bit + SVCALLACT: u1 = 0, + /// Debug monitor active bit + MONITORACT: u1 = 0, reserved5: u1 = 0, - PENDSVACT: u1, // bit offset: 10 desc: PendSV exception active bit - SYSTICKACT: u1, // bit offset: 11 desc: SysTick exception active bit - USGFAULTPENDED: u1, // bit offset: 12 desc: Usage fault exception pending bit - MEMFAULTPENDED: u1, // bit offset: 13 desc: Memory management fault exception pending bit - BUSFAULTPENDED: u1, // bit offset: 14 desc: Bus fault exception pending bit - SVCALLPENDED: u1, // bit offset: 15 desc: SVC call pending bit - MEMFAULTENA: u1, // bit offset: 16 desc: Memory management fault enable bit - BUSFAULTENA: u1, // bit offset: 17 desc: Bus fault enable bit - USGFAULTENA: u1, // bit offset: 18 desc: Usage fault enable bit + /// PendSV exception active bit + PENDSVACT: u1 = 0, + /// SysTick exception active bit + SYSTICKACT: u1 = 0, + /// Usage fault exception pending bit + USGFAULTPENDED: u1 = 0, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1 = 0, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1 = 0, + /// SVC call pending bit + SVCALLPENDED: u1 = 0, + /// Memory management fault enable bit + MEMFAULTENA: u1 = 0, + /// Bus fault enable bit + BUSFAULTENA: u1 = 0, + /// Usage fault enable bit + USGFAULTENA: u1 = 0, padding13: u1 = 0, padding12: u1 = 0, padding11: u1 = 0, @@ -22135,34 +29082,51 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 40 Configurable fault status register + + /// Configurable fault status register pub const CFSR_UFSR_BFSR_MMFSR = mmio(Address + 0x00000028, 32, packed struct { reserved1: u1 = 0, - IACCVIOL: u1, // bit offset: 1 desc: Instruction access violation flag + /// Instruction access violation flag + IACCVIOL: u1 = 0, reserved2: u1 = 0, - MUNSTKERR: u1, // bit offset: 3 desc: Memory manager fault on unstacking for a return from exception - MSTKERR: u1, // bit offset: 4 desc: Memory manager fault on stacking for exception entry. - MLSPERR: u1, // bit offset: 5 desc: MLSPERR + /// Memory manager fault on unstacking for a return from exception + MUNSTKERR: u1 = 0, + /// Memory manager fault on stacking for exception entry. + MSTKERR: u1 = 0, reserved3: u1 = 0, - MMARVALID: u1, // bit offset: 7 desc: Memory Management Fault Address Register (MMAR) valid flag - IBUSERR: u1, // bit offset: 8 desc: Instruction bus error - PRECISERR: u1, // bit offset: 9 desc: Precise data bus error - IMPRECISERR: u1, // bit offset: 10 desc: Imprecise data bus error - UNSTKERR: u1, // bit offset: 11 desc: Bus fault on unstacking for a return from exception - STKERR: u1, // bit offset: 12 desc: Bus fault on stacking for exception entry - LSPERR: u1, // bit offset: 13 desc: Bus fault on floating-point lazy state preservation + /// Memory Management Fault Address Register (MMAR) valid flag + MMARVALID: u1 = 0, + /// Instruction bus error + IBUSERR: u1 = 0, + /// Precise data bus error + PRECISERR: u1 = 0, + /// Imprecise data bus error + IMPRECISERR: u1 = 0, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1 = 0, + /// Bus fault on stacking for exception entry + STKERR: u1 = 0, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1 = 0, reserved4: u1 = 0, - BFARVALID: u1, // bit offset: 15 desc: Bus Fault Address Register (BFAR) valid flag - UNDEFINSTR: u1, // bit offset: 16 desc: Undefined instruction usage fault - INVSTATE: u1, // bit offset: 17 desc: Invalid state usage fault - INVPC: u1, // bit offset: 18 desc: Invalid PC load usage fault - NOCP: u1, // bit offset: 19 desc: No coprocessor usage fault. + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1 = 0, + /// Undefined instruction usage fault + UNDEFINSTR: u1 = 0, + /// Invalid state usage fault + INVSTATE: u1 = 0, + /// Invalid PC load usage fault + INVPC: u1 = 0, + /// No coprocessor usage fault. + NOCP: u1 = 0, reserved8: u1 = 0, reserved7: u1 = 0, reserved6: u1 = 0, reserved5: u1 = 0, - UNALIGNED: u1, // bit offset: 24 desc: Unaligned access usage fault - DIVBYZERO: u1, // bit offset: 25 desc: Divide by zero usage fault + /// Unaligned access usage fault + UNALIGNED: u1 = 0, + /// Divide by zero usage fault + DIVBYZERO: u1 = 0, padding6: u1 = 0, padding5: u1 = 0, padding4: u1 = 0, @@ -22170,10 +29134,12 @@ pub const SCB = extern struct { padding2: u1 = 0, padding1: u1 = 0, }); - // byte offset: 44 Hard fault status register + + /// Hard fault status register pub const HFSR = mmio(Address + 0x0000002c, 32, packed struct { reserved1: u1 = 0, - VECTTBL: u1, // bit offset: 1 desc: Vector table hard fault + /// Vector table hard fault + VECTTBL: u1 = 0, reserved29: u1 = 0, reserved28: u1 = 0, reserved27: u1 = 0, @@ -22202,27 +29168,33 @@ pub const SCB = extern struct { reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, - FORCED: u1, // bit offset: 30 desc: Forced hard fault - DEBUG_VT: u1, // bit offset: 31 desc: Reserved for Debug use - }); - // byte offset: 52 Memory management fault address register - pub const MMFAR = mmio(Address + 0x00000034, 32, packed struct { - MMFAR: u32, // bit offset: 0 desc: Memory management fault address + /// Forced hard fault + FORCED: u1 = 0, + /// Reserved for Debug use + DEBUG_VT: u1 = 0, }); - // byte offset: 56 Bus fault address register - pub const BFAR = mmio(Address + 0x00000038, 32, packed struct { - BFAR: u32, // bit offset: 0 desc: Bus fault address - }); - // byte offset: 60 Auxiliary fault status register + + /// Memory management fault address register + pub const MMFAR = @intToPtr(*volatile u32, Address + 0x00000034); + + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, Address + 0x00000038); + + /// Auxiliary fault status register pub const AFSR = mmio(Address + 0x0000003c, 32, packed struct { - IMPDEF: u32, // bit offset: 0 desc: Implementation defined + /// Implementation defined + IMPDEF: u32 = 0, }); }; + +/// Nested vectored interrupt controller pub const NVIC_STIR = extern struct { pub const Address: u32 = 0xe000ef00; - // byte offset: 0 Software trigger interrupt register + + /// Software trigger interrupt register pub const STIR = mmio(Address + 0x00000000, 32, packed struct { - INTID: u9, // bit offset: 0 desc: Software generated interrupt ID + /// Software generated interrupt ID + INTID: u9 = 0, padding23: u1 = 0, padding22: u1 = 0, padding21: u1 = 0, @@ -22248,9 +29220,12 @@ pub const NVIC_STIR = extern struct { padding1: u1 = 0, }); }; + +/// Floating point unit CPACR pub const FPU_CPACR = extern struct { pub const Address: u32 = 0xe000ed88; - // byte offset: 0 Coprocessor access control register + + /// Coprocessor access control register pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { reserved20: u1 = 0, reserved19: u1 = 0, @@ -22272,7 +29247,6 @@ pub const FPU_CPACR = extern struct { reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - CP: u4, // bit offset: 20 desc: CP padding8: u1 = 0, padding7: u1 = 0, padding6: u1 = 0, @@ -22283,20 +29257,18 @@ pub const FPU_CPACR = extern struct { padding1: u1 = 0, }); }; + +/// System control block ACTLR pub const SCB_ACTRL = extern struct { pub const Address: u32 = 0xe000e008; - // byte offset: 0 Auxiliary control register + + /// Auxiliary control register pub const ACTRL = mmio(Address + 0x00000000, 32, packed struct { - DISMCYCINT: u1, // bit offset: 0 desc: DISMCYCINT - DISDEFWBUF: u1, // bit offset: 1 desc: DISDEFWBUF - DISFOLD: u1, // bit offset: 2 desc: DISFOLD reserved5: u1 = 0, reserved4: u1 = 0, reserved3: u1 = 0, reserved2: u1 = 0, reserved1: u1 = 0, - DISFPCA: u1, // bit offset: 8 desc: DISFPCA - DISOOFP: u1, // bit offset: 9 desc: DISOOFP padding22: u1 = 0, padding21: u1 = 0, padding20: u1 = 0, @@ -22361,194 +29333,134 @@ pub const VectorTable = extern struct { /// Window Watchdog interrupt WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper and TimeStamp interrupts TAMP_STAMP: InterruptVector = makeUnhandledHandler("TAMP_STAMP"), - /// RTC Wakeup interrupt through the EXTI line RTC_WKUP: InterruptVector = makeUnhandledHandler("RTC_WKUP"), - /// Flash global interrupt FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line3 interrupt EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 and Touch sensing interrupts EXTI2_TSC: InterruptVector = makeUnhandledHandler("EXTI2_TSC"), - /// EXTI Line3 interrupt EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 channel 1 interrupt DMA1_CH1: InterruptVector = makeUnhandledHandler("DMA1_CH1"), - /// DMA1 channel 2 interrupt DMA1_CH2: InterruptVector = makeUnhandledHandler("DMA1_CH2"), - /// DMA1 channel 3 interrupt DMA1_CH3: InterruptVector = makeUnhandledHandler("DMA1_CH3"), - /// DMA1 channel 4 interrupt DMA1_CH4: InterruptVector = makeUnhandledHandler("DMA1_CH4"), - /// DMA1 channel 5 interrupt DMA1_CH5: InterruptVector = makeUnhandledHandler("DMA1_CH5"), - /// DMA1 channel 6 interrupt DMA1_CH6: InterruptVector = makeUnhandledHandler("DMA1_CH6"), - /// DMA1 channel 7interrupt DMA1_CH7: InterruptVector = makeUnhandledHandler("DMA1_CH7"), - /// ADC1 and ADC2 global interrupt ADC1_2: InterruptVector = makeUnhandledHandler("ADC1_2"), - /// USB High Priority/CAN_TX interrupts USB_HP_CAN_TX: InterruptVector = makeUnhandledHandler("USB_HP_CAN_TX"), - /// USB Low Priority/CAN_RX0 interrupts USB_LP_CAN_RX0: InterruptVector = makeUnhandledHandler("USB_LP_CAN_RX0"), - /// CAN_RX1 interrupt CAN_RX1: InterruptVector = makeUnhandledHandler("CAN_RX1"), - /// CAN_SCE interrupt CAN_SCE: InterruptVector = makeUnhandledHandler("CAN_SCE"), - /// EXTI Line5 to Line9 interrupts EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break/TIM15 global interruts TIM1_BRK_TIM15: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM15"), - /// TIM1 Update/TIM16 global interrupts TIM1_UP_TIM16: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM16"), - /// TIM1 trigger and commutation/TIM17 interrupts TIM1_TRG_COM_TIM17: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM17"), - /// TIM1 capture compare interrupt TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt and EXTI Line23 interrupt I2C1_EV_EXTI23: InterruptVector = makeUnhandledHandler("I2C1_EV_EXTI23"), - /// I2C1 error interrupt I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt & EXTI Line24 interrupt I2C2_EV_EXTI24: InterruptVector = makeUnhandledHandler("I2C2_EV_EXTI24"), - /// I2C2 error interrupt I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt and EXTI Line 25 interrupt USART1_EXTI25: InterruptVector = makeUnhandledHandler("USART1_EXTI25"), - /// USART2 global interrupt and EXTI Line 26 interrupt USART2_EXTI26: InterruptVector = makeUnhandledHandler("USART2_EXTI26"), - /// USART3 global interrupt and EXTI Line 28 interrupt USART3_EXTI28: InterruptVector = makeUnhandledHandler("USART3_EXTI28"), - /// EXTI Line15 to Line10 interrupts EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC alarm interrupt RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB wakeup from Suspend USB_WKUP: InterruptVector = makeUnhandledHandler("USB_WKUP"), - /// TIM8 break interrupt TIM8_BRK: InterruptVector = makeUnhandledHandler("TIM8_BRK"), - /// TIM8 update interrupt TIM8_UP: InterruptVector = makeUnhandledHandler("TIM8_UP"), - /// TIM8 Trigger and commutation interrupts TIM8_TRG_COM: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM"), - /// TIM8 capture compare interrupt TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt FMC: InterruptVector = makeUnhandledHandler("FMC"), reserved2: u32 = 0, reserved3: u32 = 0, - /// SPI3 global interrupt SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global and EXTI Line 34 interrupts UART4_EXTI34: InterruptVector = makeUnhandledHandler("UART4_EXTI34"), - /// UART5 global and EXTI Line 35 interrupts UART5_EXTI35: InterruptVector = makeUnhandledHandler("UART5_EXTI35"), - /// TIM6 global and DAC12 underrun interrupts TIM6_DACUNDER: InterruptVector = makeUnhandledHandler("TIM6_DACUNDER"), - /// TIM7 global interrupt TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 channel1 global interrupt DMA2_CH1: InterruptVector = makeUnhandledHandler("DMA2_CH1"), - /// DMA2 channel2 global interrupt DMA2_CH2: InterruptVector = makeUnhandledHandler("DMA2_CH2"), - /// DMA2 channel3 global interrupt DMA2_CH3: InterruptVector = makeUnhandledHandler("DMA2_CH3"), - /// DMA2 channel4 global interrupt DMA2_CH4: InterruptVector = makeUnhandledHandler("DMA2_CH4"), - /// DMA2 channel5 global interrupt DMA2_CH5: InterruptVector = makeUnhandledHandler("DMA2_CH5"), - /// ADC4 global interrupt ADC4: InterruptVector = makeUnhandledHandler("ADC4"), reserved4: u32 = 0, reserved5: u32 = 0, - - /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts + /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 + /// interrupts COMP123: InterruptVector = makeUnhandledHandler("COMP123"), - - /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 interrupts + /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 + /// interrupts COMP456: InterruptVector = makeUnhandledHandler("COMP456"), - /// COMP7 interrupt combined with EXTI Line 33 interrupt COMP7: InterruptVector = makeUnhandledHandler("COMP7"), reserved6: u32 = 0, @@ -22556,39 +29468,28 @@ pub const VectorTable = extern struct { reserved8: u32 = 0, reserved9: u32 = 0, reserved10: u32 = 0, - /// I2C3 Event interrupt I2C3_EV: InterruptVector = makeUnhandledHandler("I2C3_EV"), - /// I2C3 Error interrupt I2C3_ER: InterruptVector = makeUnhandledHandler("I2C3_ER"), - /// USB High priority interrupt USB_HP: InterruptVector = makeUnhandledHandler("USB_HP"), - /// USB Low priority interrupt USB_LP: InterruptVector = makeUnhandledHandler("USB_LP"), - /// USB wakeup from Suspend and EXTI Line 18 USB_WKUP_EXTI: InterruptVector = makeUnhandledHandler("USB_WKUP_EXTI"), - /// TIM20 Break interrupt TIM20_BRK: InterruptVector = makeUnhandledHandler("TIM20_BRK"), - /// TIM20 Upgrade interrupt TIM20_UP: InterruptVector = makeUnhandledHandler("TIM20_UP"), - /// TIM20 Trigger and Commutation interrupt TIM20_TRG_COM: InterruptVector = makeUnhandledHandler("TIM20_TRG_COM"), - /// TIM20 Capture Compare interrupt TIM20_CC: InterruptVector = makeUnhandledHandler("TIM20_CC"), - /// Floating point unit interrupt; Floating point interrupt FPU: InterruptVector = makeUnhandledHandler("FPU"), reserved11: u32 = 0, reserved12: u32 = 0, - /// SPI4 Global interrupt SPI4: InterruptVector = makeUnhandledHandler("SPI4"), }; @@ -22643,4 +29544,3 @@ export const vectors: VectorTable linksection("microzig_flash_start") = blk: { } break :blk temp; }; - diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py index e7cf163..b13f673 100755 --- a/src/tools/svd2zig.py +++ b/src/tools/svd2zig.py @@ -2,8 +2,10 @@ import sys import subprocess import re +import textwrap from cmsis_svd.parser import SVDParser +import cmsis_svd.model as model def cleanup_description(description): @@ -12,12 +14,19 @@ def cleanup_description(description): return ' '.join(description.replace('\n', ' ').split()) +def comment_description(description): + if description is None: + return None + + description = ' '.join(description.replace('\n', ' ').split()) + return textwrap.fill(description, width=80, initial_indent='/// ', subsequent_indent='/// ') + -# register names in some SVDs are using foo[n] for registers names -# and also for some reaons there are string formatters like %s in the reigster names -NAME_REGEX = re.compile(r"\[([^\]]+)]") -def cleanup_name(name): - return NAME_REGEX.sub(r"_\1", name).replace("%", "_") +def escape_field(field): + if not field[0].isdigit() and re.match(r'^[A-Za-z0-9_]+$', field): + return field + else: + return f"@\"{field}\"" class MMIOFileGenerator: @@ -32,89 +41,217 @@ class MMIOFileGenerator: def generate_enumerated_field(self, field): ''' returns something like: - name: enum(u){ // bit offset: 0 desc: foo description + name: enum(u){ // foo description name = value, // desc: ... name = value, // desc: _, // non-exhustive }, ''' - field.description = cleanup_description(field.description) - self.write_line(f"{field.name}:enum(u{field.bit_width}){{// bit offset: {field.bit_offset} desc: {field.description}") - - total_fields_with_values = 0 - for e in field.enumerated_values: - e.description = cleanup_description(e.description) - if e.value is None or e.name == "RESERVED": - # reserved fields doesn't have a value so we have to comment them out - self.write_line(f"// @\"{e.name}\", // desc: {e.description}") - else: - total_fields_with_values = total_fields_with_values + 1 - self.write_line(f"@\"{e.name}\" = {e.value}, // desc: {e.description}") - - # if the fields doesn't use all possible values make the enum non-exhaustive - if total_fields_with_values < 2**field.bit_width: - self.write_line("_, // non-exhaustive") - - self.write_line("},") + description = comment_description(field.description) + self.write_line(description) + self.write_line(f"{field.name}: u{field.bit_width} = 0,") + + # TODO: turn enums back on later + #self.write_line(f"{field.name}:enum(u{field.bit_width}){{") + + #total_fields_with_values = 0 + #for e in field.enumerated_values: + # e.description = cleanup_description(e.description) + # if e.value is None or e.name == "RESERVED": + # # reserved fields doesn't have a value so we have to comment them out + # escaped_field_name = escape_field(e.name) + # self.write_line(f"// {escaped_field_name}, // {e.description}") + # else: + # total_fields_with_values = total_fields_with_values + 1 + # escaped_field_name = escape_field(e.name) + # if e.name != e.description: + # self.write_line(f"/// {e.description}") + # self.write_line(f"{escaped_field_name} = {e.value},") + + ## if the fields doesn't use all possible values make the enum non-exhaustive + #if total_fields_with_values < 2**field.bit_width: + # self.write_line("_, // non-exhaustive") + + #self.write_line("},") return field.bit_offset + field.bit_width def generate_register_field(self, field): ''' returns something like: - name: u, // bit offset: 0 desc: foo description + name: u, // foo description ''' - field.description = cleanup_description(field.description) - self.write_line(f"{field.name}:u{field.bit_width},// bit offset: {field.bit_offset} desc: {field.description}") + description = comment_description(field.description) + if field.name != field.description: + self.write_line(description) + self.write_line(f"{field.name}:u{field.bit_width} = 0,") + return field.bit_offset + field.bit_width - def generate_register_declaration(self, register): - ''' + def generate_fields(self, fields, size): + last_offset = 0 + reserved_index = 0 + for field in sorted(fields, key=lambda f: f.bit_offset): + # workaround for NXP SVD which has overleaping reserved fields + if field.name == "RESERVED": + self.write_line(f"// RESERVED: u{field.bit_width}, // {field.description}") + continue + + if last_offset != field.bit_offset: + reserved_size = field.bit_offset - last_offset + self.generate_padding(reserved_size, "reserved", reserved_index) + reserved_index += reserved_size + + if field.is_enumerated_type: + last_offset = self.generate_enumerated_field(field) + else: + last_offset = self.generate_register_field(field) + + if size is not None and size != last_offset: + self.generate_padding(size - last_offset, "padding", 0) - ''' - register.description = cleanup_description(register.description) - self.write_line(f"// byte offset: {register.address_offset} {register.description}") - register.name = cleanup_name(register.name) + def generate_register_declaration_manual(self, name, description, address_offset, fields, size): + num_fields = len(fields) + description = comment_description(description) + self.write_line("") + self.write_line(description) + if num_fields == 0 or (num_fields == 1 and fields[0].bit_width == 32 and name == fields[0].name): + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {name} = @intToPtr(*volatile u{size}, Address + 0x{address_offset:08x});") + else: + self.write_line(f"pub const {name} = mmio(Address + 0x{address_offset:08x}, {size}, packed struct{{") + self.generate_fields(fields, size) + self.write_line("});") + + def generate_register_declaration(self, register): size = register.size if size == None: size = 32 # hack for now... - self.write_line(f" pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") - last_offset = 0 - reserved_index = 0 - for field in sorted(register.fields, key=lambda f: f.bit_offset): - # workaround for NXP SVD which has overleaping reserved fields - if field.name == "RESERVED": - self.write_line(f"// RESERVED: u{field.bit_width}, // bit offset: {field.bit_offset} desc: {field.description}") - continue - - if last_offset != field.bit_offset: - reserved_size = field.bit_offset - last_offset - self.generate_padding(reserved_size, "reserved", reserved_index) - reserved_index = reserved_index + reserved_size - - if field.is_enumerated_type: - last_offset = self.generate_enumerated_field(field) - else: - last_offset = self.generate_register_field(field) + num_fields = len(register.fields) + description = comment_description(register.description) - if size is not None: - if len(register.fields) == 0: - self.write_line(f"raw: u{size}, // placeholder field") - else: - self.generate_padding(size - last_offset, "padding", 0) + self.write_line("") + self.write_line(description) + if num_fields == 0 or (num_fields == 1 and register.fields[0].bit_width == 32 and register.name == register.fields[0].name): + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {register.name} = @intToPtr(*volatile u{size}, Address + 0x{register.address_offset:08x});") + else: + self.write_line(f"pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") + self.generate_fields(register.fields, size) + self.write_line("});") + + def generate_register_cluster(self, cluster): + if cluster.derived_from is not None: + raise Exception("TODO: derived_from") - self.write_line("});") + self.write_line("") + self.write_line(f"pub const {cluster.name} = struct {{") + for register in cluster._register: + if isinstance(register, model.SVDRegisterArray): + self.generate_register_array(register) + elif isinstance(register, model.SVDRegister): + self.generate_register_declaration(register) + + + self.write_line("};") + + def generate_register_cluster_array(self, cluster): + max_fields = int(cluster.dim_increment / 4) + if len(cluster._register) > max_fields: + raise Exception("not enough room for fields") + + name = cluster.name.replace("[%s]", "") + self.write_line(f"pub const {name} = @intToPtr(*volatile [{cluster.dim}]packed struct {{") + for register in cluster._register: + + size = register.size + if size == None: + size = 32 # hack for now... + last_offset = 0 + reserved_index = 0 + + if size != 32: + raise Exception("TODO: handle registers that are not 32-bit") + + description = comment_description(register.description) - def generate_peripherial_declaration(self, peripherial): - # TODO: write peripherial description - self.write_line(f"pub const {peripherial.name} = extern struct {{") - self.write_line(f"pub const Address: u32 = 0x{peripherial.base_address:08x};") + self.write_line("") + self.write_line(description) + if len(register.fields) == 0 or (len(register.fields) == 1 and register.fields[0].bit_width == size and register.name == register.fields[0].name): + self.write_line(f"{register.name}: u{size},") + else: + self.write_line(register.name + f": MMIO({size}, packed struct {{") + self.generate_fields(register.fields, size) + self.write_line("}),") + + + for i in range(0, max_fields - len(cluster._register)): + self.write_line(f" padding{i}: u32,") + + # TODO: this would be cleaner, but we'll probably run into packed struct bugs + #num_bits = size * (max_fields - len(cluster._register)) + #self.write_line(f"_: u{num_bits},") + + self.write_line(f" }}, Address + 0x{cluster.address_offset:08x});") + + + # TODO: calculate size in here, fine since everything we're working with rn is 32 bit + def generate_register_array(self, register_array): + description = comment_description(register_array.description) + + if register_array.dim_indices.start != 0 or ("%s" in register_array.name and not "[%s]" in register_array.name): + for i in register_array.dim_indices: + fmt = register_array.name.replace("%s", "{}") + name = fmt.format(i) + self.generate_register_declaration_manual(name, + register_array.description, + register_array.address_offset + (i * register_array.dim_increment), + register_array._fields, + 32) + return + + if register_array.dim_increment != 4: + raise Exception("TODO register " + register_array.name + " dim_increment != 4" + ", it is " + str(register_array.dim_increment)) + + name = register_array.name.replace("%s", "").replace("[]", "") + self.write_line(description) + num_fields = len(register_array._fields) + + # TODO: hardcoded 32 bit here + if num_fields == 0 or (num_fields == 1 and register_array._fields[0].bit_width == 32 and name == register_array._fields[0].name): + + # TODO: hardcoded 32 bit here + self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]u32, Address + 0x{register_array.address_offset:08x});") + else: + self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]MMIO(32, packed struct {{") + self.generate_fields(register_array._fields, 32) + + self.write_line(f"}}), Address + 0x{register_array.address_offset:08x});") + + def generate_peripheral_declaration(self, peripheral): + description = comment_description(peripheral.description) + self.write_line("") + self.write_line(description) + self.write_line(f"pub const {peripheral.name} = extern struct {{") + self.write_line(f"pub const Address: u32 = 0x{peripheral.base_address:08x};") - for register in sorted(peripherial.registers, key=lambda f: f.address_offset): + for register in sorted(peripheral._lookup_possibly_derived_attribute('registers'), key=lambda f: f.address_offset): self.generate_register_declaration(register) + for register_array in sorted(peripheral._lookup_possibly_derived_attribute('register_arrays'), key=lambda f: f.address_offset): + self.generate_register_array(register_array) + + for cluster in sorted(peripheral._lookup_possibly_derived_attribute('clusters'), key=lambda f: f.address_offset): + if isinstance(cluster, model.SVDRegisterCluster): + self.generate_register_cluster(cluster) + elif isinstance(cluster, model.SVDRegisterClusterArray): + #self.generate_register_cluster_array(cluster) + pass + else: + raise Exception("unhandled cluster type") + self.write_line("};") # TODO: descriptions on system interrupts/exceptions, turn on system interrupts/exceptions @@ -172,7 +309,8 @@ pub const VectorTable = extern struct { reserved_count += 1 if interrupt.description is not None: - self.write_line(f"\n /// {interrupt.description}") + description = comment_description(interrupt.description) + self.write_line(description) self.write_line(f" {interrupt.name}: InterruptVector = makeUnhandledHandler(\"{interrupt.name}\"),") expected_next_value += 1 self.write_line("};") @@ -235,11 +373,14 @@ export const vectors: VectorTable linksection(\"microzig_flash_start\") = blk: { self.write_line("// generated using svd2zig.py\n// DO NOT EDIT") self.write_line(f"// based on {device.name} version {device.version}") - self.write_line("const mmio = @import(\"microzig-mmio\").mmio;") + + self.write_line("const microzig_mmio = @import(\"microzig-mmio\");") + self.write_line("const mmio = microzig_mmio.mmio;") + self.write_line("const MMIO = microzig_mmio.MMIO;") self.write_line(f"const Name = \"{device.name}\";") interrupts = {} for peripheral in device.peripherals: - self.generate_peripherial_declaration(peripheral) + self.generate_peripheral_declaration(peripheral) if peripheral.interrupts != None: for interrupt in peripheral.interrupts: if interrupt.value in interrupts and interrupts[interrupt.value].description != interrupt.description: @@ -262,16 +403,8 @@ def main(): parser = SVDParser.for_packaged_svd(sys.argv[1], sys.argv[2] + '.svd') device = parser.get_device() - zig_fmt = subprocess.Popen(('zig', 'fmt', '--stdin'), stdin=subprocess.PIPE, - stdout=subprocess.PIPE, encoding='utf8') - - generator = MMIOFileGenerator(zig_fmt.stdin) + generator = MMIOFileGenerator(sys.stdout) generator.generate_file(device) - zig_fmt.stdin.flush() - zig_fmt.stdin.close() - print(zig_fmt.stdout.read()) - - if __name__ == "__main__": main() From 13f0a1e347f73aa782a7a6385d3aef7f1a3f1b63 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 2 Mar 2022 22:37:52 -0800 Subject: [PATCH 029/138] instantiate vector table in start.zig (#22) --- src/core/start.zig | 51 ++++++++++++++++++++++ src/modules/chips/lpc1768/lpc1768.zig | 2 +- src/modules/chips/lpc1768/registers.zig | 52 ----------------------- src/modules/chips/nrf52/nrf52.zig | 1 + src/modules/chips/stm32f103/stm32f103.zig | 3 +- src/modules/chips/stm32f303/stm32f303.zig | 1 + tests/interrupt.zig | 3 +- 7 files changed, 57 insertions(+), 56 deletions(-) diff --git a/src/core/start.zig b/src/core/start.zig index b84c395..27242c6 100644 --- a/src/core/start.zig +++ b/src/core/start.zig @@ -4,6 +4,57 @@ const microzig = @import("microzig"); pub usingnamespace app; +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +const VectorTable = microzig.chip.VectorTable; +export const vector_table: VectorTable linksection("microzig_flash_start") = blk: { + var tmp: microzig.chip.VectorTable = .{}; + if (@hasDecl(app, "interrupts")) { + if (@typeInfo(app.interrupts) != .Struct) + @compileLog("root.interrupts must be a struct"); + + inline for (@typeInfo(app.interrupts).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(app.interrupts, decl.name))).Fn.calling_convention; + const handler = @field(app.interrupts, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(tmp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk tmp; +}; + /// This is the logical entry point for microzig. /// It will invoke the main function from the root source file /// and provides error return handling as well as a event loop if requested. diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 9341851..edf8614 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -3,7 +3,7 @@ const micro = @import("microzig"); pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); - +pub const VectorTable = registers.VectorTable; pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 436e99e..e0d36c5 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -21798,55 +21798,3 @@ pub const VectorTable = extern struct { USBActivity: InterruptVector = makeUnhandledHandler("USBActivity"), CANActivity: InterruptVector = makeUnhandledHandler("CANActivity"), }; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); -} - -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; - } - } - break :blk temp; -}; - diff --git a/src/modules/chips/nrf52/nrf52.zig b/src/modules/chips/nrf52/nrf52.zig index 5ae1cd3..f9865cd 100644 --- a/src/modules/chips/nrf52/nrf52.zig +++ b/src/modules/chips/nrf52/nrf52.zig @@ -1,2 +1,3 @@ pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); +pub const VectorTable = registers.VectorTable; diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig index 6ede441..f9865cd 100644 --- a/src/modules/chips/stm32f103/stm32f103.zig +++ b/src/modules/chips/stm32f103/stm32f103.zig @@ -1,4 +1,3 @@ -const std = @import("std"); - pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); +pub const VectorTable = registers.VectorTable; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 9c13c60..4fb8ca0 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -3,6 +3,7 @@ const micro = @import("microzig"); pub const cpu = @import("cpu"); pub const registers = @import("registers.zig"); +pub const VectorTable = registers.VectorTable; pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; diff --git a/tests/interrupt.zig b/tests/interrupt.zig index 73dd4ea..f16fdd8 100644 --- a/tests/interrupt.zig +++ b/tests/interrupt.zig @@ -5,7 +5,8 @@ const micro = @import("microzig"); // right now. pub const panic = micro.panic; -pub const vector_table = struct { + +pub const interrupts = struct { pub fn SysTick() void { @panic("hit systick!"); } From 74e22672d0be099e2e3fa3182b47059e3baf035e Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 3 Mar 2022 06:02:10 -0800 Subject: [PATCH 030/138] use register code generated by regz (#23) --- src/core/start.zig | 4 +- src/modules/chips/lpc1768/lpc1768.zig | 102 +- src/modules/chips/lpc1768/registers.zig | 40579 ++++++------- src/modules/chips/nrf52/registers.zig | 37659 +++++------- src/modules/chips/stm32f103/registers.zig | 46002 +++++++------- src/modules/chips/stm32f103/stm32f103.zig | 3 +- src/modules/chips/stm32f303/registers.zig | 63836 +++++++++++--------- src/modules/chips/stm32f303/stm32f303.zig | 13 +- tests/uart-sync.zig | 18 +- 9 files changed, 93419 insertions(+), 94797 deletions(-) diff --git a/src/core/start.zig b/src/core/start.zig index 27242c6..73f33da 100644 --- a/src/core/start.zig +++ b/src/core/start.zig @@ -12,7 +12,9 @@ fn isValidField(field_name: []const u8) bool { const VectorTable = microzig.chip.VectorTable; export const vector_table: VectorTable linksection("microzig_flash_start") = blk: { - var tmp: microzig.chip.VectorTable = .{}; + var tmp: microzig.chip.VectorTable = .{ + .initial_stack_pointer = microzig.config.end_of_stack, + }; if (@hasDecl(app, "interrupts")) { if (@typeInfo(app.interrupts) != .Struct) @compileLog("root.interrupts must be a struct"); diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index edf8614..907b7c9 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -1,9 +1,11 @@ const std = @import("std"); const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, @@ -26,14 +28,14 @@ pub fn parsePin(comptime spec: []const u8) type { const _regs = struct { const name_suffix = std.fmt.comptimePrint("{d}", .{_port}); - const pinsel_reg = @field(registers.PINCONNECT, sel_reg_name); + const pinsel_reg = @field(regs.PINCONNECT, sel_reg_name); const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin }); - const dir = @field(registers.GPIO, "DIR" ++ name_suffix); - const pin = @field(registers.GPIO, "PIN" ++ name_suffix); - const set = @field(registers.GPIO, "SET" ++ name_suffix); - const clr = @field(registers.GPIO, "CLR" ++ name_suffix); - const mask = @field(registers.GPIO, "MASK" ++ name_suffix); + const dir = @field(regs.GPIO, "DIR" ++ name_suffix); + const pin = @field(regs.GPIO, "PIN" ++ name_suffix); + const set = @field(regs.GPIO, "SET" ++ name_suffix); + const clr = @field(regs.GPIO, "CLR" ++ name_suffix); + const mask = @field(regs.GPIO, "MASK" ++ name_suffix); }; return struct { @@ -48,7 +50,7 @@ pub fn parsePin(comptime spec: []const u8) type { pub fn routePin(comptime pin: type, function: PinTarget) void { var val = pin.regs.pinsel_reg.read(); - @field(val, pin.regs.pinsel_field) = @intToEnum(@TypeOf(@field(val, pin.regs.pinsel_field)), @enumToInt(function)); + @field(val, pin.regs.pinsel_field) = @enumToInt(function); pin.regs.pinsel_reg.write(val); } @@ -77,36 +79,40 @@ pub const gpio = struct { }; pub const uart = struct { - const RegisterDataBitsEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .WLS).field_type; pub const DataBits = enum(u2) { - five = @enumToInt(RegisterDataBitsEnum.@"5_BIT_CHARACTER_LENG"), - six = @enumToInt(RegisterDataBitsEnum.@"6_BIT_CHARACTER_LENG"), - seven = @enumToInt(RegisterDataBitsEnum.@"7_BIT_CHARACTER_LENG"), - eight = @enumToInt(RegisterDataBitsEnum.@"8_BIT_CHARACTER_LENG"), + five = 0, + six = 1, + seven = 2, + eight = 3, }; - const RegisterStopBitEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .SBS).field_type; pub const StopBits = enum(u1) { - one = @enumToInt(RegisterStopBitEnum.@"1_STOP_BIT_"), - two = @enumToInt(RegisterStopBitEnum.@"2_STOP_BITS_1_5_IF_"), + one = 0, + two = 1, }; - const RegisterParityEnum = std.meta.fieldInfo(@TypeOf(registers.UART0.LCR.*).underlying_type, .PS).field_type; pub const Parity = enum(u2) { - odd = @enumToInt(RegisterParityEnum.@"ODD_PARITY_NUMBER_O"), - even = @enumToInt(RegisterParityEnum.@"EVEN_PARITY_NUMBER_"), - mark = @enumToInt(RegisterParityEnum.@"FORCED_1_STICK_PARIT"), - space = @enumToInt(RegisterParityEnum.@"FORCED_0_STICK_PARIT"), + odd = 0, + even = 1, + mark = 2, + space = 3, + }; + + pub const CClkDiv = enum(u2) { + four = 0, + one = 1, + two = 2, + eight = 3, }; }; pub fn Uart(comptime index: usize) type { return struct { const UARTn = switch (index) { - 0 => registers.UART0, - 1 => registers.UART1, - 2 => registers.UART2, - 3 => registers.UART3, + 0 => regs.UART0, + 1 => regs.UART1, + 2 => regs.UART2, + 3 => regs.UART3, else => @compileError("LPC1768 has 4 UARTs available."), }; const Self = @This(); @@ -115,33 +121,33 @@ pub fn Uart(comptime index: usize) type { micro.debug.write("0"); switch (index) { 0 => { - registers.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) }); }, 1 => { - registers.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) }); }, 2 => { - registers.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) }); }, 3 => { - registers.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); - registers.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = .CCLK_DIV_4 }); + regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); + regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) }); }, else => unreachable, } micro.debug.write("1"); - UARTn.LCR.write(.{ + UARTn.LCR.modify(.{ // 8N1 - .WLS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .WLS).field_type, @enumToInt(config.data_bits)), - .SBS = @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .SBS).field_type, @enumToInt(config.stop_bits)), - .PE = if (config.parity) |_| .ENABLE_PARITY_GENERA else .DISABLE_PARITY_GENER, - .PS = if (config.parity) |p| @intToEnum(std.meta.fieldInfo(@TypeOf(UARTn.LCR.*).underlying_type, .PS).field_type, @enumToInt(p)) else .ODD_PARITY_NUMBER_O, - .BC = .DISABLE_BREAK_TRANSM, - .DLAB = .ENABLE_ACCESS_TO_DIV, + .WLS = @enumToInt(config.data_bits), + .SBS = @enumToInt(config.stop_bits), + .PE = if (config.parity) |_| @as(u1, 0) else @as(u1, 1), + .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd), + .BC = 0, + .DLAB = 1, }); micro.debug.write("2"); @@ -158,10 +164,10 @@ pub fn Uart(comptime index: usize) type { const regval = std.math.cast(u16, divider) catch return error.UnsupportedBaudRate; - UARTn.DLL.write(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); - UARTn.DLM.write(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); + UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); + UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); - UARTn.LCR.modify(.{ .DLAB = .DISABLE_ACCESS_TO_DI }); + UARTn.LCR.modify(.{ .DLAB = 0 }); return Self{}; } @@ -169,8 +175,8 @@ pub fn Uart(comptime index: usize) type { pub fn canWrite(self: Self) bool { _ = self; return switch (UARTn.LSR.read().THRE) { - .VALID => true, - .THR_IS_EMPTY_ => false, + 0 => true, // valid + 1 => false, // is empty }; } pub fn tx(self: Self, ch: u8) void { @@ -181,8 +187,8 @@ pub fn Uart(comptime index: usize) type { pub fn canRead(self: Self) bool { _ = self; return switch (UARTn.LSR.read().RDR) { - .EMPTY => false, - .NOTEMPTY => true, + 0 => false, // empty + 1 => true, // not empty }; } pub fn rx(self: Self) u8 { diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index e0d36c5..160617f 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -1,21800 +1,18801 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on LPC176x5x version 0.2 -const mmio = @import("microzig-mmio").mmio; -const Name = "LPC176x5x"; -pub const WDT = extern struct { - pub const Address: u32 = 0x40000000; - // byte offset: 0 Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - WDEN: enum(u1) { // bit offset: 0 desc: Watchdog enable bit. This bit is Set Only. - @"STOP" = 0, // desc: The watchdog timer is stopped. - @"RUN" = 1, // desc: The watchdog timer is running. - }, - WDRESET: enum(u1) { // bit offset: 1 desc: Watchdog reset enable bit. This bit is Set Only. See Table 652. - @"NORESET" = 0, // desc: A watchdog timeout will not cause a chip reset. - @"RESET" = 1, // desc: A watchdog timeout will cause a chip reset. - }, - WDTOF: u1, // bit offset: 2 desc: Watchdog time-out flag. Set when the watchdog timer times out, cleared by software. - WDINT: u1, // bit offset: 3 desc: Watchdog interrupt flag. Cleared by software. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Watchdog timer constant register. The value in this register determines the time-out value. - pub const TC = mmio(Address + 0x00000004, 32, packed struct { - Count: u32, // bit offset: 0 desc: Watchdog time-out interval. - }); - // byte offset: 8 Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. - pub const FEED = mmio(Address + 0x00000008, 32, packed struct { - Feed: u8, // bit offset: 0 desc: Feed value should be 0xAA followed by 0x55. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Watchdog timer value register. This register reads out the current value of the Watchdog timer. - pub const TV = mmio(Address + 0x0000000c, 32, packed struct { - Count: u32, // bit offset: 0 desc: Counter timer value. - }); - // byte offset: 16 Watchdog clock select register. - pub const CLKSEL = mmio(Address + 0x00000010, 32, packed struct { - CLKSEL: enum(u2) { // bit offset: 0 desc: Selects source of WDT clock - @"IRC" = 0, // desc: IRC - @"PCLK" = 1, // desc: Peripheral clock - @"RTCOSC" = 2, // desc: RTC oscillator - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - // RESERVED: u30, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - LOCK: enum(u1) { // bit offset: 31 desc: If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. - @"UNLOCKED" = 0, // desc: This bit is set to 0 on any reset. It cannot be cleared by software. - @"LOCKED" = 1, // desc: Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified. - }, - }); -}; -pub const TIMER0 = extern struct { - pub const Address: u32 = 0x40004000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER1 = extern struct { - pub const Address: u32 = 0x40008000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART0 = extern struct { - pub const Address: u32 = 0x4000c000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART1 = extern struct { - pub const Address: u32 = 0x40010000; - // byte offset: 0 DLAB =0 Receiver Buffer Register. Contains the next received character to be read. - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - MSIE: enum(u1) { // bit offset: 3 desc: Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. - @"DISABLE_THE_MODEM_IN" = 0, // desc: Disable the modem interrupt. - @"ENABLE_THE_MODEM_INT" = 1, // desc: Enable the modem interrupt. - }, - // RESERVED: u3, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CTSIE: enum(u1) { // bit offset: 7 desc: CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. - @"DISABLE_THE_CTS_INTE" = 0, // desc: Disable the CTS interrupt. - @"ENABLE_THE_CTS_INTER" = 1, // desc: Enable the CTS interrupt. - }, - ABEOIE: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOIE: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). - @"RLS" = 3, // desc: 1 - Receive Line Status (RLS). - @"RDA" = 2, // desc: 2a - Receive Data Available (RDA). - @"CTI" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"THRE" = 1, // desc: 3 - THRE Interrupt. - @"MODEM" = 0, // desc: 4 - Modem Interrupt. - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of FCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART1 FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO enable. - @"MUST_NOT_BE_USED_IN_" = 0, // desc: Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UART1 FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length. - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length. - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length. - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length. - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select. - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if LCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select. - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED1STICK_PAR" = 2, // desc: Forced 1 stick parity. - @"FORCED0STICK_PAR" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control. - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit (DLAB) - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Modem Control Register. Contains controls for flow control handshaking and loopback mode. - pub const MCR = mmio(Address + 0x00000010, 32, packed struct { - DTRCTRL: u1, // bit offset: 0 desc: DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. - RTSCTRL: u1, // bit offset: 1 desc: RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. - // RESERVED: u2, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - LMS: enum(u1) { // bit offset: 4 desc: Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. - @"DISABLE_MODEM_LOOPBA" = 0, // desc: Disable modem loopback mode. - @"ENABLE_MODEM_LOOPBAC" = 1, // desc: Enable modem loopback mode. - }, - // RESERVED: u1, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - RTSEN: enum(u1) { // bit offset: 6 desc: RTS enable. - @"DISABLE_AUTO_RTS_FLO" = 0, // desc: Disable auto-rts flow control. - @"ENABLE_AUTO_RTS_FLOW" = 1, // desc: Enable auto-rts flow control. - }, - CTSEN: enum(u1) { // bit offset: 7 desc: CTS enable. - @"DISABLE_AUTO_CTS_FLO" = 0, // desc: Disable auto-cts flow control. - @"ENABLE_AUTO_CTS_FLOW" = 1, // desc: Enable auto-cts flow control. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UART1 receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UART1 receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. - @"VALID" = 0, // desc: THR contains valid data. - @"THR_IS_EMPTY_" = 1, // desc: THR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. - @"VALID" = 0, // desc: THR and/or the TSR contains valid data. - @"EMPTY" = 1, // desc: THR and the TSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. - @"NOERROR" = 0, // desc: RBR contains no UART1 RX errors or FCR[0]=0. - @"ERRORS" = 1, // desc: UART1 RBR contains at least one UART1 RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Modem Status Register. Contains handshake signal status flags. - pub const MSR = mmio(Address + 0x00000018, 32, packed struct { - DCTS: enum(u1) { // bit offset: 0 desc: Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, CTS. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, CTS. - }, - DDSR: enum(u1) { // bit offset: 1 desc: Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DSR. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DSR. - }, - TERI: enum(u1) { // bit offset: 2 desc: Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, RI. - @"LOW_TO_HIGH_TRANSITI" = 1, // desc: Low-to-high transition detected on RI. - }, - DDCD: enum(u1) { // bit offset: 3 desc: Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. - @"NO_CHANGE_DETECTED_O" = 0, // desc: No change detected on modem input, DCD. - @"STATE_CHANGE_DETECTE" = 1, // desc: State change detected on modem input, DCD. - }, - CTS: u1, // bit offset: 4 desc: Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. - DSR: u1, // bit offset: 5 desc: Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. - RI: u1, // bit offset: 6 desc: Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. - DCD: u1, // bit offset: 7 desc: Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - Pad: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Auto-baud start bit. This bit is automatically cleared after auto-baud completion. - @"STOP" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"START" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Auto-baud restart bit. - @"NO_RESTART" = 0, // desc: No restart - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UART1 Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only). - @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. - @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only). - @"WRITING_A_0_HAS_NO_I" = 0, // desc: Writing a 0 has no impact. - @"WRITING_A_1_WILL_CLE" = 1, // desc: Writing a 1 will clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate. - MULVAL: u4, // bit offset: 4 desc: Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_IN_THIS_MOD" = 1, // desc: Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receive enable. - @"ENABLED_" = 0, // desc: Enabled. - @"DISABLED_" = 1, // desc: Disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: Auto Address Detect (AAD) enable. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - SEL: enum(u1) { // bit offset: 3 desc: Direction control. - @"RTS_IF_DIRECTION_CO" = 0, // desc: RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. - @"DTR_IF_DIRECTION_CO" = 1, // desc: DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. - }, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. - @"LOW_THE_DIRECTION_C" = 0, // desc: LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"HIGH_THE_DIRECTION_" = 1, // desc: HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const PWM1 = extern struct { - pub const Address: u32 = 0x40018000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - PWMMR0INT: u1, // bit offset: 0 desc: Interrupt flag for PWM match channel 0. - PWMMR1INT: u1, // bit offset: 1 desc: Interrupt flag for PWM match channel 1. - PWMMR2INT: u1, // bit offset: 2 desc: Interrupt flag for PWM match channel 2. - PWMMR3INT: u1, // bit offset: 3 desc: Interrupt flag for PWM match channel 3. - PWMCAP0INT: u1, // bit offset: 4 desc: Interrupt flag for capture input 0 - PWMCAP1INT: u1, // bit offset: 5 desc: Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). - // RESERVED: u2, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMMR4INT: u1, // bit offset: 8 desc: Interrupt flag for PWM match channel 4. - PWMMR5INT: u1, // bit offset: 9 desc: Interrupt flag for PWM match channel 5. - PWMMR6INT: u1, // bit offset: 10 desc: Interrupt flag for PWM match channel 6. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CE: enum(u1) { // bit offset: 0 desc: Counter Enable - @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and PWM Prescale Counter are enabled for counting. - @"THE_COUNTERS_ARE_DIS" = 0, // desc: The counters are disabled. - }, - CR: enum(u1) { // bit offset: 1 desc: Counter Reset - @"THE_PWM_TIMER_COUNTE" = 1, // desc: The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. - @"CLEAR_RESET_" = 0, // desc: Clear reset. - }, - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - PWMEN: enum(u1) { // bit offset: 3 desc: PWM Enable - @"PWM_MODE_IS_ENABLED_" = 1, // desc: PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. - @"TIMER_MODE_IS_ENABLE" = 0, // desc: Timer mode is enabled (counter resets to 0). - }, - MDIS: enum(u1) { // bit offset: 4 desc: Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). - @"MASTER_USE_PWM0_IS_" = 1, // desc: Master use. PWM0 is the master, and both PWMs are enabled for counting. - @"INDIVIDUAL_USE_THE_" = 0, // desc: Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. Determines how often the PWM counter is incremented. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. Prescaler for the main PWM counter. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - PWMMR0I: enum(u1) { // bit offset: 0 desc: Interrupt PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR0" = 1, // desc: Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC. - }, - PWMMR0R: enum(u1) { // bit offset: 1 desc: Reset PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR0_THE" = 1, // desc: Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. - }, - PWMMR0S: enum(u1) { // bit offset: 2 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR0_THE_" = 1, // desc: Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR1I: enum(u1) { // bit offset: 3 desc: Interrupt PWM1 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR1" = 1, // desc: Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. - }, - PWMMR1R: enum(u1) { // bit offset: 4 desc: Reset PWM1 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR1_THE" = 1, // desc: Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. - }, - PWMMR1S: enum(u1) { // bit offset: 5 desc: Stop PWM1 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR1_THE_" = 1, // desc: Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC. - }, - PWMMR2I: enum(u1) { // bit offset: 6 desc: Interrupt PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR2" = 1, // desc: Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC. - }, - PWMMR2R: enum(u1) { // bit offset: 7 desc: Reset PWM0 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR2_THE" = 1, // desc: Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. - }, - PWMMR2S: enum(u1) { // bit offset: 8 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR2_THE_" = 1, // desc: Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR3I: enum(u1) { // bit offset: 9 desc: Interrupt PWM3 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR3" = 1, // desc: Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC. - }, - PWMMR3R: enum(u1) { // bit offset: 10 desc: Reset PWM3 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR3_THE" = 1, // desc: Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. - }, - PWMMR3S: enum(u1) { // bit offset: 11 desc: Stop PWM0 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR3_THE_" = 1, // desc: Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. - }, - PWMMR4I: enum(u1) { // bit offset: 12 desc: Interrupt PWM4 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR4" = 1, // desc: Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC. - }, - PWMMR4R: enum(u1) { // bit offset: 13 desc: Reset PWM4 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR4_THE" = 1, // desc: Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. - }, - PWMMR4S: enum(u1) { // bit offset: 14 desc: Stop PWM4 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR4_THE_" = 1, // desc: Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC. - }, - PWMMR5I: enum(u1) { // bit offset: 15 desc: Interrupt PWM5 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR5" = 1, // desc: Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC. - }, - PWMMR5R: enum(u1) { // bit offset: 16 desc: Reset PWM5 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR5_THE" = 1, // desc: Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. - }, - PWMMR5S: enum(u1) { // bit offset: 17 desc: Stop PWM5 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR5_THE_" = 1, // desc: Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC. - }, - PWMMR6I: enum(u1) { // bit offset: 18 desc: Interrupt PWM6 - @"DISABLED_" = 0, // desc: Disabled. - @"INTERRUPT_ON_PWMMR6" = 1, // desc: Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC. - }, - PWMMR6R: enum(u1) { // bit offset: 19 desc: Reset PWM6 - @"DISABLED_" = 0, // desc: Disabled. - @"RESET_ON_PWMMR6_THE" = 1, // desc: Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. - }, - PWMMR6S: enum(u1) { // bit offset: 20 desc: Stop PWM6 - @"DISABLED" = 0, // desc: Disabled - @"STOP_ON_PWMMR6_THE_" = 1, // desc: Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC. - }, - // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0_R: enum(u1) { // bit offset: 0 desc: Capture on PWMn_CAP0 rising edge - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC. - }, - CAP0_F: enum(u1) { // bit offset: 1 desc: Capture on PWMn_CAP0 falling edge - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC. - }, - CAP0_I: enum(u1) { // bit offset: 2 desc: Interrupt on PWMn_CAP0 event - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"INTERRUPT_A_CR0_LOA" = 1, // desc: Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt. - }, - CAP1_R: enum(u1) { // bit offset: 3 desc: Capture on PWMn_CAP1 rising edge. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"RISING_EDGE_A_SYNCH" = 1, // desc: Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC. - }, - CAP1_F: enum(u1) { // bit offset: 4 desc: Capture on PWMn_CAP1 falling edge. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"FALLING_EDGE_A_SYNC" = 1, // desc: Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC. - }, - CAP1_I: enum(u1) { // bit offset: 5 desc: Interrupt on PWMn_CAP1 event. Reserved for PWM0. - @"DISABLED_THIS_FEATU" = 0, // desc: Disabled. This feature is disabled. - @"INTERRUPT_A_CR1_LOA" = 1, // desc: Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR4 = mmio(Address + 0x00000040, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 68 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR5 = mmio(Address + 0x00000044, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 72 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. - pub const MR6 = mmio(Address + 0x00000048, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 76 PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. - pub const PCR = mmio(Address + 0x0000004c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PWMSEL2: enum(u1) { // bit offset: 2 desc: PWM[2] output single/double edge mode control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL3: enum(u1) { // bit offset: 3 desc: PWM[3] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL4: enum(u1) { // bit offset: 4 desc: PWM[4] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL5: enum(u1) { // bit offset: 5 desc: PWM[5] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - PWMSEL6: enum(u1) { // bit offset: 6 desc: PWM[6] output edge control. - @"SINGLE_EDGE_CONTROLL" = 0, // desc: Single edge controlled mode is selected. - @"DOUBLE_EDGE_CONTROLL" = 1, // desc: Double edge controlled mode is selected. - }, - // RESERVED: u2, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - PWMENA1: enum(u1) { // bit offset: 9 desc: PWM[1] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA2: enum(u1) { // bit offset: 10 desc: PWM[2] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA3: enum(u1) { // bit offset: 11 desc: PWM[3] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA4: enum(u1) { // bit offset: 12 desc: PWM[4] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA5: enum(u1) { // bit offset: 13 desc: PWM[5] output enable control. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - PWMENA6: enum(u1) { // bit offset: 14 desc: PWM[6] output enable control. See PWMENA1 for details. - @"THE_PWM_OUTPUT_IS_DI" = 0, // desc: The PWM output is disabled. - @"THE_PWM_OUTPUT_IS_EN" = 1, // desc: The PWM output is enabled. - }, - // RESERVED: u17, // bit offset: 15 desc: Unused, always zero. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 Load Enable Register. Enables use of updated PWM match values. - pub const LER = mmio(Address + 0x00000050, 32, packed struct { - MAT0LATCHEN: u1, // bit offset: 0 desc: Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. - MAT1LATCHEN: u1, // bit offset: 1 desc: Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. - MAT2LATCHEN: u1, // bit offset: 2 desc: Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. - MAT3LATCHEN: u1, // bit offset: 3 desc: Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. - MAT4LATCHEN: u1, // bit offset: 4 desc: Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. - MAT5LATCHEN: u1, // bit offset: 5 desc: Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. - MAT6LATCHEN: u1, // bit offset: 6 desc: Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - MOD: enum(u2) { // bit offset: 0 desc: Counter/ Timer Mode - @"TIMER_MODE_THE_TC_I" = 0, // desc: Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register. - @"RISING_EDGE_COUNTER_" = 1, // desc: Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2. - @"FALLING_EDGE_COUNTER" = 2, // desc: Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2. - @"DUAL_EDGE_COUNTER_MO" = 3, // desc: Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2. - }, - CIS: enum(u2) { // bit offset: 2 desc: Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. - @"FOR_PWM0_00_EQ_PWM0_" = 0, // desc: For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved) - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2C0 = extern struct { - pub const Address: u32 = 0x4001c000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SPI = extern struct { - pub const Address: u32 = 0x40020000; - // byte offset: 0 SPI Control Register. This register controls the operation of the SPI. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - BITENABLE: enum(u1) { // bit offset: 2 desc: The SPI controller sends and receives 8 bits of data per transfer. - @"THE_SPI_CONTROLLER_S" = 1, // desc: The SPI controller sends and receives the number of bits selected by bits 11:8. - _, // non-exhaustive - }, - CPHA: enum(u1) { // bit offset: 3 desc: Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. - @"FIRST_EDGE" = 0, // desc: Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. - @"SECOND_EDGE" = 1, // desc: Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. - }, - CPOL: enum(u1) { // bit offset: 4 desc: Clock polarity control. - @"SCK_IS_ACTIVE_HIGH_" = 0, // desc: SCK is active high. - @"SCK_IS_ACTIVE_LOW_" = 1, // desc: SCK is active low. - }, - MSTR: enum(u1) { // bit offset: 5 desc: Master mode select. - @"SLAVE" = 0, // desc: The SPI operates in Slave mode. - @"MASTER" = 1, // desc: The SPI operates in Master mode. - }, - LSBF: enum(u1) { // bit offset: 6 desc: LSB First controls which direction each byte is shifted when transferred. - @"MSB" = 0, // desc: SPI data is transferred MSB (bit 7) first. - @"LSB" = 1, // desc: SPI data is transferred LSB (bit 0) first. - }, - SPIE: enum(u1) { // bit offset: 7 desc: Serial peripheral interrupt enable. - @"INTBLOCK" = 0, // desc: SPI interrupts are inhibited. - @"HWINT" = 1, // desc: A hardware interrupt is generated each time the SPIF or MODF bits are activated. - }, - BITS: enum(u4) { // bit offset: 8 desc: When bit 2 of this register is 1, this field controls the number of bits per transfer: - @"8_BITS_PER_TRANSFER" = 8, // desc: 8 bits per transfer - @"9_BITS_PER_TRANSFER" = 9, // desc: 9 bits per transfer - @"10_BITS_PER_TRANSFER" = 10, // desc: 10 bits per transfer - @"11_BITS_PER_TRANSFER" = 11, // desc: 11 bits per transfer - @"12_BITS_PER_TRANSFER" = 12, // desc: 12 bits per transfer - @"13_BITS_PER_TRANSFER" = 13, // desc: 13 bits per transfer - @"14_BITS_PER_TRANSFER" = 14, // desc: 14 bits per transfer - @"15_BITS_PER_TRANSFER" = 15, // desc: 15 bits per transfer - @"16_BITS_PER_TRANSFER" = 0, // desc: 16 bits per transfer - _, // non-exhaustive - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 SPI Status Register. This register shows the status of the SPI. - pub const SR = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABRT: u1, // bit offset: 3 desc: Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. - MODF: u1, // bit offset: 4 desc: Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. - ROVR: u1, // bit offset: 5 desc: Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. - WCOL: u1, // bit offset: 6 desc: Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. - SPIF: u1, // bit offset: 7 desc: SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATALOW: u8, // bit offset: 0 desc: SPI Bi-directional data port. - DATAHIGH: u8, // bit offset: 8 desc: If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 SPI Clock Counter Register. This register controls the frequency of a master's SCK0. - pub const CCR = mmio(Address + 0x0000000c, 32, packed struct { - COUNTER: u8, // bit offset: 0 desc: SPI0 Clock counter setting. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. - pub const INT = mmio(Address + 0x0000001c, 32, packed struct { - SPIF: u1, // bit offset: 0 desc: SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. - // RESERVED: u7, // bit offset: 1 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const RTC = extern struct { - pub const Address: u32 = 0x40024000; - // byte offset: 0 Interrupt Location Register - pub const ILR = mmio(Address + 0x00000000, 32, packed struct { - RTCCIF: u1, // bit offset: 0 desc: When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. - RTCALF: u1, // bit offset: 1 desc: When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. - // RESERVED: u11, // bit offset: 21 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Clock Control Register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - CLKEN: enum(u1) { // bit offset: 0 desc: Clock Enable. - @"THE_TIME_COUNTERS_AR" = 1, // desc: The time counters are enabled. - @"THE_TIME_COUNTERS_AR" = 0, // desc: The time counters are disabled so that they may be initialized. - }, - CTCRST: enum(u1) { // bit offset: 1 desc: CTC Reset. - @"RESET" = 1, // desc: When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. - @"NO_EFFECT_" = 0, // desc: No effect. - }, - // RESERVED: u2, // bit offset: 2 desc: Internal test mode controls. These bits must be 0 for normal RTC operation. - reserved2: u1 = 0, - reserved1: u1 = 0, - CCALEN: enum(u1) { // bit offset: 4 desc: Calibration counter enable. - @"THE_CALIBRATION_COUN" = 1, // desc: The calibration counter is disabled and reset to zero. - @"THE_CALIBRATION_COUN" = 0, // desc: The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Counter Increment Interrupt Register - pub const CIIR = mmio(Address + 0x0000000c, 32, packed struct { - IMSEC: u1, // bit offset: 0 desc: When 1, an increment of the Second value generates an interrupt. - IMMIN: u1, // bit offset: 1 desc: When 1, an increment of the Minute value generates an interrupt. - IMHOUR: u1, // bit offset: 2 desc: When 1, an increment of the Hour value generates an interrupt. - IMDOM: u1, // bit offset: 3 desc: When 1, an increment of the Day of Month value generates an interrupt. - IMDOW: u1, // bit offset: 4 desc: When 1, an increment of the Day of Week value generates an interrupt. - IMDOY: u1, // bit offset: 5 desc: When 1, an increment of the Day of Year value generates an interrupt. - IMMON: u1, // bit offset: 6 desc: When 1, an increment of the Month value generates an interrupt. - IMYEAR: u1, // bit offset: 7 desc: When 1, an increment of the Year value generates an interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Alarm Mask Register - pub const AMR = mmio(Address + 0x00000010, 32, packed struct { - AMRSEC: u1, // bit offset: 0 desc: When 1, the Second value is not compared for the alarm. - AMRMIN: u1, // bit offset: 1 desc: When 1, the Minutes value is not compared for the alarm. - AMRHOUR: u1, // bit offset: 2 desc: When 1, the Hour value is not compared for the alarm. - AMRDOM: u1, // bit offset: 3 desc: When 1, the Day of Month value is not compared for the alarm. - AMRDOW: u1, // bit offset: 4 desc: When 1, the Day of Week value is not compared for the alarm. - AMRDOY: u1, // bit offset: 5 desc: When 1, the Day of Year value is not compared for the alarm. - AMRMON: u1, // bit offset: 6 desc: When 1, the Month value is not compared for the alarm. - AMRYEAR: u1, // bit offset: 7 desc: When 1, the Year value is not compared for the alarm. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Consolidated Time Register 0 - pub const CTIME0 = mmio(Address + 0x00000014, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u2, // bit offset: 6 desc: Reserved. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - MINUTES: u6, // bit offset: 8 desc: Minutes value in the range of 0 to 59 - // RESERVED: u2, // bit offset: 14 desc: Reserved. The value read from a reserved bit is not defined. - reserved4: u1 = 0, - reserved3: u1 = 0, - HOURS: u5, // bit offset: 16 desc: Hours value in the range of 0 to 23 - // RESERVED: u3, // bit offset: 21 desc: Reserved. The value read from a reserved bit is not defined. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - DOW: u3, // bit offset: 24 desc: Day of week value in the range of 0 to 6 - // RESERVED: u5, // bit offset: 27 desc: Reserved. The value read from a reserved bit is not defined. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Consolidated Time Register 1 - pub const CTIME1 = mmio(Address + 0x00000018, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u3, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MONTH: u4, // bit offset: 8 desc: Month value in the range of 1 to 12. - // RESERVED: u4, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - YEAR: u12, // bit offset: 16 desc: Year value in the range of 0 to 4095. - // RESERVED: u4, // bit offset: 28 desc: Reserved. The value read from a reserved bit is not defined. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Consolidated Time Register 2 - pub const CTIME2 = mmio(Address + 0x0000001c, 32, packed struct { - DOY: u12, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Seconds Counter - pub const SEC = mmio(Address + 0x00000020, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 Minutes Register - pub const MIN = mmio(Address + 0x00000024, 32, packed struct { - MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Hours Register - pub const HRS = mmio(Address + 0x00000028, 32, packed struct { - HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Day of Month Register - pub const DOM = mmio(Address + 0x0000002c, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Day of Week Register - pub const DOW = mmio(Address + 0x00000030, 32, packed struct { - DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. - // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 Day of Year Register - pub const DOY = mmio(Address + 0x00000034, 32, packed struct { - DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Months Register - pub const MONTH = mmio(Address + 0x00000038, 32, packed struct { - MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 Years Register - pub const YEAR = mmio(Address + 0x0000003c, 32, packed struct { - YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Calibration Value Register - pub const CALIBRATION = mmio(Address + 0x00000040, 32, packed struct { - CALVAL: u17, // bit offset: 0 desc: If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. - CALDIR: enum(u1) { // bit offset: 17 desc: Calibration direction - @"BACKWARD_CALIBRATION" = 1, // desc: Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. - @"FORWARD_CALIBRATION_" = 0, // desc: Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. - }, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 General Purpose Register 0 - pub const GPREG0 = mmio(Address + 0x00000044, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 72 General Purpose Register 0 - pub const GPREG1 = mmio(Address + 0x00000048, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 76 General Purpose Register 0 - pub const GPREG2 = mmio(Address + 0x0000004c, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 80 General Purpose Register 0 - pub const GPREG3 = mmio(Address + 0x00000050, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 84 General Purpose Register 0 - pub const GPREG4 = mmio(Address + 0x00000054, 32, packed struct { - GP: u32, // bit offset: 0 desc: General purpose storage. - }); - // byte offset: 88 RTC Auxiliary Enable register - pub const RTC_AUXEN = mmio(Address + 0x00000058, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RTC_OSCFEN: u1, // bit offset: 4 desc: Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 RTC Auxiliary control register - pub const RTC_AUX = mmio(Address + 0x0000005c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RTC_OSCF: u1, // bit offset: 4 desc: RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. - // RESERVED: u1, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - RTC_PDOUT: u1, // bit offset: 6 desc: When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 96 Alarm value for Seconds - pub const ASEC = mmio(Address + 0x00000060, 32, packed struct { - SECONDS: u6, // bit offset: 0 desc: Seconds value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 100 Alarm value for Minutes - pub const AMIN = mmio(Address + 0x00000064, 32, packed struct { - MINUTES: u6, // bit offset: 0 desc: Minutes value in the range of 0 to 59 - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 104 Alarm value for Hours - pub const AHRS = mmio(Address + 0x00000068, 32, packed struct { - HOURS: u5, // bit offset: 0 desc: Hours value in the range of 0 to 23 - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 108 Alarm value for Day of Month - pub const ADOM = mmio(Address + 0x0000006c, 32, packed struct { - DOM: u5, // bit offset: 0 desc: Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Alarm value for Day of Week - pub const ADOW = mmio(Address + 0x00000070, 32, packed struct { - DOW: u3, // bit offset: 0 desc: Day of week value in the range of 0 to 6. - // RESERVED: u29, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Alarm value for Day of Year - pub const ADOY = mmio(Address + 0x00000074, 32, packed struct { - DOY: u9, // bit offset: 0 desc: Day of year value in the range of 1 to 365 (366 for leap years). - // RESERVED: u23, // bit offset: 9 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 120 Alarm value for Months - pub const AMON = mmio(Address + 0x00000078, 32, packed struct { - MONTH: u4, // bit offset: 0 desc: Month value in the range of 1 to 12. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 124 Alarm value for Year - pub const AYRS = mmio(Address + 0x0000007c, 32, packed struct { - YEAR: u12, // bit offset: 0 desc: Year value in the range of 0 to 4095. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const GPIOINT = extern struct { - pub const Address: u32 = 0x40028080; - // byte offset: 0 GPIO overall Interrupt Status. - pub const STATUS = mmio(Address + 0x00000000, 32, packed struct { - P0INT: enum(u1) { // bit offset: 0 desc: Port 0 GPIO interrupt pending. - @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 0. - @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 0. - }, - // RESERVED: u1, // bit offset: 1 desc: Reserved. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - P2INT: enum(u1) { // bit offset: 2 desc: Port 2 GPIO interrupt pending. - @"NO_PENDING_INTERRUPT" = 0, // desc: No pending interrupts on Port 2. - @"AT_LEAST_ONE_PENDING" = 1, // desc: At least one pending interrupt on Port 2. - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR0 = mmio(Address + 0x00000004, 32, packed struct { - P0_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_14REI: u1, // bit offset: 14 desc: Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_15REI: u1, // bit offset: 15 desc: Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_16REI: u1, // bit offset: 16 desc: Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_17REI: u1, // bit offset: 17 desc: Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_18REI: u1, // bit offset: 18 desc: Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_19REI: u1, // bit offset: 19 desc: Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_20REI: u1, // bit offset: 20 desc: Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_21REI: u1, // bit offset: 21 desc: Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_22REI: u1, // bit offset: 22 desc: Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_23REI: u1, // bit offset: 23 desc: Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_24REI: u1, // bit offset: 24 desc: Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_25REI: u1, // bit offset: 25 desc: Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_26REI: u1, // bit offset: 26 desc: Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_27REI: u1, // bit offset: 27 desc: Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_28REI: u1, // bit offset: 28 desc: Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_29REI: u1, // bit offset: 29 desc: Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P0_30REI: u1, // bit offset: 30 desc: Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 8 GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF0 = mmio(Address + 0x00000008, 32, packed struct { - P0_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_14FEI: u1, // bit offset: 14 desc: Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_15FEI: u1, // bit offset: 15 desc: Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_16FEI: u1, // bit offset: 16 desc: Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_17FEI: u1, // bit offset: 17 desc: Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_18FEI: u1, // bit offset: 18 desc: Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_19FEI: u1, // bit offset: 19 desc: Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_20FEI: u1, // bit offset: 20 desc: Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_21FEI: u1, // bit offset: 21 desc: Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_22FEI: u1, // bit offset: 22 desc: Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_23FEI: u1, // bit offset: 23 desc: Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_24FEI: u1, // bit offset: 24 desc: Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_25FEI: u1, // bit offset: 25 desc: Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_26FEI: u1, // bit offset: 26 desc: Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_27FEI: u1, // bit offset: 27 desc: Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_28FEI: u1, // bit offset: 28 desc: Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_29FEI: u1, // bit offset: 29 desc: Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P0_30FEI: u1, // bit offset: 30 desc: Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 12 GPIO Interrupt Clear. - pub const CLR0 = mmio(Address + 0x0000000c, 32, packed struct { - P0_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_14CI: u1, // bit offset: 14 desc: Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_15CI: u1, // bit offset: 15 desc: Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_16CI: u1, // bit offset: 16 desc: Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_17CI: u1, // bit offset: 17 desc: Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_18CI: u1, // bit offset: 18 desc: Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_19CI: u1, // bit offset: 19 desc: Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_20CI: u1, // bit offset: 20 desc: Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_21CI: u1, // bit offset: 21 desc: Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_22CI: u1, // bit offset: 22 desc: Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_23CI: u1, // bit offset: 23 desc: Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_24CI: u1, // bit offset: 24 desc: Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_25CI: u1, // bit offset: 25 desc: Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_26CI: u1, // bit offset: 26 desc: Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_27CI: u1, // bit offset: 27 desc: Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_28CI: u1, // bit offset: 28 desc: Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_29CI: u1, // bit offset: 29 desc: Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P0_30CI: u1, // bit offset: 30 desc: Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 16 GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR0 = mmio(Address + 0x00000010, 32, packed struct { - P0_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_14ER: u1, // bit offset: 14 desc: Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_15ER: u1, // bit offset: 15 desc: Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_16ER: u1, // bit offset: 16 desc: Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_17ER: u1, // bit offset: 17 desc: Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_18ER: u1, // bit offset: 18 desc: Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_19ER: u1, // bit offset: 19 desc: Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_20ER: u1, // bit offset: 20 desc: Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_21ER: u1, // bit offset: 21 desc: Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_22ER: u1, // bit offset: 22 desc: Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_23ER: u1, // bit offset: 23 desc: Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_24ER: u1, // bit offset: 24 desc: Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_25ER: u1, // bit offset: 25 desc: Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_26ER: u1, // bit offset: 26 desc: Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_27ER: u1, // bit offset: 27 desc: Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_28ER: u1, // bit offset: 28 desc: Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_29ER: u1, // bit offset: 29 desc: Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P0_30ER: u1, // bit offset: 30 desc: Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 20 GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF0 = mmio(Address + 0x00000014, 32, packed struct { - P0_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_14EF: u1, // bit offset: 14 desc: Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_15EF: u1, // bit offset: 15 desc: Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_16EF: u1, // bit offset: 16 desc: Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_17EF: u1, // bit offset: 17 desc: Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_18EF: u1, // bit offset: 18 desc: Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_19EF: u1, // bit offset: 19 desc: Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_20EF: u1, // bit offset: 20 desc: Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_21EF: u1, // bit offset: 21 desc: Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_22EF: u1, // bit offset: 22 desc: Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_23EF: u1, // bit offset: 23 desc: Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_24EF: u1, // bit offset: 24 desc: Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_25EF: u1, // bit offset: 25 desc: Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_26EF: u1, // bit offset: 26 desc: Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_27EF: u1, // bit offset: 27 desc: Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_28EF: u1, // bit offset: 28 desc: Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_29EF: u1, // bit offset: 29 desc: Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P0_30EF: u1, // bit offset: 30 desc: Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 36 GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR2 = mmio(Address + 0x00000024, 32, packed struct { - P2_0REI: u1, // bit offset: 0 desc: Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_1REI: u1, // bit offset: 1 desc: Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_2REI: u1, // bit offset: 2 desc: Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_3REI: u1, // bit offset: 3 desc: Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_4REI: u1, // bit offset: 4 desc: Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_5REI: u1, // bit offset: 5 desc: Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_6REI: u1, // bit offset: 6 desc: Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_7REI: u1, // bit offset: 7 desc: Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_8REI: u1, // bit offset: 8 desc: Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_9REI: u1, // bit offset: 9 desc: Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_10REI: u1, // bit offset: 10 desc: Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_11REI: u1, // bit offset: 11 desc: Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_12REI: u1, // bit offset: 12 desc: Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - P2_13REI: u1, // bit offset: 13 desc: Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF2 = mmio(Address + 0x00000028, 32, packed struct { - P2_0FEI: u1, // bit offset: 0 desc: Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_1FEI: u1, // bit offset: 1 desc: Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_2FEI: u1, // bit offset: 2 desc: Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_3FEI: u1, // bit offset: 3 desc: Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_4FEI: u1, // bit offset: 4 desc: Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_5FEI: u1, // bit offset: 5 desc: Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_6FEI: u1, // bit offset: 6 desc: Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_7FEI: u1, // bit offset: 7 desc: Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_8FEI: u1, // bit offset: 8 desc: Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_9FEI: u1, // bit offset: 9 desc: Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_10FEI: u1, // bit offset: 10 desc: Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_11FEI: u1, // bit offset: 11 desc: Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_12FEI: u1, // bit offset: 12 desc: Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - P2_13FEI: u1, // bit offset: 13 desc: Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 GPIO Interrupt Clear. - pub const CLR2 = mmio(Address + 0x0000002c, 32, packed struct { - P2_0CI: u1, // bit offset: 0 desc: Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_1CI: u1, // bit offset: 1 desc: Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_2CI: u1, // bit offset: 2 desc: Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_3CI: u1, // bit offset: 3 desc: Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_4CI: u1, // bit offset: 4 desc: Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_5CI: u1, // bit offset: 5 desc: Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_6CI: u1, // bit offset: 6 desc: Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_7CI: u1, // bit offset: 7 desc: Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_8CI: u1, // bit offset: 8 desc: Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_9CI: u1, // bit offset: 9 desc: Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_10CI: u1, // bit offset: 10 desc: Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_11CI: u1, // bit offset: 11 desc: Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_12CI: u1, // bit offset: 12 desc: Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - P2_13CI: u1, // bit offset: 13 desc: Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR2 = mmio(Address + 0x00000030, 32, packed struct { - P2_0ER: u1, // bit offset: 0 desc: Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_1ER: u1, // bit offset: 1 desc: Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_2ER: u1, // bit offset: 2 desc: Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_3ER: u1, // bit offset: 3 desc: Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_4ER: u1, // bit offset: 4 desc: Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_5ER: u1, // bit offset: 5 desc: Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_6ER: u1, // bit offset: 6 desc: Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_7ER: u1, // bit offset: 7 desc: Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_8ER: u1, // bit offset: 8 desc: Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_9ER: u1, // bit offset: 9 desc: Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_10ER: u1, // bit offset: 10 desc: Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_11ER: u1, // bit offset: 11 desc: Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_12ER: u1, // bit offset: 12 desc: Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - P2_13ER: u1, // bit offset: 13 desc: Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF2 = mmio(Address + 0x00000034, 32, packed struct { - P2_0EF: u1, // bit offset: 0 desc: Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_1EF: u1, // bit offset: 1 desc: Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_2EF: u1, // bit offset: 2 desc: Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_3EF: u1, // bit offset: 3 desc: Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_4EF: u1, // bit offset: 4 desc: Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_5EF: u1, // bit offset: 5 desc: Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_6EF: u1, // bit offset: 6 desc: Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_7EF: u1, // bit offset: 7 desc: Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_8EF: u1, // bit offset: 8 desc: Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_9EF: u1, // bit offset: 9 desc: Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_10EF: u1, // bit offset: 10 desc: Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_11EF: u1, // bit offset: 11 desc: Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_12EF: u1, // bit offset: 12 desc: Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - P2_13EF: u1, // bit offset: 13 desc: Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const PINCONNECT = extern struct { - pub const Address: u32 = 0x4002c000; - // byte offset: 0 Pin function select register 0. - pub const PINSEL0 = mmio(Address + 0x00000000, 32, packed struct { - P0_0: enum(u2) { // bit offset: 0 desc: Pin function select P0.0. - @"GPIO_P0" = 0, // desc: GPIO P0.0 - @"RD1" = 1, // desc: RD1 - @"TXD3" = 2, // desc: TXD3 - @"SDA1" = 3, // desc: SDA1 - }, - P0_1: enum(u2) { // bit offset: 2 desc: Pin function select P0.1. - @"GPIO_P0" = 0, // desc: GPIO P0.1 - @"TD1" = 1, // desc: TD1 - @"RXD3" = 2, // desc: RXD3 - @"SCL1" = 3, // desc: SCL1 - }, - P0_2: enum(u2) { // bit offset: 4 desc: Pin function select P0.2. - @"GPIO_P0" = 0, // desc: GPIO P0.2 - @"TXD0" = 1, // desc: TXD0 - @"AD0" = 2, // desc: AD0.7 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_3: enum(u2) { // bit offset: 6 desc: Pin function select P0.3. - @"GPIO_P0" = 0, // desc: GPIO P0.3. - @"RXD0" = 1, // desc: RXD0 - @"AD0" = 2, // desc: AD0.6 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P0_4: enum(u2) { // bit offset: 8 desc: Pin function select P0.4. - @"GPIO_P0" = 0, // desc: GPIO P0.4. - @"I2SRX_CLK" = 1, // desc: I2SRX_CLK - @"RD2" = 2, // desc: RD2 - @"CAP2" = 3, // desc: CAP2.0 - }, - P0_5: enum(u2) { // bit offset: 10 desc: Pin function select P0.5. - @"GPIO_P0" = 0, // desc: GPIO P0.5. - @"I2SRX_WS" = 1, // desc: I2SRX_WS - @"TD2" = 2, // desc: TD2 - @"CAP2" = 3, // desc: CAP2.1 - }, - P0_6: enum(u2) { // bit offset: 12 desc: Pin function select P0.6. - @"GPIO_P0" = 0, // desc: GPIO P0.6. - @"I2SRX_SDA" = 1, // desc: I2SRX_SDA - @"SSEL1" = 2, // desc: SSEL1 - @"MAT2" = 3, // desc: MAT2.0 - }, - P0_7: enum(u2) { // bit offset: 14 desc: Pin function select P0.7. - @"GPIO_P0" = 0, // desc: GPIO P0.7. - @"I2STX_CLK" = 1, // desc: I2STX_CLK - @"SCK1" = 2, // desc: SCK1 - @"MAT2" = 3, // desc: MAT2.1 - }, - P0_8: enum(u2) { // bit offset: 16 desc: Pin function select P0.8. - @"GPIO_P0" = 0, // desc: GPIO P0.8. - @"I2STX_WS" = 1, // desc: I2STX_WS - @"MISO1" = 2, // desc: MISO1 - @"MAT2" = 3, // desc: MAT2.2 - }, - P0_9: enum(u2) { // bit offset: 18 desc: Pin function select P0.9. - @"GPIO_P0" = 0, // desc: GPIO P0.9 - @"I2STX_SDA" = 1, // desc: I2STX_SDA - @"MOSI1" = 2, // desc: MOSI1 - @"MAT2" = 3, // desc: MAT2.3 - }, - P0_10: enum(u2) { // bit offset: 20 desc: Pin function select P0.10. - @"GPIO_P0" = 0, // desc: GPIO P0.10 - @"TXD2" = 1, // desc: TXD2 - @"SDA2" = 2, // desc: SDA2 - @"MAT3" = 3, // desc: MAT3.0 - }, - P0_11: enum(u2) { // bit offset: 22 desc: Pin function select P0.11. - @"GPIO_P0" = 0, // desc: GPIO P0.11 - @"RXD2" = 1, // desc: RXD2 - @"SCL2" = 2, // desc: SCL2 - @"MAT3" = 3, // desc: MAT3.1 - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15: enum(u2) { // bit offset: 30 desc: Pin function select P0.15. - @"GPIO_P0" = 0, // desc: GPIO P0.15 - @"TXD1" = 1, // desc: TXD1 - @"SCK0" = 2, // desc: SCK0 - @"SCK" = 3, // desc: SCK - }, - }); - // byte offset: 4 Pin function select register 1. - pub const PINSEL1 = mmio(Address + 0x00000004, 32, packed struct { - P0_16: enum(u2) { // bit offset: 0 desc: Pin function select P0.16. - @"GPIO_P0" = 0, // desc: GPIO P0.16 - @"RXD1" = 1, // desc: RXD1 - @"SSEL0" = 2, // desc: SSEL0 - @"SSEL" = 3, // desc: SSEL - }, - P0_17: enum(u2) { // bit offset: 2 desc: Pin function select P0.17. - @"GPIO_P0" = 0, // desc: GPIO P0.17 - @"CTS1" = 1, // desc: CTS1 - @"MISO0" = 2, // desc: MISO0 - @"MISO" = 3, // desc: MISO - }, - P0_18: enum(u2) { // bit offset: 4 desc: Pin function select P0.18. - @"GPIO_P0" = 0, // desc: GPIO P0.18 - @"DCD1" = 1, // desc: DCD1 - @"MOSI0" = 2, // desc: MOSI0 - @"MOSI" = 3, // desc: MOSI - }, - P0_19: enum(u2) { // bit offset: 6 desc: Pin function select P019. - @"GPIO_P0" = 0, // desc: GPIO P0.19. - @"DSR1" = 1, // desc: DSR1 - // @"RESERVED", // desc: Reserved - @"SDA1" = 3, // desc: SDA1 - _, // non-exhaustive - }, - P0_20: enum(u2) { // bit offset: 8 desc: Pin function select P0.20. - @"GPIO_P0" = 0, // desc: GPIO P0.20. - @"DTR1" = 1, // desc: DTR1 - // @"RESERVED", // desc: Reserved - @"SCL1" = 3, // desc: SCL1 - _, // non-exhaustive - }, - P0_21: enum(u2) { // bit offset: 10 desc: Pin function select P0.21. - @"GPIO_PORT_0" = 0, // desc: GPIO Port 0.21. - @"RI1" = 1, // desc: RI1 - // @"RESERVED", // desc: Reserved - @"RD1" = 3, // desc: RD1 - _, // non-exhaustive - }, - P0_22: enum(u2) { // bit offset: 12 desc: Pin function select P022 - @"GPIO_P0" = 0, // desc: GPIO P0.22. - @"RTS1" = 1, // desc: RTS1 - // @"RESERVED", // desc: Reserved - @"TD1" = 3, // desc: TD1 - _, // non-exhaustive - }, - P0_23: enum(u2) { // bit offset: 14 desc: Pin function select P023. - @"GPIO_P0" = 0, // desc: GPIO P0.23. - @"AD0" = 1, // desc: AD0.0 - @"I2SRX_CLK" = 2, // desc: I2SRX_CLK - @"CAP3" = 3, // desc: CAP3.0 - }, - P0_24: enum(u2) { // bit offset: 16 desc: Pin function select P0.24. - @"GPIO_P0" = 0, // desc: GPIO P0.24. - @"AD0" = 1, // desc: AD0.1 - @"I2SRX_WS" = 2, // desc: I2SRX_WS - @"CAP3" = 3, // desc: CAP3.1 - }, - P0_25: enum(u2) { // bit offset: 18 desc: Pin function select P0.25. - @"GPIO_P0" = 0, // desc: GPIO P0.25 - @"AD0" = 1, // desc: AD0.2 - @"I2SRX_SDA" = 2, // desc: I2SRX_SDA - @"TXD3" = 3, // desc: TXD3 - }, - P0_26: enum(u2) { // bit offset: 20 desc: Pin function select P0.26. - @"GPIO_P0" = 0, // desc: GPIO P0.26 - @"AD0" = 1, // desc: AD0.3 - @"AOUT" = 2, // desc: AOUT - @"RXD3" = 3, // desc: RXD3 - }, - P0_27: enum(u2) { // bit offset: 22 desc: Pin function select P0.27. - @"GPIO_P0" = 0, // desc: GPIO P0.27 - @"SDA0" = 1, // desc: SDA0 - @"USB_SDA" = 2, // desc: USB_SDA - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_28: enum(u2) { // bit offset: 24 desc: Pin function select P0.28. - @"GPIO_P0" = 0, // desc: GPIO P0.28 - @"SCL0" = 1, // desc: SCL0 - @"USB_SCL" = 2, // desc: USB_SCL - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_29: enum(u2) { // bit offset: 26 desc: Pin function select P0.29 - @"GPIO_P0" = 0, // desc: GPIO P0.29 - @"USB_DP" = 1, // desc: USB_D+ - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P0_30: enum(u2) { // bit offset: 28 desc: Pin function select P0.30. - @"GPIO_P0" = 0, // desc: GPIO P0.30 - @"USB_DM" = 1, // desc: USB_D- - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 30 desc: Reserved - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Pin function select register 2. - pub const PINSEL2 = mmio(Address + 0x00000008, 32, packed struct { - P1_0: enum(u2) { // bit offset: 0 desc: Pin function select P1.0. - @"GPIO_P1" = 0, // desc: GPIO P1.0 - @"ENET_TXD0" = 1, // desc: ENET_TXD0 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_1: enum(u2) { // bit offset: 2 desc: Pin function select P1.1. - @"GPIO_P1" = 0, // desc: GPIO P1.1 - @"ENET_TXD1" = 1, // desc: ENET_TXD1 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u4, // bit offset: 4 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_4: enum(u2) { // bit offset: 8 desc: Pin function select P1.4. - @"GPIO_P1" = 0, // desc: GPIO P1.4. - @"ENET_TX_EN" = 1, // desc: ENET_TX_EN - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u6, // bit offset: 10 desc: Reserved. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - P1_8: enum(u2) { // bit offset: 16 desc: Pin function select P1.8. - @"GPIO_P1" = 0, // desc: GPIO P1.8. - @"ENET_CRS" = 1, // desc: ENET_CRS - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_9: enum(u2) { // bit offset: 18 desc: Pin function select P1.9. - @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.9 - @"ENET_RXD0" = 1, // desc: ENET_RXD0 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_10: enum(u2) { // bit offset: 20 desc: Pin function select P1.10. - @"GPIO_P1" = 0, // desc: GPIO P1.10 - @"ENET_RXD1" = 1, // desc: ENET_RXD1 - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_14: enum(u2) { // bit offset: 22 desc: Pin function select P1.14. - @"GPIO_P1" = 0, // desc: GPIO P1.14 - @"ENET_RX_ER" = 1, // desc: ENET_RX_ER - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - P1_15: enum(u2) { // bit offset: 30 desc: Pin function select P1.15. - @"GPIO_P1" = 0, // desc: GPIO P1.15 - @"ENET_REF_CLK" = 1, // desc: ENET_REF_CLK - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - }); - // byte offset: 12 Pin function select register 3. - pub const PINSEL3 = mmio(Address + 0x0000000c, 32, packed struct { - P1_16: enum(u2) { // bit offset: 0 desc: Pin function select P1.16. - @"GPIO_P1" = 0, // desc: GPIO P1.16 - @"ENET_MDC" = 1, // desc: ENET_MDC - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_17: enum(u2) { // bit offset: 2 desc: Pin function select P1.17. - @"GPIO_P1" = 0, // desc: GPIO P1.17 - @"ENET_MDIO" = 1, // desc: ENET_MDIO - // @"RESERVED", // desc: Reserved - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P1_18: enum(u2) { // bit offset: 4 desc: Pin function select P1.18. - @"GPIO_P1" = 0, // desc: GPIO P1.18 - @"USB_UP_LED" = 1, // desc: USB_UP_LED - @"PWM1" = 2, // desc: PWM1.1 - @"CAP1" = 3, // desc: CAP1.0 - }, - P1_19: enum(u2) { // bit offset: 6 desc: Pin function select P1.19. - @"GPIO_P1" = 0, // desc: GPIO P1.19. - @"MCOA0" = 1, // desc: MCOA0 - @"USB_PPWR" = 2, // desc: USB_PPWR - @"CAP1" = 3, // desc: CAP1.1 - }, - P1_20: enum(u2) { // bit offset: 8 desc: Pin function select P1.20. - @"GPIO_P1" = 0, // desc: GPIO P1.20. - @"MCI0" = 1, // desc: MCI0 - @"PWM1" = 2, // desc: PWM1.2 - @"SCK0" = 3, // desc: SCK0 - }, - P1_21: enum(u2) { // bit offset: 10 desc: Pin function select P1.21. - @"GPIO_P1" = 0, // desc: GPIO P1.21. - @"MCABORT" = 1, // desc: MCABORT - @"PWM1" = 2, // desc: PWM1.3 - @"SSEL0" = 3, // desc: SSEL0 - }, - P1_22: enum(u2) { // bit offset: 12 desc: Pin function select P1.22 - @"GPIO_P1" = 0, // desc: GPIO P1.22. - @"MCOB0" = 1, // desc: MCOB0 - @"USB_PWRD" = 2, // desc: USB_PWRD - @"MAT1" = 3, // desc: MAT1.0 - }, - P1_23: enum(u2) { // bit offset: 14 desc: Pin function select P1.23. - @"GPIO_P1" = 0, // desc: GPIO P1.23. - @"MCI1" = 1, // desc: MCI1 - @"PWM1" = 2, // desc: PWM1.4 - @"MISO0" = 3, // desc: MISO0 - }, - P1_24: enum(u2) { // bit offset: 16 desc: Pin function select P1.24. - @"GPIO_P1" = 0, // desc: GPIO P1.24. - @"MCI2" = 1, // desc: MCI2 - @"PWM1" = 2, // desc: PWM1.5 - @"MOSI0" = 3, // desc: MOSI0 - }, - P1_25: enum(u2) { // bit offset: 18 desc: Pin function select P1.25. - @"GPIO_P1" = 0, // desc: GPIO P1.25 - @"MCOA1" = 1, // desc: MCOA1 - // @"RESERVED", // desc: Reserved - @"MAT1" = 3, // desc: MAT1.1 - _, // non-exhaustive - }, - P1_26: enum(u2) { // bit offset: 20 desc: Pin function select P1.26. - @"GPIO_P1" = 0, // desc: GPIO P1.26 - @"MCOB1" = 1, // desc: MCOB1 - @"PWM1" = 2, // desc: PWM1.6 - @"CAP0" = 3, // desc: CAP0.0 - }, - P1_27: enum(u2) { // bit offset: 22 desc: Pin function select P1.27. - @"GPIO_P1" = 0, // desc: GPIO P1.27 - @"CLKOUT" = 1, // desc: CLKOUT - @"USB_OVRCR" = 2, // desc: USB_OVRCR - @"CAP0" = 3, // desc: CAP0.1 - }, - P1_28: enum(u2) { // bit offset: 24 desc: Pin function select P1.28. - @"GPIO_P1" = 0, // desc: GPIO P1.28 - @"MCOA2" = 1, // desc: MCOA2 - @"PCAP1" = 2, // desc: PCAP1.0 - @"MAT0" = 3, // desc: MAT0.0 - }, - P1_29: enum(u2) { // bit offset: 26 desc: Pin function select P1.29 - @"GPIO_P1" = 0, // desc: GPIO P1.29 - @"MCOB2" = 1, // desc: MCOB2 - @"PCAP1" = 2, // desc: PCAP1.1 - @"MAT0" = 3, // desc: MAT0.1 - }, - P1_30: enum(u2) { // bit offset: 28 desc: Pin function select P1.30. - @"GPIO_P1" = 0, // desc: GPIO P1.30 - // @"RESERVED", // desc: Reserved - @"VBUS" = 2, // desc: VBUS - @"AD0" = 3, // desc: AD0.4 - _, // non-exhaustive - }, - P1_31: enum(u2) { // bit offset: 30 desc: Pin function select P1.31. - @"GPIO_PORT_1" = 0, // desc: GPIO Port 1.31 - // @"RESERVED", // desc: Reserved - @"SCK1" = 2, // desc: SCK1 - @"AD0" = 3, // desc: AD0.5 - _, // non-exhaustive - }, - }); - // byte offset: 16 Pin function select register 4 - pub const PINSEL4 = mmio(Address + 0x00000010, 32, packed struct { - P2_0: enum(u2) { // bit offset: 0 desc: Pin function select P2.0. - @"GPIO_P2" = 0, // desc: GPIO P2.0 - @"PWM1" = 1, // desc: PWM1.1 - @"TXD1" = 2, // desc: TXD1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_1: enum(u2) { // bit offset: 2 desc: Pin function select P2.1. - @"GPIO_P2" = 0, // desc: GPIO P2.1 - @"PWM1" = 1, // desc: PWM1.2 - @"RXD1" = 2, // desc: RXD1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_2: enum(u2) { // bit offset: 4 desc: Pin function select P2.2. - @"GPIO_P2" = 0, // desc: GPIO P2.2 - @"PWM1" = 1, // desc: PWM1.3 - @"CTS1" = 2, // desc: CTS1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_3: enum(u2) { // bit offset: 6 desc: Pin function select P2.3. - @"GPIO_P2" = 0, // desc: GPIO P2.3. - @"PWM1" = 1, // desc: PWM1.4 - @"DCD1" = 2, // desc: DCD1 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P2_4: enum(u2) { // bit offset: 8 desc: Pin function select P2.4. - @"GPIO_P2" = 0, // desc: GPIO P2.4. - @"PWM1" = 1, // desc: PWM1.5 - @"DSR1" = 2, // desc: DSR1 - // @"RESERVED", // desc: Reserved. - _, // non-exhaustive - }, - P2_5: enum(u2) { // bit offset: 10 desc: Pin function select P2.5. - @"GPIO_P2" = 0, // desc: GPIO P2.5. - @"PWM1" = 1, // desc: PWM1.6 - @"DTR1" = 2, // desc: DTR1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_6: enum(u2) { // bit offset: 12 desc: Pin function select P2.6. - @"GPIO_P2" = 0, // desc: GPIO P2.6. - @"PCAP1" = 1, // desc: PCAP1.0 - @"RI1" = 2, // desc: RI1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_7: enum(u2) { // bit offset: 14 desc: Pin function select P2.7. - @"GPIO_P2" = 0, // desc: GPIO P2.7. - @"RD2" = 1, // desc: RD2 - @"RTS1" = 2, // desc: RTS1 - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_8: enum(u2) { // bit offset: 16 desc: Pin function select P2.8. - @"GPIO_P2" = 0, // desc: GPIO P2.8. - @"TD2" = 1, // desc: TD2 - @"TXD2" = 2, // desc: TXD2 - @"ENET_MDC" = 3, // desc: ENET_MDC - }, - P2_9: enum(u2) { // bit offset: 18 desc: Pin function select P2.9. - @"GPIO_P2" = 0, // desc: GPIO P2.9 - @"USB_CONNECT" = 1, // desc: USB_CONNECT - @"RXD2" = 2, // desc: RXD2 - @"ENET_MDIO" = 3, // desc: ENET_MDIO - }, - P2_10: enum(u2) { // bit offset: 20 desc: Pin function select P2.10. - @"GPIO_P2" = 0, // desc: GPIO P2.10 - @"EINT0" = 1, // desc: EINT0 - @"NMI" = 2, // desc: NMI - // @"RESERVED", // desc: Reserved - _, // non-exhaustive - }, - P2_11: enum(u2) { // bit offset: 22 desc: Pin function select P2.11. - @"GPIO_P2" = 0, // desc: GPIO P2.11 - @"EINT1" = 1, // desc: EINT1 - // @"RESERVED", // desc: Reserved - @"I2STX_CLK" = 3, // desc: I2STX_CLK - _, // non-exhaustive - }, - P2_12: enum(u2) { // bit offset: 24 desc: Pin function select P2.12. - @"GPIO_P2" = 0, // desc: GPIO P2.12 - @"EINT2" = 1, // desc: EINT2 - // @"RESERVED", // desc: Reserved - @"I2STX_WS" = 3, // desc: I2STX_WS - _, // non-exhaustive - }, - P2_13: enum(u2) { // bit offset: 26 desc: Pin function select P2.13. - @"GPIO_P2" = 0, // desc: GPIO P2.13 - @"EINT3" = 1, // desc: EINT3 - // @"RESERVED", // desc: Reserved - @"I2STX_SDA" = 3, // desc: I2STX_SDA - _, // non-exhaustive - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Pin function select register 7 - pub const PINSEL7 = mmio(Address + 0x0000001c, 32, packed struct { - // RESERVED: u18, // bit offset: 0 desc: Reserved. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25: enum(u2) { // bit offset: 18 desc: Pin function select P3.25. - @"GPIO_P3" = 0, // desc: GPIO P3.25 - // @"RESERVED", // desc: Reserved - @"MAT0" = 2, // desc: MAT0.0 - @"PWM1" = 3, // desc: PWM1.2 - _, // non-exhaustive - }, - P3_26: enum(u2) { // bit offset: 20 desc: Pin function select P3.26. - @"GPIO_P3" = 0, // desc: GPIO P3.26 - @"STCLK" = 1, // desc: STCLK - @"MAT0" = 2, // desc: MAT0.1 - @"PWM1" = 3, // desc: PWM1.3 - }, - // RESERVED: u10, // bit offset: 22 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 Pin function select register 9 - pub const PINSEL9 = mmio(Address + 0x00000024, 32, packed struct { - // RESERVED: u24, // bit offset: 0 desc: Reserved. - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28: enum(u2) { // bit offset: 24 desc: Pin function select P4.28. - @"GPIO_P4" = 0, // desc: GPIO P4.28 - @"RX_MCLK" = 1, // desc: RX_MCLK - @"MAT2" = 2, // desc: MAT2.0 - @"TXD3" = 3, // desc: TXD3 - }, - P4_29: enum(u2) { // bit offset: 26 desc: Pin function select P4.29. - @"GPIO_P4" = 0, // desc: GPIO P4.29 - @"TX_MCLK" = 1, // desc: TX_MCLK - @"MAT2" = 2, // desc: MAT2.1 - @"RXD3" = 3, // desc: RXD3 - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Pin function select register 10 - pub const PINSEL10 = mmio(Address + 0x00000028, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Reserved. Software should not write 1 to these bits. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TPIUCTRL: enum(u1) { // bit offset: 3 desc: TPIU interface pins control. - @"DISABLED" = 0, // desc: Disabled. TPIU interface is disabled. - @"ENABLED" = 1, // desc: Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Software should not write 1 to these bits. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Pin mode select register 0 - pub const PINMODE0 = mmio(Address + 0x00000040, 32, packed struct { - P0_00MODE: enum(u2) { // bit offset: 0 desc: Port 0 pin 0 on-chip pull-up/down resistor control. - @"PULL_UP" = 0, // desc: Pull-up. P0.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.0 has a pull-down resistor enabled. - }, - P0_01MODE: enum(u2) { // bit offset: 2 desc: Port 0 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.1 has a pull-down resistor enabled. - }, - P0_02MODE: enum(u2) { // bit offset: 4 desc: Port 0 pin 2 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.2 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.2 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.2 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.2 has a pull-down resistor enabled. - }, - P0_03MODE: enum(u2) { // bit offset: 6 desc: Port 0 pin 3 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.3 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.3 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.3 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.3 has a pull-down resistor enabled. - }, - P0_04MODE: enum(u2) { // bit offset: 8 desc: Port 0 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.4 has a pull-down resistor enabled. - }, - P0_05MODE: enum(u2) { // bit offset: 10 desc: Port 0 pin 5 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.5 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.5 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.5 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.5 has a pull-down resistor enabled. - }, - P0_06MODE: enum(u2) { // bit offset: 12 desc: Port 0 pin 6 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.6 pin has a pull-up resistor enabled. - @"DISABLED" = 1, // desc: Disabled. Repeater. P0.6 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.6 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.6 has a pull-down resistor enabled. - }, - P0_07MODE: enum(u2) { // bit offset: 14 desc: Port 0 pin 7 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.7 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.7 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.7 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.7 has a pull-down resistor enabled. - }, - P0_08MODE: enum(u2) { // bit offset: 16 desc: Port 0 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.8 has a pull-down resistor enabled. - }, - P0_09MODE: enum(u2) { // bit offset: 18 desc: Port 0 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.9 has a pull-down resistor enabled. - }, - P0_10MODE: enum(u2) { // bit offset: 20 desc: Port 0 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.10 has a pull-down resistor enabled. - }, - P0_11MODE: enum(u2) { // bit offset: 22 desc: Port 0 pin 11 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.11 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.11 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.11 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.11 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 24 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15MODE: enum(u2) { // bit offset: 30 desc: Port 0 pin 15 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.15 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.15 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.15 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.15 has a pull-down resistor enabled. - }, - }); - // byte offset: 68 Pin mode select register 1 - pub const PINMODE1 = mmio(Address + 0x00000044, 32, packed struct { - P0_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.16 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.16 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.16 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.16 has a pull-down resistor enabled. - }, - P0_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.17 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.17 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.17 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.17 has a pull-down resistor enabled. - }, - P0_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.18 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.18 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.18 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.18 has a pull-down resistor enabled. - }, - P0_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.19 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.19 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.19 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.19 has a pull-down resistor enabled. - }, - P0_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.20 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.20 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.20 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.20 has a pull-down resistor enabled. - }, - P0_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.21 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.21 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.21 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.21 has a pull-down resistor enabled. - }, - P0_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.22 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.22 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.22 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.22 has a pull-down resistor enabled. - }, - P0_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.23 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.23 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.23 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.23 has a pull-down resistor enabled. - }, - P0_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.24 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.24 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.24 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.24 has a pull-down resistor enabled. - }, - P0_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.25 has a pull-down resistor enabled. - }, - P0_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P0.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P0.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P0.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P0.26 has a pull-down resistor enabled. - }, - // RESERVED: u8, // bit offset: 22 desc: Reserved. - // RESERVED: u2, // bit offset: 30 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Pin mode select register 2 - pub const PINMODE2 = mmio(Address + 0x00000048, 32, packed struct { - P1_00MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 0 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.0 has a pull-down resistor enabled. - }, - P1_01MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.1 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 4 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_04MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.4 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 10 desc: Reserved. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - P1_08MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.8 has a pull-down resistor enabled. - }, - P1_09MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.9 has a pull-down resistor enabled. - }, - P1_10MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.10 has a pull-down resistor enabled. - }, - // RESERVED: u6, // bit offset: 22 desc: Reserved. - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - P1_14MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 14 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.14 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.14 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.14 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.14 has a pull-down resistor enabled. - }, - P1_15MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 15 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.15 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.15 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.15 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.15 has a pull-down resistor enabled. - }, - }); - // byte offset: 76 Pin mode select register 3. - pub const PINMODE3 = mmio(Address + 0x0000004c, 32, packed struct { - P1_16MODE: enum(u2) { // bit offset: 0 desc: Port 1 pin 16 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.16 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.16 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.16 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.16 has a pull-down resistor enabled. - }, - P1_17MODE: enum(u2) { // bit offset: 2 desc: Port 1 pin 17 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.17 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.17 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.17 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.17 has a pull-down resistor enabled. - }, - P1_18MODE: enum(u2) { // bit offset: 4 desc: Port 1 pin 18 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.18 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.18 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.18 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.18 has a pull-down resistor enabled. - }, - P1_19MODE: enum(u2) { // bit offset: 6 desc: Port 1 pin 19 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.19 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.19 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.19 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.19 has a pull-down resistor enabled. - }, - P1_20MODE: enum(u2) { // bit offset: 8 desc: Port 1 pin 20 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.20 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.20 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.20 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.20 has a pull-down resistor enabled. - }, - P1_21MODE: enum(u2) { // bit offset: 10 desc: Port 1 pin 21 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.21 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.21 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.21 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.21 has a pull-down resistor enabled. - }, - P1_22MODE: enum(u2) { // bit offset: 12 desc: Port 1 pin 22 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.22 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.22 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.22 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.22 has a pull-down resistor enabled. - }, - P1_23MODE: enum(u2) { // bit offset: 14 desc: Port 1 pin 23 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.23 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.23 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.23 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.23 has a pull-down resistor enabled. - }, - P1_24MODE: enum(u2) { // bit offset: 16 desc: Port 1 pin 24 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.24 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.24 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.24 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.24 has a pull-down resistor enabled. - }, - P1_25MODE: enum(u2) { // bit offset: 18 desc: Port 1 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.25 has a pull-down resistor enabled. - }, - P1_26MODE: enum(u2) { // bit offset: 20 desc: Port 1 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.26 has a pull-down resistor enabled. - }, - P1_27MODE: enum(u2) { // bit offset: 22 desc: Port 1 pin 27 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.27 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.27 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.27 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.27 has a pull-down resistor enabled. - }, - P1_28MODE: enum(u2) { // bit offset: 24 desc: Port 1 pin 28 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.28 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.28 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.28 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.28 has a pull-down resistor enabled. - }, - P1_29MODE: enum(u2) { // bit offset: 26 desc: Port 1 pin 29 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.29 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.29 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.29 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.29 has a pull-down resistor enabled. - }, - P1_30MODE: enum(u2) { // bit offset: 28 desc: Port 1 pin 30 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.30 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.30 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.30 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.30 has a pull-down resistor enabled. - }, - P1_31MODE: enum(u2) { // bit offset: 30 desc: Port 1 pin 31 control. - @"PULL_UP" = 0, // desc: Pull-up. P1.31 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P1.31 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P1.31 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P1.31 has a pull-down resistor enabled. - }, - }); - // byte offset: 80 Pin mode select register 4 - pub const PINMODE4 = mmio(Address + 0x00000050, 32, packed struct { - P2_00MODE: enum(u2) { // bit offset: 0 desc: Port 2 pin 0 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.0 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.0 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.0 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.0 has a pull-down resistor enabled. - }, - P2_01MODE: enum(u2) { // bit offset: 2 desc: Port 2 pin 1 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.1 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.1 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.1 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.1 has a pull-down resistor enabled. - }, - P2_02MODE: enum(u2) { // bit offset: 4 desc: Port 2 pin 2 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.2 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.2 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.2 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.2 has a pull-down resistor enabled. - }, - P2_03MODE: enum(u2) { // bit offset: 6 desc: Port 2 pin 3 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.3 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.3 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.3 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.3 has a pull-down resistor enabled. - }, - P2_04MODE: enum(u2) { // bit offset: 8 desc: Port 2 pin 4 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.4 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.4 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.4 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.4 has a pull-down resistor enabled. - }, - P2_05MODE: enum(u2) { // bit offset: 10 desc: Port 2 pin 5 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.5 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.5 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.5 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.5 has a pull-down resistor enabled. - }, - P2_06MODE: enum(u2) { // bit offset: 12 desc: Port 2 pin 6 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.6 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.6 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.6 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.6 has a pull-down resistor enabled. - }, - P2_07MODE: enum(u2) { // bit offset: 14 desc: Port 2 pin 7 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.7 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.7 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.7 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.7 has a pull-down resistor enabled. - }, - P2_08MODE: enum(u2) { // bit offset: 16 desc: Port 2 pin 8 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.8 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.8 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.8 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.8 has a pull-down resistor enabled. - }, - P2_09MODE: enum(u2) { // bit offset: 18 desc: Port 2 pin 9 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.9 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.9 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.9 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.9 has a pull-down resistor enabled. - }, - P2_10MODE: enum(u2) { // bit offset: 20 desc: Port 2 pin 10 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.10 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.10 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.10 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.10 has a pull-down resistor enabled. - }, - P2_11MODE: enum(u2) { // bit offset: 22 desc: Port 2 pin 11 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.11 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.11 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.11 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.11 has a pull-down resistor enabled. - }, - P2_12MODE: enum(u2) { // bit offset: 24 desc: Port 2 pin 12 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.12 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.12 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.12 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.12 has a pull-down resistor enabled. - }, - P2_13MODE: enum(u2) { // bit offset: 26 desc: Port 2 pin 13 control. - @"PULL_UP" = 0, // desc: Pull-up. P2.13 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P2.13 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P2.13 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P2.13 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 Pin mode select register 7 - pub const PINMODE7 = mmio(Address + 0x0000005c, 32, packed struct { - // RESERVED: u18, // bit offset: 0 desc: Reserved - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25MODE: enum(u2) { // bit offset: 18 desc: Port 3 pin 25 control. - @"PULL_UP" = 0, // desc: Pull-up. P3.25 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P3.25 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P3.25 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P3.25 has a pull-down resistor enabled. - }, - P3_26MODE: enum(u2) { // bit offset: 20 desc: Port 3 pin 26 control. - @"PULL_UP" = 0, // desc: Pull-up. P3.26 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P3.26 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P3.26 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P3.26 has a pull-down resistor enabled. - }, - // RESERVED: u10, // bit offset: 22 desc: Reserved. - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 100 Pin mode select register 9 - pub const PINMODE9 = mmio(Address + 0x00000064, 32, packed struct { - // RESERVED: u24, // bit offset: 0 desc: Reserved. - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28MODE: enum(u2) { // bit offset: 24 desc: Port 4 pin 28 control. - @"PULL_UP" = 0, // desc: Pull-up. P4.28 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P4.28 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P4.28 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P4.28 has a pull-down resistor enabled. - }, - P4_29MODE: enum(u2) { // bit offset: 26 desc: Port 4 pin 29 control. - @"PULL_UP" = 0, // desc: Pull-up. P4.29 pin has a pull-up resistor enabled. - @"REPEATER" = 1, // desc: Repeater. P4.29 pin has repeater mode enabled. - @"DISABLED" = 2, // desc: Disabled. P4.29 pin has neither pull-up nor pull-down. - @"PULL_DOWN" = 3, // desc: Pull-down. P4.29 has a pull-down resistor enabled. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 104 Open drain mode control register 0 - pub const PINMODE_OD0 = mmio(Address + 0x00000068, 32, packed struct { - P0_00OD: enum(u1) { // bit offset: 0 desc: Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.0 pin is in the open drain mode. - }, - P0_01OD: enum(u1) { // bit offset: 1 desc: Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.1 pin is in the open drain mode. - }, - P0_02OD: enum(u1) { // bit offset: 2 desc: Port 0 pin 2 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.2 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.2 pin is in the open drain mode. - }, - P0_03OD: enum(u1) { // bit offset: 3 desc: Port 0 pin 3 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.3 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.3 pin is in the open drain mode. - }, - P0_04OD: enum(u1) { // bit offset: 4 desc: Port 0 pin 4 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.4 pin is in the open drain mode. - }, - P0_05OD: enum(u1) { // bit offset: 5 desc: Port 0 pin 5 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.5 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.5 pin is in the open drain mode. - }, - P0_06OD: enum(u1) { // bit offset: 6 desc: Port 0 pin 6 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.6 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.6 pin is in the open drain mode. - }, - P0_07OD: enum(u1) { // bit offset: 7 desc: Port 0 pin 7 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.7 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.7 pin is in the open drain mode. - }, - P0_08OD: enum(u1) { // bit offset: 8 desc: Port 0 pin 8 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.8 pin is in the open drain mode. - }, - P0_09OD: enum(u1) { // bit offset: 9 desc: Port 0 pin 9 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.9 pin is in the open drain mode. - }, - P0_10OD: enum(u1) { // bit offset: 10 desc: Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.10 pin is in the open drain mode. - }, - P0_11OD: enum(u1) { // bit offset: 11 desc: Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.11 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.11 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 12 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P0_15OD: enum(u1) { // bit offset: 15 desc: Port 0 pin 15 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.15 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.15 pin is in the open drain mode. - }, - P0_16OD: enum(u1) { // bit offset: 16 desc: Port 0 pin 16 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.16 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.16 pin is in the open drain mode. - }, - P0_17OD: enum(u1) { // bit offset: 17 desc: Port 0 pin 17 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.17 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.17 pin is in the open drain mode. - }, - P0_18OD: enum(u1) { // bit offset: 18 desc: Port 0 pin 18 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.18 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.18 pin is in the open drain mode. - }, - P0_19OD: enum(u1) { // bit offset: 19 desc: Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.19 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.19 pin is in the open drain mode. - }, - P0_20OD: enum(u1) { // bit offset: 20 desc: Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. - @"NORMAL" = 0, // desc: Normal. P0.20 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.20 pin is in the open drain mode. - }, - P0_21OD: enum(u1) { // bit offset: 21 desc: Port 0 pin 21 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.21 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.21 pin is in the open drain mode. - }, - P0_22OD: enum(u1) { // bit offset: 22 desc: Port 0 pin 22 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.22 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.22 pin is in the open drain mode. - }, - P0_23OD: enum(u1) { // bit offset: 23 desc: Port 0 pin 23 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. - }, - P0_24OD: enum(u1) { // bit offset: 24 desc: Port 0 pin 24open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.23 pin is in the open drain mode. - }, - P0_25OD: enum(u1) { // bit offset: 25 desc: Port 0 pin 25 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.25 pin is in the open drain mode. - }, - P0_26OD: enum(u1) { // bit offset: 26 desc: Port 0 pin 26 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.26 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.26 pin is in the open drain mode. - }, - // RESERVED: u2, // bit offset: 27 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - P0_29OD: enum(u1) { // bit offset: 29 desc: Port 0 pin 29 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.29 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.29 pin is in the open drain mode. - }, - P0_30OD: enum(u1) { // bit offset: 30 desc: Port 0 pin 30 open drain mode control - @"NORMAL" = 0, // desc: Normal. P0.30 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P0.30 pin is in the open drain mode. - }, - // RESERVED: u1, // bit offset: 31 desc: Reserved. - padding1: u1 = 0, - }); - // byte offset: 108 Open drain mode control register 1 - pub const PINMODE_OD1 = mmio(Address + 0x0000006c, 32, packed struct { - P1_00OD: enum(u1) { // bit offset: 0 desc: Port 1 pin 0 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P1.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.0 pin is in the open drain mode. - }, - P1_01OD: enum(u1) { // bit offset: 1 desc: Port 1 pin 1 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.1 pin is in the open drain mode. - }, - // RESERVED: u2, // bit offset: 2 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - P1_04OD: enum(u1) { // bit offset: 4 desc: Port 1 pin 4 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.4 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 5 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - P1_08OD: enum(u1) { // bit offset: 8 desc: Port 1 pin 8 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.8 pin is in the open drain mode. - }, - P1_09OD: enum(u1) { // bit offset: 9 desc: Port 1 pin 9 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.9 pin is in the open drain mode. - }, - P1_10OD: enum(u1) { // bit offset: 10 desc: Port 1 pin 10 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.10 pin is in the open drain mode. - }, - // RESERVED: u3, // bit offset: 11 desc: Reserved. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - P1_14OD: enum(u1) { // bit offset: 14 desc: Port 1 pin 14 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.14 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.14 pin is in the open drain mode. - }, - P1_15OD: enum(u1) { // bit offset: 15 desc: Port 1 pin 15 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.15 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.15 pin is in the open drain mode. - }, - P1_16OD: enum(u1) { // bit offset: 16 desc: Port 1 pin 16 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.16 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.16 pin is in the open drain mode. - }, - P1_17OD: enum(u1) { // bit offset: 17 desc: Port 1 pin 17 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.17 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.17 pin is in the open drain mode. - }, - P1_18OD: enum(u1) { // bit offset: 18 desc: Port 1 pin 18 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.18 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.18 pin is in the open drain mode. - }, - P1_19OD: enum(u1) { // bit offset: 19 desc: Port 1 pin 19 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.19 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.19 pin is in the open drain mode. - }, - P1_20OD: enum(u1) { // bit offset: 20 desc: Port 1 pin 20open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.20 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.20 pin is in the open drain mode. - }, - P1_21OD: enum(u1) { // bit offset: 21 desc: Port 1 pin 21 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.21 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.21 pin is in the open drain mode. - }, - P1_22OD: enum(u1) { // bit offset: 22 desc: Port 1 pin 22 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.22 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.22 pin is in the open drain mode. - }, - P1_23OD: enum(u1) { // bit offset: 23 desc: Port 1 pin 23 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.23 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.23 pin is in the open drain mode. - }, - P1_24OD: enum(u1) { // bit offset: 24 desc: Port 1 pin 24open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.24 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.24 pin is in the open drain mode. - }, - P1_25OD: enum(u1) { // bit offset: 25 desc: Port 1 pin 25 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.25 pin is in the open drain mode. - }, - P1_26OD: enum(u1) { // bit offset: 26 desc: Port 1 pin 26 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.26 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.26 pin is in the open drain mode. - }, - P1_27OD: enum(u1) { // bit offset: 27 desc: Port 1 pin 27 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.27 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.27 pin is in the open drain mode. - }, - P1_28OD: enum(u1) { // bit offset: 28 desc: Port 1 pin 28 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.28 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.28 pin is in the open drain mode. - }, - P1_29OD: enum(u1) { // bit offset: 29 desc: Port 1 pin 29 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.29 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.29 pin is in the open drain mode. - }, - P1_30OD: enum(u1) { // bit offset: 30 desc: Port 1 pin 30 open drain mode control, see P1.00OD - @"NORMAL" = 0, // desc: Normal. P1.30 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.30 pin is in the open drain mode. - }, - P1_31OD: enum(u1) { // bit offset: 31 desc: Port 1 pin 31 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P1.31 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P1.31 pin is in the open drain mode. - }, - }); - // byte offset: 112 Open drain mode control register 2 - pub const PINMODE_OD2 = mmio(Address + 0x00000070, 32, packed struct { - P2_00OD: enum(u1) { // bit offset: 0 desc: Port 2 pin 0 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P2.0 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.0 pin is in the open drain mode. - }, - P2_01OD: enum(u1) { // bit offset: 1 desc: Port 2 pin 1 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.1 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.1p in is in the open drain mode. - }, - P2_02OD: enum(u1) { // bit offset: 2 desc: Port 2 pin 2 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.2 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.2 pin is in the open drain mode. - }, - P2_03OD: enum(u1) { // bit offset: 3 desc: Port 2 pin 3 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.3 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.3 pin is in the open drain mode. - }, - P2_04OD: enum(u1) { // bit offset: 4 desc: Port 2 pin 4 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.4 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.4 pin is in the open drain mode. - }, - P2_05OD: enum(u1) { // bit offset: 5 desc: Port 2 pin 5 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.5 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.5 pin is in the open drain mode. - }, - P2_06OD: enum(u1) { // bit offset: 6 desc: Port 2 pin 6 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.6 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.6 pin is in the open drain mode. - }, - P2_07OD: enum(u1) { // bit offset: 7 desc: Port 2 pin 7 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.7 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.7 pin is in the open drain mode. - }, - P2_08OD: enum(u1) { // bit offset: 8 desc: Port 2 pin 8 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.8 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.8 pin is in the open drain mode. - }, - P2_09OD: enum(u1) { // bit offset: 9 desc: Port 2 pin 9 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.9 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.9 pin is in the open drain mode. - }, - P2_10OD: enum(u1) { // bit offset: 10 desc: Port 2 pin 10 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.10 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.10 pin is in the open drain mode. - }, - P2_11OD: enum(u1) { // bit offset: 11 desc: Port 2 pin 11 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.11 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.11 pin is in the open drain mode. - }, - P2_12OD: enum(u1) { // bit offset: 12 desc: Port 2 pin 12 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.12 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.12 pin is in the open drain mode. - }, - P2_13OD: enum(u1) { // bit offset: 13 desc: Port 2 pin 13 open drain mode control, see P2.00OD - @"NORMAL" = 0, // desc: Normal. P2.13 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P2.13 pin is in the open drain mode. - }, - // RESERVED: u18, // bit offset: 14 desc: Reserved. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Open drain mode control register 3 - pub const PINMODE_OD3 = mmio(Address + 0x00000074, 32, packed struct { - // RESERVED: u25, // bit offset: 0 desc: Reserved. - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P3_25OD: enum(u1) { // bit offset: 25 desc: Port 3 pin 25 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P3.25 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P3.25 pin is in the open drain mode. - }, - P3_26OD: u1, // bit offset: 26 desc: Port 3 pin 26 open drain mode control, see P3.25OD - // RESERVED: u5, // bit offset: 27 desc: Reserved. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 120 Open drain mode control register 4 - pub const PINMODE_OD4 = mmio(Address + 0x00000078, 32, packed struct { - // RESERVED: u28, // bit offset: 0 desc: Reserved. - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - P4_28OD: enum(u1) { // bit offset: 28 desc: Port 4 pin 28 open drain mode control. - @"NORMAL" = 0, // desc: Normal. P4.28 pin is in the normal (not open drain) mode. - @"OPEN_DRAIN" = 1, // desc: Open-drain. P4.28 pin is in the open drain mode. - }, - P4_29OD: u1, // bit offset: 29 desc: Port 4 pin 29 open drain mode control, see P4.28OD - // RESERVED: u2, // bit offset: 30 desc: Reserved. - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 124 I2C Pin Configuration register - pub const I2CPADCFG = mmio(Address + 0x0000007c, 32, packed struct { - SDADRV0: enum(u1) { // bit offset: 0 desc: Drive mode control for the SDA0 pin, P0.27. - @"STANDARD" = 0, // desc: Standard. The SDA0 pin is in the standard drive mode. - @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode. - }, - SDAI2C0: enum(u1) { // bit offset: 1 desc: I 2C filter mode control for the SDA0 pin, P0.27. - @"ENABLED" = 0, // desc: Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled. - @"DISABLED" = 1, // desc: Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled. - }, - SCLDRV0: enum(u1) { // bit offset: 2 desc: Drive mode control for the SCL0 pin, P0.28. - @"STANDARD" = 0, // desc: Standard. The SCL0 pin is in the standard drive mode. - @"FAST_MODE_PLUS" = 1, // desc: Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode. - }, - SCLI2C0: enum(u1) { // bit offset: 3 desc: I 2C filter mode control for the SCL0 pin, P0.28. - @"ENABLED" = 0, // desc: Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled. - @"DISABLED" = 1, // desc: Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SSP1 = extern struct { - pub const Address: u32 = 0x40030000; - // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer - @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer - @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer - @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer - @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer - @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer - @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer - @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer - @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer - @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer - @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer - @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer - @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer - _, // non-exhaustive - }, - FRF: enum(u2) { // bit offset: 4 desc: Frame Format. - @"SPI" = 0, // desc: SPI - @"TI" = 1, // desc: TI - @"MICROWIRE" = 2, // desc: Microwire - @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. - }, - CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. - @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. - }, - CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. - @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. - @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. - }, - SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control Register 1. Selects master/slave and other modes. - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. - @"NORMAL" = 0, // desc: During normal operation. - @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). - }, - SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. - @"DISABLED" = 0, // desc: The SSP controller is disabled. - @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. - }, - MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. - @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. - }, - SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Status Register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Clock Prescale Register - pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { - CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Interrupt Mask Set and Clear Register - pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Raw Interrupt Status Register - pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Masked Interrupt Status Register - pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 SSPICR Interrupt Clear Register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 SSP0 DMA control register - pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const ADC = extern struct { - pub const Address: u32 = 0x40034000; - // byte offset: 0 A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - SEL: u8, // bit offset: 0 desc: Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. - CLKDIV: u8, // bit offset: 8 desc: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. - BURST: enum(u1) { // bit offset: 16 desc: Burst mode - @"BURST" = 1, // desc: The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start. - @"SW" = 0, // desc: Conversions are software controlled and require 31 clocks. - }, - // RESERVED: u4, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PDN: enum(u1) { // bit offset: 21 desc: Power down mode - @"POWERED" = 1, // desc: The A/D converter is operational. - @"POWERDOWN" = 0, // desc: The A/D converter is in power-down mode. - }, - // RESERVED: u2, // bit offset: 22 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - START: enum(u3) { // bit offset: 24 desc: When the BURST bit is 0, these bits control whether and when an A/D conversion is started: - @"NO_START_THIS_VALUE" = 0, // desc: No start (this value should be used when clearing PDN to 0). - @"START_CONVERSION_NOW" = 1, // desc: Start conversion now. - @"P2_10" = 2, // desc: Start conversion when the edge selected by bit 27 occurs on the P2[10] pin. - @"P1_27" = 3, // desc: Start conversion when the edge selected by bit 27 occurs on the P1[27] pin. - @"MAT0_1" = 4, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. - @"MAT0_3" = 5, // desc: Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. - @"MAT1_0" = 6, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. - @"MAT1_1" = 7, // desc: Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. - }, - EDGE: enum(u1) { // bit offset: 27 desc: This bit is significant only when the START field contains 010-111. In these cases: - @"FALLLING" = 1, // desc: Start conversion on a falling edge on the selected CAP/MAT signal. - @"RISING" = 0, // desc: Start conversion on a rising edge on the selected CAP/MAT signal. - }, - // RESERVED: u4, // bit offset: 28 desc: Reserved. Read value is undefined, only zero should be written. - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion. - pub const GDR = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u8, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - CHN: u3, // bit offset: 24 desc: These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). - // RESERVED: u3, // bit offset: 27 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. - }); - // byte offset: 12 A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. - pub const INTEN = mmio(Address + 0x0000000c, 32, packed struct { - ADINTEN0: enum(u1) { // bit offset: 0 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 0 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 0 will generate an interrupt. - }, - ADINTEN1: enum(u1) { // bit offset: 1 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 1 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 1 will generate an interrupt. - }, - ADINTEN2: enum(u1) { // bit offset: 2 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 2 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 2 will generate an interrupt. - }, - ADINTEN3: enum(u1) { // bit offset: 3 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 3 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 3 will generate an interrupt. - }, - ADINTEN4: enum(u1) { // bit offset: 4 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 4 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 4 will generate an interrupt. - }, - ADINTEN5: enum(u1) { // bit offset: 5 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 5 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 5 will generate an interrupt. - }, - ADINTEN6: enum(u1) { // bit offset: 6 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 6 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 6 will generate an interrupt. - }, - ADINTEN7: enum(u1) { // bit offset: 7 desc: Interrupt enable - @"DISABLE" = 0, // desc: Completion of a conversion on ADC channel 7 will not generate an interrupt. - @"ENABLE" = 1, // desc: Completion of a conversion on ADC channel 7 will generate an interrupt. - }, - ADGINTEN: enum(u1) { // bit offset: 8 desc: Interrupt enable - @"CHANNELS" = 0, // desc: Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts. - @"GLOBAL" = 1, // desc: The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts. - }, - // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_0 = mmio(Address + 0x00000010, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 20 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_1 = mmio(Address + 0x00000014, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 24 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_2 = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 28 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_3 = mmio(Address + 0x0000001c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 32 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_4 = mmio(Address + 0x00000020, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 36 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_5 = mmio(Address + 0x00000024, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 40 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_6 = mmio(Address + 0x00000028, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 44 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. - pub const DR_7 = mmio(Address + 0x0000002c, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESULT: u12, // bit offset: 4 desc: When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. - // RESERVED: u14, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - OVERRUN: u1, // bit offset: 30 desc: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. - DONE: u1, // bit offset: 31 desc: This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. - }); - // byte offset: 48 A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. - pub const STAT = mmio(Address + 0x00000030, 32, packed struct { - DONE0: u1, // bit offset: 0 desc: This bit mirrors the DONE status flag from the result register for A/D channel 0. - DONE1: u1, // bit offset: 1 desc: This bit mirrors the DONE status flag from the result register for A/D channel 1. - DONE2: u1, // bit offset: 2 desc: This bit mirrors the DONE status flag from the result register for A/D channel 2. - DONE3: u1, // bit offset: 3 desc: This bit mirrors the DONE status flag from the result register for A/D channel 3. - DONE4: u1, // bit offset: 4 desc: This bit mirrors the DONE status flag from the result register for A/D channel 4. - DONE5: u1, // bit offset: 5 desc: This bit mirrors the DONE status flag from the result register for A/D channel 5. - DONE6: u1, // bit offset: 6 desc: This bit mirrors the DONE status flag from the result register for A/D channel 6. - DONE7: u1, // bit offset: 7 desc: This bit mirrors the DONE status flag from the result register for A/D channel 7. - OVERRUN0: u1, // bit offset: 8 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. - OVERRUN1: u1, // bit offset: 9 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. - OVERRUN2: u1, // bit offset: 10 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. - OVERRUN3: u1, // bit offset: 11 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. - OVERRUN4: u1, // bit offset: 12 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. - OVERRUN5: u1, // bit offset: 13 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. - OVERRUN6: u1, // bit offset: 14 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. - OVERRUN7: u1, // bit offset: 15 desc: This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. - ADINT: u1, // bit offset: 16 desc: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. - // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 ADC trim register. - pub const TRM = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ADCOFFS: u4, // bit offset: 4 desc: Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. - TRIM: u4, // bit offset: 8 desc: written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const CANAFRAM = extern struct { - pub const Address: u32 = 0x40038000; - // byte offset: 0 CAN AF ram access register - pub const MASK_0 = mmio(Address + 0x00000000, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 4 CAN AF ram access register - pub const MASK_1 = mmio(Address + 0x00000004, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 8 CAN AF ram access register - pub const MASK_2 = mmio(Address + 0x00000008, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 12 CAN AF ram access register - pub const MASK_3 = mmio(Address + 0x0000000c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 16 CAN AF ram access register - pub const MASK_4 = mmio(Address + 0x00000010, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 20 CAN AF ram access register - pub const MASK_5 = mmio(Address + 0x00000014, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 24 CAN AF ram access register - pub const MASK_6 = mmio(Address + 0x00000018, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 28 CAN AF ram access register - pub const MASK_7 = mmio(Address + 0x0000001c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 32 CAN AF ram access register - pub const MASK_8 = mmio(Address + 0x00000020, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 36 CAN AF ram access register - pub const MASK_9 = mmio(Address + 0x00000024, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 40 CAN AF ram access register - pub const MASK_10 = mmio(Address + 0x00000028, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 44 CAN AF ram access register - pub const MASK_11 = mmio(Address + 0x0000002c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 48 CAN AF ram access register - pub const MASK_12 = mmio(Address + 0x00000030, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 52 CAN AF ram access register - pub const MASK_13 = mmio(Address + 0x00000034, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 56 CAN AF ram access register - pub const MASK_14 = mmio(Address + 0x00000038, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 60 CAN AF ram access register - pub const MASK_15 = mmio(Address + 0x0000003c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 64 CAN AF ram access register - pub const MASK_16 = mmio(Address + 0x00000040, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 68 CAN AF ram access register - pub const MASK_17 = mmio(Address + 0x00000044, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 72 CAN AF ram access register - pub const MASK_18 = mmio(Address + 0x00000048, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 76 CAN AF ram access register - pub const MASK_19 = mmio(Address + 0x0000004c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 80 CAN AF ram access register - pub const MASK_20 = mmio(Address + 0x00000050, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 84 CAN AF ram access register - pub const MASK_21 = mmio(Address + 0x00000054, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 88 CAN AF ram access register - pub const MASK_22 = mmio(Address + 0x00000058, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 92 CAN AF ram access register - pub const MASK_23 = mmio(Address + 0x0000005c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 96 CAN AF ram access register - pub const MASK_24 = mmio(Address + 0x00000060, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 100 CAN AF ram access register - pub const MASK_25 = mmio(Address + 0x00000064, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 104 CAN AF ram access register - pub const MASK_26 = mmio(Address + 0x00000068, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 108 CAN AF ram access register - pub const MASK_27 = mmio(Address + 0x0000006c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 112 CAN AF ram access register - pub const MASK_28 = mmio(Address + 0x00000070, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 116 CAN AF ram access register - pub const MASK_29 = mmio(Address + 0x00000074, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 120 CAN AF ram access register - pub const MASK_30 = mmio(Address + 0x00000078, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 124 CAN AF ram access register - pub const MASK_31 = mmio(Address + 0x0000007c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 128 CAN AF ram access register - pub const MASK_32 = mmio(Address + 0x00000080, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 132 CAN AF ram access register - pub const MASK_33 = mmio(Address + 0x00000084, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 136 CAN AF ram access register - pub const MASK_34 = mmio(Address + 0x00000088, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 140 CAN AF ram access register - pub const MASK_35 = mmio(Address + 0x0000008c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 144 CAN AF ram access register - pub const MASK_36 = mmio(Address + 0x00000090, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 148 CAN AF ram access register - pub const MASK_37 = mmio(Address + 0x00000094, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 152 CAN AF ram access register - pub const MASK_38 = mmio(Address + 0x00000098, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 156 CAN AF ram access register - pub const MASK_39 = mmio(Address + 0x0000009c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 160 CAN AF ram access register - pub const MASK_40 = mmio(Address + 0x000000a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 164 CAN AF ram access register - pub const MASK_41 = mmio(Address + 0x000000a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 168 CAN AF ram access register - pub const MASK_42 = mmio(Address + 0x000000a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 172 CAN AF ram access register - pub const MASK_43 = mmio(Address + 0x000000ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 176 CAN AF ram access register - pub const MASK_44 = mmio(Address + 0x000000b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 180 CAN AF ram access register - pub const MASK_45 = mmio(Address + 0x000000b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 184 CAN AF ram access register - pub const MASK_46 = mmio(Address + 0x000000b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 188 CAN AF ram access register - pub const MASK_47 = mmio(Address + 0x000000bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 192 CAN AF ram access register - pub const MASK_48 = mmio(Address + 0x000000c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 196 CAN AF ram access register - pub const MASK_49 = mmio(Address + 0x000000c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 200 CAN AF ram access register - pub const MASK_50 = mmio(Address + 0x000000c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 204 CAN AF ram access register - pub const MASK_51 = mmio(Address + 0x000000cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 208 CAN AF ram access register - pub const MASK_52 = mmio(Address + 0x000000d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 212 CAN AF ram access register - pub const MASK_53 = mmio(Address + 0x000000d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 216 CAN AF ram access register - pub const MASK_54 = mmio(Address + 0x000000d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 220 CAN AF ram access register - pub const MASK_55 = mmio(Address + 0x000000dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 224 CAN AF ram access register - pub const MASK_56 = mmio(Address + 0x000000e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 228 CAN AF ram access register - pub const MASK_57 = mmio(Address + 0x000000e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 232 CAN AF ram access register - pub const MASK_58 = mmio(Address + 0x000000e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 236 CAN AF ram access register - pub const MASK_59 = mmio(Address + 0x000000ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 240 CAN AF ram access register - pub const MASK_60 = mmio(Address + 0x000000f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 244 CAN AF ram access register - pub const MASK_61 = mmio(Address + 0x000000f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 248 CAN AF ram access register - pub const MASK_62 = mmio(Address + 0x000000f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 252 CAN AF ram access register - pub const MASK_63 = mmio(Address + 0x000000fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 256 CAN AF ram access register - pub const MASK_64 = mmio(Address + 0x00000100, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 260 CAN AF ram access register - pub const MASK_65 = mmio(Address + 0x00000104, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 264 CAN AF ram access register - pub const MASK_66 = mmio(Address + 0x00000108, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 268 CAN AF ram access register - pub const MASK_67 = mmio(Address + 0x0000010c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 272 CAN AF ram access register - pub const MASK_68 = mmio(Address + 0x00000110, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 276 CAN AF ram access register - pub const MASK_69 = mmio(Address + 0x00000114, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 280 CAN AF ram access register - pub const MASK_70 = mmio(Address + 0x00000118, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 284 CAN AF ram access register - pub const MASK_71 = mmio(Address + 0x0000011c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 288 CAN AF ram access register - pub const MASK_72 = mmio(Address + 0x00000120, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 292 CAN AF ram access register - pub const MASK_73 = mmio(Address + 0x00000124, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 296 CAN AF ram access register - pub const MASK_74 = mmio(Address + 0x00000128, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 300 CAN AF ram access register - pub const MASK_75 = mmio(Address + 0x0000012c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 304 CAN AF ram access register - pub const MASK_76 = mmio(Address + 0x00000130, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 308 CAN AF ram access register - pub const MASK_77 = mmio(Address + 0x00000134, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 312 CAN AF ram access register - pub const MASK_78 = mmio(Address + 0x00000138, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 316 CAN AF ram access register - pub const MASK_79 = mmio(Address + 0x0000013c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 320 CAN AF ram access register - pub const MASK_80 = mmio(Address + 0x00000140, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 324 CAN AF ram access register - pub const MASK_81 = mmio(Address + 0x00000144, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 328 CAN AF ram access register - pub const MASK_82 = mmio(Address + 0x00000148, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 332 CAN AF ram access register - pub const MASK_83 = mmio(Address + 0x0000014c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 336 CAN AF ram access register - pub const MASK_84 = mmio(Address + 0x00000150, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 340 CAN AF ram access register - pub const MASK_85 = mmio(Address + 0x00000154, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 344 CAN AF ram access register - pub const MASK_86 = mmio(Address + 0x00000158, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 348 CAN AF ram access register - pub const MASK_87 = mmio(Address + 0x0000015c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 352 CAN AF ram access register - pub const MASK_88 = mmio(Address + 0x00000160, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 356 CAN AF ram access register - pub const MASK_89 = mmio(Address + 0x00000164, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 360 CAN AF ram access register - pub const MASK_90 = mmio(Address + 0x00000168, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 364 CAN AF ram access register - pub const MASK_91 = mmio(Address + 0x0000016c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 368 CAN AF ram access register - pub const MASK_92 = mmio(Address + 0x00000170, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 372 CAN AF ram access register - pub const MASK_93 = mmio(Address + 0x00000174, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 376 CAN AF ram access register - pub const MASK_94 = mmio(Address + 0x00000178, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 380 CAN AF ram access register - pub const MASK_95 = mmio(Address + 0x0000017c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 384 CAN AF ram access register - pub const MASK_96 = mmio(Address + 0x00000180, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 388 CAN AF ram access register - pub const MASK_97 = mmio(Address + 0x00000184, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 392 CAN AF ram access register - pub const MASK_98 = mmio(Address + 0x00000188, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 396 CAN AF ram access register - pub const MASK_99 = mmio(Address + 0x0000018c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 400 CAN AF ram access register - pub const MASK_100 = mmio(Address + 0x00000190, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 404 CAN AF ram access register - pub const MASK_101 = mmio(Address + 0x00000194, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 408 CAN AF ram access register - pub const MASK_102 = mmio(Address + 0x00000198, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 412 CAN AF ram access register - pub const MASK_103 = mmio(Address + 0x0000019c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 416 CAN AF ram access register - pub const MASK_104 = mmio(Address + 0x000001a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 420 CAN AF ram access register - pub const MASK_105 = mmio(Address + 0x000001a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 424 CAN AF ram access register - pub const MASK_106 = mmio(Address + 0x000001a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 428 CAN AF ram access register - pub const MASK_107 = mmio(Address + 0x000001ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 432 CAN AF ram access register - pub const MASK_108 = mmio(Address + 0x000001b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 436 CAN AF ram access register - pub const MASK_109 = mmio(Address + 0x000001b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 440 CAN AF ram access register - pub const MASK_110 = mmio(Address + 0x000001b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 444 CAN AF ram access register - pub const MASK_111 = mmio(Address + 0x000001bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 448 CAN AF ram access register - pub const MASK_112 = mmio(Address + 0x000001c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 452 CAN AF ram access register - pub const MASK_113 = mmio(Address + 0x000001c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 456 CAN AF ram access register - pub const MASK_114 = mmio(Address + 0x000001c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 460 CAN AF ram access register - pub const MASK_115 = mmio(Address + 0x000001cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 464 CAN AF ram access register - pub const MASK_116 = mmio(Address + 0x000001d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 468 CAN AF ram access register - pub const MASK_117 = mmio(Address + 0x000001d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 472 CAN AF ram access register - pub const MASK_118 = mmio(Address + 0x000001d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 476 CAN AF ram access register - pub const MASK_119 = mmio(Address + 0x000001dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 480 CAN AF ram access register - pub const MASK_120 = mmio(Address + 0x000001e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 484 CAN AF ram access register - pub const MASK_121 = mmio(Address + 0x000001e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 488 CAN AF ram access register - pub const MASK_122 = mmio(Address + 0x000001e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 492 CAN AF ram access register - pub const MASK_123 = mmio(Address + 0x000001ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 496 CAN AF ram access register - pub const MASK_124 = mmio(Address + 0x000001f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 500 CAN AF ram access register - pub const MASK_125 = mmio(Address + 0x000001f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 504 CAN AF ram access register - pub const MASK_126 = mmio(Address + 0x000001f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 508 CAN AF ram access register - pub const MASK_127 = mmio(Address + 0x000001fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 512 CAN AF ram access register - pub const MASK_128 = mmio(Address + 0x00000200, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 516 CAN AF ram access register - pub const MASK_129 = mmio(Address + 0x00000204, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 520 CAN AF ram access register - pub const MASK_130 = mmio(Address + 0x00000208, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 524 CAN AF ram access register - pub const MASK_131 = mmio(Address + 0x0000020c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 528 CAN AF ram access register - pub const MASK_132 = mmio(Address + 0x00000210, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 532 CAN AF ram access register - pub const MASK_133 = mmio(Address + 0x00000214, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 536 CAN AF ram access register - pub const MASK_134 = mmio(Address + 0x00000218, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 540 CAN AF ram access register - pub const MASK_135 = mmio(Address + 0x0000021c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 544 CAN AF ram access register - pub const MASK_136 = mmio(Address + 0x00000220, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 548 CAN AF ram access register - pub const MASK_137 = mmio(Address + 0x00000224, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 552 CAN AF ram access register - pub const MASK_138 = mmio(Address + 0x00000228, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 556 CAN AF ram access register - pub const MASK_139 = mmio(Address + 0x0000022c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 560 CAN AF ram access register - pub const MASK_140 = mmio(Address + 0x00000230, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 564 CAN AF ram access register - pub const MASK_141 = mmio(Address + 0x00000234, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 568 CAN AF ram access register - pub const MASK_142 = mmio(Address + 0x00000238, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 572 CAN AF ram access register - pub const MASK_143 = mmio(Address + 0x0000023c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 576 CAN AF ram access register - pub const MASK_144 = mmio(Address + 0x00000240, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 580 CAN AF ram access register - pub const MASK_145 = mmio(Address + 0x00000244, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 584 CAN AF ram access register - pub const MASK_146 = mmio(Address + 0x00000248, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 588 CAN AF ram access register - pub const MASK_147 = mmio(Address + 0x0000024c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 592 CAN AF ram access register - pub const MASK_148 = mmio(Address + 0x00000250, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 596 CAN AF ram access register - pub const MASK_149 = mmio(Address + 0x00000254, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 600 CAN AF ram access register - pub const MASK_150 = mmio(Address + 0x00000258, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 604 CAN AF ram access register - pub const MASK_151 = mmio(Address + 0x0000025c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 608 CAN AF ram access register - pub const MASK_152 = mmio(Address + 0x00000260, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 612 CAN AF ram access register - pub const MASK_153 = mmio(Address + 0x00000264, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 616 CAN AF ram access register - pub const MASK_154 = mmio(Address + 0x00000268, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 620 CAN AF ram access register - pub const MASK_155 = mmio(Address + 0x0000026c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 624 CAN AF ram access register - pub const MASK_156 = mmio(Address + 0x00000270, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 628 CAN AF ram access register - pub const MASK_157 = mmio(Address + 0x00000274, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 632 CAN AF ram access register - pub const MASK_158 = mmio(Address + 0x00000278, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 636 CAN AF ram access register - pub const MASK_159 = mmio(Address + 0x0000027c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 640 CAN AF ram access register - pub const MASK_160 = mmio(Address + 0x00000280, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 644 CAN AF ram access register - pub const MASK_161 = mmio(Address + 0x00000284, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 648 CAN AF ram access register - pub const MASK_162 = mmio(Address + 0x00000288, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 652 CAN AF ram access register - pub const MASK_163 = mmio(Address + 0x0000028c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 656 CAN AF ram access register - pub const MASK_164 = mmio(Address + 0x00000290, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 660 CAN AF ram access register - pub const MASK_165 = mmio(Address + 0x00000294, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 664 CAN AF ram access register - pub const MASK_166 = mmio(Address + 0x00000298, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 668 CAN AF ram access register - pub const MASK_167 = mmio(Address + 0x0000029c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 672 CAN AF ram access register - pub const MASK_168 = mmio(Address + 0x000002a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 676 CAN AF ram access register - pub const MASK_169 = mmio(Address + 0x000002a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 680 CAN AF ram access register - pub const MASK_170 = mmio(Address + 0x000002a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 684 CAN AF ram access register - pub const MASK_171 = mmio(Address + 0x000002ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 688 CAN AF ram access register - pub const MASK_172 = mmio(Address + 0x000002b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 692 CAN AF ram access register - pub const MASK_173 = mmio(Address + 0x000002b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 696 CAN AF ram access register - pub const MASK_174 = mmio(Address + 0x000002b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 700 CAN AF ram access register - pub const MASK_175 = mmio(Address + 0x000002bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 704 CAN AF ram access register - pub const MASK_176 = mmio(Address + 0x000002c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 708 CAN AF ram access register - pub const MASK_177 = mmio(Address + 0x000002c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 712 CAN AF ram access register - pub const MASK_178 = mmio(Address + 0x000002c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 716 CAN AF ram access register - pub const MASK_179 = mmio(Address + 0x000002cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 720 CAN AF ram access register - pub const MASK_180 = mmio(Address + 0x000002d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 724 CAN AF ram access register - pub const MASK_181 = mmio(Address + 0x000002d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 728 CAN AF ram access register - pub const MASK_182 = mmio(Address + 0x000002d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 732 CAN AF ram access register - pub const MASK_183 = mmio(Address + 0x000002dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 736 CAN AF ram access register - pub const MASK_184 = mmio(Address + 0x000002e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 740 CAN AF ram access register - pub const MASK_185 = mmio(Address + 0x000002e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 744 CAN AF ram access register - pub const MASK_186 = mmio(Address + 0x000002e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 748 CAN AF ram access register - pub const MASK_187 = mmio(Address + 0x000002ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 752 CAN AF ram access register - pub const MASK_188 = mmio(Address + 0x000002f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 756 CAN AF ram access register - pub const MASK_189 = mmio(Address + 0x000002f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 760 CAN AF ram access register - pub const MASK_190 = mmio(Address + 0x000002f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 764 CAN AF ram access register - pub const MASK_191 = mmio(Address + 0x000002fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 768 CAN AF ram access register - pub const MASK_192 = mmio(Address + 0x00000300, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 772 CAN AF ram access register - pub const MASK_193 = mmio(Address + 0x00000304, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 776 CAN AF ram access register - pub const MASK_194 = mmio(Address + 0x00000308, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 780 CAN AF ram access register - pub const MASK_195 = mmio(Address + 0x0000030c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 784 CAN AF ram access register - pub const MASK_196 = mmio(Address + 0x00000310, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 788 CAN AF ram access register - pub const MASK_197 = mmio(Address + 0x00000314, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 792 CAN AF ram access register - pub const MASK_198 = mmio(Address + 0x00000318, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 796 CAN AF ram access register - pub const MASK_199 = mmio(Address + 0x0000031c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 800 CAN AF ram access register - pub const MASK_200 = mmio(Address + 0x00000320, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 804 CAN AF ram access register - pub const MASK_201 = mmio(Address + 0x00000324, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 808 CAN AF ram access register - pub const MASK_202 = mmio(Address + 0x00000328, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 812 CAN AF ram access register - pub const MASK_203 = mmio(Address + 0x0000032c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 816 CAN AF ram access register - pub const MASK_204 = mmio(Address + 0x00000330, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 820 CAN AF ram access register - pub const MASK_205 = mmio(Address + 0x00000334, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 824 CAN AF ram access register - pub const MASK_206 = mmio(Address + 0x00000338, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 828 CAN AF ram access register - pub const MASK_207 = mmio(Address + 0x0000033c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 832 CAN AF ram access register - pub const MASK_208 = mmio(Address + 0x00000340, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 836 CAN AF ram access register - pub const MASK_209 = mmio(Address + 0x00000344, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 840 CAN AF ram access register - pub const MASK_210 = mmio(Address + 0x00000348, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 844 CAN AF ram access register - pub const MASK_211 = mmio(Address + 0x0000034c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 848 CAN AF ram access register - pub const MASK_212 = mmio(Address + 0x00000350, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 852 CAN AF ram access register - pub const MASK_213 = mmio(Address + 0x00000354, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 856 CAN AF ram access register - pub const MASK_214 = mmio(Address + 0x00000358, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 860 CAN AF ram access register - pub const MASK_215 = mmio(Address + 0x0000035c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 864 CAN AF ram access register - pub const MASK_216 = mmio(Address + 0x00000360, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 868 CAN AF ram access register - pub const MASK_217 = mmio(Address + 0x00000364, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 872 CAN AF ram access register - pub const MASK_218 = mmio(Address + 0x00000368, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 876 CAN AF ram access register - pub const MASK_219 = mmio(Address + 0x0000036c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 880 CAN AF ram access register - pub const MASK_220 = mmio(Address + 0x00000370, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 884 CAN AF ram access register - pub const MASK_221 = mmio(Address + 0x00000374, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 888 CAN AF ram access register - pub const MASK_222 = mmio(Address + 0x00000378, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 892 CAN AF ram access register - pub const MASK_223 = mmio(Address + 0x0000037c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 896 CAN AF ram access register - pub const MASK_224 = mmio(Address + 0x00000380, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 900 CAN AF ram access register - pub const MASK_225 = mmio(Address + 0x00000384, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 904 CAN AF ram access register - pub const MASK_226 = mmio(Address + 0x00000388, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 908 CAN AF ram access register - pub const MASK_227 = mmio(Address + 0x0000038c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 912 CAN AF ram access register - pub const MASK_228 = mmio(Address + 0x00000390, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 916 CAN AF ram access register - pub const MASK_229 = mmio(Address + 0x00000394, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 920 CAN AF ram access register - pub const MASK_230 = mmio(Address + 0x00000398, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 924 CAN AF ram access register - pub const MASK_231 = mmio(Address + 0x0000039c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 928 CAN AF ram access register - pub const MASK_232 = mmio(Address + 0x000003a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 932 CAN AF ram access register - pub const MASK_233 = mmio(Address + 0x000003a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 936 CAN AF ram access register - pub const MASK_234 = mmio(Address + 0x000003a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 940 CAN AF ram access register - pub const MASK_235 = mmio(Address + 0x000003ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 944 CAN AF ram access register - pub const MASK_236 = mmio(Address + 0x000003b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 948 CAN AF ram access register - pub const MASK_237 = mmio(Address + 0x000003b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 952 CAN AF ram access register - pub const MASK_238 = mmio(Address + 0x000003b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 956 CAN AF ram access register - pub const MASK_239 = mmio(Address + 0x000003bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 960 CAN AF ram access register - pub const MASK_240 = mmio(Address + 0x000003c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 964 CAN AF ram access register - pub const MASK_241 = mmio(Address + 0x000003c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 968 CAN AF ram access register - pub const MASK_242 = mmio(Address + 0x000003c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 972 CAN AF ram access register - pub const MASK_243 = mmio(Address + 0x000003cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 976 CAN AF ram access register - pub const MASK_244 = mmio(Address + 0x000003d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 980 CAN AF ram access register - pub const MASK_245 = mmio(Address + 0x000003d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 984 CAN AF ram access register - pub const MASK_246 = mmio(Address + 0x000003d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 988 CAN AF ram access register - pub const MASK_247 = mmio(Address + 0x000003dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 992 CAN AF ram access register - pub const MASK_248 = mmio(Address + 0x000003e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 996 CAN AF ram access register - pub const MASK_249 = mmio(Address + 0x000003e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1000 CAN AF ram access register - pub const MASK_250 = mmio(Address + 0x000003e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1004 CAN AF ram access register - pub const MASK_251 = mmio(Address + 0x000003ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1008 CAN AF ram access register - pub const MASK_252 = mmio(Address + 0x000003f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1012 CAN AF ram access register - pub const MASK_253 = mmio(Address + 0x000003f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1016 CAN AF ram access register - pub const MASK_254 = mmio(Address + 0x000003f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1020 CAN AF ram access register - pub const MASK_255 = mmio(Address + 0x000003fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1024 CAN AF ram access register - pub const MASK_256 = mmio(Address + 0x00000400, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1028 CAN AF ram access register - pub const MASK_257 = mmio(Address + 0x00000404, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1032 CAN AF ram access register - pub const MASK_258 = mmio(Address + 0x00000408, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1036 CAN AF ram access register - pub const MASK_259 = mmio(Address + 0x0000040c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1040 CAN AF ram access register - pub const MASK_260 = mmio(Address + 0x00000410, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1044 CAN AF ram access register - pub const MASK_261 = mmio(Address + 0x00000414, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1048 CAN AF ram access register - pub const MASK_262 = mmio(Address + 0x00000418, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1052 CAN AF ram access register - pub const MASK_263 = mmio(Address + 0x0000041c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1056 CAN AF ram access register - pub const MASK_264 = mmio(Address + 0x00000420, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1060 CAN AF ram access register - pub const MASK_265 = mmio(Address + 0x00000424, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1064 CAN AF ram access register - pub const MASK_266 = mmio(Address + 0x00000428, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1068 CAN AF ram access register - pub const MASK_267 = mmio(Address + 0x0000042c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1072 CAN AF ram access register - pub const MASK_268 = mmio(Address + 0x00000430, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1076 CAN AF ram access register - pub const MASK_269 = mmio(Address + 0x00000434, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1080 CAN AF ram access register - pub const MASK_270 = mmio(Address + 0x00000438, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1084 CAN AF ram access register - pub const MASK_271 = mmio(Address + 0x0000043c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1088 CAN AF ram access register - pub const MASK_272 = mmio(Address + 0x00000440, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1092 CAN AF ram access register - pub const MASK_273 = mmio(Address + 0x00000444, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1096 CAN AF ram access register - pub const MASK_274 = mmio(Address + 0x00000448, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1100 CAN AF ram access register - pub const MASK_275 = mmio(Address + 0x0000044c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1104 CAN AF ram access register - pub const MASK_276 = mmio(Address + 0x00000450, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1108 CAN AF ram access register - pub const MASK_277 = mmio(Address + 0x00000454, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1112 CAN AF ram access register - pub const MASK_278 = mmio(Address + 0x00000458, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1116 CAN AF ram access register - pub const MASK_279 = mmio(Address + 0x0000045c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1120 CAN AF ram access register - pub const MASK_280 = mmio(Address + 0x00000460, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1124 CAN AF ram access register - pub const MASK_281 = mmio(Address + 0x00000464, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1128 CAN AF ram access register - pub const MASK_282 = mmio(Address + 0x00000468, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1132 CAN AF ram access register - pub const MASK_283 = mmio(Address + 0x0000046c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1136 CAN AF ram access register - pub const MASK_284 = mmio(Address + 0x00000470, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1140 CAN AF ram access register - pub const MASK_285 = mmio(Address + 0x00000474, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1144 CAN AF ram access register - pub const MASK_286 = mmio(Address + 0x00000478, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1148 CAN AF ram access register - pub const MASK_287 = mmio(Address + 0x0000047c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1152 CAN AF ram access register - pub const MASK_288 = mmio(Address + 0x00000480, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1156 CAN AF ram access register - pub const MASK_289 = mmio(Address + 0x00000484, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1160 CAN AF ram access register - pub const MASK_290 = mmio(Address + 0x00000488, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1164 CAN AF ram access register - pub const MASK_291 = mmio(Address + 0x0000048c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1168 CAN AF ram access register - pub const MASK_292 = mmio(Address + 0x00000490, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1172 CAN AF ram access register - pub const MASK_293 = mmio(Address + 0x00000494, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1176 CAN AF ram access register - pub const MASK_294 = mmio(Address + 0x00000498, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1180 CAN AF ram access register - pub const MASK_295 = mmio(Address + 0x0000049c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1184 CAN AF ram access register - pub const MASK_296 = mmio(Address + 0x000004a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1188 CAN AF ram access register - pub const MASK_297 = mmio(Address + 0x000004a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1192 CAN AF ram access register - pub const MASK_298 = mmio(Address + 0x000004a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1196 CAN AF ram access register - pub const MASK_299 = mmio(Address + 0x000004ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1200 CAN AF ram access register - pub const MASK_300 = mmio(Address + 0x000004b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1204 CAN AF ram access register - pub const MASK_301 = mmio(Address + 0x000004b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1208 CAN AF ram access register - pub const MASK_302 = mmio(Address + 0x000004b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1212 CAN AF ram access register - pub const MASK_303 = mmio(Address + 0x000004bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1216 CAN AF ram access register - pub const MASK_304 = mmio(Address + 0x000004c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1220 CAN AF ram access register - pub const MASK_305 = mmio(Address + 0x000004c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1224 CAN AF ram access register - pub const MASK_306 = mmio(Address + 0x000004c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1228 CAN AF ram access register - pub const MASK_307 = mmio(Address + 0x000004cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1232 CAN AF ram access register - pub const MASK_308 = mmio(Address + 0x000004d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1236 CAN AF ram access register - pub const MASK_309 = mmio(Address + 0x000004d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1240 CAN AF ram access register - pub const MASK_310 = mmio(Address + 0x000004d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1244 CAN AF ram access register - pub const MASK_311 = mmio(Address + 0x000004dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1248 CAN AF ram access register - pub const MASK_312 = mmio(Address + 0x000004e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1252 CAN AF ram access register - pub const MASK_313 = mmio(Address + 0x000004e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1256 CAN AF ram access register - pub const MASK_314 = mmio(Address + 0x000004e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1260 CAN AF ram access register - pub const MASK_315 = mmio(Address + 0x000004ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1264 CAN AF ram access register - pub const MASK_316 = mmio(Address + 0x000004f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1268 CAN AF ram access register - pub const MASK_317 = mmio(Address + 0x000004f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1272 CAN AF ram access register - pub const MASK_318 = mmio(Address + 0x000004f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1276 CAN AF ram access register - pub const MASK_319 = mmio(Address + 0x000004fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1280 CAN AF ram access register - pub const MASK_320 = mmio(Address + 0x00000500, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1284 CAN AF ram access register - pub const MASK_321 = mmio(Address + 0x00000504, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1288 CAN AF ram access register - pub const MASK_322 = mmio(Address + 0x00000508, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1292 CAN AF ram access register - pub const MASK_323 = mmio(Address + 0x0000050c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1296 CAN AF ram access register - pub const MASK_324 = mmio(Address + 0x00000510, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1300 CAN AF ram access register - pub const MASK_325 = mmio(Address + 0x00000514, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1304 CAN AF ram access register - pub const MASK_326 = mmio(Address + 0x00000518, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1308 CAN AF ram access register - pub const MASK_327 = mmio(Address + 0x0000051c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1312 CAN AF ram access register - pub const MASK_328 = mmio(Address + 0x00000520, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1316 CAN AF ram access register - pub const MASK_329 = mmio(Address + 0x00000524, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1320 CAN AF ram access register - pub const MASK_330 = mmio(Address + 0x00000528, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1324 CAN AF ram access register - pub const MASK_331 = mmio(Address + 0x0000052c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1328 CAN AF ram access register - pub const MASK_332 = mmio(Address + 0x00000530, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1332 CAN AF ram access register - pub const MASK_333 = mmio(Address + 0x00000534, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1336 CAN AF ram access register - pub const MASK_334 = mmio(Address + 0x00000538, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1340 CAN AF ram access register - pub const MASK_335 = mmio(Address + 0x0000053c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1344 CAN AF ram access register - pub const MASK_336 = mmio(Address + 0x00000540, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1348 CAN AF ram access register - pub const MASK_337 = mmio(Address + 0x00000544, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1352 CAN AF ram access register - pub const MASK_338 = mmio(Address + 0x00000548, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1356 CAN AF ram access register - pub const MASK_339 = mmio(Address + 0x0000054c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1360 CAN AF ram access register - pub const MASK_340 = mmio(Address + 0x00000550, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1364 CAN AF ram access register - pub const MASK_341 = mmio(Address + 0x00000554, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1368 CAN AF ram access register - pub const MASK_342 = mmio(Address + 0x00000558, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1372 CAN AF ram access register - pub const MASK_343 = mmio(Address + 0x0000055c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1376 CAN AF ram access register - pub const MASK_344 = mmio(Address + 0x00000560, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1380 CAN AF ram access register - pub const MASK_345 = mmio(Address + 0x00000564, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1384 CAN AF ram access register - pub const MASK_346 = mmio(Address + 0x00000568, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1388 CAN AF ram access register - pub const MASK_347 = mmio(Address + 0x0000056c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1392 CAN AF ram access register - pub const MASK_348 = mmio(Address + 0x00000570, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1396 CAN AF ram access register - pub const MASK_349 = mmio(Address + 0x00000574, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1400 CAN AF ram access register - pub const MASK_350 = mmio(Address + 0x00000578, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1404 CAN AF ram access register - pub const MASK_351 = mmio(Address + 0x0000057c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1408 CAN AF ram access register - pub const MASK_352 = mmio(Address + 0x00000580, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1412 CAN AF ram access register - pub const MASK_353 = mmio(Address + 0x00000584, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1416 CAN AF ram access register - pub const MASK_354 = mmio(Address + 0x00000588, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1420 CAN AF ram access register - pub const MASK_355 = mmio(Address + 0x0000058c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1424 CAN AF ram access register - pub const MASK_356 = mmio(Address + 0x00000590, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1428 CAN AF ram access register - pub const MASK_357 = mmio(Address + 0x00000594, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1432 CAN AF ram access register - pub const MASK_358 = mmio(Address + 0x00000598, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1436 CAN AF ram access register - pub const MASK_359 = mmio(Address + 0x0000059c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1440 CAN AF ram access register - pub const MASK_360 = mmio(Address + 0x000005a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1444 CAN AF ram access register - pub const MASK_361 = mmio(Address + 0x000005a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1448 CAN AF ram access register - pub const MASK_362 = mmio(Address + 0x000005a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1452 CAN AF ram access register - pub const MASK_363 = mmio(Address + 0x000005ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1456 CAN AF ram access register - pub const MASK_364 = mmio(Address + 0x000005b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1460 CAN AF ram access register - pub const MASK_365 = mmio(Address + 0x000005b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1464 CAN AF ram access register - pub const MASK_366 = mmio(Address + 0x000005b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1468 CAN AF ram access register - pub const MASK_367 = mmio(Address + 0x000005bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1472 CAN AF ram access register - pub const MASK_368 = mmio(Address + 0x000005c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1476 CAN AF ram access register - pub const MASK_369 = mmio(Address + 0x000005c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1480 CAN AF ram access register - pub const MASK_370 = mmio(Address + 0x000005c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1484 CAN AF ram access register - pub const MASK_371 = mmio(Address + 0x000005cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1488 CAN AF ram access register - pub const MASK_372 = mmio(Address + 0x000005d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1492 CAN AF ram access register - pub const MASK_373 = mmio(Address + 0x000005d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1496 CAN AF ram access register - pub const MASK_374 = mmio(Address + 0x000005d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1500 CAN AF ram access register - pub const MASK_375 = mmio(Address + 0x000005dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1504 CAN AF ram access register - pub const MASK_376 = mmio(Address + 0x000005e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1508 CAN AF ram access register - pub const MASK_377 = mmio(Address + 0x000005e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1512 CAN AF ram access register - pub const MASK_378 = mmio(Address + 0x000005e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1516 CAN AF ram access register - pub const MASK_379 = mmio(Address + 0x000005ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1520 CAN AF ram access register - pub const MASK_380 = mmio(Address + 0x000005f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1524 CAN AF ram access register - pub const MASK_381 = mmio(Address + 0x000005f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1528 CAN AF ram access register - pub const MASK_382 = mmio(Address + 0x000005f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1532 CAN AF ram access register - pub const MASK_383 = mmio(Address + 0x000005fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1536 CAN AF ram access register - pub const MASK_384 = mmio(Address + 0x00000600, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1540 CAN AF ram access register - pub const MASK_385 = mmio(Address + 0x00000604, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1544 CAN AF ram access register - pub const MASK_386 = mmio(Address + 0x00000608, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1548 CAN AF ram access register - pub const MASK_387 = mmio(Address + 0x0000060c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1552 CAN AF ram access register - pub const MASK_388 = mmio(Address + 0x00000610, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1556 CAN AF ram access register - pub const MASK_389 = mmio(Address + 0x00000614, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1560 CAN AF ram access register - pub const MASK_390 = mmio(Address + 0x00000618, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1564 CAN AF ram access register - pub const MASK_391 = mmio(Address + 0x0000061c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1568 CAN AF ram access register - pub const MASK_392 = mmio(Address + 0x00000620, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1572 CAN AF ram access register - pub const MASK_393 = mmio(Address + 0x00000624, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1576 CAN AF ram access register - pub const MASK_394 = mmio(Address + 0x00000628, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1580 CAN AF ram access register - pub const MASK_395 = mmio(Address + 0x0000062c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1584 CAN AF ram access register - pub const MASK_396 = mmio(Address + 0x00000630, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1588 CAN AF ram access register - pub const MASK_397 = mmio(Address + 0x00000634, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1592 CAN AF ram access register - pub const MASK_398 = mmio(Address + 0x00000638, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1596 CAN AF ram access register - pub const MASK_399 = mmio(Address + 0x0000063c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1600 CAN AF ram access register - pub const MASK_400 = mmio(Address + 0x00000640, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1604 CAN AF ram access register - pub const MASK_401 = mmio(Address + 0x00000644, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1608 CAN AF ram access register - pub const MASK_402 = mmio(Address + 0x00000648, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1612 CAN AF ram access register - pub const MASK_403 = mmio(Address + 0x0000064c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1616 CAN AF ram access register - pub const MASK_404 = mmio(Address + 0x00000650, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1620 CAN AF ram access register - pub const MASK_405 = mmio(Address + 0x00000654, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1624 CAN AF ram access register - pub const MASK_406 = mmio(Address + 0x00000658, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1628 CAN AF ram access register - pub const MASK_407 = mmio(Address + 0x0000065c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1632 CAN AF ram access register - pub const MASK_408 = mmio(Address + 0x00000660, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1636 CAN AF ram access register - pub const MASK_409 = mmio(Address + 0x00000664, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1640 CAN AF ram access register - pub const MASK_410 = mmio(Address + 0x00000668, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1644 CAN AF ram access register - pub const MASK_411 = mmio(Address + 0x0000066c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1648 CAN AF ram access register - pub const MASK_412 = mmio(Address + 0x00000670, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1652 CAN AF ram access register - pub const MASK_413 = mmio(Address + 0x00000674, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1656 CAN AF ram access register - pub const MASK_414 = mmio(Address + 0x00000678, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1660 CAN AF ram access register - pub const MASK_415 = mmio(Address + 0x0000067c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1664 CAN AF ram access register - pub const MASK_416 = mmio(Address + 0x00000680, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1668 CAN AF ram access register - pub const MASK_417 = mmio(Address + 0x00000684, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1672 CAN AF ram access register - pub const MASK_418 = mmio(Address + 0x00000688, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1676 CAN AF ram access register - pub const MASK_419 = mmio(Address + 0x0000068c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1680 CAN AF ram access register - pub const MASK_420 = mmio(Address + 0x00000690, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1684 CAN AF ram access register - pub const MASK_421 = mmio(Address + 0x00000694, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1688 CAN AF ram access register - pub const MASK_422 = mmio(Address + 0x00000698, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1692 CAN AF ram access register - pub const MASK_423 = mmio(Address + 0x0000069c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1696 CAN AF ram access register - pub const MASK_424 = mmio(Address + 0x000006a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1700 CAN AF ram access register - pub const MASK_425 = mmio(Address + 0x000006a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1704 CAN AF ram access register - pub const MASK_426 = mmio(Address + 0x000006a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1708 CAN AF ram access register - pub const MASK_427 = mmio(Address + 0x000006ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1712 CAN AF ram access register - pub const MASK_428 = mmio(Address + 0x000006b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1716 CAN AF ram access register - pub const MASK_429 = mmio(Address + 0x000006b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1720 CAN AF ram access register - pub const MASK_430 = mmio(Address + 0x000006b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1724 CAN AF ram access register - pub const MASK_431 = mmio(Address + 0x000006bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1728 CAN AF ram access register - pub const MASK_432 = mmio(Address + 0x000006c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1732 CAN AF ram access register - pub const MASK_433 = mmio(Address + 0x000006c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1736 CAN AF ram access register - pub const MASK_434 = mmio(Address + 0x000006c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1740 CAN AF ram access register - pub const MASK_435 = mmio(Address + 0x000006cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1744 CAN AF ram access register - pub const MASK_436 = mmio(Address + 0x000006d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1748 CAN AF ram access register - pub const MASK_437 = mmio(Address + 0x000006d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1752 CAN AF ram access register - pub const MASK_438 = mmio(Address + 0x000006d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1756 CAN AF ram access register - pub const MASK_439 = mmio(Address + 0x000006dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1760 CAN AF ram access register - pub const MASK_440 = mmio(Address + 0x000006e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1764 CAN AF ram access register - pub const MASK_441 = mmio(Address + 0x000006e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1768 CAN AF ram access register - pub const MASK_442 = mmio(Address + 0x000006e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1772 CAN AF ram access register - pub const MASK_443 = mmio(Address + 0x000006ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1776 CAN AF ram access register - pub const MASK_444 = mmio(Address + 0x000006f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1780 CAN AF ram access register - pub const MASK_445 = mmio(Address + 0x000006f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1784 CAN AF ram access register - pub const MASK_446 = mmio(Address + 0x000006f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1788 CAN AF ram access register - pub const MASK_447 = mmio(Address + 0x000006fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1792 CAN AF ram access register - pub const MASK_448 = mmio(Address + 0x00000700, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1796 CAN AF ram access register - pub const MASK_449 = mmio(Address + 0x00000704, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1800 CAN AF ram access register - pub const MASK_450 = mmio(Address + 0x00000708, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1804 CAN AF ram access register - pub const MASK_451 = mmio(Address + 0x0000070c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1808 CAN AF ram access register - pub const MASK_452 = mmio(Address + 0x00000710, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1812 CAN AF ram access register - pub const MASK_453 = mmio(Address + 0x00000714, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1816 CAN AF ram access register - pub const MASK_454 = mmio(Address + 0x00000718, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1820 CAN AF ram access register - pub const MASK_455 = mmio(Address + 0x0000071c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1824 CAN AF ram access register - pub const MASK_456 = mmio(Address + 0x00000720, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1828 CAN AF ram access register - pub const MASK_457 = mmio(Address + 0x00000724, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1832 CAN AF ram access register - pub const MASK_458 = mmio(Address + 0x00000728, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1836 CAN AF ram access register - pub const MASK_459 = mmio(Address + 0x0000072c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1840 CAN AF ram access register - pub const MASK_460 = mmio(Address + 0x00000730, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1844 CAN AF ram access register - pub const MASK_461 = mmio(Address + 0x00000734, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1848 CAN AF ram access register - pub const MASK_462 = mmio(Address + 0x00000738, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1852 CAN AF ram access register - pub const MASK_463 = mmio(Address + 0x0000073c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1856 CAN AF ram access register - pub const MASK_464 = mmio(Address + 0x00000740, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1860 CAN AF ram access register - pub const MASK_465 = mmio(Address + 0x00000744, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1864 CAN AF ram access register - pub const MASK_466 = mmio(Address + 0x00000748, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1868 CAN AF ram access register - pub const MASK_467 = mmio(Address + 0x0000074c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1872 CAN AF ram access register - pub const MASK_468 = mmio(Address + 0x00000750, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1876 CAN AF ram access register - pub const MASK_469 = mmio(Address + 0x00000754, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1880 CAN AF ram access register - pub const MASK_470 = mmio(Address + 0x00000758, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1884 CAN AF ram access register - pub const MASK_471 = mmio(Address + 0x0000075c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1888 CAN AF ram access register - pub const MASK_472 = mmio(Address + 0x00000760, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1892 CAN AF ram access register - pub const MASK_473 = mmio(Address + 0x00000764, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1896 CAN AF ram access register - pub const MASK_474 = mmio(Address + 0x00000768, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1900 CAN AF ram access register - pub const MASK_475 = mmio(Address + 0x0000076c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1904 CAN AF ram access register - pub const MASK_476 = mmio(Address + 0x00000770, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1908 CAN AF ram access register - pub const MASK_477 = mmio(Address + 0x00000774, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1912 CAN AF ram access register - pub const MASK_478 = mmio(Address + 0x00000778, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1916 CAN AF ram access register - pub const MASK_479 = mmio(Address + 0x0000077c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1920 CAN AF ram access register - pub const MASK_480 = mmio(Address + 0x00000780, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1924 CAN AF ram access register - pub const MASK_481 = mmio(Address + 0x00000784, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1928 CAN AF ram access register - pub const MASK_482 = mmio(Address + 0x00000788, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1932 CAN AF ram access register - pub const MASK_483 = mmio(Address + 0x0000078c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1936 CAN AF ram access register - pub const MASK_484 = mmio(Address + 0x00000790, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1940 CAN AF ram access register - pub const MASK_485 = mmio(Address + 0x00000794, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1944 CAN AF ram access register - pub const MASK_486 = mmio(Address + 0x00000798, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1948 CAN AF ram access register - pub const MASK_487 = mmio(Address + 0x0000079c, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1952 CAN AF ram access register - pub const MASK_488 = mmio(Address + 0x000007a0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1956 CAN AF ram access register - pub const MASK_489 = mmio(Address + 0x000007a4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1960 CAN AF ram access register - pub const MASK_490 = mmio(Address + 0x000007a8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1964 CAN AF ram access register - pub const MASK_491 = mmio(Address + 0x000007ac, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1968 CAN AF ram access register - pub const MASK_492 = mmio(Address + 0x000007b0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1972 CAN AF ram access register - pub const MASK_493 = mmio(Address + 0x000007b4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1976 CAN AF ram access register - pub const MASK_494 = mmio(Address + 0x000007b8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1980 CAN AF ram access register - pub const MASK_495 = mmio(Address + 0x000007bc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1984 CAN AF ram access register - pub const MASK_496 = mmio(Address + 0x000007c0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1988 CAN AF ram access register - pub const MASK_497 = mmio(Address + 0x000007c4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1992 CAN AF ram access register - pub const MASK_498 = mmio(Address + 0x000007c8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 1996 CAN AF ram access register - pub const MASK_499 = mmio(Address + 0x000007cc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2000 CAN AF ram access register - pub const MASK_500 = mmio(Address + 0x000007d0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2004 CAN AF ram access register - pub const MASK_501 = mmio(Address + 0x000007d4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2008 CAN AF ram access register - pub const MASK_502 = mmio(Address + 0x000007d8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2012 CAN AF ram access register - pub const MASK_503 = mmio(Address + 0x000007dc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2016 CAN AF ram access register - pub const MASK_504 = mmio(Address + 0x000007e0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2020 CAN AF ram access register - pub const MASK_505 = mmio(Address + 0x000007e4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2024 CAN AF ram access register - pub const MASK_506 = mmio(Address + 0x000007e8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2028 CAN AF ram access register - pub const MASK_507 = mmio(Address + 0x000007ec, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2032 CAN AF ram access register - pub const MASK_508 = mmio(Address + 0x000007f0, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2036 CAN AF ram access register - pub const MASK_509 = mmio(Address + 0x000007f4, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2040 CAN AF ram access register - pub const MASK_510 = mmio(Address + 0x000007f8, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); - // byte offset: 2044 CAN AF ram access register - pub const MASK_511 = mmio(Address + 0x000007fc, 32, packed struct { - MASK: u32, // bit offset: 0 desc: CAN AF RAM mask - }); -}; -pub const CANAF = extern struct { - pub const Address: u32 = 0x4003c000; - // byte offset: 0 Acceptance Filter Register - pub const AFMR = mmio(Address + 0x00000000, 32, packed struct { - ACCOFF: u1, // bit offset: 0 desc: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. - ACCBP: u1, // bit offset: 1 desc: All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. - EFCAN: enum(u1) { // bit offset: 2 desc: FullCAN mode - @"SOFTWARE_MUST_READ_A" = 0, // desc: Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers. - @"THE_ACCEPTANCE_FILTE" = 1, // desc: The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Standard Frame Individual Start Address Register - pub const SFF_SA = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - SFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Standard Frame Group Start Address Register - pub const SFF_GRP_SA = mmio(Address + 0x00000008, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - SFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Extended Frame Start Address Register - pub const EFF_SA = mmio(Address + 0x0000000c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - EFF_SA: u9, // bit offset: 2 desc: The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Extended Frame Group Start Address Register - pub const EFF_GRP_SA = mmio(Address + 0x00000010, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - EFF_GRP_SA: u10, // bit offset: 2 desc: The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 End of AF Tables register - pub const ENDOFTABLE = mmio(Address + 0x00000014, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - ENDOFTABLE: u10, // bit offset: 2 desc: The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 LUT Error Address register - pub const LUTERRAD = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - LUTERRAD: u9, // bit offset: 2 desc: It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 LUT Error Register - pub const LUTERR = mmio(Address + 0x0000001c, 32, packed struct { - LUTERR: u1, // bit offset: 0 desc: This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. - // RESERVED: u31, // bit offset: 1 desc: Reserved, the value read from a reserved bit is not defined. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 FullCAN interrupt enable register - pub const FCANIE = mmio(Address + 0x00000020, 32, packed struct { - FCANIE: u1, // bit offset: 0 desc: Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. - // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 FullCAN interrupt and capture register0 - pub const FCANIC0 = mmio(Address + 0x00000024, 32, packed struct { - INTPND: u32, // bit offset: 0 desc: FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. - }); - // byte offset: 40 FullCAN interrupt and capture register1 - pub const FCANIC1 = mmio(Address + 0x00000028, 32, packed struct { - IntPnd32: u32, // bit offset: 0 desc: FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. - }); -}; -pub const CCAN = extern struct { - pub const Address: u32 = 0x40040000; - // byte offset: 0 CAN Central Transmit Status Register - pub const TXSR = mmio(Address + 0x00000000, 32, packed struct { - TS1: u1, // bit offset: 0 desc: When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). - TS2: u1, // bit offset: 1 desc: When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TBS1: u1, // bit offset: 8 desc: When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). - TBS2: u1, // bit offset: 9 desc: When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). - // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TCS1: u1, // bit offset: 16 desc: When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). - TCS2: u1, // bit offset: 17 desc: When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). - // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 CAN Central Receive Status Register - pub const RXSR = mmio(Address + 0x00000004, 32, packed struct { - RS1: u1, // bit offset: 0 desc: When 1, CAN1 is receiving a message (same as RS in CAN1GSR). - RS2: u1, // bit offset: 1 desc: When 1, CAN2 is receiving a message (same as RS in CAN2GSR). - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RB1: u1, // bit offset: 8 desc: When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). - RB2: u1, // bit offset: 9 desc: When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). - // RESERVED: u6, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - DOS1: u1, // bit offset: 16 desc: When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). - DOS2: u1, // bit offset: 17 desc: When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). - // RESERVED: u14, // bit offset: 18 desc: Reserved, the value read from a reserved bit is not defined. - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 CAN Central Miscellaneous Register - pub const MSR = mmio(Address + 0x00000008, 32, packed struct { - E1: u1, // bit offset: 0 desc: When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) - E2: u1, // bit offset: 1 desc: When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) - // RESERVED: u6, // bit offset: 2 desc: Reserved, the value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - BS1: u1, // bit offset: 8 desc: When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). - BS2: u1, // bit offset: 9 desc: When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). - // RESERVED: u22, // bit offset: 10 desc: Reserved, the value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const CAN1 = extern struct { - pub const Address: u32 = 0x40044000; - // byte offset: 0 Controls the operating mode of the CAN Controller. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: enum(u1) { // bit offset: 0 desc: Reset Mode. - @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. - @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. - }, - LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. - @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. - @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. - }, - STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. - @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. - @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. - }, - TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. - @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. - @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. - }, - SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. - @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. - @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. - }, - RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. - @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). - @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. - }, - // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - TM: enum(u1) { // bit offset: 7 desc: Test Mode. - @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. - @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Command bits that affect the state of the CAN Controller - pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: enum(u1) { // bit offset: 0 desc: Transmission Request. - @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) - }, - AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. - @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. - @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. - }, - RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. - @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. - @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). - }, - CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. - @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. - @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. - }, - SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. - @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. - }, - STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. - }, - STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. - }, - STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. - pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. - @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. - }, - DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). - @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). - }, - TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. - @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). - @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. - @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. - }, - RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. - }, - TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. - }, - ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. - @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. - }, - BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. - @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities - @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. - }, - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). - TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). - }); - // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. - @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. - }, - ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: - @"BIT_ERROR" = 0, // desc: Bit error - @"FORM_ERROR" = 1, // desc: Form error - @"STUFF_ERROR" = 2, // desc: Stuff error - @"OTHER_ERROR" = 3, // desc: Other error - }, - ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. - }); - // byte offset: 16 Interrupt Enable - pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = mmio(Address + 0x00000014, 32, packed struct { - BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. - // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. - TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. - TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: enum(u1) { // bit offset: 23 desc: Sampling - @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) - @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) - }, - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = mmio(Address + 0x00000018, 32, packed struct { - EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Status Register - pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. - }, - RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. - }, - ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. - }, - RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. - }, - ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. - }, - RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. - }, - ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = mmio(Address + 0x00000020, 32, packed struct { - IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. - }); - // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = mmio(Address + 0x00000024, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = mmio(Address + 0x00000028, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. - DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. - DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. - DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. - }); - // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. - DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. - DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. - DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. - }); - // byte offset: 48 Transmit frame info (Tx Buffer ) - pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 52 Transmit Identifier (Tx Buffer) - pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 64 Transmit frame info (Tx Buffer ) - pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 68 Transmit Identifier (Tx Buffer) - pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 84 Transmit Identifier (Tx Buffer) - pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); -}; -pub const CAN2 = extern struct { - pub const Address: u32 = 0x40048000; - // byte offset: 0 Controls the operating mode of the CAN Controller. - pub const MOD = mmio(Address + 0x00000000, 32, packed struct { - RM: enum(u1) { // bit offset: 0 desc: Reset Mode. - @"NORMAL_THE_CAN_CONTR" = 0, // desc: Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. - @"RESET_CAN_OPERATION" = 1, // desc: Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. - }, - LOM: enum(u1) { // bit offset: 1 desc: Listen Only Mode. - @"NORMAL_THE_CAN_CONT" = 0, // desc: Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. - @"LISTEN_ONLY_THE_CON" = 1, // desc: Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. - }, - STM: enum(u1) { // bit offset: 2 desc: Self Test Mode. - @"NORMAL_A_TRANSMITTE" = 0, // desc: Normal. A transmitted message must be acknowledged to be considered successful. - @"SELF_TEST_THE_CONTR" = 1, // desc: Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. - }, - TPM: enum(u1) { // bit offset: 3 desc: Transmit Priority Mode. - @"CAN_ID_THE_TRANSMIT" = 0, // desc: CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. - @"LOCAL_PRIORITY_THE_" = 1, // desc: Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. - }, - SM: enum(u1) { // bit offset: 4 desc: Sleep Mode. - @"WAKE_UP_NORMAL_OPER" = 0, // desc: Wake-up. Normal operation. - @"SLEEP_THE_CAN_CONTR" = 1, // desc: Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. - }, - RPM: enum(u1) { // bit offset: 5 desc: Receive Polarity Mode. - @"LOW_ACTIVE_RD_INPUT" = 0, // desc: Low active. RD input is active Low (dominant bit = 0). - @"HIGH_ACTIVE_RD_INPU" = 1, // desc: High active. RD input is active High (dominant bit = 1) -- reverse polarity. - }, - // RESERVED: u1, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - TM: enum(u1) { // bit offset: 7 desc: Test Mode. - @"DISABLED_NORMAL_OPE" = 0, // desc: Disabled. Normal operation. - @"ENABLED_THE_TD_PIN_" = 1, // desc: Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Command bits that affect the state of the CAN Controller - pub const CMR = mmio(Address + 0x00000004, 32, packed struct { - TR: enum(u1) { // bit offset: 0 desc: Transmission Request. - @"ABSENT_NO_TRANSMISSI" = 0, // desc: Absent.No transmission request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) - }, - AT: enum(u1) { // bit offset: 1 desc: Abort Transmission. - @"NO_ACTION_DO_NOT_AB" = 0, // desc: No action. Do not abort the transmission. - @"PRESENT_IF_NOT_ALRE" = 1, // desc: Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. - }, - RRB: enum(u1) { // bit offset: 2 desc: Release Receive Buffer. - @"NO_ACTION_DO_NOT_RE" = 0, // desc: No action. Do not release the receive buffer. - @"RELEASED_THE_INFORM" = 1, // desc: Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). - }, - CDO: enum(u1) { // bit offset: 3 desc: Clear Data Overrun. - @"NO_ACTION_DO_NOT_CL" = 0, // desc: No action. Do not clear the data overrun bit. - @"CLEAR_THE_DATA_OVER" = 1, // desc: Clear. The Data Overrun bit in Status Register(s) is cleared. - }, - SRR: enum(u1) { // bit offset: 4 desc: Self Reception Request. - @"ABSENT_NO_SELF_RECE" = 0, // desc: Absent. No self reception request. - @"PRESENT_THE_MESSAGE" = 1, // desc: Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. - }, - STB1: enum(u1) { // bit offset: 5 desc: Select Tx Buffer 1. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 1 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 1 is selected for transmission. - }, - STB2: enum(u1) { // bit offset: 6 desc: Select Tx Buffer 2. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 2 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 2 is selected for transmission. - }, - STB3: enum(u1) { // bit offset: 7 desc: Select Tx Buffer 3. - @"NOT_SELECTED_TX_BUF" = 0, // desc: Not selected. Tx Buffer 3 is not selected for transmission. - @"SELECTED_TX_BUFFER_" = 1, // desc: Selected. Tx Buffer 3 is selected for transmission. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. - pub const GSR = mmio(Address + 0x00000008, 32, packed struct { - RBS: enum(u1) { // bit offset: 0 desc: Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. - @"EMPTY_NO_MESSAGE_IS" = 0, // desc: Empty. No message is available. - @"FULL_AT_LEAST_ONE_C" = 1, // desc: Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. - }, - DOS: enum(u1) { // bit offset: 1 desc: Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. - @"ABSENT_NO_DATA_OVER" = 0, // desc: Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). - @"OVERRUN_A_MESSAGE_W" = 1, // desc: Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). - }, - TBS: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status. - @"LOCKED_AT_LEAST_ONE" = 0, // desc: Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). - @"RELEASED_ALL_THREE_" = 1, // desc: Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS: enum(u1) { // bit offset: 3 desc: Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. - @"INCOMPLETE_AT_LEAST" = 0, // desc: Incomplete. At least one requested transmission has not been successfully completed yet. - @"COMPLETE_ALL_REQUES" = 1, // desc: Complete. All requested transmission(s) has (have) been successfully completed. - }, - RS: enum(u1) { // bit offset: 4 desc: Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"RECEIVE_THE_CAN_CON" = 1, // desc: Receive. The CAN controller is receiving a message. - }, - TS: enum(u1) { // bit offset: 5 desc: Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. - @"IDLE_THE_CAN_CONTRO" = 0, // desc: Idle. The CAN controller is idle. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN controller is sending a message. - }, - ES: enum(u1) { // bit offset: 6 desc: Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). - @"OK_BOTH_ERROR_COUNT" = 0, // desc: OK. Both error counters are below the Error Warning Limit. - @"ERROR_ONE_OR_BOTH_O" = 1, // desc: Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. - }, - BS: enum(u1) { // bit offset: 7 desc: Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. - @"BUS_ON_THE_CAN_CONT" = 0, // desc: Bus-on. The CAN Controller is involved in bus activities - @"BUS_OFF_THE_CAN_CON" = 1, // desc: Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. - }, - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXERR: u8, // bit offset: 16 desc: The current value of the Rx Error Counter (an 8-bit value). - TXERR: u8, // bit offset: 24 desc: The current value of the Tx Error Counter (an 8-bit value). - }); - // byte offset: 12 Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = mmio(Address + 0x0000000c, 32, packed struct { - RI: enum(u1) { // bit offset: 0 desc: Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI1: enum(u1) { // bit offset: 1 desc: Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EI: enum(u1) { // bit offset: 2 desc: Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - DOI: enum(u1) { // bit offset: 3 desc: Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - WUI: enum(u1) { // bit offset: 4 desc: Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - EPI: enum(u1) { // bit offset: 5 desc: Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - ALI: enum(u1) { // bit offset: 6 desc: Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - BEI: enum(u1) { // bit offset: 7 desc: Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - IDI: enum(u1) { // bit offset: 8 desc: ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI2: enum(u1) { // bit offset: 9 desc: Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - TI3: enum(u1) { // bit offset: 10 desc: Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. - @"RESET" = 0, // desc: Reset - @"SET" = 1, // desc: Set - }, - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ERRBIT4_0: u5, // bit offset: 16 desc: Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. - ERRDIR: enum(u1) { // bit offset: 21 desc: When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. - @"ERROR_OCCURRED_DURIN" = 0, // desc: Error occurred during transmitting. - @"ERROR_OCCURRED_DURIN" = 1, // desc: Error occurred during receiving. - }, - ERRC1_0: enum(u2) { // bit offset: 22 desc: When the CAN controller detects a bus error, the type of error is captured in this field: - @"BIT_ERROR" = 0, // desc: Bit error - @"FORM_ERROR" = 1, // desc: Form error - @"STUFF_ERROR" = 2, // desc: Stuff error - @"OTHER_ERROR" = 3, // desc: Other error - }, - ALCBIT: u8, // bit offset: 24 desc: Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. - }); - // byte offset: 16 Interrupt Enable - pub const IER = mmio(Address + 0x00000010, 32, packed struct { - RIE: u1, // bit offset: 0 desc: Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. - TIE1: u1, // bit offset: 1 desc: Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - EIE: u1, // bit offset: 2 desc: Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. - DOIE: u1, // bit offset: 3 desc: Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. - WUIE: u1, // bit offset: 4 desc: Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. - EPIE: u1, // bit offset: 5 desc: Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. - ALIE: u1, // bit offset: 6 desc: Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. - BEIE: u1, // bit offset: 7 desc: Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. - IDIE: u1, // bit offset: 8 desc: ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. - TIE2: u1, // bit offset: 9 desc: Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - TIE3: u1, // bit offset: 10 desc: Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = mmio(Address + 0x00000014, 32, packed struct { - BRP: u10, // bit offset: 0 desc: Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. - // RESERVED: u4, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SJW: u2, // bit offset: 14 desc: The Synchronization Jump Width is (this value plus one) CAN clocks. - TESG1: u4, // bit offset: 16 desc: The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. - TESG2: u3, // bit offset: 20 desc: The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. - SAM: enum(u1) { // bit offset: 23 desc: Sampling - @"THE_BUS_IS_SAMPLED_O" = 0, // desc: The bus is sampled once (recommended for high speed buses) - @"THE_BUS_IS_SAMPLED_3" = 1, // desc: The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) - }, - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = mmio(Address + 0x00000018, 32, packed struct { - EWL: u8, // bit offset: 0 desc: During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Status Register - pub const SR = mmio(Address + 0x0000001c, 32, packed struct { - RBS_1: u1, // bit offset: 0 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_1: u1, // bit offset: 1 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS1_1: enum(u1) { // bit offset: 2 desc: Transmit Buffer Status 1. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS1_1: enum(u1) { // bit offset: 3 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. - }, - RS_1: u1, // bit offset: 4 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS1_1: enum(u1) { // bit offset: 5 desc: Transmit Status 1. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 1. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. - }, - ES_1: u1, // bit offset: 6 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_1: u1, // bit offset: 7 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_2: u1, // bit offset: 8 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_2: u1, // bit offset: 9 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS2_2: enum(u1) { // bit offset: 10 desc: Transmit Buffer Status 2. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS2_2: enum(u1) { // bit offset: 11 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. - }, - RS_2: u1, // bit offset: 12 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS2_2: enum(u1) { // bit offset: 13 desc: Transmit Status 2. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 2. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. - }, - ES_2: u1, // bit offset: 14 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_2: u1, // bit offset: 15 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - RBS_3: u1, // bit offset: 16 desc: Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - DOS_3: u1, // bit offset: 17 desc: Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - TBS3_3: enum(u1) { // bit offset: 18 desc: Transmit Buffer Status 3. - @"LOCKED_SOFTWARE_CAN" = 0, // desc: Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. - @"RELEASED_SOFTWARE_M" = 1, // desc: Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. - }, - TCS3_3: enum(u1) { // bit offset: 19 desc: Transmission Complete Status. - @"INCOMPLETE_THE_PREV" = 0, // desc: Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. - @"COMPLETE_THE_PREVIO" = 1, // desc: Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. - }, - RS_3: u1, // bit offset: 20 desc: Receive Status. This bit is identical to the RS bit in the GSR. - TS3_3: enum(u1) { // bit offset: 21 desc: Transmit Status 3. - @"IDLE_THERE_IS_NO_TR" = 0, // desc: Idle. There is no transmission from Tx Buffer 3. - @"TRANSMIT_THE_CAN_CO" = 1, // desc: Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. - }, - ES_3: u1, // bit offset: 22 desc: Error Status. This bit is identical to the ES bit in the CANxGSR. - BS_3: u1, // bit offset: 23 desc: Bus Status. This bit is identical to the BS bit in the CANxGSR. - // RESERVED: u8, // bit offset: 24 desc: Reserved, the value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = mmio(Address + 0x00000020, 32, packed struct { - IDINDEX: u10, // bit offset: 0 desc: ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. - BP: u1, // bit offset: 10 desc: If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. - // RESERVED: u5, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - RTR: u1, // bit offset: 30 desc: This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. - FF: u1, // bit offset: 31 desc: A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. - }); - // byte offset: 36 Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = mmio(Address + 0x00000024, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - // RESERVED: u21, // bit offset: 11 desc: Reserved. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = mmio(Address + 0x00000028, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. - DATA2: u8, // bit offset: 8 desc: Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. - DATA3: u8, // bit offset: 16 desc: Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. - DATA4: u8, // bit offset: 24 desc: Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. - }); - // byte offset: 44 Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = mmio(Address + 0x0000002c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. - DATA6: u8, // bit offset: 8 desc: Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. - DATA7: u8, // bit offset: 16 desc: Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. - DATA8: u8, // bit offset: 24 desc: Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. - }); - // byte offset: 48 Transmit frame info (Tx Buffer ) - pub const TFI1 = mmio(Address + 0x00000030, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 52 Transmit Identifier (Tx Buffer) - pub const TID1 = mmio(Address + 0x00000034, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA1 = mmio(Address + 0x00000038, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 60 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB1 = mmio(Address + 0x0000003c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 64 Transmit frame info (Tx Buffer ) - pub const TFI2 = mmio(Address + 0x00000040, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 68 Transmit Identifier (Tx Buffer) - pub const TID2 = mmio(Address + 0x00000044, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA2 = mmio(Address + 0x00000048, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 76 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB2 = mmio(Address + 0x0000004c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); - // byte offset: 80 Transmit frame info (Tx Buffer ) - pub const TFI3 = mmio(Address + 0x00000050, 32, packed struct { - PRIO: u8, // bit offset: 0 desc: If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. - // RESERVED: u8, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - DLC: u4, // bit offset: 16 desc: Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes - // RESERVED: u10, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - RTR: u1, // bit offset: 30 desc: This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. - FF: u1, // bit offset: 31 desc: If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). - }); - // byte offset: 84 Transmit Identifier (Tx Buffer) - pub const TID3 = mmio(Address + 0x00000054, 32, packed struct { - ID: u11, // bit offset: 0 desc: The 11-bit Identifier to be sent in the next transmit message. - // RESERVED: u21, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Transmit data bytes 1-4 (Tx Buffer) - pub const TDA3 = mmio(Address + 0x00000058, 32, packed struct { - DATA1: u8, // bit offset: 0 desc: Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. - DATA2: u8, // bit offset: 8 desc: Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. - DATA3: u8, // bit offset: 16 desc: Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. - DATA4: u8, // bit offset: 24 desc: Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. - }); - // byte offset: 92 Transmit data bytes 5-8 (Tx Buffer ) - pub const TDB3 = mmio(Address + 0x0000005c, 32, packed struct { - DATA5: u8, // bit offset: 0 desc: Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. - DATA6: u8, // bit offset: 8 desc: Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. - DATA7: u8, // bit offset: 16 desc: Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. - DATA8: u8, // bit offset: 24 desc: Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. - }); -}; -pub const I2C1 = extern struct { - pub const Address: u32 = 0x4005c000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SSP0 = extern struct { - pub const Address: u32 = 0x40088000; - // byte offset: 0 Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = mmio(Address + 0x00000000, 32, packed struct { - DSS: enum(u4) { // bit offset: 0 desc: Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. - @"4_BIT_TRANSFER" = 3, // desc: 4-bit transfer - @"5_BIT_TRANSFER" = 4, // desc: 5-bit transfer - @"6_BIT_TRANSFER" = 5, // desc: 6-bit transfer - @"7_BIT_TRANSFER" = 6, // desc: 7-bit transfer - @"8_BIT_TRANSFER" = 7, // desc: 8-bit transfer - @"9_BIT_TRANSFER" = 8, // desc: 9-bit transfer - @"10_BIT_TRANSFER" = 9, // desc: 10-bit transfer - @"11_BIT_TRANSFER" = 10, // desc: 11-bit transfer - @"12_BIT_TRANSFER" = 11, // desc: 12-bit transfer - @"13_BIT_TRANSFER" = 12, // desc: 13-bit transfer - @"14_BIT_TRANSFER" = 13, // desc: 14-bit transfer - @"15_BIT_TRANSFER" = 14, // desc: 15-bit transfer - @"16_BIT_TRANSFER" = 15, // desc: 16-bit transfer - _, // non-exhaustive - }, - FRF: enum(u2) { // bit offset: 4 desc: Frame Format. - @"SPI" = 0, // desc: SPI - @"TI" = 1, // desc: TI - @"MICROWIRE" = 2, // desc: Microwire - @"THIS_COMBINATION_IS_" = 3, // desc: This combination is not supported and should not be used. - }, - CPOL: enum(u1) { // bit offset: 6 desc: Clock Out Polarity. This bit is only used in SPI mode. - @"BUS_LOW" = 0, // desc: SSP controller maintains the bus clock low between frames. - @"BUS_HIGH" = 1, // desc: SSP controller maintains the bus clock high between frames. - }, - CPHA: enum(u1) { // bit offset: 7 desc: Clock Out Phase. This bit is only used in SPI mode. - @"FIRST_CLOCK" = 0, // desc: SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. - @"SECOND_CLOCK" = 1, // desc: SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. - }, - SCR: u8, // bit offset: 8 desc: Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Control Register 1. Selects master/slave and other modes. - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - LBM: enum(u1) { // bit offset: 0 desc: Loop Back Mode. - @"NORMAL" = 0, // desc: During normal operation. - @"OUPTU" = 1, // desc: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). - }, - SSE: enum(u1) { // bit offset: 1 desc: SSP Enable. - @"DISABLED" = 0, // desc: The SSP controller is disabled. - @"ENABLED" = 1, // desc: The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. - }, - MS: enum(u1) { // bit offset: 2 desc: Master/Slave Mode.This bit can only be written when the SSE bit is 0. - @"MASTER" = 0, // desc: The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. - @"SLAVE" = 1, // desc: The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. - }, - SOD: u1, // bit offset: 3 desc: Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = mmio(Address + 0x00000008, 32, packed struct { - DATA: u16, // bit offset: 0 desc: Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Status Register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - TFE: u1, // bit offset: 0 desc: Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TNF: u1, // bit offset: 1 desc: Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - RNE: u1, // bit offset: 2 desc: Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RFF: u1, // bit offset: 3 desc: Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - BSY: u1, // bit offset: 4 desc: Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. - // RESERVED: u27, // bit offset: 5 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Clock Prescale Register - pub const CPSR = mmio(Address + 0x00000010, 32, packed struct { - CPSDVSR: u8, // bit offset: 0 desc: This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Interrupt Mask Set and Clear Register - pub const IMSC = mmio(Address + 0x00000014, 32, packed struct { - RORIM: u1, // bit offset: 0 desc: Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTIM: u1, // bit offset: 1 desc: Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXIM: u1, // bit offset: 2 desc: Software should set this bit to enable interrupt when the Rx FIFO is at least half full. - TXIM: u1, // bit offset: 3 desc: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Raw Interrupt Status Register - pub const RIS = mmio(Address + 0x00000018, 32, packed struct { - RORRIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. - RTRIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXRIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full. - TXRIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Masked Interrupt Status Register - pub const MIS = mmio(Address + 0x0000001c, 32, packed struct { - RORMIS: u1, // bit offset: 0 desc: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. - RTMIS: u1, // bit offset: 1 desc: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RXMIS: u1, // bit offset: 2 desc: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. - TXMIS: u1, // bit offset: 3 desc: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 SSPICR Interrupt Clear Register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - RORIC: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. - RTIC: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 SSP0 DMA control register - pub const DMACR = mmio(Address + 0x00000024, 32, packed struct { - RXDMAE: u1, // bit offset: 0 desc: Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. - TXDMAE: u1, // bit offset: 1 desc: Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const DAC = extern struct { - pub const Address: u32 = 0x4008c000; - // byte offset: 0 D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u6, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - VALUE: u10, // bit offset: 6 desc: After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN. - BIAS: enum(u1) { // bit offset: 16 desc: Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. - @"FAST" = 0, // desc: The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. - @"SLOW" = 1, // desc: The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. - }, - // RESERVED: u15, // bit offset: 17 desc: Reserved. Read value is undefined, only zero should be written. - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DAC Control register. This register controls DMA and timer operation. - pub const CTRL = mmio(Address + 0x00000004, 32, packed struct { - INT_DMA_REQ: enum(u1) { // bit offset: 0 desc: DMA interrupt request - @"CLEAR_ON_ANY_WRITE_T" = 0, // desc: Clear on any write to the DACR register. - @"SET_BY_HARDWARE_WHEN" = 1, // desc: Set by hardware when the timer times out. - }, - DBLBUF_ENA: enum(u1) { // bit offset: 1 desc: Double buffering - @"DISABLE" = 0, // desc: Disable - @"ENABLE_WHEN_THIS_BI" = 1, // desc: Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. - }, - CNT_ENA: enum(u1) { // bit offset: 2 desc: Time-out counter operation - @"DISABLE" = 0, // desc: Disable - @"ENABLE" = 1, // desc: Enable - }, - DMA_ENA: enum(u1) { // bit offset: 3 desc: DMA access - @"DISABLE" = 0, // desc: Disable - @"ENABLE_DMA_BURST_RE" = 1, // desc: Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672). - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. - pub const CNTVAL = mmio(Address + 0x00000008, 32, packed struct { - VALUE: u16, // bit offset: 0 desc: 16-bit reload value for the DAC interrupt/DMA timer. - // RESERVED: u16, // bit offset: 16 desc: Reserved - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER2 = extern struct { - pub const Address: u32 = 0x40090000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const TIMER3 = extern struct { - pub const Address: u32 = 0x40094000; - // byte offset: 0 Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. - pub const IR = mmio(Address + 0x00000000, 32, packed struct { - MR0INT: u1, // bit offset: 0 desc: Interrupt flag for match channel 0. - MR1INT: u1, // bit offset: 1 desc: Interrupt flag for match channel 1. - MR2INT: u1, // bit offset: 2 desc: Interrupt flag for match channel 2. - MR3INT: u1, // bit offset: 3 desc: Interrupt flag for match channel 3. - CR0INT: u1, // bit offset: 4 desc: Interrupt flag for capture channel 0 event. - CR1INT: u1, // bit offset: 5 desc: Interrupt flag for capture channel 1 event. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. - pub const TCR = mmio(Address + 0x00000004, 32, packed struct { - CEN: u1, // bit offset: 0 desc: When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. - CRST: u1, // bit offset: 1 desc: When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. - pub const TC = mmio(Address + 0x00000008, 32, packed struct { - TC: u32, // bit offset: 0 desc: Timer counter value. - }); - // byte offset: 12 Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. - pub const PR = mmio(Address + 0x0000000c, 32, packed struct { - PM: u32, // bit offset: 0 desc: Prescale counter maximum value. - }); - // byte offset: 16 Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. - pub const PC = mmio(Address + 0x00000010, 32, packed struct { - PC: u32, // bit offset: 0 desc: Prescale counter value. - }); - // byte offset: 20 Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. - pub const MCR = mmio(Address + 0x00000014, 32, packed struct { - MR0I: enum(u1) { // bit offset: 0 desc: Interrupt on MR0 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR0 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR0R: enum(u1) { // bit offset: 1 desc: Reset on MR0 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR0 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR0S: enum(u1) { // bit offset: 2 desc: Stop on MR0 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1I: enum(u1) { // bit offset: 3 desc: Interrupt on MR1 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR1 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled. - }, - MR1R: enum(u1) { // bit offset: 4 desc: Reset on MR1 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR1 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR1S: enum(u1) { // bit offset: 5 desc: Stop on MR1 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2I: enum(u1) { // bit offset: 6 desc: Interrupt on MR2 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR2 matches the value in the TC. - @"INTERRUPT_IS_DISABLE" = 0, // desc: Interrupt is disabled - }, - MR2R: enum(u1) { // bit offset: 7 desc: Reset on MR2 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR2 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR2S: enum(u1) { // bit offset: 8 desc: Stop on MR2. - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3I: enum(u1) { // bit offset: 9 desc: Interrupt on MR3 - @"INTERRUPT_IS_GENERAT" = 1, // desc: Interrupt is generated when MR3 matches the value in the TC. - @"THIS_INTERRUPT_IS_DI" = 0, // desc: This interrupt is disabled - }, - MR3R: enum(u1) { // bit offset: 10 desc: Reset on MR3 - @"TC_WILL_BE_RESET_IF_" = 1, // desc: TC will be reset if MR3 matches it. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - MR3S: enum(u1) { // bit offset: 11 desc: Stop on MR3 - @"TC_AND_PC_WILL_BE_ST" = 1, // desc: TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. - @"FEATURE_DISABLED_" = 0, // desc: Feature disabled. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_0 = mmio(Address + 0x00000018, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 28 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_1 = mmio(Address + 0x0000001c, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 32 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_2 = mmio(Address + 0x00000020, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 36 Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR_3 = mmio(Address + 0x00000024, 32, packed struct { - MATCH: u32, // bit offset: 0 desc: Timer counter match value. - }); - // byte offset: 40 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. - pub const CCR = mmio(Address + 0x00000028, 32, packed struct { - CAP0RE: enum(u1) { // bit offset: 0 desc: Capture on CAPn.0 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0FE: enum(u1) { // bit offset: 1 desc: Capture on CAPn.0 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP0I: enum(u1) { // bit offset: 2 desc: Interrupt on CAPn.0 event - @"ENABLE" = 1, // desc: A CR0 load due to a CAPn.0 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1RE: enum(u1) { // bit offset: 3 desc: Capture on CAPn.1 rising edge - @"ENABLE" = 1, // desc: A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1FE: enum(u1) { // bit offset: 4 desc: Capture on CAPn.1 falling edge - @"ENABLE" = 1, // desc: A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - CAP1I: enum(u1) { // bit offset: 5 desc: Interrupt on CAPn.1 event - @"ENABLE" = 1, // desc: A CR1 load due to a CAPn.1 event will generate an interrupt. - @"DISABLE" = 0, // desc: This feature is disabled. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_0 = mmio(Address + 0x0000002c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 48 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. - pub const CR_1 = mmio(Address + 0x00000030, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Timer counter capture value. - }); - // byte offset: 60 External Match Register. The EMR controls the external match pins. - pub const EMR = mmio(Address + 0x0000003c, 32, packed struct { - EM0: u1, // bit offset: 0 desc: External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM1: u1, // bit offset: 1 desc: External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). - EM2: u1, // bit offset: 2 desc: External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EM3: u1, // bit offset: 3 desc: External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). - EMC0: enum(u2) { // bit offset: 4 desc: External Match Control 0. Determines the functionality of External Match 0. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC1: enum(u2) { // bit offset: 6 desc: External Match Control 1. Determines the functionality of External Match 1. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC2: enum(u2) { // bit offset: 8 desc: External Match Control 2. Determines the functionality of External Match 2. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - EMC3: enum(u2) { // bit offset: 10 desc: External Match Control 3. Determines the functionality of External Match 3. - @"DO_NOTHING_" = 0, // desc: Do Nothing. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). - @"SET_THE_CORRESPONDIN" = 2, // desc: Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). - @"TOGGLE_THE_CORRESPON" = 3, // desc: Toggle the corresponding External Match bit/output. - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. - pub const CTCR = mmio(Address + 0x00000070, 32, packed struct { - CTMODE: enum(u2) { // bit offset: 0 desc: Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - @"TIMER_MODE_EVERY_RI" = 0, // desc: Timer Mode: every rising PCLK edge - @"RISING" = 1, // desc: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. - @"FALLING" = 2, // desc: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. - @"DUALEDGE" = 3, // desc: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. - }, - CINSEL: enum(u2) { // bit offset: 2 desc: Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - @"CAPN_0_FOR_TIMERN" = 0, // desc: CAPn.0 for TIMERn - @"CAPN_1_FOR_TIMERN" = 1, // desc: CAPn.1 for TIMERn - _, // non-exhaustive - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART2 = extern struct { - pub const Address: u32 = 0x40098000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const UART3 = extern struct { - pub const Address: u32 = 0x4009c000; - // byte offset: 0 Receiver Buffer Register. Contains the next received character to be read (DLAB =0). - pub const RBR = mmio(Address + 0x00000000, 32, packed struct { - RBR: u8, // bit offset: 0 desc: The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. - // RESERVED: u24, // bit offset: 8 desc: Reserved, the value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). - pub const THR = mmio(Address + 0x00000000, 32, packed struct { - THR: u8, // bit offset: 0 desc: Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 0 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLL = mmio(Address + 0x00000000, 32, packed struct { - DLLSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). - pub const DLM = mmio(Address + 0x00000004, 32, packed struct { - DLMSB: u8, // bit offset: 0 desc: The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - RBRIE: enum(u1) { // bit offset: 0 desc: RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. - @"DISABLE_THE_RDA_INTE" = 0, // desc: Disable the RDA interrupts. - @"ENABLE_THE_RDA_INTER" = 1, // desc: Enable the RDA interrupts. - }, - THREIE: enum(u1) { // bit offset: 1 desc: THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. - @"DISABLE_THE_THRE_INT" = 0, // desc: Disable the THRE interrupts. - @"ENABLE_THE_THRE_INTE" = 1, // desc: Enable the THRE interrupts. - }, - RXIE: enum(u1) { // bit offset: 2 desc: RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. - @"DISABLE_THE_RX_LINE_" = 0, // desc: Disable the RX line status interrupts. - @"ENABLE_THE_RX_LINE_S" = 1, // desc: Enable the RX line status interrupts. - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTEN: enum(u1) { // bit offset: 8 desc: Enables the end of auto-baud interrupt. - @"DISABLE_END_OF_AUTO_" = 0, // desc: Disable end of auto-baud Interrupt. - @"ENABLE_END_OF_AUTO_B" = 1, // desc: Enable end of auto-baud Interrupt. - }, - ABTOINTEN: enum(u1) { // bit offset: 9 desc: Enables the auto-baud time-out interrupt. - @"DISABLE_AUTO_BAUD_TI" = 0, // desc: Disable auto-baud time-out Interrupt. - @"ENABLE_AUTO_BAUD_TIM" = 1, // desc: Enable auto-baud time-out Interrupt. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = mmio(Address + 0x00000008, 32, packed struct { - INTSTATUS: enum(u1) { // bit offset: 0 desc: Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. - @"AT_LEAST_ONE_INTERRU" = 0, // desc: At least one interrupt is pending. - @"NO_INTERRUPT_IS_PEND" = 1, // desc: No interrupt is pending. - }, - INTID: enum(u3) { // bit offset: 1 desc: Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). - @"1_RECEIVE_LINE_S" = 3, // desc: 1 - Receive Line Status (RLS). - @"2A__RECEIVE_DATA_AV" = 2, // desc: 2a - Receive Data Available (RDA). - @"2B__CHARACTER_TIME_" = 6, // desc: 2b - Character Time-out Indicator (CTI). - @"3_THRE_INTERRUPT" = 1, // desc: 3 - THRE Interrupt - _, // non-exhaustive - }, - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - FIFOENABLE: u2, // bit offset: 6 desc: Copies of UnFCR[0]. - ABEOINT: u1, // bit offset: 8 desc: End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. - ABTOINT: u1, // bit offset: 9 desc: Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = mmio(Address + 0x00000008, 32, packed struct { - FIFOEN: enum(u1) { // bit offset: 0 desc: FIFO Enable. - @"UARTN_FIFOS_ARE_DISA" = 0, // desc: UARTn FIFOs are disabled. Must not be used in the application. - @"ACTIVE_HIGH_ENABLE_F" = 1, // desc: Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. - }, - RXFIFORES: enum(u1) { // bit offset: 1 desc: RX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. - }, - TXFIFORES: enum(u1) { // bit offset: 2 desc: TX FIFO Reset. - @"NO_IMPACT_ON_EITHER_" = 0, // desc: No impact on either of UARTn FIFOs. - @"WRITING_A_LOGIC_1_TO" = 1, // desc: Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. - }, - DMAMODE: u1, // bit offset: 3 desc: DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. - // RESERVED: u2, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - RXTRIGLVL: enum(u2) { // bit offset: 6 desc: RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. - @"TRIGGER_LEVEL_0_1_C" = 0, // desc: Trigger level 0 (1 character or 0x01). - @"TRIGGER_LEVEL_1_4_C" = 1, // desc: Trigger level 1 (4 characters or 0x04). - @"TRIGGER_LEVEL_2_8_C" = 2, // desc: Trigger level 2 (8 characters or 0x08). - @"TRIGGER_LEVEL_3_14_" = 3, // desc: Trigger level 3 (14 characters or 0x0E). - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Line Control Register. Contains controls for frame formatting and break generation. - pub const LCR = mmio(Address + 0x0000000c, 32, packed struct { - WLS: enum(u2) { // bit offset: 0 desc: Word Length Select. - @"5_BIT_CHARACTER_LENG" = 0, // desc: 5-bit character length - @"6_BIT_CHARACTER_LENG" = 1, // desc: 6-bit character length - @"7_BIT_CHARACTER_LENG" = 2, // desc: 7-bit character length - @"8_BIT_CHARACTER_LENG" = 3, // desc: 8-bit character length - }, - SBS: enum(u1) { // bit offset: 2 desc: Stop Bit Select - @"1_STOP_BIT_" = 0, // desc: 1 stop bit. - @"2_STOP_BITS_1_5_IF_" = 1, // desc: 2 stop bits (1.5 if UnLCR[1:0]=00). - }, - PE: enum(u1) { // bit offset: 3 desc: Parity Enable. - @"DISABLE_PARITY_GENER" = 0, // desc: Disable parity generation and checking. - @"ENABLE_PARITY_GENERA" = 1, // desc: Enable parity generation and checking. - }, - PS: enum(u2) { // bit offset: 4 desc: Parity Select - @"ODD_PARITY_NUMBER_O" = 0, // desc: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. - @"EVEN_PARITY_NUMBER_" = 1, // desc: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. - @"FORCED_1_STICK_PARIT" = 2, // desc: Forced 1 stick parity. - @"FORCED_0_STICK_PARIT" = 3, // desc: Forced 0 stick parity. - }, - BC: enum(u1) { // bit offset: 6 desc: Break Control - @"DISABLE_BREAK_TRANSM" = 0, // desc: Disable break transmission. - @"ENABLE_BREAK_TRANSMI" = 1, // desc: Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. - }, - DLAB: enum(u1) { // bit offset: 7 desc: Divisor Latch Access Bit - @"DISABLE_ACCESS_TO_DI" = 0, // desc: Disable access to Divisor Latches. - @"ENABLE_ACCESS_TO_DIV" = 1, // desc: Enable access to Divisor Latches. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Line Status Register. Contains flags for transmit and receive status, including line errors. - pub const LSR = mmio(Address + 0x00000014, 32, packed struct { - RDR: enum(u1) { // bit offset: 0 desc: Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. - @"EMPTY" = 0, // desc: The UARTn receiver FIFO is empty. - @"NOTEMPTY" = 1, // desc: The UARTn receiver FIFO is not empty. - }, - OE: enum(u1) { // bit offset: 1 desc: Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. - @"INACTIVE" = 0, // desc: Overrun error status is inactive. - @"ACTIVE" = 1, // desc: Overrun error status is active. - }, - PE: enum(u1) { // bit offset: 2 desc: Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Parity error status is inactive. - @"ACTIVE" = 1, // desc: Parity error status is active. - }, - FE: enum(u1) { // bit offset: 3 desc: Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Framing error status is inactive. - @"ACTIVE" = 1, // desc: Framing error status is active. - }, - BI: enum(u1) { // bit offset: 4 desc: Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. - @"INACTIVE" = 0, // desc: Break interrupt status is inactive. - @"ACTIVE" = 1, // desc: Break interrupt status is active. - }, - THRE: enum(u1) { // bit offset: 5 desc: Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. - @"VALIDDATA" = 0, // desc: UnTHR contains valid data. - @"EMPTY" = 1, // desc: UnTHR is empty. - }, - TEMT: enum(u1) { // bit offset: 6 desc: Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. - @"VALIDDATA" = 0, // desc: UnTHR and/or the UnTSR contains valid data. - @"EMPTY" = 1, // desc: UnTHR and the UnTSR are empty. - }, - RXFE: enum(u1) { // bit offset: 7 desc: Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. - @"NOERROR" = 0, // desc: UnRBR contains no UARTn RX errors or UnFCR[0]=0. - @"ERRORS" = 1, // desc: UARTn RBR contains at least one UARTn RX error. - }, - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = mmio(Address + 0x0000001c, 32, packed struct { - PAD: u8, // bit offset: 0 desc: A readable, writable byte. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = mmio(Address + 0x00000020, 32, packed struct { - START: enum(u1) { // bit offset: 0 desc: Start bit. This bit is automatically cleared after auto-baud completion. - @"AUTO_BAUD_STOP_AUTO" = 0, // desc: Auto-baud stop (auto-baud is not running). - @"AUTO_BAUD_START_AUT" = 1, // desc: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. - }, - MODE: enum(u1) { // bit offset: 1 desc: Auto-baud mode select bit. - @"MODE_0_" = 0, // desc: Mode 0. - @"MODE_1_" = 1, // desc: Mode 1. - }, - AUTORESTART: enum(u1) { // bit offset: 2 desc: Restart bit. - @"NO_RESTART_" = 0, // desc: No restart. - @"RESTART_IN_CASE_OF_T" = 1, // desc: Restart in case of time-out (counter restarts at next UARTn Rx falling edge) - }, - // RESERVED: u5, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - ABEOINTCLR: enum(u1) { // bit offset: 8 desc: End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - ABTOINTCLR: enum(u1) { // bit offset: 9 desc: Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - @"NO_IMPACT_" = 0, // desc: No impact. - @"CLEAR_THE_CORRESPOND" = 1, // desc: Clear the corresponding interrupt in the IIR. - }, - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = mmio(Address + 0x00000028, 32, packed struct { - DIVADDVAL: u4, // bit offset: 0 desc: Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. - MULVAL: u4, // bit offset: 4 desc: Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 Transmit Enable Register. Turns off UART transmitter for use with software flow control. - pub const TER = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - TXEN: u1, // bit offset: 7 desc: When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 76 RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. - pub const RS485CTRL = mmio(Address + 0x0000004c, 32, packed struct { - NMMEN: enum(u1) { // bit offset: 0 desc: NMM enable. - @"DISABLED" = 0, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. - @"ENABLED" = 1, // desc: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. - }, - RXDIS: enum(u1) { // bit offset: 1 desc: Receiver enable. - @"ENABLED" = 0, // desc: The receiver is enabled. - @"DISABLED" = 1, // desc: The receiver is disabled. - }, - AADEN: enum(u1) { // bit offset: 2 desc: AAD enable. - @"DISABLED" = 0, // desc: Auto Address Detect (AAD) is disabled. - @"ENABLED" = 1, // desc: Auto Address Detect (AAD) is enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DCTRL: enum(u1) { // bit offset: 4 desc: Direction control enable. - @"DISABLE_AUTO_DIRECTI" = 0, // desc: Disable Auto Direction Control. - @"ENABLE_AUTO_DIRECTIO" = 1, // desc: Enable Auto Direction Control. - }, - OINV: enum(u1) { // bit offset: 5 desc: Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. - @"DIRLOW" = 0, // desc: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. - @"DIRHIGH" = 1, // desc: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 80 RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. - pub const RS485ADRMATCH = mmio(Address + 0x00000050, 32, packed struct { - ADRMATCH: u8, // bit offset: 0 desc: Contains the address match value. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 RS-485/EIA-485 direction control delay. - pub const RS485DLY = mmio(Address + 0x00000054, 32, packed struct { - DLY: u8, // bit offset: 0 desc: Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2C2 = extern struct { - pub const Address: u32 = 0x400a0000; - // byte offset: 0 I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONSET = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AA: u1, // bit offset: 2 desc: Assert acknowledge flag. - SI: u1, // bit offset: 3 desc: I2C interrupt flag. - STO: u1, // bit offset: 4 desc: STOP flag. - STA: u1, // bit offset: 5 desc: START flag. - I2EN: u1, // bit offset: 6 desc: I2C interface enable. - // RESERVED: u25, // bit offset: 7 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: These bits are unused and are always 0. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - Status: u5, // bit offset: 3 desc: These bits give the actual status information about the I 2C interface. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. - pub const DAT = mmio(Address + 0x00000008, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds data values that have been received or are to be transmitted. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = mmio(Address + 0x0000000c, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. - pub const SCLH = mmio(Address + 0x00000010, 32, packed struct { - SCLH: u16, // bit offset: 0 desc: Count for SCL HIGH time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. - pub const SCLL = mmio(Address + 0x00000014, 32, packed struct { - SCLL: u16, // bit offset: 0 desc: Count for SCL low time period selection. - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. - pub const CONCLR = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved2: u1 = 0, - reserved1: u1 = 0, - AAC: u1, // bit offset: 2 desc: Assert acknowledge Clear bit. - SIC: u1, // bit offset: 3 desc: I2C interrupt Clear bit. - // RESERVED: u1, // bit offset: 4 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved3: u1 = 0, - STAC: u1, // bit offset: 5 desc: START flag Clear bit. - I2ENC: u1, // bit offset: 6 desc: I2C interface Disable bit. - // RESERVED: u1, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Monitor mode control register. - pub const MMCTRL = mmio(Address + 0x0000001c, 32, packed struct { - MM_ENA: enum(u1) { // bit offset: 0 desc: Monitor mode enable. - @"MONITOR_MODE_DISABLE" = 0, // desc: Monitor mode disabled. - @"THE_I_2C_MODULE_WILL" = 1, // desc: The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. - }, - ENA_SCL: enum(u1) { // bit offset: 1 desc: SCL output enable. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] - }, - MATCH_ALL: enum(u1) { // bit offset: 2 desc: Select interrupt register match. - @"WHEN_THIS_BIT_IS_CLE" = 0, // desc: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. - @"WHEN_THIS_BIT_IS_SET" = 1, // desc: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from reserved bits is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = mmio(Address + 0x00000020, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = mmio(Address + 0x00000024, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = mmio(Address + 0x00000028, 32, packed struct { - GC: u1, // bit offset: 0 desc: General Call enable bit. - Address: u7, // bit offset: 1 desc: The I2C device address for slave mode. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = mmio(Address + 0x0000002c, 32, packed struct { - Data: u8, // bit offset: 0 desc: This register holds contents of the 8 MSBs of the DAT shift register. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2C Slave address mask register - pub const MASK_0 = mmio(Address + 0x00000030, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2C Slave address mask register - pub const MASK_1 = mmio(Address + 0x00000034, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 56 I2C Slave address mask register - pub const MASK_2 = mmio(Address + 0x00000038, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 60 I2C Slave address mask register - pub const MASK_3 = mmio(Address + 0x0000003c, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. - reserved1: u1 = 0, - MASK: u7, // bit offset: 1 desc: Mask bits. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const I2S = extern struct { - pub const Address: u32 = 0x400a8000; - // byte offset: 0 I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. - pub const DAO = mmio(Address + 0x00000000, 32, packed struct { - WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: - @"8_BIT_DATA" = 0, // desc: 8-bit data - @"16_BIT_DATA" = 1, // desc: 16-bit data - @"32_BIT_DATA" = 3, // desc: 32-bit data - _, // non-exhaustive - }, - MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: u1, // bit offset: 4 desc: When 1, asynchronously resets the transmit channel and FIFO. - WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. - WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - MUTE: u1, // bit offset: 15 desc: When 1, the transmit channel sends only zeroes. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. - pub const DAI = mmio(Address + 0x00000004, 32, packed struct { - WORDWIDTH: enum(u2) { // bit offset: 0 desc: Selects the number of bytes in data as follows: - @"8_BIT_DATA" = 0, // desc: 8-bit data - @"16_BIT_DATA" = 1, // desc: 16-bit data - @"32_BIT_DATA" = 3, // desc: 32-bit data - _, // non-exhaustive - }, - MONO: u1, // bit offset: 2 desc: When 1, data is of monaural format. When 0, the data is in stereo format. - STOP: u1, // bit offset: 3 desc: When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - RESET: u1, // bit offset: 4 desc: When 1, asynchronously reset the transmit channel and FIFO. - WS_SEL: u1, // bit offset: 5 desc: When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. - WS_HALFPERIOD: u9, // bit offset: 6 desc: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - // RESERVED: u17, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. - pub const TXFIFO = mmio(Address + 0x00000008, 32, packed struct { - I2STXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. - }); - // byte offset: 12 I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. - pub const RXFIFO = mmio(Address + 0x0000000c, 32, packed struct { - I2SRXFIFO: u32, // bit offset: 0 desc: 8 x 32-bit transmit FIFO. - }); - // byte offset: 16 I2S Status Feedback Register. Contains status information about the I2S interface. - pub const STATE = mmio(Address + 0x00000010, 32, packed struct { - IRQ: u1, // bit offset: 0 desc: This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. - DMAREQ1: u1, // bit offset: 1 desc: This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. - DMAREQ2: u1, // bit offset: 2 desc: This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. - // RESERVED: u5, // bit offset: 3 desc: Reserved. - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_LEVEL: u4, // bit offset: 8 desc: Reflects the current level of the Receive FIFO. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - TX_LEVEL: u4, // bit offset: 16 desc: Reflects the current level of the Transmit FIFO. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 I2S DMA Configuration Register 1. Contains control information for DMA request 1. - pub const DMA1 = mmio(Address + 0x00000014, 32, packed struct { - RX_DMA1_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA1_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. - // RESERVED: u6, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_DMA1: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA1. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_DMA1: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA1. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 I2S DMA Configuration Register 2. Contains control information for DMA request 2. - pub const DMA2 = mmio(Address + 0x00000018, 32, packed struct { - RX_DMA2_ENABLE: u1, // bit offset: 0 desc: When 1, enables DMA1 for I2S receive. - TX_DMA2_ENABLE: u1, // bit offset: 1 desc: When 1, enables DMA1 for I2S transmit. - // RESERVED: u6, // bit offset: 2 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_DMA2: u4, // bit offset: 8 desc: Set the FIFO level that triggers a receive DMA request on DMA2. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_DMA2: u4, // bit offset: 16 desc: Set the FIFO level that triggers a transmit DMA request on DMA2. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. - pub const IRQ = mmio(Address + 0x0000001c, 32, packed struct { - RX_IRQ_ENABLE: u1, // bit offset: 0 desc: When 1, enables I2S receive interrupt. - TX_IRQ_ENABLE: u1, // bit offset: 1 desc: When 1, enables I2S transmit interrupt. - // RESERVED: u6, // bit offset: 2 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RX_DEPTH_IRQ: u4, // bit offset: 8 desc: Set the FIFO level on which to create an irq request. - // RESERVED: u4, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - TX_DEPTH_IRQ: u4, // bit offset: 16 desc: Set the FIFO level on which to create an irq request. - // RESERVED: u12, // bit offset: 20 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. - pub const TXRATE = mmio(Address + 0x00000020, 32, packed struct { - Y_DIVIDER: u8, // bit offset: 0 desc: I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. - X_DIVIDER: u8, // bit offset: 8 desc: I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. - pub const RXRATE = mmio(Address + 0x00000024, 32, packed struct { - Y_DIVIDER: u8, // bit offset: 0 desc: I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. - X_DIVIDER: u8, // bit offset: 8 desc: I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. - // RESERVED: u16, // bit offset: 16 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. - pub const TXBITRATE = mmio(Address + 0x00000028, 32, packed struct { - TX_BITRATE: u6, // bit offset: 0 desc: I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. - pub const RXBITRATE = mmio(Address + 0x0000002c, 32, packed struct { - RX_BITRATE: u6, // bit offset: 0 desc: I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. - // RESERVED: u26, // bit offset: 6 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 I2S Transmit mode control. - pub const TXMODE = mmio(Address + 0x00000030, 32, packed struct { - TXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the transmit bit clock divider. - @"SELECT_THE_TX_FRACTI" = 0, // desc: Select the TX fractional rate divider clock output as the source - @"SELECT_THE_RX_MCLK_S" = 2, // desc: Select the RX_MCLK signal as the TX_MCLK clock source - _, // non-exhaustive - }, - TX4PIN: u1, // bit offset: 2 desc: Transmit 4-pin mode selection. When 1, enables 4-pin mode. - TXMCENA: u1, // bit offset: 3 desc: Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 I2S Receive mode control. - pub const RXMODE = mmio(Address + 0x00000034, 32, packed struct { - RXCLKSEL: enum(u2) { // bit offset: 0 desc: Clock source selection for the receive bit clock divider. - @"SELECT_THE_RX_FRACTI" = 0, // desc: Select the RX fractional rate divider clock output as the source - @"SELECT_THE_TX_MCLK_S" = 2, // desc: Select the TX_MCLK signal as the RX_MCLK clock source - _, // non-exhaustive - }, - RX4PIN: u1, // bit offset: 2 desc: Receive 4-pin mode selection. When 1, enables 4-pin mode. - RXMCENA: u1, // bit offset: 3 desc: Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const RITIMER = extern struct { - pub const Address: u32 = 0x400b0000; - // byte offset: 0 Compare register - pub const COMPVAL = mmio(Address + 0x00000000, 32, packed struct { - RICOMP: u32, // bit offset: 0 desc: Compare register. Holds the compare value which is compared to the counter. - }); - // byte offset: 4 Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. - pub const MASK = mmio(Address + 0x00000004, 32, packed struct { - RIMASK: u32, // bit offset: 0 desc: Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). - }); - // byte offset: 8 Control register. - pub const CTRL = mmio(Address + 0x00000008, 32, packed struct { - RITINT: enum(u1) { // bit offset: 0 desc: Interrupt flag - @"THIS_BIT_IS_SET_TO_1" = 1, // desc: This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. - @"THE_COUNTER_VALUE_DO" = 0, // desc: The counter value does not equal the masked compare value. - }, - RITENCLR: enum(u1) { // bit offset: 1 desc: Timer enable clear - @"THE_TIMER_WILL_BE_CL" = 1, // desc: The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. - @"THE_TIMER_WILL_NOT_B" = 0, // desc: The timer will not be cleared to 0. - }, - RITENBR: enum(u1) { // bit offset: 2 desc: Timer enable for debug - @"THE_TIMER_IS_HALTED_" = 1, // desc: The timer is halted when the processor is halted for debugging. - @"DEBUG_HAS_NO_EFFECT_" = 0, // desc: Debug has no effect on the timer operation. - }, - RITEN: enum(u1) { // bit offset: 3 desc: Timer enable. - @"TIMER_ENABLED_THIS_" = 1, // desc: Timer enabled. This can be overruled by a debug halt if enabled in bit 2. - @"TIMER_DISABLED_" = 0, // desc: Timer disabled. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 32-bit counter - pub const COUNTER = mmio(Address + 0x0000000c, 32, packed struct { - RICOUNTER: u32, // bit offset: 0 desc: 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. - }); -}; -pub const MCPWM = extern struct { - pub const Address: u32 = 0x400b8000; - // byte offset: 0 PWM Control read address - pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RUN0: enum(u1) { // bit offset: 0 desc: Stops/starts timer channel 0. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER0: enum(u1) { // bit offset: 1 desc: Edge/center aligned operation for channel 0. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA0: enum(u1) { // bit offset: 2 desc: Selects polarity of the MCOA0 and MCOB0 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE0: enum(u1) { // bit offset: 3 desc: Controls the dead-time feature for channel 0. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP0: enum(u1) { // bit offset: 4 desc: Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u3, // bit offset: 5 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1: enum(u1) { // bit offset: 8 desc: Stops/starts timer channel 1. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER1: enum(u1) { // bit offset: 9 desc: Edge/center aligned operation for channel 1. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA1: enum(u1) { // bit offset: 10 desc: Selects polarity of the MCOA1 and MCOB1 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE1: enum(u1) { // bit offset: 11 desc: Controls the dead-time feature for channel 1. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP1: enum(u1) { // bit offset: 12 desc: Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u3, // bit offset: 13 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2: enum(u1) { // bit offset: 16 desc: Stops/starts timer channel 2. - @"STOP_" = 0, // desc: Stop. - @"RUN_" = 1, // desc: Run. - }, - CENTER2: enum(u1) { // bit offset: 17 desc: Edge/center aligned operation for channel 2. - @"EDGE_ALIGNED_" = 0, // desc: Edge-aligned. - @"CENTER_ALIGNED_" = 1, // desc: Center-aligned. - }, - POLA2: enum(u1) { // bit offset: 18 desc: Selects polarity of the MCOA2 and MCOB2 pins. - @"PASSIVE_STATE_IS_LOW" = 0, // desc: Passive state is LOW, active state is HIGH. - @"PASSIVE_STATE_IS_HIG" = 1, // desc: Passive state is HIGH, active state is LOW. - }, - DTE2: enum(u1) { // bit offset: 19 desc: Controls the dead-time feature for channel 1. - @"DEAD_TIME_DISABLED_" = 0, // desc: Dead-time disabled. - @"DEAD_TIME_ENABLED_" = 1, // desc: Dead-time enabled. - }, - DISUP2: enum(u1) { // bit offset: 20 desc: Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). - @"UPDATE" = 0, // desc: Functional registers are updated from the write registers at the end of each PWM cycle. - @"NOUPDATE" = 1, // desc: Functional registers remain the same as long as the timer is running. - }, - // RESERVED: u8, // bit offset: 21 desc: Reserved. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC: enum(u1) { // bit offset: 29 desc: Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. - @"OPPOSITE" = 0, // desc: The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). - @"SAME" = 1, // desc: The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6) - }, - ACMODE: enum(u1) { // bit offset: 30 desc: 3-phase AC mode select (see Section 24.8.7). - @"3_PHASE_AC_MODE_OFF" = 0, // desc: 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. - @"3_PHASE_AC_MODE_ON_" = 1, // desc: 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. - }, - DCMODE: enum(u1) { // bit offset: 31 desc: 3-phase DC mode select (see Section 24.8.6). - @"3_PHASE_DC_MODE_OFF" = 0, // desc: 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) - @"3_PHASE_DC_MODE_ON_" = 1, // desc: 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. - }, - }); - // byte offset: 4 PWM Control set address - pub const CON_SET = mmio(Address + 0x00000004, 32, packed struct { - RUN0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CON register. - CENTER0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CON register. - POLA0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CON register. - DTE0_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CON register. - DISUP0_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CON register. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CON register. - CENTER1_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CON register. - POLA1_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CON register. - DTE1_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CON register. - DISUP1_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CON register. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CON register. - CENTER2_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CON register. - POLA2_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bit in the CON register. - DTE2_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bit in the CON register. - DISUP2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bit in the CON register. - // RESERVED: u8, // bit offset: 21 desc: Writing a one sets the corresponding bit in the CON register. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CON register. - ACMODE_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CON register. - DCMODE_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CON register. - }); - // byte offset: 8 PWM Control clear address - pub const CON_CLR = mmio(Address + 0x00000008, 32, packed struct { - RUN0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CON register. - CENTER0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CON register. - POLA0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CON register. - DTE0_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CON register. - DISUP0_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CON register. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RUN1_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CON register. - CENTER1_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CON register. - POLA1_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CON register. - DTE1_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CON register. - DISUP1_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u3, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CON register. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - RUN2_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CON register. - CENTER2_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CON register. - POLA2_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bit in the CON register. - DTE2_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bit in the CON register. - DISUP2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bit in the CON register. - // RESERVED: u8, // bit offset: 21 desc: Writing a one clears the corresponding bit in the CON register. - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - INVBDC_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CON register. - ACMOD_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CON register. - DCMODE_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CON register. - }); - // byte offset: 12 Capture Control read address - pub const CAPCON = mmio(Address + 0x0000000c, 32, packed struct { - CAP0MCI0_RE: u1, // bit offset: 0 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. - CAP0MCI0_FE: u1, // bit offset: 1 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. - CAP0MCI1_RE: u1, // bit offset: 2 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. - CAP0MCI1_FE: u1, // bit offset: 3 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. - CAP0MCI2_RE: u1, // bit offset: 4 desc: A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. - CAP0MCI2_FE: u1, // bit offset: 5 desc: A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. - CAP1MCI0_RE: u1, // bit offset: 6 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. - CAP1MCI0_FE: u1, // bit offset: 7 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. - CAP1MCI1_RE: u1, // bit offset: 8 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. - CAP1MCI1_FE: u1, // bit offset: 9 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. - CAP1MCI2_RE: u1, // bit offset: 10 desc: A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. - CAP1MCI2_FE: u1, // bit offset: 11 desc: A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. - CAP2MCI0_RE: u1, // bit offset: 12 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. - CAP2MCI0_FE: u1, // bit offset: 13 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. - CAP2MCI1_RE: u1, // bit offset: 14 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. - CAP2MCI1_FE: u1, // bit offset: 15 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. - CAP2MCI2_RE: u1, // bit offset: 16 desc: A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. - CAP2MCI2_FE: u1, // bit offset: 17 desc: A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. - RT0: u1, // bit offset: 18 desc: If this bit is 1, TC0 is reset by a channel 0 capture event. - RT1: u1, // bit offset: 19 desc: If this bit is 1, TC1 is reset by a channel 1 capture event. - RT2: u1, // bit offset: 20 desc: If this bit is 1, TC2 is reset by a channel 2 capture event. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Capture Control set address - pub const CAPCON_SET = mmio(Address + 0x00000010, 32, packed struct { - CAP0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT0_SET: u1, // bit offset: 18 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT1_SET: u1, // bit offset: 19 desc: Writing a one sets the corresponding bits in the CAPCON register. - RT2_SET: u1, // bit offset: 20 desc: Writing a one sets the corresponding bits in the CAPCON register. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Event Control clear address - pub const CAPCON_CLR = mmio(Address + 0x00000014, 32, packed struct { - CAP0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_RE_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT0_CLR: u1, // bit offset: 18 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT1_CLR: u1, // bit offset: 19 desc: Writing a one clears the corresponding bits in the CAPCON register. - RT2_CLR: u1, // bit offset: 20 desc: Writing a one clears the corresponding bits in the CAPCON register. - // RESERVED: u11, // bit offset: 21 desc: Reserved. - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 Timer Counter register - pub const TC_0 = mmio(Address + 0x00000018, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 28 Timer Counter register - pub const TC_1 = mmio(Address + 0x0000001c, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 32 Timer Counter register - pub const TC_2 = mmio(Address + 0x00000020, 32, packed struct { - MCTC: u32, // bit offset: 0 desc: Timer/Counter value. - }); - // byte offset: 36 Limit register - pub const LIM_0 = mmio(Address + 0x00000024, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 40 Limit register - pub const LIM_1 = mmio(Address + 0x00000028, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 44 Limit register - pub const LIM_2 = mmio(Address + 0x0000002c, 32, packed struct { - MCLIM: u32, // bit offset: 0 desc: Limit value. - }); - // byte offset: 48 Match register - pub const MAT_0 = mmio(Address + 0x00000030, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 52 Match register - pub const MAT_1 = mmio(Address + 0x00000034, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 56 Match register - pub const MAT_2 = mmio(Address + 0x00000038, 32, packed struct { - MCMAT: u32, // bit offset: 0 desc: Match value. - }); - // byte offset: 60 Dead time register - pub const DT = mmio(Address + 0x0000003c, 32, packed struct { - DT0: u10, // bit offset: 0 desc: Dead time for channel 0.[1] - DT1: u10, // bit offset: 10 desc: Dead time for channel 1.[2] - DT2: u10, // bit offset: 20 desc: Dead time for channel 2.[2] - // RESERVED: u2, // bit offset: 30 desc: reserved - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Communication Pattern register - pub const CP = mmio(Address + 0x00000040, 32, packed struct { - CCPA0: enum(u1) { // bit offset: 0 desc: Communication pattern output A, channel 0. - @"MCOA0_PASSIVE_" = 0, // desc: MCOA0 passive. - @"INTERNAL_MCOA0_" = 1, // desc: internal MCOA0. - }, - CCPB0: enum(u1) { // bit offset: 1 desc: Communication pattern output B, channel 0. - @"MCOB0_PASSIVE_" = 0, // desc: MCOB0 passive. - @"MCOB0_TRACKS_INTERNA" = 1, // desc: MCOB0 tracks internal MCOA0. - }, - CCPA1: enum(u1) { // bit offset: 2 desc: Communication pattern output A, channel 1. - @"MCOA1_PASSIVE_" = 0, // desc: MCOA1 passive. - @"MCOA1_TRACKS_INTERNA" = 1, // desc: MCOA1 tracks internal MCOA0. - }, - CCPB1: enum(u1) { // bit offset: 3 desc: Communication pattern output B, channel 1. - @"MCOB1_PASSIVE_" = 0, // desc: MCOB1 passive. - @"MCOB1_TRACKS_INTERNA" = 1, // desc: MCOB1 tracks internal MCOA0. - }, - CCPA2: enum(u1) { // bit offset: 4 desc: Communication pattern output A, channel 2. - @"MCOA2_PASSIVE_" = 0, // desc: MCOA2 passive. - @"MCOA2_TRACKS_INTERNA" = 1, // desc: MCOA2 tracks internal MCOA0. - }, - CCPB2: enum(u1) { // bit offset: 5 desc: Communication pattern output B, channel 2. - @"MCOB2_PASSIVE_" = 0, // desc: MCOB2 passive. - @"MCOB2_TRACKS_INTERNA" = 1, // desc: MCOB2 tracks internal MCOA0. - }, - // RESERVED: u26, // bit offset: 6 desc: Reserved. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 Capture register - pub const CAP_0 = mmio(Address + 0x00000044, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 72 Capture register - pub const CAP_1 = mmio(Address + 0x00000048, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 76 Capture register - pub const CAP_2 = mmio(Address + 0x0000004c, 32, packed struct { - CAP: u32, // bit offset: 0 desc: Current TC value at a capture event. - }); - // byte offset: 80 Interrupt Enable read address - pub const INTEN = mmio(Address + 0x00000050, 32, packed struct { - ILIM0: enum(u1) { // bit offset: 0 desc: Limit interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT0: enum(u1) { // bit offset: 1 desc: Match interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP0: enum(u1) { // bit offset: 2 desc: Capture interrupt for channel 0. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1: enum(u1) { // bit offset: 4 desc: Limit interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT1: enum(u1) { // bit offset: 5 desc: Match interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP1: enum(u1) { // bit offset: 6 desc: Capture interrupt for channel 1. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2: enum(u1) { // bit offset: 8 desc: Limit interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - IMAT2: enum(u1) { // bit offset: 9 desc: Match interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - ICAP2: enum(u1) { // bit offset: 10 desc: Capture interrupt for channel 2. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT: enum(u1) { // bit offset: 15 desc: Fast abort interrupt. - @"INTERRUPT_DISABLED_" = 0, // desc: Interrupt disabled. - @"INTERRUPT_ENABLED_" = 1, // desc: Interrupt enabled. - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 84 Interrupt Enable set address - pub const INTEN_SET = mmio(Address + 0x00000054, 32, packed struct { - ILIM0_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT0_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP0_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT1_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP1_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved3: u1 = 0, - reserved2: u1 = 0, - ILIM2_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT2_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP2_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u3, // bit offset: 12 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - ABORT_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 88 Interrupt Enable clear address - pub const INTEN_CLR = mmio(Address + 0x00000058, 32, packed struct { - ILIM0_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT0_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 92 Count Control read address - pub const CNTCON = mmio(Address + 0x0000005c, 32, packed struct { - TC0MCI0_RE: enum(u1) { // bit offset: 0 desc: Counter 0 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI0. - }, - TC0MCI0_FE: enum(u1) { // bit offset: 1 desc: Counter 0 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. - @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI0. - }, - TC0MCI1_RE: enum(u1) { // bit offset: 2 desc: Counter 0 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI1. - }, - TC0MCI1_FE: enum(u1) { // bit offset: 3 desc: Counter 0 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 0. - @"FALLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI1. - }, - TC0MCI2_RE: enum(u1) { // bit offset: 4 desc: Counter 0 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 0. - @"RISING" = 1, // desc: If MODE0 is 1, counter 0 advances on a rising edge on MCI2. - }, - TC0MCI2_FE: enum(u1) { // bit offset: 5 desc: Counter 0 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 0. - @"FALLLING" = 1, // desc: If MODE0 is 1, counter 0 advances on a falling edge on MCI2. - }, - TC1MCI0_RE: enum(u1) { // bit offset: 6 desc: Counter 1 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI0. - }, - TC1MCI0_FE: enum(u1) { // bit offset: 7 desc: Counter 1 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI0. - }, - TC1MCI1_RE: enum(u1) { // bit offset: 8 desc: Counter 1 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI1. - }, - TC1MCI1_FE: enum(u1) { // bit offset: 9 desc: Counter 1 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI1. - }, - TC1MCI2_RE: enum(u1) { // bit offset: 10 desc: Counter 1 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 1. - @"RISING" = 1, // desc: If MODE1 is 1, counter 1 advances on a rising edge on MCI2. - }, - TC1MCI2_FE: enum(u1) { // bit offset: 11 desc: Counter 1 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 1. - @"FALLING" = 1, // desc: If MODE1 is 1, counter 1 advances on a falling edge on MCI2. - }, - TC2MCI0_RE: enum(u1) { // bit offset: 12 desc: Counter 2 rising edge mode, channel 0. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI0 does not affect counter 2. - @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI0. - }, - TC2MCI0_FE: enum(u1) { // bit offset: 13 desc: Counter 2 falling edge mode, channel 0. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI0 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI0. - }, - TC2MCI1_RE: enum(u1) { // bit offset: 14 desc: Counter 2 rising edge mode, channel 1. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI1 does not affect counter 2. - @"RISING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI1. - }, - TC2MCI1_FE: enum(u1) { // bit offset: 15 desc: Counter 2 falling edge mode, channel 1. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI1 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI1. - }, - TC2MCI2_RE: enum(u1) { // bit offset: 16 desc: Counter 2 rising edge mode, channel 2. - @"A_RISING_EDGE_ON_MCI" = 0, // desc: A rising edge on MCI2 does not affect counter 2. - @"RISIING" = 1, // desc: If MODE2 is 1, counter 2 advances on a rising edge on MCI2. - }, - TC2MCI2_FE: enum(u1) { // bit offset: 17 desc: Counter 2 falling edge mode, channel 2. - @"A_FALLING_EDGE_ON_MC" = 0, // desc: A falling edge on MCI2 does not affect counter 2. - @"FALLING" = 1, // desc: If MODE2 is 1, counter 2 advances on a falling edge on MCI2. - }, - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0: enum(u1) { // bit offset: 29 desc: Channel 0 counter/timer mode. - @"CHANNEL_0_IS_IN_TIME" = 0, // desc: Channel 0 is in timer mode. - @"CHANNEL_0_IS_IN_COUN" = 1, // desc: Channel 0 is in counter mode. - }, - CNTR1: enum(u1) { // bit offset: 30 desc: Channel 1 counter/timer mode. - @"CHANNEL_1_IS_IN_TIME" = 0, // desc: Channel 1 is in timer mode. - @"CHANNEL_1_IS_IN_COUN" = 1, // desc: Channel 1 is in counter mode. - }, - CNTR2: enum(u1) { // bit offset: 31 desc: Channel 2 counter/timer mode. - @"CHANNEL_2_IS_IN_TIME" = 0, // desc: Channel 2 is in timer mode. - @"CHANNEL_2_IS_IN_COUN" = 1, // desc: Channel 2 is in counter mode. - }, - }); - // byte offset: 96 Count Control set address - pub const CNTCON_SET = mmio(Address + 0x00000060, 32, packed struct { - TC0MCI0_RE_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI0_FE_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_RE_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_FE_SET: u1, // bit offset: 3 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_RE_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_FE_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_RE_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_FE_SET: u1, // bit offset: 7 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_RE_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_FE_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_RE_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_FE_SET: u1, // bit offset: 11 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_RE_SET: u1, // bit offset: 12 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_FE_SET: u1, // bit offset: 13 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_RE_SET: u1, // bit offset: 14 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_FE_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_RE_SET: u1, // bit offset: 16 desc: Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_FE_SET: u1, // bit offset: 17 desc: Writing a one sets the corresponding bit in the CNTCON register. - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0_SET: u1, // bit offset: 29 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR1_SET: u1, // bit offset: 30 desc: Writing a one sets the corresponding bit in the CNTCON register. - CNTR2_SET: u1, // bit offset: 31 desc: Writing a one sets the corresponding bit in the CNTCON register. - }); - // byte offset: 100 Count Control clear address - pub const CNTCON_CLR = mmio(Address + 0x00000064, 32, packed struct { - TC0MCI0_RE_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI0_FE_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_RE_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_FE_CLR: u1, // bit offset: 3 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_RE: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_FE_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_RE_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_FE_CLR: u1, // bit offset: 7 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_RE_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_FE_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_RE_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_FE_CLR: u1, // bit offset: 11 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_RE_CLR: u1, // bit offset: 12 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_FE_CLR: u1, // bit offset: 13 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_RE_CLR: u1, // bit offset: 14 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_FE_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_RE_CLR: u1, // bit offset: 16 desc: Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_FE_CLR: u1, // bit offset: 17 desc: Writing a one clears the corresponding bit in the CNTCON register. - // RESERVED: u11, // bit offset: 18 desc: Reserved. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CNTR0_CLR: u1, // bit offset: 29 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR1_CLR: u1, // bit offset: 30 desc: Writing a one clears the corresponding bit in the CNTCON register. - CNTR2_CLR: u1, // bit offset: 31 desc: Writing a one clears the corresponding bit in the CNTCON register. - }); - // byte offset: 104 Interrupt flags read address - pub const INTF = mmio(Address + 0x00000068, 32, packed struct { - ILIM0_F: enum(u1) { // bit offset: 0 desc: Limit interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT0_F: enum(u1) { // bit offset: 1 desc: Match interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP0_F: enum(u1) { // bit offset: 2 desc: Capture interrupt flag for channel 0. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F: enum(u1) { // bit offset: 4 desc: Limit interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT1_F: enum(u1) { // bit offset: 5 desc: Match interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP1_F: enum(u1) { // bit offset: 6 desc: Capture interrupt flag for channel 1. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F: enum(u1) { // bit offset: 8 desc: Limit interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - IMAT2_F: enum(u1) { // bit offset: 9 desc: Match interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - ICAP2_F: enum(u1) { // bit offset: 10 desc: Capture interrupt flag for channel 2. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F: enum(u1) { // bit offset: 15 desc: Fast abort interrupt flag. - @"THIS_INTERRUPT_SOURC" = 0, // desc: This interrupt source is not contributing to the MCPWM interrupt request. - @"IF_THE_CORRESPONDING" = 1, // desc: If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 108 Interrupt flags set address - pub const INTF_SET = mmio(Address + 0x0000006c, 32, packed struct { - ILIM0_F_SET: u1, // bit offset: 0 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT0_F_SET: u1, // bit offset: 1 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP0_F_SET: u1, // bit offset: 2 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F_SET: u1, // bit offset: 4 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT1_F_SET: u1, // bit offset: 5 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP1_F_SET: u1, // bit offset: 6 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F_SET: u1, // bit offset: 8 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - IMAT2_F_SET: u1, // bit offset: 9 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - ICAP2_F_SET: u1, // bit offset: 10 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u4, // bit offset: 11 desc: Reserved. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F_SET: u1, // bit offset: 15 desc: Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 112 Interrupt flags clear address - pub const INTF_CLR = mmio(Address + 0x00000070, 32, packed struct { - ILIM0_F_CLR: u1, // bit offset: 0 desc: Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. - IMAT0_F_CLR: u1, // bit offset: 1 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP0_F_CLR: u1, // bit offset: 2 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 3 desc: Reserved. - reserved1: u1 = 0, - ILIM1_F_CLR: u1, // bit offset: 4 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT1_F_CLR: u1, // bit offset: 5 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP1_F_CLR: u1, // bit offset: 6 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u1, // bit offset: 7 desc: Reserved. - reserved2: u1 = 0, - ILIM2_F_CLR: u1, // bit offset: 8 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - IMAT2_F_CLR: u1, // bit offset: 9 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - ICAP2_F_CLR: u1, // bit offset: 10 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u4, // bit offset: 11 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - ABORT_F_CLR: u1, // bit offset: 15 desc: Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. - // RESERVED: u16, // bit offset: 16 desc: Reserved. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 116 Capture clear address - pub const CAP_CLR = mmio(Address + 0x00000074, 32, packed struct { - CAP_CLR0: u1, // bit offset: 0 desc: Writing a 1 to this bit clears the CAP0 register. - CAP_CLR1: u1, // bit offset: 1 desc: Writing a 1 to this bit clears the CAP1 register. - CAP_CLR2: u1, // bit offset: 2 desc: Writing a 1 to this bit clears the CAP2 register. - // RESERVED: u29, // bit offset: 3 desc: Reserved - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const QEI = extern struct { - pub const Address: u32 = 0x400bc000; - // byte offset: 0 Control register - pub const CON = mmio(Address + 0x00000000, 32, packed struct { - RESP: u1, // bit offset: 0 desc: Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. - RESPI: u1, // bit offset: 1 desc: Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. - RESV: u1, // bit offset: 2 desc: Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. - RESI: u1, // bit offset: 3 desc: Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 Status register - pub const STAT = mmio(Address + 0x00000004, 32, packed struct { - DIR: u1, // bit offset: 0 desc: Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. - // RESERVED: u31, // bit offset: 1 desc: Reserved. Read value is undefined, only zero should be written. - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Configuration register - pub const CONF = mmio(Address + 0x00000008, 32, packed struct { - DIRINV: u1, // bit offset: 0 desc: Direction invert. When 1, complements the DIR bit. - SIGMODE: u1, // bit offset: 1 desc: Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. - CAPMODE: u1, // bit offset: 2 desc: Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. - INVINX: u1, // bit offset: 3 desc: Invert Index. When 1, inverts the sense of the index input. - CRESPI: u1, // bit offset: 4 desc: Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). - // RESERVED: u11, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - INXGATE: u4, // bit offset: 16 desc: Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. - // RESERVED: u12, // bit offset: 20 desc: Reserved. Read value is undefined, only zero should be written. - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Position register - pub const POS = mmio(Address + 0x0000000c, 32, packed struct { - POS: u32, // bit offset: 0 desc: Current position value. - }); - // byte offset: 16 Maximum position register - pub const MAXPOS = mmio(Address + 0x00000010, 32, packed struct { - MAXPOS: u32, // bit offset: 0 desc: Current maximum position value. - }); - // byte offset: 20 Position compare register 0 - pub const CMPOS0 = mmio(Address + 0x00000014, 32, packed struct { - PCMP0: u32, // bit offset: 0 desc: Position compare value 0. - }); - // byte offset: 24 Position compare register 1 - pub const CMPOS1 = mmio(Address + 0x00000018, 32, packed struct { - PCMP1: u32, // bit offset: 0 desc: Position compare value 1. - }); - // byte offset: 28 Position compare register 2 - pub const CMPOS2 = mmio(Address + 0x0000001c, 32, packed struct { - PCMP2: u32, // bit offset: 0 desc: Position compare value 2. - }); - // byte offset: 32 Index count register 0 - pub const INXCNT = mmio(Address + 0x00000020, 32, packed struct { - ENCPOS: u32, // bit offset: 0 desc: Current index counter value. - }); - // byte offset: 36 Index compare register 0 - pub const INXCMP0 = mmio(Address + 0x00000024, 32, packed struct { - ICMP0: u32, // bit offset: 0 desc: Index compare value 0. - }); - // byte offset: 40 Velocity timer reload register - pub const LOAD = mmio(Address + 0x00000028, 32, packed struct { - VELLOAD: u32, // bit offset: 0 desc: Current velocity timer load value. - }); - // byte offset: 44 Velocity timer register - pub const TIME = mmio(Address + 0x0000002c, 32, packed struct { - VELVAL: u32, // bit offset: 0 desc: Current velocity timer value. - }); - // byte offset: 48 Velocity counter register - pub const VEL = mmio(Address + 0x00000030, 32, packed struct { - VELPC: u32, // bit offset: 0 desc: Current velocity pulse count. - }); - // byte offset: 52 Velocity capture register - pub const CAP = mmio(Address + 0x00000034, 32, packed struct { - VELCAP: u32, // bit offset: 0 desc: Last velocity capture. - }); - // byte offset: 56 Velocity compare register - pub const VELCOMP = mmio(Address + 0x00000038, 32, packed struct { - VELPC: u32, // bit offset: 0 desc: Compare velocity pulse count. - }); - // byte offset: 60 Digital filter register - pub const FILTER = mmio(Address + 0x0000003c, 32, packed struct { - FILTA: u32, // bit offset: 0 desc: Digital filter sampling delay. - }); - // byte offset: 4056 Interrupt enable clear register - pub const IEC = mmio(Address + 0x00000fd8, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 disables the INX_Int interrupt in the QEIIE register. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 disables the TIN_Int interrupt in the QEIIE register. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 disables the VELC_Int interrupt in the QEIIE register. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 disables the DIR_Int interrupt in the QEIIE register. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 disables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 disables the POS0_Int interrupt in the QEIIE register. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 disables the POS1_Int interrupt in the QEIIE register. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 disables the POS2_Int interrupt in the QEIIE register. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 disables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 disables the REV1_Int interrupt in the QEIIE register. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 disables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4060 Interrupt enable set register - pub const IES = mmio(Address + 0x00000fdc, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 enables the INX_Int interrupt in the QEIIE register. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 enables the TIN_Int interrupt in the QEIIE register. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 enables the VELC_Int interrupt in the QEIIE register. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 enables the DIR_Int interrupt in the QEIIE register. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 enables the ERR_Int interrupt in the QEIIE register. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 enables the POS0_Int interrupt in the QEIIE register. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 enables the POS1_Int interrupt in the QEIIE register. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 enables the POS2_Int interrupt in the QEIIE register. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 enables the REV0_Int interrupt in the QEIIE register. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 enables the REV1_Int interrupt in the QEIIE register. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 enables the REV2_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4064 Interrupt status register - pub const INTSTAT = mmio(Address + 0x00000fe0, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Indicates that an index pulse was detected. - TIM_INT: u1, // bit offset: 1 desc: Indicates that a velocity timer overflow occurred - VELC_INT: u1, // bit offset: 2 desc: Indicates that captured velocity is less than compare velocity. - DIR_INT: u1, // bit offset: 3 desc: Indicates that a change of direction was detected. - ERR_INT: u1, // bit offset: 4 desc: Indicates that an encoder phase error was detected. - ENCLK_INT: u1, // bit offset: 5 desc: Indicates that and encoder clock pulse was detected. - POS0_INT: u1, // bit offset: 6 desc: Indicates that the position 0 compare value is equal to the current position. - POS1_INT: u1, // bit offset: 7 desc: Indicates that the position 1compare value is equal to the current position. - POS2_INT: u1, // bit offset: 8 desc: Indicates that the position 2 compare value is equal to the current position. - REV0_INT: u1, // bit offset: 9 desc: Indicates that the index compare 0 value is equal to the current index count. - POS0REV_INT: u1, // bit offset: 10 desc: Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. - POS1REV_INT: u1, // bit offset: 11 desc: Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. - POS2REV_INT: u1, // bit offset: 12 desc: Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. - REV1_INT: u1, // bit offset: 13 desc: Indicates that the index compare 1value is equal to the current index count. - REV2_INT: u1, // bit offset: 14 desc: Indicates that the index compare 2 value is equal to the current index count. - MAXPOS_INT: u1, // bit offset: 15 desc: Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4068 Interrupt enable register - pub const IE = mmio(Address + 0x00000fe4, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: When 1, the INX_Int interrupt is enabled. - TIM_INT: u1, // bit offset: 1 desc: When 1, the TIN_Int interrupt is enabled. - VELC_INT: u1, // bit offset: 2 desc: When 1, the VELC_Int interrupt is enabled. - DIR_INT: u1, // bit offset: 3 desc: When 1, the DIR_Int interrupt is enabled. - ERR_INT: u1, // bit offset: 4 desc: When 1, the ERR_Int interrupt is enabled. - ENCLK_INT: u1, // bit offset: 5 desc: When 1, the ENCLK_Int interrupt is enabled. - POS0_INT: u1, // bit offset: 6 desc: When 1, the POS0_Int interrupt is enabled. - POS1_INT: u1, // bit offset: 7 desc: When 1, the POS1_Int interrupt is enabled. - POS2_INT: u1, // bit offset: 8 desc: When 1, the POS2_Int interrupt is enabled. - REV0_INT: u1, // bit offset: 9 desc: When 1, the REV0_Int interrupt is enabled. - POS0REV_INT: u1, // bit offset: 10 desc: When 1, the POS0REV_Int interrupt is enabled. - POS1REV_INT: u1, // bit offset: 11 desc: When 1, the POS1REV_Int interrupt is enabled. - POS2REV_INT: u1, // bit offset: 12 desc: When 1, the POS2REV_Int interrupt is enabled. - REV1_INT: u1, // bit offset: 13 desc: When 1, the REV1_Int interrupt is enabled. - REV2_INT: u1, // bit offset: 14 desc: When 1, the REV2_Int interrupt is enabled. - MAXPOS_INT: u1, // bit offset: 15 desc: When 1, the MAXPOS_Int interrupt is enabled. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4072 Interrupt status clear register - pub const CLR = mmio(Address + 0x00000fe8, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 clears the INX_Int bit in QEIINTSTAT. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 clears the TIN_Int bit in QEIINTSTAT. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 clears the VELC_Int bit in QEIINTSTAT. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 clears the DIR_Int bit in QEIINTSTAT. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 clears the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 clears the POS0_Int bit in QEIINTSTAT. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 clears the POS1_Int bit in QEIINTSTAT. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 clears the POS2_Int bit in QEIINTSTAT. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 clears the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 clears the REV1_Int bit in QEIINTSTAT. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 clears the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4076 Interrupt status set register - pub const SET = mmio(Address + 0x00000fec, 32, packed struct { - INX_INT: u1, // bit offset: 0 desc: Writing a 1 sets the INX_Int bit in QEIINTSTAT. - TIM_INT: u1, // bit offset: 1 desc: Writing a 1 sets the TIN_Int bit in QEIINTSTAT. - VELC_INT: u1, // bit offset: 2 desc: Writing a 1 sets the VELC_Int bit in QEIINTSTAT. - DIR_INT: u1, // bit offset: 3 desc: Writing a 1 sets the DIR_Int bit in QEIINTSTAT. - ERR_INT: u1, // bit offset: 4 desc: Writing a 1 sets the ERR_Int bit in QEIINTSTAT. - ENCLK_INT: u1, // bit offset: 5 desc: Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. - POS0_INT: u1, // bit offset: 6 desc: Writing a 1 sets the POS0_Int bit in QEIINTSTAT. - POS1_INT: u1, // bit offset: 7 desc: Writing a 1 sets the POS1_Int bit in QEIINTSTAT. - POS2_INT: u1, // bit offset: 8 desc: Writing a 1 sets the POS2_Int bit in QEIINTSTAT. - REV0_INT: u1, // bit offset: 9 desc: Writing a 1 sets the REV0_Int bit in QEIINTSTAT. - POS0REV_INT: u1, // bit offset: 10 desc: Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, // bit offset: 11 desc: Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, // bit offset: 12 desc: Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. - REV1_INT: u1, // bit offset: 13 desc: Writing a 1 sets the REV1_Int bit in QEIINTSTAT. - REV2_INT: u1, // bit offset: 14 desc: Writing a 1 sets the REV2_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, // bit offset: 15 desc: Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const SYSCON = extern struct { - pub const Address: u32 = 0x400fc000; - // byte offset: 0 Flash Accelerator Configuration Register. Controls flash access timing. - pub const FLASHCFG = mmio(Address + 0x00000000, 32, packed struct { - // RESERVED: u12, // bit offset: 0 desc: Reserved, user software should not change these bits from the reset value. - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - FLASHTIM: enum(u4) { // bit offset: 12 desc: Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. - @"1CLK" = 0, // desc: Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. - @"2CLK" = 1, // desc: Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. - @"3CLK" = 2, // desc: Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. - @"4CLK" = 3, // desc: Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. - @"5CLK" = 4, // desc: Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. - @"6CLK" = 5, // desc: Flash accesses use 6 CPU clocks. This safe setting will work under any conditions. - _, // non-exhaustive - }, - // RESERVED: u16, // bit offset: 16 desc: Reserved. The value read from a reserved bit is not defined. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 128 PLL0 Control Register - pub const PLL0CON = mmio(Address + 0x00000080, 32, packed struct { - PLLE0: u1, // bit offset: 0 desc: PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register. - PLLC0: u1, // bit offset: 1 desc: PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register. - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 132 PLL0 Configuration Register - pub const PLL0CFG = mmio(Address + 0x00000084, 32, packed struct { - MSEL0: u15, // bit offset: 0 desc: PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware. - // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - NSEL0: u8, // bit offset: 16 desc: PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32. - // RESERVED: u8, // bit offset: 24 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 136 PLL0 Status Register - pub const PLL0STAT = mmio(Address + 0x00000088, 32, packed struct { - MSEL0: u15, // bit offset: 0 desc: Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier. - // RESERVED: u1, // bit offset: 15 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - NSEL0: u8, // bit offset: 16 desc: Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider. - PLLE0_STAT: u1, // bit offset: 24 desc: Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. - PLLC0_STAT: u1, // bit offset: 25 desc: Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. - PLOCK0: u1, // bit offset: 26 desc: Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. - // RESERVED: u5, // bit offset: 27 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 140 PLL0 Feed Register - pub const PLL0FEED = mmio(Address + 0x0000008c, 32, packed struct { - PLL0FEED: u8, // bit offset: 0 desc: The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 160 PLL1 Control Register - pub const PLL1CON = mmio(Address + 0x000000a0, 32, packed struct { - PLLE1: u1, // bit offset: 0 desc: PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. - PLLC1: u1, // bit offset: 1 desc: PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register. - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 164 PLL1 Configuration Register - pub const PLL1CFG = mmio(Address + 0x000000a4, 32, packed struct { - MSEL1: u5, // bit offset: 0 desc: PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. - PSEL1: u2, // bit offset: 5 desc: PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. - // RESERVED: u25, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 168 PLL1 Status Register - pub const PLL1STAT = mmio(Address + 0x000000a8, 32, packed struct { - MSEL1: u5, // bit offset: 0 desc: Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1. - PSEL1: u2, // bit offset: 5 desc: Read-back for the PLL1 Divider value. This is the value currently used by PLL1. - // RESERVED: u1, // bit offset: 7 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved1: u1 = 0, - PLLE1_STAT: u1, // bit offset: 8 desc: Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. - PLLC1_STAT: u1, // bit offset: 9 desc: Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. - PLOCK1: u1, // bit offset: 10 desc: Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. - // RESERVED: u21, // bit offset: 11 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 172 PLL1 Feed Register - pub const PLL1FEED = mmio(Address + 0x000000ac, 32, packed struct { - PLL1FEED: u8, // bit offset: 0 desc: The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 192 Power Control Register - pub const PCON = mmio(Address + 0x000000c0, 32, packed struct { - PM0: u1, // bit offset: 0 desc: Power mode control bit 0. This bit controls entry to the Power-down mode. - PM1: u1, // bit offset: 1 desc: Power mode control bit 1. This bit controls entry to the Deep Power-down mode. - BODRPM: u1, // bit offset: 2 desc: Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. - BOGD: u1, // bit offset: 3 desc: Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. - // RESERVED: u5, // bit offset: 3 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - BORD: u1, // bit offset: 4 desc: Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SMFLAG: u1, // bit offset: 8 desc: Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. - DSFLAG: u1, // bit offset: 9 desc: Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. - PDFLAG: u1, // bit offset: 10 desc: Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. - DPDFLAG: u1, // bit offset: 11 desc: Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. - // RESERVED: u20, // bit offset: 12 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 196 Power Control for Peripherals Register - pub const PCONP = mmio(Address + 0x000000c4, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. - reserved1: u1 = 0, - PCTIM0: u1, // bit offset: 1 desc: Timer/Counter 0 power/clock control bit. - PCTIM1: u1, // bit offset: 2 desc: Timer/Counter 1 power/clock control bit. - PCUART0: u1, // bit offset: 3 desc: UART0 power/clock control bit. - PCUART1: u1, // bit offset: 4 desc: UART1 power/clock control bit. - // RESERVED: u1, // bit offset: 5 desc: Reserved. - reserved2: u1 = 0, - PCPWM1: u1, // bit offset: 6 desc: PWM1 power/clock control bit. - PCI2C0: u1, // bit offset: 7 desc: The I2C0 interface power/clock control bit. - PCSPI: u1, // bit offset: 8 desc: The SPI interface power/clock control bit. - PCRTC: u1, // bit offset: 9 desc: The RTC power/clock control bit. - PCSSP1: u1, // bit offset: 10 desc: The SSP 1 interface power/clock control bit. - // RESERVED: u1, // bit offset: 11 desc: Reserved. - reserved3: u1 = 0, - PCADC: u1, // bit offset: 12 desc: A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. - PCCAN1: u1, // bit offset: 13 desc: CAN Controller 1 power/clock control bit. - PCCAN2: u1, // bit offset: 14 desc: CAN Controller 2 power/clock control bit. - PCGPIO: u1, // bit offset: 15 desc: Power/clock control bit for IOCON, GPIO, and GPIO interrupts. - PCRIT: u1, // bit offset: 16 desc: Repetitive Interrupt Timer power/clock control bit. - PCMCPWM: u1, // bit offset: 17 desc: Motor Control PWM - PCQEI: u1, // bit offset: 18 desc: Quadrature Encoder Interface power/clock control bit. - PCI2C1: u1, // bit offset: 19 desc: The I2C1 interface power/clock control bit. - // RESERVED: u1, // bit offset: 20 desc: Reserved. - reserved4: u1 = 0, - PCSSP0: u1, // bit offset: 21 desc: The SSP0 interface power/clock control bit. - PCTIM2: u1, // bit offset: 22 desc: Timer 2 power/clock control bit. - PCTIM3: u1, // bit offset: 23 desc: Timer 3 power/clock control bit. - PCUART2: u1, // bit offset: 24 desc: UART 2 power/clock control bit. - PCUART3: u1, // bit offset: 25 desc: UART 3 power/clock control bit. - PCI2C2: u1, // bit offset: 26 desc: I2C interface 2 power/clock control bit. - PCI2S: u1, // bit offset: 27 desc: I2S interface power/clock control bit. - // RESERVED: u1, // bit offset: 28 desc: Reserved. - reserved5: u1 = 0, - PCGPDMA: u1, // bit offset: 29 desc: GPDMA function power/clock control bit. - PCENET: u1, // bit offset: 30 desc: Ethernet block power/clock control bit. - PCUSB: u1, // bit offset: 31 desc: USB interface power/clock control bit. - }); - // byte offset: 260 CPU Clock Configuration Register - pub const CCLKCFG = mmio(Address + 0x00000104, 32, packed struct { - CCLKSEL: u8, // bit offset: 0 desc: Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock. - // RESERVED: u24, // bit offset: 8 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 USB Clock Configuration Register - pub const USBCLKCFG = mmio(Address + 0x00000108, 32, packed struct { - USBSEL: u4, // bit offset: 0 desc: Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 268 Clock Source Select Register - pub const CLKSRCSEL = mmio(Address + 0x0000010c, 32, packed struct { - CLKSRC: enum(u2) { // bit offset: 0 desc: Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. - @"SELECTS_THE_INTERNAL" = 0, // desc: Selects the Internal RC oscillator as the PLL0 clock source (default). - @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s. - @"SELECTS_THE_RTC_OSCI" = 2, // desc: Selects the RTC oscillator as the PLL0 clock source. - // @"RESERVED", // desc: Reserved, do not use this setting. - _, // non-exhaustive - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 272 Allows clearing the current CAN channel sleep state as well as reading that state. - pub const CANSLEEPCLR = mmio(Address + 0x00000110, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - CAN1SLEEP: u1, // bit offset: 1 desc: Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. - CAN2SLEEP: u1, // bit offset: 2 desc: Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 276 Allows reading the wake-up state of the CAN channels. - pub const CANWAKEFLAGS = mmio(Address + 0x00000114, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - CAN1WAKE: u1, // bit offset: 1 desc: Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. - CAN2WAKE: u1, // bit offset: 2 desc: Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 320 External Interrupt Flag Register - pub const EXTINT = mmio(Address + 0x00000140, 32, packed struct { - EINT0: u1, // bit offset: 0 desc: In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT1: u1, // bit offset: 1 desc: In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT2: u1, // bit offset: 2 desc: In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - EINT3: u1, // bit offset: 3 desc: In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 328 External Interrupt Mode register - pub const EXTMODE = mmio(Address + 0x00000148, 32, packed struct { - EXTMODE0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT0. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT0 is edge sensitive. - }, - EXTMODE1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT1. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT1 is edge sensitive. - }, - EXTMODE2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT2. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT2 is edge sensitive. - }, - EXTMODE3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 mode. - @"LEVEL_SENSITIVE" = 0, // desc: Level-sensitive. Level-sensitivity is selected for EINT3. - @"EDGE_SENSITIVE" = 1, // desc: Edge-sensitive. EINT3 is edge sensitive. - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 332 External Interrupt Polarity Register - pub const EXTPOLAR = mmio(Address + 0x0000014c, 32, packed struct { - EXTPOLAR0: enum(u1) { // bit offset: 0 desc: External interrupt 0 EINT0 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). - }, - EXTPOLAR1: enum(u1) { // bit offset: 1 desc: External interrupt 1 EINT1 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). - }, - EXTPOLAR2: enum(u1) { // bit offset: 2 desc: External interrupt 2 EINT2 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). - }, - EXTPOLAR3: enum(u1) { // bit offset: 3 desc: External interrupt 3 EINT3 polarity. - @"FALLING_EDGE" = 0, // desc: Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). - @"RISING_EDGE" = 1, // desc: Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). - }, - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 384 Reset Source Identification Register - pub const RSID = mmio(Address + 0x00000180, 32, packed struct { - POR: u1, // bit offset: 0 desc: Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. - EXTR: u1, // bit offset: 1 desc: Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR. - WDTR: u1, // bit offset: 2 desc: This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. - BODR: u1, // bit offset: 3 desc: This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. - // RESERVED: u28, // bit offset: 4 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 416 System control and status - pub const SCS = mmio(Address + 0x000001a0, 32, packed struct { - // RESERVED: u4, // bit offset: 0 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - OSCRANGE: enum(u1) { // bit offset: 4 desc: Main oscillator range select. - @"LOW" = 0, // desc: Low. The frequency range of the main oscillator is 1 MHz to 20 MHz. - @"HIGH" = 1, // desc: High. The frequency range of the main oscillator is 15 MHz to 25 MHz. - }, - OSCEN: enum(u1) { // bit offset: 5 desc: Main oscillator enable. - @"DISABLED" = 0, // desc: Disabled. The main oscillator is disabled. - @"ENABLED" = 1, // desc: Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. - }, - OSCSTAT: enum(u1) { // bit offset: 6 desc: Main oscillator status. - @"NOT_READY" = 0, // desc: Not ready. The main oscillator is not ready to be used as a clock source. - @"READY" = 1, // desc: Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. - }, - // RESERVED: u25, // bit offset: 7 desc: Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 424 Peripheral Clock Selection register 0. - pub const PCLKSEL0 = mmio(Address + 0x000001a8, 32, packed struct { - PCLK_WDT: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for WDT. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER0: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for TIMER0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER1: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for TIMER1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART0: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for UART0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART1: enum(u2) { // bit offset: 8 desc: Peripheral clock selection for UART1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 10 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PCLK_PWM1: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for PWM1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C0: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for I2C0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_SPI: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for SPI. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 18 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - PCLK_SSP1: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for SSP1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_DAC: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for DAC. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_ADC: enum(u2) { // bit offset: 24 desc: Peripheral clock selection for ADC. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_CAN1: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6. - }, - PCLK_CAN2: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6, - }, - PCLK_ACF: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_6" = 3, // desc: CCLK div 6. PCLK_peripheral = CCLK/6 - }, - }); - // byte offset: 428 Peripheral Clock Selection register 1. - pub const PCLKSEL1 = mmio(Address + 0x000001ac, 32, packed struct { - PCLK_QEI: enum(u2) { // bit offset: 0 desc: Peripheral clock selection for the Quadrature Encoder Interface. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_GPIOINT: enum(u2) { // bit offset: 2 desc: Peripheral clock selection for GPIO interrupts. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_PCB: enum(u2) { // bit offset: 4 desc: Peripheral clock selection for the Pin Connect block. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C1: enum(u2) { // bit offset: 6 desc: Peripheral clock selection for I2C1. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 8 desc: Reserved. - reserved2: u1 = 0, - reserved1: u1 = 0, - PCLK_SSP0: enum(u2) { // bit offset: 10 desc: Peripheral clock selection for SSP0. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER2: enum(u2) { // bit offset: 12 desc: Peripheral clock selection for TIMER2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_TIMER3: enum(u2) { // bit offset: 14 desc: Peripheral clock selection for TIMER3. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART2: enum(u2) { // bit offset: 16 desc: Peripheral clock selection for UART2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_UART3: enum(u2) { // bit offset: 18 desc: Peripheral clock selection for UART3. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2C2: enum(u2) { // bit offset: 20 desc: Peripheral clock selection for I2C2. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_I2S: enum(u2) { // bit offset: 22 desc: Peripheral clock selection for I2S. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - // RESERVED: u2, // bit offset: 24 desc: Reserved. - reserved4: u1 = 0, - reserved3: u1 = 0, - PCLK_RIT: enum(u2) { // bit offset: 26 desc: Peripheral clock selection for Repetitive Interrupt Timer. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_SYSCON: enum(u2) { // bit offset: 28 desc: Peripheral clock selection for the System Control block. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - PCLK_MC: enum(u2) { // bit offset: 30 desc: Peripheral clock selection for the Motor Control PWM. - @"CCLK_DIV_4" = 0, // desc: CCLK div 4. PCLK_peripheral = CCLK/4 - @"CCLK" = 1, // desc: CCLK. PCLK_peripheral = CCLK - @"CCLK_DIV_2" = 2, // desc: CCLK div 2. PCLK_peripheral = CCLK/2 - @"CCLK_DIV_8" = 3, // desc: CCLK div 8. PCLK_peripheral = CCLK/8 - }, - }); - // byte offset: 448 USB Interrupt Status - pub const USBINTST = mmio(Address + 0x000001c0, 32, packed struct { - USB_INT_REQ_LP: u1, // bit offset: 0 desc: Low priority interrupt line status. This bit is read-only. - USB_INT_REQ_HP: u1, // bit offset: 1 desc: High priority interrupt line status. This bit is read-only. - USB_INT_REQ_DMA: u1, // bit offset: 2 desc: DMA interrupt line status. This bit is read-only. - USB_HOST_INT: u1, // bit offset: 3 desc: USB host interrupt line status. This bit is read-only. - USB_ATX_INT: u1, // bit offset: 4 desc: External ATX interrupt line status. This bit is read-only. - USB_OTG_INT: u1, // bit offset: 5 desc: OTG interrupt line status. This bit is read-only. - USB_I2C_INT: u1, // bit offset: 6 desc: I2C module interrupt line status. This bit is read-only. - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - USB_NEED_CLK: u1, // bit offset: 8 desc: USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only. - // RESERVED: u22, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - EN_USB_INTS: u1, // bit offset: 31 desc: Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. - }); - // byte offset: 452 Selects between alternative requests on DMA channels 0 through 7 and 10 through 15 - pub const DMACREQSEL = mmio(Address + 0x000001c4, 32, packed struct { - DMASEL08: u1, // bit offset: 0 desc: Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected. - DMASEL09: u1, // bit offset: 1 desc: Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected. - DMASEL10: u1, // bit offset: 2 desc: Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected. - DMASEL11: u1, // bit offset: 3 desc: Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected. - DMASEL12: u1, // bit offset: 4 desc: Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected. - DMASEL13: u1, // bit offset: 5 desc: Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected. - DMASEL14: u1, // bit offset: 6 desc: Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected. - DMASEL15: u1, // bit offset: 7 desc: Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 456 Clock Output Configuration Register - pub const CLKOUTCFG = mmio(Address + 0x000001c8, 32, packed struct { - CLKOUTSEL: enum(u4) { // bit offset: 0 desc: Selects the clock source for the CLKOUT function. Other values are reserved. Do not use. - @"SELECTS_THE_CPU_CLOC" = 0, // desc: Selects the CPU clock as the CLKOUT source. - @"SELECTS_THE_MAIN_OSC" = 1, // desc: Selects the main oscillator as the CLKOUT source. - @"SELECTS_THE_INTERNAL" = 2, // desc: Selects the Internal RC oscillator as the CLKOUT source. - @"SELECTS_THE_USB_CLOC" = 3, // desc: Selects the USB clock as the CLKOUT source. - @"SELECTS_THE_RTC_OSCI" = 4, // desc: Selects the RTC oscillator as the CLKOUT source. - _, // non-exhaustive - }, - CLKOUTDIV: u4, // bit offset: 4 desc: Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16. - CLKOUT_EN: u1, // bit offset: 8 desc: CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. - CLKOUT_ACT: u1, // bit offset: 9 desc: CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. - // RESERVED: u22, // bit offset: 10 desc: Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const EMAC = extern struct { - pub const Address: u32 = 0x50000000; - // byte offset: 0 MAC configuration register 1. - pub const MAC1 = mmio(Address + 0x00000000, 32, packed struct { - RXENABLE: u1, // bit offset: 0 desc: RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. - PARF: u1, // bit offset: 1 desc: PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. - RXFLOWCTRL: u1, // bit offset: 2 desc: RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. - TXFLOWCTRL: u1, // bit offset: 3 desc: TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. - LOOPBACK: u1, // bit offset: 4 desc: Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. - // RESERVED: u3, // bit offset: 5 desc: Unused - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESETTX: u1, // bit offset: 8 desc: Setting this bit will put the Transmit Function logic in reset. - RESETMCSTX: u1, // bit offset: 9 desc: Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. - RESETRX: u1, // bit offset: 10 desc: Setting this bit will put the Ethernet receive logic in reset. - RESETMCSRX: u1, // bit offset: 11 desc: Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. - // RESERVED: u2, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - reserved5: u1 = 0, - reserved4: u1 = 0, - SIMRESET: u1, // bit offset: 14 desc: SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. - SOFTRESET: u1, // bit offset: 15 desc: SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 MAC configuration register 2. - pub const MAC2 = mmio(Address + 0x00000004, 32, packed struct { - FULLDUPLEX: u1, // bit offset: 0 desc: When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. - FLC: u1, // bit offset: 1 desc: FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. - HFEN: u1, // bit offset: 2 desc: HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. - DELAYEDCRC: u1, // bit offset: 3 desc: DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. - CRCEN: u1, // bit offset: 4 desc: CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. - PADCRCEN: u1, // bit offset: 5 desc: PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. - VLANPADEN: u1, // bit offset: 6 desc: VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - AUTODETPADEN: u1, // bit offset: 7 desc: AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. - PPENF: u1, // bit offset: 8 desc: PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. - LPENF: u1, // bit offset: 9 desc: LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. - // RESERVED: u2, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - reserved1: u1 = 0, - NOBACKOFF: u1, // bit offset: 12 desc: When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. - BP_NOBACKOFF: u1, // bit offset: 13 desc: BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. - EXCESSDEFER: u1, // bit offset: 14 desc: When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. - // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 Back-to-Back Inter-Packet-Gap register. - pub const IPGT = mmio(Address + 0x00000008, 32, packed struct { - BTOBINTEGAP: u7, // bit offset: 0 desc: BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). - // RESERVED: u25, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 Non Back-to-Back Inter-Packet-Gap register. - pub const IPGR = mmio(Address + 0x0000000c, 32, packed struct { - NBTOBINTEGAP2: u7, // bit offset: 0 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - NBTOBINTEGAP1: u7, // bit offset: 8 desc: NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) - // RESERVED: u17, // bit offset: 15 desc: Reserved. Read value is undefined, only zero should be written. - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 Collision window / Retry register. - pub const CLRT = mmio(Address + 0x00000010, 32, packed struct { - RETRANSMAX: u4, // bit offset: 0 desc: RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. - // RESERVED: u4, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - COLLWIN: u6, // bit offset: 8 desc: COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. - // RESERVED: u18, // bit offset: 14 desc: Reserved. Read value is undefined, only zero should be written. - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 Maximum Frame register. - pub const MAXF = mmio(Address + 0x00000014, 32, packed struct { - MAXFLEN: u16, // bit offset: 0 desc: MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 PHY Support register. - pub const SUPP = mmio(Address + 0x00000018, 32, packed struct { - // RESERVED: u8, // bit offset: 0 desc: Unused - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SPEED: u1, // bit offset: 8 desc: This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 Test register. - pub const TEST = mmio(Address + 0x0000001c, 32, packed struct { - SCPQ: u1, // bit offset: 0 desc: SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. - TESTPAUSE: u1, // bit offset: 1 desc: This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. - TESTBP: u1, // bit offset: 2 desc: TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. - // RESERVED: u29, // bit offset: 3 desc: Unused - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 MII Mgmt Configuration register. - pub const MCFG = mmio(Address + 0x00000020, 32, packed struct { - SCANINC: u1, // bit offset: 0 desc: SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. - SUPPPREAMBLE: u1, // bit offset: 1 desc: SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. - CLOCKSEL: u4, // bit offset: 2 desc: CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field. - // RESERVED: u9, // bit offset: 6 desc: Unused - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RESETMIIMGMT: u1, // bit offset: 15 desc: RESET MII MGMT. This bit resets the MII Management hardware. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 MII Mgmt Command register. - pub const MCMD = mmio(Address + 0x00000024, 32, packed struct { - READ: u1, // bit offset: 0 desc: This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). - SCAN: u1, // bit offset: 1 desc: This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. - // RESERVED: u30, // bit offset: 2 desc: Unused - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 MII Mgmt Address register. - pub const MADR = mmio(Address + 0x00000028, 32, packed struct { - REGADDR: u5, // bit offset: 0 desc: REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. - // RESERVED: u3, // bit offset: 5 desc: Unused - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PHYADDR: u5, // bit offset: 8 desc: PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). - // RESERVED: u19, // bit offset: 13 desc: Unused - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 MII Mgmt Write Data register. - pub const MWTD = mmio(Address + 0x0000002c, 32, packed struct { - WRITEDATA: u16, // bit offset: 0 desc: WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 MII Mgmt Read Data register. - pub const MRDD = mmio(Address + 0x00000030, 32, packed struct { - READDATA: u16, // bit offset: 0 desc: READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 MII Mgmt Indicators register. - pub const MIND = mmio(Address + 0x00000034, 32, packed struct { - BUSY: u1, // bit offset: 0 desc: When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. - SCANNING: u1, // bit offset: 1 desc: When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. - NOTVALID: u1, // bit offset: 2 desc: When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. - MIILINKFAIL: u1, // bit offset: 3 desc: When 1 is returned - indicates that an MII Mgmt link fail has occurred. - // RESERVED: u28, // bit offset: 4 desc: Unused - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 64 Station Address 0 register. - pub const SA0 = mmio(Address + 0x00000040, 32, packed struct { - SADDR2: u8, // bit offset: 0 desc: STATION ADDRESS, 2nd octet. This field holds the second octet of the station address. - SADDR1: u8, // bit offset: 8 desc: STATION ADDRESS, 1st octet. This field holds the first octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 68 Station Address 1 register. - pub const SA1 = mmio(Address + 0x00000044, 32, packed struct { - SADDR4: u8, // bit offset: 0 desc: STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address. - SADDR3: u8, // bit offset: 8 desc: STATION ADDRESS, 3rd octet. This field holds the third octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 72 Station Address 2 register. - pub const SA2 = mmio(Address + 0x00000048, 32, packed struct { - SADDR6: u8, // bit offset: 0 desc: STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address. - SADDR5: u8, // bit offset: 8 desc: STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 Command register. - pub const COMMAND = mmio(Address + 0x00000100, 32, packed struct { - RXENABLE: u1, // bit offset: 0 desc: Enable receive. - TXENABLE: u1, // bit offset: 1 desc: Enable transmit. - // RESERVED: u1, // bit offset: 2 desc: Unused - reserved1: u1 = 0, - REGRESET: u1, // bit offset: 3 desc: When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. - TXRESET: u1, // bit offset: 4 desc: When a 1 is written, the transmit datapath is reset. - RXRESET: u1, // bit offset: 5 desc: When a 1 is written, the receive datapath is reset. - PASSRUNTFRAME: u1, // bit offset: 6 desc: When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. - PASSRXFILTER: u1, // bit offset: 7 desc: When set to 1 , disables receive filtering i.e. all frames received are written to memory. - TXFLOWCONTROL: u1, // bit offset: 8 desc: Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. - RMII: u1, // bit offset: 9 desc: When set to 1 , RMII mode is selected; if 0, MII mode is selected. - FULLDUPLEX: u1, // bit offset: 10 desc: When set to 1 , indicates full duplex operation. - // RESERVED: u21, // bit offset: 11 desc: Unused - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 260 Status register. - pub const STATUS = mmio(Address + 0x00000104, 32, packed struct { - RXSTATUS: u1, // bit offset: 0 desc: If 1, the receive channel is active. If 0, the receive channel is inactive. - TXSTATUS: u1, // bit offset: 1 desc: If 1, the transmit channel is active. If 0, the transmit channel is inactive. - // RESERVED: u30, // bit offset: 2 desc: Unused - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 Receive descriptor base address register. - pub const RXDESCRIPTOR = mmio(Address + 0x00000108, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - RXDESCRIPTOR: u30, // bit offset: 2 desc: MSBs of receive descriptor base address. - }); - // byte offset: 268 Receive status base address register. - pub const RXSTATUS = mmio(Address + 0x0000010c, 32, packed struct { - // RESERVED: u3, // bit offset: 0 desc: Fixed to 000 - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - RXSTATUS: u29, // bit offset: 3 desc: MSBs of receive status base address. - }); - // byte offset: 272 Receive number of descriptors register. - pub const RXDESCRIPTORNUMBER = mmio(Address + 0x00000110, 32, packed struct { - RXDESCRIPTORN: u16, // bit offset: 0 desc: RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 276 Receive produce index register. - pub const RXPRODUCEINDEX = mmio(Address + 0x00000114, 32, packed struct { - RXPRODUCEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be filled next by the receive datapath. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 280 Receive consume index register. - pub const RXCONSUMEINDEX = mmio(Address + 0x00000118, 32, packed struct { - RXCONSUMEIX: u16, // bit offset: 0 desc: Index of the descriptor that is going to be processed next by the receive - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 284 Transmit descriptor base address register. - pub const TXDESCRIPTOR = mmio(Address + 0x0000011c, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - TXD: u30, // bit offset: 2 desc: TxDescriptor. MSBs of transmit descriptor base address. - }); - // byte offset: 288 Transmit status base address register. - pub const TXSTATUS = mmio(Address + 0x00000120, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Fixed to 00 - reserved2: u1 = 0, - reserved1: u1 = 0, - TXSTAT: u30, // bit offset: 2 desc: TxStatus. MSBs of transmit status base address. - }); - // byte offset: 292 Transmit number of descriptors register. - pub const TXDESCRIPTORNUMBER = mmio(Address + 0x00000124, 32, packed struct { - TXDN: u16, // bit offset: 0 desc: TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 296 Transmit produce index register. - pub const TXPRODUCEINDEX = mmio(Address + 0x00000128, 32, packed struct { - TXPI: u16, // bit offset: 0 desc: TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 300 Transmit consume index register. - pub const TXCONSUMEINDEX = mmio(Address + 0x0000012c, 32, packed struct { - TXCI: u16, // bit offset: 0 desc: TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 344 Transmit status vector 0 register. - pub const TSV0 = mmio(Address + 0x00000158, 32, packed struct { - CRCERR: u1, // bit offset: 0 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCE: u1, // bit offset: 1 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: u1, // bit offset: 2 desc: Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - DONE: u1, // bit offset: 3 desc: Transmission of packet was completed. - MULTICAST: u1, // bit offset: 4 desc: Packet's destination was a multicast address. - BROADCAST: u1, // bit offset: 5 desc: Packet's destination was a broadcast address. - PACKETDEFER: u1, // bit offset: 6 desc: Packet was deferred for at least one attempt, but less than an excessive defer. - EXDF: u1, // bit offset: 7 desc: Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. - EXCOL: u1, // bit offset: 8 desc: Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. - LCOL: u1, // bit offset: 9 desc: Late Collision. Collision occurred beyond collision window, 512 bit times. - GIANT: u1, // bit offset: 10 desc: Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. - UNDERRUN: u1, // bit offset: 11 desc: Host side caused buffer underrun. - TOTALBYTES: u16, // bit offset: 12 desc: The total number of bytes transferred including collided attempts. - CONTROLFRAME: u1, // bit offset: 28 desc: The frame was a control frame. - PAUSE: u1, // bit offset: 29 desc: The frame was a control frame with a valid PAUSE opcode. - BACKPRESSURE: u1, // bit offset: 30 desc: Carrier-sense method backpressure was previously applied. - VLAN: u1, // bit offset: 31 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. - }); - // byte offset: 348 Transmit status vector 1 register. - pub const TSV1 = mmio(Address + 0x0000015c, 32, packed struct { - TBC: u16, // bit offset: 0 desc: Transmit byte count. The total number of bytes in the frame, not counting the collided bytes. - TCC: u4, // bit offset: 16 desc: Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented. - // RESERVED: u12, // bit offset: 20 desc: Unused - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 352 Receive status vector register. - pub const RSV = mmio(Address + 0x00000160, 32, packed struct { - RBC: u16, // bit offset: 0 desc: Received byte count. Indicates length of received frame. - PPI: u1, // bit offset: 16 desc: Packet previously ignored. Indicates that a packet was dropped. - RXDVSEEN: u1, // bit offset: 17 desc: RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. - CESEEN: u1, // bit offset: 18 desc: Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. - RCV: u1, // bit offset: 19 desc: Receive code violation. Indicates that received PHY data does not represent a valid receive code. - CRCERR: u1, // bit offset: 20 desc: CRC error. The attached CRC in the packet did not match the internally generated CRC. - LCERR: u1, // bit offset: 21 desc: Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. - LOR: u1, // bit offset: 22 desc: Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. - ROK: u1, // bit offset: 23 desc: Receive OK. The packet had valid CRC and no symbol errors. - MULTICAST: u1, // bit offset: 24 desc: The packet destination was a multicast address. - BROADCAST: u1, // bit offset: 25 desc: The packet destination was a broadcast address. - DRIBBLENIBBLE: u1, // bit offset: 26 desc: Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. - CONTROLFRAME: u1, // bit offset: 27 desc: The frame was a control frame. - PAUSE: u1, // bit offset: 28 desc: The frame was a control frame with a valid PAUSE opcode. - UO: u1, // bit offset: 29 desc: Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. - VLAN: u1, // bit offset: 30 desc: Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. - // RESERVED: u1, // bit offset: 31 desc: Unused - padding1: u1 = 0, - }); - // byte offset: 368 Flow control counter register. - pub const FLOWCONTROLCOUNTER = mmio(Address + 0x00000170, 32, packed struct { - MC: u16, // bit offset: 0 desc: MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame. - PT: u16, // bit offset: 16 desc: PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. - }); - // byte offset: 372 Flow control status register. - pub const FLOWCONTROLSTATUS = mmio(Address + 0x00000174, 32, packed struct { - MCC: u16, // bit offset: 0 desc: MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. - // RESERVED: u16, // bit offset: 16 desc: Unused - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 512 Receive filter control register. - pub const RXFILTERCTRL = mmio(Address + 0x00000200, 32, packed struct { - AUE: u1, // bit offset: 0 desc: AcceptUnicastEn. When set to 1, all unicast frames are accepted. - ABE: u1, // bit offset: 1 desc: AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. - AME: u1, // bit offset: 2 desc: AcceptMulticastEn. When set to 1, all multicast frames are accepted. - AUHE: u1, // bit offset: 3 desc: AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. - AMHE: u1, // bit offset: 4 desc: AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. - APE: u1, // bit offset: 5 desc: AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. - // RESERVED: u6, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - MPEW: u1, // bit offset: 12 desc: MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. - RFEW: u1, // bit offset: 13 desc: RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 516 Receive filter WoL status register. - pub const RXFILTERWOLSTATUS = mmio(Address + 0x00000204, 32, packed struct { - AUW: u1, // bit offset: 0 desc: AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. - ABW: u1, // bit offset: 1 desc: AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. - AMW: u1, // bit offset: 2 desc: AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. - AUHW: u1, // bit offset: 3 desc: AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. - AMHW: u1, // bit offset: 4 desc: AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. - APW: u1, // bit offset: 5 desc: AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. - // RESERVED: u1, // bit offset: 6 desc: Unused - reserved1: u1 = 0, - RFW: u1, // bit offset: 7 desc: RxFilterWoL. When the value is 1, the receive filter caused WoL. - MPW: u1, // bit offset: 8 desc: MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 520 Receive filter WoL clear register. - pub const RXFILTERWOLCLEAR = mmio(Address + 0x00000208, 32, packed struct { - AUWCLR: u1, // bit offset: 0 desc: AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - ABWCLR: u1, // bit offset: 1 desc: AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMWCLR: u1, // bit offset: 2 desc: AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AUHWCLR: u1, // bit offset: 3 desc: AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - AMHWCLR: u1, // bit offset: 4 desc: AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - APWCLR: u1, // bit offset: 5 desc: AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - // RESERVED: u1, // bit offset: 6 desc: Unused - reserved1: u1 = 0, - RFWCLR: u1, // bit offset: 7 desc: RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - MPWCLR: u1, // bit offset: 8 desc: MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. - // RESERVED: u23, // bit offset: 9 desc: Unused - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 528 Hash filter table LSBs register. - pub const HASHFILTERL = mmio(Address + 0x00000210, 32, packed struct { - HFL: u32, // bit offset: 0 desc: HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. - }); - // byte offset: 532 Hash filter table MSBs register. - pub const HASHFILTERH = mmio(Address + 0x00000214, 32, packed struct { - HFH: u32, // bit offset: 0 desc: Bits 63:32 of the imperfect filter hash table for receive filtering. - }); - // byte offset: 4064 Interrupt status register. - pub const INTSTATUS = mmio(Address + 0x00000fe0, 32, packed struct { - RXOVERRUNINT: u1, // bit offset: 0 desc: Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. - RXERRORINT: u1, // bit offset: 1 desc: Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. - RXFINISHEDINT: u1, // bit offset: 2 desc: Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINT: u1, // bit offset: 3 desc: Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINT: u1, // bit offset: 4 desc: Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. - TXERRORINT: u1, // bit offset: 5 desc: Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. - TXFINISHEDINT: u1, // bit offset: 6 desc: Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINT: u1, // bit offset: 7 desc: Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINT: u1, // bit offset: 12 desc: Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINT: u1, // bit offset: 13 desc: Interrupt triggered by a Wake-up event detected by the receive filter. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4068 Interrupt enable register. - pub const INTENABLE = mmio(Address + 0x00000fe4, 32, packed struct { - RXOVERRUNINTEN: u1, // bit offset: 0 desc: Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. - RXERRORINTEN: u1, // bit offset: 1 desc: Enable for interrupt trigger on receive errors. - RXFINISHEDINTEN: u1, // bit offset: 2 desc: Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXDONEINTEN: u1, // bit offset: 3 desc: Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. - TXUNDERRUNINTEN: u1, // bit offset: 4 desc: Enable for interrupt trigger on transmit buffer or descriptor underrun situations. - TXERRORINTEN: u1, // bit offset: 5 desc: Enable for interrupt trigger on transmit errors. - TXFINISHEDINTEN: u1, // bit offset: 6 desc: Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXDONEINTEN: u1, // bit offset: 7 desc: Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTEN: u1, // bit offset: 12 desc: Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. - WAKEUPINTEN: u1, // bit offset: 13 desc: Enable for interrupt triggered by a Wake-up event detected by the receive filter. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4072 Interrupt clear register. - pub const INTCLEAR = mmio(Address + 0x00000fe8, 32, packed struct { - RXOVERRUNINTCLR: u1, // bit offset: 0 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXERRORINTCLR: u1, // bit offset: 1 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTCLR: u1, // bit offset: 2 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - RXDONEINTCLR: u1, // bit offset: 3 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTCLR: u1, // bit offset: 4 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXERRORINTCLR: u1, // bit offset: 5 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTCLR: u1, // bit offset: 6 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - TXDONEINTCLR: u1, // bit offset: 7 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTCLR: u1, // bit offset: 12 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTCLR: u1, // bit offset: 13 desc: Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4076 Interrupt set register. - pub const INTSET = mmio(Address + 0x00000fec, 32, packed struct { - RXOVERRUNINTSET: u1, // bit offset: 0 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXERRORINTSET: u1, // bit offset: 1 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXFINISHEDINTSET: u1, // bit offset: 2 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - RXDONEINTSET: u1, // bit offset: 3 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXUNDERRUNINTSET: u1, // bit offset: 4 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXERRORINTSET: u1, // bit offset: 5 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXFINISHEDINTSET: u1, // bit offset: 6 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - TXDONEINTSET: u1, // bit offset: 7 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u4, // bit offset: 8 desc: Unused - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - SOFTINTSET: u1, // bit offset: 12 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - WAKEUPINTSET: u1, // bit offset: 13 desc: Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. - // RESERVED: u18, // bit offset: 14 desc: Unused - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 Power-down register. - pub const POWERDOWN = mmio(Address + 0x00000ff4, 32, packed struct { - // RESERVED: u31, // bit offset: 0 desc: Unused - reserved31: u1 = 0, - reserved30: u1 = 0, - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - PD: u1, // bit offset: 31 desc: PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. - }); -}; -pub const GPDMA = extern struct { - pub const Address: u32 = 0x50004000; - // byte offset: 0 DMA Interrupt Status Register - pub const INTSTAT = mmio(Address + 0x00000000, 32, packed struct { - INTSTAT0: u1, // bit offset: 0 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT1: u1, // bit offset: 1 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT2: u1, // bit offset: 2 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT3: u1, // bit offset: 3 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT4: u1, // bit offset: 4 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT5: u1, // bit offset: 5 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT6: u1, // bit offset: 6 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - INTSTAT7: u1, // bit offset: 7 desc: Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4 DMA Interrupt Terminal Count Request Status Register - pub const INTTCSTAT = mmio(Address + 0x00000004, 32, packed struct { - INTTCSTAT0: u1, // bit offset: 0 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT1: u1, // bit offset: 1 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT2: u1, // bit offset: 2 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT3: u1, // bit offset: 3 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT4: u1, // bit offset: 4 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT5: u1, // bit offset: 5 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT6: u1, // bit offset: 6 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - INTTCSTAT7: u1, // bit offset: 7 desc: Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 8 DMA Interrupt Terminal Count Request Clear Register - pub const INTTCCLEAR = mmio(Address + 0x00000008, 32, packed struct { - INTTCCLEAR0: u1, // bit offset: 0 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR1: u1, // bit offset: 1 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR2: u1, // bit offset: 2 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR3: u1, // bit offset: 3 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR4: u1, // bit offset: 4 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR5: u1, // bit offset: 5 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR6: u1, // bit offset: 6 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - INTTCCLEAR7: u1, // bit offset: 7 desc: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 12 DMA Interrupt Error Status Register - pub const INTERRSTAT = mmio(Address + 0x0000000c, 32, packed struct { - INTERRSTAT0: u1, // bit offset: 0 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT1: u1, // bit offset: 1 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT2: u1, // bit offset: 2 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT3: u1, // bit offset: 3 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT4: u1, // bit offset: 4 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT5: u1, // bit offset: 5 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT6: u1, // bit offset: 6 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - INTERRSTAT7: u1, // bit offset: 7 desc: Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 16 DMA Interrupt Error Clear Register - pub const INTERRCLR = mmio(Address + 0x00000010, 32, packed struct { - INTERRCLR0: u1, // bit offset: 0 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR1: u1, // bit offset: 1 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR2: u1, // bit offset: 2 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR3: u1, // bit offset: 3 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR4: u1, // bit offset: 4 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR5: u1, // bit offset: 5 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR6: u1, // bit offset: 6 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - INTERRCLR7: u1, // bit offset: 7 desc: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 20 DMA Raw Interrupt Terminal Count Status Register - pub const RAWINTTCSTAT = mmio(Address + 0x00000014, 32, packed struct { - RAWINTTCSTAT0: u1, // bit offset: 0 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT1: u1, // bit offset: 1 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT2: u1, // bit offset: 2 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT3: u1, // bit offset: 3 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT4: u1, // bit offset: 4 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT5: u1, // bit offset: 5 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT6: u1, // bit offset: 6 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - RAWINTTCSTAT7: u1, // bit offset: 7 desc: Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 24 DMA Raw Error Interrupt Status Register - pub const RAWINTERRSTAT = mmio(Address + 0x00000018, 32, packed struct { - RAWINTERRSTAT0: u1, // bit offset: 0 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT1: u1, // bit offset: 1 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT2: u1, // bit offset: 2 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT3: u1, // bit offset: 3 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT4: u1, // bit offset: 4 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT5: u1, // bit offset: 5 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT6: u1, // bit offset: 6 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - RAWINTERRSTAT7: u1, // bit offset: 7 desc: Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 28 DMA Enabled Channel Register - pub const ENBLDCHNS = mmio(Address + 0x0000001c, 32, packed struct { - ENABLEDCHANNELS0: u1, // bit offset: 0 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS1: u1, // bit offset: 1 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS2: u1, // bit offset: 2 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS3: u1, // bit offset: 3 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS4: u1, // bit offset: 4 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS5: u1, // bit offset: 5 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS6: u1, // bit offset: 6 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS7: u1, // bit offset: 7 desc: Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 32 DMA Software Burst Request Register - pub const SOFTBREQ = mmio(Address + 0x00000020, 32, packed struct { - SOFTBREQ0: u1, // bit offset: 0 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ1: u1, // bit offset: 1 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ2: u1, // bit offset: 2 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ3: u1, // bit offset: 3 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ4: u1, // bit offset: 4 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ5: u1, // bit offset: 5 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ6: u1, // bit offset: 6 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ7: u1, // bit offset: 7 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ8: u1, // bit offset: 8 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ9: u1, // bit offset: 9 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ10: u1, // bit offset: 10 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ11: u1, // bit offset: 11 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ12: u1, // bit offset: 12 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ13: u1, // bit offset: 13 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ14: u1, // bit offset: 14 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - SOFTBREQ15: u1, // bit offset: 15 desc: Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 36 DMA Software Single Request Register - pub const SOFTSREQ = mmio(Address + 0x00000024, 32, packed struct { - SOFTSREQ0: u1, // bit offset: 0 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ1: u1, // bit offset: 1 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ2: u1, // bit offset: 2 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ3: u1, // bit offset: 3 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ4: u1, // bit offset: 4 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ5: u1, // bit offset: 5 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ6: u1, // bit offset: 6 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ7: u1, // bit offset: 7 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ8: u1, // bit offset: 8 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ9: u1, // bit offset: 9 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ10: u1, // bit offset: 10 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ11: u1, // bit offset: 11 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ12: u1, // bit offset: 12 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ13: u1, // bit offset: 13 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ14: u1, // bit offset: 14 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - SOFTSREQ15: u1, // bit offset: 15 desc: Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read undefined. Write reserved bits as zero. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 40 DMA Software Last Burst Request Register - pub const SOFTLBREQ = mmio(Address + 0x00000028, 32, packed struct { - SOFTLBREQ0: u1, // bit offset: 0 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ1: u1, // bit offset: 1 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ2: u1, // bit offset: 2 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ3: u1, // bit offset: 3 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ4: u1, // bit offset: 4 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ5: u1, // bit offset: 5 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ6: u1, // bit offset: 6 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ7: u1, // bit offset: 7 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ8: u1, // bit offset: 8 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ9: u1, // bit offset: 9 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ10: u1, // bit offset: 10 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ11: u1, // bit offset: 11 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ12: u1, // bit offset: 12 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ13: u1, // bit offset: 13 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ14: u1, // bit offset: 14 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - SOFTLBREQ15: u1, // bit offset: 15 desc: Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 44 DMA Software Last Single Request Register - pub const SOFTLSREQ = mmio(Address + 0x0000002c, 32, packed struct { - SOFTLSREQ0: u1, // bit offset: 0 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ1: u1, // bit offset: 1 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ2: u1, // bit offset: 2 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ3: u1, // bit offset: 3 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ4: u1, // bit offset: 4 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ5: u1, // bit offset: 5 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ6: u1, // bit offset: 6 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ7: u1, // bit offset: 7 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ8: u1, // bit offset: 8 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ9: u1, // bit offset: 9 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ10: u1, // bit offset: 10 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ11: u1, // bit offset: 11 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ12: u1, // bit offset: 12 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ13: u1, // bit offset: 13 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ14: u1, // bit offset: 14 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - SOFTLSREQ15: u1, // bit offset: 15 desc: Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 48 DMA Configuration Register - pub const CONFIG = mmio(Address + 0x00000030, 32, packed struct { - E: u1, // bit offset: 0 desc: DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. - M: u1, // bit offset: 1 desc: AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 52 DMA Synchronization Register - pub const SYNC = mmio(Address + 0x00000034, 32, packed struct { - DMACSYNC0: u1, // bit offset: 0 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC1: u1, // bit offset: 1 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC2: u1, // bit offset: 2 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC3: u1, // bit offset: 3 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC4: u1, // bit offset: 4 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC5: u1, // bit offset: 5 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC6: u1, // bit offset: 6 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC7: u1, // bit offset: 7 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC8: u1, // bit offset: 8 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC9: u1, // bit offset: 9 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC10: u1, // bit offset: 10 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC11: u1, // bit offset: 11 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC12: u1, // bit offset: 12 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC13: u1, // bit offset: 13 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC14: u1, // bit offset: 14 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC15: u1, // bit offset: 15 desc: Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 DMA Channel 0 Source Address Register - pub const SRCADDR0 = mmio(Address + 0x00000100, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 260 DMA Channel 0 Destination Address Register - pub const DESTADDR0 = mmio(Address + 0x00000104, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 264 DMA Channel 0 Linked List Item Register - pub const LLI0 = mmio(Address + 0x00000108, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 268 DMA Channel 0 Control Register - pub const CONTROL0 = mmio(Address + 0x0000010c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 272 DMA Channel 0 Configuration Register[1] - pub const CONFIG0 = mmio(Address + 0x00000110, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 288 DMA Channel 0 Source Address Register - pub const SRCADDR1 = mmio(Address + 0x00000120, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 292 DMA Channel 0 Destination Address Register - pub const DESTADDR1 = mmio(Address + 0x00000124, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 296 DMA Channel 0 Linked List Item Register - pub const LLI1 = mmio(Address + 0x00000128, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 300 DMA Channel 0 Control Register - pub const CONTROL1 = mmio(Address + 0x0000012c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 304 DMA Channel 0 Configuration Register[1] - pub const CONFIG1 = mmio(Address + 0x00000130, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 320 DMA Channel 0 Source Address Register - pub const SRCADDR2 = mmio(Address + 0x00000140, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 324 DMA Channel 0 Destination Address Register - pub const DESTADDR2 = mmio(Address + 0x00000144, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 328 DMA Channel 0 Linked List Item Register - pub const LLI2 = mmio(Address + 0x00000148, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 332 DMA Channel 0 Control Register - pub const CONTROL2 = mmio(Address + 0x0000014c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 336 DMA Channel 0 Configuration Register[1] - pub const CONFIG2 = mmio(Address + 0x00000150, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 352 DMA Channel 0 Source Address Register - pub const SRCADDR3 = mmio(Address + 0x00000160, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 356 DMA Channel 0 Destination Address Register - pub const DESTADDR3 = mmio(Address + 0x00000164, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 360 DMA Channel 0 Linked List Item Register - pub const LLI3 = mmio(Address + 0x00000168, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 364 DMA Channel 0 Control Register - pub const CONTROL3 = mmio(Address + 0x0000016c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 368 DMA Channel 0 Configuration Register[1] - pub const CONFIG3 = mmio(Address + 0x00000170, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 384 DMA Channel 0 Source Address Register - pub const SRCADDR4 = mmio(Address + 0x00000180, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 388 DMA Channel 0 Destination Address Register - pub const DESTADDR4 = mmio(Address + 0x00000184, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 392 DMA Channel 0 Linked List Item Register - pub const LLI4 = mmio(Address + 0x00000188, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 396 DMA Channel 0 Control Register - pub const CONTROL4 = mmio(Address + 0x0000018c, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 400 DMA Channel 0 Configuration Register[1] - pub const CONFIG4 = mmio(Address + 0x00000190, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 416 DMA Channel 0 Source Address Register - pub const SRCADDR5 = mmio(Address + 0x000001a0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 420 DMA Channel 0 Destination Address Register - pub const DESTADDR5 = mmio(Address + 0x000001a4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 424 DMA Channel 0 Linked List Item Register - pub const LLI5 = mmio(Address + 0x000001a8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 428 DMA Channel 0 Control Register - pub const CONTROL5 = mmio(Address + 0x000001ac, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 432 DMA Channel 0 Configuration Register[1] - pub const CONFIG5 = mmio(Address + 0x000001b0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 448 DMA Channel 0 Source Address Register - pub const SRCADDR6 = mmio(Address + 0x000001c0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 452 DMA Channel 0 Destination Address Register - pub const DESTADDR6 = mmio(Address + 0x000001c4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 456 DMA Channel 0 Linked List Item Register - pub const LLI6 = mmio(Address + 0x000001c8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 460 DMA Channel 0 Control Register - pub const CONTROL6 = mmio(Address + 0x000001cc, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 464 DMA Channel 0 Configuration Register[1] - pub const CONFIG6 = mmio(Address + 0x000001d0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 480 DMA Channel 0 Source Address Register - pub const SRCADDR7 = mmio(Address + 0x000001e0, 32, packed struct { - SRCADDR: u32, // bit offset: 0 desc: DMA source address. Reading this register will return the current source address. - }); - // byte offset: 484 DMA Channel 0 Destination Address Register - pub const DESTADDR7 = mmio(Address + 0x000001e4, 32, packed struct { - DESTADDR: u32, // bit offset: 0 desc: DMA Destination address. Reading this register will return the current destination address. - }); - // byte offset: 488 DMA Channel 0 Linked List Item Register - pub const LLI7 = mmio(Address + 0x000001e8, 32, packed struct { - // RESERVED: u2, // bit offset: 0 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - LLI: u30, // bit offset: 2 desc: Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. - }); - // byte offset: 492 DMA Channel 0 Control Register - pub const CONTROL7 = mmio(Address + 0x000001ec, 32, packed struct { - TRANSFERSIZE: u12, // bit offset: 0 desc: Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. - SBSIZE: u3, // bit offset: 12 desc: Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, // bit offset: 15 desc: Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - SWIDTH: u3, // bit offset: 18 desc: Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - DWIDTH: u3, // bit offset: 21 desc: Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved - // RESERVED: u2, // bit offset: 24 desc: Reserved, and must be written as 0. - reserved2: u1 = 0, - reserved1: u1 = 0, - SI: u1, // bit offset: 26 desc: Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. - DI: u1, // bit offset: 27 desc: Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. - PROT1: u1, // bit offset: 28 desc: This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT2: u1, // bit offset: 29 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. - PROT3: u1, // bit offset: 30 desc: This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. - I: u1, // bit offset: 31 desc: Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. - }); - // byte offset: 496 DMA Channel 0 Configuration Register[1] - pub const CONFIG7 = mmio(Address + 0x000001f0, 32, packed struct { - E: u1, // bit offset: 0 desc: Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. - SRCPERIPHERAL: u5, // bit offset: 1 desc: Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, // bit offset: 6 desc: Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. - TRANSFERTYPE: u3, // bit offset: 11 desc: This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. - IE: u1, // bit offset: 14 desc: Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. - ITC: u1, // bit offset: 15 desc: Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. - L: u1, // bit offset: 16 desc: Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. - A: u1, // bit offset: 17 desc: Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. - H: u1, // bit offset: 18 desc: Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. - // RESERVED: u13, // bit offset: 19 desc: Reserved. Read value is undefined, only zero should be written. - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; -pub const USB = extern struct { - pub const Address: u32 = 0x50008000; - // byte offset: 220 USB Receive Packet Length - pub const RXPLEN = mmio(Address + 0x000000dc, 32, packed struct { - PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. - DV: enum(u1) { // bit offset: 10 desc: Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. - @"DATA_IS_INVALID_" = 0, // desc: Data is invalid. - @"DATA_IS_VALID_" = 1, // desc: Data is valid. - }, - PKT_RDY: u1, // bit offset: 11 desc: The PKT_LNGTH field is valid and the packet is ready for reading. - // RESERVED: u20, // bit offset: 12 desc: Reserved. The value read from a reserved bit is not defined. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 256 OTG Interrupt Status - pub const INTST = mmio(Address + 0x00000100, 32, packed struct { - TMR: u1, // bit offset: 0 desc: Timer time-out. - REMOVE_PU: u1, // bit offset: 1 desc: Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. - HNP_FAILURE: u1, // bit offset: 2 desc: HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. - HNP_SUCCESS: u1, // bit offset: 3 desc: HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 260 OTG Interrupt Enable - pub const INTEN = mmio(Address + 0x00000104, 32, packed struct { - TMR_EN: u1, // bit offset: 0 desc: 1 = enable the corresponding bit in the IntSt register. - REMOVE_PU_EN: u1, // bit offset: 1 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_FAILURE_EN: u1, // bit offset: 2 desc: 1 = enable the corresponding bit in the IntSt register. - HNP_SUCCES_EN: u1, // bit offset: 3 desc: 1 = enable the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 264 OTG Interrupt Set - pub const INTSET = mmio(Address + 0x00000108, 32, packed struct { - TMR_SET: u1, // bit offset: 0 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - REMOVE_PU_SET: u1, // bit offset: 1 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_FAILURE_SET: u1, // bit offset: 2 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_SUCCES_SET: u1, // bit offset: 3 desc: 0 = no effect. 1 = set the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 268 OTG Interrupt Clear - pub const INTCLR = mmio(Address + 0x0000010c, 32, packed struct { - TMR_CLR: u1, // bit offset: 0 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - REMOVE_PU_CLR: u1, // bit offset: 1 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_FAILURE_CLR: u1, // bit offset: 2 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_SUCCES_CLR: u1, // bit offset: 3 desc: 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - // RESERVED: u28, // bit offset: 4 desc: Reserved. Read value is undefined, only zero should be written. - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 272 OTG Status and Control and USB port select - pub const STCTRL = mmio(Address + 0x00000110, 32, packed struct { - PORT_FUNC: u2, // bit offset: 0 desc: Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. - TMR_SCALE: u2, // bit offset: 2 desc: Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved - TMR_MODE: u1, // bit offset: 4 desc: Timer mode selection. 0: monoshot 1: free running - TMR_EN: u1, // bit offset: 5 desc: Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. - TMR_RST: u1, // bit offset: 6 desc: Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. - // RESERVED: u1, // bit offset: 7 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - B_HNP_TRACK: u1, // bit offset: 8 desc: Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - A_HNP_TRACK: u1, // bit offset: 9 desc: Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - PU_REMOVED: u1, // bit offset: 10 desc: When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. - // RESERVED: u5, // bit offset: 11 desc: Reserved. Read value is undefined, only zero should be written. - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - TMR_CNT: u16, // bit offset: 16 desc: Current timer count value. - }); - // byte offset: 276 OTG Timer - pub const TMR = mmio(Address + 0x00000114, 32, packed struct { - TIMEOUT_CNT: u16, // bit offset: 0 desc: The TMR interrupt is set when TMR_CNT reaches this value. - // RESERVED: u16, // bit offset: 16 desc: Reserved. Read value is undefined, only zero should be written. - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 512 USB Device Interrupt Status - pub const DEVINTST = mmio(Address + 0x00000200, 32, packed struct { - FRAME: u1, // bit offset: 0 desc: The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. - EP_FAST: u1, // bit offset: 1 desc: Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. - EP_SLOW: u1, // bit offset: 2 desc: Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. - DEV_STAT: u1, // bit offset: 3 desc: Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. - CCEMPTY: u1, // bit offset: 4 desc: The command code register (USBCmdCode) is empty (New command can be written). - CDFULL: u1, // bit offset: 5 desc: Command data register (USBCmdData) is full (Data can be read now). - RxENDPKT: u1, // bit offset: 6 desc: The current packet in the endpoint buffer is transferred to the CPU. - TxENDPKT: u1, // bit offset: 7 desc: The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). - EP_RLZED: u1, // bit offset: 8 desc: Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. - ERR_INT: u1, // bit offset: 9 desc: Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 - // RESERVED: u22, // bit offset: 10 desc: Reserved. The value read from a reserved bit is not defined. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 516 USB Device Interrupt Enable - pub const DEVINTEN = mmio(Address + 0x00000204, 32, packed struct { - FRAMEEN: u1, // bit offset: 0 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_FASTEN: u1, // bit offset: 1 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_SLOWEN: u1, // bit offset: 2 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - DEV_STATEN: u1, // bit offset: 3 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CCEMPTYEN: u1, // bit offset: 4 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CDFULLEN: u1, // bit offset: 5 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - RxENDPKTEN: u1, // bit offset: 6 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - TxENDPKTEN: u1, // bit offset: 7 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_RLZEDEN: u1, // bit offset: 8 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - ERR_INTEN: u1, // bit offset: 9 desc: 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 520 USB Device Interrupt Clear - pub const DEVINTCLR = mmio(Address + 0x00000208, 32, packed struct { - FRAMECLR: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_FASTCLR: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_SLOWCLR: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - DEV_STATCLR: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CCEMPTYCLR: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - CDFULLCLR: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - RxENDPKTCLR: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - TxENDPKTCLR: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - EP_RLZEDCLR: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - ERR_INTCLR: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 524 USB Device Interrupt Set - pub const DEVINTSET = mmio(Address + 0x0000020c, 32, packed struct { - FRAMESET: u1, // bit offset: 0 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_FASTSET: u1, // bit offset: 1 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_SLOWSET: u1, // bit offset: 2 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - DEV_STATSET: u1, // bit offset: 3 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CCEMPTYSET: u1, // bit offset: 4 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - CDFULLSET: u1, // bit offset: 5 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - RxENDPKTSET: u1, // bit offset: 6 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - TxENDPKTSET: u1, // bit offset: 7 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - EP_RLZEDSET: u1, // bit offset: 8 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - ERR_INTSET: u1, // bit offset: 9 desc: 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. - // RESERVED: u22, // bit offset: 10 desc: Reserved - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 528 USB Command Code - pub const CMDCODE = mmio(Address + 0x00000210, 32, packed struct { - // RESERVED: u8, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - CMD_PHASE: enum(u8) { // bit offset: 8 desc: The command phase: - @"READ" = 2, // desc: Read - @"WRITE" = 1, // desc: Write - @"COMMAND" = 5, // desc: Command - _, // non-exhaustive - }, - CMD_CODE_WDATA: u8, // bit offset: 16 desc: This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). - // RESERVED: u8, // bit offset: 24 desc: Reserved. Read value is undefined, only zero should be written. - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 532 USB Command Data - pub const CMDDATA = mmio(Address + 0x00000214, 32, packed struct { - CMD_RDATA: u8, // bit offset: 0 desc: Command Read Data. - // RESERVED: u24, // bit offset: 8 desc: Reserved. The value read from a reserved bit is not defined. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 536 USB Receive Data - pub const RXDATA = mmio(Address + 0x00000218, 32, packed struct { - RX_DATA: u32, // bit offset: 0 desc: Data received. - }); - // byte offset: 540 USB Transmit Data - pub const TXDATA = mmio(Address + 0x0000021c, 32, packed struct { - TX_DATA: u32, // bit offset: 0 desc: Transmit Data. - }); - // byte offset: 548 USB Transmit Packet Length - pub const TXPLEN = mmio(Address + 0x00000224, 32, packed struct { - PKT_LNGTH: u10, // bit offset: 0 desc: The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 552 USB Control - pub const CTRL = mmio(Address + 0x00000228, 32, packed struct { - RD_EN: enum(u1) { // bit offset: 0 desc: Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - WR_EN: enum(u1) { // bit offset: 1 desc: Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - LOG_ENDPOINT: u4, // bit offset: 2 desc: Logical Endpoint number. - // RESERVED: u26, // bit offset: 6 desc: Reserved. Read value is undefined, only zero should be written. - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 556 USB Device Interrupt Priority - pub const DEVINTPRI = mmio(Address + 0x0000022c, 32, packed struct { - FRAME: enum(u1) { // bit offset: 0 desc: Frame interrupt routing - @"LP" = 0, // desc: FRAME interrupt is routed to USB_INT_REQ_LP. - @"HP" = 1, // desc: FRAME interrupt is routed to USB_INT_REQ_HP. - }, - EP_FAST: enum(u1) { // bit offset: 1 desc: Fast endpoint interrupt routing - @"LP" = 0, // desc: EP_FAST interrupt is routed to USB_INT_REQ_LP. - @"HP" = 1, // desc: EP_FAST interrupt is routed to USB_INT_REQ_HP. - }, - // RESERVED: u30, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 560 USB Endpoint Interrupt Status - pub const EPINTST = mmio(Address + 0x00000230, 32, packed struct { - EPST0: u1, // bit offset: 0 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST1: u1, // bit offset: 1 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST2: u1, // bit offset: 2 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST3: u1, // bit offset: 3 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST4: u1, // bit offset: 4 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST5: u1, // bit offset: 5 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST6: u1, // bit offset: 6 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST7: u1, // bit offset: 7 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST8: u1, // bit offset: 8 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST9: u1, // bit offset: 9 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST10: u1, // bit offset: 10 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST11: u1, // bit offset: 11 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST12: u1, // bit offset: 12 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST13: u1, // bit offset: 13 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST14: u1, // bit offset: 14 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST15: u1, // bit offset: 15 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST16: u1, // bit offset: 16 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST17: u1, // bit offset: 17 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST18: u1, // bit offset: 18 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST19: u1, // bit offset: 19 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST20: u1, // bit offset: 20 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST21: u1, // bit offset: 21 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST22: u1, // bit offset: 22 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST23: u1, // bit offset: 23 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST24: u1, // bit offset: 24 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST25: u1, // bit offset: 25 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST26: u1, // bit offset: 26 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST27: u1, // bit offset: 27 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST28: u1, // bit offset: 28 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST29: u1, // bit offset: 29 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST30: u1, // bit offset: 30 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - EPST31: u1, // bit offset: 31 desc: 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. - }); - // byte offset: 564 USB Endpoint Interrupt Enable - pub const EPINTEN = mmio(Address + 0x00000234, 32, packed struct { - EPEN0: u1, // bit offset: 0 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN1: u1, // bit offset: 1 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN2: u1, // bit offset: 2 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN3: u1, // bit offset: 3 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN4: u1, // bit offset: 4 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN5: u1, // bit offset: 5 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN6: u1, // bit offset: 6 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN7: u1, // bit offset: 7 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN8: u1, // bit offset: 8 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN9: u1, // bit offset: 9 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN10: u1, // bit offset: 10 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN11: u1, // bit offset: 11 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN12: u1, // bit offset: 12 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN13: u1, // bit offset: 13 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN14: u1, // bit offset: 14 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN15: u1, // bit offset: 15 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN16: u1, // bit offset: 16 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN17: u1, // bit offset: 17 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN18: u1, // bit offset: 18 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN19: u1, // bit offset: 19 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN20: u1, // bit offset: 20 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN21: u1, // bit offset: 21 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN22: u1, // bit offset: 22 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN23: u1, // bit offset: 23 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN24: u1, // bit offset: 24 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN25: u1, // bit offset: 25 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN26: u1, // bit offset: 26 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN27: u1, // bit offset: 27 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN28: u1, // bit offset: 28 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN29: u1, // bit offset: 29 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN30: u1, // bit offset: 30 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN31: u1, // bit offset: 31 desc: 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. - }); - // byte offset: 568 USB Endpoint Interrupt Clear - pub const EPINTCLR = mmio(Address + 0x00000238, 32, packed struct { - EPCLR0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. - }); - // byte offset: 572 USB Endpoint Interrupt Set - pub const EPINTSET = mmio(Address + 0x0000023c, 32, packed struct { - EPSET0: u1, // bit offset: 0 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET1: u1, // bit offset: 1 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET2: u1, // bit offset: 2 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET3: u1, // bit offset: 3 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET4: u1, // bit offset: 4 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET5: u1, // bit offset: 5 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET6: u1, // bit offset: 6 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET7: u1, // bit offset: 7 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET8: u1, // bit offset: 8 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET9: u1, // bit offset: 9 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET10: u1, // bit offset: 10 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET11: u1, // bit offset: 11 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET12: u1, // bit offset: 12 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET13: u1, // bit offset: 13 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET14: u1, // bit offset: 14 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET15: u1, // bit offset: 15 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET16: u1, // bit offset: 16 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET17: u1, // bit offset: 17 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET18: u1, // bit offset: 18 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET19: u1, // bit offset: 19 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET20: u1, // bit offset: 20 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET21: u1, // bit offset: 21 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET22: u1, // bit offset: 22 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET23: u1, // bit offset: 23 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET24: u1, // bit offset: 24 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET25: u1, // bit offset: 25 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET26: u1, // bit offset: 26 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET27: u1, // bit offset: 27 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET28: u1, // bit offset: 28 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET29: u1, // bit offset: 29 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET30: u1, // bit offset: 30 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET31: u1, // bit offset: 31 desc: 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - }); - // byte offset: 576 USB Endpoint Priority - pub const EPINTPRI = mmio(Address + 0x00000240, 32, packed struct { - EPPRI0: u1, // bit offset: 0 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI1: u1, // bit offset: 1 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI2: u1, // bit offset: 2 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI3: u1, // bit offset: 3 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI4: u1, // bit offset: 4 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI5: u1, // bit offset: 5 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI6: u1, // bit offset: 6 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI7: u1, // bit offset: 7 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI8: u1, // bit offset: 8 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI9: u1, // bit offset: 9 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI10: u1, // bit offset: 10 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI11: u1, // bit offset: 11 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI12: u1, // bit offset: 12 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI13: u1, // bit offset: 13 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI14: u1, // bit offset: 14 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI15: u1, // bit offset: 15 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI16: u1, // bit offset: 16 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI17: u1, // bit offset: 17 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI18: u1, // bit offset: 18 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI19: u1, // bit offset: 19 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI20: u1, // bit offset: 20 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI21: u1, // bit offset: 21 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI22: u1, // bit offset: 22 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI23: u1, // bit offset: 23 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI24: u1, // bit offset: 24 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI25: u1, // bit offset: 25 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI26: u1, // bit offset: 26 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI27: u1, // bit offset: 27 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI28: u1, // bit offset: 28 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI29: u1, // bit offset: 29 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI30: u1, // bit offset: 30 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI31: u1, // bit offset: 31 desc: 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - }); - // byte offset: 580 USB Realize Endpoint - pub const REEP = mmio(Address + 0x00000244, 32, packed struct { - EPR0: u1, // bit offset: 0 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR1: u1, // bit offset: 1 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR2: u1, // bit offset: 2 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR3: u1, // bit offset: 3 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR4: u1, // bit offset: 4 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR5: u1, // bit offset: 5 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR6: u1, // bit offset: 6 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR7: u1, // bit offset: 7 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR8: u1, // bit offset: 8 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR9: u1, // bit offset: 9 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR10: u1, // bit offset: 10 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR11: u1, // bit offset: 11 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR12: u1, // bit offset: 12 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR13: u1, // bit offset: 13 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR14: u1, // bit offset: 14 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR15: u1, // bit offset: 15 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR16: u1, // bit offset: 16 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR17: u1, // bit offset: 17 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR18: u1, // bit offset: 18 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR19: u1, // bit offset: 19 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR20: u1, // bit offset: 20 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR21: u1, // bit offset: 21 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR22: u1, // bit offset: 22 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR23: u1, // bit offset: 23 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR24: u1, // bit offset: 24 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR25: u1, // bit offset: 25 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR26: u1, // bit offset: 26 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR27: u1, // bit offset: 27 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR28: u1, // bit offset: 28 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR29: u1, // bit offset: 29 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR30: u1, // bit offset: 30 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR31: u1, // bit offset: 31 desc: 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - }); - // byte offset: 584 USB Endpoint Index - pub const EPIND = mmio(Address + 0x00000248, 32, packed struct { - PHY_EP: u5, // bit offset: 0 desc: Physical endpoint number (0-31) - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 588 USB MaxPacketSize - pub const MAXPSIZE = mmio(Address + 0x0000024c, 32, packed struct { - MPS: u10, // bit offset: 0 desc: The maximum packet size value. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 592 USB DMA Request Status - pub const DMARST = mmio(Address + 0x00000250, 32, packed struct { - EPRST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). - EPRST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). - EPRST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - EPRST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. - }); - // byte offset: 596 USB DMA Request Clear - pub const DMARCLR = mmio(Address + 0x00000254, 32, packed struct { - EPRCLR0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRCLR1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRCLR2: u1, // bit offset: 2 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR3: u1, // bit offset: 3 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR4: u1, // bit offset: 4 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR5: u1, // bit offset: 5 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR6: u1, // bit offset: 6 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR7: u1, // bit offset: 7 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR8: u1, // bit offset: 8 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR9: u1, // bit offset: 9 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR10: u1, // bit offset: 10 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR11: u1, // bit offset: 11 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR12: u1, // bit offset: 12 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR13: u1, // bit offset: 13 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR14: u1, // bit offset: 14 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR15: u1, // bit offset: 15 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR16: u1, // bit offset: 16 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR17: u1, // bit offset: 17 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR18: u1, // bit offset: 18 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR19: u1, // bit offset: 19 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR20: u1, // bit offset: 20 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR21: u1, // bit offset: 21 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR22: u1, // bit offset: 22 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR23: u1, // bit offset: 23 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR24: u1, // bit offset: 24 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR25: u1, // bit offset: 25 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR26: u1, // bit offset: 26 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR27: u1, // bit offset: 27 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR28: u1, // bit offset: 28 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR29: u1, // bit offset: 29 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR30: u1, // bit offset: 30 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - EPRCLR31: u1, // bit offset: 31 desc: Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. - }); - // byte offset: 600 USB DMA Request Set - pub const DMARSET = mmio(Address + 0x00000258, 32, packed struct { - EPRSET0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). - EPRSET1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). - EPRSET2: u1, // bit offset: 2 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET3: u1, // bit offset: 3 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET4: u1, // bit offset: 4 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET5: u1, // bit offset: 5 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET6: u1, // bit offset: 6 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET7: u1, // bit offset: 7 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET8: u1, // bit offset: 8 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET9: u1, // bit offset: 9 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET10: u1, // bit offset: 10 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET11: u1, // bit offset: 11 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET12: u1, // bit offset: 12 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET13: u1, // bit offset: 13 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET14: u1, // bit offset: 14 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET15: u1, // bit offset: 15 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET16: u1, // bit offset: 16 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET17: u1, // bit offset: 17 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET18: u1, // bit offset: 18 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET19: u1, // bit offset: 19 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET20: u1, // bit offset: 20 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET21: u1, // bit offset: 21 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET22: u1, // bit offset: 22 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET23: u1, // bit offset: 23 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET24: u1, // bit offset: 24 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET25: u1, // bit offset: 25 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET26: u1, // bit offset: 26 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET27: u1, // bit offset: 27 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET28: u1, // bit offset: 28 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET29: u1, // bit offset: 29 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET30: u1, // bit offset: 30 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - EPRSET31: u1, // bit offset: 31 desc: Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. - }); - // byte offset: 640 USB UDCA Head - pub const UDCAH = mmio(Address + 0x00000280, 32, packed struct { - // RESERVED: u7, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries. - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - UDCA_ADDR: u25, // bit offset: 7 desc: Start address of the UDCA. - }); - // byte offset: 644 USB Endpoint DMA Status - pub const EPDMAST = mmio(Address + 0x00000284, 32, packed struct { - EP_DMA_ST0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). - EP_DMA_ST1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). - EP_DMA_ST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. - }); - // byte offset: 648 USB Endpoint DMA Enable - pub const EPDMAEN = mmio(Address + 0x00000288, 32, packed struct { - EP_DMA_EN0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). - EP_DMA_EN1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). - EP_DMA_EN: u30, // bit offset: 2 desc: Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx. - }); - // byte offset: 652 USB Endpoint DMA Disable - pub const EPDMADIS = mmio(Address + 0x0000028c, 32, packed struct { - EP_DMA_DIS0: u1, // bit offset: 0 desc: Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). - EP_DMA_DIS1: u1, // bit offset: 1 desc: Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). - EP_DMA_DIS2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - EP_DMA_DIS31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. - }); - // byte offset: 656 USB DMA Interrupt Status - pub const DMAINTST = mmio(Address + 0x00000290, 32, packed struct { - EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt bit. - @"ALL_BITS_IN_THE_USBE" = 0, // desc: All bits in the USBEoTIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBEoTIntSt is set. - }, - NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt bit. - @"ALL_BITS_IN_THE_USBN" = 0, // desc: All bits in the USBNDDRIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBNDDRIntSt is set. - }, - ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt bit. - @"ALL_BITS_IN_THE_USBS" = 0, // desc: All bits in the USBSysErrIntSt register are 0. - @"AT_LEAST_ONE_BIT_IN_" = 1, // desc: At least one bit in the USBSysErrIntSt is set. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. The value read from a reserved bit is not defined. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 660 USB DMA Interrupt Enable - pub const DMAINTEN = mmio(Address + 0x00000294, 32, packed struct { - EOT: enum(u1) { // bit offset: 0 desc: End of Transfer Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - NDDR: enum(u1) { // bit offset: 1 desc: New DD Request Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - ERR: enum(u1) { // bit offset: 2 desc: System Error Interrupt enable bit. - @"DISABLED_" = 0, // desc: Disabled. - @"ENABLED_" = 1, // desc: Enabled. - }, - // RESERVED: u29, // bit offset: 3 desc: Reserved. Read value is undefined, only zero should be written. - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 672 USB End of Transfer Interrupt Status - pub const EOTINTST = mmio(Address + 0x000002a0, 32, packed struct { - EPTXINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - EPTXINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. - }); - // byte offset: 676 USB End of Transfer Interrupt Clear - pub const EOTINTCLR = mmio(Address + 0x000002a4, 32, packed struct { - EPTXINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - }); - // byte offset: 680 USB End of Transfer Interrupt Set - pub const EOTINTSET = mmio(Address + 0x000002a8, 32, packed struct { - EPTXINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - EPTXINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. - }); - // byte offset: 684 USB New DD Request Interrupt Status - pub const NDDRINTST = mmio(Address + 0x000002ac, 32, packed struct { - EPNDDINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - EPNDDINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. - }); - // byte offset: 688 USB New DD Request Interrupt Clear - pub const NDDRINTCLR = mmio(Address + 0x000002b0, 32, packed struct { - EPNDDINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - }); - // byte offset: 692 USB New DD Request Interrupt Set - pub const NDDRINTSET = mmio(Address + 0x000002b4, 32, packed struct { - EPNDDINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. - }); - // byte offset: 696 USB System Error Interrupt Status - pub const SYSERRINTST = mmio(Address + 0x000002b8, 32, packed struct { - EPERRINTST0: u1, // bit offset: 0 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST1: u1, // bit offset: 1 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST2: u1, // bit offset: 2 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST3: u1, // bit offset: 3 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST4: u1, // bit offset: 4 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST5: u1, // bit offset: 5 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST6: u1, // bit offset: 6 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST7: u1, // bit offset: 7 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST8: u1, // bit offset: 8 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST9: u1, // bit offset: 9 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST10: u1, // bit offset: 10 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST11: u1, // bit offset: 11 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST12: u1, // bit offset: 12 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST13: u1, // bit offset: 13 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST14: u1, // bit offset: 14 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST15: u1, // bit offset: 15 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST16: u1, // bit offset: 16 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST17: u1, // bit offset: 17 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST18: u1, // bit offset: 18 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST19: u1, // bit offset: 19 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST20: u1, // bit offset: 20 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST21: u1, // bit offset: 21 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST22: u1, // bit offset: 22 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST23: u1, // bit offset: 23 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST24: u1, // bit offset: 24 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST25: u1, // bit offset: 25 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST26: u1, // bit offset: 26 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST27: u1, // bit offset: 27 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST28: u1, // bit offset: 28 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST29: u1, // bit offset: 29 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST30: u1, // bit offset: 30 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - EPERRINTST31: u1, // bit offset: 31 desc: Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. - }); - // byte offset: 700 USB System Error Interrupt Clear - pub const SYSERRINTCLR = mmio(Address + 0x000002bc, 32, packed struct { - EPERRINTCLR0: u1, // bit offset: 0 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR1: u1, // bit offset: 1 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR2: u1, // bit offset: 2 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR3: u1, // bit offset: 3 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR4: u1, // bit offset: 4 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR5: u1, // bit offset: 5 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR6: u1, // bit offset: 6 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR7: u1, // bit offset: 7 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR8: u1, // bit offset: 8 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR9: u1, // bit offset: 9 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR10: u1, // bit offset: 10 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR11: u1, // bit offset: 11 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR12: u1, // bit offset: 12 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR13: u1, // bit offset: 13 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR14: u1, // bit offset: 14 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR15: u1, // bit offset: 15 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR16: u1, // bit offset: 16 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR17: u1, // bit offset: 17 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR18: u1, // bit offset: 18 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR19: u1, // bit offset: 19 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR20: u1, // bit offset: 20 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR21: u1, // bit offset: 21 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR22: u1, // bit offset: 22 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR23: u1, // bit offset: 23 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR24: u1, // bit offset: 24 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR25: u1, // bit offset: 25 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR26: u1, // bit offset: 26 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR27: u1, // bit offset: 27 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR28: u1, // bit offset: 28 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR29: u1, // bit offset: 29 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR30: u1, // bit offset: 30 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTCLR31: u1, // bit offset: 31 desc: Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. - }); - // byte offset: 704 USB System Error Interrupt Set - pub const SYSERRINTSET = mmio(Address + 0x000002c0, 32, packed struct { - EPERRINTSET0: u1, // bit offset: 0 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET1: u1, // bit offset: 1 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET2: u1, // bit offset: 2 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET3: u1, // bit offset: 3 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET4: u1, // bit offset: 4 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET5: u1, // bit offset: 5 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET6: u1, // bit offset: 6 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET7: u1, // bit offset: 7 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET8: u1, // bit offset: 8 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET9: u1, // bit offset: 9 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET10: u1, // bit offset: 10 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET11: u1, // bit offset: 11 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET12: u1, // bit offset: 12 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET13: u1, // bit offset: 13 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET14: u1, // bit offset: 14 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET15: u1, // bit offset: 15 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET16: u1, // bit offset: 16 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET17: u1, // bit offset: 17 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET18: u1, // bit offset: 18 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET19: u1, // bit offset: 19 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET20: u1, // bit offset: 20 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET21: u1, // bit offset: 21 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET22: u1, // bit offset: 22 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET23: u1, // bit offset: 23 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET24: u1, // bit offset: 24 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET25: u1, // bit offset: 25 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET26: u1, // bit offset: 26 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET27: u1, // bit offset: 27 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET28: u1, // bit offset: 28 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET29: u1, // bit offset: 29 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET30: u1, // bit offset: 30 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET31: u1, // bit offset: 31 desc: Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - }); - // byte offset: 768 I2C Receive - pub const I2C_RX = mmio(Address + 0x00000300, 32, packed struct { - RXDATA: u8, // bit offset: 0 desc: Receive data. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 768 I2C Transmit - pub const I2C_WO = mmio(Address + 0x00000300, 32, packed struct { - TXDATA: u8, // bit offset: 0 desc: Transmit data. - START: u1, // bit offset: 8 desc: When 1, issue a START condition before transmitting this byte. - STOP: u1, // bit offset: 9 desc: When 1, issue a STOP condition after transmitting this byte. - // RESERVED: u22, // bit offset: 10 desc: Reserved. Read value is undefined, only zero should be written. - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 772 I2C Status - pub const I2C_STS = mmio(Address + 0x00000304, 32, packed struct { - TDI: enum(u1) { // bit offset: 0 desc: Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. - @"NOT_COMPLETE" = 0, // desc: Transaction has not completed. - @"COMPLETE" = 1, // desc: Transaction completed. - }, - AFI: enum(u1) { // bit offset: 1 desc: Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. - @"NO_ARBITRATION_FAILU" = 0, // desc: No arbitration failure on last transmission. - @"ARBITRATION_FAILURE_" = 1, // desc: Arbitration failure occurred on last transmission. - }, - NAI: enum(u1) { // bit offset: 2 desc: No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. - @"ACKNOWLEDGE_RCVD" = 0, // desc: Last transmission received an acknowledge. - @"NO_ACKNOWLEDGE_RCVD" = 1, // desc: Last transmission did not receive an acknowledge. - }, - DRMI: enum(u1) { // bit offset: 3 desc: Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. - @"BUSY" = 0, // desc: Master transmitter does not need data. - @"NEED_DATA" = 1, // desc: Master transmitter needs data. - }, - DRSI: enum(u1) { // bit offset: 4 desc: Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. - @"BUSY" = 0, // desc: Slave transmitter does not need data. - @"NEED_DATA" = 1, // desc: Slave transmitter needs data. - }, - Active: u1, // bit offset: 5 desc: Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. - SCL: u1, // bit offset: 6 desc: The current value of the SCL signal. - SDA: u1, // bit offset: 7 desc: The current value of the SDA signal. - RFF: enum(u1) { // bit offset: 8 desc: Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. - @"RX_FIFO_IS_NOT_FULL" = 0, // desc: RX FIFO is not full - @"RX_FIFO_IS_FULL" = 1, // desc: RX FIFO is full - }, - RFE: enum(u1) { // bit offset: 9 desc: Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. - @"DATA" = 0, // desc: RX FIFO contains data. - @"EMPTY" = 1, // desc: RX FIFO is empty - }, - TFF: enum(u1) { // bit offset: 10 desc: Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. - @"TX_FIFO_IS_NOT_FULL_" = 0, // desc: TX FIFO is not full. - @"TX_FIFO_IS_FULL" = 1, // desc: TX FIFO is full - }, - TFE: enum(u1) { // bit offset: 11 desc: Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. - @"VALID_DATA" = 0, // desc: TX FIFO contains valid data. - @"EMPTY" = 1, // desc: TX FIFO is empty - }, - // RESERVED: u20, // bit offset: 12 desc: Reserved. Read value is undefined, only zero should be written. - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 776 I2C Control - pub const I2C_CTL = mmio(Address + 0x00000308, 32, packed struct { - TDIE: enum(u1) { // bit offset: 0 desc: Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. - @"DISABLE_THE_TDI_INTE" = 0, // desc: Disable the TDI interrupt. - @"ENABLE_THE_TDI_INTER" = 1, // desc: Enable the TDI interrupt. - }, - AFIE: enum(u1) { // bit offset: 1 desc: Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. - @"DISABLE_THE_AFI_" = 0, // desc: Disable the AFI. - @"ENABLE_THE_AFI_" = 1, // desc: Enable the AFI. - }, - NAIE: enum(u1) { // bit offset: 2 desc: Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. - @"DISABLE_THE_NAI_" = 0, // desc: Disable the NAI. - @"ENABLE_THE_NAI_" = 1, // desc: Enable the NAI. - }, - DRMIE: enum(u1) { // bit offset: 3 desc: Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. - @"DISABLE_THE_DRMI_INT" = 0, // desc: Disable the DRMI interrupt. - @"ENABLE_THE_DRMI_INTE" = 1, // desc: Enable the DRMI interrupt. - }, - DRSIE: enum(u1) { // bit offset: 4 desc: Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. - @"DISABLE_THE_DRSI_INT" = 0, // desc: Disable the DRSI interrupt. - @"ENABLE_THE_DRSI_INTE" = 1, // desc: Enable the DRSI interrupt. - }, - REFIE: enum(u1) { // bit offset: 5 desc: Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. - @"DISABLE_THE_RFFI_" = 0, // desc: Disable the RFFI. - @"ENABLE_THE_RFFI_" = 1, // desc: Enable the RFFI. - }, - RFDAIE: enum(u1) { // bit offset: 6 desc: Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). - @"DISABLE_THE_DAI_" = 0, // desc: Disable the DAI. - @"ENABLE_THE_DAI_" = 1, // desc: Enable the DAI. - }, - TFFIE: enum(u1) { // bit offset: 7 desc: Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. - @"DISABLE_THE_TFFI_" = 0, // desc: Disable the TFFI. - @"ENABLE_THE_TFFI_" = 1, // desc: Enable the TFFI. - }, - SRST: enum(u1) { // bit offset: 8 desc: Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. - @"NO_RESET" = 0, // desc: No reset. - @"RESET" = 1, // desc: Reset the I2C to idle state. Self clearing. - }, - // RESERVED: u23, // bit offset: 9 desc: Reserved. Read value is undefined, only zero should be written. - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 780 I2C Clock High - pub const I2C_CLKHI = mmio(Address + 0x0000030c, 32, packed struct { - CDHI: u8, // bit offset: 0 desc: Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 784 I2C Clock Low - pub const I2C_CLKLO = mmio(Address + 0x00000310, 32, packed struct { - CDLO: u8, // bit offset: 0 desc: Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. - // RESERVED: u24, // bit offset: 8 desc: Reserved. Read value is undefined, only zero should be written. - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 USB Clock Control - pub const USBCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DEV_CLK_EN: u1, // bit offset: 1 desc: Device clock enable. Enables the usbclk input to the device controller - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - PORTSEL_CLK_EN: u1, // bit offset: 3 desc: Port select register clock enable. - AHB_CLK_EN: u1, // bit offset: 4 desc: AHB clock enable - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4084 OTG clock controller - pub const OTGCLKCTRL = mmio(Address + 0x00000ff4, 32, packed struct { - HOST_CLK_EN: enum(u1) { // bit offset: 0 desc: Host clock enable - @"DISABLE_THE_HOST_CLO" = 0, // desc: Disable the Host clock. - @"ENABLE_THE_HOST_CLOC" = 1, // desc: Enable the Host clock. - }, - DEV_CLK_EN: enum(u1) { // bit offset: 1 desc: Device clock enable - @"DISABLE_THE_DEVICE_C" = 0, // desc: Disable the Device clock. - @"ENABLE_THE_DEVICE_CL" = 1, // desc: Enable the Device clock. - }, - I2C_CLK_EN: enum(u1) { // bit offset: 2 desc: I2C clock enable - @"DISABLE_THE_I2C_CLOC" = 0, // desc: Disable the I2C clock. - @"ENABLE_THE_I2C_CLOCK" = 1, // desc: Enable the I2C clock. - }, - OTG_CLK_EN: enum(u1) { // bit offset: 3 desc: OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. - @"DISABLE_THE_OTG_CLOC" = 0, // desc: Disable the OTG clock. - @"ENABLE_THE_OTG_CLOCK" = 1, // desc: Enable the OTG clock. - }, - AHB_CLK_EN: enum(u1) { // bit offset: 4 desc: AHB master clock enable - @"DISABLE_THE_AHB_CLOC" = 0, // desc: Disable the AHB clock. - @"ENABLE_THE_AHB_CLOCK" = 1, // desc: Enable the AHB clock. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4088 USB Clock Status - pub const USBCLKST = mmio(Address + 0x00000ff8, 32, packed struct { - // RESERVED: u1, // bit offset: 0 desc: Reserved. Read value is undefined, only zero should be written. - reserved1: u1 = 0, - DEV_CLK_ON: u1, // bit offset: 1 desc: Device clock on. The usbclk input to the device controller is active . - // RESERVED: u1, // bit offset: 2 desc: Reserved. Read value is undefined, only zero should be written. - reserved2: u1 = 0, - PORTSEL_CLK_ON: u1, // bit offset: 3 desc: Port select register clock on. - AHB_CLK_ON: u1, // bit offset: 4 desc: AHB clock on. - // RESERVED: u27, // bit offset: 5 desc: Reserved. The value read from a reserved bit is not defined. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - // byte offset: 4088 OTG clock status - pub const OTGCLKST = mmio(Address + 0x00000ff8, 32, packed struct { - HOST_CLK_ON: enum(u1) { // bit offset: 0 desc: Host clock status. - @"HOST_CLOCK_IS_NOT_AV" = 0, // desc: Host clock is not available. - @"HOST_CLOCK_IS_AVAILA" = 1, // desc: Host clock is available. - }, - DEV_CLK_ON: enum(u1) { // bit offset: 1 desc: Device clock status. - @"DEVICE_CLOCK_IS_NOT_" = 0, // desc: Device clock is not available. - @"DEVICE_CLOCK_IS_AVAI" = 1, // desc: Device clock is available. - }, - I2C_CLK_ON: enum(u1) { // bit offset: 2 desc: I2C clock status. - @"I2C_CLOCK_IS_NOT_AVA" = 0, // desc: I2C clock is not available. - @"I2C_CLOCK_IS_AVAILAB" = 1, // desc: I2C clock is available. - }, - OTG_CLK_ON: enum(u1) { // bit offset: 3 desc: OTG clock status. - @"OTG_CLOCK_IS_NOT_AVA" = 0, // desc: OTG clock is not available. - @"OTG_CLOCK_IS_AVAILAB" = 1, // desc: OTG clock is available. - }, - AHB_CLK_ON: enum(u1) { // bit offset: 4 desc: AHB master clock status. - @"AHB_CLOCK_IS_NOT_AVA" = 0, // desc: AHB clock is not available. - @"AHB_CLOCK_IS_AVAILAB" = 1, // desc: AHB clock is available. - }, - // RESERVED: u27, // bit offset: 5 desc: Reserved. Read value is undefined, only zero should be written. - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); +// this file is generated by regz +// +// device: LPC176x5x +// cpu: CM3 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + TIMER0: InterruptVector = unhandled, + TIMER1: InterruptVector = unhandled, + TIMER2: InterruptVector = unhandled, + TIMER3: InterruptVector = unhandled, + UART0: InterruptVector = unhandled, + UART1: InterruptVector = unhandled, + UART2: InterruptVector = unhandled, + UART3: InterruptVector = unhandled, + PWM1: InterruptVector = unhandled, + I2C0: InterruptVector = unhandled, + I2C1: InterruptVector = unhandled, + I2C2: InterruptVector = unhandled, + SPI: InterruptVector = unhandled, + SSP0: InterruptVector = unhandled, + SSP1: InterruptVector = unhandled, + PLL0: InterruptVector = unhandled, + RTC: InterruptVector = unhandled, + EINT0: InterruptVector = unhandled, + EINT1: InterruptVector = unhandled, + EINT2: InterruptVector = unhandled, + EINT3: InterruptVector = unhandled, + ADC: InterruptVector = unhandled, + BOD: InterruptVector = unhandled, + USB: InterruptVector = unhandled, + CAN: InterruptVector = unhandled, + DMA: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + ENET: InterruptVector = unhandled, + RIT: InterruptVector = unhandled, + MCPWM: InterruptVector = unhandled, + QEI: InterruptVector = unhandled, + PLL1: InterruptVector = unhandled, + USBActivity: InterruptVector = unhandled, + CANActivity: InterruptVector = unhandled, }; -pub const GPIO = extern struct { - pub const Address: u32 = 0x2009c000; - // byte offset: 0 GPIO Port Direction control register. - pub const DIR0 = mmio(Address + 0x00000000, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 16 Mask register for Port. - pub const MASK0 = mmio(Address + 0x00000010, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 20 Port Pin value register using FIOMASK. - pub const PIN0 = mmio(Address + 0x00000014, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 24 Port Output Set register using FIOMASK. - pub const SET0 = mmio(Address + 0x00000018, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 28 Port Output Clear register using FIOMASK. - pub const CLR0 = mmio(Address + 0x0000001c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 32 GPIO Port Direction control register. - pub const DIR1 = mmio(Address + 0x00000020, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 48 Mask register for Port. - pub const MASK1 = mmio(Address + 0x00000030, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 52 Port Pin value register using FIOMASK. - pub const PIN1 = mmio(Address + 0x00000034, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 56 Port Output Set register using FIOMASK. - pub const SET1 = mmio(Address + 0x00000038, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 60 Port Output Clear register using FIOMASK. - pub const CLR1 = mmio(Address + 0x0000003c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 64 GPIO Port Direction control register. - pub const DIR2 = mmio(Address + 0x00000040, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 80 Mask register for Port. - pub const MASK2 = mmio(Address + 0x00000050, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 84 Port Pin value register using FIOMASK. - pub const PIN2 = mmio(Address + 0x00000054, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 88 Port Output Set register using FIOMASK. - pub const SET2 = mmio(Address + 0x00000058, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 92 Port Output Clear register using FIOMASK. - pub const CLR2 = mmio(Address + 0x0000005c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 96 GPIO Port Direction control register. - pub const DIR3 = mmio(Address + 0x00000060, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 112 Mask register for Port. - pub const MASK3 = mmio(Address + 0x00000070, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 116 Port Pin value register using FIOMASK. - pub const PIN3 = mmio(Address + 0x00000074, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 120 Port Output Set register using FIOMASK. - pub const SET3 = mmio(Address + 0x00000078, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 124 Port Output Clear register using FIOMASK. - pub const CLR3 = mmio(Address + 0x0000007c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); - // byte offset: 128 GPIO Port Direction control register. - pub const DIR4 = mmio(Address + 0x00000080, 32, packed struct { - PINDIR0: u1, // bit offset: 0 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR1: u1, // bit offset: 1 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR2: u1, // bit offset: 2 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR3: u1, // bit offset: 3 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR4: u1, // bit offset: 4 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR5: u1, // bit offset: 5 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR6: u1, // bit offset: 6 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR7: u1, // bit offset: 7 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR8: u1, // bit offset: 8 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR9: u1, // bit offset: 9 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR10: u1, // bit offset: 10 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR11: u1, // bit offset: 11 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR12: u1, // bit offset: 12 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR13: u1, // bit offset: 13 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR14: u1, // bit offset: 14 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR15: u1, // bit offset: 15 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR16: u1, // bit offset: 16 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR17: u1, // bit offset: 17 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR18: u1, // bit offset: 18 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR19: u1, // bit offset: 19 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR20: u1, // bit offset: 20 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR21: u1, // bit offset: 21 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR22: u1, // bit offset: 22 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR23: u1, // bit offset: 23 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR24: u1, // bit offset: 24 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR25: u1, // bit offset: 25 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR26: u1, // bit offset: 26 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR27: u1, // bit offset: 27 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR28: u1, // bit offset: 28 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR29: u1, // bit offset: 29 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR30: u1, // bit offset: 30 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - PINDIR31: u1, // bit offset: 31 desc: Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. - }); - // byte offset: 144 Mask register for Port. - pub const MASK4 = mmio(Address + 0x00000090, 32, packed struct { - PINMASK0: u1, // bit offset: 0 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK1: u1, // bit offset: 1 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK2: u1, // bit offset: 2 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK3: u1, // bit offset: 3 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK4: u1, // bit offset: 4 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK5: u1, // bit offset: 5 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK6: u1, // bit offset: 6 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK7: u1, // bit offset: 7 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK8: u1, // bit offset: 8 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK9: u1, // bit offset: 9 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK10: u1, // bit offset: 10 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK11: u1, // bit offset: 11 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK12: u1, // bit offset: 12 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK13: u1, // bit offset: 13 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK14: u1, // bit offset: 14 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK15: u1, // bit offset: 15 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK16: u1, // bit offset: 16 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK17: u1, // bit offset: 17 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK18: u1, // bit offset: 18 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK19: u1, // bit offset: 19 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK20: u1, // bit offset: 20 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK21: u1, // bit offset: 21 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK22: u1, // bit offset: 22 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK23: u1, // bit offset: 23 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK24: u1, // bit offset: 24 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK25: u1, // bit offset: 25 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK26: u1, // bit offset: 26 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK27: u1, // bit offset: 27 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK28: u1, // bit offset: 28 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK29: u1, // bit offset: 29 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK30: u1, // bit offset: 30 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - PINMASK31: u1, // bit offset: 31 desc: Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin. - }); - // byte offset: 148 Port Pin value register using FIOMASK. - pub const PIN4 = mmio(Address + 0x00000094, 32, packed struct { - PINVAL0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - PINVAL31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 152 Port Output Set register using FIOMASK. - pub const SET4 = mmio(Address + 0x00000098, 32, packed struct { - PINSET0: u1, // bit offset: 0 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET1: u1, // bit offset: 1 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET2: u1, // bit offset: 2 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET3: u1, // bit offset: 3 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET4: u1, // bit offset: 4 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET5: u1, // bit offset: 5 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET6: u1, // bit offset: 6 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET7: u1, // bit offset: 7 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET8: u1, // bit offset: 8 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET9: u1, // bit offset: 9 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET10: u1, // bit offset: 10 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET11: u1, // bit offset: 11 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET12: u1, // bit offset: 12 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET13: u1, // bit offset: 13 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET14: u1, // bit offset: 14 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET15: u1, // bit offset: 15 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET16: u1, // bit offset: 16 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET17: u1, // bit offset: 17 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET18: u1, // bit offset: 18 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET19: u1, // bit offset: 19 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET20: u1, // bit offset: 20 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET21: u1, // bit offset: 21 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET22: u1, // bit offset: 22 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET23: u1, // bit offset: 23 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET24: u1, // bit offset: 24 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET25: u1, // bit offset: 25 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET26: u1, // bit offset: 26 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET27: u1, // bit offset: 27 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET28: u1, // bit offset: 28 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET29: u1, // bit offset: 29 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET30: u1, // bit offset: 30 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - PINSET31: u1, // bit offset: 31 desc: Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. - }); - // byte offset: 156 Port Output Clear register using FIOMASK. - pub const CLR4 = mmio(Address + 0x0000009c, 32, packed struct { - PINCLR0: u1, // bit offset: 0 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR1: u1, // bit offset: 1 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR2: u1, // bit offset: 2 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR3: u1, // bit offset: 3 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR4: u1, // bit offset: 4 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR5: u1, // bit offset: 5 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR6: u1, // bit offset: 6 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR7: u1, // bit offset: 7 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR8: u1, // bit offset: 8 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR9: u1, // bit offset: 9 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR10: u1, // bit offset: 10 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR11: u1, // bit offset: 11 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR12: u1, // bit offset: 12 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR13: u1, // bit offset: 13 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR14: u1, // bit offset: 14 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR15: u1, // bit offset: 15 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR16: u1, // bit offset: 16 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR17: u1, // bit offset: 17 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR18: u1, // bit offset: 18 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR19: u1, // bit offset: 19 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR20: u1, // bit offset: 20 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR21: u1, // bit offset: 21 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR22: u1, // bit offset: 22 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR23: u1, // bit offset: 23 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR24: u1, // bit offset: 24 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR25: u1, // bit offset: 25 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR26: u1, // bit offset: 26 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR27: u1, // bit offset: 27 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR28: u1, // bit offset: 28 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR29: u1, // bit offset: 29 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR30: u1, // bit offset: 30 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - PINCLR31: u1, // bit offset: 31 desc: Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. - }); + +pub const registers = struct { + /// Watchdog Timer (WDT) + pub const WDT = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// Watchdog mode register. This register determines the basic mode and status of + /// the Watchdog Timer. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog enable bit. This bit is Set Only. + WDEN: u1, + /// Watchdog reset enable bit. This bit is Set Only. See Table 652. + WDRESET: u1, + /// Watchdog time-out flag. Set when the watchdog timer times out, cleared by + /// software. + WDTOF: u1, + /// Watchdog interrupt flag. Cleared by software. + WDINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x0); + + /// address: 0x40000004 + /// Watchdog timer constant register. The value in this register determines the + /// time-out value. + pub const TC = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog time-out interval. + Count: u32, + }), base_address + 0x4); + + /// address: 0x40000008 + /// Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register + /// reloads the Watchdog timer with the value contained in WDTC. + pub const FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// Feed value should be 0xAA followed by 0x55. + Feed: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// Watchdog timer value register. This register reads out the current value of the + /// Watchdog timer. + pub const TV = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter timer value. + Count: u32, + }), base_address + 0xc); + + /// address: 0x40000010 + /// Watchdog clock select register. + pub const CLKSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects source of WDT clock + CLKSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// If this bit is set to one writing to this register does not affect bit 0. The + /// clock source can only be changed by first clearing this bit, then writing the + /// new value of bit 0. + LOCK: u1, + }), base_address + 0x10); + }; + /// Timer0/1/2/3 + pub const TIMER0 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40004004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40004008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000400c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40004010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40004014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40004018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40004028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4000402c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4000403c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40004070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const TIMER1 = struct { + pub const base_address = 0x40008000; + + /// address: 0x40008000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40008004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40008008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000800c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40008010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40008014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40008018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40008028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4000802c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4000803c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40008070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + /// UART0/2/3 + pub const UART0 = struct { + pub const base_address = 0x4000c000; + + /// address: 0x4000c000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4000c004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4000c004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x4000c008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x4000c008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4000c00c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x4000c014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4000c01c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x4000c020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x4000c028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4000c030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4000c04c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x4000c050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x4000c054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + /// UART1 + pub const UART1 = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// DLAB =0 Receiver Buffer Register. Contains the next received character to be + /// read. + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Receiver Buffer Register contains the oldest received byte in the + /// UART1 RX FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010000 + /// DLAB =0. Transmit Holding Register. The next character to be transmitted is + /// written here. + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UART1 Transmit Holding Register causes the data to be stored in + /// the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010000 + /// DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor + /// value. The full divisor is used to generate a baud rate from the fractional rate + /// divider. + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines + /// the baud rate of the UART1. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor + /// value. The full divisor is used to generate a baud rate from the fractional rate + /// divider. + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines + /// the baud rate of the UART1. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40010004 + /// DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits + /// for the 7 potential UART1 interrupts. + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this + /// interrupt can be read from LSR[5]. + THREIE: u1, + /// RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The + /// status of this interrupt can be read from LSR[4:1]. + RXIE: u1, + /// Modem Status Interrupt Enable. Enables the modem interrupt. The status of this + /// interrupt can be read from MSR[3:0]. + MSIE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u3, + /// CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the + /// modem status interrupt generation on a CTS1 signal transition. If auto-cts mode + /// is disabled a CTS1 transition will generate an interrupt if Modem Status + /// Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition + /// will generate a Modem Status Interrupt unless the interrupt has been disabled by + /// clearing the IER[3] bit in the IER register. In auto-cts mode a transition on + /// the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits + /// are set. + CTSIE: u1, + /// Enables the end of auto-baud interrupt. + ABEOIE: u1, + /// Enables the auto-baud time-out interrupt. + ABTOIE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x40010008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that IIR[0] is active low. The pending interrupt can be + /// determined by evaluating IIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. IER[3:1] identifies an interrupt corresponding to the + /// UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are + /// reserved (100,101,111). + INTID: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Copies of FCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x40010008 + /// FIFO Control Register. Controls UART1 FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this + /// bit selects the DMA mode. See Section 36.6.6.1. + DMAMODE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UART1 FIFO + /// characters must be written before an interrupt is activated. + RXTRIGLVL: u2, + /// Reserved, user software should not write ones to reserved bits. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4001000c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select. + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select. + PS: u2, + /// Break Control. + BC: u1, + /// Divisor Latch Access Bit (DLAB) + DLAB: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// Modem Control Register. Contains controls for flow control handshaking and + /// loopback mode. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem + /// loopback mode is active. + DTRCTRL: u1, + /// RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem + /// loopback mode is active. + RTSCTRL: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Loopback Mode Select. The modem loopback mode provides a mechanism to perform + /// diagnostic loopback testing. Serial data from the transmitter is connected + /// internally to serial input of the receiver. Input pin, RXD1, has no effect on + /// loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, + /// DSR, RI and DCD) are disconnected externally. Externally, the modem outputs + /// (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to + /// the 4 modem inputs. As a result of these connections, the upper 4 bits of the + /// MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs + /// in normal mode. This permits modem status interrupts to be generated in loopback + /// mode by writing the lower 4 bits of MCR. + LMS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// RTS enable. + RTSEN: u1, + /// CTS enable. + CTSEN: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40010014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is + /// cleared when the UART1 RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An LSR + /// read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled + /// and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be + /// overwritten and the character in the UART1 RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection + /// is dependent on FCR[0]. Note: A parity error is associated with the character at + /// the top of the UART1 RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An LSR read clears LSR[3]. The time of the framing error detection + /// is dependent on FCR0. Upon detection of a framing error, the RX will attempt to + /// resynchronize to the data and assume that the bad stop bit is actually an early + /// start bit. However, it cannot be assumed that the next received byte will be + /// correct even if there is no Framing Error. Note: A framing error is associated + /// with the character at the top of the UART1 RBR FIFO. + FE: u1, + /// Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXD1 goes to marking state (all ones). An LSR read clears this status bit. The + /// time of break detection is dependent on FCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UART1 RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UART1 THR and is cleared on a THR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared + /// when either the TSR or the THR contain valid data. + TEMT: u1, + /// Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing + /// error, parity error or break interrupt, is loaded into the RBR. This bit is + /// cleared when the LSR register is read and there are no subsequent errors in the + /// UART1 FIFO. + RXFE: u1, + /// Reserved, the value read from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// Modem Status Register. Contains handshake signal status flags. + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. + DCTS: u1, + /// Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. + DDSR: u1, + /// Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR + /// read. + TERI: u1, + /// Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. + DDCD: u1, + /// Clear To Send State. Complement of input signal CTS. This bit is connected to + /// MCR[1] in modem loopback mode. + CTS: u1, + /// Data Set Ready State. Complement of input signal DSR. This bit is connected to + /// MCR[0] in modem loopback mode. + DSR: u1, + /// Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in + /// modem loopback mode. + RI: u1, + /// Data Carrier Detect State. Complement of input DCD. This bit is connected to + /// MCR[3] in modem loopback mode. + DCD: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4001001c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + Pad: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Auto-baud start bit. This bit is automatically cleared after auto-baud + /// completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Auto-baud restart bit. + AUTORESTART: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only). + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only). + ABTOINTCLR: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x40010028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud rate generator will not impact the UART1 baud rate. + DIVADDVAL: u4, + /// Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UART1 to operate properly, regardless of whether the fractional baud rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x40010030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit cleared to + /// 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software can clear this bit when it + /// detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, + /// or with software handshaking, when it receives an XOFF character (DC3). Software + /// can set this bit again when it detects that the TX-permit signal has gone true, + /// or when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4001004c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. + NMMEN: u1, + /// Receive enable. + RXDIS: u1, + /// Auto Address Detect (AAD) enable. + AADEN: u1, + /// Direction control. + SEL: u1, + /// Direction control enable. + DCTRL: u1, + /// Polarity. This bit reverses the polarity of the direction control signal on the + /// RTS (or DTR) pin. + OINV: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x40010050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x40010054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (RTS or DTR) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + /// Pulse Width Modulators (PWM1) + pub const PWM1 = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Interrupt Register. The IR can be written to clear interrupts, or read to + /// identify which PWM interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for PWM match channel 0. + PWMMR0INT: u1, + /// Interrupt flag for PWM match channel 1. + PWMMR1INT: u1, + /// Interrupt flag for PWM match channel 2. + PWMMR2INT: u1, + /// Interrupt flag for PWM match channel 3. + PWMMR3INT: u1, + /// Interrupt flag for capture input 0 + PWMCAP0INT: u1, + /// Interrupt flag for capture input 1 (available in PWM1IR only; this bit is + /// reserved in PWM0IR). + PWMCAP1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Interrupt flag for PWM match channel 4. + PWMMR4INT: u1, + /// Interrupt flag for PWM match channel 5. + PWMMR5INT: u1, + /// Interrupt flag for PWM match channel 6. + PWMMR6INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x0); + + /// address: 0x40018004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter Enable + CE: u1, + /// Counter Reset + CR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// PWM Enable + PWMEN: u1, + /// Master Disable (PWM0 only). The two PWMs may be synchronized using the Master + /// Disable control bit. The Master disable bit of the Master PWM (PWM0 module) + /// controls a secondary enable input to both PWMs, as shown in Figure 141. This bit + /// has no function in the Slave PWM (PWM1). + MDIS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x4); + + /// address: 0x40018008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001800c + /// Prescale Register. Determines how often the PWM counter is incremented. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40018010 + /// Prescale Counter. Prescaler for the main PWM counter. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40018014 + /// Match Control Register. The MCR is used to control whether an interrupt is + /// generated and if the PWM counter is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt PWM0 + PWMMR0I: u1, + /// Reset PWM0 + PWMMR0R: u1, + /// Stop PWM0 + PWMMR0S: u1, + /// Interrupt PWM1 + PWMMR1I: u1, + /// Reset PWM1 + PWMMR1R: u1, + /// Stop PWM1 + PWMMR1S: u1, + /// Interrupt PWM0 + PWMMR2I: u1, + /// Reset PWM0 + PWMMR2R: u1, + /// Stop PWM0 + PWMMR2S: u1, + /// Interrupt PWM3 + PWMMR3I: u1, + /// Reset PWM3 + PWMMR3R: u1, + /// Stop PWM0 + PWMMR3S: u1, + /// Interrupt PWM4 + PWMMR4I: u1, + /// Reset PWM4 + PWMMR4R: u1, + /// Stop PWM4 + PWMMR4S: u1, + /// Interrupt PWM5 + PWMMR5I: u1, + /// Reset PWM5 + PWMMR5R: u1, + /// Stop PWM5 + PWMMR5S: u1, + /// Interrupt PWM6 + PWMMR6I: u1, + /// Reset PWM6 + PWMMR6R: u1, + /// Stop PWM6 + PWMMR6S: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + }), base_address + 0x14); + + /// address: 0x40018018 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x4001801c + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x1c); + + /// address: 0x40018020 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x20); + + /// address: 0x40018024 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x24); + + /// address: 0x40018028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// for a capture event. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on PWMn_CAP0 rising edge + CAP0_R: u1, + /// Capture on PWMn_CAP0 falling edge + CAP0_F: u1, + /// Interrupt on PWMn_CAP0 event + CAP0_I: u1, + /// Capture on PWMn_CAP1 rising edge. Reserved for PWM0. + CAP1_R: u1, + /// Capture on PWMn_CAP1 falling edge. Reserved for PWM0. + CAP1_F: u1, + /// Interrupt on PWMn_CAP1 event. Reserved for PWM0. + CAP1_I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4001802c + /// PWM Control Register. Enables PWM outputs and selects either single edge or + /// double edge controlled PWM outputs. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Reserved. + RESERVED: u2, + /// PWM[2] output single/double edge mode control. + PWMSEL2: u1, + /// PWM[3] output edge control. + PWMSEL3: u1, + /// PWM[4] output edge control. + PWMSEL4: u1, + /// PWM[5] output edge control. + PWMSEL5: u1, + /// PWM[6] output edge control. + PWMSEL6: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// PWM[1] output enable control. + PWMENA1: u1, + /// PWM[2] output enable control. + PWMENA2: u1, + /// PWM[3] output enable control. + PWMENA3: u1, + /// PWM[4] output enable control. + PWMENA4: u1, + /// PWM[5] output enable control. + PWMENA5: u1, + /// PWM[6] output enable control. See PWMENA1 for details. + PWMENA6: u1, + /// Unused, always zero. + RESERVED: u17, + }), base_address + 0x2c); + + /// address: 0x40018040 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x40); + + /// address: 0x40018044 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x44); + + /// address: 0x40018048 + /// Match Register. Match registers + /// are continuously compared to the PWM counter in order to control PWM + /// output edges. + pub const MR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x48); + + /// address: 0x4001804c + /// PWM Control Register. Enables PWM outputs and selects either single edge or + /// double edge controlled PWM outputs. + pub const PCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u2, + /// PWM[2] output single/double edge mode control. + PWMSEL2: u1, + /// PWM[3] output edge control. + PWMSEL3: u1, + /// PWM[4] output edge control. + PWMSEL4: u1, + /// PWM[5] output edge control. + PWMSEL5: u1, + /// PWM[6] output edge control. + PWMSEL6: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// PWM[1] output enable control. + PWMENA1: u1, + /// PWM[2] output enable control. + PWMENA2: u1, + /// PWM[3] output enable control. + PWMENA3: u1, + /// PWM[4] output enable control. + PWMENA4: u1, + /// PWM[5] output enable control. + PWMENA5: u1, + /// PWM[6] output enable control. See PWMENA1 for details. + PWMENA6: u1, + /// Unused, always zero. + RESERVED: u17, + }), base_address + 0x4c); + + /// address: 0x40018050 + /// Load Enable Register. Enables use of updated PWM match values. + pub const LER = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this + /// bit allows the last value written to the PWM Match Register 0 to be become + /// effective when the timer is next reset by a PWM Match event. See Section 27.6.7. + MAT0LATCHEN: u1, + /// Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for + /// details. + MAT1LATCHEN: u1, + /// Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for + /// details. + MAT2LATCHEN: u1, + /// Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for + /// details. + MAT3LATCHEN: u1, + /// Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for + /// details. + MAT4LATCHEN: u1, + /// Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for + /// details. + MAT5LATCHEN: u1, + /// Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for + /// details. + MAT6LATCHEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x50); + + /// address: 0x40018070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/ Timer Mode + MOD: u2, + /// Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP + /// pin carries the signal used to increment the TC. Other combinations are + /// reserved. + CIS: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + /// I2C bus interface + pub const I2C0 = struct { + pub const base_address = 0x4001c000; + + /// address: 0x4001c000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x4001c004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4001c008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4001c00c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4001c010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x4001c014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x4001c018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4001c01c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x4001c020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x4001c024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x4001c028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4001c02c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x4001c030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// SPI + pub const SPI = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// SPI Control Register. This register controls the operation of the SPI. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// The SPI controller sends and receives 8 bits of data per transfer. + BITENABLE: u1, + /// Clock phase control determines the relationship between the data and the clock + /// on SPI transfers, and controls when a slave transfer is defined as starting and + /// ending. + CPHA: u1, + /// Clock polarity control. + CPOL: u1, + /// Master mode select. + MSTR: u1, + /// LSB First controls which direction each byte is shifted when transferred. + LSBF: u1, + /// Serial peripheral interrupt enable. + SPIE: u1, + /// When bit 2 of this register is 1, this field controls the number of bits per + /// transfer: + BITS: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x0); + + /// address: 0x40020004 + /// SPI Status Register. This register shows the status of the SPI. + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u3, + /// Slave abort. When 1, this bit indicates that a slave abort has occurred. This + /// bit is cleared by reading this register. + ABRT: u1, + /// Mode fault. when 1, this bit indicates that a Mode fault error has occurred. + /// This bit is cleared by reading this register, then writing the SPI0 control + /// register. + MODF: u1, + /// Read overrun. When 1, this bit indicates that a read overrun has occurred. This + /// bit is cleared by reading this register. + ROVR: u1, + /// Write collision. When 1, this bit indicates that a write collision has occurred. + /// This bit is cleared by reading this register, then accessing the SPI Data + /// Register. + WCOL: u1, + /// SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer + /// is complete. When a master, this bit is set at the end of the last cycle of the + /// transfer. When a slave, this bit is set on the last data sampling edge of the + /// SCK. This bit is cleared by first reading this register, then accessing the SPI + /// Data Register. Note: this is not the SPI interrupt flag. This flag is found in + /// the SPINT register. + SPIF: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40020008 + /// SPI Data Register. This bi-directional register provides the transmit and + /// receive data for the SPI. Transmit data is provided to the SPI0 by writing to + /// this register. Data received by the SPI0 can be read from this register. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI Bi-directional data port. + DATALOW: u8, + /// If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of + /// these bits contain the additional transmit and receive bits. When less than 16 + /// bits are selected, the more significant among these bits read as zeroes. + DATAHIGH: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4002000c + /// SPI Clock Counter Register. This register controls the frequency of a master's + /// SCK0. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI0 Clock counter setting. + COUNTER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4002001c + /// SPI Interrupt Flag. This register contains the interrupt flag for the SPI + /// interface. + pub const INT = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared + /// by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at + /// least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit + /// is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be + /// processed by interrupt handling software. + SPIF: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u7, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x1c); + }; + /// Real Time Clock (RTC) + pub const RTC = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// Interrupt Location Register + pub const ILR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Counter Increment Interrupt block generated an interrupt. Writing + /// a one to this bit location clears the counter increment interrupt. + RTCCIF: u1, + /// When one, the alarm registers generated an interrupt. Writing a one to this bit + /// location clears the alarm interrupt. + RTCALF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + }), base_address + 0x0); + + /// address: 0x40024008 + /// Clock Control Register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock Enable. + CLKEN: u1, + /// CTC Reset. + CTCRST: u1, + /// Internal test mode controls. These bits must be 0 for normal RTC operation. + RESERVED: u2, + /// Calibration counter enable. + CCALEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x8); + + /// address: 0x4002400c + /// Counter Increment Interrupt Register + pub const CIIR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, an increment of the Second value generates an interrupt. + IMSEC: u1, + /// When 1, an increment of the Minute value generates an interrupt. + IMMIN: u1, + /// When 1, an increment of the Hour value generates an interrupt. + IMHOUR: u1, + /// When 1, an increment of the Day of Month value generates an interrupt. + IMDOM: u1, + /// When 1, an increment of the Day of Week value generates an interrupt. + IMDOW: u1, + /// When 1, an increment of the Day of Year value generates an interrupt. + IMDOY: u1, + /// When 1, an increment of the Month value generates an interrupt. + IMMON: u1, + /// When 1, an increment of the Year value generates an interrupt. + IMYEAR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x40024010 + /// Alarm Mask Register + pub const AMR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the Second value is not compared for the alarm. + AMRSEC: u1, + /// When 1, the Minutes value is not compared for the alarm. + AMRMIN: u1, + /// When 1, the Hour value is not compared for the alarm. + AMRHOUR: u1, + /// When 1, the Day of Month value is not compared for the alarm. + AMRDOM: u1, + /// When 1, the Day of Week value is not compared for the alarm. + AMRDOW: u1, + /// When 1, the Day of Year value is not compared for the alarm. + AMRDOY: u1, + /// When 1, the Month value is not compared for the alarm. + AMRMON: u1, + /// When 1, the Year value is not compared for the alarm. + AMRYEAR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40024014 + /// Consolidated Time Register 0 + pub const CTIME0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u2, + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u2, + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u3, + /// Day of week value in the range of 0 to 6 + DOW: u3, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + }), base_address + 0x14); + + /// address: 0x40024018 + /// Consolidated Time Register 1 + pub const CTIME1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u3, + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u4, + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u4, + }), base_address + 0x18); + + /// address: 0x4002401c + /// Consolidated Time Register 2 + pub const CTIME2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u12, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x1c); + + /// address: 0x40024020 + /// Seconds Counter + pub const SEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x20); + + /// address: 0x40024024 + /// Minutes Register + pub const MIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x24); + + /// address: 0x40024028 + /// Hours Register + pub const HRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x28); + + /// address: 0x4002402c + /// Day of Month Register + pub const DOM = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x2c); + + /// address: 0x40024030 + /// Day of Week Register + pub const DOW = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of week value in the range of 0 to 6. + DOW: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x30); + + /// address: 0x40024034 + /// Day of Year Register + pub const DOY = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u23, + }), base_address + 0x34); + + /// address: 0x40024038 + /// Months Register + pub const MONTH = @intToPtr(*volatile Mmio(32, packed struct { + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x38); + + /// address: 0x4002403c + /// Years Register + pub const YEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40024040 + /// Calibration Value Register + pub const CALIBRATION = @intToPtr(*volatile Mmio(32, packed struct { + /// If enabled, the calibration counter counts up to this value. The maximum value + /// is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL + /// = 0. + CALVAL: u17, + /// Calibration direction + CALDIR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x40); + + /// address: 0x40024044 + /// General Purpose Register 0 + pub const GPREG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x44); + + /// address: 0x40024048 + /// General Purpose Register 0 + pub const GPREG1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x48); + + /// address: 0x4002404c + /// General Purpose Register 0 + pub const GPREG2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x4c); + + /// address: 0x40024050 + /// General Purpose Register 0 + pub const GPREG3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x50); + + /// address: 0x40024054 + /// General Purpose Register 0 + pub const GPREG4 = @intToPtr(*volatile Mmio(32, packed struct { + /// General purpose storage. + GP: u32, + }), base_address + 0x54); + + /// address: 0x4002405c + /// RTC Auxiliary control register + pub const RTC_AUX = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator + /// stops, and when RTC power is first turned on. An interrupt will occur when this + /// bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is + /// enabled in the NVIC. Write: writing a 1 to this bit clears the flag. + RTC_OSCF: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM + /// pin indicates Deep Power-down mode. + RTC_PDOUT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x5c); + + /// address: 0x40024058 + /// RTC Auxiliary Enable register + pub const RTC_AUXEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect + /// interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is + /// enabled. See Section 30.6.2.5. + RTC_OSCFEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x58); + + /// address: 0x40024060 + /// Alarm value for Seconds + pub const ASEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds value in the range of 0 to 59 + SECONDS: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x60); + + /// address: 0x40024064 + /// Alarm value for Minutes + pub const AMIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Minutes value in the range of 0 to 59 + MINUTES: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x64); + + /// address: 0x40024068 + /// Alarm value for Hours + pub const AHRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Hours value in the range of 0 to 23 + HOURS: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x68); + + /// address: 0x4002406c + /// Alarm value for Day of Month + pub const ADOM = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the + /// month and whether it is a leap year). + DOM: u5, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0x6c); + + /// address: 0x40024070 + /// Alarm value for Day of Week + pub const ADOW = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of week value in the range of 0 to 6. + DOW: u3, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x70); + + /// address: 0x40024074 + /// Alarm value for Day of Year + pub const ADOY = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of year value in the range of 1 to 365 (366 for leap years). + DOY: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u23, + }), base_address + 0x74); + + /// address: 0x40024078 + /// Alarm value for Months + pub const AMON = @intToPtr(*volatile Mmio(32, packed struct { + /// Month value in the range of 1 to 12. + MONTH: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x78); + + /// address: 0x4002407c + /// Alarm value for Year + pub const AYRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Year value in the range of 0 to 4095. + YEAR: u12, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x7c); + }; + /// GPIO + pub const GPIOINT = struct { + pub const base_address = 0x40028080; + + /// address: 0x40028080 + /// GPIO overall Interrupt Status. + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 GPIO interrupt pending. + P0INT: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u1, + /// Port 2 GPIO interrupt pending. + P2INT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40028084 + /// GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_0REI: u1, + /// Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_1REI: u1, + /// Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_2REI: u1, + /// Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_3REI: u1, + /// Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_4REI: u1, + /// Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_5REI: u1, + /// Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_6REI: u1, + /// Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_7REI: u1, + /// Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_8REI: u1, + /// Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_9REI: u1, + /// Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_10REI: u1, + /// Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_11REI: u1, + /// Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_12REI: u1, + /// Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_13REI: u1, + /// Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_14REI: u1, + /// Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_15REI: u1, + /// Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_16REI: u1, + /// Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_17REI: u1, + /// Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_18REI: u1, + /// Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_19REI: u1, + /// Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_20REI: u1, + /// Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_21REI: u1, + /// Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_22REI: u1, + /// Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_23REI: u1, + /// Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_24REI: u1, + /// Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_25REI: u1, + /// Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_26REI: u1, + /// Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_27REI: u1, + /// Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_28REI: u1, + /// Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_29REI: u1, + /// Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P0_30REI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x4); + + /// address: 0x40028088 + /// GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_0FEI: u1, + /// Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_1FEI: u1, + /// Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_2FEI: u1, + /// Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_3FEI: u1, + /// Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_4FEI: u1, + /// Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_5FEI: u1, + /// Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_6FEI: u1, + /// Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_7FEI: u1, + /// Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_8FEI: u1, + /// Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_9FEI: u1, + /// Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_10FEI: u1, + /// Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_11FEI: u1, + /// Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_12FEI: u1, + /// Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_13FEI: u1, + /// Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_14FEI: u1, + /// Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_15FEI: u1, + /// Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_16FEI: u1, + /// Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_17FEI: u1, + /// Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_18FEI: u1, + /// Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_19FEI: u1, + /// Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_20FEI: u1, + /// Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_21FEI: u1, + /// Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_22FEI: u1, + /// Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_23FEI: u1, + /// Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_24FEI: u1, + /// Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_25FEI: u1, + /// Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_26FEI: u1, + /// Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_27FEI: u1, + /// Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_28FEI: u1, + /// Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_29FEI: u1, + /// Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P0_30FEI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x8); + + /// address: 0x4002808c + /// GPIO Interrupt Clear. + pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_0CI: u1, + /// Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_1CI: u1, + /// Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_2CI: u1, + /// Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_3CI: u1, + /// Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_4CI: u1, + /// Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_5CI: u1, + /// Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_6CI: u1, + /// Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_7CI: u1, + /// Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_8CI: u1, + /// Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_9CI: u1, + /// Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_10CI: u1, + /// Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_11CI: u1, + /// Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_12CI: u1, + /// Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_13CI: u1, + /// Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_14CI: u1, + /// Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_15CI: u1, + /// Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_16CI: u1, + /// Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_17CI: u1, + /// Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_18CI: u1, + /// Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_19CI: u1, + /// Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_20CI: u1, + /// Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_21CI: u1, + /// Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_22CI: u1, + /// Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_23CI: u1, + /// Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_24CI: u1, + /// Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_25CI: u1, + /// Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_26CI: u1, + /// Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_27CI: u1, + /// Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_28CI: u1, + /// Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_29CI: u1, + /// Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P0_30CI: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0xc); + + /// address: 0x40028090 + /// GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_0ER: u1, + /// Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_1ER: u1, + /// Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_2ER: u1, + /// Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_3ER: u1, + /// Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_4ER: u1, + /// Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_5ER: u1, + /// Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_6ER: u1, + /// Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_7ER: u1, + /// Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_8ER: u1, + /// Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_9ER: u1, + /// Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_10ER: u1, + /// Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_11ER: u1, + /// Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_12ER: u1, + /// Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_13ER: u1, + /// Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_14ER: u1, + /// Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_15ER: u1, + /// Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_16ER: u1, + /// Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_17ER: u1, + /// Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_18ER: u1, + /// Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_19ER: u1, + /// Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_20ER: u1, + /// Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_21ER: u1, + /// Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_22ER: u1, + /// Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_23ER: u1, + /// Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_24ER: u1, + /// Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_25ER: u1, + /// Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_26ER: u1, + /// Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_27ER: u1, + /// Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_28ER: u1, + /// Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_29ER: u1, + /// Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P0_30ER: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x10); + + /// address: 0x40028094 + /// GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_0EF: u1, + /// Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_1EF: u1, + /// Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_2EF: u1, + /// Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_3EF: u1, + /// Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_4EF: u1, + /// Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_5EF: u1, + /// Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_6EF: u1, + /// Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_7EF: u1, + /// Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_8EF: u1, + /// Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P0_9EF: u1, + /// Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_10EF: u1, + /// Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_11EF: u1, + /// Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_12EF: u1, + /// Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_13EF: u1, + /// Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_14EF: u1, + /// Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_15EF: u1, + /// Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_16EF: u1, + /// Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_17EF: u1, + /// Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_18EF: u1, + /// Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_19EF: u1, + /// Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_20EF: u1, + /// Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_21EF: u1, + /// Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_22EF: u1, + /// Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_23EF: u1, + /// Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_24EF: u1, + /// Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_25EF: u1, + /// Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_26EF: u1, + /// Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_27EF: u1, + /// Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_28EF: u1, + /// Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_29EF: u1, + /// Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P0_30EF: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x14); + + /// address: 0x400280a4 + /// GPIO Interrupt Status for Rising edge for Port 0. + pub const STATR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_0REI: u1, + /// Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_1REI: u1, + /// Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_2REI: u1, + /// Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_3REI: u1, + /// Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_4REI: u1, + /// Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_5REI: u1, + /// Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_6REI: u1, + /// Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_7REI: u1, + /// Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_8REI: u1, + /// Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_9REI: u1, + /// Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_10REI: u1, + /// Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_11REI: u1, + /// Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_12REI: u1, + /// Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = + /// Rising edge interrupt generated. + P2_13REI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x24); + + /// address: 0x400280a8 + /// GPIO Interrupt Status for Falling edge for Port 0. + pub const STATF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_0FEI: u1, + /// Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_1FEI: u1, + /// Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_2FEI: u1, + /// Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_3FEI: u1, + /// Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_4FEI: u1, + /// Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_5FEI: u1, + /// Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_6FEI: u1, + /// Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_7FEI: u1, + /// Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_8FEI: u1, + /// Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_9FEI: u1, + /// Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_10FEI: u1, + /// Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_11FEI: u1, + /// Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_12FEI: u1, + /// Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = + /// Falling edge interrupt generated. + P2_13FEI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x28); + + /// address: 0x400280ac + /// GPIO Interrupt Clear. + pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_0CI: u1, + /// Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_1CI: u1, + /// Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_2CI: u1, + /// Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_3CI: u1, + /// Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_4CI: u1, + /// Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_5CI: u1, + /// Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_6CI: u1, + /// Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_7CI: u1, + /// Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_8CI: u1, + /// Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_9CI: u1, + /// Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_10CI: u1, + /// Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_11CI: u1, + /// Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_12CI: u1, + /// Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding + /// bits in IOnINTSTATR and IOnSTATF. + P2_13CI: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x2c); + + /// address: 0x400280b0 + /// GPIO Interrupt Enable for Rising edge for Port 0. + pub const ENR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_0ER: u1, + /// Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_1ER: u1, + /// Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_2ER: u1, + /// Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_3ER: u1, + /// Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_4ER: u1, + /// Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_5ER: u1, + /// Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_6ER: u1, + /// Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_7ER: u1, + /// Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_8ER: u1, + /// Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_9ER: u1, + /// Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_10ER: u1, + /// Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_11ER: u1, + /// Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_12ER: u1, + /// Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = + /// Enable rising edge interrupt. + P2_13ER: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x30); + + /// address: 0x400280b4 + /// GPIO Interrupt Enable for Falling edge for Port 0. + pub const ENF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_0EF: u1, + /// Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_1EF: u1, + /// Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_2EF: u1, + /// Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_3EF: u1, + /// Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_4EF: u1, + /// Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_5EF: u1, + /// Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_6EF: u1, + /// Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_7EF: u1, + /// Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_8EF: u1, + /// Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = + /// Enable falling edge interrupt. + P2_9EF: u1, + /// Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_10EF: u1, + /// Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_11EF: u1, + /// Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_12EF: u1, + /// Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 + /// = Enable falling edge interrupt. + P2_13EF: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x34); + }; + /// Pin connect block + pub const PINCONNECT = struct { + pub const base_address = 0x4002c000; + + /// address: 0x4002c000 + /// Pin function select register 0. + pub const PINSEL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P0.0. + P0_0: u2, + /// Pin function select P0.1. + P0_1: u2, + /// Pin function select P0.2. + P0_2: u2, + /// Pin function select P0.3. + P0_3: u2, + /// Pin function select P0.4. + P0_4: u2, + /// Pin function select P0.5. + P0_5: u2, + /// Pin function select P0.6. + P0_6: u2, + /// Pin function select P0.7. + P0_7: u2, + /// Pin function select P0.8. + P0_8: u2, + /// Pin function select P0.9. + P0_9: u2, + /// Pin function select P0.10. + P0_10: u2, + /// Pin function select P0.11. + P0_11: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P0.15. + P0_15: u2, + }), base_address + 0x0); + + /// address: 0x4002c004 + /// Pin function select register 1. + pub const PINSEL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P0.16. + P0_16: u2, + /// Pin function select P0.17. + P0_17: u2, + /// Pin function select P0.18. + P0_18: u2, + /// Pin function select P019. + P0_19: u2, + /// Pin function select P0.20. + P0_20: u2, + /// Pin function select P0.21. + P0_21: u2, + /// Pin function select P022 + P0_22: u2, + /// Pin function select P023. + P0_23: u2, + /// Pin function select P0.24. + P0_24: u2, + /// Pin function select P0.25. + P0_25: u2, + /// Pin function select P0.26. + P0_26: u2, + /// Pin function select P0.27. + P0_27: u2, + /// Pin function select P0.28. + P0_28: u2, + /// Pin function select P0.29 + P0_29: u2, + /// Pin function select P0.30. + P0_30: u2, + /// Reserved + RESERVED: u2, + }), base_address + 0x4); + + /// address: 0x4002c008 + /// Pin function select register 2. + pub const PINSEL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P1.0. + P1_0: u2, + /// Pin function select P1.1. + P1_1: u2, + /// Reserved. + RESERVED: u4, + /// Pin function select P1.4. + P1_4: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P1.8. + P1_8: u2, + /// Pin function select P1.9. + P1_9: u2, + /// Pin function select P1.10. + P1_10: u2, + /// Pin function select P1.14. + P1_14: u2, + /// Reserved. + RESERVED: u6, + /// Pin function select P1.15. + P1_15: u2, + }), base_address + 0x8); + + /// address: 0x4002c00c + /// Pin function select register 3. + pub const PINSEL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P1.16. + P1_16: u2, + /// Pin function select P1.17. + P1_17: u2, + /// Pin function select P1.18. + P1_18: u2, + /// Pin function select P1.19. + P1_19: u2, + /// Pin function select P1.20. + P1_20: u2, + /// Pin function select P1.21. + P1_21: u2, + /// Pin function select P1.22 + P1_22: u2, + /// Pin function select P1.23. + P1_23: u2, + /// Pin function select P1.24. + P1_24: u2, + /// Pin function select P1.25. + P1_25: u2, + /// Pin function select P1.26. + P1_26: u2, + /// Pin function select P1.27. + P1_27: u2, + /// Pin function select P1.28. + P1_28: u2, + /// Pin function select P1.29 + P1_29: u2, + /// Pin function select P1.30. + P1_30: u2, + /// Pin function select P1.31. + P1_31: u2, + }), base_address + 0xc); + + /// address: 0x4002c010 + /// Pin function select register 4 + pub const PINSEL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pin function select P2.0. + P2_0: u2, + /// Pin function select P2.1. + P2_1: u2, + /// Pin function select P2.2. + P2_2: u2, + /// Pin function select P2.3. + P2_3: u2, + /// Pin function select P2.4. + P2_4: u2, + /// Pin function select P2.5. + P2_5: u2, + /// Pin function select P2.6. + P2_6: u2, + /// Pin function select P2.7. + P2_7: u2, + /// Pin function select P2.8. + P2_8: u2, + /// Pin function select P2.9. + P2_9: u2, + /// Pin function select P2.10. + P2_10: u2, + /// Pin function select P2.11. + P2_11: u2, + /// Pin function select P2.12. + P2_12: u2, + /// Pin function select P2.13. + P2_13: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x10); + + /// address: 0x4002c01c + /// Pin function select register 7 + pub const PINSEL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u18, + /// Pin function select P3.25. + P3_25: u2, + /// Pin function select P3.26. + P3_26: u2, + /// Reserved. + RESERVED: u10, + }), base_address + 0x1c); + + /// address: 0x4002c024 + /// Pin function select register 9 + pub const PINSEL9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u24, + /// Pin function select P4.28. + P4_28: u2, + /// Pin function select P4.29. + P4_29: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x24); + + /// address: 0x4002c028 + /// Pin function select register 10 + pub const PINSEL10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Software should not write 1 to these bits. + RESERVED: u3, + /// TPIU interface pins control. + TPIUCTRL: u1, + /// Reserved. Software should not write 1 to these bits. + RESERVED: u28, + }), base_address + 0x28); + + /// address: 0x4002c040 + /// Pin mode select register 0 + pub const PINMODE0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 pin 0 on-chip pull-up/down resistor control. + P0_00MODE: u2, + /// Port 0 pin 1 control. + P0_01MODE: u2, + /// Port 0 pin 2 control. + P0_02MODE: u2, + /// Port 0 pin 3 control. + P0_03MODE: u2, + /// Port 0 pin 4 control. + P0_04MODE: u2, + /// Port 0 pin 5 control. + P0_05MODE: u2, + /// Port 0 pin 6 control. + P0_06MODE: u2, + /// Port 0 pin 7 control. + P0_07MODE: u2, + /// Port 0 pin 8 control. + P0_08MODE: u2, + /// Port 0 pin 9 control. + P0_09MODE: u2, + /// Port 0 pin 10 control. + P0_10MODE: u2, + /// Port 0 pin 11 control. + P0_11MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 0 pin 15 control. + P0_15MODE: u2, + }), base_address + 0x40); + + /// address: 0x4002c044 + /// Pin mode select register 1 + pub const PINMODE1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 16 control. + P0_16MODE: u2, + /// Port 1 pin 17 control. + P0_17MODE: u2, + /// Port 1 pin 18 control. + P0_18MODE: u2, + /// Port 1 pin 19 control. + P0_19MODE: u2, + /// Port 1 pin 20 control. + P0_20MODE: u2, + /// Port 1 pin 21 control. + P0_21MODE: u2, + /// Port 1 pin 22 control. + P0_22MODE: u2, + /// Port 1 pin 23 control. + P0_23MODE: u2, + /// Port 1 pin 24 control. + P0_24MODE: u2, + /// Port 1 pin 25 control. + P0_25MODE: u2, + /// Port 1 pin 26 control. + P0_26MODE: u2, + /// Reserved. + RESERVED: u8, + /// Reserved. + RESERVED: u2, + }), base_address + 0x44); + + /// address: 0x4002c048 + /// Pin mode select register 2 + pub const PINMODE2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 0 control. + P1_00MODE: u2, + /// Port 1 pin 1 control. + P1_01MODE: u2, + /// Reserved. + RESERVED: u4, + /// Port 1 pin 4 control. + P1_04MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 1 pin 8 control. + P1_08MODE: u2, + /// Port 1 pin 9 control. + P1_09MODE: u2, + /// Port 1 pin 10 control. + P1_10MODE: u2, + /// Reserved. + RESERVED: u6, + /// Port 1 pin 14 control. + P1_14MODE: u2, + /// Port 1 pin 15 control. + P1_15MODE: u2, + }), base_address + 0x48); + + /// address: 0x4002c04c + /// Pin mode select register 3. + pub const PINMODE3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 16 control. + P1_16MODE: u2, + /// Port 1 pin 17 control. + P1_17MODE: u2, + /// Port 1 pin 18 control. + P1_18MODE: u2, + /// Port 1 pin 19 control. + P1_19MODE: u2, + /// Port 1 pin 20 control. + P1_20MODE: u2, + /// Port 1 pin 21 control. + P1_21MODE: u2, + /// Port 1 pin 22 control. + P1_22MODE: u2, + /// Port 1 pin 23 control. + P1_23MODE: u2, + /// Port 1 pin 24 control. + P1_24MODE: u2, + /// Port 1 pin 25 control. + P1_25MODE: u2, + /// Port 1 pin 26 control. + P1_26MODE: u2, + /// Port 1 pin 27 control. + P1_27MODE: u2, + /// Port 1 pin 28 control. + P1_28MODE: u2, + /// Port 1 pin 29 control. + P1_29MODE: u2, + /// Port 1 pin 30 control. + P1_30MODE: u2, + /// Port 1 pin 31 control. + P1_31MODE: u2, + }), base_address + 0x4c); + + /// address: 0x4002c050 + /// Pin mode select register 4 + pub const PINMODE4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 2 pin 0 control. + P2_00MODE: u2, + /// Port 2 pin 1 control. + P2_01MODE: u2, + /// Port 2 pin 2 control. + P2_02MODE: u2, + /// Port 2 pin 3 control. + P2_03MODE: u2, + /// Port 2 pin 4 control. + P2_04MODE: u2, + /// Port 2 pin 5 control. + P2_05MODE: u2, + /// Port 2 pin 6 control. + P2_06MODE: u2, + /// Port 2 pin 7 control. + P2_07MODE: u2, + /// Port 2 pin 8 control. + P2_08MODE: u2, + /// Port 2 pin 9 control. + P2_09MODE: u2, + /// Port 2 pin 10 control. + P2_10MODE: u2, + /// Port 2 pin 11 control. + P2_11MODE: u2, + /// Port 2 pin 12 control. + P2_12MODE: u2, + /// Port 2 pin 13 control. + P2_13MODE: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x50); + + /// address: 0x4002c05c + /// Pin mode select register 7 + pub const PINMODE7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved + RESERVED: u18, + /// Port 3 pin 25 control. + P3_25MODE: u2, + /// Port 3 pin 26 control. + P3_26MODE: u2, + /// Reserved. + RESERVED: u10, + }), base_address + 0x5c); + + /// address: 0x4002c064 + /// Pin mode select register 9 + pub const PINMODE9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u24, + /// Port 4 pin 28 control. + P4_28MODE: u2, + /// Port 4 pin 29 control. + P4_29MODE: u2, + /// Reserved. + RESERVED: u4, + }), base_address + 0x64); + + /// address: 0x4002c068 + /// Open drain mode control register 0 + pub const PINMODE_OD0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_00OD: u1, + /// Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_01OD: u1, + /// Port 0 pin 2 open drain mode control + P0_02OD: u1, + /// Port 0 pin 3 open drain mode control + P0_03OD: u1, + /// Port 0 pin 4 open drain mode control + P0_04OD: u1, + /// Port 0 pin 5 open drain mode control + P0_05OD: u1, + /// Port 0 pin 6 open drain mode control + P0_06OD: u1, + /// Port 0 pin 7 open drain mode control + P0_07OD: u1, + /// Port 0 pin 8 open drain mode control + P0_08OD: u1, + /// Port 0 pin 9 open drain mode control + P0_09OD: u1, + /// Port 0 pin 10 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_10OD: u1, + /// Port 0 pin 11 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_11OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 0 pin 15 open drain mode control + P0_15OD: u1, + /// Port 0 pin 16 open drain mode control + P0_16OD: u1, + /// Port 0 pin 17 open drain mode control + P0_17OD: u1, + /// Port 0 pin 18 open drain mode control + P0_18OD: u1, + /// Port 0 pin 19 open drain mode control. Pins may potentially be used for + /// I2C-buses using standard port pins. If so, they should be configured for open + /// drain mode via the related bits in PINMODE_OD0. + P0_19OD: u1, + /// Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses + /// using standard port pins. If so, they should be configured for open drain mode + /// via the related bits in PINMODE_OD0. + P0_20OD: u1, + /// Port 0 pin 21 open drain mode control + P0_21OD: u1, + /// Port 0 pin 22 open drain mode control + P0_22OD: u1, + /// Port 0 pin 23 open drain mode control + P0_23OD: u1, + /// Port 0 pin 24open drain mode control + P0_24OD: u1, + /// Port 0 pin 25 open drain mode control + P0_25OD: u1, + /// Port 0 pin 26 open drain mode control + P0_26OD: u1, + /// Reserved. + RESERVED: u2, + /// Port 0 pin 29 open drain mode control + P0_29OD: u1, + /// Port 0 pin 30 open drain mode control + P0_30OD: u1, + /// Reserved. + RESERVED: u1, + }), base_address + 0x68); + + /// address: 0x4002c06c + /// Open drain mode control register 1 + pub const PINMODE_OD1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 1 pin 0 open drain mode control. + P1_00OD: u1, + /// Port 1 pin 1 open drain mode control, see P1.00OD + P1_01OD: u1, + /// Reserved. + RESERVED: u2, + /// Port 1 pin 4 open drain mode control, see P1.00OD + P1_04OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 1 pin 8 open drain mode control, see P1.00OD + P1_08OD: u1, + /// Port 1 pin 9 open drain mode control, see P1.00OD + P1_09OD: u1, + /// Port 1 pin 10 open drain mode control, see P1.00OD + P1_10OD: u1, + /// Reserved. + RESERVED: u3, + /// Port 1 pin 14 open drain mode control, see P1.00OD + P1_14OD: u1, + /// Port 1 pin 15 open drain mode control, see P1.00OD + P1_15OD: u1, + /// Port 1 pin 16 open drain mode control, see P1.00OD + P1_16OD: u1, + /// Port 1 pin 17 open drain mode control, see P1.00OD + P1_17OD: u1, + /// Port 1 pin 18 open drain mode control, see P1.00OD + P1_18OD: u1, + /// Port 1 pin 19 open drain mode control, see P1.00OD + P1_19OD: u1, + /// Port 1 pin 20open drain mode control, see P1.00OD + P1_20OD: u1, + /// Port 1 pin 21 open drain mode control, see P1.00OD + P1_21OD: u1, + /// Port 1 pin 22 open drain mode control, see P1.00OD + P1_22OD: u1, + /// Port 1 pin 23 open drain mode control, see P1.00OD + P1_23OD: u1, + /// Port 1 pin 24open drain mode control, see P1.00OD + P1_24OD: u1, + /// Port 1 pin 25 open drain mode control, see P1.00OD + P1_25OD: u1, + /// Port 1 pin 26 open drain mode control, see P1.00OD + P1_26OD: u1, + /// Port 1 pin 27 open drain mode control, see P1.00OD + P1_27OD: u1, + /// Port 1 pin 28 open drain mode control, see P1.00OD + P1_28OD: u1, + /// Port 1 pin 29 open drain mode control, see P1.00OD + P1_29OD: u1, + /// Port 1 pin 30 open drain mode control, see P1.00OD + P1_30OD: u1, + /// Port 1 pin 31 open drain mode control. + P1_31OD: u1, + }), base_address + 0x6c); + + /// address: 0x4002c070 + /// Open drain mode control register 2 + pub const PINMODE_OD2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 2 pin 0 open drain mode control. + P2_00OD: u1, + /// Port 2 pin 1 open drain mode control, see P2.00OD + P2_01OD: u1, + /// Port 2 pin 2 open drain mode control, see P2.00OD + P2_02OD: u1, + /// Port 2 pin 3 open drain mode control, see P2.00OD + P2_03OD: u1, + /// Port 2 pin 4 open drain mode control, see P2.00OD + P2_04OD: u1, + /// Port 2 pin 5 open drain mode control, see P2.00OD + P2_05OD: u1, + /// Port 2 pin 6 open drain mode control, see P2.00OD + P2_06OD: u1, + /// Port 2 pin 7 open drain mode control, see P2.00OD + P2_07OD: u1, + /// Port 2 pin 8 open drain mode control, see P2.00OD + P2_08OD: u1, + /// Port 2 pin 9 open drain mode control, see P2.00OD + P2_09OD: u1, + /// Port 2 pin 10 open drain mode control, see P2.00OD + P2_10OD: u1, + /// Port 2 pin 11 open drain mode control, see P2.00OD + P2_11OD: u1, + /// Port 2 pin 12 open drain mode control, see P2.00OD + P2_12OD: u1, + /// Port 2 pin 13 open drain mode control, see P2.00OD + P2_13OD: u1, + /// Reserved. + RESERVED: u18, + }), base_address + 0x70); + + /// address: 0x4002c074 + /// Open drain mode control register 3 + pub const PINMODE_OD3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u25, + /// Port 3 pin 25 open drain mode control. + P3_25OD: u1, + /// Port 3 pin 26 open drain mode control, see P3.25OD + P3_26OD: u1, + /// Reserved. + RESERVED: u5, + }), base_address + 0x74); + + /// address: 0x4002c078 + /// Open drain mode control register 4 + pub const PINMODE_OD4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + RESERVED: u28, + /// Port 4 pin 28 open drain mode control. + P4_28OD: u1, + /// Port 4 pin 29 open drain mode control, see P4.28OD + P4_29OD: u1, + /// Reserved. + RESERVED: u2, + }), base_address + 0x78); + + /// address: 0x4002c07c + /// I2C Pin Configuration register + pub const I2CPADCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Drive mode control for the SDA0 pin, P0.27. + SDADRV0: u1, + /// I 2C filter mode control for the SDA0 pin, P0.27. + SDAI2C0: u1, + /// Drive mode control for the SCL0 pin, P0.28. + SCLDRV0: u1, + /// I 2C filter mode control for the SCL0 pin, P0.28. + SCLI2C0: u1, + /// Reserved. + RESERVED: u28, + }), base_address + 0x7c); + }; + /// SSP1 controller + pub const SSP1 = struct { + pub const base_address = 0x40030000; + + /// address: 0x40030000 + /// Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select. This field controls the number of bits transferred in each + /// frame. Values 0000-0010 are not supported and should not be used. + DSS: u4, + /// Frame Format. + FRF: u2, + /// Clock Out Polarity. This bit is only used in SPI mode. + CPOL: u1, + /// Clock Out Phase. This bit is only used in SPI mode. + CPHA: u1, + /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, + /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK + /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + SCR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x40030004 + /// Control Register 1. Selects master/slave and other modes. + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop Back Mode. + LBM: u1, + /// SSP Enable. + SSE: u1, + /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. + MS: u1, + /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is + /// 1, this blocks this SSP controller from driving the transmit data line (MISO). + SOD: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x40030008 + /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write: software can write data to be sent in a future frame to this register + /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is + /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy + /// on the bus, transmission of the data will begin immediately. Otherwise the data + /// written to this register will be sent as soon as all previous data has been sent + /// (and received). If the data length is less than 16 bits, software must + /// right-justify the data written to this register. Read: software can read data + /// from this register whenever the RNE bit in the Status register is 1, indicating + /// that the Rx FIFO is not empty. When software reads this register, the SSP + /// controller returns data from the least recent frame in the Rx FIFO. If the data + /// length is less than 16 bits, the data is right-justified in this field with + /// higher order bits filled with 0s. + DATA: u16, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4003000c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TFE: u1, + /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + TNF: u1, + /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RNE: u1, + /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + RFF: u1, + /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently + /// sending/receiving a frame and/or the Tx FIFO is not empty. + BSY: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xc); + + /// address: 0x40030010 + /// Clock Prescale Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// This even value between 2 and 254, by which PCLK is divided to yield the + /// prescaler output clock. Bit 0 always reads as 0. + CPSDVSR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40030014 + /// Interrupt Mask Set and Clear Register + pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Software should set this bit to enable interrupt when a Receive Overrun occurs, + /// that is, when the Rx FIFO is full and another frame is completely received. The + /// ARM spec implies that the preceding frame data is overwritten by the new frame + /// data when this occurs. + RORIM: u1, + /// Software should set this bit to enable interrupt when a Receive Time-out + /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and + /// no has not been read for a time-out period. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTIM: u1, + /// Software should set this bit to enable interrupt when the Rx FIFO is at least + /// half full. + RXIM: u1, + /// Software should set this bit to enable interrupt when the Tx FIFO is at least + /// half empty. + TXIM: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14); + + /// address: 0x40030018 + /// Raw Interrupt Status Register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full. The ARM spec implies that the preceding frame data is overwritten by the + /// new frame data when this occurs. + RORRIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out + /// period. The time-out period is the same for master and slave modes and is + /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RTRIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full. + RXRIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty. + TXRIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x18); + + /// address: 0x4003001c + /// Masked Interrupt Status Register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full, and this interrupt is enabled. + RORMIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out + /// period, and this interrupt is enabled. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTMIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is + /// enabled. + RXMIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is + /// enabled. + TXMIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x1c); + + /// address: 0x40030020 + /// SSPICR Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the frame was received when RxFIFO was full + /// interrupt. + RORIC: u1, + /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read + /// for a time-out period interrupt. The time-out period is the same for master and + /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / + /// [SCR+1]). + RTIC: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x20); + + /// address: 0x40030024 + /// SSP0 DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is + /// enabled, otherwise receive DMA is disabled. + RXDMAE: u1, + /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is + /// enabled, otherwise transmit DMA is disabled + TXDMAE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x24); + }; + /// Analog-to-Digital Converter (ADC) + pub const ADC = struct { + pub const base_address = 0x40034000; + + /// address: 0x40034000 + /// A/D Control Register. The ADCR register must be written to select the operating + /// mode before A/D conversion can occur. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For + /// AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In + /// software-controlled mode, only one of these bits should be 1. In hardware scan + /// mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to + /// 0x01. + SEL: u8, + /// The APB clock (PCLK) is divided by (this value plus one) to produce the clock + /// for the A/D converter, which should be less than or equal to 12.4 MHz. + /// Typically, software should program the smallest value in this field that yields + /// a clock of 12.4 MHz or slightly less, but in certain cases (such as a + /// high-impedance analog source) a slower clock may be desirable. + CLKDIV: u8, + /// Burst mode + BURST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Power down mode + PDN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// When the BURST bit is 0, these bits control whether and when an A/D conversion + /// is started: + START: u3, + /// This bit is significant only when the START field contains 010-111. In these + /// cases: + EDGE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + }), base_address + 0x0); + + /// address: 0x40034004 + /// A/D Global Data Register. This register contains the ADC's DONE bit and the + /// result of the most recent A/D conversion. + pub const GDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// When DONE is 1, this field contains a binary fraction representing the voltage + /// on the AD0[n] pin selected by the SEL field, as it falls within the range of + /// VREFP to VSS. Zero in the field indicates that the voltage on the input pin was + /// less than, equal to, or close to that on VSS, while 0xFFF indicates that the + /// voltage on the input was close to, equal to, or greater than that on VREFP. + RESULT: u12, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// These bits contain the channel from which the RESULT bits were converted (e.g. + /// 000 identifies channel 0, 001 channel 1...). + CHN: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u3, + /// This bit is 1 in burst mode if the results of one or more conversions was (were) + /// lost and overwritten before the conversion that produced the result in the + /// RESULT bits. This bit is cleared by reading this register. + OVERRUN: u1, + /// This bit is set to 1 when an A/D conversion completes. It is cleared when this + /// register is read and when the ADCR is written. If the ADCR is written while a + /// conversion is still in progress, this bit is set and a new conversion is + /// started. + DONE: u1, + }), base_address + 0x4); + + /// address: 0x4003400c + /// A/D Interrupt Enable Register. This register contains enable bits that allow the + /// DONE flag of each A/D channel to be included or excluded from contributing to + /// the generation of an A/D interrupt. + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt enable + ADINTEN0: u1, + /// Interrupt enable + ADINTEN1: u1, + /// Interrupt enable + ADINTEN2: u1, + /// Interrupt enable + ADINTEN3: u1, + /// Interrupt enable + ADINTEN4: u1, + /// Interrupt enable + ADINTEN5: u1, + /// Interrupt enable + ADINTEN6: u1, + /// Interrupt enable + ADINTEN7: u1, + /// Interrupt enable + ADGINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u23, + }), base_address + 0xc); + + /// address: 0x40034010 + /// A/D Channel 0 Data Register. This register contains the result of the most + /// recent conversion completed on channel 0. + pub const DR = @intToPtr(*volatile [8]Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// When DONE is 1, this field contains a binary fraction representing the voltage + /// on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the + /// field indicates that the voltage on the input pin was less than, equal to, or + /// close to that on VSS, while 0xFFF indicates that the voltage on the input was + /// close to, equal to, or greater than that on VREFP. + RESULT: u12, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u14, + /// This bit is 1 in burst mode if the results of one or more conversions was (were) + /// lost and overwritten before the conversion that produced the result in the + /// RESULT bits.This bit is cleared by reading this register. + OVERRUN: u1, + /// This bit is set to 1 when an A/D conversion completes. It is cleared when this + /// register is read. + DONE: u1, + }), base_address + 0x10); + + /// address: 0x40034030 + /// A/D Status Register. This register contains DONE and OVERRUN flags for all of + /// the A/D channels, as well as the A/D interrupt/DMA flag. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 0. + DONE0: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 1. + DONE1: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 2. + DONE2: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 3. + DONE3: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 4. + DONE4: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 5. + DONE5: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 6. + DONE6: u1, + /// This bit mirrors the DONE status flag from the result register for A/D channel + /// 7. + DONE7: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 0. + OVERRUN0: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 1. + OVERRUN1: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 2. + OVERRUN2: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 3. + OVERRUN3: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 4. + OVERRUN4: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 5. + OVERRUN5: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 6. + OVERRUN6: u1, + /// This bit mirrors the OVERRRUN status flag from the result register for A/D + /// channel 7. + OVERRUN7: u1, + /// This bit is the A/D interrupt flag. It is one when any of the individual A/D + /// channel Done flags is asserted and enabled to contribute to the A/D interrupt + /// via the ADINTEN register. + ADINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u15, + }), base_address + 0x30); + + /// address: 0x40034034 + /// ADC trim register. + pub const TRM = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// Offset trim bits for ADC operation. Initialized by the boot code. Can be + /// overwritten by the user. + ADCOFFS: u4, + /// written-to by boot code. Can not be overwritten by the user. These bits are + /// locked after boot code write. + TRIM: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x34); + }; + /// CAN acceptance filter RAM + pub const CANAFRAM = struct { + pub const base_address = 0x40038000; + + /// address: 0x40038000 + /// CAN AF ram access register + pub const MASK = @intToPtr(*volatile [512]u32, base_address + 0x0); + }; + /// CAN controller acceptance filter + pub const CANAF = struct { + pub const base_address = 0x4003c000; + + /// address: 0x4003c000 + /// Acceptance Filter Register + pub const AFMR = @intToPtr(*volatile Mmio(32, packed struct { + /// if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all + /// CAN buses are ignored. + ACCOFF: u1, + /// All Rx messages are accepted on enabled CAN controllers. Software must set this + /// bit before modifying the contents of any of the registers described below, and + /// before modifying the contents of Lookup Table RAM in any way other than setting + /// or clearing Disable bits in Standard Identifier entries. When both this bit and + /// AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. + ACCBP: u1, + /// FullCAN mode + EFCAN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x0); + + /// address: 0x4003c004 + /// Standard Frame Individual Start Address Register + pub const SFF_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of individual Standard Identifiers in AF Lookup + /// RAM. If the table is empty, write the same value in this register and the + /// SFF_GRP_sa register described below. For compatibility with possible future + /// devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit + /// in the AFMR is 1, this value also indicates the size of the table of Standard + /// IDs which the Acceptance Filter will search and (if found) automatically store + /// received messages in Acceptance Filter RAM. + SFF_SA: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x4); + + /// address: 0x4003c008 + /// Standard Frame Group Start Address Register + pub const SFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of grouped Standard Identifiers in AF Lookup RAM. + /// If the table is empty, write the same value in this register and the EFF_sa + /// register described below. The largest value that should be written to this + /// register is 0x800, when only the Standard Individual table is used, and the last + /// word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with + /// possible future devices, please write zeroes in bits 31:12 and 1:0 of this + /// register. + SFF_GRP_SA: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x8); + + /// address: 0x4003c00c + /// Extended Frame Start Address Register + pub const EFF_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of individual Extended Identifiers in AF Lookup + /// RAM. If the table is empty, write the same value in this register and the + /// EFF_GRP_sa register described below. The largest value that should be written to + /// this register is 0x800, when both Extended Tables are empty and the last word + /// (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible + /// future devices, please write zeroes in bits 31:11 and 1:0 of this register. + EFF_SA: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0xc); + + /// address: 0x4003c010 + /// Extended Frame Group Start Address Register + pub const EFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The start address of the table of grouped Extended Identifiers in AF Lookup RAM. + /// If the table is empty, write the same value in this register and the ENDofTable + /// register described below. The largest value that should be written to this + /// register is 0x800, when this table is empty and the last word (address 0x7FC) in + /// AF Lookup Table RAM is used. For compatibility with possible future devices, + /// please write zeroes in bits 31:12 and 1:0 of this register. + EFF_GRP_SA: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x10); + + /// address: 0x4003c014 + /// End of AF Tables register + pub const ENDOFTABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// The address above the last active address in the last active AF table. For + /// compatibility with possible future devices, please write zeroes in bits 31:12 + /// and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value + /// that should be written to this register is 0x800, which allows the last word + /// (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR + /// is 1, this value marks the start of the area of Acceptance Filter RAM, into + /// which the Acceptance Filter will automatically receive messages for selected IDs + /// on selected CAN buses. In this case, the maximum value that should be written to + /// this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes + /// of message storage between this address and the end of Acceptance Filter RAM, + /// for each Standard ID that is specified between the start of Acceptance Filter + /// RAM, and the next active AF table. + ENDOFTABLE: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x4003c018 + /// LUT Error Address register + pub const LUTERRAD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// It the LUT Error bit (below) is 1, this read-only field contains the address in + /// AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the + /// content of the tables. + LUTERRAD: u9, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x18); + + /// address: 0x4003c01c + /// LUT Error Register + pub const LUTERR = @intToPtr(*volatile Mmio(32, packed struct { + /// This read-only bit is set to 1 if the Acceptance Filter encounters an error in + /// the content of the tables in AF RAM. It is cleared when software reads the + /// LUTerrAd register. This condition is ORed with the other CAN interrupts from the + /// CAN controllers, to produce the request that is connected to the NVIC. + LUTERR: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u31, + }), base_address + 0x1c); + + /// address: 0x4003c020 + /// FullCAN interrupt enable register + pub const FCANIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. + FCANIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u31, + }), base_address + 0x20); + + /// address: 0x4003c024 + /// FullCAN interrupt and capture register0 + pub const FCANIC0 = @intToPtr(*volatile Mmio(32, packed struct { + /// FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan + /// Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. + INTPND: u32, + }), base_address + 0x24); + + /// address: 0x4003c028 + /// FullCAN interrupt and capture register1 + pub const FCANIC1 = @intToPtr(*volatile Mmio(32, packed struct { + /// FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = + /// FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. + IntPnd32: u32, + }), base_address + 0x28); + }; + /// Central CAN controller + pub const CCAN = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// CAN Central Transmit Status Register + pub const TXSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). + TS1: u1, + /// When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) + TS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same + /// as TBS in CAN1GSR). + TBS1: u1, + /// When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same + /// as TBS in CAN2GSR). + TBS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, all requested transmissions have been completed successfully by the CAN1 + /// controller (same as TCS in CAN1GSR). + TCS1: u1, + /// When 1, all requested transmissions have been completed successfully by the CAN2 + /// controller (same as TCS in CAN2GSR). + TCS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u14, + }), base_address + 0x0); + + /// address: 0x40040004 + /// CAN Central Receive Status Register + pub const RXSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, CAN1 is receiving a message (same as RS in CAN1GSR). + RS1: u1, + /// When 1, CAN2 is receiving a message (same as RS in CAN2GSR). + RS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, a received message is available in the CAN1 controller (same as RBS in + /// CAN1GSR). + RB1: u1, + /// When 1, a received message is available in the CAN2 controller (same as RBS in + /// CAN2GSR). + RB2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, a message was lost because the preceding message to CAN1 controller was + /// not read out quickly enough (same as DOS in CAN1GSR). + DOS1: u1, + /// When 1, a message was lost because the preceding message to CAN2 controller was + /// not read out quickly enough (same as DOS in CAN2GSR). + DOS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u14, + }), base_address + 0x4); + + /// address: 0x40040008 + /// CAN Central Miscellaneous Register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit + /// set in the CAN1EWL register (same as ES in CAN1GSR) + E1: u1, + /// When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit + /// set in the CAN2EWL register (same as ES in CAN2GSR) + E2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u6, + /// When 1, the CAN1 controller is currently involved in bus activities (same as BS + /// in CAN1GSR). + BS1: u1, + /// When 1, the CAN2 controller is currently involved in bus activities (same as BS + /// in CAN2GSR). + BS2: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x8); + }; + /// CAN1 controller + pub const CAN1 = struct { + pub const base_address = 0x40044000; + + /// address: 0x40044000 + /// Controls the operating mode of the CAN Controller. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset Mode. + RM: u1, + /// Listen Only Mode. + LOM: u1, + /// Self Test Mode. + STM: u1, + /// Transmit Priority Mode. + TPM: u1, + /// Sleep Mode. + SM: u1, + /// Receive Polarity Mode. + RPM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Test Mode. + TM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40044004 + /// Command bits that affect the state of the CAN Controller + pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request. + TR: u1, + /// Abort Transmission. + AT: u1, + /// Release Receive Buffer. + RRB: u1, + /// Clear Data Overrun. + CDO: u1, + /// Self Reception Request. + SRR: u1, + /// Select Tx Buffer 1. + STB1: u1, + /// Select Tx Buffer 2. + STB2: u1, + /// Select Tx Buffer 3. + STB3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40044008 + /// Global Controller Status and Error Counters. The error counters can only be + /// written when RM in CANMOD is 1. + pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. After reading all messages and releasing their memory + /// space with the command 'Release Receive Buffer,' this bit is cleared. + RBS: u1, + /// Data Overrun Status. If there is not enough space to store the message within + /// the Receive Buffer, that message is dropped and the Data Overrun condition is + /// signalled to the CPU in the moment this message becomes valid. If this message + /// is not completed successfully (e.g. because of an error), no overrun condition + /// is signalled. + DOS: u1, + /// Transmit Buffer Status. + TBS: u1, + /// Transmit Complete Status. The Transmission Complete Status bit is set '0' + /// (incomplete) whenever the Transmission Request bit or the Self Reception Request + /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission + /// Complete Status bit will remain '0' until all messages are transmitted + /// successfully. + TCS: u1, + /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + RS: u1, + /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + TS: u1, + /// Error Status. Errors detected during reception or transmission will effect the + /// error counters according to the CAN specification. The Error Status bit is set + /// when at least one of the error counters has reached or exceeded the Error + /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default + /// value of the Error Warning Limit after hardware reset is 96 decimal, see also + /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL + /// - 0x4004 8018). + ES: u1, + /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, + /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the + /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears + /// the Reset Mode bit. Once this is completed the CAN Controller will wait the + /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting + /// down the Transmit Error Counter. After that, the Bus Status bit is cleared + /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, + /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error + /// Counter during this time gives information about the status of the Bus-Off + /// recovery. + BS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The current value of the Rx Error Counter (an 8-bit value). + RXERR: u8, + /// The current value of the Tx Error Counter (an 8-bit value). + TXERR: u8, + }), base_address + 0x8); + + /// address: 0x4004400c + /// Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE + /// bit in CANxIER are both 1, indicating that a new message was received and stored + /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read + /// access to the Interrupt Register. Giving the Command Release Receive Buffer will + /// clear RI temporarily. If there is another message available within the Receive + /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. + RI: u1, + /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), + /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is + /// 1. + TI1: u1, + /// Error Warning Interrupt. This bit is set on every change (set or clear) of + /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set + /// within the Interrupt Enable Register at the time of the change. + EI: u1, + /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 + /// to 1 and the DOIE bit in CANxIER is 1. + DOI: u1, + /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus + /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is + /// also generated if the CPU tries to set the Sleep bit while the CAN controller is + /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also + /// get asserted when the according enable bit WUIE is not set. In this case a + /// Wake-Up Interrupt does not get asserted. + WUI: u1, + /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and + /// the CAN controller switches between Error Passive and Error Active mode in + /// either direction. This is the case when the CAN Controller has reached the Error + /// Passive Status (at least one error counter exceeds the CAN protocol defined + /// level of 127) or if the CAN Controller is in Error Passive Status and enters the + /// Error Active Status again. + EPI: u1, + /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and + /// the CAN controller loses arbitration while attempting to transmit. In this case + /// the CAN node becomes a receiver. + ALI: u1, + /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the + /// CAN controller detects an error on the bus. + BEI: u1, + /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN + /// Identifier has been received (a message was successfully transmitted or + /// aborted). This bit is set whenever a message was successfully transmitted or + /// aborted and the IDIE bit is set in the IER register. + IDI: u1, + /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), + /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is + /// 1. + TI2: u1, + /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), + /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is + /// 1. + TI3: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// Error Code Capture: when the CAN controller detects a bus error, the location of + /// the error within the frame is captured in this field. The value reflects an + /// internal state variable, and as a result is not very linear: 00011 = Start of + /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE + /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit + /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = + /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot + /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever + /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. + /// At the same time, the current position of the Bit Stream Processor is captured + /// into the Error Code Capture Register. The content within this register is fixed + /// until the user software has read out its content once. From now on, the capture + /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error + /// Interrupt. + ERRBIT4_0: u5, + /// When the CAN controller detects a bus error, the direction of the current bit is + /// captured in this bit. + ERRDIR: u1, + /// When the CAN controller detects a bus error, the type of error is captured in + /// this field: + ERRC1_0: u2, + /// Each time arbitration is lost while trying to send on the CAN, the bit number + /// within the frame is captured into this field. After the content of ALCBIT is + /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 + /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost + /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE + /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 + /// = arbitration lost in last bit of identifier (extended frame only) 31 = + /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the + /// corresponding arbitration lost interrupt is forced, if enabled. At that time, + /// the current bit position of the Bit Stream Processor is captured into the + /// Arbitration Lost Capture Register. The content within this register is fixed + /// until the user application has read out its contents once. From now on, the + /// capture mechanism is activated again. + ALCBIT: u8, + }), base_address + 0xc); + + /// address: 0x40044010 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN + /// Controller requests the respective interrupt. + RIE: u1, + /// Transmit Interrupt Enable for Buffer1. When a message has been successfully + /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE1: u1, + /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status + /// Register), the CAN Controller requests the respective interrupt. + EIE: u1, + /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status + /// Register), the CAN Controller requests the respective interrupt. + DOIE: u1, + /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the + /// respective interrupt is requested. + WUIE: u1, + /// Error Passive Interrupt Enable. If the error status of the CAN Controller + /// changes from error active to error passive or vice versa, the respective + /// interrupt is requested. + EPIE: u1, + /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, + /// the respective interrupt is requested. + ALIE: u1, + /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller + /// requests the respective interrupt. + BEIE: u1, + /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN + /// Controller requests the respective interrupt. + IDIE: u1, + /// Transmit Interrupt Enable for Buffer2. When a message has been successfully + /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE2: u1, + /// Transmit Interrupt Enable for Buffer3. When a message has been successfully + /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x10); + + /// address: 0x40044014 + /// Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to + /// produce the CAN clock. + BRP: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// The Synchronization Jump Width is (this value plus one) CAN clocks. + SJW: u2, + /// The delay from the nominal Sync point to the sample point is (this value plus + /// one) CAN clocks. + TESG1: u4, + /// The delay from the sample point to the next nominal sync point is (this value + /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in + /// TSEG1 plus 3) CAN clocks. + TESG2: u3, + /// Sampling + SAM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x14); + + /// address: 0x40044018 + /// Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { + /// During CAN operation, this value is compared to both the Tx and Rx Error + /// Counters. If either of these counter matches this value, the Error Status (ES) + /// bit in CANSR is set. + EWL: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4004401c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_1: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_1: u1, + /// Transmit Buffer Status 1. + TBS1_1: u1, + /// Transmission Complete Status. + TCS1_1: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_1: u1, + /// Transmit Status 1. + TS1_1: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_1: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_1: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_2: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_2: u1, + /// Transmit Buffer Status 2. + TBS2_2: u1, + /// Transmission Complete Status. + TCS2_2: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_2: u1, + /// Transmit Status 2. + TS2_2: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_2: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_2: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_3: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_3: u1, + /// Transmit Buffer Status 3. + TBS3_3: u1, + /// Transmission Complete Status. + TCS3_3: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_3: u1, + /// Transmit Status 3. + TS3_3: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_3: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_3: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u8, + }), base_address + 0x1c); + + /// address: 0x40044020 + /// Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { + /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the + /// Lookup Table RAM entry at which the Acceptance Filter matched the received + /// Identifier. Disabled entries in the Standard tables are included in this + /// numbering, but will not be matched. See Section 21.17 Examples of acceptance + /// filter tables and ID index values on page 587 for examples of ID Index values. + IDINDEX: u10, + /// If this bit is 1, the current message was received in AF Bypass mode, and the ID + /// Index field (above) is meaningless. + BP: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// The field contains the Data Length Code (DLC) field of the current received + /// message. When RTR = 0, this is related to the number of data bytes available in + /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = + /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to + /// be sent back, with the same encoding. + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This bit contains the Remote Transmission Request bit of the current received + /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be + /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote + /// frame, in which case the DLC value identifies the number of data bytes requested + /// to be sent using the same Identifier. + RTR: u1, + /// A 0 in this bit indicates that the current received message included an 11-bit + /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents + /// of the CANid register described below. + FF: u1, + }), base_address + 0x20); + + /// address: 0x40044024 + /// Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these + /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + ID: u11, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0x24); + + /// address: 0x40044028 + /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of + /// the current received message. + DATA1: u8, + /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of + /// the current received message. + DATA2: u8, + /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of + /// the current received message. + DATA3: u8, + /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of + /// the current received message. + DATA4: u8, + }), base_address + 0x28); + + /// address: 0x4004402c + /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of + /// the current received message. + DATA5: u8, + /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of + /// the current received message. + DATA6: u8, + /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of + /// the current received message. + DATA7: u8, + /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of + /// the current received message. + DATA8: u8, + }), base_address + 0x2c); + + /// address: 0x40044030 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x30); + + /// address: 0x40044040 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x40); + + /// address: 0x40044050 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x50); + + /// address: 0x40044034 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x34); + + /// address: 0x40044044 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x44); + + /// address: 0x40044054 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x54); + + /// address: 0x40044038 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x38); + + /// address: 0x40044048 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x48); + + /// address: 0x40044058 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x58); + + /// address: 0x4004403c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x3c); + + /// address: 0x4004404c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x4c); + + /// address: 0x4004405c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x5c); + }; + pub const CAN2 = struct { + pub const base_address = 0x40048000; + + /// address: 0x40048000 + /// Controls the operating mode of the CAN Controller. + pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset Mode. + RM: u1, + /// Listen Only Mode. + LOM: u1, + /// Self Test Mode. + STM: u1, + /// Transmit Priority Mode. + TPM: u1, + /// Sleep Mode. + SM: u1, + /// Receive Polarity Mode. + RPM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Test Mode. + TM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40048004 + /// Command bits that affect the state of the CAN Controller + pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request. + TR: u1, + /// Abort Transmission. + AT: u1, + /// Release Receive Buffer. + RRB: u1, + /// Clear Data Overrun. + CDO: u1, + /// Self Reception Request. + SRR: u1, + /// Select Tx Buffer 1. + STB1: u1, + /// Select Tx Buffer 2. + STB2: u1, + /// Select Tx Buffer 3. + STB3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40048008 + /// Global Controller Status and Error Counters. The error counters can only be + /// written when RM in CANMOD is 1. + pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. After reading all messages and releasing their memory + /// space with the command 'Release Receive Buffer,' this bit is cleared. + RBS: u1, + /// Data Overrun Status. If there is not enough space to store the message within + /// the Receive Buffer, that message is dropped and the Data Overrun condition is + /// signalled to the CPU in the moment this message becomes valid. If this message + /// is not completed successfully (e.g. because of an error), no overrun condition + /// is signalled. + DOS: u1, + /// Transmit Buffer Status. + TBS: u1, + /// Transmit Complete Status. The Transmission Complete Status bit is set '0' + /// (incomplete) whenever the Transmission Request bit or the Self Reception Request + /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission + /// Complete Status bit will remain '0' until all messages are transmitted + /// successfully. + TCS: u1, + /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + RS: u1, + /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' + /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to + /// become idle again. After hardware reset 11 consecutive recessive bits have to be + /// detected until idle status is reached. After Bus-off this will take 128 times of + /// 11 consecutive recessive bits. + TS: u1, + /// Error Status. Errors detected during reception or transmission will effect the + /// error counters according to the CAN specification. The Error Status bit is set + /// when at least one of the error counters has reached or exceeded the Error + /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default + /// value of the Error Warning Limit after hardware reset is 96 decimal, see also + /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL + /// - 0x4004 8018). + ES: u1, + /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, + /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the + /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears + /// the Reset Mode bit. Once this is completed the CAN Controller will wait the + /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting + /// down the Transmit Error Counter. After that, the Bus Status bit is cleared + /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, + /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error + /// Counter during this time gives information about the status of the Bus-Off + /// recovery. + BS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The current value of the Rx Error Counter (an 8-bit value). + RXERR: u8, + /// The current value of the Tx Error Counter (an 8-bit value). + TXERR: u8, + }), base_address + 0x8); + + /// address: 0x4004800c + /// Interrupt status, Arbitration Lost Capture, Error Code Capture + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE + /// bit in CANxIER are both 1, indicating that a new message was received and stored + /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read + /// access to the Interrupt Register. Giving the Command Release Receive Buffer will + /// clear RI temporarily. If there is another message available within the Receive + /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. + RI: u1, + /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), + /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is + /// 1. + TI1: u1, + /// Error Warning Interrupt. This bit is set on every change (set or clear) of + /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set + /// within the Interrupt Enable Register at the time of the change. + EI: u1, + /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 + /// to 1 and the DOIE bit in CANxIER is 1. + DOI: u1, + /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus + /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is + /// also generated if the CPU tries to set the Sleep bit while the CAN controller is + /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also + /// get asserted when the according enable bit WUIE is not set. In this case a + /// Wake-Up Interrupt does not get asserted. + WUI: u1, + /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and + /// the CAN controller switches between Error Passive and Error Active mode in + /// either direction. This is the case when the CAN Controller has reached the Error + /// Passive Status (at least one error counter exceeds the CAN protocol defined + /// level of 127) or if the CAN Controller is in Error Passive Status and enters the + /// Error Active Status again. + EPI: u1, + /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and + /// the CAN controller loses arbitration while attempting to transmit. In this case + /// the CAN node becomes a receiver. + ALI: u1, + /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the + /// CAN controller detects an error on the bus. + BEI: u1, + /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN + /// Identifier has been received (a message was successfully transmitted or + /// aborted). This bit is set whenever a message was successfully transmitted or + /// aborted and the IDIE bit is set in the IER register. + IDI: u1, + /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), + /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is + /// 1. + TI2: u1, + /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to + /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), + /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is + /// 1. + TI3: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// Error Code Capture: when the CAN controller detects a bus error, the location of + /// the error within the frame is captured in this field. The value reflects an + /// internal state variable, and as a result is not very linear: 00011 = Start of + /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE + /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit + /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = + /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot + /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever + /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. + /// At the same time, the current position of the Bit Stream Processor is captured + /// into the Error Code Capture Register. The content within this register is fixed + /// until the user software has read out its content once. From now on, the capture + /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error + /// Interrupt. + ERRBIT4_0: u5, + /// When the CAN controller detects a bus error, the direction of the current bit is + /// captured in this bit. + ERRDIR: u1, + /// When the CAN controller detects a bus error, the type of error is captured in + /// this field: + ERRC1_0: u2, + /// Each time arbitration is lost while trying to send on the CAN, the bit number + /// within the frame is captured into this field. After the content of ALCBIT is + /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 + /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost + /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE + /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 + /// = arbitration lost in last bit of identifier (extended frame only) 31 = + /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the + /// corresponding arbitration lost interrupt is forced, if enabled. At that time, + /// the current bit position of the Bit Stream Processor is captured into the + /// Arbitration Lost Capture Register. The content within this register is fixed + /// until the user application has read out its contents once. From now on, the + /// capture mechanism is activated again. + ALCBIT: u8, + }), base_address + 0xc); + + /// address: 0x40048010 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN + /// Controller requests the respective interrupt. + RIE: u1, + /// Transmit Interrupt Enable for Buffer1. When a message has been successfully + /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE1: u1, + /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status + /// Register), the CAN Controller requests the respective interrupt. + EIE: u1, + /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status + /// Register), the CAN Controller requests the respective interrupt. + DOIE: u1, + /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the + /// respective interrupt is requested. + WUIE: u1, + /// Error Passive Interrupt Enable. If the error status of the CAN Controller + /// changes from error active to error passive or vice versa, the respective + /// interrupt is requested. + EPIE: u1, + /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, + /// the respective interrupt is requested. + ALIE: u1, + /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller + /// requests the respective interrupt. + BEIE: u1, + /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN + /// Controller requests the respective interrupt. + IDIE: u1, + /// Transmit Interrupt Enable for Buffer2. When a message has been successfully + /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE2: u1, + /// Transmit Interrupt Enable for Buffer3. When a message has been successfully + /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an + /// Abort Transmission command), the CAN Controller requests the respective + /// interrupt. + TIE3: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x10); + + /// address: 0x40048014 + /// Bus Timing. Can only be written when RM in CANMOD is 1. + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to + /// produce the CAN clock. + BRP: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// The Synchronization Jump Width is (this value plus one) CAN clocks. + SJW: u2, + /// The delay from the nominal Sync point to the sample point is (this value plus + /// one) CAN clocks. + TESG1: u4, + /// The delay from the sample point to the next nominal sync point is (this value + /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in + /// TSEG1 plus 3) CAN clocks. + TESG2: u3, + /// Sampling + SAM: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x14); + + /// address: 0x40048018 + /// Error Warning Limit. Can only be written when RM in CANMOD is 1. + pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { + /// During CAN operation, this value is compared to both the Tx and Rx Error + /// Counters. If either of these counter matches this value, the Error Status (ES) + /// bit in CANSR is set. + EWL: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4004801c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_1: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_1: u1, + /// Transmit Buffer Status 1. + TBS1_1: u1, + /// Transmission Complete Status. + TCS1_1: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_1: u1, + /// Transmit Status 1. + TS1_1: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_1: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_1: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_2: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_2: u1, + /// Transmit Buffer Status 2. + TBS2_2: u1, + /// Transmission Complete Status. + TCS2_2: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_2: u1, + /// Transmit Status 2. + TS2_2: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_2: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_2: u1, + /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. + RBS_3: u1, + /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. + DOS_3: u1, + /// Transmit Buffer Status 3. + TBS3_3: u1, + /// Transmission Complete Status. + TCS3_3: u1, + /// Receive Status. This bit is identical to the RS bit in the GSR. + RS_3: u1, + /// Transmit Status 3. + TS3_3: u1, + /// Error Status. This bit is identical to the ES bit in the CANxGSR. + ES_3: u1, + /// Bus Status. This bit is identical to the BS bit in the CANxGSR. + BS_3: u1, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u8, + }), base_address + 0x1c); + + /// address: 0x40048020 + /// Receive frame status. Can only be written when RM in CANMOD is 1. + pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { + /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the + /// Lookup Table RAM entry at which the Acceptance Filter matched the received + /// Identifier. Disabled entries in the Standard tables are included in this + /// numbering, but will not be matched. See Section 21.17 Examples of acceptance + /// filter tables and ID index values on page 587 for examples of ID Index values. + IDINDEX: u10, + /// If this bit is 1, the current message was received in AF Bypass mode, and the ID + /// Index field (above) is meaningless. + BP: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u5, + /// The field contains the Data Length Code (DLC) field of the current received + /// message. When RTR = 0, this is related to the number of data bytes available in + /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = + /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to + /// be sent back, with the same encoding. + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This bit contains the Remote Transmission Request bit of the current received + /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be + /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote + /// frame, in which case the DLC value identifies the number of data bytes requested + /// to be sent using the same Identifier. + RTR: u1, + /// A 0 in this bit indicates that the current received message included an 11-bit + /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents + /// of the CANid register described below. + FF: u1, + }), base_address + 0x20); + + /// address: 0x40048024 + /// Received Identifier. Can only be written when RM in CANMOD is 1. + pub const RID = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these + /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. + ID: u11, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0x24); + + /// address: 0x40048028 + /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. + pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of + /// the current received message. + DATA1: u8, + /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of + /// the current received message. + DATA2: u8, + /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of + /// the current received message. + DATA3: u8, + /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of + /// the current received message. + DATA4: u8, + }), base_address + 0x28); + + /// address: 0x4004802c + /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. + pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of + /// the current received message. + DATA5: u8, + /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of + /// the current received message. + DATA6: u8, + /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of + /// the current received message. + DATA7: u8, + /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of + /// the current received message. + DATA8: u8, + }), base_address + 0x2c); + + /// address: 0x40048030 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x30); + + /// address: 0x40048040 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x40); + + /// address: 0x40048050 + /// Transmit + /// frame info (Tx Buffer ) + pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, + /// enabled Tx Buffers contend for the right to send their messages based on this + /// field. The buffer with the lowest TX Priority value wins the prioritization and + /// is sent first. + PRIO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// Data Length Code. This value is sent in the DLC field of the next transmit + /// message. In addition, if RTR = 0, this value controls the number of Data bytes + /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: + /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes + DLC: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u10, + /// This value is sent in the RTR bit of the next transmit message. If this bit is + /// 0, the number of data bytes called out by the DLC field are sent from the + /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, + /// containing a request for that number of bytes. + RTR: u1, + /// If this bit is 0, the next transmit message will be sent with an 11-bit + /// Identifier (standard frame format), while if it's 1, the message will be sent + /// with a 29-bit Identifier (extended frame format). + FF: u1, + }), base_address + 0x50); + + /// address: 0x40048034 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x34); + + /// address: 0x40048044 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x44); + + /// address: 0x40048054 + /// Transmit + /// Identifier (Tx Buffer) + pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// The 11-bit Identifier to be sent in the next transmit message. + ID: u11, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u21, + }), base_address + 0x54); + + /// address: 0x40048038 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x38); + + /// address: 0x40048048 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x48); + + /// address: 0x40048058 + /// Transmit + /// data bytes 1-4 (Tx Buffer) + pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is + /// sent as the first Data byte of the next transmit message. + DATA1: u8, + /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is + /// sent as the 2nd Data byte of the next transmit message. + DATA2: u8, + /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is + /// sent as the 3rd Data byte of the next transmit message. + DATA3: u8, + /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is + /// sent as the 4th Data byte of the next transmit message. + DATA4: u8, + }), base_address + 0x58); + + /// address: 0x4004803c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x3c); + + /// address: 0x4004804c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x4c); + + /// address: 0x4004805c + /// Transmit + /// data bytes 5-8 (Tx Buffer ) + pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is + /// sent as the 5th Data byte of the next transmit message. + DATA5: u8, + /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is + /// sent as the 6th Data byte of the next transmit message. + DATA6: u8, + /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is + /// sent as the 7th Data byte of the next transmit message. + DATA7: u8, + /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is + /// sent as the 8th Data byte of the next transmit message. + DATA8: u8, + }), base_address + 0x5c); + }; + pub const I2C1 = struct { + pub const base_address = 0x4005c000; + + /// address: 0x4005c000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x4005c004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4005c008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4005c00c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4005c010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x4005c014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x4005c018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x4005c01c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x4005c020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x4005c024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x4005c028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4005c02c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x4005c030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// SSP controller + pub const SSP0 = struct { + pub const base_address = 0x40088000; + + /// address: 0x40088000 + /// Control Register 0. Selects the serial clock rate, bus type, and data size. + pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select. This field controls the number of bits transferred in each + /// frame. Values 0000-0010 are not supported and should not be used. + DSS: u4, + /// Frame Format. + FRF: u2, + /// Clock Out Polarity. This bit is only used in SPI mode. + CPOL: u1, + /// Clock Out Phase. This bit is only used in SPI mode. + CPHA: u1, + /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, + /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK + /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + SCR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x40088004 + /// Control Register 1. Selects master/slave and other modes. + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop Back Mode. + LBM: u1, + /// SSP Enable. + SSE: u1, + /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. + MS: u1, + /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is + /// 1, this blocks this SSP controller from driving the transmit data line (MISO). + SOD: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x40088008 + /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write: software can write data to be sent in a future frame to this register + /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is + /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy + /// on the bus, transmission of the data will begin immediately. Otherwise the data + /// written to this register will be sent as soon as all previous data has been sent + /// (and received). If the data length is less than 16 bits, software must + /// right-justify the data written to this register. Read: software can read data + /// from this register whenever the RNE bit in the Status register is 1, indicating + /// that the Rx FIFO is not empty. When software reads this register, the SSP + /// controller returns data from the least recent frame in the Rx FIFO. If the data + /// length is less than 16 bits, the data is right-justified in this field with + /// higher order bits filled with 0s. + DATA: u16, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x8); + + /// address: 0x4008800c + /// Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + TFE: u1, + /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + TNF: u1, + /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + RNE: u1, + /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + RFF: u1, + /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently + /// sending/receiving a frame and/or the Tx FIFO is not empty. + BSY: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xc); + + /// address: 0x40088010 + /// Clock Prescale Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// This even value between 2 and 254, by which PCLK is divided to yield the + /// prescaler output clock. Bit 0 always reads as 0. + CPSDVSR: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x40088014 + /// Interrupt Mask Set and Clear Register + pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Software should set this bit to enable interrupt when a Receive Overrun occurs, + /// that is, when the Rx FIFO is full and another frame is completely received. The + /// ARM spec implies that the preceding frame data is overwritten by the new frame + /// data when this occurs. + RORIM: u1, + /// Software should set this bit to enable interrupt when a Receive Time-out + /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and + /// no has not been read for a time-out period. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTIM: u1, + /// Software should set this bit to enable interrupt when the Rx FIFO is at least + /// half full. + RXIM: u1, + /// Software should set this bit to enable interrupt when the Tx FIFO is at least + /// half empty. + TXIM: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14); + + /// address: 0x40088018 + /// Raw Interrupt Status Register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full. The ARM spec implies that the preceding frame data is overwritten by the + /// new frame data when this occurs. + RORRIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out + /// period. The time-out period is the same for master and slave modes and is + /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). + RTRIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full. + RXRIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty. + TXRIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x18); + + /// address: 0x4008801c + /// Masked Interrupt Status Register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit is 1 if another frame was completely received while the RxFIFO was + /// full, and this interrupt is enabled. + RORMIS: u1, + /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out + /// period, and this interrupt is enabled. The time-out period is the same for + /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / + /// (CPSDVSR X [SCR+1]). + RTMIS: u1, + /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is + /// enabled. + RXMIS: u1, + /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is + /// enabled. + TXMIS: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x1c); + + /// address: 0x40088020 + /// SSPICR Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the frame was received when RxFIFO was full + /// interrupt. + RORIC: u1, + /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read + /// for a time-out period interrupt. The time-out period is the same for master and + /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / + /// [SCR+1]). + RTIC: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x20); + + /// address: 0x40088024 + /// SSP0 DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is + /// enabled, otherwise receive DMA is disabled. + RXDMAE: u1, + /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is + /// enabled, otherwise transmit DMA is disabled + TXDMAE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x24); + }; + /// Digital-to-Analog Converter (DAC) + pub const DAC = struct { + pub const base_address = 0x4008c000; + + /// address: 0x4008c000 + /// D/A Converter Register. This register contains the digital value to be converted + /// to analog and a power control bit. + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u6, + /// After the selected settling time after this field is written with a new VALUE, + /// the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V + /// REFN)/1024) + VREFN. + VALUE: u10, + /// Settling time The settling times noted in the description of the BIAS bit are + /// valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load + /// impedance value greater than that value will cause settling time longer than the + /// specified time. One or more graphs of load impedance vs. settling time will be + /// included in the final data sheet. + BIAS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u15, + }), base_address + 0x0); + + /// address: 0x4008c004 + /// DAC Control register. This register controls DMA and timer operation. + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA interrupt request + INT_DMA_REQ: u1, + /// Double buffering + DBLBUF_ENA: u1, + /// Time-out counter operation + CNT_ENA: u1, + /// DMA access + DMA_ENA: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x4); + + /// address: 0x4008c008 + /// DAC Counter Value register. This register contains the reload value for the DAC + /// DMA/Interrupt timer. + pub const CNTVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// 16-bit reload value for the DAC interrupt/DMA timer. + VALUE: u16, + /// Reserved + RESERVED: u16, + }), base_address + 0x8); + }; + pub const TIMER2 = struct { + pub const base_address = 0x40090000; + + /// address: 0x40090000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40090004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40090008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4009000c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40090010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40090014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40090018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40090028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4009002c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4009003c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40090070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const TIMER3 = struct { + pub const base_address = 0x40094000; + + /// address: 0x40094000 + /// Interrupt Register. The IR can be written to clear interrupts. The IR can be + /// read to identify which of eight possible interrupt sources are pending. + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag for match channel 0. + MR0INT: u1, + /// Interrupt flag for match channel 1. + MR1INT: u1, + /// Interrupt flag for match channel 2. + MR2INT: u1, + /// Interrupt flag for match channel 3. + MR3INT: u1, + /// Interrupt flag for capture channel 0 event. + CR0INT: u1, + /// Interrupt flag for capture channel 1 event. + CR1INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x0); + + /// address: 0x40094004 + /// Timer Control Register. The TCR is used to control the Timer Counter functions. + /// The Timer Counter can be disabled or reset through the TCR. + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + /// When one, the Timer Counter and Prescale Counter are enabled for counting. When + /// zero, the counters are disabled. + CEN: u1, + /// When one, the Timer Counter and the Prescale Counter are synchronously reset on + /// the next positive edge of PCLK. The counters remain reset until TCR[1] is + /// returned to zero. + CRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x4); + + /// address: 0x40094008 + /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is + /// controlled through the TCR. + pub const TC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4009400c + /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the + /// next clock increments the TC and clears the PC. + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescale counter maximum value. + PM: u32, + }), base_address + 0xc); + + /// address: 0x40094010 + /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value + /// stored in PR. When the value in PR is reached, the TC is incremented and the PC + /// is cleared. The PC is observable and controllable through the bus interface. + pub const PC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40094014 + /// Match Control Register. The MCR is used to control if an interrupt is generated + /// and if the TC is reset when a Match occurs. + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt on MR0 + MR0I: u1, + /// Reset on MR0 + MR0R: u1, + /// Stop on MR0 + MR0S: u1, + /// Interrupt on MR1 + MR1I: u1, + /// Reset on MR1 + MR1R: u1, + /// Stop on MR1 + MR1S: u1, + /// Interrupt on MR2 + MR2I: u1, + /// Reset on MR2 + MR2R: u1, + /// Stop on MR2. + MR2S: u1, + /// Interrupt on MR3 + MR3I: u1, + /// Reset on MR3 + MR3R: u1, + /// Stop on MR3 + MR3S: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x14); + + /// address: 0x40094018 + /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both + /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. + pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Timer counter match value. + MATCH: u32, + }), base_address + 0x18); + + /// address: 0x40094028 + /// Capture Control Register. The CCR controls which edges of the capture inputs are + /// used to load the Capture Registers and whether or not an interrupt is generated + /// when a capture takes place. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture on CAPn.0 rising edge + CAP0RE: u1, + /// Capture on CAPn.0 falling edge + CAP0FE: u1, + /// Interrupt on CAPn.0 event + CAP0I: u1, + /// Capture on CAPn.1 rising edge + CAP1RE: u1, + /// Capture on CAPn.1 falling edge + CAP1FE: u1, + /// Interrupt on CAPn.1 event + CAP1I: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x4009402c + /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on + /// the CAPn.0 input. + pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Timer counter capture value. + CAP: u32, + }), base_address + 0x2c); + + /// address: 0x4009403c + /// External Match Register. The EMR controls the external match pins. + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Match 0. When a match occurs between the TC and MR0, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM0: u1, + /// External Match 1. When a match occurs between the TC and MR1, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this + /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM1: u1, + /// External Match 2. When a match occurs between the TC and MR2, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM2: u1, + /// External Match 3. When a match occurs between the TC and MR3, this bit can + /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this + /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner + /// (0 = low, 1 = high). + EM3: u1, + /// External Match Control 0. Determines the functionality of External Match 0. + EMC0: u2, + /// External Match Control 1. Determines the functionality of External Match 1. + EMC1: u2, + /// External Match Control 2. Determines the functionality of External Match 2. + EMC2: u2, + /// External Match Control 3. Determines the functionality of External Match 3. + EMC3: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0x3c); + + /// address: 0x40094070 + /// Count Control Register. The CTCR selects between Timer and Counter mode, and in + /// Counter mode selects the signal and edge(s) for counting. + pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter/Timer Mode This field selects which rising PCLK edges can increment + /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale + /// Register. + CTMODE: u2, + /// Count Input Select When bits 1:0 in this register are not 00, these bits select + /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a + /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture + /// Control Register (TnCCR) must be programmed as 000. However, capture and/or + /// interrupt can be selected for the other 3 CAPn inputs in the same timer. + CINSEL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x70); + }; + pub const UART2 = struct { + pub const base_address = 0x40098000; + + /// address: 0x40098000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x40098004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x40098004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x40098008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x40098008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4009800c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x40098014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4009801c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x40098020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x40098028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x40098030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4009804c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x40098050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x40098054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + pub const UART3 = struct { + pub const base_address = 0x4009c000; + + /// address: 0x4009c000 + /// Receiver Buffer Register. Contains the next received character to be read (DLAB + /// =0). + pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Receiver Buffer Register contains the oldest received byte in the + /// UARTn Rx FIFO. + RBR: u8, + /// Reserved, the value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c000 + /// Transmit Holding Regiter. The next character to be transmitted is written here + /// (DLAB =0). + pub const THR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing to the UARTn Transmit Holding Register causes the data to be stored in + /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the + /// FIFO and the transmitter is available. + THR: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c000 + /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines + /// the baud rate of the UARTn. + DLLSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x4009c004 + /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The + /// full divisor is used to generate a baud rate from the fractional rate divider + /// (DLAB =1). + pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { + /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines + /// the baud rate of the UARTn. + DLMSB: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x4009c004 + /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 + /// potential UART interrupts (DLAB =0). + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It + /// also controls the Character Receive Time-out interrupt. + RBRIE: u1, + /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this + /// can be read from UnLSR[5]. + THREIE: u1, + /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. + /// The status of this interrupt can be read from UnLSR[4:1]. + RXIE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Enables the end of auto-baud interrupt. + ABEOINTEN: u1, + /// Enables the auto-baud time-out interrupt. + ABTOINTEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x4); + + /// address: 0x4009c008 + /// Interrupt ID Register. Identifies which interrupt(s) are pending. + pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be + /// determined by evaluating UnIIR[3:1]. + INTSTATUS: u1, + /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to + /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below + /// are reserved (000,100,101,111). + INTID: u3, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// Copies of UnFCR[0]. + FIFOENABLE: u2, + /// End of auto-baud interrupt. True if auto-baud has finished successfully and + /// interrupt is enabled. + ABEOINT: u1, + /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is + /// enabled. + ABTOINT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x8); + + /// address: 0x4009c008 + /// FIFO Control Register. Controls UART FIFO usage and modes. + pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO Enable. + FIFOEN: u1, + /// RX FIFO Reset. + RXFIFORES: u1, + /// TX FIFO Reset. + TXFIFORES: u1, + /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit + /// selects the DMA mode. See Section 18.6.6.1. + DMAMODE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO + /// characters must be written before an interrupt or DMA request is activated. + RXTRIGLVL: u2, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x4009c00c + /// Line Control Register. Contains controls for frame formatting and break + /// generation. + pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Word Length Select. + WLS: u2, + /// Stop Bit Select + SBS: u1, + /// Parity Enable. + PE: u1, + /// Parity Select + PS: u2, + /// Break Control + BC: u1, + /// Divisor Latch Access Bit + DLAB: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x4009c014 + /// Line Status Register. Contains flags for transmit and receive status, including + /// line errors. + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character + /// and is cleared when the UARTn RBR FIFO is empty. + RDR: u1, + /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR + /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character + /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will + /// not be overwritten and the character in the UARTn RSR will be lost. + OE: u1, + /// Parity Error. When the parity bit of a received character is in the wrong state, + /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error + /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the + /// character at the top of the UARTn RBR FIFO. + PE: u1, + /// Framing Error. When the stop bit of a received character is a logic 0, a framing + /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error + /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx + /// will attempt to resynchronize to the data and assume that the bad stop bit is + /// actually an early start bit. However, it cannot be assumed that the next + /// received byte will be correct even if there is no Framing Error. Note: A framing + /// error is associated with the character at the top of the UARTn RBR FIFO. + FE: u1, + /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one + /// full character transmission (start, data, parity, stop), a break interrupt + /// occurs. Once the break condition has been detected, the receiver goes idle until + /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The + /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is + /// associated with the character at the top of the UARTn RBR FIFO. + BI: u1, + /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an + /// empty UARTn THR and is cleared on a UnTHR write. + THRE: u1, + /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is + /// cleared when either the UnTSR or the UnTHR contain valid data. + TEMT: u1, + /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as + /// framing error, parity error or break interrupt, is loaded into the UnRBR. This + /// bit is cleared when the UnLSR register is read and there are no subsequent + /// errors in the UARTn FIFO. + RXFE: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x4009c01c + /// Scratch Pad Register. 8-bit temporary storage for software. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + /// A readable, writable byte. + PAD: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x4009c020 + /// Auto-baud Control Register. Contains controls for the auto-baud feature. + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit. This bit is automatically cleared after auto-baud completion. + START: u1, + /// Auto-baud mode select bit. + MODE: u1, + /// Restart bit. + AUTORESTART: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABEOINTCLR: u1, + /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will + /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. + ABTOINTCLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x20); + + /// address: 0x4009c028 + /// Fractional Divider Register. Generates a clock input for the baud rate divider. + pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional + /// baud-rate generator will not impact the UARTn baudrate. + DIVADDVAL: u4, + /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for + /// UARTn to operate properly, regardless of whether the fractional baud-rate + /// generator is used or not. + MULVAL: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x4009c030 + /// Transmit Enable Register. Turns off UART transmitter for use with software flow + /// control. + pub const TER = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u7, + /// When this bit is 1, as it is after a Reset, data written to the THR is output on + /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared + /// to 0 while a character is being sent, the transmission of that character is + /// completed, but no further characters are sent until this bit is set again. In + /// other words, a 0 in this bit blocks the transfer of characters from the THR or + /// TX FIFO into the transmit shift register. Software implementing + /// software-handshaking can clear this bit when it receives an XOFF character + /// (DC3). Software can set this bit again when it receives an XON (DC1) character. + TXEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30); + + /// address: 0x4009c04c + /// RS-485/EIA-485 Control. Contains controls to configure various aspects of + /// RS-485/EIA-485 modes. + pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// NMM enable. + NMMEN: u1, + /// Receiver enable. + RXDIS: u1, + /// AAD enable. + AADEN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Direction control enable. + DCTRL: u1, + /// Direction control pin polarity. This bit reverses the polarity of the direction + /// control signal on the Un_OE pin. + OINV: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x4c); + + /// address: 0x4009c050 + /// RS-485/EIA-485 address match. Contains the address match value for + /// RS-485/EIA-485 mode. + pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the address match value. + ADRMATCH: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x50); + + /// address: 0x4009c054 + /// RS-485/EIA-485 direction control delay. + pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Contains the direction control (UnOE) delay value. This register works in + /// conjunction with an 8-bit counter. + DLY: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x54); + }; + pub const I2C2 = struct { + pub const base_address = 0x400a0000; + + /// address: 0x400a0000 + /// I2C Control Set Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is set. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge flag. + AA: u1, + /// I2C interrupt flag. + SI: u1, + /// STOP flag. + STO: u1, + /// START flag. + STA: u1, + /// I2C interface enable. + I2EN: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x0); + + /// address: 0x400a0004 + /// I2C Status Register. During I2C operation, this register provides detailed + /// status codes that allow software to determine the next action needed. + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits are unused and are always 0. + RESERVED: u3, + /// These bits give the actual status information about the I 2C interface. + Status: u5, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x400a0008 + /// I2C Data Register. During master or slave transmit mode, data to be transmitted + /// is written to this register. During master or slave receive mode, data that has + /// been received may be read from this register. + pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds data values that have been received or are to be + /// transmitted. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x400a000c + /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x400a0010 + /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C + /// clock. + pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL HIGH time period selection. + SCLH: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x10); + + /// address: 0x400a0014 + /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. + /// SCLL and SCLH together determine the clock frequency generated by an I2C master + /// and certain times used in slave mode. + pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { + /// Count for SCL low time period selection. + SCLL: u16, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x400a0018 + /// I2C Control Clear Register. When a one is written to a bit of this register, the + /// corresponding bit in the I2C control register is cleared. Writing a zero has no + /// effect on the corresponding bit in the I2C control register. + pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u2, + /// Assert acknowledge Clear bit. + AAC: u1, + /// I2C interrupt Clear bit. + SIC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// START flag Clear bit. + STAC: u1, + /// I2C interface Disable bit. + I2ENC: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x400a001c + /// Monitor mode control register. + pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor mode enable. + MM_ENA: u1, + /// SCL output enable. + ENA_SCL: u1, + /// Select interrupt register match. + MATCH_ALL: u1, + /// Reserved. The value read from reserved bits is not defined. + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x400a0020 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x20); + + /// address: 0x400a0024 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x24); + + /// address: 0x400a0028 + /// I2C Slave Address Register. Contains the 7-bit slave address for operation of + /// the I2C interface in slave mode, and is not used in master mode. The least + /// significant bit determines whether a slave responds to the General Call address. + pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call enable bit. + GC: u1, + /// The I2C device address for slave mode. + Address: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x28); + + /// address: 0x400a002c + /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will + /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of + /// data plus ACK or NACK) has been received on the bus. + pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { + /// This register holds contents of the 8 MSBs of the DAT shift register. + Data: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x2c); + + /// address: 0x400a0030 + /// I2C Slave address mask register + pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. This bit reads + /// always back as 0. + RESERVED: u1, + /// Mask bits. + MASK: u7, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x30); + }; + /// I2S interface + pub const I2S = struct { + pub const base_address = 0x400a8000; + + /// address: 0x400a8000 + /// I2S Digital Audio Output Register. Contains control bits for the I2S transmit + /// channel. + pub const DAO = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the number of bytes in data as follows: + WORDWIDTH: u2, + /// When 1, data is of monaural format. When 0, the data is in stereo format. + MONO: u1, + /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + STOP: u1, + /// When 1, asynchronously resets the transmit channel and FIFO. + RESET: u1, + /// When 0, the interface is in master mode. When 1, the interface is in slave mode. + /// See Section 34.7.2 for a summary of useful combinations for this bit with + /// TXMODE. + WS_SEL: u1, + /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + WS_HALFPERIOD: u9, + /// When 1, the transmit channel sends only zeroes. + MUTE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x400a8004 + /// I2S Digital Audio Input Register. Contains control bits for the I2S receive + /// channel. + pub const DAI = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the number of bytes in data as follows: + WORDWIDTH: u2, + /// When 1, data is of monaural format. When 0, the data is in stereo format. + MONO: u1, + /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. + STOP: u1, + /// When 1, asynchronously reset the transmit channel and FIFO. + RESET: u1, + /// When 0, the interface is in master mode. When 1, the interface is in slave mode. + /// See Section 34.7.2 for a summary of useful combinations for this bit with + /// RXMODE. + WS_SEL: u1, + /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. + WS_HALFPERIOD: u9, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u17, + }), base_address + 0x4); + + /// address: 0x400a8008 + /// I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. + pub const TXFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// 8 x 32-bit transmit FIFO. + I2STXFIFO: u32, + }), base_address + 0x8); + + /// address: 0x400a800c + /// I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. + pub const RXFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// 8 x 32-bit transmit FIFO. + I2SRXFIFO: u32, + }), base_address + 0xc); + + /// address: 0x400a8010 + /// I2S Status Feedback Register. Contains status information about the I2S + /// interface. + pub const STATE = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This + /// is determined by comparing the current FIFO levels to the rx_depth_irq and + /// tx_depth_irq fields in the IRQ register. + IRQ: u1, + /// This bit reflects the presence of Receive or Transmit DMA Request 1. This is + /// determined by comparing the current FIFO levels to the rx_depth_dma1 and + /// tx_depth_dma1 fields in the DMA1 register. + DMAREQ1: u1, + /// This bit reflects the presence of Receive or Transmit DMA Request 2. This is + /// determined by comparing the current FIFO levels to the rx_depth_dma2 and + /// tx_depth_dma2 fields in the DMA2 register. + DMAREQ2: u1, + /// Reserved. + RESERVED: u5, + /// Reflects the current level of the Receive FIFO. + RX_LEVEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Reflects the current level of the Transmit FIFO. + TX_LEVEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x10); + + /// address: 0x400a8014 + /// I2S DMA Configuration Register 1. Contains control information for DMA request + /// 1. + pub const DMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables DMA1 for I2S receive. + RX_DMA1_ENABLE: u1, + /// When 1, enables DMA1 for I2S transmit. + TX_DMA1_ENABLE: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u6, + /// Set the FIFO level that triggers a receive DMA request on DMA1. + RX_DEPTH_DMA1: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level that triggers a transmit DMA request on DMA1. + TX_DEPTH_DMA1: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x14); + + /// address: 0x400a8018 + /// I2S DMA Configuration Register 2. Contains control information for DMA request + /// 2. + pub const DMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables DMA1 for I2S receive. + RX_DMA2_ENABLE: u1, + /// When 1, enables DMA1 for I2S transmit. + TX_DMA2_ENABLE: u1, + /// Reserved. + RESERVED: u6, + /// Set the FIFO level that triggers a receive DMA request on DMA2. + RX_DEPTH_DMA2: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level that triggers a transmit DMA request on DMA2. + TX_DEPTH_DMA2: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x18); + + /// address: 0x400a801c + /// I2S Interrupt Request Control Register. Contains bits that control how the I2S + /// interrupt request is generated. + pub const IRQ = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enables I2S receive interrupt. + RX_IRQ_ENABLE: u1, + /// When 1, enables I2S transmit interrupt. + TX_IRQ_ENABLE: u1, + /// Reserved. + RESERVED: u6, + /// Set the FIFO level on which to create an irq request. + RX_DEPTH_IRQ: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Set the FIFO level on which to create an irq request. + TX_DEPTH_IRQ: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u12, + }), base_address + 0x1c); + + /// address: 0x400a8020 + /// I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by + /// specifying the value to divide PCLK by in order to produce MCLK. + pub const TXRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce + /// the transmit MCLK. Eight bits of fractional divide supports a wide range of + /// possibilities. A value of 0 stops the clock. + Y_DIVIDER: u8, + /// I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to + /// produce the transmit MCLK. A value of 0 stops the clock. Eight bits of + /// fractional divide supports a wide range of possibilities. Note: the resulting + /// ratio X/Y is divided by 2. + X_DIVIDER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x20); + + /// address: 0x400a8024 + /// I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by + /// specifying the value to divide PCLK by in order to produce MCLK. + pub const RXRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S receive MCLK rate denominator. This value is used to divide PCLK to produce + /// the receive MCLK. Eight bits of fractional divide supports a wide range of + /// possibilities. A value of 0 stops the clock. + Y_DIVIDER: u8, + /// I2S receive MCLK rate numerator. This value is used to multiply PCLK by to + /// produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional + /// divide supports a wide range of possibilities. Note: the resulting ratio X/Y is + /// divided by 2. + X_DIVIDER: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u16, + }), base_address + 0x24); + + /// address: 0x400a8028 + /// I2S Transmit bit rate divider. This register determines the I2S transmit bit + /// rate by specifying the value to divide TX_MCLK by in order to produce the + /// transmit bit clock. + pub const TXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce + /// the transmit bit clock. + TX_BITRATE: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x28); + + /// address: 0x400a802c + /// I2S Receive bit rate divider. This register determines the I2S receive bit rate + /// by specifying the value to divide RX_MCLK by in order to produce the receive bit + /// clock. + pub const RXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce + /// the receive bit clock. + RX_BITRATE: u6, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u26, + }), base_address + 0x2c); + + /// address: 0x400a8030 + /// I2S Transmit mode control. + pub const TXMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock source selection for the transmit bit clock divider. + TXCLKSEL: u2, + /// Transmit 4-pin mode selection. When 1, enables 4-pin mode. + TX4PIN: u1, + /// Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, + /// output of TX_MCLK is enabled. + TXMCENA: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x30); + + /// address: 0x400a8034 + /// I2S Receive mode control. + pub const RXMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock source selection for the receive bit clock divider. + RXCLKSEL: u2, + /// Receive 4-pin mode selection. When 1, enables 4-pin mode. + RX4PIN: u1, + /// Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, + /// output of RX_MCLK is enabled. + RXMCENA: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x34); + }; + /// Repetitive Interrupt Timer (RIT) + pub const RITIMER = struct { + pub const base_address = 0x400b0000; + + /// address: 0x400b0000 + /// Compare register + pub const COMPVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Compare register. Holds the compare value which is compared to the counter. + RICOMP: u32, + }), base_address + 0x0); + + /// address: 0x400b0004 + /// Mask register. This register holds the 32-bit mask value. A 1 written to any bit + /// will force a compare on the corresponding bit of the counter and compare + /// register. + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// Mask register. This register holds the 32-bit mask value. A one written to any + /// bit overrides the result of the comparison for the corresponding bit of the + /// counter and compare register (causes the comparison of the register bits to be + /// always true). + RIMASK: u32, + }), base_address + 0x4); + + /// address: 0x400b0008 + /// Control register. + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt flag + RITINT: u1, + /// Timer enable clear + RITENCLR: u1, + /// Timer enable for debug + RITENBR: u1, + /// Timer enable. + RITEN: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x8); + + /// address: 0x400b000c + /// 32-bit counter + pub const COUNTER = @intToPtr(*volatile Mmio(32, packed struct { + /// 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is + /// cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can + /// be loaded to any value in software. + RICOUNTER: u32, + }), base_address + 0xc); + }; + /// Motor Control PWM + pub const MCPWM = struct { + pub const base_address = 0x400b8000; + + /// address: 0x400b8000 + /// PWM Control read address + pub const CON = @intToPtr(*volatile Mmio(32, packed struct { + /// Stops/starts timer channel 0. + RUN0: u1, + /// Edge/center aligned operation for channel 0. + CENTER0: u1, + /// Selects polarity of the MCOA0 and MCOB0 pins. + POLA0: u1, + /// Controls the dead-time feature for channel 0. + DTE0: u1, + /// Enable/disable updates of functional registers for channel 0 (see Section + /// 24.8.2). + DISUP0: u1, + /// Reserved. + RESERVED: u3, + /// Stops/starts timer channel 1. + RUN1: u1, + /// Edge/center aligned operation for channel 1. + CENTER1: u1, + /// Selects polarity of the MCOA1 and MCOB1 pins. + POLA1: u1, + /// Controls the dead-time feature for channel 1. + DTE1: u1, + /// Enable/disable updates of functional registers for channel 1 (see Section + /// 24.8.2). + DISUP1: u1, + /// Reserved. + RESERVED: u3, + /// Stops/starts timer channel 2. + RUN2: u1, + /// Edge/center aligned operation for channel 2. + CENTER2: u1, + /// Selects polarity of the MCOA2 and MCOB2 pins. + POLA2: u1, + /// Controls the dead-time feature for channel 1. + DTE2: u1, + /// Enable/disable updates of functional registers for channel 2 (see Section + /// 24.8.2). + DISUP2: u1, + /// Reserved. + RESERVED: u8, + /// Controls the polarity of the MCOB outputs for all 3 channels. This bit is + /// typically set to 1 only in 3-phase DC mode. + INVBDC: u1, + /// 3-phase AC mode select (see Section 24.8.7). + ACMODE: u1, + /// 3-phase DC mode select (see Section 24.8.6). + DCMODE: u1, + }), base_address + 0x0); + + /// address: 0x400b8004 + /// PWM Control set address + pub const CON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the CON register. + RUN0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP0_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one sets the corresponding bit in the CON register. + RUN1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP1_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one sets the corresponding bit in the CON register. + RUN2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + CENTER2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + POLA2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DTE2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DISUP2_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + RESERVED: u8, + /// Writing a one sets the corresponding bit in the CON register. + INVBDC_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + ACMODE_SET: u1, + /// Writing a one sets the corresponding bit in the CON register. + DCMODE_SET: u1, + }), base_address + 0x4); + + /// address: 0x400b8008 + /// PWM Control clear address + pub const CON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the CON register. + RUN0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP0_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one clears the corresponding bit in the CON register. + RUN1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP1_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u3, + /// Writing a one clears the corresponding bit in the CON register. + RUN2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + CENTER2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + POLA2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DTE2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DISUP2_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + RESERVED: u8, + /// Writing a one clears the corresponding bit in the CON register. + INVBDC_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + ACMOD_CLR: u1, + /// Writing a one clears the corresponding bit in the CON register. + DCMODE_CLR: u1, + }), base_address + 0x8); + + /// address: 0x400b800c + /// Capture Control read address + pub const CAPCON = @intToPtr(*volatile Mmio(32, packed struct { + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. + CAP0MCI0_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. + CAP0MCI0_FE: u1, + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. + CAP0MCI1_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. + CAP0MCI1_FE: u1, + /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. + CAP0MCI2_RE: u1, + /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. + CAP0MCI2_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. + CAP1MCI0_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. + CAP1MCI0_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. + CAP1MCI1_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. + CAP1MCI1_FE: u1, + /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. + CAP1MCI2_RE: u1, + /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. + CAP1MCI2_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. + CAP2MCI0_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. + CAP2MCI0_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. + CAP2MCI1_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. + CAP2MCI1_FE: u1, + /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. + CAP2MCI2_RE: u1, + /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. + CAP2MCI2_FE: u1, + /// If this bit is 1, TC0 is reset by a channel 0 capture event. + RT0: u1, + /// If this bit is 1, TC1 is reset by a channel 1 capture event. + RT1: u1, + /// If this bit is 1, TC2 is reset by a channel 2 capture event. + RT2: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0xc); + + /// address: 0x400b8010 + /// Capture Control set address + pub const CAPCON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP0MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP1MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + CAP2MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT0_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT1_SET: u1, + /// Writing a one sets the corresponding bits in the CAPCON register. + RT2_SET: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0x10); + + /// address: 0x400b8014 + /// Event Control clear address + pub const CAPCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP0MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP1MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + CAP2MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT0_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT1_CLR: u1, + /// Writing a one clears the corresponding bits in the CAPCON register. + RT2_CLR: u1, + /// Reserved. + RESERVED: u11, + }), base_address + 0x14); + + /// address: 0x400b8018 + /// Timer Counter register + pub const TC = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Timer/Counter value. + MCTC: u32, + }), base_address + 0x18); + + /// address: 0x400b8024 + /// Limit register + pub const LIM = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Limit value. + MCLIM: u32, + }), base_address + 0x24); + + /// address: 0x400b8030 + /// Match register + pub const MAT = @intToPtr(*volatile [3]Mmio(32, packed struct { + /// Match value. + MCMAT: u32, + }), base_address + 0x30); + + /// address: 0x400b803c + /// Dead time register + pub const DT = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead time for channel 0.[1] + DT0: u10, + /// Dead time for channel 1.[2] + DT1: u10, + /// Dead time for channel 2.[2] + DT2: u10, + /// reserved + RESERVED: u2, + }), base_address + 0x3c); + + /// address: 0x400b8040 + /// Communication Pattern register + pub const CP = @intToPtr(*volatile Mmio(32, packed struct { + /// Communication pattern output A, channel 0. + CCPA0: u1, + /// Communication pattern output B, channel 0. + CCPB0: u1, + /// Communication pattern output A, channel 1. + CCPA1: u1, + /// Communication pattern output B, channel 1. + CCPB1: u1, + /// Communication pattern output A, channel 2. + CCPA2: u1, + /// Communication pattern output B, channel 2. + CCPB2: u1, + /// Reserved. + RESERVED: u26, + }), base_address + 0x40); + + /// address: 0x400b8044 + /// Capture register + pub const CAP = @intToPtr(*volatile [3]u32, base_address + 0x44); + + /// address: 0x400b8050 + /// Interrupt Enable read address + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Limit interrupt for channel 0. + ILIM0: u1, + /// Match interrupt for channel 0. + IMAT0: u1, + /// Capture interrupt for channel 0. + ICAP0: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt for channel 1. + ILIM1: u1, + /// Match interrupt for channel 1. + IMAT1: u1, + /// Capture interrupt for channel 1. + ICAP1: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt for channel 2. + ILIM2: u1, + /// Match interrupt for channel 2. + IMAT2: u1, + /// Capture interrupt for channel 2. + ICAP2: u1, + /// Reserved. + RESERVED: u4, + /// Fast abort interrupt. + ABORT: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x50); + + /// address: 0x400b8054 + /// Interrupt Enable set address + pub const INTEN_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM0_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT0_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP0_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM1_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT1_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP1_SET: u1, + /// Reserved. + RESERVED: u1, + reserved0: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ILIM2_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + IMAT2_SET: u1, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ICAP2_SET: u1, + /// Reserved. + RESERVED: u3, + /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. + ABORT_SET: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x54); + + /// address: 0x400b8058 + /// Interrupt Enable clear address + pub const INTEN_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM0_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT0_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP0_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM1_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT1_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP1_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM2_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT2_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP2_CLR: u1, + /// Reserved. + RESERVED: u4, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ABORT_CLR: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x58); + + /// address: 0x400b8068 + /// Interrupt flags read address + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Limit interrupt flag for channel 0. + ILIM0_F: u1, + /// Match interrupt flag for channel 0. + IMAT0_F: u1, + /// Capture interrupt flag for channel 0. + ICAP0_F: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt flag for channel 1. + ILIM1_F: u1, + /// Match interrupt flag for channel 1. + IMAT1_F: u1, + /// Capture interrupt flag for channel 1. + ICAP1_F: u1, + /// Reserved. + RESERVED: u1, + /// Limit interrupt flag for channel 2. + ILIM2_F: u1, + /// Match interrupt flag for channel 2. + IMAT2_F: u1, + /// Capture interrupt flag for channel 2. + ICAP2_F: u1, + /// Reserved. + RESERVED: u4, + /// Fast abort interrupt flag. + ABORT_F: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x68); + + /// address: 0x400b806c + /// Interrupt flags set address + pub const INTF_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM0_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT0_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP0_F_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM1_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT1_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP1_F_SET: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ILIM2_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + IMAT2_F_SET: u1, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ICAP2_F_SET: u1, + /// Reserved. + RESERVED: u4, + /// Writing a one sets the corresponding bit in the INTF register, thus possibly + /// simulating hardware interrupt. + ABORT_F_SET: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x6c); + + /// address: 0x400b8070 + /// Interrupt flags clear address + pub const INTF_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the INTF register, thus clearing + /// the corresponding interrupt request. + ILIM0_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT0_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP0_F_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM1_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT1_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP1_F_CLR: u1, + /// Reserved. + RESERVED: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ILIM2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + IMAT2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ICAP2_F_CLR: u1, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + RESERVED: u4, + /// Writing a one clears the corresponding bit in INTEN, thus disabling the + /// interrupt. + ABORT_F_CLR: u1, + /// Reserved. + RESERVED: u16, + }), base_address + 0x70); + + /// address: 0x400b805c + /// Count Control read address + pub const CNTCON = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter 0 rising edge mode, channel 0. + TC0MCI0_RE: u1, + /// Counter 0 falling edge mode, channel 0. + TC0MCI0_FE: u1, + /// Counter 0 rising edge mode, channel 1. + TC0MCI1_RE: u1, + /// Counter 0 falling edge mode, channel 1. + TC0MCI1_FE: u1, + /// Counter 0 rising edge mode, channel 2. + TC0MCI2_RE: u1, + /// Counter 0 falling edge mode, channel 2. + TC0MCI2_FE: u1, + /// Counter 1 rising edge mode, channel 0. + TC1MCI0_RE: u1, + /// Counter 1 falling edge mode, channel 0. + TC1MCI0_FE: u1, + /// Counter 1 rising edge mode, channel 1. + TC1MCI1_RE: u1, + /// Counter 1 falling edge mode, channel 1. + TC1MCI1_FE: u1, + /// Counter 1 rising edge mode, channel 2. + TC1MCI2_RE: u1, + /// Counter 1 falling edge mode, channel 2. + TC1MCI2_FE: u1, + /// Counter 2 rising edge mode, channel 0. + TC2MCI0_RE: u1, + /// Counter 2 falling edge mode, channel 0. + TC2MCI0_FE: u1, + /// Counter 2 rising edge mode, channel 1. + TC2MCI1_RE: u1, + /// Counter 2 falling edge mode, channel 1. + TC2MCI1_FE: u1, + /// Counter 2 rising edge mode, channel 2. + TC2MCI2_RE: u1, + /// Counter 2 falling edge mode, channel 2. + TC2MCI2_FE: u1, + /// Reserved. + RESERVED: u11, + /// Channel 0 counter/timer mode. + CNTR0: u1, + /// Channel 1 counter/timer mode. + CNTR1: u1, + /// Channel 2 counter/timer mode. + CNTR2: u1, + }), base_address + 0x5c); + + /// address: 0x400b8060 + /// Count Control set address + pub const CNTCON_SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC0MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC1MCI2_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI0_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI1_FE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_RE_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + TC2MCI2_FE_SET: u1, + /// Reserved. + RESERVED: u11, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR0_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR1_SET: u1, + /// Writing a one sets the corresponding bit in the CNTCON register. + CNTR2_SET: u1, + }), base_address + 0x60); + + /// address: 0x400b8064 + /// Count Control clear address + pub const CNTCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_RE: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC0MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC1MCI2_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI0_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI1_FE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_RE_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + TC2MCI2_FE_CLR: u1, + /// Reserved. + RESERVED: u11, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR0_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR1_CLR: u1, + /// Writing a one clears the corresponding bit in the CNTCON register. + CNTR2_CLR: u1, + }), base_address + 0x64); + + /// address: 0x400b8074 + /// Capture clear address + pub const CAP_CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to this bit clears the CAP0 register. + CAP_CLR0: u1, + /// Writing a 1 to this bit clears the CAP1 register. + CAP_CLR1: u1, + /// Writing a 1 to this bit clears the CAP2 register. + CAP_CLR2: u1, + /// Reserved + RESERVED: u29, + }), base_address + 0x74); + }; + /// Quadrature Encoder Interface (QEI) + pub const QEI = struct { + pub const base_address = 0x400bc000; + + /// address: 0x400bc000 + /// Control register + pub const CON = @intToPtr(*volatile Mmio(32, packed struct { + /// Reset position counter. When set = 1, resets the position counter to all zeros. + /// Autoclears when the position counter is cleared. + RESP: u1, + /// Reset position counter on index. When set = 1, resets the position counter to + /// all zeros once only the first time an index pulse occurs. Autoclears when the + /// position counter is cleared. + RESPI: u1, + /// Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads + /// the velocity timer, and presets the velocity compare register. Autoclears when + /// the velocity counter is cleared. + RESV: u1, + /// Reset index counter. When set = 1, resets the index counter to all zeros. + /// Autoclears when the index counter is cleared. + RESI: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x0); + + /// address: 0x400bc008 + /// Configuration register + pub const CONF = @intToPtr(*volatile Mmio(32, packed struct { + /// Direction invert. When 1, complements the DIR bit. + DIRINV: u1, + /// Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, + /// PhA functions as the direction signal and PhB functions as the clock signal. + SIGMODE: u1, + /// Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB + /// edges are counted (4X), increasing resolution but decreasing range. + CAPMODE: u1, + /// Invert Index. When 1, inverts the sense of the index input. + INVINX: u1, + /// Continuously reset the position counter on index. When 1, resets the position + /// counter to all zeros whenever an index pulse occurs after the next position + /// increase (recalibration). + CRESPI: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u11, + /// Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 + /// and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when + /// PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index + /// when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the + /// index when PHA = 0 and PHB = 0, otherwise block index. + INXGATE: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u12, + }), base_address + 0x8); + + /// address: 0x400bc004 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Direction bit. In combination with DIRINV bit indicates forward or reverse + /// direction. See Table 597. + DIR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u31, + }), base_address + 0x4); + + /// address: 0x400bc00c + /// Position register + pub const POS = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x400bc010 + /// Maximum position register + pub const MAXPOS = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x400bc014 + /// Position compare register 0 + pub const CMPOS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 0. + PCMP0: u32, + }), base_address + 0x14); + + /// address: 0x400bc018 + /// Position compare register 1 + pub const CMPOS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 1. + PCMP1: u32, + }), base_address + 0x18); + + /// address: 0x400bc01c + /// Position compare register 2 + pub const CMPOS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Position compare value 2. + PCMP2: u32, + }), base_address + 0x1c); + + /// address: 0x400bc020 + /// Index count register 0 + pub const INXCNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Current index counter value. + ENCPOS: u32, + }), base_address + 0x20); + + /// address: 0x400bc024 + /// Index compare register 0 + pub const INXCMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Index compare value 0. + ICMP0: u32, + }), base_address + 0x24); + + /// address: 0x400bc028 + /// Velocity timer reload register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity timer load value. + VELLOAD: u32, + }), base_address + 0x28); + + /// address: 0x400bc02c + /// Velocity timer register + pub const TIME = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity timer value. + VELVAL: u32, + }), base_address + 0x2c); + + /// address: 0x400bc030 + /// Velocity counter register + pub const VEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Current velocity pulse count. + VELPC: u32, + }), base_address + 0x30); + + /// address: 0x400bc034 + /// Velocity capture register + pub const CAP = @intToPtr(*volatile Mmio(32, packed struct { + /// Last velocity capture. + VELCAP: u32, + }), base_address + 0x34); + + /// address: 0x400bc038 + /// Velocity compare register + pub const VELCOMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Compare velocity pulse count. + VELPC: u32, + }), base_address + 0x38); + + /// address: 0x400bc03c + /// Digital filter register + pub const FILTER = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital filter sampling delay. + FILTA: u32, + }), base_address + 0x3c); + + /// address: 0x400bcfe0 + /// Interrupt status register + pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates that an index pulse was detected. + INX_INT: u1, + /// Indicates that a velocity timer overflow occurred + TIM_INT: u1, + /// Indicates that captured velocity is less than compare velocity. + VELC_INT: u1, + /// Indicates that a change of direction was detected. + DIR_INT: u1, + /// Indicates that an encoder phase error was detected. + ERR_INT: u1, + /// Indicates that and encoder clock pulse was detected. + ENCLK_INT: u1, + /// Indicates that the position 0 compare value is equal to the current position. + POS0_INT: u1, + /// Indicates that the position 1compare value is equal to the current position. + POS1_INT: u1, + /// Indicates that the position 2 compare value is equal to the current position. + POS2_INT: u1, + /// Indicates that the index compare 0 value is equal to the current index count. + REV0_INT: u1, + /// Combined position 0 and revolution count interrupt. Set when both the POS0_Int + /// bit is set and the REV0_Int is set. + POS0REV_INT: u1, + /// Combined position 1 and revolution count interrupt. Set when both the POS1_Int + /// bit is set and the REV1_Int is set. + POS1REV_INT: u1, + /// Combined position 2 and revolution count interrupt. Set when both the POS2_Int + /// bit is set and the REV2_Int is set. + POS2REV_INT: u1, + /// Indicates that the index compare 1value is equal to the current index count. + REV1_INT: u1, + /// Indicates that the index compare 2 value is equal to the current index count. + REV2_INT: u1, + /// Indicates that the current position count goes through the MAXPOS value to zero + /// in the forward direction, or through zero to MAXPOS in the reverse direction. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe0); + + /// address: 0x400bcfec + /// Interrupt status set register + pub const SET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 sets the INX_Int bit in QEIINTSTAT. + INX_INT: u1, + /// Writing a 1 sets the TIN_Int bit in QEIINTSTAT. + TIM_INT: u1, + /// Writing a 1 sets the VELC_Int bit in QEIINTSTAT. + VELC_INT: u1, + /// Writing a 1 sets the DIR_Int bit in QEIINTSTAT. + DIR_INT: u1, + /// Writing a 1 sets the ERR_Int bit in QEIINTSTAT. + ERR_INT: u1, + /// Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. + ENCLK_INT: u1, + /// Writing a 1 sets the POS0_Int bit in QEIINTSTAT. + POS0_INT: u1, + /// Writing a 1 sets the POS1_Int bit in QEIINTSTAT. + POS1_INT: u1, + /// Writing a 1 sets the POS2_Int bit in QEIINTSTAT. + POS2_INT: u1, + /// Writing a 1 sets the REV0_Int bit in QEIINTSTAT. + REV0_INT: u1, + /// Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. + POS0REV_INT: u1, + /// Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, + /// Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, + /// Writing a 1 sets the REV1_Int bit in QEIINTSTAT. + REV1_INT: u1, + /// Writing a 1 sets the REV2_Int bit in QEIINTSTAT. + REV2_INT: u1, + /// Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfec); + + /// address: 0x400bcfe8 + /// Interrupt status clear register + pub const CLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the INX_Int bit in QEIINTSTAT. + INX_INT: u1, + /// Writing a 1 clears the TIN_Int bit in QEIINTSTAT. + TIM_INT: u1, + /// Writing a 1 clears the VELC_Int bit in QEIINTSTAT. + VELC_INT: u1, + /// Writing a 1 clears the DIR_Int bit in QEIINTSTAT. + DIR_INT: u1, + /// Writing a 1 clears the ERR_Int bit in QEIINTSTAT. + ERR_INT: u1, + /// Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. + ENCLK_INT: u1, + /// Writing a 1 clears the POS0_Int bit in QEIINTSTAT. + POS0_INT: u1, + /// Writing a 1 clears the POS1_Int bit in QEIINTSTAT. + POS1_INT: u1, + /// Writing a 1 clears the POS2_Int bit in QEIINTSTAT. + POS2_INT: u1, + /// Writing a 1 clears the REV0_Int bit in QEIINTSTAT. + REV0_INT: u1, + /// Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. + POS0REV_INT: u1, + /// Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. + POS1REV_INT: u1, + /// Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. + POS2REV_INT: u1, + /// Writing a 1 clears the REV1_Int bit in QEIINTSTAT. + REV1_INT: u1, + /// Writing a 1 clears the REV2_Int bit in QEIINTSTAT. + REV2_INT: u1, + /// Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe8); + + /// address: 0x400bcfe4 + /// Interrupt enable register + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, the INX_Int interrupt is enabled. + INX_INT: u1, + /// When 1, the TIN_Int interrupt is enabled. + TIM_INT: u1, + /// When 1, the VELC_Int interrupt is enabled. + VELC_INT: u1, + /// When 1, the DIR_Int interrupt is enabled. + DIR_INT: u1, + /// When 1, the ERR_Int interrupt is enabled. + ERR_INT: u1, + /// When 1, the ENCLK_Int interrupt is enabled. + ENCLK_INT: u1, + /// When 1, the POS0_Int interrupt is enabled. + POS0_INT: u1, + /// When 1, the POS1_Int interrupt is enabled. + POS1_INT: u1, + /// When 1, the POS2_Int interrupt is enabled. + POS2_INT: u1, + /// When 1, the REV0_Int interrupt is enabled. + REV0_INT: u1, + /// When 1, the POS0REV_Int interrupt is enabled. + POS0REV_INT: u1, + /// When 1, the POS1REV_Int interrupt is enabled. + POS1REV_INT: u1, + /// When 1, the POS2REV_Int interrupt is enabled. + POS2REV_INT: u1, + /// When 1, the REV1_Int interrupt is enabled. + REV1_INT: u1, + /// When 1, the REV2_Int interrupt is enabled. + REV2_INT: u1, + /// When 1, the MAXPOS_Int interrupt is enabled. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfe4); + + /// address: 0x400bcfdc + /// Interrupt enable set register + pub const IES = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 enables the INX_Int interrupt in the QEIIE register. + INX_INT: u1, + /// Writing a 1 enables the TIN_Int interrupt in the QEIIE register. + TIM_INT: u1, + /// Writing a 1 enables the VELC_Int interrupt in the QEIIE register. + VELC_INT: u1, + /// Writing a 1 enables the DIR_Int interrupt in the QEIIE register. + DIR_INT: u1, + /// Writing a 1 enables the ERR_Int interrupt in the QEIIE register. + ERR_INT: u1, + /// Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. + ENCLK_INT: u1, + /// Writing a 1 enables the POS0_Int interrupt in the QEIIE register. + POS0_INT: u1, + /// Writing a 1 enables the POS1_Int interrupt in the QEIIE register. + POS1_INT: u1, + /// Writing a 1 enables the POS2_Int interrupt in the QEIIE register. + POS2_INT: u1, + /// Writing a 1 enables the REV0_Int interrupt in the QEIIE register. + REV0_INT: u1, + /// Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. + POS0REV_INT: u1, + /// Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, + /// Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, + /// Writing a 1 enables the REV1_Int interrupt in the QEIIE register. + REV1_INT: u1, + /// Writing a 1 enables the REV2_Int interrupt in the QEIIE register. + REV2_INT: u1, + /// Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfdc); + + /// address: 0x400bcfd8 + /// Interrupt enable clear register + pub const IEC = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 disables the INX_Int interrupt in the QEIIE register. + INX_INT: u1, + /// Writing a 1 disables the TIN_Int interrupt in the QEIIE register. + TIM_INT: u1, + /// Writing a 1 disables the VELC_Int interrupt in the QEIIE register. + VELC_INT: u1, + /// Writing a 1 disables the DIR_Int interrupt in the QEIIE register. + DIR_INT: u1, + /// Writing a 1 disables the ERR_Int interrupt in the QEIIE register. + ERR_INT: u1, + /// Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. + ENCLK_INT: u1, + /// Writing a 1 disables the POS0_Int interrupt in the QEIIE register. + POS0_INT: u1, + /// Writing a 1 disables the POS1_Int interrupt in the QEIIE register. + POS1_INT: u1, + /// Writing a 1 disables the POS2_Int interrupt in the QEIIE register. + POS2_INT: u1, + /// Writing a 1 disables the REV0_Int interrupt in the QEIIE register. + REV0_INT: u1, + /// Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. + POS0REV_INT: u1, + /// Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. + POS1REV_INT: u1, + /// Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. + POS2REV_INT: u1, + /// Writing a 1 disables the REV1_Int interrupt in the QEIIE register. + REV1_INT: u1, + /// Writing a 1 disables the REV2_Int interrupt in the QEIIE register. + REV2_INT: u1, + /// Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. + MAXPOS_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0xfd8); + }; + /// System and clock control + pub const SYSCON = struct { + pub const base_address = 0x400fc000; + + /// address: 0x400fc000 + /// Flash Accelerator Configuration Register. Controls flash access timing. + pub const FLASHCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, user software should not change these bits from the reset value. + reserved0: u12, + /// Flash access time. The value of this field plus 1 gives the number of CPU clocks + /// used for a flash access. Warning: improper setting of this value may result in + /// incorrect operation of the device. Other values are reserved. + FLASHTIM: u4, + /// Reserved. The value read from a reserved bit is not defined. + reserved1: u16, + }), base_address + 0x0); + + /// address: 0x400fc080 + /// PLL0 Control Register + pub const PLL0CON = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 + /// and allow it to lock to the requested frequency. See PLL0STAT register. + PLLE0: u1, + /// PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then + /// followed by a valid PLL0 feed sequence causes PLL0 to become the clock source + /// for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. + /// The PLL0 output may potentially be used to clock the USB subsystem if the + /// frequency is 48 MHz. See PLL0STAT register. + PLLC0: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x80); + + /// address: 0x400fc084 + /// PLL0 Configuration Register + pub const PLL0CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The + /// value stored here is M - 1. Note: Not all values of M are needed, and therefore + /// some are not supported by hardware. + MSEL0: u15, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + reserved0: u1, + /// PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The + /// value stored here is N - 1. Supported values for N are 1 through 32. + NSEL0: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + reserved1: u8, + }), base_address + 0x84); + + /// address: 0x400fc088 + /// PLL0 Status Register + pub const PLL0STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read-back for the PLL0 Multiplier value. This is the value currently used by + /// PLL0, and is one less than the actual multiplier. + MSEL0: u15, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Read-back for the PLL0 Pre-Divider value. This is the value currently used by + /// PLL0, and is one less than the actual divider. + NSEL0: u8, + /// Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit + /// in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When + /// zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode + /// is entered. + PLLE0_STAT: u1, + /// Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit + /// in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is + /// connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, + /// PLL0 is bypassed. This bit is automatically cleared when Power-down mode is + /// entered. + PLLC0_STAT: u1, + /// Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is + /// locked onto the requested frequency. See text for details. + PLOCK0: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u5, + }), base_address + 0x88); + + /// address: 0x400fc08c + /// PLL0 Feed Register + pub const PLL0FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// The PLL0 feed sequence must be written to this register in order for PLL0 + /// configuration and control register changes to take effect. + PLL0FEED: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8c); + + /// address: 0x400fc0a0 + /// PLL1 Control Register + pub const PLL1CON = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 + /// and allow it to lock to the requested frequency. + PLLE1: u1, + /// PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then + /// followed by a valid PLL1 feed sequence causes PLL1 to become the clock source + /// for the USB subsystem via the USB clock divider. See PLL1STAT register. + PLLC1: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0xa0); + + /// address: 0x400fc0a4 + /// PLL1 Configuration Register + pub const PLL1CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. + MSEL1: u5, + /// PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. + PSEL1: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0xa4); + + /// address: 0x400fc0a8 + /// PLL1 Status Register + pub const PLL1STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read-back for the PLL1 Multiplier value. This is the value currently used by + /// PLL1. + MSEL1: u5, + /// Read-back for the PLL1 Divider value. This is the value currently used by PLL1. + PSEL1: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u1, + /// Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When + /// zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode + /// is activated. + PLLE1_STAT: u1, + /// Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is + /// connected as the clock source for the microcontroller. When either PLLC or PLLE + /// is zero, PLL1 is bypassed and the oscillator clock is used directly by the + /// microcontroller. This bit is automatically cleared when Power-down mode is + /// activated. + PLLC1_STAT: u1, + /// Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is + /// locked onto the requested frequency. + PLOCK1: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u21, + }), base_address + 0xa8); + + /// address: 0x400fc0ac + /// PLL1 Feed Register + pub const PLL1FEED = @intToPtr(*volatile Mmio(32, packed struct { + /// The PLL1 feed sequence must be written to this register in order for PLL1 + /// configuration and control register changes to take effect. + PLL1FEED: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xac); + + /// address: 0x400fc0c0 + /// Power Control Register + pub const PCON = @intToPtr(*volatile Mmio(32, packed struct { + /// Power mode control bit 0. This bit controls entry to the Power-down mode. + PM0: u1, + /// Power mode control bit 1. This bit controls entry to the Deep Power-down mode. + PM1: u1, + /// Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry + /// will be turned off when chip Power-down mode or Deep Sleep mode is entered, + /// resulting in a further reduction in power usage. However, the possibility of + /// using Brown-Out Detect as a wake-up source from the reduced power mode will be + /// lost. When 0, the Brown-Out Detect function remains active during Power-down and + /// Deep Sleep modes. See the System Control Block chapter for details of Brown-Out + /// detection. + BODRPM: u1, + /// Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is + /// fully disabled at all times, and does not consume power. When 0, the Brown-Out + /// Detect circuitry is enabled. See the System Control Block chapter for details of + /// Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) + /// and the Brown-Out Interrupt (xx) must be disabled when software changes the + /// value of this bit. + BOGD: u1, + /// Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when + /// the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The + /// Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. + BORD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared + /// by software writing a one to this bit. + SMFLAG: u1, + /// Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. + /// Cleared by software writing a one to this bit. + DSFLAG: u1, + /// Power-down entry flag. Set when the Power-down mode is successfully entered. + /// Cleared by software writing a one to this bit. + PDFLAG: u1, + /// Deep Power-down entry flag. Set when the Deep Power-down mode is successfully + /// entered. Cleared by software writing a one to this bit. + DPDFLAG: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0xc0); + + /// address: 0x400fc0c4 + /// Power Control for Peripherals Register + pub const PCONP = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. + reserved0: u1, + /// Timer/Counter 0 power/clock control bit. + PCTIM0: u1, + /// Timer/Counter 1 power/clock control bit. + PCTIM1: u1, + /// UART0 power/clock control bit. + PCUART0: u1, + /// UART1 power/clock control bit. + PCUART1: u1, + /// Reserved. + reserved1: u1, + /// PWM1 power/clock control bit. + PCPWM1: u1, + /// The I2C0 interface power/clock control bit. + PCI2C0: u1, + /// The SPI interface power/clock control bit. + PCSPI: u1, + /// The RTC power/clock control bit. + PCRTC: u1, + /// The SSP 1 interface power/clock control bit. + PCSSP1: u1, + /// Reserved. + reserved2: u1, + /// A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the + /// AD0CR before clearing this bit, and set this bit before setting PDN. + PCADC: u1, + /// CAN Controller 1 power/clock control bit. + PCCAN1: u1, + /// CAN Controller 2 power/clock control bit. + PCCAN2: u1, + /// Power/clock control bit for IOCON, GPIO, and GPIO interrupts. + PCGPIO: u1, + /// Repetitive Interrupt Timer power/clock control bit. + PCRIT: u1, + /// Motor Control PWM + PCMCPWM: u1, + /// Quadrature Encoder Interface power/clock control bit. + PCQEI: u1, + /// The I2C1 interface power/clock control bit. + PCI2C1: u1, + /// Reserved. + reserved3: u1, + /// The SSP0 interface power/clock control bit. + PCSSP0: u1, + /// Timer 2 power/clock control bit. + PCTIM2: u1, + /// Timer 3 power/clock control bit. + PCTIM3: u1, + /// UART 2 power/clock control bit. + PCUART2: u1, + /// UART 3 power/clock control bit. + PCUART3: u1, + /// I2C interface 2 power/clock control bit. + PCI2C2: u1, + /// I2S interface power/clock control bit. + PCI2S: u1, + /// Reserved. + reserved4: u1, + /// GPDMA function power/clock control bit. + PCGPDMA: u1, + /// Ethernet block power/clock control bit. + PCENET: u1, + /// USB interface power/clock control bit. + PCUSB: u1, + }), base_address + 0xc4); + + /// address: 0x400fc104 + /// CPU Clock Configuration Register + pub const CCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. + /// 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed + /// when the PLL0 is connected, because the rate would always be greater than the + /// maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. + /// This setting is not allowed when the PLL0 is connected, because the rate would + /// always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 + /// to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. + /// ... 255 = pllclk is divided by 256 to produce the CPU clock. + CCLKSEL: u8, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x104); + + /// address: 0x400fc108 + /// USB Clock Configuration Register + pub const USBCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the divide value for creating the USB clock from the PLL0 output. Only + /// the values shown below can produce even number multiples of 48 MHz from the PLL0 + /// output. Warning: Improper setting of this value will result in incorrect + /// operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output + /// must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 + /// = PLL0 output is divided by 10. PLL0 output must be 480 MHz. + USBSEL: u4, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x108); + + /// address: 0x400fc10c + /// Clock Source Select Register + pub const CLKSRCSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source for PLL0 as follows. Warning: Improper setting of this + /// value, or an incorrect sequence of changing this value may result in incorrect + /// operation of the device. + CLKSRC: u2, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u30, + }), base_address + 0x10c); + + /// address: 0x400fc110 + /// Allows clearing the current CAN channel sleep state as well as reading that + /// state. + pub const CANSLEEPCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN + /// channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored + /// to CAN channel 1. + CAN1SLEEP: u1, + /// Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN + /// channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored + /// to CAN channel 2. + CAN2SLEEP: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x110); + + /// address: 0x400fc114 + /// Allows reading the wake-up state of the CAN channels. + pub const CANWAKEFLAGS = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge + /// has occurred on the receive data line of CAN channel 1. Write: writing a 1 + /// clears this bit. + CAN1WAKE: u1, + /// Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge + /// has occurred on the receive data line of CAN channel 2. Write: writing a 1 + /// clears this bit. + CAN2WAKE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x114); + + /// address: 0x400fc140 + /// External Interrupt Flag Register + pub const EXTINT = @intToPtr(*volatile Mmio(32, packed struct { + /// In level-sensitive mode, this bit is set if the EINT0 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT0 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT0: u1, + /// In level-sensitive mode, this bit is set if the EINT1 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT1 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT1: u1, + /// In level-sensitive mode, this bit is set if the EINT2 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT2 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT2: u1, + /// In level-sensitive mode, this bit is set if the EINT3 function is selected for + /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is + /// set if the EINT3 function is selected for its pin, and the selected edge occurs + /// on the pin. This bit is cleared by writing a one to it, except in level + /// sensitive mode when the pin is in its active state. + EINT3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x140); + + /// address: 0x400fc148 + /// External Interrupt Mode register + pub const EXTMODE = @intToPtr(*volatile Mmio(32, packed struct { + /// External interrupt 0 EINT0 mode. + EXTMODE0: u1, + /// External interrupt 1 EINT1 mode. + EXTMODE1: u1, + /// External interrupt 2 EINT2 mode. + EXTMODE2: u1, + /// External interrupt 3 EINT3 mode. + EXTMODE3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x148); + + /// address: 0x400fc14c + /// External Interrupt Polarity Register + pub const EXTPOLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// External interrupt 0 EINT0 polarity. + EXTPOLAR0: u1, + /// External interrupt 1 EINT1 polarity. + EXTPOLAR1: u1, + /// External interrupt 2 EINT2 polarity. + EXTPOLAR2: u1, + /// External interrupt 3 EINT3 polarity. + EXTPOLAR3: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x14c); + + /// address: 0x400fc180 + /// Reset Source Identification Register + pub const RSID = @intToPtr(*volatile Mmio(32, packed struct { + /// Assertion of the POR signal sets this bit, and clears all of the other bits in + /// this register. But if another Reset signal (e.g., External Reset) remains + /// asserted after the POR signal is negated, then its bit is set. This bit is not + /// affected by any of the other sources of Reset. + POR: u1, + /// Assertion of the RESET signal sets this bit. This bit is cleared only by + /// software or POR. + EXTR: u1, + /// This bit is set when the Watchdog Timer times out and the WDTRESET bit in the + /// Watchdog Mode Register is 1. This bit is cleared only by software or POR. + WDTR: u1, + /// This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD + /// reset trip level (typically 1.85 V under nominal room temperature conditions). + /// If the VDD(REG)(3V3) voltage dips from the normal operating range to below the + /// BOD reset trip level and recovers, the BODR bit will be set to 1. If the + /// VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD + /// reset trip level and continues to decline to the level at which POR is asserted + /// (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises + /// continuously from below 1 V to a level above the BOD reset trip level, the BODR + /// will be set to 1. This bit is cleared only by software or POR. Note: Only in the + /// case where a reset occurs and the POR = 0, the BODR bit indicates if the + /// VDD(REG)(3V3) voltage was below the BOD reset trip level or not. + BODR: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u28, + }), base_address + 0x180); + + /// address: 0x400fc1a0 + /// System control and status + pub const SCS = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u4, + /// Main oscillator range select. + OSCRANGE: u1, + /// Main oscillator enable. + OSCEN: u1, + /// Main oscillator status. + OSCSTAT: u1, + /// Reserved. User software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u25, + }), base_address + 0x1a0); + + /// address: 0x400fc1a8 + /// Peripheral Clock Selection register 0. + pub const PCLKSEL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock selection for WDT. + PCLK_WDT: u2, + /// Peripheral clock selection for TIMER0. + PCLK_TIMER0: u2, + /// Peripheral clock selection for TIMER1. + PCLK_TIMER1: u2, + /// Peripheral clock selection for UART0. + PCLK_UART0: u2, + /// Peripheral clock selection for UART1. + PCLK_UART1: u2, + /// Reserved. + reserved0: u2, + /// Peripheral clock selection for PWM1. + PCLK_PWM1: u2, + /// Peripheral clock selection for I2C0. + PCLK_I2C0: u2, + /// Peripheral clock selection for SPI. + PCLK_SPI: u2, + /// Reserved. + reserved1: u2, + /// Peripheral clock selection for SSP1. + PCLK_SSP1: u2, + /// Peripheral clock selection for DAC. + PCLK_DAC: u2, + /// Peripheral clock selection for ADC. + PCLK_ADC: u2, + /// Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same + /// PCLK divide value when the CAN function is used. + PCLK_CAN1: u2, + /// Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same + /// PCLK divide value when the CAN function is used. + PCLK_CAN2: u2, + /// Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 + /// must have the same PCLK divide value when the CAN function is used. + PCLK_ACF: u2, + }), base_address + 0x1a8); + + /// address: 0x400fc1ac + /// Peripheral Clock Selection register 1. + pub const PCLKSEL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock selection for the Quadrature Encoder Interface. + PCLK_QEI: u2, + /// Peripheral clock selection for GPIO interrupts. + PCLK_GPIOINT: u2, + /// Peripheral clock selection for the Pin Connect block. + PCLK_PCB: u2, + /// Peripheral clock selection for I2C1. + PCLK_I2C1: u2, + /// Reserved. + RESERVED: u2, + /// Peripheral clock selection for SSP0. + PCLK_SSP0: u2, + /// Peripheral clock selection for TIMER2. + PCLK_TIMER2: u2, + /// Peripheral clock selection for TIMER3. + PCLK_TIMER3: u2, + /// Peripheral clock selection for UART2. + PCLK_UART2: u2, + /// Peripheral clock selection for UART3. + PCLK_UART3: u2, + /// Peripheral clock selection for I2C2. + PCLK_I2C2: u2, + /// Peripheral clock selection for I2S. + PCLK_I2S: u2, + /// Reserved. + RESERVED: u2, + /// Peripheral clock selection for Repetitive Interrupt Timer. + PCLK_RIT: u2, + /// Peripheral clock selection for the System Control block. + PCLK_SYSCON: u2, + /// Peripheral clock selection for the Motor Control PWM. + PCLK_MC: u2, + }), base_address + 0x1ac); + + /// address: 0x400fc1c0 + /// USB Interrupt Status + pub const USBINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Low priority interrupt line status. This bit is read-only. + USB_INT_REQ_LP: u1, + /// High priority interrupt line status. This bit is read-only. + USB_INT_REQ_HP: u1, + /// DMA interrupt line status. This bit is read-only. + USB_INT_REQ_DMA: u1, + /// USB host interrupt line status. This bit is read-only. + USB_HOST_INT: u1, + /// External ATX interrupt line status. This bit is read-only. + USB_ATX_INT: u1, + /// OTG interrupt line status. This bit is read-only. + USB_OTG_INT: u1, + /// I2C module interrupt line status. This bit is read-only. + USB_I2C_INT: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// USB need clock indicator. This bit is read-only. This bit is set to 1 when USB + /// activity or a change of state on the USB data pins is detected, and it indicates + /// that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it + /// resets to zero 5 ms after the last packet has been received/sent, or 2 ms after + /// the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 + /// to 1 can wake up the microcontroller if activity on the USB bus is selected to + /// wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from + /// Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down + /// mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F + /// C0C4) for considerations about the PLL and invoking the Power-down mode. This + /// bit is read-only. + USB_NEED_CLK: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + /// Enable all USB interrupts. When this bit is cleared, the NVIC does not see the + /// ORed output of the USB interrupt lines. + EN_USB_INTS: u1, + }), base_address + 0x1c0); + + /// address: 0x400fc1c4 + /// Selects between alternative requests on DMA channels 0 through 7 and 10 through + /// 15 + pub const DMACREQSEL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is + /// selected. + DMASEL08: u1, + /// Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is + /// selected. + DMASEL09: u1, + /// Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer + /// 1 match 0 is selected. + DMASEL10: u1, + /// Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer + /// 1 match 1 is selected. + DMASEL11: u1, + /// Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer + /// 2 match 0 is selected. + DMASEL12: u1, + /// Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer + /// 2 match 1 is selected. + DMASEL13: u1, + /// Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S + /// channel 0 is selected. + DMASEL14: u1, + /// Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S + /// channel 1 is selected. + DMASEL15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x1c4); + + /// address: 0x400fc1c8 + /// Clock Output Configuration Register + pub const CLKOUTCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source for the CLKOUT function. Other values are reserved. Do + /// not use. + CLKOUTSEL: u4, + /// Integer value to divide the output clock by, minus one. 0 = Clock is divided by + /// 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is + /// divided by 16. + CLKOUTDIV: u4, + /// CLKOUT enable control, allows switching the CLKOUT source without glitches. + /// Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. + CLKOUT_EN: u1, + /// CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when + /// CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being + /// stopped. + CLKOUT_ACT: u1, + /// Reserved, user software should not write ones to reserved bits. The value read + /// from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x1c8); + }; + /// Ethernet + pub const EMAC = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// MAC configuration register 1. + pub const MAC1 = @intToPtr(*volatile Mmio(32, packed struct { + /// RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the + /// MAC synchronizes this control bit to the incoming receive stream. + RXENABLE: u1, + /// PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames + /// regardless of type (normal vs. Control). When disabled, the MAC does not pass + /// valid Control frames. + PARF: u1, + /// RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow + /// Control frames. When disabled, received PAUSE Flow Control frames are ignored. + RXFLOWCTRL: u1, + /// TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed + /// to be transmitted. When disabled, Flow Control frames are blocked. + TXFLOWCTRL: u1, + /// Setting this bit will cause the MAC Transmit interface to be looped back to the + /// MAC Receive interface. Clearing this bit results in normal operation. + LOOPBACK: u1, + /// Unused + RESERVED: u3, + /// Setting this bit will put the Transmit Function logic in reset. + RESETTX: u1, + /// Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic + /// implements flow control. + RESETMCSTX: u1, + /// Setting this bit will put the Ethernet receive logic in reset. + RESETRX: u1, + /// Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic + /// implements flow control. + RESETMCSRX: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// SIMULATION RESET. Setting this bit will cause a reset to the random number + /// generator within the Transmit Function. + SIMRESET: u1, + /// SOFT RESET. Setting this bit will put all modules within the MAC in reset except + /// the Host Interface. + SOFTRESET: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x0); + + /// address: 0x50000004 + /// MAC configuration register 2. + pub const MAC2 = @intToPtr(*volatile Mmio(32, packed struct { + /// When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, + /// the MAC operates in Half-Duplex mode. + FULLDUPLEX: u1, + /// FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame + /// lengths are compared to the Length/Type field. If the Length/Type field + /// represents a length then the check is performed. Mismatches are reported in the + /// StatusInfo word for each received frame. + FLC: u1, + /// HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted + /// and received. + HFEN: u1, + /// DELAYED CRC. This bit determines the number of bytes, if any, of proprietary + /// header information that exist on the front of IEEE 802.3 frames. When 1, four + /// bytes of header (ignored by the CRC function) are added. When 0, there is no + /// proprietary header. + DELAYEDCRC: u1, + /// CRC ENABLESet this bit to append a CRC to every frame whether padding was + /// required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames + /// presented to the MAC contain a CRC. + CRCEN: u1, + /// PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this + /// bit if frames presented to the MAC have a valid length. This bit is used in + /// conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad + /// Operation for details on the pad function. + PADCRCEN: u1, + /// VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 + /// bytes and append a valid CRC. Consult Table 153 - Pad Operation for more + /// information on the various padding features. Note: This bit is ignored if PAD / + /// CRC ENABLE is cleared. + VLANPADEN: u1, + /// AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the + /// type of frame, either tagged or un-tagged, by comparing the two octets following + /// the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 + /// - Pad Operation provides a description of the pad function based on the + /// configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is + /// cleared. + AUTODETPADEN: u1, + /// PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the + /// content of the preamble to ensure it contains 0x55 and is error-free. A packet + /// with an incorrect preamble is discarded. When disabled, no preamble checking is + /// performed. + PPENF: u1, + /// LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive + /// packets which contain preamble fields less than 12 bytes in length. When + /// disabled, the MAC allows any length preamble as per the Standard. + LPENF: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u2, + /// When enabled (set to 1), the MAC will immediately retransmit following a + /// collision rather than using the Binary Exponential Backoff algorithm as + /// specified in the Standard. + NOBACKOFF: u1, + /// BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally + /// causes a collision during back pressure, it will immediately retransmit without + /// backoff, reducing the chance of further collisions and ensuring transmit packets + /// get sent. + BP_NOBACKOFF: u1, + /// When enabled (set to 1) the MAC will defer to carrier indefinitely as per the + /// Standard. When disabled, the MAC will abort when the excessive deferral limit is + /// reached. + EXCESSDEFER: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u17, + }), base_address + 0x4); + + /// address: 0x50000008 + /// Back-to-Back Inter-Packet-Gap register. + pub const IPGT = @intToPtr(*volatile Mmio(32, packed struct { + /// BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the + /// nibble time offset of the minimum possible period between the end of any + /// transmitted packet to the beginning of the next. In Full-Duplex mode, the + /// register value should be the desired period in nibble times minus 3. In + /// Half-Duplex mode, the register value should be the desired period in nibble + /// times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which + /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps + /// mode). In Half-Duplex the recommended setting is 0x12 (18d), which also + /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps + /// mode). + BTOBINTEGAP: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u25, + }), base_address + 0x8); + + /// address: 0x5000000c + /// Non Back-to-Back Inter-Packet-Gap register. + pub const IPGR = @intToPtr(*volatile Mmio(32, packed struct { + /// NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field + /// representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is + /// 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 + /// us (in 10 Mbps mode). + NBTOBINTEGAP2: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field + /// representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 + /// 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC + /// defers to carrier. If, however, carrier becomes active after IPGR1, the MAC + /// continues timing IPGR2 and transmits, knowingly causing a collision, thus + /// ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The + /// recommended value is 0xC (12d) + NBTOBINTEGAP1: u7, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u17, + }), base_address + 0xc); + + /// address: 0x50000010 + /// Collision window / Retry register. + pub const CLRT = @intToPtr(*volatile Mmio(32, packed struct { + /// RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of + /// retransmission attempts following a collision before aborting the packet due to + /// excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). + /// See IEEE 802.3/4.2.3.2.5. + RETRANSMAX: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u4, + /// COLLISION WINDOW. This is a programmable field representing the slot time or + /// collision window during which collisions occur in properly configured networks. + /// The default value of 0x37 (55d) represents a 56 byte window following the + /// preamble and SFD. + COLLWIN: u6, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u18, + }), base_address + 0x10); + + /// address: 0x50000014 + /// Maximum Frame register. + pub const MAXF = @intToPtr(*volatile Mmio(32, packed struct { + /// MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a + /// maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is + /// 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a + /// shorter maximum length restriction is desired, program this 16-bit field. + MAXFLEN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x14); + + /// address: 0x50000018 + /// PHY Support register. + pub const SUPP = @intToPtr(*volatile Mmio(32, packed struct { + /// Unused + RESERVED: u8, + /// This bit configures the Reduced MII logic for the current operating speed. When + /// set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. + SPEED: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x18); + + /// address: 0x5000001c + /// Test register. + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + /// SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 + /// byte-times to 1 byte-time. + SCPQ: u1, + /// This bit causes the MAC Control sublayer to inhibit transmissions, just as if a + /// PAUSE Receive Control frame with a nonzero pause time parameter was received. + TESTPAUSE: u1, + /// TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on + /// the link. Backpressure causes preamble to be transmitted, raising carrier sense. + /// A transmit packet from the system will be sent during backpressure. + TESTBP: u1, + /// Unused + RESERVED: u29, + }), base_address + 0x1c); + + /// address: 0x50000020 + /// MII Mgmt Configuration register. + pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform + /// read cycles across a range of PHYs. When set, the MII Management hardware will + /// perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. + /// Clear this bit to allow continuous reads of the same PHY. + SCANINC: u1, + /// SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform + /// read/write cycles without the 32-bit preamble field. Clear this bit to cause + /// normal cycles to be performed. Some PHYs support suppressed preamble. + SUPPPREAMBLE: u1, + /// CLOCK SELECT. This field is used by the clock divide logic in creating the MII + /// Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. + /// Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) + /// is divided by the specified amount. Refer to Table 160 below for the definition + /// of values for this field. + CLOCKSEL: u4, + /// Unused + reserved0: u9, + /// RESET MII MGMT. This bit resets the MII Management hardware. + RESETMIIMGMT: u1, + /// Unused + reserved1: u16, + }), base_address + 0x20); + + /// address: 0x50000024 + /// MII Mgmt Command register. + pub const MCMD = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit causes the MII Management hardware to perform a single Read cycle. The + /// Read data is returned in Register MRDD (MII Mgmt Read Data). + READ: u1, + /// This bit causes the MII Management hardware to perform Read cycles continuously. + /// This is useful for monitoring Link Fail for example. + SCAN: u1, + /// Unused + RESERVED: u30, + }), base_address + 0x24); + + /// address: 0x50000028 + /// MII Mgmt Address register. + pub const MADR = @intToPtr(*volatile Mmio(32, packed struct { + /// REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt + /// cycles. Up to 32 registers can be accessed. + REGADDR: u5, + /// Unused + RESERVED: u3, + /// PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. + /// Up to 31 PHYs can be addressed (0 is reserved). + PHYADDR: u5, + /// Unused + RESERVED: u19, + }), base_address + 0x28); + + /// address: 0x5000002c + /// MII Mgmt Write Data register. + pub const MWTD = @intToPtr(*volatile Mmio(32, packed struct { + /// WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit + /// data and the pre-configured PHY and Register addresses from the MII Mgmt Address + /// register (MADR). + WRITEDATA: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x2c); + + /// address: 0x50000030 + /// MII Mgmt Read Data register. + pub const MRDD = @intToPtr(*volatile Mmio(32, packed struct { + /// READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from + /// this location. + READDATA: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x30); + + /// address: 0x50000034 + /// MII Mgmt Indicators register. + pub const MIND = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read + /// or Write cycle. + BUSY: u1, + /// When 1 is returned - indicates a scan operation (continuous MII Mgmt Read + /// cycles) is in progress. + SCANNING: u1, + /// When 1 is returned - indicates MII Mgmt Read cycle has not completed and the + /// Read Data is not yet valid. + NOTVALID: u1, + /// When 1 is returned - indicates that an MII Mgmt link fail has occurred. + MIILINKFAIL: u1, + /// Unused + RESERVED: u28, + }), base_address + 0x34); + + /// address: 0x50000040 + /// Station Address 0 register. + pub const SA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 2nd octet. This field holds the second octet of the station + /// address. + SADDR2: u8, + /// STATION ADDRESS, 1st octet. This field holds the first octet of the station + /// address. + SADDR1: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x40); + + /// address: 0x50000044 + /// Station Address 1 register. + pub const SA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 4th octet. This field holds the fourth octet of the station + /// address. + SADDR4: u8, + /// STATION ADDRESS, 3rd octet. This field holds the third octet of the station + /// address. + SADDR3: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x44); + + /// address: 0x50000048 + /// Station Address 2 register. + pub const SA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// STATION ADDRESS, 6th octet. This field holds the sixth octet of the station + /// address. + SADDR6: u8, + /// STATION ADDRESS, 5th octet. This field holds the fifth octet of the station + /// address. + SADDR5: u8, + /// Unused + RESERVED: u16, + }), base_address + 0x48); + + /// address: 0x50000100 + /// Command register. + pub const COMMAND = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable receive. + RXENABLE: u1, + /// Enable transmit. + TXENABLE: u1, + /// Unused + RESERVED: u1, + /// When a 1 is written, all datapaths and the host registers are reset. The MAC + /// needs to be reset separately. + REGRESET: u1, + /// When a 1 is written, the transmit datapath is reset. + TXRESET: u1, + /// When a 1 is written, the receive datapath is reset. + RXRESET: u1, + /// When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they + /// have a CRC error. If 0 runt frames are filtered out. + PASSRUNTFRAME: u1, + /// When set to 1 , disables receive filtering i.e. all frames received are written + /// to memory. + PASSRXFILTER: u1, + /// Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex + /// and continuous preamble in half duplex. + TXFLOWCONTROL: u1, + /// When set to 1 , RMII mode is selected; if 0, MII mode is selected. + RMII: u1, + /// When set to 1 , indicates full duplex operation. + FULLDUPLEX: u1, + /// Unused + RESERVED: u21, + }), base_address + 0x100); + + /// address: 0x50000104 + /// Status register. + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// If 1, the receive channel is active. If 0, the receive channel is inactive. + RXSTATUS: u1, + /// If 1, the transmit channel is active. If 0, the transmit channel is inactive. + TXSTATUS: u1, + /// Unused + RESERVED: u30, + }), base_address + 0x104); + + /// address: 0x50000108 + /// Receive descriptor base address register. + pub const RXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// MSBs of receive descriptor base address. + RXDESCRIPTOR: u30, + }), base_address + 0x108); + + /// address: 0x5000010c + /// Receive status base address register. + pub const RXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 000 + RESERVED: u3, + /// MSBs of receive status base address. + RXSTATUS: u29, + }), base_address + 0x10c); + + /// address: 0x50000110 + /// Receive number of descriptors register. + pub const RXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { + /// RxDescriptorNumber. Number of descriptors in the descriptor array for which + /// RxDescriptor is the base address. The number of descriptors is minus one + /// encoded. + RXDESCRIPTORN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x110); + + /// address: 0x50000114 + /// Receive produce index register. + pub const RXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// Index of the descriptor that is going to be filled next by the receive datapath. + RXPRODUCEIX: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x114); + + /// address: 0x50000118 + /// Receive consume index register. + pub const RXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// Index of the descriptor that is going to be processed next by the receive + RXCONSUMEIX: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x118); + + /// address: 0x5000011c + /// Transmit descriptor base address register. + pub const TXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// TxDescriptor. MSBs of transmit descriptor base address. + TXD: u30, + }), base_address + 0x11c); + + /// address: 0x50000120 + /// Transmit status base address register. + pub const TXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Fixed to 00 + RESERVED: u2, + /// TxStatus. MSBs of transmit status base address. + TXSTAT: u30, + }), base_address + 0x120); + + /// address: 0x50000124 + /// Transmit number of descriptors register. + pub const TXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { + /// TxDescriptorNumber. Number of descriptors in the descriptor array for which + /// TxDescriptor is the base address. The register is minus one encoded. + TXDN: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x124); + + /// address: 0x50000128 + /// Transmit produce index register. + pub const TXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// TxProduceIndex. Index of the descriptor that is going to be filled next by the + /// transmit software driver. + TXPI: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x128); + + /// address: 0x5000012c + /// Transmit consume index register. + pub const TXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { + /// TxConsumeIndex. Index of the descriptor that is going to be transmitted next by + /// the transmit datapath. + TXCI: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x12c); + + /// address: 0x50000158 + /// Transmit status vector 0 register. + pub const TSV0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC error. The attached CRC in the packet did not match the internally generated + /// CRC. + CRCERR: u1, + /// Length check error. Indicates the frame length field does not match the actual + /// number of data items and is not a type field. + LCE: u1, + /// Length out of range. Indicates that frame type/length field was larger than 1500 + /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. + /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame + /// type with the max length and gives the "Length out of range" error. In fact, + /// this bit is not an error indication, but simply a statement by the chip + /// regarding the status of the received frame. + LOR: u1, + /// Transmission of packet was completed. + DONE: u1, + /// Packet's destination was a multicast address. + MULTICAST: u1, + /// Packet's destination was a broadcast address. + BROADCAST: u1, + /// Packet was deferred for at least one attempt, but less than an excessive defer. + PACKETDEFER: u1, + /// Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps + /// or 24287 bit times in 10 Mbps mode. + EXDF: u1, + /// Excessive Collision. Packet was aborted due to exceeding of maximum allowed + /// number of collisions. + EXCOL: u1, + /// Late Collision. Collision occurred beyond collision window, 512 bit times. + LCOL: u1, + /// Byte count in frame was greater than can be represented in the transmit byte + /// count field in TSV1. + GIANT: u1, + /// Host side caused buffer underrun. + UNDERRUN: u1, + /// The total number of bytes transferred including collided attempts. + TOTALBYTES: u16, + /// The frame was a control frame. + CONTROLFRAME: u1, + /// The frame was a control frame with a valid PAUSE opcode. + PAUSE: u1, + /// Carrier-sense method backpressure was previously applied. + BACKPRESSURE: u1, + /// Frame's length/type field contained 0x8100 which is the VLAN protocol + /// identifier. + VLAN: u1, + }), base_address + 0x158); + + /// address: 0x5000015c + /// Transmit status vector 1 register. + pub const TSV1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit byte count. The total number of bytes in the frame, not counting the + /// collided bytes. + TBC: u16, + /// Transmit collision count. Number of collisions the current packet incurred + /// during transmission attempts. The maximum number of collisions (16) cannot be + /// represented. + TCC: u4, + /// Unused + RESERVED: u12, + }), base_address + 0x15c); + + /// address: 0x50000160 + /// Receive status vector register. + pub const RSV = @intToPtr(*volatile Mmio(32, packed struct { + /// Received byte count. Indicates length of received frame. + RBC: u16, + /// Packet previously ignored. Indicates that a packet was dropped. + PPI: u1, + /// RXDV event previously seen. Indicates that the last receive event seen was not + /// long enough to be a valid packet. + RXDVSEEN: u1, + /// Carrier event previously seen. Indicates that at some time since the last + /// receive statistics, a carrier event was detected. + CESEEN: u1, + /// Receive code violation. Indicates that received PHY data does not represent a + /// valid receive code. + RCV: u1, + /// CRC error. The attached CRC in the packet did not match the internally generated + /// CRC. + CRCERR: u1, + /// Length check error. Indicates the frame length field does not match the actual + /// number of data items and is not a type field. + LCERR: u1, + /// Length out of range. Indicates that frame type/length field was larger than 1518 + /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. + /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame + /// type with the max length and gives the "Length out of range" error. In fact, + /// this bit is not an error indication, but simply a statement by the chip + /// regarding the status of the received frame. + LOR: u1, + /// Receive OK. The packet had valid CRC and no symbol errors. + ROK: u1, + /// The packet destination was a multicast address. + MULTICAST: u1, + /// The packet destination was a broadcast address. + BROADCAST: u1, + /// Indicates that after the end of packet another 1-7 bits were received. A single + /// nibble, called dribble nibble, is formed but not sent out. + DRIBBLENIBBLE: u1, + /// The frame was a control frame. + CONTROLFRAME: u1, + /// The frame was a control frame with a valid PAUSE opcode. + PAUSE: u1, + /// Unsupported Opcode. The current frame was recognized as a Control Frame but + /// contains an unknown opcode. + UO: u1, + /// Frame's length/type field contained 0x8100 which is the VLAN protocol + /// identifier. + VLAN: u1, + /// Unused + RESERVED: u1, + }), base_address + 0x160); + + /// address: 0x50000170 + /// Flow control counter register. + pub const FLOWCONTROLCOUNTER = @intToPtr(*volatile Mmio(32, packed struct { + /// MirrorCounter. In full duplex mode the MirrorCounter specifies the number of + /// cycles before re-issuing the Pause control frame. + MC: u16, + /// PauseTimer. In full-duplex mode the PauseTimer specifies the value that is + /// inserted into the pause timer field of a pause flow control frame. In half + /// duplex mode the PauseTimer specifies the number of backpressure cycles. + PT: u16, + }), base_address + 0x170); + + /// address: 0x50000174 + /// Flow control status register. + pub const FLOWCONTROLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// MirrorCounterCurrent. In full duplex mode this register represents the current + /// value of the datapath's mirror counter which counts up to the value specified by + /// the MirrorCounter field in the FlowControlCounter register. In half duplex mode + /// the register counts until it reaches the value of the PauseTimer bits in the + /// FlowControlCounter register. + MCC: u16, + /// Unused + RESERVED: u16, + }), base_address + 0x174); + + /// address: 0x50000200 + /// Receive filter control register. + pub const RXFILTERCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastEn. When set to 1, all unicast frames are accepted. + AUE: u1, + /// AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. + ABE: u1, + /// AcceptMulticastEn. When set to 1, all multicast frames are accepted. + AME: u1, + /// AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash + /// filter are accepted. + AUHE: u1, + /// AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect + /// hash filter are accepted. + AMHE: u1, + /// AcceptPerfectEn. When set to 1, the frames with a destination address identical + /// to the station address are accepted. + APE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u6, + /// MagicPacketEnWoL. When set to 1, the result of the magic packet filter will + /// generate a WoL interrupt when there is a match. + MPEW: u1, + /// RxFilterEnWoL. When set to 1, the result of the perfect address matching filter + /// and the imperfect hash filter will generate a WoL interrupt when there is a + /// match. + RFEW: u1, + /// Unused + RESERVED: u18, + }), base_address + 0x200); + + /// address: 0x50000204 + /// Receive filter WoL status register. + pub const RXFILTERWOLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. + AUW: u1, + /// AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. + ABW: u1, + /// AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. + AMW: u1, + /// AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the + /// imperfect hash filter caused WoL. + AUHW: u1, + /// AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the + /// imperfect hash filter caused WoL. + AMHW: u1, + /// AcceptPerfectWoL. When the value is 1, the perfect address matching filter + /// caused WoL. + APW: u1, + /// Unused + RESERVED: u1, + /// RxFilterWoL. When the value is 1, the receive filter caused WoL. + RFW: u1, + /// MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. + MPW: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x204); + + /// address: 0x50000208 + /// Receive filter WoL clear register. + pub const RXFILTERWOLCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + AUWCLR: u1, + /// AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + ABWCLR: u1, + /// AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + AMWCLR: u1, + /// AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in + /// the RxFilterWoLStatus register is cleared. + AUHWCLR: u1, + /// AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in + /// the RxFilterWoLStatus register is cleared. + AMHWCLR: u1, + /// AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + APWCLR: u1, + /// Unused + RESERVED: u1, + /// RxFilterWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + RFWCLR: u1, + /// MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the + /// RxFilterWoLStatus register is cleared. + MPWCLR: u1, + /// Unused + RESERVED: u23, + }), base_address + 0x208); + + /// address: 0x50000210 + /// Hash filter table LSBs register. + pub const HASHFILTERL = @intToPtr(*volatile Mmio(32, packed struct { + /// HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. + HFL: u32, + }), base_address + 0x210); + + /// address: 0x50000214 + /// Hash filter table MSBs register. + pub const HASHFILTERH = @intToPtr(*volatile Mmio(32, packed struct { + /// Bits 63:32 of the imperfect filter hash table for receive filtering. + HFH: u32, + }), base_address + 0x214); + + /// address: 0x50000fe0 + /// Interrupt status register. + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt + /// should be resolved by a Rx soft-reset. The bit is not set when there is a + /// nonfatal overrun error. + RXOVERRUNINT: u1, + /// Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, + /// SymbolError, CRCError or NoDescriptor or Overrun. + RXERRORINT: u1, + /// Interrupt triggered when all receive descriptors have been processed i.e. on the + /// transition to the situation where ProduceIndex == ConsumeIndex. + RXFINISHEDINT: u1, + /// Interrupt triggered when a receive descriptor has been processed while the + /// Interrupt bit in the Control field of the descriptor was set. + RXDONEINT: u1, + /// Interrupt set on a fatal underrun error in the transmit queue. The fatal + /// interrupt should be resolved by a Tx soft-reset. The bit is not set when there + /// is a nonfatal underrun error. + TXUNDERRUNINT: u1, + /// Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and + /// ExcessiveDefer, NoDescriptor or Underrun. + TXERRORINT: u1, + /// Interrupt triggered when all transmit descriptors have been processed i.e. on + /// the transition to the situation where ProduceIndex == ConsumeIndex. + TXFINISHEDINT: u1, + /// Interrupt triggered when a descriptor has been transmitted while the Interrupt + /// bit in the Control field of the descriptor was set. + TXDONEINT: u1, + /// Unused + RESERVED: u4, + /// Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet + /// register. + SOFTINT: u1, + /// Interrupt triggered by a Wake-up event detected by the receive filter. + WAKEUPINT: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe0); + + /// address: 0x50000fe4 + /// Interrupt enable register. + pub const INTENABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable for interrupt trigger on receive buffer overrun or descriptor underrun + /// situations. + RXOVERRUNINTEN: u1, + /// Enable for interrupt trigger on receive errors. + RXERRORINTEN: u1, + /// Enable for interrupt triggered when all receive descriptors have been processed + /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + RXFINISHEDINTEN: u1, + /// Enable for interrupt triggered when a receive descriptor has been processed + /// while the Interrupt bit in the Control field of the descriptor was set. + RXDONEINTEN: u1, + /// Enable for interrupt trigger on transmit buffer or descriptor underrun + /// situations. + TXUNDERRUNINTEN: u1, + /// Enable for interrupt trigger on transmit errors. + TXERRORINTEN: u1, + /// Enable for interrupt triggered when all transmit descriptors have been processed + /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. + TXFINISHEDINTEN: u1, + /// Enable for interrupt triggered when a descriptor has been transmitted while the + /// Interrupt bit in the Control field of the descriptor was set. + TXDONEINTEN: u1, + /// Unused + RESERVED: u4, + /// Enable for interrupt triggered by the SoftInt bit in the IntStatus register, + /// caused by software writing a 1 to the SoftIntSet bit in the IntSet register. + SOFTINTEN: u1, + /// Enable for interrupt triggered by a Wake-up event detected by the receive + /// filter. + WAKEUPINTEN: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe4); + + /// address: 0x50000fe8 + /// Interrupt clear register. + pub const INTCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXOVERRUNINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXERRORINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXFINISHEDINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + RXDONEINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXUNDERRUNINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXERRORINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXFINISHEDINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + TXDONEINTCLR: u1, + /// Unused + RESERVED: u4, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + SOFTINTCLR: u1, + /// Writing a 1 clears the corresponding status bit in interrupt status register + /// IntStatus. + WAKEUPINTCLR: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfe8); + + /// address: 0x50000fec + /// Interrupt set register. + pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXOVERRUNINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXERRORINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXFINISHEDINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + RXDONEINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXUNDERRUNINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXERRORINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXFINISHEDINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + TXDONEINTSET: u1, + /// Unused + RESERVED: u4, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + SOFTINTSET: u1, + /// Writing a 1 to one sets the corresponding status bit in interrupt status + /// register IntStatus. + WAKEUPINTSET: u1, + /// Unused + RESERVED: u18, + }), base_address + 0xfec); + + /// address: 0x50000ff4 + /// Power-down register. + pub const POWERDOWN = @intToPtr(*volatile Mmio(32, packed struct { + /// Unused + RESERVED: u31, + /// PowerDownMACAHB. If true, all AHB accesses will return a read/write error, + /// except accesses to the Power-Down register. + PD: u1, + }), base_address + 0xff4); + }; + /// General purpose DMA controller + pub const GPDMA = struct { + pub const base_address = 0x50004000; + + /// address: 0x50004000 + /// DMA Interrupt Status Register + pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT0: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT1: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT2: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT3: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT4: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT5: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT6: u1, + /// Status of DMA channel interrupts after masking. Each bit represents one channel: + /// 0 - the corresponding channel has no active interrupt request. 1 - the + /// corresponding channel does have an active interrupt request. + INTSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x0); + + /// address: 0x50004004 + /// DMA Interrupt Terminal Count Request Status Register + pub const INTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT0: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT1: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT2: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT3: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT4: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT5: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT6: u1, + /// Terminal count interrupt request status for DMA channels. Each bit represents + /// one channel: 0 - the corresponding channel has no active terminal count + /// interrupt request. 1 - the corresponding channel does have an active terminal + /// count interrupt request. + INTTCSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x4); + + /// address: 0x50004008 + /// DMA Interrupt Terminal Count Request Clear Register + pub const INTTCCLEAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR0: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR1: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR2: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR3: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR4: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR5: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR6: u1, + /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA + /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - + /// clears the corresponding channel terminal count interrupt. + INTTCCLEAR7: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x8); + + /// address: 0x5000400c + /// DMA Interrupt Error Status Register + pub const INTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT0: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT1: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT2: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT3: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT4: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT5: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT6: u1, + /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - + /// the corresponding channel has no active error interrupt request. 1 - the + /// corresponding channel does have an active error interrupt request. + INTERRSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0xc); + + /// address: 0x50004010 + /// DMA Interrupt Error Clear Register + pub const INTERRCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR0: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR1: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR2: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR3: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR4: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR5: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR6: u1, + /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. + /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the + /// corresponding channel error interrupt. + INTERRCLR7: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x10); + + /// address: 0x50004014 + /// DMA Raw Interrupt Terminal Count Status Register + pub const RAWINTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT0: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT1: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT2: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT3: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT4: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT5: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT6: u1, + /// Status of the terminal count interrupt for DMA channels prior to masking. Each + /// bit represents one channel: 0 - the corresponding channel has no active terminal + /// count interrupt request. 1 - the corresponding channel does have an active + /// terminal count interrupt request. + RAWINTTCSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x14); + + /// address: 0x50004018 + /// DMA Raw Error Interrupt Status Register + pub const RAWINTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT0: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT1: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT2: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT3: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT4: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT5: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT6: u1, + /// Status of the error interrupt for DMA channels prior to masking. Each bit + /// represents one channel: 0 - the corresponding channel has no active error + /// interrupt request. 1 - the corresponding channel does have an active error + /// interrupt request. + RAWINTERRSTAT7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x18); + + /// address: 0x5000401c + /// DMA Enabled Channel Register + pub const ENBLDCHNS = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS0: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS1: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS2: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS3: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS4: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS5: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS6: u1, + /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel + /// is disabled. 1 - DMA channel is enabled. + ENABLEDCHANNELS7: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x1c); + + /// address: 0x50004020 + /// DMA Software Burst Request Register + pub const SOFTBREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ0: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ1: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ2: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ3: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ4: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ5: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ6: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ7: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ8: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ9: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ10: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ11: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ12: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ13: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ14: u1, + /// Software burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral Description (refer to Table 672 + /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA burst request for the corresponding + /// request line. + SOFTBREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x20); + + /// address: 0x50004024 + /// DMA Software Single Request Register + pub const SOFTSREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ0: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ1: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ2: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ3: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ4: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ5: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ6: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ7: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ8: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ9: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ10: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ11: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ12: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ13: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ14: u1, + /// Software single transfer request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA single transfer request for the + /// corresponding request line. + SOFTSREQ15: u1, + /// Reserved. Read undefined. Write reserved bits as zero. + RESERVED: u16, + }), base_address + 0x24); + + /// address: 0x50004028 + /// DMA Software Last Burst Request Register + pub const SOFTLBREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ0: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ1: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ2: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ3: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ4: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ5: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ6: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ7: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ8: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ9: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ10: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ11: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ12: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ13: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ14: u1, + /// Software last burst request flags for each of 16 possible sources. Each bit + /// represents one DMA request line or peripheral function: 0 - writing 0 has no + /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding + /// request line. + SOFTLBREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x28); + + /// address: 0x5000402c + /// DMA Software Last Single Request Register + pub const SOFTLSREQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ0: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ1: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ2: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ3: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ4: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ5: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ6: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ7: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ8: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ9: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ10: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ11: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ12: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ13: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ14: u1, + /// Software last single transfer request flags for each of 16 possible sources. + /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 + /// has no effect. 1 - writing 1 generates a DMA last single transfer request for + /// the corresponding request line. + SOFTLSREQ15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x2c); + + /// address: 0x50004030 + /// DMA Configuration Register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller + /// reduces power consumption. 1 = enabled. + E: u1, + /// AHB Master endianness configuration: 0 = little-endian mode (default). 1 = + /// big-endian mode. + M: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x30); + + /// address: 0x50004034 + /// DMA Synchronization Register + pub const SYNC = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC0: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC1: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC2: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC3: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC4: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC5: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC6: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC7: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC8: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC9: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC10: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC11: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC12: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC13: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC14: u1, + /// Controls the synchronization logic for DMA request signals. Each bit represents + /// one set of DMA request lines as described in the preceding text: 0 - + /// synchronization logic for the corresponding DMA request signals are enabled. 1 - + /// synchronization logic for the corresponding DMA request signals are disabled. + DMACSYNC15: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x34); + + /// address: 0x50004100 + /// DMA Channel 0 Source Address Register + pub const SRCADDR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x100); + + /// address: 0x50004120 + /// DMA Channel 0 Source Address Register + pub const SRCADDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x120); + + /// address: 0x50004140 + /// DMA Channel 0 Source Address Register + pub const SRCADDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x140); + + /// address: 0x50004160 + /// DMA Channel 0 Source Address Register + pub const SRCADDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x160); + + /// address: 0x50004180 + /// DMA Channel 0 Source Address Register + pub const SRCADDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x180); + + /// address: 0x500041a0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1a0); + + /// address: 0x500041c0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1c0); + + /// address: 0x500041e0 + /// DMA Channel 0 Source Address Register + pub const SRCADDR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA source address. Reading this register will return the current source + /// address. + SRCADDR: u32, + }), base_address + 0x1e0); + + /// address: 0x50004104 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x104); + + /// address: 0x50004124 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x124); + + /// address: 0x50004144 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x144); + + /// address: 0x50004164 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x164); + + /// address: 0x50004184 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x184); + + /// address: 0x500041a4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1a4); + + /// address: 0x500041c4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1c4); + + /// address: 0x500041e4 + /// DMA Channel 0 Destination Address Register + pub const DESTADDR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Destination address. Reading this register will return the current + /// destination address. + DESTADDR: u32, + }), base_address + 0x1e4); + + /// address: 0x50004108 + /// DMA Channel 0 Linked List Item Register + pub const LLI0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x108); + + /// address: 0x50004128 + /// DMA Channel 0 Linked List Item Register + pub const LLI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x128); + + /// address: 0x50004148 + /// DMA Channel 0 Linked List Item Register + pub const LLI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x148); + + /// address: 0x50004168 + /// DMA Channel 0 Linked List Item Register + pub const LLI3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x168); + + /// address: 0x50004188 + /// DMA Channel 0 Linked List Item Register + pub const LLI4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x188); + + /// address: 0x500041a8 + /// DMA Channel 0 Linked List Item Register + pub const LLI5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1a8); + + /// address: 0x500041c8 + /// DMA Channel 0 Linked List Item Register + pub const LLI6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1c8); + + /// address: 0x500041e8 + /// DMA Channel 0 Linked List Item Register + pub const LLI7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits + /// [1:0] are 0. + LLI: u30, + }), base_address + 0x1e8); + + /// address: 0x5000410c + /// DMA Channel 0 Control Register + pub const CONTROL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x10c); + + /// address: 0x5000412c + /// DMA Channel 0 Control Register + pub const CONTROL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x12c); + + /// address: 0x5000414c + /// DMA Channel 0 Control Register + pub const CONTROL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x14c); + + /// address: 0x5000416c + /// DMA Channel 0 Control Register + pub const CONTROL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x16c); + + /// address: 0x5000418c + /// DMA Channel 0 Control Register + pub const CONTROL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x18c); + + /// address: 0x500041ac + /// DMA Channel 0 Control Register + pub const CONTROL5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1ac); + + /// address: 0x500041cc + /// DMA Channel 0 Control Register + pub const CONTROL6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1cc); + + /// address: 0x500041ec + /// DMA Channel 0 Control Register + pub const CONTROL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size. This field sets the size of the transfer when the DMA controller + /// is the flow controller, in which case the value must be set before the channel + /// is enabled. Transfer size is updated as data transfers are completed. A read + /// from this field indicates the number of transfers completed on the destination + /// bus. Reading the register when the channel is active does not give useful + /// information because by the time that the software has processed the value read, + /// the channel might have progressed. It is intended to be used only when a channel + /// is enabled and then disabled. The transfer size value is not used if a + /// peripheral is the flow controller. + TRANSFERSIZE: u12, + /// Source burst size. Indicates the number of transfers that make up a source + /// burst. This value must be set to the burst size of the source peripheral, or if + /// the source is memory, to the memory boundary size. The burst size is the amount + /// of data that is transferred when the DMACBREQ signal goes active in the source + /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - + /// 256 + SBSIZE: u3, + /// Destination burst size. Indicates the number of transfers that make up a + /// destination burst transfer request. This value must be set to the burst size of + /// the destination peripheral or, if the destination is memory, to the memory + /// boundary size. The burst size is the amount of data that is transferred when the + /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - + /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 + DBSIZE: u3, + /// Source transfer width. The source and destination widths can be different from + /// each other. The hardware automatically packs and unpacks the data as required. + /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - + /// Reserved + SWIDTH: u3, + /// Destination transfer width. The source and destination widths can be different + /// from each other. The hardware automatically packs and unpacks the data as + /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to + /// 111 - Reserved + DWIDTH: u3, + /// Reserved, and must be written as 0. + RESERVED: u2, + /// Source increment: 0 - the source address is not incremented after each transfer. + /// 1 - the source address is incremented after each transfer. + SI: u1, + /// Destination increment: 0 - the destination address is not incremented after each + /// transfer. 1 - the destination address is incremented after each transfer. + DI: u1, + /// This is provided to the peripheral during a DMA bus access and indicates that + /// the access is in user mode or privileged mode. This information is not used in + /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. + PROT1: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is bufferable or not bufferable. This information is + /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is + /// bufferable. + PROT2: u1, + /// This is provided to the peripheral during a DMA bus access and indicates to the + /// peripheral that the access is cacheable or not cacheable. This information is + /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is + /// cacheable. + PROT3: u1, + /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is + /// disabled. 1 - the terminal count interrupt is enabled. + I: u1, + }), base_address + 0x1ec); + + /// address: 0x50004110 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x110); + + /// address: 0x50004130 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x130); + + /// address: 0x50004150 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x150); + + /// address: 0x50004170 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x170); + + /// address: 0x50004190 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x190); + + /// address: 0x500041b0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1b0); + + /// address: 0x500041d0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1d0); + + /// address: 0x500041f0 + /// DMA Channel 0 Configuration Register[1] + pub const CONFIG7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable. Reading this bit indicates whether a channel is currently + /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel + /// Enable bit status can also be found by reading the DMACEnbldChns Register. A + /// channel is enabled by setting this bit. A channel can be disabled by clearing + /// the Enable bit. This causes the current AHB transfer (if one is in progress) to + /// complete and the channel is then disabled. Any data in the FIFO of the relevant + /// channel is lost. Restarting the channel by setting the Channel Enable bit has + /// unpredictable effects, the channel must be fully re-initialized. The channel is + /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the + /// DMA transfer is completed, or if a channel error is encountered. If a channel + /// must be disabled without losing data in the FIFO, the Halt bit must be set so + /// that further DMA requests are ignored. The Active bit must then be polled until + /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the + /// Channel Enable bit can be cleared. + E: u1, + /// Source peripheral. This value selects the DMA source request peripheral. This + /// field is ignored if the source of the transfer is from memory. See Table 672 for + /// peripheral identification. + SRCPERIPHERAL: u5, + /// Destination peripheral. This value selects the DMA destination request + /// peripheral. This field is ignored if the destination of the transfer is to + /// memory. See Table 672 for peripheral identification. + DESTPERIPHERAL: u5, + /// This value indicates the type of transfer and specifies the flow controller. The + /// transfer type can be memory-to-memory, memory-to-peripheral, + /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the + /// DMA controller, the source peripheral, or the destination peripheral. Refer to + /// Table 694 for the encoding of this field. + TRANSFERTYPE: u3, + /// Interrupt error mask. When cleared, this bit masks out the error interrupt of + /// the relevant channel. + IE: u1, + /// Terminal count interrupt mask. When cleared, this bit masks out the terminal + /// count interrupt of the relevant channel. + ITC: u1, + /// Lock. When set, this bit enables locked transfers. This information is not used + /// in the LPC178x/177x. + L: u1, + /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO + /// has data. This value can be used with the Halt and Channel Enable bits to + /// cleanly disable a DMA channel. This is a read-only bit. + A: u1, + /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The + /// contents of the channel FIFO are drained. This value can be used with the Active + /// and Channel Enable bits to cleanly disable a DMA channel. + H: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u13, + }), base_address + 0x1f0); + }; + /// USB device/host/OTG controller + pub const USB = struct { + pub const base_address = 0x50008000; + + /// address: 0x50008100 + /// OTG Interrupt Status + pub const INTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer time-out. + TMR: u1, + /// Remove pull-up. This bit is set by hardware to indicate that software needs to + /// disable the D+ pull-up resistor. + REMOVE_PU: u1, + /// HNP failed. This bit is set by hardware to indicate that the HNP switching has + /// failed. + HNP_FAILURE: u1, + /// HNP succeeded. This bit is set by hardware to indicate that the HNP switching + /// has succeeded. + HNP_SUCCESS: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x100); + + /// address: 0x50008104 + /// OTG Interrupt Enable + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 1 = enable the corresponding bit in the IntSt register. + TMR_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + REMOVE_PU_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + HNP_FAILURE_EN: u1, + /// 1 = enable the corresponding bit in the IntSt register. + HNP_SUCCES_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x104); + + /// address: 0x50008108 + /// OTG Interrupt Set + pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + TMR_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + REMOVE_PU_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_FAILURE_SET: u1, + /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. + HNP_SUCCES_SET: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x108); + + /// address: 0x5000810c + /// OTG Interrupt Clear + pub const INTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + TMR_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + REMOVE_PU_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_FAILURE_CLR: u1, + /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. + HNP_SUCCES_CLR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u28, + }), base_address + 0x10c); + + /// address: 0x50008110 + /// OTG Status and Control and USB port select + pub const STCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by + /// hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section + /// 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: + /// Reserved 11: U1 = host, U2 = device In a device-only configuration, the + /// following values are allowed: 00: U1 = device. The USB device controller signals + /// are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = + /// device. The USB device controller signals are mapped to the U2 port: + /// USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. + PORT_FUNC: u2, + /// Timer scale selection. This field determines the duration of each timer count. + /// 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved + TMR_SCALE: u2, + /// Timer mode selection. 0: monoshot 1: free running + TMR_MODE: u1, + /// Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. + TMR_EN: u1, + /// Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single + /// bit control for the software to restart the timer when the timer is enabled. + TMR_RST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears + /// this bit when HNP_SUCCESS or HNP_FAILURE is set. + B_HNP_TRACK: u1, + /// Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this + /// bit when HNP_SUCCESS or HNP_FAILURE is set. + A_HNP_TRACK: u1, + /// When the B-device changes its role from peripheral to host, software sets this + /// bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit + /// when HNP_SUCCESS or HNP_FAILURE is set. + PU_REMOVED: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u5, + /// Current timer count value. + TMR_CNT: u16, + }), base_address + 0x110); + + /// address: 0x50008114 + /// OTG Timer + pub const TMR = @intToPtr(*volatile Mmio(32, packed struct { + /// The TMR interrupt is set when TMR_CNT reaches this value. + TIMEOUT_CNT: u16, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u16, + }), base_address + 0x114); + + /// address: 0x50008200 + /// USB Device Interrupt Status + pub const DEVINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// The frame interrupt occurs every 1 ms. This is used in isochronous packet + /// transfers. + FRAME: u1, + /// Fast endpoint interrupt. If an Endpoint Interrupt Priority register + /// (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to + /// this bit. + EP_FAST: u1, + /// Slow endpoints interrupt. If an Endpoint Interrupt Priority Register + /// (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be + /// routed to this bit. + EP_SLOW: u1, + /// Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer + /// to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page + /// 366. + DEV_STAT: u1, + /// The command code register (USBCmdCode) is empty (New command can be written). + CCEMPTY: u1, + /// Command data register (USBCmdData) is full (Data can be read now). + CDFULL: u1, + /// The current packet in the endpoint buffer is transferred to the CPU. + RxENDPKT: u1, + /// The number of data bytes transferred to the endpoint buffer equals the number of + /// bytes programmed in the TxPacket length register (USBTxPLen). + TxENDPKT: u1, + /// Endpoints realized. Set when Realize Endpoint register (USBReEp) or + /// MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation + /// is completed. + EP_RLZED: u1, + /// Error Interrupt. Any bus error interrupt from the USB device. Refer to Section + /// 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 + ERR_INT: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u22, + }), base_address + 0x200); + + /// address: 0x50008204 + /// USB Device Interrupt Enable + pub const DEVINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + FRAMEEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_FASTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_SLOWEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + DEV_STATEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CCEMPTYEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + CDFULLEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + RxENDPKTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + TxENDPKTEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + EP_RLZEDEN: u1, + /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the + /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table + /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt + /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the + /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. + ERR_INTEN: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x204); + + /// address: 0x50008208 + /// USB Device Interrupt Clear + pub const DEVINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + FRAMECLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_FASTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_SLOWCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + DEV_STATCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + CCEMPTYCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + CDFULLCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + RxENDPKTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + TxENDPKTCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + EP_RLZEDCLR: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// cleared. + ERR_INTCLR: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x208); + + /// address: 0x5000820c + /// USB Device Interrupt Set + pub const DEVINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + FRAMESET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_FASTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_SLOWSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + DEV_STATSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + CCEMPTYSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + CDFULLSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + RxENDPKTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + TxENDPKTSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + EP_RLZEDSET: u1, + /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is + /// set. + ERR_INTSET: u1, + /// Reserved + RESERVED: u22, + }), base_address + 0x20c); + + /// address: 0x50008210 + /// USB Command Code + pub const CMDCODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + /// The command phase: + CMD_PHASE: u8, + /// This is a multi-purpose field. When CMD_PHASE is Command or Read, this field + /// contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this + /// field contains the command write data (CMD_WDATA). + CMD_CODE_WDATA: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u8, + }), base_address + 0x210); + + /// address: 0x50008214 + /// USB Command Data + pub const CMDDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Command Read Data. + CMD_RDATA: u8, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u24, + }), base_address + 0x214); + + /// address: 0x50008218 + /// USB Receive Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Data received. + RX_DATA: u32, + }), base_address + 0x218); + + /// address: 0x5000821c + /// USB Transmit Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data. + TX_DATA: u32, + }), base_address + 0x21c); + + /// address: 0x500080dc + /// USB Receive Packet Length + pub const RXPLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// The remaining number of bytes to be read from the currently selected endpoint's + /// buffer. When this field decrements to 0, the RxENDPKT bit will be set in + /// USBDevIntSt. + PKT_LNGTH: u10, + /// Data valid. This bit is useful for isochronous endpoints. Non-isochronous + /// endpoints do not raise an interrupt when an erroneous data packet is received. + /// But invalid data packet can be produced with a bus reset. For isochronous + /// endpoints, data transfer will happen even if an erroneous packet is received. In + /// this case DV bit will not be set for the packet. + DV: u1, + /// The PKT_LNGTH field is valid and the packet is ready for reading. + PKT_RDY: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u20, + }), base_address + 0xdc); + + /// address: 0x50008224 + /// USB Transmit Packet Length + pub const TXPLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// The remaining number of bytes to be written to the selected endpoint buffer. + /// This field is decremented by 4 by hardware after each write to USBTxData. When + /// this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. + PKT_LNGTH: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x224); + + /// address: 0x50008228 + /// USB Control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Read mode control. Enables reading data from the OUT endpoint buffer for the + /// endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This + /// bit is cleared by hardware when the last word of the current packet is read from + /// USBRxData. + RD_EN: u1, + /// Write mode control. Enables writing data to the IN endpoint buffer for the + /// endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This + /// bit is cleared by hardware when the number of bytes in USBTxLen have been sent. + WR_EN: u1, + /// Logical Endpoint number. + LOG_ENDPOINT: u4, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u26, + }), base_address + 0x228); + + /// address: 0x5000822c + /// USB Device Interrupt Priority + pub const DEVINTPRI = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interrupt routing + FRAME: u1, + /// Fast endpoint interrupt routing + EP_FAST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u30, + }), base_address + 0x22c); + + /// address: 0x50008230 + /// USB Endpoint Interrupt Status + pub const EPINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST0: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST1: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST2: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST3: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST4: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST5: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST6: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST7: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST8: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST9: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST10: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST11: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST12: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST13: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST14: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST15: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST16: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST17: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST18: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST19: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST20: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST21: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST22: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST23: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST24: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST25: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST26: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST27: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST28: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST29: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST30: u1, + /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, + /// ..., 31) Interrupt received. + EPST31: u1, + }), base_address + 0x230); + + /// address: 0x50008234 + /// USB Endpoint Interrupt Enable + pub const EPINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN0: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN1: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN2: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN3: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN4: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN5: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN6: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN7: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN8: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN9: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN10: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN11: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN12: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN13: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN14: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN15: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN16: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN17: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN18: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN19: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN20: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN21: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN22: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN23: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN24: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN25: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN26: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN27: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN28: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN29: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN30: u1, + /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this + /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt + /// occurs for this endpoint. Implies Slave mode for this endpoint. + EPEN31: u1, + }), base_address + 0x234); + + /// address: 0x50008238 + /// USB Endpoint Interrupt Clear + pub const EPINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR0: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR1: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR2: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR3: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR4: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR5: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR6: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR7: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR8: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR9: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR10: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR11: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR12: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR13: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR14: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR15: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR16: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR17: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR18: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR19: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR20: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR21: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR22: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR23: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR24: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR25: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR26: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR27: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR28: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR29: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR30: u1, + /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the + /// SIE Select Endpoint/Clear Interrupt command for this endpoint. + EPCLR31: u1, + }), base_address + 0x238); + + /// address: 0x5000823c + /// USB Endpoint Interrupt Set + pub const EPINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET0: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET1: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET2: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET3: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET4: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET5: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET6: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET7: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET8: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET9: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET10: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET11: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET12: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET13: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET14: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET15: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET16: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET17: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET18: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET19: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET20: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET21: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET22: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET23: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET24: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET25: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET26: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET27: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET28: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET29: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET30: u1, + /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. + EPSET31: u1, + }), base_address + 0x23c); + + /// address: 0x50008240 + /// USB Endpoint Priority + pub const EPINTPRI = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI0: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI1: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI2: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI3: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI4: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI5: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI6: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI7: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI8: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI9: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI10: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI11: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI12: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI13: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI14: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI15: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI16: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI17: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI18: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI19: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI20: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI21: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI22: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI23: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI24: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI25: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI26: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI27: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI28: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI29: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI30: u1, + /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = + /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt + EPPRI31: u1, + }), base_address + 0x240); + + /// address: 0x50008244 + /// USB Realize Endpoint + pub const REEP = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR0: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR1: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR2: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR3: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR4: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR5: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR6: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR7: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR8: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR9: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR10: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR11: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR12: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR13: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR14: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR15: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR16: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR17: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR18: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR19: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR20: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR21: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR22: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR23: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR24: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR25: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR26: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR27: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR28: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR29: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR30: u1, + /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. + EPR31: u1, + }), base_address + 0x244); + + /// address: 0x50008248 + /// USB Endpoint Index + pub const EPIND = @intToPtr(*volatile Mmio(32, packed struct { + /// Physical endpoint number (0-31) + PHY_EP: u5, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0x248); + + /// address: 0x5000824c + /// USB MaxPacketSize + pub const MAXPSIZE = @intToPtr(*volatile Mmio(32, packed struct { + /// The maximum packet size value. + MPS: u10, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x24c); + + /// address: 0x50008250 + /// USB DMA Request Status + pub const DMARST = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must + /// be 0). + EPRST0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be + /// 0). + EPRST1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 + /// = DMA requested by endpoint xx. + EPRST31: u1, + }), base_address + 0x250); + + /// address: 0x50008254 + /// USB DMA Request Clear + pub const DMARCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit + /// must be 0). + EPRCLR0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit + /// must be 0). + EPRCLR1: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR2: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR3: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR4: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR5: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR6: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR7: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR8: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR9: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR10: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR11: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR12: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR13: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR14: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR15: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR16: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR17: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR18: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR19: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR20: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR21: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR22: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR23: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR24: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR25: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR26: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR27: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR28: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR29: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR30: u1, + /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the + /// corresponding bit in USBDMARSt. + EPRCLR31: u1, + }), base_address + 0x254); + + /// address: 0x50008258 + /// USB DMA Request Set + pub const DMARSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit + /// must be 0). + EPRSET0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit + /// must be 0). + EPRSET1: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET2: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET3: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET4: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET5: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET6: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET7: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET8: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET9: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET10: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET11: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET12: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET13: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET14: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET15: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET16: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET17: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET18: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET19: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET20: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET21: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET22: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET23: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET24: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET25: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET26: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET27: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET28: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET29: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET30: u1, + /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the + /// corresponding bit in USBDMARSt. + EPRSET31: u1, + }), base_address + 0x258); + + /// address: 0x50008280 + /// USB UDCA Head + pub const UDCAH = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. The UDCA is + /// aligned to 128-byte boundaries. + RESERVED: u7, + /// Start address of the UDCA. + UDCA_ADDR: u25, + }), base_address + 0x280); + + /// address: 0x50008284 + /// USB Endpoint DMA Status + pub const EPDMAST = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_ENABLE bit must be 0). + EP_DMA_ST0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_ENABLE bit must be 0). + EP_DMA_ST1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is + /// disabled. 1 = The DMA for endpoint EPxx is enabled. + EP_DMA_ST31: u1, + }), base_address + 0x284); + + /// address: 0x50008288 + /// USB Endpoint DMA Enable + pub const EPDMAEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_ENABLE bit value must be 0). + EP_DMA_EN0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_ENABLE bit must be 0). + EP_DMA_EN1: u1, + /// Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the + /// DMA operation for endpoint EPxx. + EP_DMA_EN: u30, + }), base_address + 0x288); + + /// address: 0x5000828c + /// USB Endpoint DMA Disable + pub const EPDMADIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the + /// EP0_DMA_DISABLE bit value must be 0). + EP_DMA_DIS0: u1, + /// Control endpoint IN (DMA cannot be enabled for this endpoint and the + /// EP1_DMA_DISABLE bit value must be 0). + EP_DMA_DIS1: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS2: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS3: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS4: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS5: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS6: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS7: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS8: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS9: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS10: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS11: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS12: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS13: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS14: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS15: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS16: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS17: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS18: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS19: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS20: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS21: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS22: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS23: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS24: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS25: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS26: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS27: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS28: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS29: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS30: u1, + /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable + /// the DMA operation for endpoint EPxx. + EP_DMA_DIS31: u1, + }), base_address + 0x28c); + + /// address: 0x50008290 + /// USB DMA Interrupt Status + pub const DMAINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// End of Transfer Interrupt bit. + EOT: u1, + /// New DD Request Interrupt bit. + NDDR: u1, + /// System Error Interrupt bit. + ERR: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u29, + }), base_address + 0x290); + + /// address: 0x50008294 + /// USB DMA Interrupt Enable + pub const DMAINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// End of Transfer Interrupt enable bit. + EOT: u1, + /// New DD Request Interrupt enable bit. + NDDR: u1, + /// System Error Interrupt enable bit. + ERR: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u29, + }), base_address + 0x294); + + /// address: 0x500082a0 + /// USB End of Transfer Interrupt Status + pub const EOTINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no + /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of + /// Transfer Interrupt request for endpoint xx. + EPTXINTST31: u1, + }), base_address + 0x2a0); + + /// address: 0x500082a4 + /// USB End of Transfer Interrupt Clear + pub const EOTINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTCLR31: u1, + }), base_address + 0x2a4); + + /// address: 0x500082a8 + /// USB End of Transfer Interrupt Set + pub const EOTINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No + /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt + /// register. + EPTXINTSET31: u1, + }), base_address + 0x2a8); + + /// address: 0x500082ac + /// USB New DD Request Interrupt Status + pub const NDDRINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD + /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for + /// endpoint xx. + EPNDDINTST31: u1, + }), base_address + 0x2ac); + + /// address: 0x500082b0 + /// USB New DD Request Interrupt Clear + pub const NDDRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = + /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTCLR31: u1, + }), base_address + 0x2b0); + + /// address: 0x500082b4 + /// USB New DD Request Interrupt Set + pub const NDDRINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set + /// the EPxx new DD interrupt request in the USBNDDRIntSt register. + EPNDDINTSET31: u1, + }), base_address + 0x2b4); + + /// address: 0x500082b8 + /// USB System Error Interrupt Status + pub const SYSERRINTST = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST0: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST1: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST2: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST3: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST4: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST5: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST6: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST7: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST8: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST9: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST10: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST11: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST12: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST13: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST14: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST15: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST16: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST17: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST18: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST19: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST20: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST21: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST22: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST23: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST24: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST25: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST26: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST27: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST28: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST29: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST30: u1, + /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no + /// System Error Interrupt request for endpoint xx. 1 = There is a System Error + /// Interrupt request for endpoint xx. + EPERRINTST31: u1, + }), base_address + 0x2b8); + + /// address: 0x500082bc + /// USB System Error Interrupt Clear + pub const SYSERRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR0: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR1: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR2: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR3: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR4: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR5: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR6: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR7: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR8: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR9: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR10: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR11: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR12: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR13: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR14: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR15: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR16: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR17: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR18: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR19: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR20: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR21: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR22: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR23: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR24: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR25: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR26: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR27: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR28: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR29: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR30: u1, + /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. + /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt + /// register. + EPERRINTCLR31: u1, + }), base_address + 0x2bc); + + /// address: 0x500082c0 + /// USB System Error Interrupt Set + pub const SYSERRINTSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET0: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET1: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET2: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET3: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET4: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET5: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET6: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET7: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET8: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET9: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET10: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET11: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET12: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET13: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET14: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET15: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET16: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET17: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET18: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET19: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET20: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET21: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET22: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET23: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET24: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET25: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET26: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET27: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET28: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET29: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET30: u1, + /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 + /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. + EPERRINTSET31: u1, + }), base_address + 0x2c0); + + /// address: 0x50008300 + /// I2C Receive + pub const I2C_RX = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive data. + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x50008300 + /// I2C Transmit + pub const I2C_WO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit data. + TXDATA: u8, + /// When 1, issue a START condition before transmitting this byte. + START: u1, + /// When 1, issue a STOP condition after transmitting this byte. + STOP: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u22, + }), base_address + 0x300); + + /// address: 0x50008304 + /// I2C Status + pub const I2C_STS = @intToPtr(*volatile Mmio(32, packed struct { + /// Transaction Done Interrupt. This flag is set if a transaction completes + /// successfully. It is cleared by writing a one to bit 0 of the status register. It + /// is unaffected by slave transactions. + TDI: u1, + /// Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT + /// is high, then this I2C has lost the arbitration to another device on the bus. + /// The Arbitration Failure bit is set when this happens. It is cleared by writing a + /// one to bit 1 of the status register. + AFI: u1, + /// No Acknowledge Interrupt. After every byte of data is sent, the transmitter + /// expects an acknowledge from the receiver. This bit is set if the acknowledge is + /// not received. It is cleared when a byte is written to the master TX FIFO. + NAI: u1, + /// Master Data Request Interrupt. Once a transmission is started, the transmitter + /// must have data to transmit as long as it isn't followed by a stop condition or + /// it will hold SCL low until more data is available. The Master Data Request bit + /// is set when the master transmitter is data-starved. If the master TX FIFO is + /// empty and the last byte did not have a STOP condition flag, then SCL is held low + /// until the CPU writes another byte to transmit. This bit is cleared when a byte + /// is written to the master TX FIFO. + DRMI: u1, + /// Slave Data Request Interrupt. Once a transmission is started, the transmitter + /// must have data to transmit as long as it isn't followed by a STOP condition or + /// it will hold SCL low until more data is available. The Slave Data Request bit is + /// set when the slave transmitter is data-starved. If the slave TX FIFO is empty + /// and the last byte transmitted was acknowledged, then SCL is held low until the + /// CPU writes another byte to transmit. This bit is cleared when a byte is written + /// to the slave Tx FIFO. + DRSI: u1, + /// Indicates whether the bus is busy. This bit is set when a START condition has + /// been seen. It is cleared when a STOP condition is seen.. + Active: u1, + /// The current value of the SCL signal. + SCL: u1, + /// The current value of the SDA signal. + SDA: u1, + /// Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot + /// accept any more data. It is cleared when the RX FIFO is not full. If a byte + /// arrives when the Receive FIFO is full, the SCL is held low until the CPU reads + /// the RX FIFO and makes room for it. + RFF: u1, + /// Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the + /// RX FIFO contains valid data. + RFE: u1, + /// Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the + /// TX FIFO is not full. + TFF: u1, + /// Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when + /// the TX FIFO contains valid data. + TFE: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u20, + }), base_address + 0x304); + + /// address: 0x50008308 + /// I2C Control + pub const I2C_CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that + /// this I2C issued a STOP condition. + TDIE: u1, + /// Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt + /// which is asserted during transmission when trying to set SDA high, but the bus + /// is driven low by another device. + AFIE: u1, + /// Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt + /// signalling that transmitted byte was not acknowledged. + NAIE: u1, + /// Master Transmitter Data Request Interrupt Enable. This enables the DRMI + /// interrupt which signals that the master transmitter has run out of data, has not + /// issued a STOP, and is holding the SCL line low. + DRMIE: u1, + /// Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt + /// which signals that the slave transmitter has run out of data and the last byte + /// was acknowledged, so the SCL line is being held low. + DRSIE: u1, + /// Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt + /// to indicate that the receive FIFO cannot accept any more data. + REFIE: u1, + /// Receive Data Available Interrupt Enable. This enables the DAI interrupt to + /// indicate that data is available in the receive FIFO (i.e. not empty). + RFDAIE: u1, + /// Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full + /// interrupt to indicate that the more data can be written to the transmit FIFO. + /// Note that this is not full. It is intended help the CPU to write to the I2C + /// block only when there is room in the FIFO and do this without polling the status + /// register. + TFFIE: u1, + /// Soft reset. This is only needed in unusual circumstances. If a device issues a + /// start condition without issuing a stop condition. A system timer may be used to + /// reset the I2C if the bus remains busy longer than the time-out period. On a soft + /// reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all + /// internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and + /// I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. + SRST: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u23, + }), base_address + 0x308); + + /// address: 0x5000830c + /// I2C Clock High + pub const I2C_CLKHI = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divisor high. This value is the number of 48 MHz clocks the serial clock + /// (SCL) will be high. + CDHI: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x30c); + + /// address: 0x50008310 + /// I2C Clock Low + pub const I2C_CLKLO = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divisor low. This value is the number of 48 MHz clocks the serial clock + /// (SCL) will be low. + CDLO: u8, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u24, + }), base_address + 0x310); + + /// address: 0x50008ff4 + /// USB Clock Control + pub const USBCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Device clock enable. Enables the usbclk input to the device controller + DEV_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Port select register clock enable. + PORTSEL_CLK_EN: u1, + /// AHB clock enable + AHB_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff4); + + /// address: 0x50008ff4 + /// OTG clock controller + pub const OTGCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Host clock enable + HOST_CLK_EN: u1, + /// Device clock enable + DEV_CLK_EN: u1, + /// I2C clock enable + I2C_CLK_EN: u1, + /// OTG clock enable. In device-only applications, this bit enables access to the + /// PORTSEL register. + OTG_CLK_EN: u1, + /// AHB master clock enable + AHB_CLK_EN: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff4); + + /// address: 0x50008ff8 + /// USB Clock Status + pub const USBCLKST = @intToPtr(*volatile Mmio(32, packed struct { + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Device clock on. The usbclk input to the device controller is active . + DEV_CLK_ON: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u1, + /// Port select register clock on. + PORTSEL_CLK_ON: u1, + /// AHB clock on. + AHB_CLK_ON: u1, + /// Reserved. The value read from a reserved bit is not defined. + RESERVED: u27, + }), base_address + 0xff8); + + /// address: 0x50008ff8 + /// OTG clock status + pub const OTGCLKST = @intToPtr(*volatile Mmio(32, packed struct { + /// Host clock status. + HOST_CLK_ON: u1, + /// Device clock status. + DEV_CLK_ON: u1, + /// I2C clock status. + I2C_CLK_ON: u1, + /// OTG clock status. + OTG_CLK_ON: u1, + /// AHB master clock status. + AHB_CLK_ON: u1, + /// Reserved. Read value is undefined, only zero should be written. + RESERVED: u27, + }), base_address + 0xff8); + }; + /// General Purpose I/O + pub const GPIO = struct { + pub const base_address = 0x2009c000; + + /// address: 0x2009c000 + /// GPIO Port Direction control register. + pub const DIR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x0); + + /// address: 0x2009c020 + /// GPIO Port Direction control register. + pub const DIR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x20); + + /// address: 0x2009c040 + /// GPIO Port Direction control register. + pub const DIR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x40); + + /// address: 0x2009c060 + /// GPIO Port Direction control register. + pub const DIR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x60); + + /// address: 0x2009c080 + /// GPIO Port Direction control register. + pub const DIR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR0: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR1: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR2: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR3: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR4: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR5: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR6: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR7: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR8: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR9: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR10: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR11: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR12: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR13: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR14: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR15: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR16: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR17: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR18: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR19: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR20: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR21: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR22: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR23: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR24: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR25: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR26: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR27: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR28: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR29: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR30: u1, + /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 + /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is + /// output. + PINDIR31: u1, + }), base_address + 0x80); + + /// address: 0x2009c010 + /// Mask register for Port. + pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x10); + + /// address: 0x2009c030 + /// Mask register for Port. + pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x30); + + /// address: 0x2009c050 + /// Mask register for Port. + pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x50); + + /// address: 0x2009c070 + /// Mask register for Port. + pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x70); + + /// address: 0x2009c090 + /// Mask register for Port. + pub const MASK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK0: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK1: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK2: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK3: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK4: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK5: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK6: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK7: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK8: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK9: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK10: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK11: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK12: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK13: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK14: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK15: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK16: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK17: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK18: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK19: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK20: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK21: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK22: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK23: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK24: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK25: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK26: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK27: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK28: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK29: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK30: u1, + /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes + /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be + /// read from the PINx register. 1 = Controlled pin is not affected by writes into + /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this + /// bit will not be updated with the state of the physical pin. + PINMASK31: u1, + }), base_address + 0x90); + + /// address: 0x2009c014 + /// Port Pin value register using FIOMASK. + pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x14); + + /// address: 0x2009c034 + /// Port Pin value register using FIOMASK. + pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x34); + + /// address: 0x2009c054 + /// Port Pin value register using FIOMASK. + pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x54); + + /// address: 0x2009c074 + /// Port Pin value register using FIOMASK. + pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x74); + + /// address: 0x2009c094 + /// Port Pin value register using FIOMASK. + pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL0: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL1: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL2: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL3: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL4: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL5: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL6: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL7: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL8: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL9: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL10: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL11: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL12: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL13: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL14: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL15: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL16: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL17: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL18: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL19: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL20: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL21: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL22: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL23: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL24: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL25: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL26: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL27: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL28: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL29: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL30: u1, + /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 + /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = + /// Controlled pin output is set to HIGH. + PINVAL31: u1, + }), base_address + 0x94); + + /// address: 0x2009c018 + /// Port Output Set register using FIOMASK. + pub const SET0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x18); + + /// address: 0x2009c038 + /// Port Output Set register using FIOMASK. + pub const SET1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x38); + + /// address: 0x2009c058 + /// Port Output Set register using FIOMASK. + pub const SET2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x58); + + /// address: 0x2009c078 + /// Port Output Set register using FIOMASK. + pub const SET3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x78); + + /// address: 0x2009c098 + /// Port Output Set register using FIOMASK. + pub const SET4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET0: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET1: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET2: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET3: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET4: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET5: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET6: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET7: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET8: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET9: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET10: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET11: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET12: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET13: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET14: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET15: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET16: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET17: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET18: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET19: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET20: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET21: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET22: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET23: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET24: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET25: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET26: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET27: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET28: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET29: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET30: u1, + /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in + /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to HIGH. + PINSET31: u1, + }), base_address + 0x98); + + /// address: 0x2009c01c + /// Port Output Clear register using FIOMASK. + pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x1c); + + /// address: 0x2009c03c + /// Port Output Clear register using FIOMASK. + pub const CLR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x3c); + + /// address: 0x2009c05c + /// Port Output Clear register using FIOMASK. + pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x5c); + + /// address: 0x2009c07c + /// Port Output Clear register using FIOMASK. + pub const CLR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x7c); + + /// address: 0x2009c09c + /// Port Output Clear register using FIOMASK. + pub const CLR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR0: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR1: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR2: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR3: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR4: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR5: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR6: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR7: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR8: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR9: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR10: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR11: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR12: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR13: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR14: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR15: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR16: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR17: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR18: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR19: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR20: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR21: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR22: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR23: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR24: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR25: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR26: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR27: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR28: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR29: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR30: u1, + /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in + /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled + /// pin output is set to LOW. + PINCLR31: u1, + }), base_address + 0x9c); + }; }; const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm }; -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - WDT: InterruptVector = makeUnhandledHandler("WDT"), - TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), - TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), - TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), - TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), - UART0: InterruptVector = makeUnhandledHandler("UART0"), - UART1: InterruptVector = makeUnhandledHandler("UART1"), - UART2: InterruptVector = makeUnhandledHandler("UART2"), - UART3: InterruptVector = makeUnhandledHandler("UART3"), - PWM1: InterruptVector = makeUnhandledHandler("PWM1"), - I2C0: InterruptVector = makeUnhandledHandler("I2C0"), - I2C1: InterruptVector = makeUnhandledHandler("I2C1"), - I2C2: InterruptVector = makeUnhandledHandler("I2C2"), - SPI: InterruptVector = makeUnhandledHandler("SPI"), - SSP0: InterruptVector = makeUnhandledHandler("SSP0"), - SSP1: InterruptVector = makeUnhandledHandler("SSP1"), - PLL0: InterruptVector = makeUnhandledHandler("PLL0"), - RTC: InterruptVector = makeUnhandledHandler("RTC"), - EINT0: InterruptVector = makeUnhandledHandler("EINT0"), - EINT1: InterruptVector = makeUnhandledHandler("EINT1"), - EINT2: InterruptVector = makeUnhandledHandler("EINT2"), - EINT3: InterruptVector = makeUnhandledHandler("EINT3"), - ADC: InterruptVector = makeUnhandledHandler("ADC"), - BOD: InterruptVector = makeUnhandledHandler("BOD"), - USB: InterruptVector = makeUnhandledHandler("USB"), - CAN: InterruptVector = makeUnhandledHandler("CAN"), - DMA: InterruptVector = makeUnhandledHandler("DMA"), - I2S: InterruptVector = makeUnhandledHandler("I2S"), - ENET: InterruptVector = makeUnhandledHandler("ENET"), - RIT: InterruptVector = makeUnhandledHandler("RIT"), - MCPWM: InterruptVector = makeUnhandledHandler("MCPWM"), - QEI: InterruptVector = makeUnhandledHandler("QEI"), - PLL1: InterruptVector = makeUnhandledHandler("PLL1"), - USBActivity: InterruptVector = makeUnhandledHandler("USBActivity"), - CANActivity: InterruptVector = makeUnhandledHandler("CANActivity"), +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, }; diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig index 97e4fec..ccde288 100644 --- a/src/modules/chips/nrf52/registers.zig +++ b/src/modules/chips/nrf52/registers.zig @@ -1,21145 +1,16848 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on nrf52 version 1 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "nrf52"; - -/// Factory Information Configuration Registers -pub const FICR = extern struct { - pub const Address: u32 = 0x10000000; - - /// Code memory page size - pub const CODEPAGESIZE = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Code memory size - pub const CODESIZE = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Device address type - pub const DEVICEADDRTYPE = mmio(Address + 0x000000a0, 32, packed struct { - /// Device address type - DEVICEADDRTYPE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Device identifier - pub const DEVICEID = @intToPtr(*volatile [2]u32, Address + 0x00000060); - /// Description collection[0]: Encryption Root, word 0 - pub const ER = @intToPtr(*volatile [4]u32, Address + 0x00000080); - /// Description collection[0]: Identity Root, word 0 - pub const IR = @intToPtr(*volatile [4]u32, Address + 0x00000090); - /// Description collection[0]: Device address 0 - pub const DEVICEADDR = @intToPtr(*volatile [2]u32, Address + 0x000000a4); - - pub const INFO = struct { - - /// Part code - pub const PART = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Part Variant, Hardware version and Production configuration - pub const VARIANT = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Package option - pub const PACKAGE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// RAM variant - pub const RAM = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Flash variant - pub const FLASH = @intToPtr(*volatile u32, Address + 0x00000010); - /// Description collection[0]: Unspecified - pub const UNUSED0 = @intToPtr(*volatile [3]u32, Address + 0x00000014); - }; +// this file is generated by regz +// +// vendor: Nordic Semiconductor +// device: nrf52 +// cpu: CM4 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + POWER_CLOCK: InterruptVector = unhandled, + RADIO: InterruptVector = unhandled, + UARTE0_UART0: InterruptVector = unhandled, + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = unhandled, + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = unhandled, + NFCT: InterruptVector = unhandled, + GPIOTE: InterruptVector = unhandled, + SAADC: InterruptVector = unhandled, + TIMER0: InterruptVector = unhandled, + TIMER1: InterruptVector = unhandled, + TIMER2: InterruptVector = unhandled, + RTC0: InterruptVector = unhandled, + TEMP: InterruptVector = unhandled, + RNG: InterruptVector = unhandled, + ECB: InterruptVector = unhandled, + CCM_AAR: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + RTC1: InterruptVector = unhandled, + QDEC: InterruptVector = unhandled, + COMP_LPCOMP: InterruptVector = unhandled, + SWI0_EGU0: InterruptVector = unhandled, + SWI1_EGU1: InterruptVector = unhandled, + SWI2_EGU2: InterruptVector = unhandled, + SWI3_EGU3: InterruptVector = unhandled, + SWI4_EGU4: InterruptVector = unhandled, + SWI5_EGU5: InterruptVector = unhandled, + TIMER3: InterruptVector = unhandled, + TIMER4: InterruptVector = unhandled, + PWM0: InterruptVector = unhandled, + PDM: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, + MWU: InterruptVector = unhandled, + PWM1: InterruptVector = unhandled, + PWM2: InterruptVector = unhandled, + SPIM2_SPIS2_SPI2: InterruptVector = unhandled, + RTC2: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + FPU: InterruptVector = unhandled, +}; - pub const TEMP = struct { +pub const registers = struct { + /// Factory Information Configuration Registers + pub const FICR = struct { + pub const base_address = 0x10000000; - /// Slope definition A0. - pub const A0 = mmio(Address + 0x00000000, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A1. - pub const A1 = mmio(Address + 0x00000004, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A2. - pub const A2 = mmio(Address + 0x00000008, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A3. - pub const A3 = mmio(Address + 0x0000000c, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A4. - pub const A4 = mmio(Address + 0x00000010, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope definition A5. - pub const A5 = mmio(Address + 0x00000014, 32, packed struct { - /// A (slope definition) register. - A: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B0. - pub const B0 = mmio(Address + 0x00000018, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B1. - pub const B1 = mmio(Address + 0x0000001c, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B2. - pub const B2 = mmio(Address + 0x00000020, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B3. - pub const B3 = mmio(Address + 0x00000024, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B4. - pub const B4 = mmio(Address + 0x00000028, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept B5. - pub const B5 = mmio(Address + 0x0000002c, 32, packed struct { - /// B (y-intercept) - B: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T0. - pub const T0 = mmio(Address + 0x00000030, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T1. - pub const T1 = mmio(Address + 0x00000034, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T2. - pub const T2 = mmio(Address + 0x00000038, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T3. - pub const T3 = mmio(Address + 0x0000003c, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Segment end T4. - pub const T4 = mmio(Address + 0x00000040, 32, packed struct { - /// T (segment end)register. - T: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + /// address: 0x10000010 + /// Code memory page size + pub const CODEPAGESIZE = @intToPtr(*volatile u32, base_address + 0x10); - pub const NFC = struct { - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER0 = mmio(Address + 0x00000000, 32, packed struct { - /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F - MFGID: u8 = 0, - /// Unique identifier byte 1 - UD1: u8 = 0, - /// Unique identifier byte 2 - UD2: u8 = 0, - /// Unique identifier byte 3 - UD3: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER1 = mmio(Address + 0x00000004, 32, packed struct { - /// Unique identifier byte 4 - UD4: u8 = 0, - /// Unique identifier byte 5 - UD5: u8 = 0, - /// Unique identifier byte 6 - UD6: u8 = 0, - /// Unique identifier byte 7 - UD7: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER2 = mmio(Address + 0x00000008, 32, packed struct { - /// Unique identifier byte 8 - UD8: u8 = 0, - /// Unique identifier byte 9 - UD9: u8 = 0, - /// Unique identifier byte 10 - UD10: u8 = 0, - /// Unique identifier byte 11 - UD11: u8 = 0, - }); - - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER3 = mmio(Address + 0x0000000c, 32, packed struct { - /// Unique identifier byte 12 - UD12: u8 = 0, - /// Unique identifier byte 13 - UD13: u8 = 0, - /// Unique identifier byte 14 - UD14: u8 = 0, - /// Unique identifier byte 15 - UD15: u8 = 0, - }); - }; -}; + /// address: 0x10000014 + /// Code memory size + pub const CODESIZE = @intToPtr(*volatile u32, base_address + 0x14); -/// User Information Configuration Registers -pub const UICR = extern struct { - pub const Address: u32 = 0x10001000; - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Unspecified - pub const UNUSED1 = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Unspecified - pub const UNUSED2 = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Unspecified - pub const UNUSED3 = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Access Port protection - pub const APPROTECT = mmio(Address + 0x00000208, 32, packed struct { - /// Enable or disable Access Port protection. Any other value than 0xFF being - /// written to this field will enable protection. - PALL: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - pub const NFCPINS = mmio(Address + 0x0000020c, 32, packed struct { - /// Setting of pins dedicated to NFC functionality - PROTECT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Reserved for Nordic firmware design - pub const NRFFW = @intToPtr(*volatile [15]u32, Address + 0x00000014); - /// Description collection[0]: Reserved for Nordic hardware design - pub const NRFHW = @intToPtr(*volatile [12]u32, Address + 0x00000050); - /// Description collection[0]: Reserved for customer - pub const CUSTOMER = @intToPtr(*volatile [32]u32, Address + 0x00000080); - /// Description collection[0]: Mapping of the nRESET function (see POWER chapter - /// for details) - pub const PSELRESET = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// GPIO number P0.n onto which Reset is exposed - PIN: u6 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }), Address + 0x00000200); -}; + /// address: 0x10000060 + /// Description collection[0]: Device identifier + pub const DEVICEID = @intToPtr(*volatile [2]u32, base_address + 0x60); -/// Block Protect -pub const BPROT = extern struct { - pub const Address: u32 = 0x40000000; - - /// Block protect configuration register 0 - pub const CONFIG0 = mmio(Address + 0x00000600, 32, packed struct { - /// Enable protection for region 0. Write '0' has no effect. - REGION0: u1 = 0, - /// Enable protection for region 1. Write '0' has no effect. - REGION1: u1 = 0, - /// Enable protection for region 2. Write '0' has no effect. - REGION2: u1 = 0, - /// Enable protection for region 3. Write '0' has no effect. - REGION3: u1 = 0, - /// Enable protection for region 4. Write '0' has no effect. - REGION4: u1 = 0, - /// Enable protection for region 5. Write '0' has no effect. - REGION5: u1 = 0, - /// Enable protection for region 6. Write '0' has no effect. - REGION6: u1 = 0, - /// Enable protection for region 7. Write '0' has no effect. - REGION7: u1 = 0, - /// Enable protection for region 8. Write '0' has no effect. - REGION8: u1 = 0, - /// Enable protection for region 9. Write '0' has no effect. - REGION9: u1 = 0, - /// Enable protection for region 10. Write '0' has no effect. - REGION10: u1 = 0, - /// Enable protection for region 11. Write '0' has no effect. - REGION11: u1 = 0, - /// Enable protection for region 12. Write '0' has no effect. - REGION12: u1 = 0, - /// Enable protection for region 13. Write '0' has no effect. - REGION13: u1 = 0, - /// Enable protection for region 14. Write '0' has no effect. - REGION14: u1 = 0, - /// Enable protection for region 15. Write '0' has no effect. - REGION15: u1 = 0, - /// Enable protection for region 16. Write '0' has no effect. - REGION16: u1 = 0, - /// Enable protection for region 17. Write '0' has no effect. - REGION17: u1 = 0, - /// Enable protection for region 18. Write '0' has no effect. - REGION18: u1 = 0, - /// Enable protection for region 19. Write '0' has no effect. - REGION19: u1 = 0, - /// Enable protection for region 20. Write '0' has no effect. - REGION20: u1 = 0, - /// Enable protection for region 21. Write '0' has no effect. - REGION21: u1 = 0, - /// Enable protection for region 22. Write '0' has no effect. - REGION22: u1 = 0, - /// Enable protection for region 23. Write '0' has no effect. - REGION23: u1 = 0, - /// Enable protection for region 24. Write '0' has no effect. - REGION24: u1 = 0, - /// Enable protection for region 25. Write '0' has no effect. - REGION25: u1 = 0, - /// Enable protection for region 26. Write '0' has no effect. - REGION26: u1 = 0, - /// Enable protection for region 27. Write '0' has no effect. - REGION27: u1 = 0, - /// Enable protection for region 28. Write '0' has no effect. - REGION28: u1 = 0, - /// Enable protection for region 29. Write '0' has no effect. - REGION29: u1 = 0, - /// Enable protection for region 30. Write '0' has no effect. - REGION30: u1 = 0, - /// Enable protection for region 31. Write '0' has no effect. - REGION31: u1 = 0, - }); - - /// Block protect configuration register 1 - pub const CONFIG1 = mmio(Address + 0x00000604, 32, packed struct { - /// Enable protection for region 32. Write '0' has no effect. - REGION32: u1 = 0, - /// Enable protection for region 33. Write '0' has no effect. - REGION33: u1 = 0, - /// Enable protection for region 34. Write '0' has no effect. - REGION34: u1 = 0, - /// Enable protection for region 35. Write '0' has no effect. - REGION35: u1 = 0, - /// Enable protection for region 36. Write '0' has no effect. - REGION36: u1 = 0, - /// Enable protection for region 37. Write '0' has no effect. - REGION37: u1 = 0, - /// Enable protection for region 38. Write '0' has no effect. - REGION38: u1 = 0, - /// Enable protection for region 39. Write '0' has no effect. - REGION39: u1 = 0, - /// Enable protection for region 40. Write '0' has no effect. - REGION40: u1 = 0, - /// Enable protection for region 41. Write '0' has no effect. - REGION41: u1 = 0, - /// Enable protection for region 42. Write '0' has no effect. - REGION42: u1 = 0, - /// Enable protection for region 43. Write '0' has no effect. - REGION43: u1 = 0, - /// Enable protection for region 44. Write '0' has no effect. - REGION44: u1 = 0, - /// Enable protection for region 45. Write '0' has no effect. - REGION45: u1 = 0, - /// Enable protection for region 46. Write '0' has no effect. - REGION46: u1 = 0, - /// Enable protection for region 47. Write '0' has no effect. - REGION47: u1 = 0, - /// Enable protection for region 48. Write '0' has no effect. - REGION48: u1 = 0, - /// Enable protection for region 49. Write '0' has no effect. - REGION49: u1 = 0, - /// Enable protection for region 50. Write '0' has no effect. - REGION50: u1 = 0, - /// Enable protection for region 51. Write '0' has no effect. - REGION51: u1 = 0, - /// Enable protection for region 52. Write '0' has no effect. - REGION52: u1 = 0, - /// Enable protection for region 53. Write '0' has no effect. - REGION53: u1 = 0, - /// Enable protection for region 54. Write '0' has no effect. - REGION54: u1 = 0, - /// Enable protection for region 55. Write '0' has no effect. - REGION55: u1 = 0, - /// Enable protection for region 56. Write '0' has no effect. - REGION56: u1 = 0, - /// Enable protection for region 57. Write '0' has no effect. - REGION57: u1 = 0, - /// Enable protection for region 58. Write '0' has no effect. - REGION58: u1 = 0, - /// Enable protection for region 59. Write '0' has no effect. - REGION59: u1 = 0, - /// Enable protection for region 60. Write '0' has no effect. - REGION60: u1 = 0, - /// Enable protection for region 61. Write '0' has no effect. - REGION61: u1 = 0, - /// Enable protection for region 62. Write '0' has no effect. - REGION62: u1 = 0, - /// Enable protection for region 63. Write '0' has no effect. - REGION63: u1 = 0, - }); - - /// Disable protection mechanism in debug interface mode - pub const DISABLEINDEBUG = mmio(Address + 0x00000608, 32, packed struct { - /// Disable the protection mechanism for NVM regions while in debug interface - /// mode. This register will only disable the protection mechanism if the device - /// is in debug interface mode. - DISABLEINDEBUG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x0000060c); - - /// Block protect configuration register 2 - pub const CONFIG2 = mmio(Address + 0x00000610, 32, packed struct { - /// Enable protection for region 64. Write '0' has no effect. - REGION64: u1 = 0, - /// Enable protection for region 65. Write '0' has no effect. - REGION65: u1 = 0, - /// Enable protection for region 66. Write '0' has no effect. - REGION66: u1 = 0, - /// Enable protection for region 67. Write '0' has no effect. - REGION67: u1 = 0, - /// Enable protection for region 68. Write '0' has no effect. - REGION68: u1 = 0, - /// Enable protection for region 69. Write '0' has no effect. - REGION69: u1 = 0, - /// Enable protection for region 70. Write '0' has no effect. - REGION70: u1 = 0, - /// Enable protection for region 71. Write '0' has no effect. - REGION71: u1 = 0, - /// Enable protection for region 72. Write '0' has no effect. - REGION72: u1 = 0, - /// Enable protection for region 73. Write '0' has no effect. - REGION73: u1 = 0, - /// Enable protection for region 74. Write '0' has no effect. - REGION74: u1 = 0, - /// Enable protection for region 75. Write '0' has no effect. - REGION75: u1 = 0, - /// Enable protection for region 76. Write '0' has no effect. - REGION76: u1 = 0, - /// Enable protection for region 77. Write '0' has no effect. - REGION77: u1 = 0, - /// Enable protection for region 78. Write '0' has no effect. - REGION78: u1 = 0, - /// Enable protection for region 79. Write '0' has no effect. - REGION79: u1 = 0, - /// Enable protection for region 80. Write '0' has no effect. - REGION80: u1 = 0, - /// Enable protection for region 81. Write '0' has no effect. - REGION81: u1 = 0, - /// Enable protection for region 82. Write '0' has no effect. - REGION82: u1 = 0, - /// Enable protection for region 83. Write '0' has no effect. - REGION83: u1 = 0, - /// Enable protection for region 84. Write '0' has no effect. - REGION84: u1 = 0, - /// Enable protection for region 85. Write '0' has no effect. - REGION85: u1 = 0, - /// Enable protection for region 86. Write '0' has no effect. - REGION86: u1 = 0, - /// Enable protection for region 87. Write '0' has no effect. - REGION87: u1 = 0, - /// Enable protection for region 88. Write '0' has no effect. - REGION88: u1 = 0, - /// Enable protection for region 89. Write '0' has no effect. - REGION89: u1 = 0, - /// Enable protection for region 90. Write '0' has no effect. - REGION90: u1 = 0, - /// Enable protection for region 91. Write '0' has no effect. - REGION91: u1 = 0, - /// Enable protection for region 92. Write '0' has no effect. - REGION92: u1 = 0, - /// Enable protection for region 93. Write '0' has no effect. - REGION93: u1 = 0, - /// Enable protection for region 94. Write '0' has no effect. - REGION94: u1 = 0, - /// Enable protection for region 95. Write '0' has no effect. - REGION95: u1 = 0, - }); - - /// Block protect configuration register 3 - pub const CONFIG3 = mmio(Address + 0x00000614, 32, packed struct { - /// Enable protection for region 96. Write '0' has no effect. - REGION96: u1 = 0, - /// Enable protection for region 97. Write '0' has no effect. - REGION97: u1 = 0, - /// Enable protection for region 98. Write '0' has no effect. - REGION98: u1 = 0, - /// Enable protection for region 99. Write '0' has no effect. - REGION99: u1 = 0, - /// Enable protection for region 100. Write '0' has no effect. - REGION100: u1 = 0, - /// Enable protection for region 101. Write '0' has no effect. - REGION101: u1 = 0, - /// Enable protection for region 102. Write '0' has no effect. - REGION102: u1 = 0, - /// Enable protection for region 103. Write '0' has no effect. - REGION103: u1 = 0, - /// Enable protection for region 104. Write '0' has no effect. - REGION104: u1 = 0, - /// Enable protection for region 105. Write '0' has no effect. - REGION105: u1 = 0, - /// Enable protection for region 106. Write '0' has no effect. - REGION106: u1 = 0, - /// Enable protection for region 107. Write '0' has no effect. - REGION107: u1 = 0, - /// Enable protection for region 108. Write '0' has no effect. - REGION108: u1 = 0, - /// Enable protection for region 109. Write '0' has no effect. - REGION109: u1 = 0, - /// Enable protection for region 110. Write '0' has no effect. - REGION110: u1 = 0, - /// Enable protection for region 111. Write '0' has no effect. - REGION111: u1 = 0, - /// Enable protection for region 112. Write '0' has no effect. - REGION112: u1 = 0, - /// Enable protection for region 113. Write '0' has no effect. - REGION113: u1 = 0, - /// Enable protection for region 114. Write '0' has no effect. - REGION114: u1 = 0, - /// Enable protection for region 115. Write '0' has no effect. - REGION115: u1 = 0, - /// Enable protection for region 116. Write '0' has no effect. - REGION116: u1 = 0, - /// Enable protection for region 117. Write '0' has no effect. - REGION117: u1 = 0, - /// Enable protection for region 118. Write '0' has no effect. - REGION118: u1 = 0, - /// Enable protection for region 119. Write '0' has no effect. - REGION119: u1 = 0, - /// Enable protection for region 120. Write '0' has no effect. - REGION120: u1 = 0, - /// Enable protection for region 121. Write '0' has no effect. - REGION121: u1 = 0, - /// Enable protection for region 122. Write '0' has no effect. - REGION122: u1 = 0, - /// Enable protection for region 123. Write '0' has no effect. - REGION123: u1 = 0, - /// Enable protection for region 124. Write '0' has no effect. - REGION124: u1 = 0, - /// Enable protection for region 125. Write '0' has no effect. - REGION125: u1 = 0, - /// Enable protection for region 126. Write '0' has no effect. - REGION126: u1 = 0, - /// Enable protection for region 127. Write '0' has no effect. - REGION127: u1 = 0, - }); -}; + /// address: 0x10000080 + /// Description collection[0]: Encryption Root, word 0 + pub const ER = @intToPtr(*volatile [4]u32, base_address + 0x80); -/// Power control -pub const POWER = extern struct { - pub const Address: u32 = 0x40000000; - - /// Enable constant latency mode - pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, Address + 0x00000078); - - /// Enable low power mode (variable latency) - pub const TASKS_LOWPWR = @intToPtr(*volatile u32, Address + 0x0000007c); - - /// Power failure warning - pub const EVENTS_POFWARN = @intToPtr(*volatile u32, Address + 0x00000108); - - /// CPU entered WFI/WFE sleep - pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, Address + 0x00000114); - - /// CPU exited WFI/WFE sleep - pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for POFWARN event - POFWARN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for SLEEPENTER event - SLEEPENTER: u1 = 0, - /// Write '1' to Enable interrupt for SLEEPEXIT event - SLEEPEXIT: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for POFWARN event - POFWARN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for SLEEPENTER event - SLEEPENTER: u1 = 0, - /// Write '1' to Disable interrupt for SLEEPEXIT event - SLEEPEXIT: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reset reason - pub const RESETREAS = mmio(Address + 0x00000400, 32, packed struct { - /// Reset from pin-reset detected - RESETPIN: u1 = 0, - /// Reset from watchdog detected - DOG: u1 = 0, - /// Reset from soft reset detected - SREQ: u1 = 0, - /// Reset from CPU lock-up detected - LOCKUP: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// DETECT signal from GPIO - OFF: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// ANADETECT signal from LPCOMP - LPCOMP: u1 = 0, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// entering into debug interface mode - DIF: u1 = 0, - /// Reset due to wake up from System OFF mode by NFC field detect - NFC: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM status register - pub const RAMSTATUS = mmio(Address + 0x00000428, 32, packed struct { - /// RAM block 0 is on or off/powering up - RAMBLOCK0: u1 = 0, - /// RAM block 1 is on or off/powering up - RAMBLOCK1: u1 = 0, - /// RAM block 2 is on or off/powering up - RAMBLOCK2: u1 = 0, - /// RAM block 3 is on or off/powering up - RAMBLOCK3: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System OFF register - pub const SYSTEMOFF = mmio(Address + 0x00000500, 32, packed struct { - /// Enable System OFF mode - SYSTEMOFF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Power failure comparator configuration - pub const POFCON = mmio(Address + 0x00000510, 32, packed struct { - /// Enable or disable power failure comparator - POF: u1 = 0, - /// Power failure comparator threshold setting - THRESHOLD: u4 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// General purpose retention register - pub const GPREGRET = mmio(Address + 0x0000051c, 32, packed struct { - /// General purpose retention register - GPREGRET: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// General purpose retention register - pub const GPREGRET2 = mmio(Address + 0x00000520, 32, packed struct { - /// General purpose retention register - GPREGRET: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMON = mmio(Address + 0x00000524, 32, packed struct { - /// Keep RAM block 0 on or off in system ON Mode - ONRAM0: u1 = 0, - /// Keep RAM block 1 on or off in system ON Mode - ONRAM1: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Keep retention on RAM block 0 when RAM block is switched off - OFFRAM0: u1 = 0, - /// Keep retention on RAM block 1 when RAM block is switched off - OFFRAM1: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMONB = mmio(Address + 0x00000554, 32, packed struct { - /// Keep RAM block 2 on or off in system ON Mode - ONRAM2: u1 = 0, - /// Keep RAM block 3 on or off in system ON Mode - ONRAM3: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Keep retention on RAM block 2 when RAM block is switched off - OFFRAM2: u1 = 0, - /// Keep retention on RAM block 3 when RAM block is switched off - OFFRAM3: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DC/DC enable register - pub const DCDCEN = mmio(Address + 0x00000578, 32, packed struct { - /// Enable or disable DC/DC converter - DCDCEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x10000090 + /// Description collection[0]: Identity Root, word 0 + pub const IR = @intToPtr(*volatile [4]u32, base_address + 0x90); -/// Clock control -pub const CLOCK = extern struct { - pub const Address: u32 = 0x40000000; - - /// Start HFCLK crystal oscillator - pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop HFCLK crystal oscillator - pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start LFCLK source - pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop LFCLK source - pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Start calibration of LFRC oscillator - pub const TASKS_CAL = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Start calibration timer - pub const TASKS_CTSTART = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Stop calibration timer - pub const TASKS_CTSTOP = @intToPtr(*volatile u32, Address + 0x00000018); - - /// HFCLK oscillator started - pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// LFCLK started - pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Calibration of LFCLK RC oscillator complete event - pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Calibration timer timeout - pub const EVENTS_CTTO = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Enable interrupt for CTTO event - CTTO: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Disable interrupt for CTTO event - CTTO: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status indicating that HFCLKSTART task has been triggered - pub const HFCLKRUN = mmio(Address + 0x00000408, 32, packed struct { - /// HFCLKSTART task triggered or not - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// HFCLK status - pub const HFCLKSTAT = mmio(Address + 0x0000040c, 32, packed struct { - /// Source of HFCLK - SRC: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// HFCLK state - STATE: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status indicating that LFCLKSTART task has been triggered - pub const LFCLKRUN = mmio(Address + 0x00000414, 32, packed struct { - /// LFCLKSTART task triggered or not - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// LFCLK status - pub const LFCLKSTAT = mmio(Address + 0x00000418, 32, packed struct { - /// Source of LFCLK - SRC: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// LFCLK state - STATE: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - pub const LFCLKSRCCOPY = mmio(Address + 0x0000041c, 32, packed struct { - /// Clock source - SRC: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock source for the LFCLK - pub const LFCLKSRC = mmio(Address + 0x00000518, 32, packed struct { - /// Clock source - SRC: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable bypass of LFCLK crystal oscillator with external clock - /// source - BYPASS: u1 = 0, - /// Enable or disable external source for LFCLK - EXTERNAL: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration timer interval - pub const CTIV = mmio(Address + 0x00000538, 32, packed struct { - /// Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds - /// to 31.75 seconds. - CTIV: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clocking options for the Trace Port debug interface - pub const TRACECONFIG = mmio(Address + 0x0000055c, 32, packed struct { - /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock - /// divided by two. - TRACEPORTSPEED: u2 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Pin multiplexing of trace signals. - TRACEMUX: u2 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x100000a0 + /// Device address type + pub const DEVICEADDRTYPE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa0); + + /// address: 0x100000a4 + /// Description collection[0]: Device address 0 + pub const DEVICEADDR = @intToPtr(*volatile [2]u32, base_address + 0xa4); + + /// Device info + pub const INFO = struct { + + /// address: 0x10000000 + /// Part code + pub const PART = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x10000004 + /// Part Variant, Hardware version and Production configuration + pub const VARIANT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x10000008 + /// Package option + pub const PACKAGE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x1000000c + /// RAM variant + pub const RAM = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x10000010 + /// Flash variant + pub const FLASH = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x10000014 + /// Description collection[0]: Unspecified + pub const UNUSED0 = @intToPtr(*volatile [3]u32, base_address + 0x14); + }; + + /// Registers storing factory TEMP module linearization coefficients + pub const TEMP = struct { + + /// address: 0x10000000 + /// Slope definition A0. + pub const A0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x10000004 + /// Slope definition A1. + pub const A1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x10000008 + /// Slope definition A2. + pub const A2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x1000000c + /// Slope definition A3. + pub const A3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0xc); + + /// address: 0x10000010 + /// Slope definition A4. + pub const A4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x10); + + /// address: 0x10000014 + /// Slope definition A5. + pub const A5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A (slope definition) register. + A: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x10000018 + /// y-intercept B0. + pub const B0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x18); + + /// address: 0x1000001c + /// y-intercept B1. + pub const B1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x10000020 + /// y-intercept B2. + pub const B2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x10000024 + /// y-intercept B3. + pub const B3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x24); + + /// address: 0x10000028 + /// y-intercept B4. + pub const B4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x28); + + /// address: 0x1000002c + /// y-intercept B5. + pub const B5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// B (y-intercept) + B: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x2c); + + /// address: 0x10000030 + /// Segment end T0. + pub const T0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x10000034 + /// Segment end T1. + pub const T1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x34); + + /// address: 0x10000038 + /// Segment end T2. + pub const T2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x38); + + /// address: 0x1000003c + /// Segment end T3. + pub const T3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x10000040 + /// Segment end T4. + pub const T4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// T (segment end)register. + T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x40); + }; + + pub const NFC = struct { + + /// address: 0x10000000 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + MFGID: u8, + /// Unique identifier byte 1 + UD1: u8, + /// Unique identifier byte 2 + UD2: u8, + /// Unique identifier byte 3 + UD3: u8, + }), base_address + 0x0); + + /// address: 0x10000004 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 4 + UD4: u8, + /// Unique identifier byte 5 + UD5: u8, + /// Unique identifier byte 6 + UD6: u8, + /// Unique identifier byte 7 + UD7: u8, + }), base_address + 0x4); + + /// address: 0x10000008 + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 8 + UD8: u8, + /// Unique identifier byte 9 + UD9: u8, + /// Unique identifier byte 10 + UD10: u8, + /// Unique identifier byte 11 + UD11: u8, + }), base_address + 0x8); + + /// address: 0x1000000c + /// Default header for NFC Tag. Software can read these values to populate + /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + pub const TAGHEADER3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Unique identifier byte 12 + UD12: u8, + /// Unique identifier byte 13 + UD13: u8, + /// Unique identifier byte 14 + UD14: u8, + /// Unique identifier byte 15 + UD15: u8, + }), base_address + 0xc); + }; + }; + /// User Information Configuration Registers + pub const UICR = struct { + pub const base_address = 0x10001000; + + /// address: 0x10001000 + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x10001004 + /// Unspecified + pub const UNUSED1 = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x10001008 + /// Unspecified + pub const UNUSED2 = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x10001010 + /// Unspecified + pub const UNUSED3 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x10001014 + /// Description collection[0]: Reserved for Nordic firmware design + pub const NRFFW = @intToPtr(*volatile [15]u32, base_address + 0x14); + + /// address: 0x10001050 + /// Description collection[0]: Reserved for Nordic hardware design + pub const NRFHW = @intToPtr(*volatile [12]u32, base_address + 0x50); + + /// address: 0x10001080 + /// Description collection[0]: Reserved for customer + pub const CUSTOMER = @intToPtr(*volatile [32]u32, base_address + 0x80); + + /// address: 0x10001200 + /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for + /// details) + pub const PSELRESET = @intToPtr(*volatile [2]Mmio(32, packed struct{ + /// GPIO number P0.n onto which Reset is exposed + PIN: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x200); + + /// address: 0x10001208 + /// Access Port protection + pub const APPROTECT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable Access Port protection. Any other value than 0xFF being + /// written to this field will enable protection. + PALL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x208); + + /// address: 0x1000120c + /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + pub const NFCPINS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Setting of pins dedicated to NFC functionality + PROTECT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20c); + }; + /// Block Protect + pub const BPROT = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000600 + /// Block protect configuration register 0 + pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 0. Write '0' has no effect. + REGION0: u1, + /// Enable protection for region 1. Write '0' has no effect. + REGION1: u1, + /// Enable protection for region 2. Write '0' has no effect. + REGION2: u1, + /// Enable protection for region 3. Write '0' has no effect. + REGION3: u1, + /// Enable protection for region 4. Write '0' has no effect. + REGION4: u1, + /// Enable protection for region 5. Write '0' has no effect. + REGION5: u1, + /// Enable protection for region 6. Write '0' has no effect. + REGION6: u1, + /// Enable protection for region 7. Write '0' has no effect. + REGION7: u1, + /// Enable protection for region 8. Write '0' has no effect. + REGION8: u1, + /// Enable protection for region 9. Write '0' has no effect. + REGION9: u1, + /// Enable protection for region 10. Write '0' has no effect. + REGION10: u1, + /// Enable protection for region 11. Write '0' has no effect. + REGION11: u1, + /// Enable protection for region 12. Write '0' has no effect. + REGION12: u1, + /// Enable protection for region 13. Write '0' has no effect. + REGION13: u1, + /// Enable protection for region 14. Write '0' has no effect. + REGION14: u1, + /// Enable protection for region 15. Write '0' has no effect. + REGION15: u1, + /// Enable protection for region 16. Write '0' has no effect. + REGION16: u1, + /// Enable protection for region 17. Write '0' has no effect. + REGION17: u1, + /// Enable protection for region 18. Write '0' has no effect. + REGION18: u1, + /// Enable protection for region 19. Write '0' has no effect. + REGION19: u1, + /// Enable protection for region 20. Write '0' has no effect. + REGION20: u1, + /// Enable protection for region 21. Write '0' has no effect. + REGION21: u1, + /// Enable protection for region 22. Write '0' has no effect. + REGION22: u1, + /// Enable protection for region 23. Write '0' has no effect. + REGION23: u1, + /// Enable protection for region 24. Write '0' has no effect. + REGION24: u1, + /// Enable protection for region 25. Write '0' has no effect. + REGION25: u1, + /// Enable protection for region 26. Write '0' has no effect. + REGION26: u1, + /// Enable protection for region 27. Write '0' has no effect. + REGION27: u1, + /// Enable protection for region 28. Write '0' has no effect. + REGION28: u1, + /// Enable protection for region 29. Write '0' has no effect. + REGION29: u1, + /// Enable protection for region 30. Write '0' has no effect. + REGION30: u1, + /// Enable protection for region 31. Write '0' has no effect. + REGION31: u1, + }), base_address + 0x600); + + /// address: 0x40000604 + /// Block protect configuration register 1 + pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 32. Write '0' has no effect. + REGION32: u1, + /// Enable protection for region 33. Write '0' has no effect. + REGION33: u1, + /// Enable protection for region 34. Write '0' has no effect. + REGION34: u1, + /// Enable protection for region 35. Write '0' has no effect. + REGION35: u1, + /// Enable protection for region 36. Write '0' has no effect. + REGION36: u1, + /// Enable protection for region 37. Write '0' has no effect. + REGION37: u1, + /// Enable protection for region 38. Write '0' has no effect. + REGION38: u1, + /// Enable protection for region 39. Write '0' has no effect. + REGION39: u1, + /// Enable protection for region 40. Write '0' has no effect. + REGION40: u1, + /// Enable protection for region 41. Write '0' has no effect. + REGION41: u1, + /// Enable protection for region 42. Write '0' has no effect. + REGION42: u1, + /// Enable protection for region 43. Write '0' has no effect. + REGION43: u1, + /// Enable protection for region 44. Write '0' has no effect. + REGION44: u1, + /// Enable protection for region 45. Write '0' has no effect. + REGION45: u1, + /// Enable protection for region 46. Write '0' has no effect. + REGION46: u1, + /// Enable protection for region 47. Write '0' has no effect. + REGION47: u1, + /// Enable protection for region 48. Write '0' has no effect. + REGION48: u1, + /// Enable protection for region 49. Write '0' has no effect. + REGION49: u1, + /// Enable protection for region 50. Write '0' has no effect. + REGION50: u1, + /// Enable protection for region 51. Write '0' has no effect. + REGION51: u1, + /// Enable protection for region 52. Write '0' has no effect. + REGION52: u1, + /// Enable protection for region 53. Write '0' has no effect. + REGION53: u1, + /// Enable protection for region 54. Write '0' has no effect. + REGION54: u1, + /// Enable protection for region 55. Write '0' has no effect. + REGION55: u1, + /// Enable protection for region 56. Write '0' has no effect. + REGION56: u1, + /// Enable protection for region 57. Write '0' has no effect. + REGION57: u1, + /// Enable protection for region 58. Write '0' has no effect. + REGION58: u1, + /// Enable protection for region 59. Write '0' has no effect. + REGION59: u1, + /// Enable protection for region 60. Write '0' has no effect. + REGION60: u1, + /// Enable protection for region 61. Write '0' has no effect. + REGION61: u1, + /// Enable protection for region 62. Write '0' has no effect. + REGION62: u1, + /// Enable protection for region 63. Write '0' has no effect. + REGION63: u1, + }), base_address + 0x604); + + /// address: 0x40000608 + /// Disable protection mechanism in debug interface mode + pub const DISABLEINDEBUG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x608); + + /// address: 0x4000060c + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x60c); + + /// address: 0x40000610 + /// Block protect configuration register 2 + pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 64. Write '0' has no effect. + REGION64: u1, + /// Enable protection for region 65. Write '0' has no effect. + REGION65: u1, + /// Enable protection for region 66. Write '0' has no effect. + REGION66: u1, + /// Enable protection for region 67. Write '0' has no effect. + REGION67: u1, + /// Enable protection for region 68. Write '0' has no effect. + REGION68: u1, + /// Enable protection for region 69. Write '0' has no effect. + REGION69: u1, + /// Enable protection for region 70. Write '0' has no effect. + REGION70: u1, + /// Enable protection for region 71. Write '0' has no effect. + REGION71: u1, + /// Enable protection for region 72. Write '0' has no effect. + REGION72: u1, + /// Enable protection for region 73. Write '0' has no effect. + REGION73: u1, + /// Enable protection for region 74. Write '0' has no effect. + REGION74: u1, + /// Enable protection for region 75. Write '0' has no effect. + REGION75: u1, + /// Enable protection for region 76. Write '0' has no effect. + REGION76: u1, + /// Enable protection for region 77. Write '0' has no effect. + REGION77: u1, + /// Enable protection for region 78. Write '0' has no effect. + REGION78: u1, + /// Enable protection for region 79. Write '0' has no effect. + REGION79: u1, + /// Enable protection for region 80. Write '0' has no effect. + REGION80: u1, + /// Enable protection for region 81. Write '0' has no effect. + REGION81: u1, + /// Enable protection for region 82. Write '0' has no effect. + REGION82: u1, + /// Enable protection for region 83. Write '0' has no effect. + REGION83: u1, + /// Enable protection for region 84. Write '0' has no effect. + REGION84: u1, + /// Enable protection for region 85. Write '0' has no effect. + REGION85: u1, + /// Enable protection for region 86. Write '0' has no effect. + REGION86: u1, + /// Enable protection for region 87. Write '0' has no effect. + REGION87: u1, + /// Enable protection for region 88. Write '0' has no effect. + REGION88: u1, + /// Enable protection for region 89. Write '0' has no effect. + REGION89: u1, + /// Enable protection for region 90. Write '0' has no effect. + REGION90: u1, + /// Enable protection for region 91. Write '0' has no effect. + REGION91: u1, + /// Enable protection for region 92. Write '0' has no effect. + REGION92: u1, + /// Enable protection for region 93. Write '0' has no effect. + REGION93: u1, + /// Enable protection for region 94. Write '0' has no effect. + REGION94: u1, + /// Enable protection for region 95. Write '0' has no effect. + REGION95: u1, + }), base_address + 0x610); + + /// address: 0x40000614 + /// Block protect configuration register 3 + pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable protection for region 96. Write '0' has no effect. + REGION96: u1, + /// Enable protection for region 97. Write '0' has no effect. + REGION97: u1, + /// Enable protection for region 98. Write '0' has no effect. + REGION98: u1, + /// Enable protection for region 99. Write '0' has no effect. + REGION99: u1, + /// Enable protection for region 100. Write '0' has no effect. + REGION100: u1, + /// Enable protection for region 101. Write '0' has no effect. + REGION101: u1, + /// Enable protection for region 102. Write '0' has no effect. + REGION102: u1, + /// Enable protection for region 103. Write '0' has no effect. + REGION103: u1, + /// Enable protection for region 104. Write '0' has no effect. + REGION104: u1, + /// Enable protection for region 105. Write '0' has no effect. + REGION105: u1, + /// Enable protection for region 106. Write '0' has no effect. + REGION106: u1, + /// Enable protection for region 107. Write '0' has no effect. + REGION107: u1, + /// Enable protection for region 108. Write '0' has no effect. + REGION108: u1, + /// Enable protection for region 109. Write '0' has no effect. + REGION109: u1, + /// Enable protection for region 110. Write '0' has no effect. + REGION110: u1, + /// Enable protection for region 111. Write '0' has no effect. + REGION111: u1, + /// Enable protection for region 112. Write '0' has no effect. + REGION112: u1, + /// Enable protection for region 113. Write '0' has no effect. + REGION113: u1, + /// Enable protection for region 114. Write '0' has no effect. + REGION114: u1, + /// Enable protection for region 115. Write '0' has no effect. + REGION115: u1, + /// Enable protection for region 116. Write '0' has no effect. + REGION116: u1, + /// Enable protection for region 117. Write '0' has no effect. + REGION117: u1, + /// Enable protection for region 118. Write '0' has no effect. + REGION118: u1, + /// Enable protection for region 119. Write '0' has no effect. + REGION119: u1, + /// Enable protection for region 120. Write '0' has no effect. + REGION120: u1, + /// Enable protection for region 121. Write '0' has no effect. + REGION121: u1, + /// Enable protection for region 122. Write '0' has no effect. + REGION122: u1, + /// Enable protection for region 123. Write '0' has no effect. + REGION123: u1, + /// Enable protection for region 124. Write '0' has no effect. + REGION124: u1, + /// Enable protection for region 125. Write '0' has no effect. + REGION125: u1, + /// Enable protection for region 126. Write '0' has no effect. + REGION126: u1, + /// Enable protection for region 127. Write '0' has no effect. + REGION127: u1, + }), base_address + 0x614); + }; + /// Power control + pub const POWER = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000078 + /// Enable constant latency mode + pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x4000007c + /// Enable low power mode (variable latency) + pub const TASKS_LOWPWR = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x40000108 + /// Power failure warning + pub const EVENTS_POFWARN = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40000114 + /// CPU entered WFI/WFE sleep + pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40000118 + /// CPU exited WFI/WFE sleep + pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40000304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for POFWARN event + POFWARN: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER: u1, + /// Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x304); + + /// address: 0x40000308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for POFWARN event + POFWARN: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER: u1, + /// Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x40000400 + /// Reset reason + pub const RESETREAS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset from pin-reset detected + RESETPIN: u1, + /// Reset from watchdog detected + DOG: u1, + /// Reset from soft reset detected + SREQ: u1, + /// Reset from CPU lock-up detected + LOCKUP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT + /// signal from GPIO + OFF: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from + /// ANADETECT signal from LPCOMP + LPCOMP: u1, + /// Reset due to wake up from System OFF mode when wakeup is triggered from entering + /// into debug interface mode + DIF: u1, + /// Reset due to wake up from System OFF mode by NFC field detect + NFC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x400); + + /// address: 0x40000428 + /// Deprecated register - RAM status register + pub const RAMSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// RAM block 0 is on or off/powering up + RAMBLOCK0: u1, + /// RAM block 1 is on or off/powering up + RAMBLOCK1: u1, + /// RAM block 2 is on or off/powering up + RAMBLOCK2: u1, + /// RAM block 3 is on or off/powering up + RAMBLOCK3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x428); + + /// address: 0x40000500 + /// System OFF register + pub const SYSTEMOFF = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40000510 + /// Power failure comparator configuration + pub const POFCON = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable power failure comparator + POF: u1, + /// Power failure comparator threshold setting + THRESHOLD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x510); + + /// address: 0x4000051c + /// General purpose retention register + pub const GPREGRET = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); -/// 2.4 GHz Radio -pub const RADIO = extern struct { - pub const Address: u32 = 0x40001000; - - /// Enable RADIO in TX mode - pub const TASKS_TXEN = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Enable RADIO in RX mode - pub const TASKS_RXEN = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start RADIO - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop RADIO - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Disable RADIO - pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Start the RSSI and take one single sample of the receive signal strength. - pub const TASKS_RSSISTART = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Stop the RSSI measurement - pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, Address + 0x00000018); - - /// Start the bit counter - pub const TASKS_BCSTART = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Stop the bit counter - pub const TASKS_BCSTOP = @intToPtr(*volatile u32, Address + 0x00000020); - - /// RADIO has ramped up and is ready to be started - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Address sent or received - pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Packet payload sent or received - pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Packet sent or received - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// RADIO has been disabled - pub const EVENTS_DISABLED = @intToPtr(*volatile u32, Address + 0x00000110); - - /// A device address match occurred on the last received packet - pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, Address + 0x00000114); - - /// No device address match occurred on the last received packet - pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Sampling of receive signal strength complete. - pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Bit counter reached bit count value. - pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Packet received with CRC ok - pub const EVENTS_CRCOK = @intToPtr(*volatile u32, Address + 0x00000130); - - /// Packet received with CRC error - pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, Address + 0x00000134); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and START task - READY_START: u1 = 0, - /// Shortcut between END event and DISABLE task - END_DISABLE: u1 = 0, - /// Shortcut between DISABLED event and TXEN task - DISABLED_TXEN: u1 = 0, - /// Shortcut between DISABLED event and RXEN task - DISABLED_RXEN: u1 = 0, - /// Shortcut between ADDRESS event and RSSISTART task - ADDRESS_RSSISTART: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - /// Shortcut between ADDRESS event and BCSTART task - ADDRESS_BCSTART: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between DISABLED event and RSSISTOP task - DISABLED_RSSISTOP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for ADDRESS event - ADDRESS: u1 = 0, - /// Write '1' to Enable interrupt for PAYLOAD event - PAYLOAD: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for DISABLED event - DISABLED: u1 = 0, - /// Write '1' to Enable interrupt for DEVMATCH event - DEVMATCH: u1 = 0, - /// Write '1' to Enable interrupt for DEVMISS event - DEVMISS: u1 = 0, - /// Write '1' to Enable interrupt for RSSIEND event - RSSIEND: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for BCMATCH event - BCMATCH: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for CRCOK event - CRCOK: u1 = 0, - /// Write '1' to Enable interrupt for CRCERROR event - CRCERROR: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for ADDRESS event - ADDRESS: u1 = 0, - /// Write '1' to Disable interrupt for PAYLOAD event - PAYLOAD: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for DISABLED event - DISABLED: u1 = 0, - /// Write '1' to Disable interrupt for DEVMATCH event - DEVMATCH: u1 = 0, - /// Write '1' to Disable interrupt for DEVMISS event - DEVMISS: u1 = 0, - /// Write '1' to Disable interrupt for RSSIEND event - RSSIEND: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for BCMATCH event - BCMATCH: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for CRCOK event - CRCOK: u1 = 0, - /// Write '1' to Disable interrupt for CRCERROR event - CRCERROR: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC status - pub const CRCSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// CRC status of packet received - CRCSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Received address - pub const RXMATCH = mmio(Address + 0x00000408, 32, packed struct { + /// address: 0x40000520 + /// General purpose retention register + pub const GPREGRET2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// General purpose retention register + GPREGRET: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x520); + + /// address: 0x40000524 + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMON = @intToPtr(*volatile Mmio(32, packed struct{ + /// Keep RAM block 0 on or off in system ON Mode + ONRAM0: u1, + /// Keep RAM block 1 on or off in system ON Mode + ONRAM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0: u1, + /// Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x524); + + /// address: 0x40000554 + /// Deprecated register - RAM on/off register (this register is retained) + pub const RAMONB = @intToPtr(*volatile Mmio(32, packed struct{ + /// Keep RAM block 2 on or off in system ON Mode + ONRAM2: u1, + /// Keep RAM block 3 on or off in system ON Mode + ONRAM3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2: u1, + /// Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x554); + + /// address: 0x40000578 + /// DC/DC enable register + pub const DCDCEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x578); + + pub const RAM = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: RAM0 power control register + POWER: Mmio(32, packed struct{ + /// Keep RAM section S0 ON or OFF in System ON mode. + S0POWER: u1, + /// Keep RAM section S1 ON or OFF in System ON mode. + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is in OFF + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is in OFF + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + + /// Description cluster[0]: RAM0 power control set register + POWERSET: Mmio(32, packed struct{ + /// Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER: u1, + /// Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is switched off + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is switched off + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + + /// Description cluster[0]: RAM0 power control clear register + POWERCLR: Mmio(32, packed struct{ + /// Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER: u1, + /// Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Keep retention on RAM section S0 when RAM section is switched off + S0RETENTION: u1, + /// Keep retention on RAM section S1 when RAM section is switched off + S1RETENTION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), + padding0: u32, + }, base_address + 0x900); + }; + /// Clock control + pub const CLOCK = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// Start HFCLK crystal oscillator + pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40000004 + /// Stop HFCLK crystal oscillator + pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40000008 + /// Start LFCLK source + pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000000c + /// Stop LFCLK source + pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40000010 + /// Start calibration of LFRC oscillator + pub const TASKS_CAL = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40000014 + /// Start calibration timer + pub const TASKS_CTSTART = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40000018 + /// Stop calibration timer + pub const TASKS_CTSTOP = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x40000100 + /// HFCLK oscillator started + pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40000104 + /// LFCLK started + pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000010c + /// Calibration of LFCLK RC oscillator complete event + pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40000110 + /// Calibration timer timeout + pub const EVENTS_CTTO = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40000304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1, + /// Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1, + reserved0: u1, + /// Write '1' to Enable interrupt for DONE event + DONE: u1, + /// Write '1' to Enable interrupt for CTTO event + CTTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x304); + + /// address: 0x40000308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED: u1, + /// Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED: u1, + reserved0: u1, + /// Write '1' to Disable interrupt for DONE event + DONE: u1, + /// Write '1' to Disable interrupt for CTTO event + CTTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x308); + + /// address: 0x40000408 + /// Status indicating that HFCLKSTART task has been triggered + pub const HFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + /// HFCLKSTART task triggered or not + STATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x408); + + /// address: 0x4000040c + /// HFCLK status + pub const HFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Source of HFCLK + SRC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// HFCLK state + STATE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x40c); + + /// address: 0x40000414 + /// Status indicating that LFCLKSTART task has been triggered + pub const LFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + /// LFCLKSTART task triggered or not + STATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x414); + + /// address: 0x40000418 + /// LFCLK status + pub const LFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Source of LFCLK + SRC: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LFCLK state + STATE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x418); + + /// address: 0x4000041c + /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + pub const LFCLKSRCCOPY = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock source + SRC: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x41c); + + /// address: 0x40000518 + /// Clock source for the LFCLK + pub const LFCLKSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock source + SRC: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable bypass of LFCLK crystal oscillator with external clock source + BYPASS: u1, + /// Enable or disable external source for LFCLK + EXTERNAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x518); + + /// address: 0x40000538 + /// Calibration timer interval + pub const CTIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x538); + + /// address: 0x4000055c + /// Clocking options for the Trace Port debug interface + pub const TRACECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock + /// divided by two. + TRACEPORTSPEED: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Pin multiplexing of trace signals. + TRACEMUX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x55c); + }; + /// 2.4 GHz Radio + pub const RADIO = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// Enable RADIO in TX mode + pub const TASKS_TXEN = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40001004 + /// Enable RADIO in RX mode + pub const TASKS_RXEN = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40001008 + /// Start RADIO + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000100c + /// Stop RADIO + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40001010 + /// Disable RADIO + pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40001014 + /// Start the RSSI and take one single sample of the receive signal strength. + pub const TASKS_RSSISTART = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40001018 + /// Stop the RSSI measurement + pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4000101c + /// Start the bit counter + pub const TASKS_BCSTART = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40001020 + /// Stop the bit counter + pub const TASKS_BCSTOP = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40001100 + /// RADIO has ramped up and is ready to be started + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40001104 + /// Address sent or received + pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40001108 + /// Packet payload sent or received + pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000110c + /// Packet sent or received + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40001110 + /// RADIO has been disabled + pub const EVENTS_DISABLED = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40001114 + /// A device address match occurred on the last received packet + pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40001118 + /// No device address match occurred on the last received packet + pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4000111c + /// Sampling of receive signal strength complete. + pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40001128 + /// Bit counter reached bit count value. + pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40001130 + /// Packet received with CRC ok + pub const EVENTS_CRCOK = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x40001134 + /// Packet received with CRC error + pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x40001200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and START task + READY_START: u1, + /// Shortcut between END event and DISABLE task + END_DISABLE: u1, + /// Shortcut between DISABLED event and TXEN task + DISABLED_TXEN: u1, + /// Shortcut between DISABLED event and RXEN task + DISABLED_RXEN: u1, + /// Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART: u1, + /// Shortcut between END event and START task + END_START: u1, + /// Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART: u1, + reserved0: u1, + /// Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x200); + + /// address: 0x40001304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for ADDRESS event + ADDRESS: u1, + /// Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for DISABLED event + DISABLED: u1, + /// Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH: u1, + /// Write '1' to Enable interrupt for DEVMISS event + DEVMISS: u1, + /// Write '1' to Enable interrupt for RSSIEND event + RSSIEND: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for BCMATCH event + BCMATCH: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for CRCOK event + CRCOK: u1, + /// Write '1' to Enable interrupt for CRCERROR event + CRCERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x304); + + /// address: 0x40001308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for ADDRESS event + ADDRESS: u1, + /// Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for DISABLED event + DISABLED: u1, + /// Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH: u1, + /// Write '1' to Disable interrupt for DEVMISS event + DEVMISS: u1, + /// Write '1' to Disable interrupt for RSSIEND event + RSSIEND: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for BCMATCH event + BCMATCH: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for CRCOK event + CRCOK: u1, + /// Write '1' to Disable interrupt for CRCERROR event + CRCERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x308); + + /// address: 0x40001400 + /// CRC status + pub const CRCSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40001408 /// Received address - RXMATCH: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC field of previously received packet - pub const RXCRC = mmio(Address + 0x0000040c, 32, packed struct { + pub const RXMATCH = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x408); + + /// address: 0x4000140c /// CRC field of previously received packet - RXCRC: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Device address match index - pub const DAI = mmio(Address + 0x00000410, 32, packed struct { + pub const RXCRC = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40c); + + /// address: 0x40001410 /// Device address match index - DAI: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet pointer - pub const PACKETPTR = @intToPtr(*volatile u32, Address + 0x00000504); - - /// Frequency - pub const FREQUENCY = mmio(Address + 0x00000508, 32, packed struct { - /// Radio channel frequency - FREQUENCY: u7 = 0, - reserved1: u1 = 0, - /// Channel map selection. - MAP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Output power - pub const TXPOWER = mmio(Address + 0x0000050c, 32, packed struct { - /// RADIO output power. - TXPOWER: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data rate and modulation - pub const MODE = mmio(Address + 0x00000510, 32, packed struct { - /// Radio data rate and modulation setting. The radio supports Frequency-shift - /// Keying (FSK) modulation. - MODE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet configuration register 0 - pub const PCNF0 = mmio(Address + 0x00000514, 32, packed struct { - /// Length on air of LENGTH field in number of bits. - LFLEN: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Length on air of S0 field in number of bytes. - S0LEN: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Length on air of S1 field in number of bits. - S1LEN: u4 = 0, - /// Include or exclude S1 field in RAM - S1INCL: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - /// Length of preamble on air. Decision point: TASKS_START task - PLEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet configuration register 1 - pub const PCNF1 = mmio(Address + 0x00000518, 32, packed struct { - /// Maximum length of packet payload. If the packet payload is larger than - /// MAXLEN, the radio will truncate the payload to MAXLEN. - MAXLEN: u8 = 0, - /// Static length in number of bytes - STATLEN: u8 = 0, - /// Base address length in number of bytes - BALEN: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the - /// PAYLOAD fields. - ENDIAN: u1 = 0, - /// Enable or disable packet whitening - WHITEEN: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Base address 0 - pub const BASE0 = @intToPtr(*volatile u32, Address + 0x0000051c); - - /// Base address 1 - pub const BASE1 = @intToPtr(*volatile u32, Address + 0x00000520); - - /// Prefixes bytes for logical addresses 0-3 - pub const PREFIX0 = mmio(Address + 0x00000524, 32, packed struct { - /// Address prefix 0. - AP0: u8 = 0, - /// Address prefix 1. - AP1: u8 = 0, - /// Address prefix 2. - AP2: u8 = 0, - /// Address prefix 3. - AP3: u8 = 0, - }); - - /// Prefixes bytes for logical addresses 4-7 - pub const PREFIX1 = mmio(Address + 0x00000528, 32, packed struct { - /// Address prefix 4. - AP4: u8 = 0, - /// Address prefix 5. - AP5: u8 = 0, - /// Address prefix 6. - AP6: u8 = 0, - /// Address prefix 7. - AP7: u8 = 0, - }); - - /// Transmit address select - pub const TXADDRESS = mmio(Address + 0x0000052c, 32, packed struct { + pub const DAI = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x410); + + /// address: 0x40001504 + /// Packet pointer + pub const PACKETPTR = @intToPtr(*volatile u32, base_address + 0x504); + + /// address: 0x40001508 + /// Frequency + pub const FREQUENCY = @intToPtr(*volatile Mmio(32, packed struct{ + /// Radio channel frequency + FREQUENCY: u7, + reserved0: u1, + /// Channel map selection. + MAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x508); + + /// address: 0x4000150c + /// Output power + pub const TXPOWER = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x50c); + + /// address: 0x40001510 + /// Data rate and modulation + pub const MODE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40001514 + /// Packet configuration register 0 + pub const PCNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Length on air of LENGTH field in number of bits. + LFLEN: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Length on air of S0 field in number of bytes. + S0LEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Length on air of S1 field in number of bits. + S1LEN: u4, + /// Include or exclude S1 field in RAM + S1INCL: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Length of preamble on air. Decision point: TASKS_START task + PLEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x514); + + /// address: 0x40001518 + /// Packet configuration register 1 + pub const PCNF1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, + /// the radio will truncate the payload to MAXLEN. + MAXLEN: u8, + /// Static length in number of bytes + STATLEN: u8, + /// Base address length in number of bytes + BALEN: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD + /// fields. + ENDIAN: u1, + /// Enable or disable packet whitening + WHITEEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x518); + + /// address: 0x4000151c + /// Base address 0 + pub const BASE0 = @intToPtr(*volatile u32, base_address + 0x51c); + + /// address: 0x40001520 + /// Base address 1 + pub const BASE1 = @intToPtr(*volatile u32, base_address + 0x520); + + /// address: 0x40001524 + /// Prefixes bytes for logical addresses 0-3 + pub const PREFIX0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address prefix 0. + AP0: u8, + /// Address prefix 1. + AP1: u8, + /// Address prefix 2. + AP2: u8, + /// Address prefix 3. + AP3: u8, + }), base_address + 0x524); + + /// address: 0x40001528 + /// Prefixes bytes for logical addresses 4-7 + pub const PREFIX1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address prefix 4. + AP4: u8, + /// Address prefix 5. + AP5: u8, + /// Address prefix 6. + AP6: u8, + /// Address prefix 7. + AP7: u8, + }), base_address + 0x528); + + /// address: 0x4000152c /// Transmit address select - TXADDRESS: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive address select - pub const RXADDRESSES = mmio(Address + 0x00000530, 32, packed struct { - /// Enable or disable reception on logical address 0. - ADDR0: u1 = 0, - /// Enable or disable reception on logical address 1. - ADDR1: u1 = 0, - /// Enable or disable reception on logical address 2. - ADDR2: u1 = 0, - /// Enable or disable reception on logical address 3. - ADDR3: u1 = 0, - /// Enable or disable reception on logical address 4. - ADDR4: u1 = 0, - /// Enable or disable reception on logical address 5. - ADDR5: u1 = 0, - /// Enable or disable reception on logical address 6. - ADDR6: u1 = 0, - /// Enable or disable reception on logical address 7. - ADDR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC configuration - pub const CRCCNF = mmio(Address + 0x00000534, 32, packed struct { - /// CRC length in number of bytes. - LEN: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Include or exclude packet address field out of CRC calculation. - SKIPADDR: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial - pub const CRCPOLY = mmio(Address + 0x00000538, 32, packed struct { + pub const TXADDRESS = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x52c); + + /// address: 0x40001530 + /// Receive address select + pub const RXADDRESSES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable reception on logical address 0. + ADDR0: u1, + /// Enable or disable reception on logical address 1. + ADDR1: u1, + /// Enable or disable reception on logical address 2. + ADDR2: u1, + /// Enable or disable reception on logical address 3. + ADDR3: u1, + /// Enable or disable reception on logical address 4. + ADDR4: u1, + /// Enable or disable reception on logical address 5. + ADDR5: u1, + /// Enable or disable reception on logical address 6. + ADDR6: u1, + /// Enable or disable reception on logical address 7. + ADDR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x530); + + /// address: 0x40001534 + /// CRC configuration + pub const CRCCNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC length in number of bytes. + LEN: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Include or exclude packet address field out of CRC calculation. + SKIPADDR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x534); + + /// address: 0x40001538 /// CRC polynomial - CRCPOLY: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC initial value - pub const CRCINIT = mmio(Address + 0x0000053c, 32, packed struct { + pub const CRCPOLY = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x538); + + /// address: 0x4000153c /// CRC initial value - CRCINIT: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, Address + 0x00000540); - - /// Inter Frame Spacing in us - pub const TIFS = mmio(Address + 0x00000544, 32, packed struct { - /// Inter Frame Spacing in us - TIFS: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RSSI sample - pub const RSSISAMPLE = mmio(Address + 0x00000548, 32, packed struct { - /// RSSI sample - RSSISAMPLE: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current radio state - pub const STATE = mmio(Address + 0x00000550, 32, packed struct { - /// Current radio state - STATE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data whitening initial value - pub const DATAWHITEIV = mmio(Address + 0x00000554, 32, packed struct { - /// Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it - /// has no effect, and it will always be read back and used by the device as - /// '1'. - DATAWHITEIV: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bit counter compare - pub const BCC = @intToPtr(*volatile u32, Address + 0x00000560); - - /// Device address match configuration - pub const DACNF = mmio(Address + 0x00000640, 32, packed struct { - /// Enable or disable device address matching using device address 0 - ENA0: u1 = 0, - /// Enable or disable device address matching using device address 1 - ENA1: u1 = 0, - /// Enable or disable device address matching using device address 2 - ENA2: u1 = 0, - /// Enable or disable device address matching using device address 3 - ENA3: u1 = 0, - /// Enable or disable device address matching using device address 4 - ENA4: u1 = 0, - /// Enable or disable device address matching using device address 5 - ENA5: u1 = 0, - /// Enable or disable device address matching using device address 6 - ENA6: u1 = 0, - /// Enable or disable device address matching using device address 7 - ENA7: u1 = 0, - /// TxAdd for device address 0 - TXADD0: u1 = 0, - /// TxAdd for device address 1 - TXADD1: u1 = 0, - /// TxAdd for device address 2 - TXADD2: u1 = 0, - /// TxAdd for device address 3 - TXADD3: u1 = 0, - /// TxAdd for device address 4 - TXADD4: u1 = 0, - /// TxAdd for device address 5 - TXADD5: u1 = 0, - /// TxAdd for device address 6 - TXADD6: u1 = 0, - /// TxAdd for device address 7 - TXADD7: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Radio mode configuration register 0 - pub const MODECNF0 = mmio(Address + 0x00000650, 32, packed struct { - /// Radio ramp-up time - RU: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Default TX value - DTX: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Peripheral power control - pub const POWER = mmio(Address + 0x00000ffc, 32, packed struct { - /// Peripheral power control. The peripheral and its registers will be reset to - /// its initial state by switching the peripheral off and then back on again. - POWER: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Device address base segment 0 - pub const DAB = @intToPtr(*volatile [8]u32, Address + 0x00000600); - /// Description collection[0]: Device address prefix 0 - pub const DAP = @intToPtr(*volatile [8]MMIO(32, packed struct { - /// Device address prefix 0 - DAP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000620); -}; + pub const CRCINIT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x53c); -/// UART with EasyDMA -pub const UARTE0 = extern struct { - pub const Address: u32 = 0x40002000; - - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Flush RX FIFO into RX buffer - pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, Address + 0x0000002c); - - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); - - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Data received in RXD (but potentially not yet transferred to Data RAM) - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Receive buffer is filled up - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Last TX byte transmitted - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); - - /// UART receiver has started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// UART transmitter has started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Transmitter stopped - pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, Address + 0x00000158); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between ENDRX event and STARTRX task - ENDRX_STARTRX: u1 = 0, - /// Shortcut between ENDRX event and STOPRX task - ENDRX_STOPRX: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for CTS event - CTS: u1 = 0, - /// Enable or disable interrupt for NCTS event - NCTS: u1 = 0, - /// Enable or disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Enable or disable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Enable or disable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Write '1' to Enable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved12: u1 = 0, - /// Write '1' to Disable interrupt for TXSTOPPED event - TXSTOPPED: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// Parity error - PARITY: u1 = 0, - /// Framing error occurred - FRAMING: u1 = 0, - /// Break condition - BREAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable UART - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable UARTE - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate. Accuracy depends on the HFCLK source selected. - pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration of parity and hardware flow control - pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { - /// Hardware flow control - HWFC: u1 = 0, - /// Parity - PARITY: u3 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for RTS signal - pub const RTS = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for TXD signal - pub const TXD = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for CTS signal - pub const CTS = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for RXD signal - pub const RXD = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; + /// address: 0x40001540 + /// Unspecified + pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x540); - pub const RXD = struct { + /// address: 0x40001544 + /// Inter Frame Spacing in us + pub const TIFS = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x544); - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40001548 + /// RSSI sample + pub const RSSISAMPLE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x548); - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40001550 + /// Current radio state + pub const STATE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x550); + + /// address: 0x40001554 + /// Data whitening initial value + pub const DATAWHITEIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x554); + + /// address: 0x40001560 + /// Bit counter compare + pub const BCC = @intToPtr(*volatile u32, base_address + 0x560); + + /// address: 0x40001600 + /// Description collection[0]: Device address base segment 0 + pub const DAB = @intToPtr(*volatile [8]u32, base_address + 0x600); + + /// address: 0x40001620 + /// Description collection[0]: Device address prefix 0 + pub const DAP = @intToPtr(*volatile [8]MmioInt(32, u16), base_address + 0x620); + + /// address: 0x40001640 + /// Device address match configuration + pub const DACNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable device address matching using device address 0 + ENA0: u1, + /// Enable or disable device address matching using device address 1 + ENA1: u1, + /// Enable or disable device address matching using device address 2 + ENA2: u1, + /// Enable or disable device address matching using device address 3 + ENA3: u1, + /// Enable or disable device address matching using device address 4 + ENA4: u1, + /// Enable or disable device address matching using device address 5 + ENA5: u1, + /// Enable or disable device address matching using device address 6 + ENA6: u1, + /// Enable or disable device address matching using device address 7 + ENA7: u1, + /// TxAdd for device address 0 + TXADD0: u1, + /// TxAdd for device address 1 + TXADD1: u1, + /// TxAdd for device address 2 + TXADD2: u1, + /// TxAdd for device address 3 + TXADD3: u1, + /// TxAdd for device address 4 + TXADD4: u1, + /// TxAdd for device address 5 + TXADD5: u1, + /// TxAdd for device address 6 + TXADD6: u1, + /// TxAdd for device address 7 + TXADD7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x640); + + /// address: 0x40001650 + /// Radio mode configuration register 0 + pub const MODECNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Radio ramp-up time + RU: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Default TX value + DTX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x650); + + /// address: 0x40001ffc + /// Peripheral power control + pub const POWER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xffc); + }; + /// UART with EasyDMA + pub const UARTE0 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40002008 + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000200c + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000202c + /// Flush RX FIFO into RX buffer + pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x40002100 + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40002104 + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40002108 + /// Data received in RXD (but potentially not yet transferred to Data RAM) + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40002110 + /// Receive buffer is filled up + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x4000211c + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40002120 + /// Last TX byte transmitted + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x40002124 + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40002144 + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x4000214c + /// UART receiver has started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40002150 + /// UART transmitter has started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40002158 + /// Transmitter stopped + pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x40002200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX: u1, + /// Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x200); + + /// address: 0x40002300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for CTS event + CTS: u1, + /// Enable or disable interrupt for NCTS event + NCTS: u1, + /// Enable or disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Enable or disable interrupt for TXDRDY event + TXDRDY: u1, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Enable or disable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Enable or disable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x300); + + /// address: 0x40002304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for CTS event + CTS: u1, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x304); + + /// address: 0x40002308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for CTS event + CTS: u1, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1, + reserved10: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved11: u1, + /// Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x308); + + /// address: 0x40002480 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// Parity error + PARITY: u1, + /// Framing error occurred + FRAMING: u1, + /// Break condition + BREAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x480); + + /// address: 0x40002500 + /// Enable UART + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40002524 + /// Baud rate. Accuracy depends on the HFCLK source selected. + pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x4000256c + /// Configuration of parity and hardware flow control + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Hardware flow control + HWFC: u1, + /// Parity + PARITY: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x56c); + + pub const PSEL = struct { + + /// address: 0x40002000 + /// Pin select for RTS signal + pub const RTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40002004 + /// Pin select for TXD signal + pub const TXD = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40002008 + /// Pin select for CTS signal + pub const CTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4000200c + /// Pin select for RXD signal + pub const RXD = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40002000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40002008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + /// TXD EasyDMA channel + pub const TXD = struct { - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40002000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40002004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40002008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; - -/// Universal Asynchronous Receiver/Transmitter -pub const UART0 = extern struct { - pub const Address: u32 = 0x40002000; - - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Suspend UART - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, Address + 0x00000100); - - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Data received in RXD - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, Address + 0x00000144); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between CTS event and STARTRX task - CTS_STARTRX: u1 = 0, - /// Shortcut between NCTS event and STOPRX task - NCTS_STOPRX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1 = 0, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1 = 0, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x00000480, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// Parity error - PARITY: u1 = 0, - /// Framing error occurred - FRAMING: u1 = 0, - /// Break condition - BREAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable UART - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable UART - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for RTS - pub const PSELRTS = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for TXD - pub const PSELTXD = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Pin select for CTS - pub const PSELCTS = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pin select for RXD - pub const PSELRXD = @intToPtr(*volatile u32, Address + 0x00000514); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received in previous transfers, double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to be transferred - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate - pub const BAUDRATE = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration of parity and hardware flow control - pub const CONFIG = mmio(Address + 0x0000056c, 32, packed struct { - /// Hardware flow control - HWFC: u1 = 0, - /// Parity - PARITY: u3 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// Universal Asynchronous Receiver/Transmitter + pub const UART0 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// Start UART receiver + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40002004 + /// Stop UART receiver + pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40002008 + /// Start UART transmitter + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000200c + /// Stop UART transmitter + pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000201c + /// Suspend UART + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40002100 + /// CTS is activated (set low). Clear To Send. + pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40002104 + /// CTS is deactivated (set high). Not Clear To Send. + pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40002108 + /// Data received in RXD + pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000211c + /// Data sent from TXD + pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40002124 + /// Error detected + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40002144 + /// Receiver timeout + pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x40002200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Shortcut between CTS event and STARTRX task + CTS_STARTRX: u1, + /// Shortcut between NCTS event and STOPRX task + NCTS_STOPRX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40002304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for CTS event + CTS: u1, + /// Write '1' to Enable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Enable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for TXDRDY event + TXDRDY: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Write '1' to Enable interrupt for RXTO event + RXTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x304); + + /// address: 0x40002308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for CTS event + CTS: u1, + /// Write '1' to Disable interrupt for NCTS event + NCTS: u1, + /// Write '1' to Disable interrupt for RXDRDY event + RXDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for TXDRDY event + TXDRDY: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Write '1' to Disable interrupt for RXTO event + RXTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x308); + + /// address: 0x40002480 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// Parity error + PARITY: u1, + /// Framing error occurred + FRAMING: u1, + /// Break condition + BREAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x480); + + /// address: 0x40002500 + /// Enable UART + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40002508 + /// Pin select for RTS + pub const PSELRTS = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000250c + /// Pin select for TXD + pub const PSELTXD = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40002510 + /// Pin select for CTS + pub const PSELCTS = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x40002514 + /// Pin select for RXD + pub const PSELRXD = @intToPtr(*volatile u32, base_address + 0x514); + + /// address: 0x40002518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Serial Peripheral Interface Master with EasyDMA 0 -pub const SPIM0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// address: 0x4000251c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40002524 + /// Baud rate + pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x4000256c + /// Configuration of parity and hardware flow control + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Hardware flow control + HWFC: u1, + /// Parity + PARITY: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x56c); + }; + /// Serial Peripheral Interface Master with EasyDMA 0 + pub const SPIM0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40003014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40003118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40003120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4000314c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40003500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400035c0 /// Over-read character. Character clocked out in case and over-read of the TXD /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MOSI signal - pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MISO signal - pub const MISO = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; - - pub const RXD = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MOSI signal + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MISO signal + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - pub const TXD = struct { + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// TXD EasyDMA channel + pub const TXD = struct { - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); -/// SPI Slave 0 -pub const SPIS0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MISO signal - pub const MISO = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for MOSI signal - pub const MOSI = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for CSN signal - pub const CSN = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; }; - - pub const RXD = struct { - - /// RXD data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// SPI Slave 0 + pub const SPIS0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40003028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40003128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40003400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40003440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40003500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4000355c + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); + + /// address: 0x400035c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MISO signal + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MOSI signal + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Pin select for CSN signal + pub const CSN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + }; + + pub const RXD = struct { + + /// address: 0x40003000 + /// RXD data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes received in last granted transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes received in the last granted transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 + /// Number of bytes received in last granted transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + pub const TXD = struct { - /// TXD data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003000 + /// TXD data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003004 /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transmitted in last granted transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transmitted in last granted transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; - -/// I2C compatible Two-Wire Master Interface with EasyDMA 0 -pub const TWIM0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Last byte has been sent out after the SUSPEND task has been issued, TWI - /// traffic is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); - - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1 = 0, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1 = 0, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1 = 0, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1 = 0, - reserved8: u1 = 0, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// I2C compatible Two-Wire Master Interface with EasyDMA 0 + pub const TWIM0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40003014 + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40003148 + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic + /// is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000314c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x4000315c + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x40003160 + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1, + reserved7: u1, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x200); + + /// address: 0x40003300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x300); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x308); + + /// address: 0x400034c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40003500 + /// Enable TWIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003588 /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCL signal - pub const SCL = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDA signal - pub const SDA = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; - - pub const RXD = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of bytes in receive buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCL signal + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for SDA signal + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in receive buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes transferred in the last transaction. In case of NACK error, - /// includes the NACK'ed byte. - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - pub const TXD = struct { + /// address: 0x40003008 + /// Number of bytes transferred in the last transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { - /// Maximum number of bytes in transmit buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of bytes transferred in the last transaction. In case of NACK error, - /// includes the NACK'ed byte. - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// EasyDMA list type - pub const LIST = mmio(Address + 0x0000000c, 32, packed struct { - /// List type - LIST: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; + /// TXD EasyDMA channel + pub const TXD = struct { -/// I2C compatible Two-Wire Slave Interface with EasyDMA 0 -pub const TWIS0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); - - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); - - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1 = 0, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Enable or disable interrupt for WRITE event - WRITE: u1 = 0, - /// Enable or disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Enable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - reserved1: u1 = 0, - /// NACK sent after receiving a data byte - DNACK: u1 = 0, - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register indicating which address had a match - pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIS - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIS - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the address match mechanism - pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1 = 0, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// TWI slave address - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000588); - - pub const PSEL = struct { - - /// Pin select for SCL signal - pub const SCL = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDA signal - pub const SDA = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; + /// address: 0x40003000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - pub const RXD = struct { + /// address: 0x40003004 + /// Maximum number of bytes in transmit buffer + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - /// RXD Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003008 + /// Number of bytes transferred in the last transaction + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - /// Maximum number of bytes in RXD buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x4000300c + /// EasyDMA list type + pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); + }; + }; + /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 + pub const TWIS0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003030 + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0x40003034 + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x4000314c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40003150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40003164 + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x40003168 + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x200); + + /// address: 0x40003300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Enable or disable interrupt for WRITE event + WRITE: u1, + /// Enable or disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Enable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x308); + + /// address: 0x400034d0 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + reserved0: u1, + /// NACK sent after receiving a data byte + DNACK: u1, + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4d0); + + /// address: 0x400034d4 + /// Status register indicating which address had a match + pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); + + /// address: 0x40003500 + /// Enable TWIS + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003588 + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); + + /// address: 0x40003594 + /// Configuration register for the address match mechanism + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x594); + + /// address: 0x400035c0 + /// Over-read character. Character sent out in case of an over-read of the transmit + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCL signal + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for SDA signal + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + /// RXD EasyDMA channel + pub const RXD = struct { + + /// address: 0x40003000 + /// RXD Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003004 /// Maximum number of bytes in RXD buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last RXD transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last RXD transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; - pub const TXD = struct { + /// TXD EasyDMA channel + pub const TXD = struct { - /// TXD Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + /// address: 0x40003000 + /// TXD Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - /// Maximum number of bytes in TXD buffer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + /// address: 0x40003004 /// Maximum number of bytes in TXD buffer - MAXCNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of bytes transferred in the last TXD transaction - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40003008 /// Number of bytes transferred in the last TXD transaction - AMOUNT: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + }; }; -}; + /// Serial Peripheral Interface 0 + pub const SPI0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40003500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Serial Peripheral Interface 0 -pub const SPI0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for SCK - pub const SCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number configuration for SPI SCK signal - PSELSCK: u32 = 0, - }); - - /// Pin select for MOSI - pub const MOSI = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number configuration for SPI MOSI signal - PSELMOSI: u32 = 0, - }); - - /// Pin select for MISO - pub const MISO = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number configuration for SPI MISO signal - PSELMISO: u32 = 0, - }); + /// address: 0x4000351c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40003524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40003554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + pub const PSEL = struct { + + /// address: 0x40003000 + /// Pin select for SCK + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI SCK signal + PSELSCK: u32, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Pin select for MOSI + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI MOSI signal + PSELMOSI: u32, + }), base_address + 0x4); + + /// address: 0x40003008 + /// Pin select for MISO + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number configuration for SPI MISO signal + PSELMISO: u32, + }), base_address + 0x8); + }; }; -}; - -/// I2C compatible Two-Wire Interface 0 -pub const TWI0 = extern struct { - pub const Address: u32 = 0x40003000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); - - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1 = 0, - /// Shortcut between BB event and STOP task - BB_STOP: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Enable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Disable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// I2C compatible Two-Wire Interface 0 + pub const TWI0 = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40003008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40003014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000301c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40003020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40003104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40003108 + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000311c + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40003124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40003138 + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40003148 + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x40003200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1, + /// Shortcut between BB event and STOP task + BB_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40003304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x304); + + /// address: 0x40003308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x308); + + /// address: 0x400034c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40003500 + /// Enable TWI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40003508 + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000350c + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40003518 /// RXD register - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); + + /// address: 0x4000351c /// TXD register - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { - /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40003524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); -/// Serial Peripheral Interface Master with EasyDMA 1 -pub const SPIM1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { + /// address: 0x40003588 + /// Address used in the TWI transfer + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// Serial Peripheral Interface Master with EasyDMA 1 + pub const SPIM1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40004014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40004118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40004120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4000414c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40004500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400045c0 /// Over-read character. Character clocked out in case and over-read of the TXD /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// SPI Slave 1 -pub const SPIS1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// SPI Slave 1 + pub const SPIS1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40004028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40004104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40004128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40004400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40004440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40004500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4000455c /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); -/// I2C compatible Two-Wire Master Interface with EasyDMA 1 -pub const TWIM1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Last byte has been sent out after the SUSPEND task has been issued, TWI - /// traffic is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, Address + 0x0000015c); - - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, Address + 0x00000160); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1 = 0, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1 = 0, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1 = 0, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1 = 0, - reserved8: u1 = 0, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1 = 0, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { + /// address: 0x400045c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// I2C compatible Two-Wire Master Interface with EasyDMA 1 + pub const TWIM1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40004008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40004014 + /// Stop TWI transaction. Must be issued while the TWI master is not suspended. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40004148 + /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic + /// is now suspended. + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000414c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x4000415c + /// Byte boundary, starting to receive the last byte + pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x40004160 + /// Byte boundary, starting to transmit the last byte + pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX: u1, + /// Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND: u1, + /// Shortcut between LASTTX event and STOP task + LASTTX_STOP: u1, + /// Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX: u1, + reserved7: u1, + /// Shortcut between LASTRX event and STOP task + LASTRX_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x200); + + /// address: 0x40004300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Enable or disable interrupt for LASTRX event + LASTRX: u1, + /// Enable or disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x300); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Enable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Enable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved16: u1, + reserved17: u1, + /// Write '1' to Disable interrupt for LASTRX event + LASTRX: u1, + /// Write '1' to Disable interrupt for LASTTX event + LASTTX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x308); + + /// address: 0x400044c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40004500 + /// Enable TWIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004588 /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// I2C compatible Two-Wire Slave Interface with EasyDMA 1 -pub const TWIS1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, Address + 0x00000030); - - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, Address + 0x00000034); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, Address + 0x00000164); - - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, Address + 0x00000168); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1 = 0, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Enable or disable interrupt for WRITE event - WRITE: u1 = 0, - /// Enable or disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Enable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1 = 0, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1 = 0, - /// Write '1' to Disable interrupt for READ event - READ: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004d0, 32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - reserved1: u1 = 0, - /// NACK sent after receiving a data byte - DNACK: u1 = 0, - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register indicating which address had a match - pub const MATCH = mmio(Address + 0x000004d4, 32, packed struct { - /// Which of the addresses in {ADDRESS} matched the incoming address - MATCH: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWIS - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWIS - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the address match mechanism - pub const CONFIG = mmio(Address + 0x00000594, 32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1 = 0, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character sent out in case of an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MMIO(32, packed struct { - /// TWI slave address - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000588); -}; - -/// Serial Peripheral Interface 1 -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 + pub const TWIS1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004030 + /// Prepare the TWI slave to respond to a write command + pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0x40004034 + /// Prepare the TWI slave to respond to a read command + pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x4000414c + /// Receive sequence started + pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40004150 + /// Transmit sequence started + pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40004164 + /// Write command received + pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x40004168 + /// Read command received + pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND: u1, + /// Shortcut between READ event and SUSPEND task + READ_SUSPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x200); + + /// address: 0x40004300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Enable or disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Enable or disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Enable or disable interrupt for WRITE event + WRITE: u1, + /// Enable or disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Enable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Enable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED: u1, + /// Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// Write '1' to Disable interrupt for WRITE event + WRITE: u1, + /// Write '1' to Disable interrupt for READ event + READ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x308); + + /// address: 0x400044d0 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + reserved0: u1, + /// NACK sent after receiving a data byte + DNACK: u1, + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4d0); + + /// address: 0x400044d4 + /// Status register indicating which address had a match + pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); + + /// address: 0x40004500 + /// Enable TWIS + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004588 + /// Description collection[0]: TWI slave address 0 + pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); + + /// address: 0x40004594 + /// Configuration register for the address match mechanism + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable address matching on ADDRESS[0] + ADDRESS0: u1, + /// Enable or disable address matching on ADDRESS[1] + ADDRESS1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x594); + + /// address: 0x400045c0 + /// Over-read character. Character sent out in case of an over-read of the transmit + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// Serial Peripheral Interface 1 + pub const SPI1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40004500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// I2C compatible Two-Wire Interface 1 -pub const TWI1 = extern struct { - pub const Address: u32 = 0x40004000; - - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000124); - - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, Address + 0x00000138); - - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, Address + 0x00000148); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1 = 0, - /// Shortcut between BB event and STOP task - BB_STOP: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Enable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Write '1' to Disable interrupt for BB event - BB: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Error source - pub const ERRORSRC = mmio(Address + 0x000004c4, 32, packed struct { - /// Overrun error - OVERRUN: u1 = 0, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1 = 0, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable TWI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable TWI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { + /// address: 0x4000451c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40004524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + }; + /// I2C compatible Two-Wire Interface 1 + pub const TWI1 = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// Start TWI receive sequence + pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40004008 + /// Start TWI transmit sequence + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40004014 + /// Stop TWI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000401c + /// Suspend TWI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40004020 + /// Resume TWI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40004104 + /// TWI stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40004108 + /// TWI RXD byte received + pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000411c + /// TWI TXD byte sent + pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40004124 + /// TWI error + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x40004138 + /// TWI byte boundary, generated before each byte that is sent or received + pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40004148 + /// TWI entered the suspended state + pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x40004200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between BB event and SUSPEND task + BB_SUSPEND: u1, + /// Shortcut between BB event and STOP task + BB_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40004304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Enable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x304); + + /// address: 0x40004308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for RXDREADY event + RXDREADY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for TXDSENT event + TXDSENT: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Write '1' to Disable interrupt for BB event + BB: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x308); + + /// address: 0x400044c4 + /// Error source + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + /// Overrun error + OVERRUN: u1, + /// NACK received after sending the address (write '1' to clear) + ANACK: u1, + /// NACK received after sending a data byte (write '1' to clear) + DNACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4c4); + + /// address: 0x40004500 + /// Enable TWI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40004508 + /// Pin select for SCL + pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000450c + /// Pin select for SDA + pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x40004518 /// RXD register - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); + + /// address: 0x4000451c /// TXD register - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Address used in the TWI transfer - pub const ADDRESS = mmio(Address + 0x00000588, 32, packed struct { - /// Address used in the TWI transfer - ADDRESS: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); -/// NFC-A compatible radio -pub const NFCT = extern struct { - pub const Address: u32 = 0x40005000; - - /// Activate NFC peripheral for incoming and outgoing frames, change state to - /// activated - pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Disable NFC peripheral - pub const TASKS_DISABLE = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Enable NFC sense field mode, change state to sense mode - pub const TASKS_SENSE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Start transmission of a outgoing frame, change state to transmit - pub const TASKS_STARTTX = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Initializes the EasyDMA for receive. - pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Force state machine to IDLE state - pub const TASKS_GOIDLE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Force state machine to SLEEP_A state - pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, Address + 0x00000028); - - /// The NFC peripheral is ready to receive and send frames - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Remote NFC field detected - pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Remote NFC field lost - pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Marks the start of the first symbol of a transmitted frame - pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Marks the end of the last transmitted on-air symbol of a frame - pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Marks the end of the first symbol of a received frame - pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Received data have been checked (CRC, parity) and transferred to RAM, and - /// EasyDMA has ended accessing the RX buffer - pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// NFC error reported. The ERRORSTATUS register contains details on the source - /// of the error. - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on - /// the source of the error. - pub const EVENTS_RXERROR = @intToPtr(*volatile u32, Address + 0x00000128); - - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x0000012c); - - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the - /// TX buffer - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000130); - - /// Auto collision resolution process has started - pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, Address + 0x00000138); - - /// NFC Auto collision resolution error reported. - pub const EVENTS_COLLISION = @intToPtr(*volatile u32, Address + 0x00000148); - - /// NFC Auto collision resolution successfully completed - pub const EVENTS_SELECTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// EasyDMA is ready to receive or send frames. - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000150); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between FIELDDETECTED event and ACTIVATE task - FIELDDETECTED_ACTIVATE: u1 = 0, - /// Shortcut between FIELDLOST event and SENSE task - FIELDLOST_SENSE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1 = 0, - /// Enable or disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Enable or disable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Enable or disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Enable or disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Enable or disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Enable or disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Enable or disable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Enable or disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Enable or disable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Enable or disable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Write '1' to Enable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Write '1' to Enable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Write '1' to Enable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Write '1' to Enable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Write '1' to Enable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Write '1' to Enable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1 = 0, - /// Write '1' to Disable interrupt for FIELDLOST event - FIELDLOST: u1 = 0, - /// Write '1' to Disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1 = 0, - /// Write '1' to Disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1 = 0, - /// Write '1' to Disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1 = 0, - /// Write '1' to Disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for RXERROR event - RXERROR: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved3: u1 = 0, - /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for COLLISION event - COLLISION: u1 = 0, - /// Write '1' to Disable interrupt for SELECTED event - SELECTED: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC Error Status register - pub const ERRORSTATUS = mmio(Address + 0x00000404, 32, packed struct { - /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - FRAMEDELAYTIMEOUT: u1 = 0, - reserved1: u1 = 0, - /// Field level is too high at max load resistance - NFCFIELDTOOSTRONG: u1 = 0, - /// Field level is too low at min load resistance - NFCFIELDTOOWEAK: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current value driven to the NFC Load Control - pub const CURRENTLOADCTRL = mmio(Address + 0x00000430, 32, packed struct { + /// address: 0x40004524 + /// TWI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40004588 + /// Address used in the TWI transfer + pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); + }; + /// NFC-A compatible radio + pub const NFCT = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Activate NFC peripheral for incoming and outgoing frames, change state to + /// activated + pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40005004 + /// Disable NFC peripheral + pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40005008 + /// Enable NFC sense field mode, change state to sense mode + pub const TASKS_SENSE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000500c + /// Start transmission of a outgoing frame, change state to transmit + pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000501c + /// Initializes the EasyDMA for receive. + pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40005024 + /// Force state machine to IDLE state + pub const TASKS_GOIDLE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40005028 + /// Force state machine to SLEEP_A state + pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40005100 + /// The NFC peripheral is ready to receive and send frames + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40005104 + /// Remote NFC field detected + pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40005108 + /// Remote NFC field lost + pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000510c + /// Marks the start of the first symbol of a transmitted frame + pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40005110 + /// Marks the end of the last transmitted on-air symbol of a frame + pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40005114 + /// Marks the end of the first symbol of a received frame + pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40005118 + /// Received data have been checked (CRC, parity) and transferred to RAM, and + /// EasyDMA has ended accessing the RX buffer + pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4000511c + /// NFC error reported. The ERRORSTATUS register contains details on the source of + /// the error. + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40005128 + /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the + /// source of the error. + pub const EVENTS_RXERROR = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x4000512c + /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x40005130 + /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX + /// buffer + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x40005138 + /// Auto collision resolution process has started + pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x40005148 + /// NFC Auto collision resolution error reported. + pub const EVENTS_COLLISION = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x4000514c + /// NFC Auto collision resolution successfully completed + pub const EVENTS_SELECTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40005150 + /// EasyDMA is ready to receive or send frames. + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x40005200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE: u1, + /// Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x200); + + /// address: 0x40005300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for READY event + READY: u1, + /// Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Enable or disable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Enable or disable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Enable or disable interrupt for RXERROR event + RXERROR: u1, + /// Enable or disable interrupt for ENDRX event + ENDRX: u1, + /// Enable or disable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Enable or disable interrupt for COLLISION event + COLLISION: u1, + /// Enable or disable interrupt for SELECTED event + SELECTED: u1, + /// Enable or disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x300); + + /// address: 0x40005304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for RXERROR event + RXERROR: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Write '1' to Enable interrupt for COLLISION event + COLLISION: u1, + /// Write '1' to Enable interrupt for SELECTED event + SELECTED: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x304); + + /// address: 0x40005308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED: u1, + /// Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST: u1, + /// Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART: u1, + /// Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND: u1, + /// Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART: u1, + /// Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for RXERROR event + RXERROR: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Write '1' to Disable interrupt for COLLISION event + COLLISION: u1, + /// Write '1' to Disable interrupt for SELECTED event + SELECTED: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x308); + + /// address: 0x40005404 + /// NFC Error Status register + pub const ERRORSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + FRAMEDELAYTIMEOUT: u1, + reserved0: u1, + /// Field level is too high at max load resistance + NFCFIELDTOOSTRONG: u1, + /// Field level is too low at min load resistance + NFCFIELDTOOWEAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x404); + + /// address: 0x40005430 /// Current value driven to the NFC Load Control - CURRENTLOADCTRL: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Indicates the presence or not of a valid field - pub const FIELDPRESENT = mmio(Address + 0x0000043c, 32, packed struct { - /// Indicates the presence or not of a valid field. Available only in the - /// activated state. - FIELDPRESENT: u1 = 0, - /// Indicates if the low level has locked to the field - LOCKDETECT: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Minimum frame delay - pub const FRAMEDELAYMIN = mmio(Address + 0x00000504, 32, packed struct { - /// Minimum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMIN: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Maximum frame delay - pub const FRAMEDELAYMAX = mmio(Address + 0x00000508, 32, packed struct { - /// Maximum frame delay in number of 13.56 MHz clocks - FRAMEDELAYMAX: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register for the Frame Delay Timer - pub const FRAMEDELAYMODE = mmio(Address + 0x0000050c, 32, packed struct { + pub const CURRENTLOADCTRL = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x430); + + /// address: 0x4000543c + /// Indicates the presence or not of a valid field + pub const FIELDPRESENT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Indicates the presence or not of a valid field. Available only in the activated + /// state. + FIELDPRESENT: u1, + /// Indicates if the low level has locked to the field + LOCKDETECT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x43c); + + /// address: 0x40005504 + /// Minimum frame delay + pub const FRAMEDELAYMIN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x504); + + /// address: 0x40005508 + /// Maximum frame delay + pub const FRAMEDELAYMAX = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x508); + + /// address: 0x4000550c /// Configuration register for the Frame Delay Timer - FRAMEDELAYMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Packet pointer for TXD and RXD data storage in Data RAM - pub const PACKETPTR = mmio(Address + 0x00000510, 32, packed struct { - /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a - /// byte aligned RAM address. - PTR: u32 = 0, - }); - - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - pub const MAXLEN = mmio(Address + 0x00000514, 32, packed struct { - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - MAXLEN: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Last NFCID1 part (4, 7 or 10 bytes ID) - pub const NFCID1_LAST = mmio(Address + 0x00000590, 32, packed struct { - /// NFCID1 byte Z (very last byte sent) - NFCID1_Z: u8 = 0, - /// NFCID1 byte Y - NFCID1_Y: u8 = 0, - /// NFCID1 byte X - NFCID1_X: u8 = 0, - /// NFCID1 byte W - NFCID1_W: u8 = 0, - }); - - /// Second last NFCID1 part (7 or 10 bytes ID) - pub const NFCID1_2ND_LAST = mmio(Address + 0x00000594, 32, packed struct { - /// NFCID1 byte V - NFCID1_V: u8 = 0, - /// NFCID1 byte U - NFCID1_U: u8 = 0, - /// NFCID1 byte T - NFCID1_T: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Third last NFCID1 part (10 bytes ID) - pub const NFCID1_3RD_LAST = mmio(Address + 0x00000598, 32, packed struct { - /// NFCID1 byte S - NFCID1_S: u8 = 0, - /// NFCID1 byte R - NFCID1_R: u8 = 0, - /// NFCID1 byte Q - NFCID1_Q: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC-A SENS_RES auto-response settings - pub const SENSRES = mmio(Address + 0x000005a0, 32, packed struct { - /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the - /// NFC Forum, NFC Digital Protocol Technical Specification - BITFRAMESDD: u5 = 0, - /// Reserved for future use. Shall be 0. - RFU5: u1 = 0, - /// NFCID1 size. This value is used by the Auto collision resolution engine. - NFCIDSIZE: u2 = 0, - /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES - /// response in the NFC Forum, NFC Digital Protocol Technical Specification - PLATFCONFIG: u4 = 0, - /// Reserved for future use. Shall be 0. - RFU74: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// NFC-A SEL_RES auto-response settings - pub const SELRES = mmio(Address + 0x000005a4, 32, packed struct { - /// Reserved for future use. Shall be 0. - RFU10: u2 = 0, - /// Cascade bit (controlled by hardware, write has no effect) - CASCADE: u1 = 0, - /// Reserved for future use. Shall be 0. - RFU43: u2 = 0, - /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC - /// Digital Protocol Technical Specification - PROTOCOL: u2 = 0, - /// Reserved for future use. Shall be 0. - RFU7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const FRAMESTATUS = struct { - - /// Result of last incoming frames - pub const RX = mmio(Address + 0x00000000, 32, packed struct { - /// No valid End of Frame detected - CRCERROR: u1 = 0, - reserved1: u1 = 0, - /// Parity status of received frame - PARITYSTATUS: u1 = 0, - /// Overrun detected - OVERRUN: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const FRAMEDELAYMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x50c); - pub const TXD = struct { - - /// Configuration of outgoing frames - pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { - /// Adding parity or not in the frame - PARITY: u1 = 0, - /// Discarding unused bits in start or at end of a Frame - DISCARDMODE: u1 = 0, - /// Adding SoF or not in TX frames - SOF: u1 = 0, - reserved1: u1 = 0, - /// CRC mode for outgoing frames - CRCMODETX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Size of outgoing frame - pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { - /// Number of bits in the last or first byte read from RAM that shall be - /// included in the frame (excluding parity bit). - TXDATABITS: u3 = 0, - /// Number of complete bytes that shall be included in the frame, excluding CRC, - /// parity and framing - TXDATABYTES: u9 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + /// address: 0x40005510 + /// Packet pointer for TXD and RXD data storage in Data RAM + pub const PACKETPTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte + /// aligned RAM address. + PTR: u32, + }), base_address + 0x510); - pub const RXD = struct { - - /// Configuration of incoming frames - pub const FRAMECONFIG = mmio(Address + 0x00000000, 32, packed struct { - /// Parity expected or not in RX frame - PARITY: u1 = 0, - reserved1: u1 = 0, - /// SoF expected or not in RX frames - SOF: u1 = 0, - reserved2: u1 = 0, - /// CRC mode for incoming frames - CRCMODERX: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Size of last incoming frame - pub const AMOUNT = mmio(Address + 0x00000004, 32, packed struct { - /// Number of bits in the last byte in the frame, if less than 8 (including CRC, - /// but excluding parity and SoF/EoF framing). - RXDATABITS: u3 = 0, - /// Number of complete bytes received in the frame (including CRC, but excluding - /// parity and SoF/EoF framing) - RXDATABYTES: u9 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// address: 0x40005514 + /// Size of allocated for TXD and RXD data storage buffer in Data RAM + pub const MAXLEN = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x514); + + /// address: 0x40005590 + /// Last NFCID1 part (4, 7 or 10 bytes ID) + pub const NFCID1_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte Z (very last byte sent) + NFCID1_Z: u8, + /// NFCID1 byte Y + NFCID1_Y: u8, + /// NFCID1 byte X + NFCID1_X: u8, + /// NFCID1 byte W + NFCID1_W: u8, + }), base_address + 0x590); + + /// address: 0x40005594 + /// Second last NFCID1 part (7 or 10 bytes ID) + pub const NFCID1_2ND_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte V + NFCID1_V: u8, + /// NFCID1 byte U + NFCID1_U: u8, + /// NFCID1 byte T + NFCID1_T: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x594); + + /// address: 0x40005598 + /// Third last NFCID1 part (10 bytes ID) + pub const NFCID1_3RD_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + /// NFCID1 byte S + NFCID1_S: u8, + /// NFCID1 byte R + NFCID1_R: u8, + /// NFCID1 byte Q + NFCID1_Q: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x598); + + /// address: 0x400055a0 + /// NFC-A SENS_RES auto-response settings + pub const SENSRES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC + /// Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD: u5, + /// Reserved for future use. Shall be 0. + RFU5: u1, + /// NFCID1 size. This value is used by the Auto collision resolution engine. + NFCIDSIZE: u2, + /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES + /// response in the NFC Forum, NFC Digital Protocol Technical Specification + PLATFCONFIG: u4, + /// Reserved for future use. Shall be 0. + RFU74: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5a0); + + /// address: 0x400055a4 + /// NFC-A SEL_RES auto-response settings + pub const SELRES = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reserved for future use. Shall be 0. + RFU10: u2, + /// Cascade bit (controlled by hardware, write has no effect) + CASCADE: u1, + /// Reserved for future use. Shall be 0. + RFU43: u2, + /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC + /// Digital Protocol Technical Specification + PROTOCOL: u2, + /// Reserved for future use. Shall be 0. + RFU7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x5a4); + + pub const FRAMESTATUS = struct { + + /// address: 0x40005000 + /// Result of last incoming frames + pub const RX = @intToPtr(*volatile Mmio(32, packed struct{ + /// No valid End of Frame detected + CRCERROR: u1, + reserved0: u1, + /// Parity status of received frame + PARITYSTATUS: u1, + /// Overrun detected + OVERRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x0); + }; + + pub const TXD = struct { + + /// address: 0x40005000 + /// Configuration of outgoing frames + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Adding parity or not in the frame + PARITY: u1, + /// Discarding unused bits in start or at end of a Frame + DISCARDMODE: u1, + /// Adding SoF or not in TX frames + SOF: u1, + reserved0: u1, + /// CRC mode for outgoing frames + CRCMODETX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Size of outgoing frame + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of bits in the last or first byte read from RAM that shall be included in + /// the frame (excluding parity bit). + TXDATABITS: u3, + /// Number of complete bytes that shall be included in the frame, excluding CRC, + /// parity and framing + TXDATABYTES: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + }; + + pub const RXD = struct { + + /// address: 0x40005000 + /// Configuration of incoming frames + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity expected or not in RX frame + PARITY: u1, + reserved0: u1, + /// SoF expected or not in RX frames + SOF: u1, + reserved1: u1, + /// CRC mode for incoming frames + CRCMODERX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Size of last incoming frame + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of bits in the last byte in the frame, if less than 8 (including CRC, but + /// excluding parity and SoF/EoF framing). + RXDATABITS: u3, + /// Number of complete bytes received in the frame (including CRC, but excluding + /// parity and SoF/EoF framing) + RXDATABYTES: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + }; }; -}; - -/// GPIO Tasks and Events -pub const GPIOTE = extern struct { - pub const Address: u32 = 0x40006000; - - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - pub const EVENTS_PORT = @intToPtr(*volatile u32, Address + 0x0000017c); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for IN[0] event - IN0: u1 = 0, - /// Write '1' to Enable interrupt for IN[1] event - IN1: u1 = 0, - /// Write '1' to Enable interrupt for IN[2] event - IN2: u1 = 0, - /// Write '1' to Enable interrupt for IN[3] event - IN3: u1 = 0, - /// Write '1' to Enable interrupt for IN[4] event - IN4: u1 = 0, - /// Write '1' to Enable interrupt for IN[5] event - IN5: u1 = 0, - /// Write '1' to Enable interrupt for IN[6] event - IN6: u1 = 0, - /// Write '1' to Enable interrupt for IN[7] event - IN7: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for PORT event - PORT: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for IN[0] event - IN0: u1 = 0, - /// Write '1' to Disable interrupt for IN[1] event - IN1: u1 = 0, - /// Write '1' to Disable interrupt for IN[2] event - IN2: u1 = 0, - /// Write '1' to Disable interrupt for IN[3] event - IN3: u1 = 0, - /// Write '1' to Disable interrupt for IN[4] event - IN4: u1 = 0, - /// Write '1' to Disable interrupt for IN[5] event - IN5: u1 = 0, - /// Write '1' to Disable interrupt for IN[6] event - IN6: u1 = 0, - /// Write '1' to Disable interrupt for IN[7] event - IN7: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for PORT event - PORT: u1 = 0, - }); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. - pub const TASKS_OUT = @intToPtr(*volatile [8]u32, Address + 0x00000000); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is to set it high. - pub const TASKS_SET = @intToPtr(*volatile [8]u32, Address + 0x00000030); - /// Description collection[0]: Task for writing to pin specified in - /// CONFIG[0].PSEL. Action on pin is to set it low. - pub const TASKS_CLR = @intToPtr(*volatile [8]u32, Address + 0x00000060); - /// Description collection[0]: Event generated from pin specified in - /// CONFIG[0].PSEL - pub const EVENTS_IN = @intToPtr(*volatile [8]u32, Address + 0x00000100); - /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks - /// and IN[n] event - pub const CONFIG = @intToPtr(*volatile [8]MMIO(32, packed struct { - /// Mode - MODE: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - PSEL: u5 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// When In task mode: Operation to be performed on output when OUT[n] task is - /// triggered. When In event mode: Operation on input that shall trigger IN[n] - /// event. - POLARITY: u2 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - /// When in task mode: Initial value of the output when the GPIOTE channel is - /// configured. When in event mode: No effect. - OUTINIT: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000510); -}; - -/// Analog to Digital Converter -pub const SAADC = extern struct { - pub const Address: u32 = 0x40007000; - - /// Start the ADC and prepare the result buffer in RAM - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Take one ADC sample, if scan is enabled all channels are sampled - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Stop the ADC and terminate any on-going conversion - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Starts offset auto-calibration - pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// The ADC has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// The ADC has filled up the Result buffer - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// A conversion task has been completed. Depending on the mode, multiple - /// conversions might be needed for a result to be transferred to RAM. - pub const EVENTS_DONE = @intToPtr(*volatile u32, Address + 0x00000108); - - /// A result is ready to get transferred to RAM. - pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Calibration is complete - pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, Address + 0x00000110); - - /// The ADC has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - /// Enable or disable interrupt for END event - END: u1 = 0, - /// Enable or disable interrupt for DONE event - DONE: u1 = 0, - /// Enable or disable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Enable or disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Enable or disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Enable or disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Enable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Write '1' to Enable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Write '1' to Enable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Write '1' to Enable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for DONE event - DONE: u1 = 0, - /// Write '1' to Disable interrupt for RESULTDONE event - RESULTDONE: u1 = 0, - /// Write '1' to Disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1 = 0, - /// Write '1' to Disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1 = 0, - /// Write '1' to Disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status - pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { + /// GPIO Tasks and Events + pub const GPIOTE = struct { + pub const base_address = 0x40006000; + + /// address: 0x40006000 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is configured in CONFIG[0].POLARITY. + pub const TASKS_OUT = @intToPtr(*volatile [8]u32, base_address + 0x0); + + /// address: 0x40006030 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is to set it high. + pub const TASKS_SET = @intToPtr(*volatile [8]u32, base_address + 0x30); + + /// address: 0x40006060 + /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. + /// Action on pin is to set it low. + pub const TASKS_CLR = @intToPtr(*volatile [8]u32, base_address + 0x60); + + /// address: 0x40006100 + /// Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + pub const EVENTS_IN = @intToPtr(*volatile [8]u32, base_address + 0x100); + + /// address: 0x4000617c + /// Event generated from multiple input GPIO pins with SENSE mechanism enabled + pub const EVENTS_PORT = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x40006304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for IN[0] event + IN0: u1, + /// Write '1' to Enable interrupt for IN[1] event + IN1: u1, + /// Write '1' to Enable interrupt for IN[2] event + IN2: u1, + /// Write '1' to Enable interrupt for IN[3] event + IN3: u1, + /// Write '1' to Enable interrupt for IN[4] event + IN4: u1, + /// Write '1' to Enable interrupt for IN[5] event + IN5: u1, + /// Write '1' to Enable interrupt for IN[6] event + IN6: u1, + /// Write '1' to Enable interrupt for IN[7] event + IN7: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// Write '1' to Enable interrupt for PORT event + PORT: u1, + }), base_address + 0x304); + + /// address: 0x40006308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for IN[0] event + IN0: u1, + /// Write '1' to Disable interrupt for IN[1] event + IN1: u1, + /// Write '1' to Disable interrupt for IN[2] event + IN2: u1, + /// Write '1' to Disable interrupt for IN[3] event + IN3: u1, + /// Write '1' to Disable interrupt for IN[4] event + IN4: u1, + /// Write '1' to Disable interrupt for IN[5] event + IN5: u1, + /// Write '1' to Disable interrupt for IN[6] event + IN6: u1, + /// Write '1' to Disable interrupt for IN[7] event + IN7: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// Write '1' to Disable interrupt for PORT event + PORT: u1, + }), base_address + 0x308); + + /// address: 0x40006510 + /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and + /// IN[n] event + pub const CONFIG = @intToPtr(*volatile [8]Mmio(32, packed struct{ + /// Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + PSEL: u5, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// When In task mode: Operation to be performed on output when OUT[n] task is + /// triggered. When In event mode: Operation on input that shall trigger IN[n] + /// event. + POLARITY: u2, + reserved9: u1, + reserved10: u1, + /// When in task mode: Initial value of the output when the GPIOTE channel is + /// configured. When in event mode: No effect. + OUTINIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x510); + }; + /// Analog to Digital Converter + pub const SAADC = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// Start the ADC and prepare the result buffer in RAM + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40007004 + /// Take one ADC sample, if scan is enabled all channels are sampled + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40007008 + /// Stop the ADC and terminate any on-going conversion + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000700c + /// Starts offset auto-calibration + pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40007100 + /// The ADC has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40007104 + /// The ADC has filled up the Result buffer + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40007108 + /// A conversion task has been completed. Depending on the mode, multiple + /// conversions might be needed for a result to be transferred to RAM. + pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000710c + /// A result is ready to get transferred to RAM. + pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40007110 + /// Calibration is complete + pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40007114 + /// The ADC has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40007300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for STARTED event + STARTED: u1, + /// Enable or disable interrupt for END event + END: u1, + /// Enable or disable interrupt for DONE event + DONE: u1, + /// Enable or disable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x300); + + /// address: 0x40007304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for DONE event + DONE: u1, + /// Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40007308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for DONE event + DONE: u1, + /// Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE: u1, + /// Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH: u1, + /// Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL: u1, + /// Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH: u1, + /// Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL: u1, + /// Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH: u1, + /// Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL: u1, + /// Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH: u1, + /// Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL: u1, + /// Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH: u1, + /// Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL: u1, + /// Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH: u1, + /// Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL: u1, + /// Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH: u1, + /// Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL: u1, + /// Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH: u1, + /// Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40007400 /// Status - STATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable ADC - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { + pub const STATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40007500 /// Enable or disable ADC - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Resolution configuration - pub const RESOLUTION = mmio(Address + 0x000005f0, 32, packed struct { - /// Set the resolution - VAL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The - /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher - /// RESOLUTION should be used. - pub const OVERSAMPLE = mmio(Address + 0x000005f4, 32, packed struct { - /// Oversample control - OVERSAMPLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Controls normal or continuous sample rate - pub const SAMPLERATE = mmio(Address + 0x000005f8, 32, packed struct { - /// Capture and compare value. Sample rate is 16 MHz/CC - CC: u11 = 0, - reserved1: u1 = 0, - /// Select mode for sample rate control - MODE: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const RESULT = struct { - - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Maximum number of buffer words to transfer - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x400075f0 + /// Resolution configuration + pub const RESOLUTION = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set the resolution + VAL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x5f0); + + /// address: 0x400075f4 + /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The + /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher + /// RESOLUTION should be used. + pub const OVERSAMPLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x5f4); + + /// address: 0x400075f8 + /// Controls normal or continuous sample rate + pub const SAMPLERATE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture and compare value. Sample rate is 16 MHz/CC + CC: u11, + reserved0: u1, + /// Select mode for sample rate control + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x5f8); + + pub const EVENTS_CH = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH + LIMITH: u32, + + /// Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW + LIMITL: u32, + }, base_address + 0x118); + + pub const CH = @ptrCast(*volatile [8]packed struct { + /// Description cluster[0]: Input positive pin selection for CH[0] + PSELP: MmioInt(32, u5), + + /// Description cluster[0]: Input negative pin selection for CH[0] + PSELN: MmioInt(32, u5), + + /// Description cluster[0]: Input configuration for CH[0] + CONFIG: Mmio(32, packed struct{ + /// Positive channel resistor control + RESP: u2, + reserved0: u1, + reserved1: u1, + /// Negative channel resistor control + RESN: u2, + reserved2: u1, + reserved3: u1, + /// Gain control + GAIN: u3, + reserved4: u1, + /// Reference control + REFSEL: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Acquisition time, the time the ADC uses to sample the input voltage + TACQ: u3, + reserved8: u1, + /// Enable differential mode + MODE: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Enable burst mode + BURST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), + + /// Description cluster[0]: High/low limits for event monitoring a channel + LIMIT: Mmio(32, packed struct{ + /// Low level limit + LOW: u16, + /// High level limit + HIGH: u16, + }), + }, base_address + 0x510); + + /// RESULT EasyDMA channel + pub const RESULT = struct { + + /// address: 0x40007000 + /// Data pointer + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40007004 /// Maximum number of buffer words to transfer - MAXCNT: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of buffer words transferred since last START - pub const AMOUNT = mmio(Address + 0x00000008, 32, packed struct { - /// Number of buffer words transferred since last START. This register can be - /// read after an END or STOPPED event. - AMOUNT: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; -}; - -/// Timer/Counter 0 -pub const TIMER0 = extern struct { - pub const Address: u32 = 0x40008000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x4); -/// Timer/Counter 1 -pub const TIMER1 = extern struct { - pub const Address: u32 = 0x40009000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; - -/// Timer/Counter 2 -pub const TIMER2 = extern struct { - pub const Address: u32 = 0x4000a000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; - -/// Real time counter 0 -pub const RTC0 = extern struct { - pub const Address: u32 = 0x4000b000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; - -/// Temperature Sensor -pub const TEMP = extern struct { - pub const Address: u32 = 0x4000c000; - - /// Start temperature measurement - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop temperature measurement - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Temperature measurement complete, data ready - pub const EVENTS_DATARDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for DATARDY event - DATARDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for DATARDY event - DATARDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Temperature in degC (0.25deg steps) - pub const TEMP = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Slope of 1st piece wise linear function - pub const A0 = mmio(Address + 0x00000520, 32, packed struct { + /// address: 0x40007008 + /// Number of buffer words transferred since last START + pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x8); + }; + }; + /// Timer/Counter 0 + pub const TIMER0 = struct { + pub const base_address = 0x40008000; + + /// address: 0x40008000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40008004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40008008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000800c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40008010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40008040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x40008140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x40008200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40008304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40008308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40008504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x40008508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x40008510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40008540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 1 + pub const TIMER1 = struct { + pub const base_address = 0x40009000; + + /// address: 0x40009000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40009004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40009008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000900c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40009010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40009040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x40009140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x40009200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40009304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x40009308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x40009504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x40009508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x40009510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x40009540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 2 + pub const TIMER2 = struct { + pub const base_address = 0x4000a000; + + /// address: 0x4000a000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000a004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000a008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000a00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000a010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4000a040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4000a140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4000a200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4000a304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4000a308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4000a504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4000a508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4000a510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4000a540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Real time counter 0 + pub const RTC0 = struct { + pub const base_address = 0x4000b000; + + /// address: 0x4000b000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000b004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000b008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000b00c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4000b100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000b104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000b140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x4000b304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x4000b308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x4000b340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x4000b344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x4000b348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x4000b504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x4000b508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x4000b540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Temperature Sensor + pub const TEMP = struct { + pub const base_address = 0x4000c000; + + /// address: 0x4000c000 + /// Start temperature measurement + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000c004 + /// Stop temperature measurement + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000c100 + /// Temperature measurement complete, data ready + pub const EVENTS_DATARDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000c304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for DATARDY event + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x4000c308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for DATARDY event + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x4000c508 + /// Temperature in degC (0.25deg steps) + pub const TEMP = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000c520 /// Slope of 1st piece wise linear function - A0: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 2nd piece wise linear function - pub const A1 = mmio(Address + 0x00000524, 32, packed struct { + pub const A0 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x520); + + /// address: 0x4000c524 /// Slope of 2nd piece wise linear function - A1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 3rd piece wise linear function - pub const A2 = mmio(Address + 0x00000528, 32, packed struct { + pub const A1 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x524); + + /// address: 0x4000c528 /// Slope of 3rd piece wise linear function - A2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 4th piece wise linear function - pub const A3 = mmio(Address + 0x0000052c, 32, packed struct { + pub const A2 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x528); + + /// address: 0x4000c52c /// Slope of 4th piece wise linear function - A3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 5th piece wise linear function - pub const A4 = mmio(Address + 0x00000530, 32, packed struct { + pub const A3 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x52c); + + /// address: 0x4000c530 /// Slope of 5th piece wise linear function - A4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Slope of 6th piece wise linear function - pub const A5 = mmio(Address + 0x00000534, 32, packed struct { + pub const A4 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x530); + + /// address: 0x4000c534 /// Slope of 6th piece wise linear function - A5: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 1st piece wise linear function - pub const B0 = mmio(Address + 0x00000540, 32, packed struct { + pub const A5 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x534); + + /// address: 0x4000c540 /// y-intercept of 1st piece wise linear function - B0: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 2nd piece wise linear function - pub const B1 = mmio(Address + 0x00000544, 32, packed struct { + pub const B0 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x540); + + /// address: 0x4000c544 /// y-intercept of 2nd piece wise linear function - B1: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 3rd piece wise linear function - pub const B2 = mmio(Address + 0x00000548, 32, packed struct { + pub const B1 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x544); + + /// address: 0x4000c548 /// y-intercept of 3rd piece wise linear function - B2: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 4th piece wise linear function - pub const B3 = mmio(Address + 0x0000054c, 32, packed struct { + pub const B2 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x548); + + /// address: 0x4000c54c /// y-intercept of 4th piece wise linear function - B3: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 5th piece wise linear function - pub const B4 = mmio(Address + 0x00000550, 32, packed struct { + pub const B3 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x54c); + + /// address: 0x4000c550 /// y-intercept of 5th piece wise linear function - B4: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// y-intercept of 6th piece wise linear function - pub const B5 = mmio(Address + 0x00000554, 32, packed struct { + pub const B4 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x550); + + /// address: 0x4000c554 /// y-intercept of 6th piece wise linear function - B5: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 1st piece wise linear function - pub const T0 = mmio(Address + 0x00000560, 32, packed struct { + pub const B5 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x554); + + /// address: 0x4000c560 /// End point of 1st piece wise linear function - T0: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 2nd piece wise linear function - pub const T1 = mmio(Address + 0x00000564, 32, packed struct { + pub const T0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x560); + + /// address: 0x4000c564 /// End point of 2nd piece wise linear function - T1: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 3rd piece wise linear function - pub const T2 = mmio(Address + 0x00000568, 32, packed struct { + pub const T1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x564); + + /// address: 0x4000c568 /// End point of 3rd piece wise linear function - T2: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 4th piece wise linear function - pub const T3 = mmio(Address + 0x0000056c, 32, packed struct { + pub const T2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x568); + + /// address: 0x4000c56c /// End point of 4th piece wise linear function - T3: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// End point of 5th piece wise linear function - pub const T4 = mmio(Address + 0x00000570, 32, packed struct { + pub const T3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x56c); + + /// address: 0x4000c570 /// End point of 5th piece wise linear function - T4: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const T4 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x570); + }; + /// Random Number Generator + pub const RNG = struct { + pub const base_address = 0x4000d000; + + /// address: 0x4000d000 + /// Task starting the random number generator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000d004 + /// Task stopping the random number generator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000d100 + /// Event being generated for every new random number written to the VALUE register + pub const EVENTS_VALRDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000d200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between VALRDY event and STOP task + VALRDY_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x4000d304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for VALRDY event + VALRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x4000d308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for VALRDY event + VALRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x4000d504 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bias correction + DERCEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x4000d508 + /// Output random number + pub const VALUE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x508); + }; + /// AES ECB Mode Encryption + pub const ECB = struct { + pub const base_address = 0x4000e000; + + /// address: 0x4000e000 + /// Start ECB block encrypt + pub const TASKS_STARTECB = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000e004 + /// Abort a possible executing ECB operation + pub const TASKS_STOPECB = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000e100 + /// ECB block encrypt complete + pub const EVENTS_ENDECB = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000e104 + /// ECB block encrypt aborted because of a STOPECB task or due to an error + pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000e304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for ENDECB event + ENDECB: u1, + /// Write '1' to Enable interrupt for ERRORECB event + ERRORECB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x304); + + /// address: 0x4000e308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for ENDECB event + ENDECB: u1, + /// Write '1' to Disable interrupt for ERRORECB event + ERRORECB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x308); + + /// address: 0x4000e504 + /// ECB block encrypt memory pointers + pub const ECBDATAPTR = @intToPtr(*volatile u32, base_address + 0x504); + }; + /// AES CCM Mode Encryption + pub const CCM = struct { + pub const base_address = 0x4000f000; + + /// address: 0x4000f000 + /// Start generation of key-stream. This operation will stop by itself when + /// completed. + pub const TASKS_KSGEN = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000f004 + /// Start encryption/decryption. This operation will stop by itself when completed. + pub const TASKS_CRYPT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4000f008 + /// Stop encryption/decryption + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000f100 + /// Key-stream generation complete + pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000f104 + /// Encrypt/decrypt complete + pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000f108 + /// CCM error event + pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000f200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x4000f304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN: u1, + /// Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT: u1, + /// Write '1' to Enable interrupt for ERROR event + ERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4000f308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN: u1, + /// Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT: u1, + /// Write '1' to Disable interrupt for ERROR event + ERROR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4000f400 + /// MIC check result + pub const MICSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x4000f500 + /// Enable + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x4000f504 + /// Operation mode + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// The mode of operation to be used + MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Data rate that the CCM shall run in synch with + DATARATE: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Packet length configuration + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x504); + + /// address: 0x4000f508 + /// Pointer to data structure holding AES key and NONCE vector + pub const CNFPTR = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000f50c + /// Input pointer + pub const INPTR = @intToPtr(*volatile u32, base_address + 0x50c); + + /// address: 0x4000f510 + /// Output pointer + pub const OUTPTR = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4000f514 + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); + }; + /// Accelerated Address Resolver + pub const AAR = struct { + pub const base_address = 0x4000f000; + + /// address: 0x4000f000 + /// Start resolving addresses based on IRKs specified in the IRK data structure + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4000f008 + /// Stop resolving addresses + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000f100 + /// Address resolution procedure complete + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4000f104 + /// Address resolved + pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4000f108 + /// Address not resolved + pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4000f304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for END event + END: u1, + /// Write '1' to Enable interrupt for RESOLVED event + RESOLVED: u1, + /// Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4000f308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for END event + END: u1, + /// Write '1' to Disable interrupt for RESOLVED event + RESOLVED: u1, + /// Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4000f400 + /// Resolution status + pub const STATUS = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x400); + + /// address: 0x4000f500 + /// Enable AAR + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x4000f504 + /// Number of IRKs + pub const NIRK = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x504); + + /// address: 0x4000f508 + /// Pointer to IRK data structure + pub const IRKPTR = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4000f510 + /// Pointer to the resolvable address + pub const ADDRPTR = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4000f514 + /// Pointer to data area used for temporary storage + pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); + }; + /// Watchdog Timer + pub const WDT = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// Start the watchdog + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40010100 + /// Watchdog timeout + pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40010304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x304); + + /// address: 0x40010308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x308); + + /// address: 0x40010400 + /// Run status + pub const RUNSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40010404 + /// Request status + pub const REQSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Request status for RR[0] register + RR0: u1, + /// Request status for RR[1] register + RR1: u1, + /// Request status for RR[2] register + RR2: u1, + /// Request status for RR[3] register + RR3: u1, + /// Request status for RR[4] register + RR4: u1, + /// Request status for RR[5] register + RR5: u1, + /// Request status for RR[6] register + RR6: u1, + /// Request status for RR[7] register + RR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x404); + + /// address: 0x40010504 + /// Counter reload value + pub const CRV = @intToPtr(*volatile u32, base_address + 0x504); + + /// address: 0x40010508 + /// Enable register for reload request registers + pub const RREN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable RR[0] register + RR0: u1, + /// Enable or disable RR[1] register + RR1: u1, + /// Enable or disable RR[2] register + RR2: u1, + /// Enable or disable RR[3] register + RR3: u1, + /// Enable or disable RR[4] register + RR4: u1, + /// Enable or disable RR[5] register + RR5: u1, + /// Enable or disable RR[6] register + RR6: u1, + /// Enable or disable RR[7] register + RR7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x508); + + /// address: 0x4001050c + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Configure the watchdog to either be paused, or kept running, while the CPU is + /// sleeping + SLEEP: u1, + reserved0: u1, + reserved1: u1, + /// Configure the watchdog to either be paused, or kept running, while the CPU is + /// halted by the debugger + HALT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x50c); + + /// address: 0x40010600 + /// Description collection[0]: Reload request 0 + pub const RR = @intToPtr(*volatile [8]u32, base_address + 0x600); + }; + /// Real time counter 1 + pub const RTC1 = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40011004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40011008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001100c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40011100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40011104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40011140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x40011304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40011308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40011340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x40011344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x40011348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x40011504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x40011508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x40011540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Quadrature Decoder + pub const QDEC = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// Task starting the quadrature decoder + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40012004 + /// Task stopping the quadrature decoder + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40012008 + /// Read and clear ACC and ACCDBL + pub const TASKS_READCLRACC = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001200c + /// Read and clear ACC + pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40012010 + /// Read and clear ACCDBL + pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40012100 + /// Event being generated for every new sample value written to the SAMPLE register + pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40012104 + /// Non-null report ready + pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40012108 + /// ACC or ACCDBL register overflow + pub const EVENTS_ACCOF = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001210c + /// Double displacement(s) detected + pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40012110 + /// QDEC has been stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40012200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC: u1, + /// Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP: u1, + /// Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC: u1, + /// Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP: u1, + /// Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL: u1, + /// Shortcut between DBLRDY event and STOP task + DBLRDY_STOP: u1, + /// Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x200); + + /// address: 0x40012304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY: u1, + /// Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY: u1, + /// Write '1' to Enable interrupt for ACCOF event + ACCOF: u1, + /// Write '1' to Enable interrupt for DBLRDY event + DBLRDY: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x304); + + /// address: 0x40012308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY: u1, + /// Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY: u1, + /// Write '1' to Disable interrupt for ACCOF event + ACCOF: u1, + /// Write '1' to Disable interrupt for DBLRDY event + DBLRDY: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x308); + + /// address: 0x40012500 + /// Enable the quadrature decoder + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40012504 + /// LED output pin polarity + pub const LEDPOL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x504); -/// Random Number Generator -pub const RNG = extern struct { - pub const Address: u32 = 0x4000d000; - - /// Task starting the random number generator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Task stopping the random number generator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Event being generated for every new random number written to the VALUE - /// register - pub const EVENTS_VALRDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between VALRDY event and STOP task - VALRDY_STOP: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for VALRDY event - VALRDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for VALRDY event - VALRDY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { - /// Bias correction - DERCEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Output random number - pub const VALUE = mmio(Address + 0x00000508, 32, packed struct { - /// Generated random number - VALUE: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x40012508 + /// Sample period + pub const SAMPLEPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); -/// AES ECB Mode Encryption -pub const ECB = extern struct { - pub const Address: u32 = 0x4000e000; - - /// Start ECB block encrypt - pub const TASKS_STARTECB = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Abort a possible executing ECB operation - pub const TASKS_STOPECB = @intToPtr(*volatile u32, Address + 0x00000004); - - /// ECB block encrypt complete - pub const EVENTS_ENDECB = @intToPtr(*volatile u32, Address + 0x00000100); - - /// ECB block encrypt aborted because of a STOPECB task or due to an error - pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for ENDECB event - ENDECB: u1 = 0, - /// Write '1' to Enable interrupt for ERRORECB event - ERRORECB: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for ENDECB event - ENDECB: u1 = 0, - /// Write '1' to Disable interrupt for ERRORECB event - ERRORECB: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ECB block encrypt memory pointers - pub const ECBDATAPTR = @intToPtr(*volatile u32, Address + 0x00000504); -}; + /// address: 0x4001250c + /// Motion sample value + pub const SAMPLE = @intToPtr(*volatile u32, base_address + 0x50c); -/// AES CCM Mode Encryption -pub const CCM = extern struct { - pub const Address: u32 = 0x4000f000; - - /// Start generation of key-stream. This operation will stop by itself when - /// completed. - pub const TASKS_KSGEN = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Start encryption/decryption. This operation will stop by itself when - /// completed. - pub const TASKS_CRYPT = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Stop encryption/decryption - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Key-stream generation complete - pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Encrypt/decrypt complete - pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, Address + 0x00000104); - - /// CCM error event - pub const EVENTS_ERROR = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between ENDKSGEN event and CRYPT task - ENDKSGEN_CRYPT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for ENDKSGEN event - ENDKSGEN: u1 = 0, - /// Write '1' to Enable interrupt for ENDCRYPT event - ENDCRYPT: u1 = 0, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for ENDKSGEN event - ENDKSGEN: u1 = 0, - /// Write '1' to Disable interrupt for ENDCRYPT event - ENDCRYPT: u1 = 0, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MIC check result - pub const MICSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// The result of the MIC check performed during the previous decryption - /// operation - MICSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable CCM - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Operation mode - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// The mode of operation to be used - MODE: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Data rate that the CCM shall run in synch with - DATARATE: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - /// Packet length configuration - LENGTH: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pointer to data structure holding AES key and NONCE vector - pub const CNFPTR = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Input pointer - pub const INPTR = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Output pointer - pub const OUTPTR = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); -}; + /// address: 0x40012510 + /// Number of samples to be taken before REPORTRDY and DBLRDY events can be + /// generated + pub const REPORTPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); -/// Accelerated Address Resolver -pub const AAR = extern struct { - pub const Address: u32 = 0x4000f000; - - /// Start resolving addresses based on IRKs specified in the IRK data structure - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop resolving addresses - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Address resolution procedure complete - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Address resolved - pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Address not resolved - pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - /// Write '1' to Enable interrupt for RESOLVED event - RESOLVED: u1 = 0, - /// Write '1' to Enable interrupt for NOTRESOLVED event - NOTRESOLVED: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - /// Write '1' to Disable interrupt for RESOLVED event - RESOLVED: u1 = 0, - /// Write '1' to Disable interrupt for NOTRESOLVED event - NOTRESOLVED: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Resolution status - pub const STATUS = mmio(Address + 0x00000400, 32, packed struct { - /// The IRK that was used last time an address was resolved - STATUS: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable AAR - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable AAR - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Number of IRKs - pub const NIRK = mmio(Address + 0x00000504, 32, packed struct { - /// Number of Identity root keys available in the IRK data structure - NIRK: u5 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pointer to IRK data structure - pub const IRKPTR = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Pointer to the resolvable address - pub const ADDRPTR = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, Address + 0x00000514); -}; + /// address: 0x40012514 + /// Register accumulating the valid transitions + pub const ACC = @intToPtr(*volatile u32, base_address + 0x514); -/// Watchdog Timer -pub const WDT = extern struct { - pub const Address: u32 = 0x40010000; - - /// Start the watchdog - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Watchdog timeout - pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TIMEOUT event - TIMEOUT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TIMEOUT event - TIMEOUT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Run status - pub const RUNSTATUS = mmio(Address + 0x00000400, 32, packed struct { - /// Indicates whether or not the watchdog is running - RUNSTATUS: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Request status - pub const REQSTATUS = mmio(Address + 0x00000404, 32, packed struct { - /// Request status for RR[0] register - RR0: u1 = 0, - /// Request status for RR[1] register - RR1: u1 = 0, - /// Request status for RR[2] register - RR2: u1 = 0, - /// Request status for RR[3] register - RR3: u1 = 0, - /// Request status for RR[4] register - RR4: u1 = 0, - /// Request status for RR[5] register - RR5: u1 = 0, - /// Request status for RR[6] register - RR6: u1 = 0, - /// Request status for RR[7] register - RR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Counter reload value - pub const CRV = @intToPtr(*volatile u32, Address + 0x00000504); - - /// Enable register for reload request registers - pub const RREN = mmio(Address + 0x00000508, 32, packed struct { - /// Enable or disable RR[0] register - RR0: u1 = 0, - /// Enable or disable RR[1] register - RR1: u1 = 0, - /// Enable or disable RR[2] register - RR2: u1 = 0, - /// Enable or disable RR[3] register - RR3: u1 = 0, - /// Enable or disable RR[4] register - RR4: u1 = 0, - /// Enable or disable RR[5] register - RR5: u1 = 0, - /// Enable or disable RR[6] register - RR6: u1 = 0, - /// Enable or disable RR[7] register - RR7: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x0000050c, 32, packed struct { - /// Configure the watchdog to either be paused, or kept running, while the CPU - /// is sleeping - SLEEP: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Configure the watchdog to either be paused, or kept running, while the CPU - /// is halted by the debugger - HALT: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Reload request 0 - pub const RR = @intToPtr(*volatile [8]u32, Address + 0x00000600); -}; - -/// Real time counter 1 -pub const RTC1 = extern struct { - pub const Address: u32 = 0x40011000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; + /// address: 0x40012518 + /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + pub const ACCREAD = @intToPtr(*volatile u32, base_address + 0x518); -/// Quadrature Decoder -pub const QDEC = extern struct { - pub const Address: u32 = 0x40012000; - - /// Task starting the quadrature decoder - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Task stopping the quadrature decoder - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Read and clear ACC and ACCDBL - pub const TASKS_READCLRACC = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Read and clear ACC - pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Read and clear ACCDBL - pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Event being generated for every new sample value written to the SAMPLE - /// register - pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Non-null report ready - pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, Address + 0x00000104); - - /// ACC or ACCDBL register overflow - pub const EVENTS_ACCOF = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Double displacement(s) detected - pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// QDEC has been stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between REPORTRDY event and READCLRACC task - REPORTRDY_READCLRACC: u1 = 0, - /// Shortcut between SAMPLERDY event and STOP task - SAMPLERDY_STOP: u1 = 0, - /// Shortcut between REPORTRDY event and RDCLRACC task - REPORTRDY_RDCLRACC: u1 = 0, - /// Shortcut between REPORTRDY event and STOP task - REPORTRDY_STOP: u1 = 0, - /// Shortcut between DBLRDY event and RDCLRDBL task - DBLRDY_RDCLRDBL: u1 = 0, - /// Shortcut between DBLRDY event and STOP task - DBLRDY_STOP: u1 = 0, - /// Shortcut between SAMPLERDY event and READCLRACC task - SAMPLERDY_READCLRACC: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for SAMPLERDY event - SAMPLERDY: u1 = 0, - /// Write '1' to Enable interrupt for REPORTRDY event - REPORTRDY: u1 = 0, - /// Write '1' to Enable interrupt for ACCOF event - ACCOF: u1 = 0, - /// Write '1' to Enable interrupt for DBLRDY event - DBLRDY: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for SAMPLERDY event - SAMPLERDY: u1 = 0, - /// Write '1' to Disable interrupt for REPORTRDY event - REPORTRDY: u1 = 0, - /// Write '1' to Disable interrupt for ACCOF event - ACCOF: u1 = 0, - /// Write '1' to Disable interrupt for DBLRDY event - DBLRDY: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable the quadrature decoder - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable the quadrature decoder - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// LED output pin polarity - pub const LEDPOL = mmio(Address + 0x00000504, 32, packed struct { - /// LED output pin polarity - LEDPOL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Sample period - pub const SAMPLEPER = mmio(Address + 0x00000508, 32, packed struct { - /// Sample period. The SAMPLE register will be updated for every new sample - SAMPLEPER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Motion sample value - pub const SAMPLE = @intToPtr(*volatile u32, Address + 0x0000050c); - - /// Number of samples to be taken before REPORTRDY and DBLRDY events can be - /// generated - pub const REPORTPER = mmio(Address + 0x00000510, 32, packed struct { - /// Specifies the number of samples to be accumulated in the ACC register before - /// the REPORTRDY and DBLRDY events can be generated - REPORTPER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register accumulating the valid transitions - pub const ACC = @intToPtr(*volatile u32, Address + 0x00000514); - - /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - pub const ACCREAD = @intToPtr(*volatile u32, Address + 0x00000518); - - /// Enable input debounce filters - pub const DBFEN = mmio(Address + 0x00000528, 32, packed struct { + /// address: 0x40012528 /// Enable input debounce filters - DBFEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Time period the LED is switched ON prior to sampling - pub const LEDPRE = mmio(Address + 0x00000540, 32, packed struct { - /// Period in us the LED is switched on prior to sampling - LEDPRE: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register accumulating the number of detected double transitions - pub const ACCDBL = mmio(Address + 0x00000544, 32, packed struct { - /// Register accumulating the number of detected double or illegal transitions. - /// ( SAMPLE = 2 ). - ACCDBL: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - pub const ACCDBLREAD = mmio(Address + 0x00000548, 32, packed struct { - /// Snapshot of the ACCDBL register. This field is updated when the READCLRACC - /// or RDCLRDBL task is triggered. - ACCDBLREAD: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin select for LED signal - pub const LED = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for A signal - pub const A = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for B signal - pub const B = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + pub const DBFEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x528); + + /// address: 0x40012540 + /// Time period the LED is switched ON prior to sampling + pub const LEDPRE = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x540); + + /// address: 0x40012544 + /// Register accumulating the number of detected double transitions + pub const ACCDBL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x544); + + /// address: 0x40012548 + /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + pub const ACCDBLREAD = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x548); + + pub const PSEL = struct { + + /// address: 0x40012000 + /// Pin select for LED signal + pub const LED = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40012004 + /// Pin select for A signal + pub const A = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40012008 + /// Pin select for B signal + pub const B = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + }; }; -}; + /// Comparator + pub const COMP = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40013004 + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40013008 + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40013100 + /// COMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40013104 + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40013108 + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001310c + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40013200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1, + /// Shortcut between READY event and STOP task + READY_STOP: u1, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1, + /// Shortcut between UP event and STOP task + UP_STOP: u1, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40013300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for READY event + READY: u1, + /// Enable or disable interrupt for DOWN event + DOWN: u1, + /// Enable or disable interrupt for UP event + UP: u1, + /// Enable or disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x300); + + /// address: 0x40013304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Enable interrupt for UP event + UP: u1, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x304); + + /// address: 0x40013308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Disable interrupt for UP event + UP: u1, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x308); + + /// address: 0x40013400 + /// Compare result + pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40013500 + /// COMP enable + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x40013504 + /// Pin select + pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); + + /// address: 0x40013508 + /// Reference source select for single-ended mode + pub const REFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x508); + + /// address: 0x4001350c + /// External reference select + pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40013530 + /// Threshold configuration for hysteresis unit + pub const TH = @intToPtr(*volatile Mmio(32, packed struct{ + /// VDOWN = (THDOWN+1)/64*VREF + THDOWN: u6, + reserved0: u1, + reserved1: u1, + /// VUP = (THUP+1)/64*VREF + THUP: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x530); + + /// address: 0x40013534 + /// Mode configuration + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Speed and power modes + SP: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Main operation modes + MAIN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x534); + + /// address: 0x40013538 + /// Comparator hysteresis enable + pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); -/// Comparator -pub const COMP = extern struct { - pub const Address: u32 = 0x40013000; - - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// COMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1 = 0, - /// Shortcut between READY event and STOP task - READY_STOP: u1 = 0, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1 = 0, - /// Shortcut between UP event and STOP task - UP_STOP: u1 = 0, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1 = 0, - /// Enable or disable interrupt for DOWN event - DOWN: u1 = 0, - /// Enable or disable interrupt for UP event - UP: u1 = 0, - /// Enable or disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Enable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Disable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Compare result - pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { - /// Result of last compare. Decision point SAMPLE task. - RESULT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// COMP enable - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable COMP - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pin select - pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { - /// Analog pin select - PSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reference source select for single-ended mode - pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { + /// address: 0x4001353c + /// Current source select on analog input + pub const ISOURCE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x53c); + }; + /// Low Power Comparator + pub const LPCOMP = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// Start comparator + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40013004 + /// Stop comparator + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40013008 + /// Sample comparator value + pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x40013100 + /// LPCOMP is ready and output is valid + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40013104 + /// Downward crossing + pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40013108 + /// Upward crossing + pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001310c + /// Downward or upward crossing + pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x40013200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between READY event and SAMPLE task + READY_SAMPLE: u1, + /// Shortcut between READY event and STOP task + READY_STOP: u1, + /// Shortcut between DOWN event and STOP task + DOWN_STOP: u1, + /// Shortcut between UP event and STOP task + UP_STOP: u1, + /// Shortcut between CROSS event and STOP task + CROSS_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40013304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for READY event + READY: u1, + /// Write '1' to Enable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Enable interrupt for UP event + UP: u1, + /// Write '1' to Enable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x304); + + /// address: 0x40013308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for READY event + READY: u1, + /// Write '1' to Disable interrupt for DOWN event + DOWN: u1, + /// Write '1' to Disable interrupt for UP event + UP: u1, + /// Write '1' to Disable interrupt for CROSS event + CROSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x308); + + /// address: 0x40013400 + /// Compare result + pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x40013500 + /// Enable LPCOMP + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); + + /// address: 0x40013504 + /// Input pin select + pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); + + /// address: 0x40013508 /// Reference select - REFSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External reference select - pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { - /// External analog reference select - EXTREFSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Threshold configuration for hysteresis unit - pub const TH = mmio(Address + 0x00000530, 32, packed struct { - /// VDOWN = (THDOWN+1)/64*VREF - THDOWN: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// VUP = (THUP+1)/64*VREF - THUP: u6 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Mode configuration - pub const MODE = mmio(Address + 0x00000534, 32, packed struct { - /// Speed and power modes - SP: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Main operation modes - MAIN: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Comparator hysteresis enable - pub const HYST = mmio(Address + 0x00000538, 32, packed struct { - /// Comparator hysteresis - HYST: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current source select on analog input - pub const ISOURCE = mmio(Address + 0x0000053c, 32, packed struct { - /// Comparator hysteresis - ISOURCE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const REFSEL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); -/// Low Power Comparator -pub const LPCOMP = extern struct { - pub const Address: u32 = 0x40013000; - - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, Address + 0x00000008); - - /// LPCOMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, Address + 0x0000010c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1 = 0, - /// Shortcut between READY event and STOP task - READY_STOP: u1 = 0, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1 = 0, - /// Shortcut between UP event and STOP task - UP_STOP: u1 = 0, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Enable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1 = 0, - /// Write '1' to Disable interrupt for UP event - UP: u1 = 0, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Compare result - pub const RESULT = mmio(Address + 0x00000400, 32, packed struct { - /// Result of last compare. Decision point SAMPLE task. - RESULT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable LPCOMP - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable LPCOMP - ENABLE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Input pin select - pub const PSEL = mmio(Address + 0x00000504, 32, packed struct { - /// Analog pin select - PSEL: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reference select - pub const REFSEL = mmio(Address + 0x00000508, 32, packed struct { - /// Reference select - REFSEL: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External reference select - pub const EXTREFSEL = mmio(Address + 0x0000050c, 32, packed struct { - /// External analog reference select - EXTREFSEL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog detect configuration - pub const ANADETECT = mmio(Address + 0x00000520, 32, packed struct { - /// Analog detect configuration - ANADETECT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Comparator hysteresis enable - pub const HYST = mmio(Address + 0x00000538, 32, packed struct { - /// Comparator hysteresis enable - HYST: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + /// address: 0x4001350c + /// External reference select + pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); -/// Software interrupt 0 -pub const SWI0 = extern struct { - pub const Address: u32 = 0x40014000; + /// address: 0x40013520 + /// Analog detect configuration + pub const ANADETECT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x520); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40013538 + /// Comparator hysteresis enable + pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); + }; + /// Software interrupt 0 + pub const SWI0 = struct { + pub const base_address = 0x40014000; -/// Event Generator Unit 0 -pub const EGU0 = extern struct { - pub const Address: u32 = 0x40014000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40014000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 0 + pub const EGU0 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40014100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40014300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40014304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40014308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 1 + pub const SWI1 = struct { + pub const base_address = 0x40015000; -/// Software interrupt 1 -pub const SWI1 = extern struct { - pub const Address: u32 = 0x40015000; + /// address: 0x40015000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 1 + pub const EGU1 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40015100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40015300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40015304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40015308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 2 + pub const SWI2 = struct { + pub const base_address = 0x40016000; - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40016000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 2 + pub const EGU2 = struct { + pub const base_address = 0x40016000; + + /// address: 0x40016000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40016100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40016300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40016304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40016308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 3 + pub const SWI3 = struct { + pub const base_address = 0x40017000; -/// Event Generator Unit 1 -pub const EGU1 = extern struct { - pub const Address: u32 = 0x40015000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40017000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 3 + pub const EGU3 = struct { + pub const base_address = 0x40017000; + + /// address: 0x40017000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40017100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40017300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40017304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40017308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 4 + pub const SWI4 = struct { + pub const base_address = 0x40018000; -/// Software interrupt 2 -pub const SWI2 = extern struct { - pub const Address: u32 = 0x40016000; + /// address: 0x40018000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 4 + pub const EGU4 = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40018100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40018300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40018304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40018308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Software interrupt 5 + pub const SWI5 = struct { + pub const base_address = 0x40019000; - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40019000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); + }; + /// Event Generator Unit 5 + pub const EGU5 = struct { + pub const base_address = 0x40019000; + + /// address: 0x40019000 + /// Description collection[0]: Trigger 0 for triggering the corresponding + /// TRIGGERED[0] event + pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); + + /// address: 0x40019100 + /// Description collection[0]: Event number 0 generated by triggering the + /// corresponding TRIGGER[0] task + pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); + + /// address: 0x40019300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Enable or disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Enable or disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Enable or disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Enable or disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Enable or disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Enable or disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Enable or disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Enable or disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Enable or disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Enable or disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Enable or disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Enable or disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Enable or disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Enable or disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Enable or disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x300); + + /// address: 0x40019304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Enable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Enable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Enable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Enable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Enable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Enable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Enable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Enable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Enable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Enable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Enable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Enable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Enable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Enable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Enable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x304); + + /// address: 0x40019308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED0: u1, + /// Write '1' to Disable interrupt for TRIGGERED[1] event + TRIGGERED1: u1, + /// Write '1' to Disable interrupt for TRIGGERED[2] event + TRIGGERED2: u1, + /// Write '1' to Disable interrupt for TRIGGERED[3] event + TRIGGERED3: u1, + /// Write '1' to Disable interrupt for TRIGGERED[4] event + TRIGGERED4: u1, + /// Write '1' to Disable interrupt for TRIGGERED[5] event + TRIGGERED5: u1, + /// Write '1' to Disable interrupt for TRIGGERED[6] event + TRIGGERED6: u1, + /// Write '1' to Disable interrupt for TRIGGERED[7] event + TRIGGERED7: u1, + /// Write '1' to Disable interrupt for TRIGGERED[8] event + TRIGGERED8: u1, + /// Write '1' to Disable interrupt for TRIGGERED[9] event + TRIGGERED9: u1, + /// Write '1' to Disable interrupt for TRIGGERED[10] event + TRIGGERED10: u1, + /// Write '1' to Disable interrupt for TRIGGERED[11] event + TRIGGERED11: u1, + /// Write '1' to Disable interrupt for TRIGGERED[12] event + TRIGGERED12: u1, + /// Write '1' to Disable interrupt for TRIGGERED[13] event + TRIGGERED13: u1, + /// Write '1' to Disable interrupt for TRIGGERED[14] event + TRIGGERED14: u1, + /// Write '1' to Disable interrupt for TRIGGERED[15] event + TRIGGERED15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x308); + }; + /// Timer/Counter 3 + pub const TIMER3 = struct { + pub const base_address = 0x4001a000; + + /// address: 0x4001a000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001a004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001a008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001a00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4001a010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001a040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4001a140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4001a200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4001a304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4001a308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4001a504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4001a508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4001a510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4001a540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Timer/Counter 4 + pub const TIMER4 = struct { + pub const base_address = 0x4001b000; + + /// address: 0x4001b000 + /// Start Timer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001b004 + /// Stop Timer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001b008 + /// Increment Timer (Counter mode only) + pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4001b00c + /// Clear time + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x4001b010 + /// Deprecated register - Shut down timer + pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001b040 + /// Description collection[0]: Capture Timer value to CC[0] register + pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); + + /// address: 0x4001b140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); + + /// address: 0x4001b200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR: u1, + /// Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR: u1, + /// Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR: u1, + /// Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR: u1, + /// Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR: u1, + /// Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR: u1, + reserved0: u1, + reserved1: u1, + /// Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP: u1, + /// Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP: u1, + /// Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP: u1, + /// Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP: u1, + /// Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP: u1, + /// Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x4001b304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Enable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Enable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x304); + + /// address: 0x4001b308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + /// Write '1' to Disable interrupt for COMPARE[4] event + COMPARE4: u1, + /// Write '1' to Disable interrupt for COMPARE[5] event + COMPARE5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x308); + + /// address: 0x4001b504 + /// Timer mode selection + pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); + + /// address: 0x4001b508 + /// Configure the number of bits used by the TIMER + pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); + + /// address: 0x4001b510 + /// Timer prescaler register + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); + + /// address: 0x4001b540 + /// Description collection[0]: Capture/Compare register 0 + pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); + }; + /// Pulse Width Modulation Unit 0 + pub const PWM0 = struct { + pub const base_address = 0x4001c000; + + /// address: 0x4001c004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001c008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x4001c010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x4001c104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4001c108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x4001c110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x4001c118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4001c11c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x4001c200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x4001c300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x4001c304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x4001c308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x4001c500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x4001c504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x4001c508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4001c50c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x4001c510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x4001c514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + + pub const SEQ = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Beginning address in Data RAM of this sequence + PTR: u32, + + /// Description cluster[0]: Amount of values (duty cycles) in this sequence + CNT: MmioInt(32, u15), + + /// Description cluster[0]: Amount of additional PWM periods between samples loaded + /// into compare register + REFRESH: Mmio(32, packed struct{ + /// Amount of additional PWM periods between samples loaded into compare register + /// (load every REFRESH.CNT+1 PWM periods) + CNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), + + /// Description cluster[0]: Time added after the sequence + ENDDELAY: Mmio(32, packed struct{ + /// Time added after the sequence in PWM periods + CNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), + padding0: u32, + padding1: u32, + padding2: u32, + padding3: u32, + }, base_address + 0x520); + + pub const PSEL = struct { + + /// address: 0x4001c000 + /// Description collection[0]: Output pin select for PWM channel 0 + pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + }; + }; + /// Pulse Density Modulation (Digital Microphone) Interface + pub const PDM = struct { + pub const base_address = 0x4001d000; + + /// address: 0x4001d000 + /// Starts continuous PDM transfer + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x4001d004 + /// Stops PDM transfer + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4001d100 + /// PDM transfer has started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x4001d104 + /// PDM transfer has finished + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x4001d108 + /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last + /// sample after a STOP task has been received) to Data RAM + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x4001d300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for STARTED event + STARTED: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x300); + + /// address: 0x4001d304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x4001d308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x4001d500 + /// PDM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x4001d504 + /// PDM clock generator control + pub const PDMCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// PDM_CLK frequency + FREQ: u32, + }), base_address + 0x504); + + /// address: 0x4001d508 + /// Defines the routing of the connected PDM microphones' signals + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Mono or stereo operation + OPERATION: u1, + /// Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x508); + + /// address: 0x4001d518 + /// Left output gain adjustment + pub const GAINL = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x518); + + /// address: 0x4001d51c + /// Right output gain adjustment + pub const GAINR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + pub const PSEL = struct { + + /// address: 0x4001d000 + /// Pin number configuration for PDM CLK signal + pub const CLK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x4001d004 + /// Pin number configuration for PDM DIN signal + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + }; + + pub const SAMPLE = struct { + + /// address: 0x4001d000 + /// RAM address pointer to write samples to with EasyDMA + pub const PTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address to write PDM samples to over DMA + SAMPLEPTR: u32, + }), base_address + 0x0); + + /// address: 0x4001d004 + /// Number of samples to allocate memory for in EasyDMA mode + pub const MAXCNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Length of DMA RAM allocation in number of samples + BUFFSIZE: u15, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + }; + }; + /// Non Volatile Memory Controller + pub const NVMC = struct { + pub const base_address = 0x4001e000; + + /// address: 0x4001e400 + /// Ready flag + pub const READY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); + + /// address: 0x4001e504 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Program memory access mode. It is strongly recommended to only activate erase + /// and write modes when they are actively used. Enabling write or erase will + /// invalidate the cache and keep it invalidated. + WEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x504); + + /// address: 0x4001e508 + /// Register for erasing a page in Code area + pub const ERASEPAGE = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4001e508 + /// Deprecated register - Register for erasing a page in Code area. Equivalent to + /// ERASEPAGE. + pub const ERASEPCR1 = @intToPtr(*volatile u32, base_address + 0x508); + + /// address: 0x4001e50c + /// Register for erasing all non-volatile user memory + pub const ERASEALL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); + + /// address: 0x4001e510 + /// Deprecated register - Register for erasing a page in Code area. Equivalent to + /// ERASEPAGE. + pub const ERASEPCR0 = @intToPtr(*volatile u32, base_address + 0x510); + + /// address: 0x4001e514 + /// Register for erasing User Information Configuration Registers + pub const ERASEUICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x514); + + /// address: 0x4001e540 + /// I-Code cache configuration register. + pub const ICACHECNF = @intToPtr(*volatile Mmio(32, packed struct{ + /// Cache enable + CACHEEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Cache profiling enable + CACHEPROFEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x540); + + /// address: 0x4001e548 + /// I-Code cache hit counter. + pub const IHIT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of cache hits + HITS: u32, + }), base_address + 0x548); + + /// address: 0x4001e54c + /// I-Code cache miss counter. + pub const IMISS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of cache misses + MISSES: u32, + }), base_address + 0x54c); + }; + /// Programmable Peripheral Interconnect + pub const PPI = struct { + pub const base_address = 0x4001f000; + + /// address: 0x4001f500 + /// Channel enable register + pub const CHEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable channel 0 + CH0: u1, + /// Enable or disable channel 1 + CH1: u1, + /// Enable or disable channel 2 + CH2: u1, + /// Enable or disable channel 3 + CH3: u1, + /// Enable or disable channel 4 + CH4: u1, + /// Enable or disable channel 5 + CH5: u1, + /// Enable or disable channel 6 + CH6: u1, + /// Enable or disable channel 7 + CH7: u1, + /// Enable or disable channel 8 + CH8: u1, + /// Enable or disable channel 9 + CH9: u1, + /// Enable or disable channel 10 + CH10: u1, + /// Enable or disable channel 11 + CH11: u1, + /// Enable or disable channel 12 + CH12: u1, + /// Enable or disable channel 13 + CH13: u1, + /// Enable or disable channel 14 + CH14: u1, + /// Enable or disable channel 15 + CH15: u1, + /// Enable or disable channel 16 + CH16: u1, + /// Enable or disable channel 17 + CH17: u1, + /// Enable or disable channel 18 + CH18: u1, + /// Enable or disable channel 19 + CH19: u1, + /// Enable or disable channel 20 + CH20: u1, + /// Enable or disable channel 21 + CH21: u1, + /// Enable or disable channel 22 + CH22: u1, + /// Enable or disable channel 23 + CH23: u1, + /// Enable or disable channel 24 + CH24: u1, + /// Enable or disable channel 25 + CH25: u1, + /// Enable or disable channel 26 + CH26: u1, + /// Enable or disable channel 27 + CH27: u1, + /// Enable or disable channel 28 + CH28: u1, + /// Enable or disable channel 29 + CH29: u1, + /// Enable or disable channel 30 + CH30: u1, + /// Enable or disable channel 31 + CH31: u1, + }), base_address + 0x500); + + /// address: 0x4001f504 + /// Channel enable set register + pub const CHENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 enable set register. Writing '0' has no effect + CH0: u1, + /// Channel 1 enable set register. Writing '0' has no effect + CH1: u1, + /// Channel 2 enable set register. Writing '0' has no effect + CH2: u1, + /// Channel 3 enable set register. Writing '0' has no effect + CH3: u1, + /// Channel 4 enable set register. Writing '0' has no effect + CH4: u1, + /// Channel 5 enable set register. Writing '0' has no effect + CH5: u1, + /// Channel 6 enable set register. Writing '0' has no effect + CH6: u1, + /// Channel 7 enable set register. Writing '0' has no effect + CH7: u1, + /// Channel 8 enable set register. Writing '0' has no effect + CH8: u1, + /// Channel 9 enable set register. Writing '0' has no effect + CH9: u1, + /// Channel 10 enable set register. Writing '0' has no effect + CH10: u1, + /// Channel 11 enable set register. Writing '0' has no effect + CH11: u1, + /// Channel 12 enable set register. Writing '0' has no effect + CH12: u1, + /// Channel 13 enable set register. Writing '0' has no effect + CH13: u1, + /// Channel 14 enable set register. Writing '0' has no effect + CH14: u1, + /// Channel 15 enable set register. Writing '0' has no effect + CH15: u1, + /// Channel 16 enable set register. Writing '0' has no effect + CH16: u1, + /// Channel 17 enable set register. Writing '0' has no effect + CH17: u1, + /// Channel 18 enable set register. Writing '0' has no effect + CH18: u1, + /// Channel 19 enable set register. Writing '0' has no effect + CH19: u1, + /// Channel 20 enable set register. Writing '0' has no effect + CH20: u1, + /// Channel 21 enable set register. Writing '0' has no effect + CH21: u1, + /// Channel 22 enable set register. Writing '0' has no effect + CH22: u1, + /// Channel 23 enable set register. Writing '0' has no effect + CH23: u1, + /// Channel 24 enable set register. Writing '0' has no effect + CH24: u1, + /// Channel 25 enable set register. Writing '0' has no effect + CH25: u1, + /// Channel 26 enable set register. Writing '0' has no effect + CH26: u1, + /// Channel 27 enable set register. Writing '0' has no effect + CH27: u1, + /// Channel 28 enable set register. Writing '0' has no effect + CH28: u1, + /// Channel 29 enable set register. Writing '0' has no effect + CH29: u1, + /// Channel 30 enable set register. Writing '0' has no effect + CH30: u1, + /// Channel 31 enable set register. Writing '0' has no effect + CH31: u1, + }), base_address + 0x504); + + /// address: 0x4001f508 + /// Channel enable clear register + pub const CHENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 enable clear register. Writing '0' has no effect + CH0: u1, + /// Channel 1 enable clear register. Writing '0' has no effect + CH1: u1, + /// Channel 2 enable clear register. Writing '0' has no effect + CH2: u1, + /// Channel 3 enable clear register. Writing '0' has no effect + CH3: u1, + /// Channel 4 enable clear register. Writing '0' has no effect + CH4: u1, + /// Channel 5 enable clear register. Writing '0' has no effect + CH5: u1, + /// Channel 6 enable clear register. Writing '0' has no effect + CH6: u1, + /// Channel 7 enable clear register. Writing '0' has no effect + CH7: u1, + /// Channel 8 enable clear register. Writing '0' has no effect + CH8: u1, + /// Channel 9 enable clear register. Writing '0' has no effect + CH9: u1, + /// Channel 10 enable clear register. Writing '0' has no effect + CH10: u1, + /// Channel 11 enable clear register. Writing '0' has no effect + CH11: u1, + /// Channel 12 enable clear register. Writing '0' has no effect + CH12: u1, + /// Channel 13 enable clear register. Writing '0' has no effect + CH13: u1, + /// Channel 14 enable clear register. Writing '0' has no effect + CH14: u1, + /// Channel 15 enable clear register. Writing '0' has no effect + CH15: u1, + /// Channel 16 enable clear register. Writing '0' has no effect + CH16: u1, + /// Channel 17 enable clear register. Writing '0' has no effect + CH17: u1, + /// Channel 18 enable clear register. Writing '0' has no effect + CH18: u1, + /// Channel 19 enable clear register. Writing '0' has no effect + CH19: u1, + /// Channel 20 enable clear register. Writing '0' has no effect + CH20: u1, + /// Channel 21 enable clear register. Writing '0' has no effect + CH21: u1, + /// Channel 22 enable clear register. Writing '0' has no effect + CH22: u1, + /// Channel 23 enable clear register. Writing '0' has no effect + CH23: u1, + /// Channel 24 enable clear register. Writing '0' has no effect + CH24: u1, + /// Channel 25 enable clear register. Writing '0' has no effect + CH25: u1, + /// Channel 26 enable clear register. Writing '0' has no effect + CH26: u1, + /// Channel 27 enable clear register. Writing '0' has no effect + CH27: u1, + /// Channel 28 enable clear register. Writing '0' has no effect + CH28: u1, + /// Channel 29 enable clear register. Writing '0' has no effect + CH29: u1, + /// Channel 30 enable clear register. Writing '0' has no effect + CH30: u1, + /// Channel 31 enable clear register. Writing '0' has no effect + CH31: u1, + }), base_address + 0x508); + + /// address: 0x4001f800 + /// Description collection[0]: Channel group 0 + pub const CHG = @intToPtr(*volatile [6]Mmio(32, packed struct{ + /// Include or exclude channel 0 + CH0: u1, + /// Include or exclude channel 1 + CH1: u1, + /// Include or exclude channel 2 + CH2: u1, + /// Include or exclude channel 3 + CH3: u1, + /// Include or exclude channel 4 + CH4: u1, + /// Include or exclude channel 5 + CH5: u1, + /// Include or exclude channel 6 + CH6: u1, + /// Include or exclude channel 7 + CH7: u1, + /// Include or exclude channel 8 + CH8: u1, + /// Include or exclude channel 9 + CH9: u1, + /// Include or exclude channel 10 + CH10: u1, + /// Include or exclude channel 11 + CH11: u1, + /// Include or exclude channel 12 + CH12: u1, + /// Include or exclude channel 13 + CH13: u1, + /// Include or exclude channel 14 + CH14: u1, + /// Include or exclude channel 15 + CH15: u1, + /// Include or exclude channel 16 + CH16: u1, + /// Include or exclude channel 17 + CH17: u1, + /// Include or exclude channel 18 + CH18: u1, + /// Include or exclude channel 19 + CH19: u1, + /// Include or exclude channel 20 + CH20: u1, + /// Include or exclude channel 21 + CH21: u1, + /// Include or exclude channel 22 + CH22: u1, + /// Include or exclude channel 23 + CH23: u1, + /// Include or exclude channel 24 + CH24: u1, + /// Include or exclude channel 25 + CH25: u1, + /// Include or exclude channel 26 + CH26: u1, + /// Include or exclude channel 27 + CH27: u1, + /// Include or exclude channel 28 + CH28: u1, + /// Include or exclude channel 29 + CH29: u1, + /// Include or exclude channel 30 + CH30: u1, + /// Include or exclude channel 31 + CH31: u1, + }), base_address + 0x800); + + /// Channel group tasks + pub const TASKS_CHG = @ptrCast(*volatile [6]packed struct { + /// Description cluster[0]: Enable channel group 0 + EN: u32, + + /// Description cluster[0]: Disable channel group 0 + DIS: u32, + }, base_address + 0x0); + + /// PPI Channel + pub const CH = @ptrCast(*volatile [20]packed struct { + /// Description cluster[0]: Channel 0 event end-point + EEP: u32, + + /// Description cluster[0]: Channel 0 task end-point + TEP: u32, + }, base_address + 0x510); + + /// Fork + pub const FORK = @ptrCast(*volatile [32]packed struct { + /// Description cluster[0]: Channel 0 task end-point + TEP: u32, + }, base_address + 0x910); + }; + /// Memory Watch Unit + pub const MWU = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Enable or disable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Enable or disable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Enable or disable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Enable or disable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Enable or disable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Enable or disable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Enable or disable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Enable or disable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Enable or disable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Enable or disable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x300); + + /// address: 0x40020304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x304); + + /// address: 0x40020308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x308); + + /// address: 0x40020320 + /// Enable or disable non-maskable interrupt + pub const NMIEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x320); + + /// address: 0x40020324 + /// Enable non-maskable interrupt + pub const NMIENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x324); + + /// address: 0x40020328 + /// Disable non-maskable interrupt + pub const NMIENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA: u1, + /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA: u1, + /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x328); + + /// address: 0x40020510 + /// Enable/disable regions watch + pub const REGIONEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable/disable write access watch in region[0] + RGN0WA: u1, + /// Enable/disable read access watch in region[0] + RGN0RA: u1, + /// Enable/disable write access watch in region[1] + RGN1WA: u1, + /// Enable/disable read access watch in region[1] + RGN1RA: u1, + /// Enable/disable write access watch in region[2] + RGN2WA: u1, + /// Enable/disable read access watch in region[2] + RGN2RA: u1, + /// Enable/disable write access watch in region[3] + RGN3WA: u1, + /// Enable/disable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable/disable write access watch in PREGION[0] + PRGN0WA: u1, + /// Enable/disable read access watch in PREGION[0] + PRGN0RA: u1, + /// Enable/disable write access watch in PREGION[1] + PRGN1WA: u1, + /// Enable/disable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x510); + + /// address: 0x40020514 + /// Enable regions watch + pub const REGIONENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable write access watch in region[0] + RGN0WA: u1, + /// Enable read access watch in region[0] + RGN0RA: u1, + /// Enable write access watch in region[1] + RGN1WA: u1, + /// Enable read access watch in region[1] + RGN1RA: u1, + /// Enable write access watch in region[2] + RGN2WA: u1, + /// Enable read access watch in region[2] + RGN2RA: u1, + /// Enable write access watch in region[3] + RGN3WA: u1, + /// Enable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Enable write access watch in PREGION[0] + PRGN0WA: u1, + /// Enable read access watch in PREGION[0] + PRGN0RA: u1, + /// Enable write access watch in PREGION[1] + PRGN1WA: u1, + /// Enable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x514); + + /// address: 0x40020518 + /// Disable regions watch + pub const REGIONENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Disable write access watch in region[0] + RGN0WA: u1, + /// Disable read access watch in region[0] + RGN0RA: u1, + /// Disable write access watch in region[1] + RGN1WA: u1, + /// Disable read access watch in region[1] + RGN1RA: u1, + /// Disable write access watch in region[2] + RGN2WA: u1, + /// Disable read access watch in region[2] + RGN2RA: u1, + /// Disable write access watch in region[3] + RGN3WA: u1, + /// Disable read access watch in region[3] + RGN3RA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Disable write access watch in PREGION[0] + PRGN0WA: u1, + /// Disable read access watch in PREGION[0] + PRGN0RA: u1, + /// Disable write access watch in PREGION[1] + PRGN1WA: u1, + /// Disable read access watch in PREGION[1] + PRGN1RA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x518); + + pub const EVENTS_REGION = @ptrCast(*volatile [4]packed struct { + /// Description cluster[0]: Write access to region 0 detected + WA: u32, + + /// Description cluster[0]: Read access to region 0 detected + RA: u32, + }, base_address + 0x100); + + pub const EVENTS_PREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Write access to peripheral region 0 detected + WA: u32, + + /// Description cluster[0]: Read access to peripheral region 0 detected + RA: u32, + }, base_address + 0x160); + + pub const PERREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Source of event/interrupt in region 0, write access + /// detected while corresponding subregion was enabled for watching + SUBSTATWA: Mmio(32, packed struct{ + /// Subregion 0 in region 0 (write '1' to clear) + SR0: u1, + /// Subregion 1 in region 0 (write '1' to clear) + SR1: u1, + /// Subregion 2 in region 0 (write '1' to clear) + SR2: u1, + /// Subregion 3 in region 0 (write '1' to clear) + SR3: u1, + /// Subregion 4 in region 0 (write '1' to clear) + SR4: u1, + /// Subregion 5 in region 0 (write '1' to clear) + SR5: u1, + /// Subregion 6 in region 0 (write '1' to clear) + SR6: u1, + /// Subregion 7 in region 0 (write '1' to clear) + SR7: u1, + /// Subregion 8 in region 0 (write '1' to clear) + SR8: u1, + /// Subregion 9 in region 0 (write '1' to clear) + SR9: u1, + /// Subregion 10 in region 0 (write '1' to clear) + SR10: u1, + /// Subregion 11 in region 0 (write '1' to clear) + SR11: u1, + /// Subregion 12 in region 0 (write '1' to clear) + SR12: u1, + /// Subregion 13 in region 0 (write '1' to clear) + SR13: u1, + /// Subregion 14 in region 0 (write '1' to clear) + SR14: u1, + /// Subregion 15 in region 0 (write '1' to clear) + SR15: u1, + /// Subregion 16 in region 0 (write '1' to clear) + SR16: u1, + /// Subregion 17 in region 0 (write '1' to clear) + SR17: u1, + /// Subregion 18 in region 0 (write '1' to clear) + SR18: u1, + /// Subregion 19 in region 0 (write '1' to clear) + SR19: u1, + /// Subregion 20 in region 0 (write '1' to clear) + SR20: u1, + /// Subregion 21 in region 0 (write '1' to clear) + SR21: u1, + /// Subregion 22 in region 0 (write '1' to clear) + SR22: u1, + /// Subregion 23 in region 0 (write '1' to clear) + SR23: u1, + /// Subregion 24 in region 0 (write '1' to clear) + SR24: u1, + /// Subregion 25 in region 0 (write '1' to clear) + SR25: u1, + /// Subregion 26 in region 0 (write '1' to clear) + SR26: u1, + /// Subregion 27 in region 0 (write '1' to clear) + SR27: u1, + /// Subregion 28 in region 0 (write '1' to clear) + SR28: u1, + /// Subregion 29 in region 0 (write '1' to clear) + SR29: u1, + /// Subregion 30 in region 0 (write '1' to clear) + SR30: u1, + /// Subregion 31 in region 0 (write '1' to clear) + SR31: u1, + }), + + /// Description cluster[0]: Source of event/interrupt in region 0, read access + /// detected while corresponding subregion was enabled for watching + SUBSTATRA: Mmio(32, packed struct{ + /// Subregion 0 in region 0 (write '1' to clear) + SR0: u1, + /// Subregion 1 in region 0 (write '1' to clear) + SR1: u1, + /// Subregion 2 in region 0 (write '1' to clear) + SR2: u1, + /// Subregion 3 in region 0 (write '1' to clear) + SR3: u1, + /// Subregion 4 in region 0 (write '1' to clear) + SR4: u1, + /// Subregion 5 in region 0 (write '1' to clear) + SR5: u1, + /// Subregion 6 in region 0 (write '1' to clear) + SR6: u1, + /// Subregion 7 in region 0 (write '1' to clear) + SR7: u1, + /// Subregion 8 in region 0 (write '1' to clear) + SR8: u1, + /// Subregion 9 in region 0 (write '1' to clear) + SR9: u1, + /// Subregion 10 in region 0 (write '1' to clear) + SR10: u1, + /// Subregion 11 in region 0 (write '1' to clear) + SR11: u1, + /// Subregion 12 in region 0 (write '1' to clear) + SR12: u1, + /// Subregion 13 in region 0 (write '1' to clear) + SR13: u1, + /// Subregion 14 in region 0 (write '1' to clear) + SR14: u1, + /// Subregion 15 in region 0 (write '1' to clear) + SR15: u1, + /// Subregion 16 in region 0 (write '1' to clear) + SR16: u1, + /// Subregion 17 in region 0 (write '1' to clear) + SR17: u1, + /// Subregion 18 in region 0 (write '1' to clear) + SR18: u1, + /// Subregion 19 in region 0 (write '1' to clear) + SR19: u1, + /// Subregion 20 in region 0 (write '1' to clear) + SR20: u1, + /// Subregion 21 in region 0 (write '1' to clear) + SR21: u1, + /// Subregion 22 in region 0 (write '1' to clear) + SR22: u1, + /// Subregion 23 in region 0 (write '1' to clear) + SR23: u1, + /// Subregion 24 in region 0 (write '1' to clear) + SR24: u1, + /// Subregion 25 in region 0 (write '1' to clear) + SR25: u1, + /// Subregion 26 in region 0 (write '1' to clear) + SR26: u1, + /// Subregion 27 in region 0 (write '1' to clear) + SR27: u1, + /// Subregion 28 in region 0 (write '1' to clear) + SR28: u1, + /// Subregion 29 in region 0 (write '1' to clear) + SR29: u1, + /// Subregion 30 in region 0 (write '1' to clear) + SR30: u1, + /// Subregion 31 in region 0 (write '1' to clear) + SR31: u1, + }), + }, base_address + 0x400); + + pub const REGION = @ptrCast(*volatile [4]packed struct { + /// Description cluster[0]: Start address for region 0 + START: u32, + + /// Description cluster[0]: End address of region 0 + END: u32, + padding0: u32, + padding1: u32, + }, base_address + 0x600); + + pub const PREGION = @ptrCast(*volatile [2]packed struct { + /// Description cluster[0]: Reserved for future use + START: u32, + + /// Description cluster[0]: Reserved for future use + END: u32, + + /// Description cluster[0]: Subregions of region 0 + SUBS: Mmio(32, packed struct{ + /// Include or exclude subregion 0 in region + SR0: u1, + /// Include or exclude subregion 1 in region + SR1: u1, + /// Include or exclude subregion 2 in region + SR2: u1, + /// Include or exclude subregion 3 in region + SR3: u1, + /// Include or exclude subregion 4 in region + SR4: u1, + /// Include or exclude subregion 5 in region + SR5: u1, + /// Include or exclude subregion 6 in region + SR6: u1, + /// Include or exclude subregion 7 in region + SR7: u1, + /// Include or exclude subregion 8 in region + SR8: u1, + /// Include or exclude subregion 9 in region + SR9: u1, + /// Include or exclude subregion 10 in region + SR10: u1, + /// Include or exclude subregion 11 in region + SR11: u1, + /// Include or exclude subregion 12 in region + SR12: u1, + /// Include or exclude subregion 13 in region + SR13: u1, + /// Include or exclude subregion 14 in region + SR14: u1, + /// Include or exclude subregion 15 in region + SR15: u1, + /// Include or exclude subregion 16 in region + SR16: u1, + /// Include or exclude subregion 17 in region + SR17: u1, + /// Include or exclude subregion 18 in region + SR18: u1, + /// Include or exclude subregion 19 in region + SR19: u1, + /// Include or exclude subregion 20 in region + SR20: u1, + /// Include or exclude subregion 21 in region + SR21: u1, + /// Include or exclude subregion 22 in region + SR22: u1, + /// Include or exclude subregion 23 in region + SR23: u1, + /// Include or exclude subregion 24 in region + SR24: u1, + /// Include or exclude subregion 25 in region + SR25: u1, + /// Include or exclude subregion 26 in region + SR26: u1, + /// Include or exclude subregion 27 in region + SR27: u1, + /// Include or exclude subregion 28 in region + SR28: u1, + /// Include or exclude subregion 29 in region + SR29: u1, + /// Include or exclude subregion 30 in region + SR30: u1, + /// Include or exclude subregion 31 in region + SR31: u1, + }), + padding0: u32, + }, base_address + 0x6c0); + }; + /// Pulse Width Modulation Unit 1 + pub const PWM1 = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40021008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x40021010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40021104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40021108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x40021110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x40021118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4002111c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40021200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40021300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x40021304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x40021308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x40021500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40021504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x40021508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4002150c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40021510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x40021514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + }; + /// Pulse Width Modulation Unit 2 + pub const PWM2 = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022004 + /// Stops PWM pulse generation on all channels at the end of current PWM period, and + /// stops sequence playback + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40022008 + /// Description collection[0]: Loads the first PWM value on all enabled channels + /// from sequence 0, and starts playing that sequence at the rate defined in + /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not + /// running. + pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); + + /// address: 0x40022010 + /// Steps by one value in the current sequence on all enabled channels if + /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not + /// running. + pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40022104 + /// Response to STOP task, emitted when PWM pulses are no longer generated + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40022108 + /// Description collection[0]: First PWM period started on sequence 0 + pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); + + /// address: 0x40022110 + /// Description collection[0]: Emitted at end of every sequence 0, when last value + /// from RAM has been applied to wave counter + pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); + + /// address: 0x40022118 + /// Emitted at the end of each PWM period + pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x4002211c + /// Concatenated sequences have been played the amount of times defined in LOOP.CNT + pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x40022200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP: u1, + /// Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART0: u1, + /// Shortcut between LOOPSDONE event and SEQSTART[1] task + LOOPSDONE_SEQSTART1: u1, + /// Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x200); + + /// address: 0x40022300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + /// Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Enable or disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Enable or disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Enable or disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Enable or disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x300); + + /// address: 0x40022304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Enable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Enable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Enable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x304); + + /// address: 0x40022308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED0: u1, + /// Write '1' to Disable interrupt for SEQSTARTED[1] event + SEQSTARTED1: u1, + /// Write '1' to Disable interrupt for SEQEND[0] event + SEQEND0: u1, + /// Write '1' to Disable interrupt for SEQEND[1] event + SEQEND1: u1, + /// Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND: u1, + /// Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x308); + + /// address: 0x40022500 + /// PWM module enable register + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); + + /// address: 0x40022504 + /// Selects operating mode of the wave counter + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Selects up or up and down as wave counter mode + UPDOWN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x504); + + /// address: 0x40022508 + /// Value up to which the pulse generator counter counts + pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); + + /// address: 0x4002250c + /// Configuration for PWM_CLK + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); + + /// address: 0x40022510 + /// Configuration of the decoder + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// How a sequence is read from RAM and spread to the compare register + LOAD: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Selects source for advancing the active sequence + MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x510); + + /// address: 0x40022514 + /// Amount of playback of a loop + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + /// Amount of playback of pattern cycles + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x514); + }; + /// Serial Peripheral Interface Master with EasyDMA 2 + pub const SPIM2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023010 + /// Start SPI transaction + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40023014 + /// Stop SPI transaction + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4002301c + /// Suspend SPI transaction + pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40023020 + /// Resume SPI transaction + pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40023104 + /// SPI transaction has stopped + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40023110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40023118 + /// End of RXD buffer and TXD buffer reached + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x40023120 + /// End of TXD buffer reached + pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x4002314c + /// Transaction started + pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x40023200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Shortcut between END event and START task + END_START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x200); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Enable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Enable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved4: u1, + /// Write '1' to Disable interrupt for ENDTX event + ENDTX: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Write '1' to Disable interrupt for STARTED event + STARTED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40023500 + /// Enable SPIM + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023524 + /// SPI frequency. Accuracy depends on the HFCLK source selected. + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x400235c0 + /// Over-read character. Character clocked out in case and over-read of the TXD + /// buffer. + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// SPI Slave 2 + pub const SPIS2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023024 + /// Acquire SPI semaphore + pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40023028 + /// Release SPI semaphore, enabling the SPI slave to acquire it + pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40023104 + /// Granted transaction completed + pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40023110 + /// End of RXD buffer reached + pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x40023128 + /// Semaphore acquired + pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x40023200 + /// Shortcut register + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Shortcut between END event and ACQUIRE task + END_ACQUIRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x200); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for END event + END: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for ENDRX event + ENDRX: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x308); + + /// address: 0x40023400 + /// Semaphore status register + pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); + + /// address: 0x40023440 + /// Status from last transaction + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + /// TX buffer over-read detected, and prevented + OVERREAD: u1, + /// RX buffer overflow detected, and prevented + OVERFLOW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x440); + + /// address: 0x40023500 + /// Enable SPI slave + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + + /// address: 0x4002355c + /// Default character. Character clocked out in case of an ignored transaction. + pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); -/// Event Generator Unit 2 -pub const EGU2 = extern struct { - pub const Address: u32 = 0x40016000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x400235c0 + /// Over-read character + pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); + }; + /// Serial Peripheral Interface 2 + pub const SPI2 = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023108 + /// TXD byte sent and RXD byte received + pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40023304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Enable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x304); + + /// address: 0x40023308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Write '1' to Disable interrupt for READY event + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x308); + + /// address: 0x40023500 + /// Enable SPI + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); + + /// address: 0x40023518 + /// RXD register + pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); -/// Software interrupt 3 -pub const SWI3 = extern struct { - pub const Address: u32 = 0x40017000; + /// address: 0x4002351c + /// TXD register + pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); + + /// address: 0x40023524 + /// SPI frequency + pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); + + /// address: 0x40023554 + /// Configuration register + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bit order + ORDER: u1, + /// Serial clock (SCK) phase + CPHA: u1, + /// Serial clock (SCK) polarity + CPOL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x554); + }; + /// Real time counter 2 + pub const RTC2 = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// Start RTC COUNTER + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40024004 + /// Stop RTC COUNTER + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40024008 + /// Clear RTC COUNTER + pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002400c + /// Set COUNTER to 0xFFFFF0 + pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40024100 + /// Event on COUNTER increment + pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x40024104 + /// Event on COUNTER overflow + pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40024140 + /// Description collection[0]: Compare event on CC[0] match + pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); + + /// address: 0x40024304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable interrupt for TICK event + TICK: u1, + /// Write '1' to Enable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x304); + + /// address: 0x40024308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable interrupt for TICK event + TICK: u1, + /// Write '1' to Disable interrupt for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable interrupt for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable interrupt for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable interrupt for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable interrupt for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x308); + + /// address: 0x40024340 + /// Enable or disable event routing + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enable or disable event routing for TICK event + TICK: u1, + /// Enable or disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Enable or disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Enable or disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Enable or disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Enable or disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x340); + + /// address: 0x40024344 + /// Enable event routing + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Enable event routing for TICK event + TICK: u1, + /// Write '1' to Enable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Enable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Enable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Enable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Enable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x344); + + /// address: 0x40024348 + /// Disable event routing + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write '1' to Disable event routing for TICK event + TICK: u1, + /// Write '1' to Disable event routing for OVRFLW event + OVRFLW: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Write '1' to Disable event routing for COMPARE[0] event + COMPARE0: u1, + /// Write '1' to Disable event routing for COMPARE[1] event + COMPARE1: u1, + /// Write '1' to Disable event routing for COMPARE[2] event + COMPARE2: u1, + /// Write '1' to Disable event routing for COMPARE[3] event + COMPARE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x348); + + /// address: 0x40024504 + /// Current COUNTER value + pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); + + /// address: 0x40024508 + /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written + /// when RTC is stopped + pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); + + /// address: 0x40024540 + /// Description collection[0]: Compare register 0 + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + /// Compare value + COMPARE: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x540); + }; + /// Inter-IC Sound + pub const I2S = struct { + pub const base_address = 0x40025000; + + /// address: 0x40025000 + /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40025004 + /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause + /// the {event:STOPPED} event to be generated. + pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40025104 + /// The RXD.PTR register has been copied to internal double-buffers. When the I2S + /// module is started and RX is enabled, this event will be generated for every + /// RXTXD.MAXCNT words that are received on the SDIN pin. + pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x40025108 + /// I2S transfer stopped. + pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x40025114 + /// The TDX.PTR register has been copied to internal double-buffers. When the I2S + /// module is started and TX is enabled, this event will be generated for every + /// RXTXD.MAXCNT words that are sent on the SDOUT pin. + pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x40025300 + /// Enable or disable interrupt + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Enable or disable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Enable or disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Enable or disable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x300); + + /// address: 0x40025304 + /// Enable interrupt + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Write '1' to Enable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x304); + + /// address: 0x40025308 + /// Disable interrupt + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD: u1, + /// Write '1' to Disable interrupt for STOPPED event + STOPPED: u1, + reserved1: u1, + reserved2: u1, + /// Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x308); + + /// address: 0x40025500 + /// Enable I2S module. + pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + pub const CONFIG = struct { -/// Event Generator Unit 3 -pub const EGU3 = extern struct { - pub const Address: u32 = 0x40017000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40025000 + /// I2S mode. + pub const MODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); -/// Software interrupt 4 -pub const SWI4 = extern struct { - pub const Address: u32 = 0x40018000; + /// address: 0x40025004 + /// Reception (RX) enable. + pub const RXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40025008 + /// Transmission (TX) enable. + pub const TXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); -/// Event Generator Unit 4 -pub const EGU4 = extern struct { - pub const Address: u32 = 0x40018000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x4002500c + /// Master clock generator enable. + pub const MCKEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc); -/// Software interrupt 5 -pub const SWI5 = extern struct { - pub const Address: u32 = 0x40019000; + /// address: 0x40025010 + /// Master clock generator frequency. + pub const MCKFREQ = @intToPtr(*volatile u32, base_address + 0x10); - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + /// address: 0x40025014 + /// MCK / LRCK ratio. + pub const RATIO = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x14); -/// Event Generator Unit 5 -pub const EGU5 = extern struct { - pub const Address: u32 = 0x40019000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1 = 0, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, Address + 0x00000000); - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, Address + 0x00000100); -}; + /// address: 0x40025018 + /// Sample width. + pub const SWIDTH = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x18); -/// Timer/Counter 3 -pub const TIMER3 = extern struct { - pub const Address: u32 = 0x4001a000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + /// address: 0x4002501c + /// Alignment of sample within a frame. + pub const ALIGN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c); -/// Timer/Counter 4 -pub const TIMER4 = extern struct { - pub const Address: u32 = 0x4001b000; - - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1 = 0, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1 = 0, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1 = 0, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1 = 0, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1 = 0, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1 = 0, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1 = 0, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1 = 0, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1 = 0, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1 = 0, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer mode selection - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Timer mode - MODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configure the number of bits used by the TIMER - pub const BITMODE = mmio(Address + 0x00000508, 32, packed struct { - /// Timer bit width - BITMODE: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timer prescaler register - pub const PRESCALER = mmio(Address + 0x00000510, 32, packed struct { - /// Prescaler value - PRESCALER: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, Address + 0x00000040); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, Address + 0x00000140); - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, Address + 0x00000540); -}; + /// address: 0x40025020 + /// Frame format. + pub const FORMAT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20); -/// Pulse Width Modulation Unit 0 -pub const PWM0 = extern struct { - pub const Address: u32 = 0x4001c000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); - - pub const PSEL = struct { - /// Description collection[0]: Output pin select for PWM channel 0 - pub const OUT = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }), Address + 0x00000000); + /// address: 0x40025024 + /// Enable channels. + pub const CHANNELS = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x24); + }; + + pub const RXD = struct { + + /// address: 0x40025000 + /// Receive buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + }; + + pub const TXD = struct { + + /// address: 0x40025000 + /// Transmit buffer RAM start address. + pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); + }; + + pub const RXTXD = struct { + + /// address: 0x40025000 + /// Size of RXD and TXD buffers. + pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x0); + }; + + pub const PSEL = struct { + + /// address: 0x40025000 + /// Pin select for MCK signal. + pub const MCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x0); + + /// address: 0x40025004 + /// Pin select for SCK signal. + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x4); + + /// address: 0x40025008 + /// Pin select for LRCK signal. + pub const LRCK = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x8); + + /// address: 0x4002500c + /// Pin select for SDIN signal. + pub const SDIN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0xc); + + /// address: 0x40025010 + /// Pin select for SDOUT signal. + pub const SDOUT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin number + PIN: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Connection + CONNECT: u1, + }), base_address + 0x10); + }; }; -}; + /// FPU + pub const FPU = struct { + pub const base_address = 0x40026000; -/// Pulse Density Modulation (Digital Microphone) Interface -pub const PDM = extern struct { - pub const Address: u32 = 0x4001d000; - - /// Starts continuous PDM transfer - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stops PDM transfer - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// PDM transfer has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x00000100); - - /// PDM transfer has finished - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last - /// sample after a STOP task has been received) to Data RAM - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PDM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PDM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PDM clock generator control - pub const PDMCLKCTRL = mmio(Address + 0x00000504, 32, packed struct { - /// PDM_CLK frequency - FREQ: u32 = 0, - }); - - /// Defines the routing of the connected PDM microphones' signals - pub const MODE = mmio(Address + 0x00000508, 32, packed struct { - /// Mono or stereo operation - OPERATION: u1 = 0, - /// Defines on which PDM_CLK edge Left (or mono) is sampled - EDGE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Left output gain adjustment - pub const GAINL = mmio(Address + 0x00000518, 32, packed struct { - /// Left output gain adjustment, in 0.5 dB steps, around the default module gain - /// (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain - /// adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB - /// gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - GAINL: u7 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Right output gain adjustment - pub const GAINR = mmio(Address + 0x0000051c, 32, packed struct { - /// Right output gain adjustment, in 0.5 dB steps, around the default module - /// gain (see electrical parameters) - GAINR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const PSEL = struct { - - /// Pin number configuration for PDM CLK signal - pub const CLK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin number configuration for PDM DIN signal - pub const DIN = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); + /// address: 0x40026000 + /// Unused. + pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); }; - - pub const SAMPLE = struct { - - /// RAM address pointer to write samples to with EasyDMA - pub const PTR = mmio(Address + 0x00000000, 32, packed struct { - /// Address to write PDM samples to over DMA - SAMPLEPTR: u32 = 0, - }); - - /// Number of samples to allocate memory for in EasyDMA mode - pub const MAXCNT = mmio(Address + 0x00000004, 32, packed struct { - /// Length of DMA RAM allocation in number of samples - BUFFSIZE: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// GPIO Port 1 + pub const P0 = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000504 + /// Write GPIO port + pub const OUT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x504); + + /// address: 0x50000508 + /// Set individual bits in GPIO port + pub const OUTSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x508); + + /// address: 0x5000050c + /// Clear individual bits in GPIO port + pub const OUTCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x50c); + + /// address: 0x50000510 + /// Read GPIO port + pub const IN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x510); + + /// address: 0x50000514 + /// Direction of GPIO pins + pub const DIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin 0 + PIN0: u1, + /// Pin 1 + PIN1: u1, + /// Pin 2 + PIN2: u1, + /// Pin 3 + PIN3: u1, + /// Pin 4 + PIN4: u1, + /// Pin 5 + PIN5: u1, + /// Pin 6 + PIN6: u1, + /// Pin 7 + PIN7: u1, + /// Pin 8 + PIN8: u1, + /// Pin 9 + PIN9: u1, + /// Pin 10 + PIN10: u1, + /// Pin 11 + PIN11: u1, + /// Pin 12 + PIN12: u1, + /// Pin 13 + PIN13: u1, + /// Pin 14 + PIN14: u1, + /// Pin 15 + PIN15: u1, + /// Pin 16 + PIN16: u1, + /// Pin 17 + PIN17: u1, + /// Pin 18 + PIN18: u1, + /// Pin 19 + PIN19: u1, + /// Pin 20 + PIN20: u1, + /// Pin 21 + PIN21: u1, + /// Pin 22 + PIN22: u1, + /// Pin 23 + PIN23: u1, + /// Pin 24 + PIN24: u1, + /// Pin 25 + PIN25: u1, + /// Pin 26 + PIN26: u1, + /// Pin 27 + PIN27: u1, + /// Pin 28 + PIN28: u1, + /// Pin 29 + PIN29: u1, + /// Pin 30 + PIN30: u1, + /// Pin 31 + PIN31: u1, + }), base_address + 0x514); + + /// address: 0x50000518 + /// DIR set register + pub const DIRSET = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set as output pin 0 + PIN0: u1, + /// Set as output pin 1 + PIN1: u1, + /// Set as output pin 2 + PIN2: u1, + /// Set as output pin 3 + PIN3: u1, + /// Set as output pin 4 + PIN4: u1, + /// Set as output pin 5 + PIN5: u1, + /// Set as output pin 6 + PIN6: u1, + /// Set as output pin 7 + PIN7: u1, + /// Set as output pin 8 + PIN8: u1, + /// Set as output pin 9 + PIN9: u1, + /// Set as output pin 10 + PIN10: u1, + /// Set as output pin 11 + PIN11: u1, + /// Set as output pin 12 + PIN12: u1, + /// Set as output pin 13 + PIN13: u1, + /// Set as output pin 14 + PIN14: u1, + /// Set as output pin 15 + PIN15: u1, + /// Set as output pin 16 + PIN16: u1, + /// Set as output pin 17 + PIN17: u1, + /// Set as output pin 18 + PIN18: u1, + /// Set as output pin 19 + PIN19: u1, + /// Set as output pin 20 + PIN20: u1, + /// Set as output pin 21 + PIN21: u1, + /// Set as output pin 22 + PIN22: u1, + /// Set as output pin 23 + PIN23: u1, + /// Set as output pin 24 + PIN24: u1, + /// Set as output pin 25 + PIN25: u1, + /// Set as output pin 26 + PIN26: u1, + /// Set as output pin 27 + PIN27: u1, + /// Set as output pin 28 + PIN28: u1, + /// Set as output pin 29 + PIN29: u1, + /// Set as output pin 30 + PIN30: u1, + /// Set as output pin 31 + PIN31: u1, + }), base_address + 0x518); + + /// address: 0x5000051c + /// DIR clear register + pub const DIRCLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set as input pin 0 + PIN0: u1, + /// Set as input pin 1 + PIN1: u1, + /// Set as input pin 2 + PIN2: u1, + /// Set as input pin 3 + PIN3: u1, + /// Set as input pin 4 + PIN4: u1, + /// Set as input pin 5 + PIN5: u1, + /// Set as input pin 6 + PIN6: u1, + /// Set as input pin 7 + PIN7: u1, + /// Set as input pin 8 + PIN8: u1, + /// Set as input pin 9 + PIN9: u1, + /// Set as input pin 10 + PIN10: u1, + /// Set as input pin 11 + PIN11: u1, + /// Set as input pin 12 + PIN12: u1, + /// Set as input pin 13 + PIN13: u1, + /// Set as input pin 14 + PIN14: u1, + /// Set as input pin 15 + PIN15: u1, + /// Set as input pin 16 + PIN16: u1, + /// Set as input pin 17 + PIN17: u1, + /// Set as input pin 18 + PIN18: u1, + /// Set as input pin 19 + PIN19: u1, + /// Set as input pin 20 + PIN20: u1, + /// Set as input pin 21 + PIN21: u1, + /// Set as input pin 22 + PIN22: u1, + /// Set as input pin 23 + PIN23: u1, + /// Set as input pin 24 + PIN24: u1, + /// Set as input pin 25 + PIN25: u1, + /// Set as input pin 26 + PIN26: u1, + /// Set as input pin 27 + PIN27: u1, + /// Set as input pin 28 + PIN28: u1, + /// Set as input pin 29 + PIN29: u1, + /// Set as input pin 30 + PIN30: u1, + /// Set as input pin 31 + PIN31: u1, + }), base_address + 0x51c); + + /// address: 0x50000520 + /// Latch register indicating what GPIO pins that have met the criteria set in the + /// PIN_CNF[n].SENSE registers + pub const LATCH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write + /// '1' to clear. + PIN0: u1, + /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write + /// '1' to clear. + PIN1: u1, + /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write + /// '1' to clear. + PIN2: u1, + /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write + /// '1' to clear. + PIN3: u1, + /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write + /// '1' to clear. + PIN4: u1, + /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write + /// '1' to clear. + PIN5: u1, + /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write + /// '1' to clear. + PIN6: u1, + /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write + /// '1' to clear. + PIN7: u1, + /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write + /// '1' to clear. + PIN8: u1, + /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write + /// '1' to clear. + PIN9: u1, + /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write + /// '1' to clear. + PIN10: u1, + /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write + /// '1' to clear. + PIN11: u1, + /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write + /// '1' to clear. + PIN12: u1, + /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write + /// '1' to clear. + PIN13: u1, + /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write + /// '1' to clear. + PIN14: u1, + /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write + /// '1' to clear. + PIN15: u1, + /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write + /// '1' to clear. + PIN16: u1, + /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write + /// '1' to clear. + PIN17: u1, + /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write + /// '1' to clear. + PIN18: u1, + /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write + /// '1' to clear. + PIN19: u1, + /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write + /// '1' to clear. + PIN20: u1, + /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write + /// '1' to clear. + PIN21: u1, + /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write + /// '1' to clear. + PIN22: u1, + /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write + /// '1' to clear. + PIN23: u1, + /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write + /// '1' to clear. + PIN24: u1, + /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write + /// '1' to clear. + PIN25: u1, + /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write + /// '1' to clear. + PIN26: u1, + /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write + /// '1' to clear. + PIN27: u1, + /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write + /// '1' to clear. + PIN28: u1, + /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write + /// '1' to clear. + PIN29: u1, + /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write + /// '1' to clear. + PIN30: u1, + /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write + /// '1' to clear. + PIN31: u1, + }), base_address + 0x520); + + /// address: 0x50000524 + /// Select between default DETECT signal behaviour and LDETECT mode + pub const DETECTMODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x524); + + /// address: 0x50000700 + /// Description collection[0]: Configuration of GPIO pins + pub const PIN_CNF = @intToPtr(*volatile [32]Mmio(32, packed struct{ + /// Pin direction. Same physical register as DIR register + DIR: u1, + /// Connect or disconnect input buffer + INPUT: u1, + /// Pull configuration + PULL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Drive configuration + DRIVE: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Pin sensing mechanism + SENSE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x700); }; }; -/// Non Volatile Memory Controller -pub const NVMC = extern struct { - pub const Address: u32 = 0x4001e000; - - /// Ready flag - pub const READY = mmio(Address + 0x00000400, 32, packed struct { - /// NVMC is ready or busy - READY: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000504, 32, packed struct { - /// Program memory access mode. It is strongly recommended to only activate - /// erase and write modes when they are actively used. Enabling write or erase - /// will invalidate the cache and keep it invalidated. - WEN: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Register for erasing a page in Code area - pub const ERASEPAGE = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Deprecated register - Register for erasing a page in Code area. Equivalent - /// to ERASEPAGE. - pub const ERASEPCR1 = @intToPtr(*volatile u32, Address + 0x00000508); - - /// Register for erasing all non-volatile user memory - pub const ERASEALL = mmio(Address + 0x0000050c, 32, packed struct { - /// Erase all non-volatile memory including UICR registers. Note that code erase - /// has to be enabled by CONFIG.EEN before the UICR can be erased. - ERASEALL: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Deprecated register - Register for erasing a page in Code area. Equivalent - /// to ERASEPAGE. - pub const ERASEPCR0 = @intToPtr(*volatile u32, Address + 0x00000510); - - /// Register for erasing User Information Configuration Registers - pub const ERASEUICR = mmio(Address + 0x00000514, 32, packed struct { - /// Register starting erase of all User Information Configuration Registers. - /// Note that code erase has to be enabled by CONFIG.EEN before the UICR can be - /// erased. - ERASEUICR: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I-Code cache configuration register. - pub const ICACHECNF = mmio(Address + 0x00000540, 32, packed struct { - /// Cache enable - CACHEEN: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Cache profiling enable - CACHEPROFEN: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I-Code cache hit counter. - pub const IHIT = mmio(Address + 0x00000548, 32, packed struct { - /// Number of cache hits - HITS: u32 = 0, - }); - - /// I-Code cache miss counter. - pub const IMISS = mmio(Address + 0x0000054c, 32, packed struct { - /// Number of cache misses - MISSES: u32 = 0, - }); -}; - -/// Programmable Peripheral Interconnect -pub const PPI = extern struct { - pub const Address: u32 = 0x4001f000; - - /// Channel enable register - pub const CHEN = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable channel 0 - CH0: u1 = 0, - /// Enable or disable channel 1 - CH1: u1 = 0, - /// Enable or disable channel 2 - CH2: u1 = 0, - /// Enable or disable channel 3 - CH3: u1 = 0, - /// Enable or disable channel 4 - CH4: u1 = 0, - /// Enable or disable channel 5 - CH5: u1 = 0, - /// Enable or disable channel 6 - CH6: u1 = 0, - /// Enable or disable channel 7 - CH7: u1 = 0, - /// Enable or disable channel 8 - CH8: u1 = 0, - /// Enable or disable channel 9 - CH9: u1 = 0, - /// Enable or disable channel 10 - CH10: u1 = 0, - /// Enable or disable channel 11 - CH11: u1 = 0, - /// Enable or disable channel 12 - CH12: u1 = 0, - /// Enable or disable channel 13 - CH13: u1 = 0, - /// Enable or disable channel 14 - CH14: u1 = 0, - /// Enable or disable channel 15 - CH15: u1 = 0, - /// Enable or disable channel 16 - CH16: u1 = 0, - /// Enable or disable channel 17 - CH17: u1 = 0, - /// Enable or disable channel 18 - CH18: u1 = 0, - /// Enable or disable channel 19 - CH19: u1 = 0, - /// Enable or disable channel 20 - CH20: u1 = 0, - /// Enable or disable channel 21 - CH21: u1 = 0, - /// Enable or disable channel 22 - CH22: u1 = 0, - /// Enable or disable channel 23 - CH23: u1 = 0, - /// Enable or disable channel 24 - CH24: u1 = 0, - /// Enable or disable channel 25 - CH25: u1 = 0, - /// Enable or disable channel 26 - CH26: u1 = 0, - /// Enable or disable channel 27 - CH27: u1 = 0, - /// Enable or disable channel 28 - CH28: u1 = 0, - /// Enable or disable channel 29 - CH29: u1 = 0, - /// Enable or disable channel 30 - CH30: u1 = 0, - /// Enable or disable channel 31 - CH31: u1 = 0, - }); - - /// Channel enable set register - pub const CHENSET = mmio(Address + 0x00000504, 32, packed struct { - /// Channel 0 enable set register. Writing '0' has no effect - CH0: u1 = 0, - /// Channel 1 enable set register. Writing '0' has no effect - CH1: u1 = 0, - /// Channel 2 enable set register. Writing '0' has no effect - CH2: u1 = 0, - /// Channel 3 enable set register. Writing '0' has no effect - CH3: u1 = 0, - /// Channel 4 enable set register. Writing '0' has no effect - CH4: u1 = 0, - /// Channel 5 enable set register. Writing '0' has no effect - CH5: u1 = 0, - /// Channel 6 enable set register. Writing '0' has no effect - CH6: u1 = 0, - /// Channel 7 enable set register. Writing '0' has no effect - CH7: u1 = 0, - /// Channel 8 enable set register. Writing '0' has no effect - CH8: u1 = 0, - /// Channel 9 enable set register. Writing '0' has no effect - CH9: u1 = 0, - /// Channel 10 enable set register. Writing '0' has no effect - CH10: u1 = 0, - /// Channel 11 enable set register. Writing '0' has no effect - CH11: u1 = 0, - /// Channel 12 enable set register. Writing '0' has no effect - CH12: u1 = 0, - /// Channel 13 enable set register. Writing '0' has no effect - CH13: u1 = 0, - /// Channel 14 enable set register. Writing '0' has no effect - CH14: u1 = 0, - /// Channel 15 enable set register. Writing '0' has no effect - CH15: u1 = 0, - /// Channel 16 enable set register. Writing '0' has no effect - CH16: u1 = 0, - /// Channel 17 enable set register. Writing '0' has no effect - CH17: u1 = 0, - /// Channel 18 enable set register. Writing '0' has no effect - CH18: u1 = 0, - /// Channel 19 enable set register. Writing '0' has no effect - CH19: u1 = 0, - /// Channel 20 enable set register. Writing '0' has no effect - CH20: u1 = 0, - /// Channel 21 enable set register. Writing '0' has no effect - CH21: u1 = 0, - /// Channel 22 enable set register. Writing '0' has no effect - CH22: u1 = 0, - /// Channel 23 enable set register. Writing '0' has no effect - CH23: u1 = 0, - /// Channel 24 enable set register. Writing '0' has no effect - CH24: u1 = 0, - /// Channel 25 enable set register. Writing '0' has no effect - CH25: u1 = 0, - /// Channel 26 enable set register. Writing '0' has no effect - CH26: u1 = 0, - /// Channel 27 enable set register. Writing '0' has no effect - CH27: u1 = 0, - /// Channel 28 enable set register. Writing '0' has no effect - CH28: u1 = 0, - /// Channel 29 enable set register. Writing '0' has no effect - CH29: u1 = 0, - /// Channel 30 enable set register. Writing '0' has no effect - CH30: u1 = 0, - /// Channel 31 enable set register. Writing '0' has no effect - CH31: u1 = 0, - }); - - /// Channel enable clear register - pub const CHENCLR = mmio(Address + 0x00000508, 32, packed struct { - /// Channel 0 enable clear register. Writing '0' has no effect - CH0: u1 = 0, - /// Channel 1 enable clear register. Writing '0' has no effect - CH1: u1 = 0, - /// Channel 2 enable clear register. Writing '0' has no effect - CH2: u1 = 0, - /// Channel 3 enable clear register. Writing '0' has no effect - CH3: u1 = 0, - /// Channel 4 enable clear register. Writing '0' has no effect - CH4: u1 = 0, - /// Channel 5 enable clear register. Writing '0' has no effect - CH5: u1 = 0, - /// Channel 6 enable clear register. Writing '0' has no effect - CH6: u1 = 0, - /// Channel 7 enable clear register. Writing '0' has no effect - CH7: u1 = 0, - /// Channel 8 enable clear register. Writing '0' has no effect - CH8: u1 = 0, - /// Channel 9 enable clear register. Writing '0' has no effect - CH9: u1 = 0, - /// Channel 10 enable clear register. Writing '0' has no effect - CH10: u1 = 0, - /// Channel 11 enable clear register. Writing '0' has no effect - CH11: u1 = 0, - /// Channel 12 enable clear register. Writing '0' has no effect - CH12: u1 = 0, - /// Channel 13 enable clear register. Writing '0' has no effect - CH13: u1 = 0, - /// Channel 14 enable clear register. Writing '0' has no effect - CH14: u1 = 0, - /// Channel 15 enable clear register. Writing '0' has no effect - CH15: u1 = 0, - /// Channel 16 enable clear register. Writing '0' has no effect - CH16: u1 = 0, - /// Channel 17 enable clear register. Writing '0' has no effect - CH17: u1 = 0, - /// Channel 18 enable clear register. Writing '0' has no effect - CH18: u1 = 0, - /// Channel 19 enable clear register. Writing '0' has no effect - CH19: u1 = 0, - /// Channel 20 enable clear register. Writing '0' has no effect - CH20: u1 = 0, - /// Channel 21 enable clear register. Writing '0' has no effect - CH21: u1 = 0, - /// Channel 22 enable clear register. Writing '0' has no effect - CH22: u1 = 0, - /// Channel 23 enable clear register. Writing '0' has no effect - CH23: u1 = 0, - /// Channel 24 enable clear register. Writing '0' has no effect - CH24: u1 = 0, - /// Channel 25 enable clear register. Writing '0' has no effect - CH25: u1 = 0, - /// Channel 26 enable clear register. Writing '0' has no effect - CH26: u1 = 0, - /// Channel 27 enable clear register. Writing '0' has no effect - CH27: u1 = 0, - /// Channel 28 enable clear register. Writing '0' has no effect - CH28: u1 = 0, - /// Channel 29 enable clear register. Writing '0' has no effect - CH29: u1 = 0, - /// Channel 30 enable clear register. Writing '0' has no effect - CH30: u1 = 0, - /// Channel 31 enable clear register. Writing '0' has no effect - CH31: u1 = 0, - }); - /// Description collection[0]: Channel group 0 - pub const CHG = @intToPtr(*volatile [6]MMIO(32, packed struct { - /// Include or exclude channel 0 - CH0: u1 = 0, - /// Include or exclude channel 1 - CH1: u1 = 0, - /// Include or exclude channel 2 - CH2: u1 = 0, - /// Include or exclude channel 3 - CH3: u1 = 0, - /// Include or exclude channel 4 - CH4: u1 = 0, - /// Include or exclude channel 5 - CH5: u1 = 0, - /// Include or exclude channel 6 - CH6: u1 = 0, - /// Include or exclude channel 7 - CH7: u1 = 0, - /// Include or exclude channel 8 - CH8: u1 = 0, - /// Include or exclude channel 9 - CH9: u1 = 0, - /// Include or exclude channel 10 - CH10: u1 = 0, - /// Include or exclude channel 11 - CH11: u1 = 0, - /// Include or exclude channel 12 - CH12: u1 = 0, - /// Include or exclude channel 13 - CH13: u1 = 0, - /// Include or exclude channel 14 - CH14: u1 = 0, - /// Include or exclude channel 15 - CH15: u1 = 0, - /// Include or exclude channel 16 - CH16: u1 = 0, - /// Include or exclude channel 17 - CH17: u1 = 0, - /// Include or exclude channel 18 - CH18: u1 = 0, - /// Include or exclude channel 19 - CH19: u1 = 0, - /// Include or exclude channel 20 - CH20: u1 = 0, - /// Include or exclude channel 21 - CH21: u1 = 0, - /// Include or exclude channel 22 - CH22: u1 = 0, - /// Include or exclude channel 23 - CH23: u1 = 0, - /// Include or exclude channel 24 - CH24: u1 = 0, - /// Include or exclude channel 25 - CH25: u1 = 0, - /// Include or exclude channel 26 - CH26: u1 = 0, - /// Include or exclude channel 27 - CH27: u1 = 0, - /// Include or exclude channel 28 - CH28: u1 = 0, - /// Include or exclude channel 29 - CH29: u1 = 0, - /// Include or exclude channel 30 - CH30: u1 = 0, - /// Include or exclude channel 31 - CH31: u1 = 0, - }), Address + 0x00000800); -}; +const std = @import("std"); -/// Memory Watch Unit -pub const MWU = extern struct { - pub const Address: u32 = 0x40020000; - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - /// Enable or disable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Enable or disable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Enable or disable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Enable or disable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Enable or disable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Enable or disable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Enable or disable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Enable or disable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Enable or disable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Enable or disable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Enable or disable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Enable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Enable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Disable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Disable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable non-maskable interrupt - pub const NMIEN = mmio(Address + 0x00000320, 32, packed struct { - /// Enable or disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Enable or disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Enable or disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable non-maskable interrupt - pub const NMIENSET = mmio(Address + 0x00000324, 32, packed struct { - /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable non-maskable interrupt - pub const NMIENCLR = mmio(Address + 0x00000328, 32, packed struct { - /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1 = 0, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable/disable regions watch - pub const REGIONEN = mmio(Address + 0x00000510, 32, packed struct { - /// Enable/disable write access watch in region[0] - RGN0WA: u1 = 0, - /// Enable/disable read access watch in region[0] - RGN0RA: u1 = 0, - /// Enable/disable write access watch in region[1] - RGN1WA: u1 = 0, - /// Enable/disable read access watch in region[1] - RGN1RA: u1 = 0, - /// Enable/disable write access watch in region[2] - RGN2WA: u1 = 0, - /// Enable/disable read access watch in region[2] - RGN2RA: u1 = 0, - /// Enable/disable write access watch in region[3] - RGN3WA: u1 = 0, - /// Enable/disable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable/disable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Enable/disable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Enable/disable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Enable/disable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable regions watch - pub const REGIONENSET = mmio(Address + 0x00000514, 32, packed struct { - /// Enable write access watch in region[0] - RGN0WA: u1 = 0, - /// Enable read access watch in region[0] - RGN0RA: u1 = 0, - /// Enable write access watch in region[1] - RGN1WA: u1 = 0, - /// Enable read access watch in region[1] - RGN1RA: u1 = 0, - /// Enable write access watch in region[2] - RGN2WA: u1 = 0, - /// Enable read access watch in region[2] - RGN2RA: u1 = 0, - /// Enable write access watch in region[3] - RGN3WA: u1 = 0, - /// Enable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Enable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Enable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Enable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable regions watch - pub const REGIONENCLR = mmio(Address + 0x00000518, 32, packed struct { - /// Disable write access watch in region[0] - RGN0WA: u1 = 0, - /// Disable read access watch in region[0] - RGN0RA: u1 = 0, - /// Disable write access watch in region[1] - RGN1WA: u1 = 0, - /// Disable read access watch in region[1] - RGN1RA: u1 = 0, - /// Disable write access watch in region[2] - RGN2WA: u1 = 0, - /// Disable read access watch in region[2] - RGN2RA: u1 = 0, - /// Disable write access watch in region[3] - RGN3WA: u1 = 0, - /// Disable read access watch in region[3] - RGN3RA: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Disable write access watch in PREGION[0] - PRGN0WA: u1 = 0, - /// Disable read access watch in PREGION[0] - PRGN0RA: u1 = 0, - /// Disable write access watch in PREGION[1] - PRGN1WA: u1 = 0, - /// Disable read access watch in PREGION[1] - PRGN1RA: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} -/// Pulse Width Modulation Unit 1 -pub const PWM1 = extern struct { - pub const Address: u32 = 0x40021000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); -}; +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); -/// Pulse Width Modulation Unit 2 -pub const PWM2 = extern struct { - pub const Address: u32 = 0x40022000; - - /// Stops PWM pulse generation on all channels at the end of current PWM period, - /// and stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, Address + 0x00000118); - - /// Concatenated sequences have been played the amount of times defined in - /// LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, Address + 0x0000011c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1 = 0, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1 = 0, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1 = 0, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1 = 0, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1 = 0, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1 = 0, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1 = 0, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PWM module enable register - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable PWM module - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Selects operating mode of the wave counter - pub const MODE = mmio(Address + 0x00000504, 32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = mmio(Address + 0x00000508, 32, packed struct { - /// Value up to which the pulse generator counter counts. This register is - /// ignored when DECODER.MODE=WaveForm and only values from RAM will be used. - COUNTERTOP: u15 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration for PWM_CLK - pub const PRESCALER = mmio(Address + 0x0000050c, 32, packed struct { - /// Pre-scaler of PWM_CLK - PRESCALER: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration of the decoder - pub const DECODER = mmio(Address + 0x00000510, 32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Selects source for advancing the active sequence - MODE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Amount of playback of a loop - pub const LOOP = mmio(Address + 0x00000514, 32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, Address + 0x00000008); - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, Address + 0x00000108); - /// Description collection[0]: Emitted at end of every sequence 0, when last - /// value from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, Address + 0x00000110); -}; + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); -/// Serial Peripheral Interface Master with EasyDMA 2 -pub const SPIM2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000010); - - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000014); - - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, Address + 0x0000001c); - - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, Address + 0x00000020); - - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000118); - - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, Address + 0x00000120); - - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, Address + 0x0000014c); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and START task - END_START: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved5: u1 = 0, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPIM - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPIM - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + const IntT = std.meta.Int(.unsigned, size); -/// SPI Slave 2 -pub const SPIS2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, Address + 0x00000024); - - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, Address + 0x00000028); - - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, Address + 0x00000104); - - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, Address + 0x00000110); - - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, Address + 0x00000128); - - /// Shortcut register - pub const SHORTS = mmio(Address + 0x00000200, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for END event - END: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Semaphore status register - pub const SEMSTAT = mmio(Address + 0x00000400, 32, packed struct { - /// Semaphore status - SEMSTAT: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status from last transaction - pub const STATUS = mmio(Address + 0x00000440, 32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1 = 0, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI slave - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI slave - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = mmio(Address + 0x0000055c, 32, packed struct { - /// Default character. Character clocked out in case of an ignored transaction. - DEF: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Over-read character - pub const ORC = mmio(Address + 0x000005c0, 32, packed struct { - /// Over-read character. Character clocked out after an over-read of the - /// transmit buffer. - ORC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); -/// Serial Peripheral Interface 2 -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40023000; - - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, Address + 0x00000108); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for READY event - READY: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable SPI - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable or disable SPI - ENABLE: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RXD register - pub const RXD = mmio(Address + 0x00000518, 32, packed struct { - /// RX data received. Double buffered - RXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TXD register - pub const TXD = mmio(Address + 0x0000051c, 32, packed struct { - /// TX data to send. Double buffered - TXD: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, Address + 0x00000524); - - /// Configuration register - pub const CONFIG = mmio(Address + 0x00000554, 32, packed struct { - /// Bit order - ORDER: u1 = 0, - /// Serial clock (SCK) phase - CPHA: u1 = 0, - /// Serial clock (SCK) polarity - CPOL: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + return extern struct { + const Self = @This(); -/// Real time counter 2 -pub const RTC2 = extern struct { - pub const Address: u32 = 0x40024000; - - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, Address + 0x0000000c); - - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, Address + 0x00000100); - - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, Address + 0x00000104); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1 = 0, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable or disable event routing - pub const EVTEN = mmio(Address + 0x00000340, 32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1 = 0, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable event routing - pub const EVTENSET = mmio(Address + 0x00000344, 32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable event routing - pub const EVTENCLR = mmio(Address + 0x00000348, 32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1 = 0, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1 = 0, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Current COUNTER value - pub const COUNTER = mmio(Address + 0x00000504, 32, packed struct { - /// Counter value - COUNTER: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = mmio(Address + 0x00000508, 32, packed struct { - /// Prescaler value - PRESCALER: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, Address + 0x00000140); - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]MMIO(32, packed struct { - /// Compare value - COMPARE: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000540); -}; + raw: IntT, -/// Inter-IC Sound -pub const I2S = extern struct { - pub const Address: u32 = 0x40025000; - - /// Starts continuous I2S transfer. Also starts MCK generator when this is - /// enabled. - pub const TASKS_START = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will - /// cause the {event:STOPPED} event to be generated. - pub const TASKS_STOP = @intToPtr(*volatile u32, Address + 0x00000004); - - /// The RXD.PTR register has been copied to internal double-buffers. When the - /// I2S module is started and RX is enabled, this event will be generated for - /// every RXTXD.MAXCNT words that are received on the SDIN pin. - pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000104); - - /// I2S transfer stopped. - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, Address + 0x00000108); - - /// The TDX.PTR register has been copied to internal double-buffers. When the - /// I2S module is started and TX is enabled, this event will be generated for - /// every RXTXD.MAXCNT words that are sent on the SDOUT pin. - pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, Address + 0x00000114); - - /// Enable or disable interrupt - pub const INTEN = mmio(Address + 0x00000300, 32, packed struct { - reserved1: u1 = 0, - /// Enable or disable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Enable or disable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable interrupt - pub const INTENSET = mmio(Address + 0x00000304, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Enable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Enable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Disable interrupt - pub const INTENCLR = mmio(Address + 0x00000308, 32, packed struct { - reserved1: u1 = 0, - /// Write '1' to Disable interrupt for RXPTRUPD event - RXPTRUPD: u1 = 0, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Write '1' to Disable interrupt for TXPTRUPD event - TXPTRUPD: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable I2S module. - pub const ENABLE = mmio(Address + 0x00000500, 32, packed struct { - /// Enable I2S module. - ENABLE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - pub const CONFIG = struct { - - /// I2S mode. - pub const MODE = mmio(Address + 0x00000000, 32, packed struct { - /// I2S mode. - MODE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reception (RX) enable. - pub const RXEN = mmio(Address + 0x00000004, 32, packed struct { - /// Reception (RX) enable. - RXEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmission (TX) enable. - pub const TXEN = mmio(Address + 0x00000008, 32, packed struct { - /// Transmission (TX) enable. - TXEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Master clock generator enable. - pub const MCKEN = mmio(Address + 0x0000000c, 32, packed struct { - /// Master clock generator enable. - MCKEN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Master clock generator frequency. - pub const MCKFREQ = @intToPtr(*volatile u32, Address + 0x00000010); - - /// MCK / LRCK ratio. - pub const RATIO = mmio(Address + 0x00000014, 32, packed struct { - /// MCK / LRCK ratio. - RATIO: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Sample width. - pub const SWIDTH = mmio(Address + 0x00000018, 32, packed struct { - /// Sample width. - SWIDTH: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Alignment of sample within a frame. - pub const ALIGN = mmio(Address + 0x0000001c, 32, packed struct { - /// Alignment of sample within a frame. - ALIGN: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Frame format. - pub const FORMAT = mmio(Address + 0x00000020, 32, packed struct { - /// Frame format. - FORMAT: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Enable channels. - pub const CHANNELS = mmio(Address + 0x00000024, 32, packed struct { - /// Enable channels. - CHANNELS: u2 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; + pub const underlying_type = PackedT; - pub const RXD = struct { + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } - /// Receive buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); - }; + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } - pub const TXD = struct { + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } - /// Transmit buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, Address + 0x00000000); + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } }; +} - pub const RXTXD = struct { - - /// Size of RXD and TXD buffers. - pub const MAXCNT = mmio(Address + 0x00000000, 32, packed struct { - /// Size of RXD and TXD buffers in number of 32 bit words. - MAXCNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - }; +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); - pub const PSEL = struct { - - /// Pin select for MCK signal. - pub const MCK = mmio(Address + 0x00000000, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SCK signal. - pub const SCK = mmio(Address + 0x00000004, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for LRCK signal. - pub const LRCK = mmio(Address + 0x00000008, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDIN signal. - pub const SDIN = mmio(Address + 0x0000000c, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - - /// Pin select for SDOUT signal. - pub const SDOUT = mmio(Address + 0x00000010, 32, packed struct { - /// Pin number - PIN: u5 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Connection - CONNECT: u1 = 0, - }); - }; -}; + raw: std.meta.Int(.unsigned, size), -/// FPU -pub const FPU = extern struct { - pub const Address: u32 = 0x40026000; + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, Address + 0x00000000); -}; + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); -/// GPIO Port 1 -pub const P0 = extern struct { - pub const Address: u32 = 0x50000000; - - /// Write GPIO port - pub const OUT = mmio(Address + 0x00000504, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Set individual bits in GPIO port - pub const OUTSET = mmio(Address + 0x00000508, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Clear individual bits in GPIO port - pub const OUTCLR = mmio(Address + 0x0000050c, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Read GPIO port - pub const IN = mmio(Address + 0x00000510, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// Direction of GPIO pins - pub const DIR = mmio(Address + 0x00000514, 32, packed struct { - /// Pin 0 - PIN0: u1 = 0, - /// Pin 1 - PIN1: u1 = 0, - /// Pin 2 - PIN2: u1 = 0, - /// Pin 3 - PIN3: u1 = 0, - /// Pin 4 - PIN4: u1 = 0, - /// Pin 5 - PIN5: u1 = 0, - /// Pin 6 - PIN6: u1 = 0, - /// Pin 7 - PIN7: u1 = 0, - /// Pin 8 - PIN8: u1 = 0, - /// Pin 9 - PIN9: u1 = 0, - /// Pin 10 - PIN10: u1 = 0, - /// Pin 11 - PIN11: u1 = 0, - /// Pin 12 - PIN12: u1 = 0, - /// Pin 13 - PIN13: u1 = 0, - /// Pin 14 - PIN14: u1 = 0, - /// Pin 15 - PIN15: u1 = 0, - /// Pin 16 - PIN16: u1 = 0, - /// Pin 17 - PIN17: u1 = 0, - /// Pin 18 - PIN18: u1 = 0, - /// Pin 19 - PIN19: u1 = 0, - /// Pin 20 - PIN20: u1 = 0, - /// Pin 21 - PIN21: u1 = 0, - /// Pin 22 - PIN22: u1 = 0, - /// Pin 23 - PIN23: u1 = 0, - /// Pin 24 - PIN24: u1 = 0, - /// Pin 25 - PIN25: u1 = 0, - /// Pin 26 - PIN26: u1 = 0, - /// Pin 27 - PIN27: u1 = 0, - /// Pin 28 - PIN28: u1 = 0, - /// Pin 29 - PIN29: u1 = 0, - /// Pin 30 - PIN30: u1 = 0, - /// Pin 31 - PIN31: u1 = 0, - }); - - /// DIR set register - pub const DIRSET = mmio(Address + 0x00000518, 32, packed struct { - /// Set as output pin 0 - PIN0: u1 = 0, - /// Set as output pin 1 - PIN1: u1 = 0, - /// Set as output pin 2 - PIN2: u1 = 0, - /// Set as output pin 3 - PIN3: u1 = 0, - /// Set as output pin 4 - PIN4: u1 = 0, - /// Set as output pin 5 - PIN5: u1 = 0, - /// Set as output pin 6 - PIN6: u1 = 0, - /// Set as output pin 7 - PIN7: u1 = 0, - /// Set as output pin 8 - PIN8: u1 = 0, - /// Set as output pin 9 - PIN9: u1 = 0, - /// Set as output pin 10 - PIN10: u1 = 0, - /// Set as output pin 11 - PIN11: u1 = 0, - /// Set as output pin 12 - PIN12: u1 = 0, - /// Set as output pin 13 - PIN13: u1 = 0, - /// Set as output pin 14 - PIN14: u1 = 0, - /// Set as output pin 15 - PIN15: u1 = 0, - /// Set as output pin 16 - PIN16: u1 = 0, - /// Set as output pin 17 - PIN17: u1 = 0, - /// Set as output pin 18 - PIN18: u1 = 0, - /// Set as output pin 19 - PIN19: u1 = 0, - /// Set as output pin 20 - PIN20: u1 = 0, - /// Set as output pin 21 - PIN21: u1 = 0, - /// Set as output pin 22 - PIN22: u1 = 0, - /// Set as output pin 23 - PIN23: u1 = 0, - /// Set as output pin 24 - PIN24: u1 = 0, - /// Set as output pin 25 - PIN25: u1 = 0, - /// Set as output pin 26 - PIN26: u1 = 0, - /// Set as output pin 27 - PIN27: u1 = 0, - /// Set as output pin 28 - PIN28: u1 = 0, - /// Set as output pin 29 - PIN29: u1 = 0, - /// Set as output pin 30 - PIN30: u1 = 0, - /// Set as output pin 31 - PIN31: u1 = 0, - }); - - /// DIR clear register - pub const DIRCLR = mmio(Address + 0x0000051c, 32, packed struct { - /// Set as input pin 0 - PIN0: u1 = 0, - /// Set as input pin 1 - PIN1: u1 = 0, - /// Set as input pin 2 - PIN2: u1 = 0, - /// Set as input pin 3 - PIN3: u1 = 0, - /// Set as input pin 4 - PIN4: u1 = 0, - /// Set as input pin 5 - PIN5: u1 = 0, - /// Set as input pin 6 - PIN6: u1 = 0, - /// Set as input pin 7 - PIN7: u1 = 0, - /// Set as input pin 8 - PIN8: u1 = 0, - /// Set as input pin 9 - PIN9: u1 = 0, - /// Set as input pin 10 - PIN10: u1 = 0, - /// Set as input pin 11 - PIN11: u1 = 0, - /// Set as input pin 12 - PIN12: u1 = 0, - /// Set as input pin 13 - PIN13: u1 = 0, - /// Set as input pin 14 - PIN14: u1 = 0, - /// Set as input pin 15 - PIN15: u1 = 0, - /// Set as input pin 16 - PIN16: u1 = 0, - /// Set as input pin 17 - PIN17: u1 = 0, - /// Set as input pin 18 - PIN18: u1 = 0, - /// Set as input pin 19 - PIN19: u1 = 0, - /// Set as input pin 20 - PIN20: u1 = 0, - /// Set as input pin 21 - PIN21: u1 = 0, - /// Set as input pin 22 - PIN22: u1 = 0, - /// Set as input pin 23 - PIN23: u1 = 0, - /// Set as input pin 24 - PIN24: u1 = 0, - /// Set as input pin 25 - PIN25: u1 = 0, - /// Set as input pin 26 - PIN26: u1 = 0, - /// Set as input pin 27 - PIN27: u1 = 0, - /// Set as input pin 28 - PIN28: u1 = 0, - /// Set as input pin 29 - PIN29: u1 = 0, - /// Set as input pin 30 - PIN30: u1 = 0, - /// Set as input pin 31 - PIN31: u1 = 0, - }); - - /// Latch register indicating what GPIO pins that have met the criteria set in - /// the PIN_CNF[n].SENSE registers - pub const LATCH = mmio(Address + 0x00000520, 32, packed struct { - /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. - /// Write '1' to clear. - PIN0: u1 = 0, - /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. - /// Write '1' to clear. - PIN1: u1 = 0, - /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. - /// Write '1' to clear. - PIN2: u1 = 0, - /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. - /// Write '1' to clear. - PIN3: u1 = 0, - /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. - /// Write '1' to clear. - PIN4: u1 = 0, - /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. - /// Write '1' to clear. - PIN5: u1 = 0, - /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. - /// Write '1' to clear. - PIN6: u1 = 0, - /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. - /// Write '1' to clear. - PIN7: u1 = 0, - /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. - /// Write '1' to clear. - PIN8: u1 = 0, - /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. - /// Write '1' to clear. - PIN9: u1 = 0, - /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. - /// Write '1' to clear. - PIN10: u1 = 0, - /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. - /// Write '1' to clear. - PIN11: u1 = 0, - /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. - /// Write '1' to clear. - PIN12: u1 = 0, - /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. - /// Write '1' to clear. - PIN13: u1 = 0, - /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. - /// Write '1' to clear. - PIN14: u1 = 0, - /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. - /// Write '1' to clear. - PIN15: u1 = 0, - /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. - /// Write '1' to clear. - PIN16: u1 = 0, - /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. - /// Write '1' to clear. - PIN17: u1 = 0, - /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. - /// Write '1' to clear. - PIN18: u1 = 0, - /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. - /// Write '1' to clear. - PIN19: u1 = 0, - /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. - /// Write '1' to clear. - PIN20: u1 = 0, - /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. - /// Write '1' to clear. - PIN21: u1 = 0, - /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. - /// Write '1' to clear. - PIN22: u1 = 0, - /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. - /// Write '1' to clear. - PIN23: u1 = 0, - /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. - /// Write '1' to clear. - PIN24: u1 = 0, - /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. - /// Write '1' to clear. - PIN25: u1 = 0, - /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. - /// Write '1' to clear. - PIN26: u1 = 0, - /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. - /// Write '1' to clear. - PIN27: u1 = 0, - /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. - /// Write '1' to clear. - PIN28: u1 = 0, - /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. - /// Write '1' to clear. - PIN29: u1 = 0, - /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. - /// Write '1' to clear. - PIN30: u1 = 0, - /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. - /// Write '1' to clear. - PIN31: u1 = 0, - }); - - /// Select between default DETECT signal behaviour and LDETECT mode - pub const DETECTMODE = mmio(Address + 0x00000524, 32, packed struct { - /// Select between default DETECT signal behaviour and LDETECT mode - DETECTMODE: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - /// Description collection[0]: Configuration of GPIO pins - pub const PIN_CNF = @intToPtr(*volatile [32]MMIO(32, packed struct { - /// Pin direction. Same physical register as DIR register - DIR: u1 = 0, - /// Connect or disconnect input buffer - INPUT: u1 = 0, - /// Pull configuration - PULL: u2 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Drive configuration - DRIVE: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Pin sensing mechanism - SENSE: u2 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }), Address + 0x00000700); -}; + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm }; -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - POWER_CLOCK: InterruptVector = makeUnhandledHandler("POWER_CLOCK"), - RADIO: InterruptVector = makeUnhandledHandler("RADIO"), - UARTE0_UART0: InterruptVector = makeUnhandledHandler("UARTE0_UART0"), - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = makeUnhandledHandler("SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0"), - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = makeUnhandledHandler("SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1"), - NFCT: InterruptVector = makeUnhandledHandler("NFCT"), - GPIOTE: InterruptVector = makeUnhandledHandler("GPIOTE"), - SAADC: InterruptVector = makeUnhandledHandler("SAADC"), - TIMER0: InterruptVector = makeUnhandledHandler("TIMER0"), - TIMER1: InterruptVector = makeUnhandledHandler("TIMER1"), - TIMER2: InterruptVector = makeUnhandledHandler("TIMER2"), - RTC0: InterruptVector = makeUnhandledHandler("RTC0"), - TEMP: InterruptVector = makeUnhandledHandler("TEMP"), - RNG: InterruptVector = makeUnhandledHandler("RNG"), - ECB: InterruptVector = makeUnhandledHandler("ECB"), - CCM_AAR: InterruptVector = makeUnhandledHandler("CCM_AAR"), - WDT: InterruptVector = makeUnhandledHandler("WDT"), - RTC1: InterruptVector = makeUnhandledHandler("RTC1"), - QDEC: InterruptVector = makeUnhandledHandler("QDEC"), - COMP_LPCOMP: InterruptVector = makeUnhandledHandler("COMP_LPCOMP"), - SWI0_EGU0: InterruptVector = makeUnhandledHandler("SWI0_EGU0"), - SWI1_EGU1: InterruptVector = makeUnhandledHandler("SWI1_EGU1"), - SWI2_EGU2: InterruptVector = makeUnhandledHandler("SWI2_EGU2"), - SWI3_EGU3: InterruptVector = makeUnhandledHandler("SWI3_EGU3"), - SWI4_EGU4: InterruptVector = makeUnhandledHandler("SWI4_EGU4"), - SWI5_EGU5: InterruptVector = makeUnhandledHandler("SWI5_EGU5"), - TIMER3: InterruptVector = makeUnhandledHandler("TIMER3"), - TIMER4: InterruptVector = makeUnhandledHandler("TIMER4"), - PWM0: InterruptVector = makeUnhandledHandler("PWM0"), - PDM: InterruptVector = makeUnhandledHandler("PDM"), - reserved2: u32 = 0, - reserved3: u32 = 0, - MWU: InterruptVector = makeUnhandledHandler("MWU"), - PWM1: InterruptVector = makeUnhandledHandler("PWM1"), - PWM2: InterruptVector = makeUnhandledHandler("PWM2"), - SPIM2_SPIS2_SPI2: InterruptVector = makeUnhandledHandler("SPIM2_SPIS2_SPI2"), - RTC2: InterruptVector = makeUnhandledHandler("RTC2"), - I2S: InterruptVector = makeUnhandledHandler("I2S"), - FPU: InterruptVector = makeUnhandledHandler("FPU"), -}; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); -} - -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index f56973f..6c72470 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -1,22512 +1,23556 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on STM32F103xx version 1.3 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "STM32F103xx"; - -/// Flexible static memory controller -pub const FSMC = extern struct { - pub const Address: u32 = 0xa0000000; - - /// SRAM/NOR-Flash chip-select control register 1 - pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 1 - pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 2 - pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 2 - pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 3 - pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 3 - pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 4 - pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 4 - pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PC Card/NAND Flash control register 2 - pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 2 - pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); - - /// Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct { - /// Attribute memory x setup time - ATTSETx: u8 = 0, - /// Attribute memory x wait time - ATTWAITx: u8 = 0, - /// Attribute memory x hold time - ATTHOLDx: u8 = 0, - /// Attribute memory x databus HiZ time - ATTHIZx: u8 = 0, - }); - - /// ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct { - /// ECC result - ECCx: u32 = 0, - }); - - /// PC Card/NAND Flash control register 3 - pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 3 - pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); - - /// PC Card/NAND Flash control register 4 - pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 4 - pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// SRAM/NOR-Flash write timing registers 1 - pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 2 - pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 3 - pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 4 - pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Power control -pub const PWR = extern struct { - pub const Address: u32 = 0x40007000; - - /// Power control register (PWR_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Low Power Deep Sleep - LPDS: u1 = 0, - /// Power Down Deep Sleep - PDDS: u1 = 0, - /// Clear Wake-up Flag - CWUF: u1 = 0, - /// Clear STANDBY Flag - CSBF: u1 = 0, - /// Power Voltage Detector Enable - PVDE: u1 = 0, - /// PVD Level Selection - PLS: u3 = 0, - /// Disable Backup Domain write protection - DBP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Power control register (PWR_CR) - pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - /// Wake-Up Flag - WUF: u1 = 0, - /// STANDBY Flag - SBF: u1 = 0, - /// PVD Output - PVDO: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable WKUP pin - EWUP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Reset and clock control -pub const RCC = extern struct { - pub const Address: u32 = 0x40021000; - - /// Clock control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Internal High Speed clock enable - HSION: u1 = 0, - /// Internal High Speed clock ready flag - HSIRDY: u1 = 0, - reserved1: u1 = 0, - /// Internal High Speed clock trimming - HSITRIM: u5 = 0, - /// Internal High Speed clock Calibration - HSICAL: u8 = 0, - /// External High Speed clock enable - HSEON: u1 = 0, - /// External High Speed clock ready flag - HSERDY: u1 = 0, - /// External High Speed clock Bypass - HSEBYP: u1 = 0, - /// Clock Security System enable - CSSON: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// PLL enable - PLLON: u1 = 0, - /// PLL clock ready flag - PLLRDY: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register (RCC_CFGR) - pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - /// System clock Switch - SW: u2 = 0, - /// System Clock Switch Status - SWS: u2 = 0, - /// AHB prescaler - HPRE: u4 = 0, - /// APB Low speed prescaler (APB1) - PPRE1: u3 = 0, - /// APB High speed prescaler (APB2) - PPRE2: u3 = 0, - /// ADC prescaler - ADCPRE: u2 = 0, - /// PLL entry clock source - PLLSRC: u1 = 0, - /// HSE divider for PLL entry - PLLXTPRE: u1 = 0, - /// PLL Multiplication Factor - PLLMUL: u4 = 0, - /// USB OTG FS prescaler - OTGFSPRE: u1 = 0, - reserved1: u1 = 0, - /// Microcontroller clock output - MCO: u3 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock interrupt register (RCC_CIR) - pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1 = 0, - /// LSE Ready Interrupt flag - LSERDYF: u1 = 0, - /// HSI Ready Interrupt flag - HSIRDYF: u1 = 0, - /// HSE Ready Interrupt flag - HSERDYF: u1 = 0, - /// PLL Ready Interrupt flag - PLLRDYF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock Security System Interrupt flag - CSSF: u1 = 0, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1 = 0, - /// LSE Ready Interrupt Enable - LSERDYIE: u1 = 0, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1 = 0, - /// HSE Ready Interrupt Enable - HSERDYIE: u1 = 0, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// LSI Ready Interrupt Clear - LSIRDYC: u1 = 0, - /// LSE Ready Interrupt Clear - LSERDYC: u1 = 0, - /// HSI Ready Interrupt Clear - HSIRDYC: u1 = 0, - /// HSE Ready Interrupt Clear - HSERDYC: u1 = 0, - /// PLL Ready Interrupt Clear - PLLRDYC: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Clock security system interrupt clear - CSSC: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral reset register (RCC_APB2RSTR) - pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - /// Alternate function I/O reset - AFIORST: u1 = 0, - reserved1: u1 = 0, - /// IO port A reset - IOPARST: u1 = 0, - /// IO port B reset - IOPBRST: u1 = 0, - /// IO port C reset - IOPCRST: u1 = 0, - /// IO port D reset - IOPDRST: u1 = 0, - /// IO port E reset - IOPERST: u1 = 0, - /// IO port F reset - IOPFRST: u1 = 0, - /// IO port G reset - IOPGRST: u1 = 0, - /// ADC 1 interface reset - ADC1RST: u1 = 0, - /// ADC 2 interface reset - ADC2RST: u1 = 0, - /// TIM1 timer reset - TIM1RST: u1 = 0, - /// SPI 1 reset - SPI1RST: u1 = 0, - /// TIM8 timer reset - TIM8RST: u1 = 0, - /// USART1 reset - USART1RST: u1 = 0, - /// ADC 3 interface reset - ADC3RST: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// TIM9 timer reset - TIM9RST: u1 = 0, - /// TIM10 timer reset - TIM10RST: u1 = 0, - /// TIM11 timer reset - TIM11RST: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral reset register (RCC_APB1RSTR) - pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - /// Timer 2 reset - TIM2RST: u1 = 0, - /// Timer 3 reset - TIM3RST: u1 = 0, - /// Timer 4 reset - TIM4RST: u1 = 0, - /// Timer 5 reset - TIM5RST: u1 = 0, - /// Timer 6 reset - TIM6RST: u1 = 0, - /// Timer 7 reset - TIM7RST: u1 = 0, - /// Timer 12 reset - TIM12RST: u1 = 0, - /// Timer 13 reset - TIM13RST: u1 = 0, - /// Timer 14 reset - TIM14RST: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Window watchdog reset - WWDGRST: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// SPI2 reset - SPI2RST: u1 = 0, - /// SPI3 reset - SPI3RST: u1 = 0, - reserved5: u1 = 0, - /// USART 2 reset - USART2RST: u1 = 0, - /// USART 3 reset - USART3RST: u1 = 0, - /// UART 4 reset - UART4RST: u1 = 0, - /// UART 5 reset - UART5RST: u1 = 0, - /// I2C1 reset - I2C1RST: u1 = 0, - /// I2C2 reset - I2C2RST: u1 = 0, - /// USB reset - USBRST: u1 = 0, - reserved6: u1 = 0, - /// CAN reset - CANRST: u1 = 0, - reserved7: u1 = 0, - /// Backup interface reset - BKPRST: u1 = 0, - /// Power interface reset - PWRRST: u1 = 0, - /// DAC interface reset - DACRST: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AHB Peripheral Clock enable register (RCC_AHBENR) - pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - /// DMA1 clock enable - DMA1EN: u1 = 0, - /// DMA2 clock enable - DMA2EN: u1 = 0, - /// SRAM interface clock enable - SRAMEN: u1 = 0, - reserved1: u1 = 0, - /// FLITF clock enable - FLITFEN: u1 = 0, - reserved2: u1 = 0, - /// CRC clock enable - CRCEN: u1 = 0, - reserved3: u1 = 0, - /// FSMC clock enable - FSMCEN: u1 = 0, - reserved4: u1 = 0, - /// SDIO clock enable - SDIOEN: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral clock enable register (RCC_APB2ENR) - pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - /// Alternate function I/O clock enable - AFIOEN: u1 = 0, - reserved1: u1 = 0, - /// I/O port A clock enable - IOPAEN: u1 = 0, - /// I/O port B clock enable - IOPBEN: u1 = 0, - /// I/O port C clock enable - IOPCEN: u1 = 0, - /// I/O port D clock enable - IOPDEN: u1 = 0, - /// I/O port E clock enable - IOPEEN: u1 = 0, - /// I/O port F clock enable - IOPFEN: u1 = 0, - /// I/O port G clock enable - IOPGEN: u1 = 0, - /// ADC 1 interface clock enable - ADC1EN: u1 = 0, - /// ADC 2 interface clock enable - ADC2EN: u1 = 0, - /// TIM1 Timer clock enable - TIM1EN: u1 = 0, - /// SPI 1 clock enable - SPI1EN: u1 = 0, - /// TIM8 Timer clock enable - TIM8EN: u1 = 0, - /// USART1 clock enable - USART1EN: u1 = 0, - /// ADC3 interface clock enable - ADC3EN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// TIM9 Timer clock enable - TIM9EN: u1 = 0, - /// TIM10 Timer clock enable - TIM10EN: u1 = 0, - /// TIM11 Timer clock enable - TIM11EN: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral clock enable register (RCC_APB1ENR) - pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1 = 0, - /// Timer 3 clock enable - TIM3EN: u1 = 0, - /// Timer 4 clock enable - TIM4EN: u1 = 0, - /// Timer 5 clock enable - TIM5EN: u1 = 0, - /// Timer 6 clock enable - TIM6EN: u1 = 0, - /// Timer 7 clock enable - TIM7EN: u1 = 0, - /// Timer 12 clock enable - TIM12EN: u1 = 0, - /// Timer 13 clock enable - TIM13EN: u1 = 0, - /// Timer 14 clock enable - TIM14EN: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Window watchdog clock enable - WWDGEN: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// SPI 2 clock enable - SPI2EN: u1 = 0, - /// SPI 3 clock enable - SPI3EN: u1 = 0, - reserved5: u1 = 0, - /// USART 2 clock enable - USART2EN: u1 = 0, - /// USART 3 clock enable - USART3EN: u1 = 0, - /// UART 4 clock enable - UART4EN: u1 = 0, - /// UART 5 clock enable - UART5EN: u1 = 0, - /// I2C 1 clock enable - I2C1EN: u1 = 0, - /// I2C 2 clock enable - I2C2EN: u1 = 0, - /// USB clock enable - USBEN: u1 = 0, - reserved6: u1 = 0, - /// CAN clock enable - CANEN: u1 = 0, - reserved7: u1 = 0, - /// Backup interface clock enable - BKPEN: u1 = 0, - /// Power interface clock enable - PWREN: u1 = 0, - /// DAC interface clock enable - DACEN: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup domain control register (RCC_BDCR) - pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - /// External Low Speed oscillator enable - LSEON: u1 = 0, - /// External Low Speed oscillator ready - LSERDY: u1 = 0, - /// External Low Speed oscillator bypass - LSEBYP: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// RTC clock source selection - RTCSEL: u2 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// RTC clock enable - RTCEN: u1 = 0, - /// Backup domain software reset - BDRST: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control/status register (RCC_CSR) - pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Internal low speed oscillator enable - LSION: u1 = 0, - /// Internal low speed oscillator ready - LSIRDY: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Remove reset flag - RMVF: u1 = 0, - reserved23: u1 = 0, - /// PIN reset flag - PINRSTF: u1 = 0, - /// POR/PDR reset flag - PORRSTF: u1 = 0, - /// Software reset flag - SFTRSTF: u1 = 0, - /// Independent watchdog reset flag - IWDGRSTF: u1 = 0, - /// Window watchdog reset flag - WWDGRSTF: u1 = 0, - /// Low-power reset flag - LPWRRSTF: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOA = extern struct { - pub const Address: u32 = 0x40010800; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOB = extern struct { - pub const Address: u32 = 0x40010c00; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOC = extern struct { - pub const Address: u32 = 0x40011000; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOD = extern struct { - pub const Address: u32 = 0x40011400; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOE = extern struct { - pub const Address: u32 = 0x40011800; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOF = extern struct { - pub const Address: u32 = 0x40011c00; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose I/O -pub const GPIOG = extern struct { - pub const Address: u32 = 0x40012000; - - /// Port configuration register low (GPIOn_CRL) - pub const CRL = mmio(Address + 0x00000000, 32, packed struct { - /// Port n.0 mode bits - MODE0: u2 = 0, - /// Port n.0 configuration bits - CNF0: u2 = 0, - /// Port n.1 mode bits - MODE1: u2 = 0, - /// Port n.1 configuration bits - CNF1: u2 = 0, - /// Port n.2 mode bits - MODE2: u2 = 0, - /// Port n.2 configuration bits - CNF2: u2 = 0, - /// Port n.3 mode bits - MODE3: u2 = 0, - /// Port n.3 configuration bits - CNF3: u2 = 0, - /// Port n.4 mode bits - MODE4: u2 = 0, - /// Port n.4 configuration bits - CNF4: u2 = 0, - /// Port n.5 mode bits - MODE5: u2 = 0, - /// Port n.5 configuration bits - CNF5: u2 = 0, - /// Port n.6 mode bits - MODE6: u2 = 0, - /// Port n.6 configuration bits - CNF6: u2 = 0, - /// Port n.7 mode bits - MODE7: u2 = 0, - /// Port n.7 configuration bits - CNF7: u2 = 0, - }); - - /// Port configuration register high (GPIOn_CRL) - pub const CRH = mmio(Address + 0x00000004, 32, packed struct { - /// Port n.8 mode bits - MODE8: u2 = 0, - /// Port n.8 configuration bits - CNF8: u2 = 0, - /// Port n.9 mode bits - MODE9: u2 = 0, - /// Port n.9 configuration bits - CNF9: u2 = 0, - /// Port n.10 mode bits - MODE10: u2 = 0, - /// Port n.10 configuration bits - CNF10: u2 = 0, - /// Port n.11 mode bits - MODE11: u2 = 0, - /// Port n.11 configuration bits - CNF11: u2 = 0, - /// Port n.12 mode bits - MODE12: u2 = 0, - /// Port n.12 configuration bits - CNF12: u2 = 0, - /// Port n.13 mode bits - MODE13: u2 = 0, - /// Port n.13 configuration bits - CNF13: u2 = 0, - /// Port n.14 mode bits - MODE14: u2 = 0, - /// Port n.14 configuration bits - CNF14: u2 = 0, - /// Port n.15 mode bits - MODE15: u2 = 0, - /// Port n.15 configuration bits - CNF15: u2 = 0, - }); - - /// Port input data register (GPIOn_IDR) - pub const IDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port input data - IDR0: u1 = 0, - /// Port input data - IDR1: u1 = 0, - /// Port input data - IDR2: u1 = 0, - /// Port input data - IDR3: u1 = 0, - /// Port input data - IDR4: u1 = 0, - /// Port input data - IDR5: u1 = 0, - /// Port input data - IDR6: u1 = 0, - /// Port input data - IDR7: u1 = 0, - /// Port input data - IDR8: u1 = 0, - /// Port input data - IDR9: u1 = 0, - /// Port input data - IDR10: u1 = 0, - /// Port input data - IDR11: u1 = 0, - /// Port input data - IDR12: u1 = 0, - /// Port input data - IDR13: u1 = 0, - /// Port input data - IDR14: u1 = 0, - /// Port input data - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port output data register (GPIOn_ODR) - pub const ODR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port output data - ODR0: u1 = 0, - /// Port output data - ODR1: u1 = 0, - /// Port output data - ODR2: u1 = 0, - /// Port output data - ODR3: u1 = 0, - /// Port output data - ODR4: u1 = 0, - /// Port output data - ODR5: u1 = 0, - /// Port output data - ODR6: u1 = 0, - /// Port output data - ODR7: u1 = 0, - /// Port output data - ODR8: u1 = 0, - /// Port output data - ODR9: u1 = 0, - /// Port output data - ODR10: u1 = 0, - /// Port output data - ODR11: u1 = 0, - /// Port output data - ODR12: u1 = 0, - /// Port output data - ODR13: u1 = 0, - /// Port output data - ODR14: u1 = 0, - /// Port output data - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port bit set/reset register (GPIOn_BSRR) - pub const BSRR = mmio(Address + 0x00000010, 32, packed struct { - /// Set bit 0 - BS0: u1 = 0, - /// Set bit 1 - BS1: u1 = 0, - /// Set bit 1 - BS2: u1 = 0, - /// Set bit 3 - BS3: u1 = 0, - /// Set bit 4 - BS4: u1 = 0, - /// Set bit 5 - BS5: u1 = 0, - /// Set bit 6 - BS6: u1 = 0, - /// Set bit 7 - BS7: u1 = 0, - /// Set bit 8 - BS8: u1 = 0, - /// Set bit 9 - BS9: u1 = 0, - /// Set bit 10 - BS10: u1 = 0, - /// Set bit 11 - BS11: u1 = 0, - /// Set bit 12 - BS12: u1 = 0, - /// Set bit 13 - BS13: u1 = 0, - /// Set bit 14 - BS14: u1 = 0, - /// Set bit 15 - BS15: u1 = 0, - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 2 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - }); - - /// Port bit reset register (GPIOn_BRR) - pub const BRR = mmio(Address + 0x00000014, 32, packed struct { - /// Reset bit 0 - BR0: u1 = 0, - /// Reset bit 1 - BR1: u1 = 0, - /// Reset bit 1 - BR2: u1 = 0, - /// Reset bit 3 - BR3: u1 = 0, - /// Reset bit 4 - BR4: u1 = 0, - /// Reset bit 5 - BR5: u1 = 0, - /// Reset bit 6 - BR6: u1 = 0, - /// Reset bit 7 - BR7: u1 = 0, - /// Reset bit 8 - BR8: u1 = 0, - /// Reset bit 9 - BR9: u1 = 0, - /// Reset bit 10 - BR10: u1 = 0, - /// Reset bit 11 - BR11: u1 = 0, - /// Reset bit 12 - BR12: u1 = 0, - /// Reset bit 13 - BR13: u1 = 0, - /// Reset bit 14 - BR14: u1 = 0, - /// Reset bit 15 - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Port configuration lock register - pub const LCKR = mmio(Address + 0x00000018, 32, packed struct { - /// Port A Lock bit 0 - LCK0: u1 = 0, - /// Port A Lock bit 1 - LCK1: u1 = 0, - /// Port A Lock bit 2 - LCK2: u1 = 0, - /// Port A Lock bit 3 - LCK3: u1 = 0, - /// Port A Lock bit 4 - LCK4: u1 = 0, - /// Port A Lock bit 5 - LCK5: u1 = 0, - /// Port A Lock bit 6 - LCK6: u1 = 0, - /// Port A Lock bit 7 - LCK7: u1 = 0, - /// Port A Lock bit 8 - LCK8: u1 = 0, - /// Port A Lock bit 9 - LCK9: u1 = 0, - /// Port A Lock bit 10 - LCK10: u1 = 0, - /// Port A Lock bit 11 - LCK11: u1 = 0, - /// Port A Lock bit 12 - LCK12: u1 = 0, - /// Port A Lock bit 13 - LCK13: u1 = 0, - /// Port A Lock bit 14 - LCK14: u1 = 0, - /// Port A Lock bit 15 - LCK15: u1 = 0, - /// Lock key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Alternate function I/O -pub const AFIO = extern struct { - pub const Address: u32 = 0x40010000; - - /// Event Control Register (AFIO_EVCR) - pub const EVCR = mmio(Address + 0x00000000, 32, packed struct { - /// Pin selection - PIN: u4 = 0, - /// Port selection - PORT: u3 = 0, - /// Event Output Enable - EVOE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AF remap and debug I/O configuration register (AFIO_MAPR) - pub const MAPR = mmio(Address + 0x00000004, 32, packed struct { - /// SPI1 remapping - SPI1_REMAP: u1 = 0, - /// I2C1 remapping - I2C1_REMAP: u1 = 0, - /// USART1 remapping - USART1_REMAP: u1 = 0, - /// USART2 remapping - USART2_REMAP: u1 = 0, - /// USART3 remapping - USART3_REMAP: u2 = 0, - /// TIM1 remapping - TIM1_REMAP: u2 = 0, - /// TIM2 remapping - TIM2_REMAP: u2 = 0, - /// TIM3 remapping - TIM3_REMAP: u2 = 0, - /// TIM4 remapping - TIM4_REMAP: u1 = 0, - /// CAN1 remapping - CAN_REMAP: u2 = 0, - /// Port D0/Port D1 mapping on OSCIN/OSCOUT - PD01_REMAP: u1 = 0, - /// Set and cleared by software - TIM5CH4_IREMAP: u1 = 0, - /// ADC 1 External trigger injected conversion remapping - ADC1_ETRGINJ_REMAP: u1 = 0, - /// ADC 1 external trigger regular conversion remapping - ADC1_ETRGREG_REMAP: u1 = 0, - /// ADC 2 external trigger injected conversion remapping - ADC2_ETRGINJ_REMAP: u1 = 0, - /// ADC 2 external trigger regular conversion remapping - ADC2_ETRGREG_REMAP: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Serial wire JTAG configuration - SWJ_CFG: u3 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 1 (AFIO_EXTICR1) - pub const EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - /// EXTI0 configuration - EXTI0: u4 = 0, - /// EXTI1 configuration - EXTI1: u4 = 0, - /// EXTI2 configuration - EXTI2: u4 = 0, - /// EXTI3 configuration - EXTI3: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 2 (AFIO_EXTICR2) - pub const EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// EXTI4 configuration - EXTI4: u4 = 0, - /// EXTI5 configuration - EXTI5: u4 = 0, - /// EXTI6 configuration - EXTI6: u4 = 0, - /// EXTI7 configuration - EXTI7: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 3 (AFIO_EXTICR3) - pub const EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - /// EXTI8 configuration - EXTI8: u4 = 0, - /// EXTI9 configuration - EXTI9: u4 = 0, - /// EXTI10 configuration - EXTI10: u4 = 0, - /// EXTI11 configuration - EXTI11: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// External interrupt configuration register 4 (AFIO_EXTICR4) - pub const EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - /// EXTI12 configuration - EXTI12: u4 = 0, - /// EXTI13 configuration - EXTI13: u4 = 0, - /// EXTI14 configuration - EXTI14: u4 = 0, - /// EXTI15 configuration - EXTI15: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// AF remap and debug I/O configuration register - pub const MAPR2 = mmio(Address + 0x0000001c, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM9 remapping - TIM9_REMAP: u1 = 0, - /// TIM10 remapping - TIM10_REMAP: u1 = 0, - /// TIM11 remapping - TIM11_REMAP: u1 = 0, - /// TIM13 remapping - TIM13_REMAP: u1 = 0, - /// TIM14 remapping - TIM14_REMAP: u1 = 0, - /// NADV connect/disconnect - FSMC_NADV: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// EXTI -pub const EXTI = extern struct { - pub const Address: u32 = 0x40010400; - - /// Interrupt mask register (EXTI_IMR) - pub const IMR = mmio(Address + 0x00000000, 32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1 = 0, - /// Interrupt Mask on line 1 - MR1: u1 = 0, - /// Interrupt Mask on line 2 - MR2: u1 = 0, - /// Interrupt Mask on line 3 - MR3: u1 = 0, - /// Interrupt Mask on line 4 - MR4: u1 = 0, - /// Interrupt Mask on line 5 - MR5: u1 = 0, - /// Interrupt Mask on line 6 - MR6: u1 = 0, - /// Interrupt Mask on line 7 - MR7: u1 = 0, - /// Interrupt Mask on line 8 - MR8: u1 = 0, - /// Interrupt Mask on line 9 - MR9: u1 = 0, - /// Interrupt Mask on line 10 - MR10: u1 = 0, - /// Interrupt Mask on line 11 - MR11: u1 = 0, - /// Interrupt Mask on line 12 - MR12: u1 = 0, - /// Interrupt Mask on line 13 - MR13: u1 = 0, - /// Interrupt Mask on line 14 - MR14: u1 = 0, - /// Interrupt Mask on line 15 - MR15: u1 = 0, - /// Interrupt Mask on line 16 - MR16: u1 = 0, - /// Interrupt Mask on line 17 - MR17: u1 = 0, - /// Interrupt Mask on line 18 - MR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Event mask register (EXTI_EMR) - pub const EMR = mmio(Address + 0x00000004, 32, packed struct { - /// Event Mask on line 0 - MR0: u1 = 0, - /// Event Mask on line 1 - MR1: u1 = 0, - /// Event Mask on line 2 - MR2: u1 = 0, - /// Event Mask on line 3 - MR3: u1 = 0, - /// Event Mask on line 4 - MR4: u1 = 0, - /// Event Mask on line 5 - MR5: u1 = 0, - /// Event Mask on line 6 - MR6: u1 = 0, - /// Event Mask on line 7 - MR7: u1 = 0, - /// Event Mask on line 8 - MR8: u1 = 0, - /// Event Mask on line 9 - MR9: u1 = 0, - /// Event Mask on line 10 - MR10: u1 = 0, - /// Event Mask on line 11 - MR11: u1 = 0, - /// Event Mask on line 12 - MR12: u1 = 0, - /// Event Mask on line 13 - MR13: u1 = 0, - /// Event Mask on line 14 - MR14: u1 = 0, - /// Event Mask on line 15 - MR15: u1 = 0, - /// Event Mask on line 16 - MR16: u1 = 0, - /// Event Mask on line 17 - MR17: u1 = 0, - /// Event Mask on line 18 - MR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Rising Trigger selection register (EXTI_RTSR) - pub const RTSR = mmio(Address + 0x00000008, 32, packed struct { - /// Rising trigger event configuration of line 0 - TR0: u1 = 0, - /// Rising trigger event configuration of line 1 - TR1: u1 = 0, - /// Rising trigger event configuration of line 2 - TR2: u1 = 0, - /// Rising trigger event configuration of line 3 - TR3: u1 = 0, - /// Rising trigger event configuration of line 4 - TR4: u1 = 0, - /// Rising trigger event configuration of line 5 - TR5: u1 = 0, - /// Rising trigger event configuration of line 6 - TR6: u1 = 0, - /// Rising trigger event configuration of line 7 - TR7: u1 = 0, - /// Rising trigger event configuration of line 8 - TR8: u1 = 0, - /// Rising trigger event configuration of line 9 - TR9: u1 = 0, - /// Rising trigger event configuration of line 10 - TR10: u1 = 0, - /// Rising trigger event configuration of line 11 - TR11: u1 = 0, - /// Rising trigger event configuration of line 12 - TR12: u1 = 0, - /// Rising trigger event configuration of line 13 - TR13: u1 = 0, - /// Rising trigger event configuration of line 14 - TR14: u1 = 0, - /// Rising trigger event configuration of line 15 - TR15: u1 = 0, - /// Rising trigger event configuration of line 16 - TR16: u1 = 0, - /// Rising trigger event configuration of line 17 - TR17: u1 = 0, - /// Rising trigger event configuration of line 18 - TR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Falling Trigger selection register (EXTI_FTSR) - pub const FTSR = mmio(Address + 0x0000000c, 32, packed struct { - /// Falling trigger event configuration of line 0 - TR0: u1 = 0, - /// Falling trigger event configuration of line 1 - TR1: u1 = 0, - /// Falling trigger event configuration of line 2 - TR2: u1 = 0, - /// Falling trigger event configuration of line 3 - TR3: u1 = 0, - /// Falling trigger event configuration of line 4 - TR4: u1 = 0, - /// Falling trigger event configuration of line 5 - TR5: u1 = 0, - /// Falling trigger event configuration of line 6 - TR6: u1 = 0, - /// Falling trigger event configuration of line 7 - TR7: u1 = 0, - /// Falling trigger event configuration of line 8 - TR8: u1 = 0, - /// Falling trigger event configuration of line 9 - TR9: u1 = 0, - /// Falling trigger event configuration of line 10 - TR10: u1 = 0, - /// Falling trigger event configuration of line 11 - TR11: u1 = 0, - /// Falling trigger event configuration of line 12 - TR12: u1 = 0, - /// Falling trigger event configuration of line 13 - TR13: u1 = 0, - /// Falling trigger event configuration of line 14 - TR14: u1 = 0, - /// Falling trigger event configuration of line 15 - TR15: u1 = 0, - /// Falling trigger event configuration of line 16 - TR16: u1 = 0, - /// Falling trigger event configuration of line 17 - TR17: u1 = 0, - /// Falling trigger event configuration of line 18 - TR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Software interrupt event register (EXTI_SWIER) - pub const SWIER = mmio(Address + 0x00000010, 32, packed struct { - /// Software Interrupt on line 0 - SWIER0: u1 = 0, - /// Software Interrupt on line 1 - SWIER1: u1 = 0, - /// Software Interrupt on line 2 - SWIER2: u1 = 0, - /// Software Interrupt on line 3 - SWIER3: u1 = 0, - /// Software Interrupt on line 4 - SWIER4: u1 = 0, - /// Software Interrupt on line 5 - SWIER5: u1 = 0, - /// Software Interrupt on line 6 - SWIER6: u1 = 0, - /// Software Interrupt on line 7 - SWIER7: u1 = 0, - /// Software Interrupt on line 8 - SWIER8: u1 = 0, - /// Software Interrupt on line 9 - SWIER9: u1 = 0, - /// Software Interrupt on line 10 - SWIER10: u1 = 0, - /// Software Interrupt on line 11 - SWIER11: u1 = 0, - /// Software Interrupt on line 12 - SWIER12: u1 = 0, - /// Software Interrupt on line 13 - SWIER13: u1 = 0, - /// Software Interrupt on line 14 - SWIER14: u1 = 0, - /// Software Interrupt on line 15 - SWIER15: u1 = 0, - /// Software Interrupt on line 16 - SWIER16: u1 = 0, - /// Software Interrupt on line 17 - SWIER17: u1 = 0, - /// Software Interrupt on line 18 - SWIER18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pending register (EXTI_PR) - pub const PR = mmio(Address + 0x00000014, 32, packed struct { - /// Pending bit 0 - PR0: u1 = 0, - /// Pending bit 1 - PR1: u1 = 0, - /// Pending bit 2 - PR2: u1 = 0, - /// Pending bit 3 - PR3: u1 = 0, - /// Pending bit 4 - PR4: u1 = 0, - /// Pending bit 5 - PR5: u1 = 0, - /// Pending bit 6 - PR6: u1 = 0, - /// Pending bit 7 - PR7: u1 = 0, - /// Pending bit 8 - PR8: u1 = 0, - /// Pending bit 9 - PR9: u1 = 0, - /// Pending bit 10 - PR10: u1 = 0, - /// Pending bit 11 - PR11: u1 = 0, - /// Pending bit 12 - PR12: u1 = 0, - /// Pending bit 13 - PR13: u1 = 0, - /// Pending bit 14 - PR14: u1 = 0, - /// Pending bit 15 - PR15: u1 = 0, - /// Pending bit 16 - PR16: u1 = 0, - /// Pending bit 17 - PR17: u1 = 0, - /// Pending bit 18 - PR18: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// DMA controller -pub const DMA1 = extern struct { - pub const Address: u32 = 0x40020000; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// DMA controller -pub const DMA2 = extern struct { - pub const Address: u32 = 0x40020400; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// Secure digital input/output interface -pub const SDIO = extern struct { - pub const Address: u32 = 0x40018000; - - /// Bits 1:0 = PWRCTRL: Power supply control bits - pub const POWER = mmio(Address + 0x00000000, 32, packed struct { - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDI clock control register (SDIO_CLKCR) - pub const CLKCR = mmio(Address + 0x00000004, 32, packed struct { - /// Clock divide factor - CLKDIV: u8 = 0, - /// Clock enable bit - CLKEN: u1 = 0, - /// Power saving configuration bit - PWRSAV: u1 = 0, - /// Clock divider bypass enable bit - BYPASS: u1 = 0, - /// Wide bus mode enable bit - WIDBUS: u2 = 0, - /// SDIO_CK dephasing selection bit - NEGEDGE: u1 = 0, - /// HW Flow Control enable - HWFC_EN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 31:0 = : Command argument - pub const ARG = mmio(Address + 0x00000008, 32, packed struct { - /// Command argument - CMDARG: u32 = 0, - }); - - /// SDIO command register (SDIO_CMD) - pub const CMD = mmio(Address + 0x0000000c, 32, packed struct { - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO command register - pub const RESPCMD = mmio(Address + 0x00000010, 32, packed struct { - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = mmio(Address + 0x00000014, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS2 - pub const RESP2 = mmio(Address + 0x00000018, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS3 - pub const RESP3 = mmio(Address + 0x0000001c, 32, packed struct {}); - - /// Bits 31:0 = CARDSTATUS4 - pub const RESP4 = mmio(Address + 0x00000020, 32, packed struct {}); - - /// Bits 31:0 = DATATIME: Data timeout period - pub const DTIMER = mmio(Address + 0x00000024, 32, packed struct { - /// Data timeout period - DATATIME: u32 = 0, - }); - - /// Bits 24:0 = DATALENGTH: Data length value - pub const DLEN = mmio(Address + 0x00000028, 32, packed struct { - /// Data length value - DATALENGTH: u25 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO data control register (SDIO_DCTRL) - pub const DCTRL = mmio(Address + 0x0000002c, 32, packed struct { - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 24:0 = DATACOUNT: Data count value - pub const DCOUNT = mmio(Address + 0x00000030, 32, packed struct { - /// Data count value - DATACOUNT: u25 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO status register (SDIO_STA) - pub const STA = mmio(Address + 0x00000034, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO interrupt clear register (SDIO_ICR) - pub const ICR = mmio(Address + 0x00000038, 32, packed struct { - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SDIO mask register (SDIO_MASK) - pub const MASK = mmio(Address + 0x0000003c, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read - /// from the FIFO - pub const FIFOCNT = mmio(Address + 0x00000048, 32, packed struct { - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// bits 31:0 = FIFOData: Receive and transmit FIFO data - pub const FIFO = mmio(Address + 0x00000080, 32, packed struct {}); -}; - -/// Real time clock -pub const RTC = extern struct { - pub const Address: u32 = 0x40002800; - - /// RTC Control Register High - pub const CRH = mmio(Address + 0x00000000, 32, packed struct { - /// Second interrupt Enable - SECIE: u1 = 0, - /// Alarm interrupt Enable - ALRIE: u1 = 0, - /// Overflow interrupt Enable - OWIE: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Control Register Low - pub const CRL = mmio(Address + 0x00000004, 32, packed struct { - /// Second Flag - SECF: u1 = 0, - /// Alarm Flag - ALRF: u1 = 0, - /// Overflow Flag - OWF: u1 = 0, - /// Registers Synchronized Flag - RSF: u1 = 0, - /// Configuration Flag - CNF: u1 = 0, - /// RTC operation OFF - RTOFF: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Load Register High - pub const PRLH = mmio(Address + 0x00000008, 32, packed struct { - /// RTC Prescaler Load Register High - PRLH: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Load Register Low - pub const PRLL = mmio(Address + 0x0000000c, 32, packed struct { - /// RTC Prescaler Divider Register Low - PRLL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Divider Register High - pub const DIVH = mmio(Address + 0x00000010, 32, packed struct { - /// RTC prescaler divider register high - DIVH: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Prescaler Divider Register Low - pub const DIVL = mmio(Address + 0x00000014, 32, packed struct { - /// RTC prescaler divider register Low - DIVL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Counter Register High - pub const CNTH = mmio(Address + 0x00000018, 32, packed struct { - /// RTC counter register high - CNTH: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Counter Register Low - pub const CNTL = mmio(Address + 0x0000001c, 32, packed struct { - /// RTC counter register Low - CNTL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Alarm Register High - pub const ALRH = mmio(Address + 0x00000020, 32, packed struct { - /// RTC alarm register high - ALRH: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC Alarm Register Low - pub const ALRL = mmio(Address + 0x00000024, 32, packed struct { - /// RTC alarm register low - ALRL: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Backup registers -pub const BKP = extern struct { - pub const Address: u32 = 0x40006c04; - - /// Backup data register (BKP_DR) - pub const DR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Backup data - D1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Backup data - D2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Backup data - D3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR4 = mmio(Address + 0x0000000c, 32, packed struct { - /// Backup data - D4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR5 = mmio(Address + 0x00000010, 32, packed struct { - /// Backup data - D5: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR6 = mmio(Address + 0x00000014, 32, packed struct { - /// Backup data - D6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR7 = mmio(Address + 0x00000018, 32, packed struct { - /// Backup data - D7: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR8 = mmio(Address + 0x0000001c, 32, packed struct { - /// Backup data - D8: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR9 = mmio(Address + 0x00000020, 32, packed struct { - /// Backup data - D9: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR10 = mmio(Address + 0x00000024, 32, packed struct { - /// Backup data - D10: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RTC clock calibration register (BKP_RTCCR) - pub const RTCCR = mmio(Address + 0x00000028, 32, packed struct { - /// Calibration value - CAL: u7 = 0, - /// Calibration Clock Output - CCO: u1 = 0, - /// Alarm or second output enable - ASOE: u1 = 0, - /// Alarm or second output selection - ASOS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup control register (BKP_CR) - pub const CR = mmio(Address + 0x0000002c, 32, packed struct { - /// Tamper pin enable - TPE: u1 = 0, - /// Tamper pin active level - TPAL: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// BKP_CSR control/status register (BKP_CSR) - pub const CSR = mmio(Address + 0x00000030, 32, packed struct { - /// Clear Tamper event - CTE: u1 = 0, - /// Clear Tamper Interrupt - CTI: u1 = 0, - /// Tamper Pin interrupt enable - TPIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Tamper Event Flag - TEF: u1 = 0, - /// Tamper Interrupt Flag - TIF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR11 = mmio(Address + 0x0000003c, 32, packed struct { - /// Backup data - DR11: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR12 = mmio(Address + 0x00000040, 32, packed struct { - /// Backup data - DR12: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR13 = mmio(Address + 0x00000044, 32, packed struct { - /// Backup data - DR13: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR14 = mmio(Address + 0x00000048, 32, packed struct { - /// Backup data - D14: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR15 = mmio(Address + 0x0000004c, 32, packed struct { - /// Backup data - D15: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR16 = mmio(Address + 0x00000050, 32, packed struct { - /// Backup data - D16: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR17 = mmio(Address + 0x00000054, 32, packed struct { - /// Backup data - D17: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR18 = mmio(Address + 0x00000058, 32, packed struct { - /// Backup data - D18: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR19 = mmio(Address + 0x0000005c, 32, packed struct { - /// Backup data - D19: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR20 = mmio(Address + 0x00000060, 32, packed struct { - /// Backup data - D20: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR21 = mmio(Address + 0x00000064, 32, packed struct { - /// Backup data - D21: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR22 = mmio(Address + 0x00000068, 32, packed struct { - /// Backup data - D22: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR23 = mmio(Address + 0x0000006c, 32, packed struct { - /// Backup data - D23: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR24 = mmio(Address + 0x00000070, 32, packed struct { - /// Backup data - D24: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR25 = mmio(Address + 0x00000074, 32, packed struct { - /// Backup data - D25: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR26 = mmio(Address + 0x00000078, 32, packed struct { - /// Backup data - D26: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR27 = mmio(Address + 0x0000007c, 32, packed struct { - /// Backup data - D27: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR28 = mmio(Address + 0x00000080, 32, packed struct { - /// Backup data - D28: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR29 = mmio(Address + 0x00000084, 32, packed struct { - /// Backup data - D29: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR30 = mmio(Address + 0x00000088, 32, packed struct { - /// Backup data - D30: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR31 = mmio(Address + 0x0000008c, 32, packed struct { - /// Backup data - D31: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR32 = mmio(Address + 0x00000090, 32, packed struct { - /// Backup data - D32: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR33 = mmio(Address + 0x00000094, 32, packed struct { - /// Backup data - D33: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR34 = mmio(Address + 0x00000098, 32, packed struct { - /// Backup data - D34: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR35 = mmio(Address + 0x0000009c, 32, packed struct { - /// Backup data - D35: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR36 = mmio(Address + 0x000000a0, 32, packed struct { - /// Backup data - D36: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR37 = mmio(Address + 0x000000a4, 32, packed struct { - /// Backup data - D37: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR38 = mmio(Address + 0x000000a8, 32, packed struct { - /// Backup data - D38: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR39 = mmio(Address + 0x000000ac, 32, packed struct { - /// Backup data - D39: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR40 = mmio(Address + 0x000000b0, 32, packed struct { - /// Backup data - D40: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR41 = mmio(Address + 0x000000b4, 32, packed struct { - /// Backup data - D41: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup data register (BKP_DR) - pub const DR42 = mmio(Address + 0x000000b8, 32, packed struct { - /// Backup data - D42: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Independent watchdog -pub const IWDG = extern struct { - pub const Address: u32 = 0x40003000; - - /// Key register (IWDG_KR) - pub const KR = mmio(Address + 0x00000000, 32, packed struct { - /// Key value - KEY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Prescaler register (IWDG_PR) - pub const PR = mmio(Address + 0x00000004, 32, packed struct { - /// Prescaler divider - PR: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reload register (IWDG_RLR) - pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - /// Watchdog counter reload value - RL: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register (IWDG_SR) - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Watchdog prescaler value update - PVU: u1 = 0, - /// Watchdog counter reload value update - RVU: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Window watchdog -pub const WWDG = extern struct { - pub const Address: u32 = 0x40002c00; - - /// Control register (WWDG_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// 7-bit counter (MSB to LSB) - T: u7 = 0, - /// Activation bit - WDGA: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register (WWDG_CFR) - pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - /// 7-bit window value - W: u7 = 0, - /// Timer Base - WDGTB: u2 = 0, - /// Early Wakeup Interrupt - EWI: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register (WWDG_SR) - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Early Wakeup Interrupt - EWI: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM1 = extern struct { - pub const Address: u32 = 0x40012c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - ICPCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM8 = extern struct { - pub const Address: u32 = 0x40013400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - ICPCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM2 = extern struct { - pub const Address: u32 = 0x40000000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM3 = extern struct { - pub const Address: u32 = 0x40000400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM4 = extern struct { - pub const Address: u32 = 0x40000800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM5 = extern struct { - pub const Address: u32 = 0x40000c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM9 = extern struct { - pub const Address: u32 = 0x40014c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM12 = extern struct { - pub const Address: u32 = 0x40001800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM10 = extern struct { - pub const Address: u32 = 0x40015000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM11 = extern struct { - pub const Address: u32 = 0x40015400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM13 = extern struct { - pub const Address: u32 = 0x40001c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM14 = extern struct { - pub const Address: u32 = 0x40002000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - reserved1: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timer -pub const TIM6 = extern struct { - pub const Address: u32 = 0x40001000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timer -pub const TIM7 = extern struct { - pub const Address: u32 = 0x40001400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter integrated circuit -pub const I2C1 = extern struct { - pub const Address: u32 = 0x40005400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// SMBus mode - SMBUS: u1 = 0, - reserved1: u1 = 0, - /// SMBus type - SMBTYPE: u1 = 0, - /// ARP enable - ENARP: u1 = 0, - /// PEC enable - ENPEC: u1 = 0, - /// General call enable - ENGC: u1 = 0, - /// Clock stretching disable (Slave mode) - NOSTRETCH: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation - STOP: u1 = 0, - /// Acknowledge enable - ACK: u1 = 0, - /// Acknowledge/PEC Position (for data reception) - POS: u1 = 0, - /// Packet error checking - PEC: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved2: u1 = 0, - /// Software reset - SWRST: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Peripheral clock frequency - FREQ: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ITERREN: u1 = 0, - /// Event interrupt enable - ITEVTEN: u1 = 0, - /// Buffer interrupt enable - ITBUFEN: u1 = 0, - /// DMA requests enable - DMAEN: u1 = 0, - /// DMA last transfer - LAST: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - ADD0: u1 = 0, - /// Interface address - ADD7: u7 = 0, - /// Interface address - ADD10: u2 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Addressing mode (slave mode) - ADDMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// Dual addressing mode enable - ENDUAL: u1 = 0, - /// Interface address - ADD2: u7 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000010, 32, packed struct { - /// 8-bit data register - DR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 1 - pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Start bit (Master mode) - SB: u1 = 0, - /// Address sent (master mode)/matched (slave mode) - ADDR: u1 = 0, - /// Byte transfer finished - BTF: u1 = 0, - /// 10-bit header sent (Master mode) - ADD10: u1 = 0, - /// Stop detection (slave mode) - STOPF: u1 = 0, - reserved1: u1 = 0, - /// Data register not empty (receivers) - RxNE: u1 = 0, - /// Data register empty (transmitters) - TxE: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost (master mode) - ARLO: u1 = 0, - /// Acknowledge failure - AF: u1 = 0, - /// Overrun/Underrun - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - reserved2: u1 = 0, - /// Timeout or Tlow error - TIMEOUT: u1 = 0, - /// SMBus alert - SMBALERT: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 2 - pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Master/slave - MSL: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transmitter/receiver - TRA: u1 = 0, - reserved1: u1 = 0, - /// General call address (Slave mode) - GENCALL: u1 = 0, - /// SMBus device default address (Slave mode) - SMBDEFAULT: u1 = 0, - /// SMBus host header (Slave mode) - SMBHOST: u1 = 0, - /// Dual flag (Slave mode) - DUALF: u1 = 0, - /// acket error checking register - PEC: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock control register - pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - /// Clock control register in Fast/Standard mode (Master mode) - CCR: u12 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Fast mode duty cycle - DUTY: u1 = 0, - /// I2C master mode selection - F_S: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TRISE register - pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - /// Maximum rise time in Fast/Standard mode (Master mode) - TRISE: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter integrated circuit -pub const I2C2 = extern struct { - pub const Address: u32 = 0x40005800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// SMBus mode - SMBUS: u1 = 0, - reserved1: u1 = 0, - /// SMBus type - SMBTYPE: u1 = 0, - /// ARP enable - ENARP: u1 = 0, - /// PEC enable - ENPEC: u1 = 0, - /// General call enable - ENGC: u1 = 0, - /// Clock stretching disable (Slave mode) - NOSTRETCH: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation - STOP: u1 = 0, - /// Acknowledge enable - ACK: u1 = 0, - /// Acknowledge/PEC Position (for data reception) - POS: u1 = 0, - /// Packet error checking - PEC: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved2: u1 = 0, - /// Software reset - SWRST: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Peripheral clock frequency - FREQ: u6 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ITERREN: u1 = 0, - /// Event interrupt enable - ITEVTEN: u1 = 0, - /// Buffer interrupt enable - ITBUFEN: u1 = 0, - /// DMA requests enable - DMAEN: u1 = 0, - /// DMA last transfer - LAST: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - ADD0: u1 = 0, - /// Interface address - ADD7: u7 = 0, - /// Interface address - ADD10: u2 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Addressing mode (slave mode) - ADDMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// Dual addressing mode enable - ENDUAL: u1 = 0, - /// Interface address - ADD2: u7 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000010, 32, packed struct { - /// 8-bit data register - DR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 1 - pub const SR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Start bit (Master mode) - SB: u1 = 0, - /// Address sent (master mode)/matched (slave mode) - ADDR: u1 = 0, - /// Byte transfer finished - BTF: u1 = 0, - /// 10-bit header sent (Master mode) - ADD10: u1 = 0, - /// Stop detection (slave mode) - STOPF: u1 = 0, - reserved1: u1 = 0, - /// Data register not empty (receivers) - RxNE: u1 = 0, - /// Data register empty (transmitters) - TxE: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost (master mode) - ARLO: u1 = 0, - /// Acknowledge failure - AF: u1 = 0, - /// Overrun/Underrun - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - reserved2: u1 = 0, - /// Timeout or Tlow error - TIMEOUT: u1 = 0, - /// SMBus alert - SMBALERT: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register 2 - pub const SR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Master/slave - MSL: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transmitter/receiver - TRA: u1 = 0, - reserved1: u1 = 0, - /// General call address (Slave mode) - GENCALL: u1 = 0, - /// SMBus device default address (Slave mode) - SMBDEFAULT: u1 = 0, - /// SMBus host header (Slave mode) - SMBHOST: u1 = 0, - /// Dual flag (Slave mode) - DUALF: u1 = 0, - /// acket error checking register - PEC: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock control register - pub const CCR = mmio(Address + 0x0000001c, 32, packed struct { - /// Clock control register in Fast/Standard mode (Master mode) - CCR: u12 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Fast mode duty cycle - DUTY: u1 = 0, - /// I2C master mode selection - F_S: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TRISE register - pub const TRISE = mmio(Address + 0x00000020, 32, packed struct { - /// Maximum rise time in Fast/Standard mode (Master mode) - TRISE: u6 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40013000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { +// this file is generated by regz +// +// device: STM32F103xx + +pub const registers = struct { + /// Flexible static memory controller + pub const FSMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000000c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000010 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000014 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000018 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000001c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000060 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000064 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000068 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000006c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Attribute memory x setup + /// time + ATTSETx: u8, + /// Attribute memory x wait + /// time + ATTWAITx: u8, + /// Attribute memory x hold + /// time + ATTHOLDx: u8, + /// Attribute memory x databus HiZ + /// time + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000074 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECC result + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000080 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000084 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000088 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000008c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000094 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00000a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00000a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00000a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00000ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00000b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000114 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x114); + + /// address: 0xa000011c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x11c); + }; + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// Power control register + /// (PWR_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Power Deep Sleep + LPDS: u1, + /// Power Down Deep Sleep + PDDS: u1, + /// Clear Wake-up Flag + CWUF: u1, + /// Clear STANDBY Flag + CSBF: u1, + /// Power Voltage Detector + /// Enable + PVDE: u1, + /// PVD Level Selection + PLS: u3, + /// Disable Backup Domain write + /// protection + DBP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// Power control register + /// (PWR_CR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wake-Up Flag + WUF: u1, + /// STANDBY Flag + SBF: u1, + /// PVD Output + PVDO: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Enable WKUP pin + EWUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x4); + }; + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// Clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal High Speed clock + /// enable + HSION: u1, + /// Internal High Speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal High Speed clock + /// trimming + HSITRIM: u5, + /// Internal High Speed clock + /// Calibration + HSICAL: u8, + /// External High Speed clock + /// enable + HSEON: u1, + /// External High Speed clock ready + /// flag + HSERDY: u1, + /// External High Speed clock + /// Bypass + HSEBYP: u1, + /// Clock Security System + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40021004 + /// Clock configuration register + /// (RCC_CFGR) + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB High speed prescaler + /// (APB2) + PPRE2: u3, + /// ADC prescaler + ADCPRE: u2, + /// PLL entry clock source + PLLSRC: u1, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB OTG FS prescaler + OTGFSPRE: u1, + reserved0: u1, + /// Microcontroller clock + /// output + MCO: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// Clock interrupt register + /// (RCC_CIR) + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved0: u1, + reserved1: u1, + /// Clock Security System Interrupt + /// flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved5: u1, + reserved6: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4002100c + /// APB2 peripheral reset register + /// (RCC_APB2RSTR) + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function I/O + /// reset + AFIORST: u1, + reserved0: u1, + /// IO port A reset + IOPARST: u1, + /// IO port B reset + IOPBRST: u1, + /// IO port C reset + IOPCRST: u1, + /// IO port D reset + IOPDRST: u1, + /// IO port E reset + IOPERST: u1, + /// IO port F reset + IOPFRST: u1, + /// IO port G reset + IOPGRST: u1, + /// ADC 1 interface reset + ADC1RST: u1, + /// ADC 2 interface reset + ADC2RST: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// ADC 3 interface reset + ADC3RST: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TIM9 timer reset + TIM9RST: u1, + /// TIM10 timer reset + TIM10RST: u1, + /// TIM11 timer reset + TIM11RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc); + + /// address: 0x40021010 + /// APB1 peripheral reset register + /// (RCC_APB1RSTR) + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + /// Timer 12 reset + TIM12RST: u1, + /// Timer 13 reset + TIM13RST: u1, + /// Timer 14 reset + TIM14RST: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved4: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved5: u1, + /// CAN reset + CANRST: u1, + reserved6: u1, + /// Backup interface reset + BKPRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// AHB Peripheral Clock enable register + /// (RCC_AHBENR) + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock + /// enable + SRAMEN: u1, + reserved0: u1, + /// FLITF clock enable + FLITFEN: u1, + reserved1: u1, + /// CRC clock enable + CRCEN: u1, + reserved2: u1, + /// FSMC clock enable + FSMCEN: u1, + reserved3: u1, + /// SDIO clock enable + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// APB2 peripheral clock enable register + /// (RCC_APB2ENR) + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function I/O clock + /// enable + AFIOEN: u1, + reserved0: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// ADC 1 interface clock + /// enable + ADC1EN: u1, + /// ADC 2 interface clock + /// enable + ADC2EN: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// ADC3 interface clock + /// enable + ADC3EN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TIM9 Timer clock enable + TIM9EN: u1, + /// TIM10 Timer clock enable + TIM10EN: u1, + /// TIM11 Timer clock enable + TIM11EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// APB1 peripheral clock enable register + /// (RCC_APB1ENR) + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + /// Timer 12 clock enable + TIM12EN: u1, + /// Timer 13 clock enable + TIM13EN: u1, + /// Timer 14 clock enable + TIM14EN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved4: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + UART4EN: u1, + /// UART 5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved5: u1, + /// CAN clock enable + CANEN: u1, + reserved6: u1, + /// Backup interface clock + /// enable + BKPEN: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// Backup domain control register + /// (RCC_BDCR) + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// External Low Speed oscillator + /// enable + LSEON: u1, + /// External Low Speed oscillator + /// ready + LSERDY: u1, + /// External Low Speed oscillator + /// bypass + LSEBYP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock source selection + RTCSEL: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x20); + + /// address: 0x40021024 + /// Control/status register + /// (RCC_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal low speed oscillator + /// enable + LSION: u1, + /// Internal low speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + reserved22: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x24); + }; + /// General purpose I/O + pub const GPIOA = struct { + pub const base_address = 0x40010800; + + /// address: 0x40010800 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40010804 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40010808 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001080c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010810 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40010814 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010818 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOB = struct { + pub const base_address = 0x40010c00; + + /// address: 0x40010c00 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40010c04 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40010c08 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40010c0c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010c10 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40010c14 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010c18 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOC = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011004 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011008 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOD = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011404 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011408 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOE = struct { + pub const base_address = 0x40011800; + + /// address: 0x40011800 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011804 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011808 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001180c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011810 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011814 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011818 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOF = struct { + pub const base_address = 0x40011c00; + + /// address: 0x40011c00 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40011c04 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40011c08 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40011c0c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011c10 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40011c14 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011c18 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOG = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// Port configuration register low + /// (GPIOn_CRL) + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration + /// bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration + /// bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration + /// bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration + /// bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration + /// bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration + /// bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration + /// bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration + /// bits + CNF7: u2, + }), base_address + 0x0); + + /// address: 0x40012004 + /// Port configuration register high + /// (GPIOn_CRL) + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration + /// bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration + /// bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration + /// bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration + /// bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration + /// bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration + /// bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration + /// bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration + /// bits + CNF15: u2, + }), base_address + 0x4); + + /// address: 0x40012008 + /// Port input data register + /// (GPIOn_IDR) + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001200c + /// Port output data register + /// (GPIOn_ODR) + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40012010 + /// Port bit set/reset register + /// (GPIOn_BSRR) + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), base_address + 0x10); + + /// address: 0x40012014 + /// Port bit reset register + /// (GPIOn_BRR) + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40012018 + /// Port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + /// Alternate function I/O + pub const AFIO = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// Event Control Register + /// (AFIO_EVCR) + pub const EVCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pin selection + PIN: u4, + /// Port selection + PORT: u3, + /// Event Output Enable + EVOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// AF remap and debug I/O configuration + /// register (AFIO_MAPR) + pub const MAPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SPI1 remapping + SPI1_REMAP: u1, + /// I2C1 remapping + I2C1_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u1, + /// USART3 remapping + USART3_REMAP: u2, + /// TIM1 remapping + TIM1_REMAP: u2, + /// TIM2 remapping + TIM2_REMAP: u2, + /// TIM3 remapping + TIM3_REMAP: u2, + /// TIM4 remapping + TIM4_REMAP: u1, + /// CAN1 remapping + CAN_REMAP: u2, + /// Port D0/Port D1 mapping on + /// OSCIN/OSCOUT + PD01_REMAP: u1, + /// Set and cleared by + /// software + TIM5CH4_IREMAP: u1, + /// ADC 1 External trigger injected + /// conversion remapping + ADC1_ETRGINJ_REMAP: u1, + /// ADC 1 external trigger regular + /// conversion remapping + ADC1_ETRGREG_REMAP: u1, + /// ADC 2 external trigger injected + /// conversion remapping + ADC2_ETRGINJ_REMAP: u1, + /// ADC 2 external trigger regular + /// conversion remapping + ADC2_ETRGREG_REMAP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Serial wire JTAG + /// configuration + SWJ_CFG: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// External interrupt configuration register 1 + /// (AFIO_EXTICR1) + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI0 configuration + EXTI0: u4, + /// EXTI1 configuration + EXTI1: u4, + /// EXTI2 configuration + EXTI2: u4, + /// EXTI3 configuration + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// External interrupt configuration register 2 + /// (AFIO_EXTICR2) + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI4 configuration + EXTI4: u4, + /// EXTI5 configuration + EXTI5: u4, + /// EXTI6 configuration + EXTI6: u4, + /// EXTI7 configuration + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// External interrupt configuration register 3 + /// (AFIO_EXTICR3) + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI8 configuration + EXTI8: u4, + /// EXTI9 configuration + EXTI9: u4, + /// EXTI10 configuration + EXTI10: u4, + /// EXTI11 configuration + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// External interrupt configuration register 4 + /// (AFIO_EXTICR4) + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI12 configuration + EXTI12: u4, + /// EXTI13 configuration + EXTI13: u4, + /// EXTI14 configuration + EXTI14: u4, + /// EXTI15 configuration + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x4001001c + /// AF remap and debug I/O configuration + /// register + pub const MAPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// TIM9 remapping + TIM9_REMAP: u1, + /// TIM10 remapping + TIM10_REMAP: u1, + /// TIM11 remapping + TIM11_REMAP: u1, + /// TIM13 remapping + TIM13_REMAP: u1, + /// TIM14 remapping + TIM14_REMAP: u1, + /// NADV connect/disconnect + FSMC_NADV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c); + }; + /// EXTI + pub const EXTI = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// Interrupt mask register + /// (EXTI_IMR) + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// Event mask register (EXTI_EMR) + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// Rising Trigger selection register + /// (EXTI_RTSR) + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// Falling Trigger selection register + /// (EXTI_FTSR) + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// Software interrupt event register + /// (EXTI_SWIER) + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// Pending register (EXTI_PR) + pub const PR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x14); + }; + /// DMA controller + pub const DMA1 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002006c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020070 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020074 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020078 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020080 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020084 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020088 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002008c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + pub const DMA2 = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020404 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002040c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020410 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020414 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002041c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020424 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020428 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020430 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020434 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020438 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002043c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020444 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020448 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002044c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020450 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020458 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002045c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020460 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020464 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002046c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020470 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020474 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020478 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020480 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020484 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020488 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002048c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + /// Secure digital input/output + /// interface + pub const SDIO = struct { + pub const base_address = 0x40018000; + + /// address: 0x40018000 + /// Bits 1:0 = PWRCTRL: Power supply control + /// bits + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct{ + /// PWRCTRL + PWRCTRL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40018004 + /// SDI clock control register + /// (SDIO_CLKCR) + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration + /// bit + PWRSAV: u1, + /// Clock divider bypass enable + /// bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection + /// bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40018008 + /// Bits 31:0 = : Command argument + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct{ + /// Command argument + CMDARG: u32, + }), base_address + 0x8); + + /// address: 0x4001800c + /// SDIO command register + /// (SDIO_CMD) + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct{ + /// CMDINDEX + CMDINDEX: u6, + /// WAITRESP + WAITRESP: u2, + /// WAITINT + WAITINT: u1, + /// WAITPEND + WAITPEND: u1, + /// CPSMEN + CPSMEN: u1, + /// SDIOSuspend + SDIOSuspend: u1, + /// ENCMDcompl + ENCMDcompl: u1, + /// nIEN + nIEN: u1, + /// CE_ATACMD + CE_ATACMD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40018010 + /// SDIO command register + pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40018014 + /// Bits 31:0 = CARDSTATUS1 + pub const RESPI1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS1 + CARDSTATUS1: u32, + }), base_address + 0x14); + + /// address: 0x40018018 + /// Bits 31:0 = CARDSTATUS2 + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS2 + CARDSTATUS2: u32, + }), base_address + 0x18); + + /// address: 0x4001801c + /// Bits 31:0 = CARDSTATUS3 + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS3 + CARDSTATUS3: u32, + }), base_address + 0x1c); + + /// address: 0x40018020 + /// Bits 31:0 = CARDSTATUS4 + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CARDSTATUS4 + CARDSTATUS4: u32, + }), base_address + 0x20); + + /// address: 0x40018024 + /// Bits 31:0 = DATATIME: Data timeout + /// period + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data timeout period + DATATIME: u32, + }), base_address + 0x24); + + /// address: 0x40018028 + /// Bits 24:0 = DATALENGTH: Data length + /// value + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data length value + DATALENGTH: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0x4001802c + /// SDIO data control register + /// (SDIO_DCTRL) + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// DTEN + DTEN: u1, + /// DTDIR + DTDIR: u1, + /// DTMODE + DTMODE: u1, + /// DMAEN + DMAEN: u1, + /// DBLOCKSIZE + DBLOCKSIZE: u4, + /// PWSTART + PWSTART: u1, + /// PWSTOP + PWSTOP: u1, + /// RWMOD + RWMOD: u1, + /// SDIOEN + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40018030 + /// Bits 24:0 = DATACOUNT: Data count + /// value + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data count value + DATACOUNT: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + + /// address: 0x40018034 + /// SDIO status register + /// (SDIO_STA) + pub const STA = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAIL + CCRCFAIL: u1, + /// DCRCFAIL + DCRCFAIL: u1, + /// CTIMEOUT + CTIMEOUT: u1, + /// DTIMEOUT + DTIMEOUT: u1, + /// TXUNDERR + TXUNDERR: u1, + /// RXOVERR + RXOVERR: u1, + /// CMDREND + CMDREND: u1, + /// CMDSENT + CMDSENT: u1, + /// DATAEND + DATAEND: u1, + /// STBITERR + STBITERR: u1, + /// DBCKEND + DBCKEND: u1, + /// CMDACT + CMDACT: u1, + /// TXACT + TXACT: u1, + /// RXACT + RXACT: u1, + /// TXFIFOHE + TXFIFOHE: u1, + /// RXFIFOHF + RXFIFOHF: u1, + /// TXFIFOF + TXFIFOF: u1, + /// RXFIFOF + RXFIFOF: u1, + /// TXFIFOE + TXFIFOE: u1, + /// RXFIFOE + RXFIFOE: u1, + /// TXDAVL + TXDAVL: u1, + /// RXDAVL + RXDAVL: u1, + /// SDIOIT + SDIOIT: u1, + /// CEATAEND + CEATAEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x40018038 + /// SDIO interrupt clear register + /// (SDIO_ICR) + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAILC + CCRCFAILC: u1, + /// DCRCFAILC + DCRCFAILC: u1, + /// CTIMEOUTC + CTIMEOUTC: u1, + /// DTIMEOUTC + DTIMEOUTC: u1, + /// TXUNDERRC + TXUNDERRC: u1, + /// RXOVERRC + RXOVERRC: u1, + /// CMDRENDC + CMDRENDC: u1, + /// CMDSENTC + CMDSENTC: u1, + /// DATAENDC + DATAENDC: u1, + /// STBITERRC + STBITERRC: u1, + /// DBCKENDC + DBCKENDC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// SDIOITC + SDIOITC: u1, + /// CEATAENDC + CEATAENDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x38); + + /// address: 0x4001803c + /// SDIO mask register (SDIO_MASK) + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCRCFAILIE + CCRCFAILIE: u1, + /// DCRCFAILIE + DCRCFAILIE: u1, + /// CTIMEOUTIE + CTIMEOUTIE: u1, + /// DTIMEOUTIE + DTIMEOUTIE: u1, + /// TXUNDERRIE + TXUNDERRIE: u1, + /// RXOVERRIE + RXOVERRIE: u1, + /// CMDRENDIE + CMDRENDIE: u1, + /// CMDSENTIE + CMDSENTIE: u1, + /// DATAENDIE + DATAENDIE: u1, + /// STBITERRIE + STBITERRIE: u1, + /// DBACKENDIE + DBACKENDIE: u1, + /// CMDACTIE + CMDACTIE: u1, + /// TXACTIE + TXACTIE: u1, + /// RXACTIE + RXACTIE: u1, + /// TXFIFOHEIE + TXFIFOHEIE: u1, + /// RXFIFOHFIE + RXFIFOHFIE: u1, + /// TXFIFOFIE + TXFIFOFIE: u1, + /// RXFIFOFIE + RXFIFOFIE: u1, + /// TXFIFOEIE + TXFIFOEIE: u1, + /// RXFIFOEIE + RXFIFOEIE: u1, + /// TXDAVLIE + TXDAVLIE: u1, + /// RXDAVLIE + RXDAVLIE: u1, + /// SDIOITIE + SDIOITIE: u1, + /// CEATENDIE + CEATENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x40018048 + /// Bits 23:0 = FIFOCOUNT: Remaining number of + /// words to be written to or read from the + /// FIFO + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// FIF0COUNT + FIF0COUNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x40018080 + /// bits 31:0 = FIFOData: Receive and transmit + /// FIFO data + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct{ + /// FIFOData + FIFOData: u32, + }), base_address + 0x80); + }; + /// Real time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// RTC Control Register High + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second interrupt Enable + SECIE: u1, + /// Alarm interrupt Enable + ALRIE: u1, + /// Overflow interrupt Enable + OWIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// RTC Control Register Low + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second Flag + SECF: u1, + /// Alarm Flag + ALRF: u1, + /// Overflow Flag + OWF: u1, + /// Registers Synchronized + /// Flag + RSF: u1, + /// Configuration Flag + CNF: u1, + /// RTC operation OFF + RTOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// RTC Prescaler Load Register + /// High + pub const PRLH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x8); + + /// address: 0x4000280c + /// RTC Prescaler Load Register + /// Low + pub const PRLL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40002810 + /// RTC Prescaler Divider Register + /// High + pub const DIVH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); + + /// address: 0x40002814 + /// RTC Prescaler Divider Register + /// Low + pub const DIVL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x40002818 + /// RTC Counter Register High + pub const CNTH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4000281c + /// RTC Counter Register Low + pub const CNTL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x40002820 + /// RTC Alarm Register High + pub const ALRH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20); + + /// address: 0x40002824 + /// RTC Alarm Register Low + pub const ALRL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + }; + /// Backup registers + pub const BKP = struct { + pub const base_address = 0x40006c04; + + /// address: 0x40006c04 + /// Backup data register (BKP_DR) + pub const DR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40006c08 + /// Backup data register (BKP_DR) + pub const DR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40006c0c + /// Backup data register (BKP_DR) + pub const DR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40006c10 + /// Backup data register (BKP_DR) + pub const DR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40006c14 + /// Backup data register (BKP_DR) + pub const DR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D5: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40006c18 + /// Backup data register (BKP_DR) + pub const DR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D6: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40006c1c + /// Backup data register (BKP_DR) + pub const DR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D7: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40006c20 + /// Backup data register (BKP_DR) + pub const DR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D8: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40006c24 + /// Backup data register (BKP_DR) + pub const DR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D9: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40006c28 + /// Backup data register (BKP_DR) + pub const DR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D10: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x40006c40 + /// Backup data register (BKP_DR) + pub const DR11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40006c44 + /// Backup data register (BKP_DR) + pub const DR12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40006c48 + /// Backup data register (BKP_DR) + pub const DR13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x44); + + /// address: 0x40006c4c + /// Backup data register (BKP_DR) + pub const DR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D14: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40006c50 + /// Backup data register (BKP_DR) + pub const DR15 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D15: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40006c54 + /// Backup data register (BKP_DR) + pub const DR16 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D16: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x50); + + /// address: 0x40006c58 + /// Backup data register (BKP_DR) + pub const DR17 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D17: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x54); + + /// address: 0x40006c5c + /// Backup data register (BKP_DR) + pub const DR18 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D18: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x58); + + /// address: 0x40006c60 + /// Backup data register (BKP_DR) + pub const DR19 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D19: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40006c64 + /// Backup data register (BKP_DR) + pub const DR20 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D20: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x60); + + /// address: 0x40006c68 + /// Backup data register (BKP_DR) + pub const DR21 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D21: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x64); + + /// address: 0x40006c6c + /// Backup data register (BKP_DR) + pub const DR22 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D22: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x68); + + /// address: 0x40006c70 + /// Backup data register (BKP_DR) + pub const DR23 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D23: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x6c); + + /// address: 0x40006c74 + /// Backup data register (BKP_DR) + pub const DR24 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D24: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40006c78 + /// Backup data register (BKP_DR) + pub const DR25 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D25: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40006c7c + /// Backup data register (BKP_DR) + pub const DR26 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D26: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x78); + + /// address: 0x40006c80 + /// Backup data register (BKP_DR) + pub const DR27 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D27: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x7c); + + /// address: 0x40006c84 + /// Backup data register (BKP_DR) + pub const DR28 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D28: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x40006c88 + /// Backup data register (BKP_DR) + pub const DR29 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D29: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40006c8c + /// Backup data register (BKP_DR) + pub const DR30 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D30: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x40006c90 + /// Backup data register (BKP_DR) + pub const DR31 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D31: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40006c94 + /// Backup data register (BKP_DR) + pub const DR32 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D32: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x90); + + /// address: 0x40006c98 + /// Backup data register (BKP_DR) + pub const DR33 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D33: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x40006c9c + /// Backup data register (BKP_DR) + pub const DR34 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D34: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x98); + + /// address: 0x40006ca0 + /// Backup data register (BKP_DR) + pub const DR35 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D35: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x9c); + + /// address: 0x40006ca4 + /// Backup data register (BKP_DR) + pub const DR36 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D36: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa0); + + /// address: 0x40006ca8 + /// Backup data register (BKP_DR) + pub const DR37 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D37: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x40006cac + /// Backup data register (BKP_DR) + pub const DR38 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D38: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa8); + + /// address: 0x40006cb0 + /// Backup data register (BKP_DR) + pub const DR39 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D39: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x40006cb4 + /// Backup data register (BKP_DR) + pub const DR40 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D40: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb0); + + /// address: 0x40006cb8 + /// Backup data register (BKP_DR) + pub const DR41 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D41: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb4); + + /// address: 0x40006cbc + /// Backup data register (BKP_DR) + pub const DR42 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Backup data + D42: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xb8); + + /// address: 0x40006c2c + /// RTC clock calibration register + /// (BKP_RTCCR) + pub const RTCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration value + CAL: u7, + /// Calibration Clock Output + CCO: u1, + /// Alarm or second output + /// enable + ASOE: u1, + /// Alarm or second output + /// selection + ASOS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x28); + + /// address: 0x40006c30 + /// Backup control register + /// (BKP_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tamper pin enable + TPE: u1, + /// Tamper pin active level + TPAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + + /// address: 0x40006c34 + /// BKP_CSR control/status register + /// (BKP_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clear Tamper event + CTE: u1, + /// Clear Tamper Interrupt + CTI: u1, + /// Tamper Pin interrupt + /// enable + TPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tamper Event Flag + TEF: u1, + /// Tamper Interrupt Flag + TIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x30); + }; + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register (IWDG_KR) + pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Key value + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register (IWDG_PR) + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register (IWDG_RLR) + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register (IWDG_SR) + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register (WWDG_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + /// (WWDG_CFR) + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit window value + W: u7, + /// Timer Base + WDGTB: u2, + /// Early Wakeup Interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register (WWDG_SR) + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Early Wakeup Interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// Advanced timer + pub const TIM1 = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40012c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40012c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40012c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40012c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40012c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40012c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40012c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40012c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40012c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40012c30 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40012c44 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + pub const TIM8 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40013410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40013418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001341c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40013424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40013428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001342c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40013434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40013438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001343c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40013440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40013448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001344c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40013430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40013444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + /// General purpose timer + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM5 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved2: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved4: u1, + reserved5: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40000c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40000c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40000c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40000c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40000c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40000c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General purpose timer + pub const TIM9 = struct { + pub const base_address = 0x40014c00; + + /// address: 0x40014c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40014c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40014c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40014c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40014c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40014c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40014c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40014c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + pub const TIM12 = struct { + pub const base_address = 0x40001800; + + /// address: 0x40001800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40001814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40001818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40001820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000182c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40001838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + /// General purpose timer + pub const TIM10 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4001500c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40015010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40015018 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40015020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40015024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40015028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001502c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM11 = struct { + pub const base_address = 0x40015400; + + /// address: 0x40015400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40015404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4001540c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40015410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40015414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40015418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40015418 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40015420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40015424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40015428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001542c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM13 = struct { + pub const base_address = 0x40001c00; + + /// address: 0x40001c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40001c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40001c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40001c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40001c18 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40001c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40001c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40001c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM14 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40002004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000200c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40002014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40002018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + reserved0: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40002018 + /// capture/compare mode register (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40002020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40002024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40002028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000202c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40002034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + /// Basic timer + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + /// Inter integrated circuit + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005410 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40003800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005810 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + /// Serial peripheral interface + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART1 = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40013808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40013818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + /// Analog to digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012400; + + /// address: 0x40012400 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012404 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + /// Dual mode selection + DUALMOD: u4, + reserved0: u1, + reserved1: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012408 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4001240c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012410 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012414 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012418 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001241c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012420 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012424 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012428 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001242c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012430 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012434 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012438 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001243c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012440 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012444 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012448 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001244c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + /// ADC2 data + ADC2DATA: u16, + }), base_address + 0x4c); + }; + /// Analog to digital converter + pub const ADC2 = struct { + pub const base_address = 0x40012800; + + /// address: 0x40012800 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012804 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012808 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4001280c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012810 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012814 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012818 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001281c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012820 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012824 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012828 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001282c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012830 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012834 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012838 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001283c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012840 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012844 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012848 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001284c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC3 = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Direct memory access mode + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + ALIGN: u1, + /// External event select for injected + /// group + JEXTSEL: u3, + /// External trigger conversion mode for + /// injected channels + JEXTTRIG: u1, + reserved6: u1, + /// External event select for regular + /// group + EXTSEL: u3, + /// External trigger conversion mode for + /// regular channels + EXTTRIG: u1, + /// Start conversion of injected + /// channels + JSWSTART: u1, + /// Start conversion of regular + /// channels + SWSTART: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 10 sample time + /// selection + SMP10: u3, + /// Channel 11 sample time + /// selection + SMP11: u3, + /// Channel 12 sample time + /// selection + SMP12: u3, + /// Channel 13 sample time + /// selection + SMP13: u3, + /// Channel 14 sample time + /// selection + SMP14: u3, + /// Channel 15 sample time + /// selection + SMP15: u3, + /// Channel 16 sample time + /// selection + SMP16: u3, + /// Channel 17 sample time + /// selection + SMP17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40013c10 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 0 sample time + /// selection + SMP0: u3, + /// Channel 1 sample time + /// selection + SMP1: u3, + /// Channel 2 sample time + /// selection + SMP2: u3, + /// Channel 3 sample time + /// selection + SMP3: u3, + /// Channel 4 sample time + /// selection + SMP4: u3, + /// Channel 5 sample time + /// selection + SMP5: u3, + /// Channel 6 sample time + /// selection + SMP6: u3, + /// Channel 7 sample time + /// selection + SMP7: u3, + /// Channel 8 sample time + /// selection + SMP8: u3, + /// Channel 9 sample time + /// selection + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40013c18 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x40013c1c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013c20 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40013c24 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40013c28 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x40013c2c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40013c30 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40013c34 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40013c38 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x40013c3c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40013c40 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40013c44 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40013c48 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40013c4c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// Controller area network + pub const CAN = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// CAN_MCR + pub const CAN_MCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// CAN_MSR + pub const CAN_MSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// CAN_TSR + pub const CAN_TSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// CAN_RF0R + pub const CAN_RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// CAN_RF1R + pub const CAN_RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// CAN_IER + pub const CAN_IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// CAN_ESR + pub const CAN_ESR = @intToPtr(*volatile Mmio(32, packed struct{ + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// CAN_BTR + pub const CAN_BTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// CAN_TI0R + pub const CAN_TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// CAN_TDT0R + pub const CAN_TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// CAN_TDL0R + pub const CAN_TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// CAN_TDH0R + pub const CAN_TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// CAN_TI1R + pub const CAN_TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// CAN_TDT1R + pub const CAN_TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// CAN_TDL1R + pub const CAN_TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// CAN_TDH1R + pub const CAN_TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// CAN_TI2R + pub const CAN_TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// CAN_TDT2R + pub const CAN_TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// CAN_TDL2R + pub const CAN_TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// CAN_TDH2R + pub const CAN_TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// CAN_RI0R + pub const CAN_RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// CAN_RDT0R + pub const CAN_RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// CAN_RDL0R + pub const CAN_RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// CAN_RDH0R + pub const CAN_RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// CAN_RI1R + pub const CAN_RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// CAN_RDT1R + pub const CAN_RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// CAN_RDL1R + pub const CAN_RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// CAN_RDH1R + pub const CAN_RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// CAN_FMR + pub const CAN_FMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// FINIT + FINIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// CAN_FM1R + pub const CAN_FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// CAN_FS1R + pub const CAN_FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// CAN_FFA1R + pub const CAN_FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// CAN_FA1R + pub const CAN_FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + }; + /// Digital to analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// Control register (DAC_CR) + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// DAC software trigger register + /// (DAC_SWTRIGR) + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// DAC channel1 12-bit right-aligned data + /// holding register(DAC_DHR12R1) + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// DAC channel1 12-bit left aligned data + /// holding register (DAC_DHR12L1) + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// DAC channel1 8-bit right aligned data + /// holding register (DAC_DHR8R1) + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// DAC channel2 12-bit right aligned data + /// holding register (DAC_DHR12R2) + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// DAC channel2 12-bit left aligned data + /// holding register (DAC_DHR12L2) + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// DAC channel2 8-bit right-aligned data + /// holding register (DAC_DHR8R2) + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + /// Reserved + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + /// Reserved + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register (DAC_DHR8RD), Bits 31:16 Reserved + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// DAC channel1 data output register + /// (DAC_DOR1) + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// DAC channel2 data output register + /// (DAC_DOR2) + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + }; + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// DBGMCU_IDCODE + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// DEV_ID + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// REV_ID + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// DBGMCU_CR + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + /// DBG_IWDG_STOP + DBG_IWDG_STOP: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_TIM1_STOP + DBG_TIM1_STOP: u1, + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3_STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_TIM8_STOP + DBG_TIM8_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x4); + }; + /// Universal asynchronous receiver + /// transmitter + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// UART4_SR + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// UART4_DR + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// UART4_BRR + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// UART4_CR1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// UART4_CR2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// UART4_CR3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + }; + /// Universal asynchronous receiver + /// transmitter + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// UART4_SR + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// PE + PE: u1, + /// FE + FE: u1, + /// NE + NE: u1, + /// ORE + ORE: u1, + /// IDLE + IDLE: u1, + /// RXNE + RXNE: u1, + /// TC + TC: u1, + /// TXE + TXE: u1, + /// LBD + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// UART4_DR + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// UART4_BRR + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// UART4_CR1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SBK + SBK: u1, + /// RWU + RWU: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// IDLEIE + IDLEIE: u1, + /// RXNEIE + RXNEIE: u1, + /// TCIE + TCIE: u1, + /// TXEIE + TXEIE: u1, + /// PEIE + PEIE: u1, + /// PS + PS: u1, + /// PCE + PCE: u1, + /// WAKE + WAKE: u1, + /// M + M: u1, + /// UE + UE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// UART4_CR2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADD + ADD: u4, + reserved0: u1, + /// LBDL + LBDL: u1, + /// LBDIE + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP + STOP: u2, + /// LINEN + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// UART4_CR3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA enable transmitter + DMAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + }; + /// CRC calculation unit + pub const CRC = struct { + pub const base_address = 0x40023000; -/// Serial peripheral interface -pub const SPI3 = extern struct { - pub const Address: u32 = 0x40003c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// Data frame format - DFF: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { + /// address: 0x40023000 /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); -/// Universal synchronous asynchronous receiver transmitter -pub const USART1 = extern struct { - pub const Address: u32 = 0x40013800; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); + /// address: 0x40023004 + /// Independent Data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Reset bit + RESET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// FLASH + pub const FLASH = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Latency + LATENCY: u3, + /// Flash half cycle access + /// enable + HLFCYA: u1, + /// Prefetch buffer enable + PRFTBE: u1, + /// Prefetch buffer status + PRFTBS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40022004 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// FPEC key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40022008 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte key + OPTKEY: u32, + }), base_address + 0x8); + + /// address: 0x4002200c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Busy + BSY: u1, + reserved0: u1, + /// Programming error + PGERR: u1, + reserved1: u1, + /// Write protection error + WRPRTERR: u1, + /// End of operation + EOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40022010 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Programming + PG: u1, + /// Page Erase + PER: u1, + /// Mass Erase + MER: u1, + reserved0: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved1: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved2: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// Flash address register + pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash Address + FAR: u32, + }), base_address + 0x14); + + /// address: 0x4002201c + /// Option byte register + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte error + OPTERR: u1, + /// Read protection + RDPRT: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// Write protection register + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protect + WRP: u32, + }), base_address + 0x20); + }; + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e000; + + /// address: 0xe000e004 + /// Interrupt Controller Type + /// Register + pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Total number of interrupt lines in + /// groups + INTLINESNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4); + + /// address: 0xe000ef00 + /// Software Triggered Interrupt + /// Register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// interrupt to be triggered + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xf00); + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x100); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x104); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x180); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x184); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x200); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x204); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x280); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x284); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x300); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x304); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x400); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x404); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x408); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x40c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x410); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x414); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x418); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x41c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x420); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x424); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x428); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x42c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x430); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x434); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x438); + }; + /// Universal serial bus full-speed device + /// interface + pub const USB = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// endpoint 0 register + pub const EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// endpoint 1 register + pub const EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// endpoint 2 register + pub const EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// endpoint 3 register + pub const EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// endpoint 4 register + pub const EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005c14 + /// endpoint 5 register + pub const EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// endpoint 6 register + pub const EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// endpoint 7 register + pub const EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c40 + /// control register + pub const CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start of frame interrupt + /// mask + ESOFM: u1, + /// Start of frame interrupt + /// mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt + /// mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun + /// interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt + /// mask + CTRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40005c44 + /// interrupt status register + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / + /// underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40005c48 + /// frame number register + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40005c4c + /// device address + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device address + ADD: u7, + /// Enable function + EF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4c); + + /// address: 0x40005c50 + /// Buffer table address + pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); + }; }; -/// Universal synchronous asynchronous receiver transmitter -pub const USART2 = extern struct { - pub const Address: u32 = 0x40004400; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +const std = @import("std"); -/// Universal synchronous asynchronous receiver transmitter -pub const USART3 = extern struct { - pub const Address: u32 = 0x40004800; - - /// Status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - /// CTS flag - CTS: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Data register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Data value - DR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved2: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000018, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} -/// Analog to digital converter -pub const ADC1 = extern struct { - pub const Address: u32 = 0x40012400; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - /// Dual mode selection - DUALMOD: u4 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - /// ADC2 data - ADC2DATA: u16 = 0, - }); -}; +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); -/// Analog to digital converter -pub const ADC2 = extern struct { - pub const Address: u32 = 0x40012800; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); -/// Analog to digital converter -pub const ADC3 = extern struct { - pub const Address: u32 = 0x40013c00; - - /// status register - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Analog watchdog flag - AWD: u1 = 0, - /// Regular channel end of conversion - EOC: u1 = 0, - /// Injected channel end of conversion - JEOC: u1 = 0, - /// Injected channel start flag - JSTRT: u1 = 0, - /// Regular channel start flag - STRT: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Analog watchdog channel select bits - AWDCH: u5 = 0, - /// Interrupt enable for EOC - EOCIE: u1 = 0, - /// Analog watchdog interrupt enable - AWDIE: u1 = 0, - /// Interrupt enable for injected channels - JEOCIE: u1 = 0, - /// Scan mode - SCAN: u1 = 0, - /// Enable the watchdog on a single channel in scan mode - AWDSGL: u1 = 0, - /// Automatic injected group conversion - JAUTO: u1 = 0, - /// Discontinuous mode on regular channels - DISCEN: u1 = 0, - /// Discontinuous mode on injected channels - JDISCEN: u1 = 0, - /// Discontinuous mode channel count - DISCNUM: u3 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog watchdog enable on injected channels - JAWDEN: u1 = 0, - /// Analog watchdog enable on regular channels - AWDEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000008, 32, packed struct { - /// A/D converter ON / OFF - ADON: u1 = 0, - /// Continuous conversion - CONT: u1 = 0, - /// A/D calibration - CAL: u1 = 0, - /// Reset calibration - RSTCAL: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Direct memory access mode - DMA: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Data alignment - ALIGN: u1 = 0, - /// External event select for injected group - JEXTSEL: u3 = 0, - /// External trigger conversion mode for injected channels - JEXTTRIG: u1 = 0, - reserved7: u1 = 0, - /// External event select for regular group - EXTSEL: u3 = 0, - /// External trigger conversion mode for regular channels - EXTTRIG: u1 = 0, - /// Start conversion of injected channels - JSWSTART: u1 = 0, - /// Start conversion of regular channels - SWSTART: u1 = 0, - /// Temperature sensor and VREFINT enable - TSVREFE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Channel 10 sample time selection - SMP10: u3 = 0, - /// Channel 11 sample time selection - SMP11: u3 = 0, - /// Channel 12 sample time selection - SMP12: u3 = 0, - /// Channel 13 sample time selection - SMP13: u3 = 0, - /// Channel 14 sample time selection - SMP14: u3 = 0, - /// Channel 15 sample time selection - SMP15: u3 = 0, - /// Channel 16 sample time selection - SMP16: u3 = 0, - /// Channel 17 sample time selection - SMP17: u3 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Channel 0 sample time selection - SMP0: u3 = 0, - /// Channel 1 sample time selection - SMP1: u3 = 0, - /// Channel 2 sample time selection - SMP2: u3 = 0, - /// Channel 3 sample time selection - SMP3: u3 = 0, - /// Channel 4 sample time selection - SMP4: u3 = 0, - /// Channel 5 sample time selection - SMP5: u3 = 0, - /// Channel 6 sample time selection - SMP6: u3 = 0, - /// Channel 7 sample time selection - SMP7: u3 = 0, - /// Channel 8 sample time selection - SMP8: u3 = 0, - /// Channel 9 sample time selection - SMP9: u3 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Data offset for injected channel x - JOFFSET1: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Data offset for injected channel x - JOFFSET2: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR3 = mmio(Address + 0x0000001c, 32, packed struct { - /// Data offset for injected channel x - JOFFSET3: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected channel data offset register x - pub const JOFR4 = mmio(Address + 0x00000020, 32, packed struct { - /// Data offset for injected channel x - JOFFSET4: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog higher threshold register - pub const HTR = mmio(Address + 0x00000024, 32, packed struct { - /// Analog watchdog higher threshold - HT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog lower threshold register - pub const LTR = mmio(Address + 0x00000028, 32, packed struct { - /// Analog watchdog lower threshold - LT: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// 13th conversion in regular sequence - SQ13: u5 = 0, - /// 14th conversion in regular sequence - SQ14: u5 = 0, - /// 15th conversion in regular sequence - SQ15: u5 = 0, - /// 16th conversion in regular sequence - SQ16: u5 = 0, - /// Regular channel sequence length - L: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000030, 32, packed struct { - /// 7th conversion in regular sequence - SQ7: u5 = 0, - /// 8th conversion in regular sequence - SQ8: u5 = 0, - /// 9th conversion in regular sequence - SQ9: u5 = 0, - /// 10th conversion in regular sequence - SQ10: u5 = 0, - /// 11th conversion in regular sequence - SQ11: u5 = 0, - /// 12th conversion in regular sequence - SQ12: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000034, 32, packed struct { - /// 1st conversion in regular sequence - SQ1: u5 = 0, - /// 2nd conversion in regular sequence - SQ2: u5 = 0, - /// 3rd conversion in regular sequence - SQ3: u5 = 0, - /// 4th conversion in regular sequence - SQ4: u5 = 0, - /// 5th conversion in regular sequence - SQ5: u5 = 0, - /// 6th conversion in regular sequence - SQ6: u5 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x00000038, 32, packed struct { - /// 1st conversion in injected sequence - JSQ1: u5 = 0, - /// 2nd conversion in injected sequence - JSQ2: u5 = 0, - /// 3rd conversion in injected sequence - JSQ3: u5 = 0, - /// 4th conversion in injected sequence - JSQ4: u5 = 0, - /// Injected sequence length - JL: u2 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR1 = mmio(Address + 0x0000003c, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR2 = mmio(Address + 0x00000040, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR3 = mmio(Address + 0x00000044, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register x - pub const JDR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Injected data - JDATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular data register - pub const DR = mmio(Address + 0x0000004c, 32, packed struct { - /// Regular data - DATA: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + const IntT = std.meta.Int(.unsigned, size); -/// Controller area network -pub const CAN = extern struct { - pub const Address: u32 = 0x40006400; - - /// CAN_MCR - pub const CAN_MCR = mmio(Address + 0x00000000, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_MSR - pub const CAN_MSR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_TSR - pub const CAN_TSR = mmio(Address + 0x00000008, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Lowest priority flag for mailbox 0 - TME0: u1 = 0, - /// Lowest priority flag for mailbox 1 - TME1: u1 = 0, - /// Lowest priority flag for mailbox 2 - TME2: u1 = 0, - /// Lowest priority flag for mailbox 0 - LOW0: u1 = 0, - /// Lowest priority flag for mailbox 1 - LOW1: u1 = 0, - /// Lowest priority flag for mailbox 2 - LOW2: u1 = 0, - }); - - /// CAN_RF0R - pub const CAN_RF0R = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_RF1R - pub const CAN_RF1R = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_IER - pub const CAN_IER = mmio(Address + 0x00000014, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_ESR - pub const CAN_ESR = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - }); - - /// CAN_BTR - pub const CAN_BTR = mmio(Address + 0x0000001c, 32, packed struct { - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved7: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - }); - - /// CAN_TI0R - pub const CAN_TI0R = mmio(Address + 0x00000180, 32, packed struct {}); - - /// CAN_TDT0R - pub const CAN_TDT0R = mmio(Address + 0x00000184, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL0R - pub const CAN_TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); - - /// CAN_TDH0R - pub const CAN_TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); - - /// CAN_TI1R - pub const CAN_TI1R = mmio(Address + 0x00000190, 32, packed struct {}); - - /// CAN_TDT1R - pub const CAN_TDT1R = mmio(Address + 0x00000194, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL1R - pub const CAN_TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); - - /// CAN_TDH1R - pub const CAN_TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); - - /// CAN_TI2R - pub const CAN_TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); - - /// CAN_TDT2R - pub const CAN_TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// CAN_TDL2R - pub const CAN_TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); - - /// CAN_TDH2R - pub const CAN_TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); - - /// CAN_RI0R - pub const CAN_RI0R = mmio(Address + 0x000001b0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// CAN_RDT0R - pub const CAN_RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// CAN_RDL0R - pub const CAN_RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); - - /// CAN_RDH0R - pub const CAN_RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); - - /// CAN_RI1R - pub const CAN_RI1R = mmio(Address + 0x000001c0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// CAN_RDT1R - pub const CAN_RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// CAN_RDL1R - pub const CAN_RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); - - /// CAN_RDH1R - pub const CAN_RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); - - /// CAN_FMR - pub const CAN_FMR = mmio(Address + 0x00000200, 32, packed struct { - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FM1R - pub const CAN_FM1R = mmio(Address + 0x00000204, 32, packed struct { - /// Filter mode - FBM0: u1 = 0, - /// Filter mode - FBM1: u1 = 0, - /// Filter mode - FBM2: u1 = 0, - /// Filter mode - FBM3: u1 = 0, - /// Filter mode - FBM4: u1 = 0, - /// Filter mode - FBM5: u1 = 0, - /// Filter mode - FBM6: u1 = 0, - /// Filter mode - FBM7: u1 = 0, - /// Filter mode - FBM8: u1 = 0, - /// Filter mode - FBM9: u1 = 0, - /// Filter mode - FBM10: u1 = 0, - /// Filter mode - FBM11: u1 = 0, - /// Filter mode - FBM12: u1 = 0, - /// Filter mode - FBM13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FS1R - pub const CAN_FS1R = mmio(Address + 0x0000020c, 32, packed struct { - /// Filter scale configuration - FSC0: u1 = 0, - /// Filter scale configuration - FSC1: u1 = 0, - /// Filter scale configuration - FSC2: u1 = 0, - /// Filter scale configuration - FSC3: u1 = 0, - /// Filter scale configuration - FSC4: u1 = 0, - /// Filter scale configuration - FSC5: u1 = 0, - /// Filter scale configuration - FSC6: u1 = 0, - /// Filter scale configuration - FSC7: u1 = 0, - /// Filter scale configuration - FSC8: u1 = 0, - /// Filter scale configuration - FSC9: u1 = 0, - /// Filter scale configuration - FSC10: u1 = 0, - /// Filter scale configuration - FSC11: u1 = 0, - /// Filter scale configuration - FSC12: u1 = 0, - /// Filter scale configuration - FSC13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FFA1R - pub const CAN_FFA1R = mmio(Address + 0x00000214, 32, packed struct { - /// Filter FIFO assignment for filter 0 - FFA0: u1 = 0, - /// Filter FIFO assignment for filter 1 - FFA1: u1 = 0, - /// Filter FIFO assignment for filter 2 - FFA2: u1 = 0, - /// Filter FIFO assignment for filter 3 - FFA3: u1 = 0, - /// Filter FIFO assignment for filter 4 - FFA4: u1 = 0, - /// Filter FIFO assignment for filter 5 - FFA5: u1 = 0, - /// Filter FIFO assignment for filter 6 - FFA6: u1 = 0, - /// Filter FIFO assignment for filter 7 - FFA7: u1 = 0, - /// Filter FIFO assignment for filter 8 - FFA8: u1 = 0, - /// Filter FIFO assignment for filter 9 - FFA9: u1 = 0, - /// Filter FIFO assignment for filter 10 - FFA10: u1 = 0, - /// Filter FIFO assignment for filter 11 - FFA11: u1 = 0, - /// Filter FIFO assignment for filter 12 - FFA12: u1 = 0, - /// Filter FIFO assignment for filter 13 - FFA13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN_FA1R - pub const CAN_FA1R = mmio(Address + 0x0000021c, 32, packed struct { - /// Filter active - FACT0: u1 = 0, - /// Filter active - FACT1: u1 = 0, - /// Filter active - FACT2: u1 = 0, - /// Filter active - FACT3: u1 = 0, - /// Filter active - FACT4: u1 = 0, - /// Filter active - FACT5: u1 = 0, - /// Filter active - FACT6: u1 = 0, - /// Filter active - FACT7: u1 = 0, - /// Filter active - FACT8: u1 = 0, - /// Filter active - FACT9: u1 = 0, - /// Filter active - FACT10: u1 = 0, - /// Filter active - FACT11: u1 = 0, - /// Filter active - FACT12: u1 = 0, - /// Filter active - FACT13: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Filter bank 0 register 1 - pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 0 register 2 - pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 1 - pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 2 - pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 1 - pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 2 - pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 1 - pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 2 - pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 2 - pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 1 - pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 2 - pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 1 - pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 2 - pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 1 - pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 2 - pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 1 - pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 2 - pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 1 - pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 2 - pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 1 - pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 2 - pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 1 - pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 2 - pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 12 register 2 - pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 1 - pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 2 - pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); -}; + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); -/// Digital to analog converter -pub const DAC = extern struct { - pub const Address: u32 = 0x40007400; - - /// Control register (DAC_CR) - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// DAC channel1 enable - EN1: u1 = 0, - /// DAC channel1 output buffer disable - BOFF1: u1 = 0, - /// DAC channel1 trigger enable - TEN1: u1 = 0, - /// DAC channel1 trigger selection - TSEL1: u3 = 0, - /// DAC channel1 noise/triangle wave generation enable - WAVE1: u2 = 0, - /// DAC channel1 mask/amplitude selector - MAMP1: u4 = 0, - /// DAC channel1 DMA enable - DMAEN1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 enable - EN2: u1 = 0, - /// DAC channel2 output buffer disable - BOFF2: u1 = 0, - /// DAC channel2 trigger enable - TEN2: u1 = 0, - /// DAC channel2 trigger selection - TSEL2: u3 = 0, - /// DAC channel2 noise/triangle wave generation enable - WAVE2: u2 = 0, - /// DAC channel2 mask/amplitude selector - MAMP2: u4 = 0, - /// DAC channel2 DMA enable - DMAEN2: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC software trigger register (DAC_SWTRIGR) - pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - /// DAC channel1 software trigger - SWTRIG1: u1 = 0, - /// DAC channel2 software trigger - SWTRIG2: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) - pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) - pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) - pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) - pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) - pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) - pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits - /// 31:28 Reserved, Bits 15:12 Reserved - pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 - /// Reserved, Bits 3:0 Reserved - pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - }); - - /// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 - /// Reserved - pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel1 data output register (DAC_DOR1) - pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DAC channel2 data output register (DAC_DOR2) - pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + return extern struct { + const Self = @This(); -/// Debug support -pub const DBG = extern struct { - pub const Address: u32 = 0xe0042000; - - /// DBGMCU_IDCODE - pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// DBGMCU_CR - pub const CR = mmio(Address + 0x00000004, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + raw: IntT, -/// Universal asynchronous receiver transmitter -pub const UART4 = extern struct { - pub const Address: u32 = 0x40004c00; - - /// UART4_SR - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise error flag - NE: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// IDLE line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBD: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_DR - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_BRR - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Send break - SBK: u1 = 0, - /// Receiver wakeup - RWU: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// TXE interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// USART enable - UE: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - /// Address of the USART node - ADD: u4 = 0, - reserved1: u1 = 0, - /// lin break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub const underlying_type = PackedT; -/// Universal asynchronous receiver transmitter -pub const UART5 = extern struct { - pub const Address: u32 = 0x40005000; - - /// UART4_SR - pub const SR = mmio(Address + 0x00000000, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_DR - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_BRR - pub const BRR = mmio(Address + 0x00000008, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR1 - pub const CR1 = mmio(Address + 0x0000000c, 32, packed struct { - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR2 - pub const CR2 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// UART4_CR3 - pub const CR3 = mmio(Address + 0x00000014, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } -/// CRC calculation unit -pub const CRC = extern struct { - pub const Address: u32 = 0x40023000; + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } - /// Data register - pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } - /// Independent Data register - pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - /// Independent Data register - IDR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// Reset bit - RESET: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} -/// FLASH -pub const FLASH = extern struct { - pub const Address: u32 = 0x40022000; - - /// Flash access control register - pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - /// Latency - LATENCY: u3 = 0, - /// Flash half cycle access enable - HLFCYA: u1 = 0, - /// Prefetch buffer enable - PRFTBE: u1 = 0, - /// Prefetch buffer status - PRFTBS: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash key register - pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - /// FPEC key - KEY: u32 = 0, - }); - - /// Flash option key register - pub const OPTKEYR = mmio(Address + 0x00000008, 32, packed struct { - /// Option byte key - OPTKEY: u32 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Busy - BSY: u1 = 0, - reserved1: u1 = 0, - /// Programming error - PGERR: u1 = 0, - reserved2: u1 = 0, - /// Write protection error - WRPRTERR: u1 = 0, - /// End of operation - EOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000010, 32, packed struct { - /// Programming - PG: u1 = 0, - /// Page Erase - PER: u1 = 0, - /// Mass Erase - MER: u1 = 0, - reserved1: u1 = 0, - /// Option byte programming - OPTPG: u1 = 0, - /// Option byte erase - OPTER: u1 = 0, - /// Start - STRT: u1 = 0, - /// Lock - LOCK: u1 = 0, - reserved2: u1 = 0, - /// Option bytes write enable - OPTWRE: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - reserved3: u1 = 0, - /// End of operation interrupt enable - EOPIE: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash address register - pub const AR = mmio(Address + 0x00000014, 32, packed struct { - /// Flash Address - FAR: u32 = 0, - }); - - /// Option byte register - pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - /// Option byte error - OPTERR: u1 = 0, - /// Read protection - RDPRT: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Write protection register - pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - /// Write protect - WRP: u32 = 0, - }); -}; +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); -/// Nested Vectored Interrupt Controller -pub const NVIC = extern struct { - pub const Address: u32 = 0xe000e000; - - /// Interrupt Controller Type Register - pub const ICTR = mmio(Address + 0x00000004, 32, packed struct { - /// Total number of interrupt lines in groups - INTLINESNUM: u4 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000100, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000104, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000180, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000184, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000200, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000204, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000280, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000284, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000300, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000304, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000400, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000404, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000408, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000040c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000410, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000414, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000418, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000041c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000420, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000424, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000428, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000042c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000430, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000434, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000438, 32, packed struct {}); - - /// Software Triggered Interrupt Register - pub const STIR = mmio(Address + 0x00000f00, 32, packed struct { - /// interrupt to be triggered - INTID: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + raw: std.meta.Int(.unsigned, size), -/// Universal serial bus full-speed device interface -pub const USB = extern struct { - pub const Address: u32 = 0x40005c00; - - /// endpoint 0 register - pub const EP0R = mmio(Address + 0x00000000, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 1 register - pub const EP1R = mmio(Address + 0x00000004, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 2 register - pub const EP2R = mmio(Address + 0x00000008, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 3 register - pub const EP3R = mmio(Address + 0x0000000c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 4 register - pub const EP4R = mmio(Address + 0x00000010, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 5 register - pub const EP5R = mmio(Address + 0x00000014, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 6 register - pub const EP6R = mmio(Address + 0x00000018, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 7 register - pub const EP7R = mmio(Address + 0x0000001c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CNTR = mmio(Address + 0x00000040, 32, packed struct { - /// Force USB Reset - FRES: u1 = 0, - /// Power down - PDWN: u1 = 0, - /// Low-power mode - LPMODE: u1 = 0, - /// Force suspend - FSUSP: u1 = 0, - /// Resume request - RESUME: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start of frame interrupt mask - ESOFM: u1 = 0, - /// Start of frame interrupt mask - SOFM: u1 = 0, - /// USB reset interrupt mask - RESETM: u1 = 0, - /// Suspend mode interrupt mask - SUSPM: u1 = 0, - /// Wakeup interrupt mask - WKUPM: u1 = 0, - /// Error interrupt mask - ERRM: u1 = 0, - /// Packet memory area over / underrun interrupt mask - PMAOVRM: u1 = 0, - /// Correct transfer interrupt mask - CTRM: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - /// Endpoint Identifier - EP_ID: u4 = 0, - /// Direction of transaction - DIR: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start frame - ESOF: u1 = 0, - /// start of frame - SOF: u1 = 0, - /// reset request - RESET: u1 = 0, - /// Suspend mode request - SUSP: u1 = 0, - /// Wakeup - WKUP: u1 = 0, - /// Error - ERR: u1 = 0, - /// Packet memory area over / underrun - PMAOVR: u1 = 0, - /// Correct transfer - CTR: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// frame number register - pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - /// Frame number - FN: u11 = 0, - /// Lost SOF - LSOF: u2 = 0, - /// Locked - LCK: u1 = 0, - /// Receive data - line status - RXDM: u1 = 0, - /// Receive data + line status - RXDP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// device address - pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - /// Device address - ADD: u7 = 0, - /// Enable function - EF: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Buffer table address - pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Buffer table - BTABLE: u13 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); -const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } }; } -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - - /// Window Watchdog interrupt - WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt - PVD: InterruptVector = makeUnhandledHandler("PVD"), - /// Tamper interrupt - TAMPER: InterruptVector = makeUnhandledHandler("TAMPER"), - /// RTC global interrupt - RTC: InterruptVector = makeUnhandledHandler("RTC"), - /// Flash global interrupt - FLASH: InterruptVector = makeUnhandledHandler("FLASH"), - /// RCC global interrupt - RCC: InterruptVector = makeUnhandledHandler("RCC"), - /// EXTI Line0 interrupt - EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), - /// EXTI Line1 interrupt - EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 interrupt - EXTI2: InterruptVector = makeUnhandledHandler("EXTI2"), - /// EXTI Line3 interrupt - EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), - /// EXTI Line4 interrupt - EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), - /// DMA1 Channel1 global interrupt - DMA1_Channel1: InterruptVector = makeUnhandledHandler("DMA1_Channel1"), - /// DMA1 Channel2 global interrupt - DMA1_Channel2: InterruptVector = makeUnhandledHandler("DMA1_Channel2"), - /// DMA1 Channel3 global interrupt - DMA1_Channel3: InterruptVector = makeUnhandledHandler("DMA1_Channel3"), - /// DMA1 Channel4 global interrupt - DMA1_Channel4: InterruptVector = makeUnhandledHandler("DMA1_Channel4"), - /// DMA1 Channel5 global interrupt - DMA1_Channel5: InterruptVector = makeUnhandledHandler("DMA1_Channel5"), - /// DMA1 Channel6 global interrupt - DMA1_Channel6: InterruptVector = makeUnhandledHandler("DMA1_Channel6"), - /// DMA1 Channel7 global interrupt - DMA1_Channel7: InterruptVector = makeUnhandledHandler("DMA1_Channel7"), - /// ADC1 global interrupt; ADC2 global interrupt - ADC: InterruptVector = makeUnhandledHandler("ADC"), - /// CAN1 TX interrupts - CAN1_TX: InterruptVector = makeUnhandledHandler("CAN1_TX"), - /// CAN1 RX0 interrupts - CAN1_RX0: InterruptVector = makeUnhandledHandler("CAN1_RX0"), - /// CAN1 RX1 interrupt - CAN1_RX1: InterruptVector = makeUnhandledHandler("CAN1_RX1"), - /// CAN1 SCE interrupt - CAN1_SCE: InterruptVector = makeUnhandledHandler("CAN1_SCE"), - /// EXTI Line[9:5] interrupts - EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break interrupt and TIM9 global interrupt - TIM1_BRK_TIM9: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM9"), - /// TIM1 Update interrupt and TIM10 global interrupt - TIM1_UP_TIM10: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM10"), - /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt - TIM1_TRG_COM_TIM11: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM11"), - /// TIM1 Capture Compare interrupt - TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), - /// TIM2 global interrupt - TIM2: InterruptVector = makeUnhandledHandler("TIM2"), - /// TIM3 global interrupt - TIM3: InterruptVector = makeUnhandledHandler("TIM3"), - /// TIM4 global interrupt - TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt - I2C1_EV: InterruptVector = makeUnhandledHandler("I2C1_EV"), - /// I2C1 error interrupt - I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt - I2C2_EV: InterruptVector = makeUnhandledHandler("I2C2_EV"), - /// I2C2 error interrupt - I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), - /// SPI1 global interrupt - SPI1: InterruptVector = makeUnhandledHandler("SPI1"), - /// SPI2 global interrupt - SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt - USART1: InterruptVector = makeUnhandledHandler("USART1"), - /// USART2 global interrupt - USART2: InterruptVector = makeUnhandledHandler("USART2"), - /// USART3 global interrupt - USART3: InterruptVector = makeUnhandledHandler("USART3"), - /// EXTI Line[15:10] interrupts - EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), - /// RTC Alarms through EXTI line interrupt - RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), - /// USB Device FS Wakeup through EXTI line interrupt - USB_FS_WKUP: InterruptVector = makeUnhandledHandler("USB_FS_WKUP"), - /// TIM8 Break interrupt and TIM12 global interrupt - TIM8_BRK_TIM12: InterruptVector = makeUnhandledHandler("TIM8_BRK_TIM12"), - /// TIM8 Update interrupt and TIM13 global interrupt - TIM8_UP_TIM13: InterruptVector = makeUnhandledHandler("TIM8_UP_TIM13"), - /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt - TIM8_TRG_COM_TIM14: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM_TIM14"), - /// TIM8 Capture Compare interrupt - TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), - /// ADC3 global interrupt - ADC3: InterruptVector = makeUnhandledHandler("ADC3"), - /// FSMC global interrupt - FSMC: InterruptVector = makeUnhandledHandler("FSMC"), - /// SDIO global interrupt - SDIO: InterruptVector = makeUnhandledHandler("SDIO"), - /// TIM5 global interrupt - TIM5: InterruptVector = makeUnhandledHandler("TIM5"), - /// SPI3 global interrupt - SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global interrupt - UART4: InterruptVector = makeUnhandledHandler("UART4"), - /// UART5 global interrupt - UART5: InterruptVector = makeUnhandledHandler("UART5"), - /// TIM6 global interrupt - TIM6: InterruptVector = makeUnhandledHandler("TIM6"), - /// TIM7 global interrupt - TIM7: InterruptVector = makeUnhandledHandler("TIM7"), - /// DMA2 Channel1 global interrupt - DMA2_Channel1: InterruptVector = makeUnhandledHandler("DMA2_Channel1"), - /// DMA2 Channel2 global interrupt - DMA2_Channel2: InterruptVector = makeUnhandledHandler("DMA2_Channel2"), - /// DMA2 Channel3 global interrupt - DMA2_Channel3: InterruptVector = makeUnhandledHandler("DMA2_Channel3"), - /// DMA2 Channel4 and DMA2 Channel5 global interrupt - DMA2_Channel4_5: InterruptVector = makeUnhandledHandler("DMA2_Channel4_5"), -}; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); } -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig index f9865cd..e2d554e 100644 --- a/src/modules/chips/stm32f103/stm32f103.zig +++ b/src/modules/chips/stm32f103/stm32f103.zig @@ -1,3 +1,2 @@ pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; +pub usingnamespace @import("registers.zig"); diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index 88c3635..f5a994a 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -1,29546 +1,34412 @@ -// generated using svd2zig.py -// DO NOT EDIT -// based on STM32F303 version 1.4 -const microzig_mmio = @import("microzig-mmio"); -const mmio = microzig_mmio.mmio; -const MMIO = microzig_mmio.MMIO; -const Name = "STM32F303"; - -/// General-purpose I/Os -pub const GPIOA = extern struct { - pub const Address: u32 = 0x48000000; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OT0: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT1: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT2: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT3: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT4: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT5: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT6: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT7: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT8: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT9: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT10: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT11: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT12: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT13: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT14: u1 = 0, - /// Port x configuration bits (y = 0..15) - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOB = extern struct { - pub const Address: u32 = 0x48000400; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOC = extern struct { - pub const Address: u32 = 0x48000800; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOD = extern struct { - pub const Address: u32 = 0x48000c00; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOE = extern struct { - pub const Address: u32 = 0x48001000; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOF = extern struct { - pub const Address: u32 = 0x48001400; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOG = extern struct { - pub const Address: u32 = 0x48001800; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose I/Os -pub const GPIOH = extern struct { - pub const Address: u32 = 0x48001c00; - - /// GPIO port mode register - pub const MODER = mmio(Address + 0x00000000, 32, packed struct { - /// Port x configuration bits (y = 0..15) - MODER0: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER1: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER2: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER3: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER4: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER5: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER6: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER7: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER8: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER9: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER10: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER11: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER12: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER13: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER14: u2 = 0, - /// Port x configuration bits (y = 0..15) - MODER15: u2 = 0, - }); - - /// GPIO port output type register - pub const OTYPER = mmio(Address + 0x00000004, 32, packed struct { - /// Port x configuration bit 0 - OT0: u1 = 0, - /// Port x configuration bit 1 - OT1: u1 = 0, - /// Port x configuration bit 2 - OT2: u1 = 0, - /// Port x configuration bit 3 - OT3: u1 = 0, - /// Port x configuration bit 4 - OT4: u1 = 0, - /// Port x configuration bit 5 - OT5: u1 = 0, - /// Port x configuration bit 6 - OT6: u1 = 0, - /// Port x configuration bit 7 - OT7: u1 = 0, - /// Port x configuration bit 8 - OT8: u1 = 0, - /// Port x configuration bit 9 - OT9: u1 = 0, - /// Port x configuration bit 10 - OT10: u1 = 0, - /// Port x configuration bit 11 - OT11: u1 = 0, - /// Port x configuration bit 12 - OT12: u1 = 0, - /// Port x configuration bit 13 - OT13: u1 = 0, - /// Port x configuration bit 14 - OT14: u1 = 0, - /// Port x configuration bit 15 - OT15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output speed register - pub const OSPEEDR = mmio(Address + 0x00000008, 32, packed struct { - /// Port x configuration bits (y = 0..15) - OSPEEDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - OSPEEDR15: u2 = 0, - }); - - /// GPIO port pull-up/pull-down register - pub const PUPDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Port x configuration bits (y = 0..15) - PUPDR0: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR1: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR2: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR3: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR4: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR5: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR6: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR7: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR8: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR9: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR10: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR11: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR12: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR13: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR14: u2 = 0, - /// Port x configuration bits (y = 0..15) - PUPDR15: u2 = 0, - }); - - /// GPIO port input data register - pub const IDR = mmio(Address + 0x00000010, 32, packed struct { - /// Port input data (y = 0..15) - IDR0: u1 = 0, - /// Port input data (y = 0..15) - IDR1: u1 = 0, - /// Port input data (y = 0..15) - IDR2: u1 = 0, - /// Port input data (y = 0..15) - IDR3: u1 = 0, - /// Port input data (y = 0..15) - IDR4: u1 = 0, - /// Port input data (y = 0..15) - IDR5: u1 = 0, - /// Port input data (y = 0..15) - IDR6: u1 = 0, - /// Port input data (y = 0..15) - IDR7: u1 = 0, - /// Port input data (y = 0..15) - IDR8: u1 = 0, - /// Port input data (y = 0..15) - IDR9: u1 = 0, - /// Port input data (y = 0..15) - IDR10: u1 = 0, - /// Port input data (y = 0..15) - IDR11: u1 = 0, - /// Port input data (y = 0..15) - IDR12: u1 = 0, - /// Port input data (y = 0..15) - IDR13: u1 = 0, - /// Port input data (y = 0..15) - IDR14: u1 = 0, - /// Port input data (y = 0..15) - IDR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port output data register - pub const ODR = mmio(Address + 0x00000014, 32, packed struct { - /// Port output data (y = 0..15) - ODR0: u1 = 0, - /// Port output data (y = 0..15) - ODR1: u1 = 0, - /// Port output data (y = 0..15) - ODR2: u1 = 0, - /// Port output data (y = 0..15) - ODR3: u1 = 0, - /// Port output data (y = 0..15) - ODR4: u1 = 0, - /// Port output data (y = 0..15) - ODR5: u1 = 0, - /// Port output data (y = 0..15) - ODR6: u1 = 0, - /// Port output data (y = 0..15) - ODR7: u1 = 0, - /// Port output data (y = 0..15) - ODR8: u1 = 0, - /// Port output data (y = 0..15) - ODR9: u1 = 0, - /// Port output data (y = 0..15) - ODR10: u1 = 0, - /// Port output data (y = 0..15) - ODR11: u1 = 0, - /// Port output data (y = 0..15) - ODR12: u1 = 0, - /// Port output data (y = 0..15) - ODR13: u1 = 0, - /// Port output data (y = 0..15) - ODR14: u1 = 0, - /// Port output data (y = 0..15) - ODR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO port bit set/reset register - pub const BSRR = mmio(Address + 0x00000018, 32, packed struct { - /// Port x set bit y (y= 0..15) - BS0: u1 = 0, - /// Port x set bit y (y= 0..15) - BS1: u1 = 0, - /// Port x set bit y (y= 0..15) - BS2: u1 = 0, - /// Port x set bit y (y= 0..15) - BS3: u1 = 0, - /// Port x set bit y (y= 0..15) - BS4: u1 = 0, - /// Port x set bit y (y= 0..15) - BS5: u1 = 0, - /// Port x set bit y (y= 0..15) - BS6: u1 = 0, - /// Port x set bit y (y= 0..15) - BS7: u1 = 0, - /// Port x set bit y (y= 0..15) - BS8: u1 = 0, - /// Port x set bit y (y= 0..15) - BS9: u1 = 0, - /// Port x set bit y (y= 0..15) - BS10: u1 = 0, - /// Port x set bit y (y= 0..15) - BS11: u1 = 0, - /// Port x set bit y (y= 0..15) - BS12: u1 = 0, - /// Port x set bit y (y= 0..15) - BS13: u1 = 0, - /// Port x set bit y (y= 0..15) - BS14: u1 = 0, - /// Port x set bit y (y= 0..15) - BS15: u1 = 0, - /// Port x set bit y (y= 0..15) - BR0: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR1: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR2: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR3: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR4: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR5: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR6: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR7: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR8: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR9: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR10: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR11: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR12: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR13: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR14: u1 = 0, - /// Port x reset bit y (y = 0..15) - BR15: u1 = 0, - }); - - /// GPIO port configuration lock register - pub const LCKR = mmio(Address + 0x0000001c, 32, packed struct { - /// Port x lock bit y (y= 0..15) - LCK0: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK1: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK2: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK3: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK4: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK5: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK6: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK7: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK8: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK9: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK10: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK11: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK12: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK13: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK14: u1 = 0, - /// Port x lock bit y (y= 0..15) - LCK15: u1 = 0, - /// Lok Key - LCKK: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// GPIO alternate function low register - pub const AFRL = mmio(Address + 0x00000020, 32, packed struct { - /// Alternate function selection for port x bit y (y = 0..7) - AFRL0: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL1: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL2: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL3: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL4: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL5: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL6: u4 = 0, - /// Alternate function selection for port x bit y (y = 0..7) - AFRL7: u4 = 0, - }); - - /// GPIO alternate function high register - pub const AFRH = mmio(Address + 0x00000024, 32, packed struct { - /// Alternate function selection for port x bit y (y = 8..15) - AFRH8: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH9: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH10: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH11: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH12: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH13: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH14: u4 = 0, - /// Alternate function selection for port x bit y (y = 8..15) - AFRH15: u4 = 0, - }); - - /// Port bit reset register - pub const BRR = mmio(Address + 0x00000028, 32, packed struct { - /// Port x Reset bit y - BR0: u1 = 0, - /// Port x Reset bit y - BR1: u1 = 0, - /// Port x Reset bit y - BR2: u1 = 0, - /// Port x Reset bit y - BR3: u1 = 0, - /// Port x Reset bit y - BR4: u1 = 0, - /// Port x Reset bit y - BR5: u1 = 0, - /// Port x Reset bit y - BR6: u1 = 0, - /// Port x Reset bit y - BR7: u1 = 0, - /// Port x Reset bit y - BR8: u1 = 0, - /// Port x Reset bit y - BR9: u1 = 0, - /// Port x Reset bit y - BR10: u1 = 0, - /// Port x Reset bit y - BR11: u1 = 0, - /// Port x Reset bit y - BR12: u1 = 0, - /// Port x Reset bit y - BR13: u1 = 0, - /// Port x Reset bit y - BR14: u1 = 0, - /// Port x Reset bit y - BR15: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Touch sensing controller -pub const TSC = extern struct { - pub const Address: u32 = 0x40024000; - - /// control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Touch sensing controller enable - TSCE: u1 = 0, - /// Start a new acquisition - START: u1 = 0, - /// Acquisition mode - AM: u1 = 0, - /// Synchronization pin polarity - SYNCPOL: u1 = 0, - /// I/O Default mode - IODEF: u1 = 0, - /// Max count value - MCV: u3 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// pulse generator prescaler - PGPSC: u3 = 0, - /// Spread spectrum prescaler - SSPSC: u1 = 0, - /// Spread spectrum enable - SSE: u1 = 0, - /// Spread spectrum deviation - SSD: u7 = 0, - /// Charge transfer pulse low - CTPL: u4 = 0, - /// Charge transfer pulse high - CTPH: u4 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - /// End of acquisition interrupt enable - EOAIE: u1 = 0, - /// Max count error interrupt enable - MCEIE: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt clear register - pub const ICR = mmio(Address + 0x00000008, 32, packed struct { - /// End of acquisition interrupt clear - EOAIC: u1 = 0, - /// Max count error interrupt clear - MCEIC: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - /// End of acquisition flag - EOAF: u1 = 0, - /// Max count error flag - MCEF: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O hysteresis control register - pub const IOHCR = mmio(Address + 0x00000010, 32, packed struct { - /// G1_IO1 Schmitt trigger hysteresis mode - G1_IO1: u1 = 0, - /// G1_IO2 Schmitt trigger hysteresis mode - G1_IO2: u1 = 0, - /// G1_IO3 Schmitt trigger hysteresis mode - G1_IO3: u1 = 0, - /// G1_IO4 Schmitt trigger hysteresis mode - G1_IO4: u1 = 0, - /// G2_IO1 Schmitt trigger hysteresis mode - G2_IO1: u1 = 0, - /// G2_IO2 Schmitt trigger hysteresis mode - G2_IO2: u1 = 0, - /// G2_IO3 Schmitt trigger hysteresis mode - G2_IO3: u1 = 0, - /// G2_IO4 Schmitt trigger hysteresis mode - G2_IO4: u1 = 0, - /// G3_IO1 Schmitt trigger hysteresis mode - G3_IO1: u1 = 0, - /// G3_IO2 Schmitt trigger hysteresis mode - G3_IO2: u1 = 0, - /// G3_IO3 Schmitt trigger hysteresis mode - G3_IO3: u1 = 0, - /// G3_IO4 Schmitt trigger hysteresis mode - G3_IO4: u1 = 0, - /// G4_IO1 Schmitt trigger hysteresis mode - G4_IO1: u1 = 0, - /// G4_IO2 Schmitt trigger hysteresis mode - G4_IO2: u1 = 0, - /// G4_IO3 Schmitt trigger hysteresis mode - G4_IO3: u1 = 0, - /// G4_IO4 Schmitt trigger hysteresis mode - G4_IO4: u1 = 0, - /// G5_IO1 Schmitt trigger hysteresis mode - G5_IO1: u1 = 0, - /// G5_IO2 Schmitt trigger hysteresis mode - G5_IO2: u1 = 0, - /// G5_IO3 Schmitt trigger hysteresis mode - G5_IO3: u1 = 0, - /// G5_IO4 Schmitt trigger hysteresis mode - G5_IO4: u1 = 0, - /// G6_IO1 Schmitt trigger hysteresis mode - G6_IO1: u1 = 0, - /// G6_IO2 Schmitt trigger hysteresis mode - G6_IO2: u1 = 0, - /// G6_IO3 Schmitt trigger hysteresis mode - G6_IO3: u1 = 0, - /// G6_IO4 Schmitt trigger hysteresis mode - G6_IO4: u1 = 0, - /// G7_IO1 Schmitt trigger hysteresis mode - G7_IO1: u1 = 0, - /// G7_IO2 Schmitt trigger hysteresis mode - G7_IO2: u1 = 0, - /// G7_IO3 Schmitt trigger hysteresis mode - G7_IO3: u1 = 0, - /// G7_IO4 Schmitt trigger hysteresis mode - G7_IO4: u1 = 0, - /// G8_IO1 Schmitt trigger hysteresis mode - G8_IO1: u1 = 0, - /// G8_IO2 Schmitt trigger hysteresis mode - G8_IO2: u1 = 0, - /// G8_IO3 Schmitt trigger hysteresis mode - G8_IO3: u1 = 0, - /// G8_IO4 Schmitt trigger hysteresis mode - G8_IO4: u1 = 0, - }); - - /// I/O analog switch control register - pub const IOASCR = mmio(Address + 0x00000018, 32, packed struct { - /// G1_IO1 analog switch enable - G1_IO1: u1 = 0, - /// G1_IO2 analog switch enable - G1_IO2: u1 = 0, - /// G1_IO3 analog switch enable - G1_IO3: u1 = 0, - /// G1_IO4 analog switch enable - G1_IO4: u1 = 0, - /// G2_IO1 analog switch enable - G2_IO1: u1 = 0, - /// G2_IO2 analog switch enable - G2_IO2: u1 = 0, - /// G2_IO3 analog switch enable - G2_IO3: u1 = 0, - /// G2_IO4 analog switch enable - G2_IO4: u1 = 0, - /// G3_IO1 analog switch enable - G3_IO1: u1 = 0, - /// G3_IO2 analog switch enable - G3_IO2: u1 = 0, - /// G3_IO3 analog switch enable - G3_IO3: u1 = 0, - /// G3_IO4 analog switch enable - G3_IO4: u1 = 0, - /// G4_IO1 analog switch enable - G4_IO1: u1 = 0, - /// G4_IO2 analog switch enable - G4_IO2: u1 = 0, - /// G4_IO3 analog switch enable - G4_IO3: u1 = 0, - /// G4_IO4 analog switch enable - G4_IO4: u1 = 0, - /// G5_IO1 analog switch enable - G5_IO1: u1 = 0, - /// G5_IO2 analog switch enable - G5_IO2: u1 = 0, - /// G5_IO3 analog switch enable - G5_IO3: u1 = 0, - /// G5_IO4 analog switch enable - G5_IO4: u1 = 0, - /// G6_IO1 analog switch enable - G6_IO1: u1 = 0, - /// G6_IO2 analog switch enable - G6_IO2: u1 = 0, - /// G6_IO3 analog switch enable - G6_IO3: u1 = 0, - /// G6_IO4 analog switch enable - G6_IO4: u1 = 0, - /// G7_IO1 analog switch enable - G7_IO1: u1 = 0, - /// G7_IO2 analog switch enable - G7_IO2: u1 = 0, - /// G7_IO3 analog switch enable - G7_IO3: u1 = 0, - /// G7_IO4 analog switch enable - G7_IO4: u1 = 0, - /// G8_IO1 analog switch enable - G8_IO1: u1 = 0, - /// G8_IO2 analog switch enable - G8_IO2: u1 = 0, - /// G8_IO3 analog switch enable - G8_IO3: u1 = 0, - /// G8_IO4 analog switch enable - G8_IO4: u1 = 0, - }); - - /// I/O sampling control register - pub const IOSCR = mmio(Address + 0x00000020, 32, packed struct { - /// G1_IO1 sampling mode - G1_IO1: u1 = 0, - /// G1_IO2 sampling mode - G1_IO2: u1 = 0, - /// G1_IO3 sampling mode - G1_IO3: u1 = 0, - /// G1_IO4 sampling mode - G1_IO4: u1 = 0, - /// G2_IO1 sampling mode - G2_IO1: u1 = 0, - /// G2_IO2 sampling mode - G2_IO2: u1 = 0, - /// G2_IO3 sampling mode - G2_IO3: u1 = 0, - /// G2_IO4 sampling mode - G2_IO4: u1 = 0, - /// G3_IO1 sampling mode - G3_IO1: u1 = 0, - /// G3_IO2 sampling mode - G3_IO2: u1 = 0, - /// G3_IO3 sampling mode - G3_IO3: u1 = 0, - /// G3_IO4 sampling mode - G3_IO4: u1 = 0, - /// G4_IO1 sampling mode - G4_IO1: u1 = 0, - /// G4_IO2 sampling mode - G4_IO2: u1 = 0, - /// G4_IO3 sampling mode - G4_IO3: u1 = 0, - /// G4_IO4 sampling mode - G4_IO4: u1 = 0, - /// G5_IO1 sampling mode - G5_IO1: u1 = 0, - /// G5_IO2 sampling mode - G5_IO2: u1 = 0, - /// G5_IO3 sampling mode - G5_IO3: u1 = 0, - /// G5_IO4 sampling mode - G5_IO4: u1 = 0, - /// G6_IO1 sampling mode - G6_IO1: u1 = 0, - /// G6_IO2 sampling mode - G6_IO2: u1 = 0, - /// G6_IO3 sampling mode - G6_IO3: u1 = 0, - /// G6_IO4 sampling mode - G6_IO4: u1 = 0, - /// G7_IO1 sampling mode - G7_IO1: u1 = 0, - /// G7_IO2 sampling mode - G7_IO2: u1 = 0, - /// G7_IO3 sampling mode - G7_IO3: u1 = 0, - /// G7_IO4 sampling mode - G7_IO4: u1 = 0, - /// G8_IO1 sampling mode - G8_IO1: u1 = 0, - /// G8_IO2 sampling mode - G8_IO2: u1 = 0, - /// G8_IO3 sampling mode - G8_IO3: u1 = 0, - /// G8_IO4 sampling mode - G8_IO4: u1 = 0, - }); - - /// I/O channel control register - pub const IOCCR = mmio(Address + 0x00000028, 32, packed struct { - /// G1_IO1 channel mode - G1_IO1: u1 = 0, - /// G1_IO2 channel mode - G1_IO2: u1 = 0, - /// G1_IO3 channel mode - G1_IO3: u1 = 0, - /// G1_IO4 channel mode - G1_IO4: u1 = 0, - /// G2_IO1 channel mode - G2_IO1: u1 = 0, - /// G2_IO2 channel mode - G2_IO2: u1 = 0, - /// G2_IO3 channel mode - G2_IO3: u1 = 0, - /// G2_IO4 channel mode - G2_IO4: u1 = 0, - /// G3_IO1 channel mode - G3_IO1: u1 = 0, - /// G3_IO2 channel mode - G3_IO2: u1 = 0, - /// G3_IO3 channel mode - G3_IO3: u1 = 0, - /// G3_IO4 channel mode - G3_IO4: u1 = 0, - /// G4_IO1 channel mode - G4_IO1: u1 = 0, - /// G4_IO2 channel mode - G4_IO2: u1 = 0, - /// G4_IO3 channel mode - G4_IO3: u1 = 0, - /// G4_IO4 channel mode - G4_IO4: u1 = 0, - /// G5_IO1 channel mode - G5_IO1: u1 = 0, - /// G5_IO2 channel mode - G5_IO2: u1 = 0, - /// G5_IO3 channel mode - G5_IO3: u1 = 0, - /// G5_IO4 channel mode - G5_IO4: u1 = 0, - /// G6_IO1 channel mode - G6_IO1: u1 = 0, - /// G6_IO2 channel mode - G6_IO2: u1 = 0, - /// G6_IO3 channel mode - G6_IO3: u1 = 0, - /// G6_IO4 channel mode - G6_IO4: u1 = 0, - /// G7_IO1 channel mode - G7_IO1: u1 = 0, - /// G7_IO2 channel mode - G7_IO2: u1 = 0, - /// G7_IO3 channel mode - G7_IO3: u1 = 0, - /// G7_IO4 channel mode - G7_IO4: u1 = 0, - /// G8_IO1 channel mode - G8_IO1: u1 = 0, - /// G8_IO2 channel mode - G8_IO2: u1 = 0, - /// G8_IO3 channel mode - G8_IO3: u1 = 0, - /// G8_IO4 channel mode - G8_IO4: u1 = 0, - }); - - /// I/O group control status register - pub const IOGCSR = mmio(Address + 0x00000030, 32, packed struct { - /// Analog I/O group x enable - G1E: u1 = 0, - /// Analog I/O group x enable - G2E: u1 = 0, - /// Analog I/O group x enable - G3E: u1 = 0, - /// Analog I/O group x enable - G4E: u1 = 0, - /// Analog I/O group x enable - G5E: u1 = 0, - /// Analog I/O group x enable - G6E: u1 = 0, - /// Analog I/O group x enable - G7E: u1 = 0, - /// Analog I/O group x enable - G8E: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Analog I/O group x status - G1S: u1 = 0, - /// Analog I/O group x status - G2S: u1 = 0, - /// Analog I/O group x status - G3S: u1 = 0, - /// Analog I/O group x status - G4S: u1 = 0, - /// Analog I/O group x status - G5S: u1 = 0, - /// Analog I/O group x status - G6S: u1 = 0, - /// Analog I/O group x status - G7S: u1 = 0, - /// Analog I/O group x status - G8S: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG1CR = mmio(Address + 0x00000034, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG2CR = mmio(Address + 0x00000038, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG3CR = mmio(Address + 0x0000003c, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG4CR = mmio(Address + 0x00000040, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG5CR = mmio(Address + 0x00000044, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG6CR = mmio(Address + 0x00000048, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG7CR = mmio(Address + 0x0000004c, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I/O group x counter register - pub const IOG8CR = mmio(Address + 0x00000050, 32, packed struct { - /// Counter value - CNT: u14 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// cyclic redundancy check calculation unit -pub const CRC = extern struct { - pub const Address: u32 = 0x40023000; - - /// Data register - pub const DR = @intToPtr(*volatile u32, Address + 0x00000000); - - /// Independent data register - pub const IDR = mmio(Address + 0x00000004, 32, packed struct { - /// General-purpose 8-bit data register bits - IDR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// reset bit - RESET: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Polynomial size - POLYSIZE: u2 = 0, - /// Reverse input data - REV_IN: u2 = 0, - /// Reverse output data - REV_OUT: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Initial CRC value - pub const INIT = @intToPtr(*volatile u32, Address + 0x00000010); - - /// CRC polynomial - pub const POL = @intToPtr(*volatile u32, Address + 0x00000014); -}; - -/// Flash -pub const Flash = extern struct { - pub const Address: u32 = 0x40022000; - - /// Flash access control register - pub const ACR = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash key register - pub const KEYR = mmio(Address + 0x00000004, 32, packed struct { - /// Flash Key - FKEYR: u32 = 0, - }); - - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile u32, Address + 0x00000008); - - /// Flash status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Busy - BSY: u1 = 0, - reserved1: u1 = 0, - /// Programming error - PGERR: u1 = 0, - reserved2: u1 = 0, - /// Write protection error - WRPRT: u1 = 0, - /// End of operation - EOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash control register - pub const CR = mmio(Address + 0x00000010, 32, packed struct { - /// Programming - PG: u1 = 0, - /// Page erase - PER: u1 = 0, - /// Mass erase - MER: u1 = 0, - reserved1: u1 = 0, - /// Option byte programming - OPTPG: u1 = 0, - /// Option byte erase - OPTER: u1 = 0, - /// Start - STRT: u1 = 0, - /// Lock - LOCK: u1 = 0, - reserved2: u1 = 0, - /// Option bytes write enable - OPTWRE: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - reserved3: u1 = 0, - /// End of operation interrupt enable - EOPIE: u1 = 0, - /// Force option byte loading - FORCE_OPTLOAD: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Flash address register - pub const AR = mmio(Address + 0x00000014, 32, packed struct { - /// Flash address - FAR: u32 = 0, - }); - - /// Option byte register - pub const OBR = mmio(Address + 0x0000001c, 32, packed struct { - /// Option byte error - OPTERR: u1 = 0, - /// Level 1 protection status - LEVEL1_PROT: u1 = 0, - /// Level 2 protection status - LEVEL2_PROT: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - }); - - /// Write protection register - pub const WRPR = mmio(Address + 0x00000020, 32, packed struct { - /// Write protect - WRP: u32 = 0, - }); -}; - -/// Reset and clock control -pub const RCC = extern struct { - pub const Address: u32 = 0x40021000; - - /// Clock control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Internal High Speed clock enable - HSION: u1 = 0, - /// Internal High Speed clock ready flag - HSIRDY: u1 = 0, - reserved1: u1 = 0, - /// Internal High Speed clock trimming - HSITRIM: u5 = 0, - /// Internal High Speed clock Calibration - HSICAL: u8 = 0, - /// External High Speed clock enable - HSEON: u1 = 0, - /// External High Speed clock ready flag - HSERDY: u1 = 0, - /// External High Speed clock Bypass - HSEBYP: u1 = 0, - /// Clock Security System enable - CSSON: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// PLL enable - PLLON: u1 = 0, - /// PLL clock ready flag - PLLRDY: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register (RCC_CFGR) - pub const CFGR = mmio(Address + 0x00000004, 32, packed struct { - /// System clock Switch - SW: u2 = 0, - /// System Clock Switch Status - SWS: u2 = 0, - /// AHB prescaler - HPRE: u4 = 0, - /// APB Low speed prescaler (APB1) - PPRE1: u3 = 0, - /// APB high speed prescaler (APB2) - PPRE2: u3 = 0, - reserved1: u1 = 0, - /// PLL entry clock source - PLLSRC: u2 = 0, - /// HSE divider for PLL entry - PLLXTPRE: u1 = 0, - /// PLL Multiplication Factor - PLLMUL: u4 = 0, - /// USB prescaler - USBPRES: u1 = 0, - /// I2S external clock source selection - I2SSRC: u1 = 0, - /// Microcontroller clock output - MCO: u3 = 0, - reserved2: u1 = 0, - /// Microcontroller Clock Output Flag - MCOF: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock interrupt register (RCC_CIR) - pub const CIR = mmio(Address + 0x00000008, 32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1 = 0, - /// LSE Ready Interrupt flag - LSERDYF: u1 = 0, - /// HSI Ready Interrupt flag - HSIRDYF: u1 = 0, - /// HSE Ready Interrupt flag - HSERDYF: u1 = 0, - /// PLL Ready Interrupt flag - PLLRDYF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock Security System Interrupt flag - CSSF: u1 = 0, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1 = 0, - /// LSE Ready Interrupt Enable - LSERDYIE: u1 = 0, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1 = 0, - /// HSE Ready Interrupt Enable - HSERDYIE: u1 = 0, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// LSI Ready Interrupt Clear - LSIRDYC: u1 = 0, - /// LSE Ready Interrupt Clear - LSERDYC: u1 = 0, - /// HSI Ready Interrupt Clear - HSIRDYC: u1 = 0, - /// HSE Ready Interrupt Clear - HSERDYC: u1 = 0, - /// PLL Ready Interrupt Clear - PLLRDYC: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Clock security system interrupt clear - CSSC: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral reset register (RCC_APB2RSTR) - pub const APB2RSTR = mmio(Address + 0x0000000c, 32, packed struct { - /// SYSCFG and COMP reset - SYSCFGRST: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM1 timer reset - TIM1RST: u1 = 0, - /// SPI 1 reset - SPI1RST: u1 = 0, - /// TIM8 timer reset - TIM8RST: u1 = 0, - /// USART1 reset - USART1RST: u1 = 0, - reserved11: u1 = 0, - /// TIM15 timer reset - TIM15RST: u1 = 0, - /// TIM16 timer reset - TIM16RST: u1 = 0, - /// TIM17 timer reset - TIM17RST: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral reset register (RCC_APB1RSTR) - pub const APB1RSTR = mmio(Address + 0x00000010, 32, packed struct { - /// Timer 2 reset - TIM2RST: u1 = 0, - /// Timer 3 reset - TIM3RST: u1 = 0, - /// Timer 14 reset - TIM4RST: u1 = 0, - reserved1: u1 = 0, - /// Timer 6 reset - TIM6RST: u1 = 0, - /// Timer 7 reset - TIM7RST: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Window watchdog reset - WWDGRST: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// SPI2 reset - SPI2RST: u1 = 0, - /// SPI3 reset - SPI3RST: u1 = 0, - reserved9: u1 = 0, - /// USART 2 reset - USART2RST: u1 = 0, - /// USART3 reset - USART3RST: u1 = 0, - /// UART 4 reset - UART4RST: u1 = 0, - /// UART 5 reset - UART5RST: u1 = 0, - /// I2C1 reset - I2C1RST: u1 = 0, - /// I2C2 reset - I2C2RST: u1 = 0, - /// USB reset - USBRST: u1 = 0, - reserved10: u1 = 0, - /// CAN reset - CANRST: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// Power interface reset - PWRRST: u1 = 0, - /// DAC interface reset - DACRST: u1 = 0, - /// I2C3 reset - I2C3RST: u1 = 0, - padding1: u1 = 0, - }); - - /// AHB Peripheral Clock enable register (RCC_AHBENR) - pub const AHBENR = mmio(Address + 0x00000014, 32, packed struct { - /// DMA1 clock enable - DMAEN: u1 = 0, - /// DMA2 clock enable - DMA2EN: u1 = 0, - /// SRAM interface clock enable - SRAMEN: u1 = 0, - reserved1: u1 = 0, - /// FLITF clock enable - FLITFEN: u1 = 0, - /// FMC clock enable - FMCEN: u1 = 0, - /// CRC clock enable - CRCEN: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// IO port H clock enable - IOPHEN: u1 = 0, - /// I/O port A clock enable - IOPAEN: u1 = 0, - /// I/O port B clock enable - IOPBEN: u1 = 0, - /// I/O port C clock enable - IOPCEN: u1 = 0, - /// I/O port D clock enable - IOPDEN: u1 = 0, - /// I/O port E clock enable - IOPEEN: u1 = 0, - /// I/O port F clock enable - IOPFEN: u1 = 0, - /// I/O port G clock enable - IOPGEN: u1 = 0, - /// Touch sensing controller clock enable - TSCEN: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - /// ADC1 and ADC2 clock enable - ADC12EN: u1 = 0, - /// ADC3 and ADC4 clock enable - ADC34EN: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB2 peripheral clock enable register (RCC_APB2ENR) - pub const APB2ENR = mmio(Address + 0x00000018, 32, packed struct { - /// SYSCFG clock enable - SYSCFGEN: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// TIM1 Timer clock enable - TIM1EN: u1 = 0, - /// SPI 1 clock enable - SPI1EN: u1 = 0, - /// TIM8 Timer clock enable - TIM8EN: u1 = 0, - /// USART1 clock enable - USART1EN: u1 = 0, - reserved11: u1 = 0, - /// TIM15 timer clock enable - TIM15EN: u1 = 0, - /// TIM16 timer clock enable - TIM16EN: u1 = 0, - /// TIM17 timer clock enable - TIM17EN: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB1 peripheral clock enable register (RCC_APB1ENR) - pub const APB1ENR = mmio(Address + 0x0000001c, 32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1 = 0, - /// Timer 3 clock enable - TIM3EN: u1 = 0, - /// Timer 4 clock enable - TIM4EN: u1 = 0, - reserved1: u1 = 0, - /// Timer 6 clock enable - TIM6EN: u1 = 0, - /// Timer 7 clock enable - TIM7EN: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Window watchdog clock enable - WWDGEN: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// SPI 2 clock enable - SPI2EN: u1 = 0, - /// SPI 3 clock enable - SPI3EN: u1 = 0, - reserved9: u1 = 0, - /// USART 2 clock enable - USART2EN: u1 = 0, - /// USART 3 clock enable - USART3EN: u1 = 0, - /// USART 4 clock enable - USART4EN: u1 = 0, - /// USART 5 clock enable - USART5EN: u1 = 0, - /// I2C 1 clock enable - I2C1EN: u1 = 0, - /// I2C 2 clock enable - I2C2EN: u1 = 0, - /// USB clock enable - USBEN: u1 = 0, - reserved10: u1 = 0, - /// CAN clock enable - CANEN: u1 = 0, - /// DAC2 interface clock enable - DAC2EN: u1 = 0, - reserved11: u1 = 0, - /// Power interface clock enable - PWREN: u1 = 0, - /// DAC interface clock enable - DACEN: u1 = 0, - /// I2C3 clock enable - I2C3EN: u1 = 0, - padding1: u1 = 0, - }); - - /// Backup domain control register (RCC_BDCR) - pub const BDCR = mmio(Address + 0x00000020, 32, packed struct { - /// External Low Speed oscillator enable - LSEON: u1 = 0, - /// External Low Speed oscillator ready - LSERDY: u1 = 0, - /// External Low Speed oscillator bypass - LSEBYP: u1 = 0, - /// LSE oscillator drive capability - LSEDRV: u2 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// RTC clock source selection - RTCSEL: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// RTC clock enable - RTCEN: u1 = 0, - /// Backup domain software reset - BDRST: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control/status register (RCC_CSR) - pub const CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Internal low speed oscillator enable - LSION: u1 = 0, - /// Internal low speed oscillator ready - LSIRDY: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Remove reset flag - RMVF: u1 = 0, - /// Option byte loader reset flag - OBLRSTF: u1 = 0, - /// PIN reset flag - PINRSTF: u1 = 0, - /// POR/PDR reset flag - PORRSTF: u1 = 0, - /// Software reset flag - SFTRSTF: u1 = 0, - /// Independent watchdog reset flag - IWDGRSTF: u1 = 0, - /// Window watchdog reset flag - WWDGRSTF: u1 = 0, - /// Low-power reset flag - LPWRRSTF: u1 = 0, - }); - - /// AHB peripheral reset register - pub const AHBRSTR = mmio(Address + 0x00000028, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// FMC reset - FMCRST: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// I/O port H reset - IOPHRST: u1 = 0, - /// I/O port A reset - IOPARST: u1 = 0, - /// I/O port B reset - IOPBRST: u1 = 0, - /// I/O port C reset - IOPCRST: u1 = 0, - /// I/O port D reset - IOPDRST: u1 = 0, - /// I/O port E reset - IOPERST: u1 = 0, - /// I/O port F reset - IOPFRST: u1 = 0, - /// Touch sensing controller reset - IOPGRST: u1 = 0, - /// Touch sensing controller reset - TSCRST: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - /// ADC1 and ADC2 reset - ADC12RST: u1 = 0, - /// ADC3 and ADC4 reset - ADC34RST: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register 2 - pub const CFGR2 = mmio(Address + 0x0000002c, 32, packed struct { - /// PREDIV division factor - PREDIV: u4 = 0, - /// ADC1 and ADC2 prescaler - ADC12PRES: u5 = 0, - /// ADC3 and ADC4 prescaler - ADC34PRES: u5 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Clock configuration register 3 - pub const CFGR3 = mmio(Address + 0x00000030, 32, packed struct { - /// USART1 clock source selection - USART1SW: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// I2C1 clock source selection - I2C1SW: u1 = 0, - /// I2C2 clock source selection - I2C2SW: u1 = 0, - /// I2C3 clock source selection - I2C3SW: u1 = 0, - reserved3: u1 = 0, - /// Timer1 clock source selection - TIM1SW: u1 = 0, - /// Timer8 clock source selection - TIM8SW: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// USART2 clock source selection - USART2SW: u2 = 0, - /// USART3 clock source selection - USART3SW: u2 = 0, - /// UART4 clock source selection - UART4SW: u2 = 0, - /// UART5 clock source selection - UART5SW: u2 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// DMA controller 1 -pub const DMA1 = extern struct { - pub const Address: u32 = 0x40020000; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// DMA controller 1 -pub const DMA2 = extern struct { - pub const Address: u32 = 0x40020400; - - /// DMA interrupt status register (DMA_ISR) - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - /// Channel 1 Global interrupt flag - GIF1: u1 = 0, - /// Channel 1 Transfer Complete flag - TCIF1: u1 = 0, - /// Channel 1 Half Transfer Complete flag - HTIF1: u1 = 0, - /// Channel 1 Transfer Error flag - TEIF1: u1 = 0, - /// Channel 2 Global interrupt flag - GIF2: u1 = 0, - /// Channel 2 Transfer Complete flag - TCIF2: u1 = 0, - /// Channel 2 Half Transfer Complete flag - HTIF2: u1 = 0, - /// Channel 2 Transfer Error flag - TEIF2: u1 = 0, - /// Channel 3 Global interrupt flag - GIF3: u1 = 0, - /// Channel 3 Transfer Complete flag - TCIF3: u1 = 0, - /// Channel 3 Half Transfer Complete flag - HTIF3: u1 = 0, - /// Channel 3 Transfer Error flag - TEIF3: u1 = 0, - /// Channel 4 Global interrupt flag - GIF4: u1 = 0, - /// Channel 4 Transfer Complete flag - TCIF4: u1 = 0, - /// Channel 4 Half Transfer Complete flag - HTIF4: u1 = 0, - /// Channel 4 Transfer Error flag - TEIF4: u1 = 0, - /// Channel 5 Global interrupt flag - GIF5: u1 = 0, - /// Channel 5 Transfer Complete flag - TCIF5: u1 = 0, - /// Channel 5 Half Transfer Complete flag - HTIF5: u1 = 0, - /// Channel 5 Transfer Error flag - TEIF5: u1 = 0, - /// Channel 6 Global interrupt flag - GIF6: u1 = 0, - /// Channel 6 Transfer Complete flag - TCIF6: u1 = 0, - /// Channel 6 Half Transfer Complete flag - HTIF6: u1 = 0, - /// Channel 6 Transfer Error flag - TEIF6: u1 = 0, - /// Channel 7 Global interrupt flag - GIF7: u1 = 0, - /// Channel 7 Transfer Complete flag - TCIF7: u1 = 0, - /// Channel 7 Half Transfer Complete flag - HTIF7: u1 = 0, - /// Channel 7 Transfer Error flag - TEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA interrupt flag clear register (DMA_IFCR) - pub const IFCR = mmio(Address + 0x00000004, 32, packed struct { - /// Channel 1 Global interrupt clear - CGIF1: u1 = 0, - /// Channel 1 Transfer Complete clear - CTCIF1: u1 = 0, - /// Channel 1 Half Transfer clear - CHTIF1: u1 = 0, - /// Channel 1 Transfer Error clear - CTEIF1: u1 = 0, - /// Channel 2 Global interrupt clear - CGIF2: u1 = 0, - /// Channel 2 Transfer Complete clear - CTCIF2: u1 = 0, - /// Channel 2 Half Transfer clear - CHTIF2: u1 = 0, - /// Channel 2 Transfer Error clear - CTEIF2: u1 = 0, - /// Channel 3 Global interrupt clear - CGIF3: u1 = 0, - /// Channel 3 Transfer Complete clear - CTCIF3: u1 = 0, - /// Channel 3 Half Transfer clear - CHTIF3: u1 = 0, - /// Channel 3 Transfer Error clear - CTEIF3: u1 = 0, - /// Channel 4 Global interrupt clear - CGIF4: u1 = 0, - /// Channel 4 Transfer Complete clear - CTCIF4: u1 = 0, - /// Channel 4 Half Transfer clear - CHTIF4: u1 = 0, - /// Channel 4 Transfer Error clear - CTEIF4: u1 = 0, - /// Channel 5 Global interrupt clear - CGIF5: u1 = 0, - /// Channel 5 Transfer Complete clear - CTCIF5: u1 = 0, - /// Channel 5 Half Transfer clear - CHTIF5: u1 = 0, - /// Channel 5 Transfer Error clear - CTEIF5: u1 = 0, - /// Channel 6 Global interrupt clear - CGIF6: u1 = 0, - /// Channel 6 Transfer Complete clear - CTCIF6: u1 = 0, - /// Channel 6 Half Transfer clear - CHTIF6: u1 = 0, - /// Channel 6 Transfer Error clear - CTEIF6: u1 = 0, - /// Channel 7 Global interrupt clear - CGIF7: u1 = 0, - /// Channel 7 Transfer Complete clear - CTCIF7: u1 = 0, - /// Channel 7 Half Transfer clear - CHTIF7: u1 = 0, - /// Channel 7 Transfer Error clear - CTEIF7: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 number of data register - pub const CNDTR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 1 peripheral address register - pub const CPAR1 = mmio(Address + 0x00000010, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 1 memory address register - pub const CMAR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 number of data register - pub const CNDTR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 2 peripheral address register - pub const CPAR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 2 memory address register - pub const CMAR2 = mmio(Address + 0x00000028, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR3 = mmio(Address + 0x00000030, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 number of data register - pub const CNDTR3 = mmio(Address + 0x00000034, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 3 peripheral address register - pub const CPAR3 = mmio(Address + 0x00000038, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 3 memory address register - pub const CMAR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR4 = mmio(Address + 0x00000044, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 number of data register - pub const CNDTR4 = mmio(Address + 0x00000048, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 4 peripheral address register - pub const CPAR4 = mmio(Address + 0x0000004c, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 4 memory address register - pub const CMAR4 = mmio(Address + 0x00000050, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 number of data register - pub const CNDTR5 = mmio(Address + 0x0000005c, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 5 peripheral address register - pub const CPAR5 = mmio(Address + 0x00000060, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 5 memory address register - pub const CMAR5 = mmio(Address + 0x00000064, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR6 = mmio(Address + 0x0000006c, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 number of data register - pub const CNDTR6 = mmio(Address + 0x00000070, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 6 peripheral address register - pub const CPAR6 = mmio(Address + 0x00000074, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 6 memory address register - pub const CMAR6 = mmio(Address + 0x00000078, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); - - /// DMA channel configuration register (DMA_CCR) - pub const CCR7 = mmio(Address + 0x00000080, 32, packed struct { - /// Channel enable - EN: u1 = 0, - /// Transfer complete interrupt enable - TCIE: u1 = 0, - /// Half Transfer interrupt enable - HTIE: u1 = 0, - /// Transfer error interrupt enable - TEIE: u1 = 0, - /// Data transfer direction - DIR: u1 = 0, - /// Circular mode - CIRC: u1 = 0, - /// Peripheral increment mode - PINC: u1 = 0, - /// Memory increment mode - MINC: u1 = 0, - /// Peripheral size - PSIZE: u2 = 0, - /// Memory size - MSIZE: u2 = 0, - /// Channel Priority level - PL: u2 = 0, - /// Memory to memory mode - MEM2MEM: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 number of data register - pub const CNDTR7 = mmio(Address + 0x00000084, 32, packed struct { - /// Number of data to transfer - NDT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA channel 7 peripheral address register - pub const CPAR7 = mmio(Address + 0x00000088, 32, packed struct { - /// Peripheral address - PA: u32 = 0, - }); - - /// DMA channel 7 memory address register - pub const CMAR7 = mmio(Address + 0x0000008c, 32, packed struct { - /// Memory address - MA: u32 = 0, - }); -}; - -/// General purpose timer -pub const TIM2 = extern struct { - pub const Address: u32 = 0x40000000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM3 = extern struct { - pub const Address: u32 = 0x40000400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timer -pub const TIM4 = extern struct { - pub const Address: u32 = 0x40000800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - reserved2: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - reserved3: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - reserved1: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - reserved1: u1 = 0, - /// Trigger generation - TG: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output compare 1 fast enable - OC1FE: u1 = 0, - /// Output compare 1 preload enable - OC1PE: u1 = 0, - /// Output compare 1 mode - OC1M: u3 = 0, - /// Output compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output compare 2 fast enable - OC2FE: u1 = 0, - /// Output compare 2 preload enable - OC2PE: u1 = 0, - /// Output compare 2 mode - OC2M: u3 = 0, - /// Output compare 2 clear enable - OC2CE: u1 = 0, - /// Output compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - O24CE: u1 = 0, - /// Output compare 3 mode bit3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 4 mode bit3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4NP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNTL: u16 = 0, - /// High counter value - CNTH: u15 = 0, - /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARRL: u16 = 0, - /// High Auto-reload value - ARRH: u16 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Low Capture/Compare 1 value - CCR1L: u16 = 0, - /// High Capture/Compare 1 value (on TIM2) - CCR1H: u16 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Low Capture/Compare 2 value - CCR2L: u16 = 0, - /// High Capture/Compare 2 value (on TIM2) - CCR2H: u16 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Low Capture/Compare value - CCR3L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR3H: u16 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Low Capture/Compare value - CCR4L: u16 = 0, - /// High Capture/Compare value (on TIM2) - CCR4H: u16 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General purpose timers -pub const TIM15 = extern struct { - pub const Address: u32 = 0x40014000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - reserved1: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Slave mode selection bit 3 - SMS_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved3: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - reserved2: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PSC: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// General-purpose-timers -pub const TIM16 = extern struct { - pub const Address: u32 = 0x40014400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 1 mode - OC1M_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option register - pub const OR = @intToPtr(*volatile u32, Address + 0x00000050); -}; - -/// General purpose timer -pub const TIM17 = extern struct { - pub const Address: u32 = 0x40014800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - reserved4: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 1 mode - OC1M_3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PSC: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART1 = extern struct { - pub const Address: u32 = 0x40013800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART2 = extern struct { - pub const Address: u32 = 0x40004400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const USART3 = extern struct { - pub const Address: u32 = 0x40004800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const UART4 = extern struct { - pub const Address: u32 = 0x40004c00; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Universal synchronous asynchronous receiver transmitter -pub const UART5 = extern struct { - pub const Address: u32 = 0x40005000; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// USART enable - UE: u1 = 0, - /// USART enable in Stop mode - UESM: u1 = 0, - /// Receiver enable - RE: u1 = 0, - /// Transmitter enable - TE: u1 = 0, - /// IDLE interrupt enable - IDLEIE: u1 = 0, - /// RXNE interrupt enable - RXNEIE: u1 = 0, - /// Transmission complete interrupt enable - TCIE: u1 = 0, - /// interrupt enable - TXEIE: u1 = 0, - /// PE interrupt enable - PEIE: u1 = 0, - /// Parity selection - PS: u1 = 0, - /// Parity control enable - PCE: u1 = 0, - /// Receiver wakeup method - WAKE: u1 = 0, - /// Word length - M: u1 = 0, - /// Mute mode enable - MME: u1 = 0, - /// Character match interrupt enable - CMIE: u1 = 0, - /// Oversampling mode - OVER8: u1 = 0, - /// Driver Enable deassertion time - DEDT: u5 = 0, - /// Driver Enable assertion time - DEAT: u5 = 0, - /// Receiver timeout interrupt enable - RTOIE: u1 = 0, - /// End of Block interrupt enable - EOBIE: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// 7-bit Address Detection/4-bit Address Detection - ADDM7: u1 = 0, - /// LIN break detection length - LBDL: u1 = 0, - /// LIN break detection interrupt enable - LBDIE: u1 = 0, - reserved5: u1 = 0, - /// Last bit clock pulse - LBCL: u1 = 0, - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Clock enable - CLKEN: u1 = 0, - /// STOP bits - STOP: u2 = 0, - /// LIN mode enable - LINEN: u1 = 0, - /// Swap TX/RX pins - SWAP: u1 = 0, - /// RX pin active level inversion - RXINV: u1 = 0, - /// TX pin active level inversion - TXINV: u1 = 0, - /// Binary data inversion - DATAINV: u1 = 0, - /// Most significant bit first - MSBFIRST: u1 = 0, - /// Auto baud rate enable - ABREN: u1 = 0, - /// Auto baud rate mode - ABRMOD: u2 = 0, - /// Receiver timeout enable - RTOEN: u1 = 0, - /// Address of the USART node - ADD0: u4 = 0, - /// Address of the USART node - ADD4: u4 = 0, - }); - - /// Control register 3 - pub const CR3 = mmio(Address + 0x00000008, 32, packed struct { - /// Error interrupt enable - EIE: u1 = 0, - /// IrDA mode enable - IREN: u1 = 0, - /// IrDA low-power - IRLP: u1 = 0, - /// Half-duplex selection - HDSEL: u1 = 0, - /// Smartcard NACK enable - NACK: u1 = 0, - /// Smartcard mode enable - SCEN: u1 = 0, - /// DMA enable receiver - DMAR: u1 = 0, - /// DMA enable transmitter - DMAT: u1 = 0, - /// RTS enable - RTSE: u1 = 0, - /// CTS enable - CTSE: u1 = 0, - /// CTS interrupt enable - CTSIE: u1 = 0, - /// One sample bit method enable - ONEBIT: u1 = 0, - /// Overrun Disable - OVRDIS: u1 = 0, - /// DMA Disable on Reception Error - DDRE: u1 = 0, - /// Driver enable mode - DEM: u1 = 0, - /// Driver enable polarity selection - DEP: u1 = 0, - reserved1: u1 = 0, - /// Smartcard auto-retry count - SCARCNT: u3 = 0, - /// Wakeup from Stop mode interrupt flag selection - WUS: u2 = 0, - /// Wakeup from Stop mode interrupt enable - WUFIE: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Baud rate register - pub const BRR = mmio(Address + 0x0000000c, 32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4 = 0, - /// mantissa of USARTDIV - DIV_Mantissa: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Guard time and prescaler register - pub const GTPR = mmio(Address + 0x00000010, 32, packed struct { - /// Prescaler value - PSC: u8 = 0, - /// Guard time value - GT: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receiver timeout register - pub const RTOR = mmio(Address + 0x00000014, 32, packed struct { - /// Receiver timeout value - RTO: u24 = 0, - /// Block Length - BLEN: u8 = 0, - }); - - /// Request register - pub const RQR = mmio(Address + 0x00000018, 32, packed struct { - /// Auto baud rate request - ABRRQ: u1 = 0, - /// Send break request - SBKRQ: u1 = 0, - /// Mute mode request - MMRQ: u1 = 0, - /// Receive data flush request - RXFRQ: u1 = 0, - /// Transmit data flush request - TXFRQ: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt & status register - pub const ISR = mmio(Address + 0x0000001c, 32, packed struct { - /// Parity error - PE: u1 = 0, - /// Framing error - FE: u1 = 0, - /// Noise detected flag - NF: u1 = 0, - /// Overrun error - ORE: u1 = 0, - /// Idle line detected - IDLE: u1 = 0, - /// Read data register not empty - RXNE: u1 = 0, - /// Transmission complete - TC: u1 = 0, - /// Transmit data register empty - TXE: u1 = 0, - /// LIN break detection flag - LBDF: u1 = 0, - /// CTS interrupt flag - CTSIF: u1 = 0, - /// CTS flag - CTS: u1 = 0, - /// Receiver timeout - RTOF: u1 = 0, - /// End of block flag - EOBF: u1 = 0, - reserved1: u1 = 0, - /// Auto baud rate error - ABRE: u1 = 0, - /// Auto baud rate flag - ABRF: u1 = 0, - /// Busy flag - BUSY: u1 = 0, - /// character match flag - CMF: u1 = 0, - /// Send break flag - SBKF: u1 = 0, - /// Receiver wakeup from Mute mode - RWU: u1 = 0, - /// Wakeup from Stop mode flag - WUF: u1 = 0, - /// Transmit enable acknowledge flag - TEACK: u1 = 0, - /// Receive enable acknowledge flag - REACK: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt flag clear register - pub const ICR = mmio(Address + 0x00000020, 32, packed struct { - /// Parity error clear flag - PECF: u1 = 0, - /// Framing error clear flag - FECF: u1 = 0, - /// Noise detected clear flag - NCF: u1 = 0, - /// Overrun error clear flag - ORECF: u1 = 0, - /// Idle line detected clear flag - IDLECF: u1 = 0, - reserved1: u1 = 0, - /// Transmission complete clear flag - TCCF: u1 = 0, - reserved2: u1 = 0, - /// LIN break detection clear flag - LBDCF: u1 = 0, - /// CTS clear flag - CTSCF: u1 = 0, - reserved3: u1 = 0, - /// Receiver timeout clear flag - RTOCF: u1 = 0, - /// End of timeout clear flag - EOBCF: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Character match clear flag - CMCF: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// Wakeup from Stop mode clear flag - WUCF: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RDR = mmio(Address + 0x00000024, 32, packed struct { - /// Receive data value - RDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TDR = mmio(Address + 0x00000028, 32, packed struct { - /// Transmit data value - TDR: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI1 = extern struct { - pub const Address: u32 = 0x40013000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI2 = extern struct { - pub const Address: u32 = 0x40003800; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI3 = extern struct { - pub const Address: u32 = 0x40003c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const I2S2ext = extern struct { - pub const Address: u32 = 0x40003400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const I2S3ext = extern struct { - pub const Address: u32 = 0x40004000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Serial peripheral interface/Inter-IC sound -pub const SPI4 = extern struct { - pub const Address: u32 = 0x40013c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Clock phase - CPHA: u1 = 0, - /// Clock polarity - CPOL: u1 = 0, - /// Master selection - MSTR: u1 = 0, - /// Baud rate control - BR: u3 = 0, - /// SPI enable - SPE: u1 = 0, - /// Frame format - LSBFIRST: u1 = 0, - /// Internal slave select - SSI: u1 = 0, - /// Software slave management - SSM: u1 = 0, - /// Receive only - RXONLY: u1 = 0, - /// CRC length - CRCL: u1 = 0, - /// CRC transfer next - CRCNEXT: u1 = 0, - /// Hardware CRC calculation enable - CRCEN: u1 = 0, - /// Output enable in bidirectional mode - BIDIOE: u1 = 0, - /// Bidirectional data mode enable - BIDIMODE: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1 = 0, - /// Tx buffer DMA enable - TXDMAEN: u1 = 0, - /// SS output enable - SSOE: u1 = 0, - /// NSS pulse management - NSSP: u1 = 0, - /// Frame format - FRF: u1 = 0, - /// Error interrupt enable - ERRIE: u1 = 0, - /// RX buffer not empty interrupt enable - RXNEIE: u1 = 0, - /// Tx buffer empty interrupt enable - TXEIE: u1 = 0, - /// Data size - DS: u4 = 0, - /// FIFO reception threshold - FRXTH: u1 = 0, - /// Last DMA transfer for reception - LDMA_RX: u1 = 0, - /// Last DMA transfer for transmission - LDMA_TX: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Receive buffer not empty - RXNE: u1 = 0, - /// Transmit buffer empty - TXE: u1 = 0, - /// Channel side - CHSIDE: u1 = 0, - /// Underrun flag - UDR: u1 = 0, - /// CRC error flag - CRCERR: u1 = 0, - /// Mode fault - MODF: u1 = 0, - /// Overrun flag - OVR: u1 = 0, - /// Busy flag - BSY: u1 = 0, - /// TI frame format error - TIFRFE: u1 = 0, - /// FIFO reception level - FRLVL: u2 = 0, - /// FIFO transmission level - FTLVL: u2 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// data register - pub const DR = mmio(Address + 0x0000000c, 32, packed struct { - /// Data register - DR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CRC polynomial register - pub const CRCPR = mmio(Address + 0x00000010, 32, packed struct { - /// CRC polynomial register - CRCPOLY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// RX CRC register - pub const RXCRCR = mmio(Address + 0x00000014, 32, packed struct { - /// Rx CRC register - RxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// TX CRC register - pub const TXCRCR = mmio(Address + 0x00000018, 32, packed struct { - /// Tx CRC register - TxCRC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S configuration register - pub const I2SCFGR = mmio(Address + 0x0000001c, 32, packed struct { - /// Channel length (number of bits per audio channel) - CHLEN: u1 = 0, - /// Data length to be transferred - DATLEN: u2 = 0, - /// Steady state clock polarity - CKPOL: u1 = 0, - /// I2S standard selection - I2SSTD: u2 = 0, - reserved1: u1 = 0, - /// PCM frame synchronization - PCMSYNC: u1 = 0, - /// I2S configuration mode - I2SCFG: u2 = 0, - /// I2S Enable - I2SE: u1 = 0, - /// I2S mode selection - I2SMOD: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// I2S prescaler register - pub const I2SPR = mmio(Address + 0x00000020, 32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8 = 0, - /// Odd factor for the prescaler - ODD: u1 = 0, - /// Master clock output enable - MCKOE: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// External interrupt/event controller -pub const EXTI = extern struct { - pub const Address: u32 = 0x40010400; - - /// Interrupt mask register - pub const IMR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1 = 0, - /// Interrupt Mask on line 1 - MR1: u1 = 0, - /// Interrupt Mask on line 2 - MR2: u1 = 0, - /// Interrupt Mask on line 3 - MR3: u1 = 0, - /// Interrupt Mask on line 4 - MR4: u1 = 0, - /// Interrupt Mask on line 5 - MR5: u1 = 0, - /// Interrupt Mask on line 6 - MR6: u1 = 0, - /// Interrupt Mask on line 7 - MR7: u1 = 0, - /// Interrupt Mask on line 8 - MR8: u1 = 0, - /// Interrupt Mask on line 9 - MR9: u1 = 0, - /// Interrupt Mask on line 10 - MR10: u1 = 0, - /// Interrupt Mask on line 11 - MR11: u1 = 0, - /// Interrupt Mask on line 12 - MR12: u1 = 0, - /// Interrupt Mask on line 13 - MR13: u1 = 0, - /// Interrupt Mask on line 14 - MR14: u1 = 0, - /// Interrupt Mask on line 15 - MR15: u1 = 0, - /// Interrupt Mask on line 16 - MR16: u1 = 0, - /// Interrupt Mask on line 17 - MR17: u1 = 0, - /// Interrupt Mask on line 18 - MR18: u1 = 0, - /// Interrupt Mask on line 19 - MR19: u1 = 0, - /// Interrupt Mask on line 20 - MR20: u1 = 0, - /// Interrupt Mask on line 21 - MR21: u1 = 0, - /// Interrupt Mask on line 22 - MR22: u1 = 0, - /// Interrupt Mask on line 23 - MR23: u1 = 0, - /// Interrupt Mask on line 24 - MR24: u1 = 0, - /// Interrupt Mask on line 25 - MR25: u1 = 0, - /// Interrupt Mask on line 26 - MR26: u1 = 0, - /// Interrupt Mask on line 27 - MR27: u1 = 0, - /// Interrupt Mask on line 28 - MR28: u1 = 0, - /// Interrupt Mask on line 29 - MR29: u1 = 0, - /// Interrupt Mask on line 30 - MR30: u1 = 0, - /// Interrupt Mask on line 31 - MR31: u1 = 0, - }); - - /// Event mask register - pub const EMR1 = mmio(Address + 0x00000004, 32, packed struct { - /// Event Mask on line 0 - MR0: u1 = 0, - /// Event Mask on line 1 - MR1: u1 = 0, - /// Event Mask on line 2 - MR2: u1 = 0, - /// Event Mask on line 3 - MR3: u1 = 0, - /// Event Mask on line 4 - MR4: u1 = 0, - /// Event Mask on line 5 - MR5: u1 = 0, - /// Event Mask on line 6 - MR6: u1 = 0, - /// Event Mask on line 7 - MR7: u1 = 0, - /// Event Mask on line 8 - MR8: u1 = 0, - /// Event Mask on line 9 - MR9: u1 = 0, - /// Event Mask on line 10 - MR10: u1 = 0, - /// Event Mask on line 11 - MR11: u1 = 0, - /// Event Mask on line 12 - MR12: u1 = 0, - /// Event Mask on line 13 - MR13: u1 = 0, - /// Event Mask on line 14 - MR14: u1 = 0, - /// Event Mask on line 15 - MR15: u1 = 0, - /// Event Mask on line 16 - MR16: u1 = 0, - /// Event Mask on line 17 - MR17: u1 = 0, - /// Event Mask on line 18 - MR18: u1 = 0, - /// Event Mask on line 19 - MR19: u1 = 0, - /// Event Mask on line 20 - MR20: u1 = 0, - /// Event Mask on line 21 - MR21: u1 = 0, - /// Event Mask on line 22 - MR22: u1 = 0, - /// Event Mask on line 23 - MR23: u1 = 0, - /// Event Mask on line 24 - MR24: u1 = 0, - /// Event Mask on line 25 - MR25: u1 = 0, - /// Event Mask on line 26 - MR26: u1 = 0, - /// Event Mask on line 27 - MR27: u1 = 0, - /// Event Mask on line 28 - MR28: u1 = 0, - /// Event Mask on line 29 - MR29: u1 = 0, - /// Event Mask on line 30 - MR30: u1 = 0, - /// Event Mask on line 31 - MR31: u1 = 0, - }); - - /// Rising Trigger selection register - pub const RTSR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Rising trigger event configuration of line 0 - TR0: u1 = 0, - /// Rising trigger event configuration of line 1 - TR1: u1 = 0, - /// Rising trigger event configuration of line 2 - TR2: u1 = 0, - /// Rising trigger event configuration of line 3 - TR3: u1 = 0, - /// Rising trigger event configuration of line 4 - TR4: u1 = 0, - /// Rising trigger event configuration of line 5 - TR5: u1 = 0, - /// Rising trigger event configuration of line 6 - TR6: u1 = 0, - /// Rising trigger event configuration of line 7 - TR7: u1 = 0, - /// Rising trigger event configuration of line 8 - TR8: u1 = 0, - /// Rising trigger event configuration of line 9 - TR9: u1 = 0, - /// Rising trigger event configuration of line 10 - TR10: u1 = 0, - /// Rising trigger event configuration of line 11 - TR11: u1 = 0, - /// Rising trigger event configuration of line 12 - TR12: u1 = 0, - /// Rising trigger event configuration of line 13 - TR13: u1 = 0, - /// Rising trigger event configuration of line 14 - TR14: u1 = 0, - /// Rising trigger event configuration of line 15 - TR15: u1 = 0, - /// Rising trigger event configuration of line 16 - TR16: u1 = 0, - /// Rising trigger event configuration of line 17 - TR17: u1 = 0, - /// Rising trigger event configuration of line 18 - TR18: u1 = 0, - /// Rising trigger event configuration of line 19 - TR19: u1 = 0, - /// Rising trigger event configuration of line 20 - TR20: u1 = 0, - /// Rising trigger event configuration of line 21 - TR21: u1 = 0, - /// Rising trigger event configuration of line 22 - TR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Rising trigger event configuration of line 29 - TR29: u1 = 0, - /// Rising trigger event configuration of line 30 - TR30: u1 = 0, - /// Rising trigger event configuration of line 31 - TR31: u1 = 0, - }); - - /// Falling Trigger selection register - pub const FTSR1 = mmio(Address + 0x0000000c, 32, packed struct { - /// Falling trigger event configuration of line 0 - TR0: u1 = 0, - /// Falling trigger event configuration of line 1 - TR1: u1 = 0, - /// Falling trigger event configuration of line 2 - TR2: u1 = 0, - /// Falling trigger event configuration of line 3 - TR3: u1 = 0, - /// Falling trigger event configuration of line 4 - TR4: u1 = 0, - /// Falling trigger event configuration of line 5 - TR5: u1 = 0, - /// Falling trigger event configuration of line 6 - TR6: u1 = 0, - /// Falling trigger event configuration of line 7 - TR7: u1 = 0, - /// Falling trigger event configuration of line 8 - TR8: u1 = 0, - /// Falling trigger event configuration of line 9 - TR9: u1 = 0, - /// Falling trigger event configuration of line 10 - TR10: u1 = 0, - /// Falling trigger event configuration of line 11 - TR11: u1 = 0, - /// Falling trigger event configuration of line 12 - TR12: u1 = 0, - /// Falling trigger event configuration of line 13 - TR13: u1 = 0, - /// Falling trigger event configuration of line 14 - TR14: u1 = 0, - /// Falling trigger event configuration of line 15 - TR15: u1 = 0, - /// Falling trigger event configuration of line 16 - TR16: u1 = 0, - /// Falling trigger event configuration of line 17 - TR17: u1 = 0, - /// Falling trigger event configuration of line 18 - TR18: u1 = 0, - /// Falling trigger event configuration of line 19 - TR19: u1 = 0, - /// Falling trigger event configuration of line 20 - TR20: u1 = 0, - /// Falling trigger event configuration of line 21 - TR21: u1 = 0, - /// Falling trigger event configuration of line 22 - TR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Falling trigger event configuration of line 29 - TR29: u1 = 0, - /// Falling trigger event configuration of line 30. - TR30: u1 = 0, - /// Falling trigger event configuration of line 31 - TR31: u1 = 0, - }); - - /// Software interrupt event register - pub const SWIER1 = mmio(Address + 0x00000010, 32, packed struct { - /// Software Interrupt on line 0 - SWIER0: u1 = 0, - /// Software Interrupt on line 1 - SWIER1: u1 = 0, - /// Software Interrupt on line 2 - SWIER2: u1 = 0, - /// Software Interrupt on line 3 - SWIER3: u1 = 0, - /// Software Interrupt on line 4 - SWIER4: u1 = 0, - /// Software Interrupt on line 5 - SWIER5: u1 = 0, - /// Software Interrupt on line 6 - SWIER6: u1 = 0, - /// Software Interrupt on line 7 - SWIER7: u1 = 0, - /// Software Interrupt on line 8 - SWIER8: u1 = 0, - /// Software Interrupt on line 9 - SWIER9: u1 = 0, - /// Software Interrupt on line 10 - SWIER10: u1 = 0, - /// Software Interrupt on line 11 - SWIER11: u1 = 0, - /// Software Interrupt on line 12 - SWIER12: u1 = 0, - /// Software Interrupt on line 13 - SWIER13: u1 = 0, - /// Software Interrupt on line 14 - SWIER14: u1 = 0, - /// Software Interrupt on line 15 - SWIER15: u1 = 0, - /// Software Interrupt on line 16 - SWIER16: u1 = 0, - /// Software Interrupt on line 17 - SWIER17: u1 = 0, - /// Software Interrupt on line 18 - SWIER18: u1 = 0, - /// Software Interrupt on line 19 - SWIER19: u1 = 0, - /// Software Interrupt on line 20 - SWIER20: u1 = 0, - /// Software Interrupt on line 21 - SWIER21: u1 = 0, - /// Software Interrupt on line 22 - SWIER22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Software Interrupt on line 29 - SWIER29: u1 = 0, - /// Software Interrupt on line 309 - SWIER30: u1 = 0, - /// Software Interrupt on line 319 - SWIER31: u1 = 0, - }); - - /// Pending register - pub const PR1 = mmio(Address + 0x00000014, 32, packed struct { - /// Pending bit 0 - PR0: u1 = 0, - /// Pending bit 1 - PR1: u1 = 0, - /// Pending bit 2 - PR2: u1 = 0, - /// Pending bit 3 - PR3: u1 = 0, - /// Pending bit 4 - PR4: u1 = 0, - /// Pending bit 5 - PR5: u1 = 0, - /// Pending bit 6 - PR6: u1 = 0, - /// Pending bit 7 - PR7: u1 = 0, - /// Pending bit 8 - PR8: u1 = 0, - /// Pending bit 9 - PR9: u1 = 0, - /// Pending bit 10 - PR10: u1 = 0, - /// Pending bit 11 - PR11: u1 = 0, - /// Pending bit 12 - PR12: u1 = 0, - /// Pending bit 13 - PR13: u1 = 0, - /// Pending bit 14 - PR14: u1 = 0, - /// Pending bit 15 - PR15: u1 = 0, - /// Pending bit 16 - PR16: u1 = 0, - /// Pending bit 17 - PR17: u1 = 0, - /// Pending bit 18 - PR18: u1 = 0, - /// Pending bit 19 - PR19: u1 = 0, - /// Pending bit 20 - PR20: u1 = 0, - /// Pending bit 21 - PR21: u1 = 0, - /// Pending bit 22 - PR22: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Pending bit 29 - PR29: u1 = 0, - /// Pending bit 30 - PR30: u1 = 0, - /// Pending bit 31 - PR31: u1 = 0, - }); - - /// Interrupt mask register - pub const IMR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Interrupt Mask on external/internal line 32 - MR32: u1 = 0, - /// Interrupt Mask on external/internal line 33 - MR33: u1 = 0, - /// Interrupt Mask on external/internal line 34 - MR34: u1 = 0, - /// Interrupt Mask on external/internal line 35 - MR35: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Event mask register - pub const EMR2 = mmio(Address + 0x0000001c, 32, packed struct { - /// Event mask on external/internal line 32 - MR32: u1 = 0, - /// Event mask on external/internal line 33 - MR33: u1 = 0, - /// Event mask on external/internal line 34 - MR34: u1 = 0, - /// Event mask on external/internal line 35 - MR35: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Rising Trigger selection register - pub const RTSR2 = mmio(Address + 0x00000020, 32, packed struct { - /// Rising trigger event configuration bit of line 32 - TR32: u1 = 0, - /// Rising trigger event configuration bit of line 33 - TR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Falling Trigger selection register - pub const FTSR2 = mmio(Address + 0x00000024, 32, packed struct { - /// Falling trigger event configuration bit of line 32 - TR32: u1 = 0, - /// Falling trigger event configuration bit of line 33 - TR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Software interrupt event register - pub const SWIER2 = mmio(Address + 0x00000028, 32, packed struct { - /// Software interrupt on line 32 - SWIER32: u1 = 0, - /// Software interrupt on line 33 - SWIER33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Pending register - pub const PR2 = mmio(Address + 0x0000002c, 32, packed struct { - /// Pending bit on line 32 - PR32: u1 = 0, - /// Pending bit on line 33 - PR33: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Power control -pub const PWR = extern struct { - pub const Address: u32 = 0x40007000; - - /// power control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// Low-power deep sleep - LPDS: u1 = 0, - /// Power down deepsleep - PDDS: u1 = 0, - /// Clear wakeup flag - CWUF: u1 = 0, - /// Clear standby flag - CSBF: u1 = 0, - /// Power voltage detector enable - PVDE: u1 = 0, - /// PVD level selection - PLS: u3 = 0, - /// Disable backup domain write protection - DBP: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// power control/status register - pub const CSR = mmio(Address + 0x00000004, 32, packed struct { - /// Wakeup flag - WUF: u1 = 0, - /// Standby flag - SBF: u1 = 0, - /// PVD output - PVDO: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Enable WKUP1 pin - EWUP1: u1 = 0, - /// Enable WKUP2 pin - EWUP2: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Controller area network -pub const CAN = extern struct { - pub const Address: u32 = 0x40006400; - - /// master control register - pub const MCR = mmio(Address + 0x00000000, 32, packed struct { - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// master status register - pub const MSR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// transmit status register - pub const TSR = mmio(Address + 0x00000008, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Lowest priority flag for mailbox 0 - TME0: u1 = 0, - /// Lowest priority flag for mailbox 1 - TME1: u1 = 0, - /// Lowest priority flag for mailbox 2 - TME2: u1 = 0, - /// Lowest priority flag for mailbox 0 - LOW0: u1 = 0, - /// Lowest priority flag for mailbox 1 - LOW1: u1 = 0, - /// Lowest priority flag for mailbox 2 - LOW2: u1 = 0, - }); - - /// receive FIFO 0 register - pub const RF0R = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// receive FIFO 1 register - pub const RF1R = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000014, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// error status register - pub const ESR = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - }); - - /// bit timing register - pub const BTR = mmio(Address + 0x0000001c, 32, packed struct { - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved7: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - }); - - /// TX mailbox identifier register - pub const TI0R = mmio(Address + 0x00000180, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT0R = mmio(Address + 0x00000184, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL0R = mmio(Address + 0x00000188, 32, packed struct {}); - - /// mailbox data high register - pub const TDH0R = mmio(Address + 0x0000018c, 32, packed struct {}); - - /// TX mailbox identifier register - pub const TI1R = mmio(Address + 0x00000190, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT1R = mmio(Address + 0x00000194, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL1R = mmio(Address + 0x00000198, 32, packed struct {}); - - /// mailbox data high register - pub const TDH1R = mmio(Address + 0x0000019c, 32, packed struct {}); - - /// TX mailbox identifier register - pub const TI2R = mmio(Address + 0x000001a0, 32, packed struct {}); - - /// mailbox data length control and time stamp register - pub const TDT2R = mmio(Address + 0x000001a4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - }); - - /// mailbox data low register - pub const TDL2R = mmio(Address + 0x000001a8, 32, packed struct {}); - - /// mailbox data high register - pub const TDH2R = mmio(Address + 0x000001ac, 32, packed struct {}); - - /// receive FIFO mailbox identifier register - pub const RI0R = mmio(Address + 0x000001b0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data length control and time stamp register - pub const RDT0R = mmio(Address + 0x000001b4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data low register - pub const RDL0R = mmio(Address + 0x000001b8, 32, packed struct {}); - - /// receive FIFO mailbox data high register - pub const RDH0R = mmio(Address + 0x000001bc, 32, packed struct {}); - - /// receive FIFO mailbox identifier register - pub const RI1R = mmio(Address + 0x000001c0, 32, packed struct { - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data length control and time stamp register - pub const RDT1R = mmio(Address + 0x000001c4, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// receive FIFO mailbox data low register - pub const RDL1R = mmio(Address + 0x000001c8, 32, packed struct {}); - - /// receive FIFO mailbox data high register - pub const RDH1R = mmio(Address + 0x000001cc, 32, packed struct {}); - - /// filter master register - pub const FMR = mmio(Address + 0x00000200, 32, packed struct { - /// Filter init mode - FINIT: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// CAN2 start bank - CAN2SB: u6 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter mode register - pub const FM1R = mmio(Address + 0x00000204, 32, packed struct { - /// Filter mode - FBM0: u1 = 0, - /// Filter mode - FBM1: u1 = 0, - /// Filter mode - FBM2: u1 = 0, - /// Filter mode - FBM3: u1 = 0, - /// Filter mode - FBM4: u1 = 0, - /// Filter mode - FBM5: u1 = 0, - /// Filter mode - FBM6: u1 = 0, - /// Filter mode - FBM7: u1 = 0, - /// Filter mode - FBM8: u1 = 0, - /// Filter mode - FBM9: u1 = 0, - /// Filter mode - FBM10: u1 = 0, - /// Filter mode - FBM11: u1 = 0, - /// Filter mode - FBM12: u1 = 0, - /// Filter mode - FBM13: u1 = 0, - /// Filter mode - FBM14: u1 = 0, - /// Filter mode - FBM15: u1 = 0, - /// Filter mode - FBM16: u1 = 0, - /// Filter mode - FBM17: u1 = 0, - /// Filter mode - FBM18: u1 = 0, - /// Filter mode - FBM19: u1 = 0, - /// Filter mode - FBM20: u1 = 0, - /// Filter mode - FBM21: u1 = 0, - /// Filter mode - FBM22: u1 = 0, - /// Filter mode - FBM23: u1 = 0, - /// Filter mode - FBM24: u1 = 0, - /// Filter mode - FBM25: u1 = 0, - /// Filter mode - FBM26: u1 = 0, - /// Filter mode - FBM27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter scale register - pub const FS1R = mmio(Address + 0x0000020c, 32, packed struct { - /// Filter scale configuration - FSC0: u1 = 0, - /// Filter scale configuration - FSC1: u1 = 0, - /// Filter scale configuration - FSC2: u1 = 0, - /// Filter scale configuration - FSC3: u1 = 0, - /// Filter scale configuration - FSC4: u1 = 0, - /// Filter scale configuration - FSC5: u1 = 0, - /// Filter scale configuration - FSC6: u1 = 0, - /// Filter scale configuration - FSC7: u1 = 0, - /// Filter scale configuration - FSC8: u1 = 0, - /// Filter scale configuration - FSC9: u1 = 0, - /// Filter scale configuration - FSC10: u1 = 0, - /// Filter scale configuration - FSC11: u1 = 0, - /// Filter scale configuration - FSC12: u1 = 0, - /// Filter scale configuration - FSC13: u1 = 0, - /// Filter scale configuration - FSC14: u1 = 0, - /// Filter scale configuration - FSC15: u1 = 0, - /// Filter scale configuration - FSC16: u1 = 0, - /// Filter scale configuration - FSC17: u1 = 0, - /// Filter scale configuration - FSC18: u1 = 0, - /// Filter scale configuration - FSC19: u1 = 0, - /// Filter scale configuration - FSC20: u1 = 0, - /// Filter scale configuration - FSC21: u1 = 0, - /// Filter scale configuration - FSC22: u1 = 0, - /// Filter scale configuration - FSC23: u1 = 0, - /// Filter scale configuration - FSC24: u1 = 0, - /// Filter scale configuration - FSC25: u1 = 0, - /// Filter scale configuration - FSC26: u1 = 0, - /// Filter scale configuration - FSC27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// filter FIFO assignment register - pub const FFA1R = mmio(Address + 0x00000214, 32, packed struct { - /// Filter FIFO assignment for filter 0 - FFA0: u1 = 0, - /// Filter FIFO assignment for filter 1 - FFA1: u1 = 0, - /// Filter FIFO assignment for filter 2 - FFA2: u1 = 0, - /// Filter FIFO assignment for filter 3 - FFA3: u1 = 0, - /// Filter FIFO assignment for filter 4 - FFA4: u1 = 0, - /// Filter FIFO assignment for filter 5 - FFA5: u1 = 0, - /// Filter FIFO assignment for filter 6 - FFA6: u1 = 0, - /// Filter FIFO assignment for filter 7 - FFA7: u1 = 0, - /// Filter FIFO assignment for filter 8 - FFA8: u1 = 0, - /// Filter FIFO assignment for filter 9 - FFA9: u1 = 0, - /// Filter FIFO assignment for filter 10 - FFA10: u1 = 0, - /// Filter FIFO assignment for filter 11 - FFA11: u1 = 0, - /// Filter FIFO assignment for filter 12 - FFA12: u1 = 0, - /// Filter FIFO assignment for filter 13 - FFA13: u1 = 0, - /// Filter FIFO assignment for filter 14 - FFA14: u1 = 0, - /// Filter FIFO assignment for filter 15 - FFA15: u1 = 0, - /// Filter FIFO assignment for filter 16 - FFA16: u1 = 0, - /// Filter FIFO assignment for filter 17 - FFA17: u1 = 0, - /// Filter FIFO assignment for filter 18 - FFA18: u1 = 0, - /// Filter FIFO assignment for filter 19 - FFA19: u1 = 0, - /// Filter FIFO assignment for filter 20 - FFA20: u1 = 0, - /// Filter FIFO assignment for filter 21 - FFA21: u1 = 0, - /// Filter FIFO assignment for filter 22 - FFA22: u1 = 0, - /// Filter FIFO assignment for filter 23 - FFA23: u1 = 0, - /// Filter FIFO assignment for filter 24 - FFA24: u1 = 0, - /// Filter FIFO assignment for filter 25 - FFA25: u1 = 0, - /// Filter FIFO assignment for filter 26 - FFA26: u1 = 0, - /// Filter FIFO assignment for filter 27 - FFA27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// CAN filter activation register - pub const FA1R = mmio(Address + 0x0000021c, 32, packed struct { - /// Filter active - FACT0: u1 = 0, - /// Filter active - FACT1: u1 = 0, - /// Filter active - FACT2: u1 = 0, - /// Filter active - FACT3: u1 = 0, - /// Filter active - FACT4: u1 = 0, - /// Filter active - FACT5: u1 = 0, - /// Filter active - FACT6: u1 = 0, - /// Filter active - FACT7: u1 = 0, - /// Filter active - FACT8: u1 = 0, - /// Filter active - FACT9: u1 = 0, - /// Filter active - FACT10: u1 = 0, - /// Filter active - FACT11: u1 = 0, - /// Filter active - FACT12: u1 = 0, - /// Filter active - FACT13: u1 = 0, - /// Filter active - FACT14: u1 = 0, - /// Filter active - FACT15: u1 = 0, - /// Filter active - FACT16: u1 = 0, - /// Filter active - FACT17: u1 = 0, - /// Filter active - FACT18: u1 = 0, - /// Filter active - FACT19: u1 = 0, - /// Filter active - FACT20: u1 = 0, - /// Filter active - FACT21: u1 = 0, - /// Filter active - FACT22: u1 = 0, - /// Filter active - FACT23: u1 = 0, - /// Filter active - FACT24: u1 = 0, - /// Filter active - FACT25: u1 = 0, - /// Filter active - FACT26: u1 = 0, - /// Filter active - FACT27: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Filter bank 0 register 1 - pub const F0R1 = mmio(Address + 0x00000240, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 0 register 2 - pub const F0R2 = mmio(Address + 0x00000244, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 1 - pub const F1R1 = mmio(Address + 0x00000248, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 1 register 2 - pub const F1R2 = mmio(Address + 0x0000024c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 1 - pub const F2R1 = mmio(Address + 0x00000250, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 2 register 2 - pub const F2R2 = mmio(Address + 0x00000254, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 1 - pub const F3R1 = mmio(Address + 0x00000258, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 3 register 2 - pub const F3R2 = mmio(Address + 0x0000025c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F4R1 = mmio(Address + 0x00000260, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 2 - pub const F4R2 = mmio(Address + 0x00000264, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 1 - pub const F5R1 = mmio(Address + 0x00000268, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 5 register 2 - pub const F5R2 = mmio(Address + 0x0000026c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 1 - pub const F6R1 = mmio(Address + 0x00000270, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 6 register 2 - pub const F6R2 = mmio(Address + 0x00000274, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 1 - pub const F7R1 = mmio(Address + 0x00000278, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 7 register 2 - pub const F7R2 = mmio(Address + 0x0000027c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 1 - pub const F8R1 = mmio(Address + 0x00000280, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 8 register 2 - pub const F8R2 = mmio(Address + 0x00000284, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 1 - pub const F9R1 = mmio(Address + 0x00000288, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 9 register 2 - pub const F9R2 = mmio(Address + 0x0000028c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 1 - pub const F10R1 = mmio(Address + 0x00000290, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 10 register 2 - pub const F10R2 = mmio(Address + 0x00000294, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 1 - pub const F11R1 = mmio(Address + 0x00000298, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 11 register 2 - pub const F11R2 = mmio(Address + 0x0000029c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 4 register 1 - pub const F12R1 = mmio(Address + 0x000002a0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 12 register 2 - pub const F12R2 = mmio(Address + 0x000002a4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 1 - pub const F13R1 = mmio(Address + 0x000002a8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 13 register 2 - pub const F13R2 = mmio(Address + 0x000002ac, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 14 register 1 - pub const F14R1 = mmio(Address + 0x000002b0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 14 register 2 - pub const F14R2 = mmio(Address + 0x000002b4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 15 register 1 - pub const F15R1 = mmio(Address + 0x000002b8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 15 register 2 - pub const F15R2 = mmio(Address + 0x000002bc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 16 register 1 - pub const F16R1 = mmio(Address + 0x000002c0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 16 register 2 - pub const F16R2 = mmio(Address + 0x000002c4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 17 register 1 - pub const F17R1 = mmio(Address + 0x000002c8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 17 register 2 - pub const F17R2 = mmio(Address + 0x000002cc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 18 register 1 - pub const F18R1 = mmio(Address + 0x000002d0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 18 register 2 - pub const F18R2 = mmio(Address + 0x000002d4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 19 register 1 - pub const F19R1 = mmio(Address + 0x000002d8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 19 register 2 - pub const F19R2 = mmio(Address + 0x000002dc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 20 register 1 - pub const F20R1 = mmio(Address + 0x000002e0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 20 register 2 - pub const F20R2 = mmio(Address + 0x000002e4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 21 register 1 - pub const F21R1 = mmio(Address + 0x000002e8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 21 register 2 - pub const F21R2 = mmio(Address + 0x000002ec, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 22 register 1 - pub const F22R1 = mmio(Address + 0x000002f0, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 22 register 2 - pub const F22R2 = mmio(Address + 0x000002f4, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 23 register 1 - pub const F23R1 = mmio(Address + 0x000002f8, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 23 register 2 - pub const F23R2 = mmio(Address + 0x000002fc, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 24 register 1 - pub const F24R1 = mmio(Address + 0x00000300, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 24 register 2 - pub const F24R2 = mmio(Address + 0x00000304, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 25 register 1 - pub const F25R1 = mmio(Address + 0x00000308, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 25 register 2 - pub const F25R2 = mmio(Address + 0x0000030c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 26 register 1 - pub const F26R1 = mmio(Address + 0x00000310, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 26 register 2 - pub const F26R2 = mmio(Address + 0x00000314, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 27 register 1 - pub const F27R1 = mmio(Address + 0x00000318, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); - - /// Filter bank 27 register 2 - pub const F27R2 = mmio(Address + 0x0000031c, 32, packed struct { - /// Filter bits - FB0: u1 = 0, - /// Filter bits - FB1: u1 = 0, - /// Filter bits - FB2: u1 = 0, - /// Filter bits - FB3: u1 = 0, - /// Filter bits - FB4: u1 = 0, - /// Filter bits - FB5: u1 = 0, - /// Filter bits - FB6: u1 = 0, - /// Filter bits - FB7: u1 = 0, - /// Filter bits - FB8: u1 = 0, - /// Filter bits - FB9: u1 = 0, - /// Filter bits - FB10: u1 = 0, - /// Filter bits - FB11: u1 = 0, - /// Filter bits - FB12: u1 = 0, - /// Filter bits - FB13: u1 = 0, - /// Filter bits - FB14: u1 = 0, - /// Filter bits - FB15: u1 = 0, - /// Filter bits - FB16: u1 = 0, - /// Filter bits - FB17: u1 = 0, - /// Filter bits - FB18: u1 = 0, - /// Filter bits - FB19: u1 = 0, - /// Filter bits - FB20: u1 = 0, - /// Filter bits - FB21: u1 = 0, - /// Filter bits - FB22: u1 = 0, - /// Filter bits - FB23: u1 = 0, - /// Filter bits - FB24: u1 = 0, - /// Filter bits - FB25: u1 = 0, - /// Filter bits - FB26: u1 = 0, - /// Filter bits - FB27: u1 = 0, - /// Filter bits - FB28: u1 = 0, - /// Filter bits - FB29: u1 = 0, - /// Filter bits - FB30: u1 = 0, - /// Filter bits - FB31: u1 = 0, - }); -}; - -/// Universal serial bus full-speed device interface -pub const USB_FS = extern struct { - pub const Address: u32 = 0x40005c00; - - /// endpoint 0 register - pub const USB_EP0R = mmio(Address + 0x00000000, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 1 register - pub const USB_EP1R = mmio(Address + 0x00000004, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 2 register - pub const USB_EP2R = mmio(Address + 0x00000008, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 3 register - pub const USB_EP3R = mmio(Address + 0x0000000c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 4 register - pub const USB_EP4R = mmio(Address + 0x00000010, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 5 register - pub const USB_EP5R = mmio(Address + 0x00000014, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 6 register - pub const USB_EP6R = mmio(Address + 0x00000018, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// endpoint 7 register - pub const USB_EP7R = mmio(Address + 0x0000001c, 32, packed struct { - /// Endpoint address - EA: u4 = 0, - /// Status bits, for transmission transfers - STAT_TX: u2 = 0, - /// Data Toggle, for transmission transfers - DTOG_TX: u1 = 0, - /// Correct Transfer for transmission - CTR_TX: u1 = 0, - /// Endpoint kind - EP_KIND: u1 = 0, - /// Endpoint type - EP_TYPE: u2 = 0, - /// Setup transaction completed - SETUP: u1 = 0, - /// Status bits, for reception transfers - STAT_RX: u2 = 0, - /// Data Toggle, for reception transfers - DTOG_RX: u1 = 0, - /// Correct transfer for reception - CTR_RX: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const USB_CNTR = mmio(Address + 0x00000040, 32, packed struct { - /// Force USB Reset - FRES: u1 = 0, - /// Power down - PDWN: u1 = 0, - /// Low-power mode - LPMODE: u1 = 0, - /// Force suspend - FSUSP: u1 = 0, - /// Resume request - RESUME: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start of frame interrupt mask - ESOFM: u1 = 0, - /// Start of frame interrupt mask - SOFM: u1 = 0, - /// USB reset interrupt mask - RESETM: u1 = 0, - /// Suspend mode interrupt mask - SUSPM: u1 = 0, - /// Wakeup interrupt mask - WKUPM: u1 = 0, - /// Error interrupt mask - ERRM: u1 = 0, - /// Packet memory area over / underrun interrupt mask - PMAOVRM: u1 = 0, - /// Correct transfer interrupt mask - CTRM: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt status register - pub const ISTR = mmio(Address + 0x00000044, 32, packed struct { - /// Endpoint Identifier - EP_ID: u4 = 0, - /// Direction of transaction - DIR: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Expected start frame - ESOF: u1 = 0, - /// start of frame - SOF: u1 = 0, - /// reset request - RESET: u1 = 0, - /// Suspend mode request - SUSP: u1 = 0, - /// Wakeup - WKUP: u1 = 0, - /// Error - ERR: u1 = 0, - /// Packet memory area over / underrun - PMAOVR: u1 = 0, - /// Correct transfer - CTR: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// frame number register - pub const FNR = mmio(Address + 0x00000048, 32, packed struct { - /// Frame number - FN: u11 = 0, - /// Lost SOF - LSOF: u2 = 0, - /// Locked - LCK: u1 = 0, - /// Receive data - line status - RXDM: u1 = 0, - /// Receive data + line status - RXDP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// device address - pub const DADDR = mmio(Address + 0x0000004c, 32, packed struct { - /// Device address - ADD: u1 = 0, - /// Device address - ADD1: u1 = 0, - /// Device address - ADD2: u1 = 0, - /// Device address - ADD3: u1 = 0, - /// Device address - ADD4: u1 = 0, - /// Device address - ADD5: u1 = 0, - /// Device address - ADD6: u1 = 0, - /// Enable function - EF: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Buffer table address - pub const BTABLE = mmio(Address + 0x00000050, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Buffer table - BTABLE: u13 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C1 = extern struct { - pub const Address: u32 = 0x40005400; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C2 = extern struct { - pub const Address: u32 = 0x40005800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Inter-integrated circuit -pub const I2C3 = extern struct { - pub const Address: u32 = 0x40007800; - - /// Control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Peripheral enable - PE: u1 = 0, - /// TX Interrupt enable - TXIE: u1 = 0, - /// RX Interrupt enable - RXIE: u1 = 0, - /// Address match interrupt enable (slave only) - ADDRIE: u1 = 0, - /// Not acknowledge received interrupt enable - NACKIE: u1 = 0, - /// STOP detection Interrupt enable - STOPIE: u1 = 0, - /// Transfer Complete interrupt enable - TCIE: u1 = 0, - /// Error interrupts enable - ERRIE: u1 = 0, - /// Digital noise filter - DNF: u4 = 0, - /// Analog noise filter OFF - ANFOFF: u1 = 0, - /// Software reset - SWRST: u1 = 0, - /// DMA transmission requests enable - TXDMAEN: u1 = 0, - /// DMA reception requests enable - RXDMAEN: u1 = 0, - /// Slave byte control - SBC: u1 = 0, - /// Clock stretching disable - NOSTRETCH: u1 = 0, - /// Wakeup from STOP enable - WUPEN: u1 = 0, - /// General call enable - GCEN: u1 = 0, - /// SMBus Host address enable - SMBHEN: u1 = 0, - /// SMBus Device Default address enable - SMBDEN: u1 = 0, - /// SMBUS alert enable - ALERTEN: u1 = 0, - /// PEC enable - PECEN: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Slave address bit 0 (master mode) - SADD0: u1 = 0, - /// Slave address bit 7:1 (master mode) - SADD1: u7 = 0, - /// Slave address bit 9:8 (master mode) - SADD8: u2 = 0, - /// Transfer direction (master mode) - RD_WRN: u1 = 0, - /// 10-bit addressing mode (master mode) - ADD10: u1 = 0, - /// 10-bit address header only read direction (master receiver mode) - HEAD10R: u1 = 0, - /// Start generation - START: u1 = 0, - /// Stop generation (master mode) - STOP: u1 = 0, - /// NACK generation (slave mode) - NACK: u1 = 0, - /// Number of bytes - NBYTES: u8 = 0, - /// NBYTES reload mode - RELOAD: u1 = 0, - /// Automatic end mode (master mode) - AUTOEND: u1 = 0, - /// Packet error checking byte - PECBYTE: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 1 - pub const OAR1 = mmio(Address + 0x00000008, 32, packed struct { - /// Interface address - OA1_0: u1 = 0, - /// Interface address - OA1_1: u7 = 0, - /// Interface address - OA1_8: u2 = 0, - /// Own Address 1 10-bit mode - OA1MODE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Own Address 1 enable - OA1EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Own address register 2 - pub const OAR2 = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - /// Interface address - OA2: u7 = 0, - /// Own Address 2 masks - OA2MSK: u3 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Own Address 2 enable - OA2EN: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Timing register - pub const TIMINGR = mmio(Address + 0x00000010, 32, packed struct { - /// SCL low period (master mode) - SCLL: u8 = 0, - /// SCL high period (master mode) - SCLH: u8 = 0, - /// Data hold time - SDADEL: u4 = 0, - /// Data setup time - SCLDEL: u4 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Timing prescaler - PRESC: u4 = 0, - }); - - /// Status register 1 - pub const TIMEOUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Bus timeout A - TIMEOUTA: u12 = 0, - /// Idle clock timeout detection - TIDLE: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Clock timeout enable - TIMOUTEN: u1 = 0, - /// Bus timeout B - TIMEOUTB: u12 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Extended clock timeout enable - TEXTEN: u1 = 0, - }); - - /// Interrupt and Status register - pub const ISR = mmio(Address + 0x00000018, 32, packed struct { - /// Transmit data register empty (transmitters) - TXE: u1 = 0, - /// Transmit interrupt status (transmitters) - TXIS: u1 = 0, - /// Receive data register not empty (receivers) - RXNE: u1 = 0, - /// Address matched (slave mode) - ADDR: u1 = 0, - /// Not acknowledge received flag - NACKF: u1 = 0, - /// Stop detection flag - STOPF: u1 = 0, - /// Transfer Complete (master mode) - TC: u1 = 0, - /// Transfer Complete Reload - TCR: u1 = 0, - /// Bus error - BERR: u1 = 0, - /// Arbitration lost - ARLO: u1 = 0, - /// Overrun/Underrun (slave mode) - OVR: u1 = 0, - /// PEC Error in reception - PECERR: u1 = 0, - /// Timeout or t_low detection flag - TIMEOUT: u1 = 0, - /// SMBus alert - ALERT: u1 = 0, - reserved1: u1 = 0, - /// Bus busy - BUSY: u1 = 0, - /// Transfer direction (Slave mode) - DIR: u1 = 0, - /// Address match code (Slave mode) - ADDCODE: u7 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Interrupt clear register - pub const ICR = mmio(Address + 0x0000001c, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Address Matched flag clear - ADDRCF: u1 = 0, - /// Not Acknowledge flag clear - NACKCF: u1 = 0, - /// Stop detection flag clear - STOPCF: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Bus error flag clear - BERRCF: u1 = 0, - /// Arbitration lost flag clear - ARLOCF: u1 = 0, - /// Overrun/Underrun flag clear - OVRCF: u1 = 0, - /// PEC Error flag clear - PECCF: u1 = 0, - /// Timeout detection flag clear - TIMOUTCF: u1 = 0, - /// Alert flag clear - ALERTCF: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PEC register - pub const PECR = mmio(Address + 0x00000020, 32, packed struct { - /// Packet error checking register - PEC: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Receive data register - pub const RXDR = mmio(Address + 0x00000024, 32, packed struct { - /// 8-bit receive data - RXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Transmit data register - pub const TXDR = mmio(Address + 0x00000028, 32, packed struct { - /// 8-bit transmit data - TXDATA: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Independent watchdog -pub const IWDG = extern struct { - pub const Address: u32 = 0x40003000; - - /// Key register - pub const KR = mmio(Address + 0x00000000, 32, packed struct { - /// Key value - KEY: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Prescaler register - pub const PR = mmio(Address + 0x00000004, 32, packed struct { - /// Prescaler divider - PR: u3 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Reload register - pub const RLR = mmio(Address + 0x00000008, 32, packed struct { - /// Watchdog counter reload value - RL: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x0000000c, 32, packed struct { - /// Watchdog prescaler value update - PVU: u1 = 0, - /// Watchdog counter reload value update - RVU: u1 = 0, - /// Watchdog counter window value update - WVU: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Window register - pub const WINR = mmio(Address + 0x00000010, 32, packed struct { - /// Watchdog counter window value - WIN: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Window watchdog -pub const WWDG = extern struct { - pub const Address: u32 = 0x40002c00; - - /// Control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// 7-bit counter - T: u7 = 0, - /// Activation bit - WDGA: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration register - pub const CFR = mmio(Address + 0x00000004, 32, packed struct { - /// 7-bit window value - W: u7 = 0, - /// Timer base - WDGTB: u2 = 0, - /// Early wakeup interrupt - EWI: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Status register - pub const SR = mmio(Address + 0x00000008, 32, packed struct { - /// Early wakeup interrupt flag - EWIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Real-time clock -pub const RTC = extern struct { - pub const Address: u32 = 0x40002800; - - /// time register - pub const TR = mmio(Address + 0x00000000, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - reserved1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - reserved2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// date register - pub const DR = mmio(Address + 0x00000004, 32, packed struct { - /// Date units in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Month units in BCD format - MU: u4 = 0, - /// Month tens in BCD format - MT: u1 = 0, - /// Week day units - WDU: u3 = 0, - /// Year units in BCD format - YU: u4 = 0, - /// Year tens in BCD format - YT: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - /// Wakeup clock selection - WCKSEL: u3 = 0, - /// Time-stamp event active edge - TSEDGE: u1 = 0, - /// Reference clock detection enable (50 or 60 Hz) - REFCKON: u1 = 0, - /// Bypass the shadow registers - BYPSHAD: u1 = 0, - /// Hour format - FMT: u1 = 0, - reserved1: u1 = 0, - /// Alarm A enable - ALRAE: u1 = 0, - /// Alarm B enable - ALRBE: u1 = 0, - /// Wakeup timer enable - WUTE: u1 = 0, - /// Time stamp enable - TSE: u1 = 0, - /// Alarm A interrupt enable - ALRAIE: u1 = 0, - /// Alarm B interrupt enable - ALRBIE: u1 = 0, - /// Wakeup timer interrupt enable - WUTIE: u1 = 0, - /// Time-stamp interrupt enable - TSIE: u1 = 0, - /// Add 1 hour (summer time change) - ADD1H: u1 = 0, - /// Subtract 1 hour (winter time change) - SUB1H: u1 = 0, - /// Backup - BKP: u1 = 0, - /// Calibration output selection - COSEL: u1 = 0, - /// Output polarity - POL: u1 = 0, - /// Output selection - OSEL: u2 = 0, - /// Calibration output enable - COE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// initialization and status register - pub const ISR = mmio(Address + 0x0000000c, 32, packed struct { - /// Alarm A write flag - ALRAWF: u1 = 0, - /// Alarm B write flag - ALRBWF: u1 = 0, - /// Wakeup timer write flag - WUTWF: u1 = 0, - /// Shift operation pending - SHPF: u1 = 0, - /// Initialization status flag - INITS: u1 = 0, - /// Registers synchronization flag - RSF: u1 = 0, - /// Initialization flag - INITF: u1 = 0, - /// Initialization mode - INIT: u1 = 0, - /// Alarm A flag - ALRAF: u1 = 0, - /// Alarm B flag - ALRBF: u1 = 0, - /// Wakeup timer flag - WUTF: u1 = 0, - /// Time-stamp flag - TSF: u1 = 0, - /// Time-stamp overflow flag - TSOVF: u1 = 0, - /// Tamper detection flag - TAMP1F: u1 = 0, - /// RTC_TAMP2 detection flag - TAMP2F: u1 = 0, - /// RTC_TAMP3 detection flag - TAMP3F: u1 = 0, - /// Recalibration pending Flag - RECALPF: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// prescaler register - pub const PRER = mmio(Address + 0x00000010, 32, packed struct { - /// Synchronous prescaler factor - PREDIV_S: u15 = 0, - reserved1: u1 = 0, - /// Asynchronous prescaler factor - PREDIV_A: u7 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// wakeup timer register - pub const WUTR = mmio(Address + 0x00000014, 32, packed struct { - /// Wakeup auto-reload value bits - WUT: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm A register - pub const ALRMAR = mmio(Address + 0x0000001c, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - /// Alarm A seconds mask - MSK1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - /// Alarm A minutes mask - MSK2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - /// Alarm A hours mask - MSK3: u1 = 0, - /// Date units or day in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - /// Week day selection - WDSEL: u1 = 0, - /// Alarm A date mask - MSK4: u1 = 0, - }); - - /// alarm B register - pub const ALRMBR = mmio(Address + 0x00000020, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - /// Alarm B seconds mask - MSK1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - /// Alarm B minutes mask - MSK2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - /// Alarm B hours mask - MSK3: u1 = 0, - /// Date units or day in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - /// Week day selection - WDSEL: u1 = 0, - /// Alarm B date mask - MSK4: u1 = 0, - }); - - /// write protection register - pub const WPR = mmio(Address + 0x00000024, 32, packed struct { - /// Write protection key - KEY: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sub second register - pub const SSR = mmio(Address + 0x00000028, 32, packed struct { - /// Sub second value - SS: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// shift control register - pub const SHIFTR = mmio(Address + 0x0000002c, 32, packed struct { - /// Subtract a fraction of a second - SUBFS: u15 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Add one second - ADD1S: u1 = 0, - }); - - /// time stamp time register - pub const TSTR = mmio(Address + 0x00000030, 32, packed struct { - /// Second units in BCD format - SU: u4 = 0, - /// Second tens in BCD format - ST: u3 = 0, - reserved1: u1 = 0, - /// Minute units in BCD format - MNU: u4 = 0, - /// Minute tens in BCD format - MNT: u3 = 0, - reserved2: u1 = 0, - /// Hour units in BCD format - HU: u4 = 0, - /// Hour tens in BCD format - HT: u2 = 0, - /// AM/PM notation - PM: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// time stamp date register - pub const TSDR = mmio(Address + 0x00000034, 32, packed struct { - /// Date units in BCD format - DU: u4 = 0, - /// Date tens in BCD format - DT: u2 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Month units in BCD format - MU: u4 = 0, - /// Month tens in BCD format - MT: u1 = 0, - /// Week day units - WDU: u3 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// timestamp sub second register - pub const TSSSR = mmio(Address + 0x00000038, 32, packed struct { - /// Sub second value - SS: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// calibration register - pub const CALR = mmio(Address + 0x0000003c, 32, packed struct { - /// Calibration minus - CALM: u9 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Use a 16-second calibration cycle period - CALW16: u1 = 0, - /// Use an 8-second calibration cycle period - CALW8: u1 = 0, - /// Increase frequency of RTC by 488.5 ppm - CALP: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// tamper and alternate function configuration register - pub const TAFCR = mmio(Address + 0x00000040, 32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1 = 0, - /// Active level for tamper 1 - TAMP1TRG: u1 = 0, - /// Tamper interrupt enable - TAMPIE: u1 = 0, - /// Tamper 2 detection enable - TAMP2E: u1 = 0, - /// Active level for tamper 2 - TAMP2TRG: u1 = 0, - /// Tamper 3 detection enable - TAMP3E: u1 = 0, - /// Active level for tamper 3 - TAMP3TRG: u1 = 0, - /// Activate timestamp on tamper detection event - TAMPTS: u1 = 0, - /// Tamper sampling frequency - TAMPFREQ: u3 = 0, - /// Tamper filter count - TAMPFLT: u2 = 0, - /// Tamper precharge duration - TAMPPRCH: u2 = 0, - /// TAMPER pull-up disable - TAMPPUDIS: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// PC13 value - PC13VALUE: u1 = 0, - /// PC13 mode - PC13MODE: u1 = 0, - /// PC14 value - PC14VALUE: u1 = 0, - /// PC 14 mode - PC14MODE: u1 = 0, - /// PC15 value - PC15VALUE: u1 = 0, - /// PC15 mode - PC15MODE: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm A sub second register - pub const ALRMASSR = mmio(Address + 0x00000044, 32, packed struct { - /// Sub seconds value - SS: u15 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Mask the most-significant bits starting at this bit - MASKSS: u4 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// alarm B sub second register - pub const ALRMBSSR = mmio(Address + 0x00000048, 32, packed struct { - /// Sub seconds value - SS: u15 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Mask the most-significant bits starting at this bit - MASKSS: u4 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// backup register - pub const BKP0R = mmio(Address + 0x00000050, 32, packed struct {}); - - /// backup register - pub const BKP1R = mmio(Address + 0x00000054, 32, packed struct {}); - - /// backup register - pub const BKP2R = mmio(Address + 0x00000058, 32, packed struct {}); - - /// backup register - pub const BKP3R = mmio(Address + 0x0000005c, 32, packed struct {}); - - /// backup register - pub const BKP4R = mmio(Address + 0x00000060, 32, packed struct {}); - - /// backup register - pub const BKP5R = mmio(Address + 0x00000064, 32, packed struct {}); - - /// backup register - pub const BKP6R = mmio(Address + 0x00000068, 32, packed struct {}); - - /// backup register - pub const BKP7R = mmio(Address + 0x0000006c, 32, packed struct {}); - - /// backup register - pub const BKP8R = mmio(Address + 0x00000070, 32, packed struct {}); - - /// backup register - pub const BKP9R = mmio(Address + 0x00000074, 32, packed struct {}); - - /// backup register - pub const BKP10R = mmio(Address + 0x00000078, 32, packed struct {}); - - /// backup register - pub const BKP11R = mmio(Address + 0x0000007c, 32, packed struct {}); - - /// backup register - pub const BKP12R = mmio(Address + 0x00000080, 32, packed struct {}); - - /// backup register - pub const BKP13R = mmio(Address + 0x00000084, 32, packed struct {}); - - /// backup register - pub const BKP14R = mmio(Address + 0x00000088, 32, packed struct {}); - - /// backup register - pub const BKP15R = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// backup register - pub const BKP16R = mmio(Address + 0x00000090, 32, packed struct {}); - - /// backup register - pub const BKP17R = mmio(Address + 0x00000094, 32, packed struct {}); - - /// backup register - pub const BKP18R = mmio(Address + 0x00000098, 32, packed struct {}); - - /// backup register - pub const BKP19R = mmio(Address + 0x0000009c, 32, packed struct {}); - - /// backup register - pub const BKP20R = mmio(Address + 0x000000a0, 32, packed struct {}); - - /// backup register - pub const BKP21R = mmio(Address + 0x000000a4, 32, packed struct {}); - - /// backup register - pub const BKP22R = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// backup register - pub const BKP23R = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// backup register - pub const BKP24R = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// backup register - pub const BKP25R = mmio(Address + 0x000000b4, 32, packed struct {}); - - /// backup register - pub const BKP26R = mmio(Address + 0x000000b8, 32, packed struct {}); - - /// backup register - pub const BKP27R = mmio(Address + 0x000000bc, 32, packed struct {}); - - /// backup register - pub const BKP28R = mmio(Address + 0x000000c0, 32, packed struct {}); - - /// backup register - pub const BKP29R = mmio(Address + 0x000000c4, 32, packed struct {}); - - /// backup register - pub const BKP30R = mmio(Address + 0x000000c8, 32, packed struct {}); - - /// backup register - pub const BKP31R = mmio(Address + 0x000000cc, 32, packed struct {}); -}; - -/// Basic timers -pub const TIM6 = extern struct { - pub const Address: u32 = 0x40001000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Basic timers -pub const TIM7 = extern struct { - pub const Address: u32 = 0x40001400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - padding31: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// Low counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF Copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Low Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Digital-to-analog converter -pub const DAC = extern struct { - pub const Address: u32 = 0x40007400; - - /// control register - pub const CR = mmio(Address + 0x00000000, 32, packed struct { - /// DAC channel1 enable - EN1: u1 = 0, - /// DAC channel1 output buffer disable - BOFF1: u1 = 0, - /// DAC channel1 trigger enable - TEN1: u1 = 0, - /// DAC channel1 trigger selection - TSEL1: u3 = 0, - /// DAC channel1 noise/triangle wave generation enable - WAVE1: u2 = 0, - /// DAC channel1 mask/amplitude selector - MAMP1: u4 = 0, - /// DAC channel1 DMA enable - DMAEN1: u1 = 0, - /// DAC channel1 DMA Underrun Interrupt enable - DMAUDRIE1: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 enable - EN2: u1 = 0, - /// DAC channel2 output buffer disable - BOFF2: u1 = 0, - /// DAC channel2 trigger enable - TEN2: u1 = 0, - /// DAC channel2 trigger selection - TSEL2: u3 = 0, - /// DAC channel2 noise/triangle wave generation enable - WAVE2: u2 = 0, - /// DAC channel2 mask/amplitude selector - MAMP2: u4 = 0, - /// DAC channel2 DMA enable - DMAEN2: u1 = 0, - /// DAC channel2 DMA underrun interrupt enable - DMAUDRIE2: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// software trigger register - pub const SWTRIGR = mmio(Address + 0x00000004, 32, packed struct { - /// DAC channel1 software trigger - SWTRIG1: u1 = 0, - /// DAC channel2 software trigger - SWTRIG2: u1 = 0, - padding30: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 12-bit right-aligned data holding register - pub const DHR12R1 = mmio(Address + 0x00000008, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 12-bit left aligned data holding register - pub const DHR12L1 = mmio(Address + 0x0000000c, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 8-bit right aligned data holding register - pub const DHR8R1 = mmio(Address + 0x00000010, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 12-bit right aligned data holding register - pub const DHR12R2 = mmio(Address + 0x00000014, 32, packed struct { - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 12-bit left aligned data holding register - pub const DHR12L2 = mmio(Address + 0x00000018, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 8-bit right-aligned data holding register - pub const DHR8R2 = mmio(Address + 0x0000001c, 32, packed struct { - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Dual DAC 12-bit right-aligned data holding register - pub const DHR12RD = mmio(Address + 0x00000020, 32, packed struct { - /// DAC channel1 12-bit right-aligned data - DACC1DHR: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel2 12-bit right-aligned data - DACC2DHR: u12 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DUAL DAC 12-bit left aligned data holding register - pub const DHR12LD = mmio(Address + 0x00000024, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 12-bit left-aligned data - DACC1DHR: u12 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// DAC channel2 12-bit left-aligned data - DACC2DHR: u12 = 0, - }); - - /// DUAL DAC 8-bit right aligned data holding register - pub const DHR8RD = mmio(Address + 0x00000028, 32, packed struct { - /// DAC channel1 8-bit right-aligned data - DACC1DHR: u8 = 0, - /// DAC channel2 8-bit right-aligned data - DACC2DHR: u8 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel1 data output register - pub const DOR1 = mmio(Address + 0x0000002c, 32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// channel2 data output register - pub const DOR2 = mmio(Address + 0x00000030, 32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000034, 32, packed struct { - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DAC channel1 DMA underrun flag - DMAUDR1: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - /// DAC channel2 DMA underrun flag - DMAUDR2: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Debug support -pub const DBGMCU = extern struct { - pub const Address: u32 = 0xe0042000; - - /// MCU Device ID Code Register - pub const IDCODE = mmio(Address + 0x00000000, 32, packed struct { - /// Device Identifier - DEV_ID: u12 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Revision Identifier - REV_ID: u16 = 0, - }); - - /// Debug MCU Configuration Register - pub const CR = mmio(Address + 0x00000004, 32, packed struct { - /// Debug Sleep mode - DBG_SLEEP: u1 = 0, - /// Debug Stop Mode - DBG_STOP: u1 = 0, - /// Debug Standby Mode - DBG_STANDBY: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Trace pin assignment control - TRACE_IOEN: u1 = 0, - /// Trace pin assignment control - TRACE_MODE: u2 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB Low Freeze Register - pub const APB1FZ = mmio(Address + 0x00000008, 32, packed struct { - /// Debug Timer 2 stopped when Core is halted - DBG_TIM2_STOP: u1 = 0, - /// Debug Timer 3 stopped when Core is halted - DBG_TIM3_STOP: u1 = 0, - /// Debug Timer 4 stopped when Core is halted - DBG_TIM4_STOP: u1 = 0, - /// Debug Timer 5 stopped when Core is halted - DBG_TIM5_STOP: u1 = 0, - /// Debug Timer 6 stopped when Core is halted - DBG_TIM6_STOP: u1 = 0, - /// Debug Timer 7 stopped when Core is halted - DBG_TIM7_STOP: u1 = 0, - /// Debug Timer 12 stopped when Core is halted - DBG_TIM12_STOP: u1 = 0, - /// Debug Timer 13 stopped when Core is halted - DBG_TIM13_STOP: u1 = 0, - /// Debug Timer 14 stopped when Core is halted - DBG_TIMER14_STOP: u1 = 0, - /// Debug Timer 18 stopped when Core is halted - DBG_TIM18_STOP: u1 = 0, - /// Debug RTC stopped when Core is halted - DBG_RTC_STOP: u1 = 0, - /// Debug Window Wachdog stopped when Core is halted - DBG_WWDG_STOP: u1 = 0, - /// Debug Independent Wachdog stopped when Core is halted - DBG_IWDG_STOP: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// SMBUS timeout mode stopped when Core is halted - I2C1_SMBUS_TIMEOUT: u1 = 0, - /// SMBUS timeout mode stopped when Core is halted - I2C2_SMBUS_TIMEOUT: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - /// Debug CAN stopped when core is halted - DBG_CAN_STOP: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// APB High Freeze Register - pub const APB2FZ = mmio(Address + 0x0000000c, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Debug Timer 15 stopped when Core is halted - DBG_TIM15_STOP: u1 = 0, - /// Debug Timer 16 stopped when Core is halted - DBG_TIM16_STOP: u1 = 0, - /// Debug Timer 17 stopped when Core is halted - DBG_TIM17_STO: u1 = 0, - /// Debug Timer 19 stopped when Core is halted - DBG_TIM19_STOP: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM1 = extern struct { - pub const Address: u32 = 0x40012c00; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC1_RMP: u2 = 0, - /// TIM1_ETR_ADC4 remapping capability - TIM1_ETR_ADC4_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced timer -pub const TIM20 = extern struct { - pub const Address: u32 = 0x40015000; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM1_ETR_ADC1 remapping capability - TIM1_ETR_ADC1_RMP: u2 = 0, - /// TIM1_ETR_ADC4 remapping capability - TIM1_ETR_ADC4_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Advanced-timers -pub const TIM8 = extern struct { - pub const Address: u32 = 0x40013400; - - /// control register 1 - pub const CR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - CEN: u1 = 0, - /// Update disable - UDIS: u1 = 0, - /// Update request source - URS: u1 = 0, - /// One-pulse mode - OPM: u1 = 0, - /// Direction - DIR: u1 = 0, - /// Center-aligned mode selection - CMS: u2 = 0, - /// Auto-reload preload enable - ARPE: u1 = 0, - /// Clock division - CKD: u2 = 0, - reserved1: u1 = 0, - /// UIF status bit remapping - UIFREMAP: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register 2 - pub const CR2 = mmio(Address + 0x00000004, 32, packed struct { - /// Capture/compare preloaded control - CCPC: u1 = 0, - reserved1: u1 = 0, - /// Capture/compare control update selection - CCUS: u1 = 0, - /// Capture/compare DMA selection - CCDS: u1 = 0, - /// Master mode selection - MMS: u3 = 0, - /// TI1 selection - TI1S: u1 = 0, - /// Output Idle state 1 - OIS1: u1 = 0, - /// Output Idle state 1 - OIS1N: u1 = 0, - /// Output Idle state 2 - OIS2: u1 = 0, - /// Output Idle state 2 - OIS2N: u1 = 0, - /// Output Idle state 3 - OIS3: u1 = 0, - /// Output Idle state 3 - OIS3N: u1 = 0, - /// Output Idle state 4 - OIS4: u1 = 0, - reserved2: u1 = 0, - /// Output Idle state 5 - OIS5: u1 = 0, - reserved3: u1 = 0, - /// Output Idle state 6 - OIS6: u1 = 0, - reserved4: u1 = 0, - /// Master mode selection 2 - MMS2: u4 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// slave mode control register - pub const SMCR = mmio(Address + 0x00000008, 32, packed struct { - /// Slave mode selection - SMS: u3 = 0, - /// OCREF clear selection - OCCS: u1 = 0, - /// Trigger selection - TS: u3 = 0, - /// Master/Slave mode - MSM: u1 = 0, - /// External trigger filter - ETF: u4 = 0, - /// External trigger prescaler - ETPS: u2 = 0, - /// External clock enable - ECE: u1 = 0, - /// External trigger polarity - ETP: u1 = 0, - /// Slave mode selection bit 3 - SMS3: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA/Interrupt enable register - pub const DIER = mmio(Address + 0x0000000c, 32, packed struct { - /// Update interrupt enable - UIE: u1 = 0, - /// Capture/Compare 1 interrupt enable - CC1IE: u1 = 0, - /// Capture/Compare 2 interrupt enable - CC2IE: u1 = 0, - /// Capture/Compare 3 interrupt enable - CC3IE: u1 = 0, - /// Capture/Compare 4 interrupt enable - CC4IE: u1 = 0, - /// COM interrupt enable - COMIE: u1 = 0, - /// Trigger interrupt enable - TIE: u1 = 0, - /// Break interrupt enable - BIE: u1 = 0, - /// Update DMA request enable - UDE: u1 = 0, - /// Capture/Compare 1 DMA request enable - CC1DE: u1 = 0, - /// Capture/Compare 2 DMA request enable - CC2DE: u1 = 0, - /// Capture/Compare 3 DMA request enable - CC3DE: u1 = 0, - /// Capture/Compare 4 DMA request enable - CC4DE: u1 = 0, - /// COM DMA request enable - COMDE: u1 = 0, - /// Trigger DMA request enable - TDE: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// status register - pub const SR = mmio(Address + 0x00000010, 32, packed struct { - /// Update interrupt flag - UIF: u1 = 0, - /// Capture/compare 1 interrupt flag - CC1IF: u1 = 0, - /// Capture/Compare 2 interrupt flag - CC2IF: u1 = 0, - /// Capture/Compare 3 interrupt flag - CC3IF: u1 = 0, - /// Capture/Compare 4 interrupt flag - CC4IF: u1 = 0, - /// COM interrupt flag - COMIF: u1 = 0, - /// Trigger interrupt flag - TIF: u1 = 0, - /// Break interrupt flag - BIF: u1 = 0, - /// Break 2 interrupt flag - B2IF: u1 = 0, - /// Capture/Compare 1 overcapture flag - CC1OF: u1 = 0, - /// Capture/compare 2 overcapture flag - CC2OF: u1 = 0, - /// Capture/Compare 3 overcapture flag - CC3OF: u1 = 0, - /// Capture/Compare 4 overcapture flag - CC4OF: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 5 interrupt flag - C5IF: u1 = 0, - /// Capture/Compare 6 interrupt flag - C6IF: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// event generation register - pub const EGR = mmio(Address + 0x00000014, 32, packed struct { - /// Update generation - UG: u1 = 0, - /// Capture/compare 1 generation - CC1G: u1 = 0, - /// Capture/compare 2 generation - CC2G: u1 = 0, - /// Capture/compare 3 generation - CC3G: u1 = 0, - /// Capture/compare 4 generation - CC4G: u1 = 0, - /// Capture/Compare control update generation - COMG: u1 = 0, - /// Trigger generation - TG: u1 = 0, - /// Break generation - BG: u1 = 0, - /// Break 2 generation - B2G: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR1_Output = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Output Compare 1 fast enable - OC1FE: u1 = 0, - /// Output Compare 1 preload enable - OC1PE: u1 = 0, - /// Output Compare 1 mode - OC1M: u3 = 0, - /// Output Compare 1 clear enable - OC1CE: u1 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Output Compare 2 fast enable - OC2FE: u1 = 0, - /// Output Compare 2 preload enable - OC2PE: u1 = 0, - /// Output Compare 2 mode - OC2M: u3 = 0, - /// Output Compare 2 clear enable - OC2CE: u1 = 0, - /// Output Compare 1 mode bit 3 - OC1M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 2 mode bit 3 - OC2M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 1 (input mode) - pub const CCMR1_Input = mmio(Address + 0x00000018, 32, packed struct { - /// Capture/Compare 1 selection - CC1S: u2 = 0, - /// Input capture 1 prescaler - IC1PCS: u2 = 0, - /// Input capture 1 filter - IC1F: u4 = 0, - /// Capture/Compare 2 selection - CC2S: u2 = 0, - /// Input capture 2 prescaler - IC2PCS: u2 = 0, - /// Input capture 2 filter - IC2F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register (output mode) - pub const CCMR2_Output = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/Compare 3 selection - CC3S: u2 = 0, - /// Output compare 3 fast enable - OC3FE: u1 = 0, - /// Output compare 3 preload enable - OC3PE: u1 = 0, - /// Output compare 3 mode - OC3M: u3 = 0, - /// Output compare 3 clear enable - OC3CE: u1 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Output compare 4 fast enable - OC4FE: u1 = 0, - /// Output compare 4 preload enable - OC4PE: u1 = 0, - /// Output compare 4 mode - OC4M: u3 = 0, - /// Output compare 4 clear enable - OC4CE: u1 = 0, - /// Output Compare 3 mode bit 3 - OC3M_3: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output Compare 4 mode bit 3 - OC4M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 2 (input mode) - pub const CCMR2_Input = mmio(Address + 0x0000001c, 32, packed struct { - /// Capture/compare 3 selection - CC3S: u2 = 0, - /// Input capture 3 prescaler - IC3PSC: u2 = 0, - /// Input capture 3 filter - IC3F: u4 = 0, - /// Capture/Compare 4 selection - CC4S: u2 = 0, - /// Input capture 4 prescaler - IC4PSC: u2 = 0, - /// Input capture 4 filter - IC4F: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare enable register - pub const CCER = mmio(Address + 0x00000020, 32, packed struct { - /// Capture/Compare 1 output enable - CC1E: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1P: u1 = 0, - /// Capture/Compare 1 complementary output enable - CC1NE: u1 = 0, - /// Capture/Compare 1 output Polarity - CC1NP: u1 = 0, - /// Capture/Compare 2 output enable - CC2E: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2P: u1 = 0, - /// Capture/Compare 2 complementary output enable - CC2NE: u1 = 0, - /// Capture/Compare 2 output Polarity - CC2NP: u1 = 0, - /// Capture/Compare 3 output enable - CC3E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3P: u1 = 0, - /// Capture/Compare 3 complementary output enable - CC3NE: u1 = 0, - /// Capture/Compare 3 output Polarity - CC3NP: u1 = 0, - /// Capture/Compare 4 output enable - CC4E: u1 = 0, - /// Capture/Compare 3 output Polarity - CC4P: u1 = 0, - reserved1: u1 = 0, - /// Capture/Compare 4 output Polarity - CC4NP: u1 = 0, - /// Capture/Compare 5 output enable - CC5E: u1 = 0, - /// Capture/Compare 5 output Polarity - CC5P: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Capture/Compare 6 output enable - CC6E: u1 = 0, - /// Capture/Compare 6 output Polarity - CC6P: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// counter - pub const CNT = mmio(Address + 0x00000024, 32, packed struct { - /// counter value - CNT: u16 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// UIF copy - UIFCPY: u1 = 0, - }); - - /// prescaler - pub const PSC = mmio(Address + 0x00000028, 32, packed struct { - /// Prescaler value - PSC: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// auto-reload register - pub const ARR = mmio(Address + 0x0000002c, 32, packed struct { - /// Auto-reload value - ARR: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// repetition counter register - pub const RCR = mmio(Address + 0x00000030, 32, packed struct { - /// Repetition counter value - REP: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 1 - pub const CCR1 = mmio(Address + 0x00000034, 32, packed struct { - /// Capture/Compare 1 value - CCR1: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 2 - pub const CCR2 = mmio(Address + 0x00000038, 32, packed struct { - /// Capture/Compare 2 value - CCR2: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 3 - pub const CCR3 = mmio(Address + 0x0000003c, 32, packed struct { - /// Capture/Compare 3 value - CCR3: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 4 - pub const CCR4 = mmio(Address + 0x00000040, 32, packed struct { - /// Capture/Compare 3 value - CCR4: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// break and dead-time register - pub const BDTR = mmio(Address + 0x00000044, 32, packed struct { - /// Dead-time generator setup - DTG: u8 = 0, - /// Lock configuration - LOCK: u2 = 0, - /// Off-state selection for Idle mode - OSSI: u1 = 0, - /// Off-state selection for Run mode - OSSR: u1 = 0, - /// Break enable - BKE: u1 = 0, - /// Break polarity - BKP: u1 = 0, - /// Automatic output enable - AOE: u1 = 0, - /// Main output enable - MOE: u1 = 0, - /// Break filter - BKF: u4 = 0, - /// Break 2 filter - BK2F: u4 = 0, - /// Break 2 enable - BK2E: u1 = 0, - /// Break 2 polarity - BK2P: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA control register - pub const DCR = mmio(Address + 0x00000048, 32, packed struct { - /// DMA base address - DBA: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// DMA burst length - DBL: u5 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// DMA address for full transfer - pub const DMAR = mmio(Address + 0x0000004c, 32, packed struct { - /// DMA register for burst accesses - DMAB: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare mode register 3 (output mode) - pub const CCMR3_Output = mmio(Address + 0x00000054, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Output compare 5 fast enable - OC5FE: u1 = 0, - /// Output compare 5 preload enable - OC5PE: u1 = 0, - /// Output compare 5 mode - OC5M: u3 = 0, - /// Output compare 5 clear enable - OC5CE: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Output compare 6 fast enable - OC6FE: u1 = 0, - /// Output compare 6 preload enable - OC6PE: u1 = 0, - /// Output compare 6 mode - OC6M: u3 = 0, - /// Output compare 6 clear enable - OC6CE: u1 = 0, - /// Outout Compare 5 mode bit 3 - OC5M_3: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Outout Compare 6 mode bit 3 - OC6M_3: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// capture/compare register 5 - pub const CCR5 = mmio(Address + 0x00000058, 32, packed struct { - /// Capture/Compare 5 value - CCR5: u16 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Group Channel 5 and Channel 1 - GC5C1: u1 = 0, - /// Group Channel 5 and Channel 2 - GC5C2: u1 = 0, - /// Group Channel 5 and Channel 3 - GC5C3: u1 = 0, - }); - - /// capture/compare register 6 - pub const CCR6 = mmio(Address + 0x0000005c, 32, packed struct { - /// Capture/Compare 6 value - CCR6: u16 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// option registers - pub const OR = mmio(Address + 0x00000060, 32, packed struct { - /// TIM8_ETR_ADC2 remapping capability - TIM8_ETR_ADC2_RMP: u2 = 0, - /// TIM8_ETR_ADC3 remapping capability - TIM8_ETR_ADC3_RMP: u2 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC1 = extern struct { - pub const Address: u32 = 0x50000000; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC2 = extern struct { - pub const Address: u32 = 0x50000100; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC3 = extern struct { - pub const Address: u32 = 0x50000400; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC4 = extern struct { - pub const Address: u32 = 0x50000500; - - /// interrupt and status register - pub const ISR = mmio(Address + 0x00000000, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// interrupt enable register - pub const IER = mmio(Address + 0x00000004, 32, packed struct { - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control register - pub const CR = mmio(Address + 0x00000008, 32, packed struct { - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// configuration register - pub const CFGR = mmio(Address + 0x0000000c, 32, packed struct { - reserved1: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 1 - pub const SMPR1 = mmio(Address + 0x00000014, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// sample time register 2 - pub const SMPR2 = mmio(Address + 0x00000018, 32, packed struct { - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 1 - pub const TR1 = mmio(Address + 0x00000020, 32, packed struct { - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register - pub const TR2 = mmio(Address + 0x00000024, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// watchdog threshold register 3 - pub const TR3 = mmio(Address + 0x00000028, 32, packed struct { - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 1 - pub const SQR1 = mmio(Address + 0x00000030, 32, packed struct { - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 2 - pub const SQR2 = mmio(Address + 0x00000034, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 3 - pub const SQR3 = mmio(Address + 0x00000038, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular sequence register 4 - pub const SQR4 = mmio(Address + 0x0000003c, 32, packed struct { - reserved1: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// regular Data Register - pub const DR = mmio(Address + 0x00000040, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected sequence register - pub const JSQR = mmio(Address + 0x0000004c, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - padding1: u1 = 0, - }); - - /// offset register 1 - pub const OFR1 = mmio(Address + 0x00000060, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 2 - pub const OFR2 = mmio(Address + 0x00000064, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 3 - pub const OFR3 = mmio(Address + 0x00000068, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// offset register 4 - pub const OFR4 = mmio(Address + 0x0000006c, 32, packed struct { - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - }); - - /// injected data register 1 - pub const JDR1 = mmio(Address + 0x00000080, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 2 - pub const JDR2 = mmio(Address + 0x00000084, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 3 - pub const JDR3 = mmio(Address + 0x00000088, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// injected data register 4 - pub const JDR4 = mmio(Address + 0x0000008c, 32, packed struct { - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 2 Configuration Register - pub const AWD2CR = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Analog Watchdog 3 Configuration Register - pub const AWD3CR = mmio(Address + 0x000000a4, 32, packed struct { - reserved1: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Differential Mode Selection Register 2 - pub const DIFSEL = mmio(Address + 0x000000b0, 32, packed struct { - reserved1: u1 = 0, - /// Differential mode for channels 15 to 1 - DIFSEL_1_15: u15 = 0, - /// Differential mode for channels 18 to 16 - DIFSEL_16_18: u3 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Calibration Factors - pub const CALFACT = mmio(Address + 0x000000b4, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC1_2 = extern struct { - pub const Address: u32 = 0x50000300; - - /// ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// End of regular conversion of the slave ADC - EOC_SLV: u1 = 0, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1 = 0, - /// Overrun flag of the slave ADC - OVR_SLV: u1 = 0, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1 = 0, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1 = 0, - /// Analog watchdog 1 flag of the slave ADC - AWD1_SLV: u1 = 0, - /// Analog watchdog 2 flag of the slave ADC - AWD2_SLV: u1 = 0, - /// Analog watchdog 3 flag of the slave ADC - AWD3_SLV: u1 = 0, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - /// Multi ADC mode selection - MULT: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Delay between 2 sampling phases - DELAY: u4 = 0, - reserved4: u1 = 0, - /// DMA configuration (for multi-ADC mode) - DMACFG: u1 = 0, - /// Direct memory access mode for multi ADC mode - MDMA: u2 = 0, - /// ADC clock mode - CKMODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// VREFINT enable - VREFEN: u1 = 0, - /// Temperature sensor enable - TSEN: u1 = 0, - /// VBAT enable - VBATEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Regular data of the master ADC - RDATA_MST: u16 = 0, - /// Regular data of the slave ADC - RDATA_SLV: u16 = 0, - }); -}; - -/// Analog-to-Digital Converter -pub const ADC3_4 = extern struct { - pub const Address: u32 = 0x50000700; - - /// ADC Common status register - pub const CSR = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// End of regular conversion of the slave ADC - EOC_SLV: u1 = 0, - /// End of regular sequence flag of the slave ADC - EOS_SLV: u1 = 0, - /// Overrun flag of the slave ADC - OVR_SLV: u1 = 0, - /// End of injected conversion flag of the slave ADC - JEOC_SLV: u1 = 0, - /// End of injected sequence flag of the slave ADC - JEOS_SLV: u1 = 0, - /// Analog watchdog 1 flag of the slave ADC - AWD1_SLV: u1 = 0, - /// Analog watchdog 2 flag of the slave ADC - AWD2_SLV: u1 = 0, - /// Analog watchdog 3 flag of the slave ADC - AWD3_SLV: u1 = 0, - /// Injected Context Queue Overflow flag of the slave ADC - JQOVF_SLV: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common control register - pub const CCR = mmio(Address + 0x00000008, 32, packed struct { - /// Multi ADC mode selection - MULT: u5 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Delay between 2 sampling phases - DELAY: u4 = 0, - reserved4: u1 = 0, - /// DMA configuration (for multi-ADC mode) - DMACFG: u1 = 0, - /// Direct memory access mode for multi ADC mode - MDMA: u2 = 0, - /// ADC clock mode - CKMODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// VREFINT enable - VREFEN: u1 = 0, - /// Temperature sensor enable - TSEN: u1 = 0, - /// VBAT enable - VBATEN: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// ADC common regular data register for dual and triple modes - pub const CDR = mmio(Address + 0x0000000c, 32, packed struct { - /// Regular data of the master ADC - RDATA_MST: u16 = 0, - /// Regular data of the slave ADC - RDATA_SLV: u16 = 0, - }); -}; - -/// System configuration controller _Comparator and Operational amplifier -pub const SYSCFG_COMP_OPAMP = extern struct { - pub const Address: u32 = 0x40010000; - - /// configuration register 1 - pub const SYSCFG_CFGR1 = mmio(Address + 0x00000000, 32, packed struct { - /// Memory mapping selection bits - MEM_MODE: u2 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// USB interrupt remap - USB_IT_RMP: u1 = 0, - /// Timer 1 ITR3 selection - TIM1_ITR_RMP: u1 = 0, - /// DAC trigger remap (when TSEL = 001) - DAC_TRIG_RMP: u1 = 0, - /// ADC24 DMA remapping bit - ADC24_DMA_RMP: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// TIM16 DMA request remapping bit - TIM16_DMA_RMP: u1 = 0, - /// TIM17 DMA request remapping bit - TIM17_DMA_RMP: u1 = 0, - /// TIM6 and DAC1 DMA request remapping bit - TIM6_DAC1_DMA_RMP: u1 = 0, - /// TIM7 and DAC2 DMA request remapping bit - TIM7_DAC2_DMA_RMP: u1 = 0, - reserved6: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB6_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB7_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB8_FM: u1 = 0, - /// Fast Mode Plus (FM+) driving capability activation bits. - I2C_PB9_FM: u1 = 0, - /// I2C1 Fast Mode Plus - I2C1_FM: u1 = 0, - /// I2C2 Fast Mode Plus - I2C2_FM: u1 = 0, - /// Encoder mode - ENCODER_MODE: u2 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - /// Interrupt enable bits from FPU - FPU_IT: u6 = 0, - }); - - /// CCM SRAM protection register - pub const SYSCFG_RCR = mmio(Address + 0x00000004, 32, packed struct { - /// CCM SRAM page write protection bit - PAGE0_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE1_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE2_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE3_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE4_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE5_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE6_WP: u1 = 0, - /// CCM SRAM page write protection bit - PAGE7_WP: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 1 - pub const SYSCFG_EXTICR1 = mmio(Address + 0x00000008, 32, packed struct { - /// EXTI 0 configuration bits - EXTI0: u4 = 0, - /// EXTI 1 configuration bits - EXTI1: u4 = 0, - /// EXTI 2 configuration bits - EXTI2: u4 = 0, - /// EXTI 3 configuration bits - EXTI3: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 2 - pub const SYSCFG_EXTICR2 = mmio(Address + 0x0000000c, 32, packed struct { - /// EXTI 4 configuration bits - EXTI4: u4 = 0, - /// EXTI 5 configuration bits - EXTI5: u4 = 0, - /// EXTI 6 configuration bits - EXTI6: u4 = 0, - /// EXTI 7 configuration bits - EXTI7: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 3 - pub const SYSCFG_EXTICR3 = mmio(Address + 0x00000010, 32, packed struct { - /// EXTI 8 configuration bits - EXTI8: u4 = 0, - /// EXTI 9 configuration bits - EXTI9: u4 = 0, - /// EXTI 10 configuration bits - EXTI10: u4 = 0, - /// EXTI 11 configuration bits - EXTI11: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// external interrupt configuration register 4 - pub const SYSCFG_EXTICR4 = mmio(Address + 0x00000014, 32, packed struct { - /// EXTI 12 configuration bits - EXTI12: u4 = 0, - /// EXTI 13 configuration bits - EXTI13: u4 = 0, - /// EXTI 14 configuration bits - EXTI14: u4 = 0, - /// EXTI 15 configuration bits - EXTI15: u4 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// configuration register 2 - pub const SYSCFG_CFGR2 = mmio(Address + 0x00000018, 32, packed struct { - /// Cortex-M0 LOCKUP bit enable bit - LOCUP_LOCK: u1 = 0, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1 = 0, - /// PVD lock enable bit - PVD_LOCK: u1 = 0, - reserved1: u1 = 0, - /// Bypass address bit 29 in parity calculation - BYP_ADD_PAR: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// SRAM parity flag - SRAM_PEF: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// control and status register - pub const COMP1_CSR = mmio(Address + 0x0000001c, 32, packed struct { - /// Comparator 1 enable - COMP1EN: u1 = 0, - /// Comparator 1 mode - COMP1MODE: u2 = 0, - /// Comparator 1 inverting input selection - COMP1INSEL: u3 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Comparator 1 output selection - COMP1_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 1 output polarity - COMP1POL: u1 = 0, - /// Comparator 1 hysteresis - COMP1HYST: u2 = 0, - /// Comparator 1 blanking source - COMP1_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 1 output - COMP1OUT: u1 = 0, - /// Comparator 1 lock - COMP1LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP2_CSR = mmio(Address + 0x00000020, 32, packed struct { - /// Comparator 2 enable - COMP2EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 2 mode - COMP2MODE: u2 = 0, - /// Comparator 2 inverting input selection - COMP2INSEL: u3 = 0, - /// Comparator 2 non inverted input selection - COMP2INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 1inverting input selection - COMP2INMSEL: u1 = 0, - /// Comparator 2 output selection - COMP2_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 2 output polarity - COMP2POL: u1 = 0, - /// Comparator 2 hysteresis - COMP2HYST: u2 = 0, - /// Comparator 2 blanking source - COMP2_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 2 lock - COMP2LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP3_CSR = mmio(Address + 0x00000024, 32, packed struct { - /// Comparator 3 enable - COMP3EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 3 mode - COMP3MODE: u2 = 0, - /// Comparator 3 inverting input selection - COMP3INSEL: u3 = 0, - /// Comparator 3 non inverted input selection - COMP3INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 3 output selection - COMP3_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 3 output polarity - COMP3POL: u1 = 0, - /// Comparator 3 hysteresis - COMP3HYST: u2 = 0, - /// Comparator 3 blanking source - COMP3_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 3 output - COMP3OUT: u1 = 0, - /// Comparator 3 lock - COMP3LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP4_CSR = mmio(Address + 0x00000028, 32, packed struct { - /// Comparator 4 enable - COMP4EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 4 mode - COMP4MODE: u2 = 0, - /// Comparator 4 inverting input selection - COMP4INSEL: u3 = 0, - /// Comparator 4 non inverted input selection - COMP4INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 4 window mode - COM4WINMODE: u1 = 0, - /// Comparator 4 output selection - COMP4_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 4 output polarity - COMP4POL: u1 = 0, - /// Comparator 4 hysteresis - COMP4HYST: u2 = 0, - /// Comparator 4 blanking source - COMP4_BLANKING: u3 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 4 output - COMP4OUT: u1 = 0, - /// Comparator 4 lock - COMP4LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP5_CSR = mmio(Address + 0x0000002c, 32, packed struct { - /// Comparator 5 enable - COMP5EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 5 mode - COMP5MODE: u2 = 0, - /// Comparator 5 inverting input selection - COMP5INSEL: u3 = 0, - /// Comparator 5 non inverted input selection - COMP5INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 5 output selection - COMP5_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 5 output polarity - COMP5POL: u1 = 0, - /// Comparator 5 hysteresis - COMP5HYST: u2 = 0, - /// Comparator 5 blanking source - COMP5_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator51 output - COMP5OUT: u1 = 0, - /// Comparator 5 lock - COMP5LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP6_CSR = mmio(Address + 0x00000030, 32, packed struct { - /// Comparator 6 enable - COMP6EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 6 mode - COMP6MODE: u2 = 0, - /// Comparator 6 inverting input selection - COMP6INSEL: u3 = 0, - /// Comparator 6 non inverted input selection - COMP6INPSEL: u1 = 0, - reserved2: u1 = 0, - /// Comparator 6 window mode - COM6WINMODE: u1 = 0, - /// Comparator 6 output selection - COMP6_OUT_SEL: u4 = 0, - reserved3: u1 = 0, - /// Comparator 6 output polarity - COMP6POL: u1 = 0, - /// Comparator 6 hysteresis - COMP6HYST: u2 = 0, - /// Comparator 6 blanking source - COMP6_BLANKING: u3 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - /// Comparator 6 output - COMP6OUT: u1 = 0, - /// Comparator 6 lock - COMP6LOCK: u1 = 0, - }); - - /// control and status register - pub const COMP7_CSR = mmio(Address + 0x00000034, 32, packed struct { - /// Comparator 7 enable - COMP7EN: u1 = 0, - reserved1: u1 = 0, - /// Comparator 7 mode - COMP7MODE: u2 = 0, - /// Comparator 7 inverting input selection - COMP7INSEL: u3 = 0, - /// Comparator 7 non inverted input selection - COMP7INPSEL: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Comparator 7 output selection - COMP7_OUT_SEL: u4 = 0, - reserved4: u1 = 0, - /// Comparator 7 output polarity - COMP7POL: u1 = 0, - /// Comparator 7 hysteresis - COMP7HYST: u2 = 0, - /// Comparator 7 blanking source - COMP7_BLANKING: u3 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Comparator 7 output - COMP7OUT: u1 = 0, - /// Comparator 7 lock - COMP7LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP1_CSR = mmio(Address + 0x00000038, 32, packed struct { - /// OPAMP1 enable - OPAMP1_EN: u1 = 0, - /// OPAMP1 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP1 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP1 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP1 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 1 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 1 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP2_CSR = mmio(Address + 0x0000003c, 32, packed struct { - /// OPAMP2 enable - OPAMP2EN: u1 = 0, - /// OPAMP2 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP2 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP2 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP2 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CAL_SEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 2 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 2 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP3_CSR = mmio(Address + 0x00000040, 32, packed struct { - /// OPAMP3 enable - OPAMP3EN: u1 = 0, - /// OPAMP3 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP3 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP3 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP3 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 3 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 3 lock - LOCK: u1 = 0, - }); - - /// control register - pub const OPAMP4_CSR = mmio(Address + 0x00000044, 32, packed struct { - /// OPAMP4 enable - OPAMP4EN: u1 = 0, - /// OPAMP4 Non inverting input selection - VP_SEL: u2 = 0, - reserved1: u1 = 0, - /// OPAMP4 inverting input selection - VM_SEL: u2 = 0, - /// Timer controlled Mux mode enable - TCM_EN: u1 = 0, - /// OPAMP4 inverting input secondary selection - VMS_SEL: u1 = 0, - /// OPAMP4 Non inverting input secondary selection - VPS_SEL: u2 = 0, - /// Calibration mode enable - CALON: u1 = 0, - /// Calibration selection - CALSEL: u2 = 0, - /// Gain in PGA mode - PGA_GAIN: u4 = 0, - /// User trimming enable - USER_TRIM: u1 = 0, - /// Offset trimming value (PMOS) - TRIMOFFSETP: u5 = 0, - /// Offset trimming value (NMOS) - TRIMOFFSETN: u5 = 0, - /// OPAMP 4 ouput status flag - OUTCAL: u1 = 0, - /// OPAMP 4 lock - LOCK: u1 = 0, - }); -}; - -/// Flexible memory controller -pub const FMC = extern struct { - pub const Address: u32 = 0xa0000400; - - /// SRAM/NOR-Flash chip-select control register 1 - pub const BCR1 = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 1 - pub const BTR1 = mmio(Address + 0x00000004, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 2 - pub const BCR2 = mmio(Address + 0x00000008, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 2 - pub const BTR2 = mmio(Address + 0x0000000c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 3 - pub const BCR3 = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 3 - pub const BTR3 = mmio(Address + 0x00000014, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select control register 4 - pub const BCR4 = mmio(Address + 0x00000018, 32, packed struct { - reserved1: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash chip-select timing register 4 - pub const BTR4 = mmio(Address + 0x0000001c, 32, packed struct { - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// PC Card/NAND Flash control register 2 - pub const PCR2 = mmio(Address + 0x00000060, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 2 - pub const SR2 = mmio(Address + 0x00000064, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 2 - pub const PMEM2 = mmio(Address + 0x00000068, 32, packed struct {}); - - /// Attribute memory space timing register 2 - pub const PATT2 = mmio(Address + 0x0000006c, 32, packed struct {}); - - /// ECC result register 2 - pub const ECCR2 = mmio(Address + 0x00000074, 32, packed struct {}); - - /// PC Card/NAND Flash control register 3 - pub const PCR3 = mmio(Address + 0x00000080, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 3 - pub const SR3 = mmio(Address + 0x00000084, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 3 - pub const PMEM3 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Attribute memory space timing register 3 - pub const PATT3 = mmio(Address + 0x0000008c, 32, packed struct {}); - - /// ECC result register 3 - pub const ECCR3 = mmio(Address + 0x00000094, 32, packed struct {}); - - /// PC Card/NAND Flash control register 4 - pub const PCR4 = mmio(Address + 0x000000a0, 32, packed struct { - reserved1: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// FIFO status and interrupt register 4 - pub const SR4 = mmio(Address + 0x000000a4, 32, packed struct { - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Common memory space timing register 4 - pub const PMEM4 = mmio(Address + 0x000000a8, 32, packed struct {}); - - /// Attribute memory space timing register 4 - pub const PATT4 = mmio(Address + 0x000000ac, 32, packed struct {}); - - /// I/O space timing register 4 - pub const PIO4 = mmio(Address + 0x000000b0, 32, packed struct {}); - - /// SRAM/NOR-Flash write timing registers 1 - pub const BWTR1 = mmio(Address + 0x00000104, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 2 - pub const BWTR2 = mmio(Address + 0x0000010c, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 3 - pub const BWTR3 = mmio(Address + 0x00000114, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SRAM/NOR-Flash write timing registers 4 - pub const BWTR4 = mmio(Address + 0x0000011c, 32, packed struct { - /// Bus turnaround phase duration - BUSTURN: u4 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Nested Vectored Interrupt Controller -pub const NVIC = extern struct { - pub const Address: u32 = 0xe000e100; - - /// Interrupt Set-Enable Register - pub const ISER0 = mmio(Address + 0x00000000, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER1 = mmio(Address + 0x00000004, 32, packed struct {}); - - /// Interrupt Set-Enable Register - pub const ISER2 = mmio(Address + 0x00000008, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER0 = mmio(Address + 0x00000080, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER1 = mmio(Address + 0x00000084, 32, packed struct {}); - - /// Interrupt Clear-Enable Register - pub const ICER2 = mmio(Address + 0x00000088, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR0 = mmio(Address + 0x00000100, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR1 = mmio(Address + 0x00000104, 32, packed struct {}); - - /// Interrupt Set-Pending Register - pub const ISPR2 = mmio(Address + 0x00000108, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR0 = mmio(Address + 0x00000180, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR1 = mmio(Address + 0x00000184, 32, packed struct {}); - - /// Interrupt Clear-Pending Register - pub const ICPR2 = mmio(Address + 0x00000188, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR0 = mmio(Address + 0x00000200, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR1 = mmio(Address + 0x00000204, 32, packed struct {}); - - /// Interrupt Active Bit Register - pub const IABR2 = mmio(Address + 0x00000208, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR0 = mmio(Address + 0x00000300, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR1 = mmio(Address + 0x00000304, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR2 = mmio(Address + 0x00000308, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR3 = mmio(Address + 0x0000030c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR4 = mmio(Address + 0x00000310, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR5 = mmio(Address + 0x00000314, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR6 = mmio(Address + 0x00000318, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR7 = mmio(Address + 0x0000031c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR8 = mmio(Address + 0x00000320, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR9 = mmio(Address + 0x00000324, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR10 = mmio(Address + 0x00000328, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR11 = mmio(Address + 0x0000032c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR12 = mmio(Address + 0x00000330, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR13 = mmio(Address + 0x00000334, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR14 = mmio(Address + 0x00000338, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR15 = mmio(Address + 0x0000033c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR16 = mmio(Address + 0x00000340, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR17 = mmio(Address + 0x00000344, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR18 = mmio(Address + 0x00000348, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR19 = mmio(Address + 0x0000034c, 32, packed struct {}); - - /// Interrupt Priority Register - pub const IPR20 = mmio(Address + 0x00000350, 32, packed struct {}); -}; - -/// Floting point unit -pub const FPU = extern struct { - pub const Address: u32 = 0xe000ef34; - - /// Floating-point context control register - pub const FPCCR = mmio(Address + 0x00000000, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - }); - - /// Floating-point context address register - pub const FPCAR = mmio(Address + 0x00000004, 32, packed struct { - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Location of unpopulated floating-point - ADDRESS: u29 = 0, - }); - - /// Floating-point status control register - pub const FPSCR = mmio(Address + 0x00000008, 32, packed struct { - /// Invalid operation cumulative exception bit - IOC: u1 = 0, - /// Division by zero cumulative exception bit. - DZC: u1 = 0, - /// Overflow cumulative exception bit - OFC: u1 = 0, - /// Underflow cumulative exception bit - UFC: u1 = 0, - /// Inexact cumulative exception bit - IXC: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Input denormal cumulative exception bit. - IDC: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Rounding Mode control field - RMode: u2 = 0, - /// Flush-to-zero mode control bit: - FZ: u1 = 0, - /// Default NaN mode control bit - DN: u1 = 0, - /// Alternative half-precision control bit - AHP: u1 = 0, - reserved17: u1 = 0, - /// Overflow condition code flag - V: u1 = 0, - /// Carry condition code flag - C: u1 = 0, - /// Zero condition code flag - Z: u1 = 0, - /// Negative condition code flag - N: u1 = 0, - }); -}; - -/// Memory protection unit -pub const MPU = extern struct { - pub const Address: u32 = 0xe000ed90; - - /// MPU type register - pub const MPU_TYPER = mmio(Address + 0x00000000, 32, packed struct { - /// Separate flag - SEPARATE: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Number of MPU data regions - DREGION: u8 = 0, - /// Number of MPU instruction regions - IREGION: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU control register - pub const MPU_CTRL = mmio(Address + 0x00000004, 32, packed struct { - /// Enables the MPU - ENABLE: u1 = 0, - /// Enables the operation of MPU during hard fault - HFNMIENA: u1 = 0, - /// Enable priviliged software access to default memory map - PRIVDEFENA: u1 = 0, - padding29: u1 = 0, - padding28: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU region number register - pub const MPU_RNR = mmio(Address + 0x00000008, 32, packed struct { - /// MPU region - REGION: u8 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// MPU region base address register - pub const MPU_RBAR = mmio(Address + 0x0000000c, 32, packed struct { - /// MPU region field - REGION: u4 = 0, - /// MPU region number valid - VALID: u1 = 0, - /// Region base address field - ADDR: u27 = 0, - }); - - /// MPU region attribute and size register - pub const MPU_RASR = mmio(Address + 0x00000010, 32, packed struct { - /// Region enable bit. - ENABLE: u1 = 0, - /// Size of the MPU protection region - SIZE: u5 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Subregion disable bits - SRD: u8 = 0, - /// memory attribute - B: u1 = 0, - /// memory attribute - C: u1 = 0, - /// Shareable memory attribute - S: u1 = 0, - /// memory attribute - TEX: u3 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Access permission - AP: u3 = 0, - reserved5: u1 = 0, - /// Instruction access disable bit - XN: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// SysTick timer -pub const STK = extern struct { - pub const Address: u32 = 0xe000e010; - - /// SysTick control and status register - pub const CTRL = mmio(Address + 0x00000000, 32, packed struct { - /// Counter enable - ENABLE: u1 = 0, - /// SysTick exception request enable - TICKINT: u1 = 0, - /// Clock source selection - CLKSOURCE: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick reload value register - pub const LOAD = mmio(Address + 0x00000004, 32, packed struct { - /// RELOAD value - RELOAD: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick current value register - pub const VAL = mmio(Address + 0x00000008, 32, packed struct { - /// Current counter value - CURRENT: u24 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// SysTick calibration value register - pub const CALIB = mmio(Address + 0x0000000c, 32, packed struct { - /// Calibration value - TENMS: u24 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// SKEW flag: Indicates whether the TENMS value is exact - SKEW: u1 = 0, - /// NOREF flag. Reads as zero - NOREF: u1 = 0, - }); -}; - -/// System control block -pub const SCB = extern struct { - pub const Address: u32 = 0xe000ed00; - - /// CPUID base register - pub const CPUID = mmio(Address + 0x00000000, 32, packed struct { - /// Revision number - Revision: u4 = 0, - /// Part number of the processor - PartNo: u12 = 0, - /// Reads as 0xF - Constant: u4 = 0, - /// Variant number - Variant: u4 = 0, - /// Implementer code - Implementer: u8 = 0, - }); - - /// Interrupt control and state register - pub const ICSR = mmio(Address + 0x00000004, 32, packed struct { - /// Active vector - VECTACTIVE: u9 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Return to base level - RETTOBASE: u1 = 0, - /// Pending vector - VECTPENDING: u7 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - /// Interrupt pending flag - ISRPENDING: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// SysTick exception clear-pending bit - PENDSTCLR: u1 = 0, - /// SysTick exception set-pending bit - PENDSTSET: u1 = 0, - /// PendSV clear-pending bit - PENDSVCLR: u1 = 0, - /// PendSV set-pending bit - PENDSVSET: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - /// NMI set-pending bit. - NMIPENDSET: u1 = 0, - }); - - /// Vector table offset register - pub const VTOR = mmio(Address + 0x00000008, 32, packed struct { - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Vector table base offset field - TBLOFF: u21 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Application interrupt and reset control register - pub const AIRCR = mmio(Address + 0x0000000c, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - /// Register key - VECTKEYSTAT: u16 = 0, - }); - - /// System control register - pub const SCR = mmio(Address + 0x00000010, 32, packed struct { - reserved1: u1 = 0, - reserved2: u1 = 0, - /// Send Event on Pending bit - SEVEONPEND: u1 = 0, - padding27: u1 = 0, - padding26: u1 = 0, - padding25: u1 = 0, - padding24: u1 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configuration and control register - pub const CCR = mmio(Address + 0x00000014, 32, packed struct { - /// Configures how the processor enters Thread mode - NONBASETHRDENA: u1 = 0, - reserved1: u1 = 0, - /// UNALIGN_ TRP - UNALIGN__TRP: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System handler priority registers - pub const SHPR1 = mmio(Address + 0x00000018, 32, packed struct { - /// Priority of system handler 4 - PRI_4: u8 = 0, - /// Priority of system handler 5 - PRI_5: u8 = 0, - /// Priority of system handler 6 - PRI_6: u8 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// System handler priority registers - pub const SHPR2 = mmio(Address + 0x0000001c, 32, packed struct { - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Priority of system handler 11 - PRI_11: u8 = 0, - }); - - /// System handler priority registers - pub const SHPR3 = mmio(Address + 0x00000020, 32, packed struct { - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - /// Priority of system handler 14 - PRI_14: u8 = 0, - /// Priority of system handler 15 - PRI_15: u8 = 0, - }); - - /// System handler control and state register - pub const SHCRS = mmio(Address + 0x00000024, 32, packed struct { - /// Memory management fault exception active bit - MEMFAULTACT: u1 = 0, - /// Bus fault exception active bit - BUSFAULTACT: u1 = 0, - reserved1: u1 = 0, - /// Usage fault exception active bit - USGFAULTACT: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// SVC call active bit - SVCALLACT: u1 = 0, - /// Debug monitor active bit - MONITORACT: u1 = 0, - reserved5: u1 = 0, - /// PendSV exception active bit - PENDSVACT: u1 = 0, - /// SysTick exception active bit - SYSTICKACT: u1 = 0, - /// Usage fault exception pending bit - USGFAULTPENDED: u1 = 0, - /// Memory management fault exception pending bit - MEMFAULTPENDED: u1 = 0, - /// Bus fault exception pending bit - BUSFAULTPENDED: u1 = 0, - /// SVC call pending bit - SVCALLPENDED: u1 = 0, - /// Memory management fault enable bit - MEMFAULTENA: u1 = 0, - /// Bus fault enable bit - BUSFAULTENA: u1 = 0, - /// Usage fault enable bit - USGFAULTENA: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Configurable fault status register - pub const CFSR_UFSR_BFSR_MMFSR = mmio(Address + 0x00000028, 32, packed struct { - reserved1: u1 = 0, - /// Instruction access violation flag - IACCVIOL: u1 = 0, - reserved2: u1 = 0, - /// Memory manager fault on unstacking for a return from exception - MUNSTKERR: u1 = 0, - /// Memory manager fault on stacking for exception entry. - MSTKERR: u1 = 0, - reserved3: u1 = 0, - /// Memory Management Fault Address Register (MMAR) valid flag - MMARVALID: u1 = 0, - /// Instruction bus error - IBUSERR: u1 = 0, - /// Precise data bus error - PRECISERR: u1 = 0, - /// Imprecise data bus error - IMPRECISERR: u1 = 0, - /// Bus fault on unstacking for a return from exception - UNSTKERR: u1 = 0, - /// Bus fault on stacking for exception entry - STKERR: u1 = 0, - /// Bus fault on floating-point lazy state preservation - LSPERR: u1 = 0, - reserved4: u1 = 0, - /// Bus Fault Address Register (BFAR) valid flag - BFARVALID: u1 = 0, - /// Undefined instruction usage fault - UNDEFINSTR: u1 = 0, - /// Invalid state usage fault - INVSTATE: u1 = 0, - /// Invalid PC load usage fault - INVPC: u1 = 0, - /// No coprocessor usage fault. - NOCP: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - /// Unaligned access usage fault - UNALIGNED: u1 = 0, - /// Divide by zero usage fault - DIVBYZERO: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); - - /// Hard fault status register - pub const HFSR = mmio(Address + 0x0000002c, 32, packed struct { - reserved1: u1 = 0, - /// Vector table hard fault - VECTTBL: u1 = 0, - reserved29: u1 = 0, - reserved28: u1 = 0, - reserved27: u1 = 0, - reserved26: u1 = 0, - reserved25: u1 = 0, - reserved24: u1 = 0, - reserved23: u1 = 0, - reserved22: u1 = 0, - reserved21: u1 = 0, - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - /// Forced hard fault - FORCED: u1 = 0, - /// Reserved for Debug use - DEBUG_VT: u1 = 0, - }); - - /// Memory management fault address register - pub const MMFAR = @intToPtr(*volatile u32, Address + 0x00000034); - - /// Bus fault address register - pub const BFAR = @intToPtr(*volatile u32, Address + 0x00000038); - - /// Auxiliary fault status register - pub const AFSR = mmio(Address + 0x0000003c, 32, packed struct { - /// Implementation defined - IMPDEF: u32 = 0, - }); -}; - -/// Nested vectored interrupt controller -pub const NVIC_STIR = extern struct { - pub const Address: u32 = 0xe000ef00; - - /// Software trigger interrupt register - pub const STIR = mmio(Address + 0x00000000, 32, packed struct { - /// Software generated interrupt ID - INTID: u9 = 0, - padding23: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// Floating point unit CPACR -pub const FPU_CPACR = extern struct { - pub const Address: u32 = 0xe000ed88; - - /// Coprocessor access control register - pub const CPACR = mmio(Address + 0x00000000, 32, packed struct { - reserved20: u1 = 0, - reserved19: u1 = 0, - reserved18: u1 = 0, - reserved17: u1 = 0, - reserved16: u1 = 0, - reserved15: u1 = 0, - reserved14: u1 = 0, - reserved13: u1 = 0, - reserved12: u1 = 0, - reserved11: u1 = 0, - reserved10: u1 = 0, - reserved9: u1 = 0, - reserved8: u1 = 0, - reserved7: u1 = 0, - reserved6: u1 = 0, - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -/// System control block ACTLR -pub const SCB_ACTRL = extern struct { - pub const Address: u32 = 0xe000e008; - - /// Auxiliary control register - pub const ACTRL = mmio(Address + 0x00000000, 32, packed struct { - reserved5: u1 = 0, - reserved4: u1 = 0, - reserved3: u1 = 0, - reserved2: u1 = 0, - reserved1: u1 = 0, - padding22: u1 = 0, - padding21: u1 = 0, - padding20: u1 = 0, - padding19: u1 = 0, - padding18: u1 = 0, - padding17: u1 = 0, - padding16: u1 = 0, - padding15: u1 = 0, - padding14: u1 = 0, - padding13: u1 = 0, - padding12: u1 = 0, - padding11: u1 = 0, - padding10: u1 = 0, - padding9: u1 = 0, - padding8: u1 = 0, - padding7: u1 = 0, - padding6: u1 = 0, - padding5: u1 = 0, - padding4: u1 = 0, - padding3: u1 = 0, - padding2: u1 = 0, - padding1: u1 = 0, - }); -}; - -const std = @import("std"); -const root = @import("root"); -const cpu = @import("cpu"); -const config = @import("microzig-config"); -const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic("unhandled interrupt: " ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler("NMI"), - HardFault: InterruptVector = makeUnhandledHandler("HardFault"), - MemManage: InterruptVector = makeUnhandledHandler("MemManage"), - BusFault: InterruptVector = makeUnhandledHandler("BusFault"), - UsageFault: InterruptVector = makeUnhandledHandler("UsageFault"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler("SVCall"), - DebugMonitor: InterruptVector = makeUnhandledHandler("DebugMonitor"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler("PendSV"), - SysTick: InterruptVector = makeUnhandledHandler("SysTick"), - +// this file is generated by regz +// +// device: STM32F303 +// cpu: CM4 + +pub const VectorTable = struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, /// Window Watchdog interrupt - WWDG: InterruptVector = makeUnhandledHandler("WWDG"), - /// PVD through EXTI line detection interrupt - PVD: InterruptVector = makeUnhandledHandler("PVD"), + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, /// Tamper and TimeStamp interrupts - TAMP_STAMP: InterruptVector = makeUnhandledHandler("TAMP_STAMP"), - /// RTC Wakeup interrupt through the EXTI line - RTC_WKUP: InterruptVector = makeUnhandledHandler("RTC_WKUP"), + TAMP_STAMP: InterruptVector = unhandled, + /// RTC Wakeup interrupt through the EXTI + /// line + RTC_WKUP: InterruptVector = unhandled, /// Flash global interrupt - FLASH: InterruptVector = makeUnhandledHandler("FLASH"), + FLASH: InterruptVector = unhandled, /// RCC global interrupt - RCC: InterruptVector = makeUnhandledHandler("RCC"), + RCC: InterruptVector = unhandled, /// EXTI Line0 interrupt - EXTI0: InterruptVector = makeUnhandledHandler("EXTI0"), + EXTI0: InterruptVector = unhandled, /// EXTI Line3 interrupt - EXTI1: InterruptVector = makeUnhandledHandler("EXTI1"), - /// EXTI Line2 and Touch sensing interrupts - EXTI2_TSC: InterruptVector = makeUnhandledHandler("EXTI2_TSC"), + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 and Touch sensing + /// interrupts + EXTI2_TSC: InterruptVector = unhandled, /// EXTI Line3 interrupt - EXTI3: InterruptVector = makeUnhandledHandler("EXTI3"), + EXTI3: InterruptVector = unhandled, /// EXTI Line4 interrupt - EXTI4: InterruptVector = makeUnhandledHandler("EXTI4"), + EXTI4: InterruptVector = unhandled, /// DMA1 channel 1 interrupt - DMA1_CH1: InterruptVector = makeUnhandledHandler("DMA1_CH1"), + DMA1_CH1: InterruptVector = unhandled, /// DMA1 channel 2 interrupt - DMA1_CH2: InterruptVector = makeUnhandledHandler("DMA1_CH2"), + DMA1_CH2: InterruptVector = unhandled, /// DMA1 channel 3 interrupt - DMA1_CH3: InterruptVector = makeUnhandledHandler("DMA1_CH3"), + DMA1_CH3: InterruptVector = unhandled, /// DMA1 channel 4 interrupt - DMA1_CH4: InterruptVector = makeUnhandledHandler("DMA1_CH4"), + DMA1_CH4: InterruptVector = unhandled, /// DMA1 channel 5 interrupt - DMA1_CH5: InterruptVector = makeUnhandledHandler("DMA1_CH5"), + DMA1_CH5: InterruptVector = unhandled, /// DMA1 channel 6 interrupt - DMA1_CH6: InterruptVector = makeUnhandledHandler("DMA1_CH6"), + DMA1_CH6: InterruptVector = unhandled, /// DMA1 channel 7interrupt - DMA1_CH7: InterruptVector = makeUnhandledHandler("DMA1_CH7"), + DMA1_CH7: InterruptVector = unhandled, /// ADC1 and ADC2 global interrupt - ADC1_2: InterruptVector = makeUnhandledHandler("ADC1_2"), - /// USB High Priority/CAN_TX interrupts - USB_HP_CAN_TX: InterruptVector = makeUnhandledHandler("USB_HP_CAN_TX"), - /// USB Low Priority/CAN_RX0 interrupts - USB_LP_CAN_RX0: InterruptVector = makeUnhandledHandler("USB_LP_CAN_RX0"), + ADC1_2: InterruptVector = unhandled, + /// USB High Priority/CAN_TX + /// interrupts + USB_HP_CAN_TX: InterruptVector = unhandled, + /// USB Low Priority/CAN_RX0 + /// interrupts + USB_LP_CAN_RX0: InterruptVector = unhandled, /// CAN_RX1 interrupt - CAN_RX1: InterruptVector = makeUnhandledHandler("CAN_RX1"), + CAN_RX1: InterruptVector = unhandled, /// CAN_SCE interrupt - CAN_SCE: InterruptVector = makeUnhandledHandler("CAN_SCE"), + CAN_SCE: InterruptVector = unhandled, /// EXTI Line5 to Line9 interrupts - EXTI9_5: InterruptVector = makeUnhandledHandler("EXTI9_5"), - /// TIM1 Break/TIM15 global interruts - TIM1_BRK_TIM15: InterruptVector = makeUnhandledHandler("TIM1_BRK_TIM15"), - /// TIM1 Update/TIM16 global interrupts - TIM1_UP_TIM16: InterruptVector = makeUnhandledHandler("TIM1_UP_TIM16"), - /// TIM1 trigger and commutation/TIM17 interrupts - TIM1_TRG_COM_TIM17: InterruptVector = makeUnhandledHandler("TIM1_TRG_COM_TIM17"), + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break/TIM15 global + /// interruts + TIM1_BRK_TIM15: InterruptVector = unhandled, + /// TIM1 Update/TIM16 global + /// interrupts + TIM1_UP_TIM16: InterruptVector = unhandled, + /// TIM1 trigger and commutation/TIM17 + /// interrupts + TIM1_TRG_COM_TIM17: InterruptVector = unhandled, /// TIM1 capture compare interrupt - TIM1_CC: InterruptVector = makeUnhandledHandler("TIM1_CC"), + TIM1_CC: InterruptVector = unhandled, /// TIM2 global interrupt - TIM2: InterruptVector = makeUnhandledHandler("TIM2"), + TIM2: InterruptVector = unhandled, /// TIM3 global interrupt - TIM3: InterruptVector = makeUnhandledHandler("TIM3"), + TIM3: InterruptVector = unhandled, /// TIM4 global interrupt - TIM4: InterruptVector = makeUnhandledHandler("TIM4"), - /// I2C1 event interrupt and EXTI Line23 interrupt - I2C1_EV_EXTI23: InterruptVector = makeUnhandledHandler("I2C1_EV_EXTI23"), + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt and EXTI Line23 + /// interrupt + I2C1_EV_EXTI23: InterruptVector = unhandled, /// I2C1 error interrupt - I2C1_ER: InterruptVector = makeUnhandledHandler("I2C1_ER"), - /// I2C2 event interrupt & EXTI Line24 interrupt - I2C2_EV_EXTI24: InterruptVector = makeUnhandledHandler("I2C2_EV_EXTI24"), + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt & EXTI Line24 + /// interrupt + I2C2_EV_EXTI24: InterruptVector = unhandled, /// I2C2 error interrupt - I2C2_ER: InterruptVector = makeUnhandledHandler("I2C2_ER"), + I2C2_ER: InterruptVector = unhandled, /// SPI1 global interrupt - SPI1: InterruptVector = makeUnhandledHandler("SPI1"), + SPI1: InterruptVector = unhandled, /// SPI2 global interrupt - SPI2: InterruptVector = makeUnhandledHandler("SPI2"), - /// USART1 global interrupt and EXTI Line 25 interrupt - USART1_EXTI25: InterruptVector = makeUnhandledHandler("USART1_EXTI25"), - /// USART2 global interrupt and EXTI Line 26 interrupt - USART2_EXTI26: InterruptVector = makeUnhandledHandler("USART2_EXTI26"), - /// USART3 global interrupt and EXTI Line 28 interrupt - USART3_EXTI28: InterruptVector = makeUnhandledHandler("USART3_EXTI28"), + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt and EXTI Line 25 + /// interrupt + USART1_EXTI25: InterruptVector = unhandled, + /// USART2 global interrupt and EXTI Line 26 + /// interrupt + USART2_EXTI26: InterruptVector = unhandled, + /// USART3 global interrupt and EXTI Line 28 + /// interrupt + USART3_EXTI28: InterruptVector = unhandled, /// EXTI Line15 to Line10 interrupts - EXTI15_10: InterruptVector = makeUnhandledHandler("EXTI15_10"), + EXTI15_10: InterruptVector = unhandled, /// RTC alarm interrupt - RTCAlarm: InterruptVector = makeUnhandledHandler("RTCAlarm"), + RTCAlarm: InterruptVector = unhandled, /// USB wakeup from Suspend - USB_WKUP: InterruptVector = makeUnhandledHandler("USB_WKUP"), + USB_WKUP: InterruptVector = unhandled, /// TIM8 break interrupt - TIM8_BRK: InterruptVector = makeUnhandledHandler("TIM8_BRK"), + TIM8_BRK: InterruptVector = unhandled, /// TIM8 update interrupt - TIM8_UP: InterruptVector = makeUnhandledHandler("TIM8_UP"), - /// TIM8 Trigger and commutation interrupts - TIM8_TRG_COM: InterruptVector = makeUnhandledHandler("TIM8_TRG_COM"), + TIM8_UP: InterruptVector = unhandled, + /// TIM8 Trigger and commutation + /// interrupts + TIM8_TRG_COM: InterruptVector = unhandled, /// TIM8 capture compare interrupt - TIM8_CC: InterruptVector = makeUnhandledHandler("TIM8_CC"), + TIM8_CC: InterruptVector = unhandled, /// ADC3 global interrupt - ADC3: InterruptVector = makeUnhandledHandler("ADC3"), + ADC3: InterruptVector = unhandled, /// FSMC global interrupt - FMC: InterruptVector = makeUnhandledHandler("FMC"), - reserved2: u32 = 0, - reserved3: u32 = 0, + FMC: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, /// SPI3 global interrupt - SPI3: InterruptVector = makeUnhandledHandler("SPI3"), - /// UART4 global and EXTI Line 34 interrupts - UART4_EXTI34: InterruptVector = makeUnhandledHandler("UART4_EXTI34"), - /// UART5 global and EXTI Line 35 interrupts - UART5_EXTI35: InterruptVector = makeUnhandledHandler("UART5_EXTI35"), - /// TIM6 global and DAC12 underrun interrupts - TIM6_DACUNDER: InterruptVector = makeUnhandledHandler("TIM6_DACUNDER"), + SPI3: InterruptVector = unhandled, + /// UART4 global and EXTI Line 34 + /// interrupts + UART4_EXTI34: InterruptVector = unhandled, + /// UART5 global and EXTI Line 35 + /// interrupts + UART5_EXTI35: InterruptVector = unhandled, + /// TIM6 global and DAC12 underrun + /// interrupts + TIM6_DACUNDER: InterruptVector = unhandled, /// TIM7 global interrupt - TIM7: InterruptVector = makeUnhandledHandler("TIM7"), + TIM7: InterruptVector = unhandled, /// DMA2 channel1 global interrupt - DMA2_CH1: InterruptVector = makeUnhandledHandler("DMA2_CH1"), + DMA2_CH1: InterruptVector = unhandled, /// DMA2 channel2 global interrupt - DMA2_CH2: InterruptVector = makeUnhandledHandler("DMA2_CH2"), + DMA2_CH2: InterruptVector = unhandled, /// DMA2 channel3 global interrupt - DMA2_CH3: InterruptVector = makeUnhandledHandler("DMA2_CH3"), + DMA2_CH3: InterruptVector = unhandled, /// DMA2 channel4 global interrupt - DMA2_CH4: InterruptVector = makeUnhandledHandler("DMA2_CH4"), + DMA2_CH4: InterruptVector = unhandled, /// DMA2 channel5 global interrupt - DMA2_CH5: InterruptVector = makeUnhandledHandler("DMA2_CH5"), + DMA2_CH5: InterruptVector = unhandled, /// ADC4 global interrupt - ADC4: InterruptVector = makeUnhandledHandler("ADC4"), - reserved4: u32 = 0, - reserved5: u32 = 0, - /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 + ADC4: InterruptVector = unhandled, + reserved4: u32 = undefined, + reserved5: u32 = undefined, + /// COMP1 & COMP2 & COMP3 interrupts + /// combined with EXTI Lines 21, 22 and 29 /// interrupts - COMP123: InterruptVector = makeUnhandledHandler("COMP123"), - /// COMP4 & COMP5 & COMP6 interrupts combined with EXTI Lines 30, 31 and 32 + COMP123: InterruptVector = unhandled, + /// COMP4 & COMP5 & COMP6 interrupts + /// combined with EXTI Lines 30, 31 and 32 /// interrupts - COMP456: InterruptVector = makeUnhandledHandler("COMP456"), - /// COMP7 interrupt combined with EXTI Line 33 interrupt - COMP7: InterruptVector = makeUnhandledHandler("COMP7"), - reserved6: u32 = 0, - reserved7: u32 = 0, - reserved8: u32 = 0, - reserved9: u32 = 0, - reserved10: u32 = 0, + COMP456: InterruptVector = unhandled, + /// COMP7 interrupt combined with EXTI Line 33 + /// interrupt + COMP7: InterruptVector = unhandled, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + reserved8: u32 = undefined, + reserved9: u32 = undefined, + reserved10: u32 = undefined, /// I2C3 Event interrupt - I2C3_EV: InterruptVector = makeUnhandledHandler("I2C3_EV"), + I2C3_EV: InterruptVector = unhandled, /// I2C3 Error interrupt - I2C3_ER: InterruptVector = makeUnhandledHandler("I2C3_ER"), + I2C3_ER: InterruptVector = unhandled, /// USB High priority interrupt - USB_HP: InterruptVector = makeUnhandledHandler("USB_HP"), + USB_HP: InterruptVector = unhandled, /// USB Low priority interrupt - USB_LP: InterruptVector = makeUnhandledHandler("USB_LP"), - /// USB wakeup from Suspend and EXTI Line 18 - USB_WKUP_EXTI: InterruptVector = makeUnhandledHandler("USB_WKUP_EXTI"), + USB_LP: InterruptVector = unhandled, + /// USB wakeup from Suspend and EXTI Line + /// 18 + USB_WKUP_EXTI: InterruptVector = unhandled, /// TIM20 Break interrupt - TIM20_BRK: InterruptVector = makeUnhandledHandler("TIM20_BRK"), + TIM20_BRK: InterruptVector = unhandled, /// TIM20 Upgrade interrupt - TIM20_UP: InterruptVector = makeUnhandledHandler("TIM20_UP"), - /// TIM20 Trigger and Commutation interrupt - TIM20_TRG_COM: InterruptVector = makeUnhandledHandler("TIM20_TRG_COM"), + TIM20_UP: InterruptVector = unhandled, + /// TIM20 Trigger and Commutation + /// interrupt + TIM20_TRG_COM: InterruptVector = unhandled, /// TIM20 Capture Compare interrupt - TIM20_CC: InterruptVector = makeUnhandledHandler("TIM20_CC"), - /// Floating point unit interrupt; Floating point interrupt - FPU: InterruptVector = makeUnhandledHandler("FPU"), - reserved11: u32 = 0, - reserved12: u32 = 0, + TIM20_CC: InterruptVector = unhandled, + /// Floating point unit interrupt + FPU: InterruptVector = unhandled, + reserved11: u32 = undefined, + reserved12: u32 = undefined, /// SPI4 Global interrupt - SPI4: InterruptVector = makeUnhandledHandler("SPI4"), + SPI4: InterruptVector = unhandled, +}; + +pub const registers = struct { + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x48000000; + + /// address: 0x48000000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800000c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800001c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000028 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + /// General-purpose I/Os + pub const GPIOB = struct { + pub const base_address = 0x48000400; + + /// address: 0x48000400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800040c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800041c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000428 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOC = struct { + pub const base_address = 0x48000800; + + /// address: 0x48000800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800080c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800081c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000828 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOD = struct { + pub const base_address = 0x48000c00; + + /// address: 0x48000c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48000c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48000c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x48000c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48000c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48000c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48000c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x48000c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48000c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48000c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48000c28 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOE = struct { + pub const base_address = 0x48001000; + + /// address: 0x48001000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800100c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800101c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001028 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOF = struct { + pub const base_address = 0x48001400; + + /// address: 0x48001400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800140c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800141c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001428 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOG = struct { + pub const base_address = 0x48001800; + + /// address: 0x48001800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4800180c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4800181c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001828 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + pub const GPIOH = struct { + pub const base_address = 0x48001c00; + + /// address: 0x48001c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x48001c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit + /// 10 + OT10: u1, + /// Port x configuration bit + /// 11 + OT11: u1, + /// Port x configuration bit + /// 12 + OT12: u1, + /// Port x configuration bit + /// 13 + OT13: u1, + /// Port x configuration bit + /// 14 + OT14: u1, + /// Port x configuration bit + /// 15 + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x48001c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x48001c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x48001c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x48001c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x48001c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x48001c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x48001c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x48001c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + + /// address: 0x48001c28 + /// Port bit reset register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + }; + /// Touch sensing controller + pub const TSC = struct { + pub const base_address = 0x40024000; + + /// address: 0x40024000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Touch sensing controller + /// enable + TSCE: u1, + /// Start a new acquisition + START: u1, + /// Acquisition mode + AM: u1, + /// Synchronization pin + /// polarity + SYNCPOL: u1, + /// I/O Default mode + IODEF: u1, + /// Max count value + MCV: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// pulse generator prescaler + PGPSC: u3, + /// Spread spectrum prescaler + SSPSC: u1, + /// Spread spectrum enable + SSE: u1, + /// Spread spectrum deviation + SSD: u7, + /// Charge transfer pulse low + CTPL: u4, + /// Charge transfer pulse high + CTPH: u4, + }), base_address + 0x0); + + /// address: 0x40024004 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition interrupt + /// enable + EOAIE: u1, + /// Max count error interrupt + /// enable + MCEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40024008 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition interrupt + /// clear + EOAIC: u1, + /// Max count error interrupt + /// clear + MCEIC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4002400c + /// interrupt status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// End of acquisition flag + EOAF: u1, + /// Max count error flag + MCEF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40024010 + /// I/O hysteresis control + /// register + pub const IOHCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 Schmitt trigger hysteresis + /// mode + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis + /// mode + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis + /// mode + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis + /// mode + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis + /// mode + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis + /// mode + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis + /// mode + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis + /// mode + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis + /// mode + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis + /// mode + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis + /// mode + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis + /// mode + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis + /// mode + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis + /// mode + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis + /// mode + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis + /// mode + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis + /// mode + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis + /// mode + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis + /// mode + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis + /// mode + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis + /// mode + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis + /// mode + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis + /// mode + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis + /// mode + G6_IO4: u1, + /// G7_IO1 Schmitt trigger hysteresis + /// mode + G7_IO1: u1, + /// G7_IO2 Schmitt trigger hysteresis + /// mode + G7_IO2: u1, + /// G7_IO3 Schmitt trigger hysteresis + /// mode + G7_IO3: u1, + /// G7_IO4 Schmitt trigger hysteresis + /// mode + G7_IO4: u1, + /// G8_IO1 Schmitt trigger hysteresis + /// mode + G8_IO1: u1, + /// G8_IO2 Schmitt trigger hysteresis + /// mode + G8_IO2: u1, + /// G8_IO3 Schmitt trigger hysteresis + /// mode + G8_IO3: u1, + /// G8_IO4 Schmitt trigger hysteresis + /// mode + G8_IO4: u1, + }), base_address + 0x10); + + /// address: 0x40024018 + /// I/O analog switch control + /// register + pub const IOASCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 analog switch + /// enable + G1_IO1: u1, + /// G1_IO2 analog switch + /// enable + G1_IO2: u1, + /// G1_IO3 analog switch + /// enable + G1_IO3: u1, + /// G1_IO4 analog switch + /// enable + G1_IO4: u1, + /// G2_IO1 analog switch + /// enable + G2_IO1: u1, + /// G2_IO2 analog switch + /// enable + G2_IO2: u1, + /// G2_IO3 analog switch + /// enable + G2_IO3: u1, + /// G2_IO4 analog switch + /// enable + G2_IO4: u1, + /// G3_IO1 analog switch + /// enable + G3_IO1: u1, + /// G3_IO2 analog switch + /// enable + G3_IO2: u1, + /// G3_IO3 analog switch + /// enable + G3_IO3: u1, + /// G3_IO4 analog switch + /// enable + G3_IO4: u1, + /// G4_IO1 analog switch + /// enable + G4_IO1: u1, + /// G4_IO2 analog switch + /// enable + G4_IO2: u1, + /// G4_IO3 analog switch + /// enable + G4_IO3: u1, + /// G4_IO4 analog switch + /// enable + G4_IO4: u1, + /// G5_IO1 analog switch + /// enable + G5_IO1: u1, + /// G5_IO2 analog switch + /// enable + G5_IO2: u1, + /// G5_IO3 analog switch + /// enable + G5_IO3: u1, + /// G5_IO4 analog switch + /// enable + G5_IO4: u1, + /// G6_IO1 analog switch + /// enable + G6_IO1: u1, + /// G6_IO2 analog switch + /// enable + G6_IO2: u1, + /// G6_IO3 analog switch + /// enable + G6_IO3: u1, + /// G6_IO4 analog switch + /// enable + G6_IO4: u1, + /// G7_IO1 analog switch + /// enable + G7_IO1: u1, + /// G7_IO2 analog switch + /// enable + G7_IO2: u1, + /// G7_IO3 analog switch + /// enable + G7_IO3: u1, + /// G7_IO4 analog switch + /// enable + G7_IO4: u1, + /// G8_IO1 analog switch + /// enable + G8_IO1: u1, + /// G8_IO2 analog switch + /// enable + G8_IO2: u1, + /// G8_IO3 analog switch + /// enable + G8_IO3: u1, + /// G8_IO4 analog switch + /// enable + G8_IO4: u1, + }), base_address + 0x18); + + /// address: 0x40024020 + /// I/O sampling control register + pub const IOSCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 sampling mode + G1_IO1: u1, + /// G1_IO2 sampling mode + G1_IO2: u1, + /// G1_IO3 sampling mode + G1_IO3: u1, + /// G1_IO4 sampling mode + G1_IO4: u1, + /// G2_IO1 sampling mode + G2_IO1: u1, + /// G2_IO2 sampling mode + G2_IO2: u1, + /// G2_IO3 sampling mode + G2_IO3: u1, + /// G2_IO4 sampling mode + G2_IO4: u1, + /// G3_IO1 sampling mode + G3_IO1: u1, + /// G3_IO2 sampling mode + G3_IO2: u1, + /// G3_IO3 sampling mode + G3_IO3: u1, + /// G3_IO4 sampling mode + G3_IO4: u1, + /// G4_IO1 sampling mode + G4_IO1: u1, + /// G4_IO2 sampling mode + G4_IO2: u1, + /// G4_IO3 sampling mode + G4_IO3: u1, + /// G4_IO4 sampling mode + G4_IO4: u1, + /// G5_IO1 sampling mode + G5_IO1: u1, + /// G5_IO2 sampling mode + G5_IO2: u1, + /// G5_IO3 sampling mode + G5_IO3: u1, + /// G5_IO4 sampling mode + G5_IO4: u1, + /// G6_IO1 sampling mode + G6_IO1: u1, + /// G6_IO2 sampling mode + G6_IO2: u1, + /// G6_IO3 sampling mode + G6_IO3: u1, + /// G6_IO4 sampling mode + G6_IO4: u1, + /// G7_IO1 sampling mode + G7_IO1: u1, + /// G7_IO2 sampling mode + G7_IO2: u1, + /// G7_IO3 sampling mode + G7_IO3: u1, + /// G7_IO4 sampling mode + G7_IO4: u1, + /// G8_IO1 sampling mode + G8_IO1: u1, + /// G8_IO2 sampling mode + G8_IO2: u1, + /// G8_IO3 sampling mode + G8_IO3: u1, + /// G8_IO4 sampling mode + G8_IO4: u1, + }), base_address + 0x20); + + /// address: 0x40024028 + /// I/O channel control register + pub const IOCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// G1_IO1 channel mode + G1_IO1: u1, + /// G1_IO2 channel mode + G1_IO2: u1, + /// G1_IO3 channel mode + G1_IO3: u1, + /// G1_IO4 channel mode + G1_IO4: u1, + /// G2_IO1 channel mode + G2_IO1: u1, + /// G2_IO2 channel mode + G2_IO2: u1, + /// G2_IO3 channel mode + G2_IO3: u1, + /// G2_IO4 channel mode + G2_IO4: u1, + /// G3_IO1 channel mode + G3_IO1: u1, + /// G3_IO2 channel mode + G3_IO2: u1, + /// G3_IO3 channel mode + G3_IO3: u1, + /// G3_IO4 channel mode + G3_IO4: u1, + /// G4_IO1 channel mode + G4_IO1: u1, + /// G4_IO2 channel mode + G4_IO2: u1, + /// G4_IO3 channel mode + G4_IO3: u1, + /// G4_IO4 channel mode + G4_IO4: u1, + /// G5_IO1 channel mode + G5_IO1: u1, + /// G5_IO2 channel mode + G5_IO2: u1, + /// G5_IO3 channel mode + G5_IO3: u1, + /// G5_IO4 channel mode + G5_IO4: u1, + /// G6_IO1 channel mode + G6_IO1: u1, + /// G6_IO2 channel mode + G6_IO2: u1, + /// G6_IO3 channel mode + G6_IO3: u1, + /// G6_IO4 channel mode + G6_IO4: u1, + /// G7_IO1 channel mode + G7_IO1: u1, + /// G7_IO2 channel mode + G7_IO2: u1, + /// G7_IO3 channel mode + G7_IO3: u1, + /// G7_IO4 channel mode + G7_IO4: u1, + /// G8_IO1 channel mode + G8_IO1: u1, + /// G8_IO2 channel mode + G8_IO2: u1, + /// G8_IO3 channel mode + G8_IO3: u1, + /// G8_IO4 channel mode + G8_IO4: u1, + }), base_address + 0x28); + + /// address: 0x40024030 + /// I/O group control status + /// register + pub const IOGCSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Analog I/O group x enable + G1E: u1, + /// Analog I/O group x enable + G2E: u1, + /// Analog I/O group x enable + G3E: u1, + /// Analog I/O group x enable + G4E: u1, + /// Analog I/O group x enable + G5E: u1, + /// Analog I/O group x enable + G6E: u1, + /// Analog I/O group x enable + G7E: u1, + /// Analog I/O group x enable + G8E: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Analog I/O group x status + G1S: u1, + /// Analog I/O group x status + G2S: u1, + /// Analog I/O group x status + G3S: u1, + /// Analog I/O group x status + G4S: u1, + /// Analog I/O group x status + G5S: u1, + /// Analog I/O group x status + G6S: u1, + /// Analog I/O group x status + G7S: u1, + /// Analog I/O group x status + G8S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x30); + + /// address: 0x40024034 + /// I/O group x counter register + pub const IOG1CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x34); + + /// address: 0x40024038 + /// I/O group x counter register + pub const IOG2CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x38); + + /// address: 0x4002403c + /// I/O group x counter register + pub const IOG3CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x3c); + + /// address: 0x40024040 + /// I/O group x counter register + pub const IOG4CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x40024044 + /// I/O group x counter register + pub const IOG5CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x44); + + /// address: 0x40024048 + /// I/O group x counter register + pub const IOG6CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x48); + + /// address: 0x4002404c + /// I/O group x counter register + pub const IOG7CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x4c); + + /// address: 0x40024050 + /// I/O group x counter register + pub const IOG8CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter value + CNT: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x50); + }; + /// cyclic redundancy check calculation + /// unit + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Independent data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// reset bit + RESET: u1, + reserved0: u1, + reserved1: u1, + /// Polynomial size + POLYSIZE: u2, + /// Reverse input data + REV_IN: u2, + /// Reverse output data + REV_OUT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x40023010 + /// Initial CRC value + pub const INIT = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40023014 + /// CRC polynomial + pub const POL = @intToPtr(*volatile u32, base_address + 0x14); + }; + /// Flash + pub const Flash = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LATENCY + LATENCY: u3, + reserved0: u1, + /// PRFTBE + PRFTBE: u1, + /// PRFTBS + PRFTBS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40022004 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash Key + FKEYR: u32, + }), base_address + 0x4); + + /// address: 0x40022008 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002200c + /// Flash status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Busy + BSY: u1, + reserved0: u1, + /// Programming error + PGERR: u1, + reserved1: u1, + /// Write protection error + WRPRT: u1, + /// End of operation + EOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40022010 + /// Flash control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + reserved0: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved1: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved2: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + /// Force option byte loading + FORCE_OPTLOAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// Flash address register + pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Flash address + FAR: u32, + }), base_address + 0x14); + + /// address: 0x4002201c + /// Option byte register + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Option byte error + OPTERR: u1, + /// Level 1 protection status + LEVEL1_PROT: u1, + /// Level 2 protection status + LEVEL2_PROT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved5: u1, + /// BOOT1 + BOOT1: u1, + /// VDDA_MONITOR + VDDA_MONITOR: u1, + /// SRAM_PARITY_CHECK + SRAM_PARITY_CHECK: u1, + reserved6: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// Write protection register + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protect + WRP: u32, + }), base_address + 0x20); + }; + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// Clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal High Speed clock + /// enable + HSION: u1, + /// Internal High Speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal High Speed clock + /// trimming + HSITRIM: u5, + /// Internal High Speed clock + /// Calibration + HSICAL: u8, + /// External High Speed clock + /// enable + HSEON: u1, + /// External High Speed clock ready + /// flag + HSERDY: u1, + /// External High Speed clock + /// Bypass + HSEBYP: u1, + /// Clock Security System + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40021004 + /// Clock configuration register + /// (RCC_CFGR) + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB high speed prescaler + /// (APB2) + PPRE2: u3, + reserved0: u1, + /// PLL entry clock source + PLLSRC: u2, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB prescaler + USBPRES: u1, + /// I2S external clock source + /// selection + I2SSRC: u1, + /// Microcontroller clock + /// output + MCO: u3, + reserved1: u1, + /// Microcontroller Clock Output + /// Flag + MCOF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// Clock interrupt register + /// (RCC_CIR) + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved0: u1, + reserved1: u1, + /// Clock Security System Interrupt + /// flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved5: u1, + reserved6: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4002100c + /// APB2 peripheral reset register + /// (RCC_APB2RSTR) + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved10: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40021010 + /// APB1 peripheral reset register + /// (RCC_APB1RSTR) + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, + reserved0: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved6: u1, + reserved7: u1, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved8: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved9: u1, + /// CAN reset + CANRST: u1, + reserved10: u1, + reserved11: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding0: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// AHB Peripheral Clock enable register + /// (RCC_AHBENR) + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA1 clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock + /// enable + SRAMEN: u1, + reserved0: u1, + /// FLITF clock enable + FLITFEN: u1, + /// FMC clock enable + FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// IO port H clock enable + IOPHEN: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// Touch sensing controller clock + /// enable + TSCEN: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// APB2 peripheral clock enable register + /// (RCC_APB2ENR) + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + reserved10: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// APB1 peripheral clock enable register + /// (RCC_APB1ENR) + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved0: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved6: u1, + reserved7: u1, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved8: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// USART 4 clock enable + USART4EN: u1, + /// USART 5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved9: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock + /// enable + DAC2EN: u1, + reserved10: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding0: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// Backup domain control register + /// (RCC_BDCR) + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// External Low Speed oscillator + /// enable + LSEON: u1, + /// External Low Speed oscillator + /// ready + LSERDY: u1, + /// External Low Speed oscillator + /// bypass + LSEBYP: u1, + /// LSE oscillator drive + /// capability + LSEDRV: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// RTC clock source selection + RTCSEL: u2, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x20); + + /// address: 0x40021024 + /// Control/status register + /// (RCC_CSR) + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Internal low speed oscillator + /// enable + LSION: u1, + /// Internal low speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset + /// flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x24); + + /// address: 0x40021028 + /// AHB peripheral reset register + pub const AHBRSTR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// FMC reset + FMCRST: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// I/O port H reset + IOPHRST: u1, + /// I/O port A reset + IOPARST: u1, + /// I/O port B reset + IOPBRST: u1, + /// I/O port C reset + IOPCRST: u1, + /// I/O port D reset + IOPDRST: u1, + /// I/O port E reset + IOPERST: u1, + /// I/O port F reset + IOPFRST: u1, + /// Touch sensing controller + /// reset + IOPGRST: u1, + /// Touch sensing controller + /// reset + TSCRST: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x28); + + /// address: 0x4002102c + /// Clock configuration register 2 + pub const CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// PREDIV division factor + PREDIV: u4, + /// ADC1 and ADC2 prescaler + ADC12PRES: u5, + /// ADC3 and ADC4 prescaler + ADC34PRES: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x2c); + + /// address: 0x40021030 + /// Clock configuration register 3 + pub const CFGR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART1 clock source + /// selection + USART1SW: u2, + reserved0: u1, + reserved1: u1, + /// I2C1 clock source + /// selection + I2C1SW: u1, + /// I2C2 clock source + /// selection + I2C2SW: u1, + /// I2C3 clock source + /// selection + I2C3SW: u1, + reserved2: u1, + /// Timer1 clock source + /// selection + TIM1SW: u1, + /// Timer8 clock source + /// selection + TIM8SW: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// USART2 clock source + /// selection + USART2SW: u2, + /// USART3 clock source + /// selection + USART3SW: u2, + /// UART4 clock source + /// selection + UART4SW: u2, + /// UART5 clock source + /// selection + UART5SW: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x30); + }; + /// DMA controller 1 + pub const DMA1 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002006c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020070 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020074 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020078 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020080 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020084 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020088 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002008c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + pub const DMA2 = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// DMA interrupt status register + /// (DMA_ISR) + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// flag + GIF1: u1, + /// Channel 1 Transfer Complete + /// flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete + /// flag + HTIF1: u1, + /// Channel 1 Transfer Error + /// flag + TEIF1: u1, + /// Channel 2 Global interrupt + /// flag + GIF2: u1, + /// Channel 2 Transfer Complete + /// flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete + /// flag + HTIF2: u1, + /// Channel 2 Transfer Error + /// flag + TEIF2: u1, + /// Channel 3 Global interrupt + /// flag + GIF3: u1, + /// Channel 3 Transfer Complete + /// flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete + /// flag + HTIF3: u1, + /// Channel 3 Transfer Error + /// flag + TEIF3: u1, + /// Channel 4 Global interrupt + /// flag + GIF4: u1, + /// Channel 4 Transfer Complete + /// flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete + /// flag + HTIF4: u1, + /// Channel 4 Transfer Error + /// flag + TEIF4: u1, + /// Channel 5 Global interrupt + /// flag + GIF5: u1, + /// Channel 5 Transfer Complete + /// flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete + /// flag + HTIF5: u1, + /// Channel 5 Transfer Error + /// flag + TEIF5: u1, + /// Channel 6 Global interrupt + /// flag + GIF6: u1, + /// Channel 6 Transfer Complete + /// flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete + /// flag + HTIF6: u1, + /// Channel 6 Transfer Error + /// flag + TEIF6: u1, + /// Channel 7 Global interrupt + /// flag + GIF7: u1, + /// Channel 7 Transfer Complete + /// flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete + /// flag + HTIF7: u1, + /// Channel 7 Transfer Error + /// flag + TEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020404 + /// DMA interrupt flag clear register + /// (DMA_IFCR) + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel 1 Global interrupt + /// clear + CGIF1: u1, + /// Channel 1 Transfer Complete + /// clear + CTCIF1: u1, + /// Channel 1 Half Transfer + /// clear + CHTIF1: u1, + /// Channel 1 Transfer Error + /// clear + CTEIF1: u1, + /// Channel 2 Global interrupt + /// clear + CGIF2: u1, + /// Channel 2 Transfer Complete + /// clear + CTCIF2: u1, + /// Channel 2 Half Transfer + /// clear + CHTIF2: u1, + /// Channel 2 Transfer Error + /// clear + CTEIF2: u1, + /// Channel 3 Global interrupt + /// clear + CGIF3: u1, + /// Channel 3 Transfer Complete + /// clear + CTCIF3: u1, + /// Channel 3 Half Transfer + /// clear + CHTIF3: u1, + /// Channel 3 Transfer Error + /// clear + CTEIF3: u1, + /// Channel 4 Global interrupt + /// clear + CGIF4: u1, + /// Channel 4 Transfer Complete + /// clear + CTCIF4: u1, + /// Channel 4 Half Transfer + /// clear + CHTIF4: u1, + /// Channel 4 Transfer Error + /// clear + CTEIF4: u1, + /// Channel 5 Global interrupt + /// clear + CGIF5: u1, + /// Channel 5 Transfer Complete + /// clear + CTCIF5: u1, + /// Channel 5 Half Transfer + /// clear + CHTIF5: u1, + /// Channel 5 Transfer Error + /// clear + CTEIF5: u1, + /// Channel 6 Global interrupt + /// clear + CGIF6: u1, + /// Channel 6 Transfer Complete + /// clear + CTCIF6: u1, + /// Channel 6 Half Transfer + /// clear + CHTIF6: u1, + /// Channel 6 Transfer Error + /// clear + CTEIF6: u1, + /// Channel 7 Global interrupt + /// clear + CGIF7: u1, + /// Channel 7 Transfer Complete + /// clear + CTCIF7: u1, + /// Channel 7 Half Transfer + /// clear + CHTIF7: u1, + /// Channel 7 Transfer Error + /// clear + CTEIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002040c + /// DMA channel 1 number of data + /// register + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020410 + /// DMA channel 1 peripheral address + /// register + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x10); + + /// address: 0x40020414 + /// DMA channel 1 memory address + /// register + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002041c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// DMA channel 2 number of data + /// register + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020424 + /// DMA channel 2 peripheral address + /// register + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x24); + + /// address: 0x40020428 + /// DMA channel 2 memory address + /// register + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x28); + + /// address: 0x40020430 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020434 + /// DMA channel 3 number of data + /// register + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020438 + /// DMA channel 3 peripheral address + /// register + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x38); + + /// address: 0x4002043c + /// DMA channel 3 memory address + /// register + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x40020444 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020448 + /// DMA channel 4 number of data + /// register + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002044c + /// DMA channel 4 peripheral address + /// register + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x4c); + + /// address: 0x40020450 + /// DMA channel 4 memory address + /// register + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x50); + + /// address: 0x40020458 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002045c + /// DMA channel 5 number of data + /// register + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020460 + /// DMA channel 5 peripheral address + /// register + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40020464 + /// DMA channel 5 memory address + /// register + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x64); + + /// address: 0x4002046c + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020470 + /// DMA channel 6 number of data + /// register + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020474 + /// DMA channel 6 peripheral address + /// register + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x74); + + /// address: 0x40020478 + /// DMA channel 6 memory address + /// register + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x78); + + /// address: 0x40020480 + /// DMA channel configuration register + /// (DMA_CCR) + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel enable + EN: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Half Transfer interrupt + /// enable + HTIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020484 + /// DMA channel 7 number of data + /// register + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Number of data to transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020488 + /// DMA channel 7 peripheral address + /// register + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral address + PA: u32, + }), base_address + 0x88); + + /// address: 0x4002048c + /// DMA channel 7 memory address + /// register + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory address + MA: u32, + }), base_address + 0x8c); + }; + /// General purpose timer + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output compare 1 fast + /// enable + OC1FE: u1, + /// Output compare 1 preload + /// enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output compare 2 fast + /// enable + OC2FE: u1, + /// Output compare 2 preload + /// enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear + /// enable + OC2CE: u1, + /// Output compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 3 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write + /// access else UIFCPY with read only + /// access + CNT_or_UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 1 + /// value + CCR1L: u16, + /// High Capture/Compare 1 value (on + /// TIM2) + CCR1H: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare 2 + /// value + CCR2L: u16, + /// High Capture/Compare 2 value (on + /// TIM2) + CCR2H: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR3H: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on + /// TIM2) + CCR4H: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General purpose timers + pub const TIM15 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x40014008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Slave mode selection bit 3 + SMS_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001400c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + reserved2: u1, + reserved3: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + reserved1: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40014018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PSC: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40014020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved0: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001402c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40014044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001404c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// General-purpose-timers + pub const TIM16 = struct { + pub const base_address = 0x40014400; + + /// address: 0x40014400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x4001440c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved3: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 1 mode + OC1M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x40014418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001442c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001444c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40014450 + /// option register + pub const OR = @intToPtr(*volatile u32, base_address + 0x50); + }; + /// General purpose timer + pub const TIM17 = struct { + pub const base_address = 0x40014800; + + /// address: 0x40014800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved3: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40014804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x4001480c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40014810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved3: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40014818 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Output Compare 1 mode + OC1M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x40014818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PSC: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40014828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001482c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014830 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40014834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014844 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x44); + + /// address: 0x40014848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001484c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART1 = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40013808 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40013818 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4001381c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40013820 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40013824 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40013828 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004408 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000441c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004420 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004424 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004428 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004808 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000481c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004820 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004824 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004828 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40004c08 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40004c18 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x40004c1c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40004c20 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40004c24 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40004c28 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt + /// enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion + /// time + DEDT: u5, + /// Driver Enable assertion + /// time + DEAT: u5, + /// Receiver timeout interrupt + /// enable + RTOIE: u1, + /// End of Block interrupt + /// enable + EOBIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// 7-bit Address Detection/4-bit Address + /// Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved4: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level + /// inversion + RXINV: u1, + /// TX pin active level + /// inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), base_address + 0x4); + + /// address: 0x40005008 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception + /// Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity + /// selection + DEP: u1, + reserved0: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag + /// selection + WUS: u2, + /// Wakeup from Stop mode interrupt + /// enable + WUFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Receiver timeout register + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), base_address + 0x14); + + /// address: 0x40005018 + /// Request register + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush + /// request + TXFRQ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x18); + + /// address: 0x4000501c + /// Interrupt & status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved0: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute + /// mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge + /// flag + TEACK: u1, + /// Receive enable acknowledge + /// flag + REACK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x1c); + + /// address: 0x40005020 + /// Interrupt flag clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear + /// flag + IDLECF: u1, + reserved0: u1, + /// Transmission complete clear + /// flag + TCCF: u1, + reserved1: u1, + /// LIN break detection clear + /// flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved2: u1, + /// Receiver timeout clear + /// flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Character match clear flag + CMCF: u1, + reserved7: u1, + reserved8: u1, + /// Wakeup from Stop mode clear + /// flag + WUCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40005024 + /// Receive data register + pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); + + /// address: 0x40005028 + /// Transmit data register + pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); + }; + /// Serial peripheral interface/Inter-IC + /// sound + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S2ext = struct { + pub const base_address = 0x40003400; + + /// address: 0x40003400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40003408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S3ext = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40004004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40004008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x4000400c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40004010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40004018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000401c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40004020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI4 = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for + /// reception + LDMA_RX: u1, + /// Last DMA transfer for + /// transmission + LDMA_TX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40013c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// Interrupt mask register + pub const IMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + /// Interrupt Mask on line 23 + MR23: u1, + /// Interrupt Mask on line 24 + MR24: u1, + /// Interrupt Mask on line 25 + MR25: u1, + /// Interrupt Mask on line 26 + MR26: u1, + /// Interrupt Mask on line 27 + MR27: u1, + /// Interrupt Mask on line 28 + MR28: u1, + /// Interrupt Mask on line 29 + MR29: u1, + /// Interrupt Mask on line 30 + MR30: u1, + /// Interrupt Mask on line 31 + MR31: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// Event mask register + pub const EMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + /// Event Mask on line 23 + MR23: u1, + /// Event Mask on line 24 + MR24: u1, + /// Event Mask on line 25 + MR25: u1, + /// Event Mask on line 26 + MR26: u1, + /// Event Mask on line 27 + MR27: u1, + /// Event Mask on line 28 + MR28: u1, + /// Event Mask on line 29 + MR29: u1, + /// Event Mask on line 30 + MR30: u1, + /// Event Mask on line 31 + MR31: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// Rising Trigger selection + /// register + pub const RTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + /// Rising trigger event configuration of + /// line 19 + TR19: u1, + /// Rising trigger event configuration of + /// line 20 + TR20: u1, + /// Rising trigger event configuration of + /// line 21 + TR21: u1, + /// Rising trigger event configuration of + /// line 22 + TR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Rising trigger event configuration of + /// line 29 + TR29: u1, + /// Rising trigger event configuration of + /// line 30 + TR30: u1, + /// Rising trigger event configuration of + /// line 31 + TR31: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// Falling Trigger selection + /// register + pub const FTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + /// Falling trigger event configuration of + /// line 19 + TR19: u1, + /// Falling trigger event configuration of + /// line 20 + TR20: u1, + /// Falling trigger event configuration of + /// line 21 + TR21: u1, + /// Falling trigger event configuration of + /// line 22 + TR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Falling trigger event configuration of + /// line 29 + TR29: u1, + /// Falling trigger event configuration of + /// line 30. + TR30: u1, + /// Falling trigger event configuration of + /// line 31 + TR31: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// Software interrupt event + /// register + pub const SWIER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + /// Software Interrupt on line + /// 19 + SWIER19: u1, + /// Software Interrupt on line + /// 20 + SWIER20: u1, + /// Software Interrupt on line + /// 21 + SWIER21: u1, + /// Software Interrupt on line + /// 22 + SWIER22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Software Interrupt on line + /// 29 + SWIER29: u1, + /// Software Interrupt on line + /// 309 + SWIER30: u1, + /// Software Interrupt on line + /// 319 + SWIER31: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// Pending register + pub const PR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Pending bit 29 + PR29: u1, + /// Pending bit 30 + PR30: u1, + /// Pending bit 31 + PR31: u1, + }), base_address + 0x14); + + /// address: 0x40010418 + /// Interrupt mask register + pub const IMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interrupt Mask on external/internal line + /// 32 + MR32: u1, + /// Interrupt Mask on external/internal line + /// 33 + MR33: u1, + /// Interrupt Mask on external/internal line + /// 34 + MR34: u1, + /// Interrupt Mask on external/internal line + /// 35 + MR35: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x18); + + /// address: 0x4001041c + /// Event mask register + pub const EMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Event mask on external/internal line + /// 32 + MR32: u1, + /// Event mask on external/internal line + /// 33 + MR33: u1, + /// Event mask on external/internal line + /// 34 + MR34: u1, + /// Event mask on external/internal line + /// 35 + MR35: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x1c); + + /// address: 0x40010420 + /// Rising Trigger selection + /// register + pub const RTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Rising trigger event configuration bit + /// of line 32 + TR32: u1, + /// Rising trigger event configuration bit + /// of line 33 + TR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x20); + + /// address: 0x40010424 + /// Falling Trigger selection + /// register + pub const FTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Falling trigger event configuration bit + /// of line 32 + TR32: u1, + /// Falling trigger event configuration bit + /// of line 33 + TR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x24); + + /// address: 0x40010428 + /// Software interrupt event + /// register + pub const SWIER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software interrupt on line + /// 32 + SWIER32: u1, + /// Software interrupt on line + /// 33 + SWIER33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4001042c + /// Pending register + pub const PR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Pending bit on line 32 + PR32: u1, + /// Pending bit on line 33 + PR33: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + }; + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector + /// enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write + /// protection + DBP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Enable WKUP1 pin + EWUP1: u1, + /// Enable WKUP2 pin + EWUP2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + }; + /// Controller area network + pub const CAN = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// error status register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct{ + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// TX mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// TX mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// receive FIFO mailbox data length control and + /// time stamp register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// receive FIFO mailbox data low + /// register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// receive FIFO mailbox identifier + /// register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// receive FIFO mailbox data length control and + /// time stamp register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// receive FIFO mailbox data low + /// register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// receive FIFO mailbox data high + /// register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter init mode + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2 start bank + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// CAN filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + /// Universal serial bus full-speed device + /// interface + pub const USB_FS = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// endpoint 0 register + pub const USB_EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// endpoint 1 register + pub const USB_EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// endpoint 2 register + pub const USB_EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// endpoint 3 register + pub const USB_EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// endpoint 4 register + pub const USB_EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40005c14 + /// endpoint 5 register + pub const USB_EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// endpoint 6 register + pub const USB_EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// endpoint 7 register + pub const USB_EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint address + EA: u4, + /// Status bits, for transmission + /// transfers + STAT_TX: u2, + /// Data Toggle, for transmission + /// transfers + DTOG_TX: u1, + /// Correct Transfer for + /// transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction + /// completed + SETUP: u1, + /// Status bits, for reception + /// transfers + STAT_RX: u2, + /// Data Toggle, for reception + /// transfers + DTOG_RX: u1, + /// Correct transfer for + /// reception + CTR_RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c40 + /// control register + pub const USB_CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start of frame interrupt + /// mask + ESOFM: u1, + /// Start of frame interrupt + /// mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt + /// mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun + /// interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt + /// mask + CTRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40005c44 + /// interrupt status register + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / + /// underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40005c48 + /// frame number register + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x40005c4c + /// device address + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device address + ADD: u1, + /// Device address + ADD1: u1, + /// Device address + ADD2: u1, + /// Device address + ADD3: u1, + /// Device address + ADD4: u1, + /// Device address + ADD5: u1, + /// Device address + ADD6: u1, + /// Enable function + EF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4c); + + /// address: 0x40005c50 + /// Buffer table address + pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); + }; + /// Inter-integrated circuit + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40005424 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40005428 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40005824 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40005828 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + pub const I2C3 = struct { + pub const base_address = 0x40007800; + + /// address: 0x40007800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave + /// only) + ADDRIE: u1, + /// Not acknowledge received interrupt + /// enable + NACKIE: u1, + /// STOP detection Interrupt + /// enable + STOPIE: u1, + /// Transfer Complete interrupt + /// enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests + /// enable + TXDMAEN: u1, + /// DMA reception requests + /// enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address + /// enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40007804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave address bit 0 (master + /// mode) + SADD0: u1, + /// Slave address bit 7:1 (master + /// mode) + SADD1: u7, + /// Slave address bit 9:8 (master + /// mode) + SADD8: u2, + /// Transfer direction (master + /// mode) + RD_WRN: u1, + /// 10-bit addressing mode (master + /// mode) + ADD10: u1, + /// 10-bit address header only read + /// direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master + /// mode) + STOP: u1, + /// NACK generation (slave + /// mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master + /// mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40007808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Own Address 1 enable + OA1EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000780c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Own Address 2 enable + OA2EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007810 + /// Timing register + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// SCL low period (master + /// mode) + SCLL: u8, + /// SCL high period (master + /// mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Timing prescaler + PRESC: u4, + }), base_address + 0x10); + + /// address: 0x40007814 + /// Status register 1 + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout + /// detection + TIDLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Extended clock timeout + /// enable + TEXTEN: u1, + }), base_address + 0x14); + + /// address: 0x40007818 + /// Interrupt and Status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Transmit data register empty + /// (transmitters) + TXE: u1, + /// Transmit interrupt status + /// (transmitters) + TXIS: u1, + /// Receive data register not empty + /// (receivers) + RXNE: u1, + /// Address matched (slave + /// mode) + ADDR: u1, + /// Not acknowledge received + /// flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master + /// mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave + /// mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection + /// flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved0: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave + /// mode) + DIR: u1, + /// Address match code (Slave + /// mode) + ADDCODE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0x4000781c + /// Interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved3: u1, + reserved4: u1, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag + /// clear + ARLOCF: u1, + /// Overrun/Underrun flag + /// clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag + /// clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c); + + /// address: 0x40007820 + /// PEC register + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Packet error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40007824 + /// Receive data register + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit receive data + RXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40007828 + /// Transmit data register + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 8-bit transmit data + TXDATA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x28); + }; + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register + pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Key value + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + /// Watchdog counter window value + /// update + WVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc); + + /// address: 0x40003010 + /// Window register + pub const WINR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Watchdog counter window + /// value + WIN: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x10); + }; + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit counter + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + /// 7-bit window value + W: u7, + /// Timer base + WDGTB: u2, + /// Early wakeup interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// time register + pub const TR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// date register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active + /// edge + TSEDGE: u1, + /// Reference clock detection enable (50 or + /// 60 Hz) + REFCKON: u1, + /// Bypass the shadow + /// registers + BYPSHAD: u1, + /// Hour format + FMT: u1, + reserved0: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt + /// enable + WUTIE: u1, + /// Time-stamp interrupt + /// enable + TSIE: u1, + /// Add 1 hour (summer time + /// change) + ADD1H: u1, + /// Subtract 1 hour (winter time + /// change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output + /// selection + COSEL: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// initialization and status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization + /// flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// RTC_TAMP2 detection flag + TAMP2F: u1, + /// RTC_TAMP3 detection flag + TAMP3F: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// prescaler register + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Synchronous prescaler + /// factor + PREDIV_S: u15, + reserved0: u1, + /// Asynchronous prescaler + /// factor + PREDIV_A: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// wakeup timer register + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Wakeup auto-reload value + /// bits + WUT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x4000281c + /// alarm A register + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// alarm B register + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// write protection register + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Write protection key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40002828 + /// sub second register + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000282c + /// shift control register + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Subtract a fraction of a + /// second + SUBFS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Add one second + ADD1S: u1, + }), base_address + 0x2c); + + /// address: 0x40002830 + /// time stamp time register + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x30); + + /// address: 0x40002834 + /// time stamp date register + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// timestamp sub second register + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x38); + + /// address: 0x4000283c + /// calibration register + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration minus + CALM: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Use a 16-second calibration cycle + /// period + CALW16: u1, + /// Use an 8-second calibration cycle + /// period + CALW8: u1, + /// Increase frequency of RTC by 488.5 + /// ppm + CALP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40002840 + /// tamper and alternate function configuration + /// register + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + /// Tamper 3 detection enable + TAMP3E: u1, + /// Active level for tamper 3 + TAMP3TRG: u1, + /// Activate timestamp on tamper detection + /// event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + reserved0: u1, + reserved1: u1, + /// PC13 value + PC13VALUE: u1, + /// PC13 mode + PC13MODE: u1, + /// PC14 value + PC14VALUE: u1, + /// PC 14 mode + PC14MODE: u1, + /// PC15 value + PC15VALUE: u1, + /// PC15 mode + PC15MODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x40002844 + /// alarm A sub second register + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x44); + + /// address: 0x40002848 + /// alarm B sub second register + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x48); + + /// address: 0x40002850 + /// backup register + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x50); + + /// address: 0x40002854 + /// backup register + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x54); + + /// address: 0x40002858 + /// backup register + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x58); + + /// address: 0x4000285c + /// backup register + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x5c); + + /// address: 0x40002860 + /// backup register + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x60); + + /// address: 0x40002864 + /// backup register + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x64); + + /// address: 0x40002868 + /// backup register + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x68); + + /// address: 0x4000286c + /// backup register + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x6c); + + /// address: 0x40002870 + /// backup register + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x70); + + /// address: 0x40002874 + /// backup register + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x74); + + /// address: 0x40002878 + /// backup register + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x78); + + /// address: 0x4000287c + /// backup register + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x7c); + + /// address: 0x40002880 + /// backup register + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x80); + + /// address: 0x40002884 + /// backup register + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x84); + + /// address: 0x40002888 + /// backup register + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x88); + + /// address: 0x4000288c + /// backup register + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x8c); + + /// address: 0x40002890 + /// backup register + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x90); + + /// address: 0x40002894 + /// backup register + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x94); + + /// address: 0x40002898 + /// backup register + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x98); + + /// address: 0x4000289c + /// backup register + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0x9c); + + /// address: 0x400028a0 + /// backup register + pub const BKP20R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa0); + + /// address: 0x400028a4 + /// backup register + pub const BKP21R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa4); + + /// address: 0x400028a8 + /// backup register + pub const BKP22R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xa8); + + /// address: 0x400028ac + /// backup register + pub const BKP23R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xac); + + /// address: 0x400028b0 + /// backup register + pub const BKP24R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb0); + + /// address: 0x400028b4 + /// backup register + pub const BKP25R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb4); + + /// address: 0x400028b8 + /// backup register + pub const BKP26R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xb8); + + /// address: 0x400028bc + /// backup register + pub const BKP27R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xbc); + + /// address: 0x400028c0 + /// backup register + pub const BKP28R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc0); + + /// address: 0x400028c4 + /// backup register + pub const BKP29R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc4); + + /// address: 0x400028c8 + /// backup register + pub const BKP30R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xc8); + + /// address: 0x400028cc + /// backup register + pub const BKP31R = @intToPtr(*volatile Mmio(32, packed struct{ + /// BKP + BKP: u32, + }), base_address + 0xcc); + }; + /// Basic timers + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// Low counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF Copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt + /// enable + DMAUDRIE1: u1, + reserved0: u1, + reserved1: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt + /// enable + DMAUDRIE2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// channel1 12-bit right-aligned data holding + /// register + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// channel1 12-bit left aligned data holding + /// register + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// channel1 8-bit right aligned data holding + /// register + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// channel2 12-bit right aligned data holding + /// register + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// channel2 12-bit left aligned data holding + /// register + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// channel2 8-bit right-aligned data holding + /// register + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// channel1 data output register + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// channel2 data output register + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x40007434 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// DAC channel1 DMA underrun + /// flag + DMAUDR1: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + /// DAC channel2 DMA underrun + /// flag + DMAUDR2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + }; + /// Debug support + pub const DBGMCU = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// MCU Device ID Code Register + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + /// Device Identifier + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Revision Identifier + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Debug MCU Configuration + /// Register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// Trace pin assignment + /// control + TRACE_IOEN: u1, + /// Trace pin assignment + /// control + TRACE_MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0xe0042008 + /// APB Low Freeze Register + pub const APB1FZ = @intToPtr(*volatile Mmio(32, packed struct{ + /// Debug Timer 2 stopped when Core is + /// halted + DBG_TIM2_STOP: u1, + /// Debug Timer 3 stopped when Core is + /// halted + DBG_TIM3_STOP: u1, + /// Debug Timer 4 stopped when Core is + /// halted + DBG_TIM4_STOP: u1, + /// Debug Timer 5 stopped when Core is + /// halted + DBG_TIM5_STOP: u1, + /// Debug Timer 6 stopped when Core is + /// halted + DBG_TIM6_STOP: u1, + /// Debug Timer 7 stopped when Core is + /// halted + DBG_TIM7_STOP: u1, + /// Debug Timer 12 stopped when Core is + /// halted + DBG_TIM12_STOP: u1, + /// Debug Timer 13 stopped when Core is + /// halted + DBG_TIM13_STOP: u1, + /// Debug Timer 14 stopped when Core is + /// halted + DBG_TIMER14_STOP: u1, + /// Debug Timer 18 stopped when Core is + /// halted + DBG_TIM18_STOP: u1, + /// Debug RTC stopped when Core is + /// halted + DBG_RTC_STOP: u1, + /// Debug Window Wachdog stopped when Core + /// is halted + DBG_WWDG_STOP: u1, + /// Debug Independent Wachdog stopped when + /// Core is halted + DBG_IWDG_STOP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// SMBUS timeout mode stopped when Core is + /// halted + I2C1_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when Core is + /// halted + I2C2_SMBUS_TIMEOUT: u1, + reserved8: u1, + reserved9: u1, + /// Debug CAN stopped when core is + /// halted + DBG_CAN_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0xe004200c + /// APB High Freeze Register + pub const APB2FZ = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Debug Timer 15 stopped when Core is + /// halted + DBG_TIM15_STOP: u1, + /// Debug Timer 16 stopped when Core is + /// halted + DBG_TIM16_STOP: u1, + /// Debug Timer 17 stopped when Core is + /// halted + DBG_TIM17_STO: u1, + /// Debug Timer 19 stopped when Core is + /// halted + DBG_TIM19_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + }; + /// Advanced timer + pub const TIM1 = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40012c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40012c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x40012c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40012c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40012c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40012c30 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40012c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40012c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x40012c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40012c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40012c44 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40012c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40012c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40012c54 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40012c58 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x40012c5c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40012c60 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM1_ETR_ADC1 remapping + /// capability + TIM1_ETR_ADC1_RMP: u2, + /// TIM1_ETR_ADC4 remapping + /// capability + TIM1_ETR_ADC4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + pub const TIM20 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40015008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001500c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40015010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40015018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001501c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4001501c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40015020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40015024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40015028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001502c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40015030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40015034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40015038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001503c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40015040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40015044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40015048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001504c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40015054 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40015058 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x4001505c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40015060 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM1_ETR_ADC1 remapping + /// capability + TIM1_ETR_ADC1_RMP: u2, + /// TIM1_ETR_ADC4 remapping + /// capability + TIM1_ETR_ADC4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + /// Advanced-timers + pub const TIM8 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved0: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved1: u1, + /// Output Idle state 5 + OIS5: u1, + reserved2: u1, + /// Output Idle state 6 + OIS6: u1, + reserved3: u1, + /// Master mode selection 2 + MMS2: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40013410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 5 interrupt + /// flag + C5IF: u1, + /// Capture/Compare 6 interrupt + /// flag + C6IF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// capture/compare mode register (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + /// Output Compare 1 mode bit + /// 3 + OC1M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 2 mode bit + /// 3 + OC2M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x40013418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + IC1PCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// capture/compare mode register (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + /// Output Compare 3 mode bit + /// 3 + OC3M_3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Output Compare 4 mode bit + /// 3 + OC4M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x4001341c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved0: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + /// Capture/Compare 5 output + /// enable + CC5E: u1, + /// Capture/Compare 5 output + /// Polarity + CC5P: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 6 output + /// enable + CC6E: u1, + /// Capture/Compare 6 output + /// Polarity + CC6P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40013424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + /// counter value + CNT: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// UIF copy + UIFCPY: u1, + }), base_address + 0x24); + + /// address: 0x40013428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001342c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40013430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Repetition counter value + REP: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x30); + + /// address: 0x40013434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40013438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001343c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40013440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40013444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x44); + + /// address: 0x40013448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001344c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40013454 + /// capture/compare mode register 3 (output + /// mode) + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + /// Output compare 5 fast + /// enable + OC5FE: u1, + /// Output compare 5 preload + /// enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear + /// enable + OC5CE: u1, + reserved2: u1, + reserved3: u1, + /// Output compare 6 fast + /// enable + OC6FE: u1, + /// Output compare 6 preload + /// enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear + /// enable + OC6CE: u1, + /// Outout Compare 5 mode bit + /// 3 + OC5M_3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Outout Compare 6 mode bit + /// 3 + OC6M_3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x54); + + /// address: 0x40013458 + /// capture/compare register 5 + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Capture/Compare 5 value + CCR5: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Group Channel 5 and Channel + /// 1 + GC5C1: u1, + /// Group Channel 5 and Channel + /// 2 + GC5C2: u1, + /// Group Channel 5 and Channel + /// 3 + GC5C3: u1, + }), base_address + 0x58); + + /// address: 0x4001345c + /// capture/compare register 6 + pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x40013460 + /// option registers + pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + /// TIM8_ETR_ADC2 remapping + /// capability + TIM8_ETR_ADC2_RMP: u2, + /// TIM8_ETR_ADC3 remapping + /// capability + TIM8_ETR_ADC3_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x60); + }; + /// Analog-to-Digital Converter + pub const ADC1 = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000014 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000020 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000024 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000030 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000034 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000038 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000040 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000004c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000060 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000064 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000068 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000006c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000080 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000084 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000088 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000008c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500000a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500000a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500000b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500000b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC2 = struct { + pub const base_address = 0x50000100; + + /// address: 0x50000100 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000104 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000108 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000010c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000114 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000118 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000120 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000124 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000128 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000130 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000134 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000138 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000013c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000140 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000014c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000160 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000164 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000168 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000016c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000180 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000184 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000188 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000018c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500001a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500001a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500001b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500001b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC3 = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000040c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000414 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000418 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000420 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000424 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000428 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000430 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000434 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000438 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000043c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000440 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000044c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000460 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000464 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000468 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000046c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000480 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000484 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000488 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000048c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500004a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500004a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500004b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500004b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + pub const ADC4 = struct { + pub const base_address = 0x50000500; + + /// address: 0x50000500 + /// interrupt and status register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x50000504 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x50000508 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), base_address + 0x8); + + /// address: 0x5000050c + /// configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved0: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000514 + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x50000518 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x50000520 + /// watchdog threshold register 1 + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT1 + LT1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// HT1 + HT1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x50000524 + /// watchdog threshold register + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT2 + LT2: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT2 + HT2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x50000528 + /// watchdog threshold register 3 + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// LT3 + LT3: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// HT3 + HT3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x50000530 + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// L3 + L3: u4, + reserved0: u1, + reserved1: u1, + /// SQ1 + SQ1: u5, + reserved2: u1, + /// SQ2 + SQ2: u5, + reserved3: u1, + /// SQ3 + SQ3: u5, + reserved4: u1, + /// SQ4 + SQ4: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x30); + + /// address: 0x50000534 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ5 + SQ5: u5, + reserved0: u1, + /// SQ6 + SQ6: u5, + reserved1: u1, + /// SQ7 + SQ7: u5, + reserved2: u1, + /// SQ8 + SQ8: u5, + reserved3: u1, + /// SQ9 + SQ9: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x34); + + /// address: 0x50000538 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ10 + SQ10: u5, + reserved0: u1, + /// SQ11 + SQ11: u5, + reserved1: u1, + /// SQ12 + SQ12: u5, + reserved2: u1, + /// SQ13 + SQ13: u5, + reserved3: u1, + /// SQ14 + SQ14: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x38); + + /// address: 0x5000053c + /// regular sequence register 4 + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SQ15 + SQ15: u5, + reserved0: u1, + /// SQ16 + SQ16: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x3c); + + /// address: 0x50000540 + /// regular Data Register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + /// regularDATA + regularDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x5000054c + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved0: u1, + /// JSQ2 + JSQ2: u5, + reserved1: u1, + /// JSQ3 + JSQ3: u5, + reserved2: u1, + /// JSQ4 + JSQ4: u5, + padding0: u1, + }), base_address + 0x4c); + + /// address: 0x50000560 + /// offset register 1 + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET1 + OFFSET1: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), base_address + 0x60); + + /// address: 0x50000564 + /// offset register 2 + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET2 + OFFSET2: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), base_address + 0x64); + + /// address: 0x50000568 + /// offset register 3 + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET3 + OFFSET3: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), base_address + 0x68); + + /// address: 0x5000056c + /// offset register 4 + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// OFFSET4 + OFFSET4: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), base_address + 0x6c); + + /// address: 0x50000580 + /// injected data register 1 + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA1 + JDATA1: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x80); + + /// address: 0x50000584 + /// injected data register 2 + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA2 + JDATA2: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x50000588 + /// injected data register 3 + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA3 + JDATA3: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x88); + + /// address: 0x5000058c + /// injected data register 4 + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// JDATA4 + JDATA4: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x500005a0 + /// Analog Watchdog 2 Configuration + /// Register + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD2CH + AWD2CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa0); + + /// address: 0x500005a4 + /// Analog Watchdog 3 Configuration + /// Register + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// AWD3CH + AWD3CH: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xa4); + + /// address: 0x500005b0 + /// Differential Mode Selection Register + /// 2 + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Differential mode for channels 15 to + /// 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to + /// 16 + DIFSEL_16_18: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xb0); + + /// address: 0x500005b4 + /// Calibration Factors + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + /// CALFACT_S + CALFACT_S: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// CALFACT_D + CALFACT_D: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xb4); + }; + /// Analog-to-Digital Converter + pub const ADC1_2 = struct { + pub const base_address = 0x50000300; + + /// address: 0x50000300 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// AWD1_MST + AWD1_MST: u1, + /// AWD2_MST + AWD2_MST: u1, + /// AWD3_MST + AWD3_MST: u1, + /// JQOVF_MST + JQOVF_MST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave + /// ADC + EOC_SLV: u1, + /// End of regular sequence flag of the + /// slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave + /// ADC + OVR_SLV: u1, + /// End of injected conversion flag of the + /// slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the + /// slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave + /// ADC + AWD1_SLV: u1, + /// Analog watchdog 2 flag of the slave + /// ADC + AWD2_SLV: u1, + /// Analog watchdog 3 flag of the slave + /// ADC + AWD3_SLV: u1, + /// Injected Context Queue Overflow flag of + /// the slave ADC + JQOVF_SLV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x50000308 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA configuration (for multi-ADC + /// mode) + DMACFG: u1, + /// Direct memory access mode for multi ADC + /// mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x5000030c + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data of the master + /// ADC + RDATA_MST: u16, + /// Regular data of the slave + /// ADC + RDATA_SLV: u16, + }), base_address + 0xc); + }; + pub const ADC3_4 = struct { + pub const base_address = 0x50000700; + + /// address: 0x50000700 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// AWD1_MST + AWD1_MST: u1, + /// AWD2_MST + AWD2_MST: u1, + /// AWD3_MST + AWD3_MST: u1, + /// JQOVF_MST + JQOVF_MST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave + /// ADC + EOC_SLV: u1, + /// End of regular sequence flag of the + /// slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave + /// ADC + OVR_SLV: u1, + /// End of injected conversion flag of the + /// slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the + /// slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave + /// ADC + AWD1_SLV: u1, + /// Analog watchdog 2 flag of the slave + /// ADC + AWD2_SLV: u1, + /// Analog watchdog 3 flag of the slave + /// ADC + AWD3_SLV: u1, + /// Injected Context Queue Overflow flag of + /// the slave ADC + JQOVF_SLV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x50000708 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA configuration (for multi-ADC + /// mode) + DMACFG: u1, + /// Direct memory access mode for multi ADC + /// mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x5000070c + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Regular data of the master + /// ADC + RDATA_MST: u16, + /// Regular data of the slave + /// ADC + RDATA_SLV: u16, + }), base_address + 0xc); + }; + /// System configuration controller _Comparator and + /// Operational amplifier + pub const SYSCFG_COMP_OPAMP = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// configuration register 1 + pub const SYSCFG_CFGR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory mapping selection + /// bits + MEM_MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// USB interrupt remap + USB_IT_RMP: u1, + /// Timer 1 ITR3 selection + TIM1_ITR_RMP: u1, + /// DAC trigger remap (when TSEL = + /// 001) + DAC_TRIG_RMP: u1, + /// ADC24 DMA remapping bit + ADC24_DMA_RMP: u1, + reserved3: u1, + reserved4: u1, + /// TIM16 DMA request remapping + /// bit + TIM16_DMA_RMP: u1, + /// TIM17 DMA request remapping + /// bit + TIM17_DMA_RMP: u1, + /// TIM6 and DAC1 DMA request remapping + /// bit + TIM6_DAC1_DMA_RMP: u1, + /// TIM7 and DAC2 DMA request remapping + /// bit + TIM7_DAC2_DMA_RMP: u1, + reserved5: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB6_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB7_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB8_FM: u1, + /// Fast Mode Plus (FM+) driving capability + /// activation bits. + I2C_PB9_FM: u1, + /// I2C1 Fast Mode Plus + I2C1_FM: u1, + /// I2C2 Fast Mode Plus + I2C2_FM: u1, + /// Encoder mode + ENCODER_MODE: u2, + reserved6: u1, + reserved7: u1, + /// Interrupt enable bits from + /// FPU + FPU_IT: u6, + }), base_address + 0x0); + + /// address: 0x40010008 + /// external interrupt configuration register + /// 1 + pub const SYSCFG_EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 0 configuration bits + EXTI0: u4, + /// EXTI 1 configuration bits + EXTI1: u4, + /// EXTI 2 configuration bits + EXTI2: u4, + /// EXTI 3 configuration bits + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// external interrupt configuration register + /// 2 + pub const SYSCFG_EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 4 configuration bits + EXTI4: u4, + /// EXTI 5 configuration bits + EXTI5: u4, + /// EXTI 6 configuration bits + EXTI6: u4, + /// EXTI 7 configuration bits + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// external interrupt configuration register + /// 3 + pub const SYSCFG_EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 8 configuration bits + EXTI8: u4, + /// EXTI 9 configuration bits + EXTI9: u4, + /// EXTI 10 configuration bits + EXTI10: u4, + /// EXTI 11 configuration bits + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// external interrupt configuration register + /// 4 + pub const SYSCFG_EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// EXTI 12 configuration bits + EXTI12: u4, + /// EXTI 13 configuration bits + EXTI13: u4, + /// EXTI 14 configuration bits + EXTI14: u4, + /// EXTI 15 configuration bits + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// configuration register 2 + pub const SYSCFG_CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Cortex-M0 LOCKUP bit enable + /// bit + LOCUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + reserved0: u1, + /// Bypass address bit 29 in parity + /// calculation + BYP_ADD_PAR: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SRAM parity flag + SRAM_PEF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x18); + + /// address: 0x40010004 + /// CCM SRAM protection register + pub const SYSCFG_RCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// CCM SRAM page write protection + /// bit + PAGE0_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE1_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE2_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE3_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE4_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE5_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE6_WP: u1, + /// CCM SRAM page write protection + /// bit + PAGE7_WP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x4001001c + /// control and status register + pub const COMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 1 enable + COMP1EN: u1, + /// COMP1_INP_DAC + COMP1_INP_DAC: u1, + /// Comparator 1 mode + COMP1MODE: u2, + /// Comparator 1 inverting input + /// selection + COMP1INSEL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 1 output + /// selection + COMP1_OUT_SEL: u4, + reserved3: u1, + /// Comparator 1 output + /// polarity + COMP1POL: u1, + /// Comparator 1 hysteresis + COMP1HYST: u2, + /// Comparator 1 blanking + /// source + COMP1_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 1 output + COMP1OUT: u1, + /// Comparator 1 lock + COMP1LOCK: u1, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// control and status register + pub const COMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 2 enable + COMP2EN: u1, + reserved0: u1, + /// Comparator 2 mode + COMP2MODE: u2, + /// Comparator 2 inverting input + /// selection + COMP2INSEL: u3, + /// Comparator 2 non inverted input + /// selection + COMP2INPSEL: u1, + reserved1: u1, + /// Comparator 1inverting input + /// selection + COMP2INMSEL: u1, + /// Comparator 2 output + /// selection + COMP2_OUT_SEL: u4, + reserved2: u1, + /// Comparator 2 output + /// polarity + COMP2POL: u1, + /// Comparator 2 hysteresis + COMP2HYST: u2, + /// Comparator 2 blanking + /// source + COMP2_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 2 lock + COMP2LOCK: u1, + }), base_address + 0x20); + + /// address: 0x40010024 + /// control and status register + pub const COMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 3 enable + COMP3EN: u1, + reserved0: u1, + /// Comparator 3 mode + COMP3MODE: u2, + /// Comparator 3 inverting input + /// selection + COMP3INSEL: u3, + /// Comparator 3 non inverted input + /// selection + COMP3INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 3 output + /// selection + COMP3_OUT_SEL: u4, + reserved3: u1, + /// Comparator 3 output + /// polarity + COMP3POL: u1, + /// Comparator 3 hysteresis + COMP3HYST: u2, + /// Comparator 3 blanking + /// source + COMP3_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 3 output + COMP3OUT: u1, + /// Comparator 3 lock + COMP3LOCK: u1, + }), base_address + 0x24); + + /// address: 0x40010028 + /// control and status register + pub const COMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 4 enable + COMP4EN: u1, + reserved0: u1, + /// Comparator 4 mode + COMP4MODE: u2, + /// Comparator 4 inverting input + /// selection + COMP4INSEL: u3, + /// Comparator 4 non inverted input + /// selection + COMP4INPSEL: u1, + reserved1: u1, + /// Comparator 4 window mode + COM4WINMODE: u1, + /// Comparator 4 output + /// selection + COMP4_OUT_SEL: u4, + reserved2: u1, + /// Comparator 4 output + /// polarity + COMP4POL: u1, + /// Comparator 4 hysteresis + COMP4HYST: u2, + /// Comparator 4 blanking + /// source + COMP4_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Comparator 4 output + COMP4OUT: u1, + /// Comparator 4 lock + COMP4LOCK: u1, + }), base_address + 0x28); + + /// address: 0x4001002c + /// control and status register + pub const COMP5_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 5 enable + COMP5EN: u1, + reserved0: u1, + /// Comparator 5 mode + COMP5MODE: u2, + /// Comparator 5 inverting input + /// selection + COMP5INSEL: u3, + /// Comparator 5 non inverted input + /// selection + COMP5INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 5 output + /// selection + COMP5_OUT_SEL: u4, + reserved3: u1, + /// Comparator 5 output + /// polarity + COMP5POL: u1, + /// Comparator 5 hysteresis + COMP5HYST: u2, + /// Comparator 5 blanking + /// source + COMP5_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator51 output + COMP5OUT: u1, + /// Comparator 5 lock + COMP5LOCK: u1, + }), base_address + 0x2c); + + /// address: 0x40010030 + /// control and status register + pub const COMP6_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 6 enable + COMP6EN: u1, + reserved0: u1, + /// Comparator 6 mode + COMP6MODE: u2, + /// Comparator 6 inverting input + /// selection + COMP6INSEL: u3, + /// Comparator 6 non inverted input + /// selection + COMP6INPSEL: u1, + reserved1: u1, + /// Comparator 6 window mode + COM6WINMODE: u1, + /// Comparator 6 output + /// selection + COMP6_OUT_SEL: u4, + reserved2: u1, + /// Comparator 6 output + /// polarity + COMP6POL: u1, + /// Comparator 6 hysteresis + COMP6HYST: u2, + /// Comparator 6 blanking + /// source + COMP6_BLANKING: u3, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Comparator 6 output + COMP6OUT: u1, + /// Comparator 6 lock + COMP6LOCK: u1, + }), base_address + 0x30); + + /// address: 0x40010034 + /// control and status register + pub const COMP7_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Comparator 7 enable + COMP7EN: u1, + reserved0: u1, + /// Comparator 7 mode + COMP7MODE: u2, + /// Comparator 7 inverting input + /// selection + COMP7INSEL: u3, + /// Comparator 7 non inverted input + /// selection + COMP7INPSEL: u1, + reserved1: u1, + reserved2: u1, + /// Comparator 7 output + /// selection + COMP7_OUT_SEL: u4, + reserved3: u1, + /// Comparator 7 output + /// polarity + COMP7POL: u1, + /// Comparator 7 hysteresis + COMP7HYST: u2, + /// Comparator 7 blanking + /// source + COMP7_BLANKING: u3, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Comparator 7 output + COMP7OUT: u1, + /// Comparator 7 lock + COMP7LOCK: u1, + }), base_address + 0x34); + + /// address: 0x40010038 + /// control register + pub const OPAMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP1 enable + OPAMP1_EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP1 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP1 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP1 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP1 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 1 ouput status flag + OUTCAL: u1, + /// OPAMP 1 lock + LOCK: u1, + }), base_address + 0x38); + + /// address: 0x4001003c + /// control register + pub const OPAMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP2 enable + OPAMP2EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP2 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP2 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP2 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP2 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CAL_SEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 2 ouput status flag + OUTCAL: u1, + /// OPAMP 2 lock + LOCK: u1, + }), base_address + 0x3c); + + /// address: 0x40010040 + /// control register + pub const OPAMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP3 enable + OPAMP3EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP3 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP3 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP3 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP3 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 3 ouput status flag + OUTCAL: u1, + /// OPAMP 3 lock + LOCK: u1, + }), base_address + 0x40); + + /// address: 0x40010044 + /// control register + pub const OPAMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// OPAMP4 enable + OPAMP4EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP4 Non inverting input + /// selection + VP_SEL: u2, + reserved0: u1, + /// OPAMP4 inverting input + /// selection + VM_SEL: u2, + /// Timer controlled Mux mode + /// enable + TCM_EN: u1, + /// OPAMP4 inverting input secondary + /// selection + VMS_SEL: u1, + /// OPAMP4 Non inverting input secondary + /// selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value + /// (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value + /// (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 4 ouput status flag + OUTCAL: u1, + /// OPAMP 4 lock + LOCK: u1, + }), base_address + 0x44); + }; + /// Flexible memory controller + pub const FMC = struct { + pub const base_address = 0xa0000400; + + /// address: 0xa0000400 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x0); + + /// address: 0xa0000404 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000408 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000040c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000410 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000414 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000418 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000041c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000460 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000464 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000468 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000046c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000474 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000480 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000484 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000488 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000048c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000494 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00004a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00004a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00004a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00004ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00004b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000504 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000050c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000514 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x114); + + /// address: 0xa000051c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase + /// duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x11c); + }; + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x4); + + /// address: 0xe000e108 + /// Interrupt Set-Enable Register + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETENA + SETENA: u32, + }), base_address + 0x8); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x84); + + /// address: 0xe000e188 + /// Interrupt Clear-Enable + /// Register + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRENA + CLRENA: u32, + }), base_address + 0x88); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x104); + + /// address: 0xe000e208 + /// Interrupt Set-Pending Register + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// SETPEND + SETPEND: u32, + }), base_address + 0x108); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x184); + + /// address: 0xe000e288 + /// Interrupt Clear-Pending + /// Register + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x188); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x204); + + /// address: 0xe000e308 + /// Interrupt Active Bit Register + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x208); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x300); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x304); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x308); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x30c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x310); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x314); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x318); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x31c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x320); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x324); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x328); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x32c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x330); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x334); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x338); + + /// address: 0xe000e43c + /// Interrupt Priority Register + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x33c); + + /// address: 0xe000e440 + /// Interrupt Priority Register + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x340); + + /// address: 0xe000e444 + /// Interrupt Priority Register + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x344); + + /// address: 0xe000e448 + /// Interrupt Priority Register + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x348); + + /// address: 0xe000e44c + /// Interrupt Priority Register + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x34c); + + /// address: 0xe000e450 + /// Interrupt Priority Register + pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct{ + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x350); + }; + /// Floting point unit + pub const FPU = struct { + pub const base_address = 0xe000ef34; + + /// address: 0xe000ef34 + /// Floating-point context control + /// register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved0: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved1: u1, + /// MONRDY + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), base_address + 0x0); + + /// address: 0xe000ef38 + /// Floating-point context address + /// register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Location of unpopulated + /// floating-point + ADDRESS: u29, + }), base_address + 0x4); + + /// address: 0xe000ef3c + /// Floating-point status control + /// register + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Invalid operation cumulative exception + /// bit + IOC: u1, + /// Division by zero cumulative exception + /// bit. + DZC: u1, + /// Overflow cumulative exception + /// bit + OFC: u1, + /// Underflow cumulative exception + /// bit + UFC: u1, + /// Inexact cumulative exception + /// bit + IXC: u1, + reserved0: u1, + reserved1: u1, + /// Input denormal cumulative exception + /// bit. + IDC: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Rounding Mode control + /// field + RMode: u2, + /// Flush-to-zero mode control + /// bit: + FZ: u1, + /// Default NaN mode control + /// bit + DN: u1, + /// Alternative half-precision control + /// bit + AHP: u1, + reserved16: u1, + /// Overflow condition code + /// flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code + /// flag + N: u1, + }), base_address + 0x8); + }; + /// Memory protection unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU type register + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct{ + /// Separate flag + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction + /// regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU control register + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard + /// fault + HFNMIENA: u1, + /// Enable priviliged software access to + /// default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU region number register + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct{ + /// MPU region + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU region base address + /// register + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct{ + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU region attribute and size + /// register + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection + /// region + SIZE: u5, + reserved0: u1, + reserved1: u1, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved2: u1, + reserved3: u1, + /// Access permission + AP: u3, + reserved4: u1, + /// Instruction access disable + /// bit + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + }; + /// SysTick timer + pub const STK = struct { + pub const base_address = 0xe000e010; + + /// address: 0xe000e010 + /// SysTick control and status + /// register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Counter enable + ENABLE: u1, + /// SysTick exception request + /// enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// COUNTFLAG + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0xe000e014 + /// SysTick reload value register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct{ + /// RELOAD value + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0xe000e018 + /// SysTick current value register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct{ + /// Current counter value + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0xe000e01c + /// SysTick calibration value + /// register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct{ + /// Calibration value + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// SKEW flag: Indicates whether the TENMS + /// value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), base_address + 0xc); + }; + /// System control block + pub const SCB = struct { + pub const base_address = 0xe000ed00; + + /// address: 0xe000ed00 + /// CPUID base register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct{ + /// Revision number + Revision: u4, + /// Part number of the + /// processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), base_address + 0x0); + + /// address: 0xe000ed04 + /// Interrupt control and state + /// register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Active vector + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt pending flag + ISRPENDING: u1, + reserved5: u1, + reserved6: u1, + /// SysTick exception clear-pending + /// bit + PENDSTCLR: u1, + /// SysTick exception set-pending + /// bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), base_address + 0x4); + + /// address: 0xe000ed08 + /// Vector table offset register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Vector table base offset + /// field + TBLOFF: u21, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0xe000ed0c + /// Application interrupt and reset control + /// register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PRIGROUP + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), base_address + 0xc); + + /// address: 0xe000ed10 + /// System control register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0xe000ed14 + /// Configuration and control + /// register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Configures how the processor enters + /// Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved0: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0xe000ed18 + /// System handler priority + /// registers + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + /// Priority of system handler + /// 4 + PRI_4: u8, + /// Priority of system handler + /// 5 + PRI_5: u8, + /// Priority of system handler + /// 6 + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000ed1c + /// System handler priority + /// registers + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler + /// 11 + PRI_11: u8, + }), base_address + 0x1c); + + /// address: 0xe000ed20 + /// System handler priority + /// registers + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler + /// 14 + PRI_14: u8, + /// Priority of system handler + /// 15 + PRI_15: u8, + }), base_address + 0x20); + + /// address: 0xe000ed24 + /// System handler control and state + /// register + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct{ + /// Memory management fault exception active + /// bit + MEMFAULTACT: u1, + /// Bus fault exception active + /// bit + BUSFAULTACT: u1, + reserved0: u1, + /// Usage fault exception active + /// bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active + /// bit + PENDSVACT: u1, + /// SysTick exception active + /// bit + SYSTICKACT: u1, + /// Usage fault exception pending + /// bit + USGFAULTPENDED: u1, + /// Memory management fault exception + /// pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending + /// bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable + /// bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0xe000ed28 + /// Configurable fault status + /// register + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Instruction access violation + /// flag + IACCVIOL: u1, + reserved1: u1, + /// Memory manager fault on unstacking for a + /// return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for + /// exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved2: u1, + /// Memory Management Fault Address Register + /// (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return + /// from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception + /// entry + STKERR: u1, + /// Bus fault on floating-point lazy state + /// preservation + LSPERR: u1, + reserved3: u1, + /// Bus Fault Address Register (BFAR) valid + /// flag + BFARVALID: u1, + /// Undefined instruction usage + /// fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage + /// fault + INVPC: u1, + /// No coprocessor usage + /// fault. + NOCP: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Unaligned access usage + /// fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0xe000ed2c + /// Hard fault status register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), base_address + 0x2c); + + /// address: 0xe000ed34 + /// Memory management fault address + /// register + pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0xe000ed38 + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0xe000ed3c + /// Auxiliary fault status + /// register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Implementation defined + IMPDEF: u32, + }), base_address + 0x3c); + }; + /// Nested vectored interrupt + /// controller + pub const NVIC_STIR = struct { + pub const base_address = 0xe000ef00; + + /// address: 0xe000ef00 + /// Software trigger interrupt + /// register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + /// Software generated interrupt + /// ID + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + }; + /// Floating point unit CPACR + pub const FPU_CPACR = struct { + pub const base_address = 0xe000ed88; + + /// address: 0xe000ed88 + /// Coprocessor access control + /// register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct{ + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// CP + CP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + }; + /// System control block ACTLR + pub const SCB_ACTRL = struct { + pub const base_address = 0xe000e008; + + /// address: 0xe000e008 + /// Auxiliary control register + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct{ + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + }; }; -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); } -export const vectors: VectorTable linksection("microzig_flash_start") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, "vector_table")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog("root.vector_table must be a struct"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "', declarations in 'root.vector_table' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); } - } - break :blk temp; + }.tmp, }; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 4fb8ca0..91f25cd 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -1,10 +1,11 @@ const std = @import("std"); const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; -pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; +pub usingnamespace chip; +pub const cpu = @import("cpu"); pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -18,7 +19,7 @@ pub fn parsePin(comptime spec: []const u8) type { return struct { /// 'A'...'H' const gpio_port_name = spec[1..2]; - const gpio_port = @field(registers, "GPIO" ++ gpio_port_name); + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); }; } @@ -31,12 +32,12 @@ fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void pub const gpio = struct { pub fn setOutput(comptime pin: type) void { - setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); } pub fn setInput(comptime pin: type) void { - setRegField(registers.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); } diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 8c97d4f..a1713b2 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -26,32 +26,32 @@ const PLL = struct { overclock_pll(3); // 100 MHz } - fn overclock_flash(timing: u5) void { - micro.chip.registers.SYSCON.FLASHCFG.write(.{ - .FLASHTIM = @intToEnum(@TypeOf(micro.chip.registers.SYSCON.FLASHCFG.read().FLASHTIM), @intCast(u4, timing - 1)), + fn overclock_flash(timing: u4) void { + micro.chip.registers.SYSCON.FLASHCFG.modify(.{ + .FLASHTIM = timing - 1, }); } inline fn feed_pll() void { - micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0xAA }); - micro.chip.registers.SYSCON.PLL0FEED.write(.{ .PLL0FEED = 0x55 }); + micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0xAA }); + micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0x55 }); } fn overclock_pll(divider: u8) void { // PLL einrichten für RC - micro.chip.registers.SYSCON.PLL0CON.write(.{ + micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = 0, .PLLC0 = 0, }); feed_pll(); - micro.chip.registers.SYSCON.CLKSRCSEL.write(.{ .CLKSRC = .SELECTS_THE_INTERNAL }); // RC-Oszillator als Quelle - micro.chip.registers.SYSCON.PLL0CFG.write(.{ + micro.chip.registers.SYSCON.CLKSRCSEL.modify(.{ .CLKSRC = 0 }); // RC-Oszillator als Quelle + micro.chip.registers.SYSCON.PLL0CFG.modify(.{ // SysClk = (4MHz / 2) * (2 * 75) = 300 MHz .MSEL0 = 74, .NSEL0 = 1, }); // CPU Takt = SysClk / divider - micro.chip.registers.SYSCON.CCLKCFG.write(.{ .CCLKSEL = divider - 1 }); + micro.chip.registers.SYSCON.CCLKCFG.modify(.{ .CCLKSEL = divider - 1 }); feed_pll(); From d4120f9c9913eea61b410908314ee91cbc8f1311 Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Thu, 10 Mar 2022 22:41:49 +0100 Subject: [PATCH 031/138] After #23 repair Reset on stm32, lpc1768 (#24) --- src/core/start.zig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/core/start.zig b/src/core/start.zig index 73f33da..c802b01 100644 --- a/src/core/start.zig +++ b/src/core/start.zig @@ -14,6 +14,7 @@ const VectorTable = microzig.chip.VectorTable; export const vector_table: VectorTable linksection("microzig_flash_start") = blk: { var tmp: microzig.chip.VectorTable = .{ .initial_stack_pointer = microzig.config.end_of_stack, + .Reset = .{ .C = microzig.cpu.startup_logic._start }, }; if (@hasDecl(app, "interrupts")) { if (@typeInfo(app.interrupts) != .Struct) From 92a2922742499f514ef4c29fefc78504aef6022e Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Thu, 10 Mar 2022 22:42:31 +0100 Subject: [PATCH 032/138] stm32f3discovery/stm32f303 Initial UART1 support, including @panic() (#20) * build.zig: Trivial rename around UART test * mmio: Add writeRaw() to set a full register * UART: Add TODO for auto baud rate detection * STM32F30x Initial USART1 output/transmit support All code assumes default chip clock configuration. Code assumes STM32F303xB / STM32F3030xC. Code supports only 8 data bits, 1 stop bit. * stm32f3discovery @panic() to UART1 This is done by implementing `debugWrite()` for the board, which only initializes UART1 if that was not yet done, and flushes afterwards to make sure the host receives all. * stm32f303: Support UART1 reader This is done by implementing `rx()` and `canRead()`. * stm32f303 UART1 correctly support 7 and 8 bits This includes correctly masking the parity bit on reads. * stm32f3 UART1 support 0.5/1.5/2 stop bits * stm32f303 UART1 simplify parity code * Make work with regz-generated registers.zig change * After #23 repair Reset on stm32, lpc1768 --- build.zig | 6 +- src/core/mmio.zig | 6 +- src/core/uart.zig | 13 ++ .../stm32f3discovery/stm32f3discovery.zig | 14 ++ src/modules/chips/stm32f303/stm32f303.zig | 179 ++++++++++++++++++ 5 files changed, 214 insertions(+), 4 deletions(-) diff --git a/build.zig b/build.zig index bb380ae..e570737 100644 --- a/build.zig +++ b/build.zig @@ -14,14 +14,14 @@ pub fn build(b: *std.build.Builder) !void { const test_step = b.step("test", "Builds and runs the library test suite"); - const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart: bool = true }; + const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true }; const all_backings = [_]BuildConfig{ //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, - BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart = false }, + BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, }; const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false }; @@ -38,7 +38,7 @@ pub fn build(b: *std.build.Builder) !void { inline for (all_backings) |cfg| { inline for (all_tests) |tst| { - if (tst.uses_uart and !cfg.supports_uart) continue; + if (tst.uses_uart and !cfg.supports_uart_test) continue; const exe = try microzig.addEmbeddedExecutable( b, diff --git a/src/core/mmio.zig b/src/core/mmio.zig index 4df5ef4..70ba1f7 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -31,7 +31,11 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { // This is a workaround for a compiler bug related to miscompilation // If the tmp var is not used, result location will fuck things up var tmp = @bitCast(IntT, val); - addr.raw = tmp; + addr.writeRaw(tmp); + } + + pub fn writeRaw(addr: *volatile Self, val: IntT) void { + addr.raw = val; } pub fn modify(addr: *volatile Self, fields: anytype) void { diff --git a/src/core/uart.zig b/src/core/uart.zig index 1cf8e41..f84d2dc 100644 --- a/src/core/uart.zig +++ b/src/core/uart.zig @@ -17,6 +17,18 @@ pub fn Uart(comptime index: usize) type { }; } + /// If the UART is already initialized, try to return a handle to it, + /// else initialize with the given config. + pub fn getOrInit(config: Config) InitError!Self { + if (!@hasDecl(SystemUart, "getOrInit")) { + // fallback to reinitializing the UART + return init(config); + } + return Self{ + .internal = try SystemUart.getOrInit(config), + }; + } + pub fn canRead(self: Self) bool { return self.internal.canRead(); } @@ -54,6 +66,7 @@ pub fn Uart(comptime index: usize) type { /// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the /// most common serial format. pub const Config = struct { + /// TODO: Make this optional, to support STM32F303 et al. auto baud-rate detection? baud_rate: u32, stop_bits: StopBits = .one, parity: ?Parity = null, diff --git a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig index 8f2aa47..995e8a5 100644 --- a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig +++ b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig @@ -1,4 +1,5 @@ pub const chip = @import("chip"); +pub const micro = @import("microzig"); pub const cpu_frequency = 8_000_000; @@ -22,3 +23,16 @@ pub const pin_map = .{ // W green .@"LD6" = "PE15", }; + +pub fn debugWrite(string: []const u8) void { + const uart1 = micro.Uart(1).getOrInit(.{ + .baud_rate = 9600, + .data_bits = .eight, + .parity = null, + .stop_bits = .one, + }) catch unreachable; + + const writer = uart1.writer(); + _ = writer.write(string) catch unreachable; + uart1.internal.txflush(); +} diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 91f25cd..97122b1 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -1,3 +1,39 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code currently assumes the STM32F303xB / STM32F303xC clock configuration. +//! TODO: Do something useful for other STM32f30x chips. +//! +//! Specifically, TIM6 is running on an 8 MHz clock, +//! HSI = 8 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 8 MHz. +//! And with the default APB1 prescaler = /2: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE1 = 4 }); +//! ``` +//! +//! results in PCLK1, +//! and the resulting implicit factor *2 for TIM2/3/4/6/7 +//! makes TIM6 run at 8MHz/2*2 = 8 MHz. +//! +//! The above default configuration makes U(S)ART2..5 +//! (which use PCLK1 without that implicit *2 factor) +//! run at 4 MHz by default. +//! +//! USART1 uses PCLK2, which uses the APB2 prescaler on HCLK, +//! default APB2 prescaler = /1: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE2 = 0 }); +//! ``` +//! +//! and therefore USART1 runs on 8 MHz. + const std = @import("std"); const micro = @import("microzig"); const chip = @import("registers.zig"); @@ -55,3 +91,146 @@ pub const gpio = struct { } } }; + +pub const uart = struct { + pub const DataBits = enum(u4) { + seven = 7, + eight = 8, + }; + + /// uses the values of USART_CR2.STOP + pub const StopBits = enum(u2) { + one = 0b00, + half = 0b01, + two = 0b10, + one_and_half = 0b11, + }; + + /// uses the values of USART_CR1.PS + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; +}; + +pub fn Uart(comptime index: usize) type { + if (!(index == 1)) @compileError("TODO: only USART1 is currently supported"); + + return struct { + parity_read_mask: u8, + + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + // The following must all be written when the USART is disabled (UE=0). + if (regs.USART1.CR1.read().UE == 1) + @panic("Trying to initialize USART1 while it is already enabled"); + // LATER: Alternatively, set UE=0 at this point? Then wait for something? + // Or add a destroy() function which disables the USART? + + // enable the USART1 clock + regs.RCC.APB2ENR.modify(.{ .USART1EN = 1 }); + // enable GPIOC clock + regs.RCC.AHBENR.modify(.{ .IOPCEN = 1 }); + // set PC4+PC5 to alternate function 7, USART1_TX + USART1_RX + regs.GPIOC.MODER.modify(.{ .MODER4 = 0b10, .MODER5 = 0b10 }); + regs.GPIOC.AFRL.modify(.{ .AFRL4 = 7, .AFRL5 = 7 }); + + // clear USART1 configuration to its default + regs.USART1.CR1.raw = 0; + regs.USART1.CR2.raw = 0; + regs.USART1.CR3.raw = 0; + + // set word length + // Per the reference manual, M[1:0] means + // - 00: 8 bits (7 data + 1 parity, or 8 data), probably the chip default + // - 01: 9 bits (8 data + 1 parity) + // - 10: 7 bits (7 data) + // So M1==1 means "7-bit mode" (in which + // "the Smartcard mode, LIN master mode and Auto baud rate [...] are not supported"); + // and M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + const m1: u1 = if (config.data_bits == .seven and config.parity == null) 1 else 0; + const m0: u1 = if (config.data_bits == .eight and config.parity != null) 1 else 0; + // Note that .padding0 = bit 28 = .M1 (.svd file bug?), and .M == .M0. + regs.USART1.CR1.modify(.{ .padding0 = m1, .M = m0 }); + + // set parity + if (config.parity) |parity| { + regs.USART1.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); + } else regs.USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default + + // set number of stop bits + regs.USART1.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); + + // set the baud rate + // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency + // from the chip, which can be affected by how the board configures the chip. + // In our case, these are accidentally the same at chip reset, + // if the board doesn't configure e.g. an HSE external crystal. + // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) + // TODO: Do a rounding div, instead of a truncating div? + const usartdiv = @intCast(u16, @divTrunc(micro.board.cpu_frequency, config.baud_rate)); + regs.USART1.BRR.raw = usartdiv; + // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction, + // those seem to be for another chipset; .svd file bug? + // TODO: We assume the default OVER8=0 configuration above. + + // enable USART1, and its transmitter and receiver + regs.USART1.CR1.modify(.{ .UE = 1 }); + regs.USART1.CR1.modify(.{ .TE = 1 }); + regs.USART1.CR1.modify(.{ .RE = 1 }); + + // For code simplicity, at cost of one or more register reads, + // we read back the actual configuration from the registers, + // instead of using the `config` values. + return readFromRegisters(); + } + + pub fn getOrInit(config: micro.uart.Config) !Self { + if (regs.USART1.CR1.read().UE == 1) { + // UART1 already enabled, don't reinitialize and disturb things; + // instead read and use the actual configuration. + return readFromRegisters(); + } else return init(config); + } + + fn readFromRegisters() Self { + const cr1 = regs.USART1.CR1.read(); + // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, + // then we also mask away the 8th bit. + return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return switch (regs.USART1.ISR.read().TXE) { + 1 => true, + 0 => false, + }; + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + regs.USART1.TDR.modify(ch); + } + + pub fn txflush(_: Self) void { + while (regs.USART1.ISR.read().TC == 0) {} + } + + pub fn canRead(self: Self) bool { + _ = self; + return switch (regs.USART1.ISR.read().RXNE) { + 1 => true, + 0 => false, + }; + } + + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + const data_with_parity_bit: u9 = regs.USART1.RDR.read().RDR; + return @intCast(u8, data_with_parity_bit & self.parity_read_mask); + } + }; +} From 5050ce5eb024cbcd6ac1937855fe0b71dd23540a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 11 Mar 2022 13:29:50 +0100 Subject: [PATCH 033/138] Diverse fixes (#25) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Makes default panic uses logging facilities to print the panic message. * Makes MMIO functions inline for better codegen * Brings LPC1768 up to date. Co-authored-by: Felix "xq" Queißner --- src/core/microzig.zig | 4 + src/core/mmio.zig | 8 +- src/modules/chips/lpc1768/lpc1768.zig | 12 +- src/modules/chips/lpc1768/registers.zig | 142 +++++++++++++----------- 4 files changed, 87 insertions(+), 79 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 893a8ab..d7805e6 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -39,6 +39,10 @@ pub const debug = @import("debug.zig"); /// pub const panic = micro.panic; /// ``` pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { + // utilize logging functions + std.log.err("microzig PANIC: {s}", .{message}); + + // then use the current debug channel var writer = debug.writer(); writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable; if (maybe_stack_trace) |stack_trace| { diff --git a/src/core/mmio.zig b/src/core/mmio.zig index 70ba1f7..cb6b347 100644 --- a/src/core/mmio.zig +++ b/src/core/mmio.zig @@ -23,11 +23,11 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { pub const underlying_type = PackedT; - pub fn read(addr: *volatile Self) PackedT { + pub inline fn read(addr: *volatile Self) PackedT { return @bitCast(PackedT, addr.raw); } - pub fn write(addr: *volatile Self, val: PackedT) void { + pub inline fn write(addr: *volatile Self, val: PackedT) void { // This is a workaround for a compiler bug related to miscompilation // If the tmp var is not used, result location will fuck things up var tmp = @bitCast(IntT, val); @@ -38,7 +38,7 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { addr.raw = val; } - pub fn modify(addr: *volatile Self, fields: anytype) void { + pub inline fn modify(addr: *volatile Self, fields: anytype) void { var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, field.name) = @field(fields, field.name); @@ -46,7 +46,7 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { write(addr, val); } - pub fn toggle(addr: *volatile Self, fields: anytype) void { + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 907b7c9..ace8395 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -144,7 +144,7 @@ pub fn Uart(comptime index: usize) type { // 8N1 .WLS = @enumToInt(config.data_bits), .SBS = @enumToInt(config.stop_bits), - .PE = if (config.parity) |_| @as(u1, 0) else @as(u1, 1), + .PE = if (config.parity != null) @as(u1, 1) else @as(u1, 0), .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd), .BC = 0, .DLAB = 1, @@ -174,10 +174,7 @@ pub fn Uart(comptime index: usize) type { pub fn canWrite(self: Self) bool { _ = self; - return switch (UARTn.LSR.read().THRE) { - 0 => true, // valid - 1 => false, // is empty - }; + return (UARTn.LSR.read().THRE == 1); } pub fn tx(self: Self, ch: u8) void { while (!self.canWrite()) {} // Wait for Previous transmission @@ -186,10 +183,7 @@ pub fn Uart(comptime index: usize) type { pub fn canRead(self: Self) bool { _ = self; - return switch (UARTn.LSR.read().RDR) { - 0 => false, // empty - 1 => true, // not empty - }; + return (UARTn.LSR.read().RDR == 1); } pub fn rx(self: Self) u8 { while (!self.canRead()) {} // Wait till the data is received diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 160617f..b382030 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -552,7 +552,8 @@ pub const registers = struct { /// FIFO and the transmitter is available. THR: u8, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x0); /// address: 0x4000c000 @@ -564,7 +565,8 @@ pub const registers = struct { /// the baud rate of the UARTn. DLLSB: u8, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x0); /// address: 0x4000c004 @@ -576,7 +578,8 @@ pub const registers = struct { /// the baud rate of the UARTn. DLMSB: u8, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x4); /// address: 0x4000c004 @@ -644,7 +647,8 @@ pub const registers = struct { /// characters must be written before an interrupt or DMA request is activated. RXTRIGLVL: u2, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x8); /// address: 0x4000c00c @@ -734,7 +738,8 @@ pub const registers = struct { /// errors in the UARTn FIFO. RXFE: u1, /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x14); /// address: 0x4000c01c @@ -743,7 +748,8 @@ pub const registers = struct { /// A readable, writable byte. PAD: u8, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x1c); /// address: 0x4000c020 @@ -778,7 +784,8 @@ pub const registers = struct { /// generator is used or not. MULVAL: u4, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x28); /// address: 0x4000c030 @@ -797,7 +804,8 @@ pub const registers = struct { /// (DC3). Software can set this bit again when it receives an XON (DC1) character. TXEN: u1, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x30); /// address: 0x4000c04c @@ -838,7 +846,8 @@ pub const registers = struct { /// conjunction with an 8-bit counter. DLY: u8, /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, + RESERVED0: u8, + RESERVED1: u16, }), base_address + 0x54); }; /// UART1 @@ -5954,7 +5963,8 @@ pub const registers = struct { CPSDVSR: u8, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - RESERVED: u24, + RESERVED0: u8 = 0, + RESERVED1: u16 = 0, }), base_address + 0x10); /// address: 0x40088014 @@ -8670,13 +8680,13 @@ pub const registers = struct { /// Flash Accelerator Configuration Register. Controls flash access timing. pub const FLASHCFG = @intToPtr(*volatile Mmio(32, packed struct { /// Reserved, user software should not change these bits from the reset value. - reserved0: u12, + reserved0: u12 = 0, /// Flash access time. The value of this field plus 1 gives the number of CPU clocks /// used for a flash access. Warning: improper setting of this value may result in /// incorrect operation of the device. Other values are reserved. FLASHTIM: u4, /// Reserved. The value read from a reserved bit is not defined. - reserved1: u16, + reserved1: u16 = 0, }), base_address + 0x0); /// address: 0x400fc080 @@ -8693,7 +8703,7 @@ pub const registers = struct { PLLC0: u1, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - RESERVED: u30, + RESERVED: u30=0, }), base_address + 0x80); /// address: 0x400fc084 @@ -8705,13 +8715,13 @@ pub const registers = struct { MSEL0: u15, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - reserved0: u1, + reserved0: u1 = 0, /// PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The /// value stored here is N - 1. Supported values for N are 1 through 32. NSEL0: u8, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - reserved1: u8, + reserved1: u8 = 0, }), base_address + 0x84); /// address: 0x400fc088 @@ -8753,30 +8763,30 @@ pub const registers = struct { PLL0FEED: u8, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, }), base_address + 0x8c); /// address: 0x400fc0a0 @@ -8976,30 +8986,30 @@ pub const registers = struct { CCLKSEL: u8, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, }), base_address + 0x104); /// address: 0x400fc108 @@ -9026,7 +9036,7 @@ pub const registers = struct { CLKSRC: u2, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - RESERVED: u30, + RESERVED: u30=0, }), base_address + 0x10c); /// address: 0x400fc110 @@ -9228,7 +9238,7 @@ pub const registers = struct { /// Peripheral clock selection for I2C1. PCLK_I2C1: u2, /// Reserved. - RESERVED: u2, + RESERVED0: u2=1, /// Peripheral clock selection for SSP0. PCLK_SSP0: u2, /// Peripheral clock selection for TIMER2. @@ -9244,7 +9254,7 @@ pub const registers = struct { /// Peripheral clock selection for I2S. PCLK_I2S: u2, /// Reserved. - RESERVED: u2, + RESERVED1: u2=1, /// Peripheral clock selection for Repetitive Interrupt Timer. PCLK_RIT: u2, /// Peripheral clock selection for the System Control block. From 1c1730445ca992d7510b9446ac8cddb0cfc2bbbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Mon, 14 Mar 2022 17:10:00 +0100 Subject: [PATCH 034/138] Brings AVR up to date (blink builds and blinks again! (#27) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Brings AVR up to date (blink builds and blinks again! * Fixes vector tables and build. Co-authored-by: Felix "xq" Queißner --- build.zig | 19 +- src/core/microzig.zig | 29 +- src/core/start.zig | 14 +- src/main.zig | 10 +- src/modules/chips/atmega328p/atmega328p.zig | 11 +- src/modules/chips/lpc1768/registers.zig | 2 +- src/modules/chips/nrf52/registers.zig | 676 +++---- src/modules/chips/stm32f103/registers.zig | 1240 ++++++------- src/modules/chips/stm32f303/registers.zig | 1784 +++++++++---------- 9 files changed, 1905 insertions(+), 1880 deletions(-) diff --git a/build.zig b/build.zig index e570737..cb8771c 100644 --- a/build.zig +++ b/build.zig @@ -16,33 +16,34 @@ pub fn build(b: *std.build.Builder) !void { const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true }; const all_backings = [_]BuildConfig{ - //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, + BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, - //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = pkgs.chips.atmega328p } }, + BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, }; - const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false }; + const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true }; const all_tests = [_]Test{ Test{ .name = "minimal", .source = "tests/minimal.zig" }, Test{ .name = "blinky", .source = "tests/blinky.zig" }, - Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true }, + Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true, .on_avr = false }, // Note: this example uses the systick interrupt and therefore only for arm microcontrollers - Test{ .name = "interrupt", .source = "tests/interrupt.zig" }, + Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_avr = false }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); - inline for (all_backings) |cfg| { - inline for (all_tests) |tst| { + for (all_backings) |cfg| { + for (all_tests) |tst| { if (tst.uses_uart and !cfg.supports_uart_test) continue; + if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue; const exe = try microzig.addEmbeddedExecutable( b, - "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".elf", + b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }), tst.source, cfg.backing, .{}, @@ -56,7 +57,7 @@ pub fn build(b: *std.build.Builder) !void { const bin = b.addInstallRaw( exe, - "test-" ++ tst.name ++ "-" ++ cfg.name ++ ".bin", + b.fmt("test-{s}-{s}.bin", .{ tst.name, cfg.name }), .{}, ); b.getInstallStep().dependOn(&bin.step); diff --git a/src/core/microzig.zig b/src/core/microzig.zig index d7805e6..4343a23 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -1,5 +1,6 @@ const std = @import("std"); const root = @import("root"); +const builtin = @import("builtin"); /// Contains build-time generated configuration options for microzig. /// Contains a CPU target description, chip, board and cpu information @@ -39,22 +40,24 @@ pub const debug = @import("debug.zig"); /// pub const panic = micro.panic; /// ``` pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { + // utilize logging functions std.log.err("microzig PANIC: {s}", .{message}); - // then use the current debug channel - var writer = debug.writer(); - writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable; - if (maybe_stack_trace) |stack_trace| { - var frame_index: usize = 0; - var frames_left: usize = std.math.min(stack_trace.index, stack_trace.instruction_addresses.len); - - while (frames_left != 0) : ({ - frames_left -= 1; - frame_index = (frame_index + 1) % stack_trace.instruction_addresses.len; - }) { - const return_address = stack_trace.instruction_addresses[frame_index]; - writer.print("0x{X:0>8}\r\n", .{return_address}) catch unreachable; + if (builtin.cpu.arch != .avr) { + var writer = debug.writer(); + writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable; + + if (maybe_stack_trace) |stack_trace| { + var frame_index: usize = 0; + var frames_left: usize = std.math.min(stack_trace.index, stack_trace.instruction_addresses.len); + while (frames_left != 0) : ({ + frames_left -= 1; + frame_index = (frame_index + 1) % stack_trace.instruction_addresses.len; + }) { + const return_address = stack_trace.instruction_addresses[frame_index]; + writer.print("0x{X:0>8}\r\n", .{return_address}) catch unreachable; + } } } hang(); diff --git a/src/core/start.zig b/src/core/start.zig index c802b01..3414f48 100644 --- a/src/core/start.zig +++ b/src/core/start.zig @@ -1,5 +1,6 @@ const std = @import("std"); const app = @import("app"); +const builtin = @import("builtin"); const microzig = @import("microzig"); pub usingnamespace app; @@ -10,12 +11,23 @@ fn isValidField(field_name: []const u8) bool { !std.mem.eql(u8, field_name, "reset"); } +comptime { + if (builtin.cpu.arch == .arm or builtin.cpu.arch == .thumb) { + @export(vector_table, .{ + .name = "vector_table", + .section = "microzig_flash_start", + .linkage = .Strong, + }); + } +} + const VectorTable = microzig.chip.VectorTable; -export const vector_table: VectorTable linksection("microzig_flash_start") = blk: { +const vector_table: VectorTable = blk: { var tmp: microzig.chip.VectorTable = .{ .initial_stack_pointer = microzig.config.end_of_stack, .Reset = .{ .C = microzig.cpu.startup_logic._start }, }; + if (@hasDecl(app, "interrupts")) { if (@typeInfo(app.interrupts) != .Struct) @compileLog("root.interrupts must be a struct"); diff --git a/src/main.zig b/src/main.zig index 275ea18..9174abf 100644 --- a/src/main.zig +++ b/src/main.zig @@ -7,9 +7,17 @@ pub const cpus = @import("modules/cpus.zig"); pub const Board = @import("modules/Board.zig"); pub const Chip = @import("modules/Chip.zig"); pub const Cpu = @import("modules/Cpu.zig"); + pub const Backing = union(enum) { board: Board, chip: Chip, + + pub fn getTarget(self: @This()) std.zig.CrossTarget { + return switch (self) { + .board => |brd| brd.chip.cpu.target, + .chip => |chip| chip.cpu.target, + }; + } }; const Pkg = std.build.Pkg; @@ -133,7 +141,7 @@ pub fn addEmbeddedExecutable( // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.bundle_compiler_rt = true; + exe.bundle_compiler_rt = (exe.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now switch (backing) { .chip => { var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 1d6f83d..30b93c7 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const micro = @import("microzig"); pub const cpu = @import("cpu"); const Port = enum(u8) { @@ -42,15 +43,15 @@ pub const gpio = struct { cpu.cbi(regs(pin).dir_addr, pin.pin); } - pub fn read(comptime pin: type) u1 { + pub fn read(comptime pin: type) micro.gpio.State { return if ((regs(pin).pin.* & (1 << pin.pin)) != 0) - @as(u1, 1) + .high else - 0; + .low; } - pub fn write(comptime pin: type, state: u1) void { - if (state == 1) { + pub fn write(comptime pin: type, state: micro.gpio.State) void { + if (state == .high) { cpu.sbi(regs(pin).port_addr, pin.pin); } else { cpu.cbi(regs(pin).port_addr, pin.pin); diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index b382030..12d3ba1 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -3,7 +3,7 @@ // device: LPC176x5x // cpu: CM3 -pub const VectorTable = struct { +pub const VectorTable = extern struct { initial_stack_pointer: u32, Reset: InterruptVector = unhandled, NMI: InterruptVector = unhandled, diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig index ccde288..617e52f 100644 --- a/src/modules/chips/nrf52/registers.zig +++ b/src/modules/chips/nrf52/registers.zig @@ -4,7 +4,7 @@ // device: nrf52 // cpu: CM4 -pub const VectorTable = struct { +pub const VectorTable = extern struct { initial_stack_pointer: u32, Reset: InterruptVector = unhandled, NMI: InterruptVector = unhandled, @@ -124,7 +124,7 @@ pub const registers = struct { /// address: 0x10000000 /// Slope definition A0. - pub const A0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A0 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -151,7 +151,7 @@ pub const registers = struct { /// address: 0x10000004 /// Slope definition A1. - pub const A1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A1 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -178,7 +178,7 @@ pub const registers = struct { /// address: 0x10000008 /// Slope definition A2. - pub const A2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A2 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -205,7 +205,7 @@ pub const registers = struct { /// address: 0x1000000c /// Slope definition A3. - pub const A3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A3 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -232,7 +232,7 @@ pub const registers = struct { /// address: 0x10000010 /// Slope definition A4. - pub const A4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A4 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -259,7 +259,7 @@ pub const registers = struct { /// address: 0x10000014 /// Slope definition A5. - pub const A5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A5 = @intToPtr(*volatile Mmio(32, packed struct { /// A (slope definition) register. A: u12, padding0: u1, @@ -286,7 +286,7 @@ pub const registers = struct { /// address: 0x10000018 /// y-intercept B0. - pub const B0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B0 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -311,7 +311,7 @@ pub const registers = struct { /// address: 0x1000001c /// y-intercept B1. - pub const B1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B1 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -336,7 +336,7 @@ pub const registers = struct { /// address: 0x10000020 /// y-intercept B2. - pub const B2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B2 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -361,7 +361,7 @@ pub const registers = struct { /// address: 0x10000024 /// y-intercept B3. - pub const B3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B3 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -386,7 +386,7 @@ pub const registers = struct { /// address: 0x10000028 /// y-intercept B4. - pub const B4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B4 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -411,7 +411,7 @@ pub const registers = struct { /// address: 0x1000002c /// y-intercept B5. - pub const B5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B5 = @intToPtr(*volatile Mmio(32, packed struct { /// B (y-intercept) B: u14, padding0: u1, @@ -436,7 +436,7 @@ pub const registers = struct { /// address: 0x10000030 /// Segment end T0. - pub const T0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const T0 = @intToPtr(*volatile Mmio(32, packed struct { /// T (segment end)register. T: u8, padding0: u1, @@ -467,7 +467,7 @@ pub const registers = struct { /// address: 0x10000034 /// Segment end T1. - pub const T1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const T1 = @intToPtr(*volatile Mmio(32, packed struct { /// T (segment end)register. T: u8, padding0: u1, @@ -498,7 +498,7 @@ pub const registers = struct { /// address: 0x10000038 /// Segment end T2. - pub const T2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const T2 = @intToPtr(*volatile Mmio(32, packed struct { /// T (segment end)register. T: u8, padding0: u1, @@ -529,7 +529,7 @@ pub const registers = struct { /// address: 0x1000003c /// Segment end T3. - pub const T3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const T3 = @intToPtr(*volatile Mmio(32, packed struct { /// T (segment end)register. T: u8, padding0: u1, @@ -560,7 +560,7 @@ pub const registers = struct { /// address: 0x10000040 /// Segment end T4. - pub const T4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const T4 = @intToPtr(*volatile Mmio(32, packed struct { /// T (segment end)register. T: u8, padding0: u1, @@ -595,7 +595,7 @@ pub const registers = struct { /// address: 0x10000000 /// Default header for NFC Tag. Software can read these values to populate /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TAGHEADER0 = @intToPtr(*volatile Mmio(32, packed struct { /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F MFGID: u8, /// Unique identifier byte 1 @@ -609,7 +609,7 @@ pub const registers = struct { /// address: 0x10000004 /// Default header for NFC Tag. Software can read these values to populate /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TAGHEADER1 = @intToPtr(*volatile Mmio(32, packed struct { /// Unique identifier byte 4 UD4: u8, /// Unique identifier byte 5 @@ -623,7 +623,7 @@ pub const registers = struct { /// address: 0x10000008 /// Default header for NFC Tag. Software can read these values to populate /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TAGHEADER2 = @intToPtr(*volatile Mmio(32, packed struct { /// Unique identifier byte 8 UD8: u8, /// Unique identifier byte 9 @@ -637,7 +637,7 @@ pub const registers = struct { /// address: 0x1000000c /// Default header for NFC Tag. Software can read these values to populate /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TAGHEADER3 = @intToPtr(*volatile Mmio(32, packed struct { /// Unique identifier byte 12 UD12: u8, /// Unique identifier byte 13 @@ -684,7 +684,7 @@ pub const registers = struct { /// address: 0x10001200 /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for /// details) - pub const PSELRESET = @intToPtr(*volatile [2]Mmio(32, packed struct{ + pub const PSELRESET = @intToPtr(*volatile [2]Mmio(32, packed struct { /// GPIO number P0.n onto which Reset is exposed PIN: u6, reserved0: u1, @@ -718,7 +718,7 @@ pub const registers = struct { /// address: 0x10001208 /// Access Port protection - pub const APPROTECT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APPROTECT = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable Access Port protection. Any other value than 0xFF being /// written to this field will enable protection. PALL: u8, @@ -750,7 +750,7 @@ pub const registers = struct { /// address: 0x1000120c /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - pub const NFCPINS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NFCPINS = @intToPtr(*volatile Mmio(32, packed struct { /// Setting of pins dedicated to NFC functionality PROTECT: u1, padding0: u1, @@ -792,7 +792,7 @@ pub const registers = struct { /// address: 0x40000600 /// Block protect configuration register 0 - pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct { /// Enable protection for region 0. Write '0' has no effect. REGION0: u1, /// Enable protection for region 1. Write '0' has no effect. @@ -861,7 +861,7 @@ pub const registers = struct { /// address: 0x40000604 /// Block protect configuration register 1 - pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct { /// Enable protection for region 32. Write '0' has no effect. REGION32: u1, /// Enable protection for region 33. Write '0' has no effect. @@ -938,7 +938,7 @@ pub const registers = struct { /// address: 0x40000610 /// Block protect configuration register 2 - pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct { /// Enable protection for region 64. Write '0' has no effect. REGION64: u1, /// Enable protection for region 65. Write '0' has no effect. @@ -1007,7 +1007,7 @@ pub const registers = struct { /// address: 0x40000614 /// Block protect configuration register 3 - pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct { /// Enable protection for region 96. Write '0' has no effect. REGION96: u1, /// Enable protection for region 97. Write '0' has no effect. @@ -1100,7 +1100,7 @@ pub const registers = struct { /// address: 0x40000304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Enable interrupt for POFWARN event @@ -1140,7 +1140,7 @@ pub const registers = struct { /// address: 0x40000308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Disable interrupt for POFWARN event @@ -1180,7 +1180,7 @@ pub const registers = struct { /// address: 0x40000400 /// Reset reason - pub const RESETREAS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESETREAS = @intToPtr(*volatile Mmio(32, packed struct { /// Reset from pin-reset detected RESETPIN: u1, /// Reset from watchdog detected @@ -1228,7 +1228,7 @@ pub const registers = struct { /// address: 0x40000428 /// Deprecated register - RAM status register - pub const RAMSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RAMSTATUS = @intToPtr(*volatile Mmio(32, packed struct { /// RAM block 0 is on or off/powering up RAMBLOCK0: u1, /// RAM block 1 is on or off/powering up @@ -1273,7 +1273,7 @@ pub const registers = struct { /// address: 0x40000510 /// Power failure comparator configuration - pub const POFCON = @intToPtr(*volatile Mmio(32, packed struct{ + pub const POFCON = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable power failure comparator POF: u1, /// Power failure comparator threshold setting @@ -1313,7 +1313,7 @@ pub const registers = struct { /// address: 0x40000520 /// General purpose retention register - pub const GPREGRET2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GPREGRET2 = @intToPtr(*volatile Mmio(32, packed struct { /// General purpose retention register GPREGRET: u8, padding0: u1, @@ -1344,7 +1344,7 @@ pub const registers = struct { /// address: 0x40000524 /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMON = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RAMON = @intToPtr(*volatile Mmio(32, packed struct { /// Keep RAM block 0 on or off in system ON Mode ONRAM0: u1, /// Keep RAM block 1 on or off in system ON Mode @@ -1385,7 +1385,7 @@ pub const registers = struct { /// address: 0x40000554 /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMONB = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RAMONB = @intToPtr(*volatile Mmio(32, packed struct { /// Keep RAM block 2 on or off in system ON Mode ONRAM2: u1, /// Keep RAM block 3 on or off in system ON Mode @@ -1430,7 +1430,7 @@ pub const registers = struct { pub const RAM = @ptrCast(*volatile [8]packed struct { /// Description cluster[0]: RAM0 power control register - POWER: Mmio(32, packed struct{ + POWER: Mmio(32, packed struct { /// Keep RAM section S0 ON or OFF in System ON mode. S0POWER: u1, /// Keep RAM section S1 ON or OFF in System ON mode. @@ -1470,7 +1470,7 @@ pub const registers = struct { }), /// Description cluster[0]: RAM0 power control set register - POWERSET: Mmio(32, packed struct{ + POWERSET: Mmio(32, packed struct { /// Keep RAM section S0 of RAM0 on or off in System ON mode S0POWER: u1, /// Keep RAM section S1 of RAM0 on or off in System ON mode @@ -1510,7 +1510,7 @@ pub const registers = struct { }), /// Description cluster[0]: RAM0 power control clear register - POWERCLR: Mmio(32, packed struct{ + POWERCLR: Mmio(32, packed struct { /// Keep RAM section S0 of RAM0 on or off in System ON mode S0POWER: u1, /// Keep RAM section S1 of RAM0 on or off in System ON mode @@ -1601,7 +1601,7 @@ pub const registers = struct { /// address: 0x40000304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for HFCLKSTARTED event HFCLKSTARTED: u1, /// Write '1' to Enable interrupt for LFCLKSTARTED event @@ -1642,7 +1642,7 @@ pub const registers = struct { /// address: 0x40000308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for HFCLKSTARTED event HFCLKSTARTED: u1, /// Write '1' to Disable interrupt for LFCLKSTARTED event @@ -1683,7 +1683,7 @@ pub const registers = struct { /// address: 0x40000408 /// Status indicating that HFCLKSTART task has been triggered - pub const HFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct { /// HFCLKSTART task triggered or not STATUS: u1, padding0: u1, @@ -1721,7 +1721,7 @@ pub const registers = struct { /// address: 0x4000040c /// HFCLK status - pub const HFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct { /// Source of HFCLK SRC: u1, reserved0: u1, @@ -1760,7 +1760,7 @@ pub const registers = struct { /// address: 0x40000414 /// Status indicating that LFCLKSTART task has been triggered - pub const LFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct { /// LFCLKSTART task triggered or not STATUS: u1, padding0: u1, @@ -1798,7 +1798,7 @@ pub const registers = struct { /// address: 0x40000418 /// LFCLK status - pub const LFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct { /// Source of LFCLK SRC: u2, reserved0: u1, @@ -1836,7 +1836,7 @@ pub const registers = struct { /// address: 0x4000041c /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - pub const LFCLKSRCCOPY = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LFCLKSRCCOPY = @intToPtr(*volatile Mmio(32, packed struct { /// Clock source SRC: u2, padding0: u1, @@ -1873,7 +1873,7 @@ pub const registers = struct { /// address: 0x40000518 /// Clock source for the LFCLK - pub const LFCLKSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LFCLKSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Clock source SRC: u2, reserved0: u1, @@ -1916,7 +1916,7 @@ pub const registers = struct { /// address: 0x4000055c /// Clocking options for the Trace Port debug interface - pub const TRACECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TRACECONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock /// divided by two. TRACEPORTSPEED: u2, @@ -2038,7 +2038,7 @@ pub const registers = struct { /// address: 0x40001200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between READY event and START task READY_START: u1, /// Shortcut between END event and DISABLE task @@ -2083,7 +2083,7 @@ pub const registers = struct { /// address: 0x40001304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for READY event READY: u1, /// Write '1' to Enable interrupt for ADDRESS event @@ -2131,7 +2131,7 @@ pub const registers = struct { /// address: 0x40001308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for READY event READY: u1, /// Write '1' to Disable interrupt for ADDRESS event @@ -2199,7 +2199,7 @@ pub const registers = struct { /// address: 0x40001508 /// Frequency - pub const FREQUENCY = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FREQUENCY = @intToPtr(*volatile Mmio(32, packed struct { /// Radio channel frequency FREQUENCY: u7, reserved0: u1, @@ -2240,7 +2240,7 @@ pub const registers = struct { /// address: 0x40001514 /// Packet configuration register 0 - pub const PCNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCNF0 = @intToPtr(*volatile Mmio(32, packed struct { /// Length on air of LENGTH field in number of bits. LFLEN: u4, reserved0: u1, @@ -2276,7 +2276,7 @@ pub const registers = struct { /// address: 0x40001518 /// Packet configuration register 1 - pub const PCNF1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCNF1 = @intToPtr(*volatile Mmio(32, packed struct { /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, /// the radio will truncate the payload to MAXLEN. MAXLEN: u8, @@ -2312,7 +2312,7 @@ pub const registers = struct { /// address: 0x40001524 /// Prefixes bytes for logical addresses 0-3 - pub const PREFIX0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PREFIX0 = @intToPtr(*volatile Mmio(32, packed struct { /// Address prefix 0. AP0: u8, /// Address prefix 1. @@ -2325,7 +2325,7 @@ pub const registers = struct { /// address: 0x40001528 /// Prefixes bytes for logical addresses 4-7 - pub const PREFIX1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PREFIX1 = @intToPtr(*volatile Mmio(32, packed struct { /// Address prefix 4. AP4: u8, /// Address prefix 5. @@ -2342,7 +2342,7 @@ pub const registers = struct { /// address: 0x40001530 /// Receive address select - pub const RXADDRESSES = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXADDRESSES = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable reception on logical address 0. ADDR0: u1, /// Enable or disable reception on logical address 1. @@ -2387,7 +2387,7 @@ pub const registers = struct { /// address: 0x40001534 /// CRC configuration - pub const CRCCNF = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCCNF = @intToPtr(*volatile Mmio(32, packed struct { /// CRC length in number of bytes. LEN: u2, reserved0: u1, @@ -2465,7 +2465,7 @@ pub const registers = struct { /// address: 0x40001640 /// Device address match configuration - pub const DACNF = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DACNF = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable device address matching using device address 0 ENA0: u1, /// Enable or disable device address matching using device address 1 @@ -2518,7 +2518,7 @@ pub const registers = struct { /// address: 0x40001650 /// Radio mode configuration register 0 - pub const MODECNF0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODECNF0 = @intToPtr(*volatile Mmio(32, packed struct { /// Radio ramp-up time RU: u1, reserved0: u1, @@ -2628,7 +2628,7 @@ pub const registers = struct { /// address: 0x40002200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -2667,7 +2667,7 @@ pub const registers = struct { /// address: 0x40002300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for CTS event CTS: u1, /// Enable or disable interrupt for NCTS event @@ -2715,7 +2715,7 @@ pub const registers = struct { /// address: 0x40002304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for CTS event CTS: u1, /// Write '1' to Enable interrupt for NCTS event @@ -2763,7 +2763,7 @@ pub const registers = struct { /// address: 0x40002308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for CTS event CTS: u1, /// Write '1' to Disable interrupt for NCTS event @@ -2811,7 +2811,7 @@ pub const registers = struct { /// address: 0x40002480 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// Parity error @@ -2860,7 +2860,7 @@ pub const registers = struct { /// address: 0x4000256c /// Configuration of parity and hardware flow control - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Hardware flow control HWFC: u1, /// Parity @@ -2899,7 +2899,7 @@ pub const registers = struct { /// address: 0x40002000 /// Pin select for RTS signal - pub const RTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTS = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -2934,7 +2934,7 @@ pub const registers = struct { /// address: 0x40002004 /// Pin select for TXD signal - pub const TXD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXD = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -2969,7 +2969,7 @@ pub const registers = struct { /// address: 0x40002008 /// Pin select for CTS signal - pub const CTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CTS = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3004,7 +3004,7 @@ pub const registers = struct { /// address: 0x4000200c /// Pin select for RXD signal - pub const RXD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXD = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3120,7 +3120,7 @@ pub const registers = struct { /// address: 0x40002200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -3159,7 +3159,7 @@ pub const registers = struct { /// address: 0x40002304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for CTS event CTS: u1, /// Write '1' to Enable interrupt for NCTS event @@ -3202,7 +3202,7 @@ pub const registers = struct { /// address: 0x40002308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for CTS event CTS: u1, /// Write '1' to Disable interrupt for NCTS event @@ -3245,7 +3245,7 @@ pub const registers = struct { /// address: 0x40002480 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// Parity error @@ -3318,7 +3318,7 @@ pub const registers = struct { /// address: 0x4000256c /// Configuration of parity and hardware flow control - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Hardware flow control HWFC: u1, /// Parity @@ -3395,7 +3395,7 @@ pub const registers = struct { /// address: 0x40003200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -3433,7 +3433,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -3475,7 +3475,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -3525,7 +3525,7 @@ pub const registers = struct { /// address: 0x40003554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -3572,7 +3572,7 @@ pub const registers = struct { /// address: 0x40003000 /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3607,7 +3607,7 @@ pub const registers = struct { /// address: 0x40003004 /// Pin select for MOSI signal - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3642,7 +3642,7 @@ pub const registers = struct { /// address: 0x40003008 /// Pin select for MISO signal - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3742,7 +3742,7 @@ pub const registers = struct { /// address: 0x40003200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Shortcut between END event and ACQUIRE task @@ -3780,7 +3780,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for END event END: u1, @@ -3820,7 +3820,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for END event END: u1, @@ -3864,7 +3864,7 @@ pub const registers = struct { /// address: 0x40003440 /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { /// TX buffer over-read detected, and prevented OVERREAD: u1, /// RX buffer overflow detected, and prevented @@ -3907,7 +3907,7 @@ pub const registers = struct { /// address: 0x40003554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -3957,7 +3957,7 @@ pub const registers = struct { /// address: 0x40003000 /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -3992,7 +3992,7 @@ pub const registers = struct { /// address: 0x40003004 /// Pin select for MISO signal - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4027,7 +4027,7 @@ pub const registers = struct { /// address: 0x40003008 /// Pin select for MOSI signal - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4062,7 +4062,7 @@ pub const registers = struct { /// address: 0x4000300c /// Pin select for CSN signal - pub const CSN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSN = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4181,7 +4181,7 @@ pub const registers = struct { /// address: 0x40003200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -4223,7 +4223,7 @@ pub const registers = struct { /// address: 0x40003300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -4267,7 +4267,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -4311,7 +4311,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -4355,7 +4355,7 @@ pub const registers = struct { /// address: 0x400034c4 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// NACK received after sending the address (write '1' to clear) @@ -4409,7 +4409,7 @@ pub const registers = struct { /// address: 0x40003000 /// Pin select for SCL signal - pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4444,7 +4444,7 @@ pub const registers = struct { /// address: 0x40003004 /// Pin select for SDA signal - pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4568,7 +4568,7 @@ pub const registers = struct { /// address: 0x40003200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -4607,7 +4607,7 @@ pub const registers = struct { /// address: 0x40003300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -4650,7 +4650,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -4693,7 +4693,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -4736,7 +4736,7 @@ pub const registers = struct { /// address: 0x400034d0 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// RX buffer overflow detected, and prevented OVERFLOW: u1, reserved0: u1, @@ -4788,7 +4788,7 @@ pub const registers = struct { /// address: 0x40003594 /// Configuration register for the address match mechanism - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable address matching on ADDRESS[0] ADDRESS0: u1, /// Enable or disable address matching on ADDRESS[1] @@ -4834,7 +4834,7 @@ pub const registers = struct { /// address: 0x40003000 /// Pin select for SCL signal - pub const SCL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4869,7 +4869,7 @@ pub const registers = struct { /// address: 0x40003004 /// Pin select for SDA signal - pub const SDA = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SDA = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -4945,7 +4945,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Enable interrupt for READY event @@ -4983,7 +4983,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Disable interrupt for READY event @@ -5037,7 +5037,7 @@ pub const registers = struct { /// address: 0x40003554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -5079,21 +5079,21 @@ pub const registers = struct { /// address: 0x40003000 /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number configuration for SPI SCK signal PSELSCK: u32, }), base_address + 0x0); /// address: 0x40003004 /// Pin select for MOSI - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number configuration for SPI MOSI signal PSELMOSI: u32, }), base_address + 0x4); /// address: 0x40003008 /// Pin select for MISO - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number configuration for SPI MISO signal PSELMISO: u32, }), base_address + 0x8); @@ -5149,7 +5149,7 @@ pub const registers = struct { /// address: 0x40003200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between BB event and SUSPEND task BB_SUSPEND: u1, /// Shortcut between BB event and STOP task @@ -5188,7 +5188,7 @@ pub const registers = struct { /// address: 0x40003304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -5231,7 +5231,7 @@ pub const registers = struct { /// address: 0x40003308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -5274,7 +5274,7 @@ pub const registers = struct { /// address: 0x400034c4 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// NACK received after sending the address (write '1' to clear) @@ -5382,7 +5382,7 @@ pub const registers = struct { /// address: 0x40004200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -5420,7 +5420,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -5462,7 +5462,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -5512,7 +5512,7 @@ pub const registers = struct { /// address: 0x40004554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -5581,7 +5581,7 @@ pub const registers = struct { /// address: 0x40004200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Shortcut between END event and ACQUIRE task @@ -5619,7 +5619,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for END event END: u1, @@ -5659,7 +5659,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for END event END: u1, @@ -5703,7 +5703,7 @@ pub const registers = struct { /// address: 0x40004440 /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { /// TX buffer over-read detected, and prevented OVERREAD: u1, /// RX buffer overflow detected, and prevented @@ -5746,7 +5746,7 @@ pub const registers = struct { /// address: 0x40004554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -5847,7 +5847,7 @@ pub const registers = struct { /// address: 0x40004200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -5889,7 +5889,7 @@ pub const registers = struct { /// address: 0x40004300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -5933,7 +5933,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -5977,7 +5977,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -6021,7 +6021,7 @@ pub const registers = struct { /// address: 0x400044c4 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// NACK received after sending the address (write '1' to clear) @@ -6121,7 +6121,7 @@ pub const registers = struct { /// address: 0x40004200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -6160,7 +6160,7 @@ pub const registers = struct { /// address: 0x40004300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -6203,7 +6203,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -6246,7 +6246,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -6289,7 +6289,7 @@ pub const registers = struct { /// address: 0x400044d0 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// RX buffer overflow detected, and prevented OVERFLOW: u1, reserved0: u1, @@ -6341,7 +6341,7 @@ pub const registers = struct { /// address: 0x40004594 /// Configuration register for the address match mechanism - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable address matching on ADDRESS[0] ADDRESS0: u1, /// Enable or disable address matching on ADDRESS[1] @@ -6393,7 +6393,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Enable interrupt for READY event @@ -6431,7 +6431,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Disable interrupt for READY event @@ -6485,7 +6485,7 @@ pub const registers = struct { /// address: 0x40004554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -6573,7 +6573,7 @@ pub const registers = struct { /// address: 0x40004200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between BB event and SUSPEND task BB_SUSPEND: u1, /// Shortcut between BB event and STOP task @@ -6612,7 +6612,7 @@ pub const registers = struct { /// address: 0x40004304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -6655,7 +6655,7 @@ pub const registers = struct { /// address: 0x40004308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -6698,7 +6698,7 @@ pub const registers = struct { /// address: 0x400044c4 /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { /// Overrun error OVERRUN: u1, /// NACK received after sending the address (write '1' to clear) @@ -6863,7 +6863,7 @@ pub const registers = struct { /// address: 0x40005200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between FIELDDETECTED event and ACTIVATE task FIELDDETECTED_ACTIVATE: u1, /// Shortcut between FIELDLOST event and SENSE task @@ -6902,7 +6902,7 @@ pub const registers = struct { /// address: 0x40005300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for READY event READY: u1, /// Enable or disable interrupt for FIELDDETECTED event @@ -6954,7 +6954,7 @@ pub const registers = struct { /// address: 0x40005304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for READY event READY: u1, /// Write '1' to Enable interrupt for FIELDDETECTED event @@ -7006,7 +7006,7 @@ pub const registers = struct { /// address: 0x40005308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for READY event READY: u1, /// Write '1' to Disable interrupt for FIELDDETECTED event @@ -7058,7 +7058,7 @@ pub const registers = struct { /// address: 0x40005404 /// NFC Error Status register - pub const ERRORSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ERRORSTATUS = @intToPtr(*volatile Mmio(32, packed struct { /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX FRAMEDELAYTIMEOUT: u1, reserved0: u1, @@ -7102,7 +7102,7 @@ pub const registers = struct { /// address: 0x4000543c /// Indicates the presence or not of a valid field - pub const FIELDPRESENT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FIELDPRESENT = @intToPtr(*volatile Mmio(32, packed struct { /// Indicates the presence or not of a valid field. Available only in the activated /// state. FIELDPRESENT: u1, @@ -7154,7 +7154,7 @@ pub const registers = struct { /// address: 0x40005510 /// Packet pointer for TXD and RXD data storage in Data RAM - pub const PACKETPTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PACKETPTR = @intToPtr(*volatile Mmio(32, packed struct { /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte /// aligned RAM address. PTR: u32, @@ -7166,7 +7166,7 @@ pub const registers = struct { /// address: 0x40005590 /// Last NFCID1 part (4, 7 or 10 bytes ID) - pub const NFCID1_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NFCID1_LAST = @intToPtr(*volatile Mmio(32, packed struct { /// NFCID1 byte Z (very last byte sent) NFCID1_Z: u8, /// NFCID1 byte Y @@ -7179,7 +7179,7 @@ pub const registers = struct { /// address: 0x40005594 /// Second last NFCID1 part (7 or 10 bytes ID) - pub const NFCID1_2ND_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NFCID1_2ND_LAST = @intToPtr(*volatile Mmio(32, packed struct { /// NFCID1 byte V NFCID1_V: u8, /// NFCID1 byte U @@ -7198,7 +7198,7 @@ pub const registers = struct { /// address: 0x40005598 /// Third last NFCID1 part (10 bytes ID) - pub const NFCID1_3RD_LAST = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NFCID1_3RD_LAST = @intToPtr(*volatile Mmio(32, packed struct { /// NFCID1 byte S NFCID1_S: u8, /// NFCID1 byte R @@ -7217,7 +7217,7 @@ pub const registers = struct { /// address: 0x400055a0 /// NFC-A SENS_RES auto-response settings - pub const SENSRES = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SENSRES = @intToPtr(*volatile Mmio(32, packed struct { /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC /// Forum, NFC Digital Protocol Technical Specification BITFRAMESDD: u5, @@ -7250,7 +7250,7 @@ pub const registers = struct { /// address: 0x400055a4 /// NFC-A SEL_RES auto-response settings - pub const SELRES = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SELRES = @intToPtr(*volatile Mmio(32, packed struct { /// Reserved for future use. Shall be 0. RFU10: u2, /// Cascade bit (controlled by hardware, write has no effect) @@ -7292,7 +7292,7 @@ pub const registers = struct { /// address: 0x40005000 /// Result of last incoming frames - pub const RX = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RX = @intToPtr(*volatile Mmio(32, packed struct { /// No valid End of Frame detected CRCERROR: u1, reserved0: u1, @@ -7335,7 +7335,7 @@ pub const registers = struct { /// address: 0x40005000 /// Configuration of outgoing frames - pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Adding parity or not in the frame PARITY: u1, /// Discarding unused bits in start or at end of a Frame @@ -7376,7 +7376,7 @@ pub const registers = struct { /// address: 0x40005004 /// Size of outgoing frame - pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct { /// Number of bits in the last or first byte read from RAM that shall be included in /// the frame (excluding parity bit). TXDATABITS: u3, @@ -7410,7 +7410,7 @@ pub const registers = struct { /// address: 0x40005000 /// Configuration of incoming frames - pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Parity expected or not in RX frame PARITY: u1, reserved0: u1, @@ -7450,7 +7450,7 @@ pub const registers = struct { /// address: 0x40005004 /// Size of last incoming frame - pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct { /// Number of bits in the last byte in the frame, if less than 8 (including CRC, but /// excluding parity and SoF/EoF framing). RXDATABITS: u3, @@ -7509,7 +7509,7 @@ pub const registers = struct { /// address: 0x40006304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for IN[0] event IN0: u1, /// Write '1' to Enable interrupt for IN[1] event @@ -7555,7 +7555,7 @@ pub const registers = struct { /// address: 0x40006308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for IN[0] event IN0: u1, /// Write '1' to Disable interrupt for IN[1] event @@ -7602,7 +7602,7 @@ pub const registers = struct { /// address: 0x40006510 /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and /// IN[n] event - pub const CONFIG = @intToPtr(*volatile [8]Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile [8]Mmio(32, packed struct { /// Mode MODE: u2, reserved0: u1, @@ -7685,7 +7685,7 @@ pub const registers = struct { /// address: 0x40007300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for STARTED event STARTED: u1, /// Enable or disable interrupt for END event @@ -7744,7 +7744,7 @@ pub const registers = struct { /// address: 0x40007304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for STARTED event STARTED: u1, /// Write '1' to Enable interrupt for END event @@ -7803,7 +7803,7 @@ pub const registers = struct { /// address: 0x40007308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for STARTED event STARTED: u1, /// Write '1' to Disable interrupt for END event @@ -7870,7 +7870,7 @@ pub const registers = struct { /// address: 0x400075f0 /// Resolution configuration - pub const RESOLUTION = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESOLUTION = @intToPtr(*volatile Mmio(32, packed struct { /// Set the resolution VAL: u3, padding0: u1, @@ -7912,7 +7912,7 @@ pub const registers = struct { /// address: 0x400075f8 /// Controls normal or continuous sample rate - pub const SAMPLERATE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SAMPLERATE = @intToPtr(*volatile Mmio(32, packed struct { /// Capture and compare value. Sample rate is 16 MHz/CC CC: u11, reserved0: u1, @@ -7955,7 +7955,7 @@ pub const registers = struct { PSELN: MmioInt(32, u5), /// Description cluster[0]: Input configuration for CH[0] - CONFIG: Mmio(32, packed struct{ + CONFIG: Mmio(32, packed struct { /// Positive channel resistor control RESP: u2, reserved0: u1, @@ -7992,7 +7992,7 @@ pub const registers = struct { }), /// Description cluster[0]: High/low limits for event monitoring a channel - LIMIT: Mmio(32, packed struct{ + LIMIT: Mmio(32, packed struct { /// Low level limit LOW: u16, /// High level limit @@ -8050,7 +8050,7 @@ pub const registers = struct { /// address: 0x40008200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between COMPARE[0] event and CLEAR task COMPARE0_CLEAR: u1, /// Shortcut between COMPARE[1] event and CLEAR task @@ -8099,7 +8099,7 @@ pub const registers = struct { /// address: 0x40008304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8142,7 +8142,7 @@ pub const registers = struct { /// address: 0x40008308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8233,7 +8233,7 @@ pub const registers = struct { /// address: 0x40009200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between COMPARE[0] event and CLEAR task COMPARE0_CLEAR: u1, /// Shortcut between COMPARE[1] event and CLEAR task @@ -8282,7 +8282,7 @@ pub const registers = struct { /// address: 0x40009304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8325,7 +8325,7 @@ pub const registers = struct { /// address: 0x40009308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8416,7 +8416,7 @@ pub const registers = struct { /// address: 0x4000a200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between COMPARE[0] event and CLEAR task COMPARE0_CLEAR: u1, /// Shortcut between COMPARE[1] event and CLEAR task @@ -8465,7 +8465,7 @@ pub const registers = struct { /// address: 0x4000a304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8508,7 +8508,7 @@ pub const registers = struct { /// address: 0x4000a308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8599,7 +8599,7 @@ pub const registers = struct { /// address: 0x4000b304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TICK event TICK: u1, /// Write '1' to Enable interrupt for OVRFLW event @@ -8642,7 +8642,7 @@ pub const registers = struct { /// address: 0x4000b308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TICK event TICK: u1, /// Write '1' to Disable interrupt for OVRFLW event @@ -8685,7 +8685,7 @@ pub const registers = struct { /// address: 0x4000b340 /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable event routing for TICK event TICK: u1, /// Enable or disable event routing for OVRFLW event @@ -8728,7 +8728,7 @@ pub const registers = struct { /// address: 0x4000b344 /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable event routing for TICK event TICK: u1, /// Write '1' to Enable event routing for OVRFLW event @@ -8771,7 +8771,7 @@ pub const registers = struct { /// address: 0x4000b348 /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable event routing for TICK event TICK: u1, /// Write '1' to Disable event routing for OVRFLW event @@ -8823,7 +8823,7 @@ pub const registers = struct { /// address: 0x4000b540 /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { /// Compare value COMPARE: u24, padding0: u1, @@ -8854,7 +8854,7 @@ pub const registers = struct { /// address: 0x4000c304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for DATARDY event DATARDY: u1, padding0: u1, @@ -8892,7 +8892,7 @@ pub const registers = struct { /// address: 0x4000c308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for DATARDY event DATARDY: u1, padding0: u1, @@ -9018,7 +9018,7 @@ pub const registers = struct { /// address: 0x4000d200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between VALRDY event and STOP task VALRDY_STOP: u1, padding0: u1, @@ -9056,7 +9056,7 @@ pub const registers = struct { /// address: 0x4000d304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for VALRDY event VALRDY: u1, padding0: u1, @@ -9094,7 +9094,7 @@ pub const registers = struct { /// address: 0x4000d308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for VALRDY event VALRDY: u1, padding0: u1, @@ -9132,7 +9132,7 @@ pub const registers = struct { /// address: 0x4000d504 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bias correction DERCEN: u1, padding0: u1, @@ -9194,7 +9194,7 @@ pub const registers = struct { /// address: 0x4000e304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for ENDECB event ENDECB: u1, /// Write '1' to Enable interrupt for ERRORECB event @@ -9233,7 +9233,7 @@ pub const registers = struct { /// address: 0x4000e308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for ENDECB event ENDECB: u1, /// Write '1' to Disable interrupt for ERRORECB event @@ -9305,7 +9305,7 @@ pub const registers = struct { /// address: 0x4000f200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between ENDKSGEN event and CRYPT task ENDKSGEN_CRYPT: u1, padding0: u1, @@ -9343,7 +9343,7 @@ pub const registers = struct { /// address: 0x4000f304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for ENDKSGEN event ENDKSGEN: u1, /// Write '1' to Enable interrupt for ENDCRYPT event @@ -9383,7 +9383,7 @@ pub const registers = struct { /// address: 0x4000f308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for ENDKSGEN event ENDKSGEN: u1, /// Write '1' to Disable interrupt for ENDCRYPT event @@ -9431,7 +9431,7 @@ pub const registers = struct { /// address: 0x4000f504 /// Operation mode - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// The mode of operation to be used MODE: u1, reserved0: u1, @@ -9511,7 +9511,7 @@ pub const registers = struct { /// address: 0x4000f304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for END event END: u1, /// Write '1' to Enable interrupt for RESOLVED event @@ -9551,7 +9551,7 @@ pub const registers = struct { /// address: 0x4000f308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for END event END: u1, /// Write '1' to Disable interrupt for RESOLVED event @@ -9627,7 +9627,7 @@ pub const registers = struct { /// address: 0x40010304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TIMEOUT event TIMEOUT: u1, padding0: u1, @@ -9665,7 +9665,7 @@ pub const registers = struct { /// address: 0x40010308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TIMEOUT event TIMEOUT: u1, padding0: u1, @@ -9707,7 +9707,7 @@ pub const registers = struct { /// address: 0x40010404 /// Request status - pub const REQSTATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const REQSTATUS = @intToPtr(*volatile Mmio(32, packed struct { /// Request status for RR[0] register RR0: u1, /// Request status for RR[1] register @@ -9756,7 +9756,7 @@ pub const registers = struct { /// address: 0x40010508 /// Enable register for reload request registers - pub const RREN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RREN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable RR[0] register RR0: u1, /// Enable or disable RR[1] register @@ -9801,7 +9801,7 @@ pub const registers = struct { /// address: 0x4001050c /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Configure the watchdog to either be paused, or kept running, while the CPU is /// sleeping SLEEP: u1, @@ -9878,7 +9878,7 @@ pub const registers = struct { /// address: 0x40011304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TICK event TICK: u1, /// Write '1' to Enable interrupt for OVRFLW event @@ -9921,7 +9921,7 @@ pub const registers = struct { /// address: 0x40011308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TICK event TICK: u1, /// Write '1' to Disable interrupt for OVRFLW event @@ -9964,7 +9964,7 @@ pub const registers = struct { /// address: 0x40011340 /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable event routing for TICK event TICK: u1, /// Enable or disable event routing for OVRFLW event @@ -10007,7 +10007,7 @@ pub const registers = struct { /// address: 0x40011344 /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable event routing for TICK event TICK: u1, /// Write '1' to Enable event routing for OVRFLW event @@ -10050,7 +10050,7 @@ pub const registers = struct { /// address: 0x40011348 /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable event routing for TICK event TICK: u1, /// Write '1' to Disable event routing for OVRFLW event @@ -10102,7 +10102,7 @@ pub const registers = struct { /// address: 0x40011540 /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { /// Compare value COMPARE: u24, padding0: u1, @@ -10161,7 +10161,7 @@ pub const registers = struct { /// address: 0x40012200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between REPORTRDY event and READCLRACC task REPORTRDY_READCLRACC: u1, /// Shortcut between SAMPLERDY event and STOP task @@ -10205,7 +10205,7 @@ pub const registers = struct { /// address: 0x40012304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for SAMPLERDY event SAMPLERDY: u1, /// Write '1' to Enable interrupt for REPORTRDY event @@ -10247,7 +10247,7 @@ pub const registers = struct { /// address: 0x40012308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for SAMPLERDY event SAMPLERDY: u1, /// Write '1' to Disable interrupt for REPORTRDY event @@ -10336,7 +10336,7 @@ pub const registers = struct { /// address: 0x40012000 /// Pin select for LED signal - pub const LED = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LED = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -10371,7 +10371,7 @@ pub const registers = struct { /// address: 0x40012004 /// Pin select for A signal - pub const A = @intToPtr(*volatile Mmio(32, packed struct{ + pub const A = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -10406,7 +10406,7 @@ pub const registers = struct { /// address: 0x40012008 /// Pin select for B signal - pub const B = @intToPtr(*volatile Mmio(32, packed struct{ + pub const B = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -10474,7 +10474,7 @@ pub const registers = struct { /// address: 0x40013200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between READY event and SAMPLE task READY_SAMPLE: u1, /// Shortcut between READY event and STOP task @@ -10516,7 +10516,7 @@ pub const registers = struct { /// address: 0x40013300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for READY event READY: u1, /// Enable or disable interrupt for DOWN event @@ -10557,7 +10557,7 @@ pub const registers = struct { /// address: 0x40013304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for READY event READY: u1, /// Write '1' to Enable interrupt for DOWN event @@ -10598,7 +10598,7 @@ pub const registers = struct { /// address: 0x40013308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for READY event READY: u1, /// Write '1' to Disable interrupt for DOWN event @@ -10659,7 +10659,7 @@ pub const registers = struct { /// address: 0x40013530 /// Threshold configuration for hysteresis unit - pub const TH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TH = @intToPtr(*volatile Mmio(32, packed struct { /// VDOWN = (THDOWN+1)/64*VREF THDOWN: u6, reserved0: u1, @@ -10688,7 +10688,7 @@ pub const registers = struct { /// address: 0x40013534 /// Mode configuration - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// Speed and power modes SP: u2, reserved0: u1, @@ -10766,7 +10766,7 @@ pub const registers = struct { /// address: 0x40013200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between READY event and SAMPLE task READY_SAMPLE: u1, /// Shortcut between READY event and STOP task @@ -10808,7 +10808,7 @@ pub const registers = struct { /// address: 0x40013304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for READY event READY: u1, /// Write '1' to Enable interrupt for DOWN event @@ -10849,7 +10849,7 @@ pub const registers = struct { /// address: 0x40013308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for READY event READY: u1, /// Write '1' to Disable interrupt for DOWN event @@ -10940,7 +10940,7 @@ pub const registers = struct { /// address: 0x40014300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -10993,7 +10993,7 @@ pub const registers = struct { /// address: 0x40014304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11046,7 +11046,7 @@ pub const registers = struct { /// address: 0x40014308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -11121,7 +11121,7 @@ pub const registers = struct { /// address: 0x40015300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -11174,7 +11174,7 @@ pub const registers = struct { /// address: 0x40015304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11227,7 +11227,7 @@ pub const registers = struct { /// address: 0x40015308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -11302,7 +11302,7 @@ pub const registers = struct { /// address: 0x40016300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -11355,7 +11355,7 @@ pub const registers = struct { /// address: 0x40016304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11408,7 +11408,7 @@ pub const registers = struct { /// address: 0x40016308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -11483,7 +11483,7 @@ pub const registers = struct { /// address: 0x40017300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -11536,7 +11536,7 @@ pub const registers = struct { /// address: 0x40017304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11589,7 +11589,7 @@ pub const registers = struct { /// address: 0x40017308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -11664,7 +11664,7 @@ pub const registers = struct { /// address: 0x40018300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -11717,7 +11717,7 @@ pub const registers = struct { /// address: 0x40018304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11770,7 +11770,7 @@ pub const registers = struct { /// address: 0x40018308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -11845,7 +11845,7 @@ pub const registers = struct { /// address: 0x40019300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Enable or disable interrupt for TRIGGERED[1] event @@ -11898,7 +11898,7 @@ pub const registers = struct { /// address: 0x40019304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Enable interrupt for TRIGGERED[1] event @@ -11951,7 +11951,7 @@ pub const registers = struct { /// address: 0x40019308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TRIGGERED[0] event TRIGGERED0: u1, /// Write '1' to Disable interrupt for TRIGGERED[1] event @@ -12036,7 +12036,7 @@ pub const registers = struct { /// address: 0x4001a200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between COMPARE[0] event and CLEAR task COMPARE0_CLEAR: u1, /// Shortcut between COMPARE[1] event and CLEAR task @@ -12085,7 +12085,7 @@ pub const registers = struct { /// address: 0x4001a304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12128,7 +12128,7 @@ pub const registers = struct { /// address: 0x4001a308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12219,7 +12219,7 @@ pub const registers = struct { /// address: 0x4001b200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between COMPARE[0] event and CLEAR task COMPARE0_CLEAR: u1, /// Shortcut between COMPARE[1] event and CLEAR task @@ -12268,7 +12268,7 @@ pub const registers = struct { /// address: 0x4001b304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12311,7 +12311,7 @@ pub const registers = struct { /// address: 0x4001b308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12413,7 +12413,7 @@ pub const registers = struct { /// address: 0x4001c200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between SEQEND[0] event and STOP task SEQEND0_STOP: u1, /// Shortcut between SEQEND[1] event and STOP task @@ -12455,7 +12455,7 @@ pub const registers = struct { /// address: 0x4001c300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -12499,7 +12499,7 @@ pub const registers = struct { /// address: 0x4001c304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -12543,7 +12543,7 @@ pub const registers = struct { /// address: 0x4001c308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -12591,7 +12591,7 @@ pub const registers = struct { /// address: 0x4001c504 /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// Selects up or up and down as wave counter mode UPDOWN: u1, padding0: u1, @@ -12637,7 +12637,7 @@ pub const registers = struct { /// address: 0x4001c510 /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { /// How a sequence is read from RAM and spread to the compare register LOAD: u2, reserved0: u1, @@ -12675,7 +12675,7 @@ pub const registers = struct { /// address: 0x4001c514 /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { /// Amount of playback of pattern cycles CNT: u16, padding0: u1, @@ -12705,7 +12705,7 @@ pub const registers = struct { /// Description cluster[0]: Amount of additional PWM periods between samples loaded /// into compare register - REFRESH: Mmio(32, packed struct{ + REFRESH: Mmio(32, packed struct { /// Amount of additional PWM periods between samples loaded into compare register /// (load every REFRESH.CNT+1 PWM periods) CNT: u24, @@ -12720,7 +12720,7 @@ pub const registers = struct { }), /// Description cluster[0]: Time added after the sequence - ENDDELAY: Mmio(32, packed struct{ + ENDDELAY: Mmio(32, packed struct { /// Time added after the sequence in PWM periods CNT: u24, padding0: u1, @@ -12742,7 +12742,7 @@ pub const registers = struct { /// address: 0x4001c000 /// Description collection[0]: Output pin select for PWM channel 0 - pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct{ + pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -12803,7 +12803,7 @@ pub const registers = struct { /// address: 0x4001d300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for STARTED event STARTED: u1, /// Enable or disable interrupt for STOPPED event @@ -12843,7 +12843,7 @@ pub const registers = struct { /// address: 0x4001d304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for STARTED event STARTED: u1, /// Write '1' to Enable interrupt for STOPPED event @@ -12883,7 +12883,7 @@ pub const registers = struct { /// address: 0x4001d308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for STARTED event STARTED: u1, /// Write '1' to Disable interrupt for STOPPED event @@ -12927,14 +12927,14 @@ pub const registers = struct { /// address: 0x4001d504 /// PDM clock generator control - pub const PDMCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PDMCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { /// PDM_CLK frequency FREQ: u32, }), base_address + 0x504); /// address: 0x4001d508 /// Defines the routing of the connected PDM microphones' signals - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// Mono or stereo operation OPERATION: u1, /// Defines on which PDM_CLK edge Left (or mono) is sampled @@ -12983,7 +12983,7 @@ pub const registers = struct { /// address: 0x4001d000 /// Pin number configuration for PDM CLK signal - pub const CLK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CLK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -13018,7 +13018,7 @@ pub const registers = struct { /// address: 0x4001d004 /// Pin number configuration for PDM DIN signal - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -13056,14 +13056,14 @@ pub const registers = struct { /// address: 0x4001d000 /// RAM address pointer to write samples to with EasyDMA - pub const PTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PTR = @intToPtr(*volatile Mmio(32, packed struct { /// Address to write PDM samples to over DMA SAMPLEPTR: u32, }), base_address + 0x0); /// address: 0x4001d004 /// Number of samples to allocate memory for in EasyDMA mode - pub const MAXCNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MAXCNT = @intToPtr(*volatile Mmio(32, packed struct { /// Length of DMA RAM allocation in number of samples BUFFSIZE: u15, padding0: u1, @@ -13096,7 +13096,7 @@ pub const registers = struct { /// address: 0x4001e504 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Program memory access mode. It is strongly recommended to only activate erase /// and write modes when they are actively used. Enabling write or erase will /// invalidate the cache and keep it invalidated. @@ -13157,7 +13157,7 @@ pub const registers = struct { /// address: 0x4001e540 /// I-Code cache configuration register. - pub const ICACHECNF = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICACHECNF = @intToPtr(*volatile Mmio(32, packed struct { /// Cache enable CACHEEN: u1, reserved0: u1, @@ -13196,14 +13196,14 @@ pub const registers = struct { /// address: 0x4001e548 /// I-Code cache hit counter. - pub const IHIT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IHIT = @intToPtr(*volatile Mmio(32, packed struct { /// Number of cache hits HITS: u32, }), base_address + 0x548); /// address: 0x4001e54c /// I-Code cache miss counter. - pub const IMISS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IMISS = @intToPtr(*volatile Mmio(32, packed struct { /// Number of cache misses MISSES: u32, }), base_address + 0x54c); @@ -13214,7 +13214,7 @@ pub const registers = struct { /// address: 0x4001f500 /// Channel enable register - pub const CHEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CHEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable channel 0 CH0: u1, /// Enable or disable channel 1 @@ -13283,7 +13283,7 @@ pub const registers = struct { /// address: 0x4001f504 /// Channel enable set register - pub const CHENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CHENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 0 enable set register. Writing '0' has no effect CH0: u1, /// Channel 1 enable set register. Writing '0' has no effect @@ -13352,7 +13352,7 @@ pub const registers = struct { /// address: 0x4001f508 /// Channel enable clear register - pub const CHENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CHENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 0 enable clear register. Writing '0' has no effect CH0: u1, /// Channel 1 enable clear register. Writing '0' has no effect @@ -13421,7 +13421,7 @@ pub const registers = struct { /// address: 0x4001f800 /// Description collection[0]: Channel group 0 - pub const CHG = @intToPtr(*volatile [6]Mmio(32, packed struct{ + pub const CHG = @intToPtr(*volatile [6]Mmio(32, packed struct { /// Include or exclude channel 0 CH0: u1, /// Include or exclude channel 1 @@ -13518,7 +13518,7 @@ pub const registers = struct { /// address: 0x40020300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable interrupt for REGION[0].WA event REGION0WA: u1, /// Enable or disable interrupt for REGION[0].RA event @@ -13567,7 +13567,7 @@ pub const registers = struct { /// address: 0x40020304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for REGION[0].WA event REGION0WA: u1, /// Write '1' to Enable interrupt for REGION[0].RA event @@ -13616,7 +13616,7 @@ pub const registers = struct { /// address: 0x40020308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for REGION[0].WA event REGION0WA: u1, /// Write '1' to Disable interrupt for REGION[0].RA event @@ -13665,7 +13665,7 @@ pub const registers = struct { /// address: 0x40020320 /// Enable or disable non-maskable interrupt - pub const NMIEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NMIEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable non-maskable interrupt for REGION[0].WA event REGION0WA: u1, /// Enable or disable non-maskable interrupt for REGION[0].RA event @@ -13714,7 +13714,7 @@ pub const registers = struct { /// address: 0x40020324 /// Enable non-maskable interrupt - pub const NMIENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NMIENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event REGION0WA: u1, /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event @@ -13763,7 +13763,7 @@ pub const registers = struct { /// address: 0x40020328 /// Disable non-maskable interrupt - pub const NMIENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const NMIENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event REGION0WA: u1, /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event @@ -13812,7 +13812,7 @@ pub const registers = struct { /// address: 0x40020510 /// Enable/disable regions watch - pub const REGIONEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const REGIONEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable/disable write access watch in region[0] RGN0WA: u1, /// Enable/disable read access watch in region[0] @@ -13861,7 +13861,7 @@ pub const registers = struct { /// address: 0x40020514 /// Enable regions watch - pub const REGIONENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const REGIONENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Enable write access watch in region[0] RGN0WA: u1, /// Enable read access watch in region[0] @@ -13910,7 +13910,7 @@ pub const registers = struct { /// address: 0x40020518 /// Disable regions watch - pub const REGIONENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const REGIONENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Disable write access watch in region[0] RGN0WA: u1, /// Disable read access watch in region[0] @@ -13976,7 +13976,7 @@ pub const registers = struct { pub const PERREGION = @ptrCast(*volatile [2]packed struct { /// Description cluster[0]: Source of event/interrupt in region 0, write access /// detected while corresponding subregion was enabled for watching - SUBSTATWA: Mmio(32, packed struct{ + SUBSTATWA: Mmio(32, packed struct { /// Subregion 0 in region 0 (write '1' to clear) SR0: u1, /// Subregion 1 in region 0 (write '1' to clear) @@ -14045,7 +14045,7 @@ pub const registers = struct { /// Description cluster[0]: Source of event/interrupt in region 0, read access /// detected while corresponding subregion was enabled for watching - SUBSTATRA: Mmio(32, packed struct{ + SUBSTATRA: Mmio(32, packed struct { /// Subregion 0 in region 0 (write '1' to clear) SR0: u1, /// Subregion 1 in region 0 (write '1' to clear) @@ -14131,7 +14131,7 @@ pub const registers = struct { END: u32, /// Description cluster[0]: Subregions of region 0 - SUBS: Mmio(32, packed struct{ + SUBS: Mmio(32, packed struct { /// Include or exclude subregion 0 in region SR0: u1, /// Include or exclude subregion 1 in region @@ -14245,7 +14245,7 @@ pub const registers = struct { /// address: 0x40021200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between SEQEND[0] event and STOP task SEQEND0_STOP: u1, /// Shortcut between SEQEND[1] event and STOP task @@ -14287,7 +14287,7 @@ pub const registers = struct { /// address: 0x40021300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -14331,7 +14331,7 @@ pub const registers = struct { /// address: 0x40021304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -14375,7 +14375,7 @@ pub const registers = struct { /// address: 0x40021308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -14423,7 +14423,7 @@ pub const registers = struct { /// address: 0x40021504 /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// Selects up or up and down as wave counter mode UPDOWN: u1, padding0: u1, @@ -14469,7 +14469,7 @@ pub const registers = struct { /// address: 0x40021510 /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { /// How a sequence is read from RAM and spread to the compare register LOAD: u2, reserved0: u1, @@ -14507,7 +14507,7 @@ pub const registers = struct { /// address: 0x40021514 /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { /// Amount of playback of pattern cycles CNT: u16, padding0: u1, @@ -14573,7 +14573,7 @@ pub const registers = struct { /// address: 0x40022200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { /// Shortcut between SEQEND[0] event and STOP task SEQEND0_STOP: u1, /// Shortcut between SEQEND[1] event and STOP task @@ -14615,7 +14615,7 @@ pub const registers = struct { /// address: 0x40022300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for STOPPED event STOPPED: u1, @@ -14659,7 +14659,7 @@ pub const registers = struct { /// address: 0x40022304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -14703,7 +14703,7 @@ pub const registers = struct { /// address: 0x40022308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -14751,7 +14751,7 @@ pub const registers = struct { /// address: 0x40022504 /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { /// Selects up or up and down as wave counter mode UPDOWN: u1, padding0: u1, @@ -14797,7 +14797,7 @@ pub const registers = struct { /// address: 0x40022510 /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { /// How a sequence is read from RAM and spread to the compare register LOAD: u2, reserved0: u1, @@ -14835,7 +14835,7 @@ pub const registers = struct { /// address: 0x40022514 /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { /// Amount of playback of pattern cycles CNT: u16, padding0: u1, @@ -14898,7 +14898,7 @@ pub const registers = struct { /// address: 0x40023200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -14936,7 +14936,7 @@ pub const registers = struct { /// address: 0x40023304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for STOPPED event STOPPED: u1, @@ -14978,7 +14978,7 @@ pub const registers = struct { /// address: 0x40023308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for STOPPED event STOPPED: u1, @@ -15028,7 +15028,7 @@ pub const registers = struct { /// address: 0x40023554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -15097,7 +15097,7 @@ pub const registers = struct { /// address: 0x40023200 /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Shortcut between END event and ACQUIRE task @@ -15135,7 +15135,7 @@ pub const registers = struct { /// address: 0x40023304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for END event END: u1, @@ -15175,7 +15175,7 @@ pub const registers = struct { /// address: 0x40023308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for END event END: u1, @@ -15219,7 +15219,7 @@ pub const registers = struct { /// address: 0x40023440 /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { /// TX buffer over-read detected, and prevented OVERREAD: u1, /// RX buffer overflow detected, and prevented @@ -15262,7 +15262,7 @@ pub const registers = struct { /// address: 0x40023554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -15318,7 +15318,7 @@ pub const registers = struct { /// address: 0x40023304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Enable interrupt for READY event @@ -15356,7 +15356,7 @@ pub const registers = struct { /// address: 0x40023308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Write '1' to Disable interrupt for READY event @@ -15410,7 +15410,7 @@ pub const registers = struct { /// address: 0x40023554 /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { /// Bit order ORDER: u1, /// Serial clock (SCK) phase @@ -15482,7 +15482,7 @@ pub const registers = struct { /// address: 0x40024304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable interrupt for TICK event TICK: u1, /// Write '1' to Enable interrupt for OVRFLW event @@ -15525,7 +15525,7 @@ pub const registers = struct { /// address: 0x40024308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable interrupt for TICK event TICK: u1, /// Write '1' to Disable interrupt for OVRFLW event @@ -15568,7 +15568,7 @@ pub const registers = struct { /// address: 0x40024340 /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { /// Enable or disable event routing for TICK event TICK: u1, /// Enable or disable event routing for OVRFLW event @@ -15611,7 +15611,7 @@ pub const registers = struct { /// address: 0x40024344 /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Enable event routing for TICK event TICK: u1, /// Write '1' to Enable event routing for OVRFLW event @@ -15654,7 +15654,7 @@ pub const registers = struct { /// address: 0x40024348 /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Write '1' to Disable event routing for TICK event TICK: u1, /// Write '1' to Disable event routing for OVRFLW event @@ -15706,7 +15706,7 @@ pub const registers = struct { /// address: 0x40024540 /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct{ + pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { /// Compare value COMPARE: u24, padding0: u1, @@ -15750,7 +15750,7 @@ pub const registers = struct { /// address: 0x40025300 /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Enable or disable interrupt for RXPTRUPD event RXPTRUPD: u1, @@ -15790,7 +15790,7 @@ pub const registers = struct { /// address: 0x40025304 /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Enable interrupt for RXPTRUPD event RXPTRUPD: u1, @@ -15830,7 +15830,7 @@ pub const registers = struct { /// address: 0x40025308 /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Write '1' to Disable interrupt for RXPTRUPD event RXPTRUPD: u1, @@ -15940,7 +15940,7 @@ pub const registers = struct { /// address: 0x40025000 /// Pin select for MCK signal. - pub const MCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -15975,7 +15975,7 @@ pub const registers = struct { /// address: 0x40025004 /// Pin select for SCK signal. - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -16010,7 +16010,7 @@ pub const registers = struct { /// address: 0x40025008 /// Pin select for LRCK signal. - pub const LRCK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LRCK = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -16045,7 +16045,7 @@ pub const registers = struct { /// address: 0x4002500c /// Pin select for SDIN signal. - pub const SDIN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SDIN = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -16080,7 +16080,7 @@ pub const registers = struct { /// address: 0x40025010 /// Pin select for SDOUT signal. - pub const SDOUT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SDOUT = @intToPtr(*volatile Mmio(32, packed struct { /// Pin number PIN: u5, reserved0: u1, @@ -16128,7 +16128,7 @@ pub const registers = struct { /// address: 0x50000504 /// Write GPIO port - pub const OUT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OUT = @intToPtr(*volatile Mmio(32, packed struct { /// Pin 0 PIN0: u1, /// Pin 1 @@ -16197,7 +16197,7 @@ pub const registers = struct { /// address: 0x50000508 /// Set individual bits in GPIO port - pub const OUTSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OUTSET = @intToPtr(*volatile Mmio(32, packed struct { /// Pin 0 PIN0: u1, /// Pin 1 @@ -16266,7 +16266,7 @@ pub const registers = struct { /// address: 0x5000050c /// Clear individual bits in GPIO port - pub const OUTCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OUTCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Pin 0 PIN0: u1, /// Pin 1 @@ -16335,7 +16335,7 @@ pub const registers = struct { /// address: 0x50000510 /// Read GPIO port - pub const IN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IN = @intToPtr(*volatile Mmio(32, packed struct { /// Pin 0 PIN0: u1, /// Pin 1 @@ -16404,7 +16404,7 @@ pub const registers = struct { /// address: 0x50000514 /// Direction of GPIO pins - pub const DIR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIR = @intToPtr(*volatile Mmio(32, packed struct { /// Pin 0 PIN0: u1, /// Pin 1 @@ -16473,7 +16473,7 @@ pub const registers = struct { /// address: 0x50000518 /// DIR set register - pub const DIRSET = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIRSET = @intToPtr(*volatile Mmio(32, packed struct { /// Set as output pin 0 PIN0: u1, /// Set as output pin 1 @@ -16542,7 +16542,7 @@ pub const registers = struct { /// address: 0x5000051c /// DIR clear register - pub const DIRCLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIRCLR = @intToPtr(*volatile Mmio(32, packed struct { /// Set as input pin 0 PIN0: u1, /// Set as input pin 1 @@ -16612,7 +16612,7 @@ pub const registers = struct { /// address: 0x50000520 /// Latch register indicating what GPIO pins that have met the criteria set in the /// PIN_CNF[n].SENSE registers - pub const LATCH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LATCH = @intToPtr(*volatile Mmio(32, packed struct { /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write /// '1' to clear. PIN0: u1, @@ -16717,7 +16717,7 @@ pub const registers = struct { /// address: 0x50000700 /// Description collection[0]: Configuration of GPIO pins - pub const PIN_CNF = @intToPtr(*volatile [32]Mmio(32, packed struct{ + pub const PIN_CNF = @intToPtr(*volatile [32]Mmio(32, packed struct { /// Pin direction. Same physical register as DIR register DIR: u1, /// Connect or disconnect input buffer diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 6c72470..10d7649 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -10,7 +10,7 @@ pub const registers = struct { /// address: 0xa0000000 /// SRAM/NOR-Flash chip-select control register /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -59,7 +59,7 @@ pub const registers = struct { /// address: 0xa0000004 /// SRAM/NOR-Flash chip-select timing register /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -81,7 +81,7 @@ pub const registers = struct { /// address: 0xa0000008 /// SRAM/NOR-Flash chip-select control register /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -131,7 +131,7 @@ pub const registers = struct { /// address: 0xa000000c /// SRAM/NOR-Flash chip-select timing register /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -153,7 +153,7 @@ pub const registers = struct { /// address: 0xa0000010 /// SRAM/NOR-Flash chip-select control register /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -203,7 +203,7 @@ pub const registers = struct { /// address: 0xa0000014 /// SRAM/NOR-Flash chip-select timing register /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -225,7 +225,7 @@ pub const registers = struct { /// address: 0xa0000018 /// SRAM/NOR-Flash chip-select control register /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -275,7 +275,7 @@ pub const registers = struct { /// address: 0xa000001c /// SRAM/NOR-Flash chip-select timing register /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -297,7 +297,7 @@ pub const registers = struct { /// address: 0xa0000060 /// PC Card/NAND Flash control register /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -334,7 +334,7 @@ pub const registers = struct { /// address: 0xa0000064 /// FIFO status and interrupt register /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -379,7 +379,7 @@ pub const registers = struct { /// address: 0xa0000068 /// Common memory space timing register /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -393,7 +393,7 @@ pub const registers = struct { /// address: 0xa000006c /// Attribute memory space timing register /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { /// Attribute memory x setup /// time ATTSETx: u8, @@ -410,7 +410,7 @@ pub const registers = struct { /// address: 0xa0000074 /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ECC result ECCx: u32, }), base_address + 0x74); @@ -418,7 +418,7 @@ pub const registers = struct { /// address: 0xa0000080 /// PC Card/NAND Flash control register /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -455,7 +455,7 @@ pub const registers = struct { /// address: 0xa0000084 /// FIFO status and interrupt register /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -500,7 +500,7 @@ pub const registers = struct { /// address: 0xa0000088 /// Common memory space timing register /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -514,7 +514,7 @@ pub const registers = struct { /// address: 0xa000008c /// Attribute memory space timing register /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { /// ATTSETx ATTSETx: u8, /// ATTWAITx @@ -527,7 +527,7 @@ pub const registers = struct { /// address: 0xa0000094 /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ECCx ECCx: u32, }), base_address + 0x94); @@ -535,7 +535,7 @@ pub const registers = struct { /// address: 0xa00000a0 /// PC Card/NAND Flash control register /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -572,7 +572,7 @@ pub const registers = struct { /// address: 0xa00000a4 /// FIFO status and interrupt register /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -617,7 +617,7 @@ pub const registers = struct { /// address: 0xa00000a8 /// Common memory space timing register /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -631,7 +631,7 @@ pub const registers = struct { /// address: 0xa00000ac /// Attribute memory space timing register /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { /// ATTSETx ATTSETx: u8, /// ATTWAITx @@ -644,7 +644,7 @@ pub const registers = struct { /// address: 0xa00000b0 /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { /// IOSETx IOSETx: u8, /// IOWAITx @@ -658,7 +658,7 @@ pub const registers = struct { /// address: 0xa0000104 /// SRAM/NOR-Flash write timing registers /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -682,7 +682,7 @@ pub const registers = struct { /// address: 0xa000010c /// SRAM/NOR-Flash write timing registers /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -706,7 +706,7 @@ pub const registers = struct { /// address: 0xa0000114 /// SRAM/NOR-Flash write timing registers /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -730,7 +730,7 @@ pub const registers = struct { /// address: 0xa000011c /// SRAM/NOR-Flash write timing registers /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -758,7 +758,7 @@ pub const registers = struct { /// address: 0x40007000 /// Power control register /// (PWR_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Low Power Deep Sleep LPDS: u1, /// Power Down Deep Sleep @@ -803,7 +803,7 @@ pub const registers = struct { /// address: 0x40007004 /// Power control register /// (PWR_CR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Wake-Up Flag WUF: u1, /// STANDBY Flag @@ -848,7 +848,7 @@ pub const registers = struct { /// address: 0x40021000 /// Clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Internal High Speed clock /// enable HSION: u1, @@ -893,7 +893,7 @@ pub const registers = struct { /// address: 0x40021004 /// Clock configuration register /// (RCC_CFGR) - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// System clock Switch SW: u2, /// System Clock Switch Status @@ -930,7 +930,7 @@ pub const registers = struct { /// address: 0x40021008 /// Clock interrupt register /// (RCC_CIR) - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { /// LSI Ready Interrupt flag LSIRDYF: u1, /// LSE Ready Interrupt flag @@ -987,7 +987,7 @@ pub const registers = struct { /// address: 0x4002100c /// APB2 peripheral reset register /// (RCC_APB2RSTR) - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function I/O /// reset AFIORST: u1, @@ -1044,7 +1044,7 @@ pub const registers = struct { /// address: 0x40021010 /// APB1 peripheral reset register /// (RCC_APB1RSTR) - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { /// Timer 2 reset TIM2RST: u1, /// Timer 3 reset @@ -1105,7 +1105,7 @@ pub const registers = struct { /// address: 0x40021014 /// AHB Peripheral Clock enable register /// (RCC_AHBENR) - pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA1 clock enable DMA1EN: u1, /// DMA2 clock enable @@ -1151,7 +1151,7 @@ pub const registers = struct { /// address: 0x40021018 /// APB2 peripheral clock enable register /// (RCC_APB2ENR) - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function I/O clock /// enable AFIOEN: u1, @@ -1211,7 +1211,7 @@ pub const registers = struct { /// address: 0x4002101c /// APB1 peripheral clock enable register /// (RCC_APB1ENR) - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { /// Timer 2 clock enable TIM2EN: u1, /// Timer 3 clock enable @@ -1275,7 +1275,7 @@ pub const registers = struct { /// address: 0x40021020 /// Backup domain control register /// (RCC_BDCR) - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { /// External Low Speed oscillator /// enable LSEON: u1, @@ -1322,7 +1322,7 @@ pub const registers = struct { /// address: 0x40021024 /// Control/status register /// (RCC_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Internal low speed oscillator /// enable LSION: u1, @@ -1376,7 +1376,7 @@ pub const registers = struct { /// address: 0x40010800 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -1422,7 +1422,7 @@ pub const registers = struct { /// address: 0x40010804 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -1468,7 +1468,7 @@ pub const registers = struct { /// address: 0x40010808 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -1522,7 +1522,7 @@ pub const registers = struct { /// address: 0x4001080c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -1576,7 +1576,7 @@ pub const registers = struct { /// address: 0x40010810 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -1646,7 +1646,7 @@ pub const registers = struct { /// address: 0x40010814 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -1700,7 +1700,7 @@ pub const registers = struct { /// address: 0x40010818 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -1758,7 +1758,7 @@ pub const registers = struct { /// address: 0x40010c00 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -1804,7 +1804,7 @@ pub const registers = struct { /// address: 0x40010c04 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -1850,7 +1850,7 @@ pub const registers = struct { /// address: 0x40010c08 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -1904,7 +1904,7 @@ pub const registers = struct { /// address: 0x40010c0c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -1958,7 +1958,7 @@ pub const registers = struct { /// address: 0x40010c10 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -2028,7 +2028,7 @@ pub const registers = struct { /// address: 0x40010c14 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -2082,7 +2082,7 @@ pub const registers = struct { /// address: 0x40010c18 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -2140,7 +2140,7 @@ pub const registers = struct { /// address: 0x40011000 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -2186,7 +2186,7 @@ pub const registers = struct { /// address: 0x40011004 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -2232,7 +2232,7 @@ pub const registers = struct { /// address: 0x40011008 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -2286,7 +2286,7 @@ pub const registers = struct { /// address: 0x4001100c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -2340,7 +2340,7 @@ pub const registers = struct { /// address: 0x40011010 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -2410,7 +2410,7 @@ pub const registers = struct { /// address: 0x40011014 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -2464,7 +2464,7 @@ pub const registers = struct { /// address: 0x40011018 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -2522,7 +2522,7 @@ pub const registers = struct { /// address: 0x40011400 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -2568,7 +2568,7 @@ pub const registers = struct { /// address: 0x40011404 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -2614,7 +2614,7 @@ pub const registers = struct { /// address: 0x40011408 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -2668,7 +2668,7 @@ pub const registers = struct { /// address: 0x4001140c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -2722,7 +2722,7 @@ pub const registers = struct { /// address: 0x40011410 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -2792,7 +2792,7 @@ pub const registers = struct { /// address: 0x40011414 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -2846,7 +2846,7 @@ pub const registers = struct { /// address: 0x40011418 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -2904,7 +2904,7 @@ pub const registers = struct { /// address: 0x40011800 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -2950,7 +2950,7 @@ pub const registers = struct { /// address: 0x40011804 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -2996,7 +2996,7 @@ pub const registers = struct { /// address: 0x40011808 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -3050,7 +3050,7 @@ pub const registers = struct { /// address: 0x4001180c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -3104,7 +3104,7 @@ pub const registers = struct { /// address: 0x40011810 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -3174,7 +3174,7 @@ pub const registers = struct { /// address: 0x40011814 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -3228,7 +3228,7 @@ pub const registers = struct { /// address: 0x40011818 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -3286,7 +3286,7 @@ pub const registers = struct { /// address: 0x40011c00 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -3332,7 +3332,7 @@ pub const registers = struct { /// address: 0x40011c04 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -3378,7 +3378,7 @@ pub const registers = struct { /// address: 0x40011c08 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -3432,7 +3432,7 @@ pub const registers = struct { /// address: 0x40011c0c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -3486,7 +3486,7 @@ pub const registers = struct { /// address: 0x40011c10 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -3556,7 +3556,7 @@ pub const registers = struct { /// address: 0x40011c14 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -3610,7 +3610,7 @@ pub const registers = struct { /// address: 0x40011c18 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -3668,7 +3668,7 @@ pub const registers = struct { /// address: 0x40012000 /// Port configuration register low /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.0 mode bits MODE0: u2, /// Port n.0 configuration @@ -3714,7 +3714,7 @@ pub const registers = struct { /// address: 0x40012004 /// Port configuration register high /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Port n.8 mode bits MODE8: u2, /// Port n.8 configuration @@ -3760,7 +3760,7 @@ pub const registers = struct { /// address: 0x40012008 /// Port input data register /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data IDR0: u1, /// Port input data @@ -3814,7 +3814,7 @@ pub const registers = struct { /// address: 0x4001200c /// Port output data register /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data ODR0: u1, /// Port output data @@ -3868,7 +3868,7 @@ pub const registers = struct { /// address: 0x40012010 /// Port bit set/reset register /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Set bit 0 BS0: u1, /// Set bit 1 @@ -3938,7 +3938,7 @@ pub const registers = struct { /// address: 0x40012014 /// Port bit reset register /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit 0 BR0: u1, /// Reset bit 1 @@ -3992,7 +3992,7 @@ pub const registers = struct { /// address: 0x40012018 /// Port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port A Lock bit 0 LCK0: u1, /// Port A Lock bit 1 @@ -4051,7 +4051,7 @@ pub const registers = struct { /// address: 0x40010000 /// Event Control Register /// (AFIO_EVCR) - pub const EVCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EVCR = @intToPtr(*volatile Mmio(32, packed struct { /// Pin selection PIN: u4, /// Port selection @@ -4087,7 +4087,7 @@ pub const registers = struct { /// address: 0x40010004 /// AF remap and debug I/O configuration /// register (AFIO_MAPR) - pub const MAPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MAPR = @intToPtr(*volatile Mmio(32, packed struct { /// SPI1 remapping SPI1_REMAP: u1, /// I2C1 remapping @@ -4142,7 +4142,7 @@ pub const registers = struct { /// address: 0x40010008 /// External interrupt configuration register 1 /// (AFIO_EXTICR1) - pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI0 configuration EXTI0: u4, /// EXTI1 configuration @@ -4172,7 +4172,7 @@ pub const registers = struct { /// address: 0x4001000c /// External interrupt configuration register 2 /// (AFIO_EXTICR2) - pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI4 configuration EXTI4: u4, /// EXTI5 configuration @@ -4202,7 +4202,7 @@ pub const registers = struct { /// address: 0x40010010 /// External interrupt configuration register 3 /// (AFIO_EXTICR3) - pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI8 configuration EXTI8: u4, /// EXTI9 configuration @@ -4232,7 +4232,7 @@ pub const registers = struct { /// address: 0x40010014 /// External interrupt configuration register 4 /// (AFIO_EXTICR4) - pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI12 configuration EXTI12: u4, /// EXTI13 configuration @@ -4262,7 +4262,7 @@ pub const registers = struct { /// address: 0x4001001c /// AF remap and debug I/O configuration /// register - pub const MAPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MAPR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -4310,7 +4310,7 @@ pub const registers = struct { /// address: 0x40010400 /// Interrupt mask register /// (EXTI_IMR) - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { /// Interrupt Mask on line 0 MR0: u1, /// Interrupt Mask on line 1 @@ -4366,7 +4366,7 @@ pub const registers = struct { /// address: 0x40010404 /// Event mask register (EXTI_EMR) - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { /// Event Mask on line 0 MR0: u1, /// Event Mask on line 1 @@ -4423,7 +4423,7 @@ pub const registers = struct { /// address: 0x40010408 /// Rising Trigger selection register /// (EXTI_RTSR) - pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { /// Rising trigger event configuration of /// line 0 TR0: u1, @@ -4499,7 +4499,7 @@ pub const registers = struct { /// address: 0x4001040c /// Falling Trigger selection register /// (EXTI_FTSR) - pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { /// Falling trigger event configuration of /// line 0 TR0: u1, @@ -4575,7 +4575,7 @@ pub const registers = struct { /// address: 0x40010410 /// Software interrupt event register /// (EXTI_SWIER) - pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { /// Software Interrupt on line /// 0 SWIER0: u1, @@ -4650,7 +4650,7 @@ pub const registers = struct { /// address: 0x40010414 /// Pending register (EXTI_PR) - pub const PR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { /// Pending bit 0 PR0: u1, /// Pending bit 1 @@ -4711,7 +4711,7 @@ pub const registers = struct { /// address: 0x40020000 /// DMA interrupt status register /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// flag GIF1: u1, @@ -4805,7 +4805,7 @@ pub const registers = struct { /// address: 0x40020004 /// DMA interrupt flag clear register /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// clear CGIF1: u1, @@ -4899,7 +4899,7 @@ pub const registers = struct { /// address: 0x40020008 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -4949,7 +4949,7 @@ pub const registers = struct { /// address: 0x4002000c /// DMA channel 1 number of data /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -4973,7 +4973,7 @@ pub const registers = struct { /// address: 0x40020010 /// DMA channel 1 peripheral address /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x10); @@ -4981,7 +4981,7 @@ pub const registers = struct { /// address: 0x40020014 /// DMA channel 1 memory address /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x14); @@ -4989,7 +4989,7 @@ pub const registers = struct { /// address: 0x4002001c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5039,7 +5039,7 @@ pub const registers = struct { /// address: 0x40020020 /// DMA channel 2 number of data /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5063,7 +5063,7 @@ pub const registers = struct { /// address: 0x40020024 /// DMA channel 2 peripheral address /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x24); @@ -5071,7 +5071,7 @@ pub const registers = struct { /// address: 0x40020028 /// DMA channel 2 memory address /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x28); @@ -5079,7 +5079,7 @@ pub const registers = struct { /// address: 0x40020030 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5129,7 +5129,7 @@ pub const registers = struct { /// address: 0x40020034 /// DMA channel 3 number of data /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5153,7 +5153,7 @@ pub const registers = struct { /// address: 0x40020038 /// DMA channel 3 peripheral address /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x38); @@ -5161,7 +5161,7 @@ pub const registers = struct { /// address: 0x4002003c /// DMA channel 3 memory address /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x3c); @@ -5169,7 +5169,7 @@ pub const registers = struct { /// address: 0x40020044 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5219,7 +5219,7 @@ pub const registers = struct { /// address: 0x40020048 /// DMA channel 4 number of data /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5243,7 +5243,7 @@ pub const registers = struct { /// address: 0x4002004c /// DMA channel 4 peripheral address /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x4c); @@ -5251,7 +5251,7 @@ pub const registers = struct { /// address: 0x40020050 /// DMA channel 4 memory address /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x50); @@ -5259,7 +5259,7 @@ pub const registers = struct { /// address: 0x40020058 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5309,7 +5309,7 @@ pub const registers = struct { /// address: 0x4002005c /// DMA channel 5 number of data /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5333,7 +5333,7 @@ pub const registers = struct { /// address: 0x40020060 /// DMA channel 5 peripheral address /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x60); @@ -5341,7 +5341,7 @@ pub const registers = struct { /// address: 0x40020064 /// DMA channel 5 memory address /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x64); @@ -5349,7 +5349,7 @@ pub const registers = struct { /// address: 0x4002006c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5399,7 +5399,7 @@ pub const registers = struct { /// address: 0x40020070 /// DMA channel 6 number of data /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5423,7 +5423,7 @@ pub const registers = struct { /// address: 0x40020074 /// DMA channel 6 peripheral address /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x74); @@ -5431,7 +5431,7 @@ pub const registers = struct { /// address: 0x40020078 /// DMA channel 6 memory address /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x78); @@ -5439,7 +5439,7 @@ pub const registers = struct { /// address: 0x40020080 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5489,7 +5489,7 @@ pub const registers = struct { /// address: 0x40020084 /// DMA channel 7 number of data /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5513,7 +5513,7 @@ pub const registers = struct { /// address: 0x40020088 /// DMA channel 7 peripheral address /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x88); @@ -5521,7 +5521,7 @@ pub const registers = struct { /// address: 0x4002008c /// DMA channel 7 memory address /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x8c); @@ -5532,7 +5532,7 @@ pub const registers = struct { /// address: 0x40020400 /// DMA interrupt status register /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// flag GIF1: u1, @@ -5626,7 +5626,7 @@ pub const registers = struct { /// address: 0x40020404 /// DMA interrupt flag clear register /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// clear CGIF1: u1, @@ -5720,7 +5720,7 @@ pub const registers = struct { /// address: 0x40020408 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5770,7 +5770,7 @@ pub const registers = struct { /// address: 0x4002040c /// DMA channel 1 number of data /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5794,7 +5794,7 @@ pub const registers = struct { /// address: 0x40020410 /// DMA channel 1 peripheral address /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x10); @@ -5802,7 +5802,7 @@ pub const registers = struct { /// address: 0x40020414 /// DMA channel 1 memory address /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x14); @@ -5810,7 +5810,7 @@ pub const registers = struct { /// address: 0x4002041c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5860,7 +5860,7 @@ pub const registers = struct { /// address: 0x40020420 /// DMA channel 2 number of data /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5884,7 +5884,7 @@ pub const registers = struct { /// address: 0x40020424 /// DMA channel 2 peripheral address /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x24); @@ -5892,7 +5892,7 @@ pub const registers = struct { /// address: 0x40020428 /// DMA channel 2 memory address /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x28); @@ -5900,7 +5900,7 @@ pub const registers = struct { /// address: 0x40020430 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -5950,7 +5950,7 @@ pub const registers = struct { /// address: 0x40020434 /// DMA channel 3 number of data /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -5974,7 +5974,7 @@ pub const registers = struct { /// address: 0x40020438 /// DMA channel 3 peripheral address /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x38); @@ -5982,7 +5982,7 @@ pub const registers = struct { /// address: 0x4002043c /// DMA channel 3 memory address /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x3c); @@ -5990,7 +5990,7 @@ pub const registers = struct { /// address: 0x40020444 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -6040,7 +6040,7 @@ pub const registers = struct { /// address: 0x40020448 /// DMA channel 4 number of data /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -6064,7 +6064,7 @@ pub const registers = struct { /// address: 0x4002044c /// DMA channel 4 peripheral address /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x4c); @@ -6072,7 +6072,7 @@ pub const registers = struct { /// address: 0x40020450 /// DMA channel 4 memory address /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x50); @@ -6080,7 +6080,7 @@ pub const registers = struct { /// address: 0x40020458 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -6130,7 +6130,7 @@ pub const registers = struct { /// address: 0x4002045c /// DMA channel 5 number of data /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -6154,7 +6154,7 @@ pub const registers = struct { /// address: 0x40020460 /// DMA channel 5 peripheral address /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x60); @@ -6162,7 +6162,7 @@ pub const registers = struct { /// address: 0x40020464 /// DMA channel 5 memory address /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x64); @@ -6170,7 +6170,7 @@ pub const registers = struct { /// address: 0x4002046c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -6220,7 +6220,7 @@ pub const registers = struct { /// address: 0x40020470 /// DMA channel 6 number of data /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -6244,7 +6244,7 @@ pub const registers = struct { /// address: 0x40020474 /// DMA channel 6 peripheral address /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x74); @@ -6252,7 +6252,7 @@ pub const registers = struct { /// address: 0x40020478 /// DMA channel 6 memory address /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x78); @@ -6260,7 +6260,7 @@ pub const registers = struct { /// address: 0x40020480 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -6310,7 +6310,7 @@ pub const registers = struct { /// address: 0x40020484 /// DMA channel 7 number of data /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -6334,7 +6334,7 @@ pub const registers = struct { /// address: 0x40020488 /// DMA channel 7 peripheral address /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x88); @@ -6342,7 +6342,7 @@ pub const registers = struct { /// address: 0x4002048c /// DMA channel 7 memory address /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x8c); @@ -6355,7 +6355,7 @@ pub const registers = struct { /// address: 0x40018000 /// Bits 1:0 = PWRCTRL: Power supply control /// bits - pub const POWER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { /// PWRCTRL PWRCTRL: u2, padding0: u1, @@ -6393,7 +6393,7 @@ pub const registers = struct { /// address: 0x40018004 /// SDI clock control register /// (SDIO_CLKCR) - pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { /// Clock divide factor CLKDIV: u8, /// Clock enable bit @@ -6432,7 +6432,7 @@ pub const registers = struct { /// address: 0x40018008 /// Bits 31:0 = : Command argument - pub const ARG = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { /// Command argument CMDARG: u32, }), base_address + 0x8); @@ -6440,7 +6440,7 @@ pub const registers = struct { /// address: 0x4001800c /// SDIO command register /// (SDIO_CMD) - pub const CMD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { /// CMDINDEX CMDINDEX: u6, /// WAITRESP @@ -6484,28 +6484,28 @@ pub const registers = struct { /// address: 0x40018014 /// Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESPI1 = @intToPtr(*volatile Mmio(32, packed struct { /// CARDSTATUS1 CARDSTATUS1: u32, }), base_address + 0x14); /// address: 0x40018018 /// Bits 31:0 = CARDSTATUS2 - pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { /// CARDSTATUS2 CARDSTATUS2: u32, }), base_address + 0x18); /// address: 0x4001801c /// Bits 31:0 = CARDSTATUS3 - pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { /// CARDSTATUS3 CARDSTATUS3: u32, }), base_address + 0x1c); /// address: 0x40018020 /// Bits 31:0 = CARDSTATUS4 - pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { /// CARDSTATUS4 CARDSTATUS4: u32, }), base_address + 0x20); @@ -6513,7 +6513,7 @@ pub const registers = struct { /// address: 0x40018024 /// Bits 31:0 = DATATIME: Data timeout /// period - pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { /// Data timeout period DATATIME: u32, }), base_address + 0x24); @@ -6521,7 +6521,7 @@ pub const registers = struct { /// address: 0x40018028 /// Bits 24:0 = DATALENGTH: Data length /// value - pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { /// Data length value DATALENGTH: u25, padding0: u1, @@ -6536,7 +6536,7 @@ pub const registers = struct { /// address: 0x4001802c /// SDIO data control register /// (SDIO_DCTRL) - pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { /// DTEN DTEN: u1, /// DTDIR @@ -6580,7 +6580,7 @@ pub const registers = struct { /// address: 0x40018030 /// Bits 24:0 = DATACOUNT: Data count /// value - pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { /// Data count value DATACOUNT: u25, padding0: u1, @@ -6595,7 +6595,7 @@ pub const registers = struct { /// address: 0x40018034 /// SDIO status register /// (SDIO_STA) - pub const STA = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STA = @intToPtr(*volatile Mmio(32, packed struct { /// CCRCFAIL CCRCFAIL: u1, /// DCRCFAIL @@ -6657,7 +6657,7 @@ pub const registers = struct { /// address: 0x40018038 /// SDIO interrupt clear register /// (SDIO_ICR) - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// CCRCFAILC CCRCFAILC: u1, /// DCRCFAILC @@ -6707,7 +6707,7 @@ pub const registers = struct { /// address: 0x4001803c /// SDIO mask register (SDIO_MASK) - pub const MASK = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { /// CCRCFAILIE CCRCFAILIE: u1, /// DCRCFAILIE @@ -6770,7 +6770,7 @@ pub const registers = struct { /// Bits 23:0 = FIFOCOUNT: Remaining number of /// words to be written to or read from the /// FIFO - pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { /// FIF0COUNT FIF0COUNT: u24, padding0: u1, @@ -6786,7 +6786,7 @@ pub const registers = struct { /// address: 0x40018080 /// bits 31:0 = FIFOData: Receive and transmit /// FIFO data - pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { /// FIFOData FIFOData: u32, }), base_address + 0x80); @@ -6797,7 +6797,7 @@ pub const registers = struct { /// address: 0x40002800 /// RTC Control Register High - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { /// Second interrupt Enable SECIE: u1, /// Alarm interrupt Enable @@ -6837,7 +6837,7 @@ pub const registers = struct { /// address: 0x40002804 /// RTC Control Register Low - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { /// Second Flag SECF: u1, /// Alarm Flag @@ -6921,7 +6921,7 @@ pub const registers = struct { /// address: 0x40006c04 /// Backup data register (BKP_DR) - pub const DR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D1: u16, padding0: u1, @@ -6944,7 +6944,7 @@ pub const registers = struct { /// address: 0x40006c08 /// Backup data register (BKP_DR) - pub const DR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D2: u16, padding0: u1, @@ -6967,7 +6967,7 @@ pub const registers = struct { /// address: 0x40006c0c /// Backup data register (BKP_DR) - pub const DR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D3: u16, padding0: u1, @@ -6990,7 +6990,7 @@ pub const registers = struct { /// address: 0x40006c10 /// Backup data register (BKP_DR) - pub const DR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D4: u16, padding0: u1, @@ -7013,7 +7013,7 @@ pub const registers = struct { /// address: 0x40006c14 /// Backup data register (BKP_DR) - pub const DR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D5: u16, padding0: u1, @@ -7036,7 +7036,7 @@ pub const registers = struct { /// address: 0x40006c18 /// Backup data register (BKP_DR) - pub const DR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D6: u16, padding0: u1, @@ -7059,7 +7059,7 @@ pub const registers = struct { /// address: 0x40006c1c /// Backup data register (BKP_DR) - pub const DR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D7: u16, padding0: u1, @@ -7082,7 +7082,7 @@ pub const registers = struct { /// address: 0x40006c20 /// Backup data register (BKP_DR) - pub const DR8 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR8 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D8: u16, padding0: u1, @@ -7105,7 +7105,7 @@ pub const registers = struct { /// address: 0x40006c24 /// Backup data register (BKP_DR) - pub const DR9 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR9 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D9: u16, padding0: u1, @@ -7128,7 +7128,7 @@ pub const registers = struct { /// address: 0x40006c28 /// Backup data register (BKP_DR) - pub const DR10 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR10 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D10: u16, padding0: u1, @@ -7163,7 +7163,7 @@ pub const registers = struct { /// address: 0x40006c4c /// Backup data register (BKP_DR) - pub const DR14 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR14 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D14: u16, padding0: u1, @@ -7186,7 +7186,7 @@ pub const registers = struct { /// address: 0x40006c50 /// Backup data register (BKP_DR) - pub const DR15 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR15 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D15: u16, padding0: u1, @@ -7209,7 +7209,7 @@ pub const registers = struct { /// address: 0x40006c54 /// Backup data register (BKP_DR) - pub const DR16 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR16 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D16: u16, padding0: u1, @@ -7232,7 +7232,7 @@ pub const registers = struct { /// address: 0x40006c58 /// Backup data register (BKP_DR) - pub const DR17 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR17 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D17: u16, padding0: u1, @@ -7255,7 +7255,7 @@ pub const registers = struct { /// address: 0x40006c5c /// Backup data register (BKP_DR) - pub const DR18 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR18 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D18: u16, padding0: u1, @@ -7278,7 +7278,7 @@ pub const registers = struct { /// address: 0x40006c60 /// Backup data register (BKP_DR) - pub const DR19 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR19 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D19: u16, padding0: u1, @@ -7301,7 +7301,7 @@ pub const registers = struct { /// address: 0x40006c64 /// Backup data register (BKP_DR) - pub const DR20 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR20 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D20: u16, padding0: u1, @@ -7324,7 +7324,7 @@ pub const registers = struct { /// address: 0x40006c68 /// Backup data register (BKP_DR) - pub const DR21 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR21 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D21: u16, padding0: u1, @@ -7347,7 +7347,7 @@ pub const registers = struct { /// address: 0x40006c6c /// Backup data register (BKP_DR) - pub const DR22 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR22 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D22: u16, padding0: u1, @@ -7370,7 +7370,7 @@ pub const registers = struct { /// address: 0x40006c70 /// Backup data register (BKP_DR) - pub const DR23 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR23 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D23: u16, padding0: u1, @@ -7393,7 +7393,7 @@ pub const registers = struct { /// address: 0x40006c74 /// Backup data register (BKP_DR) - pub const DR24 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR24 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D24: u16, padding0: u1, @@ -7416,7 +7416,7 @@ pub const registers = struct { /// address: 0x40006c78 /// Backup data register (BKP_DR) - pub const DR25 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR25 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D25: u16, padding0: u1, @@ -7439,7 +7439,7 @@ pub const registers = struct { /// address: 0x40006c7c /// Backup data register (BKP_DR) - pub const DR26 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR26 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D26: u16, padding0: u1, @@ -7462,7 +7462,7 @@ pub const registers = struct { /// address: 0x40006c80 /// Backup data register (BKP_DR) - pub const DR27 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR27 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D27: u16, padding0: u1, @@ -7485,7 +7485,7 @@ pub const registers = struct { /// address: 0x40006c84 /// Backup data register (BKP_DR) - pub const DR28 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR28 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D28: u16, padding0: u1, @@ -7508,7 +7508,7 @@ pub const registers = struct { /// address: 0x40006c88 /// Backup data register (BKP_DR) - pub const DR29 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR29 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D29: u16, padding0: u1, @@ -7531,7 +7531,7 @@ pub const registers = struct { /// address: 0x40006c8c /// Backup data register (BKP_DR) - pub const DR30 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR30 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D30: u16, padding0: u1, @@ -7554,7 +7554,7 @@ pub const registers = struct { /// address: 0x40006c90 /// Backup data register (BKP_DR) - pub const DR31 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR31 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D31: u16, padding0: u1, @@ -7577,7 +7577,7 @@ pub const registers = struct { /// address: 0x40006c94 /// Backup data register (BKP_DR) - pub const DR32 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR32 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D32: u16, padding0: u1, @@ -7600,7 +7600,7 @@ pub const registers = struct { /// address: 0x40006c98 /// Backup data register (BKP_DR) - pub const DR33 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR33 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D33: u16, padding0: u1, @@ -7623,7 +7623,7 @@ pub const registers = struct { /// address: 0x40006c9c /// Backup data register (BKP_DR) - pub const DR34 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR34 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D34: u16, padding0: u1, @@ -7646,7 +7646,7 @@ pub const registers = struct { /// address: 0x40006ca0 /// Backup data register (BKP_DR) - pub const DR35 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR35 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D35: u16, padding0: u1, @@ -7669,7 +7669,7 @@ pub const registers = struct { /// address: 0x40006ca4 /// Backup data register (BKP_DR) - pub const DR36 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR36 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D36: u16, padding0: u1, @@ -7692,7 +7692,7 @@ pub const registers = struct { /// address: 0x40006ca8 /// Backup data register (BKP_DR) - pub const DR37 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR37 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D37: u16, padding0: u1, @@ -7715,7 +7715,7 @@ pub const registers = struct { /// address: 0x40006cac /// Backup data register (BKP_DR) - pub const DR38 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR38 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D38: u16, padding0: u1, @@ -7738,7 +7738,7 @@ pub const registers = struct { /// address: 0x40006cb0 /// Backup data register (BKP_DR) - pub const DR39 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR39 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D39: u16, padding0: u1, @@ -7761,7 +7761,7 @@ pub const registers = struct { /// address: 0x40006cb4 /// Backup data register (BKP_DR) - pub const DR40 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR40 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D40: u16, padding0: u1, @@ -7784,7 +7784,7 @@ pub const registers = struct { /// address: 0x40006cb8 /// Backup data register (BKP_DR) - pub const DR41 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR41 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D41: u16, padding0: u1, @@ -7807,7 +7807,7 @@ pub const registers = struct { /// address: 0x40006cbc /// Backup data register (BKP_DR) - pub const DR42 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR42 = @intToPtr(*volatile Mmio(32, packed struct { /// Backup data D42: u16, padding0: u1, @@ -7831,7 +7831,7 @@ pub const registers = struct { /// address: 0x40006c2c /// RTC clock calibration register /// (BKP_RTCCR) - pub const RTCCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTCCR = @intToPtr(*volatile Mmio(32, packed struct { /// Calibration value CAL: u7, /// Calibration Clock Output @@ -7869,7 +7869,7 @@ pub const registers = struct { /// address: 0x40006c30 /// Backup control register /// (BKP_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Tamper pin enable TPE: u1, /// Tamper pin active level @@ -7909,7 +7909,7 @@ pub const registers = struct { /// address: 0x40006c34 /// BKP_CSR control/status register /// (BKP_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Clear Tamper event CTE: u1, /// Clear Tamper Interrupt @@ -7956,7 +7956,7 @@ pub const registers = struct { /// address: 0x40003000 /// Key register (IWDG_KR) - pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const KR = @intToPtr(*volatile Mmio(32, packed struct { /// Key value KEY: u16, padding0: u1, @@ -7983,7 +7983,7 @@ pub const registers = struct { /// address: 0x40003008 /// Reload register (IWDG_RLR) - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { /// Watchdog counter reload /// value RL: u12, @@ -8011,7 +8011,7 @@ pub const registers = struct { /// address: 0x4000300c /// Status register (IWDG_SR) - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Watchdog prescaler value /// update PVU: u1, @@ -8056,7 +8056,7 @@ pub const registers = struct { /// address: 0x40002c00 /// Control register (WWDG_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// 7-bit counter (MSB to LSB) T: u7, /// Activation bit @@ -8090,7 +8090,7 @@ pub const registers = struct { /// address: 0x40002c04 /// Configuration register /// (WWDG_CFR) - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { /// 7-bit window value W: u7, /// Timer Base @@ -8123,7 +8123,7 @@ pub const registers = struct { /// address: 0x40002c08 /// Status register (WWDG_SR) - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Early Wakeup Interrupt EWI: u1, padding0: u1, @@ -8165,7 +8165,7 @@ pub const registers = struct { /// address: 0x40012c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -8209,7 +8209,7 @@ pub const registers = struct { /// address: 0x40012c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -8259,7 +8259,7 @@ pub const registers = struct { /// address: 0x40012c08 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -8295,7 +8295,7 @@ pub const registers = struct { /// address: 0x40012c0c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -8355,7 +8355,7 @@ pub const registers = struct { /// address: 0x40012c10 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -8412,7 +8412,7 @@ pub const registers = struct { /// address: 0x40012c14 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -8463,7 +8463,7 @@ pub const registers = struct { /// address: 0x40012c18 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -8513,7 +8513,7 @@ pub const registers = struct { /// address: 0x40012c18 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -8549,7 +8549,7 @@ pub const registers = struct { /// address: 0x40012c1c /// capture/compare mode register (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -8599,7 +8599,7 @@ pub const registers = struct { /// address: 0x40012c1c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare 3 /// selection CC3S: u2, @@ -8635,7 +8635,7 @@ pub const registers = struct { /// address: 0x40012c20 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -8728,7 +8728,7 @@ pub const registers = struct { /// address: 0x40012c48 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -8759,7 +8759,7 @@ pub const registers = struct { /// address: 0x40012c4c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -8783,7 +8783,7 @@ pub const registers = struct { /// address: 0x40012c30 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u8, padding0: u1, @@ -8814,7 +8814,7 @@ pub const registers = struct { /// address: 0x40012c44 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -8856,7 +8856,7 @@ pub const registers = struct { /// address: 0x40013400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -8900,7 +8900,7 @@ pub const registers = struct { /// address: 0x40013404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -8950,7 +8950,7 @@ pub const registers = struct { /// address: 0x40013408 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -8986,7 +8986,7 @@ pub const registers = struct { /// address: 0x4001340c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -9046,7 +9046,7 @@ pub const registers = struct { /// address: 0x40013410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -9103,7 +9103,7 @@ pub const registers = struct { /// address: 0x40013414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -9154,7 +9154,7 @@ pub const registers = struct { /// address: 0x40013418 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9204,7 +9204,7 @@ pub const registers = struct { /// address: 0x40013418 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9240,7 +9240,7 @@ pub const registers = struct { /// address: 0x4001341c /// capture/compare mode register (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9290,7 +9290,7 @@ pub const registers = struct { /// address: 0x4001341c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare 3 /// selection CC3S: u2, @@ -9326,7 +9326,7 @@ pub const registers = struct { /// address: 0x40013420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -9419,7 +9419,7 @@ pub const registers = struct { /// address: 0x40013448 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -9450,7 +9450,7 @@ pub const registers = struct { /// address: 0x4001344c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -9474,7 +9474,7 @@ pub const registers = struct { /// address: 0x40013430 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u8, padding0: u1, @@ -9505,7 +9505,7 @@ pub const registers = struct { /// address: 0x40013444 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -9548,7 +9548,7 @@ pub const registers = struct { /// address: 0x40000000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -9592,7 +9592,7 @@ pub const registers = struct { /// address: 0x40000004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -9631,7 +9631,7 @@ pub const registers = struct { /// address: 0x40000008 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -9667,7 +9667,7 @@ pub const registers = struct { /// address: 0x4000000c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -9724,7 +9724,7 @@ pub const registers = struct { /// address: 0x40000010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -9779,7 +9779,7 @@ pub const registers = struct { /// address: 0x40000014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -9827,7 +9827,7 @@ pub const registers = struct { /// address: 0x40000018 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9877,7 +9877,7 @@ pub const registers = struct { /// address: 0x40000018 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9913,7 +9913,7 @@ pub const registers = struct { /// address: 0x4000001c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9963,7 +9963,7 @@ pub const registers = struct { /// address: 0x4000001c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9999,7 +9999,7 @@ pub const registers = struct { /// address: 0x40000020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -10080,7 +10080,7 @@ pub const registers = struct { /// address: 0x40000048 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -10111,7 +10111,7 @@ pub const registers = struct { /// address: 0x4000004c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -10138,7 +10138,7 @@ pub const registers = struct { /// address: 0x40000400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -10182,7 +10182,7 @@ pub const registers = struct { /// address: 0x40000404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -10221,7 +10221,7 @@ pub const registers = struct { /// address: 0x40000408 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -10257,7 +10257,7 @@ pub const registers = struct { /// address: 0x4000040c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -10314,7 +10314,7 @@ pub const registers = struct { /// address: 0x40000410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -10369,7 +10369,7 @@ pub const registers = struct { /// address: 0x40000414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -10417,7 +10417,7 @@ pub const registers = struct { /// address: 0x40000418 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10467,7 +10467,7 @@ pub const registers = struct { /// address: 0x40000418 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10503,7 +10503,7 @@ pub const registers = struct { /// address: 0x4000041c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -10553,7 +10553,7 @@ pub const registers = struct { /// address: 0x4000041c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -10589,7 +10589,7 @@ pub const registers = struct { /// address: 0x40000420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -10670,7 +10670,7 @@ pub const registers = struct { /// address: 0x40000448 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -10701,7 +10701,7 @@ pub const registers = struct { /// address: 0x4000044c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -10728,7 +10728,7 @@ pub const registers = struct { /// address: 0x40000800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -10772,7 +10772,7 @@ pub const registers = struct { /// address: 0x40000804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -10811,7 +10811,7 @@ pub const registers = struct { /// address: 0x40000808 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -10847,7 +10847,7 @@ pub const registers = struct { /// address: 0x4000080c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -10904,7 +10904,7 @@ pub const registers = struct { /// address: 0x40000810 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -10959,7 +10959,7 @@ pub const registers = struct { /// address: 0x40000814 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -11007,7 +11007,7 @@ pub const registers = struct { /// address: 0x40000818 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11057,7 +11057,7 @@ pub const registers = struct { /// address: 0x40000818 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11093,7 +11093,7 @@ pub const registers = struct { /// address: 0x4000081c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -11143,7 +11143,7 @@ pub const registers = struct { /// address: 0x4000081c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -11179,7 +11179,7 @@ pub const registers = struct { /// address: 0x40000820 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -11260,7 +11260,7 @@ pub const registers = struct { /// address: 0x40000848 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -11291,7 +11291,7 @@ pub const registers = struct { /// address: 0x4000084c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -11318,7 +11318,7 @@ pub const registers = struct { /// address: 0x40000c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -11362,7 +11362,7 @@ pub const registers = struct { /// address: 0x40000c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -11401,7 +11401,7 @@ pub const registers = struct { /// address: 0x40000c08 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -11437,7 +11437,7 @@ pub const registers = struct { /// address: 0x40000c0c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -11494,7 +11494,7 @@ pub const registers = struct { /// address: 0x40000c10 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -11549,7 +11549,7 @@ pub const registers = struct { /// address: 0x40000c14 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -11597,7 +11597,7 @@ pub const registers = struct { /// address: 0x40000c18 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11647,7 +11647,7 @@ pub const registers = struct { /// address: 0x40000c18 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11683,7 +11683,7 @@ pub const registers = struct { /// address: 0x40000c1c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -11733,7 +11733,7 @@ pub const registers = struct { /// address: 0x40000c1c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -11769,7 +11769,7 @@ pub const registers = struct { /// address: 0x40000c20 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -11850,7 +11850,7 @@ pub const registers = struct { /// address: 0x40000c48 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -11881,7 +11881,7 @@ pub const registers = struct { /// address: 0x40000c4c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -11909,7 +11909,7 @@ pub const registers = struct { /// address: 0x40014c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -11951,7 +11951,7 @@ pub const registers = struct { /// address: 0x40014c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -11987,7 +11987,7 @@ pub const registers = struct { /// address: 0x40014c08 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -12023,7 +12023,7 @@ pub const registers = struct { /// address: 0x40014c0c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -12066,7 +12066,7 @@ pub const registers = struct { /// address: 0x40014c10 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -12113,7 +12113,7 @@ pub const registers = struct { /// address: 0x40014c14 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -12157,7 +12157,7 @@ pub const registers = struct { /// address: 0x40014c18 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12203,7 +12203,7 @@ pub const registers = struct { /// address: 0x40014c18 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12239,7 +12239,7 @@ pub const registers = struct { /// address: 0x40014c20 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -12311,7 +12311,7 @@ pub const registers = struct { /// address: 0x40001800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -12353,7 +12353,7 @@ pub const registers = struct { /// address: 0x40001804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12389,7 +12389,7 @@ pub const registers = struct { /// address: 0x40001808 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -12425,7 +12425,7 @@ pub const registers = struct { /// address: 0x4000180c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -12468,7 +12468,7 @@ pub const registers = struct { /// address: 0x40001810 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -12515,7 +12515,7 @@ pub const registers = struct { /// address: 0x40001814 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -12559,7 +12559,7 @@ pub const registers = struct { /// address: 0x40001818 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12605,7 +12605,7 @@ pub const registers = struct { /// address: 0x40001818 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12641,7 +12641,7 @@ pub const registers = struct { /// address: 0x40001820 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -12714,7 +12714,7 @@ pub const registers = struct { /// address: 0x40015000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -12755,7 +12755,7 @@ pub const registers = struct { /// address: 0x40015004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12791,7 +12791,7 @@ pub const registers = struct { /// address: 0x4001500c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -12831,7 +12831,7 @@ pub const registers = struct { /// address: 0x40015010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -12873,7 +12873,7 @@ pub const registers = struct { /// address: 0x40015014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -12914,7 +12914,7 @@ pub const registers = struct { /// address: 0x40015018 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12954,7 +12954,7 @@ pub const registers = struct { /// address: 0x40015018 /// capture/compare mode register (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12991,7 +12991,7 @@ pub const registers = struct { /// address: 0x40015020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -13053,7 +13053,7 @@ pub const registers = struct { /// address: 0x40015400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -13094,7 +13094,7 @@ pub const registers = struct { /// address: 0x40015404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13130,7 +13130,7 @@ pub const registers = struct { /// address: 0x4001540c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -13170,7 +13170,7 @@ pub const registers = struct { /// address: 0x40015410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -13212,7 +13212,7 @@ pub const registers = struct { /// address: 0x40015414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -13253,7 +13253,7 @@ pub const registers = struct { /// address: 0x40015418 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -13293,7 +13293,7 @@ pub const registers = struct { /// address: 0x40015418 /// capture/compare mode register (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -13330,7 +13330,7 @@ pub const registers = struct { /// address: 0x40015420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -13392,7 +13392,7 @@ pub const registers = struct { /// address: 0x40001c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -13433,7 +13433,7 @@ pub const registers = struct { /// address: 0x40001c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13469,7 +13469,7 @@ pub const registers = struct { /// address: 0x40001c0c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -13509,7 +13509,7 @@ pub const registers = struct { /// address: 0x40001c10 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -13551,7 +13551,7 @@ pub const registers = struct { /// address: 0x40001c14 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -13592,7 +13592,7 @@ pub const registers = struct { /// address: 0x40001c18 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -13632,7 +13632,7 @@ pub const registers = struct { /// address: 0x40001c18 /// capture/compare mode register (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -13669,7 +13669,7 @@ pub const registers = struct { /// address: 0x40001c20 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -13731,7 +13731,7 @@ pub const registers = struct { /// address: 0x40002000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -13772,7 +13772,7 @@ pub const registers = struct { /// address: 0x40002004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13808,7 +13808,7 @@ pub const registers = struct { /// address: 0x4000200c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -13848,7 +13848,7 @@ pub const registers = struct { /// address: 0x40002010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -13890,7 +13890,7 @@ pub const registers = struct { /// address: 0x40002014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -13931,7 +13931,7 @@ pub const registers = struct { /// address: 0x40002018 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -13971,7 +13971,7 @@ pub const registers = struct { /// address: 0x40002018 /// capture/compare mode register (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -14008,7 +14008,7 @@ pub const registers = struct { /// address: 0x40002020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -14071,7 +14071,7 @@ pub const registers = struct { /// address: 0x40001000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -14113,7 +14113,7 @@ pub const registers = struct { /// address: 0x40001004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -14149,7 +14149,7 @@ pub const registers = struct { /// address: 0x4000100c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, reserved0: u1, @@ -14188,7 +14188,7 @@ pub const registers = struct { /// address: 0x40001010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, padding0: u1, @@ -14226,7 +14226,7 @@ pub const registers = struct { /// address: 0x40001014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, padding0: u1, @@ -14279,7 +14279,7 @@ pub const registers = struct { /// address: 0x40001400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -14321,7 +14321,7 @@ pub const registers = struct { /// address: 0x40001404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -14357,7 +14357,7 @@ pub const registers = struct { /// address: 0x4000140c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, reserved0: u1, @@ -14396,7 +14396,7 @@ pub const registers = struct { /// address: 0x40001410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, padding0: u1, @@ -14434,7 +14434,7 @@ pub const registers = struct { /// address: 0x40001414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, padding0: u1, @@ -14488,7 +14488,7 @@ pub const registers = struct { /// address: 0x40005400 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral enable PE: u1, /// SMBus mode @@ -14541,7 +14541,7 @@ pub const registers = struct { /// address: 0x40005404 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral clock frequency FREQ: u6, reserved0: u1, @@ -14579,7 +14579,7 @@ pub const registers = struct { /// address: 0x40005408 /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interface address ADD0: u1, /// Interface address @@ -14614,7 +14614,7 @@ pub const registers = struct { /// address: 0x4000540c /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Dual addressing mode /// enable ENDUAL: u1, @@ -14652,7 +14652,7 @@ pub const registers = struct { /// address: 0x40005414 /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Start bit (Master mode) SB: u1, /// Address sent (master mode)/matched @@ -14709,7 +14709,7 @@ pub const registers = struct { /// address: 0x40005418 /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Master/slave MSL: u1, /// Bus busy @@ -14751,7 +14751,7 @@ pub const registers = struct { /// address: 0x4000541c /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { /// Clock control register in Fast/Standard /// mode (Master mode) CCR: u12, @@ -14788,7 +14788,7 @@ pub const registers = struct { /// address: 0x40005800 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral enable PE: u1, /// SMBus mode @@ -14841,7 +14841,7 @@ pub const registers = struct { /// address: 0x40005804 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral clock frequency FREQ: u6, reserved0: u1, @@ -14879,7 +14879,7 @@ pub const registers = struct { /// address: 0x40005808 /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interface address ADD0: u1, /// Interface address @@ -14914,7 +14914,7 @@ pub const registers = struct { /// address: 0x4000580c /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Dual addressing mode /// enable ENDUAL: u1, @@ -14952,7 +14952,7 @@ pub const registers = struct { /// address: 0x40005814 /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Start bit (Master mode) SB: u1, /// Address sent (master mode)/matched @@ -15009,7 +15009,7 @@ pub const registers = struct { /// address: 0x40005818 /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Master/slave MSL: u1, /// Bus busy @@ -15051,7 +15051,7 @@ pub const registers = struct { /// address: 0x4000581c /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { /// Clock control register in Fast/Standard /// mode (Master mode) CCR: u12, @@ -15089,7 +15089,7 @@ pub const registers = struct { /// address: 0x40013000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15141,7 +15141,7 @@ pub const registers = struct { /// address: 0x40013004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15186,7 +15186,7 @@ pub const registers = struct { /// address: 0x40013008 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15235,7 +15235,7 @@ pub const registers = struct { /// address: 0x40013010 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15258,7 +15258,7 @@ pub const registers = struct { /// address: 0x40013014 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15281,7 +15281,7 @@ pub const registers = struct { /// address: 0x40013018 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15304,7 +15304,7 @@ pub const registers = struct { /// address: 0x4001301c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15349,7 +15349,7 @@ pub const registers = struct { /// address: 0x40013020 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15386,7 +15386,7 @@ pub const registers = struct { /// address: 0x40003800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15438,7 +15438,7 @@ pub const registers = struct { /// address: 0x40003804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15483,7 +15483,7 @@ pub const registers = struct { /// address: 0x40003808 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15532,7 +15532,7 @@ pub const registers = struct { /// address: 0x40003810 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15555,7 +15555,7 @@ pub const registers = struct { /// address: 0x40003814 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15578,7 +15578,7 @@ pub const registers = struct { /// address: 0x40003818 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15601,7 +15601,7 @@ pub const registers = struct { /// address: 0x4000381c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15646,7 +15646,7 @@ pub const registers = struct { /// address: 0x40003820 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15683,7 +15683,7 @@ pub const registers = struct { /// address: 0x40003c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15735,7 +15735,7 @@ pub const registers = struct { /// address: 0x40003c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15780,7 +15780,7 @@ pub const registers = struct { /// address: 0x40003c08 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15829,7 +15829,7 @@ pub const registers = struct { /// address: 0x40003c10 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15852,7 +15852,7 @@ pub const registers = struct { /// address: 0x40003c14 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15875,7 +15875,7 @@ pub const registers = struct { /// address: 0x40003c18 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15898,7 +15898,7 @@ pub const registers = struct { /// address: 0x40003c1c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15943,7 +15943,7 @@ pub const registers = struct { /// address: 0x40003c20 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15982,7 +15982,7 @@ pub const registers = struct { /// address: 0x40013800 /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -16035,7 +16035,7 @@ pub const registers = struct { /// address: 0x40013808 /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -16060,7 +16060,7 @@ pub const registers = struct { /// address: 0x4001380c /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Send break SBK: u1, /// Receiver wakeup @@ -16112,7 +16112,7 @@ pub const registers = struct { /// address: 0x40013810 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Address of the USART node ADD: u4, reserved0: u1, @@ -16155,7 +16155,7 @@ pub const registers = struct { /// address: 0x40013814 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -16204,7 +16204,7 @@ pub const registers = struct { /// address: 0x40013818 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -16232,7 +16232,7 @@ pub const registers = struct { /// address: 0x40004400 /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -16285,7 +16285,7 @@ pub const registers = struct { /// address: 0x40004408 /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -16310,7 +16310,7 @@ pub const registers = struct { /// address: 0x4000440c /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Send break SBK: u1, /// Receiver wakeup @@ -16362,7 +16362,7 @@ pub const registers = struct { /// address: 0x40004410 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Address of the USART node ADD: u4, reserved0: u1, @@ -16405,7 +16405,7 @@ pub const registers = struct { /// address: 0x40004414 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -16454,7 +16454,7 @@ pub const registers = struct { /// address: 0x40004418 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -16482,7 +16482,7 @@ pub const registers = struct { /// address: 0x40004800 /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -16535,7 +16535,7 @@ pub const registers = struct { /// address: 0x40004808 /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -16560,7 +16560,7 @@ pub const registers = struct { /// address: 0x4000480c /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Send break SBK: u1, /// Receiver wakeup @@ -16612,7 +16612,7 @@ pub const registers = struct { /// address: 0x40004810 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Address of the USART node ADD: u4, reserved0: u1, @@ -16655,7 +16655,7 @@ pub const registers = struct { /// address: 0x40004814 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -16704,7 +16704,7 @@ pub const registers = struct { /// address: 0x40004818 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -16733,7 +16733,7 @@ pub const registers = struct { /// address: 0x40012400 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog flag AWD: u1, /// Regular channel end of @@ -16778,7 +16778,7 @@ pub const registers = struct { /// address: 0x40012404 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog channel select /// bits AWDCH: u5, @@ -16829,7 +16829,7 @@ pub const registers = struct { /// address: 0x40012408 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// A/D converter ON / OFF ADON: u1, /// Continuous conversion @@ -16882,7 +16882,7 @@ pub const registers = struct { /// address: 0x4001240c /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 10 sample time /// selection SMP10: u3, @@ -16919,7 +16919,7 @@ pub const registers = struct { /// address: 0x40012410 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 0 sample time /// selection SMP0: u3, @@ -16957,7 +16957,7 @@ pub const registers = struct { /// address: 0x40012414 /// injected channel data offset register /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET1: u12, @@ -16986,7 +16986,7 @@ pub const registers = struct { /// address: 0x40012418 /// injected channel data offset register /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET2: u12, @@ -17015,7 +17015,7 @@ pub const registers = struct { /// address: 0x4001241c /// injected channel data offset register /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET3: u12, @@ -17044,7 +17044,7 @@ pub const registers = struct { /// address: 0x40012420 /// injected channel data offset register /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET4: u12, @@ -17073,7 +17073,7 @@ pub const registers = struct { /// address: 0x40012424 /// watchdog higher threshold /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog higher /// threshold HT: u12, @@ -17102,7 +17102,7 @@ pub const registers = struct { /// address: 0x40012428 /// watchdog lower threshold /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog lower /// threshold LT: u12, @@ -17130,7 +17130,7 @@ pub const registers = struct { /// address: 0x4001242c /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// 13th conversion in regular /// sequence SQ13: u5, @@ -17158,7 +17158,7 @@ pub const registers = struct { /// address: 0x40012430 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// 7th conversion in regular /// sequence SQ7: u5, @@ -17183,7 +17183,7 @@ pub const registers = struct { /// address: 0x40012434 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in regular /// sequence SQ1: u5, @@ -17208,7 +17208,7 @@ pub const registers = struct { /// address: 0x40012438 /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in injected /// sequence JSQ1: u5, @@ -17237,7 +17237,7 @@ pub const registers = struct { /// address: 0x4001243c /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17260,7 +17260,7 @@ pub const registers = struct { /// address: 0x40012440 /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17283,7 +17283,7 @@ pub const registers = struct { /// address: 0x40012444 /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17306,7 +17306,7 @@ pub const registers = struct { /// address: 0x40012448 /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17329,7 +17329,7 @@ pub const registers = struct { /// address: 0x4001244c /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// Regular data DATA: u16, /// ADC2 data @@ -17342,7 +17342,7 @@ pub const registers = struct { /// address: 0x40012800 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog flag AWD: u1, /// Regular channel end of @@ -17387,7 +17387,7 @@ pub const registers = struct { /// address: 0x40012804 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog channel select /// bits AWDCH: u5, @@ -17440,7 +17440,7 @@ pub const registers = struct { /// address: 0x40012808 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// A/D converter ON / OFF ADON: u1, /// Continuous conversion @@ -17493,7 +17493,7 @@ pub const registers = struct { /// address: 0x4001280c /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 10 sample time /// selection SMP10: u3, @@ -17530,7 +17530,7 @@ pub const registers = struct { /// address: 0x40012810 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 0 sample time /// selection SMP0: u3, @@ -17568,7 +17568,7 @@ pub const registers = struct { /// address: 0x40012814 /// injected channel data offset register /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET1: u12, @@ -17597,7 +17597,7 @@ pub const registers = struct { /// address: 0x40012818 /// injected channel data offset register /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET2: u12, @@ -17626,7 +17626,7 @@ pub const registers = struct { /// address: 0x4001281c /// injected channel data offset register /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET3: u12, @@ -17655,7 +17655,7 @@ pub const registers = struct { /// address: 0x40012820 /// injected channel data offset register /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET4: u12, @@ -17684,7 +17684,7 @@ pub const registers = struct { /// address: 0x40012824 /// watchdog higher threshold /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog higher /// threshold HT: u12, @@ -17713,7 +17713,7 @@ pub const registers = struct { /// address: 0x40012828 /// watchdog lower threshold /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog lower /// threshold LT: u12, @@ -17741,7 +17741,7 @@ pub const registers = struct { /// address: 0x4001282c /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// 13th conversion in regular /// sequence SQ13: u5, @@ -17769,7 +17769,7 @@ pub const registers = struct { /// address: 0x40012830 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// 7th conversion in regular /// sequence SQ7: u5, @@ -17794,7 +17794,7 @@ pub const registers = struct { /// address: 0x40012834 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in regular /// sequence SQ1: u5, @@ -17819,7 +17819,7 @@ pub const registers = struct { /// address: 0x40012838 /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in injected /// sequence JSQ1: u5, @@ -17848,7 +17848,7 @@ pub const registers = struct { /// address: 0x4001283c /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17871,7 +17871,7 @@ pub const registers = struct { /// address: 0x40012840 /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17894,7 +17894,7 @@ pub const registers = struct { /// address: 0x40012844 /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17917,7 +17917,7 @@ pub const registers = struct { /// address: 0x40012848 /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -17940,7 +17940,7 @@ pub const registers = struct { /// address: 0x4001284c /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// Regular data DATA: u16, padding0: u1, @@ -17966,7 +17966,7 @@ pub const registers = struct { /// address: 0x40013c00 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog flag AWD: u1, /// Regular channel end of @@ -18011,7 +18011,7 @@ pub const registers = struct { /// address: 0x40013c04 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog channel select /// bits AWDCH: u5, @@ -18064,7 +18064,7 @@ pub const registers = struct { /// address: 0x40013c08 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// A/D converter ON / OFF ADON: u1, /// Continuous conversion @@ -18117,7 +18117,7 @@ pub const registers = struct { /// address: 0x40013c0c /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 10 sample time /// selection SMP10: u3, @@ -18154,7 +18154,7 @@ pub const registers = struct { /// address: 0x40013c10 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 0 sample time /// selection SMP0: u3, @@ -18192,7 +18192,7 @@ pub const registers = struct { /// address: 0x40013c14 /// injected channel data offset register /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET1: u12, @@ -18221,7 +18221,7 @@ pub const registers = struct { /// address: 0x40013c18 /// injected channel data offset register /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET2: u12, @@ -18250,7 +18250,7 @@ pub const registers = struct { /// address: 0x40013c1c /// injected channel data offset register /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET3: u12, @@ -18279,7 +18279,7 @@ pub const registers = struct { /// address: 0x40013c20 /// injected channel data offset register /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Data offset for injected channel /// x JOFFSET4: u12, @@ -18308,7 +18308,7 @@ pub const registers = struct { /// address: 0x40013c24 /// watchdog higher threshold /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog higher /// threshold HT: u12, @@ -18337,7 +18337,7 @@ pub const registers = struct { /// address: 0x40013c28 /// watchdog lower threshold /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog watchdog lower /// threshold LT: u12, @@ -18365,7 +18365,7 @@ pub const registers = struct { /// address: 0x40013c2c /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// 13th conversion in regular /// sequence SQ13: u5, @@ -18393,7 +18393,7 @@ pub const registers = struct { /// address: 0x40013c30 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// 7th conversion in regular /// sequence SQ7: u5, @@ -18418,7 +18418,7 @@ pub const registers = struct { /// address: 0x40013c34 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in regular /// sequence SQ1: u5, @@ -18443,7 +18443,7 @@ pub const registers = struct { /// address: 0x40013c38 /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// 1st conversion in injected /// sequence JSQ1: u5, @@ -18472,7 +18472,7 @@ pub const registers = struct { /// address: 0x40013c3c /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -18495,7 +18495,7 @@ pub const registers = struct { /// address: 0x40013c40 /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -18518,7 +18518,7 @@ pub const registers = struct { /// address: 0x40013c44 /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -18541,7 +18541,7 @@ pub const registers = struct { /// address: 0x40013c48 /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Injected data JDATA: u16, padding0: u1, @@ -18564,7 +18564,7 @@ pub const registers = struct { /// address: 0x40013c4c /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// Regular data DATA: u16, padding0: u1, @@ -18591,7 +18591,7 @@ pub const registers = struct { /// address: 0x40006400 /// CAN_MCR - pub const CAN_MCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_MCR = @intToPtr(*volatile Mmio(32, packed struct { /// INRQ INRQ: u1, /// SLEEP @@ -18638,7 +18638,7 @@ pub const registers = struct { /// address: 0x40006404 /// CAN_MSR - pub const CAN_MSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_MSR = @intToPtr(*volatile Mmio(32, packed struct { /// INAK INAK: u1, /// SLAK @@ -18684,7 +18684,7 @@ pub const registers = struct { /// address: 0x40006408 /// CAN_TSR - pub const CAN_TSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TSR = @intToPtr(*volatile Mmio(32, packed struct { /// RQCP0 RQCP0: u1, /// TXOK0 @@ -18748,7 +18748,7 @@ pub const registers = struct { /// address: 0x4000640c /// CAN_RF0R - pub const CAN_RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RF0R = @intToPtr(*volatile Mmio(32, packed struct { /// FMP0 FMP0: u2, reserved0: u1, @@ -18788,7 +18788,7 @@ pub const registers = struct { /// address: 0x40006410 /// CAN_RF1R - pub const CAN_RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RF1R = @intToPtr(*volatile Mmio(32, packed struct { /// FMP1 FMP1: u2, reserved0: u1, @@ -18828,7 +18828,7 @@ pub const registers = struct { /// address: 0x40006414 /// CAN_IER - pub const CAN_IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_IER = @intToPtr(*volatile Mmio(32, packed struct { /// TMEIE TMEIE: u1, /// FMPIE0 @@ -18879,7 +18879,7 @@ pub const registers = struct { /// address: 0x40006418 /// CAN_ESR - pub const CAN_ESR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_ESR = @intToPtr(*volatile Mmio(32, packed struct { /// EWGF EWGF: u1, /// EPVF @@ -18906,7 +18906,7 @@ pub const registers = struct { /// address: 0x4000641c /// CAN_BTR - pub const CAN_BTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_BTR = @intToPtr(*volatile Mmio(32, packed struct { /// BRP BRP: u10, reserved0: u1, @@ -18934,7 +18934,7 @@ pub const registers = struct { /// address: 0x40006580 /// CAN_TI0R - pub const CAN_TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TI0R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -18949,7 +18949,7 @@ pub const registers = struct { /// address: 0x40006584 /// CAN_TDT0R - pub const CAN_TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDT0R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -18971,7 +18971,7 @@ pub const registers = struct { /// address: 0x40006588 /// CAN_TDL0R - pub const CAN_TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDL0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -18984,7 +18984,7 @@ pub const registers = struct { /// address: 0x4000658c /// CAN_TDH0R - pub const CAN_TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDH0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -18997,7 +18997,7 @@ pub const registers = struct { /// address: 0x40006590 /// CAN_TI1R - pub const CAN_TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TI1R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -19012,7 +19012,7 @@ pub const registers = struct { /// address: 0x40006594 /// CAN_TDT1R - pub const CAN_TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDT1R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -19034,7 +19034,7 @@ pub const registers = struct { /// address: 0x40006598 /// CAN_TDL1R - pub const CAN_TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDL1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -19047,7 +19047,7 @@ pub const registers = struct { /// address: 0x4000659c /// CAN_TDH1R - pub const CAN_TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDH1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -19060,7 +19060,7 @@ pub const registers = struct { /// address: 0x400065a0 /// CAN_TI2R - pub const CAN_TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TI2R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -19075,7 +19075,7 @@ pub const registers = struct { /// address: 0x400065a4 /// CAN_TDT2R - pub const CAN_TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDT2R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -19097,7 +19097,7 @@ pub const registers = struct { /// address: 0x400065a8 /// CAN_TDL2R - pub const CAN_TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDL2R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -19110,7 +19110,7 @@ pub const registers = struct { /// address: 0x400065ac /// CAN_TDH2R - pub const CAN_TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_TDH2R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -19123,7 +19123,7 @@ pub const registers = struct { /// address: 0x400065b0 /// CAN_RI0R - pub const CAN_RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RI0R = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// RTR RTR: u1, @@ -19137,7 +19137,7 @@ pub const registers = struct { /// address: 0x400065b4 /// CAN_RDT0R - pub const CAN_RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDT0R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -19152,7 +19152,7 @@ pub const registers = struct { /// address: 0x400065b8 /// CAN_RDL0R - pub const CAN_RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDL0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -19165,7 +19165,7 @@ pub const registers = struct { /// address: 0x400065bc /// CAN_RDH0R - pub const CAN_RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDH0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -19178,7 +19178,7 @@ pub const registers = struct { /// address: 0x400065c0 /// CAN_RI1R - pub const CAN_RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RI1R = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// RTR RTR: u1, @@ -19192,7 +19192,7 @@ pub const registers = struct { /// address: 0x400065c4 /// CAN_RDT1R - pub const CAN_RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDT1R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -19207,7 +19207,7 @@ pub const registers = struct { /// address: 0x400065c8 /// CAN_RDL1R - pub const CAN_RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDL1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -19220,7 +19220,7 @@ pub const registers = struct { /// address: 0x400065cc /// CAN_RDH1R - pub const CAN_RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_RDH1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -19233,7 +19233,7 @@ pub const registers = struct { /// address: 0x40006600 /// CAN_FMR - pub const CAN_FMR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_FMR = @intToPtr(*volatile Mmio(32, packed struct { /// FINIT FINIT: u1, padding0: u1, @@ -19271,7 +19271,7 @@ pub const registers = struct { /// address: 0x40006604 /// CAN_FM1R - pub const CAN_FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_FM1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter mode FBM0: u1, /// Filter mode @@ -19322,7 +19322,7 @@ pub const registers = struct { /// address: 0x4000660c /// CAN_FS1R - pub const CAN_FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_FS1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter scale configuration FSC0: u1, /// Filter scale configuration @@ -19373,7 +19373,7 @@ pub const registers = struct { /// address: 0x40006614 /// CAN_FFA1R - pub const CAN_FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_FFA1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter FIFO assignment for filter /// 0 FFA0: u1, @@ -19438,7 +19438,7 @@ pub const registers = struct { /// address: 0x4000661c /// CAN_FA1R - pub const CAN_FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CAN_FA1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter active FACT0: u1, /// Filter active @@ -19489,7 +19489,7 @@ pub const registers = struct { /// address: 0x40006640 /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19558,7 +19558,7 @@ pub const registers = struct { /// address: 0x40006644 /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19627,7 +19627,7 @@ pub const registers = struct { /// address: 0x40006648 /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19696,7 +19696,7 @@ pub const registers = struct { /// address: 0x4000664c /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19765,7 +19765,7 @@ pub const registers = struct { /// address: 0x40006650 /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19834,7 +19834,7 @@ pub const registers = struct { /// address: 0x40006654 /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19903,7 +19903,7 @@ pub const registers = struct { /// address: 0x40006658 /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19972,7 +19972,7 @@ pub const registers = struct { /// address: 0x4000665c /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20041,7 +20041,7 @@ pub const registers = struct { /// address: 0x40006660 /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20110,7 +20110,7 @@ pub const registers = struct { /// address: 0x40006664 /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20179,7 +20179,7 @@ pub const registers = struct { /// address: 0x40006668 /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20248,7 +20248,7 @@ pub const registers = struct { /// address: 0x4000666c /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20317,7 +20317,7 @@ pub const registers = struct { /// address: 0x40006670 /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20386,7 +20386,7 @@ pub const registers = struct { /// address: 0x40006674 /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20455,7 +20455,7 @@ pub const registers = struct { /// address: 0x40006678 /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20524,7 +20524,7 @@ pub const registers = struct { /// address: 0x4000667c /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20593,7 +20593,7 @@ pub const registers = struct { /// address: 0x40006680 /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20662,7 +20662,7 @@ pub const registers = struct { /// address: 0x40006684 /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20731,7 +20731,7 @@ pub const registers = struct { /// address: 0x40006688 /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20800,7 +20800,7 @@ pub const registers = struct { /// address: 0x4000668c /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20869,7 +20869,7 @@ pub const registers = struct { /// address: 0x40006690 /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20938,7 +20938,7 @@ pub const registers = struct { /// address: 0x40006694 /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21007,7 +21007,7 @@ pub const registers = struct { /// address: 0x40006698 /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21076,7 +21076,7 @@ pub const registers = struct { /// address: 0x4000669c /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21145,7 +21145,7 @@ pub const registers = struct { /// address: 0x400066a0 /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21214,7 +21214,7 @@ pub const registers = struct { /// address: 0x400066a4 /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21283,7 +21283,7 @@ pub const registers = struct { /// address: 0x400066a8 /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21352,7 +21352,7 @@ pub const registers = struct { /// address: 0x400066ac /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21425,7 +21425,7 @@ pub const registers = struct { /// address: 0x40007400 /// Control register (DAC_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 enable EN1: u1, /// DAC channel1 output buffer @@ -21475,7 +21475,7 @@ pub const registers = struct { /// address: 0x40007404 /// DAC software trigger register /// (DAC_SWTRIGR) - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 software /// trigger SWTRIG1: u1, @@ -21517,7 +21517,7 @@ pub const registers = struct { /// address: 0x40007408 /// DAC channel1 12-bit right-aligned data /// holding register(DAC_DHR12R1) - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 12-bit right-aligned /// data DACC1DHR: u12, @@ -21546,7 +21546,7 @@ pub const registers = struct { /// address: 0x4000740c /// DAC channel1 12-bit left aligned data /// holding register (DAC_DHR12L1) - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -21575,7 +21575,7 @@ pub const registers = struct { /// address: 0x40007410 /// DAC channel1 8-bit right aligned data /// holding register (DAC_DHR8R1) - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 8-bit right-aligned /// data DACC1DHR: u8, @@ -21608,7 +21608,7 @@ pub const registers = struct { /// address: 0x40007414 /// DAC channel2 12-bit right aligned data /// holding register (DAC_DHR12R2) - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 12-bit right-aligned /// data DACC2DHR: u12, @@ -21637,7 +21637,7 @@ pub const registers = struct { /// address: 0x40007418 /// DAC channel2 12-bit left aligned data /// holding register (DAC_DHR12L2) - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -21666,7 +21666,7 @@ pub const registers = struct { /// address: 0x4000741c /// DAC channel2 8-bit right-aligned data /// holding register (DAC_DHR8R2) - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 8-bit right-aligned /// data DACC2DHR: u8, @@ -21700,7 +21700,7 @@ pub const registers = struct { /// Dual DAC 12-bit right-aligned data holding /// register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 /// Reserved - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 12-bit right-aligned /// data DACC1DHR: u12, @@ -21721,7 +21721,7 @@ pub const registers = struct { /// DUAL DAC 12-bit left aligned data holding /// register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 /// Reserved - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -21741,7 +21741,7 @@ pub const registers = struct { /// address: 0x40007428 /// DUAL DAC 8-bit right aligned data holding /// register (DAC_DHR8RD), Bits 31:16 Reserved - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 8-bit right-aligned /// data DACC1DHR: u8, @@ -21769,7 +21769,7 @@ pub const registers = struct { /// address: 0x4000742c /// DAC channel1 data output register /// (DAC_DOR1) - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 data output DACC1DOR: u12, padding0: u1, @@ -21797,7 +21797,7 @@ pub const registers = struct { /// address: 0x40007430 /// DAC channel2 data output register /// (DAC_DOR2) - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 data output DACC2DOR: u12, padding0: u1, @@ -21828,7 +21828,7 @@ pub const registers = struct { /// address: 0xe0042000 /// DBGMCU_IDCODE - pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct { /// DEV_ID DEV_ID: u12, reserved0: u1, @@ -21841,7 +21841,7 @@ pub const registers = struct { /// address: 0xe0042004 /// DBGMCU_CR - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// DBG_SLEEP DBG_SLEEP: u1, /// DBG_STOP @@ -21901,7 +21901,7 @@ pub const registers = struct { /// address: 0x40004c00 /// UART4_SR - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -21953,7 +21953,7 @@ pub const registers = struct { /// address: 0x40004c08 /// UART4_BRR - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// DIV_Fraction DIV_Fraction: u4, /// DIV_Mantissa @@ -21978,7 +21978,7 @@ pub const registers = struct { /// address: 0x40004c0c /// UART4_CR1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Send break SBK: u1, /// Receiver wakeup @@ -22030,7 +22030,7 @@ pub const registers = struct { /// address: 0x40004c10 /// UART4_CR2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Address of the USART node ADD: u4, reserved0: u1, @@ -22069,7 +22069,7 @@ pub const registers = struct { /// address: 0x40004c14 /// UART4_CR3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -22117,7 +22117,7 @@ pub const registers = struct { /// address: 0x40005000 /// UART4_SR - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// PE PE: u1, /// FE @@ -22167,7 +22167,7 @@ pub const registers = struct { /// address: 0x40005008 /// UART4_BRR - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// DIV_Fraction DIV_Fraction: u4, /// DIV_Mantissa @@ -22192,7 +22192,7 @@ pub const registers = struct { /// address: 0x4000500c /// UART4_CR1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// SBK SBK: u1, /// RWU @@ -22243,7 +22243,7 @@ pub const registers = struct { /// address: 0x40005010 /// UART4_CR2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ADD ADD: u4, reserved0: u1, @@ -22281,7 +22281,7 @@ pub const registers = struct { /// address: 0x40005014 /// UART4_CR3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -22335,7 +22335,7 @@ pub const registers = struct { /// address: 0x40023008 /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Reset bit RESET: u1, padding0: u1, @@ -22377,7 +22377,7 @@ pub const registers = struct { /// address: 0x40022000 /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { /// Latency LATENCY: u3, /// Flash half cycle access @@ -22417,21 +22417,21 @@ pub const registers = struct { /// address: 0x40022004 /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { /// FPEC key KEY: u32, }), base_address + 0x4); /// address: 0x40022008 /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { /// Option byte key OPTKEY: u32, }), base_address + 0x8); /// address: 0x4002200c /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Busy BSY: u1, reserved0: u1, @@ -22472,7 +22472,7 @@ pub const registers = struct { /// address: 0x40022010 /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Programming PG: u1, /// Page Erase @@ -22520,14 +22520,14 @@ pub const registers = struct { /// address: 0x40022014 /// Flash address register - pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AR = @intToPtr(*volatile Mmio(32, packed struct { /// Flash Address FAR: u32, }), base_address + 0x14); /// address: 0x4002201c /// Option byte register - pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct { /// Option byte error OPTERR: u1, /// Read protection @@ -22557,7 +22557,7 @@ pub const registers = struct { /// address: 0x40022020 /// Write protection register - pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct { /// Write protect WRP: u32, }), base_address + 0x20); @@ -22570,7 +22570,7 @@ pub const registers = struct { /// address: 0xe000e004 /// Interrupt Controller Type /// Register - pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct { /// Total number of interrupt lines in /// groups INTLINESNUM: u4, @@ -22607,7 +22607,7 @@ pub const registers = struct { /// address: 0xe000ef00 /// Software Triggered Interrupt /// Register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { /// interrupt to be triggered INTID: u9, padding0: u1, @@ -22637,14 +22637,14 @@ pub const registers = struct { /// address: 0xe000e100 /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { /// SETENA SETENA: u32, }), base_address + 0x100); /// address: 0xe000e104 /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { /// SETENA SETENA: u32, }), base_address + 0x104); @@ -22652,7 +22652,7 @@ pub const registers = struct { /// address: 0xe000e180 /// Interrupt Clear-Enable /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRENA CLRENA: u32, }), base_address + 0x180); @@ -22660,21 +22660,21 @@ pub const registers = struct { /// address: 0xe000e184 /// Interrupt Clear-Enable /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRENA CLRENA: u32, }), base_address + 0x184); /// address: 0xe000e200 /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// SETPEND SETPEND: u32, }), base_address + 0x200); /// address: 0xe000e204 /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// SETPEND SETPEND: u32, }), base_address + 0x204); @@ -22682,7 +22682,7 @@ pub const registers = struct { /// address: 0xe000e280 /// Interrupt Clear-Pending /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRPEND CLRPEND: u32, }), base_address + 0x280); @@ -22690,28 +22690,28 @@ pub const registers = struct { /// address: 0xe000e284 /// Interrupt Clear-Pending /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRPEND CLRPEND: u32, }), base_address + 0x284); /// address: 0xe000e300 /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { /// ACTIVE ACTIVE: u32, }), base_address + 0x300); /// address: 0xe000e304 /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ACTIVE ACTIVE: u32, }), base_address + 0x304); /// address: 0xe000e400 /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22724,7 +22724,7 @@ pub const registers = struct { /// address: 0xe000e404 /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22737,7 +22737,7 @@ pub const registers = struct { /// address: 0xe000e408 /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22750,7 +22750,7 @@ pub const registers = struct { /// address: 0xe000e40c /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22763,7 +22763,7 @@ pub const registers = struct { /// address: 0xe000e410 /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22776,7 +22776,7 @@ pub const registers = struct { /// address: 0xe000e414 /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22789,7 +22789,7 @@ pub const registers = struct { /// address: 0xe000e418 /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22802,7 +22802,7 @@ pub const registers = struct { /// address: 0xe000e41c /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22815,7 +22815,7 @@ pub const registers = struct { /// address: 0xe000e420 /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22828,7 +22828,7 @@ pub const registers = struct { /// address: 0xe000e424 /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22841,7 +22841,7 @@ pub const registers = struct { /// address: 0xe000e428 /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22854,7 +22854,7 @@ pub const registers = struct { /// address: 0xe000e42c /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22867,7 +22867,7 @@ pub const registers = struct { /// address: 0xe000e430 /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22880,7 +22880,7 @@ pub const registers = struct { /// address: 0xe000e434 /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22893,7 +22893,7 @@ pub const registers = struct { /// address: 0xe000e438 /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -22911,7 +22911,7 @@ pub const registers = struct { /// address: 0x40005c00 /// endpoint 0 register - pub const EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP0R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -22959,7 +22959,7 @@ pub const registers = struct { /// address: 0x40005c04 /// endpoint 1 register - pub const EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP1R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23007,7 +23007,7 @@ pub const registers = struct { /// address: 0x40005c08 /// endpoint 2 register - pub const EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP2R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23055,7 +23055,7 @@ pub const registers = struct { /// address: 0x40005c0c /// endpoint 3 register - pub const EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP3R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23103,7 +23103,7 @@ pub const registers = struct { /// address: 0x40005c10 /// endpoint 4 register - pub const EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP4R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23151,7 +23151,7 @@ pub const registers = struct { /// address: 0x40005c14 /// endpoint 5 register - pub const EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP5R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23199,7 +23199,7 @@ pub const registers = struct { /// address: 0x40005c18 /// endpoint 6 register - pub const EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP6R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23247,7 +23247,7 @@ pub const registers = struct { /// address: 0x40005c1c /// endpoint 7 register - pub const EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EP7R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -23295,7 +23295,7 @@ pub const registers = struct { /// address: 0x40005c40 /// control register - pub const CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNTR = @intToPtr(*volatile Mmio(32, packed struct { /// Force USB Reset FRES: u1, /// Power down @@ -23350,7 +23350,7 @@ pub const registers = struct { /// address: 0x40005c44 /// interrupt status register - pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint Identifier EP_ID: u4, /// Direction of transaction @@ -23395,7 +23395,7 @@ pub const registers = struct { /// address: 0x40005c48 /// frame number register - pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct { /// Frame number FN: u11, /// Lost SOF @@ -23426,7 +23426,7 @@ pub const registers = struct { /// address: 0x40005c4c /// device address - pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct { /// Device address ADD: u7, /// Enable function diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index f5a994a..64ff216 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -3,7 +3,7 @@ // device: STM32F303 // cpu: CM4 -pub const VectorTable = struct { +pub const VectorTable = extern struct { initial_stack_pointer: u32, Reset: InterruptVector = unhandled, NMI: InterruptVector = unhandled, @@ -208,7 +208,7 @@ pub const registers = struct { /// address: 0x48000000 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -261,7 +261,7 @@ pub const registers = struct { /// address: 0x48000004 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OT0: u1, @@ -331,7 +331,7 @@ pub const registers = struct { /// address: 0x48000008 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -385,7 +385,7 @@ pub const registers = struct { /// address: 0x4800000c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -438,7 +438,7 @@ pub const registers = struct { /// address: 0x48000010 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -507,7 +507,7 @@ pub const registers = struct { /// address: 0x48000014 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -577,7 +577,7 @@ pub const registers = struct { /// address: 0x48000018 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -679,7 +679,7 @@ pub const registers = struct { /// address: 0x4800001c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -750,7 +750,7 @@ pub const registers = struct { /// address: 0x48000020 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -780,7 +780,7 @@ pub const registers = struct { /// address: 0x48000024 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -809,7 +809,7 @@ pub const registers = struct { /// address: 0x48000028 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -866,7 +866,7 @@ pub const registers = struct { /// address: 0x48000400 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -919,7 +919,7 @@ pub const registers = struct { /// address: 0x48000404 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -979,7 +979,7 @@ pub const registers = struct { /// address: 0x48000408 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -1033,7 +1033,7 @@ pub const registers = struct { /// address: 0x4800040c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -1086,7 +1086,7 @@ pub const registers = struct { /// address: 0x48000410 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -1155,7 +1155,7 @@ pub const registers = struct { /// address: 0x48000414 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -1225,7 +1225,7 @@ pub const registers = struct { /// address: 0x48000418 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -1327,7 +1327,7 @@ pub const registers = struct { /// address: 0x4800041c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -1398,7 +1398,7 @@ pub const registers = struct { /// address: 0x48000420 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -1428,7 +1428,7 @@ pub const registers = struct { /// address: 0x48000424 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -1457,7 +1457,7 @@ pub const registers = struct { /// address: 0x48000428 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -1513,7 +1513,7 @@ pub const registers = struct { /// address: 0x48000800 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -1566,7 +1566,7 @@ pub const registers = struct { /// address: 0x48000804 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -1626,7 +1626,7 @@ pub const registers = struct { /// address: 0x48000808 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -1680,7 +1680,7 @@ pub const registers = struct { /// address: 0x4800080c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -1733,7 +1733,7 @@ pub const registers = struct { /// address: 0x48000810 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -1802,7 +1802,7 @@ pub const registers = struct { /// address: 0x48000814 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -1872,7 +1872,7 @@ pub const registers = struct { /// address: 0x48000818 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -1974,7 +1974,7 @@ pub const registers = struct { /// address: 0x4800081c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -2045,7 +2045,7 @@ pub const registers = struct { /// address: 0x48000820 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -2075,7 +2075,7 @@ pub const registers = struct { /// address: 0x48000824 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -2104,7 +2104,7 @@ pub const registers = struct { /// address: 0x48000828 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -2160,7 +2160,7 @@ pub const registers = struct { /// address: 0x48000c00 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -2213,7 +2213,7 @@ pub const registers = struct { /// address: 0x48000c04 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -2273,7 +2273,7 @@ pub const registers = struct { /// address: 0x48000c08 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -2327,7 +2327,7 @@ pub const registers = struct { /// address: 0x48000c0c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -2380,7 +2380,7 @@ pub const registers = struct { /// address: 0x48000c10 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -2449,7 +2449,7 @@ pub const registers = struct { /// address: 0x48000c14 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -2519,7 +2519,7 @@ pub const registers = struct { /// address: 0x48000c18 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -2621,7 +2621,7 @@ pub const registers = struct { /// address: 0x48000c1c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -2692,7 +2692,7 @@ pub const registers = struct { /// address: 0x48000c20 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -2722,7 +2722,7 @@ pub const registers = struct { /// address: 0x48000c24 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -2751,7 +2751,7 @@ pub const registers = struct { /// address: 0x48000c28 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -2807,7 +2807,7 @@ pub const registers = struct { /// address: 0x48001000 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -2860,7 +2860,7 @@ pub const registers = struct { /// address: 0x48001004 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -2920,7 +2920,7 @@ pub const registers = struct { /// address: 0x48001008 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -2974,7 +2974,7 @@ pub const registers = struct { /// address: 0x4800100c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -3027,7 +3027,7 @@ pub const registers = struct { /// address: 0x48001010 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -3096,7 +3096,7 @@ pub const registers = struct { /// address: 0x48001014 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -3166,7 +3166,7 @@ pub const registers = struct { /// address: 0x48001018 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -3268,7 +3268,7 @@ pub const registers = struct { /// address: 0x4800101c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -3339,7 +3339,7 @@ pub const registers = struct { /// address: 0x48001020 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -3369,7 +3369,7 @@ pub const registers = struct { /// address: 0x48001024 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -3398,7 +3398,7 @@ pub const registers = struct { /// address: 0x48001028 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -3454,7 +3454,7 @@ pub const registers = struct { /// address: 0x48001400 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -3507,7 +3507,7 @@ pub const registers = struct { /// address: 0x48001404 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -3567,7 +3567,7 @@ pub const registers = struct { /// address: 0x48001408 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -3621,7 +3621,7 @@ pub const registers = struct { /// address: 0x4800140c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -3674,7 +3674,7 @@ pub const registers = struct { /// address: 0x48001410 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -3743,7 +3743,7 @@ pub const registers = struct { /// address: 0x48001414 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -3813,7 +3813,7 @@ pub const registers = struct { /// address: 0x48001418 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -3915,7 +3915,7 @@ pub const registers = struct { /// address: 0x4800141c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -3986,7 +3986,7 @@ pub const registers = struct { /// address: 0x48001420 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -4016,7 +4016,7 @@ pub const registers = struct { /// address: 0x48001424 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -4045,7 +4045,7 @@ pub const registers = struct { /// address: 0x48001428 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -4101,7 +4101,7 @@ pub const registers = struct { /// address: 0x48001800 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -4154,7 +4154,7 @@ pub const registers = struct { /// address: 0x48001804 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -4214,7 +4214,7 @@ pub const registers = struct { /// address: 0x48001808 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -4268,7 +4268,7 @@ pub const registers = struct { /// address: 0x4800180c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -4321,7 +4321,7 @@ pub const registers = struct { /// address: 0x48001810 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -4390,7 +4390,7 @@ pub const registers = struct { /// address: 0x48001814 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -4460,7 +4460,7 @@ pub const registers = struct { /// address: 0x48001818 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -4562,7 +4562,7 @@ pub const registers = struct { /// address: 0x4800181c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -4633,7 +4633,7 @@ pub const registers = struct { /// address: 0x48001820 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -4663,7 +4663,7 @@ pub const registers = struct { /// address: 0x48001824 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -4692,7 +4692,7 @@ pub const registers = struct { /// address: 0x48001828 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -4748,7 +4748,7 @@ pub const registers = struct { /// address: 0x48001c00 /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) MODER0: u2, @@ -4801,7 +4801,7 @@ pub const registers = struct { /// address: 0x48001c04 /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bit 0 OT0: u1, /// Port x configuration bit 1 @@ -4861,7 +4861,7 @@ pub const registers = struct { /// address: 0x48001c08 /// GPIO port output speed /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) OSPEEDR0: u2, @@ -4915,7 +4915,7 @@ pub const registers = struct { /// address: 0x48001c0c /// GPIO port pull-up/pull-down /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x configuration bits (y = /// 0..15) PUPDR0: u2, @@ -4968,7 +4968,7 @@ pub const registers = struct { /// address: 0x48001c10 /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { /// Port input data (y = /// 0..15) IDR0: u1, @@ -5037,7 +5037,7 @@ pub const registers = struct { /// address: 0x48001c14 /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { /// Port output data (y = /// 0..15) ODR0: u1, @@ -5107,7 +5107,7 @@ pub const registers = struct { /// address: 0x48001c18 /// GPIO port bit set/reset /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x set bit y (y= /// 0..15) BS0: u1, @@ -5209,7 +5209,7 @@ pub const registers = struct { /// address: 0x48001c1c /// GPIO port configuration lock /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x lock bit y (y= /// 0..15) LCK0: u1, @@ -5280,7 +5280,7 @@ pub const registers = struct { /// address: 0x48001c20 /// GPIO alternate function low /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 0..7) AFRL0: u4, @@ -5310,7 +5310,7 @@ pub const registers = struct { /// address: 0x48001c24 /// GPIO alternate function high /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { /// Alternate function selection for port x /// bit y (y = 8..15) AFRH8: u4, @@ -5339,7 +5339,7 @@ pub const registers = struct { /// address: 0x48001c28 /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// Port x Reset bit y BR0: u1, /// Port x Reset bit y @@ -5396,7 +5396,7 @@ pub const registers = struct { /// address: 0x40024000 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Touch sensing controller /// enable TSCE: u1, @@ -5431,7 +5431,7 @@ pub const registers = struct { /// address: 0x40024004 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// End of acquisition interrupt /// enable EOAIE: u1, @@ -5472,7 +5472,7 @@ pub const registers = struct { /// address: 0x40024008 /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// End of acquisition interrupt /// clear EOAIC: u1, @@ -5513,7 +5513,7 @@ pub const registers = struct { /// address: 0x4002400c /// interrupt status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// End of acquisition flag EOAF: u1, /// Max count error flag @@ -5553,7 +5553,7 @@ pub const registers = struct { /// address: 0x40024010 /// I/O hysteresis control /// register - pub const IOHCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOHCR = @intToPtr(*volatile Mmio(32, packed struct { /// G1_IO1 Schmitt trigger hysteresis /// mode G1_IO1: u1, @@ -5655,7 +5655,7 @@ pub const registers = struct { /// address: 0x40024018 /// I/O analog switch control /// register - pub const IOASCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOASCR = @intToPtr(*volatile Mmio(32, packed struct { /// G1_IO1 analog switch /// enable G1_IO1: u1, @@ -5756,7 +5756,7 @@ pub const registers = struct { /// address: 0x40024020 /// I/O sampling control register - pub const IOSCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOSCR = @intToPtr(*volatile Mmio(32, packed struct { /// G1_IO1 sampling mode G1_IO1: u1, /// G1_IO2 sampling mode @@ -5825,7 +5825,7 @@ pub const registers = struct { /// address: 0x40024028 /// I/O channel control register - pub const IOCCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOCCR = @intToPtr(*volatile Mmio(32, packed struct { /// G1_IO1 channel mode G1_IO1: u1, /// G1_IO2 channel mode @@ -5895,7 +5895,7 @@ pub const registers = struct { /// address: 0x40024030 /// I/O group control status /// register - pub const IOGCSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOGCSR = @intToPtr(*volatile Mmio(32, packed struct { /// Analog I/O group x enable G1E: u1, /// Analog I/O group x enable @@ -5948,7 +5948,7 @@ pub const registers = struct { /// address: 0x40024034 /// I/O group x counter register - pub const IOG1CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG1CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -5973,7 +5973,7 @@ pub const registers = struct { /// address: 0x40024038 /// I/O group x counter register - pub const IOG2CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG2CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -5998,7 +5998,7 @@ pub const registers = struct { /// address: 0x4002403c /// I/O group x counter register - pub const IOG3CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG3CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6023,7 +6023,7 @@ pub const registers = struct { /// address: 0x40024040 /// I/O group x counter register - pub const IOG4CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG4CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6048,7 +6048,7 @@ pub const registers = struct { /// address: 0x40024044 /// I/O group x counter register - pub const IOG5CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG5CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6073,7 +6073,7 @@ pub const registers = struct { /// address: 0x40024048 /// I/O group x counter register - pub const IOG6CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG6CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6098,7 +6098,7 @@ pub const registers = struct { /// address: 0x4002404c /// I/O group x counter register - pub const IOG7CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG7CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6123,7 +6123,7 @@ pub const registers = struct { /// address: 0x40024050 /// I/O group x counter register - pub const IOG8CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IOG8CR = @intToPtr(*volatile Mmio(32, packed struct { /// Counter value CNT: u14, padding0: u1, @@ -6161,7 +6161,7 @@ pub const registers = struct { /// address: 0x40023008 /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// reset bit RESET: u1, reserved0: u1, @@ -6212,7 +6212,7 @@ pub const registers = struct { /// address: 0x40022000 /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { /// LATENCY LATENCY: u3, reserved0: u1, @@ -6250,7 +6250,7 @@ pub const registers = struct { /// address: 0x40022004 /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { /// Flash Key FKEYR: u32, }), base_address + 0x4); @@ -6261,7 +6261,7 @@ pub const registers = struct { /// address: 0x4002200c /// Flash status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Busy BSY: u1, reserved0: u1, @@ -6302,7 +6302,7 @@ pub const registers = struct { /// address: 0x40022010 /// Flash control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Programming PG: u1, /// Page erase @@ -6351,14 +6351,14 @@ pub const registers = struct { /// address: 0x40022014 /// Flash address register - pub const AR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AR = @intToPtr(*volatile Mmio(32, packed struct { /// Flash address FAR: u32, }), base_address + 0x14); /// address: 0x4002201c /// Option byte register - pub const OBR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OBR = @intToPtr(*volatile Mmio(32, packed struct { /// Option byte error OPTERR: u1, /// Level 1 protection status @@ -6392,7 +6392,7 @@ pub const registers = struct { /// address: 0x40022020 /// Write protection register - pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct { /// Write protect WRP: u32, }), base_address + 0x20); @@ -6403,7 +6403,7 @@ pub const registers = struct { /// address: 0x40021000 /// Clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Internal High Speed clock /// enable HSION: u1, @@ -6448,7 +6448,7 @@ pub const registers = struct { /// address: 0x40021004 /// Clock configuration register /// (RCC_CFGR) - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// System clock Switch SW: u2, /// System Clock Switch Status @@ -6488,7 +6488,7 @@ pub const registers = struct { /// address: 0x40021008 /// Clock interrupt register /// (RCC_CIR) - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { /// LSI Ready Interrupt flag LSIRDYF: u1, /// LSE Ready Interrupt flag @@ -6545,7 +6545,7 @@ pub const registers = struct { /// address: 0x4002100c /// APB2 peripheral reset register /// (RCC_APB2RSTR) - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { /// SYSCFG and COMP reset SYSCFGRST: u1, reserved0: u1, @@ -6591,7 +6591,7 @@ pub const registers = struct { /// address: 0x40021010 /// APB1 peripheral reset register /// (RCC_APB1RSTR) - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { /// Timer 2 reset TIM2RST: u1, /// Timer 3 reset @@ -6648,7 +6648,7 @@ pub const registers = struct { /// address: 0x40021014 /// AHB Peripheral Clock enable register /// (RCC_AHBENR) - pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA1 clock enable DMAEN: u1, /// DMA2 clock enable @@ -6705,7 +6705,7 @@ pub const registers = struct { /// address: 0x40021018 /// APB2 peripheral clock enable register /// (RCC_APB2ENR) - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { /// SYSCFG clock enable SYSCFGEN: u1, reserved0: u1, @@ -6751,7 +6751,7 @@ pub const registers = struct { /// address: 0x4002101c /// APB1 peripheral clock enable register /// (RCC_APB1ENR) - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { /// Timer 2 clock enable TIM2EN: u1, /// Timer 3 clock enable @@ -6812,7 +6812,7 @@ pub const registers = struct { /// address: 0x40021020 /// Backup domain control register /// (RCC_BDCR) - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { /// External Low Speed oscillator /// enable LSEON: u1, @@ -6860,7 +6860,7 @@ pub const registers = struct { /// address: 0x40021024 /// Control/status register /// (RCC_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Internal low speed oscillator /// enable LSION: u1, @@ -6911,7 +6911,7 @@ pub const registers = struct { /// address: 0x40021028 /// AHB peripheral reset register - pub const AHBRSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AHBRSTR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -6962,7 +6962,7 @@ pub const registers = struct { /// address: 0x4002102c /// Clock configuration register 2 - pub const CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR2 = @intToPtr(*volatile Mmio(32, packed struct { /// PREDIV division factor PREDIV: u4, /// ADC1 and ADC2 prescaler @@ -6991,7 +6991,7 @@ pub const registers = struct { /// address: 0x40021030 /// Clock configuration register 3 - pub const CFGR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR3 = @intToPtr(*volatile Mmio(32, packed struct { /// USART1 clock source /// selection USART1SW: u2, @@ -7048,7 +7048,7 @@ pub const registers = struct { /// address: 0x40020000 /// DMA interrupt status register /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// flag GIF1: u1, @@ -7142,7 +7142,7 @@ pub const registers = struct { /// address: 0x40020004 /// DMA interrupt flag clear register /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// clear CGIF1: u1, @@ -7236,7 +7236,7 @@ pub const registers = struct { /// address: 0x40020008 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7286,7 +7286,7 @@ pub const registers = struct { /// address: 0x4002000c /// DMA channel 1 number of data /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7310,7 +7310,7 @@ pub const registers = struct { /// address: 0x40020010 /// DMA channel 1 peripheral address /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x10); @@ -7318,7 +7318,7 @@ pub const registers = struct { /// address: 0x40020014 /// DMA channel 1 memory address /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x14); @@ -7326,7 +7326,7 @@ pub const registers = struct { /// address: 0x4002001c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7376,7 +7376,7 @@ pub const registers = struct { /// address: 0x40020020 /// DMA channel 2 number of data /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7400,7 +7400,7 @@ pub const registers = struct { /// address: 0x40020024 /// DMA channel 2 peripheral address /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x24); @@ -7408,7 +7408,7 @@ pub const registers = struct { /// address: 0x40020028 /// DMA channel 2 memory address /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x28); @@ -7416,7 +7416,7 @@ pub const registers = struct { /// address: 0x40020030 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7466,7 +7466,7 @@ pub const registers = struct { /// address: 0x40020034 /// DMA channel 3 number of data /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7490,7 +7490,7 @@ pub const registers = struct { /// address: 0x40020038 /// DMA channel 3 peripheral address /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x38); @@ -7498,7 +7498,7 @@ pub const registers = struct { /// address: 0x4002003c /// DMA channel 3 memory address /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x3c); @@ -7506,7 +7506,7 @@ pub const registers = struct { /// address: 0x40020044 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7556,7 +7556,7 @@ pub const registers = struct { /// address: 0x40020048 /// DMA channel 4 number of data /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7580,7 +7580,7 @@ pub const registers = struct { /// address: 0x4002004c /// DMA channel 4 peripheral address /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x4c); @@ -7588,7 +7588,7 @@ pub const registers = struct { /// address: 0x40020050 /// DMA channel 4 memory address /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x50); @@ -7596,7 +7596,7 @@ pub const registers = struct { /// address: 0x40020058 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7646,7 +7646,7 @@ pub const registers = struct { /// address: 0x4002005c /// DMA channel 5 number of data /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7670,7 +7670,7 @@ pub const registers = struct { /// address: 0x40020060 /// DMA channel 5 peripheral address /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x60); @@ -7678,7 +7678,7 @@ pub const registers = struct { /// address: 0x40020064 /// DMA channel 5 memory address /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x64); @@ -7686,7 +7686,7 @@ pub const registers = struct { /// address: 0x4002006c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7736,7 +7736,7 @@ pub const registers = struct { /// address: 0x40020070 /// DMA channel 6 number of data /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7760,7 +7760,7 @@ pub const registers = struct { /// address: 0x40020074 /// DMA channel 6 peripheral address /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x74); @@ -7768,7 +7768,7 @@ pub const registers = struct { /// address: 0x40020078 /// DMA channel 6 memory address /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x78); @@ -7776,7 +7776,7 @@ pub const registers = struct { /// address: 0x40020080 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -7826,7 +7826,7 @@ pub const registers = struct { /// address: 0x40020084 /// DMA channel 7 number of data /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -7850,7 +7850,7 @@ pub const registers = struct { /// address: 0x40020088 /// DMA channel 7 peripheral address /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x88); @@ -7858,7 +7858,7 @@ pub const registers = struct { /// address: 0x4002008c /// DMA channel 7 memory address /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x8c); @@ -7869,7 +7869,7 @@ pub const registers = struct { /// address: 0x40020400 /// DMA interrupt status register /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// flag GIF1: u1, @@ -7963,7 +7963,7 @@ pub const registers = struct { /// address: 0x40020404 /// DMA interrupt flag clear register /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel 1 Global interrupt /// clear CGIF1: u1, @@ -8057,7 +8057,7 @@ pub const registers = struct { /// address: 0x40020408 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8107,7 +8107,7 @@ pub const registers = struct { /// address: 0x4002040c /// DMA channel 1 number of data /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8131,7 +8131,7 @@ pub const registers = struct { /// address: 0x40020410 /// DMA channel 1 peripheral address /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x10); @@ -8139,7 +8139,7 @@ pub const registers = struct { /// address: 0x40020414 /// DMA channel 1 memory address /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x14); @@ -8147,7 +8147,7 @@ pub const registers = struct { /// address: 0x4002041c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8197,7 +8197,7 @@ pub const registers = struct { /// address: 0x40020420 /// DMA channel 2 number of data /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8221,7 +8221,7 @@ pub const registers = struct { /// address: 0x40020424 /// DMA channel 2 peripheral address /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x24); @@ -8229,7 +8229,7 @@ pub const registers = struct { /// address: 0x40020428 /// DMA channel 2 memory address /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x28); @@ -8237,7 +8237,7 @@ pub const registers = struct { /// address: 0x40020430 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8287,7 +8287,7 @@ pub const registers = struct { /// address: 0x40020434 /// DMA channel 3 number of data /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8311,7 +8311,7 @@ pub const registers = struct { /// address: 0x40020438 /// DMA channel 3 peripheral address /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x38); @@ -8319,7 +8319,7 @@ pub const registers = struct { /// address: 0x4002043c /// DMA channel 3 memory address /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x3c); @@ -8327,7 +8327,7 @@ pub const registers = struct { /// address: 0x40020444 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8377,7 +8377,7 @@ pub const registers = struct { /// address: 0x40020448 /// DMA channel 4 number of data /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8401,7 +8401,7 @@ pub const registers = struct { /// address: 0x4002044c /// DMA channel 4 peripheral address /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x4c); @@ -8409,7 +8409,7 @@ pub const registers = struct { /// address: 0x40020450 /// DMA channel 4 memory address /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x50); @@ -8417,7 +8417,7 @@ pub const registers = struct { /// address: 0x40020458 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8467,7 +8467,7 @@ pub const registers = struct { /// address: 0x4002045c /// DMA channel 5 number of data /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8491,7 +8491,7 @@ pub const registers = struct { /// address: 0x40020460 /// DMA channel 5 peripheral address /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x60); @@ -8499,7 +8499,7 @@ pub const registers = struct { /// address: 0x40020464 /// DMA channel 5 memory address /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x64); @@ -8507,7 +8507,7 @@ pub const registers = struct { /// address: 0x4002046c /// DMA channel configuration register /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8557,7 +8557,7 @@ pub const registers = struct { /// address: 0x40020470 /// DMA channel 6 number of data /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8581,7 +8581,7 @@ pub const registers = struct { /// address: 0x40020474 /// DMA channel 6 peripheral address /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x74); @@ -8589,7 +8589,7 @@ pub const registers = struct { /// address: 0x40020478 /// DMA channel 6 memory address /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x78); @@ -8597,7 +8597,7 @@ pub const registers = struct { /// address: 0x40020480 /// DMA channel configuration register /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Channel enable EN: u1, /// Transfer complete interrupt @@ -8647,7 +8647,7 @@ pub const registers = struct { /// address: 0x40020484 /// DMA channel 7 number of data /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Number of data to transfer NDT: u16, padding0: u1, @@ -8671,7 +8671,7 @@ pub const registers = struct { /// address: 0x40020488 /// DMA channel 7 peripheral address /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral address PA: u32, }), base_address + 0x88); @@ -8679,7 +8679,7 @@ pub const registers = struct { /// address: 0x4002048c /// DMA channel 7 memory address /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory address MA: u32, }), base_address + 0x8c); @@ -8690,7 +8690,7 @@ pub const registers = struct { /// address: 0x40000000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -8735,7 +8735,7 @@ pub const registers = struct { /// address: 0x40000004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -8774,7 +8774,7 @@ pub const registers = struct { /// address: 0x40000008 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -8812,7 +8812,7 @@ pub const registers = struct { /// address: 0x4000000c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -8869,7 +8869,7 @@ pub const registers = struct { /// address: 0x40000010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -8924,7 +8924,7 @@ pub const registers = struct { /// address: 0x40000014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -8972,7 +8972,7 @@ pub const registers = struct { /// address: 0x40000018 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9026,7 +9026,7 @@ pub const registers = struct { /// address: 0x40000018 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9062,7 +9062,7 @@ pub const registers = struct { /// address: 0x4000001c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9114,7 +9114,7 @@ pub const registers = struct { /// address: 0x4000001c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9150,7 +9150,7 @@ pub const registers = struct { /// address: 0x40000020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -9211,7 +9211,7 @@ pub const registers = struct { /// address: 0x40000024 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// Low counter value CNTL: u16, /// High counter value @@ -9228,7 +9228,7 @@ pub const registers = struct { /// address: 0x4000002c /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { /// Low Auto-reload value ARRL: u16, /// High Auto-reload value @@ -9237,7 +9237,7 @@ pub const registers = struct { /// address: 0x40000034 /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 1 /// value CCR1L: u16, @@ -9248,7 +9248,7 @@ pub const registers = struct { /// address: 0x40000038 /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 2 /// value CCR2L: u16, @@ -9259,7 +9259,7 @@ pub const registers = struct { /// address: 0x4000003c /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR3L: u16, /// High Capture/Compare value (on @@ -9269,7 +9269,7 @@ pub const registers = struct { /// address: 0x40000040 /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR4L: u16, /// High Capture/Compare value (on @@ -9279,7 +9279,7 @@ pub const registers = struct { /// address: 0x40000048 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -9310,7 +9310,7 @@ pub const registers = struct { /// address: 0x4000004c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -9337,7 +9337,7 @@ pub const registers = struct { /// address: 0x40000400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -9382,7 +9382,7 @@ pub const registers = struct { /// address: 0x40000404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -9421,7 +9421,7 @@ pub const registers = struct { /// address: 0x40000408 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -9459,7 +9459,7 @@ pub const registers = struct { /// address: 0x4000040c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -9516,7 +9516,7 @@ pub const registers = struct { /// address: 0x40000410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -9571,7 +9571,7 @@ pub const registers = struct { /// address: 0x40000414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -9619,7 +9619,7 @@ pub const registers = struct { /// address: 0x40000418 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9673,7 +9673,7 @@ pub const registers = struct { /// address: 0x40000418 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -9709,7 +9709,7 @@ pub const registers = struct { /// address: 0x4000041c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9761,7 +9761,7 @@ pub const registers = struct { /// address: 0x4000041c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -9797,7 +9797,7 @@ pub const registers = struct { /// address: 0x40000420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -9858,7 +9858,7 @@ pub const registers = struct { /// address: 0x40000424 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// Low counter value CNTL: u16, /// High counter value @@ -9875,7 +9875,7 @@ pub const registers = struct { /// address: 0x4000042c /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { /// Low Auto-reload value ARRL: u16, /// High Auto-reload value @@ -9884,7 +9884,7 @@ pub const registers = struct { /// address: 0x40000434 /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 1 /// value CCR1L: u16, @@ -9895,7 +9895,7 @@ pub const registers = struct { /// address: 0x40000438 /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 2 /// value CCR2L: u16, @@ -9906,7 +9906,7 @@ pub const registers = struct { /// address: 0x4000043c /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR3L: u16, /// High Capture/Compare value (on @@ -9916,7 +9916,7 @@ pub const registers = struct { /// address: 0x40000440 /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR4L: u16, /// High Capture/Compare value (on @@ -9926,7 +9926,7 @@ pub const registers = struct { /// address: 0x40000448 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -9957,7 +9957,7 @@ pub const registers = struct { /// address: 0x4000044c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -9984,7 +9984,7 @@ pub const registers = struct { /// address: 0x40000800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -10029,7 +10029,7 @@ pub const registers = struct { /// address: 0x40000804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -10068,7 +10068,7 @@ pub const registers = struct { /// address: 0x40000808 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -10106,7 +10106,7 @@ pub const registers = struct { /// address: 0x4000080c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -10163,7 +10163,7 @@ pub const registers = struct { /// address: 0x40000810 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -10218,7 +10218,7 @@ pub const registers = struct { /// address: 0x40000814 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -10266,7 +10266,7 @@ pub const registers = struct { /// address: 0x40000818 /// capture/compare mode register 1 (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10320,7 +10320,7 @@ pub const registers = struct { /// address: 0x40000818 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10356,7 +10356,7 @@ pub const registers = struct { /// address: 0x4000081c /// capture/compare mode register 2 (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -10408,7 +10408,7 @@ pub const registers = struct { /// address: 0x4000081c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -10444,7 +10444,7 @@ pub const registers = struct { /// address: 0x40000820 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -10505,7 +10505,7 @@ pub const registers = struct { /// address: 0x40000824 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// Low counter value CNTL: u16, /// High counter value @@ -10522,7 +10522,7 @@ pub const registers = struct { /// address: 0x4000082c /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { /// Low Auto-reload value ARRL: u16, /// High Auto-reload value @@ -10531,7 +10531,7 @@ pub const registers = struct { /// address: 0x40000834 /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 1 /// value CCR1L: u16, @@ -10542,7 +10542,7 @@ pub const registers = struct { /// address: 0x40000838 /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare 2 /// value CCR2L: u16, @@ -10553,7 +10553,7 @@ pub const registers = struct { /// address: 0x4000083c /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR3L: u16, /// High Capture/Compare value (on @@ -10563,7 +10563,7 @@ pub const registers = struct { /// address: 0x40000840 /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// Low Capture/Compare value CCR4L: u16, /// High Capture/Compare value (on @@ -10573,7 +10573,7 @@ pub const registers = struct { /// address: 0x40000848 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -10604,7 +10604,7 @@ pub const registers = struct { /// address: 0x4000084c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -10632,7 +10632,7 @@ pub const registers = struct { /// address: 0x40014000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -10675,7 +10675,7 @@ pub const registers = struct { /// address: 0x40014004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -10721,7 +10721,7 @@ pub const registers = struct { /// address: 0x40014008 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, reserved0: u1, @@ -10758,7 +10758,7 @@ pub const registers = struct { /// address: 0x4001400c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -10810,7 +10810,7 @@ pub const registers = struct { /// address: 0x40014010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -10859,7 +10859,7 @@ pub const registers = struct { /// address: 0x40014014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -10906,7 +10906,7 @@ pub const registers = struct { /// address: 0x40014018 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10956,7 +10956,7 @@ pub const registers = struct { /// address: 0x40014018 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -10992,7 +10992,7 @@ pub const registers = struct { /// address: 0x40014020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -11043,7 +11043,7 @@ pub const registers = struct { /// address: 0x40014024 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -11075,7 +11075,7 @@ pub const registers = struct { /// address: 0x40014030 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u8, padding0: u1, @@ -11114,7 +11114,7 @@ pub const registers = struct { /// address: 0x40014044 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -11151,7 +11151,7 @@ pub const registers = struct { /// address: 0x40014048 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -11182,7 +11182,7 @@ pub const registers = struct { /// address: 0x4001404c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -11210,7 +11210,7 @@ pub const registers = struct { /// address: 0x40014400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -11253,7 +11253,7 @@ pub const registers = struct { /// address: 0x40014404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -11298,7 +11298,7 @@ pub const registers = struct { /// address: 0x4001440c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -11346,7 +11346,7 @@ pub const registers = struct { /// address: 0x40014410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -11391,7 +11391,7 @@ pub const registers = struct { /// address: 0x40014414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -11436,7 +11436,7 @@ pub const registers = struct { /// address: 0x40014418 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11479,7 +11479,7 @@ pub const registers = struct { /// address: 0x40014418 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11516,7 +11516,7 @@ pub const registers = struct { /// address: 0x40014420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -11561,7 +11561,7 @@ pub const registers = struct { /// address: 0x40014424 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -11593,7 +11593,7 @@ pub const registers = struct { /// address: 0x40014430 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u8, padding0: u1, @@ -11628,7 +11628,7 @@ pub const registers = struct { /// address: 0x40014444 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -11665,7 +11665,7 @@ pub const registers = struct { /// address: 0x40014448 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -11696,7 +11696,7 @@ pub const registers = struct { /// address: 0x4001444c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -11728,7 +11728,7 @@ pub const registers = struct { /// address: 0x40014800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -11771,7 +11771,7 @@ pub const registers = struct { /// address: 0x40014804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -11816,7 +11816,7 @@ pub const registers = struct { /// address: 0x4001480c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -11864,7 +11864,7 @@ pub const registers = struct { /// address: 0x40014810 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -11909,7 +11909,7 @@ pub const registers = struct { /// address: 0x40014814 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -11954,7 +11954,7 @@ pub const registers = struct { /// address: 0x40014818 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -11997,7 +11997,7 @@ pub const registers = struct { /// address: 0x40014818 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -12034,7 +12034,7 @@ pub const registers = struct { /// address: 0x40014820 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -12079,7 +12079,7 @@ pub const registers = struct { /// address: 0x40014824 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -12111,7 +12111,7 @@ pub const registers = struct { /// address: 0x40014830 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u8, padding0: u1, @@ -12146,7 +12146,7 @@ pub const registers = struct { /// address: 0x40014844 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -12183,7 +12183,7 @@ pub const registers = struct { /// address: 0x40014848 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -12214,7 +12214,7 @@ pub const registers = struct { /// address: 0x4001484c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -12243,7 +12243,7 @@ pub const registers = struct { /// address: 0x40013800 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// USART enable UE: u1, /// USART enable in Stop mode @@ -12298,7 +12298,7 @@ pub const registers = struct { /// address: 0x40013804 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12350,7 +12350,7 @@ pub const registers = struct { /// address: 0x40013808 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -12408,7 +12408,7 @@ pub const registers = struct { /// address: 0x4001380c /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -12434,7 +12434,7 @@ pub const registers = struct { /// address: 0x40013810 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -12459,7 +12459,7 @@ pub const registers = struct { /// address: 0x40013814 /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { /// Receiver timeout value RTO: u24, /// Block Length @@ -12468,7 +12468,7 @@ pub const registers = struct { /// address: 0x40013818 /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { /// Auto baud rate request ABRRQ: u1, /// Send break request @@ -12512,7 +12512,7 @@ pub const registers = struct { /// address: 0x4001381c /// Interrupt & status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -12576,7 +12576,7 @@ pub const registers = struct { /// address: 0x40013820 /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error clear flag PECF: u1, /// Framing error clear flag @@ -12641,7 +12641,7 @@ pub const registers = struct { /// address: 0x40004400 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// USART enable UE: u1, /// USART enable in Stop mode @@ -12696,7 +12696,7 @@ pub const registers = struct { /// address: 0x40004404 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -12748,7 +12748,7 @@ pub const registers = struct { /// address: 0x40004408 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -12806,7 +12806,7 @@ pub const registers = struct { /// address: 0x4000440c /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -12832,7 +12832,7 @@ pub const registers = struct { /// address: 0x40004410 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -12857,7 +12857,7 @@ pub const registers = struct { /// address: 0x40004414 /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { /// Receiver timeout value RTO: u24, /// Block Length @@ -12866,7 +12866,7 @@ pub const registers = struct { /// address: 0x40004418 /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { /// Auto baud rate request ABRRQ: u1, /// Send break request @@ -12910,7 +12910,7 @@ pub const registers = struct { /// address: 0x4000441c /// Interrupt & status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -12974,7 +12974,7 @@ pub const registers = struct { /// address: 0x40004420 /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error clear flag PECF: u1, /// Framing error clear flag @@ -13039,7 +13039,7 @@ pub const registers = struct { /// address: 0x40004800 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// USART enable UE: u1, /// USART enable in Stop mode @@ -13094,7 +13094,7 @@ pub const registers = struct { /// address: 0x40004804 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13146,7 +13146,7 @@ pub const registers = struct { /// address: 0x40004808 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -13204,7 +13204,7 @@ pub const registers = struct { /// address: 0x4000480c /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -13230,7 +13230,7 @@ pub const registers = struct { /// address: 0x40004810 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -13255,7 +13255,7 @@ pub const registers = struct { /// address: 0x40004814 /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { /// Receiver timeout value RTO: u24, /// Block Length @@ -13264,7 +13264,7 @@ pub const registers = struct { /// address: 0x40004818 /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { /// Auto baud rate request ABRRQ: u1, /// Send break request @@ -13308,7 +13308,7 @@ pub const registers = struct { /// address: 0x4000481c /// Interrupt & status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -13372,7 +13372,7 @@ pub const registers = struct { /// address: 0x40004820 /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error clear flag PECF: u1, /// Framing error clear flag @@ -13437,7 +13437,7 @@ pub const registers = struct { /// address: 0x40004c00 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// USART enable UE: u1, /// USART enable in Stop mode @@ -13492,7 +13492,7 @@ pub const registers = struct { /// address: 0x40004c04 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13544,7 +13544,7 @@ pub const registers = struct { /// address: 0x40004c08 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -13602,7 +13602,7 @@ pub const registers = struct { /// address: 0x40004c0c /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -13628,7 +13628,7 @@ pub const registers = struct { /// address: 0x40004c10 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -13653,7 +13653,7 @@ pub const registers = struct { /// address: 0x40004c14 /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { /// Receiver timeout value RTO: u24, /// Block Length @@ -13662,7 +13662,7 @@ pub const registers = struct { /// address: 0x40004c18 /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { /// Auto baud rate request ABRRQ: u1, /// Send break request @@ -13706,7 +13706,7 @@ pub const registers = struct { /// address: 0x40004c1c /// Interrupt & status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -13770,7 +13770,7 @@ pub const registers = struct { /// address: 0x40004c20 /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error clear flag PECF: u1, /// Framing error clear flag @@ -13835,7 +13835,7 @@ pub const registers = struct { /// address: 0x40005000 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// USART enable UE: u1, /// USART enable in Stop mode @@ -13890,7 +13890,7 @@ pub const registers = struct { /// address: 0x40005004 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -13942,7 +13942,7 @@ pub const registers = struct { /// address: 0x40005008 /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { /// Error interrupt enable EIE: u1, /// IrDA mode enable @@ -14000,7 +14000,7 @@ pub const registers = struct { /// address: 0x4000500c /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { /// fraction of USARTDIV DIV_Fraction: u4, /// mantissa of USARTDIV @@ -14026,7 +14026,7 @@ pub const registers = struct { /// address: 0x40005010 /// Guard time and prescaler /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { /// Prescaler value PSC: u8, /// Guard time value @@ -14051,7 +14051,7 @@ pub const registers = struct { /// address: 0x40005014 /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { /// Receiver timeout value RTO: u24, /// Block Length @@ -14060,7 +14060,7 @@ pub const registers = struct { /// address: 0x40005018 /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { /// Auto baud rate request ABRRQ: u1, /// Send break request @@ -14104,7 +14104,7 @@ pub const registers = struct { /// address: 0x4000501c /// Interrupt & status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error PE: u1, /// Framing error @@ -14168,7 +14168,7 @@ pub const registers = struct { /// address: 0x40005020 /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { /// Parity error clear flag PECF: u1, /// Framing error clear flag @@ -14235,7 +14235,7 @@ pub const registers = struct { /// address: 0x40013000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -14287,7 +14287,7 @@ pub const registers = struct { /// address: 0x40013004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -14337,7 +14337,7 @@ pub const registers = struct { /// address: 0x40013008 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -14387,7 +14387,7 @@ pub const registers = struct { /// address: 0x40013010 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -14410,7 +14410,7 @@ pub const registers = struct { /// address: 0x40013014 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -14433,7 +14433,7 @@ pub const registers = struct { /// address: 0x40013018 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -14456,7 +14456,7 @@ pub const registers = struct { /// address: 0x4001301c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -14501,7 +14501,7 @@ pub const registers = struct { /// address: 0x40013020 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -14538,7 +14538,7 @@ pub const registers = struct { /// address: 0x40003800 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -14590,7 +14590,7 @@ pub const registers = struct { /// address: 0x40003804 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -14640,7 +14640,7 @@ pub const registers = struct { /// address: 0x40003808 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -14690,7 +14690,7 @@ pub const registers = struct { /// address: 0x40003810 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -14713,7 +14713,7 @@ pub const registers = struct { /// address: 0x40003814 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -14736,7 +14736,7 @@ pub const registers = struct { /// address: 0x40003818 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -14759,7 +14759,7 @@ pub const registers = struct { /// address: 0x4000381c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -14804,7 +14804,7 @@ pub const registers = struct { /// address: 0x40003820 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -14841,7 +14841,7 @@ pub const registers = struct { /// address: 0x40003c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -14893,7 +14893,7 @@ pub const registers = struct { /// address: 0x40003c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -14943,7 +14943,7 @@ pub const registers = struct { /// address: 0x40003c08 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -14993,7 +14993,7 @@ pub const registers = struct { /// address: 0x40003c10 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15016,7 +15016,7 @@ pub const registers = struct { /// address: 0x40003c14 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15039,7 +15039,7 @@ pub const registers = struct { /// address: 0x40003c18 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15062,7 +15062,7 @@ pub const registers = struct { /// address: 0x40003c1c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15107,7 +15107,7 @@ pub const registers = struct { /// address: 0x40003c20 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15144,7 +15144,7 @@ pub const registers = struct { /// address: 0x40003400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15196,7 +15196,7 @@ pub const registers = struct { /// address: 0x40003404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15246,7 +15246,7 @@ pub const registers = struct { /// address: 0x40003408 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15296,7 +15296,7 @@ pub const registers = struct { /// address: 0x40003410 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15319,7 +15319,7 @@ pub const registers = struct { /// address: 0x40003414 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15342,7 +15342,7 @@ pub const registers = struct { /// address: 0x40003418 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15365,7 +15365,7 @@ pub const registers = struct { /// address: 0x4000341c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15410,7 +15410,7 @@ pub const registers = struct { /// address: 0x40003420 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15447,7 +15447,7 @@ pub const registers = struct { /// address: 0x40004000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15499,7 +15499,7 @@ pub const registers = struct { /// address: 0x40004004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15549,7 +15549,7 @@ pub const registers = struct { /// address: 0x40004008 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15599,7 +15599,7 @@ pub const registers = struct { /// address: 0x40004010 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15622,7 +15622,7 @@ pub const registers = struct { /// address: 0x40004014 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15645,7 +15645,7 @@ pub const registers = struct { /// address: 0x40004018 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15668,7 +15668,7 @@ pub const registers = struct { /// address: 0x4000401c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -15713,7 +15713,7 @@ pub const registers = struct { /// address: 0x40004020 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -15750,7 +15750,7 @@ pub const registers = struct { /// address: 0x40013c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Clock phase CPHA: u1, /// Clock polarity @@ -15802,7 +15802,7 @@ pub const registers = struct { /// address: 0x40013c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rx buffer DMA enable RXDMAEN: u1, /// Tx buffer DMA enable @@ -15852,7 +15852,7 @@ pub const registers = struct { /// address: 0x40013c08 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Receive buffer not empty RXNE: u1, /// Transmit buffer empty @@ -15902,7 +15902,7 @@ pub const registers = struct { /// address: 0x40013c10 /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { /// CRC polynomial register CRCPOLY: u16, padding0: u1, @@ -15925,7 +15925,7 @@ pub const registers = struct { /// address: 0x40013c14 /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Rx CRC register RxCRC: u16, padding0: u1, @@ -15948,7 +15948,7 @@ pub const registers = struct { /// address: 0x40013c18 /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tx CRC register TxCRC: u16, padding0: u1, @@ -15971,7 +15971,7 @@ pub const registers = struct { /// address: 0x40013c1c /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { /// Channel length (number of bits per audio /// channel) CHLEN: u1, @@ -16016,7 +16016,7 @@ pub const registers = struct { /// address: 0x40013c20 /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { /// I2S Linear prescaler I2SDIV: u8, /// Odd factor for the @@ -16055,7 +16055,7 @@ pub const registers = struct { /// address: 0x40010400 /// Interrupt mask register - pub const IMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IMR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interrupt Mask on line 0 MR0: u1, /// Interrupt Mask on line 1 @@ -16124,7 +16124,7 @@ pub const registers = struct { /// address: 0x40010404 /// Event mask register - pub const EMR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EMR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Event Mask on line 0 MR0: u1, /// Event Mask on line 1 @@ -16194,7 +16194,7 @@ pub const registers = struct { /// address: 0x40010408 /// Rising Trigger selection /// register - pub const RTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTSR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Rising trigger event configuration of /// line 0 TR0: u1, @@ -16284,7 +16284,7 @@ pub const registers = struct { /// address: 0x4001040c /// Falling Trigger selection /// register - pub const FTSR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FTSR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Falling trigger event configuration of /// line 0 TR0: u1, @@ -16374,7 +16374,7 @@ pub const registers = struct { /// address: 0x40010410 /// Software interrupt event /// register - pub const SWIER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SWIER1 = @intToPtr(*volatile Mmio(32, packed struct { /// Software Interrupt on line /// 0 SWIER0: u1, @@ -16463,7 +16463,7 @@ pub const registers = struct { /// address: 0x40010414 /// Pending register - pub const PR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Pending bit 0 PR0: u1, /// Pending bit 1 @@ -16526,7 +16526,7 @@ pub const registers = struct { /// address: 0x40010418 /// Interrupt mask register - pub const IMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IMR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Interrupt Mask on external/internal line /// 32 MR32: u1, @@ -16571,7 +16571,7 @@ pub const registers = struct { /// address: 0x4001041c /// Event mask register - pub const EMR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EMR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Event mask on external/internal line /// 32 MR32: u1, @@ -16617,7 +16617,7 @@ pub const registers = struct { /// address: 0x40010420 /// Rising Trigger selection /// register - pub const RTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RTSR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Rising trigger event configuration bit /// of line 32 TR32: u1, @@ -16659,7 +16659,7 @@ pub const registers = struct { /// address: 0x40010424 /// Falling Trigger selection /// register - pub const FTSR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FTSR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Falling trigger event configuration bit /// of line 32 TR32: u1, @@ -16701,7 +16701,7 @@ pub const registers = struct { /// address: 0x40010428 /// Software interrupt event /// register - pub const SWIER2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SWIER2 = @intToPtr(*volatile Mmio(32, packed struct { /// Software interrupt on line /// 32 SWIER32: u1, @@ -16742,7 +16742,7 @@ pub const registers = struct { /// address: 0x4001042c /// Pending register - pub const PR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Pending bit on line 32 PR32: u1, /// Pending bit on line 33 @@ -16785,7 +16785,7 @@ pub const registers = struct { /// address: 0x40007000 /// power control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Low-power deep sleep LPDS: u1, /// Power down deepsleep @@ -16829,7 +16829,7 @@ pub const registers = struct { /// address: 0x40007004 /// power control/status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Wakeup flag WUF: u1, /// Standby flag @@ -16875,7 +16875,7 @@ pub const registers = struct { /// address: 0x40006400 /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { /// INRQ INRQ: u1, /// SLEEP @@ -16922,7 +16922,7 @@ pub const registers = struct { /// address: 0x40006404 /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { /// INAK INAK: u1, /// SLAK @@ -16968,7 +16968,7 @@ pub const registers = struct { /// address: 0x40006408 /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { /// RQCP0 RQCP0: u1, /// TXOK0 @@ -17032,7 +17032,7 @@ pub const registers = struct { /// address: 0x4000640c /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { /// FMP0 FMP0: u2, reserved0: u1, @@ -17072,7 +17072,7 @@ pub const registers = struct { /// address: 0x40006410 /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { /// FMP1 FMP1: u2, reserved0: u1, @@ -17112,7 +17112,7 @@ pub const registers = struct { /// address: 0x40006414 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// TMEIE TMEIE: u1, /// FMPIE0 @@ -17163,7 +17163,7 @@ pub const registers = struct { /// address: 0x40006418 /// error status register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { /// EWGF EWGF: u1, /// EPVF @@ -17190,7 +17190,7 @@ pub const registers = struct { /// address: 0x4000641c /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { /// BRP BRP: u10, reserved0: u1, @@ -17218,7 +17218,7 @@ pub const registers = struct { /// address: 0x40006580 /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -17234,7 +17234,7 @@ pub const registers = struct { /// address: 0x40006584 /// mailbox data length control and time stamp /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -17256,7 +17256,7 @@ pub const registers = struct { /// address: 0x40006588 /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -17269,7 +17269,7 @@ pub const registers = struct { /// address: 0x4000658c /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -17282,7 +17282,7 @@ pub const registers = struct { /// address: 0x40006590 /// TX mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -17298,7 +17298,7 @@ pub const registers = struct { /// address: 0x40006594 /// mailbox data length control and time stamp /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -17320,7 +17320,7 @@ pub const registers = struct { /// address: 0x40006598 /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -17333,7 +17333,7 @@ pub const registers = struct { /// address: 0x4000659c /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -17346,7 +17346,7 @@ pub const registers = struct { /// address: 0x400065a0 /// TX mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { /// TXRQ TXRQ: u1, /// RTR @@ -17362,7 +17362,7 @@ pub const registers = struct { /// address: 0x400065a4 /// mailbox data length control and time stamp /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -17384,7 +17384,7 @@ pub const registers = struct { /// address: 0x400065a8 /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -17397,7 +17397,7 @@ pub const registers = struct { /// address: 0x400065ac /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -17411,7 +17411,7 @@ pub const registers = struct { /// address: 0x400065b0 /// receive FIFO mailbox identifier /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// RTR RTR: u1, @@ -17426,7 +17426,7 @@ pub const registers = struct { /// address: 0x400065b4 /// receive FIFO mailbox data length control and /// time stamp register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -17442,7 +17442,7 @@ pub const registers = struct { /// address: 0x400065b8 /// receive FIFO mailbox data low /// register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -17456,7 +17456,7 @@ pub const registers = struct { /// address: 0x400065bc /// receive FIFO mailbox data high /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -17470,7 +17470,7 @@ pub const registers = struct { /// address: 0x400065c0 /// receive FIFO mailbox identifier /// register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// RTR RTR: u1, @@ -17485,7 +17485,7 @@ pub const registers = struct { /// address: 0x400065c4 /// receive FIFO mailbox data length control and /// time stamp register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { /// DLC DLC: u4, reserved0: u1, @@ -17501,7 +17501,7 @@ pub const registers = struct { /// address: 0x400065c8 /// receive FIFO mailbox data low /// register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA0 DATA0: u8, /// DATA1 @@ -17515,7 +17515,7 @@ pub const registers = struct { /// address: 0x400065cc /// receive FIFO mailbox data high /// register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { /// DATA4 DATA4: u8, /// DATA5 @@ -17528,7 +17528,7 @@ pub const registers = struct { /// address: 0x40006600 /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { /// Filter init mode FINIT: u1, reserved0: u1, @@ -17562,7 +17562,7 @@ pub const registers = struct { /// address: 0x40006604 /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter mode FBM0: u1, /// Filter mode @@ -17627,7 +17627,7 @@ pub const registers = struct { /// address: 0x4000660c /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter scale configuration FSC0: u1, /// Filter scale configuration @@ -17693,7 +17693,7 @@ pub const registers = struct { /// address: 0x40006614 /// filter FIFO assignment /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter FIFO assignment for filter /// 0 FFA0: u1, @@ -17786,7 +17786,7 @@ pub const registers = struct { /// address: 0x4000661c /// CAN filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { /// Filter active FACT0: u1, /// Filter active @@ -17851,7 +17851,7 @@ pub const registers = struct { /// address: 0x40006640 /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -17920,7 +17920,7 @@ pub const registers = struct { /// address: 0x40006644 /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -17989,7 +17989,7 @@ pub const registers = struct { /// address: 0x40006648 /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18058,7 +18058,7 @@ pub const registers = struct { /// address: 0x4000664c /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18127,7 +18127,7 @@ pub const registers = struct { /// address: 0x40006650 /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18196,7 +18196,7 @@ pub const registers = struct { /// address: 0x40006654 /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18265,7 +18265,7 @@ pub const registers = struct { /// address: 0x40006658 /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18334,7 +18334,7 @@ pub const registers = struct { /// address: 0x4000665c /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18403,7 +18403,7 @@ pub const registers = struct { /// address: 0x40006660 /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18472,7 +18472,7 @@ pub const registers = struct { /// address: 0x40006664 /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18541,7 +18541,7 @@ pub const registers = struct { /// address: 0x40006668 /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18610,7 +18610,7 @@ pub const registers = struct { /// address: 0x4000666c /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18679,7 +18679,7 @@ pub const registers = struct { /// address: 0x40006670 /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18748,7 +18748,7 @@ pub const registers = struct { /// address: 0x40006674 /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18817,7 +18817,7 @@ pub const registers = struct { /// address: 0x40006678 /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18886,7 +18886,7 @@ pub const registers = struct { /// address: 0x4000667c /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -18955,7 +18955,7 @@ pub const registers = struct { /// address: 0x40006680 /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19024,7 +19024,7 @@ pub const registers = struct { /// address: 0x40006684 /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19093,7 +19093,7 @@ pub const registers = struct { /// address: 0x40006688 /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19162,7 +19162,7 @@ pub const registers = struct { /// address: 0x4000668c /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19231,7 +19231,7 @@ pub const registers = struct { /// address: 0x40006690 /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19300,7 +19300,7 @@ pub const registers = struct { /// address: 0x40006694 /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19369,7 +19369,7 @@ pub const registers = struct { /// address: 0x40006698 /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19438,7 +19438,7 @@ pub const registers = struct { /// address: 0x4000669c /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19507,7 +19507,7 @@ pub const registers = struct { /// address: 0x400066a0 /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19576,7 +19576,7 @@ pub const registers = struct { /// address: 0x400066a4 /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19645,7 +19645,7 @@ pub const registers = struct { /// address: 0x400066a8 /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19714,7 +19714,7 @@ pub const registers = struct { /// address: 0x400066ac /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19783,7 +19783,7 @@ pub const registers = struct { /// address: 0x400066b0 /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19852,7 +19852,7 @@ pub const registers = struct { /// address: 0x400066b4 /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19921,7 +19921,7 @@ pub const registers = struct { /// address: 0x400066b8 /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -19990,7 +19990,7 @@ pub const registers = struct { /// address: 0x400066bc /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20059,7 +20059,7 @@ pub const registers = struct { /// address: 0x400066c0 /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20128,7 +20128,7 @@ pub const registers = struct { /// address: 0x400066c4 /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20197,7 +20197,7 @@ pub const registers = struct { /// address: 0x400066c8 /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20266,7 +20266,7 @@ pub const registers = struct { /// address: 0x400066cc /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20335,7 +20335,7 @@ pub const registers = struct { /// address: 0x400066d0 /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20404,7 +20404,7 @@ pub const registers = struct { /// address: 0x400066d4 /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20473,7 +20473,7 @@ pub const registers = struct { /// address: 0x400066d8 /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20542,7 +20542,7 @@ pub const registers = struct { /// address: 0x400066dc /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20611,7 +20611,7 @@ pub const registers = struct { /// address: 0x400066e0 /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20680,7 +20680,7 @@ pub const registers = struct { /// address: 0x400066e4 /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20749,7 +20749,7 @@ pub const registers = struct { /// address: 0x400066e8 /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20818,7 +20818,7 @@ pub const registers = struct { /// address: 0x400066ec /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20887,7 +20887,7 @@ pub const registers = struct { /// address: 0x400066f0 /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -20956,7 +20956,7 @@ pub const registers = struct { /// address: 0x400066f4 /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21025,7 +21025,7 @@ pub const registers = struct { /// address: 0x400066f8 /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21094,7 +21094,7 @@ pub const registers = struct { /// address: 0x400066fc /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21163,7 +21163,7 @@ pub const registers = struct { /// address: 0x40006700 /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21232,7 +21232,7 @@ pub const registers = struct { /// address: 0x40006704 /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21301,7 +21301,7 @@ pub const registers = struct { /// address: 0x40006708 /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21370,7 +21370,7 @@ pub const registers = struct { /// address: 0x4000670c /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21439,7 +21439,7 @@ pub const registers = struct { /// address: 0x40006710 /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21508,7 +21508,7 @@ pub const registers = struct { /// address: 0x40006714 /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21577,7 +21577,7 @@ pub const registers = struct { /// address: 0x40006718 /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21646,7 +21646,7 @@ pub const registers = struct { /// address: 0x4000671c /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { /// Filter bits FB0: u1, /// Filter bits @@ -21720,7 +21720,7 @@ pub const registers = struct { /// address: 0x40005c00 /// endpoint 0 register - pub const USB_EP0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP0R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -21768,7 +21768,7 @@ pub const registers = struct { /// address: 0x40005c04 /// endpoint 1 register - pub const USB_EP1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP1R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -21816,7 +21816,7 @@ pub const registers = struct { /// address: 0x40005c08 /// endpoint 2 register - pub const USB_EP2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP2R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -21864,7 +21864,7 @@ pub const registers = struct { /// address: 0x40005c0c /// endpoint 3 register - pub const USB_EP3R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP3R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -21912,7 +21912,7 @@ pub const registers = struct { /// address: 0x40005c10 /// endpoint 4 register - pub const USB_EP4R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP4R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -21960,7 +21960,7 @@ pub const registers = struct { /// address: 0x40005c14 /// endpoint 5 register - pub const USB_EP5R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP5R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -22008,7 +22008,7 @@ pub const registers = struct { /// address: 0x40005c18 /// endpoint 6 register - pub const USB_EP6R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP6R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -22056,7 +22056,7 @@ pub const registers = struct { /// address: 0x40005c1c /// endpoint 7 register - pub const USB_EP7R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_EP7R = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint address EA: u4, /// Status bits, for transmission @@ -22104,7 +22104,7 @@ pub const registers = struct { /// address: 0x40005c40 /// control register - pub const USB_CNTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const USB_CNTR = @intToPtr(*volatile Mmio(32, packed struct { /// Force USB Reset FRES: u1, /// Power down @@ -22159,7 +22159,7 @@ pub const registers = struct { /// address: 0x40005c44 /// interrupt status register - pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct { /// Endpoint Identifier EP_ID: u4, /// Direction of transaction @@ -22204,7 +22204,7 @@ pub const registers = struct { /// address: 0x40005c48 /// frame number register - pub const FNR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FNR = @intToPtr(*volatile Mmio(32, packed struct { /// Frame number FN: u11, /// Lost SOF @@ -22235,7 +22235,7 @@ pub const registers = struct { /// address: 0x40005c4c /// device address - pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct { /// Device address ADD: u1, /// Device address @@ -22288,7 +22288,7 @@ pub const registers = struct { /// address: 0x40005400 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral enable PE: u1, /// TX Interrupt enable @@ -22350,7 +22350,7 @@ pub const registers = struct { /// address: 0x40005404 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Slave address bit 0 (master /// mode) SADD0: u1, @@ -22395,7 +22395,7 @@ pub const registers = struct { /// address: 0x40005408 /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interface address OA1_0: u1, /// Interface address @@ -22430,7 +22430,7 @@ pub const registers = struct { /// address: 0x4000540c /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Interface address OA2: u7, @@ -22462,7 +22462,7 @@ pub const registers = struct { /// address: 0x40005410 /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { /// SCL low period (master /// mode) SCLL: u8, @@ -22483,7 +22483,7 @@ pub const registers = struct { /// address: 0x40005414 /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { /// Bus timeout A TIMEOUTA: u12, /// Idle clock timeout @@ -22505,7 +22505,7 @@ pub const registers = struct { /// address: 0x40005418 /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Transmit data register empty /// (transmitters) TXE: u1, @@ -22563,7 +22563,7 @@ pub const registers = struct { /// address: 0x4000541c /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -22612,7 +22612,7 @@ pub const registers = struct { /// address: 0x40005420 /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { /// Packet error checking /// register PEC: u8, @@ -22644,7 +22644,7 @@ pub const registers = struct { /// address: 0x40005424 /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit receive data RXDATA: u8, padding0: u1, @@ -22675,7 +22675,7 @@ pub const registers = struct { /// address: 0x40005428 /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit transmit data TXDATA: u8, padding0: u1, @@ -22709,7 +22709,7 @@ pub const registers = struct { /// address: 0x40005800 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral enable PE: u1, /// TX Interrupt enable @@ -22771,7 +22771,7 @@ pub const registers = struct { /// address: 0x40005804 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Slave address bit 0 (master /// mode) SADD0: u1, @@ -22816,7 +22816,7 @@ pub const registers = struct { /// address: 0x40005808 /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interface address OA1_0: u1, /// Interface address @@ -22851,7 +22851,7 @@ pub const registers = struct { /// address: 0x4000580c /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Interface address OA2: u7, @@ -22883,7 +22883,7 @@ pub const registers = struct { /// address: 0x40005810 /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { /// SCL low period (master /// mode) SCLL: u8, @@ -22904,7 +22904,7 @@ pub const registers = struct { /// address: 0x40005814 /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { /// Bus timeout A TIMEOUTA: u12, /// Idle clock timeout @@ -22926,7 +22926,7 @@ pub const registers = struct { /// address: 0x40005818 /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Transmit data register empty /// (transmitters) TXE: u1, @@ -22984,7 +22984,7 @@ pub const registers = struct { /// address: 0x4000581c /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -23033,7 +23033,7 @@ pub const registers = struct { /// address: 0x40005820 /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { /// Packet error checking /// register PEC: u8, @@ -23065,7 +23065,7 @@ pub const registers = struct { /// address: 0x40005824 /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit receive data RXDATA: u8, padding0: u1, @@ -23096,7 +23096,7 @@ pub const registers = struct { /// address: 0x40005828 /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit transmit data TXDATA: u8, padding0: u1, @@ -23130,7 +23130,7 @@ pub const registers = struct { /// address: 0x40007800 /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Peripheral enable PE: u1, /// TX Interrupt enable @@ -23192,7 +23192,7 @@ pub const registers = struct { /// address: 0x40007804 /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Slave address bit 0 (master /// mode) SADD0: u1, @@ -23237,7 +23237,7 @@ pub const registers = struct { /// address: 0x40007808 /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Interface address OA1_0: u1, /// Interface address @@ -23272,7 +23272,7 @@ pub const registers = struct { /// address: 0x4000780c /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Interface address OA2: u7, @@ -23304,7 +23304,7 @@ pub const registers = struct { /// address: 0x40007810 /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { /// SCL low period (master /// mode) SCLL: u8, @@ -23325,7 +23325,7 @@ pub const registers = struct { /// address: 0x40007814 /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { /// Bus timeout A TIMEOUTA: u12, /// Idle clock timeout @@ -23347,7 +23347,7 @@ pub const registers = struct { /// address: 0x40007818 /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Transmit data register empty /// (transmitters) TXE: u1, @@ -23405,7 +23405,7 @@ pub const registers = struct { /// address: 0x4000781c /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -23454,7 +23454,7 @@ pub const registers = struct { /// address: 0x40007820 /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { /// Packet error checking /// register PEC: u8, @@ -23486,7 +23486,7 @@ pub const registers = struct { /// address: 0x40007824 /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit receive data RXDATA: u8, padding0: u1, @@ -23517,7 +23517,7 @@ pub const registers = struct { /// address: 0x40007828 /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { /// 8-bit transmit data TXDATA: u8, padding0: u1, @@ -23552,7 +23552,7 @@ pub const registers = struct { /// address: 0x40003000 /// Key register - pub const KR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const KR = @intToPtr(*volatile Mmio(32, packed struct { /// Key value KEY: u16, padding0: u1, @@ -23579,7 +23579,7 @@ pub const registers = struct { /// address: 0x40003008 /// Reload register - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { /// Watchdog counter reload /// value RL: u12, @@ -23607,7 +23607,7 @@ pub const registers = struct { /// address: 0x4000300c /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Watchdog prescaler value /// update PVU: u1, @@ -23650,7 +23650,7 @@ pub const registers = struct { /// address: 0x40003010 /// Window register - pub const WINR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const WINR = @intToPtr(*volatile Mmio(32, packed struct { /// Watchdog counter window /// value WIN: u12, @@ -23682,7 +23682,7 @@ pub const registers = struct { /// address: 0x40002c00 /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// 7-bit counter T: u7, /// Activation bit @@ -23715,7 +23715,7 @@ pub const registers = struct { /// address: 0x40002c04 /// Configuration register - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { /// 7-bit window value W: u7, /// Timer base @@ -23748,7 +23748,7 @@ pub const registers = struct { /// address: 0x40002c08 /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Early wakeup interrupt /// flag EWIF: u1, @@ -23791,7 +23791,7 @@ pub const registers = struct { /// address: 0x40002800 /// time register - pub const TR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR = @intToPtr(*volatile Mmio(32, packed struct { /// Second units in BCD format SU: u4, /// Second tens in BCD format @@ -23821,7 +23821,7 @@ pub const registers = struct { /// address: 0x40002804 /// date register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// Date units in BCD format DU: u4, /// Date tens in BCD format @@ -23850,7 +23850,7 @@ pub const registers = struct { /// address: 0x40002808 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Wakeup clock selection WCKSEL: u3, /// Time-stamp event active @@ -23913,7 +23913,7 @@ pub const registers = struct { /// address: 0x4000280c /// initialization and status /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// Alarm A write flag ALRAWF: u1, /// Alarm B write flag @@ -23968,7 +23968,7 @@ pub const registers = struct { /// address: 0x40002810 /// prescaler register - pub const PRER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { /// Synchronous prescaler /// factor PREDIV_S: u15, @@ -23989,7 +23989,7 @@ pub const registers = struct { /// address: 0x40002814 /// wakeup timer register - pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { /// Wakeup auto-reload value /// bits WUT: u16, @@ -24013,7 +24013,7 @@ pub const registers = struct { /// address: 0x4000281c /// alarm A register - pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { /// Second units in BCD format SU: u4, /// Second tens in BCD format @@ -24047,7 +24047,7 @@ pub const registers = struct { /// address: 0x40002820 /// alarm B register - pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { /// Second units in BCD format SU: u4, /// Second tens in BCD format @@ -24081,7 +24081,7 @@ pub const registers = struct { /// address: 0x40002824 /// write protection register - pub const WPR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { /// Write protection key KEY: u8, padding0: u1, @@ -24112,7 +24112,7 @@ pub const registers = struct { /// address: 0x40002828 /// sub second register - pub const SSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { /// Sub second value SS: u16, padding0: u1, @@ -24135,7 +24135,7 @@ pub const registers = struct { /// address: 0x4000282c /// shift control register - pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { /// Subtract a fraction of a /// second SUBFS: u15, @@ -24161,7 +24161,7 @@ pub const registers = struct { /// address: 0x40002830 /// time stamp time register - pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { /// Second units in BCD format SU: u4, /// Second tens in BCD format @@ -24191,7 +24191,7 @@ pub const registers = struct { /// address: 0x40002834 /// time stamp date register - pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { /// Date units in BCD format DU: u4, /// Date tens in BCD format @@ -24224,7 +24224,7 @@ pub const registers = struct { /// address: 0x40002838 /// timestamp sub second register - pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { /// Sub second value SS: u16, padding0: u1, @@ -24247,7 +24247,7 @@ pub const registers = struct { /// address: 0x4000283c /// calibration register - pub const CALR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { /// Calibration minus CALM: u9, reserved0: u1, @@ -24284,7 +24284,7 @@ pub const registers = struct { /// address: 0x40002840 /// tamper and alternate function configuration /// register - pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { /// Tamper 1 detection enable TAMP1E: u1, /// Active level for tamper 1 @@ -24336,7 +24336,7 @@ pub const registers = struct { /// address: 0x40002844 /// alarm A sub second register - pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { /// Sub seconds value SS: u15, reserved0: u1, @@ -24359,7 +24359,7 @@ pub const registers = struct { /// address: 0x40002848 /// alarm B sub second register - pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { /// Sub seconds value SS: u15, reserved0: u1, @@ -24382,224 +24382,224 @@ pub const registers = struct { /// address: 0x40002850 /// backup register - pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x50); /// address: 0x40002854 /// backup register - pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x54); /// address: 0x40002858 /// backup register - pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x58); /// address: 0x4000285c /// backup register - pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x5c); /// address: 0x40002860 /// backup register - pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x60); /// address: 0x40002864 /// backup register - pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x64); /// address: 0x40002868 /// backup register - pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x68); /// address: 0x4000286c /// backup register - pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x6c); /// address: 0x40002870 /// backup register - pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x70); /// address: 0x40002874 /// backup register - pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x74); /// address: 0x40002878 /// backup register - pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x78); /// address: 0x4000287c /// backup register - pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x7c); /// address: 0x40002880 /// backup register - pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x80); /// address: 0x40002884 /// backup register - pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x84); /// address: 0x40002888 /// backup register - pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x88); /// address: 0x4000288c /// backup register - pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x8c); /// address: 0x40002890 /// backup register - pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x90); /// address: 0x40002894 /// backup register - pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x94); /// address: 0x40002898 /// backup register - pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x98); /// address: 0x4000289c /// backup register - pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0x9c); /// address: 0x400028a0 /// backup register - pub const BKP20R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP20R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xa0); /// address: 0x400028a4 /// backup register - pub const BKP21R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP21R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xa4); /// address: 0x400028a8 /// backup register - pub const BKP22R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP22R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xa8); /// address: 0x400028ac /// backup register - pub const BKP23R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP23R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xac); /// address: 0x400028b0 /// backup register - pub const BKP24R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP24R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xb0); /// address: 0x400028b4 /// backup register - pub const BKP25R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP25R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xb4); /// address: 0x400028b8 /// backup register - pub const BKP26R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP26R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xb8); /// address: 0x400028bc /// backup register - pub const BKP27R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP27R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xbc); /// address: 0x400028c0 /// backup register - pub const BKP28R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP28R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xc0); /// address: 0x400028c4 /// backup register - pub const BKP29R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP29R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xc4); /// address: 0x400028c8 /// backup register - pub const BKP30R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP30R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xc8); /// address: 0x400028cc /// backup register - pub const BKP31R = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BKP31R = @intToPtr(*volatile Mmio(32, packed struct { /// BKP BKP: u32, }), base_address + 0xcc); @@ -24610,7 +24610,7 @@ pub const registers = struct { /// address: 0x40001000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -24653,7 +24653,7 @@ pub const registers = struct { /// address: 0x40001004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -24689,7 +24689,7 @@ pub const registers = struct { /// address: 0x4000100c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, reserved0: u1, @@ -24728,7 +24728,7 @@ pub const registers = struct { /// address: 0x40001010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, padding0: u1, @@ -24766,7 +24766,7 @@ pub const registers = struct { /// address: 0x40001014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, padding0: u1, @@ -24804,7 +24804,7 @@ pub const registers = struct { /// address: 0x40001024 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// Low counter value CNT: u16, reserved0: u1, @@ -24839,7 +24839,7 @@ pub const registers = struct { /// address: 0x40001400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -24882,7 +24882,7 @@ pub const registers = struct { /// address: 0x40001404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -24918,7 +24918,7 @@ pub const registers = struct { /// address: 0x4000140c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, reserved0: u1, @@ -24957,7 +24957,7 @@ pub const registers = struct { /// address: 0x40001410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, padding0: u1, @@ -24995,7 +24995,7 @@ pub const registers = struct { /// address: 0x40001414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, padding0: u1, @@ -25033,7 +25033,7 @@ pub const registers = struct { /// address: 0x40001424 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// Low counter value CNT: u16, reserved0: u1, @@ -25069,7 +25069,7 @@ pub const registers = struct { /// address: 0x40007400 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 enable EN1: u1, /// DAC channel1 output buffer @@ -25122,7 +25122,7 @@ pub const registers = struct { /// address: 0x40007404 /// software trigger register - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 software /// trigger SWTRIG1: u1, @@ -25164,7 +25164,7 @@ pub const registers = struct { /// address: 0x40007408 /// channel1 12-bit right-aligned data holding /// register - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 12-bit right-aligned /// data DACC1DHR: u12, @@ -25193,7 +25193,7 @@ pub const registers = struct { /// address: 0x4000740c /// channel1 12-bit left aligned data holding /// register - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -25222,7 +25222,7 @@ pub const registers = struct { /// address: 0x40007410 /// channel1 8-bit right aligned data holding /// register - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 8-bit right-aligned /// data DACC1DHR: u8, @@ -25255,7 +25255,7 @@ pub const registers = struct { /// address: 0x40007414 /// channel2 12-bit right aligned data holding /// register - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 12-bit right-aligned /// data DACC2DHR: u12, @@ -25284,7 +25284,7 @@ pub const registers = struct { /// address: 0x40007418 /// channel2 12-bit left aligned data holding /// register - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -25313,7 +25313,7 @@ pub const registers = struct { /// address: 0x4000741c /// channel2 8-bit right-aligned data holding /// register - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 8-bit right-aligned /// data DACC2DHR: u8, @@ -25346,7 +25346,7 @@ pub const registers = struct { /// address: 0x40007420 /// Dual DAC 12-bit right-aligned data holding /// register - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 12-bit right-aligned /// data DACC1DHR: u12, @@ -25366,7 +25366,7 @@ pub const registers = struct { /// address: 0x40007424 /// DUAL DAC 12-bit left aligned data holding /// register - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -25386,7 +25386,7 @@ pub const registers = struct { /// address: 0x40007428 /// DUAL DAC 8-bit right aligned data holding /// register - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 8-bit right-aligned /// data DACC1DHR: u8, @@ -25413,7 +25413,7 @@ pub const registers = struct { /// address: 0x4000742c /// channel1 data output register - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel1 data output DACC1DOR: u12, padding0: u1, @@ -25440,7 +25440,7 @@ pub const registers = struct { /// address: 0x40007430 /// channel2 data output register - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { /// DAC channel2 data output DACC2DOR: u12, padding0: u1, @@ -25467,7 +25467,7 @@ pub const registers = struct { /// address: 0x40007434 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -25512,7 +25512,7 @@ pub const registers = struct { /// address: 0xe0042000 /// MCU Device ID Code Register - pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct { /// Device Identifier DEV_ID: u12, reserved0: u1, @@ -25526,7 +25526,7 @@ pub const registers = struct { /// address: 0xe0042004 /// Debug MCU Configuration /// Register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// Debug Sleep mode DBG_SLEEP: u1, /// Debug Stop Mode @@ -25569,7 +25569,7 @@ pub const registers = struct { /// address: 0xe0042008 /// APB Low Freeze Register - pub const APB1FZ = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB1FZ = @intToPtr(*volatile Mmio(32, packed struct { /// Debug Timer 2 stopped when Core is /// halted DBG_TIM2_STOP: u1, @@ -25638,7 +25638,7 @@ pub const registers = struct { /// address: 0xe004200c /// APB High Freeze Register - pub const APB2FZ = @intToPtr(*volatile Mmio(32, packed struct{ + pub const APB2FZ = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Debug Timer 15 stopped when Core is @@ -25687,7 +25687,7 @@ pub const registers = struct { /// address: 0x40012c00 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -25732,7 +25732,7 @@ pub const registers = struct { /// address: 0x40012c04 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -25782,7 +25782,7 @@ pub const registers = struct { /// address: 0x40012c08 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -25820,7 +25820,7 @@ pub const registers = struct { /// address: 0x40012c0c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -25880,7 +25880,7 @@ pub const registers = struct { /// address: 0x40012c10 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -25942,7 +25942,7 @@ pub const registers = struct { /// address: 0x40012c14 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -25994,7 +25994,7 @@ pub const registers = struct { /// address: 0x40012c18 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -26048,7 +26048,7 @@ pub const registers = struct { /// address: 0x40012c18 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -26084,7 +26084,7 @@ pub const registers = struct { /// address: 0x40012c1c /// capture/compare mode register (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -26138,7 +26138,7 @@ pub const registers = struct { /// address: 0x40012c1c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare 3 /// selection CC3S: u2, @@ -26174,7 +26174,7 @@ pub const registers = struct { /// address: 0x40012c20 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -26249,7 +26249,7 @@ pub const registers = struct { /// address: 0x40012c24 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -26281,7 +26281,7 @@ pub const registers = struct { /// address: 0x40012c30 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u16, padding0: u1, @@ -26320,7 +26320,7 @@ pub const registers = struct { /// address: 0x40012c44 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -26357,7 +26357,7 @@ pub const registers = struct { /// address: 0x40012c48 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -26388,7 +26388,7 @@ pub const registers = struct { /// address: 0x40012c4c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -26413,7 +26413,7 @@ pub const registers = struct { /// address: 0x40012c54 /// capture/compare mode register 3 (output /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Output compare 5 fast @@ -26464,7 +26464,7 @@ pub const registers = struct { /// address: 0x40012c58 /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 5 value CCR5: u16, reserved0: u1, @@ -26497,7 +26497,7 @@ pub const registers = struct { /// address: 0x40012c60 /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { /// TIM1_ETR_ADC1 remapping /// capability TIM1_ETR_ADC1_RMP: u2, @@ -26539,7 +26539,7 @@ pub const registers = struct { /// address: 0x40015000 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -26584,7 +26584,7 @@ pub const registers = struct { /// address: 0x40015004 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -26634,7 +26634,7 @@ pub const registers = struct { /// address: 0x40015008 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -26672,7 +26672,7 @@ pub const registers = struct { /// address: 0x4001500c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -26732,7 +26732,7 @@ pub const registers = struct { /// address: 0x40015010 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -26794,7 +26794,7 @@ pub const registers = struct { /// address: 0x40015014 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -26846,7 +26846,7 @@ pub const registers = struct { /// address: 0x40015018 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -26900,7 +26900,7 @@ pub const registers = struct { /// address: 0x40015018 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -26936,7 +26936,7 @@ pub const registers = struct { /// address: 0x4001501c /// capture/compare mode register (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -26990,7 +26990,7 @@ pub const registers = struct { /// address: 0x4001501c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare 3 /// selection CC3S: u2, @@ -27026,7 +27026,7 @@ pub const registers = struct { /// address: 0x40015020 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -27101,7 +27101,7 @@ pub const registers = struct { /// address: 0x40015024 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -27133,7 +27133,7 @@ pub const registers = struct { /// address: 0x40015030 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u16, padding0: u1, @@ -27172,7 +27172,7 @@ pub const registers = struct { /// address: 0x40015044 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -27209,7 +27209,7 @@ pub const registers = struct { /// address: 0x40015048 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -27240,7 +27240,7 @@ pub const registers = struct { /// address: 0x4001504c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -27265,7 +27265,7 @@ pub const registers = struct { /// address: 0x40015054 /// capture/compare mode register 3 (output /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Output compare 5 fast @@ -27316,7 +27316,7 @@ pub const registers = struct { /// address: 0x40015058 /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 5 value CCR5: u16, reserved0: u1, @@ -27349,7 +27349,7 @@ pub const registers = struct { /// address: 0x40015060 /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { /// TIM1_ETR_ADC1 remapping /// capability TIM1_ETR_ADC1_RMP: u2, @@ -27392,7 +27392,7 @@ pub const registers = struct { /// address: 0x40013400 /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable CEN: u1, /// Update disable @@ -27437,7 +27437,7 @@ pub const registers = struct { /// address: 0x40013404 /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare preloaded /// control CCPC: u1, @@ -27487,7 +27487,7 @@ pub const registers = struct { /// address: 0x40013408 /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { /// Slave mode selection SMS: u3, /// OCREF clear selection @@ -27525,7 +27525,7 @@ pub const registers = struct { /// address: 0x4001340c /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt enable UIE: u1, /// Capture/Compare 1 interrupt @@ -27585,7 +27585,7 @@ pub const registers = struct { /// address: 0x40013410 /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { /// Update interrupt flag UIF: u1, /// Capture/compare 1 interrupt @@ -27647,7 +27647,7 @@ pub const registers = struct { /// address: 0x40013414 /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { /// Update generation UG: u1, /// Capture/compare 1 @@ -27699,7 +27699,7 @@ pub const registers = struct { /// address: 0x40013418 /// capture/compare mode register (output /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -27753,7 +27753,7 @@ pub const registers = struct { /// address: 0x40013418 /// capture/compare mode register 1 (input /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 /// selection CC1S: u2, @@ -27789,7 +27789,7 @@ pub const registers = struct { /// address: 0x4001341c /// capture/compare mode register (output /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 3 /// selection CC3S: u2, @@ -27843,7 +27843,7 @@ pub const registers = struct { /// address: 0x4001341c /// capture/compare mode register 2 (input /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/compare 3 /// selection CC3S: u2, @@ -27879,7 +27879,7 @@ pub const registers = struct { /// address: 0x40013420 /// capture/compare enable /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 1 output /// enable CC1E: u1, @@ -27954,7 +27954,7 @@ pub const registers = struct { /// address: 0x40013424 /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { /// counter value CNT: u16, reserved0: u1, @@ -27986,7 +27986,7 @@ pub const registers = struct { /// address: 0x40013430 /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { /// Repetition counter value REP: u16, padding0: u1, @@ -28025,7 +28025,7 @@ pub const registers = struct { /// address: 0x40013444 /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { /// Dead-time generator setup DTG: u8, /// Lock configuration @@ -28062,7 +28062,7 @@ pub const registers = struct { /// address: 0x40013448 /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA base address DBA: u5, reserved0: u1, @@ -28093,7 +28093,7 @@ pub const registers = struct { /// address: 0x4001344c /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { /// DMA register for burst /// accesses DMAB: u16, @@ -28118,7 +28118,7 @@ pub const registers = struct { /// address: 0x40013454 /// capture/compare mode register 3 (output /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, /// Output compare 5 fast @@ -28169,7 +28169,7 @@ pub const registers = struct { /// address: 0x40013458 /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { /// Capture/Compare 5 value CCR5: u16, reserved0: u1, @@ -28202,7 +28202,7 @@ pub const registers = struct { /// address: 0x40013460 /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { /// TIM8_ETR_ADC2 remapping /// capability TIM8_ETR_ADC2_RMP: u2, @@ -28245,7 +28245,7 @@ pub const registers = struct { /// address: 0x50000000 /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDY ADRDY: u1, /// EOSMP @@ -28293,7 +28293,7 @@ pub const registers = struct { /// address: 0x50000004 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDYIE ADRDYIE: u1, /// EOSMPIE @@ -28341,7 +28341,7 @@ pub const registers = struct { /// address: 0x50000008 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// ADEN ADEN: u1, /// ADDIS @@ -28388,7 +28388,7 @@ pub const registers = struct { /// address: 0x5000000c /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// DMAEN DMAEN: u1, /// DMACFG @@ -28433,7 +28433,7 @@ pub const registers = struct { /// address: 0x50000014 /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -28461,7 +28461,7 @@ pub const registers = struct { /// address: 0x50000018 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SMP10 SMP10: u3, /// SMP11 @@ -28489,7 +28489,7 @@ pub const registers = struct { /// address: 0x50000020 /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { /// LT1 LT1: u12, reserved0: u1, @@ -28506,7 +28506,7 @@ pub const registers = struct { /// address: 0x50000024 /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { /// LT2 LT2: u8, reserved0: u1, @@ -28531,7 +28531,7 @@ pub const registers = struct { /// address: 0x50000028 /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { /// LT3 LT3: u8, reserved0: u1, @@ -28556,7 +28556,7 @@ pub const registers = struct { /// address: 0x50000030 /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// L3 L3: u4, reserved0: u1, @@ -28579,7 +28579,7 @@ pub const registers = struct { /// address: 0x50000034 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ5 SQ5: u5, reserved0: u1, @@ -28601,7 +28601,7 @@ pub const registers = struct { /// address: 0x50000038 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ10 SQ10: u5, reserved0: u1, @@ -28623,7 +28623,7 @@ pub const registers = struct { /// address: 0x5000003c /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ15 SQ15: u5, reserved0: u1, @@ -28654,7 +28654,7 @@ pub const registers = struct { /// address: 0x50000040 /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// regularDATA regularDATA: u16, padding0: u1, @@ -28677,7 +28677,7 @@ pub const registers = struct { /// address: 0x5000004c /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// JL JL: u2, /// JEXTSEL @@ -28700,7 +28700,7 @@ pub const registers = struct { /// address: 0x50000060 /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET1 OFFSET1: u12, reserved0: u1, @@ -28725,7 +28725,7 @@ pub const registers = struct { /// address: 0x50000064 /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET2 OFFSET2: u12, reserved0: u1, @@ -28750,7 +28750,7 @@ pub const registers = struct { /// address: 0x50000068 /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET3 OFFSET3: u12, reserved0: u1, @@ -28775,7 +28775,7 @@ pub const registers = struct { /// address: 0x5000006c /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET4 OFFSET4: u12, reserved0: u1, @@ -28800,7 +28800,7 @@ pub const registers = struct { /// address: 0x50000080 /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA1 JDATA1: u16, padding0: u1, @@ -28823,7 +28823,7 @@ pub const registers = struct { /// address: 0x50000084 /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA2 JDATA2: u16, padding0: u1, @@ -28846,7 +28846,7 @@ pub const registers = struct { /// address: 0x50000088 /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA3 JDATA3: u16, padding0: u1, @@ -28869,7 +28869,7 @@ pub const registers = struct { /// address: 0x5000008c /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA4 JDATA4: u16, padding0: u1, @@ -28893,7 +28893,7 @@ pub const registers = struct { /// address: 0x500000a0 /// Analog Watchdog 2 Configuration /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD2CH AWD2CH: u18, @@ -28915,7 +28915,7 @@ pub const registers = struct { /// address: 0x500000a4 /// Analog Watchdog 3 Configuration /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD3CH AWD3CH: u18, @@ -28937,7 +28937,7 @@ pub const registers = struct { /// address: 0x500000b0 /// Differential Mode Selection Register /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Differential mode for channels 15 to /// 1 @@ -28962,7 +28962,7 @@ pub const registers = struct { /// address: 0x500000b4 /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { /// CALFACT_S CALFACT_S: u7, reserved0: u1, @@ -28992,7 +28992,7 @@ pub const registers = struct { /// address: 0x50000100 /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDY ADRDY: u1, /// EOSMP @@ -29040,7 +29040,7 @@ pub const registers = struct { /// address: 0x50000104 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDYIE ADRDYIE: u1, /// EOSMPIE @@ -29088,7 +29088,7 @@ pub const registers = struct { /// address: 0x50000108 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// ADEN ADEN: u1, /// ADDIS @@ -29135,7 +29135,7 @@ pub const registers = struct { /// address: 0x5000010c /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// DMAEN DMAEN: u1, /// DMACFG @@ -29180,7 +29180,7 @@ pub const registers = struct { /// address: 0x50000114 /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -29208,7 +29208,7 @@ pub const registers = struct { /// address: 0x50000118 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SMP10 SMP10: u3, /// SMP11 @@ -29236,7 +29236,7 @@ pub const registers = struct { /// address: 0x50000120 /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { /// LT1 LT1: u12, reserved0: u1, @@ -29253,7 +29253,7 @@ pub const registers = struct { /// address: 0x50000124 /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { /// LT2 LT2: u8, reserved0: u1, @@ -29278,7 +29278,7 @@ pub const registers = struct { /// address: 0x50000128 /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { /// LT3 LT3: u8, reserved0: u1, @@ -29303,7 +29303,7 @@ pub const registers = struct { /// address: 0x50000130 /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// L3 L3: u4, reserved0: u1, @@ -29326,7 +29326,7 @@ pub const registers = struct { /// address: 0x50000134 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ5 SQ5: u5, reserved0: u1, @@ -29348,7 +29348,7 @@ pub const registers = struct { /// address: 0x50000138 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ10 SQ10: u5, reserved0: u1, @@ -29370,7 +29370,7 @@ pub const registers = struct { /// address: 0x5000013c /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ15 SQ15: u5, reserved0: u1, @@ -29401,7 +29401,7 @@ pub const registers = struct { /// address: 0x50000140 /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// regularDATA regularDATA: u16, padding0: u1, @@ -29424,7 +29424,7 @@ pub const registers = struct { /// address: 0x5000014c /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// JL JL: u2, /// JEXTSEL @@ -29447,7 +29447,7 @@ pub const registers = struct { /// address: 0x50000160 /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET1 OFFSET1: u12, reserved0: u1, @@ -29472,7 +29472,7 @@ pub const registers = struct { /// address: 0x50000164 /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET2 OFFSET2: u12, reserved0: u1, @@ -29497,7 +29497,7 @@ pub const registers = struct { /// address: 0x50000168 /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET3 OFFSET3: u12, reserved0: u1, @@ -29522,7 +29522,7 @@ pub const registers = struct { /// address: 0x5000016c /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET4 OFFSET4: u12, reserved0: u1, @@ -29547,7 +29547,7 @@ pub const registers = struct { /// address: 0x50000180 /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA1 JDATA1: u16, padding0: u1, @@ -29570,7 +29570,7 @@ pub const registers = struct { /// address: 0x50000184 /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA2 JDATA2: u16, padding0: u1, @@ -29593,7 +29593,7 @@ pub const registers = struct { /// address: 0x50000188 /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA3 JDATA3: u16, padding0: u1, @@ -29616,7 +29616,7 @@ pub const registers = struct { /// address: 0x5000018c /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA4 JDATA4: u16, padding0: u1, @@ -29640,7 +29640,7 @@ pub const registers = struct { /// address: 0x500001a0 /// Analog Watchdog 2 Configuration /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD2CH AWD2CH: u18, @@ -29662,7 +29662,7 @@ pub const registers = struct { /// address: 0x500001a4 /// Analog Watchdog 3 Configuration /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD3CH AWD3CH: u18, @@ -29684,7 +29684,7 @@ pub const registers = struct { /// address: 0x500001b0 /// Differential Mode Selection Register /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Differential mode for channels 15 to /// 1 @@ -29709,7 +29709,7 @@ pub const registers = struct { /// address: 0x500001b4 /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { /// CALFACT_S CALFACT_S: u7, reserved0: u1, @@ -29739,7 +29739,7 @@ pub const registers = struct { /// address: 0x50000400 /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDY ADRDY: u1, /// EOSMP @@ -29787,7 +29787,7 @@ pub const registers = struct { /// address: 0x50000404 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDYIE ADRDYIE: u1, /// EOSMPIE @@ -29835,7 +29835,7 @@ pub const registers = struct { /// address: 0x50000408 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// ADEN ADEN: u1, /// ADDIS @@ -29882,7 +29882,7 @@ pub const registers = struct { /// address: 0x5000040c /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// DMAEN DMAEN: u1, /// DMACFG @@ -29927,7 +29927,7 @@ pub const registers = struct { /// address: 0x50000414 /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -29955,7 +29955,7 @@ pub const registers = struct { /// address: 0x50000418 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SMP10 SMP10: u3, /// SMP11 @@ -29983,7 +29983,7 @@ pub const registers = struct { /// address: 0x50000420 /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { /// LT1 LT1: u12, reserved0: u1, @@ -30000,7 +30000,7 @@ pub const registers = struct { /// address: 0x50000424 /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { /// LT2 LT2: u8, reserved0: u1, @@ -30025,7 +30025,7 @@ pub const registers = struct { /// address: 0x50000428 /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { /// LT3 LT3: u8, reserved0: u1, @@ -30050,7 +30050,7 @@ pub const registers = struct { /// address: 0x50000430 /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// L3 L3: u4, reserved0: u1, @@ -30073,7 +30073,7 @@ pub const registers = struct { /// address: 0x50000434 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ5 SQ5: u5, reserved0: u1, @@ -30095,7 +30095,7 @@ pub const registers = struct { /// address: 0x50000438 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ10 SQ10: u5, reserved0: u1, @@ -30117,7 +30117,7 @@ pub const registers = struct { /// address: 0x5000043c /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ15 SQ15: u5, reserved0: u1, @@ -30148,7 +30148,7 @@ pub const registers = struct { /// address: 0x50000440 /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// regularDATA regularDATA: u16, padding0: u1, @@ -30171,7 +30171,7 @@ pub const registers = struct { /// address: 0x5000044c /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// JL JL: u2, /// JEXTSEL @@ -30194,7 +30194,7 @@ pub const registers = struct { /// address: 0x50000460 /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET1 OFFSET1: u12, reserved0: u1, @@ -30219,7 +30219,7 @@ pub const registers = struct { /// address: 0x50000464 /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET2 OFFSET2: u12, reserved0: u1, @@ -30244,7 +30244,7 @@ pub const registers = struct { /// address: 0x50000468 /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET3 OFFSET3: u12, reserved0: u1, @@ -30269,7 +30269,7 @@ pub const registers = struct { /// address: 0x5000046c /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET4 OFFSET4: u12, reserved0: u1, @@ -30294,7 +30294,7 @@ pub const registers = struct { /// address: 0x50000480 /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA1 JDATA1: u16, padding0: u1, @@ -30317,7 +30317,7 @@ pub const registers = struct { /// address: 0x50000484 /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA2 JDATA2: u16, padding0: u1, @@ -30340,7 +30340,7 @@ pub const registers = struct { /// address: 0x50000488 /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA3 JDATA3: u16, padding0: u1, @@ -30363,7 +30363,7 @@ pub const registers = struct { /// address: 0x5000048c /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA4 JDATA4: u16, padding0: u1, @@ -30387,7 +30387,7 @@ pub const registers = struct { /// address: 0x500004a0 /// Analog Watchdog 2 Configuration /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD2CH AWD2CH: u18, @@ -30409,7 +30409,7 @@ pub const registers = struct { /// address: 0x500004a4 /// Analog Watchdog 3 Configuration /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD3CH AWD3CH: u18, @@ -30431,7 +30431,7 @@ pub const registers = struct { /// address: 0x500004b0 /// Differential Mode Selection Register /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Differential mode for channels 15 to /// 1 @@ -30456,7 +30456,7 @@ pub const registers = struct { /// address: 0x500004b4 /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { /// CALFACT_S CALFACT_S: u7, reserved0: u1, @@ -30486,7 +30486,7 @@ pub const registers = struct { /// address: 0x50000500 /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDY ADRDY: u1, /// EOSMP @@ -30534,7 +30534,7 @@ pub const registers = struct { /// address: 0x50000504 /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { /// ADRDYIE ADRDYIE: u1, /// EOSMPIE @@ -30582,7 +30582,7 @@ pub const registers = struct { /// address: 0x50000508 /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { /// ADEN ADEN: u1, /// ADDIS @@ -30629,7 +30629,7 @@ pub const registers = struct { /// address: 0x5000050c /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { /// DMAEN DMAEN: u1, /// DMACFG @@ -30674,7 +30674,7 @@ pub const registers = struct { /// address: 0x50000514 /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -30702,7 +30702,7 @@ pub const registers = struct { /// address: 0x50000518 /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SMP10 SMP10: u3, /// SMP11 @@ -30730,7 +30730,7 @@ pub const registers = struct { /// address: 0x50000520 /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { /// LT1 LT1: u12, reserved0: u1, @@ -30747,7 +30747,7 @@ pub const registers = struct { /// address: 0x50000524 /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { /// LT2 LT2: u8, reserved0: u1, @@ -30772,7 +30772,7 @@ pub const registers = struct { /// address: 0x50000528 /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { /// LT3 LT3: u8, reserved0: u1, @@ -30797,7 +30797,7 @@ pub const registers = struct { /// address: 0x50000530 /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { /// L3 L3: u4, reserved0: u1, @@ -30820,7 +30820,7 @@ pub const registers = struct { /// address: 0x50000534 /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ5 SQ5: u5, reserved0: u1, @@ -30842,7 +30842,7 @@ pub const registers = struct { /// address: 0x50000538 /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ10 SQ10: u5, reserved0: u1, @@ -30864,7 +30864,7 @@ pub const registers = struct { /// address: 0x5000053c /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { /// SQ15 SQ15: u5, reserved0: u1, @@ -30895,7 +30895,7 @@ pub const registers = struct { /// address: 0x50000540 /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { /// regularDATA regularDATA: u16, padding0: u1, @@ -30918,7 +30918,7 @@ pub const registers = struct { /// address: 0x5000054c /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { /// JL JL: u2, /// JEXTSEL @@ -30941,7 +30941,7 @@ pub const registers = struct { /// address: 0x50000560 /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET1 OFFSET1: u12, reserved0: u1, @@ -30966,7 +30966,7 @@ pub const registers = struct { /// address: 0x50000564 /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET2 OFFSET2: u12, reserved0: u1, @@ -30991,7 +30991,7 @@ pub const registers = struct { /// address: 0x50000568 /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET3 OFFSET3: u12, reserved0: u1, @@ -31016,7 +31016,7 @@ pub const registers = struct { /// address: 0x5000056c /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { /// OFFSET4 OFFSET4: u12, reserved0: u1, @@ -31041,7 +31041,7 @@ pub const registers = struct { /// address: 0x50000580 /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA1 JDATA1: u16, padding0: u1, @@ -31064,7 +31064,7 @@ pub const registers = struct { /// address: 0x50000584 /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA2 JDATA2: u16, padding0: u1, @@ -31087,7 +31087,7 @@ pub const registers = struct { /// address: 0x50000588 /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA3 JDATA3: u16, padding0: u1, @@ -31110,7 +31110,7 @@ pub const registers = struct { /// address: 0x5000058c /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { /// JDATA4 JDATA4: u16, padding0: u1, @@ -31134,7 +31134,7 @@ pub const registers = struct { /// address: 0x500005a0 /// Analog Watchdog 2 Configuration /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD2CH AWD2CH: u18, @@ -31156,7 +31156,7 @@ pub const registers = struct { /// address: 0x500005a4 /// Analog Watchdog 3 Configuration /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// AWD3CH AWD3CH: u18, @@ -31178,7 +31178,7 @@ pub const registers = struct { /// address: 0x500005b0 /// Differential Mode Selection Register /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Differential mode for channels 15 to /// 1 @@ -31203,7 +31203,7 @@ pub const registers = struct { /// address: 0x500005b4 /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { /// CALFACT_S CALFACT_S: u7, reserved0: u1, @@ -31234,7 +31234,7 @@ pub const registers = struct { /// address: 0x50000300 /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// ADDRDY_MST ADDRDY_MST: u1, /// EOSMP_MST @@ -31302,7 +31302,7 @@ pub const registers = struct { /// address: 0x50000308 /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { /// Multi ADC mode selection MULT: u5, reserved0: u1, @@ -31342,7 +31342,7 @@ pub const registers = struct { /// address: 0x5000030c /// ADC common regular data register for dual /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { /// Regular data of the master /// ADC RDATA_MST: u16, @@ -31356,7 +31356,7 @@ pub const registers = struct { /// address: 0x50000700 /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { /// ADDRDY_MST ADDRDY_MST: u1, /// EOSMP_MST @@ -31424,7 +31424,7 @@ pub const registers = struct { /// address: 0x50000708 /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { /// Multi ADC mode selection MULT: u5, reserved0: u1, @@ -31464,7 +31464,7 @@ pub const registers = struct { /// address: 0x5000070c /// ADC common regular data register for dual /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { /// Regular data of the master /// ADC RDATA_MST: u16, @@ -31480,7 +31480,7 @@ pub const registers = struct { /// address: 0x40010000 /// configuration register 1 - pub const SYSCFG_CFGR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_CFGR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Memory mapping selection /// bits MEM_MODE: u2, @@ -31539,7 +31539,7 @@ pub const registers = struct { /// address: 0x40010008 /// external interrupt configuration register /// 1 - pub const SYSCFG_EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI 0 configuration bits EXTI0: u4, /// EXTI 1 configuration bits @@ -31569,7 +31569,7 @@ pub const registers = struct { /// address: 0x4001000c /// external interrupt configuration register /// 2 - pub const SYSCFG_EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI 4 configuration bits EXTI4: u4, /// EXTI 5 configuration bits @@ -31599,7 +31599,7 @@ pub const registers = struct { /// address: 0x40010010 /// external interrupt configuration register /// 3 - pub const SYSCFG_EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI 8 configuration bits EXTI8: u4, /// EXTI 9 configuration bits @@ -31629,7 +31629,7 @@ pub const registers = struct { /// address: 0x40010014 /// external interrupt configuration register /// 4 - pub const SYSCFG_EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { /// EXTI 12 configuration bits EXTI12: u4, /// EXTI 13 configuration bits @@ -31658,7 +31658,7 @@ pub const registers = struct { /// address: 0x40010018 /// configuration register 2 - pub const SYSCFG_CFGR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_CFGR2 = @intToPtr(*volatile Mmio(32, packed struct { /// Cortex-M0 LOCKUP bit enable /// bit LOCUP_LOCK: u1, @@ -31702,7 +31702,7 @@ pub const registers = struct { /// address: 0x40010004 /// CCM SRAM protection register - pub const SYSCFG_RCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SYSCFG_RCR = @intToPtr(*volatile Mmio(32, packed struct { /// CCM SRAM page write protection /// bit PAGE0_WP: u1, @@ -31755,7 +31755,7 @@ pub const registers = struct { /// address: 0x4001001c /// control and status register - pub const COMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 1 enable COMP1EN: u1, /// COMP1_INP_DAC @@ -31797,7 +31797,7 @@ pub const registers = struct { /// address: 0x40010020 /// control and status register - pub const COMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 2 enable COMP2EN: u1, reserved0: u1, @@ -31841,7 +31841,7 @@ pub const registers = struct { /// address: 0x40010024 /// control and status register - pub const COMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 3 enable COMP3EN: u1, reserved0: u1, @@ -31884,7 +31884,7 @@ pub const registers = struct { /// address: 0x40010028 /// control and status register - pub const COMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 4 enable COMP4EN: u1, reserved0: u1, @@ -31928,7 +31928,7 @@ pub const registers = struct { /// address: 0x4001002c /// control and status register - pub const COMP5_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP5_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 5 enable COMP5EN: u1, reserved0: u1, @@ -31971,7 +31971,7 @@ pub const registers = struct { /// address: 0x40010030 /// control and status register - pub const COMP6_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP6_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 6 enable COMP6EN: u1, reserved0: u1, @@ -32015,7 +32015,7 @@ pub const registers = struct { /// address: 0x40010034 /// control and status register - pub const COMP7_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const COMP7_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// Comparator 7 enable COMP7EN: u1, reserved0: u1, @@ -32058,7 +32058,7 @@ pub const registers = struct { /// address: 0x40010038 /// control register - pub const OPAMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OPAMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// OPAMP1 enable OPAMP1_EN: u1, /// FORCE_VP @@ -32103,7 +32103,7 @@ pub const registers = struct { /// address: 0x4001003c /// control register - pub const OPAMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OPAMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// OPAMP2 enable OPAMP2EN: u1, /// FORCE_VP @@ -32148,7 +32148,7 @@ pub const registers = struct { /// address: 0x40010040 /// control register - pub const OPAMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OPAMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// OPAMP3 enable OPAMP3EN: u1, /// FORCE_VP @@ -32193,7 +32193,7 @@ pub const registers = struct { /// address: 0x40010044 /// control register - pub const OPAMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const OPAMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct { /// OPAMP4 enable OPAMP4EN: u1, /// FORCE_VP @@ -32243,7 +32243,7 @@ pub const registers = struct { /// address: 0xa0000400 /// SRAM/NOR-Flash chip-select control register /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -32293,7 +32293,7 @@ pub const registers = struct { /// address: 0xa0000404 /// SRAM/NOR-Flash chip-select timing register /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32315,7 +32315,7 @@ pub const registers = struct { /// address: 0xa0000408 /// SRAM/NOR-Flash chip-select control register /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -32365,7 +32365,7 @@ pub const registers = struct { /// address: 0xa000040c /// SRAM/NOR-Flash chip-select timing register /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32387,7 +32387,7 @@ pub const registers = struct { /// address: 0xa0000410 /// SRAM/NOR-Flash chip-select control register /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -32437,7 +32437,7 @@ pub const registers = struct { /// address: 0xa0000414 /// SRAM/NOR-Flash chip-select timing register /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32459,7 +32459,7 @@ pub const registers = struct { /// address: 0xa0000418 /// SRAM/NOR-Flash chip-select control register /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { /// MBKEN MBKEN: u1, /// MUXEN @@ -32509,7 +32509,7 @@ pub const registers = struct { /// address: 0xa000041c /// SRAM/NOR-Flash chip-select timing register /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32531,7 +32531,7 @@ pub const registers = struct { /// address: 0xa0000460 /// PC Card/NAND Flash control register /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -32568,7 +32568,7 @@ pub const registers = struct { /// address: 0xa0000464 /// FIFO status and interrupt register /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -32613,7 +32613,7 @@ pub const registers = struct { /// address: 0xa0000468 /// Common memory space timing register /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -32627,7 +32627,7 @@ pub const registers = struct { /// address: 0xa000046c /// Attribute memory space timing register /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { /// ATTSETx ATTSETx: u8, /// ATTWAITx @@ -32640,7 +32640,7 @@ pub const registers = struct { /// address: 0xa0000474 /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ECCx ECCx: u32, }), base_address + 0x74); @@ -32648,7 +32648,7 @@ pub const registers = struct { /// address: 0xa0000480 /// PC Card/NAND Flash control register /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -32685,7 +32685,7 @@ pub const registers = struct { /// address: 0xa0000484 /// FIFO status and interrupt register /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -32730,7 +32730,7 @@ pub const registers = struct { /// address: 0xa0000488 /// Common memory space timing register /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -32744,7 +32744,7 @@ pub const registers = struct { /// address: 0xa000048c /// Attribute memory space timing register /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { /// ATTSETx ATTSETx: u8, /// ATTWAITx @@ -32757,7 +32757,7 @@ pub const registers = struct { /// address: 0xa0000494 /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ECCx ECCx: u32, }), base_address + 0x94); @@ -32765,7 +32765,7 @@ pub const registers = struct { /// address: 0xa00004a0 /// PC Card/NAND Flash control register /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// PWAITEN PWAITEN: u1, @@ -32802,7 +32802,7 @@ pub const registers = struct { /// address: 0xa00004a4 /// FIFO status and interrupt register /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { /// IRS IRS: u1, /// ILS @@ -32847,7 +32847,7 @@ pub const registers = struct { /// address: 0xa00004a8 /// Common memory space timing register /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { /// MEMSETx MEMSETx: u8, /// MEMWAITx @@ -32861,7 +32861,7 @@ pub const registers = struct { /// address: 0xa00004ac /// Attribute memory space timing register /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { /// ATTSETx ATTSETx: u8, /// ATTWAITx @@ -32874,7 +32874,7 @@ pub const registers = struct { /// address: 0xa00004b0 /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { /// IOSETx IOSETx: u8, /// IOWAITx @@ -32888,7 +32888,7 @@ pub const registers = struct { /// address: 0xa0000504 /// SRAM/NOR-Flash write timing registers /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32911,7 +32911,7 @@ pub const registers = struct { /// address: 0xa000050c /// SRAM/NOR-Flash write timing registers /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32934,7 +32934,7 @@ pub const registers = struct { /// address: 0xa0000514 /// SRAM/NOR-Flash write timing registers /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32957,7 +32957,7 @@ pub const registers = struct { /// address: 0xa000051c /// SRAM/NOR-Flash write timing registers /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { /// ADDSET ADDSET: u4, /// ADDHLD @@ -32984,21 +32984,21 @@ pub const registers = struct { /// address: 0xe000e100 /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { /// SETENA SETENA: u32, }), base_address + 0x0); /// address: 0xe000e104 /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { /// SETENA SETENA: u32, }), base_address + 0x4); /// address: 0xe000e108 /// Interrupt Set-Enable Register - pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { /// SETENA SETENA: u32, }), base_address + 0x8); @@ -33006,7 +33006,7 @@ pub const registers = struct { /// address: 0xe000e180 /// Interrupt Clear-Enable /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRENA CLRENA: u32, }), base_address + 0x80); @@ -33014,7 +33014,7 @@ pub const registers = struct { /// address: 0xe000e184 /// Interrupt Clear-Enable /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRENA CLRENA: u32, }), base_address + 0x84); @@ -33022,28 +33022,28 @@ pub const registers = struct { /// address: 0xe000e188 /// Interrupt Clear-Enable /// Register - pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRENA CLRENA: u32, }), base_address + 0x88); /// address: 0xe000e200 /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// SETPEND SETPEND: u32, }), base_address + 0x100); /// address: 0xe000e204 /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// SETPEND SETPEND: u32, }), base_address + 0x104); /// address: 0xe000e208 /// Interrupt Set-Pending Register - pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// SETPEND SETPEND: u32, }), base_address + 0x108); @@ -33051,7 +33051,7 @@ pub const registers = struct { /// address: 0xe000e280 /// Interrupt Clear-Pending /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRPEND CLRPEND: u32, }), base_address + 0x180); @@ -33059,7 +33059,7 @@ pub const registers = struct { /// address: 0xe000e284 /// Interrupt Clear-Pending /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRPEND CLRPEND: u32, }), base_address + 0x184); @@ -33067,35 +33067,35 @@ pub const registers = struct { /// address: 0xe000e288 /// Interrupt Clear-Pending /// Register - pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// CLRPEND CLRPEND: u32, }), base_address + 0x188); /// address: 0xe000e300 /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { /// ACTIVE ACTIVE: u32, }), base_address + 0x200); /// address: 0xe000e304 /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { /// ACTIVE ACTIVE: u32, }), base_address + 0x204); /// address: 0xe000e308 /// Interrupt Active Bit Register - pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { /// ACTIVE ACTIVE: u32, }), base_address + 0x208); /// address: 0xe000e400 /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33108,7 +33108,7 @@ pub const registers = struct { /// address: 0xe000e404 /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33121,7 +33121,7 @@ pub const registers = struct { /// address: 0xe000e408 /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33134,7 +33134,7 @@ pub const registers = struct { /// address: 0xe000e40c /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33147,7 +33147,7 @@ pub const registers = struct { /// address: 0xe000e410 /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33160,7 +33160,7 @@ pub const registers = struct { /// address: 0xe000e414 /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33173,7 +33173,7 @@ pub const registers = struct { /// address: 0xe000e418 /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33186,7 +33186,7 @@ pub const registers = struct { /// address: 0xe000e41c /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33199,7 +33199,7 @@ pub const registers = struct { /// address: 0xe000e420 /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33212,7 +33212,7 @@ pub const registers = struct { /// address: 0xe000e424 /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33225,7 +33225,7 @@ pub const registers = struct { /// address: 0xe000e428 /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33238,7 +33238,7 @@ pub const registers = struct { /// address: 0xe000e42c /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33251,7 +33251,7 @@ pub const registers = struct { /// address: 0xe000e430 /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33264,7 +33264,7 @@ pub const registers = struct { /// address: 0xe000e434 /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33277,7 +33277,7 @@ pub const registers = struct { /// address: 0xe000e438 /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33290,7 +33290,7 @@ pub const registers = struct { /// address: 0xe000e43c /// Interrupt Priority Register - pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33303,7 +33303,7 @@ pub const registers = struct { /// address: 0xe000e440 /// Interrupt Priority Register - pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33316,7 +33316,7 @@ pub const registers = struct { /// address: 0xe000e444 /// Interrupt Priority Register - pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33329,7 +33329,7 @@ pub const registers = struct { /// address: 0xe000e448 /// Interrupt Priority Register - pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33342,7 +33342,7 @@ pub const registers = struct { /// address: 0xe000e44c /// Interrupt Priority Register - pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33355,7 +33355,7 @@ pub const registers = struct { /// address: 0xe000e450 /// Interrupt Priority Register - pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct { /// IPR_N0 IPR_N0: u8, /// IPR_N1 @@ -33373,7 +33373,7 @@ pub const registers = struct { /// address: 0xe000ef34 /// Floating-point context control /// register - pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { /// LSPACT LSPACT: u1, /// USER @@ -33420,7 +33420,7 @@ pub const registers = struct { /// address: 0xe000ef38 /// Floating-point context address /// register - pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -33432,7 +33432,7 @@ pub const registers = struct { /// address: 0xe000ef3c /// Floating-point status control /// register - pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { /// Invalid operation cumulative exception /// bit IOC: u1, @@ -33498,7 +33498,7 @@ pub const registers = struct { /// address: 0xe000ed90 /// MPU type register - pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { /// Separate flag SEPARATE: u1, reserved0: u1, @@ -33525,7 +33525,7 @@ pub const registers = struct { /// address: 0xe000ed94 /// MPU control register - pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { /// Enables the MPU ENABLE: u1, /// Enables the operation of MPU during hard @@ -33567,7 +33567,7 @@ pub const registers = struct { /// address: 0xe000ed98 /// MPU region number register - pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { /// MPU region REGION: u8, padding0: u1, @@ -33599,7 +33599,7 @@ pub const registers = struct { /// address: 0xe000ed9c /// MPU region base address /// register - pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { /// MPU region field REGION: u4, /// MPU region number valid @@ -33611,7 +33611,7 @@ pub const registers = struct { /// address: 0xe000eda0 /// MPU region attribute and size /// register - pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { /// Region enable bit. ENABLE: u1, /// Size of the MPU protection @@ -33649,7 +33649,7 @@ pub const registers = struct { /// address: 0xe000e010 /// SysTick control and status /// register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { /// Counter enable ENABLE: u1, /// SysTick exception request @@ -33691,7 +33691,7 @@ pub const registers = struct { /// address: 0xe000e014 /// SysTick reload value register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct{ + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { /// RELOAD value RELOAD: u24, padding0: u1, @@ -33706,7 +33706,7 @@ pub const registers = struct { /// address: 0xe000e018 /// SysTick current value register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { /// Current counter value CURRENT: u24, padding0: u1, @@ -33722,7 +33722,7 @@ pub const registers = struct { /// address: 0xe000e01c /// SysTick calibration value /// register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { /// Calibration value TENMS: u24, reserved0: u1, @@ -33744,7 +33744,7 @@ pub const registers = struct { /// address: 0xe000ed00 /// CPUID base register - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { /// Revision number Revision: u4, /// Part number of the @@ -33761,7 +33761,7 @@ pub const registers = struct { /// address: 0xe000ed04 /// Interrupt control and state /// register - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { /// Active vector VECTACTIVE: u9, reserved0: u1, @@ -33795,7 +33795,7 @@ pub const registers = struct { /// address: 0xe000ed08 /// Vector table offset register - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -33815,7 +33815,7 @@ pub const registers = struct { /// address: 0xe000ed0c /// Application interrupt and reset control /// register - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { /// VECTRESET VECTRESET: u1, /// VECTCLRACTIVE @@ -33841,7 +33841,7 @@ pub const registers = struct { /// address: 0xe000ed10 /// System control register - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// SLEEPONEXIT SLEEPONEXIT: u1, @@ -33882,7 +33882,7 @@ pub const registers = struct { /// address: 0xe000ed14 /// Configuration and control /// register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { /// Configures how the processor enters /// Thread mode NONBASETHRDENA: u1, @@ -33927,7 +33927,7 @@ pub const registers = struct { /// address: 0xe000ed18 /// System handler priority /// registers - pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { /// Priority of system handler /// 4 PRI_4: u8, @@ -33950,7 +33950,7 @@ pub const registers = struct { /// address: 0xe000ed1c /// System handler priority /// registers - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -33983,7 +33983,7 @@ pub const registers = struct { /// address: 0xe000ed20 /// System handler priority /// registers - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -34011,7 +34011,7 @@ pub const registers = struct { /// address: 0xe000ed24 /// System handler control and state /// register - pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct{ + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { /// Memory management fault exception active /// bit MEMFAULTACT: u1, @@ -34072,7 +34072,7 @@ pub const registers = struct { /// address: 0xe000ed28 /// Configurable fault status /// register - pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Instruction access violation /// flag @@ -34139,7 +34139,7 @@ pub const registers = struct { /// address: 0xe000ed2c /// Hard fault status register - pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, /// Vector table hard fault VECTTBL: u1, @@ -34189,7 +34189,7 @@ pub const registers = struct { /// address: 0xe000ed3c /// Auxiliary fault status /// register - pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { /// Implementation defined IMPDEF: u32, }), base_address + 0x3c); @@ -34202,7 +34202,7 @@ pub const registers = struct { /// address: 0xe000ef00 /// Software trigger interrupt /// register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { /// Software generated interrupt /// ID INTID: u9, @@ -34238,7 +34238,7 @@ pub const registers = struct { /// address: 0xe000ed88 /// Coprocessor access control /// register - pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct{ + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1, reserved1: u1, reserved2: u1, @@ -34277,7 +34277,7 @@ pub const registers = struct { /// address: 0xe000e008 /// Auxiliary control register - pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct{ + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { /// DISMCYCINT DISMCYCINT: u1, /// DISDEFWBUF From 823ff6577fde2f6cef2aadf25686259242a0ef58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Tue, 15 Mar 2022 08:41:59 +0100 Subject: [PATCH 035/138] Greatly simplifies the package logic by using a proxy-to-root package. (#28) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Greatly simplifies the package logic by using a proxy-to-root package. * Makes startup logic less obscure. Co-authored-by: Felix "xq" Queißner --- src/core/clock.zig | 7 +- src/core/import-package.zig | 8 ++ src/core/interrupts.zig | 4 +- src/core/microzig.zig | 81 +++++++++++++- src/core/start.zig | 112 ------------------- src/main.zig | 114 +++++++------------- src/modules/chips/atmega328p/atmega328p.zig | 2 +- src/modules/chips/lpc1768/lpc1768.zig | 1 - src/modules/cpus/cortex-m/cortex-m.zig | 59 +++++++++- 9 files changed, 191 insertions(+), 197 deletions(-) create mode 100644 src/core/import-package.zig delete mode 100644 src/core/start.zig diff --git a/src/core/clock.zig b/src/core/clock.zig index ee7b408..a7d8b64 100644 --- a/src/core/clock.zig +++ b/src/core/clock.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const root = @import("root"); const micro = @import("microzig.zig"); /// An enumeration of clock sources. @@ -20,7 +19,7 @@ pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&@field(clock_source_typ /// Contains the source which provides microzig with clock information. pub const source: Source = switch (clock_source_type) { - root => .application, + micro.app => .application, micro.board => .board, micro.chip => .chip, micro.cpu => .cpu, @@ -43,8 +42,8 @@ pub inline fn get() u32 { const freq_decl_name = "cpu_frequency"; const no_clock_source_type = opaque {}; -const clock_source_type = if (@hasDecl(root, freq_decl_name)) - root +const clock_source_type = if (@hasDecl(micro.app, freq_decl_name)) + micro.app else if (micro.config.has_board and @hasDecl(micro.board, freq_decl_name)) micro.board else if (@hasDecl(micro.chip, freq_decl_name)) diff --git a/src/core/import-package.zig b/src/core/import-package.zig new file mode 100644 index 0000000..79581ff --- /dev/null +++ b/src/core/import-package.zig @@ -0,0 +1,8 @@ +//! This file is meant as a dependency for the "app" package. +//! It will only re-export all symbols from "root" under the name "microzig" +//! So we have a flattened and simplified dependency tree. +//! +//! Each config/module of microzig will also just depend on this file, so we can use +//! the same benefits there. + +pub usingnamespace @import("root"); diff --git a/src/core/interrupts.zig b/src/core/interrupts.zig index 79f297f..dd67e8c 100644 --- a/src/core/interrupts.zig +++ b/src/core/interrupts.zig @@ -23,13 +23,13 @@ pub fn isEnabled(comptime interrupt: anytype) bool { /// *Set Enable Interrupt*, will enable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. pub fn sei() void { - micro.chip.cpu.sei(); + micro.cpu.sei(); } /// *Clear Enable Interrupt*, will disable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. pub fn cli() void { - micro.chip.cpu.cli(); + micro.cpu.cli(); } /// Returns true, when interrupts are globally enabled via `sei()`. diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 4343a23..67293df 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -1,7 +1,15 @@ +//! This is the entry point and root file of microzig. +//! If you do a @import("microzig"), you'll *basically* get this file. +//! +//! But microzig employs a proxy tactic + const std = @import("std"); const root = @import("root"); const builtin = @import("builtin"); +/// The app that is currently built. +pub const app = @import("app"); + /// Contains build-time generated configuration options for microzig. /// Contains a CPU target description, chip, board and cpu information /// and so on. @@ -14,7 +22,7 @@ pub const chip = @import("chip"); pub const board = if (config.has_board) @import("board") else void; /// Provides access to the low level features of the CPU. -pub const cpu = chip.cpu; +pub const cpu = @import("cpu"); /// Module that helps with interrupt handling. pub const interrupts = @import("interrupts.zig"); @@ -33,6 +41,8 @@ pub const Uart = uart.Uart; pub const debug = @import("debug.zig"); +pub const mmio = @import("mmio.zig"); + /// The microzig panic handler. Will disable interrupts and loop endlessly. /// Export this symbol from your main file to enable microzig: /// ``` @@ -73,6 +83,75 @@ pub fn hang() noreturn { } } +// Startup logic: comptime { + // Instantiate the startup logic for the given CPU type. + // This usually implements the `_start` symbol that will populate + // the sections .data and .bss with the correct data. + // .rodata is not always necessary to be populated (flash based systems + // can just index flash, while harvard or flash-less architectures need + // to copy .rodata into RAM). _ = cpu.startup_logic; + + // Export the vector table to flash start if we have any. + // For a lot of systems, the vector table provides a reset vector + // that is either called (Cortex-M) or executed (AVR) when initalized. + + // Allow board and chip to override CPU vector table. + const vector_table = if (board != void and @hasDecl(board, "vector_table")) + board.vector_table + else if (@hasDecl(chip, "vector_table")) + chip.vector_table + else if (@hasDecl(cpu, "vector_table")) + cpu.vector_table + else + null; + if (@TypeOf(vector_table) != @TypeOf(null)) { // ugh, comptime shenanigans + @export(vector_table, .{ + .name = "vector_table", + .section = "microzig_flash_start", + .linkage = .Strong, + }); + } +} + +/// This is the logical entry point for microzig. +/// It will invoke the main function from the root source file +/// and provides error return handling as well as a event loop if requested. +/// +/// Why is this function exported? +/// This is due to the modular design of microzig to allow the "chip" dependency of microzig +/// to call into our main function here. If we would use a normal function call, we'd have a +/// circular dependency between the `microzig` and `chip` package. This function is also likely +/// to be invoked from assembly, so it's also convenient in that regard. +export fn microzig_main() noreturn { + if (!@hasDecl(app, "main")) + @compileError("The root source file must provide a public function main!"); + + const main = @field(app, "main"); + const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); + + const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; + if (info != .Fn or info.Fn.args.len > 0) + @compileError(invalid_main_msg); + + const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); + + if (info.Fn.calling_convention == .Async) + @compileError("TODO: Embedded event loop not supported yet. Please try again later."); + + if (@typeInfo(return_type) == .ErrorUnion) { + main() catch |err| { + // TODO: + // - Compute maximum size on the type of "err" + // - Do not emit error names when std.builtin.strip is set. + var msg: [64]u8 = undefined; + @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); + }; + } else { + main(); + } + + // main returned, just hang around here a bit + hang(); } diff --git a/src/core/start.zig b/src/core/start.zig deleted file mode 100644 index 3414f48..0000000 --- a/src/core/start.zig +++ /dev/null @@ -1,112 +0,0 @@ -const std = @import("std"); -const app = @import("app"); -const builtin = @import("builtin"); -const microzig = @import("microzig"); - -pub usingnamespace app; - -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); -} - -comptime { - if (builtin.cpu.arch == .arm or builtin.cpu.arch == .thumb) { - @export(vector_table, .{ - .name = "vector_table", - .section = "microzig_flash_start", - .linkage = .Strong, - }); - } -} - -const VectorTable = microzig.chip.VectorTable; -const vector_table: VectorTable = blk: { - var tmp: microzig.chip.VectorTable = .{ - .initial_stack_pointer = microzig.config.end_of_stack, - .Reset = .{ .C = microzig.cpu.startup_logic._start }, - }; - - if (@hasDecl(app, "interrupts")) { - if (@typeInfo(app.interrupts) != .Struct) - @compileLog("root.interrupts must be a struct"); - - inline for (@typeInfo(app.interrupts).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(app.interrupts, decl.name))).Fn.calling_convention; - const handler = @field(app.interrupts, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ " " ++ field.name ++ "\n"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - - @field(tmp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; - } - } - break :blk tmp; -}; - -/// This is the logical entry point for microzig. -/// It will invoke the main function from the root source file -/// and provides error return handling as well as a event loop if requested. -/// -/// Why is this function exported? -/// This is due to the modular design of microzig to allow the "chip" dependency of microzig -/// to call into our main function here. If we would use a normal function call, we'd have a -/// circular dependency between the `microzig` and `chip` package. This function is also likely -/// to be invoked from assembly, so it's also convenient in that regard. -export fn microzig_main() noreturn { - if (!@hasDecl(app, "main")) - @compileError("The root source file must provide a public function main!"); - - const main = @field(app, "main"); - const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); - - const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; - if (info != .Fn or info.Fn.args.len > 0) - @compileError(invalid_main_msg); - - const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); - - if (info.Fn.calling_convention == .Async) - @compileError("TODO: Embedded event loop not supported yet. Please try again later."); - - if (@typeInfo(return_type) == .ErrorUnion) { - main() catch |err| { - // TODO: - // - Compute maximum size on the type of "err" - // - Do not emit error names when std.builtin.strip is set. - var msg: [64]u8 = undefined; - @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); - }; - } else { - main(); - } - - // main returned, just hang around here a bit - microzig.hang(); -} diff --git a/src/main.zig b/src/main.zig index 9174abf..721a405 100644 --- a/src/main.zig +++ b/src/main.zig @@ -102,11 +102,6 @@ pub fn addEmbeddedExecutable( try writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}); } - const microzig_pkg = Pkg{ - .name = "microzig", - .path = .{ .path = root_path ++ "core/microzig.zig" }, - }; - const config_pkg = Pkg{ .name = "microzig-config", .path = .{ .path = config_file_name }, @@ -115,19 +110,16 @@ pub fn addEmbeddedExecutable( const chip_pkg = Pkg{ .name = "chip", .path = .{ .path = chip.path }, - .dependencies = &[_]Pkg{ - microzig_pkg, - pkgs.mmio, - config_pkg, - Pkg{ - .name = "cpu", - .path = .{ .path = chip.cpu.path }, - .dependencies = &[_]Pkg{ microzig_pkg, pkgs.mmio }, - }, - }, + .dependencies = &.{pkgs.microzig}, + }; + + const cpu_pkg = Pkg{ + .name = "cpu", + .path = .{ .path = chip.cpu.path }, + .dependencies = &.{pkgs.microzig}, }; - const exe = builder.addExecutable(name, root_path ++ "core/start.zig"); + const exe = builder.addExecutable(name, root_path ++ "core/microzig.zig"); // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) @@ -142,72 +134,39 @@ pub fn addEmbeddedExecutable( // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this exe.bundle_compiler_rt = (exe.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now - switch (backing) { - .chip => { - var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); - try app_pkgs.append(Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, - }); - if (options.packages) |packages| - try app_pkgs.appendSlice(packages); + const app_pkg = blk: { + var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); - exe.addPackage(Pkg{ - .name = "app", - .path = .{ .path = source }, - .dependencies = app_pkgs.items, - }); + try app_pkgs.append(pkgs.microzig); // proxy package + if (options.packages) |packages| + try app_pkgs.appendSlice(packages); - exe.addPackage(Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ config_pkg, chip_pkg }, - }); - }, - .board => |board| { - var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); - try app_pkgs.append( - Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ - config_pkg, - chip_pkg, - Pkg{ - .name = "board", - .path = .{ .path = board.path }, - .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, - }, - }, - }, - ); - - if (options.packages) |packages| - try app_pkgs.appendSlice(packages); - - exe.addPackage(Pkg{ - .name = "app", - .path = .{ .path = source }, - .dependencies = app_pkgs.items, - }); + break :blk std.build.Pkg{ + .name = "app", + .path = .{ .path = source }, + .dependencies = app_pkgs.items, + }; + }; - exe.addPackage(Pkg{ - .name = microzig_pkg.name, - .path = microzig_pkg.path, - .dependencies = &[_]Pkg{ - config_pkg, - chip_pkg, - Pkg{ - .name = "board", - .path = .{ .path = board.path }, - .dependencies = &[_]Pkg{ microzig_pkg, chip_pkg, pkgs.mmio }, - }, - }, + // these packages will be re-exported from core/microzig.zig + + exe.addPackage(app_pkg); + exe.addPackage(config_pkg); + exe.addPackage(chip_pkg); + exe.addPackage(cpu_pkg); + + switch (backing) { + .board => |board| { + exe.addPackage(std.build.Pkg{ + .name = "board", + .path = .{ .path = board.path }, + .dependencies = &.{pkgs.microzig}, }); }, + else => {}, } + return exe; } @@ -216,4 +175,9 @@ const pkgs = struct { .name = "microzig-mmio", .path = .{ .path = root_path ++ "core/mmio.zig" }, }; + + const microzig = std.build.Pkg{ + .name = "microzig", + .path = .{ .path = root_path ++ "core/import-package.zig" }, + }; }; diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 30b93c7..b156c94 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,7 +1,7 @@ const std = @import("std"); const micro = @import("microzig"); -pub const cpu = @import("cpu"); +pub const cpu = micro.cpu; const Port = enum(u8) { B = 1, C = 2, diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index ace8395..666d272 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -5,7 +5,6 @@ const regs = chip.registers; pub usingnamespace chip; -pub const cpu = @import("cpu"); pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig index 7d0d489..33b90da 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -1,5 +1,6 @@ const std = @import("std"); -const root = @import("root"); +const microzig = @import("microzig"); +const app = microzig.app; pub fn sei() void { asm volatile ("cpsie i"); @@ -74,3 +75,59 @@ pub const startup_logic = struct { microzig_main(); } }; + +fn isValidField(field_name: []const u8) bool { + return !std.mem.startsWith(u8, field_name, "reserved") and + !std.mem.eql(u8, field_name, "initial_stack_pointer") and + !std.mem.eql(u8, field_name, "reset"); +} + +const VectorTable = microzig.chip.VectorTable; + +// will be imported by microzig.zig to allow system startup. +pub const vector_table: VectorTable = blk: { + var tmp: microzig.chip.VectorTable = .{ + .initial_stack_pointer = microzig.config.end_of_stack, + .Reset = .{ .C = microzig.cpu.startup_logic._start }, + }; + if (@hasDecl(app, "interrupts")) { + if (@typeInfo(app.interrupts) != .Struct) + @compileLog("root.interrupts must be a struct"); + + inline for (@typeInfo(app.interrupts).Struct.decls) |decl| { + const calling_convention = @typeInfo(@TypeOf(@field(app.interrupts, decl.name))).Fn.calling_convention; + const handler = @field(app.interrupts, decl.name); + + if (!@hasField(VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; + inline for (std.meta.fields(VectorTable)) |field| { + if (isValidField(field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + + if (!isValidField(decl.name)) + @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); + + @field(tmp, decl.name) = switch (calling_convention) { + .C => .{ .C = handler }, + .Naked => .{ .Naked = handler }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + }, + + else => @compileError("unsupported calling convention for function " ++ decl.name), + }; + } + } + break :blk tmp; +}; From b2793e258961e19031b0fe8f2ebfa1dfe3e8b014 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 15 Mar 2022 01:24:58 -0700 Subject: [PATCH 036/138] Avr interrupt overloading (#29) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * mostly implemented, need different patch in order to wire it in * add generated code * turned interrupts back on * fix symbol names for avr * export in cpu file * Emits a function instead of a `void` symbol. * add interrupt test to avr * Removes invalid comment. Co-authored-by: Felix "xq" Queißner --- build.zig | 2 +- src/modules/chips/atmega328p/atmega328p.zig | 1 + src/modules/chips/atmega328p/registers.zig | 1327 +++++++++++++++++++ src/modules/cpus/avr/avr5.zig | 98 +- tests/interrupt.zig | 20 +- 5 files changed, 1407 insertions(+), 41 deletions(-) create mode 100644 src/modules/chips/atmega328p/registers.zig diff --git a/build.zig b/build.zig index cb8771c..773efc6 100644 --- a/build.zig +++ b/build.zig @@ -31,7 +31,7 @@ pub fn build(b: *std.build.Builder) !void { Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true, .on_avr = false }, // Note: this example uses the systick interrupt and therefore only for arm microcontrollers - Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_avr = false }, + Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_avr = true }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index b156c94..32ffbb6 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,5 +1,6 @@ const std = @import("std"); const micro = @import("microzig"); +pub usingnamespace @import("registers.zig"); pub const cpu = micro.cpu; const Port = enum(u8) { diff --git a/src/modules/chips/atmega328p/registers.zig b/src/modules/chips/atmega328p/registers.zig new file mode 100644 index 0000000..06d4880 --- /dev/null +++ b/src/modules/chips/atmega328p/registers.zig @@ -0,0 +1,1327 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 6376709051af4d8920d5c8bb48945ca688af32ae +// +// vendor: Atmel +// device: ATmega328P +// cpu: AVR8 + +pub const VectorTable = extern struct { + /// External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + RESET: InterruptVector = unhandled, + /// External Interrupt Request 0 + INT0: InterruptVector = unhandled, + /// External Interrupt Request 1 + INT1: InterruptVector = unhandled, + /// Pin Change Interrupt Request 0 + PCINT0: InterruptVector = unhandled, + /// Pin Change Interrupt Request 1 + PCINT1: InterruptVector = unhandled, + /// Pin Change Interrupt Request 2 + PCINT2: InterruptVector = unhandled, + /// Watchdog Time-out Interrupt + WDT: InterruptVector = unhandled, + /// Timer/Counter2 Compare Match A + TIMER2_COMPA: InterruptVector = unhandled, + /// Timer/Counter2 Compare Match B + TIMER2_COMPB: InterruptVector = unhandled, + /// Timer/Counter2 Overflow + TIMER2_OVF: InterruptVector = unhandled, + /// Timer/Counter1 Capture Event + TIMER1_CAPT: InterruptVector = unhandled, + /// Timer/Counter1 Compare Match A + TIMER1_COMPA: InterruptVector = unhandled, + /// Timer/Counter1 Compare Match B + TIMER1_COMPB: InterruptVector = unhandled, + /// Timer/Counter1 Overflow + TIMER1_OVF: InterruptVector = unhandled, + /// TimerCounter0 Compare Match A + TIMER0_COMPA: InterruptVector = unhandled, + /// TimerCounter0 Compare Match B + TIMER0_COMPB: InterruptVector = unhandled, + /// Timer/Couner0 Overflow + TIMER0_OVF: InterruptVector = unhandled, + /// SPI Serial Transfer Complete + SPI_STC: InterruptVector = unhandled, + /// USART Rx Complete + USART_RX: InterruptVector = unhandled, + /// USART, Data Register Empty + USART_UDRE: InterruptVector = unhandled, + /// USART Tx Complete + USART_TX: InterruptVector = unhandled, + /// ADC Conversion Complete + ADC: InterruptVector = unhandled, + /// EEPROM Ready + EE_READY: InterruptVector = unhandled, + /// Analog Comparator + ANALOG_COMP: InterruptVector = unhandled, + /// Two-wire Serial Interface + TWI: InterruptVector = unhandled, + /// Store Program Memory Read + SPM_Ready: InterruptVector = unhandled, +}; + +pub const registers = struct { + + /// Fuses + pub const FUSE = struct { + + /// address: 0x2 + pub const EXTENDED = @intToPtr(*volatile Mmio(8, packed struct { + /// Brown-out Detector trigger level + /// + /// 0x4: Brown-out detection at VCC=4.3 V + /// 0x5: Brown-out detection at VCC=2.7 V + /// 0x6: Brown-out detection at VCC=1.8 V + /// 0x7: Brown-out detection disabled + BODLEVEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x2); + + /// address: 0x1 + pub const HIGH = @intToPtr(*volatile Mmio(8, packed struct { + /// Boot Reset vector Enabled + BOOTRST: u1, + /// Select boot size + /// + /// 0x0: Boot Flash size=2048 words start address=$3800 + /// 0x1: Boot Flash size=1024 words start address=$3C00 + /// 0x2: Boot Flash size=512 words start address=$3E00 + /// 0x3: Boot Flash size=256 words start address=$3F00 + BOOTSZ: u2, + /// Preserve EEPROM through the Chip Erase cycle + EESAVE: u1, + /// Watch-dog Timer always on + WDTON: u1, + /// Serial program downloading (SPI) enabled + SPIEN: u1, + /// Debug Wire enable + DWEN: u1, + /// Reset Disabled (Enable PC6 as i/o pin) + RSTDISBL: u1, + }), 0x1); + + /// address: 0x0 + pub const LOW = @intToPtr(*volatile Mmio(8, packed struct { + /// Select Clock Source + /// + /// 0x0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + /// 0x2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + /// 0x3: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + /// 0x4: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + /// 0x5: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + /// 0x6: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + /// 0x7: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + /// 0x8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + /// 0x9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + /// 0xa: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + /// 0xb: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + /// 0xc: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + /// 0xd: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + /// 0xe: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + /// 0xf: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + /// 0x10: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + /// 0x12: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + /// 0x13: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + /// 0x14: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + /// 0x15: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + /// 0x16: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + /// 0x17: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + /// 0x18: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + /// 0x19: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + /// 0x1a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + /// 0x1b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + /// 0x1c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + /// 0x1d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + /// 0x1e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + /// 0x1f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + /// 0x20: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + /// 0x22: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + /// 0x23: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + /// 0x24: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + /// 0x25: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + /// 0x26: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + /// 0x27: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + /// 0x28: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + /// 0x29: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + /// 0x2a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + /// 0x2b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + /// 0x2c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + /// 0x2d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + /// 0x2e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + /// 0x2f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + /// 0x36: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + /// 0x37: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + /// 0x38: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + /// 0x39: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + /// 0x3a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + /// 0x3b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + /// 0x3c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + /// 0x3d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + /// 0x3e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + /// 0x3f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + SUT_CKSEL: u6, + /// Clock output on PORTB0 + CKOUT: u1, + /// Divide clock by 8 internally + CKDIV8: u1, + }), 0x0); + }; + + /// Lockbits + pub const LOCKBIT = struct { + + /// address: 0x0 + pub const LOCKBIT = @intToPtr(*volatile Mmio(8, packed struct { + /// Memory Lock + /// + /// 0x0: Further programming and verification disabled + /// 0x2: Further programming disabled + /// 0x3: No memory lock features enabled + LB: u2, + /// Boot Loader Protection Mode + /// + /// 0x0: LPM and SPM prohibited in Application Section + /// 0x1: LPM prohibited in Application Section + /// 0x2: SPM prohibited in Application Section + /// 0x3: No lock on SPM and LPM in Application Section + BLB0: u2, + /// Boot Loader Protection Mode + /// + /// 0x0: LPM and SPM prohibited in Boot Section + /// 0x1: LPM prohibited in Boot Section + /// 0x2: SPM prohibited in Boot Section + /// 0x3: No lock on SPM and LPM in Boot Section + BLB1: u2, + padding0: u1, + padding1: u1, + }), 0x0); + }; + + /// USART + pub const USART0 = struct { + + /// address: 0xc6 + /// USART I/O Data Register + pub const UDR0 = @intToPtr(*volatile u8, 0xc6); + + /// address: 0xc0 + /// USART Control and Status Register A + pub const UCSR0A = @intToPtr(*volatile Mmio(8, packed struct { + /// Multi-processor Communication Mode + MPCM0: u1, + /// Double the USART transmission speed + U2X0: u1, + /// Parity Error + UPE0: u1, + /// Data overRun + DOR0: u1, + /// Framing Error + FE0: u1, + /// USART Data Register Empty + UDRE0: u1, + /// USART Transmitt Complete + TXC0: u1, + /// USART Receive Complete + RXC0: u1, + }), 0xc0); + + /// address: 0xc1 + /// USART Control and Status Register B + pub const UCSR0B = @intToPtr(*volatile Mmio(8, packed struct { + /// Transmit Data Bit 8 + TXB80: u1, + /// Receive Data Bit 8 + RXB80: u1, + /// Character Size - together with UCSZ0 in UCSR0C + UCSZ02: u1, + /// Transmitter Enable + TXEN0: u1, + /// Receiver Enable + RXEN0: u1, + /// USART Data register Empty Interrupt Enable + UDRIE0: u1, + /// TX Complete Interrupt Enable + TXCIE0: u1, + /// RX Complete Interrupt Enable + RXCIE0: u1, + }), 0xc1); + + /// address: 0xc2 + /// USART Control and Status Register C + pub const UCSR0C = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Polarity + UCPOL0: u1, + /// Character Size - together with UCSZ2 in UCSR0B + UCSZ0: u2, + /// Stop Bit Select + /// + /// 0x0: 1-bit + /// 0x1: 2-bit + USBS0: u1, + /// Parity Mode Bits + /// + /// 0x0: Disabled + /// 0x1: Reserved + /// 0x2: Enabled, Even Parity + /// 0x3: Enabled, Odd Parity + UPM0: u2, + /// USART Mode Select + /// + /// 0x0: Asynchronous USART + /// 0x1: Synchronous USART + /// 0x3: Master SPI + UMSEL0: u2, + }), 0xc2); + + /// address: 0xc4 + /// USART Baud Rate Register Bytes + pub const UBRR0 = @intToPtr(*volatile u12, 0xc4); + }; + + /// Two Wire Serial Interface + pub const TWI = struct { + + /// address: 0xbd + /// TWI (Slave) Address Mask Register + pub const TWAMR = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + TWAM: u7, + }), 0xbd); + + /// address: 0xb8 + /// TWI Bit Rate register + pub const TWBR = @intToPtr(*volatile u8, 0xb8); + + /// address: 0xbc + /// TWI Control Register + pub const TWCR = @intToPtr(*volatile Mmio(8, packed struct { + /// TWI Interrupt Enable + TWIE: u1, + reserved0: u1, + /// TWI Enable Bit + TWEN: u1, + /// TWI Write Collition Flag + TWWC: u1, + /// TWI Stop Condition Bit + TWSTO: u1, + /// TWI Start Condition Bit + TWSTA: u1, + /// TWI Enable Acknowledge Bit + TWEA: u1, + /// TWI Interrupt Flag + TWINT: u1, + }), 0xbc); + + /// address: 0xb9 + /// TWI Status Register + pub const TWSR = @intToPtr(*volatile Mmio(8, packed struct { + /// TWI Prescaler + /// + /// 0x0: 1 + /// 0x1: 4 + /// 0x2: 16 + /// 0x3: 64 + TWPS: u2, + reserved0: u1, + /// TWI Status + TWS: u5, + }), 0xb9); + + /// address: 0xbb + /// TWI Data register + pub const TWDR = @intToPtr(*volatile u8, 0xbb); + + /// address: 0xba + /// TWI (Slave) Address register + pub const TWAR = @intToPtr(*volatile Mmio(8, packed struct { + /// TWI General Call Recognition Enable Bit + TWGCE: u1, + /// TWI (Slave) Address register Bits + TWA: u7, + }), 0xba); + }; + + /// Timer/Counter, 16-bit + pub const TC1 = struct { + + /// address: 0x6f + /// Timer/Counter Interrupt Mask Register + pub const TIMSK1 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter1 Overflow Interrupt Enable + TOIE1: u1, + /// Timer/Counter1 Output CompareA Match Interrupt Enable + OCIE1A: u1, + /// Timer/Counter1 Output CompareB Match Interrupt Enable + OCIE1B: u1, + reserved0: u1, + reserved1: u1, + /// Timer/Counter1 Input Capture Interrupt Enable + ICIE1: u1, + padding0: u1, + padding1: u1, + }), 0x6f); + + /// address: 0x36 + /// Timer/Counter Interrupt Flag register + pub const TIFR1 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter1 Overflow Flag + TOV1: u1, + /// Output Compare Flag 1A + OCF1A: u1, + /// Output Compare Flag 1B + OCF1B: u1, + reserved0: u1, + reserved1: u1, + /// Input Capture Flag 1 + ICF1: u1, + padding0: u1, + padding1: u1, + }), 0x36); + + /// address: 0x80 + /// Timer/Counter1 Control Register A + pub const TCCR1A = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WGM1: u2, + reserved0: u1, + reserved1: u1, + /// Compare Output Mode 1B, bits + COM1B: u2, + /// Compare Output Mode 1A, bits + COM1A: u2, + }), 0x80); + + /// address: 0x81 + /// Timer/Counter1 Control Register B + pub const TCCR1B = @intToPtr(*volatile Mmio(8, packed struct { + /// Prescaler source of Timer/Counter 1 + /// + /// 0x0: No Clock Source (Stopped) + /// 0x1: Running, No Prescaling + /// 0x2: Running, CLK/8 + /// 0x3: Running, CLK/64 + /// 0x4: Running, CLK/256 + /// 0x5: Running, CLK/1024 + /// 0x6: Running, ExtClk Tn Falling Edge + /// 0x7: Running, ExtClk Tn Rising Edge + CS1: u3, + /// Waveform Generation Mode + WGM1: u2, + reserved0: u1, + /// Input Capture 1 Edge Select + ICES1: u1, + /// Input Capture 1 Noise Canceler + ICNC1: u1, + }), 0x81); + + /// address: 0x82 + /// Timer/Counter1 Control Register C + pub const TCCR1C = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + FOC1B: u1, + FOC1A: u1, + }), 0x82); + + /// address: 0x84 + /// Timer/Counter1 Bytes + pub const TCNT1 = @intToPtr(*volatile u16, 0x84); + + /// address: 0x88 + /// Timer/Counter1 Output Compare Register Bytes + pub const OCR1A = @intToPtr(*volatile u16, 0x88); + + /// address: 0x8a + /// Timer/Counter1 Output Compare Register Bytes + pub const OCR1B = @intToPtr(*volatile u16, 0x8a); + + /// address: 0x86 + /// Timer/Counter1 Input Capture Register Bytes + pub const ICR1 = @intToPtr(*volatile u16, 0x86); + + /// address: 0x43 + /// General Timer/Counter Control Register + pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Prescaler Reset Timer/Counter1 and Timer/Counter0 + PSRSYNC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), 0x43); + }; + + /// Timer/Counter, 8-bit Async + pub const TC2 = struct { + + /// address: 0x70 + /// Timer/Counter Interrupt Mask register + pub const TIMSK2 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter2 Overflow Interrupt Enable + TOIE2: u1, + /// Timer/Counter2 Output Compare Match A Interrupt Enable + OCIE2A: u1, + /// Timer/Counter2 Output Compare Match B Interrupt Enable + OCIE2B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x70); + + /// address: 0x37 + /// Timer/Counter Interrupt Flag Register + pub const TIFR2 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter2 Overflow Flag + TOV2: u1, + /// Output Compare Flag 2A + OCF2A: u1, + /// Output Compare Flag 2B + OCF2B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x37); + + /// address: 0xb0 + /// Timer/Counter2 Control Register A + pub const TCCR2A = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Genration Mode + WGM2: u2, + reserved0: u1, + reserved1: u1, + /// Compare Output Mode bits + COM2B: u2, + /// Compare Output Mode bits + COM2A: u2, + }), 0xb0); + + /// address: 0xb1 + /// Timer/Counter2 Control Register B + pub const TCCR2B = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Select bits + /// + /// 0x0: No Clock Source (Stopped) + /// 0x1: Running, No Prescaling + /// 0x2: Running, CLK/8 + /// 0x3: Running, CLK/32 + /// 0x4: Running, CLK/64 + /// 0x5: Running, CLK/128 + /// 0x6: Running, CLK/256 + /// 0x7: Running, CLK/1024 + CS2: u3, + /// Waveform Generation Mode + WGM22: u1, + reserved0: u1, + reserved1: u1, + /// Force Output Compare B + FOC2B: u1, + /// Force Output Compare A + FOC2A: u1, + }), 0xb1); + + /// address: 0xb2 + /// Timer/Counter2 + pub const TCNT2 = @intToPtr(*volatile u8, 0xb2); + + /// address: 0xb4 + /// Timer/Counter2 Output Compare Register B + pub const OCR2B = @intToPtr(*volatile u8, 0xb4); + + /// address: 0xb3 + /// Timer/Counter2 Output Compare Register A + pub const OCR2A = @intToPtr(*volatile u8, 0xb3); + + /// address: 0xb6 + /// Asynchronous Status Register + pub const ASSR = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter Control Register2 Update Busy + TCR2BUB: u1, + /// Timer/Counter Control Register2 Update Busy + TCR2AUB: u1, + /// Output Compare Register 2 Update Busy + OCR2BUB: u1, + /// Output Compare Register2 Update Busy + OCR2AUB: u1, + /// Timer/Counter2 Update Busy + TCN2UB: u1, + /// Asynchronous Timer/Counter2 + AS2: u1, + /// Enable External Clock Input + EXCLK: u1, + padding0: u1, + }), 0xb6); + + /// address: 0x43 + /// General Timer Counter Control register + pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Prescaler Reset Timer/Counter2 + PSRASY: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), 0x43); + }; + + /// Analog-to-Digital Converter + pub const ADC = struct { + + /// address: 0x7c + /// The ADC multiplexer Selection Register + pub const ADMUX = @intToPtr(*volatile Mmio(8, packed struct { + /// Analog Channel Selection Bits + /// + /// 0x0: ADC Single Ended Input pin 0 + /// 0x1: ADC Single Ended Input pin 1 + /// 0x2: ADC Single Ended Input pin 2 + /// 0x3: ADC Single Ended Input pin 3 + /// 0x4: ADC Single Ended Input pin 4 + /// 0x5: ADC Single Ended Input pin 5 + /// 0x6: ADC Single Ended Input pin 6 + /// 0x7: ADC Single Ended Input pin 7 + /// 0x8: Temperature sensor + /// 0xe: Internal Reference (VBG) + /// 0xf: 0V (GND) + MUX: u4, + reserved0: u1, + /// Left Adjust Result + ADLAR: u1, + /// Reference Selection Bits + /// + /// 0x0: AREF, Internal Vref turned off + /// 0x1: AVCC with external capacitor at AREF pin + /// 0x2: Reserved + /// 0x3: Internal 1.1V Voltage Reference with external capacitor at AREF pin + REFS: u2, + }), 0x7c); + + /// address: 0x78 + /// ADC Data Register Bytes + pub const ADC = @intToPtr(*volatile u16, 0x78); + + /// address: 0x7a + /// The ADC Control and Status register A + pub const ADCSRA = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Prescaler Select Bits + /// + /// 0x0: 2 + /// 0x1: 2 + /// 0x2: 4 + /// 0x3: 8 + /// 0x4: 16 + /// 0x5: 32 + /// 0x6: 64 + /// 0x7: 128 + ADPS: u3, + /// ADC Interrupt Enable + ADIE: u1, + /// ADC Interrupt Flag + ADIF: u1, + /// ADC Auto Trigger Enable + ADATE: u1, + /// ADC Start Conversion + ADSC: u1, + /// ADC Enable + ADEN: u1, + }), 0x7a); + + /// address: 0x7b + /// The ADC Control and Status register B + pub const ADCSRB = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Auto Trigger Source bits + /// + /// 0x0: Free Running mode + /// 0x1: Analog Comparator + /// 0x2: External Interrupt Request 0 + /// 0x3: Timer/Counter0 Compare Match A + /// 0x4: Timer/Counter0 Overflow + /// 0x5: Timer/Counter1 Compare Match B + /// 0x6: Timer/Counter1 Overflow + /// 0x7: Timer/Counter1 Capture Event + ADTS: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + ACME: u1, + padding0: u1, + }), 0x7b); + + /// address: 0x7e + /// Digital Input Disable Register + pub const DIDR0 = @intToPtr(*volatile Mmio(8, packed struct { + ADC0D: u1, + ADC1D: u1, + ADC2D: u1, + ADC3D: u1, + ADC4D: u1, + ADC5D: u1, + padding0: u1, + padding1: u1, + }), 0x7e); + }; + + /// Analog Comparator + pub const AC = struct { + + /// address: 0x50 + /// Analog Comparator Control And Status Register + pub const ACSR = @intToPtr(*volatile Mmio(8, packed struct { + /// Analog Comparator Interrupt Mode Select bits + /// + /// 0x0: Interrupt on Toggle + /// 0x1: Reserved + /// 0x2: Interrupt on Falling Edge + /// 0x3: Interrupt on Rising Edge + ACIS: u2, + /// Analog Comparator Input Capture Enable + ACIC: u1, + /// Analog Comparator Interrupt Enable + ACIE: u1, + /// Analog Comparator Interrupt Flag + ACI: u1, + /// Analog Compare Output + ACO: u1, + /// Analog Comparator Bandgap Select + ACBG: u1, + /// Analog Comparator Disable + ACD: u1, + }), 0x50); + + /// address: 0x7f + /// Digital Input Disable Register 1 + pub const DIDR1 = @intToPtr(*volatile Mmio(8, packed struct { + /// AIN0 Digital Input Disable + AIN0D: u1, + /// AIN1 Digital Input Disable + AIN1D: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), 0x7f); + }; + + /// I/O Port + pub const PORTB = struct { + + /// address: 0x25 + /// Port B Data Register + pub const PORTB = @intToPtr(*volatile u8, 0x25); + + /// address: 0x24 + /// Port B Data Direction Register + pub const DDRB = @intToPtr(*volatile u8, 0x24); + + /// address: 0x23 + /// Port B Input Pins + pub const PINB = @intToPtr(*volatile u8, 0x23); + }; + + /// I/O Port + pub const PORTC = struct { + + /// address: 0x28 + /// Port C Data Register + pub const PORTC = @intToPtr(*volatile u7, 0x28); + + /// address: 0x27 + /// Port C Data Direction Register + pub const DDRC = @intToPtr(*volatile u7, 0x27); + + /// address: 0x26 + /// Port C Input Pins + pub const PINC = @intToPtr(*volatile u7, 0x26); + }; + + /// I/O Port + pub const PORTD = struct { + + /// address: 0x2b + /// Port D Data Register + pub const PORTD = @intToPtr(*volatile u8, 0x2b); + + /// address: 0x2a + /// Port D Data Direction Register + pub const DDRD = @intToPtr(*volatile u8, 0x2a); + + /// address: 0x29 + /// Port D Input Pins + pub const PIND = @intToPtr(*volatile u8, 0x29); + }; + + /// Timer/Counter, 8-bit + pub const TC0 = struct { + + /// address: 0x48 + /// Timer/Counter0 Output Compare Register + pub const OCR0B = @intToPtr(*volatile u8, 0x48); + + /// address: 0x47 + /// Timer/Counter0 Output Compare Register + pub const OCR0A = @intToPtr(*volatile u8, 0x47); + + /// address: 0x46 + /// Timer/Counter0 + pub const TCNT0 = @intToPtr(*volatile u8, 0x46); + + /// address: 0x45 + /// Timer/Counter Control Register B + pub const TCCR0B = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Select + /// + /// 0x0: No Clock Source (Stopped) + /// 0x1: Running, No Prescaling + /// 0x2: Running, CLK/8 + /// 0x3: Running, CLK/64 + /// 0x4: Running, CLK/256 + /// 0x5: Running, CLK/1024 + /// 0x6: Running, ExtClk Tn Falling Edge + /// 0x7: Running, ExtClk Tn Rising Edge + CS0: u3, + WGM02: u1, + reserved0: u1, + reserved1: u1, + /// Force Output Compare B + FOC0B: u1, + /// Force Output Compare A + FOC0A: u1, + }), 0x45); + + /// address: 0x44 + /// Timer/Counter Control Register A + pub const TCCR0A = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WGM0: u2, + reserved0: u1, + reserved1: u1, + /// Compare Output Mode, Fast PWm + COM0B: u2, + /// Compare Output Mode, Phase Correct PWM Mode + COM0A: u2, + }), 0x44); + + /// address: 0x6e + /// Timer/Counter0 Interrupt Mask Register + pub const TIMSK0 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter0 Overflow Interrupt Enable + TOIE0: u1, + /// Timer/Counter0 Output Compare Match A Interrupt Enable + OCIE0A: u1, + /// Timer/Counter0 Output Compare Match B Interrupt Enable + OCIE0B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x6e); + + /// address: 0x35 + /// Timer/Counter0 Interrupt Flag register + pub const TIFR0 = @intToPtr(*volatile Mmio(8, packed struct { + /// Timer/Counter0 Overflow Flag + TOV0: u1, + /// Timer/Counter0 Output Compare Flag 0A + OCF0A: u1, + /// Timer/Counter0 Output Compare Flag 0B + OCF0B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x35); + + /// address: 0x43 + /// General Timer/Counter Control Register + pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Prescaler Reset Timer/Counter1 and Timer/Counter0 + PSRSYNC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer/Counter Synchronization Mode + TSM: u1, + }), 0x43); + }; + + /// External Interrupts + pub const EXINT = struct { + + /// address: 0x69 + /// External Interrupt Control Register + pub const EICRA = @intToPtr(*volatile Mmio(8, packed struct { + /// External Interrupt Sense Control 0 Bits + /// + /// 0x0: Low Level of INTX + /// 0x1: Any Logical Change of INTX + /// 0x2: Falling Edge of INTX + /// 0x3: Rising Edge of INTX + ISC0: u2, + /// External Interrupt Sense Control 1 Bits + /// + /// 0x0: Low Level of INTX + /// 0x1: Any Logical Change of INTX + /// 0x2: Falling Edge of INTX + /// 0x3: Rising Edge of INTX + ISC1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), 0x69); + + /// address: 0x3d + /// External Interrupt Mask Register + pub const EIMSK = @intToPtr(*volatile Mmio(8, packed struct { + /// External Interrupt Request 1 Enable + INT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), 0x3d); + + /// address: 0x3c + /// External Interrupt Flag Register + pub const EIFR = @intToPtr(*volatile Mmio(8, packed struct { + /// External Interrupt Flags + INTF: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), 0x3c); + + /// address: 0x68 + /// Pin Change Interrupt Control Register + pub const PCICR = @intToPtr(*volatile Mmio(8, packed struct { + /// Pin Change Interrupt Enables + PCIE: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x68); + + /// address: 0x6d + /// Pin Change Mask Register 2 + pub const PCMSK2 = @intToPtr(*volatile Mmio(8, packed struct { + /// Pin Change Enable Masks + PCINT: u8, + }), 0x6d); + + /// address: 0x6c + /// Pin Change Mask Register 1 + pub const PCMSK1 = @intToPtr(*volatile Mmio(8, packed struct { + /// Pin Change Enable Masks + PCINT: u7, + padding0: u1, + }), 0x6c); + + /// address: 0x6b + /// Pin Change Mask Register 0 + pub const PCMSK0 = @intToPtr(*volatile Mmio(8, packed struct { + /// Pin Change Enable Masks + PCINT: u8, + }), 0x6b); + + /// address: 0x3b + /// Pin Change Interrupt Flag Register + pub const PCIFR = @intToPtr(*volatile Mmio(8, packed struct { + /// Pin Change Interrupt Flags + PCIF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), 0x3b); + }; + + /// Serial Peripheral Interface + pub const SPI = struct { + + /// address: 0x4e + /// SPI Data Register + pub const SPDR = @intToPtr(*volatile u8, 0x4e); + + /// address: 0x4d + /// SPI Status Register + pub const SPSR = @intToPtr(*volatile Mmio(8, packed struct { + /// Double SPI Speed Bit + SPI2X: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Write Collision Flag + WCOL: u1, + /// SPI Interrupt Flag + SPIF: u1, + }), 0x4d); + + /// address: 0x4c + /// SPI Control Register + pub const SPCR = @intToPtr(*volatile Mmio(8, packed struct { + /// SPI Clock Rate Selects + /// + /// 0x0: fosc/2 or fosc/4 + /// 0x1: fosc/8 or fosc/16 + /// 0x2: fosc/32 or fosc/64 + /// 0x3: fosc/64 or fosc/128 + SPR: u2, + /// Clock Phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master/Slave Select + MSTR: u1, + /// Data Order + DORD: u1, + /// SPI Enable + SPE: u1, + /// SPI Interrupt Enable + SPIE: u1, + }), 0x4c); + }; + + /// Watchdog Timer + pub const WDT = struct { + + /// address: 0x60 + /// Watchdog Timer Control Register + pub const WDTCSR = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Watch Dog Enable + WDE: u1, + /// Watchdog Change Enable + WDCE: u1, + reserved3: u1, + /// Watchdog Timeout Interrupt Enable + WDIE: u1, + /// Watchdog Timeout Interrupt Flag + WDIF: u1, + }), 0x60); + }; + + /// CPU Registers + pub const CPU = struct { + + /// address: 0x64 + /// Power Reduction Register + pub const PRR = @intToPtr(*volatile Mmio(8, packed struct { + /// Power Reduction ADC + PRADC: u1, + /// Power Reduction USART + PRUSART0: u1, + /// Power Reduction Serial Peripheral Interface + PRSPI: u1, + /// Power Reduction Timer/Counter1 + PRTIM1: u1, + reserved0: u1, + /// Power Reduction Timer/Counter0 + PRTIM0: u1, + /// Power Reduction Timer/Counter2 + PRTIM2: u1, + /// Power Reduction TWI + PRTWI: u1, + }), 0x64); + + /// address: 0x66 + /// Oscillator Calibration Value + pub const OSCCAL = @intToPtr(*volatile u8, 0x66); + + /// address: 0x61 + /// Clock Prescale Register + pub const CLKPR = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Prescaler Select Bits + /// + /// 0x0: 1 + /// 0x1: 2 + /// 0x2: 4 + /// 0x3: 8 + /// 0x4: 16 + /// 0x5: 32 + /// 0x6: 64 + /// 0x7: 128 + /// 0x8: 256 + CLKPS: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Clock Prescaler Change Enable + CLKPCE: u1, + }), 0x61); + + /// address: 0x5f + /// Status Register + pub const SREG = @intToPtr(*volatile Mmio(8, packed struct { + /// Carry Flag + C: u1, + /// Zero Flag + Z: u1, + /// Negative Flag + N: u1, + /// Two's Complement Overflow Flag + V: u1, + /// Sign Bit + S: u1, + /// Half Carry Flag + H: u1, + /// Bit Copy Storage + T: u1, + /// Global Interrupt Enable + I: u1, + }), 0x5f); + + /// address: 0x5d + /// Stack Pointer + pub const SP = @intToPtr(*volatile u12, 0x5d); + + /// address: 0x57 + /// Store Program Memory Control and Status Register + pub const SPMCSR = @intToPtr(*volatile Mmio(8, packed struct { + /// Store Program Memory + SPMEN: u1, + /// Page Erase + PGERS: u1, + /// Page Write + PGWRT: u1, + /// Boot Lock Bit Set + BLBSET: u1, + /// Read-While-Write section read enable + RWWSRE: u1, + /// Signature Row Read + SIGRD: u1, + /// Read-While-Write Section Busy + RWWSB: u1, + /// SPM Interrupt Enable + SPMIE: u1, + }), 0x57); + + /// address: 0x55 + /// MCU Control Register + pub const MCUCR = @intToPtr(*volatile Mmio(8, packed struct { + IVCE: u1, + IVSEL: u1, + reserved0: u1, + reserved1: u1, + PUD: u1, + /// BOD Sleep Enable + BODSE: u1, + /// BOD Sleep + BODS: u1, + padding0: u1, + }), 0x55); + + /// address: 0x54 + /// MCU Status Register + pub const MCUSR = @intToPtr(*volatile Mmio(8, packed struct { + /// Power-on reset flag + PORF: u1, + /// External Reset Flag + EXTRF: u1, + /// Brown-out Reset Flag + BORF: u1, + /// Watchdog Reset Flag + WDRF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), 0x54); + + /// address: 0x53 + /// Sleep Mode Control Register + pub const SMCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Enable + SE: u1, + /// Sleep Mode Select Bits + /// + /// 0x0: Idle + /// 0x1: ADC Noise Reduction (If Available) + /// 0x2: Power Down + /// 0x3: Power Save + /// 0x4: Reserved + /// 0x5: Reserved + /// 0x6: Standby + /// 0x7: Extended Standby + SM: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), 0x53); + + /// address: 0x4b + /// General Purpose I/O Register 2 + pub const GPIOR2 = @intToPtr(*volatile u8, 0x4b); + + /// address: 0x4a + /// General Purpose I/O Register 1 + pub const GPIOR1 = @intToPtr(*volatile u8, 0x4a); + + /// address: 0x3e + /// General Purpose I/O Register 0 + pub const GPIOR0 = @intToPtr(*volatile u8, 0x3e); + }; + + /// EEPROM + pub const EEPROM = struct { + + /// address: 0x41 + /// EEPROM Address Register Bytes + pub const EEAR = @intToPtr(*volatile u10, 0x41); + + /// address: 0x40 + /// EEPROM Data Register + pub const EEDR = @intToPtr(*volatile u8, 0x40); + + /// address: 0x3f + /// EEPROM Control Register + pub const EECR = @intToPtr(*volatile Mmio(8, packed struct { + /// EEPROM Read Enable + EERE: u1, + /// EEPROM Write Enable + EEPE: u1, + /// EEPROM Master Write Enable + EEMPE: u1, + /// EEPROM Ready Interrupt Enable + EERIE: u1, + /// EEPROM Programming Mode Bits + /// + /// 0x0: Erase and Write in one operation + /// 0x1: Erase Only + /// 0x2: Write Only + EEPM: u2, + padding0: u1, + padding1: u1, + }), 0x3f); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index d53fd3a..ca72dcd 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -1,4 +1,5 @@ const std = @import("std"); +const microzig = @import("microzig"); pub inline fn sei() void { asm volatile ("sei"); @@ -24,46 +25,77 @@ pub inline fn cbi(comptime reg: u5, comptime bit: u3) void { ); } -pub const startup_logic = struct { - comptime { - asm ( - \\.section microzig_flash_start - \\ jmp _start - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - \\ jmp _unhandled_vector - ); +pub const vector_table = blk: { + std.debug.assert(std.mem.eql(u8, "RESET", std.meta.fields(microzig.chip.VectorTable)[0].name)); + var asm_str: []const u8 = "jmp microzig_start\n"; + + const has_interrupts = @hasDecl(microzig.app, "interrupts"); + if (has_interrupts) { + if (@hasDecl(microzig.app.interrupts, "RESET")) + @compileError("Not allowed to overload the reset vector"); + + inline for (std.meta.declarations(microzig.app.interrupts)) |decl| { + if (!@hasField(microzig.chip.VectorTable, decl.name)) { + var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. ISRs the 'interrupts' namespace must be one of:\n"; + inline for (std.meta.fields(microzig.chip.VectorTable)) |field| { + if (!std.mem.eql(u8, "RESET", field.name)) { + msg = msg ++ " " ++ field.name ++ "\n"; + } + } + + @compileError(msg); + } + } + } + + inline for (std.meta.fields(microzig.chip.VectorTable)[1..]) |field| { + const new_insn = if (has_interrupts) overload: { + if (@hasDecl(microzig.app.interrupts, field.name)) { + const handler = @field(microzig.app.interrupts, field.name); + const calling_convention = switch (@typeInfo(@TypeOf(@field(microzig.app.interrupts, field.name)))) { + .Fn => |info| info.calling_convention, + else => @compileError("Declarations in 'interrupts' namespace must all be functions. '" ++ field.name ++ "' is not a function"), + }; + + const exported_fn = switch (calling_convention) { + .Unspecified => struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, handler, .{}); + } + }.wrapper, + else => @compileError("Just leave interrupt handlers with an unspecified calling convention"), + }; + + const exported_name = "microzig_isr_" ++ field.name; + const options = .{ .name = exported_name, .linkage = .Strong }; + @export(exported_fn, options); + break :overload "jmp " ++ exported_name; + } else { + break :overload "jmp microzig_unhandled_vector"; + } + } else "jmp microzig_unhandled_vector"; + + asm_str = asm_str ++ new_insn ++ "\n"; } - export fn _unhandled_vector() callconv(.Naked) noreturn { + const T = struct { + fn _start() callconv(.Naked) void { + asm volatile (asm_str); + } + }; + + break :blk T._start; +}; + +pub const startup_logic = struct { + export fn microzig_unhandled_vector() callconv(.Naked) noreturn { @panic("Unhandled interrupt"); } extern fn microzig_main() noreturn; - export fn _start() callconv(.Naked) noreturn { + export fn microzig_start() callconv(.Naked) noreturn { // At startup the stack pointer is at the end of RAM // so, no need to set it manually! diff --git a/tests/interrupt.zig b/tests/interrupt.zig index f16fdd8..601d7fb 100644 --- a/tests/interrupt.zig +++ b/tests/interrupt.zig @@ -1,4 +1,5 @@ const micro = @import("microzig"); +const builtin = @import("builtin"); // this program will only work on arm microcontrollers, and it might not // actually run correctly at first, it's just a test for declaring interrupts @@ -6,14 +7,19 @@ const micro = @import("microzig"); pub const panic = micro.panic; -pub const interrupts = struct { - pub fn SysTick() void { - @panic("hit systick!"); - } +pub const interrupts = switch (builtin.cpu.arch) { + .avr => struct { + pub fn INT0() void { + @panic("hit PCINT0"); + } + }, + else => struct { + pub fn SysTick() void { + @panic("hit systick!"); + } + }, }; pub fn main() void { - while (true) { - micro.cpu.wfi(); - } + while (true) {} } From e639dc7983e628f004c030930dc013b61d64dd79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Tue, 15 Mar 2022 09:59:09 +0100 Subject: [PATCH 037/138] panic exporting is no longer needed. (#30) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- tests/blinky.zig | 3 --- tests/interrupt.zig | 6 ------ tests/minimal.zig | 3 --- tests/uart-sync.zig | 3 --- 4 files changed, 15 deletions(-) diff --git a/tests/blinky.zig b/tests/blinky.zig index 7a24275..0e702d0 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -1,8 +1,5 @@ const micro = @import("microzig"); -// this will instantiate microzig and pull in all dependencies -pub const panic = micro.panic; - // Configures the led_pin to a hardware pin const led_pin = if (micro.config.has_board) switch (micro.config.board_name) { diff --git a/tests/interrupt.zig b/tests/interrupt.zig index 601d7fb..34a3c68 100644 --- a/tests/interrupt.zig +++ b/tests/interrupt.zig @@ -1,12 +1,6 @@ const micro = @import("microzig"); const builtin = @import("builtin"); -// this program will only work on arm microcontrollers, and it might not -// actually run correctly at first, it's just a test for declaring interrupts -// right now. - -pub const panic = micro.panic; - pub const interrupts = switch (builtin.cpu.arch) { .avr => struct { pub fn INT0() void { diff --git a/tests/minimal.zig b/tests/minimal.zig index 17a2105..5258ce3 100644 --- a/tests/minimal.zig +++ b/tests/minimal.zig @@ -1,8 +1,5 @@ const micro = @import("microzig"); -// this will instantiate microzig and pull in all dependencies -pub const panic = micro.panic; - pub fn main() void { // This function will contain the application logic. } diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index a1713b2..2a0734e 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -1,8 +1,5 @@ const micro = @import("microzig"); -// this will instantiate microzig and pull in all dependencies -pub const panic = micro.panic; - // Configures the led_pin to a hardware pin const uart_txd_pin = micro.Pin("P0.15"); const uart_rxd_pin = micro.Pin("P0.16"); From 4384c5e9fa8b5f7625a62f5d1263a36ebb2274cc Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 18 Mar 2022 23:28:59 -0700 Subject: [PATCH 038/138] use interrupt calling convention for avr (#31) --- src/modules/cpus/avr/avr5.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index ca72dcd..25f2be0 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -59,7 +59,7 @@ pub const vector_table = blk: { const exported_fn = switch (calling_convention) { .Unspecified => struct { - fn wrapper() callconv(.C) void { + fn wrapper() callconv(.Interrupt) void { if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug @call(.{ .modifier = .always_inline }, handler, .{}); } From e44d8bf576ced9fb0b7f720ae863b9c17eb9d54e Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 18 Mar 2022 23:53:21 -0700 Subject: [PATCH 039/138] use the 'Signal' calling convention by default on AVR for ISRs, allow to explicitly use signal or interrupt calling conventions (#32) --- src/modules/cpus/avr/avr5.zig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index 25f2be0..cf79b74 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -59,12 +59,14 @@ pub const vector_table = blk: { const exported_fn = switch (calling_convention) { .Unspecified => struct { - fn wrapper() callconv(.Interrupt) void { + fn wrapper() callconv(.Signal) void { if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug @call(.{ .modifier = .always_inline }, handler, .{}); } }.wrapper, - else => @compileError("Just leave interrupt handlers with an unspecified calling convention"), + .Signal => handler, + .Interrupt => handler, + else => @compileError("Calling conventions for interrupts must be 'Interrupt', 'Signal', or unspecified. The signal calling convention leaves global interrupts disabled during the ISR, where the interrupt calling conventions enables global interrupts for nested ISRs."), }; const exported_name = "microzig_isr_" ++ field.name; From ba8feaed74fe911ceef2aced9d7209ea8f802bf9 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 19 Mar 2022 14:48:32 -0700 Subject: [PATCH 040/138] fix missing vector table on ARM (#34) --- src/core/microzig.zig | 25 ++++++++++++------------- src/modules/cpus/cortex-m/cortex-m.zig | 2 +- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 67293df..5302885 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -98,21 +98,20 @@ comptime { // that is either called (Cortex-M) or executed (AVR) when initalized. // Allow board and chip to override CPU vector table. - const vector_table = if (board != void and @hasDecl(board, "vector_table")) - board.vector_table + const export_opts = .{ + .name = "vector_table", + .section = "microzig_flash_start", + .linkage = .Strong, + }; + + if ((board != void and @hasDecl(board, "vector_table"))) + @export(board.vector_table, export_opts) else if (@hasDecl(chip, "vector_table")) - chip.vector_table + @export(chip.vector_table, export_opts) else if (@hasDecl(cpu, "vector_table")) - cpu.vector_table - else - null; - if (@TypeOf(vector_table) != @TypeOf(null)) { // ugh, comptime shenanigans - @export(vector_table, .{ - .name = "vector_table", - .section = "microzig_flash_start", - .linkage = .Strong, - }); - } + @export(cpu.vector_table, export_opts) + else if (@hasDecl(app, "interrupts")) + @compileError("interrupts not configured"); } /// This is the logical entry point for microzig. diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig index 33b90da..bd1ecda 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -85,7 +85,7 @@ fn isValidField(field_name: []const u8) bool { const VectorTable = microzig.chip.VectorTable; // will be imported by microzig.zig to allow system startup. -pub const vector_table: VectorTable = blk: { +pub var vector_table: VectorTable = blk: { var tmp: microzig.chip.VectorTable = .{ .initial_stack_pointer = microzig.config.end_of_stack, .Reset = .{ .C = microzig.cpu.startup_logic._start }, From 04bf2c4d4af0a3f573e7ddf592f80fb957a30497 Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Tue, 22 Mar 2022 09:10:23 +0100 Subject: [PATCH 041/138] Initial I2C support (#26) * build.zig: Trivial rename around UART test * mmio: Add writeRaw() to set a full register * UART: Add TODO for auto baud rate detection * STM32F30x Initial USART1 output/transmit support All code assumes default chip clock configuration. Code assumes STM32F303xB / STM32F3030xC. Code supports only 8 data bits, 1 stop bit. * stm32f3discovery @panic() to UART1 This is done by implementing `debugWrite()` for the board, which only initializes UART1 if that was not yet done, and flushes afterwards to make sure the host receives all. * stm32f303: Support UART1 reader This is done by implementing `rx()` and `canRead()`. * stm32f303 UART1 correctly support 7 and 8 bits This includes correctly masking the parity bit on reads. * stm32f3 UART1 support 0.5/1.5/2 stop bits * stm32f303 UART1 simplify parity code * stm32f303 I2C rough initial code Allows only writing and reading single bytes. * stm32f3 i2c: enable debug 'logging' * Add a few comments * I2C API changes, STM32F303 I2C multi-byte transfers Now using controller/device terminology, instead of master/slave. Now using 'transfer objects' to make STOPs and re-STARTs explicit, and allow using Writer and Reader APIs. Added 'register' abstraction. STM32F303 I2C now supports this new API, and multi-byte transfers. Now waiting for I2C_ISR.BUSY == 0, after setting I2C_CR2.STOP == 1. Without this, the sequence write-stop-write caused an additional STOP to be sent immediately the START and address of the second write. * Make work with regz-generated registers.zig change * Updated to match regz-generated update * After #23 repair Reset on stm32, lpc1768 * Clean-up I2C `readRegisters()`. * Refactor to separate read/write states * On STM32F303, make second read call fail Also doc comments to clarify the new API. * STM32 I2C: Properly support multiple write calls * I2C STM32: Fix release mode compile error ...on top of an earlier commit on this branch. * I2C Add 'write register' shorthand functions --- src/core/i2c.zig | 150 +++++++++++++++ src/core/microzig.zig | 3 + src/modules/chips/stm32f303/stm32f303.zig | 213 ++++++++++++++++++++++ 3 files changed, 366 insertions(+) create mode 100644 src/core/i2c.zig diff --git a/src/core/i2c.zig b/src/core/i2c.zig new file mode 100644 index 0000000..5cc651c --- /dev/null +++ b/src/core/i2c.zig @@ -0,0 +1,150 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); +const chip = @import("chip"); + +pub fn I2CController(comptime index: usize) type { + const SystemI2CController = chip.I2CController(index); + + const I2CDevice = struct { + const Device = @This(); + + internal: SystemI2CController, + address: u7, + + const Direction = enum { read, write }; + fn Transfer(comptime direction: Direction) type { + return switch (direction) { + .read => struct { + const Self = @This(); + + state: SystemI2CController.ReadState, + + pub const Reader = std.io.Reader(*Self, ReadError, readSome); + + /// NOTE that some platforms, notably most (all?) STM32 microcontrollers, + /// allow only a single read call per transfer. + pub fn reader(self: *Self) Reader { + return Reader{ .context = self }; + } + + fn readSome(self: *Self, buffer: []u8) ReadError!usize { + try self.state.readNoEof(buffer); + return buffer.len; + } + + /// STOP the transfer, invalidating this object. + pub fn stop(self: *Self) !void { + try self.state.stop(); + } + + /// RESTART to a new transfer, invalidating this object. + /// Note that some platforms set the repeated START condition + /// on the first read or write call. + pub fn restartTransfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { + return Transfer(direction){ .state = try self.state.restartTransfer(new_direction) }; + } + }, + .write => struct { + const Self = @This(); + + state: SystemI2CController.WriteState, + + pub const Writer = std.io.Writer(*Self, WriteError, writeSome); + + /// NOTE that some platforms, notably most (all?) STM32 microcontrollers, + /// will not immediately write all bytes, but postpone that + /// to the next write call, or to the stop() call. + pub fn writer(self: *Self) Writer { + return Writer{ .context = self }; + } + + fn writeSome(self: *Self, buffer: []const u8) WriteError!usize { + try self.state.writeAll(buffer); + return buffer.len; + } + + /// STOP the transfer, invalidating this object. + pub fn stop(self: *Self) !void { + try self.state.stop(); + } + + /// RESTART to a new transfer, invalidating this object. + /// Note that some platforms set the repeated START condition + /// on the first read or write call. + pub fn restartTransfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { + return switch (new_direction) { + .read => Transfer(new_direction){ .state = try self.state.restartRead() }, + .write => Transfer(new_direction){ .state = try self.state.restartWrite() }, + }; + } + }, + }; + } + + /// START a new transfer. + /// Note that some platforms set the START condition + /// on the first read or write call. + pub fn startTransfer(self: Device, comptime direction: Direction) !Transfer(direction) { + return switch (direction) { + .read => Transfer(direction){ .state = try SystemI2CController.ReadState.start(self.address) }, + .write => Transfer(direction){ .state = try SystemI2CController.WriteState.start(self.address) }, + }; + } + + /// Shorthand for 'register-based' devices + pub fn writeRegister(self: Device, register_address: u8, byte: u8) ReadError!void { + try self.writeRegisters(register_address, &.{byte}); + } + + /// Shorthand for 'register-based' devices + pub fn writeRegisters(self: Device, register_address: u8, buffer: []u8) ReadError!void { + var wt = try self.startTransfer(.write); + defer wt.stop() catch {}; + try wt.writer().writeByte(register_address); + try wt.writer().writeAll(buffer); + } + + /// Shorthand for 'register-based' devices + pub fn readRegister(self: Device, register_address: u8) ReadError!u8 { + var buffer: [1]u8 = undefined; + try self.readRegisters(register_address, &buffer); + return buffer[0]; + } + + /// Shorthand for 'register-based' devices + pub fn readRegisters(self: Device, register_address: u8, buffer: []u8) ReadError!void { + var rt = write_and_restart: { + var wt = try self.startTransfer(.write); + errdefer wt.stop() catch {}; + try wt.writer().writeByte(1 << 7 | register_address); // MSB == 'keep sending until I STOP' + break :write_and_restart try wt.restartTransfer(.read); + }; + defer rt.stop() catch {}; + try rt.reader().readNoEof(buffer); + } + }; + + return struct { + const Self = @This(); + + internal: SystemI2CController, + + pub fn init() InitError!Self { + return Self{ + .internal = try SystemI2CController.init(), + }; + } + + pub fn device(self: Self, address: u7) I2CDevice { + return I2CDevice{ .internal = self.internal, .address = address }; + } + }; +} + +pub const InitError = error{}; +pub const WriteError = error{}; +pub const ReadError = error{ + EndOfStream, + TooFewBytesReceived, + TooManyBytesReceived, +}; diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 5302885..7d82417 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -39,6 +39,9 @@ pub const Pin = pin.Pin; pub const uart = @import("uart.zig"); pub const Uart = uart.Uart; +pub const i2c = @import("i2c.zig"); +pub const I2CController = i2c.I2CController; + pub const debug = @import("debug.zig"); pub const mmio = @import("mmio.zig"); diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 97122b1..4bbfb0f 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -35,6 +35,7 @@ //! and therefore USART1 runs on 8 MHz. const std = @import("std"); +const runtime_safety = std.debug.runtime_safety; const micro = @import("microzig"); const chip = @import("registers.zig"); const regs = chip.registers; @@ -234,3 +235,215 @@ pub fn Uart(comptime index: usize) type { } }; } + +const enable_stm32f303_debug = false; + +fn debugPrint(comptime format: []const u8, args: anytype) void { + if (enable_stm32f303_debug) { + micro.debug.writer().print(format, args) catch {}; + } +} + +/// This implementation does not use AUTOEND=1 +pub fn I2CController(comptime index: usize) type { + if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported"); + + return struct { + const Self = @This(); + + pub fn init() !Self { + // CONFIGURE I2C1 + // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA, + // if GPIO port B is configured for alternate function 4 for these PB pins. + + // 1. Enable the I2C CLOCK and GPIO CLOCK + regs.RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); + regs.RCC.AHBENR.modify(.{ .IOPBEN = 1 }); + debugPrint("I2C1 configuration step 1 complete\r\n", .{}); + + // 2. Configure the I2C PINs for ALternate Functions + // a) Select Alternate Function in MODER Register + regs.GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 }); + // b) Select Open Drain Output + regs.GPIOB.OTYPER.modify(.{ .OT6 = 1, .OT7 = 1 }); + // c) Select High SPEED for the PINs + regs.GPIOB.OSPEEDR.modify(.{ .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); + // d) Select Pull-up for both the Pins + regs.GPIOB.PUPDR.modify(.{ .PUPDR6 = 0b01, .PUPDR7 = 0b01 }); + // e) Configure the Alternate Function in AFR Register + regs.GPIOB.AFRL.modify(.{ .AFRL6 = 4, .AFRL7 = 4 }); + debugPrint("I2C1 configuration step 2 complete\r\n", .{}); + + // 3. Reset the I2C + regs.I2C1.CR1.modify(.{ .PE = 0 }); + while (regs.I2C1.CR1.read().PE == 1) {} + // DO NOT regs.RCC.APB1RSTR.modify(.{ .I2C1RST = 1 }); + debugPrint("I2C1 configuration step 3 complete\r\n", .{}); + + // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz + // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/ + // but copying an example from the reference manual, RM0316 section 28.4.9.) + regs.I2C1.TIMINGR.modify(.{ + .PRESC = 1, + .SCLL = 0x13, + .SCLH = 0xF, + .SDADEL = 0x2, + .SCLDEL = 0x4, + }); + debugPrint("I2C1 configuration steps 4-6 complete\r\n", .{}); + + // 7. Program the I2C_CR1 register to enable the peripheral + regs.I2C1.CR1.modify(.{ .PE = 1 }); + debugPrint("I2C1 configuration step 7 complete\r\n", .{}); + + return Self{}; + } + + pub const WriteState = struct { + address: u7, + buffer: [255]u8 = undefined, + buffer_size: u8 = 0, + + pub fn start(address: u7) !WriteState { + return WriteState{ .address = address }; + } + + pub fn writeAll(self: *WriteState, bytes: []const u8) !void { + debugPrint("I2C1 writeAll() with {d} byte(s); buffer={any}\r\n", .{ bytes.len, self.buffer[0..self.buffer_size] }); + + std.debug.assert(self.buffer_size < 255); + for (bytes) |b| { + self.buffer[self.buffer_size] = b; + self.buffer_size += 1; + if (self.buffer_size == 255) { + try self.sendBuffer(1); + } + } + } + + fn sendBuffer(self: *WriteState, reload: u1) !void { + debugPrint("I2C1 sendBuffer() with {d} byte(s); RELOAD={d}; buffer={any}\r\n", .{ self.buffer_size, reload, self.buffer[0..self.buffer_size] }); + if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); + + std.debug.assert(reload == 0 or self.buffer_size == 255); // see TODOs below + + // As master, initiate write from address, 7 bit address + regs.I2C1.CR2.modify(.{ + .ADD10 = 0, + .SADD1 = self.address, + .RD_WRN = 0, // write + .NBYTES = self.buffer_size, + .RELOAD = reload, + }); + if (reload == 0) { + regs.I2C1.CR2.modify(.{ .START = 1 }); + } else { + // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, + // even though we make sure that we set NBYTES=255 per the docs. + } + for (self.buffer[0..self.buffer_size]) |b| { + // wait for empty transmit buffer + while (regs.I2C1.ISR.read().TXE == 0) { + debugPrint("I2C1 waiting for ready to send (TXE=0)\r\n", .{}); + } + debugPrint("I2C1 ready to send (TXE=1)\r\n", .{}); + // Write data byte + regs.I2C1.TXDR.modify(.{ .TXDATA = b }); + } + self.buffer_size = 0; + debugPrint("I2C1 data written\r\n", .{}); + if (reload == 1) { + // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, + // the following loop never seems to finish. + while (regs.I2C1.ISR.read().TCR == 0) { + debugPrint("I2C1 waiting transmit complete (TCR=0)\r\n", .{}); + } + debugPrint("I2C1 transmit complete (TCR=1)\r\n", .{}); + } else { + while (regs.I2C1.ISR.read().TC == 0) { + debugPrint("I2C1 waiting for transmit complete (TC=0)\r\n", .{}); + } + debugPrint("I2C1 transmit complete (TC=1)\r\n", .{}); + } + } + + pub fn stop(self: *WriteState) !void { + try self.sendBuffer(0); + // Communication STOP + debugPrint("I2C1 STOPping\r\n", .{}); + regs.I2C1.CR2.modify(.{ .STOP = 1 }); + while (regs.I2C1.ISR.read().BUSY == 1) {} + debugPrint("I2C1 STOPped\r\n", .{}); + } + + pub fn restartRead(self: *WriteState) !ReadState { + try self.sendBuffer(0); + return ReadState{ .address = self.address }; + } + pub fn restartWrite(self: *WriteState) !WriteState { + try self.sendBuffer(0); + return WriteState{ .address = self.address }; + } + }; + + pub const ReadState = struct { + address: u7, + read_allowed: if (runtime_safety) bool else void = if (runtime_safety) true else {}, + + pub fn start(address: u7) !ReadState { + return ReadState{ .address = address }; + } + + /// Fails with ReadError if incorrect number of bytes is received. + pub fn readNoEof(self: *ReadState, buffer: []u8) !void { + if (runtime_safety and !self.read_allowed) @panic("second read call not allowed"); + std.debug.assert(buffer.len < 256); // TODO: use RELOAD to read more data + + // As master, initiate read from accelerometer, 7 bit address + regs.I2C1.CR2.modify(.{ + .ADD10 = 0, + .SADD1 = self.address, + .RD_WRN = 1, // read + .NBYTES = @intCast(u8, buffer.len), + }); + debugPrint("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address }); + + // Communication START + regs.I2C1.CR2.modify(.{ .START = 1 }); + debugPrint("I2C1 RXNE={}\r\n", .{regs.I2C1.ISR.read().RXNE}); + debugPrint("I2C1 STARTed\r\n", .{}); + debugPrint("I2C1 RXNE={}\r\n", .{regs.I2C1.ISR.read().RXNE}); + + if (runtime_safety) self.read_allowed = false; + + for (buffer) |_, i| { + // Wait for data to be received + while (regs.I2C1.ISR.read().RXNE == 0) { + debugPrint("I2C1 waiting for data (RXNE=0)\r\n", .{}); + } + debugPrint("I2C1 data ready (RXNE=1)\r\n", .{}); + + // Read first data byte + buffer[i] = regs.I2C1.RXDR.read().RXDATA; + } + debugPrint("I2C1 data: {any}\r\n", .{buffer}); + } + + pub fn stop(_: *ReadState) !void { + // Communication STOP + regs.I2C1.CR2.modify(.{ .STOP = 1 }); + while (regs.I2C1.ISR.read().BUSY == 1) {} + debugPrint("I2C1 STOPped\r\n", .{}); + } + + pub fn restartRead(self: *ReadState) !ReadState { + debugPrint("I2C1 no action for restart\r\n", .{}); + return ReadState{ .address = self.address }; + } + pub fn restartWrite(self: *ReadState) !WriteState { + debugPrint("I2C1 no action for restart\r\n", .{}); + return WriteState{ .address = self.address }; + } + }; + }; +} From 97733da9e2a7975529220089ff27193203e6925e Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Tue, 29 Mar 2022 07:40:34 +0200 Subject: [PATCH 042/138] Add initial support for the stm32f4discovery eval board (#35) * Add stm32f407 registers Generated using regz with: ./regz STM32F407.svd > registers.zig Using this SVD: https://github.com/posborne/cmsis-svd/blob/871761af63200f5edad553b03fe0482113ac6a60/data/STMicro/STM32F407.svd * Add initial support for the stm32f4discovery eval board The blinky example is working on the board --- build.zig | 1 + src/modules/boards.zig | 6 + .../stm32f4discovery/stm32f4discovery.zig | 19 + src/modules/chips.zig | 12 + src/modules/chips/stm32f407/registers.zig | 52845 ++++++++++++++++ src/modules/chips/stm32f407/stm32f407.zig | 79 + tests/blinky.zig | 1 + 7 files changed, 52963 insertions(+) create mode 100644 src/modules/boards/stm32f4discovery/stm32f4discovery.zig create mode 100644 src/modules/chips/stm32f407/registers.zig create mode 100644 src/modules/chips/stm32f407/stm32f407.zig diff --git a/build.zig b/build.zig index 773efc6..bb60c58 100644 --- a/build.zig +++ b/build.zig @@ -22,6 +22,7 @@ pub fn build(b: *std.build.Builder) !void { BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, + BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery }, .supports_uart_test = false }, }; const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true }; diff --git a/src/modules/boards.zig b/src/modules/boards.zig index e0ce389..954cd4b 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -25,3 +25,9 @@ pub const stm32f3discovery = Board{ .path = root_path ++ "boards/stm32f3discovery/stm32f3discovery.zig", .chip = chips.stm32f303vc, }; + +pub const stm32f4discovery = Board{ + .name = "STM32F4DISCOVERY", + .path = root_path ++ "boards/stm32f4discovery/stm32f4discovery.zig", + .chip = chips.stm32f407vg, +}; diff --git a/src/modules/boards/stm32f4discovery/stm32f4discovery.zig b/src/modules/boards/stm32f4discovery/stm32f4discovery.zig new file mode 100644 index 0000000..8fdf824 --- /dev/null +++ b/src/modules/boards/stm32f4discovery/stm32f4discovery.zig @@ -0,0 +1,19 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 16_000_000; + +pub const pin_map = .{ + // LED cross, connected to GPIOD bits 12..15 + // N orange + .@"LD3" = "PD13", + // E red + .@"LD5" = "PD14", + // S blue + .@"LD6" = "PD15", + // W green + .@"LD4" = "PD12", + + // User button + .@"B2" = "PA0", +}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 7058431..52504d5 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -50,6 +50,18 @@ pub const stm32f303vc = Chip{ }, }; +pub const stm32f407vg = Chip{ + .name = "STM32F407VG", + .path = root_path ++ "chips/stm32f407/stm32f407.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram }, + // CCM RAM + MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, + }, +}; + pub const nrf52832 = Chip{ .name = "nRF52832", .path = root_path ++ "chips/nrf52/nrf52.zig", diff --git a/src/modules/chips/stm32f407/registers.zig b/src/modules/chips/stm32f407/registers.zig new file mode 100644 index 0000000..7e08713 --- /dev/null +++ b/src/modules/chips/stm32f407/registers.zig @@ -0,0 +1,52845 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 6376709051af4d8920d5c8bb48945ca688af32ae +// +// device: STM32F407 +// cpu: CM4 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + /// Window Watchdog interrupt + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, + /// Tamper and TimeStamp interrupts through the + /// EXTI line + TAMP_STAMP: InterruptVector = unhandled, + /// RTC Wakeup interrupt through the EXTI + /// line + RTC_WKUP: InterruptVector = unhandled, + reserved2: u32 = undefined, + /// RCC global interrupt + RCC: InterruptVector = unhandled, + /// EXTI Line0 interrupt + EXTI0: InterruptVector = unhandled, + /// EXTI Line1 interrupt + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 interrupt + EXTI2: InterruptVector = unhandled, + /// EXTI Line3 interrupt + EXTI3: InterruptVector = unhandled, + /// EXTI Line4 interrupt + EXTI4: InterruptVector = unhandled, + /// DMA1 Stream0 global interrupt + DMA1_Stream0: InterruptVector = unhandled, + /// DMA1 Stream1 global interrupt + DMA1_Stream1: InterruptVector = unhandled, + /// DMA1 Stream2 global interrupt + DMA1_Stream2: InterruptVector = unhandled, + /// DMA1 Stream3 global interrupt + DMA1_Stream3: InterruptVector = unhandled, + /// DMA1 Stream4 global interrupt + DMA1_Stream4: InterruptVector = unhandled, + /// DMA1 Stream5 global interrupt + DMA1_Stream5: InterruptVector = unhandled, + /// DMA1 Stream6 global interrupt + DMA1_Stream6: InterruptVector = unhandled, + /// ADC1 global interrupt + ADC: InterruptVector = unhandled, + /// CAN1 TX interrupts + CAN1_TX: InterruptVector = unhandled, + /// CAN1 RX0 interrupts + CAN1_RX0: InterruptVector = unhandled, + /// CAN1 RX1 interrupts + CAN1_RX1: InterruptVector = unhandled, + /// CAN1 SCE interrupt + CAN1_SCE: InterruptVector = unhandled, + /// EXTI Line[9:5] interrupts + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break interrupt and TIM9 global + /// interrupt + TIM1_BRK_TIM9: InterruptVector = unhandled, + /// TIM1 Update interrupt and TIM10 global + /// interrupt + TIM1_UP_TIM10: InterruptVector = unhandled, + /// TIM1 Trigger and Commutation interrupts and + /// TIM11 global interrupt + TIM1_TRG_COM_TIM11: InterruptVector = unhandled, + /// TIM1 Capture Compare interrupt + TIM1_CC: InterruptVector = unhandled, + /// TIM2 global interrupt + TIM2: InterruptVector = unhandled, + /// TIM3 global interrupt + TIM3: InterruptVector = unhandled, + /// TIM4 global interrupt + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt + I2C1_EV: InterruptVector = unhandled, + /// I2C1 error interrupt + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt + I2C2_EV: InterruptVector = unhandled, + /// I2C2 error interrupt + I2C2_ER: InterruptVector = unhandled, + /// SPI1 global interrupt + SPI1: InterruptVector = unhandled, + /// SPI2 global interrupt + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt + USART1: InterruptVector = unhandled, + /// USART2 global interrupt + USART2: InterruptVector = unhandled, + /// USART3 global interrupt + USART3: InterruptVector = unhandled, + /// EXTI Line[15:10] interrupts + EXTI15_10: InterruptVector = unhandled, + /// RTC Alarms (A and B) through EXTI line + /// interrupt + RTC_Alarm: InterruptVector = unhandled, + /// USB On-The-Go FS Wakeup through EXTI line + /// interrupt + OTG_FS_WKUP: InterruptVector = unhandled, + /// TIM8 Break interrupt and TIM12 global + /// interrupt + TIM8_BRK_TIM12: InterruptVector = unhandled, + /// TIM8 Update interrupt and TIM13 global + /// interrupt + TIM8_UP_TIM13: InterruptVector = unhandled, + /// TIM8 Trigger and Commutation interrupts and + /// TIM14 global interrupt + TIM8_TRG_COM_TIM14: InterruptVector = unhandled, + /// TIM8 Capture Compare interrupt + TIM8_CC: InterruptVector = unhandled, + /// DMA1 Stream7 global interrupt + DMA1_Stream7: InterruptVector = unhandled, + /// FSMC global interrupt + FSMC: InterruptVector = unhandled, + /// SDIO global interrupt + SDIO: InterruptVector = unhandled, + /// TIM5 global interrupt + TIM5: InterruptVector = unhandled, + /// SPI3 global interrupt + SPI3: InterruptVector = unhandled, + /// UART4 global interrupt + UART4: InterruptVector = unhandled, + /// UART5 global interrupt + UART5: InterruptVector = unhandled, + /// TIM6 global interrupt, DAC1 and DAC2 underrun + /// error interrupt + TIM6_DAC: InterruptVector = unhandled, + /// TIM7 global interrupt + TIM7: InterruptVector = unhandled, + /// DMA2 Stream0 global interrupt + DMA2_Stream0: InterruptVector = unhandled, + /// DMA2 Stream1 global interrupt + DMA2_Stream1: InterruptVector = unhandled, + /// DMA2 Stream2 global interrupt + DMA2_Stream2: InterruptVector = unhandled, + /// DMA2 Stream3 global interrupt + DMA2_Stream3: InterruptVector = unhandled, + /// DMA2 Stream4 global interrupt + DMA2_Stream4: InterruptVector = unhandled, + /// Ethernet global interrupt + ETH: InterruptVector = unhandled, + /// Ethernet Wakeup through EXTI line + /// interrupt + ETH_WKUP: InterruptVector = unhandled, + /// CAN2 TX interrupts + CAN2_TX: InterruptVector = unhandled, + /// CAN2 RX0 interrupts + CAN2_RX0: InterruptVector = unhandled, + /// CAN2 RX1 interrupts + CAN2_RX1: InterruptVector = unhandled, + /// CAN2 SCE interrupt + CAN2_SCE: InterruptVector = unhandled, + /// USB On The Go FS global + /// interrupt + OTG_FS: InterruptVector = unhandled, + /// DMA2 Stream5 global interrupt + DMA2_Stream5: InterruptVector = unhandled, + /// DMA2 Stream6 global interrupt + DMA2_Stream6: InterruptVector = unhandled, + /// DMA2 Stream7 global interrupt + DMA2_Stream7: InterruptVector = unhandled, + /// USART6 global interrupt + USART6: InterruptVector = unhandled, + /// I2C3 event interrupt + I2C3_EV: InterruptVector = unhandled, + /// I2C3 error interrupt + I2C3_ER: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 Out global + /// interrupt + OTG_HS_EP1_OUT: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 In global + /// interrupt + OTG_HS_EP1_IN: InterruptVector = unhandled, + /// USB On The Go HS Wakeup through EXTI + /// interrupt + OTG_HS_WKUP: InterruptVector = unhandled, + /// USB On The Go HS global + /// interrupt + OTG_HS: InterruptVector = unhandled, + /// DCMI global interrupt + DCMI: InterruptVector = unhandled, + /// CRYP crypto global interrupt + CRYP: InterruptVector = unhandled, + /// Hash and Rng global interrupt + HASH_RNG: InterruptVector = unhandled, + /// FPU interrupt + FPU: InterruptVector = unhandled, + reserved3: u32 = undefined, + reserved4: u32 = undefined, + reserved5: u32 = undefined, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + reserved8: u32 = undefined, + /// LTDC global interrupt + LCD_TFT: InterruptVector = unhandled, + /// LTDC global error interrupt + LCD_TFT_1: InterruptVector = unhandled, +}; + +pub const registers = struct { + + /// Random number generator + pub const RNG = struct { + pub const base_address = 0x50060800; + + /// address: 0x50060800 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Random number generator + /// enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x0); + + /// address: 0x50060804 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved0: u1, + reserved1: u1, + /// Clock error interrupt + /// status + CEIS: u1, + /// Seed error interrupt + /// status + SEIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x50060808 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Random data + RNDATA: u32, + }), base_address + 0x8); + }; + + /// Digital camera interface + pub const DCMI = struct { + pub const base_address = 0x50050000; + + /// address: 0x50050000 + /// control register 1 + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization + /// select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization + /// polarity + HSPOL: u1, + /// Vertical synchronization + /// polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved0: u1, + reserved1: u1, + /// DCMI enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x0); + + /// address: 0x50050004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0x50050008 + /// raw interrupt status register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete raw interrupt + /// status + FRAME_RIS: u1, + /// Overrun raw interrupt + /// status + OVR_RIS: u1, + /// Synchronization error raw interrupt + /// status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x8); + + /// address: 0x5005000c + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt + /// enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt + /// enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xc); + + /// address: 0x50050010 + /// masked interrupt status + /// register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete masked interrupt + /// status + FRAME_MIS: u1, + /// Overrun masked interrupt + /// status + OVR_MIS: u1, + /// Synchronization error masked interrupt + /// status + ERR_MIS: u1, + /// VSYNC masked interrupt + /// status + VSYNC_MIS: u1, + /// Line masked interrupt + /// status + LINE_MIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0x50050014 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt status + /// clear + FRAME_ISC: u1, + /// Overrun interrupt status + /// clear + OVR_ISC: u1, + /// Synchronization error interrupt status + /// clear + ERR_ISC: u1, + /// Vertical synch interrupt status + /// clear + VSYNC_ISC: u1, + /// line interrupt status + /// clear + LINE_ISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50050018 + /// embedded synchronization code + /// register + pub const ESCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), base_address + 0x18); + + /// address: 0x5005001c + /// embedded synchronization unmask + /// register + pub const ESUR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter + /// unmask + FSU: u8, + /// Line start delimiter + /// unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), base_address + 0x1c); + + /// address: 0x50050020 + /// crop window start + pub const CWSTRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Horizontal offset count + HOFFCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical start line count + VST: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x50050024 + /// crop window size + pub const CWSIZE = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture count + CAPCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical line count + VLINE: u14, + padding0: u1, + padding1: u1, + }), base_address + 0x24); + + /// address: 0x50050028 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), base_address + 0x28); + }; + + /// Flexible static memory controller + pub const FSMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000000c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000010 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000014 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000018 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000001c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000060 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000064 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000068 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000006c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000074 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000080 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000084 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000088 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000008c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000094 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00000a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00000a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00000a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00000ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00000b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000114 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x114); + + /// address: 0xa000011c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x11c); + }; + + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// IDCODE + pub const DBGMCU_IDCODE = @intToPtr(*volatile Mmio(32, packed struct { + /// DEV_ID + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// REV_ID + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Control Register + pub const DBGMCU_CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_TIM8_STOP + DBG_TIM8_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x4); + + /// address: 0xe0042008 + /// Debug MCU APB1 Freeze registe + pub const DBGMCU_APB1_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3 _STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_TIM12_STOP + DBG_TIM12_STOP: u1, + /// DBG_TIM13_STOP + DBG_TIM13_STOP: u1, + /// DBG_TIM14_STOP + DBG_TIM14_STOP: u1, + reserved0: u1, + reserved1: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_IWDEG_STOP + DBG_IWDEG_STOP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT: u1, + /// DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT: u1, + /// DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT: u1, + reserved10: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8); + + /// address: 0xe004200c + /// Debug MCU APB2 Freeze registe + pub const DBGMCU_APB2_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 counter stopped when core is + /// halted + DBG_TIM1_STOP: u1, + /// TIM8 counter stopped when core is + /// halted + DBG_TIM8_STOP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TIM9 counter stopped when core is + /// halted + DBG_TIM9_STOP: u1, + /// TIM10 counter stopped when core is + /// halted + DBG_TIM10_STOP: u1, + /// TIM11 counter stopped when core is + /// halted + DBG_TIM11_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + }; + + /// DMA controller + pub const DMA2 = struct { + pub const base_address = 0x40026400; + + /// address: 0x40026400 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026404 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026408 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002640c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026410 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026414 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026418 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002641c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026420 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026424 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026428 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002642c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026430 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026434 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026438 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002643c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026440 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026444 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026448 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002644c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026450 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026454 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026458 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002645c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026460 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026464 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026468 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002646c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026470 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026474 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026478 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002647c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026480 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026484 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026488 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002648c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026490 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026494 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026498 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002649c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400264a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400264a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400264a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400264ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400264b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400264b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400264b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400264bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400264c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400264c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400264c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400264cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + pub const DMA1 = struct { + pub const base_address = 0x40026000; + + /// address: 0x40026000 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026004 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026008 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002600c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026010 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026014 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026018 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002601c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026020 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026024 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026028 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002602c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026030 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026034 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026038 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002603c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026040 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026044 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026048 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002604c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026050 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026054 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026058 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002605c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026060 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026064 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026068 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002606c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026070 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026074 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026078 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002607c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026080 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026084 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026088 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002608c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026090 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026094 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026098 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002609c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400260a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400260a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400260a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400260ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400260b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400260b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400260b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400260bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400260c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400260c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400260c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400260cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40023800; + + /// address: 0x40023800 + /// clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal high-speed clock + /// enable + HSION: u1, + /// Internal high-speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal high-speed clock + /// trimming + HSITRIM: u5, + /// Internal high-speed clock + /// calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready + /// flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40023804 + /// PLL configuration register + pub const PLLCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM0: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM1: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM2: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM3: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM4: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN0: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN1: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN2: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN3: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN4: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN6: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN7: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN8: u1, + reserved0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL(PLL) and audio PLL (PLLI2S) + /// entry clock source + PLLSRC: u1, + reserved5: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ0: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ1: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ2: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40023808 + /// clock configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// System clock switch + SW0: u1, + /// System clock switch + SW1: u1, + /// System clock switch status + SWS0: u1, + /// System clock switch status + SWS1: u1, + /// AHB prescaler + HPRE: u4, + reserved0: u1, + reserved1: u1, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB high-speed prescaler + /// (APB2) + PPRE2: u3, + /// HSE division factor for RTC + /// clock + RTCPRE: u5, + /// Microcontroller clock output + /// 1 + MCO1: u2, + /// I2S clock selection + I2SSRC: u1, + /// MCO1 prescaler + MCO1PRE: u3, + /// MCO2 prescaler + MCO2PRE: u3, + /// Microcontroller clock output + /// 2 + MCO2: u2, + }), base_address + 0x8); + + /// address: 0x4002380c + /// clock interrupt register + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt + /// flag + PLLRDYF: u1, + /// PLLI2S ready interrupt + /// flag + PLLI2SRDYF: u1, + reserved0: u1, + /// Clock security system interrupt + /// flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt + /// enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt + /// enable + PLLI2SRDYIE: u1, + reserved1: u1, + reserved2: u1, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt + /// clear + PLLRDYC: u1, + /// PLLI2S ready interrupt + /// clear + PLLI2SRDYC: u1, + reserved3: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40023810 + /// AHB1 peripheral reset register + pub const AHB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC reset + CRCRST: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved11: u1, + reserved12: u1, + /// Ethernet MAC reset + ETHMACRST: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// USB OTG HS module reset + OTGHSRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40023814 + /// AHB2 peripheral reset register + pub const AHB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface reset + DCMIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Random number generator module + /// reset + RNGRST: u1, + /// USB OTG FS module reset + OTGFSRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40023818 + /// AHB3 peripheral reset register + pub const AHB3RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible static memory controller module + /// reset + FSMCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x18); + + /// address: 0x40023820 + /// APB1 peripheral reset register + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved2: u1, + reserved3: u1, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved4: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved5: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved6: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40023824 + /// APB2 peripheral reset register + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved0: u1, + reserved1: u1, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved2: u1, + reserved3: u1, + /// ADC interface reset (common to all + /// ADCs) + ADCRST: u1, + reserved4: u1, + reserved5: u1, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved6: u1, + /// System configuration controller + /// reset + SYSCFGRST: u1, + reserved7: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0x40023830 + /// AHB1 peripheral clock register + pub const AHB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable + CRCEN: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Backup SRAM interface clock + /// enable + BKPSRAMEN: u1, + reserved8: u1, + reserved9: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved10: u1, + reserved11: u1, + /// Ethernet MAC clock enable + ETHMACEN: u1, + /// Ethernet Transmission clock + /// enable + ETHMACTXEN: u1, + /// Ethernet Reception clock + /// enable + ETHMACRXEN: u1, + /// Ethernet PTP clock enable + ETHMACPTPEN: u1, + /// USB OTG HS clock enable + OTGHSEN: u1, + /// USB OTG HSULPI clock + /// enable + OTGHSULPIEN: u1, + padding0: u1, + }), base_address + 0x30); + + /// address: 0x40023834 + /// AHB2 peripheral clock enable + /// register + pub const AHB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable + DCMIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Random number generator clock + /// enable + RNGEN: u1, + /// USB OTG FS clock enable + OTGFSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x34); + + /// address: 0x40023838 + /// AHB3 peripheral clock enable + /// register + pub const AHB3ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible static memory controller module + /// clock enable + FSMCEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x38); + + /// address: 0x40023840 + /// APB1 peripheral clock enable + /// register + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved4: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved5: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved6: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x40); + + /// address: 0x40023844 + /// APB2 peripheral clock enable + /// register + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable + SYSCFGEN: u1, + reserved5: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x44); + + /// address: 0x40023850 + /// AHB1 peripheral clock enable in low power + /// mode register + pub const AHB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable during sleep + /// mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep + /// mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep + /// mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep + /// mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep + /// mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep + /// mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep + /// mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep + /// mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep + /// mode + GPIOILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable during Sleep + /// mode + CRCLPEN: u1, + reserved3: u1, + reserved4: u1, + /// Flash interface clock enable during + /// Sleep mode + FLITFLPEN: u1, + /// SRAM 1interface clock enable during + /// Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during + /// Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable + /// during Sleep mode + BKPSRAMLPEN: u1, + reserved5: u1, + reserved6: u1, + /// DMA1 clock enable during Sleep + /// mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep + /// mode + DMA2LPEN: u1, + reserved7: u1, + reserved8: u1, + /// Ethernet MAC clock enable during Sleep + /// mode + ETHMACLPEN: u1, + /// Ethernet transmission clock enable + /// during Sleep mode + ETHMACTXLPEN: u1, + /// Ethernet reception clock enable during + /// Sleep mode + ETHMACRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep + /// mode + ETHMACPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep + /// mode + OTGHSLPEN: u1, + /// USB OTG HS ULPI clock enable during + /// Sleep mode + OTGHSULPILPEN: u1, + padding0: u1, + }), base_address + 0x50); + + /// address: 0x40023854 + /// AHB2 peripheral clock enable in low power + /// mode register + pub const AHB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable during Sleep + /// mode + DCMILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Random number generator clock enable + /// during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep + /// mode + OTGFSLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40023858 + /// AHB3 peripheral clock enable in low power + /// mode register + pub const AHB3LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible static memory controller module + /// clock enable during Sleep mode + FSMCLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x58); + + /// address: 0x40023860 + /// APB1 peripheral clock enable in low power + /// mode register + pub const APB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable during Sleep + /// mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep + /// mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep + /// mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep + /// mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep + /// mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep + /// mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep + /// mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep + /// mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep + /// mode + TIM14LPEN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock enable during + /// Sleep mode + WWDGLPEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable during Sleep + /// mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep + /// mode + SPI3LPEN: u1, + reserved4: u1, + /// USART2 clock enable during Sleep + /// mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep + /// mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep + /// mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep + /// mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep + /// mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep + /// mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep + /// mode + I2C3LPEN: u1, + reserved5: u1, + /// CAN 1 clock enable during Sleep + /// mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep + /// mode + CAN2LPEN: u1, + reserved6: u1, + /// Power interface clock enable during + /// Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep + /// mode + DACLPEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x60); + + /// address: 0x40023864 + /// APB2 peripheral clock enabled in low power + /// mode register + pub const APB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable during Sleep + /// mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep + /// mode + TIM8LPEN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable during Sleep + /// mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep + /// mode + USART6LPEN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable during Sleep + /// mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep + /// mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep + /// mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep + /// mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep + /// mode + SPI1LPEN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable during Sleep mode + SYSCFGLPEN: u1, + reserved5: u1, + /// TIM9 clock enable during sleep + /// mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep + /// mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep + /// mode + TIM11LPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x64); + + /// address: 0x40023870 + /// Backup domain control register + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// External low-speed oscillator + /// enable + LSEON: u1, + /// External low-speed oscillator + /// ready + LSERDY: u1, + /// External low-speed oscillator + /// bypass + LSEBYP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock source selection + RTCSEL0: u1, + /// RTC clock source selection + RTCSEL1: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x70); + + /// address: 0x40023874 + /// clock control & status + /// register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal low-speed oscillator + /// enable + LSION: u1, + /// Internal low-speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x74); + + /// address: 0x40023880 + /// spread spectrum clock generation + /// register + pub const SSCGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved0: u1, + reserved1: u1, + /// Spread Select + SPREADSEL: u1, + /// Spread spectrum modulation + /// enable + SSCGEN: u1, + }), base_address + 0x80); + + /// address: 0x40023884 + /// PLLI2S configuration register + pub const PLLI2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// PLLI2S multiplication factor for + /// VCO + PLLI2SNx: u9, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// PLLI2S division factor for I2S + /// clocks + PLLI2SRx: u3, + padding0: u1, + }), base_address + 0x84); + }; + + /// General-purpose I/Os + pub const GPIOI = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002200c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002201c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOH = struct { + pub const base_address = 0x40021c00; + + /// address: 0x40021c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40021c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40021c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOG = struct { + pub const base_address = 0x40021800; + + /// address: 0x40021800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002180c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002181c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOF = struct { + pub const base_address = 0x40021400; + + /// address: 0x40021400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002140c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002141c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOE = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002100c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOD = struct { + pub const base_address = 0x40020c00; + + /// address: 0x40020c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40020c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40020c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOC = struct { + pub const base_address = 0x40020800; + + /// address: 0x40020800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002080c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002081c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOJ = struct { + pub const base_address = 0x40022400; + + /// address: 0x40022400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002240c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002241c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOK = struct { + pub const base_address = 0x40022800; + + /// address: 0x40022800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002280c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002281c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOB = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002040c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002041c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002000c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002001c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// System configuration controller + pub const SYSCFG = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// memory remap register + pub const MEMRM = @intToPtr(*volatile Mmio(32, packed struct { + /// MEM_MODE + MEM_MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// peripheral mode configuration + /// register + pub const PMC = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// Ethernet PHY interface + /// selection + MII_RMII_SEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013808 + /// external interrupt configuration register + /// 1 + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 0 to + /// 3) + EXTI0: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI1: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI2: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// external interrupt configuration register + /// 2 + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 4 to + /// 7) + EXTI4: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI5: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI6: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// external interrupt configuration register + /// 3 + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 8 to + /// 11) + EXTI8: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI9: u4, + /// EXTI10 + EXTI10: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// external interrupt configuration register + /// 4 + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 12 to + /// 15) + EXTI12: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI13: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI14: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013820 + /// Compensation cell control + /// register + pub const CMPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Compensation cell + /// power-down + CMP_PD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// READY + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x20); + }; + + /// Serial peripheral interface + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S2ext = struct { + pub const base_address = 0x40003400; + + /// address: 0x40003400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S3ext = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40004004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40004008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000400c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40004010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40004018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000401c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40004020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI4 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI5 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001500c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001501c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI6 = struct { + pub const base_address = 0x40015400; + + /// address: 0x40015400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001540c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001541c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + + /// Secure digital input/output + /// interface + pub const SDIO = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// power control register + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { + /// PWRCTRL + PWRCTRL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// SDI clock control register + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration + /// bit + PWRSAV: u1, + /// Clock divider bypass enable + /// bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection + /// bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// argument register + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { + /// Command argument + CMDARG: u32, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// command register + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt + /// request + WAITINT: u1, + /// CPSM Waits for ends of data transfer + /// (CmdPend internal signal). + WAITPEND: u1, + /// Command path state machine (CPSM) Enable + /// bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + /// Enable CMD completion + ENCMDcompl: u1, + /// not Interrupt Enable + nIEN: u1, + /// CE-ATA command + CE_ATACMD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// command response register + pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40012c14 + /// response 1..4 register + pub const RESP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS1: u32, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// response 1..4 register + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS2: u32, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// response 1..4 register + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS3: u32, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// response 1..4 register + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS4: u32, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// data timer register + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { + /// Data timeout period + DATATIME: u32, + }), base_address + 0x24); + + /// address: 0x40012c28 + /// data length register + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length value + DATALENGTH: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0x40012c2c + /// data control register + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DTEN + DTEN: u1, + /// Data transfer direction + /// selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream + /// or SDIO multibyte data transfer. + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40012c30 + /// data counter register + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data count value + DATACOUNT: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + + /// address: 0x40012c34 + /// status register + pub const STA = @intToPtr(*volatile Mmio(32, packed struct { + /// Command response received (CRC check + /// failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check + /// failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun + /// error + TXUNDERR: u1, + /// Received FIFO overrun + /// error + RXOVERR: u1, + /// Command response received (CRC check + /// passed) + CMDREND: u1, + /// Command sent (no response + /// required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is + /// zero) + DATAEND: u1, + /// Start bit not detected on all data + /// signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check + /// passed) + DBCKEND: u1, + /// Command transfer in + /// progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 + /// words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at + /// least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit + /// FIFO + TXDAVL: u1, + /// Data available in receive + /// FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + /// CE-ATA command completion signal + /// received for CMD61 + CEATAEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x40012c38 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// SDIOIT flag clear bit + SDIOITC: u1, + /// CEATAEND flag clear bit + CEATAENDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x38); + + /// address: 0x40012c3c + /// mask register + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// Command CRC fail interrupt + /// enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt + /// enable + DCRCFAILIE: u1, + /// Command timeout interrupt + /// enable + CTIMEOUTIE: u1, + /// Data timeout interrupt + /// enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt + /// enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt + /// enable + RXOVERRIE: u1, + /// Command response received interrupt + /// enable + CMDRENDIE: u1, + /// Command sent interrupt + /// enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// Start bit error interrupt + /// enable + STBITERRIE: u1, + /// Data block end interrupt + /// enable + DBCKENDIE: u1, + /// Command acting interrupt + /// enable + CMDACTIE: u1, + /// Data transmit acting interrupt + /// enable + TXACTIE: u1, + /// Data receive acting interrupt + /// enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt + /// enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt + /// enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt + /// enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt + /// enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt + /// enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt + /// enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt + /// enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt + /// enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt + /// enable + SDIOITIE: u1, + /// CE-ATA command completion signal + /// received interrupt enable + CEATAENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x40012c48 + /// FIFO counter register + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Remaining number of words to be written + /// to or read from the FIFO. + FIFOCOUNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x40012c80 + /// data FIFO register + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive and transmit FIFO + /// data + FIFOData: u32, + }), base_address + 0x80); + }; + + /// Analog-to-digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012004 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012008 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001200c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012010 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012014 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012018 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001201c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012020 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012024 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012028 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001202c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012030 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012034 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012038 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001203c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012040 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012044 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012048 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001204c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC2 = struct { + pub const base_address = 0x40012100; + + /// address: 0x40012100 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012104 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012108 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001210c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012110 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012114 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012118 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001211c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012120 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012124 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012128 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001212c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012130 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012134 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012138 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001213c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012140 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012144 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012148 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001214c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC3 = struct { + pub const base_address = 0x40012200; + + /// address: 0x40012200 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012204 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012208 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001220c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012210 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012214 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012218 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001221c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012220 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012224 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012228 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001222c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012230 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012234 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012238 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001223c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012240 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012244 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012248 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001224c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART6 = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART1 = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt + /// enable + DMAUDRIE1: u1, + reserved0: u1, + reserved1: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt + /// enable + DMAUDRIE2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// channel1 12-bit right-aligned data holding + /// register + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// channel1 12-bit left aligned data holding + /// register + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// channel1 8-bit right aligned data holding + /// register + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// channel2 12-bit right aligned data holding + /// register + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// channel2 12-bit left aligned data holding + /// register + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// channel2 8-bit right-aligned data holding + /// register + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// channel1 data output register + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// channel2 data output register + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x40007434 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// DAC channel1 DMA underrun + /// flag + DMAUDR1: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + /// DAC channel2 DMA underrun + /// flag + DMAUDR2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + }; + + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector + /// enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write + /// protection + DBP: u1, + /// Flash power down in Stop + /// mode + FPDS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Regulator voltage scaling output + /// selection ready bit + VOSRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + }; + + /// Inter-integrated circuit + pub const I2C3 = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005c14 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c20 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + }; + + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register + pub const KR = @intToPtr(*volatile Mmio(32, packed struct { + /// Key value (write only, read + /// 0000h) + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB0: u1, + /// Timer base + WDGTB1: u1, + /// Early wakeup interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// time register + pub const TR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// date register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active + /// edge + TSEDGE: u1, + /// Reference clock detection enable (50 or + /// 60 Hz) + REFCKON: u1, + reserved0: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration + /// enable + DCE: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt + /// enable + WUTIE: u1, + /// Time-stamp interrupt + /// enable + TSIE: u1, + /// Add 1 hour (summer time + /// change) + ADD1H: u1, + /// Subtract 1 hour (winter time + /// change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved1: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// initialization and status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization + /// flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// TAMPER2 detection flag + TAMP2F: u1, + reserved0: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// prescaler register + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { + /// Synchronous prescaler + /// factor + PREDIV_S: u15, + reserved0: u1, + /// Asynchronous prescaler + /// factor + PREDIV_A: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// wakeup timer register + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup auto-reload value + /// bits + WUT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// calibration register + pub const CALIBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital calibration + DC: u5, + reserved0: u1, + reserved1: u1, + /// Digital calibration sign + DCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x4000281c + /// alarm A register + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// alarm B register + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// write protection register + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write protection key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40002828 + /// sub second register + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000282c + /// shift control register + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Subtract a fraction of a + /// second + SUBFS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Add one second + ADD1S: u1, + }), base_address + 0x2c); + + /// address: 0x40002830 + /// time stamp time register + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x30); + + /// address: 0x40002834 + /// time stamp date register + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// timestamp sub second register + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x38); + + /// address: 0x4000283c + /// calibration register + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration minus + CALM: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Use a 16-second calibration cycle + /// period + CALW16: u1, + /// Use an 8-second calibration cycle + /// period + CALW8: u1, + /// Increase frequency of RTC by 488.5 + /// ppm + CALP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40002840 + /// tamper and alternate function configuration + /// register + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + reserved0: u1, + reserved1: u1, + /// Activate timestamp on tamper detection + /// event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40002844 + /// alarm A sub second register + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x44); + + /// address: 0x40002848 + /// alarm B sub second register + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x48); + + /// address: 0x40002850 + /// backup register + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x50); + + /// address: 0x40002854 + /// backup register + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x54); + + /// address: 0x40002858 + /// backup register + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x58); + + /// address: 0x4000285c + /// backup register + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x5c); + + /// address: 0x40002860 + /// backup register + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x60); + + /// address: 0x40002864 + /// backup register + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x64); + + /// address: 0x40002868 + /// backup register + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x68); + + /// address: 0x4000286c + /// backup register + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x6c); + + /// address: 0x40002870 + /// backup register + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x70); + + /// address: 0x40002874 + /// backup register + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x74); + + /// address: 0x40002878 + /// backup register + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x78); + + /// address: 0x4000287c + /// backup register + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x7c); + + /// address: 0x40002880 + /// backup register + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x80); + + /// address: 0x40002884 + /// backup register + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x84); + + /// address: 0x40002888 + /// backup register + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x88); + + /// address: 0x4000288c + /// backup register + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x8c); + + /// address: 0x40002890 + /// backup register + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x90); + + /// address: 0x40002894 + /// backup register + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x94); + + /// address: 0x40002898 + /// backup register + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x98); + + /// address: 0x4000289c + /// backup register + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x9c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + pub const UART7 = struct { + pub const base_address = 0x40007800; + + /// address: 0x40007800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000780c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + pub const UART8 = struct { + pub const base_address = 0x40007c00; + + /// address: 0x40007c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40007c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + + /// Common ADC registers + pub const C_ADC = struct { + pub const base_address = 0x40012300; + + /// address: 0x40012300 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag of ADC + /// 1 + AWD1: u1, + /// End of conversion of ADC 1 + EOC1: u1, + /// Injected channel end of conversion of + /// ADC 1 + JEOC1: u1, + /// Injected channel Start flag of ADC + /// 1 + JSTRT1: u1, + /// Regular channel Start flag of ADC + /// 1 + STRT1: u1, + /// Overrun flag of ADC 1 + OVR1: u1, + reserved0: u1, + reserved1: u1, + /// Analog watchdog flag of ADC + /// 2 + AWD2: u1, + /// End of conversion of ADC 2 + EOC2: u1, + /// Injected channel end of conversion of + /// ADC 2 + JEOC2: u1, + /// Injected channel Start flag of ADC + /// 2 + JSTRT2: u1, + /// Regular channel Start flag of ADC + /// 2 + STRT2: u1, + /// Overrun flag of ADC 2 + OVR2: u1, + reserved2: u1, + reserved3: u1, + /// Analog watchdog flag of ADC + /// 3 + AWD3: u1, + /// End of conversion of ADC 3 + EOC3: u1, + /// Injected channel end of conversion of + /// ADC 3 + JEOC3: u1, + /// Injected channel Start flag of ADC + /// 3 + JSTRT3: u1, + /// Regular channel Start flag of ADC + /// 3 + STRT3: u1, + /// Overrun flag of ADC3 + OVR3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x0); + + /// address: 0x40012304 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA disable selection for multi-ADC + /// mode + DDS: u1, + /// Direct memory access mode for multi ADC + /// mode + DMA: u2, + /// ADC prescaler + ADCPRE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012308 + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st data item of a pair of regular + /// conversions + DATA1: u16, + /// 2nd data item of a pair of regular + /// conversions + DATA2: u16, + }), base_address + 0x8); + }; + + /// Advanced-timers + pub const TIM1 = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + pub const TIM8 = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + + /// General purpose timers + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000050 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Timer Input 4 remap + ITR1_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// General-purpose-timers + pub const TIM5 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40000c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x40000c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000c50 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer Input 4 remap + IT4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM9 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40014004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40014008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4001400c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40014010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40014018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001402c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + pub const TIM12 = struct { + pub const base_address = 0x40001800; + + /// address: 0x40001800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40001814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40001818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000182c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40001838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + + /// General-purpose-timers + pub const TIM10 = struct { + pub const base_address = 0x40014400; + + /// address: 0x40014400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001440c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001442c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM13 = struct { + pub const base_address = 0x40001c00; + + /// address: 0x40001c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40001c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40001c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40001c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40001c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40001c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM14 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4000200c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40002014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40002018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40002018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40002020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40002024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40002028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000202c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40002034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + + /// General-purpose-timers + pub const TIM11 = struct { + pub const base_address = 0x40014800; + + /// address: 0x40014800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001480c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001482c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014850 + /// option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input 1 remapping + /// capability + RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x50); + }; + + /// Basic timers + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + + /// Ethernet: media access control + /// (MAC) + pub const Ethernet_MAC = struct { + pub const base_address = 0x40028000; + + /// address: 0x40028000 + /// Ethernet MAC configuration + /// register + pub const MACCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// DC + DC: u1, + /// BL + BL: u2, + /// APCS + APCS: u1, + reserved2: u1, + /// RD + RD: u1, + /// IPCO + IPCO: u1, + /// DM + DM: u1, + /// LM + LM: u1, + /// ROD + ROD: u1, + /// FES + FES: u1, + reserved3: u1, + /// CSD + CSD: u1, + /// IFG + IFG: u3, + reserved4: u1, + reserved5: u1, + /// JD + JD: u1, + /// WD + WD: u1, + reserved6: u1, + /// CSTF + CSTF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40028004 + /// Ethernet MAC frame filter + /// register + pub const MACFFR = @intToPtr(*volatile Mmio(32, packed struct { + /// PM + PM: u1, + /// HU + HU: u1, + /// HM + HM: u1, + /// DAIF + DAIF: u1, + /// RAM + RAM: u1, + /// BFD + BFD: u1, + /// PCF + PCF: u1, + /// SAIF + SAIF: u1, + /// SAF + SAF: u1, + /// HPF + HPF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// RA + RA: u1, + }), base_address + 0x4); + + /// address: 0x40028008 + /// Ethernet MAC hash table high + /// register + pub const MACHTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTH + HTH: u32, + }), base_address + 0x8); + + /// address: 0x4002800c + /// Ethernet MAC hash table low + /// register + pub const MACHTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + HTL: u32, + }), base_address + 0xc); + + /// address: 0x40028010 + /// Ethernet MAC MII address + /// register + pub const MACMIIAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MB + MB: u1, + /// MW + MW: u1, + /// CR + CR: u3, + reserved0: u1, + /// MR + MR: u5, + /// PA + PA: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40028014 + /// Ethernet MAC MII data register + pub const MACMIIDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TD + TD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40028018 + /// Ethernet MAC flow control + /// register + pub const MACFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FCB + FCB: u1, + /// TFCE + TFCE: u1, + /// RFCE + RFCE: u1, + /// UPFD + UPFD: u1, + /// PLT + PLT: u2, + reserved0: u1, + /// ZQPD + ZQPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// PT + PT: u16, + }), base_address + 0x18); + + /// address: 0x4002801c + /// Ethernet MAC VLAN tag register + pub const MACVLANTR = @intToPtr(*volatile Mmio(32, packed struct { + /// VLANTI + VLANTI: u16, + /// VLANTC + VLANTC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x4002802c + /// Ethernet MAC PMT control and status + /// register + pub const MACPMTCSR = @intToPtr(*volatile Mmio(32, packed struct { + /// PD + PD: u1, + /// MPE + MPE: u1, + /// WFE + WFE: u1, + reserved0: u1, + reserved1: u1, + /// MPR + MPR: u1, + /// WFR + WFR: u1, + reserved2: u1, + reserved3: u1, + /// GU + GU: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + /// WFFRPR + WFFRPR: u1, + }), base_address + 0x2c); + + /// address: 0x40028034 + /// Ethernet MAC debug register + pub const MACDBGR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x34); + + /// address: 0x40028038 + /// Ethernet MAC interrupt status + /// register + pub const MACSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTS + PMTS: u1, + /// MMCS + MMCS: u1, + /// MMCRS + MMCRS: u1, + /// MMCTS + MMCTS: u1, + reserved3: u1, + reserved4: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x38); + + /// address: 0x4002803c + /// Ethernet MAC interrupt mask + /// register + pub const MACIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTIM + PMTIM: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// TSTIM + TSTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x3c); + + /// address: 0x40028040 + /// Ethernet MAC address 0 high + /// register + pub const MACA0HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC address0 high + MACA0H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Always 1 + MO: u1, + }), base_address + 0x40); + + /// address: 0x40028044 + /// Ethernet MAC address 0 low + /// register + pub const MACA0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + MACA0L: u32, + }), base_address + 0x44); + + /// address: 0x40028048 + /// Ethernet MAC address 1 high + /// register + pub const MACA1HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA1H + MACA1H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x48); + + /// address: 0x4002804c + /// Ethernet MAC address1 low + /// register + pub const MACA1LR = @intToPtr(*volatile u32, base_address + 0x4c); + + /// address: 0x40028050 + /// Ethernet MAC address 2 high + /// register + pub const MACA2HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC2AH + MAC2AH: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x50); + + /// address: 0x40028054 + /// Ethernet MAC address 2 low + /// register + pub const MACA2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA2L + MACA2L: u31, + padding0: u1, + }), base_address + 0x54); + + /// address: 0x40028058 + /// Ethernet MAC address 3 high + /// register + pub const MACA3HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA3H + MACA3H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x58); + + /// address: 0x4002805c + /// Ethernet MAC address 3 low + /// register + pub const MACA3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MBCA3L + MBCA3L: u32, + }), base_address + 0x5c); + }; + + /// Ethernet: MAC management counters + pub const Ethernet_MMC = struct { + pub const base_address = 0x40028100; + + /// address: 0x40028100 + /// Ethernet MMC control register + pub const MMCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40028104 + /// Ethernet MMC receive interrupt + /// register + pub const MMCRIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCES + RFCES: u1, + /// RFAES + RFAES: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFS + RGUFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40028108 + /// Ethernet MMC transmit interrupt + /// register + pub const MMCTIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCS + TGFSCS: u1, + /// TGFMSCS + TGFMSCS: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// TGFS + TGFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x4002810c + /// Ethernet MMC receive interrupt mask + /// register + pub const MMCRIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCEM + RFCEM: u1, + /// RFAEM + RFAEM: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFM + RGUFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0xc); + + /// address: 0x40028110 + /// Ethernet MMC transmit interrupt mask + /// register + pub const MMCTIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCM + TGFSCM: u1, + /// TGFMSCM + TGFMSCM: u1, + /// TGFM + TGFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0x4002814c + /// Ethernet MMC transmitted good frames after a + /// single collision counter + pub const MMCTGFSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFSCC + TGFSCC: u32, + }), base_address + 0x4c); + + /// address: 0x40028150 + /// Ethernet MMC transmitted good frames after + /// more than a single collision + pub const MMCTGFMSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFMSCC + TGFMSCC: u32, + }), base_address + 0x50); + + /// address: 0x40028168 + /// Ethernet MMC transmitted good frames counter + /// register + pub const MMCTGFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + TGFC: u32, + }), base_address + 0x68); + + /// address: 0x40028194 + /// Ethernet MMC received frames with CRC error + /// counter register + pub const MMCRFCECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFCFC + RFCFC: u32, + }), base_address + 0x94); + + /// address: 0x40028198 + /// Ethernet MMC received frames with alignment + /// error counter register + pub const MMCRFAECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFAEC + RFAEC: u32, + }), base_address + 0x98); + + /// address: 0x400281c4 + /// MMC received good unicast frames counter + /// register + pub const MMCRGUFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// RGUFC + RGUFC: u32, + }), base_address + 0xc4); + }; + + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = struct { + pub const base_address = 0x40028700; + + /// address: 0x40028700 + /// Ethernet PTP time stamp control + /// register + pub const PTPTSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved0: u1, + reserved1: u1, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40028704 + /// Ethernet PTP subsecond increment + /// register + pub const PTPSSIR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSSI + STSSI: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40028708 + /// Ethernet PTP time stamp high + /// register + pub const PTPTSHR = @intToPtr(*volatile Mmio(32, packed struct { + /// STS + STS: u32, + }), base_address + 0x8); + + /// address: 0x4002870c + /// Ethernet PTP time stamp low + /// register + pub const PTPTSLR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, + }), base_address + 0xc); + + /// address: 0x40028710 + /// Ethernet PTP time stamp high update + /// register + pub const PTPTSHUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUS + TSUS: u32, + }), base_address + 0x10); + + /// address: 0x40028714 + /// Ethernet PTP time stamp low update + /// register + pub const PTPTSLUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUSS + TSUSS: u31, + /// TSUPNS + TSUPNS: u1, + }), base_address + 0x14); + + /// address: 0x40028718 + /// Ethernet PTP time stamp addend + /// register + pub const PTPTSAR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSA + TSA: u32, + }), base_address + 0x18); + + /// address: 0x4002871c + /// Ethernet PTP target time high + /// register + pub const PTPTTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + TTSH: u32, + }), base_address + 0x1c); + + /// address: 0x40028720 + /// Ethernet PTP target time low + /// register + pub const PTPTTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// TTSL + TTSL: u32, + }), base_address + 0x20); + + /// address: 0x40028728 + /// Ethernet PTP time stamp status + /// register + pub const PTPTSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4002872c + /// Ethernet PTP PPS control + /// register + pub const PTPPPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + }; + + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = struct { + pub const base_address = 0x40029000; + + /// address: 0x40029000 + /// Ethernet DMA bus mode register + pub const DMABMR = @intToPtr(*volatile Mmio(32, packed struct { + /// SR + SR: u1, + /// DA + DA: u1, + /// DSL + DSL: u5, + /// EDFE + EDFE: u1, + /// PBL + PBL: u6, + /// RTPR + RTPR: u2, + /// FB + FB: u1, + /// RDP + RDP: u6, + /// USP + USP: u1, + /// FPM + FPM: u1, + /// AAB + AAB: u1, + /// MB + MB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x40029004 + /// Ethernet DMA transmit poll demand + /// register + pub const DMATPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TPD + TPD: u32, + }), base_address + 0x4); + + /// address: 0x40029008 + /// EHERNET DMA receive poll demand + /// register + pub const DMARPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// RPD + RPD: u32, + }), base_address + 0x8); + + /// address: 0x4002900c + /// Ethernet DMA receive descriptor list address + /// register + pub const DMARDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// SRL + SRL: u32, + }), base_address + 0xc); + + /// address: 0x40029010 + /// Ethernet DMA transmit descriptor list + /// address register + pub const DMATDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// STL + STL: u32, + }), base_address + 0x10); + + /// address: 0x40029014 + /// Ethernet DMA status register + pub const DMASR = @intToPtr(*volatile Mmio(32, packed struct { + /// TS + TS: u1, + /// TPSS + TPSS: u1, + /// TBUS + TBUS: u1, + /// TJTS + TJTS: u1, + /// ROS + ROS: u1, + /// TUS + TUS: u1, + /// RS + RS: u1, + /// RBUS + RBUS: u1, + /// RPSS + RPSS: u1, + /// PWTS + PWTS: u1, + /// ETS + ETS: u1, + reserved0: u1, + reserved1: u1, + /// FBES + FBES: u1, + /// ERS + ERS: u1, + /// AIS + AIS: u1, + /// NIS + NIS: u1, + /// RPS + RPS: u3, + /// TPS + TPS: u3, + /// EBS + EBS: u3, + reserved2: u1, + /// MMCS + MMCS: u1, + /// PMTS + PMTS: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x40029018 + /// Ethernet DMA operation mode + /// register + pub const DMAOMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved1: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved10: u1, + reserved11: u1, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x4002901c + /// Ethernet DMA interrupt enable + /// register + pub const DMAIER = @intToPtr(*volatile Mmio(32, packed struct { + /// TIE + TIE: u1, + /// TPSIE + TPSIE: u1, + /// TBUIE + TBUIE: u1, + /// TJTIE + TJTIE: u1, + /// ROIE + ROIE: u1, + /// TUIE + TUIE: u1, + /// RIE + RIE: u1, + /// RBUIE + RBUIE: u1, + /// RPSIE + RPSIE: u1, + /// RWTIE + RWTIE: u1, + /// ETIE + ETIE: u1, + reserved0: u1, + reserved1: u1, + /// FBEIE + FBEIE: u1, + /// ERIE + ERIE: u1, + /// AISE + AISE: u1, + /// NISE + NISE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40029020 + /// Ethernet DMA missed frame and buffer + /// overflow counter register + pub const DMAMFBOCR = @intToPtr(*volatile Mmio(32, packed struct { + /// MFC + MFC: u16, + /// OMFC + OMFC: u1, + /// MFA + MFA: u11, + /// OFOC + OFOC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x40029024 + /// Ethernet DMA receive status watchdog timer + /// register + pub const DMARSWTR = @intToPtr(*volatile Mmio(32, packed struct { + /// RSWTC + RSWTC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40029048 + /// Ethernet DMA current host transmit + /// descriptor register + pub const DMACHTDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTDAP + HTDAP: u32, + }), base_address + 0x48); + + /// address: 0x4002904c + /// Ethernet DMA current host receive descriptor + /// register + pub const DMACHRDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRDAP + HRDAP: u32, + }), base_address + 0x4c); + + /// address: 0x40029050 + /// Ethernet DMA current host transmit buffer + /// address register + pub const DMACHTBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTBAP + HTBAP: u32, + }), base_address + 0x50); + + /// address: 0x40029054 + /// Ethernet DMA current host receive buffer + /// address register + pub const DMACHRBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRBAP + HRBAP: u32, + }), base_address + 0x54); + }; + + /// Cryptographic processor + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Independent Data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// OTG_FS control and status register + /// (OTG_FS_GOTGCTL) + pub const FS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// OTG_FS interrupt register + /// (OTG_FS_GOTGINT) + pub const FS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// OTG_FS AHB configuration register + /// (OTG_FS_GAHBCFG) + pub const FS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// OTG_FS USB configuration register + /// (OTG_FS_GUSBCFG) + pub const FS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Full Speed serial transceiver + /// select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x50000010 + /// OTG_FS reset register + /// (OTG_FS_GRSTCTL) + pub const FS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x50000014 + /// OTG_FS core interrupt register + /// (OTG_FS_GINTSTS) + pub const FS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host + /// mode)/Incomplete isochronous OUT transfer(Device + /// mode) + IPXFR_INCOMPISOOUT: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved6: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUPINT: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// OTG_FS interrupt mask register + /// (OTG_FS_GINTMSK) + pub const FS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty + /// mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host + /// mode)/Incomplete isochronous OUT transfer mask(Device + /// mode) + IPXFRM_IISOOXFRM: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved6: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x5000001c + /// OTG_FS Receive status debug read(Device + /// mode) + pub const FS_GRXSTSR_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x5000001c + /// OTG_FS Receive status debug read(Host + /// mode) + pub const FS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x50000024 + /// OTG_FS Receive FIFO size register + /// (OTG_FS_GRXFSIZ) + pub const FS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Device mode) + pub const FS_GNPTXFSIZ_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Host mode) + pub const FS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic transmit RAM start + /// address + NPTXFSA: u16, + /// Non-periodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x5000002c + /// OTG_FS non-periodic transmit FIFO/queue + /// status register (OTG_FS_GNPTXSTS) + pub const FS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Non-periodic transmit request queue + /// space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x50000038 + /// OTG_FS general core configuration register + /// (OTG_FS_GCCFG) + pub const FS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + reserved16: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// core ID register + pub const FS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x50000100 + /// OTG_FS Host periodic transmit FIFO size + /// register (OTG_FS_HPTXFSIZ) + pub const FS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), base_address + 0x100); + + /// address: 0x50000104 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF2) + pub const FS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO2 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x50000108 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF3) + pub const FS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO3 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x5000010c + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF4) + pub const FS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO4 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x10c); + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// OTG_FS host configuration register + /// (OTG_FS_HCFG) + pub const FS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// OTG_FS Host frame interval + /// register + pub const HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// OTG_FS host frame number/frame time + /// remaining register (OTG_FS_HFNUM) + pub const FS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x50000410 + /// OTG_FS_Host periodic transmit FIFO/queue + /// status register (OTG_FS_HPTXSTS) + pub const FS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x50000414 + /// OTG_FS Host all channels interrupt + /// register + pub const HAINT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x50000418 + /// OTG_FS host all channels interrupt mask + /// register + pub const HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x50000440 + /// OTG_FS host port control and status register + /// (OTG_FS_HPRT) + pub const FS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x50000500 + /// OTG_FS host channel-0 characteristics + /// register (OTG_FS_HCCHAR0) + pub const FS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x50000520 + /// OTG_FS host channel-1 characteristics + /// register (OTG_FS_HCCHAR1) + pub const FS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x50000540 + /// OTG_FS host channel-2 characteristics + /// register (OTG_FS_HCCHAR2) + pub const FS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x50000560 + /// OTG_FS host channel-3 characteristics + /// register (OTG_FS_HCCHAR3) + pub const FS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x50000580 + /// OTG_FS host channel-4 characteristics + /// register (OTG_FS_HCCHAR4) + pub const FS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x500005a0 + /// OTG_FS host channel-5 characteristics + /// register (OTG_FS_HCCHAR5) + pub const FS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x500005c0 + /// OTG_FS host channel-6 characteristics + /// register (OTG_FS_HCCHAR6) + pub const FS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x500005e0 + /// OTG_FS host channel-7 characteristics + /// register (OTG_FS_HCCHAR7) + pub const FS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x50000508 + /// OTG_FS host channel-0 interrupt register + /// (OTG_FS_HCINT0) + pub const FS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x50000528 + /// OTG_FS host channel-1 interrupt register + /// (OTG_FS_HCINT1) + pub const FS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x50000548 + /// OTG_FS host channel-2 interrupt register + /// (OTG_FS_HCINT2) + pub const FS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x50000568 + /// OTG_FS host channel-3 interrupt register + /// (OTG_FS_HCINT3) + pub const FS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x50000588 + /// OTG_FS host channel-4 interrupt register + /// (OTG_FS_HCINT4) + pub const FS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x500005a8 + /// OTG_FS host channel-5 interrupt register + /// (OTG_FS_HCINT5) + pub const FS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x500005c8 + /// OTG_FS host channel-6 interrupt register + /// (OTG_FS_HCINT6) + pub const FS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x500005e8 + /// OTG_FS host channel-7 interrupt register + /// (OTG_FS_HCINT7) + pub const FS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x5000050c + /// OTG_FS host channel-0 mask register + /// (OTG_FS_HCINTMSK0) + pub const FS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x5000052c + /// OTG_FS host channel-1 mask register + /// (OTG_FS_HCINTMSK1) + pub const FS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x5000054c + /// OTG_FS host channel-2 mask register + /// (OTG_FS_HCINTMSK2) + pub const FS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x5000056c + /// OTG_FS host channel-3 mask register + /// (OTG_FS_HCINTMSK3) + pub const FS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x5000058c + /// OTG_FS host channel-4 mask register + /// (OTG_FS_HCINTMSK4) + pub const FS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x500005ac + /// OTG_FS host channel-5 mask register + /// (OTG_FS_HCINTMSK5) + pub const FS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x500005cc + /// OTG_FS host channel-6 mask register + /// (OTG_FS_HCINTMSK6) + pub const FS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x500005ec + /// OTG_FS host channel-7 mask register + /// (OTG_FS_HCINTMSK7) + pub const FS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x50000510 + /// OTG_FS host channel-0 transfer size + /// register + pub const FS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x50000530 + /// OTG_FS host channel-1 transfer size + /// register + pub const FS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000550 + /// OTG_FS host channel-2 transfer size + /// register + pub const FS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000570 + /// OTG_FS host channel-3 transfer size + /// register + pub const FS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000590 + /// OTG_FS host channel-x transfer size + /// register + pub const FS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x500005b0 + /// OTG_FS host channel-5 transfer size + /// register + pub const FS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x500005d0 + /// OTG_FS host channel-6 transfer size + /// register + pub const FS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x500005f0 + /// OTG_FS host channel-7 transfer size + /// register + pub const FS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = struct { + pub const base_address = 0x50000800; + + /// address: 0x50000800 + /// OTG_FS device configuration register + /// (OTG_FS_DCFG) + pub const FS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x50000804 + /// OTG_FS device control register + /// (OTG_FS_DCTL) + pub const FS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x50000808 + /// OTG_FS device status register + /// (OTG_FS_DSTS) + pub const FS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x50000810 + /// OTG_FS device IN endpoint common interrupt + /// mask register (OTG_FS_DIEPMSK) + pub const FS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (Non-isochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x10); + + /// address: 0x50000814 + /// OTG_FS device OUT endpoint common interrupt + /// mask register (OTG_FS_DOEPMSK) + pub const FS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50000818 + /// OTG_FS device all endpoints interrupt + /// register (OTG_FS_DAINT) + pub const FS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x5000081c + /// OTG_FS all endpoints interrupt mask register + /// (OTG_FS_DAINTMSK) + pub const FS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x1c); + + /// address: 0x50000828 + /// OTG_FS device VBUS discharge time + /// register + pub const DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x5000082c + /// OTG_FS device VBUS pulsing time + /// register + pub const DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x50000834 + /// OTG_FS device IN endpoint FIFO empty + /// interrupt mask register + pub const DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x50000900 + /// OTG_FS device control IN endpoint 0 control + /// register (OTG_FS_DIEPCTL0) + pub const FS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved14: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved15: u1, + reserved16: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x50000920 + /// OTG device endpoint-1 control + /// register + pub const DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x50000940 + /// OTG device endpoint-2 control + /// register + pub const DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x50000960 + /// OTG device endpoint-3 control + /// register + pub const DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x50000b00 + /// device endpoint-0 control + /// register + pub const DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USBAEP + USBAEP: u1, + reserved13: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x50000b20 + /// device endpoint-1 control + /// register + pub const DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x50000b40 + /// device endpoint-2 control + /// register + pub const DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x50000b60 + /// device endpoint-3 control + /// register + pub const DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x50000908 + /// device endpoint-x interrupt + /// register + pub const DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x108); + + /// address: 0x50000928 + /// device endpoint-1 interrupt + /// register + pub const DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x128); + + /// address: 0x50000948 + /// device endpoint-2 interrupt + /// register + pub const DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x148); + + /// address: 0x50000968 + /// device endpoint-3 interrupt + /// register + pub const DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x168); + + /// address: 0x50000b08 + /// device endpoint-0 interrupt + /// register + pub const DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x50000b28 + /// device endpoint-1 interrupt + /// register + pub const DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x328); + + /// address: 0x50000b48 + /// device endpoint-2 interrupt + /// register + pub const DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x348); + + /// address: 0x50000b68 + /// device endpoint-3 interrupt + /// register + pub const DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x368); + + /// address: 0x50000910 + /// device endpoint-0 transfer size + /// register + pub const DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x50000b10 + /// device OUT endpoint-0 transfer size + /// register + pub const DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x50000930 + /// device endpoint-1 transfer size + /// register + pub const DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000950 + /// device endpoint-2 transfer size + /// register + pub const DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000970 + /// device endpoint-3 transfer size + /// register + pub const DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000918 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x50000938 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x50000958 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x50000978 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x50000b30 + /// device OUT endpoint-1 transfer size + /// register + pub const DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x50000b50 + /// device OUT endpoint-2 transfer size + /// register + pub const DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x50000b70 + /// device OUT endpoint-3 transfer size + /// register + pub const DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = struct { + pub const base_address = 0x50000e00; + + /// address: 0x50000e00 + /// OTG_FS power and clock gating control + /// register + pub const FS_PCGCCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY Suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// Controller area network + pub const CAN1 = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + pub const CAN2 = struct { + pub const base_address = 0x40006800; + + /// address: 0x40006800 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006804 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006808 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000680c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006810 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006814 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006818 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000681c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006980 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006984 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006988 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000698c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006990 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006994 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006998 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000699c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400069a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400069a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400069a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400069ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400069b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400069b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400069b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400069bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400069c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400069c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400069c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400069cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006a00 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006a04 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x40006a0c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006a14 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x40006a1c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006a40 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006a44 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006a48 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x40006a4c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006a50 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006a54 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006a58 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x40006a5c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006a60 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006a64 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006a68 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x40006a6c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006a70 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006a74 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006a78 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x40006a7c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006a80 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006a84 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006a88 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x40006a8c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006a90 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006a94 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006a98 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x40006a9c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x40006aa0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x40006aa4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x40006aa8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x40006aac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x40006ab0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x40006ab4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x40006ab8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x40006abc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x40006ac0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x40006ac4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x40006ac8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x40006acc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x40006ad0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x40006ad4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x40006ad8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x40006adc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x40006ae0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x40006ae4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x40006ae8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x40006aec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x40006af0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x40006af4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x40006af8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x40006afc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006b00 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006b04 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006b08 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x40006b0c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006b10 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006b14 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006b18 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x40006b1c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + + /// FLASH + pub const FLASH = struct { + pub const base_address = 0x40023c00; + + /// address: 0x40023c00 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Latency + LATENCY: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x40023c04 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// FPEC key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40023c08 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option byte key + OPTKEY: u32, + }), base_address + 0x8); + + /// address: 0x40023c0c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved0: u1, + reserved1: u1, + /// Write protection error + WRPERR: u1, + /// Programming alignment + /// error + PGAERR: u1, + /// Programming parallelism + /// error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Busy + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40023c10 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase + MER: u1, + /// Sector number + SNB: u4, + reserved0: u1, + /// Program size + PSIZE: u2, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Start + STRT: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Lock + LOCK: u1, + }), base_address + 0x10); + + /// address: 0x40023c14 + /// Flash option control register + pub const OPTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved0: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option + /// bytes + nRST_STOP: u1, + /// nRST_STDBY User option + /// bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14); + }; + + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// Interrupt mask register + /// (EXTI_IMR) + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// Event mask register (EXTI_EMR) + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// Rising Trigger selection register + /// (EXTI_RTSR) + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + /// Rising trigger event configuration of + /// line 19 + TR19: u1, + /// Rising trigger event configuration of + /// line 20 + TR20: u1, + /// Rising trigger event configuration of + /// line 21 + TR21: u1, + /// Rising trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// Falling Trigger selection register + /// (EXTI_FTSR) + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + /// Falling trigger event configuration of + /// line 19 + TR19: u1, + /// Falling trigger event configuration of + /// line 20 + TR20: u1, + /// Falling trigger event configuration of + /// line 21 + TR21: u1, + /// Falling trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xc); + + /// address: 0x40013c10 + /// Software interrupt event register + /// (EXTI_SWIER) + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + /// Software Interrupt on line + /// 19 + SWIER19: u1, + /// Software Interrupt on line + /// 20 + SWIER20: u1, + /// Software Interrupt on line + /// 21 + SWIER21: u1, + /// Software Interrupt on line + /// 22 + SWIER22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// Pending register (EXTI_PR) + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + }; + + /// USB on the go high speed + pub const OTG_HS_GLOBAL = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// OTG_HS control and status + /// register + pub const OTG_HS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40040004 + /// OTG_HS interrupt register + pub const OTG_HS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x40040008 + /// OTG_HS AHB configuration + /// register + pub const OTG_HS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved0: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4004000c + /// OTG_HS USB configuration + /// register + pub const OTG_HS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// USB 2.0 high-speed ULPI PHY or USB 1.1 + /// full-speed serial transceiver select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved5: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS + /// indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing + /// selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect + /// disable + ULPIIPD: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Forced host mode + FHMOD: u1, + /// Forced peripheral mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x40040010 + /// OTG_HS reset register + pub const OTG_HS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// DMA request signal + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x40040014 + /// OTG_HS core interrupt register + pub const OTG_HS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO nonempty + RXFLVL: u1, + /// Nonperiodic TxFIFO empty + NPTXFE: u1, + /// Global IN nonperiodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + BOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic + /// transfer + PXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved4: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved5: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUINT: u1, + }), base_address + 0x14); + + /// address: 0x40040018 + /// OTG_HS interrupt mask register + pub const OTG_HS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO nonempty mask + RXFLVLM: u1, + /// Nonperiodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global nonperiodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer + /// mask + PXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + reserved4: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved5: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (host mode) + pub const OTG_HS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register (host + /// mode) + pub const OTG_HS_GRXSTSP_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40040024 + /// OTG_HS Receive FIFO size + /// register + pub const OTG_HS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x40040028 + /// OTG_HS nonperiodic transmit FIFO size + /// register (host mode) + pub const OTG_HS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic transmit RAM start + /// address + NPTXFSA: u16, + /// Nonperiodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x40040028 + /// Endpoint 0 transmit FIFO size (peripheral + /// mode) + pub const OTG_HS_TX0FSIZ_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x4004002c + /// OTG_HS nonperiodic transmit FIFO/queue + /// status register + pub const OTG_HS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Nonperiodic transmit request queue space + /// available + NPTQXSAV: u8, + /// Top of the nonperiodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x40040038 + /// OTG_HS general core configuration + /// register + pub const OTG_HS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + /// Enable I2C bus connection for the + /// external I2C PHY interface + I2CPADEN: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable + /// option + NOVBUSSENS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4004003c + /// OTG_HS core ID register + pub const OTG_HS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x40040100 + /// OTG_HS Host periodic transmit FIFO size + /// register + pub const OTG_HS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFD: u16, + }), base_address + 0x100); + + /// address: 0x40040104 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x40040108 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x4004011c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x11c); + + /// address: 0x40040120 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x120); + + /// address: 0x40040124 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x124); + + /// address: 0x40040128 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x128); + + /// address: 0x4004012c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x12c); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (peripheral mode mode) + pub const OTG_HS_GRXSTSR_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register + /// (peripheral mode) + pub const OTG_HS_GRXSTSP_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x20); + }; + + /// USB on the go high speed + pub const OTG_HS_HOST = struct { + pub const base_address = 0x40040400; + + /// address: 0x40040400 + /// OTG_HS host configuration + /// register + pub const OTG_HS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40040404 + /// OTG_HS Host frame interval + /// register + pub const OTG_HS_HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40040408 + /// OTG_HS host frame number/frame time + /// remaining register + pub const OTG_HS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x40040410 + /// OTG_HS_Host periodic transmit FIFO/queue + /// status register + pub const OTG_HS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x40040414 + /// OTG_HS Host all channels interrupt + /// register + pub const OTG_HS_HAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupts + HAINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40040418 + /// OTG_HS host all channels interrupt mask + /// register + pub const OTG_HS_HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40040440 + /// OTG_HS host port control and status + /// register + pub const OTG_HS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40040500 + /// OTG_HS host channel-0 characteristics + /// register + pub const OTG_HS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x40040520 + /// OTG_HS host channel-1 characteristics + /// register + pub const OTG_HS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x40040540 + /// OTG_HS host channel-2 characteristics + /// register + pub const OTG_HS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x40040560 + /// OTG_HS host channel-3 characteristics + /// register + pub const OTG_HS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x40040580 + /// OTG_HS host channel-4 characteristics + /// register + pub const OTG_HS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x400405a0 + /// OTG_HS host channel-5 characteristics + /// register + pub const OTG_HS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400405c0 + /// OTG_HS host channel-6 characteristics + /// register + pub const OTG_HS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400405e0 + /// OTG_HS host channel-7 characteristics + /// register + pub const OTG_HS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040600 + /// OTG_HS host channel-8 characteristics + /// register + pub const OTG_HS_HCCHAR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x200); + + /// address: 0x40040620 + /// OTG_HS host channel-9 characteristics + /// register + pub const OTG_HS_HCCHAR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x220); + + /// address: 0x40040640 + /// OTG_HS host channel-10 characteristics + /// register + pub const OTG_HS_HCCHAR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x240); + + /// address: 0x40040660 + /// OTG_HS host channel-11 characteristics + /// register + pub const OTG_HS_HCCHAR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x260); + + /// address: 0x40040504 + /// OTG_HS host channel-0 split control + /// register + pub const OTG_HS_HCSPLT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x104); + + /// address: 0x40040524 + /// OTG_HS host channel-1 split control + /// register + pub const OTG_HS_HCSPLT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x124); + + /// address: 0x40040544 + /// OTG_HS host channel-2 split control + /// register + pub const OTG_HS_HCSPLT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x144); + + /// address: 0x40040564 + /// OTG_HS host channel-3 split control + /// register + pub const OTG_HS_HCSPLT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x164); + + /// address: 0x40040584 + /// OTG_HS host channel-4 split control + /// register + pub const OTG_HS_HCSPLT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x184); + + /// address: 0x400405a4 + /// OTG_HS host channel-5 split control + /// register + pub const OTG_HS_HCSPLT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1a4); + + /// address: 0x400405c4 + /// OTG_HS host channel-6 split control + /// register + pub const OTG_HS_HCSPLT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1c4); + + /// address: 0x400405e4 + /// OTG_HS host channel-7 split control + /// register + pub const OTG_HS_HCSPLT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1e4); + + /// address: 0x40040604 + /// OTG_HS host channel-8 split control + /// register + pub const OTG_HS_HCSPLT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x204); + + /// address: 0x40040624 + /// OTG_HS host channel-9 split control + /// register + pub const OTG_HS_HCSPLT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x224); + + /// address: 0x40040644 + /// OTG_HS host channel-10 split control + /// register + pub const OTG_HS_HCSPLT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x244); + + /// address: 0x40040664 + /// OTG_HS host channel-11 split control + /// register + pub const OTG_HS_HCSPLT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x264); + + /// address: 0x40040508 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x40040528 + /// OTG_HS host channel-1 interrupt + /// register + pub const OTG_HS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x40040548 + /// OTG_HS host channel-2 interrupt + /// register + pub const OTG_HS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x40040568 + /// OTG_HS host channel-3 interrupt + /// register + pub const OTG_HS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x40040588 + /// OTG_HS host channel-4 interrupt + /// register + pub const OTG_HS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x400405a8 + /// OTG_HS host channel-5 interrupt + /// register + pub const OTG_HS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x400405c8 + /// OTG_HS host channel-6 interrupt + /// register + pub const OTG_HS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x400405e8 + /// OTG_HS host channel-7 interrupt + /// register + pub const OTG_HS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x40040608 + /// OTG_HS host channel-8 interrupt + /// register + pub const OTG_HS_HCINT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x208); + + /// address: 0x40040628 + /// OTG_HS host channel-9 interrupt + /// register + pub const OTG_HS_HCINT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x228); + + /// address: 0x40040648 + /// OTG_HS host channel-10 interrupt + /// register + pub const OTG_HS_HCINT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x248); + + /// address: 0x40040668 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x268); + + /// address: 0x4004050c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x4004052c + /// OTG_HS host channel-1 interrupt mask + /// register + pub const OTG_HS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x4004054c + /// OTG_HS host channel-2 interrupt mask + /// register + pub const OTG_HS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x4004056c + /// OTG_HS host channel-3 interrupt mask + /// register + pub const OTG_HS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x4004058c + /// OTG_HS host channel-4 interrupt mask + /// register + pub const OTG_HS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x400405ac + /// OTG_HS host channel-5 interrupt mask + /// register + pub const OTG_HS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x400405cc + /// OTG_HS host channel-6 interrupt mask + /// register + pub const OTG_HS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x400405ec + /// OTG_HS host channel-7 interrupt mask + /// register + pub const OTG_HS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x4004060c + /// OTG_HS host channel-8 interrupt mask + /// register + pub const OTG_HS_HCINTMSK8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x20c); + + /// address: 0x4004062c + /// OTG_HS host channel-9 interrupt mask + /// register + pub const OTG_HS_HCINTMSK9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x22c); + + /// address: 0x4004064c + /// OTG_HS host channel-10 interrupt mask + /// register + pub const OTG_HS_HCINTMSK10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x24c); + + /// address: 0x4004066c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x26c); + + /// address: 0x40040510 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x40040530 + /// OTG_HS host channel-1 transfer size + /// register + pub const OTG_HS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040550 + /// OTG_HS host channel-2 transfer size + /// register + pub const OTG_HS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040570 + /// OTG_HS host channel-3 transfer size + /// register + pub const OTG_HS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040590 + /// OTG_HS host channel-4 transfer size + /// register + pub const OTG_HS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400405b0 + /// OTG_HS host channel-5 transfer size + /// register + pub const OTG_HS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x400405d0 + /// OTG_HS host channel-6 transfer size + /// register + pub const OTG_HS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x400405f0 + /// OTG_HS host channel-7 transfer size + /// register + pub const OTG_HS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + + /// address: 0x40040610 + /// OTG_HS host channel-8 transfer size + /// register + pub const OTG_HS_HCTSIZ8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x210); + + /// address: 0x40040630 + /// OTG_HS host channel-9 transfer size + /// register + pub const OTG_HS_HCTSIZ9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x230); + + /// address: 0x40040650 + /// OTG_HS host channel-10 transfer size + /// register + pub const OTG_HS_HCTSIZ10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x250); + + /// address: 0x40040670 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x270); + + /// address: 0x40040514 + /// OTG_HS host channel-0 DMA address + /// register + pub const OTG_HS_HCDMA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040534 + /// OTG_HS host channel-1 DMA address + /// register + pub const OTG_HS_HCDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040554 + /// OTG_HS host channel-2 DMA address + /// register + pub const OTG_HS_HCDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040574 + /// OTG_HS host channel-3 DMA address + /// register + pub const OTG_HS_HCDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040594 + /// OTG_HS host channel-4 DMA address + /// register + pub const OTG_HS_HCDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x400405b4 + /// OTG_HS host channel-5 DMA address + /// register + pub const OTG_HS_HCDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1b4); + + /// address: 0x400405d4 + /// OTG_HS host channel-6 DMA address + /// register + pub const OTG_HS_HCDMA6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1d4); + + /// address: 0x400405f4 + /// OTG_HS host channel-7 DMA address + /// register + pub const OTG_HS_HCDMA7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1f4); + + /// address: 0x40040614 + /// OTG_HS host channel-8 DMA address + /// register + pub const OTG_HS_HCDMA8 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x214); + + /// address: 0x40040634 + /// OTG_HS host channel-9 DMA address + /// register + pub const OTG_HS_HCDMA9 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x234); + + /// address: 0x40040654 + /// OTG_HS host channel-10 DMA address + /// register + pub const OTG_HS_HCDMA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x254); + + /// address: 0x40040674 + /// OTG_HS host channel-11 DMA address + /// register + pub const OTG_HS_HCDMA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x274); + }; + + /// USB on the go high speed + pub const OTG_HS_DEVICE = struct { + pub const base_address = 0x40040800; + + /// address: 0x40040800 + /// OTG_HS device configuration + /// register + pub const OTG_HS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Nonzero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic (micro)frame + /// interval + PFIVL: u2, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Periodic scheduling + /// interval + PERSCHIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40040804 + /// OTG_HS device control register + pub const OTG_HS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40040808 + /// OTG_HS device status register + pub const OTG_HS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x40040810 + /// OTG_HS device IN endpoint common interrupt + /// mask register + pub const OTG_HS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40040814 + /// OTG_HS device OUT endpoint common interrupt + /// mask register + pub const OTG_HS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + reserved1: u1, + /// Back-to-back SETUP packets received + /// mask + B2BSTUP: u1, + reserved2: u1, + /// OUT packet error mask + OPEM: u1, + /// BNA interrupt mask + BOIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0x40040818 + /// OTG_HS device all endpoints interrupt + /// register + pub const OTG_HS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x4004081c + /// OTG_HS all endpoints interrupt mask + /// register + pub const OTG_HS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, + }), base_address + 0x1c); + + /// address: 0x40040828 + /// OTG_HS device VBUS discharge time + /// register + pub const OTG_HS_DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4004082c + /// OTG_HS device VBUS pulsing time + /// register + pub const OTG_HS_DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40040830 + /// OTG_HS Device threshold control + /// register + pub const OTG_HS_DTHRCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonisochronous IN endpoints threshold + /// enable + NONISOTHREN: u1, + /// ISO IN endpoint threshold + /// enable + ISOTHREN: u1, + /// Transmit threshold length + TXTHRLEN: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Receive threshold enable + RXTHREN: u1, + /// Receive threshold length + RXTHRLEN: u9, + reserved5: u1, + /// Arbiter parking enable + ARPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x30); + + /// address: 0x40040834 + /// OTG_HS device IN endpoint FIFO empty + /// interrupt mask register + pub const OTG_HS_DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40040838 + /// OTG_HS device each endpoint interrupt + /// register + pub const OTG_HS_DEACHINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN endpoint 1interrupt bit + IEP1INT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT endpoint 1 interrupt + /// bit + OEP1INT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x38); + + /// address: 0x4004083c + /// OTG_HS device each endpoint interrupt + /// register mask + pub const OTG_HS_DEACHINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN Endpoint 1 interrupt mask + /// bit + IEP1INTM: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT Endpoint 1 interrupt mask + /// bit + OEP1INTM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x3c); + + /// address: 0x40040840 + /// OTG_HS device each in endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// NAK interrupt mask + NAKM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x40040880 + /// OTG_HS device each OUT endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// OUT packet error mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + /// Bubble error interrupt + /// mask + BERRM: u1, + /// NAK interrupt mask + NAKM: u1, + /// NYET interrupt mask + NYETM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40040900 + /// OTG device endpoint-0 control + /// register + pub const OTG_HS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x40040920 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x40040940 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x40040960 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x40040980 + /// OTG device endpoint-4 control + /// register + pub const OTG_HS_DIEPCTL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x180); + + /// address: 0x400409a0 + /// OTG device endpoint-5 control + /// register + pub const OTG_HS_DIEPCTL5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400409c0 + /// OTG device endpoint-6 control + /// register + pub const OTG_HS_DIEPCTL6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400409e0 + /// OTG device endpoint-7 control + /// register + pub const OTG_HS_DIEPCTL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040908 + /// OTG device endpoint-0 interrupt + /// register + pub const OTG_HS_DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x108); + + /// address: 0x40040928 + /// OTG device endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x128); + + /// address: 0x40040948 + /// OTG device endpoint-2 interrupt + /// register + pub const OTG_HS_DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x148); + + /// address: 0x40040968 + /// OTG device endpoint-3 interrupt + /// register + pub const OTG_HS_DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x168); + + /// address: 0x40040988 + /// OTG device endpoint-4 interrupt + /// register + pub const OTG_HS_DIEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x188); + + /// address: 0x400409a8 + /// OTG device endpoint-5 interrupt + /// register + pub const OTG_HS_DIEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1a8); + + /// address: 0x400409c8 + /// OTG device endpoint-6 interrupt + /// register + pub const OTG_HS_DIEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c8); + + /// address: 0x400409e8 + /// OTG device endpoint-7 interrupt + /// register + pub const OTG_HS_DIEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1e8); + + /// address: 0x40040910 + /// OTG_HS device IN endpoint 0 transfer size + /// register + pub const OTG_HS_DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x40040914 + /// OTG_HS device endpoint-1 DMA address + /// register + pub const OTG_HS_DIEPDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040934 + /// OTG_HS device endpoint-2 DMA address + /// register + pub const OTG_HS_DIEPDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040954 + /// OTG_HS device endpoint-3 DMA address + /// register + pub const OTG_HS_DIEPDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040974 + /// OTG_HS device endpoint-4 DMA address + /// register + pub const OTG_HS_DIEPDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040994 + /// OTG_HS device endpoint-5 DMA address + /// register + pub const OTG_HS_DIEPDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x40040918 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x40040938 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x40040958 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x40040978 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x40040998 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x198); + + /// address: 0x400409b8 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1b8); + + /// address: 0x40040930 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040950 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040970 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040990 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400409b0 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x40040b00 + /// OTG_HS device control OUT endpoint 0 control + /// register + pub const OTG_HS_DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x40040b20 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x40040b40 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x40040b60 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x40040b08 + /// OTG_HS device endpoint-0 interrupt + /// register + pub const OTG_HS_DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x308); + + /// address: 0x40040b28 + /// OTG_HS device endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x328); + + /// address: 0x40040b48 + /// OTG_HS device endpoint-2 interrupt + /// register + pub const OTG_HS_DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x348); + + /// address: 0x40040b68 + /// OTG_HS device endpoint-3 interrupt + /// register + pub const OTG_HS_DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x368); + + /// address: 0x40040b88 + /// OTG_HS device endpoint-4 interrupt + /// register + pub const OTG_HS_DOEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x388); + + /// address: 0x40040ba8 + /// OTG_HS device endpoint-5 interrupt + /// register + pub const OTG_HS_DOEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3a8); + + /// address: 0x40040bc8 + /// OTG_HS device endpoint-6 interrupt + /// register + pub const OTG_HS_DOEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3c8); + + /// address: 0x40040be8 + /// OTG_HS device endpoint-7 interrupt + /// register + pub const OTG_HS_DOEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3e8); + + /// address: 0x40040b10 + /// OTG_HS device endpoint-1 transfer size + /// register + pub const OTG_HS_DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x40040b30 + /// OTG_HS device endpoint-2 transfer size + /// register + pub const OTG_HS_DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x40040b50 + /// OTG_HS device endpoint-3 transfer size + /// register + pub const OTG_HS_DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x40040b70 + /// OTG_HS device endpoint-4 transfer size + /// register + pub const OTG_HS_DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + + /// address: 0x40040b90 + /// OTG_HS device endpoint-5 transfer size + /// register + pub const OTG_HS_DOEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x390); + }; + + /// USB on the go high speed + pub const OTG_HS_PWRCLK = struct { + pub const base_address = 0x40040e00; + + /// address: 0x40040e00 + /// Power and clock gating control + /// register + pub const OTG_HS_PCGCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x4); + + /// address: 0xe000e108 + /// Interrupt Set-Enable Register + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x8); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x84); + + /// address: 0xe000e188 + /// Interrupt Clear-Enable + /// Register + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x88); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x104); + + /// address: 0xe000e208 + /// Interrupt Set-Pending Register + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x108); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x184); + + /// address: 0xe000e288 + /// Interrupt Clear-Pending + /// Register + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x188); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x204); + + /// address: 0xe000e308 + /// Interrupt Active Bit Register + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x208); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x300); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x304); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x308); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x30c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x310); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x314); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x318); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x31c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x320); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x324); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x328); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x32c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x330); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x334); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x338); + + /// address: 0xe000e43c + /// Interrupt Priority Register + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x33c); + + /// address: 0xe000e440 + /// Interrupt Priority Register + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x340); + + /// address: 0xe000e444 + /// Interrupt Priority Register + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x344); + + /// address: 0xe000e448 + /// Interrupt Priority Register + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x348); + + /// address: 0xe000e44c + /// Interrupt Priority Register + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x34c); + }; + + /// Serial audio interface + pub const SAI1 = struct { + pub const base_address = 0x40015800; + + /// address: 0x40015804 + /// SAI AConfiguration register 1 + pub const SAI_ACR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OUTDRIV: u1, + reserved1: u1, + reserved2: u1, + /// Audio block enable + SAIAEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCKDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40015824 + /// SAI BConfiguration register 1 + pub const SAI_BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OUTDRIV: u1, + reserved1: u1, + reserved2: u1, + /// Audio block enable + SAIBEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCKDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40015808 + /// SAI AConfiguration register 2 + pub const SAI_ACR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUSH: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECNT: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40015828 + /// SAI BConfiguration register 2 + pub const SAI_BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUSH: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECNT: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4001580c + /// SAI AFrame configuration + /// register + pub const SAI_AFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x4001582c + /// SAI BFrame configuration + /// register + pub const SAI_BFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + + /// address: 0x40015810 + /// SAI ASlot register + pub const SAI_ASLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x10); + + /// address: 0x40015830 + /// SAI BSlot register + pub const SAI_BSLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x30); + + /// address: 0x40015814 + /// SAI AInterrupt mask register2 + pub const SAI_AIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDETIE: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFGIE: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDETIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40015834 + /// SAI BInterrupt mask register2 + pub const SAI_BIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDETIE: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFGIE: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDETIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x34); + + /// address: 0x40015818 + /// SAI AStatus register + pub const SAI_ASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration + /// flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLTH: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x18); + + /// address: 0x40015838 + /// SAI BStatus register + pub const SAI_BSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration + /// flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLTH: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x38); + + /// address: 0x4001581c + /// SAI AClear flag register + pub const SAI_ACLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + COVRUDR: u1, + /// Mute detection flag + CMUTEDET: u1, + /// Clear wrong clock configuration + /// flag + CWCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CCNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + CLFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x1c); + + /// address: 0x4001583c + /// SAI BClear flag register + pub const SAI_BCLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + COVRUDR: u1, + /// Mute detection flag + CMUTEDET: u1, + /// Clear wrong clock configuration + /// flag + CWCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CCNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + CLFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x3c); + + /// address: 0x40015820 + /// SAI AData register + pub const SAI_ADR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x20); + + /// address: 0x40015840 + /// SAI BData register + pub const SAI_BDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x40); + }; + + /// LCD-TFT Controller + pub const LTDC = struct { + pub const base_address = 0x40016800; + + /// address: 0x40016808 + /// Synchronization Size Configuration + /// Register + pub const SSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Synchronization Height (in + /// units of horizontal scan line) + VSH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Horizontal Synchronization Width (in + /// units of pixel clock period) + HSW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4001680c + /// Back Porch Configuration + /// Register + pub const BPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Vertical back porch (in + /// units of horizontal scan line) + AVBP: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Accumulated Horizontal back porch (in + /// units of pixel clock period) + AHBP: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x40016810 + /// Active Width Configuration + /// Register + pub const AWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Active Height (in units of + /// horizontal scan line) + AAH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// AAV + AAV: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x10); + + /// address: 0x40016814 + /// Total Width Configuration + /// Register + pub const TWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Total Height (in units of horizontal + /// scan line) + TOTALH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Total Width (in units of pixel clock + /// period) + TOTALW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x40016818 + /// Global Control Register + pub const GCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LCD-TFT controller enable + /// bit + LTDCEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Dither Blue Width + DBW: u3, + reserved3: u1, + /// Dither Green Width + DGW: u3, + reserved4: u1, + /// Dither Red Width + DRW: u3, + reserved5: u1, + /// Dither Enable + DEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Pixel Clock Polarity + PCPOL: u1, + /// Data Enable Polarity + DEPOL: u1, + /// Vertical Synchronization + /// Polarity + VSPOL: u1, + /// Horizontal Synchronization + /// Polarity + HSPOL: u1, + }), base_address + 0x18); + + /// address: 0x40016824 + /// Shadow Reload Configuration + /// Register + pub const SRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Immediate Reload + IMR: u1, + /// Vertical Blanking Reload + VBR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x24); + + /// address: 0x4001682c + /// Background Color Configuration + /// Register + pub const BCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Background Color Red value + BC: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40016834 + /// Interrupt Enable Register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt + /// Enable + FUIE: u1, + /// Transfer Error Interrupt + /// Enable + TERRIE: u1, + /// Register Reload interrupt + /// enable + RRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x34); + + /// address: 0x40016838 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt + /// flag + FUIF: u1, + /// Transfer Error interrupt + /// flag + TERRIF: u1, + /// Register Reload Interrupt + /// Flag + RRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x38); + + /// address: 0x4001683c + /// Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clears the Line Interrupt + /// Flag + CLIF: u1, + /// Clears the FIFO Underrun Interrupt + /// flag + CFUIF: u1, + /// Clears the Transfer Error Interrupt + /// Flag + CTERRIF: u1, + /// Clears Register Reload Interrupt + /// Flag + CRRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x3c); + + /// address: 0x40016840 + /// Line Interrupt Position Configuration + /// Register + pub const LIPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Position + LIPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x40); + + /// address: 0x40016844 + /// Current Position Status + /// Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, + }), base_address + 0x44); + + /// address: 0x40016848 + /// Current Display Status + /// Register + pub const CDSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Data Enable display + /// Status + VDES: u1, + /// Horizontal Data Enable display + /// Status + HDES: u1, + /// Vertical Synchronization display + /// Status + VSYNCS: u1, + /// Horizontal Synchronization display + /// Status + HSYNCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x48); + + /// address: 0x40016884 + /// Layerx Control Register + pub const L1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x84); + + /// address: 0x40016888 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L1WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4001688c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L1WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8c); + + /// address: 0x40016890 + /// Layerx Color Keying Configuration + /// Register + pub const L1CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x90); + + /// address: 0x40016894 + /// Layerx Pixel Format Configuration + /// Register + pub const L1PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x94); + + /// address: 0x40016898 + /// Layerx Constant Alpha Configuration + /// Register + pub const L1CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x98); + + /// address: 0x4001689c + /// Layerx Default Color Configuration + /// Register + pub const L1DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x9c); + + /// address: 0x400168a0 + /// Layerx Blending Factors Configuration + /// Register + pub const L1BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xa0); + + /// address: 0x400168ac + /// Layerx Color Frame Buffer Address + /// Register + pub const L1CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0xac); + + /// address: 0x400168b0 + /// Layerx Color Frame Buffer Length + /// Register + pub const L1CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0xb0); + + /// address: 0x400168b4 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L1CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xb4); + + /// address: 0x400168c4 + /// Layerx CLUT Write Register + pub const L1CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0xc4); + + /// address: 0x40016904 + /// Layerx Control Register + pub const L2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x104); + + /// address: 0x40016908 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L2WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x108); + + /// address: 0x4001690c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L2WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10c); + + /// address: 0x40016910 + /// Layerx Color Keying Configuration + /// Register + pub const L2CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u7, + /// Color Key Red value + CKRED: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x110); + + /// address: 0x40016914 + /// Layerx Pixel Format Configuration + /// Register + pub const L2PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x114); + + /// address: 0x40016918 + /// Layerx Constant Alpha Configuration + /// Register + pub const L2CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x118); + + /// address: 0x4001691c + /// Layerx Default Color Configuration + /// Register + pub const L2DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x11c); + + /// address: 0x40016920 + /// Layerx Blending Factors Configuration + /// Register + pub const L2BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x120); + + /// address: 0x4001692c + /// Layerx Color Frame Buffer Address + /// Register + pub const L2CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0x12c); + + /// address: 0x40016930 + /// Layerx Color Frame Buffer Length + /// Register + pub const L2CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x130); + + /// address: 0x40016934 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L2CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x134); + + /// address: 0x40016944 + /// Layerx CLUT Write Register + pub const L2CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0x144); + }; + + /// Hash processor + pub const HASH = struct { + pub const base_address = 0x50060400; + + /// address: 0x50060400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Initialize message digest + /// calculation + INIT: u1, + /// DMA enable + DMAE: u1, + /// Data type selection + DATATYPE: u2, + /// Mode selection + MODE: u1, + /// Algorithm selection + ALGO0: u1, + /// Number of words already + /// pushed + NBW: u4, + /// DIN not empty + DINNE: u1, + /// Multiple DMA Transfers + MDMAT: u1, + reserved2: u1, + reserved3: u1, + /// Long key selection + LKEY: u1, + reserved4: u1, + /// ALGO + ALGO1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x50060404 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x4); + + /// address: 0x50060408 + /// start register + pub const STR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of valid bits in the last word of + /// the message + NBLW: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Digest calculation + DCAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5006040c + /// digest registers + pub const HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0xc); + + /// address: 0x50060410 + /// digest registers + pub const HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x10); + + /// address: 0x50060414 + /// digest registers + pub const HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x14); + + /// address: 0x50060418 + /// digest registers + pub const HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x18); + + /// address: 0x5006041c + /// digest registers + pub const HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x1c); + + /// address: 0x50060420 + /// interrupt enable register + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// enable + DINIE: u1, + /// Digest calculation completion interrupt + /// enable + DCIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x20); + + /// address: 0x50060424 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// status + DINIS: u1, + /// Digest calculation completion interrupt + /// status + DCIS: u1, + /// DMA Status + DMAS: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x24); + + /// address: 0x500604f8 + /// context swap registers + pub const CSR0 = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x500604fc + /// context swap registers + pub const CSR1 = @intToPtr(*volatile u32, base_address + 0xfc); + + /// address: 0x50060500 + /// context swap registers + pub const CSR2 = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x50060504 + /// context swap registers + pub const CSR3 = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x50060508 + /// context swap registers + pub const CSR4 = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x5006050c + /// context swap registers + pub const CSR5 = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x50060510 + /// context swap registers + pub const CSR6 = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x50060514 + /// context swap registers + pub const CSR7 = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x50060518 + /// context swap registers + pub const CSR8 = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x5006051c + /// context swap registers + pub const CSR9 = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x50060520 + /// context swap registers + pub const CSR10 = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x50060524 + /// context swap registers + pub const CSR11 = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x50060528 + /// context swap registers + pub const CSR12 = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x5006052c + /// context swap registers + pub const CSR13 = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x50060530 + /// context swap registers + pub const CSR14 = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x50060534 + /// context swap registers + pub const CSR15 = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x50060538 + /// context swap registers + pub const CSR16 = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x5006053c + /// context swap registers + pub const CSR17 = @intToPtr(*volatile u32, base_address + 0x13c); + + /// address: 0x50060540 + /// context swap registers + pub const CSR18 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0x50060544 + /// context swap registers + pub const CSR19 = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x50060548 + /// context swap registers + pub const CSR20 = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x5006054c + /// context swap registers + pub const CSR21 = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x50060550 + /// context swap registers + pub const CSR22 = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x50060554 + /// context swap registers + pub const CSR23 = @intToPtr(*volatile u32, base_address + 0x154); + + /// address: 0x50060558 + /// context swap registers + pub const CSR24 = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x5006055c + /// context swap registers + pub const CSR25 = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x50060560 + /// context swap registers + pub const CSR26 = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x50060564 + /// context swap registers + pub const CSR27 = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x50060568 + /// context swap registers + pub const CSR28 = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x5006056c + /// context swap registers + pub const CSR29 = @intToPtr(*volatile u32, base_address + 0x16c); + + /// address: 0x50060570 + /// context swap registers + pub const CSR30 = @intToPtr(*volatile u32, base_address + 0x170); + + /// address: 0x50060574 + /// context swap registers + pub const CSR31 = @intToPtr(*volatile u32, base_address + 0x174); + + /// address: 0x50060578 + /// context swap registers + pub const CSR32 = @intToPtr(*volatile u32, base_address + 0x178); + + /// address: 0x5006057c + /// context swap registers + pub const CSR33 = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x50060580 + /// context swap registers + pub const CSR34 = @intToPtr(*volatile u32, base_address + 0x180); + + /// address: 0x50060584 + /// context swap registers + pub const CSR35 = @intToPtr(*volatile u32, base_address + 0x184); + + /// address: 0x50060588 + /// context swap registers + pub const CSR36 = @intToPtr(*volatile u32, base_address + 0x188); + + /// address: 0x5006058c + /// context swap registers + pub const CSR37 = @intToPtr(*volatile u32, base_address + 0x18c); + + /// address: 0x50060590 + /// context swap registers + pub const CSR38 = @intToPtr(*volatile u32, base_address + 0x190); + + /// address: 0x50060594 + /// context swap registers + pub const CSR39 = @intToPtr(*volatile u32, base_address + 0x194); + + /// address: 0x50060598 + /// context swap registers + pub const CSR40 = @intToPtr(*volatile u32, base_address + 0x198); + + /// address: 0x5006059c + /// context swap registers + pub const CSR41 = @intToPtr(*volatile u32, base_address + 0x19c); + + /// address: 0x500605a0 + /// context swap registers + pub const CSR42 = @intToPtr(*volatile u32, base_address + 0x1a0); + + /// address: 0x500605a4 + /// context swap registers + pub const CSR43 = @intToPtr(*volatile u32, base_address + 0x1a4); + + /// address: 0x500605a8 + /// context swap registers + pub const CSR44 = @intToPtr(*volatile u32, base_address + 0x1a8); + + /// address: 0x500605ac + /// context swap registers + pub const CSR45 = @intToPtr(*volatile u32, base_address + 0x1ac); + + /// address: 0x500605b0 + /// context swap registers + pub const CSR46 = @intToPtr(*volatile u32, base_address + 0x1b0); + + /// address: 0x500605b4 + /// context swap registers + pub const CSR47 = @intToPtr(*volatile u32, base_address + 0x1b4); + + /// address: 0x500605b8 + /// context swap registers + pub const CSR48 = @intToPtr(*volatile u32, base_address + 0x1b8); + + /// address: 0x500605bc + /// context swap registers + pub const CSR49 = @intToPtr(*volatile u32, base_address + 0x1bc); + + /// address: 0x500605c0 + /// context swap registers + pub const CSR50 = @intToPtr(*volatile u32, base_address + 0x1c0); + + /// address: 0x500605c4 + /// context swap registers + pub const CSR51 = @intToPtr(*volatile u32, base_address + 0x1c4); + + /// address: 0x500605c8 + /// context swap registers + pub const CSR52 = @intToPtr(*volatile u32, base_address + 0x1c8); + + /// address: 0x500605cc + /// context swap registers + pub const CSR53 = @intToPtr(*volatile u32, base_address + 0x1cc); + + /// address: 0x50060710 + /// HASH digest register + pub const HASH_HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0x310); + + /// address: 0x50060714 + /// read-only + pub const HASH_HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x314); + + /// address: 0x50060718 + /// read-only + pub const HASH_HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x318); + + /// address: 0x5006071c + /// read-only + pub const HASH_HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x31c); + + /// address: 0x50060720 + /// read-only + pub const HASH_HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x320); + + /// address: 0x50060724 + /// read-only + pub const HASH_HR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// H5 + H5: u32, + }), base_address + 0x324); + + /// address: 0x50060728 + /// read-only + pub const HASH_HR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// H6 + H6: u32, + }), base_address + 0x328); + + /// address: 0x5006072c + /// read-only + pub const HASH_HR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// H7 + H7: u32, + }), base_address + 0x32c); + }; + + /// Cryptographic processor + pub const CRYP = struct { + pub const base_address = 0x50060000; + + /// address: 0x50060000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Algorithm direction + ALGODIR: u1, + /// Algorithm mode + ALGOMODE0: u3, + /// Data type selection + DATATYPE: u2, + /// Key size selection (AES mode + /// only) + KEYSIZE: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// FIFO flush + FFLUSH: u1, + /// Cryptographic processor + /// enable + CRYPEN: u1, + /// GCM_CCMPH + GCM_CCMPH: u2, + reserved6: u1, + /// ALGOMODE + ALGOMODE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50060004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO empty + IFEM: u1, + /// Input FIFO not full + IFNF: u1, + /// Output FIFO not empty + OFNE: u1, + /// Output FIFO full + OFFU: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x4); + + /// address: 0x50060008 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x8); + + /// address: 0x5006000c + /// data output register + pub const DOUT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data output + DATAOUT: u32, + }), base_address + 0xc); + + /// address: 0x50060010 + /// DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA input enable + DIEN: u1, + /// DMA output enable + DOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x10); + + /// address: 0x50060014 + /// interrupt mask set/clear + /// register + pub const IMSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service interrupt + /// mask + INIM: u1, + /// Output FIFO service interrupt + /// mask + OUTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x50060018 + /// raw interrupt status register + pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service raw interrupt + /// status + INRIS: u1, + /// Output FIFO service raw interrupt + /// status + OUTRIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x18); + + /// address: 0x5006001c + /// masked interrupt status + /// register + pub const MISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service masked interrupt + /// status + INMIS: u1, + /// Output FIFO service masked interrupt + /// status + OUTMIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x1c); + + /// address: 0x50060020 + /// key registers + pub const K0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b224 + b224: u1, + /// b225 + b225: u1, + /// b226 + b226: u1, + /// b227 + b227: u1, + /// b228 + b228: u1, + /// b229 + b229: u1, + /// b230 + b230: u1, + /// b231 + b231: u1, + /// b232 + b232: u1, + /// b233 + b233: u1, + /// b234 + b234: u1, + /// b235 + b235: u1, + /// b236 + b236: u1, + /// b237 + b237: u1, + /// b238 + b238: u1, + /// b239 + b239: u1, + /// b240 + b240: u1, + /// b241 + b241: u1, + /// b242 + b242: u1, + /// b243 + b243: u1, + /// b244 + b244: u1, + /// b245 + b245: u1, + /// b246 + b246: u1, + /// b247 + b247: u1, + /// b248 + b248: u1, + /// b249 + b249: u1, + /// b250 + b250: u1, + /// b251 + b251: u1, + /// b252 + b252: u1, + /// b253 + b253: u1, + /// b254 + b254: u1, + /// b255 + b255: u1, + }), base_address + 0x20); + + /// address: 0x50060024 + /// key registers + pub const K0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b192 + b192: u1, + /// b193 + b193: u1, + /// b194 + b194: u1, + /// b195 + b195: u1, + /// b196 + b196: u1, + /// b197 + b197: u1, + /// b198 + b198: u1, + /// b199 + b199: u1, + /// b200 + b200: u1, + /// b201 + b201: u1, + /// b202 + b202: u1, + /// b203 + b203: u1, + /// b204 + b204: u1, + /// b205 + b205: u1, + /// b206 + b206: u1, + /// b207 + b207: u1, + /// b208 + b208: u1, + /// b209 + b209: u1, + /// b210 + b210: u1, + /// b211 + b211: u1, + /// b212 + b212: u1, + /// b213 + b213: u1, + /// b214 + b214: u1, + /// b215 + b215: u1, + /// b216 + b216: u1, + /// b217 + b217: u1, + /// b218 + b218: u1, + /// b219 + b219: u1, + /// b220 + b220: u1, + /// b221 + b221: u1, + /// b222 + b222: u1, + /// b223 + b223: u1, + }), base_address + 0x24); + + /// address: 0x50060028 + /// key registers + pub const K1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b160 + b160: u1, + /// b161 + b161: u1, + /// b162 + b162: u1, + /// b163 + b163: u1, + /// b164 + b164: u1, + /// b165 + b165: u1, + /// b166 + b166: u1, + /// b167 + b167: u1, + /// b168 + b168: u1, + /// b169 + b169: u1, + /// b170 + b170: u1, + /// b171 + b171: u1, + /// b172 + b172: u1, + /// b173 + b173: u1, + /// b174 + b174: u1, + /// b175 + b175: u1, + /// b176 + b176: u1, + /// b177 + b177: u1, + /// b178 + b178: u1, + /// b179 + b179: u1, + /// b180 + b180: u1, + /// b181 + b181: u1, + /// b182 + b182: u1, + /// b183 + b183: u1, + /// b184 + b184: u1, + /// b185 + b185: u1, + /// b186 + b186: u1, + /// b187 + b187: u1, + /// b188 + b188: u1, + /// b189 + b189: u1, + /// b190 + b190: u1, + /// b191 + b191: u1, + }), base_address + 0x28); + + /// address: 0x5006002c + /// key registers + pub const K1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b128 + b128: u1, + /// b129 + b129: u1, + /// b130 + b130: u1, + /// b131 + b131: u1, + /// b132 + b132: u1, + /// b133 + b133: u1, + /// b134 + b134: u1, + /// b135 + b135: u1, + /// b136 + b136: u1, + /// b137 + b137: u1, + /// b138 + b138: u1, + /// b139 + b139: u1, + /// b140 + b140: u1, + /// b141 + b141: u1, + /// b142 + b142: u1, + /// b143 + b143: u1, + /// b144 + b144: u1, + /// b145 + b145: u1, + /// b146 + b146: u1, + /// b147 + b147: u1, + /// b148 + b148: u1, + /// b149 + b149: u1, + /// b150 + b150: u1, + /// b151 + b151: u1, + /// b152 + b152: u1, + /// b153 + b153: u1, + /// b154 + b154: u1, + /// b155 + b155: u1, + /// b156 + b156: u1, + /// b157 + b157: u1, + /// b158 + b158: u1, + /// b159 + b159: u1, + }), base_address + 0x2c); + + /// address: 0x50060030 + /// key registers + pub const K2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b96 + b96: u1, + /// b97 + b97: u1, + /// b98 + b98: u1, + /// b99 + b99: u1, + /// b100 + b100: u1, + /// b101 + b101: u1, + /// b102 + b102: u1, + /// b103 + b103: u1, + /// b104 + b104: u1, + /// b105 + b105: u1, + /// b106 + b106: u1, + /// b107 + b107: u1, + /// b108 + b108: u1, + /// b109 + b109: u1, + /// b110 + b110: u1, + /// b111 + b111: u1, + /// b112 + b112: u1, + /// b113 + b113: u1, + /// b114 + b114: u1, + /// b115 + b115: u1, + /// b116 + b116: u1, + /// b117 + b117: u1, + /// b118 + b118: u1, + /// b119 + b119: u1, + /// b120 + b120: u1, + /// b121 + b121: u1, + /// b122 + b122: u1, + /// b123 + b123: u1, + /// b124 + b124: u1, + /// b125 + b125: u1, + /// b126 + b126: u1, + /// b127 + b127: u1, + }), base_address + 0x30); + + /// address: 0x50060034 + /// key registers + pub const K2RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b64 + b64: u1, + /// b65 + b65: u1, + /// b66 + b66: u1, + /// b67 + b67: u1, + /// b68 + b68: u1, + /// b69 + b69: u1, + /// b70 + b70: u1, + /// b71 + b71: u1, + /// b72 + b72: u1, + /// b73 + b73: u1, + /// b74 + b74: u1, + /// b75 + b75: u1, + /// b76 + b76: u1, + /// b77 + b77: u1, + /// b78 + b78: u1, + /// b79 + b79: u1, + /// b80 + b80: u1, + /// b81 + b81: u1, + /// b82 + b82: u1, + /// b83 + b83: u1, + /// b84 + b84: u1, + /// b85 + b85: u1, + /// b86 + b86: u1, + /// b87 + b87: u1, + /// b88 + b88: u1, + /// b89 + b89: u1, + /// b90 + b90: u1, + /// b91 + b91: u1, + /// b92 + b92: u1, + /// b93 + b93: u1, + /// b94 + b94: u1, + /// b95 + b95: u1, + }), base_address + 0x34); + + /// address: 0x50060038 + /// key registers + pub const K3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b32 + b32: u1, + /// b33 + b33: u1, + /// b34 + b34: u1, + /// b35 + b35: u1, + /// b36 + b36: u1, + /// b37 + b37: u1, + /// b38 + b38: u1, + /// b39 + b39: u1, + /// b40 + b40: u1, + /// b41 + b41: u1, + /// b42 + b42: u1, + /// b43 + b43: u1, + /// b44 + b44: u1, + /// b45 + b45: u1, + /// b46 + b46: u1, + /// b47 + b47: u1, + /// b48 + b48: u1, + /// b49 + b49: u1, + /// b50 + b50: u1, + /// b51 + b51: u1, + /// b52 + b52: u1, + /// b53 + b53: u1, + /// b54 + b54: u1, + /// b55 + b55: u1, + /// b56 + b56: u1, + /// b57 + b57: u1, + /// b58 + b58: u1, + /// b59 + b59: u1, + /// b60 + b60: u1, + /// b61 + b61: u1, + /// b62 + b62: u1, + /// b63 + b63: u1, + }), base_address + 0x38); + + /// address: 0x5006003c + /// key registers + pub const K3RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b0 + b0: u1, + /// b1 + b1: u1, + /// b2 + b2: u1, + /// b3 + b3: u1, + /// b4 + b4: u1, + /// b5 + b5: u1, + /// b6 + b6: u1, + /// b7 + b7: u1, + /// b8 + b8: u1, + /// b9 + b9: u1, + /// b10 + b10: u1, + /// b11 + b11: u1, + /// b12 + b12: u1, + /// b13 + b13: u1, + /// b14 + b14: u1, + /// b15 + b15: u1, + /// b16 + b16: u1, + /// b17 + b17: u1, + /// b18 + b18: u1, + /// b19 + b19: u1, + /// b20 + b20: u1, + /// b21 + b21: u1, + /// b22 + b22: u1, + /// b23 + b23: u1, + /// b24 + b24: u1, + /// b25 + b25: u1, + /// b26 + b26: u1, + /// b27 + b27: u1, + /// b28 + b28: u1, + /// b29 + b29: u1, + /// b30 + b30: u1, + /// b31 + b31: u1, + }), base_address + 0x3c); + + /// address: 0x50060040 + /// initialization vector + /// registers + pub const IV0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV31 + IV31: u1, + /// IV30 + IV30: u1, + /// IV29 + IV29: u1, + /// IV28 + IV28: u1, + /// IV27 + IV27: u1, + /// IV26 + IV26: u1, + /// IV25 + IV25: u1, + /// IV24 + IV24: u1, + /// IV23 + IV23: u1, + /// IV22 + IV22: u1, + /// IV21 + IV21: u1, + /// IV20 + IV20: u1, + /// IV19 + IV19: u1, + /// IV18 + IV18: u1, + /// IV17 + IV17: u1, + /// IV16 + IV16: u1, + /// IV15 + IV15: u1, + /// IV14 + IV14: u1, + /// IV13 + IV13: u1, + /// IV12 + IV12: u1, + /// IV11 + IV11: u1, + /// IV10 + IV10: u1, + /// IV9 + IV9: u1, + /// IV8 + IV8: u1, + /// IV7 + IV7: u1, + /// IV6 + IV6: u1, + /// IV5 + IV5: u1, + /// IV4 + IV4: u1, + /// IV3 + IV3: u1, + /// IV2 + IV2: u1, + /// IV1 + IV1: u1, + /// IV0 + IV0: u1, + }), base_address + 0x40); + + /// address: 0x50060044 + /// initialization vector + /// registers + pub const IV0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV63 + IV63: u1, + /// IV62 + IV62: u1, + /// IV61 + IV61: u1, + /// IV60 + IV60: u1, + /// IV59 + IV59: u1, + /// IV58 + IV58: u1, + /// IV57 + IV57: u1, + /// IV56 + IV56: u1, + /// IV55 + IV55: u1, + /// IV54 + IV54: u1, + /// IV53 + IV53: u1, + /// IV52 + IV52: u1, + /// IV51 + IV51: u1, + /// IV50 + IV50: u1, + /// IV49 + IV49: u1, + /// IV48 + IV48: u1, + /// IV47 + IV47: u1, + /// IV46 + IV46: u1, + /// IV45 + IV45: u1, + /// IV44 + IV44: u1, + /// IV43 + IV43: u1, + /// IV42 + IV42: u1, + /// IV41 + IV41: u1, + /// IV40 + IV40: u1, + /// IV39 + IV39: u1, + /// IV38 + IV38: u1, + /// IV37 + IV37: u1, + /// IV36 + IV36: u1, + /// IV35 + IV35: u1, + /// IV34 + IV34: u1, + /// IV33 + IV33: u1, + /// IV32 + IV32: u1, + }), base_address + 0x44); + + /// address: 0x50060048 + /// initialization vector + /// registers + pub const IV1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV95 + IV95: u1, + /// IV94 + IV94: u1, + /// IV93 + IV93: u1, + /// IV92 + IV92: u1, + /// IV91 + IV91: u1, + /// IV90 + IV90: u1, + /// IV89 + IV89: u1, + /// IV88 + IV88: u1, + /// IV87 + IV87: u1, + /// IV86 + IV86: u1, + /// IV85 + IV85: u1, + /// IV84 + IV84: u1, + /// IV83 + IV83: u1, + /// IV82 + IV82: u1, + /// IV81 + IV81: u1, + /// IV80 + IV80: u1, + /// IV79 + IV79: u1, + /// IV78 + IV78: u1, + /// IV77 + IV77: u1, + /// IV76 + IV76: u1, + /// IV75 + IV75: u1, + /// IV74 + IV74: u1, + /// IV73 + IV73: u1, + /// IV72 + IV72: u1, + /// IV71 + IV71: u1, + /// IV70 + IV70: u1, + /// IV69 + IV69: u1, + /// IV68 + IV68: u1, + /// IV67 + IV67: u1, + /// IV66 + IV66: u1, + /// IV65 + IV65: u1, + /// IV64 + IV64: u1, + }), base_address + 0x48); + + /// address: 0x5006004c + /// initialization vector + /// registers + pub const IV1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV127 + IV127: u1, + /// IV126 + IV126: u1, + /// IV125 + IV125: u1, + /// IV124 + IV124: u1, + /// IV123 + IV123: u1, + /// IV122 + IV122: u1, + /// IV121 + IV121: u1, + /// IV120 + IV120: u1, + /// IV119 + IV119: u1, + /// IV118 + IV118: u1, + /// IV117 + IV117: u1, + /// IV116 + IV116: u1, + /// IV115 + IV115: u1, + /// IV114 + IV114: u1, + /// IV113 + IV113: u1, + /// IV112 + IV112: u1, + /// IV111 + IV111: u1, + /// IV110 + IV110: u1, + /// IV109 + IV109: u1, + /// IV108 + IV108: u1, + /// IV107 + IV107: u1, + /// IV106 + IV106: u1, + /// IV105 + IV105: u1, + /// IV104 + IV104: u1, + /// IV103 + IV103: u1, + /// IV102 + IV102: u1, + /// IV101 + IV101: u1, + /// IV100 + IV100: u1, + /// IV99 + IV99: u1, + /// IV98 + IV98: u1, + /// IV97 + IV97: u1, + /// IV96 + IV96: u1, + }), base_address + 0x4c); + + /// address: 0x50060050 + /// context swap register + pub const CSGCMCCM0R = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0x50060054 + /// context swap register + pub const CSGCMCCM1R = @intToPtr(*volatile u32, base_address + 0x54); + + /// address: 0x50060058 + /// context swap register + pub const CSGCMCCM2R = @intToPtr(*volatile u32, base_address + 0x58); + + /// address: 0x5006005c + /// context swap register + pub const CSGCMCCM3R = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0x50060060 + /// context swap register + pub const CSGCMCCM4R = @intToPtr(*volatile u32, base_address + 0x60); + + /// address: 0x50060064 + /// context swap register + pub const CSGCMCCM5R = @intToPtr(*volatile u32, base_address + 0x64); + + /// address: 0x50060068 + /// context swap register + pub const CSGCMCCM6R = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0x5006006c + /// context swap register + pub const CSGCMCCM7R = @intToPtr(*volatile u32, base_address + 0x6c); + + /// address: 0x50060070 + /// context swap register + pub const CSGCM0R = @intToPtr(*volatile u32, base_address + 0x70); + + /// address: 0x50060074 + /// context swap register + pub const CSGCM1R = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0x50060078 + /// context swap register + pub const CSGCM2R = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x5006007c + /// context swap register + pub const CSGCM3R = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x50060080 + /// context swap register + pub const CSGCM4R = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x50060084 + /// context swap register + pub const CSGCM5R = @intToPtr(*volatile u32, base_address + 0x84); + + /// address: 0x50060088 + /// context swap register + pub const CSGCM6R = @intToPtr(*volatile u32, base_address + 0x88); + + /// address: 0x5006008c + /// context swap register + pub const CSGCM7R = @intToPtr(*volatile u32, base_address + 0x8c); + }; + + /// Floting point unit + pub const FPU = struct { + pub const base_address = 0xe000ef34; + + /// address: 0xe000ef34 + /// Floating-point context control + /// register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved0: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved1: u1, + /// MONRDY + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), base_address + 0x0); + + /// address: 0xe000ef38 + /// Floating-point context address + /// register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Location of unpopulated + /// floating-point + ADDRESS: u29, + }), base_address + 0x4); + + /// address: 0xe000ef3c + /// Floating-point status control + /// register + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Invalid operation cumulative exception + /// bit + IOC: u1, + /// Division by zero cumulative exception + /// bit. + DZC: u1, + /// Overflow cumulative exception + /// bit + OFC: u1, + /// Underflow cumulative exception + /// bit + UFC: u1, + /// Inexact cumulative exception + /// bit + IXC: u1, + reserved0: u1, + reserved1: u1, + /// Input denormal cumulative exception + /// bit. + IDC: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Rounding Mode control + /// field + RMode: u2, + /// Flush-to-zero mode control + /// bit: + FZ: u1, + /// Default NaN mode control + /// bit + DN: u1, + /// Alternative half-precision control + /// bit + AHP: u1, + reserved16: u1, + /// Overflow condition code + /// flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code + /// flag + N: u1, + }), base_address + 0x8); + }; + + /// Memory protection unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU type register + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Separate flag + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction + /// regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU control register + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard + /// fault + HFNMIENA: u1, + /// Enable priviliged software access to + /// default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU region number register + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU region base address + /// register + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU region attribute and size + /// register + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection + /// region + SIZE: u5, + reserved0: u1, + reserved1: u1, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved2: u1, + reserved3: u1, + /// Access permission + AP: u3, + reserved4: u1, + /// Instruction access disable + /// bit + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + }; + + /// SysTick timer + pub const STK = struct { + pub const base_address = 0xe000e010; + + /// address: 0xe000e010 + /// SysTick control and status + /// register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + ENABLE: u1, + /// SysTick exception request + /// enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// COUNTFLAG + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0xe000e014 + /// SysTick reload value register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + /// RELOAD value + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0xe000e018 + /// SysTick current value register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Current counter value + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0xe000e01c + /// SysTick calibration value + /// register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration value + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// SKEW flag: Indicates whether the TENMS + /// value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), base_address + 0xc); + }; + + /// System control block + pub const SCB = struct { + pub const base_address = 0xe000ed00; + + /// address: 0xe000ed00 + /// CPUID base register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Revision number + Revision: u4, + /// Part number of the + /// processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), base_address + 0x0); + + /// address: 0xe000ed04 + /// Interrupt control and state + /// register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active vector + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt pending flag + ISRPENDING: u1, + reserved5: u1, + reserved6: u1, + /// SysTick exception clear-pending + /// bit + PENDSTCLR: u1, + /// SysTick exception set-pending + /// bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), base_address + 0x4); + + /// address: 0xe000ed08 + /// Vector table offset register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Vector table base offset + /// field + TBLOFF: u21, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0xe000ed0c + /// Application interrupt and reset control + /// register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PRIGROUP + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), base_address + 0xc); + + /// address: 0xe000ed10 + /// System control register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0xe000ed14 + /// Configuration and control + /// register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Configures how the processor enters + /// Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved0: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0xe000ed18 + /// System handler priority + /// registers + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Priority of system handler + /// 4 + PRI_4: u8, + /// Priority of system handler + /// 5 + PRI_5: u8, + /// Priority of system handler + /// 6 + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000ed1c + /// System handler priority + /// registers + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler + /// 11 + PRI_11: u8, + }), base_address + 0x1c); + + /// address: 0xe000ed20 + /// System handler priority + /// registers + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler + /// 14 + PRI_14: u8, + /// Priority of system handler + /// 15 + PRI_15: u8, + }), base_address + 0x20); + + /// address: 0xe000ed24 + /// System handler control and state + /// register + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory management fault exception active + /// bit + MEMFAULTACT: u1, + /// Bus fault exception active + /// bit + BUSFAULTACT: u1, + reserved0: u1, + /// Usage fault exception active + /// bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active + /// bit + PENDSVACT: u1, + /// SysTick exception active + /// bit + SYSTICKACT: u1, + /// Usage fault exception pending + /// bit + USGFAULTPENDED: u1, + /// Memory management fault exception + /// pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending + /// bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable + /// bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0xe000ed28 + /// Configurable fault status + /// register + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Instruction access violation + /// flag + IACCVIOL: u1, + reserved1: u1, + /// Memory manager fault on unstacking for a + /// return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for + /// exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved2: u1, + /// Memory Management Fault Address Register + /// (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return + /// from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception + /// entry + STKERR: u1, + /// Bus fault on floating-point lazy state + /// preservation + LSPERR: u1, + reserved3: u1, + /// Bus Fault Address Register (BFAR) valid + /// flag + BFARVALID: u1, + /// Undefined instruction usage + /// fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage + /// fault + INVPC: u1, + /// No coprocessor usage + /// fault. + NOCP: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Unaligned access usage + /// fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0xe000ed2c + /// Hard fault status register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), base_address + 0x2c); + + /// address: 0xe000ed34 + /// Memory management fault address + /// register + pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0xe000ed38 + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0xe000ed3c + /// Auxiliary fault status + /// register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Implementation defined + IMPDEF: u32, + }), base_address + 0x3c); + }; + + /// Nested vectored interrupt + /// controller + pub const NVIC_STIR = struct { + pub const base_address = 0xe000ef00; + + /// address: 0xe000ef00 + /// Software trigger interrupt + /// register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Software generated interrupt + /// ID + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = struct { + pub const base_address = 0xe000ed88; + + /// address: 0xe000ed88 + /// Coprocessor access control + /// register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// CP + CP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + }; + + /// System control block ACTLR + pub const SCB_ACTRL = struct { + pub const base_address = 0xe000e008; + + /// address: 0xe000e008 + /// Auxiliary control register + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig new file mode 100644 index 0000000..1619f72 --- /dev/null +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -0,0 +1,79 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code currently assumes the STM32F405xx / STM32F407xx clock configuration. +//! TODO: Do something useful for other STM32F40x chips. +//! +//! Specifically, TIM6 is running on a 16 MHz clock, +//! HSI = 16 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 16 MHz. +//! And with the default APB1 prescaler = /1: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE1 = 0 }); +//! ``` +//! +//! results in PCLK1 = 16 MHz. +//! +//! TODO: add more clock calculations when adding Uart + +const std = @import("std"); +const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'I') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'I' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn setInput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + switch (state) { + .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), + .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; diff --git a/tests/blinky.zig b/tests/blinky.zig index 0e702d0..543f4da 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -6,6 +6,7 @@ const led_pin = if (micro.config.has_board) .@"Arduino Nano" => micro.Pin("D13"), .@"mbed LPC1768" => micro.Pin("LED-1"), .@"STM32F3DISCOVERY" => micro.Pin("LD3"), + .@"STM32F4DISCOVERY" => micro.Pin("LD5"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) { From d3c539e35b242edf0607fcb28fe8fa08aa6f6ae0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Thu, 31 Mar 2022 09:13:36 +0200 Subject: [PATCH 043/138] Avr fixes (#36) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Makes AVR UART work. Co-authored-by: Felix "xq" Queißner --- src/modules/chips/atmega328p/atmega328p.zig | 129 +++++++++++++++++++- src/modules/chips/atmega328p/registers.zig | 4 +- 2 files changed, 125 insertions(+), 8 deletions(-) diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 32ffbb6..43022a8 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -1,6 +1,8 @@ const std = @import("std"); const micro = @import("microzig"); + pub usingnamespace @import("registers.zig"); +const regz = @import("registers.zig").registers; pub const cpu = micro.cpu; const Port = enum(u8) { @@ -26,13 +28,15 @@ pub fn parsePin(comptime spec: []const u8) type { pub const gpio = struct { fn regs(comptime desc: type) type { return struct { - const pin_addr = 3 * @enumToInt(desc.port) + 0x00; - const dir_addr = 3 * @enumToInt(desc.port) + 0x01; - const port_addr = 3 * @enumToInt(desc.port) + 0x02; + // io address + const pin_addr: u5 = 3 * @enumToInt(desc.port) + 0x00; + const dir_addr: u5 = 3 * @enumToInt(desc.port) + 0x01; + const port_addr: u5 = 3 * @enumToInt(desc.port) + 0x02; - const pin = @intToPtr(*volatile u8, pin_addr); - const dir = @intToPtr(*volatile u8, dir_addr); - const port = @intToPtr(*volatile u8, port_addr); + // ram mapping + const pin = @intToPtr(*volatile u8, 0x20 + @as(usize, pin_addr)); + const dir = @intToPtr(*volatile u8, 0x20 + @as(usize, dir_addr)); + const port = @intToPtr(*volatile u8, 0x20 + @as(usize, port_addr)); }; } @@ -63,3 +67,116 @@ pub const gpio = struct { cpu.sbi(regs(pin).pin_addr, pin.pin); } }; + +pub const uart = struct { + pub const DataBits = enum { + five, + six, + seven, + eight, + nine, + }; + + pub const StopBits = enum { + one, + two, + }; + + pub const Parity = enum { + odd, + even, + }; +}; + +pub fn Uart(comptime index: usize) type { + if (index != 0) @compileError("Atmega328p only has a single uart!"); + return struct { + const Self = @This(); + + fn computeDivider(baud_rate: u32) !u12 { + const pclk = micro.clock.get(); + const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; + + return std.math.cast(u12, divider) catch return error.UnsupportedBaudRate; + } + + fn computeBaudRate(divider: u12) u32 { + return micro.clock.get() / (16 * @as(u32, divider) + 1); + } + + pub fn init(config: micro.uart.Config) !Self { + const ucsz: u3 = switch (config.data_bits) { + .five => 0b000, + .six => 0b001, + .seven => 0b010, + .eight => 0b011, + .nine => return error.UnsupportedWordSize, // 0b111 + }; + + const upm: u2 = if (config.parity) |parity| switch (parity) { + .even => @as(u2, 0b10), // even + .odd => @as(u2, 0b11), // odd + } else 0b00; // parity disabled + + const usbs: u1 = switch (config.stop_bits) { + .one => 0b0, + .two => 0b1, + }; + + const umsel: u2 = 0b00; // Asynchronous USART + + // baud is computed like this: + // f(osc) + // BAUD = ---------------- + // 16 * (UBRRn + 1) + + const ubrr_val = try computeDivider(config.baud_rate); + + regz.USART0.UCSR0A.modify(.{ + .MPCM0 = 0, + .U2X0 = 0, + }); + regz.USART0.UCSR0B.write(.{ + .TXB80 = 0, // we don't care about these btw + .RXB80 = 0, // we don't care about these btw + .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2), + .TXEN0 = 1, + .RXEN0 = 1, + .UDRIE0 = 0, // no interrupts + .TXCIE0 = 0, // no interrupts + .RXCIE0 = 0, // no interrupts + }); + regz.USART0.UCSR0C.write(.{ + .UCPOL0 = 0, // async mode + .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0), + .USBS0 = usbs, + .UPM0 = upm, + .UMSEL0 = umsel, + }); + + regz.USART0.UBRR0.modify(ubrr_val); + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return (regz.USART0.UCSR0A.read().UDRE0 == 1); + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + regz.USART0.UDR0.* = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + _ = self; + return (regz.USART0.UCSR0A.read().RXC0 == 1); + } + + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return regz.USART0.UDR0.*; // Read received data + } + }; +} diff --git a/src/modules/chips/atmega328p/registers.zig b/src/modules/chips/atmega328p/registers.zig index 06d4880..0c27f21 100644 --- a/src/modules/chips/atmega328p/registers.zig +++ b/src/modules/chips/atmega328p/registers.zig @@ -279,7 +279,7 @@ pub const registers = struct { /// address: 0xc4 /// USART Baud Rate Register Bytes - pub const UBRR0 = @intToPtr(*volatile u12, 0xc4); + pub const UBRR0 = @intToPtr(*volatile MmioInt(16, u12), 0xc4); }; /// Two Wire Serial Interface @@ -1110,7 +1110,7 @@ pub const registers = struct { /// address: 0x5d /// Stack Pointer - pub const SP = @intToPtr(*volatile u12, 0x5d); + pub const SP = @intToPtr(*volatile MmioInt(16, u12), 0x5d); /// address: 0x57 /// Store Program Memory Control and Status Register From f317ce0c9f593c3da554a1f0e314ff406bc67fc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Thu, 31 Mar 2022 12:06:01 +0200 Subject: [PATCH 044/138] More improvements (#37) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Makes AVR UART work. * Some comment. This is definitly not padding. * Exports panic, log and log_level from application. * Implements generic quadrature decoder driver. * Fixes `@export` bug in AVR interrupt logic. Now we get distinct interrupt vectors. Co-authored-by: Felix "xq" Queißner --- src/core/gpio.zig | 4 +++ src/core/microzig.zig | 31 +++++++++++++++++----- src/drivers/quadrature.zig | 50 +++++++++++++++++++++++++++++++++++ src/main.zig | 9 +++++++ src/modules/cpus/avr/avr5.zig | 50 ++++++++++++++++++++--------------- 5 files changed, 116 insertions(+), 28 deletions(-) create mode 100644 src/drivers/quadrature.zig diff --git a/src/core/gpio.zig b/src/core/gpio.zig index 4008b89..44e3729 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -13,6 +13,10 @@ pub const Mode = enum { pub const State = enum(u1) { low = 0, high = 1, + + pub fn value(self: State) u1 { + return @enumToInt(self); + } }; pub const Drive = enum(u1) { diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 7d82417..8df10fc 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -46,13 +46,30 @@ pub const debug = @import("debug.zig"); pub const mmio = @import("mmio.zig"); -/// The microzig panic handler. Will disable interrupts and loop endlessly. -/// Export this symbol from your main file to enable microzig: -/// ``` -/// const micro = @import("microzig"); -/// pub const panic = micro.panic; -/// ``` -pub fn panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { +// Allow app to override the panic handler +pub const panic = if (@hasDecl(app, "panic")) + app.panic +else + microzig_panic; + +// Conditionally export log_level if the app has it defined. +usingnamespace if (@hasDecl(app, "log_level")) + struct { + pub const log_level = app.log_level; + } +else + struct {}; + +// Conditionally export log() if the app has it defined. +usingnamespace if (@hasDecl(app, "log")) + struct { + pub const log = app.log; + } +else + struct {}; + +/// The microzig default panic handler. Will disable interrupts and loop endlessly. +pub fn microzig_panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { // utilize logging functions std.log.err("microzig PANIC: {s}", .{message}); diff --git a/src/drivers/quadrature.zig b/src/drivers/quadrature.zig new file mode 100644 index 0000000..c76ecab --- /dev/null +++ b/src/drivers/quadrature.zig @@ -0,0 +1,50 @@ +const micro = @import("microzig"); + +pub const Event = enum { + /// No change since the last decoding happened + idle, + /// The quadrature signal incremented a step. + increment, + /// The quadrature signal decremented a step. + decrement, + /// The quadrature signal skipped a sequence point and entered a invalid state. + @"error", +}; + +pub fn Decoder(comptime pin_a: type, comptime pin_b: type) type { + return struct { + const Self = @This(); + + last_a: micro.gpio.State, + last_b: micro.gpio.State, + + pub fn init() Self { + pin_a.init(); + pin_b.init(); + return Self{ + .last_a = pin_a.read(), + .last_b = pin_b.read(), + }; + } + + pub fn tick(self: *Self) Event { + var a = pin_a.read(); + var b = pin_b.read(); + defer self.last_a = a; + defer self.last_b = b; + + const enable = a.value() ^ b.value() ^ self.last_a.value() ^ self.last_b.value(); + const direction = a.value() ^ self.last_b.value(); + + if (enable != 0) { + if (direction != 0) { + return .increment; + } else { + return .decrement; + } + } else { + return .idle; + } + } + }; +} diff --git a/src/main.zig b/src/main.zig index 721a405..406283a 100644 --- a/src/main.zig +++ b/src/main.zig @@ -181,3 +181,12 @@ const pkgs = struct { .path = .{ .path = root_path ++ "core/import-package.zig" }, }; }; + +/// Generic purpose drivers shipped with microzig +pub const drivers = struct { + pub const quadrature = std.build.Pkg{ + .name = "microzig.quadrature", + .path = .{ .path = root_path ++ "drivers/quadrature.zig" }, + .dependencies = &.{pkgs.microzig}, + }; +}; diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr/avr5.zig index cf79b74..659157d 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr/avr5.zig @@ -52,27 +52,10 @@ pub const vector_table = blk: { const new_insn = if (has_interrupts) overload: { if (@hasDecl(microzig.app.interrupts, field.name)) { const handler = @field(microzig.app.interrupts, field.name); - const calling_convention = switch (@typeInfo(@TypeOf(@field(microzig.app.interrupts, field.name)))) { - .Fn => |info| info.calling_convention, - else => @compileError("Declarations in 'interrupts' namespace must all be functions. '" ++ field.name ++ "' is not a function"), - }; - - const exported_fn = switch (calling_convention) { - .Unspecified => struct { - fn wrapper() callconv(.Signal) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - .Signal => handler, - .Interrupt => handler, - else => @compileError("Calling conventions for interrupts must be 'Interrupt', 'Signal', or unspecified. The signal calling convention leaves global interrupts disabled during the ISR, where the interrupt calling conventions enables global interrupts for nested ISRs."), - }; - - const exported_name = "microzig_isr_" ++ field.name; - const options = .{ .name = exported_name, .linkage = .Strong }; - @export(exported_fn, options); - break :overload "jmp " ++ exported_name; + + const isr = makeIsrHandler(field.name, handler); + + break :overload "jmp " ++ isr.exported_name; } else { break :overload "jmp microzig_unhandled_vector"; } @@ -90,6 +73,31 @@ pub const vector_table = blk: { break :blk T._start; }; +fn makeIsrHandler(comptime name: []const u8, comptime func: anytype) type { + const calling_convention = switch (@typeInfo(@TypeOf(func))) { + .Fn => |info| info.calling_convention, + else => @compileError("Declarations in 'interrupts' namespace must all be functions. '" ++ name ++ "' is not a function"), + }; + + switch (calling_convention) { + .Unspecified, .Signal, .Interrupt => {}, + else => @compileError("Calling conventions for interrupts must be 'Interrupt', 'Signal', or unspecified. The signal calling convention leaves global interrupts disabled during the ISR, where the interrupt calling conventions enables global interrupts for nested ISRs."), + } + + return struct { + pub const exported_name = "microzig_isr_" ++ name; + + pub fn isr_vector() callconv(.Signal) void { + @call(.{ .modifier = .always_inline }, func, .{}); + } + + comptime { + const options = .{ .name = exported_name, .linkage = .Strong }; + @export(isr_vector, options); + } + }; +} + pub const startup_logic = struct { export fn microzig_unhandled_vector() callconv(.Naked) noreturn { @panic("Unhandled interrupt"); From 873e5995b65c0515b5db3f088f92d2cfd60e6b53 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Fri, 1 Apr 2022 02:45:50 +0200 Subject: [PATCH 045/138] Add initial support for the stm32f429idiscovery eval board (#38) * Add stm32f429 registers Generated using regz with: ./regz STM32F429.svd > registers.zig Using this SVD: https://github.com/posborne/cmsis-svd/blob/871761af63200f5edad553b03fe0482113ac6a60/data/STMicro/STM32F429.svd * Add initial support for the stm32f429idiscovery eval board Blinky example working on the board --- build.zig | 1 + src/modules/boards.zig | 6 + .../stm32f429idiscovery.zig | 15 + src/modules/chips.zig | 12 + src/modules/chips/stm32f429/registers.zig | 53887 ++++++++++++++++ src/modules/chips/stm32f429/stm32f429.zig | 78 + tests/blinky.zig | 1 + 7 files changed, 54000 insertions(+) create mode 100644 src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig create mode 100644 src/modules/chips/stm32f429/registers.zig create mode 100644 src/modules/chips/stm32f429/stm32f429.zig diff --git a/build.zig b/build.zig index bb60c58..c63cb0f 100644 --- a/build.zig +++ b/build.zig @@ -23,6 +23,7 @@ pub fn build(b: *std.build.Builder) !void { //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery }, .supports_uart_test = false }, + BuildConfig{ .name = "boards.stm32f429idiscovery", .backing = Backing{ .board = boards.stm32f429idiscovery }, .supports_uart_test = false }, }; const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true }; diff --git a/src/modules/boards.zig b/src/modules/boards.zig index 954cd4b..6793a7b 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -31,3 +31,9 @@ pub const stm32f4discovery = Board{ .path = root_path ++ "boards/stm32f4discovery/stm32f4discovery.zig", .chip = chips.stm32f407vg, }; + +pub const stm32f429idiscovery = Board{ + .name = "STM32F429IDISCOVERY", + .path = root_path ++ "boards/stm32f429idiscovery/stm32f429idiscovery.zig", + .chip = chips.stm32f429zit6u, +}; diff --git a/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig b/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig new file mode 100644 index 0000000..35418d6 --- /dev/null +++ b/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig @@ -0,0 +1,15 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 16_000_000; + +pub const pin_map = .{ + // LEDs, connected to GPIOG bits 13, 14 + // green + .@"LD3" = "PG13", + // red + .@"LD4" = "PG14", + + // User button + .@"B1" = "PA0", +}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 52504d5..5a2d5a0 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -62,6 +62,18 @@ pub const stm32f407vg = Chip{ }, }; +pub const stm32f429zit6u = Chip{ + .name = "STM32F429ZIT6U", + .path = root_path ++ "chips/stm32f429/stm32f429.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram }, + // CCM RAM + MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, + }, +}; + pub const nrf52832 = Chip{ .name = "nRF52832", .path = root_path ++ "chips/nrf52/nrf52.zig", diff --git a/src/modules/chips/stm32f429/registers.zig b/src/modules/chips/stm32f429/registers.zig new file mode 100644 index 0000000..7bd4b62 --- /dev/null +++ b/src/modules/chips/stm32f429/registers.zig @@ -0,0 +1,53887 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 6376709051af4d8920d5c8bb48945ca688af32ae +// +// device: STM32F429 +// cpu: CM4 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + /// Window Watchdog interrupt + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, + /// Tamper and TimeStamp interrupts through the + /// EXTI line + TAMP_STAMP: InterruptVector = unhandled, + /// RTC Wakeup interrupt through the EXTI + /// line + RTC_WKUP: InterruptVector = unhandled, + /// Flash global interrupt + FLASH: InterruptVector = unhandled, + /// RCC global interrupt + RCC: InterruptVector = unhandled, + /// EXTI Line0 interrupt + EXTI0: InterruptVector = unhandled, + /// EXTI Line1 interrupt + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 interrupt + EXTI2: InterruptVector = unhandled, + /// EXTI Line3 interrupt + EXTI3: InterruptVector = unhandled, + /// EXTI Line4 interrupt + EXTI4: InterruptVector = unhandled, + /// DMA1 Stream0 global interrupt + DMA1_Stream0: InterruptVector = unhandled, + /// DMA1 Stream1 global interrupt + DMA1_Stream1: InterruptVector = unhandled, + /// DMA1 Stream2 global interrupt + DMA1_Stream2: InterruptVector = unhandled, + /// DMA1 Stream3 global interrupt + DMA1_Stream3: InterruptVector = unhandled, + /// DMA1 Stream4 global interrupt + DMA1_Stream4: InterruptVector = unhandled, + /// DMA1 Stream5 global interrupt + DMA1_Stream5: InterruptVector = unhandled, + /// DMA1 Stream6 global interrupt + DMA1_Stream6: InterruptVector = unhandled, + /// ADC2 global interrupts + ADC: InterruptVector = unhandled, + /// CAN1 TX interrupts + CAN1_TX: InterruptVector = unhandled, + /// CAN1 RX0 interrupts + CAN1_RX0: InterruptVector = unhandled, + /// CAN1 RX1 interrupts + CAN1_RX1: InterruptVector = unhandled, + /// CAN1 SCE interrupt + CAN1_SCE: InterruptVector = unhandled, + /// EXTI Line[9:5] interrupts + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break interrupt and TIM9 global + /// interrupt + TIM1_BRK_TIM9: InterruptVector = unhandled, + /// TIM1 Update interrupt and TIM10 global + /// interrupt + TIM1_UP_TIM10: InterruptVector = unhandled, + /// TIM1 Trigger and Commutation interrupts and + /// TIM11 global interrupt + TIM1_TRG_COM_TIM11: InterruptVector = unhandled, + /// TIM1 Capture Compare interrupt + TIM1_CC: InterruptVector = unhandled, + /// TIM2 global interrupt + TIM2: InterruptVector = unhandled, + /// TIM3 global interrupt + TIM3: InterruptVector = unhandled, + /// TIM4 global interrupt + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt + I2C1_EV: InterruptVector = unhandled, + /// I2C1 error interrupt + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt + I2C2_EV: InterruptVector = unhandled, + /// I2C2 error interrupt + I2C2_ER: InterruptVector = unhandled, + /// SPI1 global interrupt + SPI1: InterruptVector = unhandled, + /// SPI2 global interrupt + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt + USART1: InterruptVector = unhandled, + /// USART2 global interrupt + USART2: InterruptVector = unhandled, + /// USART3 global interrupt + USART3: InterruptVector = unhandled, + /// EXTI Line[15:10] interrupts + EXTI15_10: InterruptVector = unhandled, + /// RTC Alarms (A and B) through EXTI line + /// interrupt + RTC_Alarm: InterruptVector = unhandled, + /// USB On-The-Go FS Wakeup through EXTI line + /// interrupt + OTG_FS_WKUP: InterruptVector = unhandled, + /// TIM8 Break interrupt and TIM12 global + /// interrupt + TIM8_BRK_TIM12: InterruptVector = unhandled, + /// TIM8 Update interrupt and TIM13 global + /// interrupt + TIM8_UP_TIM13: InterruptVector = unhandled, + /// TIM8 Trigger and Commutation interrupts and + /// TIM14 global interrupt + TIM8_TRG_COM_TIM14: InterruptVector = unhandled, + /// TIM8 Capture Compare interrupt + TIM8_CC: InterruptVector = unhandled, + /// DMA1 Stream7 global interrupt + DMA1_Stream7: InterruptVector = unhandled, + /// FMC global interrupt + FMC: InterruptVector = unhandled, + /// SDIO global interrupt + SDIO: InterruptVector = unhandled, + /// TIM5 global interrupt + TIM5: InterruptVector = unhandled, + /// SPI3 global interrupt + SPI3: InterruptVector = unhandled, + /// UART4 global interrupt + UART4: InterruptVector = unhandled, + /// UART5 global interrupt + UART5: InterruptVector = unhandled, + /// TIM6 global interrupt, DAC1 and DAC2 underrun + /// error interrupt + TIM6_DAC: InterruptVector = unhandled, + /// TIM7 global interrupt + TIM7: InterruptVector = unhandled, + /// DMA2 Stream0 global interrupt + DMA2_Stream0: InterruptVector = unhandled, + /// DMA2 Stream1 global interrupt + DMA2_Stream1: InterruptVector = unhandled, + /// DMA2 Stream2 global interrupt + DMA2_Stream2: InterruptVector = unhandled, + /// DMA2 Stream3 global interrupt + DMA2_Stream3: InterruptVector = unhandled, + /// DMA2 Stream4 global interrupt + DMA2_Stream4: InterruptVector = unhandled, + /// Ethernet global interrupt + ETH: InterruptVector = unhandled, + /// Ethernet Wakeup through EXTI line + /// interrupt + ETH_WKUP: InterruptVector = unhandled, + /// CAN2 TX interrupts + CAN2_TX: InterruptVector = unhandled, + /// CAN2 RX0 interrupts + CAN2_RX0: InterruptVector = unhandled, + /// CAN2 RX1 interrupts + CAN2_RX1: InterruptVector = unhandled, + /// CAN2 SCE interrupt + CAN2_SCE: InterruptVector = unhandled, + /// USB On The Go FS global + /// interrupt + OTG_FS: InterruptVector = unhandled, + /// DMA2 Stream5 global interrupt + DMA2_Stream5: InterruptVector = unhandled, + /// DMA2 Stream6 global interrupt + DMA2_Stream6: InterruptVector = unhandled, + /// DMA2 Stream7 global interrupt + DMA2_Stream7: InterruptVector = unhandled, + /// USART6 global interrupt + USART6: InterruptVector = unhandled, + /// I2C3 event interrupt + I2C3_EV: InterruptVector = unhandled, + /// I2C3 error interrupt + I2C3_ER: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 Out global + /// interrupt + OTG_HS_EP1_OUT: InterruptVector = unhandled, + /// USB On The Go HS End Point 1 In global + /// interrupt + OTG_HS_EP1_IN: InterruptVector = unhandled, + /// USB On The Go HS Wakeup through EXTI + /// interrupt + OTG_HS_WKUP: InterruptVector = unhandled, + /// USB On The Go HS global + /// interrupt + OTG_HS: InterruptVector = unhandled, + /// DCMI global interrupt + DCMI: InterruptVector = unhandled, + /// CRYP crypto global interrupt + CRYP: InterruptVector = unhandled, + /// Hash and Rng global interrupt + HASH_RNG: InterruptVector = unhandled, + /// FPU interrupt + FPU: InterruptVector = unhandled, + /// UART 7 global interrupt + UART7: InterruptVector = unhandled, + /// UART 8 global interrupt + UART8: InterruptVector = unhandled, + /// SPI 4 global interrupt + SPI4: InterruptVector = unhandled, + /// SPI 5 global interrupt + SPI5: InterruptVector = unhandled, + /// SPI 6 global interrupt + SPI6: InterruptVector = unhandled, + /// SAI1 global interrupt + SAI1: InterruptVector = unhandled, + /// LTDC global interrupt + LCD_TFT: InterruptVector = unhandled, + /// LTDC global error interrupt + LCD_TFT_1: InterruptVector = unhandled, + /// DMA2D global interrupt + DMA2D: InterruptVector = unhandled, +}; + +pub const registers = struct { + + /// Random number generator + pub const RNG = struct { + pub const base_address = 0x50060800; + + /// address: 0x50060800 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Random number generator + /// enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x0); + + /// address: 0x50060804 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved0: u1, + reserved1: u1, + /// Clock error interrupt + /// status + CEIS: u1, + /// Seed error interrupt + /// status + SEIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x50060808 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Random data + RNDATA: u32, + }), base_address + 0x8); + }; + + /// Hash processor + pub const HASH = struct { + pub const base_address = 0x50060400; + + /// address: 0x50060400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Initialize message digest + /// calculation + INIT: u1, + /// DMA enable + DMAE: u1, + /// Data type selection + DATATYPE: u2, + /// Mode selection + MODE: u1, + /// Algorithm selection + ALGO0: u1, + /// Number of words already + /// pushed + NBW: u4, + /// DIN not empty + DINNE: u1, + /// Multiple DMA Transfers + MDMAT: u1, + reserved2: u1, + reserved3: u1, + /// Long key selection + LKEY: u1, + reserved4: u1, + /// ALGO + ALGO1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x50060404 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x4); + + /// address: 0x50060408 + /// start register + pub const STR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of valid bits in the last word of + /// the message + NBLW: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Digest calculation + DCAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5006040c + /// digest registers + pub const HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0xc); + + /// address: 0x50060410 + /// digest registers + pub const HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x10); + + /// address: 0x50060414 + /// digest registers + pub const HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x14); + + /// address: 0x50060418 + /// digest registers + pub const HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x18); + + /// address: 0x5006041c + /// digest registers + pub const HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x1c); + + /// address: 0x50060420 + /// interrupt enable register + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// enable + DINIE: u1, + /// Digest calculation completion interrupt + /// enable + DCIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x20); + + /// address: 0x50060424 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input interrupt + /// status + DINIS: u1, + /// Digest calculation completion interrupt + /// status + DCIS: u1, + /// DMA Status + DMAS: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x24); + + /// address: 0x500604f8 + /// context swap registers + pub const CSR0 = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x500604fc + /// context swap registers + pub const CSR1 = @intToPtr(*volatile u32, base_address + 0xfc); + + /// address: 0x50060500 + /// context swap registers + pub const CSR2 = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x50060504 + /// context swap registers + pub const CSR3 = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x50060508 + /// context swap registers + pub const CSR4 = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x5006050c + /// context swap registers + pub const CSR5 = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0x50060510 + /// context swap registers + pub const CSR6 = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x50060514 + /// context swap registers + pub const CSR7 = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x50060518 + /// context swap registers + pub const CSR8 = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x5006051c + /// context swap registers + pub const CSR9 = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x50060520 + /// context swap registers + pub const CSR10 = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x50060524 + /// context swap registers + pub const CSR11 = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x50060528 + /// context swap registers + pub const CSR12 = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x5006052c + /// context swap registers + pub const CSR13 = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x50060530 + /// context swap registers + pub const CSR14 = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x50060534 + /// context swap registers + pub const CSR15 = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x50060538 + /// context swap registers + pub const CSR16 = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x5006053c + /// context swap registers + pub const CSR17 = @intToPtr(*volatile u32, base_address + 0x13c); + + /// address: 0x50060540 + /// context swap registers + pub const CSR18 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0x50060544 + /// context swap registers + pub const CSR19 = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x50060548 + /// context swap registers + pub const CSR20 = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x5006054c + /// context swap registers + pub const CSR21 = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0x50060550 + /// context swap registers + pub const CSR22 = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x50060554 + /// context swap registers + pub const CSR23 = @intToPtr(*volatile u32, base_address + 0x154); + + /// address: 0x50060558 + /// context swap registers + pub const CSR24 = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x5006055c + /// context swap registers + pub const CSR25 = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x50060560 + /// context swap registers + pub const CSR26 = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x50060564 + /// context swap registers + pub const CSR27 = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x50060568 + /// context swap registers + pub const CSR28 = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x5006056c + /// context swap registers + pub const CSR29 = @intToPtr(*volatile u32, base_address + 0x16c); + + /// address: 0x50060570 + /// context swap registers + pub const CSR30 = @intToPtr(*volatile u32, base_address + 0x170); + + /// address: 0x50060574 + /// context swap registers + pub const CSR31 = @intToPtr(*volatile u32, base_address + 0x174); + + /// address: 0x50060578 + /// context swap registers + pub const CSR32 = @intToPtr(*volatile u32, base_address + 0x178); + + /// address: 0x5006057c + /// context swap registers + pub const CSR33 = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x50060580 + /// context swap registers + pub const CSR34 = @intToPtr(*volatile u32, base_address + 0x180); + + /// address: 0x50060584 + /// context swap registers + pub const CSR35 = @intToPtr(*volatile u32, base_address + 0x184); + + /// address: 0x50060588 + /// context swap registers + pub const CSR36 = @intToPtr(*volatile u32, base_address + 0x188); + + /// address: 0x5006058c + /// context swap registers + pub const CSR37 = @intToPtr(*volatile u32, base_address + 0x18c); + + /// address: 0x50060590 + /// context swap registers + pub const CSR38 = @intToPtr(*volatile u32, base_address + 0x190); + + /// address: 0x50060594 + /// context swap registers + pub const CSR39 = @intToPtr(*volatile u32, base_address + 0x194); + + /// address: 0x50060598 + /// context swap registers + pub const CSR40 = @intToPtr(*volatile u32, base_address + 0x198); + + /// address: 0x5006059c + /// context swap registers + pub const CSR41 = @intToPtr(*volatile u32, base_address + 0x19c); + + /// address: 0x500605a0 + /// context swap registers + pub const CSR42 = @intToPtr(*volatile u32, base_address + 0x1a0); + + /// address: 0x500605a4 + /// context swap registers + pub const CSR43 = @intToPtr(*volatile u32, base_address + 0x1a4); + + /// address: 0x500605a8 + /// context swap registers + pub const CSR44 = @intToPtr(*volatile u32, base_address + 0x1a8); + + /// address: 0x500605ac + /// context swap registers + pub const CSR45 = @intToPtr(*volatile u32, base_address + 0x1ac); + + /// address: 0x500605b0 + /// context swap registers + pub const CSR46 = @intToPtr(*volatile u32, base_address + 0x1b0); + + /// address: 0x500605b4 + /// context swap registers + pub const CSR47 = @intToPtr(*volatile u32, base_address + 0x1b4); + + /// address: 0x500605b8 + /// context swap registers + pub const CSR48 = @intToPtr(*volatile u32, base_address + 0x1b8); + + /// address: 0x500605bc + /// context swap registers + pub const CSR49 = @intToPtr(*volatile u32, base_address + 0x1bc); + + /// address: 0x500605c0 + /// context swap registers + pub const CSR50 = @intToPtr(*volatile u32, base_address + 0x1c0); + + /// address: 0x500605c4 + /// context swap registers + pub const CSR51 = @intToPtr(*volatile u32, base_address + 0x1c4); + + /// address: 0x500605c8 + /// context swap registers + pub const CSR52 = @intToPtr(*volatile u32, base_address + 0x1c8); + + /// address: 0x500605cc + /// context swap registers + pub const CSR53 = @intToPtr(*volatile u32, base_address + 0x1cc); + + /// address: 0x50060710 + /// HASH digest register + pub const HASH_HR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// H0 + H0: u32, + }), base_address + 0x310); + + /// address: 0x50060714 + /// read-only + pub const HASH_HR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// H1 + H1: u32, + }), base_address + 0x314); + + /// address: 0x50060718 + /// read-only + pub const HASH_HR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// H2 + H2: u32, + }), base_address + 0x318); + + /// address: 0x5006071c + /// read-only + pub const HASH_HR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// H3 + H3: u32, + }), base_address + 0x31c); + + /// address: 0x50060720 + /// read-only + pub const HASH_HR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// H4 + H4: u32, + }), base_address + 0x320); + + /// address: 0x50060724 + /// read-only + pub const HASH_HR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// H5 + H5: u32, + }), base_address + 0x324); + + /// address: 0x50060728 + /// read-only + pub const HASH_HR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// H6 + H6: u32, + }), base_address + 0x328); + + /// address: 0x5006072c + /// read-only + pub const HASH_HR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// H7 + H7: u32, + }), base_address + 0x32c); + }; + + /// Cryptographic processor + pub const CRYP = struct { + pub const base_address = 0x50060000; + + /// address: 0x50060000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Algorithm direction + ALGODIR: u1, + /// Algorithm mode + ALGOMODE0: u3, + /// Data type selection + DATATYPE: u2, + /// Key size selection (AES mode + /// only) + KEYSIZE: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// FIFO flush + FFLUSH: u1, + /// Cryptographic processor + /// enable + CRYPEN: u1, + /// GCM_CCMPH + GCM_CCMPH: u2, + reserved6: u1, + /// ALGOMODE + ALGOMODE3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50060004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO empty + IFEM: u1, + /// Input FIFO not full + IFNF: u1, + /// Output FIFO not empty + OFNE: u1, + /// Output FIFO full + OFFU: u1, + /// Busy bit + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x4); + + /// address: 0x50060008 + /// data input register + pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data input + DATAIN: u32, + }), base_address + 0x8); + + /// address: 0x5006000c + /// data output register + pub const DOUT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data output + DATAOUT: u32, + }), base_address + 0xc); + + /// address: 0x50060010 + /// DMA control register + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA input enable + DIEN: u1, + /// DMA output enable + DOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x10); + + /// address: 0x50060014 + /// interrupt mask set/clear + /// register + pub const IMSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service interrupt + /// mask + INIM: u1, + /// Output FIFO service interrupt + /// mask + OUTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x50060018 + /// raw interrupt status register + pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service raw interrupt + /// status + INRIS: u1, + /// Output FIFO service raw interrupt + /// status + OUTRIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x18); + + /// address: 0x5006001c + /// masked interrupt status + /// register + pub const MISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input FIFO service masked interrupt + /// status + INMIS: u1, + /// Output FIFO service masked interrupt + /// status + OUTMIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x1c); + + /// address: 0x50060020 + /// key registers + pub const K0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b224 + b224: u1, + /// b225 + b225: u1, + /// b226 + b226: u1, + /// b227 + b227: u1, + /// b228 + b228: u1, + /// b229 + b229: u1, + /// b230 + b230: u1, + /// b231 + b231: u1, + /// b232 + b232: u1, + /// b233 + b233: u1, + /// b234 + b234: u1, + /// b235 + b235: u1, + /// b236 + b236: u1, + /// b237 + b237: u1, + /// b238 + b238: u1, + /// b239 + b239: u1, + /// b240 + b240: u1, + /// b241 + b241: u1, + /// b242 + b242: u1, + /// b243 + b243: u1, + /// b244 + b244: u1, + /// b245 + b245: u1, + /// b246 + b246: u1, + /// b247 + b247: u1, + /// b248 + b248: u1, + /// b249 + b249: u1, + /// b250 + b250: u1, + /// b251 + b251: u1, + /// b252 + b252: u1, + /// b253 + b253: u1, + /// b254 + b254: u1, + /// b255 + b255: u1, + }), base_address + 0x20); + + /// address: 0x50060024 + /// key registers + pub const K0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b192 + b192: u1, + /// b193 + b193: u1, + /// b194 + b194: u1, + /// b195 + b195: u1, + /// b196 + b196: u1, + /// b197 + b197: u1, + /// b198 + b198: u1, + /// b199 + b199: u1, + /// b200 + b200: u1, + /// b201 + b201: u1, + /// b202 + b202: u1, + /// b203 + b203: u1, + /// b204 + b204: u1, + /// b205 + b205: u1, + /// b206 + b206: u1, + /// b207 + b207: u1, + /// b208 + b208: u1, + /// b209 + b209: u1, + /// b210 + b210: u1, + /// b211 + b211: u1, + /// b212 + b212: u1, + /// b213 + b213: u1, + /// b214 + b214: u1, + /// b215 + b215: u1, + /// b216 + b216: u1, + /// b217 + b217: u1, + /// b218 + b218: u1, + /// b219 + b219: u1, + /// b220 + b220: u1, + /// b221 + b221: u1, + /// b222 + b222: u1, + /// b223 + b223: u1, + }), base_address + 0x24); + + /// address: 0x50060028 + /// key registers + pub const K1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b160 + b160: u1, + /// b161 + b161: u1, + /// b162 + b162: u1, + /// b163 + b163: u1, + /// b164 + b164: u1, + /// b165 + b165: u1, + /// b166 + b166: u1, + /// b167 + b167: u1, + /// b168 + b168: u1, + /// b169 + b169: u1, + /// b170 + b170: u1, + /// b171 + b171: u1, + /// b172 + b172: u1, + /// b173 + b173: u1, + /// b174 + b174: u1, + /// b175 + b175: u1, + /// b176 + b176: u1, + /// b177 + b177: u1, + /// b178 + b178: u1, + /// b179 + b179: u1, + /// b180 + b180: u1, + /// b181 + b181: u1, + /// b182 + b182: u1, + /// b183 + b183: u1, + /// b184 + b184: u1, + /// b185 + b185: u1, + /// b186 + b186: u1, + /// b187 + b187: u1, + /// b188 + b188: u1, + /// b189 + b189: u1, + /// b190 + b190: u1, + /// b191 + b191: u1, + }), base_address + 0x28); + + /// address: 0x5006002c + /// key registers + pub const K1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b128 + b128: u1, + /// b129 + b129: u1, + /// b130 + b130: u1, + /// b131 + b131: u1, + /// b132 + b132: u1, + /// b133 + b133: u1, + /// b134 + b134: u1, + /// b135 + b135: u1, + /// b136 + b136: u1, + /// b137 + b137: u1, + /// b138 + b138: u1, + /// b139 + b139: u1, + /// b140 + b140: u1, + /// b141 + b141: u1, + /// b142 + b142: u1, + /// b143 + b143: u1, + /// b144 + b144: u1, + /// b145 + b145: u1, + /// b146 + b146: u1, + /// b147 + b147: u1, + /// b148 + b148: u1, + /// b149 + b149: u1, + /// b150 + b150: u1, + /// b151 + b151: u1, + /// b152 + b152: u1, + /// b153 + b153: u1, + /// b154 + b154: u1, + /// b155 + b155: u1, + /// b156 + b156: u1, + /// b157 + b157: u1, + /// b158 + b158: u1, + /// b159 + b159: u1, + }), base_address + 0x2c); + + /// address: 0x50060030 + /// key registers + pub const K2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b96 + b96: u1, + /// b97 + b97: u1, + /// b98 + b98: u1, + /// b99 + b99: u1, + /// b100 + b100: u1, + /// b101 + b101: u1, + /// b102 + b102: u1, + /// b103 + b103: u1, + /// b104 + b104: u1, + /// b105 + b105: u1, + /// b106 + b106: u1, + /// b107 + b107: u1, + /// b108 + b108: u1, + /// b109 + b109: u1, + /// b110 + b110: u1, + /// b111 + b111: u1, + /// b112 + b112: u1, + /// b113 + b113: u1, + /// b114 + b114: u1, + /// b115 + b115: u1, + /// b116 + b116: u1, + /// b117 + b117: u1, + /// b118 + b118: u1, + /// b119 + b119: u1, + /// b120 + b120: u1, + /// b121 + b121: u1, + /// b122 + b122: u1, + /// b123 + b123: u1, + /// b124 + b124: u1, + /// b125 + b125: u1, + /// b126 + b126: u1, + /// b127 + b127: u1, + }), base_address + 0x30); + + /// address: 0x50060034 + /// key registers + pub const K2RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b64 + b64: u1, + /// b65 + b65: u1, + /// b66 + b66: u1, + /// b67 + b67: u1, + /// b68 + b68: u1, + /// b69 + b69: u1, + /// b70 + b70: u1, + /// b71 + b71: u1, + /// b72 + b72: u1, + /// b73 + b73: u1, + /// b74 + b74: u1, + /// b75 + b75: u1, + /// b76 + b76: u1, + /// b77 + b77: u1, + /// b78 + b78: u1, + /// b79 + b79: u1, + /// b80 + b80: u1, + /// b81 + b81: u1, + /// b82 + b82: u1, + /// b83 + b83: u1, + /// b84 + b84: u1, + /// b85 + b85: u1, + /// b86 + b86: u1, + /// b87 + b87: u1, + /// b88 + b88: u1, + /// b89 + b89: u1, + /// b90 + b90: u1, + /// b91 + b91: u1, + /// b92 + b92: u1, + /// b93 + b93: u1, + /// b94 + b94: u1, + /// b95 + b95: u1, + }), base_address + 0x34); + + /// address: 0x50060038 + /// key registers + pub const K3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// b32 + b32: u1, + /// b33 + b33: u1, + /// b34 + b34: u1, + /// b35 + b35: u1, + /// b36 + b36: u1, + /// b37 + b37: u1, + /// b38 + b38: u1, + /// b39 + b39: u1, + /// b40 + b40: u1, + /// b41 + b41: u1, + /// b42 + b42: u1, + /// b43 + b43: u1, + /// b44 + b44: u1, + /// b45 + b45: u1, + /// b46 + b46: u1, + /// b47 + b47: u1, + /// b48 + b48: u1, + /// b49 + b49: u1, + /// b50 + b50: u1, + /// b51 + b51: u1, + /// b52 + b52: u1, + /// b53 + b53: u1, + /// b54 + b54: u1, + /// b55 + b55: u1, + /// b56 + b56: u1, + /// b57 + b57: u1, + /// b58 + b58: u1, + /// b59 + b59: u1, + /// b60 + b60: u1, + /// b61 + b61: u1, + /// b62 + b62: u1, + /// b63 + b63: u1, + }), base_address + 0x38); + + /// address: 0x5006003c + /// key registers + pub const K3RR = @intToPtr(*volatile Mmio(32, packed struct { + /// b0 + b0: u1, + /// b1 + b1: u1, + /// b2 + b2: u1, + /// b3 + b3: u1, + /// b4 + b4: u1, + /// b5 + b5: u1, + /// b6 + b6: u1, + /// b7 + b7: u1, + /// b8 + b8: u1, + /// b9 + b9: u1, + /// b10 + b10: u1, + /// b11 + b11: u1, + /// b12 + b12: u1, + /// b13 + b13: u1, + /// b14 + b14: u1, + /// b15 + b15: u1, + /// b16 + b16: u1, + /// b17 + b17: u1, + /// b18 + b18: u1, + /// b19 + b19: u1, + /// b20 + b20: u1, + /// b21 + b21: u1, + /// b22 + b22: u1, + /// b23 + b23: u1, + /// b24 + b24: u1, + /// b25 + b25: u1, + /// b26 + b26: u1, + /// b27 + b27: u1, + /// b28 + b28: u1, + /// b29 + b29: u1, + /// b30 + b30: u1, + /// b31 + b31: u1, + }), base_address + 0x3c); + + /// address: 0x50060040 + /// initialization vector + /// registers + pub const IV0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV31 + IV31: u1, + /// IV30 + IV30: u1, + /// IV29 + IV29: u1, + /// IV28 + IV28: u1, + /// IV27 + IV27: u1, + /// IV26 + IV26: u1, + /// IV25 + IV25: u1, + /// IV24 + IV24: u1, + /// IV23 + IV23: u1, + /// IV22 + IV22: u1, + /// IV21 + IV21: u1, + /// IV20 + IV20: u1, + /// IV19 + IV19: u1, + /// IV18 + IV18: u1, + /// IV17 + IV17: u1, + /// IV16 + IV16: u1, + /// IV15 + IV15: u1, + /// IV14 + IV14: u1, + /// IV13 + IV13: u1, + /// IV12 + IV12: u1, + /// IV11 + IV11: u1, + /// IV10 + IV10: u1, + /// IV9 + IV9: u1, + /// IV8 + IV8: u1, + /// IV7 + IV7: u1, + /// IV6 + IV6: u1, + /// IV5 + IV5: u1, + /// IV4 + IV4: u1, + /// IV3 + IV3: u1, + /// IV2 + IV2: u1, + /// IV1 + IV1: u1, + /// IV0 + IV0: u1, + }), base_address + 0x40); + + /// address: 0x50060044 + /// initialization vector + /// registers + pub const IV0RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV63 + IV63: u1, + /// IV62 + IV62: u1, + /// IV61 + IV61: u1, + /// IV60 + IV60: u1, + /// IV59 + IV59: u1, + /// IV58 + IV58: u1, + /// IV57 + IV57: u1, + /// IV56 + IV56: u1, + /// IV55 + IV55: u1, + /// IV54 + IV54: u1, + /// IV53 + IV53: u1, + /// IV52 + IV52: u1, + /// IV51 + IV51: u1, + /// IV50 + IV50: u1, + /// IV49 + IV49: u1, + /// IV48 + IV48: u1, + /// IV47 + IV47: u1, + /// IV46 + IV46: u1, + /// IV45 + IV45: u1, + /// IV44 + IV44: u1, + /// IV43 + IV43: u1, + /// IV42 + IV42: u1, + /// IV41 + IV41: u1, + /// IV40 + IV40: u1, + /// IV39 + IV39: u1, + /// IV38 + IV38: u1, + /// IV37 + IV37: u1, + /// IV36 + IV36: u1, + /// IV35 + IV35: u1, + /// IV34 + IV34: u1, + /// IV33 + IV33: u1, + /// IV32 + IV32: u1, + }), base_address + 0x44); + + /// address: 0x50060048 + /// initialization vector + /// registers + pub const IV1LR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV95 + IV95: u1, + /// IV94 + IV94: u1, + /// IV93 + IV93: u1, + /// IV92 + IV92: u1, + /// IV91 + IV91: u1, + /// IV90 + IV90: u1, + /// IV89 + IV89: u1, + /// IV88 + IV88: u1, + /// IV87 + IV87: u1, + /// IV86 + IV86: u1, + /// IV85 + IV85: u1, + /// IV84 + IV84: u1, + /// IV83 + IV83: u1, + /// IV82 + IV82: u1, + /// IV81 + IV81: u1, + /// IV80 + IV80: u1, + /// IV79 + IV79: u1, + /// IV78 + IV78: u1, + /// IV77 + IV77: u1, + /// IV76 + IV76: u1, + /// IV75 + IV75: u1, + /// IV74 + IV74: u1, + /// IV73 + IV73: u1, + /// IV72 + IV72: u1, + /// IV71 + IV71: u1, + /// IV70 + IV70: u1, + /// IV69 + IV69: u1, + /// IV68 + IV68: u1, + /// IV67 + IV67: u1, + /// IV66 + IV66: u1, + /// IV65 + IV65: u1, + /// IV64 + IV64: u1, + }), base_address + 0x48); + + /// address: 0x5006004c + /// initialization vector + /// registers + pub const IV1RR = @intToPtr(*volatile Mmio(32, packed struct { + /// IV127 + IV127: u1, + /// IV126 + IV126: u1, + /// IV125 + IV125: u1, + /// IV124 + IV124: u1, + /// IV123 + IV123: u1, + /// IV122 + IV122: u1, + /// IV121 + IV121: u1, + /// IV120 + IV120: u1, + /// IV119 + IV119: u1, + /// IV118 + IV118: u1, + /// IV117 + IV117: u1, + /// IV116 + IV116: u1, + /// IV115 + IV115: u1, + /// IV114 + IV114: u1, + /// IV113 + IV113: u1, + /// IV112 + IV112: u1, + /// IV111 + IV111: u1, + /// IV110 + IV110: u1, + /// IV109 + IV109: u1, + /// IV108 + IV108: u1, + /// IV107 + IV107: u1, + /// IV106 + IV106: u1, + /// IV105 + IV105: u1, + /// IV104 + IV104: u1, + /// IV103 + IV103: u1, + /// IV102 + IV102: u1, + /// IV101 + IV101: u1, + /// IV100 + IV100: u1, + /// IV99 + IV99: u1, + /// IV98 + IV98: u1, + /// IV97 + IV97: u1, + /// IV96 + IV96: u1, + }), base_address + 0x4c); + + /// address: 0x50060050 + /// context swap register + pub const CSGCMCCM0R = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0x50060054 + /// context swap register + pub const CSGCMCCM1R = @intToPtr(*volatile u32, base_address + 0x54); + + /// address: 0x50060058 + /// context swap register + pub const CSGCMCCM2R = @intToPtr(*volatile u32, base_address + 0x58); + + /// address: 0x5006005c + /// context swap register + pub const CSGCMCCM3R = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0x50060060 + /// context swap register + pub const CSGCMCCM4R = @intToPtr(*volatile u32, base_address + 0x60); + + /// address: 0x50060064 + /// context swap register + pub const CSGCMCCM5R = @intToPtr(*volatile u32, base_address + 0x64); + + /// address: 0x50060068 + /// context swap register + pub const CSGCMCCM6R = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0x5006006c + /// context swap register + pub const CSGCMCCM7R = @intToPtr(*volatile u32, base_address + 0x6c); + + /// address: 0x50060070 + /// context swap register + pub const CSGCM0R = @intToPtr(*volatile u32, base_address + 0x70); + + /// address: 0x50060074 + /// context swap register + pub const CSGCM1R = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0x50060078 + /// context swap register + pub const CSGCM2R = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x5006007c + /// context swap register + pub const CSGCM3R = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x50060080 + /// context swap register + pub const CSGCM4R = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x50060084 + /// context swap register + pub const CSGCM5R = @intToPtr(*volatile u32, base_address + 0x84); + + /// address: 0x50060088 + /// context swap register + pub const CSGCM6R = @intToPtr(*volatile u32, base_address + 0x88); + + /// address: 0x5006008c + /// context swap register + pub const CSGCM7R = @intToPtr(*volatile u32, base_address + 0x8c); + }; + + /// Digital camera interface + pub const DCMI = struct { + pub const base_address = 0x50050000; + + /// address: 0x50050000 + /// control register 1 + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization + /// select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization + /// polarity + HSPOL: u1, + /// Vertical synchronization + /// polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved0: u1, + reserved1: u1, + /// DCMI enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x0); + + /// address: 0x50050004 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0x50050008 + /// raw interrupt status register + pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete raw interrupt + /// status + FRAME_RIS: u1, + /// Overrun raw interrupt + /// status + OVR_RIS: u1, + /// Synchronization error raw interrupt + /// status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x8); + + /// address: 0x5005000c + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt + /// enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt + /// enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xc); + + /// address: 0x50050010 + /// masked interrupt status + /// register + pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete masked interrupt + /// status + FRAME_MIS: u1, + /// Overrun masked interrupt + /// status + OVR_MIS: u1, + /// Synchronization error masked interrupt + /// status + ERR_MIS: u1, + /// VSYNC masked interrupt + /// status + VSYNC_MIS: u1, + /// Line masked interrupt + /// status + LINE_MIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0x50050014 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture complete interrupt status + /// clear + FRAME_ISC: u1, + /// Overrun interrupt status + /// clear + OVR_ISC: u1, + /// Synchronization error interrupt status + /// clear + ERR_ISC: u1, + /// Vertical synch interrupt status + /// clear + VSYNC_ISC: u1, + /// line interrupt status + /// clear + LINE_ISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50050018 + /// embedded synchronization code + /// register + pub const ESCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), base_address + 0x18); + + /// address: 0x5005001c + /// embedded synchronization unmask + /// register + pub const ESUR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame start delimiter + /// unmask + FSU: u8, + /// Line start delimiter + /// unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), base_address + 0x1c); + + /// address: 0x50050020 + /// crop window start + pub const CWSTRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Horizontal offset count + HOFFCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical start line count + VST: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x50050024 + /// crop window size + pub const CWSIZE = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture count + CAPCNT: u14, + reserved0: u1, + reserved1: u1, + /// Vertical line count + VLINE: u14, + padding0: u1, + padding1: u1, + }), base_address + 0x24); + + /// address: 0x50050028 + /// data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), base_address + 0x28); + }; + + /// Flexible memory controller + pub const FMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR-Flash chip-select control register + /// 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved1: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR-Flash chip-select timing register + /// 1 + pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR-Flash chip-select control register + /// 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x8); + + /// address: 0xa000000c + /// SRAM/NOR-Flash chip-select timing register + /// 2 + pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0xa0000010 + /// SRAM/NOR-Flash chip-select control register + /// 3 + pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0xa0000014 + /// SRAM/NOR-Flash chip-select timing register + /// 3 + pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0xa0000018 + /// SRAM/NOR-Flash chip-select control register + /// 4 + pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved0: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CBURSTRW + CBURSTRW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0xa000001c + /// SRAM/NOR-Flash chip-select timing register + /// 4 + pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0xa0000060 + /// PC Card/NAND Flash control register + /// 2 + pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x60); + + /// address: 0xa0000064 + /// FIFO status and interrupt register + /// 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x64); + + /// address: 0xa0000068 + /// Common memory space timing register + /// 2 + pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x68); + + /// address: 0xa000006c + /// Attribute memory space timing register + /// 2 + pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x6c); + + /// address: 0xa0000074 + /// ECC result register 2 + pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x74); + + /// address: 0xa0000080 + /// PC Card/NAND Flash control register + /// 3 + pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x80); + + /// address: 0xa0000084 + /// FIFO status and interrupt register + /// 3 + pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x84); + + /// address: 0xa0000088 + /// Common memory space timing register + /// 3 + pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0x88); + + /// address: 0xa000008c + /// Attribute memory space timing register + /// 3 + pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0x8c); + + /// address: 0xa0000094 + /// ECC result register 3 + pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ECCx + ECCx: u32, + }), base_address + 0x94); + + /// address: 0xa00000a0 + /// PC Card/NAND Flash control register + /// 4 + pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved1: u1, + reserved2: u1, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0xa0); + + /// address: 0xa00000a4 + /// FIFO status and interrupt register + /// 4 + pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xa4); + + /// address: 0xa00000a8 + /// Common memory space timing register + /// 4 + pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), base_address + 0xa8); + + /// address: 0xa00000ac + /// Attribute memory space timing register + /// 4 + pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), base_address + 0xac); + + /// address: 0xa00000b0 + /// I/O space timing register 4 + pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), base_address + 0xb0); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 1 + pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 2 + pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000104 + /// SRAM/NOR-Flash write timing registers + /// 3 + pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x104); + + /// address: 0xa000010c + /// SRAM/NOR-Flash write timing registers + /// 4 + pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10c); + + /// address: 0xa0000140 + /// SDRAM Control Register 1 + pub const SDCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of column address + /// bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x140); + + /// address: 0xa0000144 + /// SDRAM Control Register 2 + pub const SDCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of column address + /// bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x144); + + /// address: 0xa0000148 + /// SDRAM Timing register 1 + pub const SDTR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Load Mode Register to + /// Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x148); + + /// address: 0xa000014c + /// SDRAM Timing register 2 + pub const SDTR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Load Mode Register to + /// Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14c); + + /// address: 0xa0000150 + /// SDRAM Command Mode register + pub const SDCMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Command mode + MODE: u3, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x150); + + /// address: 0xa0000154 + /// SDRAM Refresh Timer register + pub const SDRTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x154); + + /// address: 0xa0000158 + /// SDRAM Status register + pub const SDSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: u2, + /// Status Mode for Bank 2 + MODES2: u2, + /// Busy status + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x158); + }; + + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// IDCODE + pub const DBGMCU_IDCODE = @intToPtr(*volatile Mmio(32, packed struct { + /// DEV_ID + DEV_ID: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// REV_ID + REV_ID: u16, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Control Register + pub const DBGMCU_CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved0: u1, + reserved1: u1, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0xe0042008 + /// Debug MCU APB1 Freeze registe + pub const DBGMCU_APB1_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3 _STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_TIM12_STOP + DBG_TIM12_STOP: u1, + /// DBG_TIM13_STOP + DBG_TIM13_STOP: u1, + /// DBG_TIM14_STOP + DBG_TIM14_STOP: u1, + reserved0: u1, + reserved1: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_IWDEG_STOP + DBG_IWDEG_STOP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT: u1, + /// DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT: u1, + /// DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT: u1, + reserved10: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8); + + /// address: 0xe004200c + /// Debug MCU APB2 Freeze registe + pub const DBGMCU_APB2_FZ = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 counter stopped when core is + /// halted + DBG_TIM1_STOP: u1, + /// TIM8 counter stopped when core is + /// halted + DBG_TIM8_STOP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TIM9 counter stopped when core is + /// halted + DBG_TIM9_STOP: u1, + /// TIM10 counter stopped when core is + /// halted + DBG_TIM10_STOP: u1, + /// TIM11 counter stopped when core is + /// halted + DBG_TIM11_STOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + }; + + /// DMA controller + pub const DMA2 = struct { + pub const base_address = 0x40026400; + + /// address: 0x40026400 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026404 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026408 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002640c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026410 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026414 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026418 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002641c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026420 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026424 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026428 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002642c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026430 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026434 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026438 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002643c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026440 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026444 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026448 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002644c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026450 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026454 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026458 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002645c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026460 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026464 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026468 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002646c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026470 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026474 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026478 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002647c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026480 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026484 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026488 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002648c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026490 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026494 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026498 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002649c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400264a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400264a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400264a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400264ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400264b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400264b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400264b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400264bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400264c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400264c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400264c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400264cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + pub const DMA1 = struct { + pub const base_address = 0x40026000; + + /// address: 0x40026000 + /// low interrupt status register + pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF0: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF1: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF2: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag + /// (x=3..0) + FEIF3: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag + /// (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag + /// (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt + /// flag (x = 3..0) + TCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40026004 + /// high interrupt status register + pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF4: u1, + reserved0: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF5: u1, + reserved1: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF6: u1, + reserved6: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag + /// (x=7..4) + FEIF7: u1, + reserved7: u1, + /// Stream x direct mode error interrupt + /// flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag + /// (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag + /// (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt + /// flag (x=7..4) + TCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40026008 + /// low interrupt flag clear + /// register + pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF0: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF1: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF2: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 3..0) + CFEIF3: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 3..0) + CTCIF3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4002600c + /// high interrupt flag clear + /// register + pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF4: u1, + reserved0: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF5: u1, + reserved1: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF5: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF6: u1, + reserved6: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag + /// (x = 7..4) + CFEIF7: u1, + reserved7: u1, + /// Stream x clear direct mode error + /// interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt + /// flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt + /// flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete + /// interrupt flag (x = 7..4) + CTCIF7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40026010 + /// stream x configuration + /// register + pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + reserved0: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40026014 + /// stream x number of data + /// register + pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40026018 + /// stream x peripheral address + /// register + pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x18); + + /// address: 0x4002601c + /// stream x memory 0 address + /// register + pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x1c); + + /// address: 0x40026020 + /// stream x memory 1 address + /// register + pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x20); + + /// address: 0x40026024 + /// stream x FIFO control register + pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40026028 + /// stream x configuration + /// register + pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x28); + + /// address: 0x4002602c + /// stream x number of data + /// register + pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x40026030 + /// stream x peripheral address + /// register + pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x30); + + /// address: 0x40026034 + /// stream x memory 0 address + /// register + pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x34); + + /// address: 0x40026038 + /// stream x memory 1 address + /// register + pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x38); + + /// address: 0x4002603c + /// stream x FIFO control register + pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x3c); + + /// address: 0x40026040 + /// stream x configuration + /// register + pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x40); + + /// address: 0x40026044 + /// stream x number of data + /// register + pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40026048 + /// stream x peripheral address + /// register + pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x48); + + /// address: 0x4002604c + /// stream x memory 0 address + /// register + pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x4c); + + /// address: 0x40026050 + /// stream x memory 1 address + /// register + pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x50); + + /// address: 0x40026054 + /// stream x FIFO control register + pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40026058 + /// stream x configuration + /// register + pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x58); + + /// address: 0x4002605c + /// stream x number of data + /// register + pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40026060 + /// stream x peripheral address + /// register + pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x60); + + /// address: 0x40026064 + /// stream x memory 0 address + /// register + pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x64); + + /// address: 0x40026068 + /// stream x memory 1 address + /// register + pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x68); + + /// address: 0x4002606c + /// stream x FIFO control register + pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x6c); + + /// address: 0x40026070 + /// stream x configuration + /// register + pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x70); + + /// address: 0x40026074 + /// stream x number of data + /// register + pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x74); + + /// address: 0x40026078 + /// stream x peripheral address + /// register + pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x78); + + /// address: 0x4002607c + /// stream x memory 0 address + /// register + pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x7c); + + /// address: 0x40026080 + /// stream x memory 1 address + /// register + pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x80); + + /// address: 0x40026084 + /// stream x FIFO control register + pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x84); + + /// address: 0x40026088 + /// stream x configuration + /// register + pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4002608c + /// stream x number of data + /// register + pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8c); + + /// address: 0x40026090 + /// stream x peripheral address + /// register + pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0x90); + + /// address: 0x40026094 + /// stream x memory 0 address + /// register + pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0x94); + + /// address: 0x40026098 + /// stream x memory 1 address + /// register + pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0x98); + + /// address: 0x4002609c + /// stream x FIFO control register + pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x9c); + + /// address: 0x400260a0 + /// stream x configuration + /// register + pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xa0); + + /// address: 0x400260a4 + /// stream x number of data + /// register + pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xa4); + + /// address: 0x400260a8 + /// stream x peripheral address + /// register + pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xa8); + + /// address: 0x400260ac + /// stream x memory 0 address + /// register + pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xac); + + /// address: 0x400260b0 + /// stream x memory 1 address + /// register + pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xb0); + + /// address: 0x400260b4 + /// stream x FIFO control register + pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xb4); + + /// address: 0x400260b8 + /// stream x configuration + /// register + pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stream enable / flag stream ready when + /// read low + EN: u1, + /// Direct mode error interrupt + /// enable + DMEIE: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Half transfer interrupt + /// enable + HTIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset + /// size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer + /// mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer + /// configuration + PBURST: u2, + /// Memory burst transfer + /// configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xb8); + + /// address: 0x400260bc + /// stream x number of data + /// register + pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data items to + /// transfer + NDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xbc); + + /// address: 0x400260c0 + /// stream x peripheral address + /// register + pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral address + PA: u32, + }), base_address + 0xc0); + + /// address: 0x400260c4 + /// stream x memory 0 address + /// register + pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 0 address + M0A: u32, + }), base_address + 0xc4); + + /// address: 0x400260c8 + /// stream x memory 1 address + /// register + pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory 1 address (used in case of Double + /// buffer mode) + M1A: u32, + }), base_address + 0xc8); + + /// address: 0x400260cc + /// stream x FIFO control register + pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved0: u1, + /// FIFO error interrupt + /// enable + FEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xcc); + }; + + /// Reset and clock control + pub const RCC = struct { + pub const base_address = 0x40023800; + + /// address: 0x40023800 + /// clock control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal high-speed clock + /// enable + HSION: u1, + /// Internal high-speed clock ready + /// flag + HSIRDY: u1, + reserved0: u1, + /// Internal high-speed clock + /// trimming + HSITRIM: u5, + /// Internal high-speed clock + /// calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system + /// enable + CSSON: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready + /// flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40023804 + /// PLL configuration register + pub const PLLCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM0: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM1: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM2: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM3: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM4: u1, + /// Division factor for the main PLL (PLL) + /// and audio PLL (PLLI2S) input clock + PLLM5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN0: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN1: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN2: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN3: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN4: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN5: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN6: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN7: u1, + /// Main PLL (PLL) multiplication factor for + /// VCO + PLLN8: u1, + reserved0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP0: u1, + /// Main PLL (PLL) division factor for main + /// system clock + PLLP1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Main PLL(PLL) and audio PLL (PLLI2S) + /// entry clock source + PLLSRC: u1, + reserved5: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ0: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ1: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ2: u1, + /// Main PLL (PLL) division factor for USB + /// OTG FS, SDIO and random number generator + /// clocks + PLLQ3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40023808 + /// clock configuration register + pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// System clock switch + SW0: u1, + /// System clock switch + SW1: u1, + /// System clock switch status + SWS0: u1, + /// System clock switch status + SWS1: u1, + /// AHB prescaler + HPRE: u4, + reserved0: u1, + reserved1: u1, + /// APB Low speed prescaler + /// (APB1) + PPRE1: u3, + /// APB high-speed prescaler + /// (APB2) + PPRE2: u3, + /// HSE division factor for RTC + /// clock + RTCPRE: u5, + /// Microcontroller clock output + /// 1 + MCO1: u2, + /// I2S clock selection + I2SSRC: u1, + /// MCO1 prescaler + MCO1PRE: u3, + /// MCO2 prescaler + MCO2PRE: u3, + /// Microcontroller clock output + /// 2 + MCO2: u2, + }), base_address + 0x8); + + /// address: 0x4002380c + /// clock interrupt register + pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt + /// flag + PLLRDYF: u1, + /// PLLI2S ready interrupt + /// flag + PLLI2SRDYF: u1, + reserved0: u1, + /// Clock security system interrupt + /// flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt + /// enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt + /// enable + PLLI2SRDYIE: u1, + reserved1: u1, + reserved2: u1, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt + /// clear + PLLRDYC: u1, + /// PLLI2S ready interrupt + /// clear + PLLI2SRDYC: u1, + reserved3: u1, + /// Clock security system interrupt + /// clear + CSSC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40023810 + /// AHB1 peripheral reset register + pub const AHB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC reset + CRCRST: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved11: u1, + reserved12: u1, + /// Ethernet MAC reset + ETHMACRST: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// USB OTG HS module reset + OTGHSRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40023814 + /// AHB2 peripheral reset register + pub const AHB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface reset + DCMIRST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptographic module reset + CRYPRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module + /// reset + RNGRST: u1, + /// USB OTG FS module reset + OTGFSRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40023818 + /// AHB3 peripheral reset register + pub const AHB3RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module + /// reset + FMCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x18); + + /// address: 0x40023820 + /// APB1 peripheral reset register + pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog reset + WWDGRST: u1, + reserved2: u1, + reserved3: u1, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved4: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved5: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved6: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40023824 + /// APB2 peripheral reset register + pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved0: u1, + reserved1: u1, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved2: u1, + reserved3: u1, + /// ADC interface reset (common to all + /// ADCs) + ADCRST: u1, + reserved4: u1, + reserved5: u1, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved6: u1, + /// System configuration controller + /// reset + SYSCFGRST: u1, + reserved7: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0x40023830 + /// AHB1 peripheral clock register + pub const AHB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable + CRCEN: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Backup SRAM interface clock + /// enable + BKPSRAMEN: u1, + reserved8: u1, + /// CCM data RAM clock enable + CCMDATARAMEN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved9: u1, + reserved10: u1, + /// Ethernet MAC clock enable + ETHMACEN: u1, + /// Ethernet Transmission clock + /// enable + ETHMACTXEN: u1, + /// Ethernet Reception clock + /// enable + ETHMACRXEN: u1, + /// Ethernet PTP clock enable + ETHMACPTPEN: u1, + /// USB OTG HS clock enable + OTGHSEN: u1, + /// USB OTG HSULPI clock + /// enable + OTGHSULPIEN: u1, + padding0: u1, + }), base_address + 0x30); + + /// address: 0x40023834 + /// AHB2 peripheral clock enable + /// register + pub const AHB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable + DCMIEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptographic modules clock + /// enable + CRYPEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock + /// enable + RNGEN: u1, + /// USB OTG FS clock enable + OTGFSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x34); + + /// address: 0x40023838 + /// AHB3 peripheral clock enable + /// register + pub const AHB3ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module clock + /// enable + FMCEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x38); + + /// address: 0x40023840 + /// APB1 peripheral clock enable + /// register + pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock + /// enable + WWDGEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved4: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved5: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved6: u1, + /// Power interface clock + /// enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x40); + + /// address: 0x40023844 + /// APB2 peripheral clock enable + /// register + pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable + SYSCFGEN: u1, + reserved5: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x44); + + /// address: 0x40023850 + /// AHB1 peripheral clock enable in low power + /// mode register + pub const AHB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// IO port A clock enable during sleep + /// mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep + /// mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep + /// mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep + /// mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep + /// mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep + /// mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep + /// mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep + /// mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep + /// mode + GPIOILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// CRC clock enable during Sleep + /// mode + CRCLPEN: u1, + reserved3: u1, + reserved4: u1, + /// Flash interface clock enable during + /// Sleep mode + FLITFLPEN: u1, + /// SRAM 1interface clock enable during + /// Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during + /// Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable + /// during Sleep mode + BKPSRAMLPEN: u1, + reserved5: u1, + reserved6: u1, + /// DMA1 clock enable during Sleep + /// mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep + /// mode + DMA2LPEN: u1, + reserved7: u1, + reserved8: u1, + /// Ethernet MAC clock enable during Sleep + /// mode + ETHMACLPEN: u1, + /// Ethernet transmission clock enable + /// during Sleep mode + ETHMACTXLPEN: u1, + /// Ethernet reception clock enable during + /// Sleep mode + ETHMACRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep + /// mode + ETHMACPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep + /// mode + OTGHSLPEN: u1, + /// USB OTG HS ULPI clock enable during + /// Sleep mode + OTGHSULPILPEN: u1, + padding0: u1, + }), base_address + 0x50); + + /// address: 0x40023854 + /// AHB2 peripheral clock enable in low power + /// mode register + pub const AHB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Camera interface enable during Sleep + /// mode + DCMILPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Cryptography modules clock enable during + /// Sleep mode + CRYPLPEN: u1, + /// Hash modules clock enable during Sleep + /// mode + HASHLPEN: u1, + /// Random number generator clock enable + /// during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep + /// mode + OTGFSLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x54); + + /// address: 0x40023858 + /// AHB3 peripheral clock enable in low power + /// mode register + pub const AHB3LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// Flexible memory controller module clock + /// enable during Sleep mode + FMCLPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x58); + + /// address: 0x40023860 + /// APB1 peripheral clock enable in low power + /// mode register + pub const APB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM2 clock enable during Sleep + /// mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep + /// mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep + /// mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep + /// mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep + /// mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep + /// mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep + /// mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep + /// mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep + /// mode + TIM14LPEN: u1, + reserved0: u1, + reserved1: u1, + /// Window watchdog clock enable during + /// Sleep mode + WWDGLPEN: u1, + reserved2: u1, + reserved3: u1, + /// SPI2 clock enable during Sleep + /// mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep + /// mode + SPI3LPEN: u1, + reserved4: u1, + /// USART2 clock enable during Sleep + /// mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep + /// mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep + /// mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep + /// mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep + /// mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep + /// mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep + /// mode + I2C3LPEN: u1, + reserved5: u1, + /// CAN 1 clock enable during Sleep + /// mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep + /// mode + CAN2LPEN: u1, + reserved6: u1, + /// Power interface clock enable during + /// Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep + /// mode + DACLPEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x60); + + /// address: 0x40023864 + /// APB2 peripheral clock enabled in low power + /// mode register + pub const APB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { + /// TIM1 clock enable during Sleep + /// mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep + /// mode + TIM8LPEN: u1, + reserved0: u1, + reserved1: u1, + /// USART1 clock enable during Sleep + /// mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep + /// mode + USART6LPEN: u1, + reserved2: u1, + reserved3: u1, + /// ADC1 clock enable during Sleep + /// mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep + /// mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep + /// mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep + /// mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep + /// mode + SPI1LPEN: u1, + reserved4: u1, + /// System configuration controller clock + /// enable during Sleep mode + SYSCFGLPEN: u1, + reserved5: u1, + /// TIM9 clock enable during sleep + /// mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep + /// mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep + /// mode + TIM11LPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x64); + + /// address: 0x40023870 + /// Backup domain control register + pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// External low-speed oscillator + /// enable + LSEON: u1, + /// External low-speed oscillator + /// ready + LSERDY: u1, + /// External low-speed oscillator + /// bypass + LSEBYP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock source selection + RTCSEL0: u1, + /// RTC clock source selection + RTCSEL1: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software + /// reset + BDRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x70); + + /// address: 0x40023874 + /// clock control & status + /// register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal low-speed oscillator + /// enable + LSION: u1, + /// Internal low-speed oscillator + /// ready + LSIRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset + /// flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), base_address + 0x74); + + /// address: 0x40023880 + /// spread spectrum clock generation + /// register + pub const SSCGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved0: u1, + reserved1: u1, + /// Spread Select + SPREADSEL: u1, + /// Spread spectrum modulation + /// enable + SSCGEN: u1, + }), base_address + 0x80); + + /// address: 0x40023884 + /// PLLI2S configuration register + pub const PLLI2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// PLLI2S multiplication factor for + /// VCO + PLLI2SN: u9, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// PLLI2S division factor for SAI1 + /// clock + PLLI2SQ: u4, + /// PLLI2S division factor for I2S + /// clocks + PLLI2SR: u3, + padding0: u1, + }), base_address + 0x84); + + /// address: 0x4002388c + /// RCC Dedicated Clock Configuration + /// Register + pub const DCKCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// PLLI2S division factor for SAI1 + /// clock + PLLI2SDIVQ: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PLLSAI division factor for SAI1 + /// clock + PLLSAIDIVQ: u5, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// division factor for + /// LCD_CLK + PLLSAIDIVR: u2, + reserved6: u1, + reserved7: u1, + /// SAI1-A clock source + /// selection + SAI1ASRC: u2, + /// SAI1-B clock source + /// selection + SAI1BSRC: u2, + /// Timers clocks prescalers + /// selection + TIMPRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8c); + + /// address: 0x40023888 + /// RCC PLL configuration register + pub const PLLSAICFGR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// PLLSAI division factor for + /// VCO + PLLSAIN: u9, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// PLLSAI division factor for SAI1 + /// clock + PLLSAIQ: u4, + /// PLLSAI division factor for LCD + /// clock + PLLSAIR: u3, + padding0: u1, + }), base_address + 0x88); + }; + + /// General-purpose I/Os + pub const GPIOK = struct { + pub const base_address = 0x40022800; + + /// address: 0x40022800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002280c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002281c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOJ = struct { + pub const base_address = 0x40022400; + + /// address: 0x40022400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002240c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002241c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOI = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40022004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40022008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002200c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40022010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40022018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002201c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40022024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOH = struct { + pub const base_address = 0x40021c00; + + /// address: 0x40021c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40021c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40021c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOG = struct { + pub const base_address = 0x40021800; + + /// address: 0x40021800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002180c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002181c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOF = struct { + pub const base_address = 0x40021400; + + /// address: 0x40021400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002140c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002141c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOE = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40021004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002100c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40021010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40021024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOD = struct { + pub const base_address = 0x40020c00; + + /// address: 0x40020c00 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020c04 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020c08 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x40020c0c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020c10 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020c14 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020c18 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x40020c1c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020c20 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020c24 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + pub const GPIOC = struct { + pub const base_address = 0x40020800; + + /// address: 0x40020800 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020804 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020808 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002080c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020810 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020814 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020818 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002081c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020820 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020824 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOB = struct { + pub const base_address = 0x40020400; + + /// address: 0x40020400 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020404 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020408 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002040c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020410 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020414 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020418 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002041c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020420 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020424 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// GPIO port mode register + pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + MODER0: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER1: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER2: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER3: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER4: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER5: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER6: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER7: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER8: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER9: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER10: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER11: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER12: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER13: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER14: u2, + /// Port x configuration bits (y = + /// 0..15) + MODER15: u2, + }), base_address + 0x0); + + /// address: 0x40020004 + /// GPIO port output type register + pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OT0: u1, + /// Port x configuration bits (y = + /// 0..15) + OT1: u1, + /// Port x configuration bits (y = + /// 0..15) + OT2: u1, + /// Port x configuration bits (y = + /// 0..15) + OT3: u1, + /// Port x configuration bits (y = + /// 0..15) + OT4: u1, + /// Port x configuration bits (y = + /// 0..15) + OT5: u1, + /// Port x configuration bits (y = + /// 0..15) + OT6: u1, + /// Port x configuration bits (y = + /// 0..15) + OT7: u1, + /// Port x configuration bits (y = + /// 0..15) + OT8: u1, + /// Port x configuration bits (y = + /// 0..15) + OT9: u1, + /// Port x configuration bits (y = + /// 0..15) + OT10: u1, + /// Port x configuration bits (y = + /// 0..15) + OT11: u1, + /// Port x configuration bits (y = + /// 0..15) + OT12: u1, + /// Port x configuration bits (y = + /// 0..15) + OT13: u1, + /// Port x configuration bits (y = + /// 0..15) + OT14: u1, + /// Port x configuration bits (y = + /// 0..15) + OT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// GPIO port output speed + /// register + pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + OSPEEDR15: u2, + }), base_address + 0x8); + + /// address: 0x4002000c + /// GPIO port pull-up/pull-down + /// register + pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x configuration bits (y = + /// 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = + /// 0..15) + PUPDR15: u2, + }), base_address + 0xc); + + /// address: 0x40020010 + /// GPIO port input data register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input data (y = + /// 0..15) + IDR0: u1, + /// Port input data (y = + /// 0..15) + IDR1: u1, + /// Port input data (y = + /// 0..15) + IDR2: u1, + /// Port input data (y = + /// 0..15) + IDR3: u1, + /// Port input data (y = + /// 0..15) + IDR4: u1, + /// Port input data (y = + /// 0..15) + IDR5: u1, + /// Port input data (y = + /// 0..15) + IDR6: u1, + /// Port input data (y = + /// 0..15) + IDR7: u1, + /// Port input data (y = + /// 0..15) + IDR8: u1, + /// Port input data (y = + /// 0..15) + IDR9: u1, + /// Port input data (y = + /// 0..15) + IDR10: u1, + /// Port input data (y = + /// 0..15) + IDR11: u1, + /// Port input data (y = + /// 0..15) + IDR12: u1, + /// Port input data (y = + /// 0..15) + IDR13: u1, + /// Port input data (y = + /// 0..15) + IDR14: u1, + /// Port input data (y = + /// 0..15) + IDR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40020014 + /// GPIO port output data register + pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output data (y = + /// 0..15) + ODR0: u1, + /// Port output data (y = + /// 0..15) + ODR1: u1, + /// Port output data (y = + /// 0..15) + ODR2: u1, + /// Port output data (y = + /// 0..15) + ODR3: u1, + /// Port output data (y = + /// 0..15) + ODR4: u1, + /// Port output data (y = + /// 0..15) + ODR5: u1, + /// Port output data (y = + /// 0..15) + ODR6: u1, + /// Port output data (y = + /// 0..15) + ODR7: u1, + /// Port output data (y = + /// 0..15) + ODR8: u1, + /// Port output data (y = + /// 0..15) + ODR9: u1, + /// Port output data (y = + /// 0..15) + ODR10: u1, + /// Port output data (y = + /// 0..15) + ODR11: u1, + /// Port output data (y = + /// 0..15) + ODR12: u1, + /// Port output data (y = + /// 0..15) + ODR13: u1, + /// Port output data (y = + /// 0..15) + ODR14: u1, + /// Port output data (y = + /// 0..15) + ODR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40020018 + /// GPIO port bit set/reset + /// register + pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x set bit y (y= + /// 0..15) + BS0: u1, + /// Port x set bit y (y= + /// 0..15) + BS1: u1, + /// Port x set bit y (y= + /// 0..15) + BS2: u1, + /// Port x set bit y (y= + /// 0..15) + BS3: u1, + /// Port x set bit y (y= + /// 0..15) + BS4: u1, + /// Port x set bit y (y= + /// 0..15) + BS5: u1, + /// Port x set bit y (y= + /// 0..15) + BS6: u1, + /// Port x set bit y (y= + /// 0..15) + BS7: u1, + /// Port x set bit y (y= + /// 0..15) + BS8: u1, + /// Port x set bit y (y= + /// 0..15) + BS9: u1, + /// Port x set bit y (y= + /// 0..15) + BS10: u1, + /// Port x set bit y (y= + /// 0..15) + BS11: u1, + /// Port x set bit y (y= + /// 0..15) + BS12: u1, + /// Port x set bit y (y= + /// 0..15) + BS13: u1, + /// Port x set bit y (y= + /// 0..15) + BS14: u1, + /// Port x set bit y (y= + /// 0..15) + BS15: u1, + /// Port x set bit y (y= + /// 0..15) + BR0: u1, + /// Port x reset bit y (y = + /// 0..15) + BR1: u1, + /// Port x reset bit y (y = + /// 0..15) + BR2: u1, + /// Port x reset bit y (y = + /// 0..15) + BR3: u1, + /// Port x reset bit y (y = + /// 0..15) + BR4: u1, + /// Port x reset bit y (y = + /// 0..15) + BR5: u1, + /// Port x reset bit y (y = + /// 0..15) + BR6: u1, + /// Port x reset bit y (y = + /// 0..15) + BR7: u1, + /// Port x reset bit y (y = + /// 0..15) + BR8: u1, + /// Port x reset bit y (y = + /// 0..15) + BR9: u1, + /// Port x reset bit y (y = + /// 0..15) + BR10: u1, + /// Port x reset bit y (y = + /// 0..15) + BR11: u1, + /// Port x reset bit y (y = + /// 0..15) + BR12: u1, + /// Port x reset bit y (y = + /// 0..15) + BR13: u1, + /// Port x reset bit y (y = + /// 0..15) + BR14: u1, + /// Port x reset bit y (y = + /// 0..15) + BR15: u1, + }), base_address + 0x18); + + /// address: 0x4002001c + /// GPIO port configuration lock + /// register + pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x lock bit y (y= + /// 0..15) + LCK0: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK1: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK2: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK3: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK4: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK5: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK6: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK7: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK8: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK9: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK10: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK11: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK12: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK13: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK14: u1, + /// Port x lock bit y (y= + /// 0..15) + LCK15: u1, + /// Port x lock bit y (y= + /// 0..15) + LCKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// GPIO alternate function low + /// register + pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x + /// bit y (y = 0..7) + AFRL7: u4, + }), base_address + 0x20); + + /// address: 0x40020024 + /// GPIO alternate function high + /// register + pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x + /// bit y (y = 8..15) + AFRH15: u4, + }), base_address + 0x24); + }; + + /// System configuration controller + pub const SYSCFG = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// memory remap register + pub const MEMRM = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory mapping selection + MEM_MODE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Flash bank mode selection + FB_MODE: u1, + reserved5: u1, + /// FMC memory mapping swap + SWP_FMC: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// peripheral mode configuration + /// register + pub const PMC = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// ADC1DC2 + ADC1DC2: u1, + /// ADC2DC2 + ADC2DC2: u1, + /// ADC3DC2 + ADC3DC2: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Ethernet PHY interface + /// selection + MII_RMII_SEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013808 + /// external interrupt configuration register + /// 1 + pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 0 to + /// 3) + EXTI0: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI1: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI2: u4, + /// EXTI x configuration (x = 0 to + /// 3) + EXTI3: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// external interrupt configuration register + /// 2 + pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 4 to + /// 7) + EXTI4: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI5: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI6: u4, + /// EXTI x configuration (x = 4 to + /// 7) + EXTI7: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// external interrupt configuration register + /// 3 + pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 8 to + /// 11) + EXTI8: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI9: u4, + /// EXTI10 + EXTI10: u4, + /// EXTI x configuration (x = 8 to + /// 11) + EXTI11: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// external interrupt configuration register + /// 4 + pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI x configuration (x = 12 to + /// 15) + EXTI12: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI13: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI14: u4, + /// EXTI x configuration (x = 12 to + /// 15) + EXTI15: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013820 + /// Compensation cell control + /// register + pub const CMPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Compensation cell + /// power-down + CMP_PD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// READY + READY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x20); + }; + + /// Serial peripheral interface + pub const SPI1 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001301c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000381c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI3 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40003c1c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S2ext = struct { + pub const base_address = 0x40003400; + + /// address: 0x40003400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40003408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40003410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40003414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40003418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40003420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const I2S3ext = struct { + pub const base_address = 0x40004000; + + /// address: 0x40004000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40004004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40004008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4000400c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40004010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40004014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40004018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000401c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40004020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI4 = struct { + pub const base_address = 0x40013400; + + /// address: 0x40013400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40013404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40013408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001340c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40013410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40013414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40013418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001341c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40013420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI5 = struct { + pub const base_address = 0x40015000; + + /// address: 0x40015000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015008 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001500c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015010 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015014 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015018 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001501c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015020 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + pub const SPI6 = struct { + pub const base_address = 0x40015400; + + /// address: 0x40015400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation + /// enable + CRCEN: u1, + /// Output enable in bidirectional + /// mode + BIDIOE: u1, + /// Bidirectional data mode + /// enable + BIDIMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40015404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved0: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RXNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TXEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40015408 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4001540c + /// data register + pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); + + /// address: 0x40015410 + /// CRC polynomial register + pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { + /// CRC polynomial register + CRCPOLY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40015414 + /// RX CRC register + pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx CRC register + RxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40015418 + /// TX CRC register + pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx CRC register + TxCRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001541c + /// I2S configuration register + pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length to be + /// transferred + DATLEN: u2, + /// Steady state clock + /// polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40015420 + /// I2S prescaler register + pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the + /// prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + }; + + /// Secure digital input/output + /// interface + pub const SDIO = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// power control register + pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { + /// PWRCTRL + PWRCTRL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// SDI clock control register + pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration + /// bit + PWRSAV: u1, + /// Clock divider bypass enable + /// bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection + /// bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// argument register + pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { + /// Command argument + CMDARG: u32, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// command register + pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt + /// request + WAITINT: u1, + /// CPSM Waits for ends of data transfer + /// (CmdPend internal signal). + WAITPEND: u1, + /// Command path state machine (CPSM) Enable + /// bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + /// Enable CMD completion + ENCMDcompl: u1, + /// not Interrupt Enable + nIEN: u1, + /// CE-ATA command + CE_ATACMD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// command response register + pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40012c14 + /// response 1..4 register + pub const RESP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS1: u32, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// response 1..4 register + pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS2: u32, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// response 1..4 register + pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS3: u32, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// response 1..4 register + pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { + /// see Table 132. + CARDSTATUS4: u32, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// data timer register + pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { + /// Data timeout period + DATATIME: u32, + }), base_address + 0x24); + + /// address: 0x40012c28 + /// data length register + pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length value + DATALENGTH: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0x40012c2c + /// data control register + pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DTEN + DTEN: u1, + /// Data transfer direction + /// selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream + /// or SDIO multibyte data transfer. + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40012c30 + /// data counter register + pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Data count value + DATACOUNT: u25, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + + /// address: 0x40012c34 + /// status register + pub const STA = @intToPtr(*volatile Mmio(32, packed struct { + /// Command response received (CRC check + /// failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check + /// failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun + /// error + TXUNDERR: u1, + /// Received FIFO overrun + /// error + RXOVERR: u1, + /// Command response received (CRC check + /// passed) + CMDREND: u1, + /// Command sent (no response + /// required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is + /// zero) + DATAEND: u1, + /// Start bit not detected on all data + /// signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check + /// passed) + DBCKEND: u1, + /// Command transfer in + /// progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 + /// words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at + /// least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit + /// FIFO + TXDAVL: u1, + /// Data available in receive + /// FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + /// CE-ATA command completion signal + /// received for CMD61 + CEATAEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x40012c38 + /// interrupt clear register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// SDIOIT flag clear bit + SDIOITC: u1, + /// CEATAEND flag clear bit + CEATAENDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x38); + + /// address: 0x40012c3c + /// mask register + pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// Command CRC fail interrupt + /// enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt + /// enable + DCRCFAILIE: u1, + /// Command timeout interrupt + /// enable + CTIMEOUTIE: u1, + /// Data timeout interrupt + /// enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt + /// enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt + /// enable + RXOVERRIE: u1, + /// Command response received interrupt + /// enable + CMDRENDIE: u1, + /// Command sent interrupt + /// enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// Start bit error interrupt + /// enable + STBITERRIE: u1, + /// Data block end interrupt + /// enable + DBCKENDIE: u1, + /// Command acting interrupt + /// enable + CMDACTIE: u1, + /// Data transmit acting interrupt + /// enable + TXACTIE: u1, + /// Data receive acting interrupt + /// enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt + /// enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt + /// enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt + /// enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt + /// enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt + /// enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt + /// enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt + /// enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt + /// enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt + /// enable + SDIOITIE: u1, + /// CE-ATA command completion signal + /// received interrupt enable + CEATAENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x40012c48 + /// FIFO counter register + pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Remaining number of words to be written + /// to or read from the FIFO. + FIFOCOUNT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x40012c80 + /// data FIFO register + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive and transmit FIFO + /// data + FIFOData: u32, + }), base_address + 0x80); + }; + + /// Analog-to-digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012000; + + /// address: 0x40012000 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012004 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012008 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001200c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012010 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012014 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012018 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001201c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012020 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012024 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012028 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001202c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012030 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012034 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012038 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001203c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012040 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012044 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012048 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001204c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC2 = struct { + pub const base_address = 0x40012100; + + /// address: 0x40012100 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012104 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012108 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001210c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012110 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012114 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012118 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001211c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012120 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012124 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012128 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001212c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012130 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012134 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012138 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001213c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012140 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012144 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012148 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001214c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const ADC3 = struct { + pub const base_address = 0x40012200; + + /// address: 0x40012200 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of + /// conversion + EOC: u1, + /// Injected channel end of + /// conversion + JEOC: u1, + /// Injected channel start + /// flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40012204 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + /// bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt + /// enable + AWDIE: u1, + /// Interrupt enable for injected + /// channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel + /// in scan mode + AWDSGL: u1, + /// Automatic injected group + /// conversion + JAUTO: u1, + /// Discontinuous mode on regular + /// channels + DISCEN: u1, + /// Discontinuous mode on injected + /// channels + JDISCEN: u1, + /// Discontinuous mode channel + /// count + DISCNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Analog watchdog enable on injected + /// channels + JAWDEN: u1, + /// Analog watchdog enable on regular + /// channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x4); + + /// address: 0x40012208 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Direct memory access mode (for single + /// ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC + /// mode) + DDS: u1, + /// End of conversion + /// selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// External event select for injected + /// group + JEXTSEL: u4, + /// External trigger enable for injected + /// channels + JEXTEN: u2, + /// Start conversion of injected + /// channels + JSWSTART: u1, + reserved10: u1, + /// External event select for regular + /// group + EXTSEL: u4, + /// External trigger enable for regular + /// channels + EXTEN: u2, + /// Start conversion of regular + /// channels + SWSTART: u1, + padding0: u1, + }), base_address + 0x8); + + /// address: 0x4001220c + /// sample time register 1 + pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0xc); + + /// address: 0x40012210 + /// sample time register 2 + pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample time bits + SMPx_x: u32, + }), base_address + 0x10); + + /// address: 0x40012214 + /// injected channel data offset register + /// x + pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET1: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012218 + /// injected channel data offset register + /// x + pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET2: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001221c + /// injected channel data offset register + /// x + pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET3: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012220 + /// injected channel data offset register + /// x + pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for injected channel + /// x + JOFFSET4: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012224 + /// watchdog higher threshold + /// register + pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog higher + /// threshold + HT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x24); + + /// address: 0x40012228 + /// watchdog lower threshold + /// register + pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog lower + /// threshold + LT: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x28); + + /// address: 0x4001222c + /// regular sequence register 1 + pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + SQ13: u5, + /// 14th conversion in regular + /// sequence + SQ14: u5, + /// 15th conversion in regular + /// sequence + SQ15: u5, + /// 16th conversion in regular + /// sequence + SQ16: u5, + /// Regular channel sequence + /// length + L: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012230 + /// regular sequence register 2 + pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + SQ7: u5, + /// 8th conversion in regular + /// sequence + SQ8: u5, + /// 9th conversion in regular + /// sequence + SQ9: u5, + /// 10th conversion in regular + /// sequence + SQ10: u5, + /// 11th conversion in regular + /// sequence + SQ11: u5, + /// 12th conversion in regular + /// sequence + SQ12: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012234 + /// regular sequence register 3 + pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + SQ1: u5, + /// 2nd conversion in regular + /// sequence + SQ2: u5, + /// 3rd conversion in regular + /// sequence + SQ3: u5, + /// 4th conversion in regular + /// sequence + SQ4: u5, + /// 5th conversion in regular + /// sequence + SQ5: u5, + /// 6th conversion in regular + /// sequence + SQ6: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012238 + /// injected sequence register + pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in injected + /// sequence + JSQ1: u5, + /// 2nd conversion in injected + /// sequence + JSQ2: u5, + /// 3rd conversion in injected + /// sequence + JSQ3: u5, + /// 4th conversion in injected + /// sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001223c + /// injected data register x + pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012240 + /// injected data register x + pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012244 + /// injected data register x + pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012248 + /// injected data register x + pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Injected data + JDATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001224c + /// regular data register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART6 = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART1 = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40011004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40011008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART3 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const UART7 = struct { + pub const base_address = 0x40007800; + + /// address: 0x40007800 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40007804 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007808 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000780c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007810 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007814 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007818 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const UART8 = struct { + pub const base_address = 0x40007c00; + + /// address: 0x40007c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40007c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40007c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40007c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40007c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007c18 + /// Guard time and prescaler + /// register + pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer + /// disable + BOFF1: u1, + /// DAC channel1 trigger + /// enable + TEN1: u1, + /// DAC channel1 trigger + /// selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave + /// generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude + /// selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt + /// enable + DMAUDRIE1: u1, + reserved0: u1, + reserved1: u1, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer + /// disable + BOFF2: u1, + /// DAC channel2 trigger + /// enable + TEN2: u1, + /// DAC channel2 trigger + /// selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave + /// generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude + /// selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt + /// enable + DMAUDRIE2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 software + /// trigger + SWTRIG1: u1, + /// DAC channel2 software + /// trigger + SWTRIG2: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// channel1 12-bit right-aligned data holding + /// register + pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// channel1 12-bit left aligned data holding + /// register + pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// channel1 8-bit right aligned data holding + /// register + pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// channel2 12-bit right aligned data holding + /// register + pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// channel2 12-bit left aligned data holding + /// register + pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// channel2 8-bit right-aligned data holding + /// register + pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// Dual DAC 12-bit right-aligned data holding + /// register + pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 12-bit right-aligned + /// data + DACC1DHR: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel2 12-bit right-aligned + /// data + DACC2DHR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DUAL DAC 12-bit left aligned data holding + /// register + pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC channel1 12-bit left-aligned + /// data + DACC1DHR: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC channel2 12-bit left-aligned + /// data + DACC2DHR: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DUAL DAC 8-bit right aligned data holding + /// register + pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 8-bit right-aligned + /// data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned + /// data + DACC2DHR: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// channel1 data output register + pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel1 data output + DACC1DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40007430 + /// channel2 data output register + pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC channel2 data output + DACC2DOR: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x40007434 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// DAC channel1 DMA underrun + /// flag + DMAUDR1: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + /// DAC channel2 DMA underrun + /// flag + DMAUDR2: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + }; + + /// Power control + pub const PWR = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector + /// enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write + /// protection + DBP: u1, + /// Flash power down in Stop + /// mode + FPDS: u1, + /// Low-Power Regulator Low Voltage in + /// deepsleep + LPLVDS: u1, + /// Main regulator low voltage in deepsleep + /// mode + MRLVDS: u1, + reserved0: u1, + reserved1: u1, + /// Regulator voltage scaling output + /// selection + VOS: u2, + /// Over-drive enable + ODEN: u1, + /// Over-drive switching + /// enabled + ODSWEN: u1, + /// Under-drive enable in stop + /// mode + UDEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Regulator voltage scaling output + /// selection ready bit + VOSRDY: u1, + reserved8: u1, + /// Over-drive mode ready + ODRDY: u1, + /// Over-drive mode switching + /// ready + ODSWRDY: u1, + /// Under-drive ready flag + UDRDY: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + }; + + /// Independent watchdog + pub const IWDG = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Key register + pub const KR = @intToPtr(*volatile Mmio(32, packed struct { + /// Key value (write only, read + /// 0000h) + KEY: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog counter reload + /// value + RL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog prescaler value + /// update + PVU: u1, + /// Watchdog counter reload value + /// update + RVU: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + + /// Window watchdog + pub const WWDG = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB0: u1, + /// Timer base + WDGTB1: u1, + /// Early wakeup interrupt + EWI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// time register + pub const TR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved0: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved1: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// date register + pub const DR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active + /// edge + TSEDGE: u1, + /// Reference clock detection enable (50 or + /// 60 Hz) + REFCKON: u1, + reserved0: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration + /// enable + DCE: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt + /// enable + WUTIE: u1, + /// Time-stamp interrupt + /// enable + TSIE: u1, + /// Add 1 hour (summer time + /// change) + ADD1H: u1, + /// Subtract 1 hour (winter time + /// change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved1: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// initialization and status + /// register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization + /// flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// TAMPER2 detection flag + TAMP2F: u1, + reserved0: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// prescaler register + pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { + /// Synchronous prescaler + /// factor + PREDIV_S: u15, + reserved0: u1, + /// Asynchronous prescaler + /// factor + PREDIV_A: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// wakeup timer register + pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup auto-reload value + /// bits + WUT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// calibration register + pub const CALIBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital calibration + DC: u5, + reserved0: u1, + reserved1: u1, + /// Digital calibration sign + DCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x4000281c + /// alarm A register + pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// alarm B register + pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD + /// format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// write protection register + pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write protection key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40002828 + /// sub second register + pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000282c + /// shift control register + pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Subtract a fraction of a + /// second + SUBFS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Add one second + ADD1S: u1, + }), base_address + 0x2c); + + /// address: 0x40002830 + /// time stamp time register + pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x30); + + /// address: 0x40002834 + /// time stamp date register + pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved0: u1, + reserved1: u1, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// timestamp sub second register + pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub second value + SS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x38); + + /// address: 0x4000283c + /// calibration register + pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration minus + CALM: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Use a 16-second calibration cycle + /// period + CALW16: u1, + /// Use an 8-second calibration cycle + /// period + CALW8: u1, + /// Increase frequency of RTC by 488.5 + /// ppm + CALP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40002840 + /// tamper and alternate function configuration + /// register + pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + reserved0: u1, + reserved1: u1, + /// Activate timestamp on tamper detection + /// event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40002844 + /// alarm A sub second register + pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x44); + + /// address: 0x40002848 + /// alarm B sub second register + pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Sub seconds value + SS: u15, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mask the most-significant bits starting + /// at this bit + MASKSS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x48); + + /// address: 0x40002850 + /// backup register + pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x50); + + /// address: 0x40002854 + /// backup register + pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x54); + + /// address: 0x40002858 + /// backup register + pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x58); + + /// address: 0x4000285c + /// backup register + pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x5c); + + /// address: 0x40002860 + /// backup register + pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x60); + + /// address: 0x40002864 + /// backup register + pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x64); + + /// address: 0x40002868 + /// backup register + pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x68); + + /// address: 0x4000286c + /// backup register + pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x6c); + + /// address: 0x40002870 + /// backup register + pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x70); + + /// address: 0x40002874 + /// backup register + pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x74); + + /// address: 0x40002878 + /// backup register + pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x78); + + /// address: 0x4000287c + /// backup register + pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x7c); + + /// address: 0x40002880 + /// backup register + pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x80); + + /// address: 0x40002884 + /// backup register + pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x84); + + /// address: 0x40002888 + /// backup register + pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x88); + + /// address: 0x4000288c + /// backup register + pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x8c); + + /// address: 0x40002890 + /// backup register + pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x90); + + /// address: 0x40002894 + /// backup register + pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x94); + + /// address: 0x40002898 + /// backup register + pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x98); + + /// address: 0x4000289c + /// backup register + pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { + /// BKP + BKP: u32, + }), base_address + 0x9c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const UART4 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + pub const UART5 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not + /// empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register + /// empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// Baud rate register + pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt + /// enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved0: u1, + /// Oversampling mode + OVER8: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART node + ADD: u4, + reserved0: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Control register 3 + pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved0: u1, + reserved1: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// One sample bit method + /// enable + ONEBIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + }; + + /// Common ADC registers + pub const C_ADC = struct { + pub const base_address = 0x40012300; + + /// address: 0x40012300 + /// ADC Common status register + pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog flag of ADC + /// 1 + AWD1: u1, + /// End of conversion of ADC 1 + EOC1: u1, + /// Injected channel end of conversion of + /// ADC 1 + JEOC1: u1, + /// Injected channel Start flag of ADC + /// 1 + JSTRT1: u1, + /// Regular channel Start flag of ADC + /// 1 + STRT1: u1, + /// Overrun flag of ADC 1 + OVR1: u1, + reserved0: u1, + reserved1: u1, + /// Analog watchdog flag of ADC + /// 2 + AWD2: u1, + /// End of conversion of ADC 2 + EOC2: u1, + /// Injected channel end of conversion of + /// ADC 2 + JEOC2: u1, + /// Injected channel Start flag of ADC + /// 2 + JSTRT2: u1, + /// Regular channel Start flag of ADC + /// 2 + STRT2: u1, + /// Overrun flag of ADC 2 + OVR2: u1, + reserved2: u1, + reserved3: u1, + /// Analog watchdog flag of ADC + /// 3 + AWD3: u1, + /// End of conversion of ADC 3 + EOC3: u1, + /// Injected channel end of conversion of + /// ADC 3 + JEOC3: u1, + /// Injected channel Start flag of ADC + /// 3 + JSTRT3: u1, + /// Regular channel Start flag of ADC + /// 3 + STRT3: u1, + /// Overrun flag of ADC3 + OVR3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x0); + + /// address: 0x40012304 + /// ADC common control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Multi ADC mode selection + MULT: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Delay between 2 sampling + /// phases + DELAY: u4, + reserved3: u1, + /// DMA disable selection for multi-ADC + /// mode + DDS: u1, + /// Direct memory access mode for multi ADC + /// mode + DMA: u2, + /// ADC prescaler + ADCPRE: u2, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT + /// enable + TSVREFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012308 + /// ADC common regular data register for dual + /// and triple modes + pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st data item of a pair of regular + /// conversions + DATA1: u16, + /// 2nd data item of a pair of regular + /// conversions + DATA2: u16, + }), base_address + 0x8); + }; + + /// Advanced-timers + pub const TIM1 = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010030 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010044 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + pub const TIM8 = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare preloaded + /// control + CCPC: u1, + reserved0: u1, + /// Capture/compare control update + /// selection + CCUS: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved0: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + /// Capture/Compare control update + /// generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40010418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear + /// enable + OC1CE: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear + /// enable + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40010418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4001041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 3 + /// selection + CC3S: u2, + /// Output compare 3 fast + /// enable + OC3FE: u1, + /// Output compare 3 preload + /// enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear + /// enable + OC3CE: u1, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Output compare 4 fast + /// enable + OC4FE: u1, + /// Output compare 4 preload + /// enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear + /// enable + OC4CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4001041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40010420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output + /// enable + CC1NE: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output + /// enable + CC2NE: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output + /// enable + CC3NE: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x20); + + /// address: 0x40010424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40010428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40010434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40010438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4001043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); + + /// address: 0x40010440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); + + /// address: 0x40010448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4001044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40010430 + /// repetition counter register + pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Repetition counter value + REP: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x30); + + /// address: 0x40010444 + /// break and dead-time register + pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle + /// mode + OSSI: u1, + /// Off-state selection for Run + /// mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + }; + + /// General purpose timers + pub const TIM2 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000002c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000050 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Timer Input 4 remap + ITR1_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM3 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000041c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000042c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + pub const TIM4 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000082c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + }; + + /// General-purpose-timers + pub const TIM5 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode + /// selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Capture/compare DMA + /// selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + /// Capture/Compare 3 interrupt + /// enable + CC3IE: u1, + /// Capture/Compare 4 interrupt + /// enable + CC4IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TIE: u1, + reserved1: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request + /// enable + CC1DE: u1, + /// Capture/Compare 2 DMA request + /// enable + CC2DE: u1, + /// Capture/Compare 3 DMA request + /// enable + CC3DE: u1, + /// Capture/Compare 4 DMA request + /// enable + CC4DE: u1, + reserved2: u1, + /// Trigger DMA request enable + TDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + /// Capture/Compare 3 interrupt + /// flag + CC3IF: u1, + /// Capture/Compare 4 interrupt + /// flag + CC4IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TIF: u1, + reserved1: u1, + reserved2: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + /// Capture/Compare 3 overcapture + /// flag + CC3OF: u1, + /// Capture/Compare 4 overcapture + /// flag + CC4OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + /// Capture/compare 3 + /// generation + CC3G: u1, + /// Capture/compare 4 + /// generation + CC4G: u1, + reserved0: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (output + /// mode) + pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// capture/compare mode register 2 (input + /// mode) + pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/compare 3 + /// selection + CC3S: u2, + /// Input capture 3 prescaler + IC3PSC: u2, + /// Input capture 3 filter + IC3F: u4, + /// Capture/Compare 4 + /// selection + CC4S: u2, + /// Input capture 4 prescaler + IC4PSC: u2, + /// Input capture 4 filter + IC4F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + /// Capture/Compare 3 output + /// enable + CC3E: u1, + /// Capture/Compare 3 output + /// Polarity + CC3P: u1, + reserved2: u1, + /// Capture/Compare 3 output + /// Polarity + CC3NP: u1, + /// Capture/Compare 4 output + /// enable + CC4E: u1, + /// Capture/Compare 3 output + /// Polarity + CC4P: u1, + reserved3: u1, + /// Capture/Compare 4 output + /// Polarity + CC4NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// counter + pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), base_address + 0x24); + + /// address: 0x40000c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40000c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), base_address + 0x2c); + + /// address: 0x40000c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 1 + /// value + CCR1_L: u16, + /// High Capture/Compare 1 + /// value + CCR1_H: u16, + }), base_address + 0x34); + + /// address: 0x40000c38 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare 2 + /// value + CCR2_L: u16, + /// High Capture/Compare 2 + /// value + CCR2_H: u16, + }), base_address + 0x38); + + /// address: 0x40000c3c + /// capture/compare register 3 + pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), base_address + 0x3c); + + /// address: 0x40000c40 + /// capture/compare register 4 + pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA control register + pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA base address + DBA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA burst length + DBL: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA address for full transfer + pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA register for burst + /// accesses + DMAB: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x40000c50 + /// TIM5 option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Timer Input 4 remap + IT4_RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x50); + }; + + /// General purpose timers + pub const TIM9 = struct { + pub const base_address = 0x40014000; + + /// address: 0x40014000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40014004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40014008 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4001400c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40014010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40014014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40014018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40014020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40014024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001402c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014038 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + pub const TIM12 = struct { + pub const base_address = 0x40001800; + + /// address: 0x40001800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// slave mode control register + pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Slave mode selection + SMS: u3, + reserved0: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + /// Capture/Compare 2 interrupt + /// enable + CC2IE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt enable + TIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + /// Capture/Compare 2 interrupt + /// flag + CC2IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger interrupt flag + TIF: u1, + reserved3: u1, + reserved4: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + /// Capture/compare 2 overcapture + /// flag + CC2OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x40001814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + /// Capture/compare 2 + /// generation + CC2G: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Trigger generation + TG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40001818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Output Compare 2 fast + /// enable + OC2FE: u1, + /// Output Compare 2 preload + /// enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u3, + reserved0: u1, + /// Capture/Compare 2 + /// selection + CC2S: u2, + /// Input capture 2 prescaler + IC2PCS: u2, + /// Input capture 2 filter + IC2F: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x40001820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + /// Capture/Compare 2 output + /// enable + CC2E: u1, + /// Capture/Compare 2 output + /// Polarity + CC2P: u1, + reserved1: u1, + /// Capture/Compare 2 output + /// Polarity + CC2NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000182c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40001838 + /// capture/compare register 2 + pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + + /// General-purpose-timers + pub const TIM10 = struct { + pub const base_address = 0x40014400; + + /// address: 0x40014400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001440c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014418 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014418 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014420 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001442c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014434 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM13 = struct { + pub const base_address = 0x40001c00; + + /// address: 0x40001c00 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40001c0c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40001c10 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40001c14 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40001c18 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40001c20 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40001c24 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001c28 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x40001c2c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40001c34 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + pub const TIM14 = struct { + pub const base_address = 0x40002000; + + /// address: 0x40002000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4000200c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40002014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40002018 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40002018 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40002020 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40002024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40002028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000202c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40002034 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + }; + + /// General-purpose-timers + pub const TIM11 = struct { + pub const base_address = 0x40014800; + + /// address: 0x40014800 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x4001480c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt + /// enable + CC1IE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40014810 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt + /// flag + CC1IF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Capture/Compare 1 overcapture + /// flag + CC1OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40014814 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + /// Capture/compare 1 + /// generation + CC1G: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x14); + + /// address: 0x40014818 + /// capture/compare mode register 1 (output + /// mode) + pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Output Compare 1 fast + /// enable + OC1FE: u1, + /// Output Compare 1 preload + /// enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x18); + + /// address: 0x40014818 + /// capture/compare mode register 1 (input + /// mode) + pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 + /// selection + CC1S: u2, + /// Input capture 1 prescaler + ICPCS: u2, + /// Input capture 1 filter + IC1F: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x40014820 + /// capture/compare enable + /// register + pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { + /// Capture/Compare 1 output + /// enable + CC1E: u1, + /// Capture/Compare 1 output + /// Polarity + CC1P: u1, + reserved0: u1, + /// Capture/Compare 1 output + /// Polarity + CC1NP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x20); + + /// address: 0x40014824 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40014828 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4001482c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + + /// address: 0x40014834 + /// capture/compare register 1 + pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); + + /// address: 0x40014850 + /// option register + pub const OR = @intToPtr(*volatile Mmio(32, packed struct { + /// Input 1 remapping + /// capability + RMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x50); + }; + + /// Basic timers + pub const TIM6 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001028 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000102c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + pub const TIM7 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload preload enable + ARPE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode selection + MMS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt enable + UIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UDE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update interrupt flag + UIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { + /// Update generation + UG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// counter + pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40001428 + /// prescaler + pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x4000142c + /// auto-reload register + pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); + }; + + /// Ethernet: media access control + /// (MAC) + pub const Ethernet_MAC = struct { + pub const base_address = 0x40028000; + + /// address: 0x40028000 + /// Ethernet MAC configuration + /// register + pub const MACCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// DC + DC: u1, + /// BL + BL: u2, + /// APCS + APCS: u1, + reserved2: u1, + /// RD + RD: u1, + /// IPCO + IPCO: u1, + /// DM + DM: u1, + /// LM + LM: u1, + /// ROD + ROD: u1, + /// FES + FES: u1, + reserved3: u1, + /// CSD + CSD: u1, + /// IFG + IFG: u3, + reserved4: u1, + reserved5: u1, + /// JD + JD: u1, + /// WD + WD: u1, + reserved6: u1, + /// CSTF + CSTF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40028004 + /// Ethernet MAC frame filter + /// register + pub const MACFFR = @intToPtr(*volatile Mmio(32, packed struct { + /// PM + PM: u1, + /// HU + HU: u1, + /// HM + HM: u1, + /// DAIF + DAIF: u1, + /// RAM + RAM: u1, + /// BFD + BFD: u1, + /// PCF + PCF: u1, + /// SAIF + SAIF: u1, + /// SAF + SAF: u1, + /// HPF + HPF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// RA + RA: u1, + }), base_address + 0x4); + + /// address: 0x40028008 + /// Ethernet MAC hash table high + /// register + pub const MACHTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTH + HTH: u32, + }), base_address + 0x8); + + /// address: 0x4002800c + /// Ethernet MAC hash table low + /// register + pub const MACHTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + HTL: u32, + }), base_address + 0xc); + + /// address: 0x40028010 + /// Ethernet MAC MII address + /// register + pub const MACMIIAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MB + MB: u1, + /// MW + MW: u1, + /// CR + CR: u3, + reserved0: u1, + /// MR + MR: u5, + /// PA + PA: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40028014 + /// Ethernet MAC MII data register + pub const MACMIIDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TD + TD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40028018 + /// Ethernet MAC flow control + /// register + pub const MACFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// FCB + FCB: u1, + /// TFCE + TFCE: u1, + /// RFCE + RFCE: u1, + /// UPFD + UPFD: u1, + /// PLT + PLT: u2, + reserved0: u1, + /// ZQPD + ZQPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// PT + PT: u16, + }), base_address + 0x18); + + /// address: 0x4002801c + /// Ethernet MAC VLAN tag register + pub const MACVLANTR = @intToPtr(*volatile Mmio(32, packed struct { + /// VLANTI + VLANTI: u16, + /// VLANTC + VLANTC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x4002802c + /// Ethernet MAC PMT control and status + /// register + pub const MACPMTCSR = @intToPtr(*volatile Mmio(32, packed struct { + /// PD + PD: u1, + /// MPE + MPE: u1, + /// WFE + WFE: u1, + reserved0: u1, + reserved1: u1, + /// MPR + MPR: u1, + /// WFR + WFR: u1, + reserved2: u1, + reserved3: u1, + /// GU + GU: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + /// WFFRPR + WFFRPR: u1, + }), base_address + 0x2c); + + /// address: 0x40028034 + /// Ethernet MAC debug register + pub const MACDBGR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x34); + + /// address: 0x40028038 + /// Ethernet MAC interrupt status + /// register + pub const MACSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTS + PMTS: u1, + /// MMCS + MMCS: u1, + /// MMCRS + MMCRS: u1, + /// MMCTS + MMCTS: u1, + reserved3: u1, + reserved4: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x38); + + /// address: 0x4002803c + /// Ethernet MAC interrupt mask + /// register + pub const MACIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// PMTIM + PMTIM: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// TSTIM + TSTIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x3c); + + /// address: 0x40028040 + /// Ethernet MAC address 0 high + /// register + pub const MACA0HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC address0 high + MACA0H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// Always 1 + MO: u1, + }), base_address + 0x40); + + /// address: 0x40028044 + /// Ethernet MAC address 0 low + /// register + pub const MACA0LR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + MACA0L: u32, + }), base_address + 0x44); + + /// address: 0x40028048 + /// Ethernet MAC address 1 high + /// register + pub const MACA1HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA1H + MACA1H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x48); + + /// address: 0x4002804c + /// Ethernet MAC address1 low + /// register + pub const MACA1LR = @intToPtr(*volatile u32, base_address + 0x4c); + + /// address: 0x40028050 + /// Ethernet MAC address 2 high + /// register + pub const MACA2HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MAC2AH + MAC2AH: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x50); + + /// address: 0x40028054 + /// Ethernet MAC address 2 low + /// register + pub const MACA2LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA2L + MACA2L: u31, + padding0: u1, + }), base_address + 0x54); + + /// address: 0x40028058 + /// Ethernet MAC address 3 high + /// register + pub const MACA3HR = @intToPtr(*volatile Mmio(32, packed struct { + /// MACA3H + MACA3H: u16, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), base_address + 0x58); + + /// address: 0x4002805c + /// Ethernet MAC address 3 low + /// register + pub const MACA3LR = @intToPtr(*volatile Mmio(32, packed struct { + /// MBCA3L + MBCA3L: u32, + }), base_address + 0x5c); + }; + + /// Ethernet: MAC management counters + pub const Ethernet_MMC = struct { + pub const base_address = 0x40028100; + + /// address: 0x40028100 + /// Ethernet MMC control register + pub const MMCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x0); + + /// address: 0x40028104 + /// Ethernet MMC receive interrupt + /// register + pub const MMCRIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCES + RFCES: u1, + /// RFAES + RFAES: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFS + RGUFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40028108 + /// Ethernet MMC transmit interrupt + /// register + pub const MMCTIR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCS + TGFSCS: u1, + /// TGFMSCS + TGFMSCS: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// TGFS + TGFS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x4002810c + /// Ethernet MMC receive interrupt mask + /// register + pub const MMCRIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RFCEM + RFCEM: u1, + /// RFAEM + RFAEM: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// RGUFM + RGUFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0xc); + + /// address: 0x40028110 + /// Ethernet MMC transmit interrupt mask + /// register + pub const MMCTIMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// TGFSCM + TGFSCM: u1, + /// TGFMSCM + TGFMSCM: u1, + /// TGFM + TGFM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0x4002814c + /// Ethernet MMC transmitted good frames after a + /// single collision counter + pub const MMCTGFSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFSCC + TGFSCC: u32, + }), base_address + 0x4c); + + /// address: 0x40028150 + /// Ethernet MMC transmitted good frames after + /// more than a single collision + pub const MMCTGFMSCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TGFMSCC + TGFMSCC: u32, + }), base_address + 0x50); + + /// address: 0x40028168 + /// Ethernet MMC transmitted good frames counter + /// register + pub const MMCTGFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTL + TGFC: u32, + }), base_address + 0x68); + + /// address: 0x40028194 + /// Ethernet MMC received frames with CRC error + /// counter register + pub const MMCRFCECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFCFC + RFCFC: u32, + }), base_address + 0x94); + + /// address: 0x40028198 + /// Ethernet MMC received frames with alignment + /// error counter register + pub const MMCRFAECR = @intToPtr(*volatile Mmio(32, packed struct { + /// RFAEC + RFAEC: u32, + }), base_address + 0x98); + + /// address: 0x400281c4 + /// MMC received good unicast frames counter + /// register + pub const MMCRGUFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// RGUFC + RGUFC: u32, + }), base_address + 0xc4); + }; + + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = struct { + pub const base_address = 0x40028700; + + /// address: 0x40028700 + /// Ethernet PTP time stamp control + /// register + pub const PTPTSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved0: u1, + reserved1: u1, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40028704 + /// Ethernet PTP subsecond increment + /// register + pub const PTPSSIR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSSI + STSSI: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x4); + + /// address: 0x40028708 + /// Ethernet PTP time stamp high + /// register + pub const PTPTSHR = @intToPtr(*volatile Mmio(32, packed struct { + /// STS + STS: u32, + }), base_address + 0x8); + + /// address: 0x4002870c + /// Ethernet PTP time stamp low + /// register + pub const PTPTSLR = @intToPtr(*volatile Mmio(32, packed struct { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, + }), base_address + 0xc); + + /// address: 0x40028710 + /// Ethernet PTP time stamp high update + /// register + pub const PTPTSHUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUS + TSUS: u32, + }), base_address + 0x10); + + /// address: 0x40028714 + /// Ethernet PTP time stamp low update + /// register + pub const PTPTSLUR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSUSS + TSUSS: u31, + /// TSUSS + TSUPNS: u1, + }), base_address + 0x14); + + /// address: 0x40028718 + /// Ethernet PTP time stamp addend + /// register + pub const PTPTSAR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSA + TSA: u32, + }), base_address + 0x18); + + /// address: 0x4002871c + /// Ethernet PTP target time high + /// register + pub const PTPTTHR = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 + TTSH: u32, + }), base_address + 0x1c); + + /// address: 0x40028720 + /// Ethernet PTP target time low + /// register + pub const PTPTTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// TTSL + TTSL: u32, + }), base_address + 0x20); + + /// address: 0x40028728 + /// Ethernet PTP time stamp status + /// register + pub const PTPTSSR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4002872c + /// Ethernet PTP PPS control + /// register + pub const PTPPPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x2c); + }; + + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = struct { + pub const base_address = 0x40029000; + + /// address: 0x40029000 + /// Ethernet DMA bus mode register + pub const DMABMR = @intToPtr(*volatile Mmio(32, packed struct { + /// SR + SR: u1, + /// DA + DA: u1, + /// DSL + DSL: u5, + /// EDFE + EDFE: u1, + /// PBL + PBL: u6, + /// RTPR + RTPR: u2, + /// FB + FB: u1, + /// RDP + RDP: u6, + /// USP + USP: u1, + /// FPM + FPM: u1, + /// AAB + AAB: u1, + /// MB + MB: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x40029004 + /// Ethernet DMA transmit poll demand + /// register + pub const DMATPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// TPD + TPD: u32, + }), base_address + 0x4); + + /// address: 0x40029008 + /// EHERNET DMA receive poll demand + /// register + pub const DMARPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// RPD + RPD: u32, + }), base_address + 0x8); + + /// address: 0x4002900c + /// Ethernet DMA receive descriptor list address + /// register + pub const DMARDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// SRL + SRL: u32, + }), base_address + 0xc); + + /// address: 0x40029010 + /// Ethernet DMA transmit descriptor list + /// address register + pub const DMATDLAR = @intToPtr(*volatile Mmio(32, packed struct { + /// STL + STL: u32, + }), base_address + 0x10); + + /// address: 0x40029014 + /// Ethernet DMA status register + pub const DMASR = @intToPtr(*volatile Mmio(32, packed struct { + /// TS + TS: u1, + /// TPSS + TPSS: u1, + /// TBUS + TBUS: u1, + /// TJTS + TJTS: u1, + /// ROS + ROS: u1, + /// TUS + TUS: u1, + /// RS + RS: u1, + /// RBUS + RBUS: u1, + /// RPSS + RPSS: u1, + /// PWTS + PWTS: u1, + /// ETS + ETS: u1, + reserved0: u1, + reserved1: u1, + /// FBES + FBES: u1, + /// ERS + ERS: u1, + /// AIS + AIS: u1, + /// NIS + NIS: u1, + /// RPS + RPS: u3, + /// TPS + TPS: u3, + /// EBS + EBS: u3, + reserved2: u1, + /// MMCS + MMCS: u1, + /// PMTS + PMTS: u1, + /// TSTS + TSTS: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x40029018 + /// Ethernet DMA operation mode + /// register + pub const DMAOMR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved1: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved10: u1, + reserved11: u1, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x4002901c + /// Ethernet DMA interrupt enable + /// register + pub const DMAIER = @intToPtr(*volatile Mmio(32, packed struct { + /// TIE + TIE: u1, + /// TPSIE + TPSIE: u1, + /// TBUIE + TBUIE: u1, + /// TJTIE + TJTIE: u1, + /// ROIE + ROIE: u1, + /// TUIE + TUIE: u1, + /// RIE + RIE: u1, + /// RBUIE + RBUIE: u1, + /// RPSIE + RPSIE: u1, + /// RWTIE + RWTIE: u1, + /// ETIE + ETIE: u1, + reserved0: u1, + reserved1: u1, + /// FBEIE + FBEIE: u1, + /// ERIE + ERIE: u1, + /// AISE + AISE: u1, + /// NISE + NISE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x1c); + + /// address: 0x40029020 + /// Ethernet DMA missed frame and buffer + /// overflow counter register + pub const DMAMFBOCR = @intToPtr(*volatile Mmio(32, packed struct { + /// MFC + MFC: u16, + /// OMFC + OMFC: u1, + /// MFA + MFA: u11, + /// OFOC + OFOC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0x40029024 + /// Ethernet DMA receive status watchdog timer + /// register + pub const DMARSWTR = @intToPtr(*volatile Mmio(32, packed struct { + /// RSWTC + RSWTC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x24); + + /// address: 0x40029048 + /// Ethernet DMA current host transmit + /// descriptor register + pub const DMACHTDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTDAP + HTDAP: u32, + }), base_address + 0x48); + + /// address: 0x4002904c + /// Ethernet DMA current host receive descriptor + /// register + pub const DMACHRDR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRDAP + HRDAP: u32, + }), base_address + 0x4c); + + /// address: 0x40029050 + /// Ethernet DMA current host transmit buffer + /// address register + pub const DMACHTBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HTBAP + HTBAP: u32, + }), base_address + 0x50); + + /// address: 0x40029054 + /// Ethernet DMA current host receive buffer + /// address register + pub const DMACHRBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// HRBAP + HRBAP: u32, + }), base_address + 0x54); + }; + + /// Cryptographic processor + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Independent Data register + pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// OTG_FS control and status register + /// (OTG_FS_GOTGCTL) + pub const FS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// OTG_FS interrupt register + /// (OTG_FS_GOTGINT) + pub const FS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// OTG_FS AHB configuration register + /// (OTG_FS_GAHBCFG) + pub const FS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// OTG_FS USB configuration register + /// (OTG_FS_GUSBCFG) + pub const FS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Full Speed serial transceiver + /// select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x50000010 + /// OTG_FS reset register + /// (OTG_FS_GRSTCTL) + pub const FS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x50000014 + /// OTG_FS core interrupt register + /// (OTG_FS_GINTSTS) + pub const FS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host + /// mode)/Incomplete isochronous OUT transfer(Device + /// mode) + IPXFR_INCOMPISOOUT: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved6: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUPINT: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// OTG_FS interrupt mask register + /// (OTG_FS_GINTMSK) + pub const FS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty + /// mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host + /// mode)/Incomplete isochronous OUT transfer mask(Device + /// mode) + IPXFRM_IISOOXFRM: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved6: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x5000001c + /// OTG_FS Receive status debug read(Device + /// mode) + pub const FS_GRXSTSR_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x5000001c + /// OTG_FS Receive status debug + /// read(Hostmode) + pub const FS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x50000024 + /// OTG_FS Receive FIFO size register + /// (OTG_FS_GRXFSIZ) + pub const FS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Device mode) + pub const FS_GNPTXFSIZ_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x50000028 + /// OTG_FS non-periodic transmit FIFO size + /// register (Host mode) + pub const FS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic transmit RAM start + /// address + NPTXFSA: u16, + /// Non-periodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x5000002c + /// OTG_FS non-periodic transmit FIFO/queue + /// status register (OTG_FS_GNPTXSTS) + pub const FS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Non-periodic transmit request queue + /// space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x50000038 + /// OTG_FS general core configuration register + /// (OTG_FS_GCCFG) + pub const FS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + reserved16: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// core ID register + pub const FS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x50000100 + /// OTG_FS Host periodic transmit FIFO size + /// register (OTG_FS_HPTXFSIZ) + pub const FS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), base_address + 0x100); + + /// address: 0x50000104 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF2) + pub const FS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO2 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x50000108 + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF3) + pub const FS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO3 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x5000010c + /// OTG_FS device IN endpoint transmit FIFO size + /// register (OTG_FS_DIEPTXF4) + pub const FS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO4 transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x10c); + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// OTG_FS host configuration register + /// (OTG_FS_HCFG) + pub const FS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// OTG_FS Host frame interval + /// register + pub const HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// OTG_FS host frame number/frame time + /// remaining register (OTG_FS_HFNUM) + pub const FS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x50000410 + /// OTG_FS_Host periodic transmit FIFO/queue + /// status register (OTG_FS_HPTXSTS) + pub const FS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x50000414 + /// OTG_FS Host all channels interrupt + /// register + pub const HAINT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x50000418 + /// OTG_FS host all channels interrupt mask + /// register + pub const HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x50000440 + /// OTG_FS host port control and status register + /// (OTG_FS_HPRT) + pub const FS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x50000500 + /// OTG_FS host channel-0 characteristics + /// register (OTG_FS_HCCHAR0) + pub const FS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x50000520 + /// OTG_FS host channel-1 characteristics + /// register (OTG_FS_HCCHAR1) + pub const FS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x50000540 + /// OTG_FS host channel-2 characteristics + /// register (OTG_FS_HCCHAR2) + pub const FS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x50000560 + /// OTG_FS host channel-3 characteristics + /// register (OTG_FS_HCCHAR3) + pub const FS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x50000580 + /// OTG_FS host channel-4 characteristics + /// register (OTG_FS_HCCHAR4) + pub const FS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x500005a0 + /// OTG_FS host channel-5 characteristics + /// register (OTG_FS_HCCHAR5) + pub const FS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x500005c0 + /// OTG_FS host channel-6 characteristics + /// register (OTG_FS_HCCHAR6) + pub const FS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x500005e0 + /// OTG_FS host channel-7 characteristics + /// register (OTG_FS_HCCHAR7) + pub const FS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x50000508 + /// OTG_FS host channel-0 interrupt register + /// (OTG_FS_HCINT0) + pub const FS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x50000528 + /// OTG_FS host channel-1 interrupt register + /// (OTG_FS_HCINT1) + pub const FS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x50000548 + /// OTG_FS host channel-2 interrupt register + /// (OTG_FS_HCINT2) + pub const FS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x50000568 + /// OTG_FS host channel-3 interrupt register + /// (OTG_FS_HCINT3) + pub const FS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x50000588 + /// OTG_FS host channel-4 interrupt register + /// (OTG_FS_HCINT4) + pub const FS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x500005a8 + /// OTG_FS host channel-5 interrupt register + /// (OTG_FS_HCINT5) + pub const FS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x500005c8 + /// OTG_FS host channel-6 interrupt register + /// (OTG_FS_HCINT6) + pub const FS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x500005e8 + /// OTG_FS host channel-7 interrupt register + /// (OTG_FS_HCINT7) + pub const FS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x5000050c + /// OTG_FS host channel-0 mask register + /// (OTG_FS_HCINTMSK0) + pub const FS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x5000052c + /// OTG_FS host channel-1 mask register + /// (OTG_FS_HCINTMSK1) + pub const FS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x5000054c + /// OTG_FS host channel-2 mask register + /// (OTG_FS_HCINTMSK2) + pub const FS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x5000056c + /// OTG_FS host channel-3 mask register + /// (OTG_FS_HCINTMSK3) + pub const FS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x5000058c + /// OTG_FS host channel-4 mask register + /// (OTG_FS_HCINTMSK4) + pub const FS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x500005ac + /// OTG_FS host channel-5 mask register + /// (OTG_FS_HCINTMSK5) + pub const FS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x500005cc + /// OTG_FS host channel-6 mask register + /// (OTG_FS_HCINTMSK6) + pub const FS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x500005ec + /// OTG_FS host channel-7 mask register + /// (OTG_FS_HCINTMSK7) + pub const FS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved0: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x50000510 + /// OTG_FS host channel-0 transfer size + /// register + pub const FS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x50000530 + /// OTG_FS host channel-1 transfer size + /// register + pub const FS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000550 + /// OTG_FS host channel-2 transfer size + /// register + pub const FS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000570 + /// OTG_FS host channel-3 transfer size + /// register + pub const FS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000590 + /// OTG_FS host channel-x transfer size + /// register + pub const FS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x500005b0 + /// OTG_FS host channel-5 transfer size + /// register + pub const FS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x500005d0 + /// OTG_FS host channel-6 transfer size + /// register + pub const FS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x500005f0 + /// OTG_FS host channel-7 transfer size + /// register + pub const FS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = struct { + pub const base_address = 0x50000800; + + /// address: 0x50000800 + /// OTG_FS device configuration register + /// (OTG_FS_DCFG) + pub const FS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x50000804 + /// OTG_FS device control register + /// (OTG_FS_DCTL) + pub const FS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x50000808 + /// OTG_FS device status register + /// (OTG_FS_DSTS) + pub const FS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x50000810 + /// OTG_FS device IN endpoint common interrupt + /// mask register (OTG_FS_DIEPMSK) + pub const FS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (Non-isochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x10); + + /// address: 0x50000814 + /// OTG_FS device OUT endpoint common interrupt + /// mask register (OTG_FS_DOEPMSK) + pub const FS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x14); + + /// address: 0x50000818 + /// OTG_FS device all endpoints interrupt + /// register (OTG_FS_DAINT) + pub const FS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x5000081c + /// OTG_FS all endpoints interrupt mask register + /// (OTG_FS_DAINTMSK) + pub const FS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x1c); + + /// address: 0x50000828 + /// OTG_FS device VBUS discharge time + /// register + pub const DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x5000082c + /// OTG_FS device VBUS pulsing time + /// register + pub const DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x50000834 + /// OTG_FS device IN endpoint FIFO empty + /// interrupt mask register + pub const DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x50000900 + /// OTG_FS device control IN endpoint 0 control + /// register (OTG_FS_DIEPCTL0) + pub const FS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved14: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved15: u1, + reserved16: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x50000920 + /// OTG device endpoint-1 control + /// register + pub const DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x50000940 + /// OTG device endpoint-2 control + /// register + pub const DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x50000960 + /// OTG device endpoint-3 control + /// register + pub const DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved4: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x50000b00 + /// device endpoint-0 control + /// register + pub const DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USBAEP + USBAEP: u1, + reserved13: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x50000b20 + /// device endpoint-1 control + /// register + pub const DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x50000b40 + /// device endpoint-2 control + /// register + pub const DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x50000b60 + /// device endpoint-3 control + /// register + pub const DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// MPSIZ + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x50000908 + /// device endpoint-x interrupt + /// register + pub const DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x108); + + /// address: 0x50000928 + /// device endpoint-1 interrupt + /// register + pub const DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x128); + + /// address: 0x50000948 + /// device endpoint-2 interrupt + /// register + pub const DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x148); + + /// address: 0x50000968 + /// device endpoint-3 interrupt + /// register + pub const DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved1: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x168); + + /// address: 0x50000b08 + /// device endpoint-0 interrupt + /// register + pub const DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x50000b28 + /// device endpoint-1 interrupt + /// register + pub const DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x328); + + /// address: 0x50000b48 + /// device endpoint-2 interrupt + /// register + pub const DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x348); + + /// address: 0x50000b68 + /// device endpoint-3 interrupt + /// register + pub const DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved0: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved1: u1, + /// B2BSTUP + B2BSTUP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x368); + + /// address: 0x50000910 + /// device endpoint-0 transfer size + /// register + pub const DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x50000b10 + /// device OUT endpoint-0 transfer size + /// register + pub const DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x50000930 + /// device endpoint-1 transfer size + /// register + pub const DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000950 + /// device endpoint-2 transfer size + /// register + pub const DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000970 + /// device endpoint-3 transfer size + /// register + pub const DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000918 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x50000938 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x50000958 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x50000978 + /// OTG_FS device IN endpoint transmit FIFO + /// status register + pub const DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// available + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x50000b30 + /// device OUT endpoint-1 transfer size + /// register + pub const DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x50000b50 + /// device OUT endpoint-2 transfer size + /// register + pub const DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x50000b70 + /// device OUT endpoint-3 transfer size + /// register + pub const DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = struct { + pub const base_address = 0x50000e00; + + /// address: 0x50000e00 + /// OTG_FS power and clock gating control + /// register (OTG_FS_PCGCCTL) + pub const FS_PCGCCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY Suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// Controller area network + pub const CAN1 = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + pub const CAN2 = struct { + pub const base_address = 0x40006800; + + /// address: 0x40006800 + /// master control register + pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006804 + /// master status register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006808 + /// transmit status register + pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox + /// 0 + TME0: u1, + /// Lowest priority flag for mailbox + /// 1 + TME1: u1, + /// Lowest priority flag for mailbox + /// 2 + TME2: u1, + /// Lowest priority flag for mailbox + /// 0 + LOW0: u1, + /// Lowest priority flag for mailbox + /// 1 + LOW1: u1, + /// Lowest priority flag for mailbox + /// 2 + LOW2: u1, + }), base_address + 0x8); + + /// address: 0x4000680c + /// receive FIFO 0 register + pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP0 + FMP0: u2, + reserved0: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006810 + /// receive FIFO 1 register + pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { + /// FMP1 + FMP1: u2, + reserved0: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006814 + /// interrupt enable register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved0: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006818 + /// interrupt enable register + pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved0: u1, + /// LEC + LEC: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), base_address + 0x18); + + /// address: 0x4000681c + /// bit timing register + pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { + /// BRP + BRP: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved6: u1, + /// SJW + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), base_address + 0x1c); + + /// address: 0x40006980 + /// TX mailbox identifier register + pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x180); + + /// address: 0x40006984 + /// mailbox data length control and time stamp + /// register + pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x184); + + /// address: 0x40006988 + /// mailbox data low register + pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x188); + + /// address: 0x4000698c + /// mailbox data high register + pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x18c); + + /// address: 0x40006990 + /// mailbox identifier register + pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x190); + + /// address: 0x40006994 + /// mailbox data length control and time stamp + /// register + pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x194); + + /// address: 0x40006998 + /// mailbox data low register + pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x198); + + /// address: 0x4000699c + /// mailbox data high register + pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x19c); + + /// address: 0x400069a0 + /// mailbox identifier register + pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1a0); + + /// address: 0x400069a4 + /// mailbox data length control and time stamp + /// register + pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// TGT + TGT: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// TIME + TIME: u16, + }), base_address + 0x1a4); + + /// address: 0x400069a8 + /// mailbox data low register + pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1a8); + + /// address: 0x400069ac + /// mailbox data high register + pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1ac); + + /// address: 0x400069b0 + /// receive FIFO mailbox identifier + /// register + pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1b0); + + /// address: 0x400069b4 + /// mailbox data high register + pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1b4); + + /// address: 0x400069b8 + /// mailbox data high register + pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1b8); + + /// address: 0x400069bc + /// receive FIFO mailbox data high + /// register + pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1bc); + + /// address: 0x400069c0 + /// mailbox data high register + pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), base_address + 0x1c0); + + /// address: 0x400069c4 + /// mailbox data high register + pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DLC + DLC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), base_address + 0x1c4); + + /// address: 0x400069c8 + /// mailbox data high register + pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), base_address + 0x1c8); + + /// address: 0x400069cc + /// mailbox data high register + pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006a00 + /// filter master register + pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { + /// FINIT + FINIT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// CAN2SB + CAN2SB: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006a04 + /// filter mode register + pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x40006a0c + /// filter scale register + pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006a14 + /// filter FIFO assignment + /// register + pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter FIFO assignment for filter + /// 0 + FFA0: u1, + /// Filter FIFO assignment for filter + /// 1 + FFA1: u1, + /// Filter FIFO assignment for filter + /// 2 + FFA2: u1, + /// Filter FIFO assignment for filter + /// 3 + FFA3: u1, + /// Filter FIFO assignment for filter + /// 4 + FFA4: u1, + /// Filter FIFO assignment for filter + /// 5 + FFA5: u1, + /// Filter FIFO assignment for filter + /// 6 + FFA6: u1, + /// Filter FIFO assignment for filter + /// 7 + FFA7: u1, + /// Filter FIFO assignment for filter + /// 8 + FFA8: u1, + /// Filter FIFO assignment for filter + /// 9 + FFA9: u1, + /// Filter FIFO assignment for filter + /// 10 + FFA10: u1, + /// Filter FIFO assignment for filter + /// 11 + FFA11: u1, + /// Filter FIFO assignment for filter + /// 12 + FFA12: u1, + /// Filter FIFO assignment for filter + /// 13 + FFA13: u1, + /// Filter FIFO assignment for filter + /// 14 + FFA14: u1, + /// Filter FIFO assignment for filter + /// 15 + FFA15: u1, + /// Filter FIFO assignment for filter + /// 16 + FFA16: u1, + /// Filter FIFO assignment for filter + /// 17 + FFA17: u1, + /// Filter FIFO assignment for filter + /// 18 + FFA18: u1, + /// Filter FIFO assignment for filter + /// 19 + FFA19: u1, + /// Filter FIFO assignment for filter + /// 20 + FFA20: u1, + /// Filter FIFO assignment for filter + /// 21 + FFA21: u1, + /// Filter FIFO assignment for filter + /// 22 + FFA22: u1, + /// Filter FIFO assignment for filter + /// 23 + FFA23: u1, + /// Filter FIFO assignment for filter + /// 24 + FFA24: u1, + /// Filter FIFO assignment for filter + /// 25 + FFA25: u1, + /// Filter FIFO assignment for filter + /// 26 + FFA26: u1, + /// Filter FIFO assignment for filter + /// 27 + FFA27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x40006a1c + /// filter activation register + pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006a40 + /// Filter bank 0 register 1 + pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x240); + + /// address: 0x40006a44 + /// Filter bank 0 register 2 + pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x244); + + /// address: 0x40006a48 + /// Filter bank 1 register 1 + pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x248); + + /// address: 0x40006a4c + /// Filter bank 1 register 2 + pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x24c); + + /// address: 0x40006a50 + /// Filter bank 2 register 1 + pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x250); + + /// address: 0x40006a54 + /// Filter bank 2 register 2 + pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x254); + + /// address: 0x40006a58 + /// Filter bank 3 register 1 + pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x258); + + /// address: 0x40006a5c + /// Filter bank 3 register 2 + pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x25c); + + /// address: 0x40006a60 + /// Filter bank 4 register 1 + pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x260); + + /// address: 0x40006a64 + /// Filter bank 4 register 2 + pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x264); + + /// address: 0x40006a68 + /// Filter bank 5 register 1 + pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x268); + + /// address: 0x40006a6c + /// Filter bank 5 register 2 + pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x26c); + + /// address: 0x40006a70 + /// Filter bank 6 register 1 + pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x270); + + /// address: 0x40006a74 + /// Filter bank 6 register 2 + pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x274); + + /// address: 0x40006a78 + /// Filter bank 7 register 1 + pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x278); + + /// address: 0x40006a7c + /// Filter bank 7 register 2 + pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x27c); + + /// address: 0x40006a80 + /// Filter bank 8 register 1 + pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x280); + + /// address: 0x40006a84 + /// Filter bank 8 register 2 + pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x284); + + /// address: 0x40006a88 + /// Filter bank 9 register 1 + pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x288); + + /// address: 0x40006a8c + /// Filter bank 9 register 2 + pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x28c); + + /// address: 0x40006a90 + /// Filter bank 10 register 1 + pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x290); + + /// address: 0x40006a94 + /// Filter bank 10 register 2 + pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x294); + + /// address: 0x40006a98 + /// Filter bank 11 register 1 + pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x298); + + /// address: 0x40006a9c + /// Filter bank 11 register 2 + pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x29c); + + /// address: 0x40006aa0 + /// Filter bank 4 register 1 + pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a0); + + /// address: 0x40006aa4 + /// Filter bank 12 register 2 + pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a4); + + /// address: 0x40006aa8 + /// Filter bank 13 register 1 + pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2a8); + + /// address: 0x40006aac + /// Filter bank 13 register 2 + pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ac); + + /// address: 0x40006ab0 + /// Filter bank 14 register 1 + pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b0); + + /// address: 0x40006ab4 + /// Filter bank 14 register 2 + pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b4); + + /// address: 0x40006ab8 + /// Filter bank 15 register 1 + pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2b8); + + /// address: 0x40006abc + /// Filter bank 15 register 2 + pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2bc); + + /// address: 0x40006ac0 + /// Filter bank 16 register 1 + pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c0); + + /// address: 0x40006ac4 + /// Filter bank 16 register 2 + pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c4); + + /// address: 0x40006ac8 + /// Filter bank 17 register 1 + pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2c8); + + /// address: 0x40006acc + /// Filter bank 17 register 2 + pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2cc); + + /// address: 0x40006ad0 + /// Filter bank 18 register 1 + pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d0); + + /// address: 0x40006ad4 + /// Filter bank 18 register 2 + pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d4); + + /// address: 0x40006ad8 + /// Filter bank 19 register 1 + pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2d8); + + /// address: 0x40006adc + /// Filter bank 19 register 2 + pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2dc); + + /// address: 0x40006ae0 + /// Filter bank 20 register 1 + pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e0); + + /// address: 0x40006ae4 + /// Filter bank 20 register 2 + pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e4); + + /// address: 0x40006ae8 + /// Filter bank 21 register 1 + pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2e8); + + /// address: 0x40006aec + /// Filter bank 21 register 2 + pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2ec); + + /// address: 0x40006af0 + /// Filter bank 22 register 1 + pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f0); + + /// address: 0x40006af4 + /// Filter bank 22 register 2 + pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f4); + + /// address: 0x40006af8 + /// Filter bank 23 register 1 + pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2f8); + + /// address: 0x40006afc + /// Filter bank 23 register 2 + pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006b00 + /// Filter bank 24 register 1 + pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x300); + + /// address: 0x40006b04 + /// Filter bank 24 register 2 + pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x304); + + /// address: 0x40006b08 + /// Filter bank 25 register 1 + pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x308); + + /// address: 0x40006b0c + /// Filter bank 25 register 2 + pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x30c); + + /// address: 0x40006b10 + /// Filter bank 26 register 1 + pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x310); + + /// address: 0x40006b14 + /// Filter bank 26 register 2 + pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x314); + + /// address: 0x40006b18 + /// Filter bank 27 register 1 + pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x318); + + /// address: 0x40006b1c + /// Filter bank 27 register 2 + pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), base_address + 0x31c); + }; + + /// Nested Vectored Interrupt + /// Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set-Enable Register + pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e104 + /// Interrupt Set-Enable Register + pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x4); + + /// address: 0xe000e108 + /// Interrupt Set-Enable Register + pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETENA + SETENA: u32, + }), base_address + 0x8); + + /// address: 0xe000e180 + /// Interrupt Clear-Enable + /// Register + pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e184 + /// Interrupt Clear-Enable + /// Register + pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x84); + + /// address: 0xe000e188 + /// Interrupt Clear-Enable + /// Register + pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRENA + CLRENA: u32, + }), base_address + 0x88); + + /// address: 0xe000e200 + /// Interrupt Set-Pending Register + pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e204 + /// Interrupt Set-Pending Register + pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x104); + + /// address: 0xe000e208 + /// Interrupt Set-Pending Register + pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// SETPEND + SETPEND: u32, + }), base_address + 0x108); + + /// address: 0xe000e280 + /// Interrupt Clear-Pending + /// Register + pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e284 + /// Interrupt Clear-Pending + /// Register + pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x184); + + /// address: 0xe000e288 + /// Interrupt Clear-Pending + /// Register + pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// CLRPEND + CLRPEND: u32, + }), base_address + 0x188); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e304 + /// Interrupt Active Bit Register + pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x204); + + /// address: 0xe000e308 + /// Interrupt Active Bit Register + pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// ACTIVE + ACTIVE: u32, + }), base_address + 0x208); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x300); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x304); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x308); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x30c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x310); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x314); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x318); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x31c); + + /// address: 0xe000e420 + /// Interrupt Priority Register + pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x320); + + /// address: 0xe000e424 + /// Interrupt Priority Register + pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x324); + + /// address: 0xe000e428 + /// Interrupt Priority Register + pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x328); + + /// address: 0xe000e42c + /// Interrupt Priority Register + pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x32c); + + /// address: 0xe000e430 + /// Interrupt Priority Register + pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x330); + + /// address: 0xe000e434 + /// Interrupt Priority Register + pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x334); + + /// address: 0xe000e438 + /// Interrupt Priority Register + pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x338); + + /// address: 0xe000e43c + /// Interrupt Priority Register + pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x33c); + + /// address: 0xe000e440 + /// Interrupt Priority Register + pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x340); + + /// address: 0xe000e444 + /// Interrupt Priority Register + pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x344); + + /// address: 0xe000e448 + /// Interrupt Priority Register + pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x348); + + /// address: 0xe000e44c + /// Interrupt Priority Register + pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x34c); + + /// address: 0xe000e450 + /// Interrupt Priority Register + pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), base_address + 0x350); + }; + + /// FLASH + pub const FLASH = struct { + pub const base_address = 0x40023c00; + + /// address: 0x40023c00 + /// Flash access control register + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Latency + LATENCY: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x40023c04 + /// Flash key register + pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// FPEC key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40023c08 + /// Flash option key register + pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option byte key + OPTKEY: u32, + }), base_address + 0x8); + + /// address: 0x40023c0c + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved0: u1, + reserved1: u1, + /// Write protection error + WRPERR: u1, + /// Programming alignment + /// error + PGAERR: u1, + /// Programming parallelism + /// error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Busy + BSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xc); + + /// address: 0x40023c10 + /// Control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase of sectors 0 to + /// 11 + MER: u1, + /// Sector number + SNB: u5, + /// Program size + PSIZE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Mass Erase of sectors 12 to + /// 23 + MER1: u1, + /// Start + STRT: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// End of operation interrupt + /// enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Lock + LOCK: u1, + }), base_address + 0x10); + + /// address: 0x40023c14 + /// Flash option control register + pub const OPTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved0: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option + /// bytes + nRST_STOP: u1, + /// nRST_STDBY User option + /// bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14); + + /// address: 0x40023c18 + /// Flash option control register + /// 1 + pub const OPTCR1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Not write protect + nWRP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x18); + }; + + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40013c00; + + /// address: 0x40013c00 + /// Interrupt mask register + /// (EXTI_IMR) + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x0); + + /// address: 0x40013c04 + /// Event mask register (EXTI_EMR) + pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x4); + + /// address: 0x40013c08 + /// Rising Trigger selection register + /// (EXTI_RTSR) + pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rising trigger event configuration of + /// line 0 + TR0: u1, + /// Rising trigger event configuration of + /// line 1 + TR1: u1, + /// Rising trigger event configuration of + /// line 2 + TR2: u1, + /// Rising trigger event configuration of + /// line 3 + TR3: u1, + /// Rising trigger event configuration of + /// line 4 + TR4: u1, + /// Rising trigger event configuration of + /// line 5 + TR5: u1, + /// Rising trigger event configuration of + /// line 6 + TR6: u1, + /// Rising trigger event configuration of + /// line 7 + TR7: u1, + /// Rising trigger event configuration of + /// line 8 + TR8: u1, + /// Rising trigger event configuration of + /// line 9 + TR9: u1, + /// Rising trigger event configuration of + /// line 10 + TR10: u1, + /// Rising trigger event configuration of + /// line 11 + TR11: u1, + /// Rising trigger event configuration of + /// line 12 + TR12: u1, + /// Rising trigger event configuration of + /// line 13 + TR13: u1, + /// Rising trigger event configuration of + /// line 14 + TR14: u1, + /// Rising trigger event configuration of + /// line 15 + TR15: u1, + /// Rising trigger event configuration of + /// line 16 + TR16: u1, + /// Rising trigger event configuration of + /// line 17 + TR17: u1, + /// Rising trigger event configuration of + /// line 18 + TR18: u1, + /// Rising trigger event configuration of + /// line 19 + TR19: u1, + /// Rising trigger event configuration of + /// line 20 + TR20: u1, + /// Rising trigger event configuration of + /// line 21 + TR21: u1, + /// Rising trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x40013c0c + /// Falling Trigger selection register + /// (EXTI_FTSR) + pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Falling trigger event configuration of + /// line 0 + TR0: u1, + /// Falling trigger event configuration of + /// line 1 + TR1: u1, + /// Falling trigger event configuration of + /// line 2 + TR2: u1, + /// Falling trigger event configuration of + /// line 3 + TR3: u1, + /// Falling trigger event configuration of + /// line 4 + TR4: u1, + /// Falling trigger event configuration of + /// line 5 + TR5: u1, + /// Falling trigger event configuration of + /// line 6 + TR6: u1, + /// Falling trigger event configuration of + /// line 7 + TR7: u1, + /// Falling trigger event configuration of + /// line 8 + TR8: u1, + /// Falling trigger event configuration of + /// line 9 + TR9: u1, + /// Falling trigger event configuration of + /// line 10 + TR10: u1, + /// Falling trigger event configuration of + /// line 11 + TR11: u1, + /// Falling trigger event configuration of + /// line 12 + TR12: u1, + /// Falling trigger event configuration of + /// line 13 + TR13: u1, + /// Falling trigger event configuration of + /// line 14 + TR14: u1, + /// Falling trigger event configuration of + /// line 15 + TR15: u1, + /// Falling trigger event configuration of + /// line 16 + TR16: u1, + /// Falling trigger event configuration of + /// line 17 + TR17: u1, + /// Falling trigger event configuration of + /// line 18 + TR18: u1, + /// Falling trigger event configuration of + /// line 19 + TR19: u1, + /// Falling trigger event configuration of + /// line 20 + TR20: u1, + /// Falling trigger event configuration of + /// line 21 + TR21: u1, + /// Falling trigger event configuration of + /// line 22 + TR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0xc); + + /// address: 0x40013c10 + /// Software interrupt event register + /// (EXTI_SWIER) + pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Interrupt on line + /// 0 + SWIER0: u1, + /// Software Interrupt on line + /// 1 + SWIER1: u1, + /// Software Interrupt on line + /// 2 + SWIER2: u1, + /// Software Interrupt on line + /// 3 + SWIER3: u1, + /// Software Interrupt on line + /// 4 + SWIER4: u1, + /// Software Interrupt on line + /// 5 + SWIER5: u1, + /// Software Interrupt on line + /// 6 + SWIER6: u1, + /// Software Interrupt on line + /// 7 + SWIER7: u1, + /// Software Interrupt on line + /// 8 + SWIER8: u1, + /// Software Interrupt on line + /// 9 + SWIER9: u1, + /// Software Interrupt on line + /// 10 + SWIER10: u1, + /// Software Interrupt on line + /// 11 + SWIER11: u1, + /// Software Interrupt on line + /// 12 + SWIER12: u1, + /// Software Interrupt on line + /// 13 + SWIER13: u1, + /// Software Interrupt on line + /// 14 + SWIER14: u1, + /// Software Interrupt on line + /// 15 + SWIER15: u1, + /// Software Interrupt on line + /// 16 + SWIER16: u1, + /// Software Interrupt on line + /// 17 + SWIER17: u1, + /// Software Interrupt on line + /// 18 + SWIER18: u1, + /// Software Interrupt on line + /// 19 + SWIER19: u1, + /// Software Interrupt on line + /// 20 + SWIER20: u1, + /// Software Interrupt on line + /// 21 + SWIER21: u1, + /// Software Interrupt on line + /// 22 + SWIER22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x10); + + /// address: 0x40013c14 + /// Pending register (EXTI_PR) + pub const PR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + }; + + /// USB on the go high speed + pub const OTG_HS_GLOBAL = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// OTG_HS control and status + /// register + pub const OTG_HS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40040004 + /// OTG_HS interrupt register + pub const OTG_HS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end detected + SEDET: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRSSCHG: u1, + /// Host negotiation success status + /// change + HNSSCHG: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x40040008 + /// OTG_HS AHB configuration + /// register + pub const OTG_HS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved0: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty + /// level + PTXFELVL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x4004000c + /// OTG_HS USB configuration + /// register + pub const OTG_HS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS timeout calibration + TOCAL: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// USB 2.0 high-speed ULPI PHY or USB 1.1 + /// full-speed serial transceiver select + PHYSEL: u1, + reserved3: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved4: u1, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved5: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS + /// indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing + /// selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect + /// disable + ULPIIPD: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Forced host mode + FHMOD: u1, + /// Forced peripheral mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), base_address + 0xc); + + /// address: 0x40040010 + /// OTG_HS reset register + pub const OTG_HS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// DMA request signal + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, + }), base_address + 0x10); + + /// address: 0x40040014 + /// OTG_HS core interrupt register + pub const OTG_HS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO nonempty + RXFLVL: u1, + /// Nonperiodic TxFIFO empty + NPTXFE: u1, + /// Global IN nonperiodic NAK + /// effective + GINAKEFF: u1, + /// Global OUT NAK effective + BOUTNAKEFF: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOODRP: u1, + /// End of periodic frame + /// interrupt + EOPF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN + /// transfer + IISOIXFR: u1, + /// Incomplete periodic + /// transfer + PXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved4: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved5: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected + /// interrupt + DISCINT: u1, + /// Session request/new session detected + /// interrupt + SRQINT: u1, + /// Resume/remote wakeup detected + /// interrupt + WKUINT: u1, + }), base_address + 0x14); + + /// address: 0x40040018 + /// OTG_HS interrupt mask register + pub const OTG_HS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode mismatch interrupt + /// mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO nonempty mask + RXFLVLM: u1, + /// Nonperiodic TxFIFO empty + /// mask + NPTXFEM: u1, + /// Global nonperiodic IN NAK effective + /// mask + GINAKEFFM: u1, + /// Global OUT NAK effective + /// mask + GONAKEFFM: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt + /// mask + ISOODRPM: u1, + /// End of periodic frame interrupt + /// mask + EOPFM: u1, + reserved3: u1, + /// Endpoint mismatch interrupt + /// mask + EPMISM: u1, + /// IN endpoints interrupt + /// mask + IEPINT: u1, + /// OUT endpoints interrupt + /// mask + OEPINT: u1, + /// Incomplete isochronous IN transfer + /// mask + IISOIXFRM: u1, + /// Incomplete periodic transfer + /// mask + PXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + reserved4: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt + /// mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved5: u1, + /// Connector ID status change + /// mask + CIDSCHGM: u1, + /// Disconnect detected interrupt + /// mask + DISCINT: u1, + /// Session request/new session detected + /// interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt + /// mask + WUIM: u1, + }), base_address + 0x18); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (host mode) + pub const OTG_HS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register (host + /// mode) + pub const OTG_HS_GRXSTSP_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x40040024 + /// OTG_HS Receive FIFO size + /// register + pub const OTG_HS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// RxFIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x40040028 + /// OTG_HS nonperiodic transmit FIFO size + /// register (host mode) + pub const OTG_HS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic transmit RAM start + /// address + NPTXFSA: u16, + /// Nonperiodic TxFIFO depth + NPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x40040028 + /// Endpoint 0 transmit FIFO size (peripheral + /// mode) + pub const OTG_HS_TX0FSIZ_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint 0 transmit RAM start + /// address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), base_address + 0x28); + + /// address: 0x4004002c + /// OTG_HS nonperiodic transmit FIFO/queue + /// status register + pub const OTG_HS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonperiodic TxFIFO space + /// available + NPTXFSAV: u16, + /// Nonperiodic transmit request queue space + /// available + NPTQXSAV: u8, + /// Top of the nonperiodic transmit request + /// queue + NPTXQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x40040038 + /// OTG_HS general core configuration + /// register + pub const OTG_HS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power down + PWRDWN: u1, + /// Enable I2C bus connection for the + /// external I2C PHY interface + I2CPADEN: u1, + /// Enable the VBUS sensing + /// device + VBUSASEN: u1, + /// Enable the VBUS sensing + /// device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable + /// option + NOVBUSSENS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4004003c + /// OTG_HS core ID register + pub const OTG_HS_CID = @intToPtr(*volatile Mmio(32, packed struct { + /// Product ID field + PRODUCT_ID: u32, + }), base_address + 0x3c); + + /// address: 0x40040100 + /// OTG_HS Host periodic transmit FIFO size + /// register + pub const OTG_HS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFD: u16, + }), base_address + 0x100); + + /// address: 0x40040104 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x40040108 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x4004011c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x11c); + + /// address: 0x40040120 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x120); + + /// address: 0x40040124 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x124); + + /// address: 0x40040128 + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF6 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x128); + + /// address: 0x4004012c + /// OTG_HS device IN endpoint transmit FIFO size + /// register + pub const OTG_HS_DIEPTXF7 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFOx transmit RAM start + /// address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), base_address + 0x12c); + + /// address: 0x4004001c + /// OTG_HS Receive status debug read register + /// (peripheral mode mode) + pub const OTG_HS_GRXSTSR_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// OTG_HS status read and pop register + /// (peripheral mode) + pub const OTG_HS_GRXSTSP_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x20); + }; + + /// USB on the go high speed + pub const OTG_HS_HOST = struct { + pub const base_address = 0x40040400; + + /// address: 0x40040400 + /// OTG_HS host configuration + /// register + pub const OTG_HS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40040404 + /// OTG_HS Host frame interval + /// register + pub const OTG_HS_HFIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRIVL: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x40040408 + /// OTG_HS host frame number/frame time + /// remaining register + pub const OTG_HS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), base_address + 0x8); + + /// address: 0x40040410 + /// OTG_HS_Host periodic transmit FIFO/queue + /// status register + pub const OTG_HS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFSAVL: u16, + /// Periodic transmit request queue space + /// available + PTXQSAV: u8, + /// Top of the periodic transmit request + /// queue + PTXQTOP: u8, + }), base_address + 0x10); + + /// address: 0x40040414 + /// OTG_HS Host all channels interrupt + /// register + pub const OTG_HS_HAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupts + HAINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40040418 + /// OTG_HS host all channels interrupt mask + /// register + pub const OTG_HS_HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt mask + HAINTM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40040440 + /// OTG_HS host port control and status + /// register + pub const OTG_HS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved0: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x40040500 + /// OTG_HS host channel-0 characteristics + /// register + pub const OTG_HS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x100); + + /// address: 0x40040520 + /// OTG_HS host channel-1 characteristics + /// register + pub const OTG_HS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x120); + + /// address: 0x40040540 + /// OTG_HS host channel-2 characteristics + /// register + pub const OTG_HS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x140); + + /// address: 0x40040560 + /// OTG_HS host channel-3 characteristics + /// register + pub const OTG_HS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x160); + + /// address: 0x40040580 + /// OTG_HS host channel-4 characteristics + /// register + pub const OTG_HS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x180); + + /// address: 0x400405a0 + /// OTG_HS host channel-5 characteristics + /// register + pub const OTG_HS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400405c0 + /// OTG_HS host channel-6 characteristics + /// register + pub const OTG_HS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400405e0 + /// OTG_HS host channel-7 characteristics + /// register + pub const OTG_HS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040600 + /// OTG_HS host channel-8 characteristics + /// register + pub const OTG_HS_HCCHAR8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x200); + + /// address: 0x40040620 + /// OTG_HS host channel-9 characteristics + /// register + pub const OTG_HS_HCCHAR9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x220); + + /// address: 0x40040640 + /// OTG_HS host channel-10 characteristics + /// register + pub const OTG_HS_HCCHAR10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x240); + + /// address: 0x40040660 + /// OTG_HS host channel-11 characteristics + /// register + pub const OTG_HS_HCCHAR11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count + /// (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), base_address + 0x260); + + /// address: 0x40040504 + /// OTG_HS host channel-0 split control + /// register + pub const OTG_HS_HCSPLT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x104); + + /// address: 0x40040524 + /// OTG_HS host channel-1 split control + /// register + pub const OTG_HS_HCSPLT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x124); + + /// address: 0x40040544 + /// OTG_HS host channel-2 split control + /// register + pub const OTG_HS_HCSPLT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x144); + + /// address: 0x40040564 + /// OTG_HS host channel-3 split control + /// register + pub const OTG_HS_HCSPLT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x164); + + /// address: 0x40040584 + /// OTG_HS host channel-4 split control + /// register + pub const OTG_HS_HCSPLT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x184); + + /// address: 0x400405a4 + /// OTG_HS host channel-5 split control + /// register + pub const OTG_HS_HCSPLT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1a4); + + /// address: 0x400405c4 + /// OTG_HS host channel-6 split control + /// register + pub const OTG_HS_HCSPLT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1c4); + + /// address: 0x400405e4 + /// OTG_HS host channel-7 split control + /// register + pub const OTG_HS_HCSPLT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x1e4); + + /// address: 0x40040604 + /// OTG_HS host channel-8 split control + /// register + pub const OTG_HS_HCSPLT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x204); + + /// address: 0x40040624 + /// OTG_HS host channel-9 split control + /// register + pub const OTG_HS_HCSPLT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x224); + + /// address: 0x40040644 + /// OTG_HS host channel-10 split control + /// register + pub const OTG_HS_HCSPLT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x244); + + /// address: 0x40040664 + /// OTG_HS host channel-11 split control + /// register + pub const OTG_HS_HCSPLT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Split enable + SPLITEN: u1, + }), base_address + 0x264); + + /// address: 0x40040508 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x40040528 + /// OTG_HS host channel-1 interrupt + /// register + pub const OTG_HS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x40040548 + /// OTG_HS host channel-2 interrupt + /// register + pub const OTG_HS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x40040568 + /// OTG_HS host channel-3 interrupt + /// register + pub const OTG_HS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x40040588 + /// OTG_HS host channel-4 interrupt + /// register + pub const OTG_HS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x400405a8 + /// OTG_HS host channel-5 interrupt + /// register + pub const OTG_HS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x400405c8 + /// OTG_HS host channel-6 interrupt + /// register + pub const OTG_HS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x400405e8 + /// OTG_HS host channel-7 interrupt + /// register + pub const OTG_HS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x40040608 + /// OTG_HS host channel-8 interrupt + /// register + pub const OTG_HS_HCINT8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x208); + + /// address: 0x40040628 + /// OTG_HS host channel-9 interrupt + /// register + pub const OTG_HS_HCINT9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x228); + + /// address: 0x40040648 + /// OTG_HS host channel-10 interrupt + /// register + pub const OTG_HS_HCINT10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x248); + + /// address: 0x40040668 + /// OTG_HS host channel-11 interrupt + /// register + pub const OTG_HS_HCINT11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + /// Response received + /// interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x268); + + /// address: 0x4004050c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x4004052c + /// OTG_HS host channel-1 interrupt mask + /// register + pub const OTG_HS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x4004054c + /// OTG_HS host channel-2 interrupt mask + /// register + pub const OTG_HS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x4004056c + /// OTG_HS host channel-3 interrupt mask + /// register + pub const OTG_HS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x4004058c + /// OTG_HS host channel-4 interrupt mask + /// register + pub const OTG_HS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x400405ac + /// OTG_HS host channel-5 interrupt mask + /// register + pub const OTG_HS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x400405cc + /// OTG_HS host channel-6 interrupt mask + /// register + pub const OTG_HS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x400405ec + /// OTG_HS host channel-7 interrupt mask + /// register + pub const OTG_HS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x4004060c + /// OTG_HS host channel-8 interrupt mask + /// register + pub const OTG_HS_HCINTMSK8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x20c); + + /// address: 0x4004062c + /// OTG_HS host channel-9 interrupt mask + /// register + pub const OTG_HS_HCINTMSK9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x22c); + + /// address: 0x4004064c + /// OTG_HS host channel-10 interrupt mask + /// register + pub const OTG_HS_HCINTMSK10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x24c); + + /// address: 0x4004066c + /// OTG_HS host channel-11 interrupt mask + /// register + pub const OTG_HS_HCINTMSK11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + /// mask + STALLM: u1, + /// NAK response received interrupt + /// mask + NAKM: u1, + /// ACK response received/transmitted + /// interrupt mask + ACKM: u1, + /// response received interrupt + /// mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x26c); + + /// address: 0x40040510 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x40040530 + /// OTG_HS host channel-1 transfer size + /// register + pub const OTG_HS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040550 + /// OTG_HS host channel-2 transfer size + /// register + pub const OTG_HS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040570 + /// OTG_HS host channel-3 transfer size + /// register + pub const OTG_HS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040590 + /// OTG_HS host channel-4 transfer size + /// register + pub const OTG_HS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400405b0 + /// OTG_HS host channel-5 transfer size + /// register + pub const OTG_HS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x400405d0 + /// OTG_HS host channel-6 transfer size + /// register + pub const OTG_HS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x400405f0 + /// OTG_HS host channel-7 transfer size + /// register + pub const OTG_HS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + + /// address: 0x40040610 + /// OTG_HS host channel-8 transfer size + /// register + pub const OTG_HS_HCTSIZ8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x210); + + /// address: 0x40040630 + /// OTG_HS host channel-9 transfer size + /// register + pub const OTG_HS_HCTSIZ9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x230); + + /// address: 0x40040650 + /// OTG_HS host channel-10 transfer size + /// register + pub const OTG_HS_HCTSIZ10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x250); + + /// address: 0x40040670 + /// OTG_HS host channel-11 transfer size + /// register + pub const OTG_HS_HCTSIZ11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x270); + + /// address: 0x40040514 + /// OTG_HS host channel-0 DMA address + /// register + pub const OTG_HS_HCDMA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040534 + /// OTG_HS host channel-1 DMA address + /// register + pub const OTG_HS_HCDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040554 + /// OTG_HS host channel-2 DMA address + /// register + pub const OTG_HS_HCDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040574 + /// OTG_HS host channel-3 DMA address + /// register + pub const OTG_HS_HCDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040594 + /// OTG_HS host channel-4 DMA address + /// register + pub const OTG_HS_HCDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x400405b4 + /// OTG_HS host channel-5 DMA address + /// register + pub const OTG_HS_HCDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1b4); + + /// address: 0x400405d4 + /// OTG_HS host channel-6 DMA address + /// register + pub const OTG_HS_HCDMA6 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1d4); + + /// address: 0x400405f4 + /// OTG_HS host channel-7 DMA address + /// register + pub const OTG_HS_HCDMA7 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x1f4); + + /// address: 0x40040614 + /// OTG_HS host channel-8 DMA address + /// register + pub const OTG_HS_HCDMA8 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x214); + + /// address: 0x40040634 + /// OTG_HS host channel-9 DMA address + /// register + pub const OTG_HS_HCDMA9 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x234); + + /// address: 0x40040654 + /// OTG_HS host channel-10 DMA address + /// register + pub const OTG_HS_HCDMA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x254); + + /// address: 0x40040674 + /// OTG_HS host channel-11 DMA address + /// register + pub const OTG_HS_HCDMA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x274); + }; + + /// USB on the go high speed + pub const OTG_HS_DEVICE = struct { + pub const base_address = 0x40040800; + + /// address: 0x40040800 + /// OTG_HS device configuration + /// register + pub const OTG_HS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DSPD: u2, + /// Nonzero-length status OUT + /// handshake + NZLSOHSK: u1, + reserved0: u1, + /// Device address + DAD: u7, + /// Periodic (micro)frame + /// interval + PFIVL: u2, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Periodic scheduling + /// interval + PERSCHIVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40040804 + /// OTG_HS device control register + pub const OTG_HS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40040808 + /// OTG_HS device status register + pub const OTG_HS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Frame number of the received + /// SOF + FNSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x40040810 + /// OTG_HS device IN endpoint common interrupt + /// mask register + pub const OTG_HS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x10); + + /// address: 0x40040814 + /// OTG_HS device OUT endpoint common interrupt + /// mask register + pub const OTG_HS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint + /// disabled mask + OTEPDM: u1, + reserved1: u1, + /// Back-to-back SETUP packets received + /// mask + B2BSTUP: u1, + reserved2: u1, + /// OUT packet error mask + OPEM: u1, + /// BNA interrupt mask + BOIM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0x40040818 + /// OTG_HS device all endpoints interrupt + /// register + pub const OTG_HS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt + /// bits + OEPINT: u16, + }), base_address + 0x18); + + /// address: 0x4004081c + /// OTG_HS all endpoints interrupt mask + /// register + pub const OTG_HS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, + }), base_address + 0x1c); + + /// address: 0x40040828 + /// OTG_HS device VBUS discharge time + /// register + pub const OTG_HS_DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS discharge time + VBUSDT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4004082c + /// OTG_HS device VBUS pulsing time + /// register + pub const OTG_HS_DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { + /// Device VBUS pulsing time + DVBUSP: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x2c); + + /// address: 0x40040830 + /// OTG_HS Device threshold control + /// register + pub const OTG_HS_DTHRCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Nonisochronous IN endpoints threshold + /// enable + NONISOTHREN: u1, + /// ISO IN endpoint threshold + /// enable + ISOTHREN: u1, + /// Transmit threshold length + TXTHRLEN: u9, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Receive threshold enable + RXTHREN: u1, + /// Receive threshold length + RXTHRLEN: u9, + reserved5: u1, + /// Arbiter parking enable + ARPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x30); + + /// address: 0x40040834 + /// OTG_HS device IN endpoint FIFO empty + /// interrupt mask register + pub const OTG_HS_DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt mask + /// bits + INEPTXFEM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40040838 + /// OTG_HS device each endpoint interrupt + /// register + pub const OTG_HS_DEACHINT = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN endpoint 1interrupt bit + IEP1INT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT endpoint 1 interrupt + /// bit + OEP1INT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x38); + + /// address: 0x4004083c + /// OTG_HS device each endpoint interrupt + /// register mask + pub const OTG_HS_DEACHINTMSK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// IN Endpoint 1 interrupt mask + /// bit + IEP1INTM: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// OUT Endpoint 1 interrupt mask + /// bit + OEP1INTM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x3c); + + /// address: 0x40040840 + /// OTG_HS device each in endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask (nonisochronous + /// endpoints) + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// NAK interrupt mask + NAKM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x40040880 + /// OTG_HS device each OUT endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt + /// mask + XFRCM: u1, + /// Endpoint disabled interrupt + /// mask + EPDM: u1, + reserved0: u1, + /// Timeout condition mask + TOM: u1, + /// IN token received when TxFIFO empty + /// mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch + /// mask + INEPNMM: u1, + /// IN endpoint NAK effective + /// mask + INEPNEM: u1, + reserved1: u1, + /// OUT packet error mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved2: u1, + reserved3: u1, + /// Bubble error interrupt + /// mask + BERRM: u1, + /// NAK interrupt mask + NAKM: u1, + /// NYET interrupt mask + NYETM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40040900 + /// OTG device endpoint-0 control + /// register + pub const OTG_HS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x100); + + /// address: 0x40040920 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x120); + + /// address: 0x40040940 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x140); + + /// address: 0x40040960 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x160); + + /// address: 0x40040980 + /// OTG device endpoint-4 control + /// register + pub const OTG_HS_DIEPCTL4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x180); + + /// address: 0x400409a0 + /// OTG device endpoint-5 control + /// register + pub const OTG_HS_DIEPCTL5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1a0); + + /// address: 0x400409c0 + /// OTG device endpoint-6 control + /// register + pub const OTG_HS_DIEPCTL6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1c0); + + /// address: 0x400409e0 + /// OTG device endpoint-7 control + /// register + pub const OTG_HS_DIEPCTL7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved4: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x1e0); + + /// address: 0x40040908 + /// OTG device endpoint-0 interrupt + /// register + pub const OTG_HS_DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x108); + + /// address: 0x40040928 + /// OTG device endpoint-1 interrupt + /// register + pub const OTG_HS_DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x128); + + /// address: 0x40040948 + /// OTG device endpoint-2 interrupt + /// register + pub const OTG_HS_DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x148); + + /// address: 0x40040968 + /// OTG device endpoint-3 interrupt + /// register + pub const OTG_HS_DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x168); + + /// address: 0x40040988 + /// OTG device endpoint-4 interrupt + /// register + pub const OTG_HS_DIEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x188); + + /// address: 0x400409a8 + /// OTG device endpoint-5 interrupt + /// register + pub const OTG_HS_DIEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1a8); + + /// address: 0x400409c8 + /// OTG device endpoint-6 interrupt + /// register + pub const OTG_HS_DIEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1c8); + + /// address: 0x400409e8 + /// OTG device endpoint-7 interrupt + /// register + pub const OTG_HS_DIEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is + /// empty + ITTXFE: u1, + reserved1: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available + /// interrupt + BNA: u1, + reserved2: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x1e8); + + /// address: 0x40040910 + /// OTG_HS device IN endpoint 0 transfer size + /// register + pub const OTG_HS_DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x40040914 + /// OTG_HS device endpoint-1 DMA address + /// register + pub const OTG_HS_DIEPDMA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x114); + + /// address: 0x40040934 + /// OTG_HS device endpoint-2 DMA address + /// register + pub const OTG_HS_DIEPDMA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x134); + + /// address: 0x40040954 + /// OTG_HS device endpoint-3 DMA address + /// register + pub const OTG_HS_DIEPDMA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x154); + + /// address: 0x40040974 + /// OTG_HS device endpoint-4 DMA address + /// register + pub const OTG_HS_DIEPDMA4 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x174); + + /// address: 0x40040994 + /// OTG_HS device endpoint-5 DMA address + /// register + pub const OTG_HS_DIEPDMA5 = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA address + DMAADDR: u32, + }), base_address + 0x194); + + /// address: 0x40040918 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x40040938 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x40040958 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x40040978 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + + /// address: 0x40040998 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS4 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x198); + + /// address: 0x400409b8 + /// OTG_HS device IN endpoint transmit FIFO + /// status register + pub const OTG_HS_DTXFSTS5 = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// avail + INEPTFSAV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1b8); + + /// address: 0x40040930 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x40040950 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x40040970 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x40040990 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x400409b0 + /// OTG_HS device endpoint transfer size + /// register + pub const OTG_HS_DIEPTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x40040b00 + /// OTG_HS device control OUT endpoint 0 control + /// register + pub const OTG_HS_DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// USB active endpoint + USBAEP: u1, + reserved13: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x300); + + /// address: 0x40040b20 + /// OTG device endpoint-1 control + /// register + pub const OTG_HS_DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x320); + + /// address: 0x40040b40 + /// OTG device endpoint-2 control + /// register + pub const OTG_HS_DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x340); + + /// address: 0x40040b60 + /// OTG device endpoint-3 control + /// register + pub const OTG_HS_DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPSIZ: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data + /// PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even + /// frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), base_address + 0x360); + + /// address: 0x40040b08 + /// OTG_HS device endpoint-0 interrupt + /// register + pub const OTG_HS_DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x308); + + /// address: 0x40040b28 + /// OTG_HS device endpoint-1 interrupt + /// register + pub const OTG_HS_DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x328); + + /// address: 0x40040b48 + /// OTG_HS device endpoint-2 interrupt + /// register + pub const OTG_HS_DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x348); + + /// address: 0x40040b68 + /// OTG_HS device endpoint-3 interrupt + /// register + pub const OTG_HS_DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x368); + + /// address: 0x40040b88 + /// OTG_HS device endpoint-4 interrupt + /// register + pub const OTG_HS_DOEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x388); + + /// address: 0x40040ba8 + /// OTG_HS device endpoint-5 interrupt + /// register + pub const OTG_HS_DOEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3a8); + + /// address: 0x40040bc8 + /// OTG_HS device endpoint-6 interrupt + /// register + pub const OTG_HS_DOEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3c8); + + /// address: 0x40040be8 + /// OTG_HS device endpoint-7 interrupt + /// register + pub const OTG_HS_DOEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed + /// interrupt + XFRC: u1, + /// Endpoint disabled + /// interrupt + EPDISD: u1, + reserved0: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint + /// disabled + OTEPDIS: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// received + B2BSTUP: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// NYET interrupt + NYET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3e8); + + /// address: 0x40040b10 + /// OTG_HS device endpoint-1 transfer size + /// register + pub const OTG_HS_DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PKTCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STUPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x40040b30 + /// OTG_HS device endpoint-2 transfer size + /// register + pub const OTG_HS_DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x40040b50 + /// OTG_HS device endpoint-3 transfer size + /// register + pub const OTG_HS_DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x40040b70 + /// OTG_HS device endpoint-4 transfer size + /// register + pub const OTG_HS_DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x370); + + /// address: 0x40040b90 + /// OTG_HS device endpoint-5 transfer size + /// register + pub const OTG_HS_DOEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet + /// count + RXDPID_STUPCNT: u2, + padding0: u1, + }), base_address + 0x390); + }; + + /// USB on the go high speed + pub const OTG_HS_PWRCLK = struct { + pub const base_address = 0x40040e00; + + /// address: 0x40040e00 + /// Power and clock gating control + /// register + pub const OTG_HS_PCGCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved0: u1, + reserved1: u1, + /// PHY suspended + PHYSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + }; + + /// LCD-TFT Controller + pub const LTDC = struct { + pub const base_address = 0x40016800; + + /// address: 0x40016808 + /// Synchronization Size Configuration + /// Register + pub const SSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Synchronization Height (in + /// units of horizontal scan line) + VSH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Horizontal Synchronization Width (in + /// units of pixel clock period) + HSW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4001680c + /// Back Porch Configuration + /// Register + pub const BPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Vertical back porch (in + /// units of horizontal scan line) + AVBP: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Accumulated Horizontal back porch (in + /// units of pixel clock period) + AHBP: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x40016810 + /// Active Width Configuration + /// Register + pub const AWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Accumulated Active Height (in units of + /// horizontal scan line) + AAH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// AAV + AAV: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x10); + + /// address: 0x40016814 + /// Total Width Configuration + /// Register + pub const TWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Total Height (in units of horizontal + /// scan line) + TOTALH: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Total Width (in units of pixel clock + /// period) + TOTALW: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x40016818 + /// Global Control Register + pub const GCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LCD-TFT controller enable + /// bit + LTDCEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Dither Blue Width + DBW: u3, + reserved3: u1, + /// Dither Green Width + DGW: u3, + reserved4: u1, + /// Dither Red Width + DRW: u3, + reserved5: u1, + /// Dither Enable + DEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + /// Pixel Clock Polarity + PCPOL: u1, + /// Data Enable Polarity + DEPOL: u1, + /// Vertical Synchronization + /// Polarity + VSPOL: u1, + /// Horizontal Synchronization + /// Polarity + HSPOL: u1, + }), base_address + 0x18); + + /// address: 0x40016824 + /// Shadow Reload Configuration + /// Register + pub const SRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Immediate Reload + IMR: u1, + /// Vertical Blanking Reload + VBR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x24); + + /// address: 0x4001682c + /// Background Color Configuration + /// Register + pub const BCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Background Color Red value + BC: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40016834 + /// Interrupt Enable Register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt + /// Enable + FUIE: u1, + /// Transfer Error Interrupt + /// Enable + TERRIE: u1, + /// Register Reload interrupt + /// enable + RRIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x34); + + /// address: 0x40016838 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt + /// flag + FUIF: u1, + /// Transfer Error interrupt + /// flag + TERRIF: u1, + /// Register Reload Interrupt + /// Flag + RRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x38); + + /// address: 0x4001683c + /// Interrupt Clear Register + pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clears the Line Interrupt + /// Flag + CLIF: u1, + /// Clears the FIFO Underrun Interrupt + /// flag + CFUIF: u1, + /// Clears the Transfer Error Interrupt + /// Flag + CTERRIF: u1, + /// Clears Register Reload Interrupt + /// Flag + CRRIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x3c); + + /// address: 0x40016840 + /// Line Interrupt Position Configuration + /// Register + pub const LIPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Interrupt Position + LIPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x40); + + /// address: 0x40016844 + /// Current Position Status + /// Register + pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, + }), base_address + 0x44); + + /// address: 0x40016848 + /// Current Display Status + /// Register + pub const CDSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Vertical Data Enable display + /// Status + VDES: u1, + /// Horizontal Data Enable display + /// Status + HDES: u1, + /// Vertical Synchronization display + /// Status + VSYNCS: u1, + /// Horizontal Synchronization display + /// Status + HSYNCS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x48); + + /// address: 0x40016884 + /// Layerx Control Register + pub const L1CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x84); + + /// address: 0x40016888 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L1WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x88); + + /// address: 0x4001688c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L1WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x8c); + + /// address: 0x40016890 + /// Layerx Color Keying Configuration + /// Register + pub const L1CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x90); + + /// address: 0x40016894 + /// Layerx Pixel Format Configuration + /// Register + pub const L1PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x94); + + /// address: 0x40016898 + /// Layerx Constant Alpha Configuration + /// Register + pub const L1CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x98); + + /// address: 0x4001689c + /// Layerx Default Color Configuration + /// Register + pub const L1DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x9c); + + /// address: 0x400168a0 + /// Layerx Blending Factors Configuration + /// Register + pub const L1BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xa0); + + /// address: 0x400168ac + /// Layerx Color Frame Buffer Address + /// Register + pub const L1CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0xac); + + /// address: 0x400168b0 + /// Layerx Color Frame Buffer Length + /// Register + pub const L1CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0xb0); + + /// address: 0x400168b4 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L1CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xb4); + + /// address: 0x400168c4 + /// Layerx CLUT Write Register + pub const L1CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0xc4); + + /// address: 0x40016904 + /// Layerx Control Register + pub const L2CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x104); + + /// address: 0x40016908 + /// Layerx Window Horizontal Position + /// Configuration Register + pub const L2WHPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Horizontal Start + /// Position + WHSTPOS: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Window Horizontal Stop + /// Position + WHSPPOS: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x108); + + /// address: 0x4001690c + /// Layerx Window Vertical Position + /// Configuration Register + pub const L2WVPCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Window Vertical Start + /// Position + WVSTPOS: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window Vertical Stop + /// Position + WVSPPOS: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10c); + + /// address: 0x40016910 + /// Layerx Color Keying Configuration + /// Register + pub const L2CKCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u7, + /// Color Key Red value + CKRED: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x110); + + /// address: 0x40016914 + /// Layerx Pixel Format Configuration + /// Register + pub const L2PFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Pixel Format + PF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x114); + + /// address: 0x40016918 + /// Layerx Constant Alpha Configuration + /// Register + pub const L2CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Constant Alpha + CONSTA: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x118); + + /// address: 0x4001691c + /// Layerx Default Color Configuration + /// Register + pub const L2DCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), base_address + 0x11c); + + /// address: 0x40016920 + /// Layerx Blending Factors Configuration + /// Register + pub const L2BFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blending Factor 2 + BF2: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Blending Factor 1 + BF1: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x120); + + /// address: 0x4001692c + /// Layerx Color Frame Buffer Address + /// Register + pub const L2CFBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Start + /// Address + CFBADD: u32, + }), base_address + 0x12c); + + /// address: 0x40016930 + /// Layerx Color Frame Buffer Length + /// Register + pub const L2CFBLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color Frame Buffer Line + /// Length + CFBLL: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Color Frame Buffer Pitch in + /// bytes + CFBP: u13, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x130); + + /// address: 0x40016934 + /// Layerx ColorFrame Buffer Line Number + /// Register + pub const L2CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x134); + + /// address: 0x40016944 + /// Layerx CLUT Write Register + pub const L2CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), base_address + 0x144); + }; + + /// Serial audio interface + pub const SAI = struct { + pub const base_address = 0x40015800; + + /// address: 0x40015824 + /// BConfiguration register 1 + pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved1: u1, + reserved2: u1, + /// Audio block B enable + SAIBEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40015828 + /// BConfiguration register 2 + pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4001582c + /// BFRCR + pub const BFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + + /// address: 0x40015830 + /// BSlot register + pub const BSLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x30); + + /// address: 0x40015834 + /// BInterrupt mask register2 + pub const BIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDET: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFG: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDETIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x34); + + /// address: 0x40015838 + /// BStatus register + pub const BSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration + /// flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLVL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x38); + + /// address: 0x4001583c + /// BClear flag register + pub const BCLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration + /// flag + WCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x3c); + + /// address: 0x40015840 + /// BData register + pub const BDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x40); + + /// address: 0x40015804 + /// AConfiguration register 1 + pub const ACR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved0: u1, + /// Data size + DS: u3, + /// Least significant bit + /// first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved1: u1, + reserved2: u1, + /// Audio block A enable + SAIAEN: u1, + /// DMA enable + DMAEN: u1, + reserved3: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40015808 + /// AConfiguration register 2 + pub const ACR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data + /// line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001580c + /// AFRCR + pub const AFRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame length + FRL: u8, + /// Frame synchronization active level + /// length + FSALL: u7, + reserved0: u1, + /// Frame synchronization + /// definition + FSDEF: u1, + /// Frame synchronization + /// polarity + FSPOL: u1, + /// Frame synchronization + /// offset + FSOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40015810 + /// ASlot register + pub const ASLOTR = @intToPtr(*volatile Mmio(32, packed struct { + /// First bit offset + FBOFF: u5, + reserved0: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio + /// frame + NBSLOT: u4, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Slot enable + SLOTEN: u16, + }), base_address + 0x10); + + /// address: 0x40015814 + /// AInterrupt mask register2 + pub const AIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun/underrun interrupt + /// enable + OVRUDRIE: u1, + /// Mute detection interrupt + /// enable + MUTEDET: u1, + /// Wrong clock configuration interrupt + /// enable + WCKCFG: u1, + /// FIFO request interrupt + /// enable + FREQIE: u1, + /// Codec not ready interrupt + /// enable + CNRDYIE: u1, + /// Anticipated frame synchronization + /// detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection + /// interrupt enable + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x40015818 + /// AStatus register + pub const ASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag. This bit + /// is read only. + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization + /// detection + AFSDET: u1, + /// Late frame synchronization + /// detection + LFSDET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// FIFO level threshold + FLVL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x18); + + /// address: 0x4001581c + /// AClear flag register + pub const ACLRFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration + /// flag + WCKCFG: u1, + reserved0: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization + /// detection flag. + CAFSDET: u1, + /// Clear late frame synchronization + /// detection flag + LFSDET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x1c); + + /// address: 0x40015820 + /// AData register + pub const ADR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x20); + }; + + /// DMA2D controller + pub const DMA2D = struct { + pub const base_address = 0x4002b000; + + /// address: 0x4002b000 + /// control register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Start + START: u1, + /// Suspend + SUSP: u1, + /// Abort + ABORT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Transfer error interrupt + /// enable + TEIE: u1, + /// Transfer complete interrupt + /// enable + TCIE: u1, + /// Transfer watermark interrupt + /// enable + TWIE: u1, + /// CLUT access error interrupt + /// enable + CAEIE: u1, + /// CLUT transfer complete interrupt + /// enable + CTCIE: u1, + /// Configuration Error Interrupt + /// Enable + CEIE: u1, + reserved5: u1, + reserved6: u1, + /// DMA2D mode + MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x0); + + /// address: 0x4002b004 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer error interrupt + /// flag + TEIF: u1, + /// Transfer complete interrupt + /// flag + TCIF: u1, + /// Transfer watermark interrupt + /// flag + TWIF: u1, + /// CLUT access error interrupt + /// flag + CAEIF: u1, + /// CLUT transfer complete interrupt + /// flag + CTCIF: u1, + /// Configuration error interrupt + /// flag + CEIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x4); + + /// address: 0x4002b008 + /// interrupt flag clear register + pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear Transfer error interrupt + /// flag + CTEIF: u1, + /// Clear transfer complete interrupt + /// flag + CTCIF: u1, + /// Clear transfer watermark interrupt + /// flag + CTWIF: u1, + /// Clear CLUT access error interrupt + /// flag + CAECIF: u1, + /// Clear CLUT transfer complete interrupt + /// flag + CCTCIF: u1, + /// Clear configuration error interrupt + /// flag + CCEIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x8); + + /// address: 0x4002b00c + /// foreground memory address + /// register + pub const FGMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0xc); + + /// address: 0x4002b010 + /// foreground offset register + pub const FGOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x10); + + /// address: 0x4002b014 + /// background memory address + /// register + pub const BGMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0x14); + + /// address: 0x4002b018 + /// background offset register + pub const BGOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x18); + + /// address: 0x4002b01c + /// foreground PFC control + /// register + pub const FGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u4, + /// CLUT color mode + CCM: u1, + /// Start + START: u1, + reserved0: u1, + reserved1: u1, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Alpha value + ALPHA: u8, + }), base_address + 0x1c); + + /// address: 0x4002b020 + /// foreground color register + pub const FGCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x4002b024 + /// background PFC control + /// register + pub const BGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u4, + /// CLUT Color mode + CCM: u1, + /// Start + START: u1, + reserved0: u1, + reserved1: u1, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Alpha value + ALPHA: u8, + }), base_address + 0x24); + + /// address: 0x4002b028 + /// background color register + pub const BGCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x28); + + /// address: 0x4002b02c + /// foreground CLUT memory address + /// register + pub const FGCMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory Address + MA: u32, + }), base_address + 0x2c); + + /// address: 0x4002b030 + /// background CLUT memory address + /// register + pub const BGCMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory address + MA: u32, + }), base_address + 0x30); + + /// address: 0x4002b034 + /// output PFC control register + pub const OPFCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Color mode + CM: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x34); + + /// address: 0x4002b038 + /// output color register + pub const OCOLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + /// Alpha Channel Value + APLHA: u8, + }), base_address + 0x38); + + /// address: 0x4002b03c + /// output memory address register + pub const OMAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory Address + MA: u32, + }), base_address + 0x3c); + + /// address: 0x4002b040 + /// output offset register + pub const OOR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line Offset + LO: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x40); + + /// address: 0x4002b044 + /// number of line register + pub const NLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of lines + NL: u16, + /// Pixel per lines + PL: u14, + padding0: u1, + padding1: u1, + }), base_address + 0x44); + + /// address: 0x4002b048 + /// line watermark register + pub const LWR = @intToPtr(*volatile Mmio(32, packed struct { + /// Line watermark + LW: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002b04c + /// AHB master timer configuration + /// register + pub const AMTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable + EN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Dead Time + DT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4c); + + /// address: 0x4002b400 + /// FGCLUT + pub const FGCLUT = @intToPtr(*volatile Mmio(32, packed struct { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), base_address + 0x400); + + /// address: 0x4002b800 + /// BGCLUT + pub const BGCLUT = @intToPtr(*volatile Mmio(32, packed struct { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), base_address + 0x800); + }; + + /// Inter-integrated circuit + pub const I2C3 = struct { + pub const base_address = 0x40005c00; + + /// address: 0x40005c00 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005c04 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005c08 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40005c0c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005c10 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005c14 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005c18 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x40005c1c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005c20 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005c24 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + pub const I2C2 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005814 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005824 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + pub const I2C1 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 1 + pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved0: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave + /// mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data + /// reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved1: u1, + /// Software reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 2 + pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral clock frequency + FREQ: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Own address register 1 + pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Addressing mode (slave + /// mode) + ADDMODE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Own address register 2 + pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Dual addressing mode + /// enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Data register + pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0x40005414 + /// Status register 1 + pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched + /// (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master + /// mode) + ADD10: u1, + /// Stop detection (slave + /// mode) + STOPF: u1, + reserved0: u1, + /// Data register not empty + /// (receivers) + RxNE: u1, + /// Data register empty + /// (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master + /// mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved1: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Status register 2 + pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved0: u1, + /// General call address (Slave + /// mode) + GENCALL: u1, + /// SMBus device default address (Slave + /// mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave + /// mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking + /// register + PEC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock control register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock control register in Fast/Standard + /// mode (Master mode) + CCR: u12, + reserved0: u1, + reserved1: u1, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// TRISE register + pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); + + /// address: 0x40005424 + /// I2C FLTR register + pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + }; + + /// Floting point unit + pub const FPU = struct { + pub const base_address = 0xe000ef34; + + /// address: 0xe000ef34 + /// Floating-point context control + /// register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved0: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved1: u1, + /// MONRDY + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), base_address + 0x0); + + /// address: 0xe000ef38 + /// Floating-point context address + /// register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Location of unpopulated + /// floating-point + ADDRESS: u29, + }), base_address + 0x4); + + /// address: 0xe000ef3c + /// Floating-point status control + /// register + pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Invalid operation cumulative exception + /// bit + IOC: u1, + /// Division by zero cumulative exception + /// bit. + DZC: u1, + /// Overflow cumulative exception + /// bit + OFC: u1, + /// Underflow cumulative exception + /// bit + UFC: u1, + /// Inexact cumulative exception + /// bit + IXC: u1, + reserved0: u1, + reserved1: u1, + /// Input denormal cumulative exception + /// bit. + IDC: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Rounding Mode control + /// field + RMode: u2, + /// Flush-to-zero mode control + /// bit: + FZ: u1, + /// Default NaN mode control + /// bit + DN: u1, + /// Alternative half-precision control + /// bit + AHP: u1, + reserved16: u1, + /// Overflow condition code + /// flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code + /// flag + N: u1, + }), base_address + 0x8); + }; + + /// Memory protection unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU type register + pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { + /// Separate flag + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction + /// regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU control register + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard + /// fault + HFNMIENA: u1, + /// Enable priviliged software access to + /// default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU region number register + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU region base address + /// register + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU region attribute and size + /// register + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection + /// region + SIZE: u5, + reserved0: u1, + reserved1: u1, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved2: u1, + reserved3: u1, + /// Access permission + AP: u3, + reserved4: u1, + /// Instruction access disable + /// bit + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + }; + + /// SysTick timer + pub const STK = struct { + pub const base_address = 0xe000e010; + + /// address: 0xe000e010 + /// SysTick control and status + /// register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Counter enable + ENABLE: u1, + /// SysTick exception request + /// enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// COUNTFLAG + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0xe000e014 + /// SysTick reload value register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + /// RELOAD value + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0xe000e018 + /// SysTick current value register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Current counter value + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0xe000e01c + /// SysTick calibration value + /// register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + /// Calibration value + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// SKEW flag: Indicates whether the TENMS + /// value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), base_address + 0xc); + }; + + /// System control block + pub const SCB = struct { + pub const base_address = 0xe000ed00; + + /// address: 0xe000ed00 + /// CPUID base register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Revision number + Revision: u4, + /// Part number of the + /// processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), base_address + 0x0); + + /// address: 0xe000ed04 + /// Interrupt control and state + /// register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active vector + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt pending flag + ISRPENDING: u1, + reserved5: u1, + reserved6: u1, + /// SysTick exception clear-pending + /// bit + PENDSTCLR: u1, + /// SysTick exception set-pending + /// bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), base_address + 0x4); + + /// address: 0xe000ed08 + /// Vector table offset register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Vector table base offset + /// field + TBLOFF: u21, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0xe000ed0c + /// Application interrupt and reset control + /// register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PRIGROUP + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), base_address + 0xc); + + /// address: 0xe000ed10 + /// System control register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x10); + + /// address: 0xe000ed14 + /// Configuration and control + /// register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Configures how the processor enters + /// Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved0: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x14); + + /// address: 0xe000ed18 + /// System handler priority + /// registers + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Priority of system handler + /// 4 + PRI_4: u8, + /// Priority of system handler + /// 5 + PRI_5: u8, + /// Priority of system handler + /// 6 + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000ed1c + /// System handler priority + /// registers + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler + /// 11 + PRI_11: u8, + }), base_address + 0x1c); + + /// address: 0xe000ed20 + /// System handler priority + /// registers + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler + /// 14 + PRI_14: u8, + /// Priority of system handler + /// 15 + PRI_15: u8, + }), base_address + 0x20); + + /// address: 0xe000ed24 + /// System handler control and state + /// register + pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory management fault exception active + /// bit + MEMFAULTACT: u1, + /// Bus fault exception active + /// bit + BUSFAULTACT: u1, + reserved0: u1, + /// Usage fault exception active + /// bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active + /// bit + PENDSVACT: u1, + /// SysTick exception active + /// bit + SYSTICKACT: u1, + /// Usage fault exception pending + /// bit + USGFAULTPENDED: u1, + /// Memory management fault exception + /// pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending + /// bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable + /// bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x24); + + /// address: 0xe000ed28 + /// Configurable fault status + /// register + pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Instruction access violation + /// flag + IACCVIOL: u1, + reserved1: u1, + /// Memory manager fault on unstacking for a + /// return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for + /// exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved2: u1, + /// Memory Management Fault Address Register + /// (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return + /// from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception + /// entry + STKERR: u1, + /// Bus fault on floating-point lazy state + /// preservation + LSPERR: u1, + reserved3: u1, + /// Bus Fault Address Register (BFAR) valid + /// flag + BFARVALID: u1, + /// Undefined instruction usage + /// fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage + /// fault + INVPC: u1, + /// No coprocessor usage + /// fault. + NOCP: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Unaligned access usage + /// fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0xe000ed2c + /// Hard fault status register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), base_address + 0x2c); + + /// address: 0xe000ed34 + /// Memory management fault address + /// register + pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0xe000ed38 + /// Bus fault address register + pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0xe000ed3c + /// Auxiliary fault status + /// register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Implementation defined + IMPDEF: u32, + }), base_address + 0x3c); + }; + + /// Nested vectored interrupt + /// controller + pub const NVIC_STIR = struct { + pub const base_address = 0xe000ef00; + + /// address: 0xe000ef00 + /// Software trigger interrupt + /// register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Software generated interrupt + /// ID + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = struct { + pub const base_address = 0xe000ed88; + + /// address: 0xe000ed88 + /// Coprocessor access control + /// register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// CP + CP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + }; + + /// System control block ACTLR + pub const SCB_ACTRL = struct { + pub const base_address = 0xe000e008; + + /// address: 0xe000e008 + /// Auxiliary control register + pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/modules/chips/stm32f429/stm32f429.zig b/src/modules/chips/stm32f429/stm32f429.zig new file mode 100644 index 0000000..737a83f --- /dev/null +++ b/src/modules/chips/stm32f429/stm32f429.zig @@ -0,0 +1,78 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code should work with all the STM32F42xx line +//! +//! Specifically, TIM6 is running on a 16 MHz clock, +//! HSI = 16 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 16 MHz. +//! And with the default APB1 prescaler = /1: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE1 = 0 }); +//! ``` +//! +//! results in PCLK1 = 16 MHz. +//! +//! TODO: add more clock calculations when adding Uart + +const std = @import("std"); +const micro = @import("microzig"); +const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'K') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'K' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn setInput(comptime pin: type) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + switch (state) { + .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), + .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; diff --git a/tests/blinky.zig b/tests/blinky.zig index 543f4da..bac49c8 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -7,6 +7,7 @@ const led_pin = if (micro.config.has_board) .@"mbed LPC1768" => micro.Pin("LED-1"), .@"STM32F3DISCOVERY" => micro.Pin("LD3"), .@"STM32F4DISCOVERY" => micro.Pin("LD5"), + .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) { From a6adc1d9da8fd834e2d0cd5d82288e7324490391 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 1 Apr 2022 10:30:13 +0200 Subject: [PATCH 046/138] Implements a generic gpio button driver with basic debouncing. (#41) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- src/drivers/button.zig | 67 ++++++++++++++++++++++++++++++++++++++++++ src/main.zig | 6 ++++ 2 files changed, 73 insertions(+) create mode 100644 src/drivers/button.zig diff --git a/src/drivers/button.zig b/src/drivers/button.zig new file mode 100644 index 0000000..be519db --- /dev/null +++ b/src/drivers/button.zig @@ -0,0 +1,67 @@ +const std = @import("std"); +const micro = @import("microzig"); + +pub const Event = enum { + /// Nothing has changed. + idle, + + /// The button was pressed. Will only trigger once per press. + /// Use `Button.isPressed()` to check if the button is currently held. + pressed, + + /// The button was released. Will only trigger once per release. + /// Use `Button.isPressed()` to check if the button is currently held. + released, +}; + +pub fn Button( + /// The GPIO pin the button is connected to. Will be initialized when calling Button.init + comptime gpio: type, + /// The active state for the button. Use `.high` for active-high, `.low` for active-low. + comptime active_state: micro.gpio.State, + /// Optional filter depth for debouncing. If `null` is passed, 16 samples are used to debounce the button, + /// otherwise the given number of samples is used. + comptime filter_depth: ?comptime_int, +) type { + return struct { + const Self = @This(); + const DebounceFilter = std.meta.Int(.unsigned, filter_depth orelse 16); + + debounce: DebounceFilter, + state: micro.gpio.State, + + pub fn init() Self { + gpio.init(); + return Self{ + .debounce = 0, + .state = gpio.read(), + }; + } + + /// Polls for the button state. Returns the change event for the button if any. + pub fn poll(self: *Self) Event { + const state = gpio.read(); + const active_unfiltered = (state == active_state); + + const previous_debounce = self.debounce; + self.debounce <<= 1; + if (active_unfiltered) { + self.debounce |= 1; + } + + if (active_unfiltered and previous_debounce == 0) { + return .pressed; + } else if (!active_unfiltered and self.debounce == 0 and previous_debounce != 0) { + return .released; + } else { + return .idle; + } + } + + /// Returns `true` when the button is pressed. + /// Will only be updated when `poll` is regularly called. + pub fn isPressed(self: *Self) bool { + return (self.debounce != 0); + } + }; +} diff --git a/src/main.zig b/src/main.zig index 406283a..8b565a8 100644 --- a/src/main.zig +++ b/src/main.zig @@ -189,4 +189,10 @@ pub const drivers = struct { .path = .{ .path = root_path ++ "drivers/quadrature.zig" }, .dependencies = &.{pkgs.microzig}, }; + + pub const button = std.build.Pkg{ + .name = "microzig.button", + .path = .{ .path = root_path ++ "drivers/button.zig" }, + .dependencies = &.{pkgs.microzig}, + }; }; From c0e0423f5c694115836fb596e19383cd92f8d2b4 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 1 Apr 2022 09:05:46 -0700 Subject: [PATCH 047/138] Readme (#40) * add readme * fix toc --- README.md | 135 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 134 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 1f130a9..1a44ae3 100644 --- a/README.md +++ b/README.md @@ -1 +1,134 @@ -# NOTHING IS STABLE IN THIS REPO +# microzig + +[![discord](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](https://discord.gg/ShUWykk38X) + +## NOTE: in development + +APIs will likely break in the future + +Table of Contents +================= + + * [Contributing](#contributing) + * [Introduction](#introduction) + * [How to](#how-to) + * [Embedded project with "supported" chip/board](#embedded-project-with-supported-chipboard) + * [Embedded project with "unsupported" chip](#embedded-project-with-unsupported-chip) + * [Interrupts](#interrupts) + + + +## Contributing + +Please see the [project page](https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1), its used as a place to brainstorm and organize work in ZEG. +There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. + +## Introduction + +This repo contains the infrastructure for getting started in an embedded Zig project, as well as some code to interact with some chips/boards. Specifically it offers: +- a single easy-to-use builder function that: + - generates your linker script + - sets up packages and start code +- generalized interfaces for common devices, such as UART. +- device drivers for interacting with external hardware +- an uncomplicated method to define [interrupts](#interrupts) + +## How to + +Here's a number of things you might be interested in doing, and how to achieve them with microzig and other ZEG tools. + +### Embedded project with "supported" chip/board + +Start with an empty Zig project by running `zig init-exe`, and add microzig as a git submodule (or your choice of package manager). +Then in your `build.zig`: + +```zig +const std = @import("std"); +const microzig = @import("path/to/microzig/src/main.zig"); + +pub fn build(b: *std.build.Builder) !void { + const backing = .{ + .board = microzig.boards.arduino_nano, + + // if you don't have one of the boards, but do have one of the + // "supported" chips: + // .chip = microzig.chips.atmega328p, + }; + + const exe = try microzig.addEmbeddedExecutable( + b, + "my-executable", + "src/main.zig", + backing, + .{ + // optional slice of packages that can be imported into your app: + // .packages = &my_packages, + }, + ); + exe.setBuildMode(.ReleaseSmall); + exe.install(); +} +``` + +`zig build` and now you have an executable for an Arduino Nano. +In your application you can import `microzig` in order to interact with the hardware: + +```zig +const microzig = @import("microzig"); + +// `microzig.chip.registers`: access to register definitions + +pub fn main() !void { + // your program here +} +``` + +### Embedded project with "unsupported" chip + +If you have a board/chip that isn't defined in microzig, you can set it up yourself! +You need to have: +- SVD or ATDF file defining registers +- flash and ram address and sizes + +First use [regz](https://github.com/ZigEmbeddedGroup/regz) to generate the register definitions for your chip and save them to a file. +Then your `build.zig` is going to be the same, but you'll define the chip yourself: + +```zig +const nrf52832 = Chip{ + .name = "nRF52832", + .path = "path/to/generated/file.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, +}; + +const backing = .{ + .chip = nrf52832, +}; +``` + +NOTE: `regz` is also still in development, and while it tends to generate code well, it's possible that there will be errors in the generated code! +Please create an issue if you run into anything fishy. + +### Interrupts + +The current supported architectures for interrupt vector generation are ARM and AVR. +To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace: + +```zig + +pub const interrupts = struct { + pub fn PCINT0() void { + // interrupt handling code + } +}; + +pub fn main() !void { + // my application +} +``` + +We're using compile-time checks along with the generated code to determine the list of interrupts. +If a function is defined whose name is not in this list, you'll get a compiler error with the list of interrupts/valid names. From 8b04413e556491b2df70e5e0e126adda86f5c806 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Wed, 13 Apr 2022 23:06:05 +0200 Subject: [PATCH 048/138] Add Uart to STM32F4Discovery and rework uart-sync example (#43) * stm32f407: add Uart support * lpc1768: add cpu_frequency in board and chip Allow using them with microzig Uart, which ensures the clock is present * lpc1768: fix UART2 and UART3 peripheral clock register They are in the PCLKSEL1 register, not PCLKSEL0 * uart-sync: use native microzig Uart, target different boards/chips The previous example was lpc1768 specific, this new example should work with all board and chips which implement the microzig Uart functionality. Instead of 4 LEDs, the new example uses a single LED to provide minimal debugging capabilities if something does not work correctly. This allows building this example for the stm32 f3 and f4 discovery boards. --- build.zig | 4 +- .../boards/mbed-lpc1768/mbed-lpc1768.zig | 2 + src/modules/chips/lpc1768/lpc1768.zig | 6 +- src/modules/chips/stm32f407/stm32f407.zig | 163 +++++++++++++++++- tests/uart-sync.zig | 144 ++++++---------- 5 files changed, 220 insertions(+), 99 deletions(-) diff --git a/build.zig b/build.zig index c63cb0f..0519e58 100644 --- a/build.zig +++ b/build.zig @@ -21,8 +21,8 @@ pub fn build(b: *std.build.Builder) !void { BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, - BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery }, .supports_uart_test = false }, - BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery }, .supports_uart_test = false }, + BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery } }, + BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery } }, BuildConfig{ .name = "boards.stm32f429idiscovery", .backing = Backing{ .board = boards.stm32f429idiscovery }, .supports_uart_test = false }, }; diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig index 95358ff..03a5fbb 100644 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig @@ -1,6 +1,8 @@ pub const chip = @import("chip"); pub const micro = @import("microzig"); +pub const cpu_frequency: u32 = 100_000_000; // 100 MHz + pub fn debugWrite(string: []const u8) void { const clk_pin = micro.Pin("DIP5"); const dat_pin = micro.Pin("DIP6"); diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 666d272..aa00f58 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -5,6 +5,8 @@ const regs = chip.registers; pub usingnamespace chip; +pub const cpu_frequency: u32 = 100_000_000; // 100 MHz + pub const PinTarget = enum(u2) { func00 = 0b00, func01 = 0b01, @@ -129,11 +131,11 @@ pub fn Uart(comptime index: usize) type { }, 2 => { regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); - regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) }); + regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) }); }, 3 => { regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); - regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) }); + regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) }); }, else => unreachable, } diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index 1619f72..1359e31 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -19,7 +19,18 @@ //! //! results in PCLK1 = 16 MHz. //! -//! TODO: add more clock calculations when adding Uart +//! The above default configuration makes U(S)ART2..5 +//! receive a 16 MHz clock by default. +//! +//! USART1 and USART6 use PCLK2, which uses the APB2 prescaler on HCLK, +//! default APB2 prescaler = /1: +//! +//! ``` +//! regs.RCC.CFGR.modify(.{ .PPRE2 = 0 }); +//! ``` +//! +//! and therefore USART1 and USART6 receive a 16 MHz clock. +//! const std = @import("std"); const micro = @import("microzig"); @@ -28,6 +39,12 @@ const regs = chip.registers; pub usingnamespace chip; +// Default clock frequencies after reset, see top comment for calculation +// TODO: these would need to change when we support multiple clock configurations +pub const ahb_frequency = 16_000_000; +pub const apb1_frequency = 16_000_000; +pub const apb2_frequency = 16_000_000; + pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -77,3 +94,147 @@ pub const gpio = struct { } } }; + +pub const uart = struct { + pub const DataBits = enum { + seven, + eight, + nine, + }; + + /// uses the values of USART_CR2.STOP + pub const StopBits = enum(u2) { + one = 0b00, + half = 0b01, + two = 0b10, + one_and_half = 0b11, + }; + + /// uses the values of USART_CR1.PS + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; +}; + +pub fn Uart(comptime index: usize) type { + if (!(index == 2)) @compileError("TODO: only USART2 is currently supported"); + + return struct { + parity_read_mask: u8, + + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + // The following must all be written when the USART is disabled (UE=0). + if (regs.USART2.CR1.read().UE == 1) + @panic("Trying to initialize USART2 while it is already enabled"); + // LATER: Alternatively, set UE=0 at this point? Then wait for something? + // Or add a destroy() function which disables the USART? + + // enable the USART2 clock + regs.RCC.APB1ENR.modify(.{ .USART2EN = 1 }); + // enable GPIOA clock + regs.RCC.AHB1ENR.modify(.{ .GPIOAEN = 1 }); + // set PA2+PA3 to alternate function 7, USART2_TX + USART2_RX + regs.GPIOA.MODER.modify(.{ .MODER2 = 0b10, .MODER3 = 0b10 }); + regs.GPIOA.AFRL.modify(.{ .AFRL2 = 7, .AFRL3 = 7 }); + + // clear USART2 configuration to its default + regs.USART2.CR1.raw = 0; + regs.USART2.CR2.raw = 0; + regs.USART2.CR3.raw = 0; + + // Return error for unsupported combinations + if (config.data_bits == .nine and config.parity != null) { + // TODO: should we consider this an unsupported word size or unsupported parity? + return error.UnsupportedWordSize; + } else if (config.data_bits == .seven and config.parity == null) { + // TODO: should we consider this an unsupported word size or unsupported parity? + return error.UnsupportedWordSize; + } + + // set word length + // Per the reference manual, M means + // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default + // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits + const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0; + regs.USART2.CR1.modify(.{ .M = m }); + + // set parity + if (config.parity) |parity| { + regs.USART2.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); + } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default + + // set number of stop bits + regs.USART2.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); + + // set the baud rate + // Despite the reference manual talking about fractional calculation and other buzzwords, + // it is actually just a simple divider. Just ignore DIV_Mantissa and DIV_Fraction and + // set the result of the division as the lower 16 bits of BRR. + // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling). + // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) + // TODO: Do a rounding div, instead of a truncating div? + const usartdiv = @intCast(u16, @divTrunc(apb1_frequency, config.baud_rate)); + regs.USART2.BRR.raw = usartdiv; + + // enable USART2, and its transmitter and receiver + regs.USART2.CR1.modify(.{ .UE = 1 }); + regs.USART2.CR1.modify(.{ .TE = 1 }); + regs.USART2.CR1.modify(.{ .RE = 1 }); + + // For code simplicity, at cost of one or more register reads, + // we read back the actual configuration from the registers, + // instead of using the `config` values. + return readFromRegisters(); + } + + pub fn getOrInit(config: micro.uart.Config) !Self { + if (regs.USART2.CR1.read().UE == 1) { + // UART1 already enabled, don't reinitialize and disturb things; + // instead read and use the actual configuration. + return readFromRegisters(); + } else return init(config); + } + + fn readFromRegisters() Self { + const cr1 = regs.USART2.CR1.read(); + // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, + // then we also mask away the 8th bit. + return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return switch (regs.USART2.SR.read().TXE) { + 1 => true, + 0 => false, + }; + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + regs.USART2.DR.modify(ch); + } + + pub fn txflush(_: Self) void { + while (regs.USART2.SR.read().TC == 0) {} + } + + pub fn canRead(self: Self) bool { + _ = self; + return switch (regs.USART2.SR.read().RXNE) { + 1 => true, + 0 => false, + }; + } + + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + const data_with_parity_bit: u9 = regs.USART2.DR.read(); + return @intCast(u8, data_with_parity_bit & self.parity_read_mask); + } + }; +} diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 2a0734e..c416c7b 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -1,120 +1,76 @@ const micro = @import("microzig"); // Configures the led_pin to a hardware pin -const uart_txd_pin = micro.Pin("P0.15"); -const uart_rxd_pin = micro.Pin("P0.16"); - -const debug_pin = micro.Pin("P0.17"); - -const led1_pin = micro.Pin("P1.18"); -const led2_pin = micro.Pin("P1.20"); -const led3_pin = micro.Pin("P1.21"); -const led4_pin = micro.Pin("P1.23"); - -pub const cpu_frequency: u32 = 100_000_000; // 100 MHz - -const PLL = struct { - fn init() void { - reset_overclocking(); +const led_pin = if (micro.config.has_board) + switch (micro.config.board_name) { + .@"Arduino Nano" => micro.Pin("D13"), + .@"mbed LPC1768" => micro.Pin("LED-1"), + .@"STM32F3DISCOVERY" => micro.Pin("LD3"), + .@"STM32F4DISCOVERY" => micro.Pin("LD5"), + .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), + else => @compileError("unknown board"), } +else switch (micro.config.chip_name) { + .@"ATmega328p" => micro.Pin("PB5"), + .@"NXP LPC1768" => micro.Pin("P1.18"), + .@"STM32F103x8" => micro.Pin("PC13"), + else => @compileError("unknown chip"), +}; - fn reset_overclocking() void { - overclock_flash(5); // 5 cycles access time - overclock_pll(3); // 100 MHz - } - - fn overclock_flash(timing: u4) void { - micro.chip.registers.SYSCON.FLASHCFG.modify(.{ - .FLASHTIM = timing - 1, - }); - } - inline fn feed_pll() void { - micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0xAA }); - micro.chip.registers.SYSCON.PLL0FEED.modify(.{ .PLL0FEED = 0x55 }); - } - - fn overclock_pll(divider: u8) void { - // PLL einrichten für RC - micro.chip.registers.SYSCON.PLL0CON.modify(.{ - .PLLE0 = 0, - .PLLC0 = 0, - }); - feed_pll(); - - micro.chip.registers.SYSCON.CLKSRCSEL.modify(.{ .CLKSRC = 0 }); // RC-Oszillator als Quelle - micro.chip.registers.SYSCON.PLL0CFG.modify(.{ - // SysClk = (4MHz / 2) * (2 * 75) = 300 MHz - .MSEL0 = 74, - .NSEL0 = 1, - }); - // CPU Takt = SysClk / divider - micro.chip.registers.SYSCON.CCLKCFG.modify(.{ .CCLKSEL = divider - 1 }); - - feed_pll(); - - micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLE0 = 1 }); // PLL einschalten - feed_pll(); - - var i: usize = 0; - while (i < 1_000) : (i += 1) { - micro.cpu.nop(); - } - - micro.chip.registers.SYSCON.PLL0CON.modify(.{ .PLLC0 = 1 }); - feed_pll(); +// Configures the uart index +const uart_idx = if (micro.config.has_board) + switch (micro.config.board_name) { + .@"mbed LPC1768" => 1, + .@"STM32F3DISCOVERY" => 1, + .@"STM32F4DISCOVERY" => 2, + else => @compileError("unknown board"), } +else switch (micro.config.chip_name) { + .@"NXP LPC1768" => 1, + else => @compileError("unknown chip"), }; pub fn main() !void { - const gpio_init = .{ .mode = .output, .initial_state = .low }; - - const led1 = micro.Gpio(led1_pin, gpio_init); - const led2 = micro.Gpio(led2_pin, gpio_init); - const led3 = micro.Gpio(led3_pin, gpio_init); - const led4 = micro.Gpio(led4_pin, gpio_init); - - const status = micro.Gpio(debug_pin, .{ + const led = micro.Gpio(led_pin, .{ .mode = .output, - .initial_state = .high, + .initial_state = .low, }); - status.init(); - led1.init(); - led2.init(); - led3.init(); - led4.init(); + led.init(); - uart_txd_pin.route(.func01); - uart_rxd_pin.route(.func01); - - PLL.init(); - led1.setToHigh(); - - var debug_port = micro.Uart(1).init(.{ + var uart = micro.Uart(uart_idx).init(.{ .baud_rate = 9600, .stop_bits = .one, .parity = null, .data_bits = .eight, }) catch |err| { - led1.write(if (err == error.UnsupportedBaudRate) micro.gpio.State.low else .high); - led2.write(if (err == error.UnsupportedParity) micro.gpio.State.low else .high); - led3.write(if (err == error.UnsupportedStopBitCount) micro.gpio.State.low else .high); - led4.write(if (err == error.UnsupportedWordSize) micro.gpio.State.low else .high); + blinkError(led, err); micro.hang(); }; - led2.setToHigh(); - - var out = debug_port.writer(); - var in = debug_port.reader(); - _ = in; - try out.writeAll("Please enter a sentence:\r\n"); - - led3.setToHigh(); + var out = uart.writer(); while (true) { - try out.writeAll("."); - led4.toggle(); + led.setToHigh(); + try out.writeAll("Hello microzig!\r\n"); + led.setToLow(); micro.debug.busySleep(100_000); } } + +fn blinkError(led: anytype, err: micro.uart.InitError) void { + var blinks: u3 = + switch (err) { + error.UnsupportedBaudRate => 1, + error.UnsupportedParity => 2, + error.UnsupportedStopBitCount => 3, + error.UnsupportedWordSize => 4, + }; + + while (blinks > 0) : (blinks -= 1) { + led.setToHigh(); + micro.debug.busySleep(1_000_000); + led.setToLow(); + micro.debug.busySleep(1_000_000); + } +} From b9cd24ae96c8351b41860e3cd372dd8743ecba3e Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Thu, 14 Apr 2022 07:08:41 +0200 Subject: [PATCH 049/138] Improve STM32F407 Uart and introduce GPIO Alternate Function (#44) --- src/core/gpio.zig | 17 ++++ src/modules/chips/stm32f407/stm32f407.zig | 113 ++++++++++++++++------ tests/uart-sync.zig | 33 ++----- 3 files changed, 107 insertions(+), 56 deletions(-) diff --git a/src/core/gpio.zig b/src/core/gpio.zig index 44e3729..75089eb 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -8,6 +8,7 @@ pub const Mode = enum { input_output, open_drain, generic, + alternate_function, }; pub const State = enum(u1) { @@ -57,6 +58,14 @@ pub fn Gpio(comptime pin: type, config: anytype) type { else => @compileError("An open_drain pin requires initial_state to be either .floating or .driven"), }); }, + .alternate_function => { + if (comptime @hasDecl(chip.gpio, "AlternateFunction")) { + const alternate_function = @as(chip.gpio.AlternateFunction, config.alternate_function); + setAlternateFunction(alternate_function); + } else { + @compileError("Alternate Function not supported yet"); + } + }, } } @@ -112,6 +121,11 @@ pub fn Gpio(comptime pin: type, config: anytype) type { fn getDrive() Drive { @compileError("open drain not implemented yet!"); } + + // alternate function + fn setAlternateFunction(af: chip.gpio.AlternateFunction) void { + chip.gpio.setAlternateFunction(pin.source_pin, af); + } }; // return only a subset of Generic for the requested pin. switch (mode) { @@ -142,6 +156,9 @@ pub fn Gpio(comptime pin: type, config: anytype) type { pub const setDrive = Generic.setDrive; pub const getDrive = Generic.getDrive; }, + .alternate_function => return struct { + pub const init = Generic.init; + }, .generic => Generic, } } diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index 1359e31..689e77d 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -53,9 +53,8 @@ pub fn parsePin(comptime spec: []const u8) type { if (spec[1] < 'A' or spec[1] > 'I') @compileError(invalid_format_msg); - const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); - return struct { + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); /// 'A'...'I' const gpio_port_name = spec[1..2]; const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); @@ -70,6 +69,25 @@ fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void } pub const gpio = struct { + pub const AlternateFunction = enum(u4) { + af0, + af1, + af2, + af3, + af4, + af5, + af6, + af7, + af8, + af9, + af10, + af11, + af12, + af13, + af14, + af15, + }; + pub fn setOutput(comptime pin: type) void { setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); @@ -80,6 +98,16 @@ pub const gpio = struct { setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); } + pub fn setAlternateFunction(comptime pin: type, af: AlternateFunction) void { + setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10); + if (pin.pin_number < 8) { + setRegField(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @enumToInt(af)); + } else { + setRegField(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @enumToInt(af)); + } + } + pub fn read(comptime pin: type) micro.gpio.State { const idr_reg = pin.gpio_port.IDR; const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? @@ -118,7 +146,27 @@ pub const uart = struct { }; pub fn Uart(comptime index: usize) type { - if (!(index == 2)) @compileError("TODO: only USART2 is currently supported"); + if (index < 1 or index > 6) @compileError("Valid USART index are 1..6"); + + const usart_name = std.fmt.comptimePrint("USART{d}", .{index}); + // TODO: support alternative pins + const pins = switch (index) { + 1 => .{ .tx = micro.Pin("PA9"), .rx = micro.Pin("PA10") }, + 2 => .{ .tx = micro.Pin("PA2"), .rx = micro.Pin("PA3") }, + 3 => .{ .tx = micro.Pin("PD8"), .rx = micro.Pin("PD9") }, + 4 => .{ .tx = micro.Pin("PC10"), .rx = micro.Pin("PC11") }, + 5 => .{ .tx = micro.Pin("PC12"), .rx = micro.Pin("PD2") }, + 6 => .{ .tx = micro.Pin("PC6"), .rx = micro.Pin("PC7") }, + else => unreachable, + }; + const tx_gpio = micro.Gpio(pins.tx, .{ + .mode = .alternate_function, + .alternate_function = .af7, + }); + const rx_gpio = micro.Gpio(pins.rx, .{ + .mode = .alternate_function, + .alternate_function = .af7, + }); return struct { parity_read_mask: u8, @@ -127,23 +175,26 @@ pub fn Uart(comptime index: usize) type { pub fn init(config: micro.uart.Config) !Self { // The following must all be written when the USART is disabled (UE=0). - if (regs.USART2.CR1.read().UE == 1) - @panic("Trying to initialize USART2 while it is already enabled"); + if (@field(regs, usart_name).CR1.read().UE == 1) + @panic("Trying to initialize " ++ usart_name ++ " while it is already enabled"); // LATER: Alternatively, set UE=0 at this point? Then wait for something? // Or add a destroy() function which disables the USART? - // enable the USART2 clock - regs.RCC.APB1ENR.modify(.{ .USART2EN = 1 }); - // enable GPIOA clock - regs.RCC.AHB1ENR.modify(.{ .GPIOAEN = 1 }); - // set PA2+PA3 to alternate function 7, USART2_TX + USART2_RX - regs.GPIOA.MODER.modify(.{ .MODER2 = 0b10, .MODER3 = 0b10 }); - regs.GPIOA.AFRL.modify(.{ .AFRL2 = 7, .AFRL3 = 7 }); + // enable the USART clock + const clk_enable_reg = switch (index) { + 1, 6 => regs.RCC.APB2ENR, + 2...5 => regs.RCC.APB1ENR, + else => unreachable, + }; + setRegField(clk_enable_reg, usart_name ++ "EN", 1); + + tx_gpio.init(); + rx_gpio.init(); - // clear USART2 configuration to its default - regs.USART2.CR1.raw = 0; - regs.USART2.CR2.raw = 0; - regs.USART2.CR3.raw = 0; + // clear USART configuration to its default + @field(regs, usart_name).CR1.raw = 0; + @field(regs, usart_name).CR2.raw = 0; + @field(regs, usart_name).CR3.raw = 0; // Return error for unsupported combinations if (config.data_bits == .nine and config.parity != null) { @@ -159,15 +210,15 @@ pub fn Uart(comptime index: usize) type { // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0; - regs.USART2.CR1.modify(.{ .M = m }); + @field(regs, usart_name).CR1.modify(.{ .M = m }); // set parity if (config.parity) |parity| { - regs.USART2.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); + @field(regs, usart_name).CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default // set number of stop bits - regs.USART2.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); + @field(regs, usart_name).CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); // set the baud rate // Despite the reference manual talking about fractional calculation and other buzzwords, @@ -177,12 +228,12 @@ pub fn Uart(comptime index: usize) type { // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) // TODO: Do a rounding div, instead of a truncating div? const usartdiv = @intCast(u16, @divTrunc(apb1_frequency, config.baud_rate)); - regs.USART2.BRR.raw = usartdiv; + @field(regs, usart_name).BRR.raw = usartdiv; - // enable USART2, and its transmitter and receiver - regs.USART2.CR1.modify(.{ .UE = 1 }); - regs.USART2.CR1.modify(.{ .TE = 1 }); - regs.USART2.CR1.modify(.{ .RE = 1 }); + // enable USART, and its transmitter and receiver + @field(regs, usart_name).CR1.modify(.{ .UE = 1 }); + @field(regs, usart_name).CR1.modify(.{ .TE = 1 }); + @field(regs, usart_name).CR1.modify(.{ .RE = 1 }); // For code simplicity, at cost of one or more register reads, // we read back the actual configuration from the registers, @@ -191,7 +242,7 @@ pub fn Uart(comptime index: usize) type { } pub fn getOrInit(config: micro.uart.Config) !Self { - if (regs.USART2.CR1.read().UE == 1) { + if (@field(regs, usart_name).CR1.read().UE == 1) { // UART1 already enabled, don't reinitialize and disturb things; // instead read and use the actual configuration. return readFromRegisters(); @@ -199,7 +250,7 @@ pub fn Uart(comptime index: usize) type { } fn readFromRegisters() Self { - const cr1 = regs.USART2.CR1.read(); + const cr1 = @field(regs, usart_name).CR1.read(); // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, // then we also mask away the 8th bit. @@ -208,7 +259,7 @@ pub fn Uart(comptime index: usize) type { pub fn canWrite(self: Self) bool { _ = self; - return switch (regs.USART2.SR.read().TXE) { + return switch (@field(regs, usart_name).SR.read().TXE) { 1 => true, 0 => false, }; @@ -216,16 +267,16 @@ pub fn Uart(comptime index: usize) type { pub fn tx(self: Self, ch: u8) void { while (!self.canWrite()) {} // Wait for Previous transmission - regs.USART2.DR.modify(ch); + @field(regs, usart_name).DR.modify(ch); } pub fn txflush(_: Self) void { - while (regs.USART2.SR.read().TC == 0) {} + while (@field(regs, usart_name).SR.read().TC == 0) {} } pub fn canRead(self: Self) bool { _ = self; - return switch (regs.USART2.SR.read().RXNE) { + return switch (@field(regs, usart_name).SR.read().RXNE) { 1 => true, 0 => false, }; @@ -233,7 +284,7 @@ pub fn Uart(comptime index: usize) type { pub fn rx(self: Self) u8 { while (!self.canRead()) {} // Wait till the data is received - const data_with_parity_bit: u9 = regs.USART2.DR.read(); + const data_with_parity_bit: u9 = @field(regs, usart_name).DR.read(); return @intCast(u8, data_with_parity_bit & self.parity_read_mask); } }; diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index c416c7b..696095b 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -1,43 +1,26 @@ const micro = @import("microzig"); -// Configures the led_pin to a hardware pin -const led_pin = if (micro.config.has_board) +// Configures the led_pin and uart index +const cfg = if (micro.config.has_board) switch (micro.config.board_name) { - .@"Arduino Nano" => micro.Pin("D13"), - .@"mbed LPC1768" => micro.Pin("LED-1"), - .@"STM32F3DISCOVERY" => micro.Pin("LD3"), - .@"STM32F4DISCOVERY" => micro.Pin("LD5"), - .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), + .@"mbed LPC1768" => .{ .led_pin = micro.Pin("LED-1"), .uart_idx = 1 }, + .@"STM32F3DISCOVERY" => .{ .led_pin = micro.Pin("LD3"), .uart_idx = 1 }, + .@"STM32F4DISCOVERY" => .{ .led_pin = micro.Pin("LD5"), .uart_idx = 2 }, else => @compileError("unknown board"), } else switch (micro.config.chip_name) { - .@"ATmega328p" => micro.Pin("PB5"), - .@"NXP LPC1768" => micro.Pin("P1.18"), - .@"STM32F103x8" => micro.Pin("PC13"), - else => @compileError("unknown chip"), -}; - -// Configures the uart index -const uart_idx = if (micro.config.has_board) - switch (micro.config.board_name) { - .@"mbed LPC1768" => 1, - .@"STM32F3DISCOVERY" => 1, - .@"STM32F4DISCOVERY" => 2, - else => @compileError("unknown board"), - } -else switch (micro.config.chip_name) { - .@"NXP LPC1768" => 1, + .@"NXP LPC1768" => .{ .led_pin = micro.Pin("P1.18"), .uart_idx = 1 }, else => @compileError("unknown chip"), }; pub fn main() !void { - const led = micro.Gpio(led_pin, .{ + const led = micro.Gpio(cfg.led_pin, .{ .mode = .output, .initial_state = .low, }); led.init(); - var uart = micro.Uart(uart_idx).init(.{ + var uart = micro.Uart(cfg.uart_idx).init(.{ .baud_rate = 9600, .stop_bits = .one, .parity = null, From 58d090644bc2cf45796c793441bfe5a88864515c Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 26 Apr 2022 23:59:25 -0700 Subject: [PATCH 050/138] Create LICENSE (#46) --- LICENSE | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..b523e66 --- /dev/null +++ b/LICENSE @@ -0,0 +1,11 @@ +Copyright (c) 2022 Matthew Knight and Felix Queißner + +This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. + +2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. + +3. This notice may not be removed or altered from any source distribution. From 8a3ec5ba02175da51ccac695bee3698db0848fa0 Mon Sep 17 00:00:00 2001 From: Vesim Date: Wed, 27 Apr 2022 10:46:59 +0200 Subject: [PATCH 051/138] Add vesim to LICENSE file (#47) --- LICENSE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LICENSE b/LICENSE index b523e66..2a30142 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2022 Matthew Knight and Felix Queißner +Copyright (c) 2022 Matthew Knight, Felix Queißner and Maciej Kuliński This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. From c418db51f6d5bf35d2ddad11317894c9a8b6f099 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 19 May 2022 18:58:46 -0700 Subject: [PATCH 052/138] add hal package option (#48) --- src/main.zig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/main.zig b/src/main.zig index 8b565a8..afd868a 100644 --- a/src/main.zig +++ b/src/main.zig @@ -28,6 +28,10 @@ fn root() []const u8 { pub const BuildOptions = struct { packages: ?[]const Pkg = null, + + // a hal package is a package with ergonomic wrappers for registers for a + // given mcu, it's only dependency can be microzig + hal_package_path: ?std.build.FileSource = null, }; pub fn addEmbeddedExecutable( @@ -156,6 +160,13 @@ pub fn addEmbeddedExecutable( exe.addPackage(chip_pkg); exe.addPackage(cpu_pkg); + if (options.hal_package_path) |hal_package_path| + exe.addPackage(.{ + .name = "hal", + .path = hal_package_path, + .dependencies = &.{pkgs.microzig}, + }); + switch (backing) { .board => |board| { exe.addPackage(std.build.Pkg{ From d253056c71327003ea357ee601f5f8508788acf5 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 27 May 2022 08:58:42 -0700 Subject: [PATCH 053/138] cortex-m0plus and fix for missing hal (#49) --- src/core/microzig.zig | 2 ++ src/modules/cpus.zig | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 8df10fc..0353d35 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -24,6 +24,8 @@ pub const board = if (config.has_board) @import("board") else void; /// Provides access to the low level features of the CPU. pub const cpu = @import("cpu"); +pub const hal = @import("hal"); + /// Module that helps with interrupt handling. pub const interrupts = @import("interrupts.zig"); diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 95f37e4..3c739c1 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -18,6 +18,17 @@ pub const avr5 = Cpu{ }, }; +pub const cortex_m0plus = Cpu{ + .name = "ARM Cortex-M0+", + .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .none, + }, +}; + pub const cortex_m3 = Cpu{ .name = "ARM Cortex-M3", .path = root_path ++ "cpus/cortex-m/cortex-m.zig", From 423c886d2ec9d78579afcf6dfef47528c188487d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sat, 28 May 2022 10:37:14 +0200 Subject: [PATCH 054/138] Master update (#51) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Adds logo * Update to latest master. Co-authored-by: Felix "xq" Queißner --- design/logo-text-inkscape-variant-1.svg | 64 +++++++++++++++++++++++++ design/logo-text-inkscape-variant-2.svg | 64 +++++++++++++++++++++++++ design/logo-text-inkscape.svg | 64 +++++++++++++++++++++++++ design/logo-text-variant-1.svg | 15 ++++++ design/logo-text-variant-2.svg | 15 ++++++ design/logo.svg | 9 ++++ src/main.zig | 20 ++++---- 7 files changed, 241 insertions(+), 10 deletions(-) create mode 100644 design/logo-text-inkscape-variant-1.svg create mode 100644 design/logo-text-inkscape-variant-2.svg create mode 100644 design/logo-text-inkscape.svg create mode 100644 design/logo-text-variant-1.svg create mode 100644 design/logo-text-variant-2.svg create mode 100644 design/logo.svg diff --git a/design/logo-text-inkscape-variant-1.svg b/design/logo-text-inkscape-variant-1.svg new file mode 100644 index 0000000..f26743e --- /dev/null +++ b/design/logo-text-inkscape-variant-1.svg @@ -0,0 +1,64 @@ + + + + + + + + + MicroZig + + diff --git a/design/logo-text-inkscape-variant-2.svg b/design/logo-text-inkscape-variant-2.svg new file mode 100644 index 0000000..875cef6 --- /dev/null +++ b/design/logo-text-inkscape-variant-2.svg @@ -0,0 +1,64 @@ + + + + + + + + + MicroZig + + diff --git a/design/logo-text-inkscape.svg b/design/logo-text-inkscape.svg new file mode 100644 index 0000000..69dba8b --- /dev/null +++ b/design/logo-text-inkscape.svg @@ -0,0 +1,64 @@ + + + + + + + + + MicroZig + + diff --git a/design/logo-text-variant-1.svg b/design/logo-text-variant-1.svg new file mode 100644 index 0000000..530592f --- /dev/null +++ b/design/logo-text-variant-1.svg @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/design/logo-text-variant-2.svg b/design/logo-text-variant-2.svg new file mode 100644 index 0000000..9a732cb --- /dev/null +++ b/design/logo-text-variant-2.svg @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/design/logo.svg b/design/logo.svg new file mode 100644 index 0000000..3e5f419 --- /dev/null +++ b/design/logo.svg @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/src/main.zig b/src/main.zig index afd868a..cd30986 100644 --- a/src/main.zig +++ b/src/main.zig @@ -108,18 +108,18 @@ pub fn addEmbeddedExecutable( const config_pkg = Pkg{ .name = "microzig-config", - .path = .{ .path = config_file_name }, + .source = .{ .path = config_file_name }, }; const chip_pkg = Pkg{ .name = "chip", - .path = .{ .path = chip.path }, + .source = .{ .path = chip.path }, .dependencies = &.{pkgs.microzig}, }; const cpu_pkg = Pkg{ .name = "cpu", - .path = .{ .path = chip.cpu.path }, + .source = .{ .path = chip.cpu.path }, .dependencies = &.{pkgs.microzig}, }; @@ -148,7 +148,7 @@ pub fn addEmbeddedExecutable( break :blk std.build.Pkg{ .name = "app", - .path = .{ .path = source }, + .source = .{ .path = source }, .dependencies = app_pkgs.items, }; }; @@ -163,7 +163,7 @@ pub fn addEmbeddedExecutable( if (options.hal_package_path) |hal_package_path| exe.addPackage(.{ .name = "hal", - .path = hal_package_path, + .source = hal_package_path, .dependencies = &.{pkgs.microzig}, }); @@ -171,7 +171,7 @@ pub fn addEmbeddedExecutable( .board => |board| { exe.addPackage(std.build.Pkg{ .name = "board", - .path = .{ .path = board.path }, + .source = .{ .path = board.path }, .dependencies = &.{pkgs.microzig}, }); }, @@ -184,12 +184,12 @@ pub fn addEmbeddedExecutable( const pkgs = struct { const mmio = std.build.Pkg{ .name = "microzig-mmio", - .path = .{ .path = root_path ++ "core/mmio.zig" }, + .source = .{ .path = root_path ++ "core/mmio.zig" }, }; const microzig = std.build.Pkg{ .name = "microzig", - .path = .{ .path = root_path ++ "core/import-package.zig" }, + .source = .{ .path = root_path ++ "core/import-package.zig" }, }; }; @@ -197,13 +197,13 @@ const pkgs = struct { pub const drivers = struct { pub const quadrature = std.build.Pkg{ .name = "microzig.quadrature", - .path = .{ .path = root_path ++ "drivers/quadrature.zig" }, + .source = .{ .path = root_path ++ "drivers/quadrature.zig" }, .dependencies = &.{pkgs.microzig}, }; pub const button = std.build.Pkg{ .name = "microzig.button", - .path = .{ .path = root_path ++ "drivers/button.zig" }, + .source = .{ .path = root_path ++ "drivers/button.zig" }, .dependencies = &.{pkgs.microzig}, }; }; From 7fcaf17c468ed5301059ace4e4be595bf7aa46a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sat, 28 May 2022 11:12:28 +0200 Subject: [PATCH 055/138] Adds logo (#50) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Creates logo with bright and dark variant * Adds logo to README.md Co-authored-by: Felix "xq" Queißner --- README.md | 19 ++--- design/logo-text-auto.svg | 13 +++ design/logo-text-brightmode.svg | 1 + design/logo-text-darkmode.svg | 1 + design/logo-text-inkscape-variant-1.svg | 64 --------------- design/logo-text-inkscape-variant-2.svg | 64 --------------- design/logo-text-inkscape.svg | 103 +++++++++++++++++------- design/logo-text-variant-1.svg | 15 ---- design/logo-text-variant-2.svg | 15 ---- design/logo.svg | 10 +-- 10 files changed, 101 insertions(+), 204 deletions(-) create mode 100644 design/logo-text-auto.svg create mode 100644 design/logo-text-brightmode.svg create mode 100644 design/logo-text-darkmode.svg delete mode 100644 design/logo-text-inkscape-variant-1.svg delete mode 100644 design/logo-text-inkscape-variant-2.svg delete mode 100644 design/logo-text-variant-1.svg delete mode 100644 design/logo-text-variant-2.svg diff --git a/README.md b/README.md index 1a44ae3..0aaf896 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# microzig +![microzig logo](design/logo-text-auto.svg) [![discord](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](https://discord.gg/ShUWykk38X) @@ -6,15 +6,14 @@ APIs will likely break in the future -Table of Contents -================= +# Table of Contents - * [Contributing](#contributing) - * [Introduction](#introduction) - * [How to](#how-to) - * [Embedded project with "supported" chip/board](#embedded-project-with-supported-chipboard) - * [Embedded project with "unsupported" chip](#embedded-project-with-unsupported-chip) - * [Interrupts](#interrupts) +- [Contributing](#contributing) +- [Introduction](#introduction) +- [How to](#how-to) + - [Embedded project with "supported" chip/board](#embedded-project-with-supported-chipboard) + - [Embedded project with "unsupported" chip](#embedded-project-with-unsupported-chip) + - [Interrupts](#interrupts) @@ -26,6 +25,7 @@ There will be issues marked as `good first issue`, or drafts for larger ideas th ## Introduction This repo contains the infrastructure for getting started in an embedded Zig project, as well as some code to interact with some chips/boards. Specifically it offers: + - a single easy-to-use builder function that: - generates your linker script - sets up packages and start code @@ -87,6 +87,7 @@ pub fn main() !void { If you have a board/chip that isn't defined in microzig, you can set it up yourself! You need to have: + - SVD or ATDF file defining registers - flash and ram address and sizes diff --git a/design/logo-text-auto.svg b/design/logo-text-auto.svg new file mode 100644 index 0000000..ab40494 --- /dev/null +++ b/design/logo-text-auto.svg @@ -0,0 +1,13 @@ + + + + + + + + \ No newline at end of file diff --git a/design/logo-text-brightmode.svg b/design/logo-text-brightmode.svg new file mode 100644 index 0000000..c048b67 --- /dev/null +++ b/design/logo-text-brightmode.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/design/logo-text-darkmode.svg b/design/logo-text-darkmode.svg new file mode 100644 index 0000000..f744c99 --- /dev/null +++ b/design/logo-text-darkmode.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/design/logo-text-inkscape-variant-1.svg b/design/logo-text-inkscape-variant-1.svg deleted file mode 100644 index f26743e..0000000 --- a/design/logo-text-inkscape-variant-1.svg +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - MicroZig - - diff --git a/design/logo-text-inkscape-variant-2.svg b/design/logo-text-inkscape-variant-2.svg deleted file mode 100644 index 875cef6..0000000 --- a/design/logo-text-inkscape-variant-2.svg +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - MicroZig - - diff --git a/design/logo-text-inkscape.svg b/design/logo-text-inkscape.svg index 69dba8b..210065c 100644 --- a/design/logo-text-inkscape.svg +++ b/design/logo-text-inkscape.svg @@ -2,16 +2,15 @@ + inkscape:current-layer="layer1" + showguides="true" + inkscape:guide-bbox="true"> + + + - - + + + MicroZig + style="font-size:112.46px;line-height:1.25;font-family:'Dash Horizon';-inkscape-font-specification:'Dash Horizon, Normal';fill:#acacac;stroke-width:2.86448;fill-opacity:1"> + + + + + + + + + + diff --git a/design/logo-text-variant-1.svg b/design/logo-text-variant-1.svg deleted file mode 100644 index 530592f..0000000 --- a/design/logo-text-variant-1.svg +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/design/logo-text-variant-2.svg b/design/logo-text-variant-2.svg deleted file mode 100644 index 9a732cb..0000000 --- a/design/logo-text-variant-2.svg +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/design/logo.svg b/design/logo.svg index 3e5f419..c48f717 100644 --- a/design/logo.svg +++ b/design/logo.svg @@ -1,9 +1 @@ - - - - - - - - - + From ac19b7de8eb1551e603b3ce23a4aab69c71d1216 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 29 May 2022 12:53:28 -0700 Subject: [PATCH 056/138] update to master (#52) --- src/modules/chips/lpc1768/lpc1768.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index aa00f58..2ca08d7 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -163,7 +163,7 @@ pub fn Uart(comptime index: usize) type { const pclk = micro.clock.get() / 4; const divider = (pclk / (16 * config.baud_rate)); - const regval = std.math.cast(u16, divider) catch return error.UnsupportedBaudRate; + const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate; UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); From 8720973005c8eb8888a5ff73a2af27074dd576c0 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Sun, 3 Jul 2022 01:59:14 +0200 Subject: [PATCH 057/138] Add support for multiple clock domains (#53) While this does not automate clock configuration yet, at least it allows using microzig with applications that configure the clock themselves and then declare the speeds of the various domains. Without this, all peripheral depending on different clock domanins (e.g. Uart or I2C on STM32 devices) could only work with the reset frequency. --- src/core/clock.zig | 12 +++++++---- .../boards/arduino-nano/arduino-nano.zig | 4 +++- .../boards/mbed-lpc1768/mbed-lpc1768.zig | 4 +++- .../stm32f4discovery/stm32f4discovery.zig | 2 -- src/modules/chips/atmega328p/atmega328p.zig | 10 +++++++-- src/modules/chips/lpc1768/lpc1768.zig | 14 ++++++++++--- src/modules/chips/stm32f303/stm32f303.zig | 20 +++++++++++++++++- src/modules/chips/stm32f407/stm32f407.zig | 21 ++++++++++++++----- src/modules/chips/stm32f429/stm32f429.zig | 17 +++++++++++++++ 9 files changed, 85 insertions(+), 19 deletions(-) diff --git a/src/core/clock.zig b/src/core/clock.zig index a7d8b64..71056bd 100644 --- a/src/core/clock.zig +++ b/src/core/clock.zig @@ -1,5 +1,6 @@ const std = @import("std"); const micro = @import("microzig.zig"); +const chip = @import("chip"); /// An enumeration of clock sources. pub const Source = enum { @@ -10,6 +11,9 @@ pub const Source = enum { cpu, }; +/// A struct containing the frequency in hertz for each clock domain +pub const Clocks = std.enums.EnumFieldStruct(chip.clock.Domain, u32, null); + /// Is `true` when microzig has a clock frequency available. /// Clock can be provided by several clock sources pub const has_clock = (clock_source_type != void); @@ -30,16 +34,16 @@ pub const source: Source = switch (clock_source_type) { /// Ensures that microzig has a clock available. This will @compileError when no clock is available, otherwise, it will be a no-op. pub fn ensure() void { if (!has_clock) - @compileError("microzig requires the clock frequency to perform this operation. Please export a const or var cpu_frequency from your root file that contains the cpu frequency in hertz!"); + @compileError("microzig requires the clock frequency to perform this operation. Please export a const or var clock_frequencies from your root file that contains the clock frequency for all chip clock domains in hertz!"); } -/// Returns the current cpu frequency in hertz. -pub inline fn get() u32 { +/// Returns the Clocks struct, with all clock domains frequencies in hertz. +pub inline fn get() Clocks { ensure(); return @field(clock_source_type, freq_decl_name); } -const freq_decl_name = "cpu_frequency"; +const freq_decl_name = "clock_frequencies"; const no_clock_source_type = opaque {}; const clock_source_type = if (@hasDecl(micro.app, freq_decl_name)) diff --git a/src/modules/boards/arduino-nano/arduino-nano.zig b/src/modules/boards/arduino-nano/arduino-nano.zig index 16ade81..96490f8 100644 --- a/src/modules/boards/arduino-nano/arduino-nano.zig +++ b/src/modules/boards/arduino-nano/arduino-nano.zig @@ -1,6 +1,8 @@ pub const chip = @import("chip"); -pub const cpu_frequency = 16_000_000; +pub const clock_frequencies = .{ + .cpu = 16_000_000, +}; pub const pin_map = .{ // Port A diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig index 03a5fbb..6c5ff9d 100644 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig @@ -1,7 +1,9 @@ pub const chip = @import("chip"); pub const micro = @import("microzig"); -pub const cpu_frequency: u32 = 100_000_000; // 100 MHz +pub const clock_frequencies = .{ + .cpu = 100_000_000, // 100 Mhz +}; pub fn debugWrite(string: []const u8) void { const clk_pin = micro.Pin("DIP5"); diff --git a/src/modules/boards/stm32f4discovery/stm32f4discovery.zig b/src/modules/boards/stm32f4discovery/stm32f4discovery.zig index 8fdf824..7703b1d 100644 --- a/src/modules/boards/stm32f4discovery/stm32f4discovery.zig +++ b/src/modules/boards/stm32f4discovery/stm32f4discovery.zig @@ -1,8 +1,6 @@ pub const chip = @import("chip"); pub const micro = @import("microzig"); -pub const cpu_frequency = 16_000_000; - pub const pin_map = .{ // LED cross, connected to GPIOD bits 12..15 // N orange diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 43022a8..9375a6d 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -11,6 +11,12 @@ const Port = enum(u8) { D = 3, }; +pub const clock = struct { + pub const Domain = enum { + cpu, + }; +}; + pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -94,14 +100,14 @@ pub fn Uart(comptime index: usize) type { const Self = @This(); fn computeDivider(baud_rate: u32) !u12 { - const pclk = micro.clock.get(); + const pclk = micro.clock.get().cpu; const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; return std.math.cast(u12, divider) catch return error.UnsupportedBaudRate; } fn computeBaudRate(divider: u12) u32 { - return micro.clock.get() / (16 * @as(u32, divider) + 1); + return micro.clock.get().cpu / (16 * @as(u32, divider) + 1); } pub fn init(config: micro.uart.Config) !Self { diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 2ca08d7..93a88a4 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -5,7 +5,15 @@ const regs = chip.registers; pub usingnamespace chip; -pub const cpu_frequency: u32 = 100_000_000; // 100 MHz +pub const clock = struct { + pub const Domain = enum { + cpu, + }; +}; + +pub const clock_frequencies = .{ + .cpu = 100_000_000, // 100 Mhz +}; pub const PinTarget = enum(u2) { func00 = 0b00, @@ -156,11 +164,11 @@ pub fn Uart(comptime index: usize) type { //UARTn.FCR.modify(.{ .FIFOEN = .UARTN_FIFOS_ARE_DISA }); micro.debug.writer().print("clock: {} baud: {} ", .{ - micro.clock.get(), + micro.clock.get().cpu, config.baud_rate, }) catch {}; - const pclk = micro.clock.get() / 4; + const pclk = micro.clock.get().cpu / 4; const divider = (pclk / (16 * config.baud_rate)); const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 4bbfb0f..4b8ff37 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -43,6 +43,24 @@ const regs = chip.registers; pub usingnamespace chip; pub const cpu = @import("cpu"); + +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + +// Default clock frequencies after reset, see top comment for calculation +pub const clock_frequencies = .{ + .cpu = 8_000_000, + .ahb = 8_000_000, + .apb1 = 8_000_000, + .apb2 = 8_000_000, +}; + pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -170,7 +188,7 @@ pub fn Uart(comptime index: usize) type { // if the board doesn't configure e.g. an HSE external crystal. // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) // TODO: Do a rounding div, instead of a truncating div? - const usartdiv = @intCast(u16, @divTrunc(micro.board.cpu_frequency, config.baud_rate)); + const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate)); regs.USART1.BRR.raw = usartdiv; // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction, // those seem to be for another chipset; .svd file bug? diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index 689e77d..17f4039 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -39,11 +39,22 @@ const regs = chip.registers; pub usingnamespace chip; +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + // Default clock frequencies after reset, see top comment for calculation -// TODO: these would need to change when we support multiple clock configurations -pub const ahb_frequency = 16_000_000; -pub const apb1_frequency = 16_000_000; -pub const apb2_frequency = 16_000_000; +pub const clock_frequencies = .{ + .cpu = 16_000_000, + .ahb = 16_000_000, + .apb1 = 16_000_000, + .apb2 = 16_000_000, +}; pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; @@ -227,7 +238,7 @@ pub fn Uart(comptime index: usize) type { // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling). // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) // TODO: Do a rounding div, instead of a truncating div? - const usartdiv = @intCast(u16, @divTrunc(apb1_frequency, config.baud_rate)); + const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate)); @field(regs, usart_name).BRR.raw = usartdiv; // enable USART, and its transmitter and receiver diff --git a/src/modules/chips/stm32f429/stm32f429.zig b/src/modules/chips/stm32f429/stm32f429.zig index 737a83f..d40d92b 100644 --- a/src/modules/chips/stm32f429/stm32f429.zig +++ b/src/modules/chips/stm32f429/stm32f429.zig @@ -27,6 +27,23 @@ const regs = chip.registers; pub usingnamespace chip; +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + +// Default clock frequencies after reset, see top comment for calculation +pub const clock_frequencies = .{ + .cpu = 16_000_000, + .ahb = 16_000_000, + .apb1 = 16_000_000, + .apb2 = 16_000_000, +}; + pub fn parsePin(comptime spec: []const u8) type { const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; From 7cfc924eed89307944d0cc85d54f68de2895e4a8 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Sun, 3 Jul 2022 17:38:40 +0200 Subject: [PATCH 058/138] pin: omit board/chip namespace when parsing and saving the pin name (#55) board: and chip: can be prefixed to the pin to force using a pin defined in the board or in the chip. Currently though, neither chips or boards are handling this prefix. Since this is just used to give priority when parsing the pin, this commit removes the namespace from the spec passed to parsePin. This isolates the namespace handling to the Pin type creation, without having to handle it in chips and boards. --- src/core/pin.zig | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/core/pin.zig b/src/core/pin.zig index b46962e..1bd4868 100644 --- a/src/core/pin.zig +++ b/src/core/pin.zig @@ -13,18 +13,30 @@ const board = @import("board"); pub fn Pin(comptime spec: []const u8) type { // TODO: Depened on board and chip here - // Pins can be namespaced with "Board:" for board and "Chip:" for chip - const pin = if (std.mem.startsWith(u8, spec, "board:")) - chip.parsePin(@field(board.pin_map, spec)) - else if (std.mem.startsWith(u8, spec, "chip:")) - chip.parsePin(spec) + const board_namespace = "board:"; + const chip_namespace = "chip:"; + + // Pins can be namespaced with "board:" for board and "chip:" for chip + // These namespaces are not passed to chip.parsePin + const pin = if (std.mem.startsWith(u8, spec, board_namespace)) + chip.parsePin(@field(board.pin_map, spec[board_namespace.len..])) + else if (std.mem.startsWith(u8, spec, chip_namespace)) + chip.parsePin(spec[chip_namespace.len..]) else if (micro.config.has_board and @hasField(@TypeOf(board.pin_map), spec)) chip.parsePin(@field(board.pin_map, spec)) else chip.parsePin(spec); return struct { - pub const name = spec; + pub const name = if (std.mem.startsWith(u8, spec, board_namespace.len)) + // Remove the board: prefix + spec[board_namespace.len..] + else if (std.mem.startsWith(u8, spec, chip_namespace)) + // Remove the chip: prefix + spec[chip_namespace.len..] + else + spec; + pub const source_pin = pin; pub fn route(target: pin.Targets) void { From 5cf1a4612dbe7471af348341fb54245ab840b006 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Sun, 3 Jul 2022 17:42:46 +0200 Subject: [PATCH 059/138] uart: allow selecting the tx/rx pins (#54) Some microcontrollers allow routing multiple pins to the same UART peripheral. This commit allows selecting specific pins on these platforms. --- src/core/uart.zig | 13 ++- .../stm32f3discovery/stm32f3discovery.zig | 2 +- src/modules/chips/atmega328p/atmega328p.zig | 5 +- src/modules/chips/lpc1768/lpc1768.zig | 5 +- src/modules/chips/stm32f303/stm32f303.zig | 4 +- src/modules/chips/stm32f407/stm32f407.zig | 82 ++++++++++++++++--- tests/uart-sync.zig | 22 +++-- 7 files changed, 108 insertions(+), 25 deletions(-) diff --git a/src/core/uart.zig b/src/core/uart.zig index f84d2dc..13b1485 100644 --- a/src/core/uart.zig +++ b/src/core/uart.zig @@ -2,8 +2,8 @@ const std = @import("std"); const micro = @import("microzig.zig"); const chip = @import("chip"); -pub fn Uart(comptime index: usize) type { - const SystemUart = chip.Uart(index); +pub fn Uart(comptime index: usize, comptime pins: Pins) type { + const SystemUart = chip.Uart(index, pins); return struct { const Self = @This(); @@ -63,7 +63,14 @@ pub fn Uart(comptime index: usize) type { }; } -/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the +/// The pin configuration. This is used to optionally configure specific pins to be used with the chosen UART. +/// This makes sense only with microcontrollers supporting multiple pins for a UART peripheral. +pub const Pins = struct { + tx: ?type = null, + rx: ?type = null, +}; + +/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the /// most common serial format. pub const Config = struct { /// TODO: Make this optional, to support STM32F303 et al. auto baud-rate detection? diff --git a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig index 995e8a5..56d249e 100644 --- a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig +++ b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig @@ -25,7 +25,7 @@ pub const pin_map = .{ }; pub fn debugWrite(string: []const u8) void { - const uart1 = micro.Uart(1).getOrInit(.{ + const uart1 = micro.Uart(1, .{}).getOrInit(.{ .baud_rate = 9600, .data_bits = .eight, .parity = null, diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 9375a6d..0a24481 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -94,8 +94,11 @@ pub const uart = struct { }; }; -pub fn Uart(comptime index: usize) type { +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { if (index != 0) @compileError("Atmega328p only has a single uart!"); + if (pins.tx != null or pins.rx != null) + @compileError("Atmega328p has fixed pins for uart!"); + return struct { const Self = @This(); diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig index 93a88a4..9239317 100644 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ b/src/modules/chips/lpc1768/lpc1768.zig @@ -115,7 +115,10 @@ pub const uart = struct { }; }; -pub fn Uart(comptime index: usize) type { +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (pins.tx != null or pins.rx != null) + @compileError("TODO: custom pins are not currently supported"); + return struct { const UARTn = switch (index) { 0 => regs.UART0, diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 4b8ff37..35bc5ac 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -132,8 +132,10 @@ pub const uart = struct { }; }; -pub fn Uart(comptime index: usize) type { +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { if (!(index == 1)) @compileError("TODO: only USART1 is currently supported"); + if (pins.tx != null or pins.rx != null) + @compileError("TODO: custom pins are not currently supported"); return struct { parity_read_mask: u8, diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index 17f4039..724e410 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -154,29 +154,85 @@ pub const uart = struct { even = 0, odd = 1, }; + + const PinDirection = std.meta.FieldEnum(micro.uart.Pins); + + /// Checks if a pin is valid for a given uart index and direction + pub fn isValidPin(comptime pin: type, comptime index: usize, comptime direction: PinDirection) bool { + const pin_name = pin.name; + + return switch (direction) { + .tx => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PA9") or std.mem.eql(u8, pin_name, "PB6"), + 2 => std.mem.eql(u8, pin_name, "PA2") or std.mem.eql(u8, pin_name, "PD5"), + 3 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PC10") or std.mem.eql(u8, pin_name, "PD8"), + 4 => std.mem.eql(u8, pin_name, "PA0") or std.mem.eql(u8, pin_name, "PC10"), + 5 => std.mem.eql(u8, pin_name, "PC12"), + 6 => std.mem.eql(u8, pin_name, "PC6") or std.mem.eql(u8, pin_name, "PG14"), + else => unreachable, + }, + // Valid RX pins for the UARTs + .rx => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PA10") or std.mem.eql(u8, pin_name, "PB7"), + 2 => std.mem.eql(u8, pin_name, "PA3") or std.mem.eql(u8, pin_name, "PD6"), + 3 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PC11") or std.mem.eql(u8, pin_name, "PD9"), + 4 => std.mem.eql(u8, pin_name, "PA1") or std.mem.eql(u8, pin_name, "PC11"), + 5 => std.mem.eql(u8, pin_name, "PD2"), + 6 => std.mem.eql(u8, pin_name, "PC7") or std.mem.eql(u8, pin_name, "PG9"), + else => unreachable, + }, + }; + } }; -pub fn Uart(comptime index: usize) type { +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { if (index < 1 or index > 6) @compileError("Valid USART index are 1..6"); const usart_name = std.fmt.comptimePrint("USART{d}", .{index}); - // TODO: support alternative pins - const pins = switch (index) { - 1 => .{ .tx = micro.Pin("PA9"), .rx = micro.Pin("PA10") }, - 2 => .{ .tx = micro.Pin("PA2"), .rx = micro.Pin("PA3") }, - 3 => .{ .tx = micro.Pin("PD8"), .rx = micro.Pin("PD9") }, - 4 => .{ .tx = micro.Pin("PC10"), .rx = micro.Pin("PC11") }, - 5 => .{ .tx = micro.Pin("PC12"), .rx = micro.Pin("PD2") }, - 6 => .{ .tx = micro.Pin("PC6"), .rx = micro.Pin("PC7") }, + const tx_pin = + if (pins.tx) |tx| + if (uart.isValidPin(tx, index, .tx)) + tx + else + @compileError(std.fmt.comptimePrint("Tx pin {s} is not valid for UART{}", .{ tx.name, index })) + else switch (index) { + // Provide default tx pins if no pin is specified + 1 => micro.Pin("PA9"), + 2 => micro.Pin("PA2"), + 3 => micro.Pin("PB10"), + 4 => micro.Pin("PA0"), + 5 => micro.Pin("PC12"), + 6 => micro.Pin("PC6"), else => unreachable, }; - const tx_gpio = micro.Gpio(pins.tx, .{ + + const rx_pin = + if (pins.rx) |rx| + if (uart.isValidPin(rx, index, .rx)) + rx + else + @compileError(std.fmt.comptimePrint("Rx pin {s} is not valid for UART{}", .{ rx.name, index })) + else switch (index) { + // Provide default rx pins if no pin is specified + 1 => micro.Pin("PA10"), + 2 => micro.Pin("PA3"), + 3 => micro.Pin("PB11"), + 4 => micro.Pin("PA1"), + 5 => micro.Pin("PD2"), + 6 => micro.Pin("PC7"), + else => unreachable, + }; + + // USART1..3 are AF7, USART 4..6 are AF8 + const alternate_function = if (index <= 3) .af7 else .af8; + + const tx_gpio = micro.Gpio(tx_pin, .{ .mode = .alternate_function, - .alternate_function = .af7, + .alternate_function = alternate_function, }); - const rx_gpio = micro.Gpio(pins.rx, .{ + const rx_gpio = micro.Gpio(rx_pin, .{ .mode = .alternate_function, - .alternate_function = .af7, + .alternate_function = alternate_function, }); return struct { diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 696095b..83378a9 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -3,13 +3,25 @@ const micro = @import("microzig"); // Configures the led_pin and uart index const cfg = if (micro.config.has_board) switch (micro.config.board_name) { - .@"mbed LPC1768" => .{ .led_pin = micro.Pin("LED-1"), .uart_idx = 1 }, - .@"STM32F3DISCOVERY" => .{ .led_pin = micro.Pin("LD3"), .uart_idx = 1 }, - .@"STM32F4DISCOVERY" => .{ .led_pin = micro.Pin("LD5"), .uart_idx = 2 }, + .@"mbed LPC1768" => .{ + .led_pin = micro.Pin("LED-1"), + .uart_idx = 1, + .pins = .{}, + }, + .@"STM32F3DISCOVERY" => .{ + .led_pin = micro.Pin("LD3"), + .uart_idx = 1, + .pins = .{}, + }, + .@"STM32F4DISCOVERY" => .{ + .led_pin = micro.Pin("LD5"), + .uart_idx = 2, + .pins = .{ .tx = micro.Pin("PA2"), .rx = micro.Pin("PA3") }, + }, else => @compileError("unknown board"), } else switch (micro.config.chip_name) { - .@"NXP LPC1768" => .{ .led_pin = micro.Pin("P1.18"), .uart_idx = 1 }, + .@"NXP LPC1768" => .{ .led_pin = micro.Pin("P1.18"), .uart_idx = 1, .pins = .{} }, else => @compileError("unknown chip"), }; @@ -20,7 +32,7 @@ pub fn main() !void { }); led.init(); - var uart = micro.Uart(cfg.uart_idx).init(.{ + var uart = micro.Uart(cfg.uart_idx, cfg.pins).init(.{ .baud_rate = 9600, .stop_bits = .one, .parity = null, From e202698a0051aa40fc3e91501f624c895f4f82d8 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Wed, 6 Jul 2022 22:46:28 +0200 Subject: [PATCH 060/138] pin: remove erroneous access to slice length (#56) The slice itself has to be used instead --- src/core/pin.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/core/pin.zig b/src/core/pin.zig index 1bd4868..5fccbaf 100644 --- a/src/core/pin.zig +++ b/src/core/pin.zig @@ -28,7 +28,7 @@ pub fn Pin(comptime spec: []const u8) type { chip.parsePin(spec); return struct { - pub const name = if (std.mem.startsWith(u8, spec, board_namespace.len)) + pub const name = if (std.mem.startsWith(u8, spec, board_namespace)) // Remove the board: prefix spec[board_namespace.len..] else if (std.mem.startsWith(u8, spec, chip_namespace)) From 7cf623aaf209cadf6c34726edca3d865dd333f21 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Wed, 6 Jul 2022 23:57:23 +0200 Subject: [PATCH 061/138] stm32f407: use the correct bus frequency to calculate usartdiv (#57) USARTs 1 and 6 are clocked by APB2 --- src/modules/chips/stm32f407/stm32f407.zig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index 724e410..b11a69a 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -294,7 +294,13 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling). // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) // TODO: Do a rounding div, instead of a truncating div? - const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate)); + const clocks = micro.clock.get(); + const bus_frequency = switch (index) { + 1, 6 => clocks.apb2, + 2...5 => clocks.apb1, + else => unreachable, + }; + const usartdiv = @intCast(u16, @divTrunc(bus_frequency, config.baud_rate)); @field(regs, usart_name).BRR.raw = usartdiv; // enable USART, and its transmitter and receiver From a400e3605859c7926d313bcf507114a894593777 Mon Sep 17 00:00:00 2001 From: Riccardo Binetti Date: Thu, 7 Jul 2022 00:49:09 +0200 Subject: [PATCH 062/138] I2C improvements (#58) * i2c: pass a config to init For now, allow setting the i2c target speed * i2c: allow selecting the scl/sda pins Similar to the previous commit for uart, this allows specifying the pins for microcontrollers that support multiple pins for a single i2c peripheral * stm32f407: add support for i2c Supports using all I2C peripherals with all their pins in standard mode (fast mode support will be added in the future). --- src/core/i2c.zig | 27 ++- src/modules/chips/stm32f303/stm32f303.zig | 8 +- src/modules/chips/stm32f407/stm32f407.zig | 262 ++++++++++++++++++++++ 3 files changed, 290 insertions(+), 7 deletions(-) diff --git a/src/core/i2c.zig b/src/core/i2c.zig index 5cc651c..48a23b4 100644 --- a/src/core/i2c.zig +++ b/src/core/i2c.zig @@ -2,8 +2,8 @@ const std = @import("std"); const micro = @import("microzig.zig"); const chip = @import("chip"); -pub fn I2CController(comptime index: usize) type { - const SystemI2CController = chip.I2CController(index); +pub fn I2CController(comptime index: usize, comptime pins: Pins) type { + const SystemI2CController = chip.I2CController(index, pins); const I2CDevice = struct { const Device = @This(); @@ -129,9 +129,9 @@ pub fn I2CController(comptime index: usize) type { internal: SystemI2CController, - pub fn init() InitError!Self { + pub fn init(config: Config) InitError!Self { return Self{ - .internal = try SystemI2CController.init(), + .internal = try SystemI2CController.init(config), }; } @@ -141,7 +141,24 @@ pub fn I2CController(comptime index: usize) type { }; } -pub const InitError = error{}; +/// The pin configuration. This is used to optionally configure specific pins to be used with the chosen I2C. +/// This makes sense only with microcontrollers supporting multiple pins for an I2C peripheral. +pub const Pins = struct { + scl: ?type = null, + sda: ?type = null, +}; + +/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the +/// most common serial format. +pub const Config = struct { + /// The target speed in bit/s. Note that the actual speed can differ from this, due to prescaler rounding. + target_speed: u32, +}; + +pub const InitError = error{ + InvalidBusFrequency, + InvalidSpeed, +}; pub const WriteError = error{}; pub const ReadError = error{ EndOfStream, diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index 35bc5ac..a80a6a6 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -265,13 +265,17 @@ fn debugPrint(comptime format: []const u8, args: anytype) void { } /// This implementation does not use AUTOEND=1 -pub fn I2CController(comptime index: usize) type { +pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported"); + if (pins.scl != null or pins.sda != null) + @compileError("TODO: custom pins are not currently supported"); return struct { const Self = @This(); - pub fn init() !Self { + pub fn init(config: micro.i2c.Config) !Self { + // TODO: use config + _ = config; // CONFIGURE I2C1 // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA, // if GPIO port B is configured for alternate function 4 for these PB pins. diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index b11a69a..c07582c 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -362,3 +362,265 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { } }; } + +pub const i2c = struct { + const PinLine = std.meta.FieldEnum(micro.i2c.Pins); + + /// Checks if a pin is valid for a given i2c index and line + pub fn isValidPin(comptime pin: type, comptime index: usize, comptime line: PinLine) bool { + const pin_name = pin.name; + + return switch (line) { + .scl => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PB6") or std.mem.eql(u8, pin_name, "PB8"), + 2 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PF1") or std.mem.eql(u8, pin_name, "PH4"), + 3 => std.mem.eql(u8, pin_name, "PA8") or std.mem.eql(u8, pin_name, "PH7"), + else => unreachable, + }, + // Valid RX pins for the UARTs + .sda => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PB7") or std.mem.eql(u8, pin_name, "PB9"), + 2 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PF0") or std.mem.eql(u8, pin_name, "PH5"), + 3 => std.mem.eql(u8, pin_name, "PC9") or std.mem.eql(u8, pin_name, "PH8"), + else => unreachable, + }, + }; + } +}; + +pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { + if (index < 1 or index > 3) @compileError("Valid I2C index are 1..3"); + + const i2c_name = std.fmt.comptimePrint("I2C{d}", .{index}); + const scl_pin = + if (pins.scl) |scl| + if (uart.isValidPin(scl, index, .scl)) + scl + else + @compileError(std.fmt.comptimePrint("SCL pin {s} is not valid for I2C{}", .{ scl.name, index })) + else switch (index) { + // Provide default scl pins if no pin is specified + 1 => micro.Pin("PB6"), + 2 => micro.Pin("PB10"), + 3 => micro.Pin("PA8"), + else => unreachable, + }; + + const sda_pin = + if (pins.sda) |sda| + if (uart.isValidPin(sda, index, .sda)) + sda + else + @compileError(std.fmt.comptimePrint("SDA pin {s} is not valid for UART{}", .{ sda.name, index })) + else switch (index) { + // Provide default sda pins if no pin is specified + 1 => micro.Pin("PB7"), + 2 => micro.Pin("PB11"), + 3 => micro.Pin("PC9"), + else => unreachable, + }; + + const scl_gpio = micro.Gpio(scl_pin, .{ + .mode = .alternate_function, + .alternate_function = .af4, + }); + const sda_gpio = micro.Gpio(sda_pin, .{ + .mode = .alternate_function, + .alternate_function = .af4, + }); + + // Base field of the specific I2C peripheral + const i2c_base = @field(regs, i2c_name); + + return struct { + const Self = @This(); + + pub fn init(config: micro.i2c.Config) !Self { + // Configure I2C + + // 1. Enable the I2C CLOCK and GPIO CLOCK + regs.RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); + regs.RCC.AHB1ENR.modify(.{ .GPIOBEN = 1 }); + + // 2. Configure the I2C PINs + // This takes care of setting them alternate function mode with the correct AF + scl_gpio.init(); + sda_gpio.init(); + + // TODO: the stuff below will probably use the microzig gpio API in the future + const scl = scl_pin.source_pin; + const sda = sda_pin.source_pin; + // Select Open Drain Output + setRegField(@field(scl.gpio_port, "OTYPER"), "OT" ++ scl.suffix, 1); + setRegField(@field(sda.gpio_port, "OTYPER"), "OT" ++ sda.suffix, 1); + // Select High Speed + setRegField(@field(scl.gpio_port, "OSPEEDR"), "OSPEEDR" ++ scl.suffix, 0b10); + setRegField(@field(sda.gpio_port, "OSPEEDR"), "OSPEEDR" ++ sda.suffix, 0b10); + // Activate Pull-up + setRegField(@field(scl.gpio_port, "PUPDR"), "PUPDR" ++ scl.suffix, 0b01); + setRegField(@field(sda.gpio_port, "PUPDR"), "PUPDR" ++ sda.suffix, 0b01); + + // 3. Reset the I2C + i2c_base.CR1.modify(.{ .PE = 0 }); + while (i2c_base.CR1.read().PE == 1) {} + + // 4. Configure I2C timing + const bus_frequency_hz = micro.clock.get().apb1; + const bus_frequency_mhz: u6 = @intCast(u6, @divExact(bus_frequency_hz, 1_000_000)); + + if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) { + return error.InvalidBusFrequency; + } + + // .FREQ is set to the bus frequency in Mhz + i2c_base.CR2.modify(.{ .FREQ = bus_frequency_mhz }); + + switch (config.target_speed) { + 10_000...100_000 => { + // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed. + const ccr = @intCast(u12, @divFloor(bus_frequency_hz, config.target_speed * 2)); + i2c_base.CCR.modify(.{ .CCR = ccr }); + // Trise is bus frequency in Mhz + 1 + i2c_base.TRISE.modify(bus_frequency_mhz + 1); + }, + 100_001...400_000 => { + // TODO: handle fast mode + return error.InvalidSpeed; + }, + else => return error.InvalidSpeed, + } + + // 5. Program the I2C_CR1 register to enable the peripheral + i2c_base.CR1.modify(.{ .PE = 1 }); + + return Self{}; + } + + pub const WriteState = struct { + address: u7, + buffer: [255]u8 = undefined, + buffer_size: u8 = 0, + + pub fn start(address: u7) !WriteState { + return WriteState{ .address = address }; + } + + pub fn writeAll(self: *WriteState, bytes: []const u8) !void { + std.debug.assert(self.buffer_size < 255); + for (bytes) |b| { + self.buffer[self.buffer_size] = b; + self.buffer_size += 1; + if (self.buffer_size == 255) { + try self.sendBuffer(); + } + } + } + + fn sendBuffer(self: *WriteState) !void { + if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); + + // Wait for the bus to be free + while (i2c_base.SR2.read().BUSY == 1) {} + + // Send start + i2c_base.CR1.modify(.{ .START = 1 }); + + // Wait for the end of the start condition, master mode selected, and BUSY bit set + while ((i2c_base.SR1.read().SB == 0 or + i2c_base.SR2.read().MSL == 0 or + i2c_base.SR2.read().BUSY == 0)) + {} + + // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation + i2c_base.DR.modify(@intCast(u8, self.address) << 1); + + // Wait for address confirmation + while (i2c_base.SR1.read().ADDR == 0) {} + + // Read SR2 to clear address condition + _ = i2c_base.SR2.read(); + + for (self.buffer[0..self.buffer_size]) |b| { + // Write data byte + i2c_base.DR.modify(b); + // Wait for transfer finished + while (i2c_base.SR1.read().BTF == 0) {} + } + self.buffer_size = 0; + } + + pub fn stop(self: *WriteState) !void { + try self.sendBuffer(); + // Communication STOP + i2c_base.CR1.modify(.{ .STOP = 1 }); + while (i2c_base.SR2.read().BUSY == 1) {} + } + + pub fn restartRead(self: *WriteState) !ReadState { + try self.sendBuffer(); + return ReadState{ .address = self.address }; + } + pub fn restartWrite(self: *WriteState) !WriteState { + try self.sendBuffer(); + return WriteState{ .address = self.address }; + } + }; + + pub const ReadState = struct { + address: u7, + + pub fn start(address: u7) !ReadState { + return ReadState{ .address = address }; + } + + /// Fails with ReadError if incorrect number of bytes is received. + pub fn readNoEof(self: *ReadState, buffer: []u8) !void { + std.debug.assert(buffer.len < 256); + + // Send start and enable ACK + i2c_base.CR1.modify(.{ .START = 1, .ACK = 1 }); + + // Wait for the end of the start condition, master mode selected, and BUSY bit set + while ((i2c_base.SR1.read().SB == 0 or + i2c_base.SR2.read().MSL == 0 or + i2c_base.SR2.read().BUSY == 0)) + {} + + // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation + i2c_base.DR.modify((@intCast(u8, self.address) << 1) | 1); + + // Wait for address confirmation + while (i2c_base.SR1.read().ADDR == 0) {} + + // Read SR2 to clear address condition + _ = i2c_base.SR2.read(); + + for (buffer) |_, i| { + if (i == buffer.len - 1) { + // Disable ACK + i2c_base.CR1.modify(.{ .ACK = 0 }); + } + + // Wait for data to be received + while (i2c_base.SR1.read().RxNE == 0) {} + + // Read data byte + buffer[i] = i2c_base.DR.read(); + } + } + + pub fn stop(_: *ReadState) !void { + // Communication STOP + i2c_base.CR1.modify(.{ .STOP = 1 }); + while (i2c_base.SR2.read().BUSY == 1) {} + } + + pub fn restartRead(self: *ReadState) !ReadState { + return ReadState{ .address = self.address }; + } + pub fn restartWrite(self: *ReadState) !WriteState { + return WriteState{ .address = self.address }; + } + }; + }; +} From 179047ab6542d1042bac16444bf400aa7e6d992d Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 7 Jul 2022 23:00:18 -0700 Subject: [PATCH 063/138] fix colliding ISRs by making sure they each get memoized (#60) * fix colliding ISRs by making sure they each get memoized * add change from regz codegen --- src/core/microzig.zig | 17 +++++++- src/modules/chips/atmega328p/registers.zig | 20 +-------- src/modules/chips/lpc1768/registers.zig | 12 +++--- src/modules/chips/nrf52/registers.zig | 34 +--------------- src/modules/chips/stm32f103/registers.zig | 2 +- src/modules/chips/stm32f303/registers.zig | 2 +- src/modules/chips/stm32f407/registers.zig | 3 +- src/modules/chips/stm32f429/registers.zig | 3 +- src/modules/cpus/cortex-m/cortex-m.zig | 47 ++++++++++++++-------- 9 files changed, 58 insertions(+), 82 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 0353d35..aab89b8 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -68,7 +68,22 @@ usingnamespace if (@hasDecl(app, "log")) pub const log = app.log; } else - struct {}; + struct { + // log is a no-op by default. Parts of microzig use the stdlib logging + // facility and compilations will now fail on freestanding systems that + // use it but do not explicitly set `root.log` + pub fn log( + comptime message_level: std.log.Level, + comptime scope: @Type(.EnumLiteral), + comptime format: []const u8, + args: anytype, + ) void { + _ = message_level; + _ = scope; + _ = format; + _ = args; + } + }; /// The microzig default panic handler. Will disable interrupts and loop endlessly. pub fn microzig_panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { diff --git a/src/modules/chips/atmega328p/registers.zig b/src/modules/chips/atmega328p/registers.zig index 0c27f21..53e47b2 100644 --- a/src/modules/chips/atmega328p/registers.zig +++ b/src/modules/chips/atmega328p/registers.zig @@ -61,10 +61,8 @@ pub const VectorTable = extern struct { }; pub const registers = struct { - /// Fuses pub const FUSE = struct { - /// address: 0x2 pub const EXTENDED = @intToPtr(*volatile Mmio(8, packed struct { /// Brown-out Detector trigger level @@ -173,7 +171,6 @@ pub const registers = struct { /// Lockbits pub const LOCKBIT = struct { - /// address: 0x0 pub const LOCKBIT = @intToPtr(*volatile Mmio(8, packed struct { /// Memory Lock @@ -203,7 +200,6 @@ pub const registers = struct { /// USART pub const USART0 = struct { - /// address: 0xc6 /// USART I/O Data Register pub const UDR0 = @intToPtr(*volatile u8, 0xc6); @@ -284,7 +280,6 @@ pub const registers = struct { /// Two Wire Serial Interface pub const TWI = struct { - /// address: 0xbd /// TWI (Slave) Address Mask Register pub const TWAMR = @intToPtr(*volatile Mmio(8, packed struct { @@ -347,7 +342,6 @@ pub const registers = struct { /// Timer/Counter, 16-bit pub const TC1 = struct { - /// address: 0x6f /// Timer/Counter Interrupt Mask Register pub const TIMSK1 = @intToPtr(*volatile Mmio(8, packed struct { @@ -465,7 +459,6 @@ pub const registers = struct { /// Timer/Counter, 8-bit Async pub const TC2 = struct { - /// address: 0x70 /// Timer/Counter Interrupt Mask register pub const TIMSK2 = @intToPtr(*volatile Mmio(8, packed struct { @@ -585,7 +578,6 @@ pub const registers = struct { /// Analog-to-Digital Converter pub const ADC = struct { - /// address: 0x7c /// The ADC multiplexer Selection Register pub const ADMUX = @intToPtr(*volatile Mmio(8, packed struct { @@ -682,7 +674,6 @@ pub const registers = struct { /// Analog Comparator pub const AC = struct { - /// address: 0x50 /// Analog Comparator Control And Status Register pub const ACSR = @intToPtr(*volatile Mmio(8, packed struct { @@ -725,7 +716,6 @@ pub const registers = struct { /// I/O Port pub const PORTB = struct { - /// address: 0x25 /// Port B Data Register pub const PORTB = @intToPtr(*volatile u8, 0x25); @@ -741,7 +731,6 @@ pub const registers = struct { /// I/O Port pub const PORTC = struct { - /// address: 0x28 /// Port C Data Register pub const PORTC = @intToPtr(*volatile u7, 0x28); @@ -757,7 +746,6 @@ pub const registers = struct { /// I/O Port pub const PORTD = struct { - /// address: 0x2b /// Port D Data Register pub const PORTD = @intToPtr(*volatile u8, 0x2b); @@ -773,7 +761,6 @@ pub const registers = struct { /// Timer/Counter, 8-bit pub const TC0 = struct { - /// address: 0x48 /// Timer/Counter0 Output Compare Register pub const OCR0B = @intToPtr(*volatile u8, 0x48); @@ -872,7 +859,6 @@ pub const registers = struct { /// External Interrupts pub const EXINT = struct { - /// address: 0x69 /// External Interrupt Control Register pub const EICRA = @intToPtr(*volatile Mmio(8, packed struct { @@ -971,7 +957,6 @@ pub const registers = struct { /// Serial Peripheral Interface pub const SPI = struct { - /// address: 0x4e /// SPI Data Register pub const SPDR = @intToPtr(*volatile u8, 0x4e); @@ -1019,7 +1004,6 @@ pub const registers = struct { /// Watchdog Timer pub const WDT = struct { - /// address: 0x60 /// Watchdog Timer Control Register pub const WDTCSR = @intToPtr(*volatile Mmio(8, packed struct { @@ -1040,7 +1024,6 @@ pub const registers = struct { /// CPU Registers pub const CPU = struct { - /// address: 0x64 /// Power Reduction Register pub const PRR = @intToPtr(*volatile Mmio(8, packed struct { @@ -1202,7 +1185,6 @@ pub const registers = struct { /// EEPROM pub const EEPROM = struct { - /// address: 0x41 /// EEPROM Address Register Bytes pub const EEAR = @intToPtr(*volatile u10, 0x41); @@ -1312,7 +1294,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 12d3ba1..0cd697c 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -647,7 +647,7 @@ pub const registers = struct { /// characters must be written before an interrupt or DMA request is activated. RXTRIGLVL: u2, /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, + RESERVED0: u8, RESERVED1: u16, }), base_address + 0x8); @@ -8703,7 +8703,7 @@ pub const registers = struct { PLLC0: u1, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - RESERVED: u30=0, + RESERVED: u30 = 0, }), base_address + 0x80); /// address: 0x400fc084 @@ -9036,7 +9036,7 @@ pub const registers = struct { CLKSRC: u2, /// Reserved, user software should not write ones to reserved bits. The value read /// from a reserved bit is not defined. - RESERVED: u30=0, + RESERVED: u30 = 0, }), base_address + 0x10c); /// address: 0x400fc110 @@ -9238,7 +9238,7 @@ pub const registers = struct { /// Peripheral clock selection for I2C1. PCLK_I2C1: u2, /// Reserved. - RESERVED0: u2=1, + RESERVED0: u2 = 1, /// Peripheral clock selection for SSP0. PCLK_SSP0: u2, /// Peripheral clock selection for TIMER2. @@ -9254,7 +9254,7 @@ pub const registers = struct { /// Peripheral clock selection for I2S. PCLK_I2S: u2, /// Reserved. - RESERVED1: u2=1, + RESERVED1: u2 = 1, /// Peripheral clock selection for Repetitive Interrupt Timer. PCLK_RIT: u2, /// Peripheral clock selection for the System Control block. @@ -18796,7 +18796,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig index 617e52f..a2333fd 100644 --- a/src/modules/chips/nrf52/registers.zig +++ b/src/modules/chips/nrf52/registers.zig @@ -93,7 +93,6 @@ pub const registers = struct { /// Device info pub const INFO = struct { - /// address: 0x10000000 /// Part code pub const PART = @intToPtr(*volatile u32, base_address + 0x0); @@ -121,7 +120,6 @@ pub const registers = struct { /// Registers storing factory TEMP module linearization coefficients pub const TEMP = struct { - /// address: 0x10000000 /// Slope definition A0. pub const A0 = @intToPtr(*volatile Mmio(32, packed struct { @@ -591,7 +589,6 @@ pub const registers = struct { }; pub const NFC = struct { - /// address: 0x10000000 /// Default header for NFC Tag. Software can read these values to populate /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. @@ -2896,7 +2893,6 @@ pub const registers = struct { }), base_address + 0x56c); pub const PSEL = struct { - /// address: 0x40002000 /// Pin select for RTS signal pub const RTS = @intToPtr(*volatile Mmio(32, packed struct { @@ -3040,7 +3036,6 @@ pub const registers = struct { /// RXD EasyDMA channel pub const RXD = struct { - /// address: 0x40002000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -3056,7 +3051,6 @@ pub const registers = struct { /// TXD EasyDMA channel pub const TXD = struct { - /// address: 0x40002000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -3569,7 +3563,6 @@ pub const registers = struct { pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); pub const PSEL = struct { - /// address: 0x40003000 /// Pin select for SCK pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { @@ -3678,7 +3671,6 @@ pub const registers = struct { /// RXD EasyDMA channel pub const RXD = struct { - /// address: 0x40003000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -3698,7 +3690,6 @@ pub const registers = struct { /// TXD EasyDMA channel pub const TXD = struct { - /// address: 0x40003000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -3954,7 +3945,6 @@ pub const registers = struct { pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); pub const PSEL = struct { - /// address: 0x40003000 /// Pin select for SCK pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { @@ -4097,7 +4087,6 @@ pub const registers = struct { }; pub const RXD = struct { - /// address: 0x40003000 /// RXD data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -4112,7 +4101,6 @@ pub const registers = struct { }; pub const TXD = struct { - /// address: 0x40003000 /// TXD data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -4406,7 +4394,6 @@ pub const registers = struct { pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); pub const PSEL = struct { - /// address: 0x40003000 /// Pin select for SCL signal pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { @@ -4480,7 +4467,6 @@ pub const registers = struct { /// RXD EasyDMA channel pub const RXD = struct { - /// address: 0x40003000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -4500,7 +4486,6 @@ pub const registers = struct { /// TXD EasyDMA channel pub const TXD = struct { - /// address: 0x40003000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -4831,7 +4816,6 @@ pub const registers = struct { pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); pub const PSEL = struct { - /// address: 0x40003000 /// Pin select for SCL signal pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { @@ -4905,7 +4889,6 @@ pub const registers = struct { /// RXD EasyDMA channel pub const RXD = struct { - /// address: 0x40003000 /// RXD Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -4921,7 +4904,6 @@ pub const registers = struct { /// TXD EasyDMA channel pub const TXD = struct { - /// address: 0x40003000 /// TXD Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -5076,7 +5058,6 @@ pub const registers = struct { }), base_address + 0x554); pub const PSEL = struct { - /// address: 0x40003000 /// Pin select for SCK pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { @@ -7289,7 +7270,6 @@ pub const registers = struct { }), base_address + 0x5a4); pub const FRAMESTATUS = struct { - /// address: 0x40005000 /// Result of last incoming frames pub const RX = @intToPtr(*volatile Mmio(32, packed struct { @@ -7332,7 +7312,6 @@ pub const registers = struct { }; pub const TXD = struct { - /// address: 0x40005000 /// Configuration of outgoing frames pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { @@ -7407,7 +7386,6 @@ pub const registers = struct { }; pub const RXD = struct { - /// address: 0x40005000 /// Configuration of incoming frames pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { @@ -8002,7 +7980,6 @@ pub const registers = struct { /// RESULT EasyDMA channel pub const RESULT = struct { - /// address: 0x40007000 /// Data pointer pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); @@ -10333,7 +10310,6 @@ pub const registers = struct { pub const ACCDBLREAD = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x548); pub const PSEL = struct { - /// address: 0x40012000 /// Pin select for LED signal pub const LED = @intToPtr(*volatile Mmio(32, packed struct { @@ -12739,7 +12715,6 @@ pub const registers = struct { }, base_address + 0x520); pub const PSEL = struct { - /// address: 0x4001c000 /// Description collection[0]: Output pin select for PWM channel 0 pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct { @@ -12980,7 +12955,6 @@ pub const registers = struct { pub const GAINR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); pub const PSEL = struct { - /// address: 0x4001d000 /// Pin number configuration for PDM CLK signal pub const CLK = @intToPtr(*volatile Mmio(32, packed struct { @@ -13053,7 +13027,6 @@ pub const registers = struct { }; pub const SAMPLE = struct { - /// address: 0x4001d000 /// RAM address pointer to write samples to with EasyDMA pub const PTR = @intToPtr(*volatile Mmio(32, packed struct { @@ -15873,7 +15846,6 @@ pub const registers = struct { pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); pub const CONFIG = struct { - /// address: 0x40025000 /// I2S mode. pub const MODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); @@ -15916,28 +15888,24 @@ pub const registers = struct { }; pub const RXD = struct { - /// address: 0x40025000 /// Receive buffer RAM start address. pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); }; pub const TXD = struct { - /// address: 0x40025000 /// Transmit buffer RAM start address. pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); }; pub const RXTXD = struct { - /// address: 0x40025000 /// Size of RXD and TXD buffers. pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x0); }; pub const PSEL = struct { - /// address: 0x40025000 /// Pin select for MCK signal. pub const MCK = @intToPtr(*volatile Mmio(32, packed struct { @@ -16833,7 +16801,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 10d7649..1edfad7 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -23541,7 +23541,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index 64ff216..a4bf055 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -34397,7 +34397,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/stm32f407/registers.zig b/src/modules/chips/stm32f407/registers.zig index 7e08713..2b24c31 100644 --- a/src/modules/chips/stm32f407/registers.zig +++ b/src/modules/chips/stm32f407/registers.zig @@ -211,7 +211,6 @@ pub const VectorTable = extern struct { }; pub const registers = struct { - /// Random number generator pub const RNG = struct { pub const base_address = 0x50060800; @@ -52830,7 +52829,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/chips/stm32f429/registers.zig b/src/modules/chips/stm32f429/registers.zig index 7bd4b62..077fcae 100644 --- a/src/modules/chips/stm32f429/registers.zig +++ b/src/modules/chips/stm32f429/registers.zig @@ -220,7 +220,6 @@ pub const VectorTable = extern struct { }; pub const registers = struct { - /// Random number generator pub const RNG = struct { pub const base_address = 0x50060800; @@ -53872,7 +53871,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig index bd1ecda..c2c6bc7 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -95,8 +95,7 @@ pub var vector_table: VectorTable = blk: { @compileLog("root.interrupts must be a struct"); inline for (@typeInfo(app.interrupts).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(app.interrupts, decl.name))).Fn.calling_convention; - const handler = @field(app.interrupts, decl.name); + const function = @field(app.interrupts, decl.name); if (!@hasField(VectorTable, decl.name)) { var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; @@ -112,22 +111,36 @@ pub var vector_table: VectorTable = blk: { if (!isValidField(decl.name)) @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - @field(tmp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError("unsupported calling convention for function " ++ decl.name), - }; + @field(tmp, decl.name) = createInterruptVector(function); } } break :blk tmp; }; + +fn createInterruptVector( + comptime function: anytype, +) microzig.chip.InterruptVector { + const calling_convention = @typeInfo(@TypeOf(function)).Fn.calling_convention; + return switch (calling_convention) { + .C => .{ .C = function }, + .Naked => .{ .Naked = function }, + // for unspecified calling convention we are going to generate small wrapper + .Unspecified => .{ + .C = struct { + fn wrapper() callconv(.C) void { + if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug + @call(.{ .modifier = .always_inline }, function, .{}); + } + }.wrapper, + }, + + else => |val| { + const conv_name = inline for (std.meta.fields(std.builtin.CallingConvention)) |field| { + if (val == @field(std.builtin.CallingConvention, field.name)) + break field.name; + } else unreachable; + + @compileError("unsupported calling convention for interrupt vector: " ++ conv_name); + }, + }; +} From e6d6ca709291a61e25874ddfa18ab6cc227c0fa0 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 10 Jul 2022 02:28:03 -0700 Subject: [PATCH 064/138] generate registers with known cpu (#63) --- src/modules/chips/stm32f103/registers.zig | 278 +++++++++++++++++++++- 1 file changed, 271 insertions(+), 7 deletions(-) diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig index 1edfad7..dd33829 100644 --- a/src/modules/chips/stm32f103/registers.zig +++ b/src/modules/chips/stm32f103/registers.zig @@ -1,8 +1,242 @@ -// this file is generated by regz +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 341b0177d90a56f4307cc3226d552b39b048e7fa // // device: STM32F103xx +// cpu: CM3 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + /// Window Watchdog interrupt + WWDG: InterruptVector = unhandled, + /// PVD through EXTI line detection + /// interrupt + PVD: InterruptVector = unhandled, + /// Tamper interrupt + TAMPER: InterruptVector = unhandled, + /// RTC global interrupt + RTC: InterruptVector = unhandled, + /// Flash global interrupt + FLASH: InterruptVector = unhandled, + /// RCC global interrupt + RCC: InterruptVector = unhandled, + /// EXTI Line0 interrupt + EXTI0: InterruptVector = unhandled, + /// EXTI Line1 interrupt + EXTI1: InterruptVector = unhandled, + /// EXTI Line2 interrupt + EXTI2: InterruptVector = unhandled, + /// EXTI Line3 interrupt + EXTI3: InterruptVector = unhandled, + /// EXTI Line4 interrupt + EXTI4: InterruptVector = unhandled, + /// DMA1 Channel1 global interrupt + DMA1_Channel1: InterruptVector = unhandled, + /// DMA1 Channel2 global interrupt + DMA1_Channel2: InterruptVector = unhandled, + /// DMA1 Channel3 global interrupt + DMA1_Channel3: InterruptVector = unhandled, + /// DMA1 Channel4 global interrupt + DMA1_Channel4: InterruptVector = unhandled, + /// DMA1 Channel5 global interrupt + DMA1_Channel5: InterruptVector = unhandled, + /// DMA1 Channel6 global interrupt + DMA1_Channel6: InterruptVector = unhandled, + /// DMA1 Channel7 global interrupt + DMA1_Channel7: InterruptVector = unhandled, + /// ADC1 global interrupt + ADC: InterruptVector = unhandled, + /// CAN1 TX interrupts + CAN1_TX: InterruptVector = unhandled, + /// CAN1 RX0 interrupts + CAN1_RX0: InterruptVector = unhandled, + /// CAN1 RX1 interrupt + CAN1_RX1: InterruptVector = unhandled, + /// CAN1 SCE interrupt + CAN1_SCE: InterruptVector = unhandled, + /// EXTI Line[9:5] interrupts + EXTI9_5: InterruptVector = unhandled, + /// TIM1 Break interrupt and TIM9 global + /// interrupt + TIM1_BRK_TIM9: InterruptVector = unhandled, + /// TIM1 Update interrupt and TIM10 global + /// interrupt + TIM1_UP_TIM10: InterruptVector = unhandled, + /// TIM1 Trigger and Commutation interrupts and + /// TIM11 global interrupt + TIM1_TRG_COM_TIM11: InterruptVector = unhandled, + /// TIM1 Capture Compare interrupt + TIM1_CC: InterruptVector = unhandled, + /// TIM2 global interrupt + TIM2: InterruptVector = unhandled, + /// TIM3 global interrupt + TIM3: InterruptVector = unhandled, + /// TIM4 global interrupt + TIM4: InterruptVector = unhandled, + /// I2C1 event interrupt + I2C1_EV: InterruptVector = unhandled, + /// I2C1 error interrupt + I2C1_ER: InterruptVector = unhandled, + /// I2C2 event interrupt + I2C2_EV: InterruptVector = unhandled, + /// I2C2 error interrupt + I2C2_ER: InterruptVector = unhandled, + /// SPI1 global interrupt + SPI1: InterruptVector = unhandled, + /// SPI2 global interrupt + SPI2: InterruptVector = unhandled, + /// USART1 global interrupt + USART1: InterruptVector = unhandled, + /// USART2 global interrupt + USART2: InterruptVector = unhandled, + /// USART3 global interrupt + USART3: InterruptVector = unhandled, + /// EXTI Line[15:10] interrupts + EXTI15_10: InterruptVector = unhandled, + /// RTC Alarms through EXTI line + /// interrupt + RTCAlarm: InterruptVector = unhandled, + /// USB Device FS Wakeup through EXTI line + /// interrupt + USB_FS_WKUP: InterruptVector = unhandled, + /// TIM8 Break interrupt and TIM12 global + /// interrupt + TIM8_BRK_TIM12: InterruptVector = unhandled, + /// TIM8 Update interrupt and TIM13 global + /// interrupt + TIM8_UP_TIM13: InterruptVector = unhandled, + /// TIM8 Trigger and Commutation interrupts and + /// TIM14 global interrupt + TIM8_TRG_COM_TIM14: InterruptVector = unhandled, + /// TIM8 Capture Compare interrupt + TIM8_CC: InterruptVector = unhandled, + /// ADC3 global interrupt + ADC3: InterruptVector = unhandled, + /// FSMC global interrupt + FSMC: InterruptVector = unhandled, + /// SDIO global interrupt + SDIO: InterruptVector = unhandled, + /// TIM5 global interrupt + TIM5: InterruptVector = unhandled, + /// SPI3 global interrupt + SPI3: InterruptVector = unhandled, + /// UART4 global interrupt + UART4: InterruptVector = unhandled, + /// UART5 global interrupt + UART5: InterruptVector = unhandled, + /// TIM6 global interrupt + TIM6: InterruptVector = unhandled, + /// TIM7 global interrupt + TIM7: InterruptVector = unhandled, + /// DMA2 Channel1 global interrupt + DMA2_Channel1: InterruptVector = unhandled, + /// DMA2 Channel2 global interrupt + DMA2_Channel2: InterruptVector = unhandled, + /// DMA2 Channel3 global interrupt + DMA2_Channel3: InterruptVector = unhandled, + /// DMA2 Channel4 and DMA2 Channel5 global + /// interrupt + DMA2_Channel4_5: InterruptVector = unhandled, +}; pub const registers = struct { + /// System Control Space + pub const SCS = struct { + pub const base_address = 0xe000e000; + + /// System Tick Timer + pub const SysTick = struct { + /// address: 0xe000e010 + /// SysTick Control and Status Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0xe000e014 + /// SysTick Reload Value Register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x14); + + /// address: 0xe000e018 + /// SysTick Current Value Register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000e01c + /// SysTick Calibration Register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + SKEW: u1, + NOREF: u1, + }), base_address + 0x1c); + }; + }; + /// Flexible static memory controller pub const FSMC = struct { pub const base_address = 0xa0000000; @@ -751,6 +985,7 @@ pub const registers = struct { padding1: u1, }), base_address + 0x11c); }; + /// Power control pub const PWR = struct { pub const base_address = 0x40007000; @@ -842,6 +1077,7 @@ pub const registers = struct { padding22: u1, }), base_address + 0x4); }; + /// Reset and clock control pub const RCC = struct { pub const base_address = 0x40021000; @@ -1369,6 +1605,7 @@ pub const registers = struct { LPWRRSTF: u1, }), base_address + 0x24); }; + /// General purpose I/O pub const GPIOA = struct { pub const base_address = 0x40010800; @@ -4044,6 +4281,7 @@ pub const registers = struct { padding14: u1, }), base_address + 0x18); }; + /// Alternate function I/O pub const AFIO = struct { pub const base_address = 0x40010000; @@ -4303,6 +4541,7 @@ pub const registers = struct { padding20: u1, }), base_address + 0x1c); }; + /// EXTI pub const EXTI = struct { pub const base_address = 0x40010400; @@ -4704,6 +4943,7 @@ pub const registers = struct { padding12: u1, }), base_address + 0x14); }; + /// DMA controller pub const DMA1 = struct { pub const base_address = 0x40020000; @@ -6347,6 +6587,7 @@ pub const registers = struct { MA: u32, }), base_address + 0x8c); }; + /// Secure digital input/output /// interface pub const SDIO = struct { @@ -6791,6 +7032,7 @@ pub const registers = struct { FIFOData: u32, }), base_address + 0x80); }; + /// Real time clock pub const RTC = struct { pub const base_address = 0x40002800; @@ -6915,6 +7157,7 @@ pub const registers = struct { /// RTC Alarm Register Low pub const ALRL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); }; + /// Backup registers pub const BKP = struct { pub const base_address = 0x40006c04; @@ -7950,6 +8193,7 @@ pub const registers = struct { padding21: u1, }), base_address + 0x30); }; + /// Independent watchdog pub const IWDG = struct { pub const base_address = 0x40003000; @@ -8050,6 +8294,7 @@ pub const registers = struct { padding29: u1, }), base_address + 0xc); }; + /// Window watchdog pub const WWDG = struct { pub const base_address = 0x40002c00; @@ -8159,6 +8404,7 @@ pub const registers = struct { padding30: u1, }), base_address + 0x8); }; + /// Advanced timer pub const TIM1 = struct { pub const base_address = 0x40012c00; @@ -9542,6 +9788,7 @@ pub const registers = struct { padding15: u1, }), base_address + 0x44); }; + /// General purpose timer pub const TIM2 = struct { pub const base_address = 0x40000000; @@ -11903,6 +12150,7 @@ pub const registers = struct { padding15: u1, }), base_address + 0x4c); }; + /// General purpose timer pub const TIM9 = struct { pub const base_address = 0x40014c00; @@ -12708,6 +12956,7 @@ pub const registers = struct { /// capture/compare register 2 pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); }; + /// General purpose timer pub const TIM10 = struct { pub const base_address = 0x40015000; @@ -14065,6 +14314,7 @@ pub const registers = struct { /// capture/compare register 1 pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); }; + /// Basic timer pub const TIM6 = struct { pub const base_address = 0x40001000; @@ -14482,6 +14732,7 @@ pub const registers = struct { /// auto-reload register pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); }; + /// Inter integrated circuit pub const I2C1 = struct { pub const base_address = 0x40005400; @@ -15083,6 +15334,7 @@ pub const registers = struct { /// TRISE register pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); }; + /// Serial peripheral interface pub const SPI1 = struct { pub const base_address = 0x40013000; @@ -15975,6 +16227,7 @@ pub const registers = struct { padding21: u1, }), base_address + 0x20); }; + /// Universal synchronous asynchronous receiver /// transmitter pub const USART1 = struct { @@ -16727,6 +16980,7 @@ pub const registers = struct { padding15: u1, }), base_address + 0x18); }; + /// Analog to digital converter pub const ADC1 = struct { pub const base_address = 0x40012400; @@ -17336,6 +17590,7 @@ pub const registers = struct { ADC2DATA: u16, }), base_address + 0x4c); }; + /// Analog to digital converter pub const ADC2 = struct { pub const base_address = 0x40012800; @@ -18585,6 +18840,7 @@ pub const registers = struct { padding15: u1, }), base_address + 0x4c); }; + /// Controller area network pub const CAN = struct { pub const base_address = 0x40006400; @@ -21419,6 +21675,7 @@ pub const registers = struct { FB31: u1, }), base_address + 0x2ac); }; + /// Digital to analog converter pub const DAC = struct { pub const base_address = 0x40007400; @@ -21822,6 +22079,7 @@ pub const registers = struct { padding19: u1, }), base_address + 0x30); }; + /// Debug support pub const DBG = struct { pub const base_address = 0xe0042000; @@ -21894,6 +22152,7 @@ pub const registers = struct { padding9: u1, }), base_address + 0x4); }; + /// Universal asynchronous receiver /// transmitter pub const UART4 = struct { @@ -22110,6 +22369,7 @@ pub const registers = struct { padding23: u1, }), base_address + 0x14); }; + /// Universal asynchronous receiver /// transmitter pub const UART5 = struct { @@ -22321,6 +22581,7 @@ pub const registers = struct { padding23: u1, }), base_address + 0x14); }; + /// CRC calculation unit pub const CRC = struct { pub const base_address = 0x40023000; @@ -22371,6 +22632,7 @@ pub const registers = struct { padding30: u1, }), base_address + 0x8); }; + /// FLASH pub const FLASH = struct { pub const base_address = 0x40022000; @@ -22562,6 +22824,7 @@ pub const registers = struct { WRP: u32, }), base_address + 0x20); }; + /// Nested Vectored Interrupt /// Controller pub const NVIC = struct { @@ -22904,6 +23167,7 @@ pub const registers = struct { IPR_N3: u8, }), base_address + 0x438); }; + /// Universal serial bus full-speed device /// interface pub const USB = struct { @@ -23488,18 +23752,18 @@ pub fn Mmio(comptime size: u8, comptime PackedT: type) type { pub const underlying_type = PackedT; - pub fn read(addr: *volatile Self) PackedT { + pub inline fn read(addr: *volatile Self) PackedT { return @bitCast(PackedT, addr.raw); } - pub fn write(addr: *volatile Self, val: PackedT) void { + pub inline fn write(addr: *volatile Self, val: PackedT) void { // This is a workaround for a compiler bug related to miscompilation // If the tmp var is not used, result location will fuck things up var tmp = @bitCast(IntT, val); addr.raw = tmp; } - pub fn modify(addr: *volatile Self, fields: anytype) void { + pub inline fn modify(addr: *volatile Self, fields: anytype) void { var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, field.name) = @field(fields, field.name); @@ -23507,7 +23771,7 @@ pub fn Mmio(comptime size: u8, comptime PackedT: type) type { write(addr, val); } - pub fn toggle(addr: *volatile Self, fields: anytype) void { + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { var val = read(addr); inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); @@ -23523,11 +23787,11 @@ pub fn MmioInt(comptime size: u8, comptime T: type) type { raw: std.meta.Int(.unsigned, size), - pub fn read(addr: *volatile Self) T { + pub inline fn read(addr: *volatile Self) T { return @truncate(T, addr.raw); } - pub fn modify(addr: *volatile Self, val: T) void { + pub inline fn modify(addr: *volatile Self, val: T) void { const Int = std.meta.Int(.unsigned, size); const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); From 6bc3fc094bbd1cb0b5a9116ea0294fcefada45db Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 10 Jul 2022 09:03:20 -0700 Subject: [PATCH 065/138] add hal or app level clock configuration (#62) * add hal or app level clock configuration * fix control flow and typo * use hal.init(), thanks kuon for the improvement --- src/core/empty.zig | 0 src/core/microzig.zig | 9 +++++++++ src/main.zig | 13 +++++++------ 3 files changed, 16 insertions(+), 6 deletions(-) create mode 100644 src/core/empty.zig diff --git a/src/core/empty.zig b/src/core/empty.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/core/microzig.zig b/src/core/microzig.zig index aab89b8..d3decbe 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -176,6 +176,15 @@ export fn microzig_main() noreturn { if (info.Fn.calling_convention == .Async) @compileError("TODO: Embedded event loop not supported yet. Please try again later."); + // A hal can export a default init function that runs before main for + // procedures like clock configuration. The user may override and customize + // this functionality by providing their own init function. + // function. + if (@hasDecl(app, "init")) + app.init() + else if (@hasDecl(hal, "init")) + hal.init(); + if (@typeInfo(return_type) == .ErrorUnion) { main() catch |err| { // TODO: diff --git a/src/main.zig b/src/main.zig index cd30986..af23dbf 100644 --- a/src/main.zig +++ b/src/main.zig @@ -160,12 +160,13 @@ pub fn addEmbeddedExecutable( exe.addPackage(chip_pkg); exe.addPackage(cpu_pkg); - if (options.hal_package_path) |hal_package_path| - exe.addPackage(.{ - .name = "hal", - .source = hal_package_path, - .dependencies = &.{pkgs.microzig}, - }); + exe.addPackage(.{ + .name = "hal", + .source = if (options.hal_package_path) |hal_package_path| + hal_package_path + else .{ .path = root_path ++ "core/empty.zig" }, + .dependencies = &.{pkgs.microzig}, + }); switch (backing) { .board => |board| { From e60d59ce49062a96b28c6d9203c28a4161fdd964 Mon Sep 17 00:00:00 2001 From: Ethan Frei Date: Wed, 13 Jul 2022 21:58:19 -0500 Subject: [PATCH 066/138] changing linker memory locations for stm32f103c8 (#65) --- src/modules/chips.zig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 5a2d5a0..6a4858e 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -35,8 +35,8 @@ pub const stm32f103x8 = Chip{ .path = root_path ++ "chips/stm32f103/stm32f103.zig", .cpu = cpus.cortex_m3, .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 64 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x10000000, .length = 20 * 1024, .kind = .ram }, + MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, }, }; From e5b8d57c72a2de4a113d0186fa8fa133915bf1f6 Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Sat, 23 Jul 2022 19:43:39 +0200 Subject: [PATCH 067/138] Stm32f303 target speed trivial check (#66) * Check new I2C target_speed config setting * Corrected incorrect doc comment --- src/core/i2c.zig | 3 +-- src/modules/chips/stm32f303/stm32f303.zig | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/core/i2c.zig b/src/core/i2c.zig index 48a23b4..2aa89f6 100644 --- a/src/core/i2c.zig +++ b/src/core/i2c.zig @@ -148,8 +148,7 @@ pub const Pins = struct { sda: ?type = null, }; -/// A UART configuration. The config defaults to the *8N1* setting, so "8 data bits, no parity, 1 stop bit" which is the -/// most common serial format. +/// An I2C configuration. pub const Config = struct { /// The target speed in bit/s. Note that the actual speed can differ from this, due to prescaler rounding. target_speed: u32, diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index a80a6a6..e9cc706 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -274,8 +274,6 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type const Self = @This(); pub fn init(config: micro.i2c.Config) !Self { - // TODO: use config - _ = config; // CONFIGURE I2C1 // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA, // if GPIO port B is configured for alternate function 4 for these PB pins. @@ -307,6 +305,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/ // but copying an example from the reference manual, RM0316 section 28.4.9.) + if (config.target_speed != 100_000) @panic("TODO: Support speeds other than 100 kHz"); regs.I2C1.TIMINGR.modify(.{ .PRESC = 1, .SCLL = 0x13, From 231508bf239adc6620c8b88df022a8bdcbf5c969 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 24 Jul 2022 10:22:59 -0700 Subject: [PATCH 068/138] move linux builds to buildkite (#67) --- .buildkite/pipeline.yml | 4 ++++ .github/workflows/build.yml | 6 ++---- 2 files changed, 6 insertions(+), 4 deletions(-) create mode 100644 .buildkite/pipeline.yml diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml new file mode 100644 index 0000000..85b90e7 --- /dev/null +++ b/.buildkite/pipeline.yml @@ -0,0 +1,4 @@ +steps: + - group: Build + steps: + - command: zig build -Drelease-small diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9135476..9001ade 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -5,7 +5,7 @@ on: pull_request: branches: [ master ] schedule: - - cron: "0 7 * * *" + - cron: "0 0 * * *" jobs: build: @@ -13,7 +13,6 @@ jobs: strategy: matrix: os: [ - ubuntu-latest, windows-latest, macos-latest, ] @@ -23,8 +22,7 @@ jobs: with: submodules: recursive fetch-depth: 0 - - # only using master until 0.9.0 is released + - name: Setup Zig uses: goto-bus-stop/setup-zig@v1.3.0 with: From aab147d43196544293d3e85f37b21568b249ef08 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 24 Jul 2022 11:58:34 -0700 Subject: [PATCH 069/138] only manage in-repo once it gets complicated (#68) --- .buildkite/pipeline.yml | 4 ---- 1 file changed, 4 deletions(-) delete mode 100644 .buildkite/pipeline.yml diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml deleted file mode 100644 index 85b90e7..0000000 --- a/.buildkite/pipeline.yml +++ /dev/null @@ -1,4 +0,0 @@ -steps: - - group: Build - steps: - - command: zig build -Drelease-small From 0cde03507b3b40cbfb41e2e55c04a6a7aeb9c653 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 24 Jul 2022 12:36:52 -0700 Subject: [PATCH 070/138] update github actions to reflect default branch name fix (#69) --- .github/workflows/build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9001ade..4ddce88 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,9 +1,9 @@ name: Build on: push: - branches: [ master ] + branches: [ main ] pull_request: - branches: [ master ] + branches: [ main ] schedule: - cron: "0 0 * * *" From d57f19c886aec13b995bdfbd9a393be8dac48270 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matheus=20C=2E=20Fran=C3=A7a?= Date: Sun, 24 Jul 2022 16:38:32 -0300 Subject: [PATCH 071/138] Gd32v Support (#21) * Logan nano - board added * Changes: - replace baseline_rv32 to sifive_e21(imac) - update registers.zig - parsepin added (WIP) - more riscv_encoding added * refactoring * fix build * Missing interrupts * minimal interrupt * remove vectorTable * skip interrupt test - riscv32 * remove supports_uart_test flag * remove `supports_interrupt_test` --- build.zig | 9 +- src/modules/boards.zig | 6 + .../boards/longan-nano/longan-nano.zig | 112 + src/modules/chips.zig | 20 + src/modules/chips/gd32vf103/gd32vf103.zig | 114 + src/modules/chips/gd32vf103/registers.zig | 24637 ++++++++++++++++ src/modules/cpus.zig | 11 + src/modules/cpus/rv32-imac/riscv32.zig | 903 + tests/blinky.zig | 2 + tests/uart-sync.zig | 6 + 10 files changed, 25817 insertions(+), 3 deletions(-) create mode 100644 src/modules/boards/longan-nano/longan-nano.zig create mode 100644 src/modules/chips/gd32vf103/gd32vf103.zig create mode 100644 src/modules/chips/gd32vf103/registers.zig create mode 100644 src/modules/cpus/rv32-imac/riscv32.zig diff --git a/build.zig b/build.zig index 0519e58..0253d08 100644 --- a/build.zig +++ b/build.zig @@ -1,6 +1,6 @@ //! Some words on the build script here: //! We cannot use a test runner here as we're building for freestanding. -//! This means we need to use addExecutable() instead of using +//! This means we need to use addExecutable() instead of using const std = @import("std"); const microzig = @import("src/main.zig"); @@ -24,16 +24,18 @@ pub fn build(b: *std.build.Builder) !void { BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery } }, BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery } }, BuildConfig{ .name = "boards.stm32f429idiscovery", .backing = Backing{ .board = boards.stm32f429idiscovery }, .supports_uart_test = false }, + BuildConfig{ .name = "chips.gd32vf103x8", .backing = Backing{ .chip = chips.gd32vf103x8 } }, + BuildConfig{ .name = "boards.longan_nano", .backing = Backing{ .board = boards.longan_nano } }, }; - const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_avr: bool = true }; + const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_riscv32: bool = true, on_avr: bool = true }; const all_tests = [_]Test{ Test{ .name = "minimal", .source = "tests/minimal.zig" }, Test{ .name = "blinky", .source = "tests/blinky.zig" }, Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true, .on_avr = false }, // Note: this example uses the systick interrupt and therefore only for arm microcontrollers - Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_avr = true }, + Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_riscv32 = false, .on_avr = true }, }; const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); @@ -42,6 +44,7 @@ pub fn build(b: *std.build.Builder) !void { for (all_tests) |tst| { if (tst.uses_uart and !cfg.supports_uart_test) continue; if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue; + if (!tst.on_riscv32) continue; const exe = try microzig.addEmbeddedExecutable( b, diff --git a/src/modules/boards.zig b/src/modules/boards.zig index 6793a7b..db1fa75 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -37,3 +37,9 @@ pub const stm32f429idiscovery = Board{ .path = root_path ++ "boards/stm32f429idiscovery/stm32f429idiscovery.zig", .chip = chips.stm32f429zit6u, }; + +pub const longan_nano = Board{ + .name = "Longan Nano", + .path = root_path ++ "boards/longan-nano/longan-nano.zig", + .chip = chips.gd32vf103xb, +}; diff --git a/src/modules/boards/longan-nano/longan-nano.zig b/src/modules/boards/longan-nano/longan-nano.zig new file mode 100644 index 0000000..e042be1 --- /dev/null +++ b/src/modules/boards/longan-nano/longan-nano.zig @@ -0,0 +1,112 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 8_000_000; // 8 MHz + +pub const pin_map = .{ + + // Port A + .PA0 = "PA0", + .PA1 = "PA1", + .PA2 = "PA2", + .PA3 = "PA3", + .PA4 = "PA4", + .PA5 = "PA5", + .PA6 = "PA6", + .PA7 = "PA7", + .PA8 = "PA8", + .PA9 = "PA9", + .PA10 = "PA10", + .PA11 = "PA11", + .PA12 = "PA12", + .PA13 = "PA13", + + // Port B + .PB0 = "PB0", + .PB1 = "PB1", + .PB2 = "PB2", + .PB3 = "PB3", + .PB4 = "PB4", + .PB5 = "PB5", + .PB6 = "PB6", + .PB7 = "PB7", + .PB8 = "PB8", + .PB9 = "PB9", + .PB10 = "PB10", + .PB11 = "PB11", + .PB12 = "PB12", + .PB13 = "PB13", + .PB14 = "PB14", + .PB15 = "PB15", + + // Port C + .PC0 = "PC0", + .PC1 = "PC1", + .PC2 = "PC2", + .PC3 = "PC3", + .PC4 = "PC4", + .PC5 = "PC5", + .PC6 = "PC6", + .PC7 = "PC7", + .PC8 = "PC8", + .PC9 = "PC9", + .PC10 = "PC10", + .PC11 = "PC11", + .PC12 = "PC12", + .PC13 = "PC13", + .PC14 = "PC14", + .PC15 = "PC15", + + // Port D + .PD0 = "PD0", + .PD1 = "PD1", + .PD2 = "PD2", + .PD3 = "PD3", + .PD4 = "PD4", + .PD5 = "PD5", + .PD6 = "PD6", + .PD7 = "PD7", + .PD8 = "PD8", + .PD9 = "PD9", + .PD10 = "PD10", + .PD11 = "PD11", + .PD12 = "PD12", + .PD13 = "PD13", + .PD14 = "PD14", + .PD15 = "PD15", + + // Port E + .PE0 = "PE0", + .PE1 = "PE1", + .PE2 = "PE2", + .PE3 = "PE3", + .PE4 = "PE4", + .PE5 = "PE5", + .PE6 = "PE6", + .PE7 = "PE7", + .PE8 = "PE8", + .PE9 = "PE9", + .PE10 = "PE10", + .PE11 = "PE11", + .PE12 = "PE12", + .PE13 = "PE13", + .PE14 = "PE14", + .PE15 = "PE15", + + // Colors LED + // LCD_COLOR_WHITE 0xFFFF + // LCD_COLOR_BLACK 0x0000 + // LCD_COLOR_GREY 0xF7DE + // LCD_COLOR_BLUE 0x001F + // LCD_COLOR_BLUE2 0x051F + // LCD_COLOR_RED 0xF800 + // LCD_COLOR_MAGENTA 0xF81F + // LCD_COLOR_GREEN 0x07E0 + // LCD_COLOR_CYAN 0x7FFF + // LCD_COLOR_YELLOW 0xFFE0 +}; + +pub fn debugWrite(string: []const u8) void { + _ = string; + // TODO: implement +} diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 6a4858e..1794e12 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -30,6 +30,26 @@ pub const lpc1768 = Chip{ }, }; +pub const gd32vf103xb = Chip{ + .name = "GD32VF103xB", + .path = root_path ++ "chips/gd32vf103/gd32vf103.zig", + .cpu = cpus.riscv32_imac, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, + }, +}; + +pub const gd32vf103x8 = Chip{ + .name = "GD32VF103x8", + .path = root_path ++ "chips/gd32vf103/gd32vf103.zig", + .cpu = cpus.riscv32_imac, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + }, +}; + pub const stm32f103x8 = Chip{ .name = "STM32F103x8", .path = root_path ++ "chips/stm32f103/stm32f103.zig", diff --git a/src/modules/chips/gd32vf103/gd32vf103.zig b/src/modules/chips/gd32vf103/gd32vf103.zig new file mode 100644 index 0000000..0758d2f --- /dev/null +++ b/src/modules/chips/gd32vf103/gd32vf103.zig @@ -0,0 +1,114 @@ +pub const cpu = @import("cpu"); +pub const micro = @import("microzig"); +pub const chip = @import("registers.zig"); +const regs = chip.registers; + +pub usingnamespace chip; + +pub const clock_frequencies = .{ + .cpu = 8_000_000, // 8 MHz +}; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'E') + @compileError(invalid_format_msg); + + return struct { + const pin_number: comptime_int = @import("std").fmt.parseInt(u2, spec[2..], 10) catch @compileError(invalid_format_msg); + // 'A'...'E' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); + const suffix = @import("std").fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + _ = pin; + // TODO: check if pin is already configured as output + } + pub fn setInput(comptime pin: type) void { + _ = pin; + // TODO: check if pin is already configured as input + } + + pub fn read(comptime pin: type) micro.gpio.State { + _ = pin; + // TODO: check if pin is configured as input + return .low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + _ = state; + // TODO: check if pin is configured as output + } +}; + +pub const uart = struct { + pub const DataBits = enum(u2) { + five = 0, + six = 1, + seven = 2, + eight = 3, + }; + + pub const StopBits = enum(u1) { + one = 0, + two = 1, + }; + + pub const Parity = enum(u2) { + odd = 0, + even = 1, + mark = 2, + space = 3, + }; +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (pins.tx != null or pins.rx != null) + @compileError("TODO: custom pins are not currently supported"); + + return struct { + const UARTn = switch (index) { + 0 => regs.UART3, + 1 => regs.UART4, + else => @compileError("GD32VF103 has 2 UARTs available."), + }; + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + _ = config; + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + return false; + } + pub fn tx(self: Self, ch: u8) void { + _ = ch; + while (!self.canWrite()) {} // Wait for Previous transmission + } + + pub fn canRead(self: Self) bool { + _ = self; + return false; + } + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return 1; // Read received data + } + }; +} diff --git a/src/modules/chips/gd32vf103/registers.zig b/src/modules/chips/gd32vf103/registers.zig new file mode 100644 index 0000000..356a07d --- /dev/null +++ b/src/modules/chips/gd32vf103/registers.zig @@ -0,0 +1,24637 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 341b0177d90a56f4307cc3226d552b39b048e7fa +// +// device: GD32VF103 +// cpu: CM3 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, + reserved4: u32 = undefined, + /// Software interrupt + INT_SFT: InterruptVector = unhandled, + reserved5: u32 = undefined, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + /// Timer interrupt + INT_TMR: InterruptVector = unhandled, + reserved8: u32 = undefined, + reserved9: u32 = undefined, + reserved10: u32 = undefined, + reserved11: u32 = undefined, + reserved12: u32 = undefined, + reserved13: u32 = undefined, + reserved14: u32 = undefined, + reserved15: u32 = undefined, + reserved16: u32 = undefined, + /// Bus Error interrupt + INT_BWEI: InterruptVector = unhandled, + /// Performance Monitor interrupt + INT_PMOVI: InterruptVector = unhandled, + WWDGT: InterruptVector = unhandled, + EXTI_LVD: InterruptVector = unhandled, + Tamper: InterruptVector = unhandled, + RTC: InterruptVector = unhandled, + FMC: InterruptVector = unhandled, + RCU: InterruptVector = unhandled, + EXTI_Line0: InterruptVector = unhandled, + EXTI_Line1: InterruptVector = unhandled, + EXTI_Line2: InterruptVector = unhandled, + EXTI_Line3: InterruptVector = unhandled, + EXTI_Line4: InterruptVector = unhandled, + DMA0_Channel0: InterruptVector = unhandled, + DMA0_Channel1: InterruptVector = unhandled, + DMA0_Channel2: InterruptVector = unhandled, + DMA0_Channel3: InterruptVector = unhandled, + DMA0_Channel4: InterruptVector = unhandled, + DMA0_Channel5: InterruptVector = unhandled, + DMA0_Channel6: InterruptVector = unhandled, + ADC0_1: InterruptVector = unhandled, + CAN0_TX: InterruptVector = unhandled, + CAN0_RX0: InterruptVector = unhandled, + CAN0_RX1: InterruptVector = unhandled, + CAN0_EWMC: InterruptVector = unhandled, + EXTI_line9_5: InterruptVector = unhandled, + TIMER0_BRK: InterruptVector = unhandled, + TIMER0_UP: InterruptVector = unhandled, + TIMER0_TRG_CMT: InterruptVector = unhandled, + TIMER0_Channel: InterruptVector = unhandled, + TIMER1: InterruptVector = unhandled, + TIMER2: InterruptVector = unhandled, + TIMER3: InterruptVector = unhandled, + I2C0_EV: InterruptVector = unhandled, + I2C0_ER: InterruptVector = unhandled, + I2C1_EV: InterruptVector = unhandled, + I2C1_ER: InterruptVector = unhandled, + SPI0: InterruptVector = unhandled, + SPI1: InterruptVector = unhandled, + USART0: InterruptVector = unhandled, + USART1: InterruptVector = unhandled, + USART2: InterruptVector = unhandled, + EXTI_line15_10: InterruptVector = unhandled, + RTC_Alarm: InterruptVector = unhandled, + USBFS_WKUP: InterruptVector = unhandled, + reserved17: u32 = undefined, + reserved18: u32 = undefined, + reserved19: u32 = undefined, + reserved20: u32 = undefined, + reserved21: u32 = undefined, + reserved22: u32 = undefined, + reserved23: u32 = undefined, + TIMER4: InterruptVector = unhandled, + SPI2: InterruptVector = unhandled, + UART3: InterruptVector = unhandled, + UART4: InterruptVector = unhandled, + TIMER5: InterruptVector = unhandled, + TIMER6: InterruptVector = unhandled, + DMA1_Channel0: InterruptVector = unhandled, + DMA1_Channel1: InterruptVector = unhandled, + DMA1_Channel2: InterruptVector = unhandled, + DMA1_Channel3: InterruptVector = unhandled, + DMA1_Channel4: InterruptVector = unhandled, + reserved24: u32 = undefined, + reserved25: u32 = undefined, + CAN1_TX: InterruptVector = unhandled, + CAN1_RX0: InterruptVector = unhandled, + CAN1_RX1: InterruptVector = unhandled, + CAN1_EWMC: InterruptVector = unhandled, + USBFS: InterruptVector = unhandled, +}; + +pub const registers = struct { + /// System Control Space + pub const SCS = struct { + pub const base_address = 0xe000e000; + + /// System Tick Timer + pub const SysTick = struct { + /// address: 0xe000e010 + /// SysTick Control and Status Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0xe000e014 + /// SysTick Reload Value Register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x14); + + /// address: 0xe000e018 + /// SysTick Current Value Register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000e01c + /// SysTick Calibration Register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + SKEW: u1, + NOREF: u1, + }), base_address + 0x1c); + }; + }; + + /// Analog to digital converter + pub const ADC0 = struct { + pub const base_address = 0x40012400; + + /// address: 0x40012400 + /// status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog event flag + WDE: u1, + /// End of group conversion flag + EOC: u1, + /// End of inserted group conversion flag + EOIC: u1, + /// Start flag of inserted channel group + STIC: u1, + /// Start flag of regular channel group + STRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012404 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + WDCHSEL: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Interrupt enable for WDE + WDEIE: u1, + /// Interrupt enable for EOIC + EOICIE: u1, + /// Scan mode + SM: u1, + /// When in scan mode, analog watchdog + /// is effective on a single channel + WDSC: u1, + /// Inserted channel group convert + /// automatically + ICA: u1, + /// Discontinuous mode on regular + /// channels + DISRC: u1, + /// Discontinuous mode on + /// inserted channels + DISIC: u1, + /// Number of conversions in + /// discontinuous mode + DISNUM: u3, + /// sync mode selection + SYNCM: u4, + reserved0: u1, + reserved1: u1, + /// Inserted channel analog watchdog + /// enable + IWDEN: u1, + /// Regular channel analog watchdog enable + RWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012408 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADC on + ADCON: u1, + /// Continuous mode + CTN: u1, + /// ADC calibration + CLB: u1, + /// Reset calibration + RSTCLB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DMA request enable + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + DAL: u1, + /// External trigger select for inserted channel + ETSIC: u3, + /// External trigger select for inserted channel + ETEIC: u1, + reserved6: u1, + /// External trigger select for regular channel + ETSRC: u3, + /// External trigger enable for regular channel + ETERC: u1, + /// Start on inserted channel + SWICST: u1, + /// Start on regular channel + SWRCST: u1, + /// Channel 16 and 17 enable of ADC0 + TSVREN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4001240c + /// Sample time register 0 + pub const SAMPT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 10 sample time + /// selection + SPT10: u3, + /// Channel 11 sample time + /// selection + SPT11: u3, + /// Channel 12 sample time + /// selection + SPT12: u3, + /// Channel 13 sample time + /// selection + SPT13: u3, + /// Channel 14 sample time + /// selection + SPT14: u3, + /// Channel 15 sample time + /// selection + SPT15: u3, + /// Channel 16 sample time + /// selection + SPT16: u3, + /// Channel 17 sample time + /// selection + SPT17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012410 + /// Sample time register 1 + pub const SAMPT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 sample time + /// selection + SPT0: u3, + /// Channel 1 sample time + /// selection + SPT1: u3, + /// Channel 2 sample time + /// selection + SPT2: u3, + /// Channel 3 sample time + /// selection + SPT3: u3, + /// Channel 4 sample time + /// selection + SPT4: u3, + /// Channel 5 sample time + /// selection + SPT5: u3, + /// Channel 6 sample time + /// selection + SPT6: u3, + /// Channel 7 sample time + /// selection + SPT7: u3, + /// Channel 8 sample time + /// selection + SPT8: u3, + /// Channel 9 sample time + /// selection + SPT9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012414 + /// Inserted channel data offset register + /// 0 + pub const IOFF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 0 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012418 + /// Inserted channel data offset register + /// 1 + pub const IOFF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 1 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001241c + /// Inserted channel data offset register + /// 2 + pub const IOFF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 2 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012420 + /// Inserted channel data offset register + /// 3 + pub const IOFF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 3 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012424 + /// watchdog higher threshold + /// register + pub const WDHT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x24); + + /// address: 0x40012428 + /// watchdog lower threshold + /// register + pub const WDLT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x28); + + /// address: 0x4001242c + /// regular sequence register 0 + pub const RSQ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + RSQ12: u5, + /// 14th conversion in regular + /// sequence + RSQ13: u5, + /// 15th conversion in regular + /// sequence + RSQ14: u5, + /// 16th conversion in regular + /// sequence + RSQ15: u5, + /// Regular channel group + /// length + RL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012430 + /// regular sequence register 1 + pub const RSQ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + RSQ6: u5, + /// 8th conversion in regular + /// sequence + RSQ7: u5, + /// 9th conversion in regular + /// sequence + RSQ8: u5, + /// 10th conversion in regular + /// sequence + RSQ9: u5, + /// 11th conversion in regular + /// sequence + RSQ10: u5, + /// 12th conversion in regular + /// sequence + RSQ11: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012434 + /// regular sequence register 2 + pub const RSQ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + RSQ0: u5, + /// 2nd conversion in regular + /// sequence + RSQ1: u5, + /// 3rd conversion in regular + /// sequence + RSQ2: u5, + /// 4th conversion in regular + /// sequence + RSQ3: u5, + /// 5th conversion in regular + /// sequence + RSQ4: u5, + /// 6th conversion in regular + /// sequence + RSQ5: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012438 + /// Inserted sequence register + pub const ISQ = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in inserted + /// sequence + ISQ0: u5, + /// 2nd conversion in inserted + /// sequence + ISQ1: u5, + /// 3rd conversion in inserted + /// sequence + ISQ2: u5, + /// 4th conversion in inserted + /// sequence + ISQ3: u5, + /// Inserted channel group length + IL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001243c + /// Inserted data register 0 + pub const IDATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012440 + /// Inserted data register 1 + pub const IDATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012444 + /// Inserted data register 2 + pub const IDATA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012448 + /// Inserted data register 3 + pub const IDATA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001244c + /// regular data register + pub const RDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Regular channel data + RDATA: u16, + /// ADC regular channel data + ADC1RDTR: u16, + }), base_address + 0x4c); + + /// address: 0x40012480 + /// Oversample control register + pub const OVSAMPCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Oversampler Enable + OVSEN: u1, + reserved0: u1, + /// Oversampling ratio + OVSR: u3, + /// Oversampling shift + OVSS: u4, + /// Triggered Oversampling + TOVS: u1, + reserved1: u1, + reserved2: u1, + /// ADC resolution + DRES: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x80); + }; + + /// Analog to digital converter + pub const ADC1 = struct { + pub const base_address = 0x40012800; + + /// address: 0x40012800 + /// status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog event flag + WDE: u1, + /// End of group conversion flag + EOC: u1, + /// End of inserted group conversion flag + EOIC: u1, + /// Start flag of inserted channel group + STIC: u1, + /// Start flag of regular channel group + STRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x0); + + /// address: 0x40012804 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Analog watchdog channel select + WDCHSEL: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Interrupt enable for WDE + WDEIE: u1, + /// Interrupt enable for EOIC + EOICIE: u1, + /// Scan mode + SM: u1, + /// When in scan mode, analog watchdog + /// is effective on a single channel + WDSC: u1, + /// Inserted channel group convert + /// automatically + ICA: u1, + /// Discontinuous mode on regular + /// channels + DISRC: u1, + /// Discontinuous mode on + /// inserted channels + DISIC: u1, + /// Number of conversions in + /// discontinuous mode + DISNUM: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Inserted channel analog watchdog + /// enable + IWDEN: u1, + /// Regular channel analog watchdog + /// enable + RWDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40012808 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// ADC on + ADCON: u1, + /// Continuous mode + CTN: u1, + /// ADC calibration + CLB: u1, + /// Reset calibration + RSTCLB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DMA request enable + DMA: u1, + reserved4: u1, + reserved5: u1, + /// Data alignment + DAL: u1, + /// External trigger select for inserted channel + ETSIC: u3, + /// External trigger enable for inserted channel + ETEIC: u1, + reserved6: u1, + /// External trigger select for regular channel + ETSRC: u3, + /// External trigger enable for regular channel + ETERC: u1, + /// Start on inserted channel + SWICST: u1, + /// Start on regular channel + SWRCST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x8); + + /// address: 0x4001280c + /// Sample time register 0 + pub const SAMPT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 10 sample time + /// selection + SPT10: u3, + /// Channel 11 sample time + /// selection + SPT11: u3, + /// Channel 12 sample time + /// selection + SPT12: u3, + /// Channel 13 sample time + /// selection + SPT13: u3, + /// Channel 14 sample time + /// selection + SPT14: u3, + /// Channel 15 sample time + /// selection + SPT15: u3, + /// Channel 16 sample time + /// selection + SPT16: u3, + /// Channel 17 sample time + /// selection + SPT17: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40012810 + /// Sample time register 1 + pub const SAMPT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 sample time + /// selection + SPT0: u3, + /// Channel 1 sample time + /// selection + SPT1: u3, + /// Channel 2 sample time + /// selection + SPT2: u3, + /// Channel 3 sample time + /// selection + SPT3: u3, + /// Channel 4 sample time + /// selection + SPT4: u3, + /// Channel 5 sample time + /// selection + SPT5: u3, + /// Channel 6 sample time + /// selection + SPT6: u3, + /// Channel 7 sample time + /// selection + SPT7: u3, + /// Channel 8 sample time + /// selection + SPT8: u3, + /// Channel 9 sample time + /// selection + SPT9: u3, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40012814 + /// Inserted channel data offset register + /// 0 + pub const IOFF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 0 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40012818 + /// Inserted channel data offset register + /// 1 + pub const IOFF1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 1 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4001281c + /// Inserted channel data offset register + /// 2 + pub const IOFF2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 2 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x40012820 + /// Inserted channel data offset register + /// 3 + pub const IOFF3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data offset for inserted channel + /// 3 + IOFF: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40012824 + /// watchdog higher threshold + /// register + pub const WDHT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x24); + + /// address: 0x40012828 + /// watchdog lower threshold + /// register + pub const WDLT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x28); + + /// address: 0x4001282c + /// regular sequence register 0 + pub const RSQ0 = @intToPtr(*volatile Mmio(32, packed struct { + /// 13th conversion in regular + /// sequence + RSQ12: u5, + /// 14th conversion in regular + /// sequence + RSQ13: u5, + /// 15th conversion in regular + /// sequence + RSQ14: u5, + /// 16th conversion in regular + /// sequence + RSQ15: u5, + /// Regular channel group + /// length + RL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2c); + + /// address: 0x40012830 + /// regular sequence register 1 + pub const RSQ1 = @intToPtr(*volatile Mmio(32, packed struct { + /// 7th conversion in regular + /// sequence + RSQ6: u5, + /// 8th conversion in regular + /// sequence + RSQ7: u5, + /// 9th conversion in regular + /// sequence + RSQ8: u5, + /// 10th conversion in regular + /// sequence + RSQ9: u5, + /// 11th conversion in regular + /// sequence + RSQ10: u5, + /// 12th conversion in regular + /// sequence + RSQ11: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x40012834 + /// regular sequence register 2 + pub const RSQ2 = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in regular + /// sequence + RSQ0: u5, + /// 2nd conversion in regular + /// sequence + RSQ1: u5, + /// 3rd conversion in regular + /// sequence + RSQ2: u5, + /// 4th conversion in regular + /// sequence + RSQ3: u5, + /// 5th conversion in regular + /// sequence + RSQ4: u5, + /// 6th conversion in regular + /// sequence + RSQ5: u5, + padding0: u1, + padding1: u1, + }), base_address + 0x34); + + /// address: 0x40012838 + /// Inserted sequence register + pub const ISQ = @intToPtr(*volatile Mmio(32, packed struct { + /// 1st conversion in inserted + /// sequence + ISQ0: u5, + /// 2nd conversion in inserted + /// sequence + ISQ1: u5, + /// 3rd conversion in inserted + /// sequence + ISQ2: u5, + /// 4th conversion in inserted + /// sequence + ISQ3: u5, + /// Inserted channel group length + IL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x4001283c + /// Inserted data register 0 + pub const IDATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x3c); + + /// address: 0x40012840 + /// Inserted data register 1 + pub const IDATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x40); + + /// address: 0x40012844 + /// Inserted data register 2 + pub const IDATA2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x44); + + /// address: 0x40012848 + /// Inserted data register 3 + pub const IDATA3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Inserted number n conversion data + IDATAn: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4001284c + /// regular data register + pub const RDATA = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c); + }; + + /// Alternate-function I/Os + pub const AFIO = struct { + pub const base_address = 0x40010000; + + /// address: 0x40010000 + /// Event control register + pub const EC = @intToPtr(*volatile Mmio(32, packed struct { + /// Event output pin selection + PIN: u4, + /// Event output port selection + PORT: u3, + /// Event output enable + EOE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40010004 + /// AFIO port configuration register 0 + pub const PCF0 = @intToPtr(*volatile Mmio(32, packed struct { + /// SPI0 remapping + SPI0_REMAP: u1, + /// I2C0 remapping + I2C0_REMAP: u1, + /// USART0 remapping + USART0_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u2, + /// TIMER0 remapping + TIMER0_REMAP: u2, + /// TIMER1 remapping + TIMER1_REMAP: u2, + /// TIMER2 remapping + TIMER2_REMAP: u2, + /// TIMER3 remapping + TIMER3_REMAP: u1, + /// CAN0 alternate interface remapping + CAN0_REMAP: u2, + /// Port D0/Port D1 mapping on OSC_IN/OSC_OUT + PD01_REMAP: u1, + /// TIMER4 channel3 internal remapping + TIMER4CH3_IREMAP: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// CAN1 I/O remapping + CAN1_REMAP: u1, + reserved5: u1, + /// Serial wire JTAG configuration + SWJ_CFG: u3, + reserved6: u1, + /// SPI2/I2S2 remapping + SPI2_REMAP: u1, + /// TIMER1 internal trigger 1 remapping + TIMER1ITI1_REMAP: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0x40010008 + /// EXTI sources selection register 0 + pub const EXTISS0 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI 0 sources selection + EXTI0_SS: u4, + /// EXTI 1 sources selection + EXTI1_SS: u4, + /// EXTI 2 sources selection + EXTI2_SS: u4, + /// EXTI 3 sources selection + EXTI3_SS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001000c + /// EXTI sources selection register 1 + pub const EXTISS1 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI 4 sources selection + EXTI4_SS: u4, + /// EXTI 5 sources selection + EXTI5_SS: u4, + /// EXTI 6 sources selection + EXTI6_SS: u4, + /// EXTI 7 sources selection + EXTI7_SS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010010 + /// EXTI sources selection register 2 + pub const EXTISS2 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI 8 sources selection + EXTI8_SS: u4, + /// EXTI 9 sources selection + EXTI9_SS: u4, + /// EXTI 10 sources selection + EXTI10_SS: u4, + /// EXTI 11 sources selection + EXTI11_SS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40010014 + /// EXTI sources selection register 3 + pub const EXTISS3 = @intToPtr(*volatile Mmio(32, packed struct { + /// EXTI 12 sources selection + EXTI12_SS: u4, + /// EXTI 13 sources selection + EXTI13_SS: u4, + /// EXTI 14 sources selection + EXTI14_SS: u4, + /// EXTI 15 sources selection + EXTI15_SS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x4001001c + /// AFIO port configuration register 1 + pub const PCF1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// EXMC_NADV connect/disconnect + EXMC_NADV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c); + }; + + /// Backup registers + pub const BKP = struct { + pub const base_address = 0x40006c00; + + /// address: 0x40006c04 + /// Backup data register 0 + pub const DATA0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x4); + + /// address: 0x40006c08 + /// Backup data register 1 + pub const DATA1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x8); + + /// address: 0x40006c0c + /// Backup data register 2 + pub const DATA2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xc); + + /// address: 0x40006c10 + /// Backup data register 3 + pub const DATA3 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x10); + + /// address: 0x40006c14 + /// Backup data register 4 + pub const DATA4 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x14); + + /// address: 0x40006c18 + /// Backup data register 5 + pub const DATA5 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x18); + + /// address: 0x40006c1c + /// Backup data register 6 + pub const DATA6 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x1c); + + /// address: 0x40006c20 + /// Backup data register 7 + pub const DATA7 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x20); + + /// address: 0x40006c24 + /// Backup data register 8 + pub const DATA8 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x24); + + /// address: 0x40006c28 + /// Backup data register 9 + pub const DATA9 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x28); + + /// address: 0x40006c40 + /// Backup data register 10 + pub const DATA10 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x40); + + /// address: 0x40006c44 + /// Backup data register 11 + pub const DATA11 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x44); + + /// address: 0x40006c48 + /// Backup data register 12 + pub const DATA12 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x48); + + /// address: 0x40006c4c + /// Backup data register 13 + pub const DATA13 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x4c); + + /// address: 0x40006c50 + /// Backup data register 14 + pub const DATA14 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x50); + + /// address: 0x40006c54 + /// Backup data register 15 + pub const DATA15 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x54); + + /// address: 0x40006c58 + /// Backup data register 16 + pub const DATA16 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x58); + + /// address: 0x40006c5c + /// Backup data register 17 + pub const DATA17 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x5c); + + /// address: 0x40006c60 + /// Backup data register 18 + pub const DATA18 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x60); + + /// address: 0x40006c64 + /// Backup data register 19 + pub const DATA19 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x64); + + /// address: 0x40006c68 + /// Backup data register 20 + pub const DATA20 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x68); + + /// address: 0x40006c6c + /// Backup data register 21 + pub const DATA21 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x6c); + + /// address: 0x40006c70 + /// Backup data register 22 + pub const DATA22 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x70); + + /// address: 0x40006c74 + /// Backup data register 23 + pub const DATA23 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x74); + + /// address: 0x40006c78 + /// Backup data register 24 + pub const DATA24 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x78); + + /// address: 0x40006c7c + /// Backup data register 25 + pub const DATA25 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x7c); + + /// address: 0x40006c80 + /// Backup data register 26 + pub const DATA26 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x80); + + /// address: 0x40006c84 + /// Backup data register 27 + pub const DATA27 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x84); + + /// address: 0x40006c88 + /// Backup data register 28 + pub const DATA28 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x88); + + /// address: 0x40006c8c + /// Backup data register 29 + pub const DATA29 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x8c); + + /// address: 0x40006c90 + /// Backup data register 30 + pub const DATA30 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x90); + + /// address: 0x40006c94 + /// Backup data register 31 + pub const DATA31 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x94); + + /// address: 0x40006c98 + /// Backup data register 32 + pub const DATA32 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x98); + + /// address: 0x40006c9c + /// Backup data register 33 + pub const DATA33 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0x9c); + + /// address: 0x40006ca0 + /// Backup data register 34 + pub const DATA34 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xa0); + + /// address: 0x40006ca4 + /// Backup data register 35 + pub const DATA35 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xa4); + + /// address: 0x40006ca8 + /// Backup data register 36 + pub const DATA36 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xa8); + + /// address: 0x40006cac + /// Backup data register 37 + pub const DATA37 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xac); + + /// address: 0x40006cb0 + /// Backup data register 38 + pub const DATA38 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xb0); + + /// address: 0x40006cb4 + /// Backup data register 39 + pub const DATA39 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xb4); + + /// address: 0x40006cb8 + /// Backup data register 40 + pub const DATA40 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xb8); + + /// address: 0x40006cbc + /// Backup data register 41 + pub const DATA41 = @intToPtr(*volatile Mmio(16, packed struct { + /// Backup data + DATA: u16, + }), base_address + 0xbc); + + /// address: 0x40006c2c + /// RTC signal output control register + pub const OCTL = @intToPtr(*volatile Mmio(16, packed struct { + /// RTC clock calibration value + RCCV: u7, + /// RTC clock calibration output enable + COEN: u1, + /// RTC alarm or second signal output enable + ASOEN: u1, + /// RTC output selection + ROSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2c); + + /// address: 0x40006c30 + /// Tamper pin control register + pub const TPCTL = @intToPtr(*volatile Mmio(16, packed struct { + /// TAMPER detection enable + TPEN: u1, + /// TAMPER pin active level + TPAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x30); + + /// address: 0x40006c34 + /// Tamper control and status register + pub const TPCS = @intToPtr(*volatile Mmio(16, packed struct { + /// Tamper event reset + TER: u1, + /// Tamper interrupt reset + TIR: u1, + /// Tamper interrupt enable + TPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tamper event flag + TEF: u1, + /// Tamper interrupt flag + TIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x34); + }; + + /// Controller area network + pub const CAN0 = struct { + pub const base_address = 0x40006400; + + /// address: 0x40006400 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Initial working mode + IWMOD: u1, + /// Sleep working mode + SLPWMOD: u1, + /// Transmit FIFO order + TFO: u1, + /// Receive FIFO overwrite disable + RFOD: u1, + /// Automatic retransmission disable + ARD: u1, + /// Automatic wakeup + AWU: u1, + /// Automatic bus-off recovery + ABOR: u1, + /// Time-triggered communication + TTC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Software reset + SWRST: u1, + /// Debug freeze + DFZ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006404 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Initial working state + IWS: u1, + /// Sleep working state + SLPWS: u1, + /// Error interrupt flag + ERRIF: u1, + /// Status change interrupt flag of wakeup + /// from sleep working mode + WUIF: u1, + /// Status change interrupt flag of sleep + /// working mode entering + SLPIF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Transmitting state + TS: u1, + /// Receiving state + RS: u1, + /// Last sample value of RX pin + LASTRX: u1, + /// RX level + RXL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006408 + /// Transmit status register + pub const TSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Mailbox 0 transmit finished + MTF0: u1, + /// Mailbox 0 transmit finished and no error + MTFNERR0: u1, + /// Mailbox 0 arbitration lost + MAL0: u1, + /// Mailbox 0 transmit error + MTE0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Mailbox 0 stop transmitting + MST0: u1, + /// Mailbox 1 transmit finished + MTF1: u1, + /// Mailbox 1 transmit finished and no error + MTFNERR1: u1, + /// Mailbox 1 arbitration lost + MAL1: u1, + /// Mailbox 1 transmit error + MTE1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Mailbox 1 stop transmitting + MST1: u1, + /// Mailbox 2 transmit finished + MTF2: u1, + /// Mailbox 2 transmit finished and no error + MTFNERR2: u1, + /// Mailbox 2 arbitration lost + MAL2: u1, + /// Mailbox 2 transmit error + MTE2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mailbox 2 stop transmitting + MST2: u1, + /// number of the transmit FIFO mailbox in + /// which the frame will be transmitted if at least one mailbox is empty + NUM: u2, + /// Transmit mailbox 0 empty + TME0: u1, + /// Transmit mailbox 1 empty + TME1: u1, + /// Transmit mailbox 2 empty + TME2: u1, + /// Transmit mailbox 0 last sending + /// in transmit FIFO + TMLS0: u1, + /// Transmit mailbox 1 last sending + /// in transmit FIFO + TMLS1: u1, + /// Transmit mailbox 2 last sending + /// in transmit FIFO + TMLS2: u1, + }), base_address + 0x8); + + /// address: 0x4000640c + /// Receive message FIFO0 register + pub const RFIFO0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO0 length + RFL0: u2, + reserved0: u1, + /// Receive FIFO0 full + RFF0: u1, + /// Receive FIFO0 overfull + RFO0: u1, + /// Receive FIFO0 dequeue + RFD0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006410 + /// Receive message FIFO1 register + pub const RFIFO1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO1 length + RFL1: u2, + reserved0: u1, + /// Receive FIFO1 full + RFF1: u1, + /// Receive FIFO1 overfull + RFO1: u1, + /// Receive FIFO1 dequeue + RFD1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006414 + /// Interrupt enable register + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit mailbox empty interrupt enable + TMEIE: u1, + /// Receive FIFO0 not empty interrupt enable + RFNEIE0: u1, + /// Receive FIFO0 full interrupt enable + RFFIE0: u1, + /// Receive FIFO0 overfull interrupt enable + RFOIE0: u1, + /// Receive FIFO1 not empty interrupt enable + RFNEIE1: u1, + /// Receive FIFO1 full interrupt enable + RFFIE1: u1, + /// Receive FIFO1 overfull interrupt enable + RFOIE1: u1, + reserved0: u1, + /// Warning error interrupt enable + WERRIE: u1, + /// Passive error interrupt enable + PERRIE: u1, + /// Bus-off interrupt enable + BOIE: u1, + /// Error number interrupt enable + ERRNIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Error interrupt enable + ERRIE: u1, + /// Wakeup interrupt enable + WIE: u1, + /// Sleep working interrupt enable + SLPWIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006418 + /// Error register + pub const ERR = @intToPtr(*volatile Mmio(32, packed struct { + /// Warning error + WERR: u1, + /// Passive error + PERR: u1, + /// Bus-off error + BOERR: u1, + reserved0: u1, + /// Error number + ERRN: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transmit Error Count defined + /// by the CAN standard + TECNT: u8, + /// Receive Error Count defined + /// by the CAN standard + RECNT: u8, + }), base_address + 0x18); + + /// address: 0x4000641c + /// Bit timing register + pub const BT = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud rate prescaler + BAUDPSC: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Bit segment 1 + BS1: u4, + /// Bit segment 2 + BS2: u3, + reserved6: u1, + /// Resynchronization jump width + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Loopback communication mode + LCMOD: u1, + /// Silent communication mode + SCMOD: u1, + }), base_address + 0x1c); + + /// address: 0x40006580 + /// Transmit mailbox identifier register 0 + pub const TMI0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x180); + + /// address: 0x40006584 + /// Transmit mailbox property register 0 + pub const TMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x184); + + /// address: 0x40006588 + /// Transmit mailbox data0 register + pub const TMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x188); + + /// address: 0x4000658c + /// Transmit mailbox data1 register + pub const TMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x18c); + + /// address: 0x40006590 + /// Transmit mailbox identifier register 1 + pub const TMI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x190); + + /// address: 0x40006594 + /// Transmit mailbox property register 1 + pub const TMP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x194); + + /// address: 0x40006598 + /// Transmit mailbox data0 register + pub const TMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x198); + + /// address: 0x4000659c + /// Transmit mailbox data1 register + pub const TMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x19c); + + /// address: 0x400065a0 + /// Transmit mailbox identifier register 2 + pub const TMI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1a0); + + /// address: 0x400065a4 + /// Transmit mailbox property register 2 + pub const TMP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x1a4); + + /// address: 0x400065a8 + /// Transmit mailbox data0 register + pub const TMDATA02 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1a8); + + /// address: 0x400065ac + /// Transmit mailbox data1 register + pub const TMDATA12 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1ac); + + /// address: 0x400065b0 + /// Receive FIFO mailbox identifier register + pub const RFIFOMI0 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1b0); + + /// address: 0x400065b4 + /// Receive FIFO0 mailbox property register + pub const RFIFOMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), base_address + 0x1b4); + + /// address: 0x400065b8 + /// Receive FIFO0 mailbox data0 register + pub const RFIFOMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1b8); + + /// address: 0x400065bc + /// Receive FIFO0 mailbox data1 register + pub const RFIFOMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1bc); + + /// address: 0x400065c0 + /// Receive FIFO1 mailbox identifier register + pub const RFIFOMI1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1c0); + + /// address: 0x400065c4 + /// Receive FIFO1 mailbox property register + pub const RFIFOMP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), base_address + 0x1c4); + + /// address: 0x400065c8 + /// Receive FIFO1 mailbox data0 register + pub const RFIFOMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1c8); + + /// address: 0x400065cc + /// Receive FIFO1 mailbox data1 register + pub const RFIFOMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006600 + /// Filter control register + pub const FCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter lock disable + FLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Header bank of CAN1 filter + HBC1F: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006604 + /// Filter mode configuration register + pub const FMCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FMOD0: u1, + /// Filter mode + FMOD1: u1, + /// Filter mode + FMOD2: u1, + /// Filter mode + FMOD3: u1, + /// Filter mode + FMOD4: u1, + /// Filter mode + FMOD5: u1, + /// Filter mode + FMOD6: u1, + /// Filter mode + FMOD7: u1, + /// Filter mode + FMOD8: u1, + /// Filter mode + FMOD9: u1, + /// Filter mode + FMOD10: u1, + /// Filter mode + FMOD11: u1, + /// Filter mode + FMOD12: u1, + /// Filter mode + FMOD13: u1, + /// Filter mode + FMOD14: u1, + /// Filter mode + FMOD15: u1, + /// Filter mode + FMOD16: u1, + /// Filter mode + FMOD17: u1, + /// Filter mode + FMOD18: u1, + /// Filter mode + FMOD19: u1, + /// Filter mode + FMOD20: u1, + /// Filter mode + FMOD21: u1, + /// Filter mode + FMOD22: u1, + /// Filter mode + FMOD23: u1, + /// Filter mode + FMOD24: u1, + /// Filter mode + FMOD25: u1, + /// Filter mode + FMOD26: u1, + /// Filter mode + FMOD27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x4000660c + /// Filter scale configuration register + pub const FSCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FS0: u1, + /// Filter scale configuration + FS1: u1, + /// Filter scale configuration + FS2: u1, + /// Filter scale configuration + FS3: u1, + /// Filter scale configuration + FS4: u1, + /// Filter scale configuration + FS5: u1, + /// Filter scale configuration + FS6: u1, + /// Filter scale configuration + FS7: u1, + /// Filter scale configuration + FS8: u1, + /// Filter scale configuration + FS9: u1, + /// Filter scale configuration + FS10: u1, + /// Filter scale configuration + FS11: u1, + /// Filter scale configuration + FS12: u1, + /// Filter scale configuration + FS13: u1, + /// Filter scale configuration + FS14: u1, + /// Filter scale configuration + FS15: u1, + /// Filter scale configuration + FS16: u1, + /// Filter scale configuration + FS17: u1, + /// Filter scale configuration + FS18: u1, + /// Filter scale configuration + FS19: u1, + /// Filter scale configuration + FS20: u1, + /// Filter scale configuration + FS21: u1, + /// Filter scale configuration + FS22: u1, + /// Filter scale configuration + FS23: u1, + /// Filter scale configuration + FS24: u1, + /// Filter scale configuration + FS25: u1, + /// Filter scale configuration + FS26: u1, + /// Filter scale configuration + FS27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006614 + /// Filter associated FIFO register + pub const FAFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter 0 associated with FIFO + FAF0: u1, + /// Filter 1 associated with FIFO + FAF1: u1, + /// Filter 2 associated with FIFO + FAF2: u1, + /// Filter 3 associated with FIFO + FAF3: u1, + /// Filter 4 associated with FIFO + FAF4: u1, + /// Filter 5 associated with FIFO + FAF5: u1, + /// Filter 6 associated with FIFO + FAF6: u1, + /// Filter 7 associated with FIFO + FAF7: u1, + /// Filter 8 associated with FIFO + FAF8: u1, + /// Filter 9 associated with FIFO + FAF9: u1, + /// Filter 10 associated with FIFO + FAF10: u1, + /// Filter 11 associated with FIFO + FAF11: u1, + /// Filter 12 associated with FIFO + FAF12: u1, + /// Filter 13 associated with FIFO + FAF13: u1, + /// Filter 14 associated with FIFO + FAF14: u1, + /// Filter 15 associated with FIFO + FAF15: u1, + /// Filter 16 associated with FIFO + FAF16: u1, + /// Filter 17 associated with FIFO + FAF17: u1, + /// Filter 18 associated with FIFO + FAF18: u1, + /// Filter 19 associated with FIFO + FAF19: u1, + /// Filter 20 associated with FIFO + FAF20: u1, + /// Filter 21 associated with FIFO + FAF21: u1, + /// Filter 22 associated with FIFO + FAF22: u1, + /// Filter 23 associated with FIFO + FAF23: u1, + /// Filter 24 associated with FIFO + FAF24: u1, + /// Filter 25 associated with FIFO + FAF25: u1, + /// Filter 26 associated with FIFO + FAF26: u1, + /// Filter 27 associated with FIFO + FAF27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x4000661c + /// Filter working register + pub const FW = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter working + FW0: u1, + /// Filter working + FW1: u1, + /// Filter working + FW2: u1, + /// Filter working + FW3: u1, + /// Filter working + FW4: u1, + /// Filter working + FW5: u1, + /// Filter working + FW6: u1, + /// Filter working + FW7: u1, + /// Filter working + FW8: u1, + /// Filter working + FW9: u1, + /// Filter working + FW10: u1, + /// Filter working + FW11: u1, + /// Filter working + FW12: u1, + /// Filter working + FW13: u1, + /// Filter working + FW14: u1, + /// Filter working + FW15: u1, + /// Filter working + FW16: u1, + /// Filter working + FW17: u1, + /// Filter working + FW18: u1, + /// Filter working + FW19: u1, + /// Filter working + FW20: u1, + /// Filter working + FW21: u1, + /// Filter working + FW22: u1, + /// Filter working + FW23: u1, + /// Filter working + FW24: u1, + /// Filter working + FW25: u1, + /// Filter working + FW26: u1, + /// Filter working + FW27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006640 + /// Filter 0 data 0 register + pub const F0DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x240); + + /// address: 0x40006644 + /// Filter 0 data 1 register + pub const F0DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x244); + + /// address: 0x40006648 + /// Filter 1 data 0 register + pub const F1DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x248); + + /// address: 0x4000664c + /// Filter 1 data 1 register + pub const F1DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x24c); + + /// address: 0x40006650 + /// Filter 2 data 0 register + pub const F2DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x250); + + /// address: 0x40006654 + /// Filter 2 data 1 register + pub const F2DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x254); + + /// address: 0x40006658 + /// Filter 3 data 0 register + pub const F3DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x258); + + /// address: 0x4000665c + /// Filter 3 data 1 register + pub const F3DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x25c); + + /// address: 0x40006660 + /// Filter 4 data 0 register + pub const F4DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x260); + + /// address: 0x40006664 + /// Filter 4 data 1 register + pub const F4DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x264); + + /// address: 0x40006668 + /// Filter 5 data 0 register + pub const F5DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x268); + + /// address: 0x4000666c + /// Filter 5 data 1 register + pub const F5DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x26c); + + /// address: 0x40006670 + /// Filter 6 data 0 register + pub const F6DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x270); + + /// address: 0x40006674 + /// Filter 6 data 1 register + pub const F6DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x274); + + /// address: 0x40006678 + /// Filter 7 data 0 register + pub const F7DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x278); + + /// address: 0x4000667c + /// Filter 7 data 1 register + pub const F7DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x27c); + + /// address: 0x40006680 + /// Filter 8 data 0 register + pub const F8DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x280); + + /// address: 0x40006684 + /// Filter 8 data 1 register + pub const F8DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x284); + + /// address: 0x40006688 + /// Filter 9 data 0 register + pub const F9DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x288); + + /// address: 0x4000668c + /// Filter 9 data 1 register + pub const F9DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x28c); + + /// address: 0x40006690 + /// Filter 10 data 0 register + pub const F10DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x290); + + /// address: 0x40006694 + /// Filter 10 data 1 register + pub const F10DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x294); + + /// address: 0x40006698 + /// Filter 11 data 0 register + pub const F11DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x298); + + /// address: 0x4000669c + /// Filter 11 data 1 register + pub const F11DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x29c); + + /// address: 0x400066a0 + /// Filter 12 data 0 register + pub const F12DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a0); + + /// address: 0x400066a4 + /// Filter 12 data 1 register + pub const F12DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a4); + + /// address: 0x400066a8 + /// Filter 13 data 0 register + pub const F13DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a8); + + /// address: 0x400066ac + /// Filter 13 data 1 register + pub const F13DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2ac); + + /// address: 0x400066b0 + /// Filter 14 data 0 register + pub const F14DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b0); + + /// address: 0x400066b4 + /// Filter 14 data 1 register + pub const F14DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b4); + + /// address: 0x400066b8 + /// Filter 15 data 0 register + pub const F15DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b8); + + /// address: 0x400066bc + /// Filter 15 data 1 register + pub const F15DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2bc); + + /// address: 0x400066c0 + /// Filter 16 data 0 register + pub const F16DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c0); + + /// address: 0x400066c4 + /// Filter 16 data 1 register + pub const F16DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c4); + + /// address: 0x400066c8 + /// Filter 17 data 0 register + pub const F17DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c8); + + /// address: 0x400066cc + /// Filter 17 data 1 register + pub const F17DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2cc); + + /// address: 0x400066d0 + /// Filter 18 data 0 register + pub const F18DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d0); + + /// address: 0x400066d4 + /// Filter 18 data 1 register + pub const F18DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d4); + + /// address: 0x400066d8 + /// Filter 19 data 0 register + pub const F19DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d8); + + /// address: 0x400066dc + /// Filter 19 data 1 register + pub const F19DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2dc); + + /// address: 0x400066e0 + /// Filter 20 data 0 register + pub const F20DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e0); + + /// address: 0x400066e4 + /// Filter 20 data 1 register + pub const F20DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e4); + + /// address: 0x400066e8 + /// Filter 21 data 0 register + pub const F21DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e8); + + /// address: 0x400066ec + /// Filter 21 data 1 register + pub const F21DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2ec); + + /// address: 0x400066f0 + /// Filter 22 data 0 register + pub const F22DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f0); + + /// address: 0x400066f4 + /// Filter 22 data 1 register + pub const F22DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f4); + + /// address: 0x400066f8 + /// Filter 23 data 0 register + pub const F23DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f8); + + /// address: 0x400066fc + /// Filter 23 data 1 register + pub const F23DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006700 + /// Filter 24 data 0 register + pub const F24DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x300); + + /// address: 0x40006704 + /// Filter 24 data 1 register + pub const F24DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x304); + + /// address: 0x40006708 + /// Filter 25 data 0 register + pub const F25DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x308); + + /// address: 0x4000670c + /// Filter 25 data 1 register + pub const F25DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x30c); + + /// address: 0x40006710 + /// Filter 26 data 0 register + pub const F26DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x310); + + /// address: 0x40006714 + /// Filter 26 data 1 register + pub const F26DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x314); + + /// address: 0x40006718 + /// Filter 27 data 0 register + pub const F27DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x318); + + /// address: 0x4000671c + /// Filter 27 data 1 register + pub const F27DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x31c); + }; + pub const CAN1 = struct { + pub const base_address = 0x40006800; + + /// address: 0x40006800 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Initial working mode + IWMOD: u1, + /// Sleep working mode + SLPWMOD: u1, + /// Transmit FIFO order + TFO: u1, + /// Receive FIFO overwrite disable + RFOD: u1, + /// Automatic retransmission disable + ARD: u1, + /// Automatic wakeup + AWU: u1, + /// Automatic bus-off recovery + ABOR: u1, + /// Time-triggered communication + TTC: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Software reset + SWRST: u1, + /// Debug freeze + DFZ: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x0); + + /// address: 0x40006804 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Initial working state + IWS: u1, + /// Sleep working state + SLPWS: u1, + /// Error interrupt flag + ERRIF: u1, + /// Status change interrupt flag of wakeup + /// from sleep working mode + WUIF: u1, + /// Status change interrupt flag of sleep + /// working mode entering + SLPIF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Transmitting state + TS: u1, + /// Receiving state + RS: u1, + /// Last sample value of RX pin + LASTRX: u1, + /// RX level + RXL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x40006808 + /// Transmit status register + pub const TSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Mailbox 0 transmit finished + MTF0: u1, + /// Mailbox 0 transmit finished and no error + MTFNERR0: u1, + /// Mailbox 0 arbitration lost + MAL0: u1, + /// Mailbox 0 transmit error + MTE0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Mailbox 0 stop transmitting + MST0: u1, + /// Mailbox 1 transmit finished + MTF1: u1, + /// Mailbox 1 transmit finished and no error + MTFNERR1: u1, + /// Mailbox 1 arbitration lost + MAL1: u1, + /// Mailbox 1 transmit error + MTE1: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Mailbox 1 stop transmitting + MST1: u1, + /// Mailbox 2 transmit finished + MTF2: u1, + /// Mailbox 2 transmit finished and no error + MTFNERR2: u1, + /// Mailbox 2 arbitration lost + MAL2: u1, + /// Mailbox 2 transmit error + MTE2: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Mailbox 2 stop transmitting + MST2: u1, + /// number of the transmit FIFO mailbox in + /// which the frame will be transmitted if at least one mailbox is empty + NUM: u2, + /// Transmit mailbox 0 empty + TME0: u1, + /// Transmit mailbox 1 empty + TME1: u1, + /// Transmit mailbox 2 empty + TME2: u1, + /// Transmit mailbox 0 last sending + /// in transmit FIFO + TMLS0: u1, + /// Transmit mailbox 1 last sending + /// in transmit FIFO + TMLS1: u1, + /// Transmit mailbox 2 last sending + /// in transmit FIFO + TMLS2: u1, + }), base_address + 0x8); + + /// address: 0x4000680c + /// Receive message FIFO0 register + pub const RFIFO0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO0 length + RFL0: u2, + reserved0: u1, + /// Receive FIFO0 full + RFF0: u1, + /// Receive FIFO0 overfull + RFO0: u1, + /// Receive FIFO0 dequeue + RFD0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40006810 + /// Receive message FIFO1 register + pub const RFIFO1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO1 length + RFL1: u2, + reserved0: u1, + /// Receive FIFO1 full + RFF1: u1, + /// Receive FIFO1 overfull + RFO1: u1, + /// Receive FIFO1 dequeue + RFD1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x10); + + /// address: 0x40006814 + /// Interrupt enable register + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit mailbox empty interrupt enable + TMEIE: u1, + /// Receive FIFO0 not empty interrupt enable + RFNEIE0: u1, + /// Receive FIFO0 full interrupt enable + RFFIE0: u1, + /// Receive FIFO0 overfull interrupt enable + RFOIE0: u1, + /// Receive FIFO1 not empty interrupt enable + RFNEIE1: u1, + /// Receive FIFO1 full interrupt enable + RFFIE1: u1, + /// Receive FIFO1 overfull interrupt enable + RFOIE1: u1, + reserved0: u1, + /// Warning error interrupt enable + WERRIE: u1, + /// Passive error interrupt enable + PERRIE: u1, + /// Bus-off interrupt enable + BOIE: u1, + /// Error number interrupt enable + ERRNIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Error interrupt enable + ERRIE: u1, + /// Wakeup interrupt enable + WIE: u1, + /// Sleep working interrupt enable + SLPWIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x14); + + /// address: 0x40006818 + /// Error register + pub const ERR = @intToPtr(*volatile Mmio(32, packed struct { + /// Warning error + WERR: u1, + /// Passive error + PERR: u1, + /// Bus-off error + BOERR: u1, + reserved0: u1, + /// Error number + ERRN: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transmit Error Count defined + /// by the CAN standard + TECNT: u8, + /// Receive Error Count defined + /// by the CAN standard + RECNT: u8, + }), base_address + 0x18); + + /// address: 0x4000681c + /// Bit timing register + pub const BT = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud rate prescaler + BAUDPSC: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Bit segment 1 + BS1: u4, + /// Bit segment 2 + BS2: u3, + reserved6: u1, + /// Resynchronization jump width + SJW: u2, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Loopback communication mode + LCMOD: u1, + /// Silent communication mode + SCMOD: u1, + }), base_address + 0x1c); + + /// address: 0x40006980 + /// Transmit mailbox identifier register 0 + pub const TMI0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x180); + + /// address: 0x40006984 + /// Transmit mailbox property register 0 + pub const TMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x184); + + /// address: 0x40006988 + /// Transmit mailbox data0 register + pub const TMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x188); + + /// address: 0x4000698c + /// Transmit mailbox data1 register + pub const TMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x18c); + + /// address: 0x40006990 + /// Transmit mailbox identifier register 1 + pub const TMI1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x190); + + /// address: 0x40006994 + /// Transmit mailbox property register 1 + pub const TMP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x194); + + /// address: 0x40006998 + /// Transmit mailbox data0 register + pub const TMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x198); + + /// address: 0x4000699c + /// Transmit mailbox data1 register + pub const TMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x19c); + + /// address: 0x400069a0 + /// Transmit mailbox identifier register 2 + pub const TMI2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1a0); + + /// address: 0x400069a4 + /// Transmit mailbox property register 2 + pub const TMP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Time stamp enable + TSEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Time stamp + TS: u16, + }), base_address + 0x1a4); + + /// address: 0x400069a8 + /// Transmit mailbox data0 register + pub const TMDATA02 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1a8); + + /// address: 0x400069ac + /// Transmit mailbox data1 register + pub const TMDATA12 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1ac); + + /// address: 0x400069b0 + /// Receive FIFO mailbox identifier register + pub const RFIFOMI0 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1b0); + + /// address: 0x400069b4 + /// Receive FIFO0 mailbox property register + pub const RFIFOMP0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), base_address + 0x1b4); + + /// address: 0x400069b8 + /// Receive FIFO0 mailbox data0 register + pub const RFIFOMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1b8); + + /// address: 0x400069bc + /// Receive FIFO0 mailbox data1 register + pub const RFIFOMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1bc); + + /// address: 0x400069c0 + /// Receive FIFO1 mailbox identifier register + pub const RFIFOMI1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), base_address + 0x1c0); + + /// address: 0x400069c4 + /// Receive FIFO1 mailbox property register + pub const RFIFOMP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data length code + DLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), base_address + 0x1c4); + + /// address: 0x400069c8 + /// Receive FIFO1 mailbox data0 register + pub const RFIFOMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), base_address + 0x1c8); + + /// address: 0x400069cc + /// Receive FIFO1 mailbox data1 register + pub const RFIFOMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), base_address + 0x1cc); + + /// address: 0x40006a00 + /// Filter control register + pub const FCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter lock disable + FLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Header bank of CAN1 filter + HBC1F: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x200); + + /// address: 0x40006a04 + /// Filter mode configuration register + pub const FMCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter mode + FMOD0: u1, + /// Filter mode + FMOD1: u1, + /// Filter mode + FMOD2: u1, + /// Filter mode + FMOD3: u1, + /// Filter mode + FMOD4: u1, + /// Filter mode + FMOD5: u1, + /// Filter mode + FMOD6: u1, + /// Filter mode + FMOD7: u1, + /// Filter mode + FMOD8: u1, + /// Filter mode + FMOD9: u1, + /// Filter mode + FMOD10: u1, + /// Filter mode + FMOD11: u1, + /// Filter mode + FMOD12: u1, + /// Filter mode + FMOD13: u1, + /// Filter mode + FMOD14: u1, + /// Filter mode + FMOD15: u1, + /// Filter mode + FMOD16: u1, + /// Filter mode + FMOD17: u1, + /// Filter mode + FMOD18: u1, + /// Filter mode + FMOD19: u1, + /// Filter mode + FMOD20: u1, + /// Filter mode + FMOD21: u1, + /// Filter mode + FMOD22: u1, + /// Filter mode + FMOD23: u1, + /// Filter mode + FMOD24: u1, + /// Filter mode + FMOD25: u1, + /// Filter mode + FMOD26: u1, + /// Filter mode + FMOD27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x204); + + /// address: 0x40006a0c + /// Filter scale configuration register + pub const FSCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter scale configuration + FS0: u1, + /// Filter scale configuration + FS1: u1, + /// Filter scale configuration + FS2: u1, + /// Filter scale configuration + FS3: u1, + /// Filter scale configuration + FS4: u1, + /// Filter scale configuration + FS5: u1, + /// Filter scale configuration + FS6: u1, + /// Filter scale configuration + FS7: u1, + /// Filter scale configuration + FS8: u1, + /// Filter scale configuration + FS9: u1, + /// Filter scale configuration + FS10: u1, + /// Filter scale configuration + FS11: u1, + /// Filter scale configuration + FS12: u1, + /// Filter scale configuration + FS13: u1, + /// Filter scale configuration + FS14: u1, + /// Filter scale configuration + FS15: u1, + /// Filter scale configuration + FS16: u1, + /// Filter scale configuration + FS17: u1, + /// Filter scale configuration + FS18: u1, + /// Filter scale configuration + FS19: u1, + /// Filter scale configuration + FS20: u1, + /// Filter scale configuration + FS21: u1, + /// Filter scale configuration + FS22: u1, + /// Filter scale configuration + FS23: u1, + /// Filter scale configuration + FS24: u1, + /// Filter scale configuration + FS25: u1, + /// Filter scale configuration + FS26: u1, + /// Filter scale configuration + FS27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20c); + + /// address: 0x40006a14 + /// Filter associated FIFO register + pub const FAFIFO = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter 0 associated with FIFO + FAF0: u1, + /// Filter 1 associated with FIFO + FAF1: u1, + /// Filter 2 associated with FIFO + FAF2: u1, + /// Filter 3 associated with FIFO + FAF3: u1, + /// Filter 4 associated with FIFO + FAF4: u1, + /// Filter 5 associated with FIFO + FAF5: u1, + /// Filter 6 associated with FIFO + FAF6: u1, + /// Filter 7 associated with FIFO + FAF7: u1, + /// Filter 8 associated with FIFO + FAF8: u1, + /// Filter 9 associated with FIFO + FAF9: u1, + /// Filter 10 associated with FIFO + FAF10: u1, + /// Filter 11 associated with FIFO + FAF11: u1, + /// Filter 12 associated with FIFO + FAF12: u1, + /// Filter 13 associated with FIFO + FAF13: u1, + /// Filter 14 associated with FIFO + FAF14: u1, + /// Filter 15 associated with FIFO + FAF15: u1, + /// Filter 16 associated with FIFO + FAF16: u1, + /// Filter 17 associated with FIFO + FAF17: u1, + /// Filter 18 associated with FIFO + FAF18: u1, + /// Filter 19 associated with FIFO + FAF19: u1, + /// Filter 20 associated with FIFO + FAF20: u1, + /// Filter 21 associated with FIFO + FAF21: u1, + /// Filter 22 associated with FIFO + FAF22: u1, + /// Filter 23 associated with FIFO + FAF23: u1, + /// Filter 24 associated with FIFO + FAF24: u1, + /// Filter 25 associated with FIFO + FAF25: u1, + /// Filter 26 associated with FIFO + FAF26: u1, + /// Filter 27 associated with FIFO + FAF27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x214); + + /// address: 0x40006a1c + /// Filter working register + pub const FW = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter working + FW0: u1, + /// Filter working + FW1: u1, + /// Filter working + FW2: u1, + /// Filter working + FW3: u1, + /// Filter working + FW4: u1, + /// Filter working + FW5: u1, + /// Filter working + FW6: u1, + /// Filter working + FW7: u1, + /// Filter working + FW8: u1, + /// Filter working + FW9: u1, + /// Filter working + FW10: u1, + /// Filter working + FW11: u1, + /// Filter working + FW12: u1, + /// Filter working + FW13: u1, + /// Filter working + FW14: u1, + /// Filter working + FW15: u1, + /// Filter working + FW16: u1, + /// Filter working + FW17: u1, + /// Filter working + FW18: u1, + /// Filter working + FW19: u1, + /// Filter working + FW20: u1, + /// Filter working + FW21: u1, + /// Filter working + FW22: u1, + /// Filter working + FW23: u1, + /// Filter working + FW24: u1, + /// Filter working + FW25: u1, + /// Filter working + FW26: u1, + /// Filter working + FW27: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x21c); + + /// address: 0x40006a40 + /// Filter 0 data 0 register + pub const F0DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x240); + + /// address: 0x40006a44 + /// Filter 0 data 1 register + pub const F0DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x244); + + /// address: 0x40006a48 + /// Filter 1 data 0 register + pub const F1DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x248); + + /// address: 0x40006a4c + /// Filter 1 data 1 register + pub const F1DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x24c); + + /// address: 0x40006a50 + /// Filter 2 data 0 register + pub const F2DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x250); + + /// address: 0x40006a54 + /// Filter 2 data 1 register + pub const F2DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x254); + + /// address: 0x40006a58 + /// Filter 3 data 0 register + pub const F3DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x258); + + /// address: 0x40006a5c + /// Filter 3 data 1 register + pub const F3DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x25c); + + /// address: 0x40006a60 + /// Filter 4 data 0 register + pub const F4DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x260); + + /// address: 0x40006a64 + /// Filter 4 data 1 register + pub const F4DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x264); + + /// address: 0x40006a68 + /// Filter 5 data 0 register + pub const F5DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x268); + + /// address: 0x40006a6c + /// Filter 5 data 1 register + pub const F5DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x26c); + + /// address: 0x40006a70 + /// Filter 6 data 0 register + pub const F6DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x270); + + /// address: 0x40006a74 + /// Filter 6 data 1 register + pub const F6DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x274); + + /// address: 0x40006a78 + /// Filter 7 data 0 register + pub const F7DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x278); + + /// address: 0x40006a7c + /// Filter 7 data 1 register + pub const F7DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x27c); + + /// address: 0x40006a80 + /// Filter 8 data 0 register + pub const F8DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x280); + + /// address: 0x40006a84 + /// Filter 8 data 1 register + pub const F8DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x284); + + /// address: 0x40006a88 + /// Filter 9 data 0 register + pub const F9DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x288); + + /// address: 0x40006a8c + /// Filter 9 data 1 register + pub const F9DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x28c); + + /// address: 0x40006a90 + /// Filter 10 data 0 register + pub const F10DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x290); + + /// address: 0x40006a94 + /// Filter 10 data 1 register + pub const F10DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x294); + + /// address: 0x40006a98 + /// Filter 11 data 0 register + pub const F11DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x298); + + /// address: 0x40006a9c + /// Filter 11 data 1 register + pub const F11DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x29c); + + /// address: 0x40006aa0 + /// Filter 12 data 0 register + pub const F12DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a0); + + /// address: 0x40006aa4 + /// Filter 12 data 1 register + pub const F12DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a4); + + /// address: 0x40006aa8 + /// Filter 13 data 0 register + pub const F13DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2a8); + + /// address: 0x40006aac + /// Filter 13 data 1 register + pub const F13DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2ac); + + /// address: 0x40006ab0 + /// Filter 14 data 0 register + pub const F14DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b0); + + /// address: 0x40006ab4 + /// Filter 14 data 1 register + pub const F14DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b4); + + /// address: 0x40006ab8 + /// Filter 15 data 0 register + pub const F15DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2b8); + + /// address: 0x40006abc + /// Filter 15 data 1 register + pub const F15DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2bc); + + /// address: 0x40006ac0 + /// Filter 16 data 0 register + pub const F16DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c0); + + /// address: 0x40006ac4 + /// Filter 16 data 1 register + pub const F16DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c4); + + /// address: 0x40006ac8 + /// Filter 17 data 0 register + pub const F17DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2c8); + + /// address: 0x40006acc + /// Filter 17 data 1 register + pub const F17DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2cc); + + /// address: 0x40006ad0 + /// Filter 18 data 0 register + pub const F18DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d0); + + /// address: 0x40006ad4 + /// Filter 18 data 1 register + pub const F18DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d4); + + /// address: 0x40006ad8 + /// Filter 19 data 0 register + pub const F19DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2d8); + + /// address: 0x40006adc + /// Filter 19 data 1 register + pub const F19DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2dc); + + /// address: 0x40006ae0 + /// Filter 20 data 0 register + pub const F20DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e0); + + /// address: 0x40006ae4 + /// Filter 20 data 1 register + pub const F20DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e4); + + /// address: 0x40006ae8 + /// Filter 21 data 0 register + pub const F21DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2e8); + + /// address: 0x40006aec + /// Filter 21 data 1 register + pub const F21DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2ec); + + /// address: 0x40006af0 + /// Filter 22 data 0 register + pub const F22DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f0); + + /// address: 0x40006af4 + /// Filter 22 data 1 register + pub const F22DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f4); + + /// address: 0x40006af8 + /// Filter 23 data 0 register + pub const F23DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2f8); + + /// address: 0x40006afc + /// Filter 23 data 1 register + pub const F23DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x2fc); + + /// address: 0x40006b00 + /// Filter 24 data 0 register + pub const F24DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x300); + + /// address: 0x40006b04 + /// Filter 24 data 1 register + pub const F24DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x304); + + /// address: 0x40006b08 + /// Filter 25 data 0 register + pub const F25DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x308); + + /// address: 0x40006b0c + /// Filter 25 data 1 register + pub const F25DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x30c); + + /// address: 0x40006b10 + /// Filter 26 data 0 register + pub const F26DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x310); + + /// address: 0x40006b14 + /// Filter 26 data 1 register + pub const F26DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x314); + + /// address: 0x40006b18 + /// Filter 27 data 0 register + pub const F27DATA0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x318); + + /// address: 0x40006b1c + /// Filter 27 data 1 register + pub const F27DATA1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), base_address + 0x31c); + }; + + /// cyclic redundancy check calculation unit + pub const CRC = struct { + pub const base_address = 0x40023000; + + /// address: 0x40023000 + /// Data register + pub const DATA = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40023004 + /// Free data register + pub const FDATA = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); + + /// address: 0x40023008 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// reset bit + RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + + /// Digital-to-analog converter + pub const DAC = struct { + pub const base_address = 0x40007400; + + /// address: 0x40007400 + /// control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 enable + DEN0: u1, + /// DAC0 output buffer turn off + DBOFF0: u1, + /// DAC0 trigger enable + DTEN0: u1, + /// DAC0 trigger selection + DTSEL0: u3, + /// DAC0 noise wave mode + DWM0: u2, + /// DAC0 noise wave bit width + DWBW0: u4, + /// DAC0 DMA enable + DDMAEN0: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DAC1 enable + DEN1: u1, + /// DAC1 output buffer turn off + DBOFF1: u1, + /// DAC1 trigger enable + DTEN1: u1, + /// DAC1 trigger selection + DTSEL1: u3, + /// DAC1 noise wave mode + DWM1: u2, + /// DAC1 noise wave bit width + DWBW1: u4, + /// DAC1 DMA enable + DDMAEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40007404 + /// software trigger register + pub const SWT = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 software trigger + SWTR0: u1, + /// DAC1 software trigger + SWTR1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40007408 + /// DAC0 12-bit right-aligned data holding register + pub const DAC0_R12DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 12-bit right-aligned + /// data + DAC0_DH: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x8); + + /// address: 0x4000740c + /// DAC0 12-bit left-aligned data holding register + pub const DAC0_L12DH = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC0 12-bit left-aligned + /// data + DAC0_DH: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40007410 + /// DAC0 8-bit right aligned data holding + /// register + pub const DAC0_R8DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 8-bit right-aligned + /// data + DAC0_DH: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40007414 + /// DAC1 12-bit right-aligned data holding + /// register + pub const DAC1_R12DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC1 12-bit right-aligned + /// data + DAC1_DH: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x40007418 + /// DAC1 12-bit left aligned data holding + /// register + pub const DAC1_L12DH = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC1 12-bit left-aligned + /// data + DAC1_DH: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000741c + /// DAC1 8-bit right aligned data holding + /// register + pub const DAC1_R8DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC1 8-bit right-aligned + /// data + DAC1_DH: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1c); + + /// address: 0x40007420 + /// DAC concurrent mode 12-bit right-aligned data holding + /// register + pub const DACC_R12DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 12-bit right-aligned + /// data + DAC0_DH: u12, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC1 12-bit right-aligned + /// data + DAC1_DH: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x20); + + /// address: 0x40007424 + /// DAC concurrent mode 12-bit left aligned data holding + /// register + pub const DACC_L12DH = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DAC0 12-bit left-aligned + /// data + DAC0_DH: u12, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// DAC1 12-bit left-aligned + /// data + DAC1_DH: u12, + }), base_address + 0x24); + + /// address: 0x40007428 + /// DAC concurrent mode 8-bit right aligned data holding + /// register + pub const DACC_R8DH = @intToPtr(*volatile Mmio(32, packed struct { + /// DAC0 8-bit right-aligned + /// data + DAC0_DH: u8, + /// DAC1 8-bit right-aligned + /// data + DAC1_DH: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x28); + + /// address: 0x4000742c + /// DAC0 data output register + pub const DAC0_DO = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x2c); + + /// address: 0x40007430 + /// DAC1 data output register + pub const DAC1_DO = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x30); + }; + + /// Debug support + pub const DBG = struct { + pub const base_address = 0xe0042000; + + /// address: 0xe0042000 + /// ID code register + pub const ID = @intToPtr(*volatile Mmio(32, packed struct { + /// DBG ID code register + ID_CODE: u32, + }), base_address + 0x0); + + /// address: 0xe0042004 + /// Control register 0 + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Sleep mode hold register + SLP_HOLD: u1, + /// Deep-sleep mode hold register + DSLP_HOLD: u1, + /// Standby mode hold register + STB_HOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// FWDGT hold bit + FWDGT_HOLD: u1, + /// WWDGT hold bit + WWDGT_HOLD: u1, + /// TIMER 0 hold bit + TIMER0_HOLD: u1, + /// TIMER 1 hold bit + TIMER1_HOLD: u1, + /// TIMER 2 hold bit + TIMER2_HOLD: u1, + /// TIMER 23 hold bit + TIMER3_HOLD: u1, + /// CAN0 hold bit + CAN0_HOLD: u1, + /// I2C0 hold bit + I2C0_HOLD: u1, + /// I2C1 hold bit + I2C1_HOLD: u1, + reserved5: u1, + /// TIMER4_HOLD + TIMER4_HOLD: u1, + /// TIMER 5 hold bit + TIMER5_HOLD: u1, + /// TIMER 6 hold bit + TIMER6_HOLD: u1, + /// CAN1 hold bit + CAN1_HOLD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x4); + }; + + /// DMA controller + pub const DMA0 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// Interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt flag of channel 0 + GIF0: u1, + /// Full Transfer finish flag of channe 0 + FTFIF0: u1, + /// Half transfer finish flag of channel 0 + HTFIF0: u1, + /// Error flag of channel 0 + ERRIF0: u1, + /// Global interrupt flag of channel 1 + GIF1: u1, + /// Full Transfer finish flag of channe 1 + FTFIF1: u1, + /// Half transfer finish flag of channel 1 + HTFIF1: u1, + /// Error flag of channel 1 + ERRIF1: u1, + /// Global interrupt flag of channel 2 + GIF2: u1, + /// Full Transfer finish flag of channe 2 + FTFIF2: u1, + /// Half transfer finish flag of channel 2 + HTFIF2: u1, + /// Error flag of channel 2 + ERRIF2: u1, + /// Global interrupt flag of channel 3 + GIF3: u1, + /// Full Transfer finish flag of channe 3 + FTFIF3: u1, + /// Half transfer finish flag of channel 3 + HTFIF3: u1, + /// Error flag of channel 3 + ERRIF3: u1, + /// Global interrupt flag of channel 4 + GIF4: u1, + /// Full Transfer finish flag of channe 4 + FTFIF4: u1, + /// Half transfer finish flag of channel 4 + HTFIF4: u1, + /// Error flag of channel 4 + ERRIF4: u1, + /// Global interrupt flag of channel 5 + GIF5: u1, + /// Full Transfer finish flag of channe 5 + FTFIF5: u1, + /// Half transfer finish flag of channel 5 + HTFIF5: u1, + /// Error flag of channel 5 + ERRIF5: u1, + /// Global interrupt flag of channel 6 + GIF6: u1, + /// Full Transfer finish flag of channe 6 + FTFIF6: u1, + /// Half transfer finish flag of channel 6 + HTFIF6: u1, + /// Error flag of channel 6 + ERRIF6: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// Interrupt flag clear register + pub const INTC = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear global interrupt flag of channel 0 + GIFC0: u1, + /// Clear bit for full transfer finish flag of channel 0 + FTFIFC0: u1, + /// Clear bit for half transfer finish flag of channel 0 + HTFIFC0: u1, + /// Clear bit for error flag of channel 0 + ERRIFC0: u1, + /// Clear global interrupt flag of channel 1 + GIFC1: u1, + /// Clear bit for full transfer finish flag of channel 1 + FTFIFC1: u1, + /// Clear bit for half transfer finish flag of channel 1 + HTFIFC1: u1, + /// Clear bit for error flag of channel 1 + ERRIFC1: u1, + /// Clear global interrupt flag of channel 2 + GIFC2: u1, + /// Clear bit for full transfer finish flag of channel 2 + FTFIFC2: u1, + /// Clear bit for half transfer finish flag of channel 2 + HTFIFC2: u1, + /// Clear bit for error flag of channel 2 + ERRIFC2: u1, + /// Clear global interrupt flag of channel 3 + GIFC3: u1, + /// Clear bit for full transfer finish flag of channel 3 + FTFIFC3: u1, + /// Clear bit for half transfer finish flag of channel 3 + HTFIFC3: u1, + /// Clear bit for error flag of channel 3 + ERRIFC3: u1, + /// Clear global interrupt flag of channel 4 + GIFC4: u1, + /// Clear bit for full transfer finish flag of channel 4 + FTFIFC4: u1, + /// Clear bit for half transfer finish flag of channel 4 + HTFIFC4: u1, + /// Clear bit for error flag of channel 4 + ERRIFC4: u1, + /// Clear global interrupt flag of channel 5 + GIFC5: u1, + /// Clear bit for full transfer finish flag of channel 5 + FTFIFC5: u1, + /// Clear bit for half transfer finish flag of channel 5 + HTFIFC5: u1, + /// Clear bit for error flag of channel 5 + ERRIFC5: u1, + /// Clear global interrupt flag of channel 6 + GIFC6: u1, + /// Clear bit for full transfer finish flag of channel 6 + FTFIFC6: u1, + /// Clear bit for half transfer finish flag of channel 6 + HTFIFC6: u1, + /// Clear bit for error flag of channel 6 + ERRIFC6: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// Channel 0 control register + pub const CH0CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// Channel 0 counter register + pub const CH0CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// Channel 0 peripheral base address register + pub const CH0PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// Channel 0 memory base address register + pub const CH0MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// Channel 1 control register + pub const CH1CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// Channel 1 counter register + pub const CH1CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// Channel 1 peripheral base address register + pub const CH1PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// Channel 1 memory base address register + pub const CH1MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// Channel 2 control register + pub const CH2CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// Channel 2 counter register + pub const CH2CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// Channel 2 peripheral base address register + pub const CH2PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// Channel 2 memory base address register + pub const CH2MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// Channel 3 control register + pub const CH3CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// Channel 3 counter register + pub const CH3CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// Channel 3 peripheral base address register + pub const CH3PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// Channel 3 memory base address register + pub const CH3MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// Channel 4 control register + pub const CH4CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// Channel 4 counter register + pub const CH4CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// Channel 4 peripheral base address register + pub const CH4PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// Channel 4 memory base address register + pub const CH4MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x64); + + /// address: 0x4002006c + /// Channel 5 control register + pub const CH5CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x6c); + + /// address: 0x40020070 + /// Channel 5 counter register + pub const CH5CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x70); + + /// address: 0x40020074 + /// Channel 5 peripheral base address register + pub const CH5PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x74); + + /// address: 0x40020078 + /// Channel 5 memory base address register + pub const CH5MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x78); + + /// address: 0x40020080 + /// Channel 6 control register + pub const CH6CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x80); + + /// address: 0x40020084 + /// Channel 6 counter register + pub const CH6CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x84); + + /// address: 0x40020088 + /// Channel 6 peripheral base address register + pub const CH6PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x88); + + /// address: 0x4002008c + /// Channel 6 memory base address register + pub const CH6MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x8c); + }; + + /// Direct memory access controller + pub const DMA1 = struct { + pub const base_address = 0x40020000; + + /// address: 0x40020000 + /// Interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt flag of channel 0 + GIF0: u1, + /// Full Transfer finish flag of channe 0 + FTFIF0: u1, + /// Half transfer finish flag of channel 0 + HTFIF0: u1, + /// Error flag of channel 0 + ERRIF0: u1, + /// Global interrupt flag of channel 1 + GIF1: u1, + /// Full Transfer finish flag of channe 1 + FTFIF1: u1, + /// Half transfer finish flag of channel 1 + HTFIF1: u1, + /// Error flag of channel 1 + ERRIF1: u1, + /// Global interrupt flag of channel 2 + GIF2: u1, + /// Full Transfer finish flag of channe 2 + FTFIF2: u1, + /// Half transfer finish flag of channel 2 + HTFIF2: u1, + /// Error flag of channel 2 + ERRIF2: u1, + /// Global interrupt flag of channel 3 + GIF3: u1, + /// Full Transfer finish flag of channe 3 + FTFIF3: u1, + /// Half transfer finish flag of channel 3 + HTFIF3: u1, + /// Error flag of channel 3 + ERRIF3: u1, + /// Global interrupt flag of channel 4 + GIF4: u1, + /// Full Transfer finish flag of channe 4 + FTFIF4: u1, + /// Half transfer finish flag of channel 4 + HTFIF4: u1, + /// Error flag of channel 4 + ERRIF4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x40020004 + /// Interrupt flag clear register + pub const INTC = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear global interrupt flag of channel 0 + GIFC0: u1, + /// Clear bit for full transfer finish flag of channel 0 + FTFIFC0: u1, + /// Clear bit for half transfer finish flag of channel 0 + HTFIFC0: u1, + /// Clear bit for error flag of channel 0 + ERRIFC0: u1, + /// Clear global interrupt flag of channel 1 + GIFC1: u1, + /// Clear bit for full transfer finish flag of channel 1 + FTFIFC1: u1, + /// Clear bit for half transfer finish flag of channel 1 + HTFIFC1: u1, + /// Clear bit for error flag of channel 1 + ERRIFC1: u1, + /// Clear global interrupt flag of channel 2 + GIFC2: u1, + /// Clear bit for full transfer finish flag of channel 2 + FTFIFC2: u1, + /// Clear bit for half transfer finish flag of channel 2 + HTFIFC2: u1, + /// Clear bit for error flag of channel 2 + ERRIFC2: u1, + /// Clear global interrupt flag of channel 3 + GIFC3: u1, + /// Clear bit for full transfer finish flag of channel 3 + FTFIFC3: u1, + /// Clear bit for half transfer finish flag of channel 3 + HTFIFC3: u1, + /// Clear bit for error flag of channel 3 + ERRIFC3: u1, + /// Clear global interrupt flag of channel 4 + GIFC4: u1, + /// Clear bit for full transfer finish flag of channel 4 + FTFIFC4: u1, + /// Clear bit for half transfer finish flag of channel 4 + HTFIFC4: u1, + /// Clear bit for error flag of channel 4 + ERRIFC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x40020008 + /// Channel 0 control register + pub const CH0CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x8); + + /// address: 0x4002000c + /// Channel 0 counter register + pub const CH0CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40020010 + /// Channel 0 peripheral base address register + pub const CH0PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x10); + + /// address: 0x40020014 + /// Channel 0 memory base address register + pub const CH0MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x14); + + /// address: 0x4002001c + /// Channel 1 control register + pub const CH1CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40020020 + /// Channel 1 counter register + pub const CH1CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40020024 + /// Channel 1 peripheral base address register + pub const CH1PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x24); + + /// address: 0x40020028 + /// Channel 1 memory base address register + pub const CH1MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x28); + + /// address: 0x40020030 + /// Channel 2 control register + pub const CH2CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x30); + + /// address: 0x40020034 + /// Channel 2 counter register + pub const CH2CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40020038 + /// Channel 2 peripheral base address register + pub const CH2PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x38); + + /// address: 0x4002003c + /// Channel 2 memory base address register + pub const CH2MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x3c); + + /// address: 0x40020044 + /// Channel 3 control register + pub const CH3CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x44); + + /// address: 0x40020048 + /// Channel 3 counter register + pub const CH3CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x48); + + /// address: 0x4002004c + /// Channel 3 peripheral base address register + pub const CH3PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x4c); + + /// address: 0x40020050 + /// Channel 3 memory base address register + pub const CH3MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x50); + + /// address: 0x40020058 + /// Channel 4 control register + pub const CH4CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x58); + + /// address: 0x4002005c + /// Channel 4 counter register + pub const CH4CNT = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer counter + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x5c); + + /// address: 0x40020060 + /// Channel 4 peripheral base address register + pub const CH4PADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral base address + PADDR: u32, + }), base_address + 0x60); + + /// address: 0x40020064 + /// Channel 4 memory base address register + pub const CH4MADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Memory base address + MADDR: u32, + }), base_address + 0x64); + }; + + /// External memory controller + pub const EXMC = struct { + pub const base_address = 0xa0000000; + + /// address: 0xa0000000 + /// SRAM/NOR flash control register 0 + pub const SNCTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// NOR bank enable + NRBKEN: u1, + /// NOR bank memory address/data multiplexing + NRMUX: u1, + /// NOR bank memory type + NRTP: u2, + /// NOR bank memory data bus width + NRW: u2, + /// NOR Flash access enable + NREN: u1, + reserved0: u1, + reserved1: u1, + /// NWAIT signal polarity + NRWTPOL: u1, + reserved2: u1, + reserved3: u1, + /// Write enable + WREN: u1, + /// NWAIT signal enable + NRWTEN: u1, + reserved4: u1, + /// Asynchronous wait + ASYNCWAIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0xa0000004 + /// SRAM/NOR flash timing configuration register 0 + pub const SNTCFG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address setup time + ASET: u4, + /// Address hold time + AHLD: u4, + /// Data setup time + DSET: u8, + /// Bus latency + BUSLAT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0xa0000008 + /// SRAM/NOR flash control register 1 + pub const SNCTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// NOR bank enable + NRBKEN: u1, + /// NOR bank memory address/data multiplexing + NRMUX: u1, + /// NOR bank memory type + NRTP: u2, + /// NOR bank memory data bus width + NRW: u2, + /// NOR Flash access enable + NREN: u1, + reserved0: u1, + reserved1: u1, + /// NWAIT signal polarity + NRWTPOL: u1, + reserved2: u1, + reserved3: u1, + /// Write enable + WREN: u1, + /// NWAIT signal enable + NRWTEN: u1, + reserved4: u1, + /// Asynchronous wait + ASYNCWAIT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + }; + + /// External interrupt/event + /// controller + pub const EXTI = struct { + pub const base_address = 0x40010400; + + /// address: 0x40010400 + /// Interrupt enable register + /// (EXTI_INTEN) + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Interrupt on line 0 + INTEN0: u1, + /// Enable Interrupt on line 1 + INTEN1: u1, + /// Enable Interrupt on line 2 + INTEN2: u1, + /// Enable Interrupt on line 3 + INTEN3: u1, + /// Enable Interrupt on line 4 + INTEN4: u1, + /// Enable Interrupt on line 5 + INTEN5: u1, + /// Enable Interrupt on line 6 + INTEN6: u1, + /// Enable Interrupt on line 7 + INTEN7: u1, + /// Enable Interrupt on line 8 + INTEN8: u1, + /// Enable Interrupt on line 9 + INTEN9: u1, + /// Enable Interrupt on line 10 + INTEN10: u1, + /// Enable Interrupt on line 11 + INTEN11: u1, + /// Enable Interrupt on line 12 + INTEN12: u1, + /// Enable Interrupt on line 13 + INTEN13: u1, + /// Enable Interrupt on line 14 + INTEN14: u1, + /// Enable Interrupt on line 15 + INTEN15: u1, + /// Enable Interrupt on line 16 + INTEN16: u1, + /// Enable Interrupt on line 17 + INTEN17: u1, + /// Enable Interrupt on line 18 + INTEN18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x0); + + /// address: 0x40010404 + /// Event enable register (EXTI_EVEN) + pub const EVEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Event on line 0 + EVEN0: u1, + /// Enable Event on line 1 + EVEN1: u1, + /// Enable Event on line 2 + EVEN2: u1, + /// Enable Event on line 3 + EVEN3: u1, + /// Enable Event on line 4 + EVEN4: u1, + /// Enable Event on line 5 + EVEN5: u1, + /// Enable Event on line 6 + EVEN6: u1, + /// Enable Event on line 7 + EVEN7: u1, + /// Enable Event on line 8 + EVEN8: u1, + /// Enable Event on line 9 + EVEN9: u1, + /// Enable Event on line 10 + EVEN10: u1, + /// Enable Event on line 11 + EVEN11: u1, + /// Enable Event on line 12 + EVEN12: u1, + /// Enable Event on line 13 + EVEN13: u1, + /// Enable Event on line 14 + EVEN14: u1, + /// Enable Event on line 15 + EVEN15: u1, + /// Enable Event on line 16 + EVEN16: u1, + /// Enable Event on line 17 + EVEN17: u1, + /// Enable Event on line 18 + EVEN18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40010408 + /// Rising Edge Trigger Enable register + /// (EXTI_RTEN) + pub const RTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Rising edge trigger enable of + /// line 0 + RTEN0: u1, + /// Rising edge trigger enable of + /// line 1 + RTEN1: u1, + /// Rising edge trigger enable of + /// line 2 + RTEN2: u1, + /// Rising edge trigger enable of + /// line 3 + RTEN3: u1, + /// Rising edge trigger enable of + /// line 4 + RTEN4: u1, + /// Rising edge trigger enable of + /// line 5 + RTEN5: u1, + /// Rising edge trigger enable of + /// line 6 + RTEN6: u1, + /// Rising edge trigger enable of + /// line 7 + RTEN7: u1, + /// Rising edge trigger enable of + /// line 8 + RTEN8: u1, + /// Rising edge trigger enable of + /// line 9 + RTEN9: u1, + /// Rising edge trigger enable of + /// line 10 + RTEN10: u1, + /// Rising edge trigger enable of + /// line 11 + RTEN11: u1, + /// Rising edge trigger enable of + /// line 12 + RTEN12: u1, + /// Rising edge trigger enable of + /// line 13 + RTEN13: u1, + /// Rising edge trigger enable of + /// line 14 + RTEN14: u1, + /// Rising edge trigger enable of + /// line 15 + RTEN15: u1, + /// Rising edge trigger enable of + /// line 16 + RTEN16: u1, + /// Rising edge trigger enable of + /// line 17 + RTEN17: u1, + /// Rising edge trigger enable of + /// line 18 + RTEN18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x8); + + /// address: 0x4001040c + /// Falling Egde Trigger Enable register + /// (EXTI_FTEN) + pub const FTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Falling edge trigger enable of + /// line 0 + FTEN0: u1, + /// Falling edge trigger enable of + /// line 1 + FTEN1: u1, + /// Falling edge trigger enable of + /// line 2 + FTEN2: u1, + /// Falling edge trigger enable of + /// line 3 + FTEN3: u1, + /// Falling edge trigger enable of + /// line 4 + FTEN4: u1, + /// Falling edge trigger enable of + /// line 5 + FTEN5: u1, + /// Falling edge trigger enable of + /// line 6 + FTEN6: u1, + /// Falling edge trigger enable of + /// line 7 + FTEN7: u1, + /// Falling edge trigger enable of + /// line 8 + FTEN8: u1, + /// Falling edge trigger enable of + /// line 9 + FTEN9: u1, + /// Falling edge trigger enable of + /// line 10 + FTEN10: u1, + /// Falling edge trigger enable of + /// line 11 + FTEN11: u1, + /// Falling edge trigger enable of + /// line 12 + FTEN12: u1, + /// Falling edge trigger enable of + /// line 13 + FTEN13: u1, + /// Falling edge trigger enable of + /// line 14 + FTEN14: u1, + /// Falling edge trigger enable of + /// line 15 + FTEN15: u1, + /// Falling edge trigger enable of + /// line 16 + FTEN16: u1, + /// Falling edge trigger enable of + /// line 17 + FTEN17: u1, + /// Falling edge trigger enable of + /// line 18 + FTEN18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xc); + + /// address: 0x40010410 + /// Software interrupt event register + /// (EXTI_SWIEV) + pub const SWIEV = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt/Event software trigger on line + /// 0 + SWIEV0: u1, + /// Interrupt/Event software trigger on line + /// 1 + SWIEV1: u1, + /// Interrupt/Event software trigger on line + /// 2 + SWIEV2: u1, + /// Interrupt/Event software trigger on line + /// 3 + SWIEV3: u1, + /// Interrupt/Event software trigger on line + /// 4 + SWIEV4: u1, + /// Interrupt/Event software trigger on line + /// 5 + SWIEV5: u1, + /// Interrupt/Event software trigger on line + /// 6 + SWIEV6: u1, + /// Interrupt/Event software trigger on line + /// 7 + SWIEV7: u1, + /// Interrupt/Event software trigger on line + /// 8 + SWIEV8: u1, + /// Interrupt/Event software trigger on line + /// 9 + SWIEV9: u1, + /// Interrupt/Event software trigger on line + /// 10 + SWIEV10: u1, + /// Interrupt/Event software trigger on line + /// 11 + SWIEV11: u1, + /// Interrupt/Event software trigger on line + /// 12 + SWIEV12: u1, + /// Interrupt/Event software trigger on line + /// 13 + SWIEV13: u1, + /// Interrupt/Event software trigger on line + /// 14 + SWIEV14: u1, + /// Interrupt/Event software trigger on line + /// 15 + SWIEV15: u1, + /// Interrupt/Event software trigger on line + /// 16 + SWIEV16: u1, + /// Interrupt/Event software trigger on line + /// 17 + SWIEV17: u1, + /// Interrupt/Event software trigger on line + /// 18 + SWIEV18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x10); + + /// address: 0x40010414 + /// Pending register (EXTI_PD) + pub const PD = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt pending status of line 0 + PD0: u1, + /// Interrupt pending status of line 1 + PD1: u1, + /// Interrupt pending status of line 2 + PD2: u1, + /// Interrupt pending status of line 3 + PD3: u1, + /// Interrupt pending status of line 4 + PD4: u1, + /// Interrupt pending status of line 5 + PD5: u1, + /// Interrupt pending status of line 6 + PD6: u1, + /// Interrupt pending status of line 7 + PD7: u1, + /// Interrupt pending status of line 8 + PD8: u1, + /// Interrupt pending status of line 9 + PD9: u1, + /// Interrupt pending status of line 10 + PD10: u1, + /// Interrupt pending status of line 11 + PD11: u1, + /// Interrupt pending status of line 12 + PD12: u1, + /// Interrupt pending status of line 13 + PD13: u1, + /// Interrupt pending status of line 14 + PD14: u1, + /// Interrupt pending status of line 15 + PD15: u1, + /// Interrupt pending status of line 16 + PD16: u1, + /// Interrupt pending status of line 17 + PD17: u1, + /// Interrupt pending status of line 18 + PD18: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x14); + }; + + /// FMC + pub const FMC = struct { + pub const base_address = 0x40022000; + + /// address: 0x40022000 + /// wait state counter register + pub const WS = @intToPtr(*volatile Mmio(32, packed struct { + /// wait state counter register + WSCNT: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40022004 + /// Unlock key register 0 + pub const KEY0 = @intToPtr(*volatile Mmio(32, packed struct { + /// FMC_CTL0 unlock key + KEY: u32, + }), base_address + 0x4); + + /// address: 0x40022008 + /// Option byte unlock key register + pub const OBKEY = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002200c + /// Status register 0 + pub const STAT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// The flash is busy bit + BUSY: u1, + reserved0: u1, + /// Program error flag bit + PGERR: u1, + reserved1: u1, + /// Erase/Program protection error flag bit + WPERR: u1, + /// End of operation flag bit + ENDF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xc); + + /// address: 0x40022010 + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Main flash program for bank0 command bit + PG: u1, + /// Main flash page erase for bank0 command bit + PER: u1, + /// Main flash mass erase for bank0 command bit + MER: u1, + reserved0: u1, + /// Option bytes program command bit + OBPG: u1, + /// Option bytes erase command bit + OBER: u1, + /// Send erase command to FMC bit + START: u1, + /// FMC_CTL0 lock bit + LK: u1, + reserved1: u1, + /// Option byte erase/program enable bit + OBWEN: u1, + /// Error interrupt enable bit + ERRIE: u1, + reserved2: u1, + /// End of operation interrupt enable bit + ENDIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0x40022014 + /// Address register 0 + pub const ADDR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Flash erase/program command address bits + ADDR: u32, + }), base_address + 0x14); + + /// address: 0x4002201c + /// Option byte status register + pub const OBSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Option bytes read error bit + OBERR: u1, + /// Option bytes security protection code + SPC: u1, + /// Store USER of option bytes block after system reset + USER: u8, + /// Store DATA[15:0] of option bytes block after system reset + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x40022020 + /// Erase/Program Protection register + pub const WP = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40022100 + /// Product ID register + pub const PID = @intToPtr(*volatile u32, base_address + 0x100); + }; + + /// free watchdog timer + pub const FWDGT = struct { + pub const base_address = 0x40003000; + + /// address: 0x40003000 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Key value + CMD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// Prescaler register + pub const PSC = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); + + /// address: 0x40003008 + /// Reload register + pub const RLD = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8); + + /// address: 0x4000300c + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Free watchdog timer prescaler value update + PUD: u1, + /// Free watchdog timer counter reload value update + RUD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + }; + + /// General-purpose I/Os + pub const GPIOA = struct { + pub const base_address = 0x40010800; + + /// address: 0x40010800 + /// port control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 0) + MD0: u2, + /// Port x configuration bits (x = + /// 0) + CTL0: u2, + /// Port x mode bits (x = + /// 1) + MD1: u2, + /// Port x configuration bits (x = + /// 1) + CTL1: u2, + /// Port x mode bits (x = + /// 2 ) + MD2: u2, + /// Port x configuration bits (x = + /// 2) + CTL2: u2, + /// Port x mode bits (x = + /// 3 ) + MD3: u2, + /// Port x configuration bits (x = + /// 3) + CTL3: u2, + /// Port x mode bits (x = + /// 4) + MD4: u2, + /// Port x configuration bits (x = + /// 4) + CTL4: u2, + /// Port x mode bits (x = + /// 5) + MD5: u2, + /// Port x configuration bits (x = + /// 5) + CTL5: u2, + /// Port x mode bits (x = + /// 6) + MD6: u2, + /// Port x configuration bits (x = + /// 6) + CTL6: u2, + /// Port x mode bits (x = + /// 7) + MD7: u2, + /// Port x configuration bits (x = + /// 7) + CTL7: u2, + }), base_address + 0x0); + + /// address: 0x40010804 + /// port control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 8) + MD8: u2, + /// Port x configuration bits (x = + /// 8) + CTL8: u2, + /// Port x mode bits (x = + /// 9) + MD9: u2, + /// Port x configuration bits (x = + /// 9) + CTL9: u2, + /// Port x mode bits (x = + /// 10 ) + MD10: u2, + /// Port x configuration bits (x = + /// 10) + CTL10: u2, + /// Port x mode bits (x = + /// 11 ) + MD11: u2, + /// Port x configuration bits (x = + /// 11) + CTL11: u2, + /// Port x mode bits (x = + /// 12) + MD12: u2, + /// Port x configuration bits (x = + /// 12) + CTL12: u2, + /// Port x mode bits (x = + /// 13) + MD13: u2, + /// Port x configuration bits (x = + /// 13) + CTL13: u2, + /// Port x mode bits (x = + /// 14) + MD14: u2, + /// Port x configuration bits (x = + /// 14) + CTL14: u2, + /// Port x mode bits (x = + /// 15) + MD15: u2, + /// Port x configuration bits (x = + /// 15) + CTL15: u2, + }), base_address + 0x4); + + /// address: 0x40010808 + /// Port input status register + pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001080c + /// Port output control register + pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010810 + /// Port bit operate register + pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), base_address + 0x10); + + /// address: 0x40010814 + /// Port bit clear register + pub const BC = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010818 + /// GPIO port configuration lock + /// register + pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOB = struct { + pub const base_address = 0x40010c00; + + /// address: 0x40010c00 + /// port control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 0) + MD0: u2, + /// Port x configuration bits (x = + /// 0) + CTL0: u2, + /// Port x mode bits (x = + /// 1) + MD1: u2, + /// Port x configuration bits (x = + /// 1) + CTL1: u2, + /// Port x mode bits (x = + /// 2 ) + MD2: u2, + /// Port x configuration bits (x = + /// 2) + CTL2: u2, + /// Port x mode bits (x = + /// 3 ) + MD3: u2, + /// Port x configuration bits (x = + /// 3) + CTL3: u2, + /// Port x mode bits (x = + /// 4) + MD4: u2, + /// Port x configuration bits (x = + /// 4) + CTL4: u2, + /// Port x mode bits (x = + /// 5) + MD5: u2, + /// Port x configuration bits (x = + /// 5) + CTL5: u2, + /// Port x mode bits (x = + /// 6) + MD6: u2, + /// Port x configuration bits (x = + /// 6) + CTL6: u2, + /// Port x mode bits (x = + /// 7) + MD7: u2, + /// Port x configuration bits (x = + /// 7) + CTL7: u2, + }), base_address + 0x0); + + /// address: 0x40010c04 + /// port control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 8) + MD8: u2, + /// Port x configuration bits (x = + /// 8) + CTL8: u2, + /// Port x mode bits (x = + /// 9) + MD9: u2, + /// Port x configuration bits (x = + /// 9) + CTL9: u2, + /// Port x mode bits (x = + /// 10 ) + MD10: u2, + /// Port x configuration bits (x = + /// 10) + CTL10: u2, + /// Port x mode bits (x = + /// 11 ) + MD11: u2, + /// Port x configuration bits (x = + /// 11) + CTL11: u2, + /// Port x mode bits (x = + /// 12) + MD12: u2, + /// Port x configuration bits (x = + /// 12) + CTL12: u2, + /// Port x mode bits (x = + /// 13) + MD13: u2, + /// Port x configuration bits (x = + /// 13) + CTL13: u2, + /// Port x mode bits (x = + /// 14) + MD14: u2, + /// Port x configuration bits (x = + /// 14) + CTL14: u2, + /// Port x mode bits (x = + /// 15) + MD15: u2, + /// Port x configuration bits (x = + /// 15) + CTL15: u2, + }), base_address + 0x4); + + /// address: 0x40010c08 + /// Port input status register + pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40010c0c + /// Port output control register + pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40010c10 + /// Port bit operate register + pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), base_address + 0x10); + + /// address: 0x40010c14 + /// Port bit clear register + pub const BC = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40010c18 + /// GPIO port configuration lock + /// register + pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOC = struct { + pub const base_address = 0x40011000; + + /// address: 0x40011000 + /// port control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 0) + MD0: u2, + /// Port x configuration bits (x = + /// 0) + CTL0: u2, + /// Port x mode bits (x = + /// 1) + MD1: u2, + /// Port x configuration bits (x = + /// 1) + CTL1: u2, + /// Port x mode bits (x = + /// 2 ) + MD2: u2, + /// Port x configuration bits (x = + /// 2) + CTL2: u2, + /// Port x mode bits (x = + /// 3 ) + MD3: u2, + /// Port x configuration bits (x = + /// 3) + CTL3: u2, + /// Port x mode bits (x = + /// 4) + MD4: u2, + /// Port x configuration bits (x = + /// 4) + CTL4: u2, + /// Port x mode bits (x = + /// 5) + MD5: u2, + /// Port x configuration bits (x = + /// 5) + CTL5: u2, + /// Port x mode bits (x = + /// 6) + MD6: u2, + /// Port x configuration bits (x = + /// 6) + CTL6: u2, + /// Port x mode bits (x = + /// 7) + MD7: u2, + /// Port x configuration bits (x = + /// 7) + CTL7: u2, + }), base_address + 0x0); + + /// address: 0x40011004 + /// port control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 8) + MD8: u2, + /// Port x configuration bits (x = + /// 8) + CTL8: u2, + /// Port x mode bits (x = + /// 9) + MD9: u2, + /// Port x configuration bits (x = + /// 9) + CTL9: u2, + /// Port x mode bits (x = + /// 10 ) + MD10: u2, + /// Port x configuration bits (x = + /// 10) + CTL10: u2, + /// Port x mode bits (x = + /// 11 ) + MD11: u2, + /// Port x configuration bits (x = + /// 11) + CTL11: u2, + /// Port x mode bits (x = + /// 12) + MD12: u2, + /// Port x configuration bits (x = + /// 12) + CTL12: u2, + /// Port x mode bits (x = + /// 13) + MD13: u2, + /// Port x configuration bits (x = + /// 13) + CTL13: u2, + /// Port x mode bits (x = + /// 14) + MD14: u2, + /// Port x configuration bits (x = + /// 14) + CTL14: u2, + /// Port x mode bits (x = + /// 15) + MD15: u2, + /// Port x configuration bits (x = + /// 15) + CTL15: u2, + }), base_address + 0x4); + + /// address: 0x40011008 + /// Port input status register + pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001100c + /// Port output control register + pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011010 + /// Port bit operate register + pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), base_address + 0x10); + + /// address: 0x40011014 + /// Port bit clear register + pub const BC = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011018 + /// GPIO port configuration lock + /// register + pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOD = struct { + pub const base_address = 0x40011400; + + /// address: 0x40011400 + /// port control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 0) + MD0: u2, + /// Port x configuration bits (x = + /// 0) + CTL0: u2, + /// Port x mode bits (x = + /// 1) + MD1: u2, + /// Port x configuration bits (x = + /// 1) + CTL1: u2, + /// Port x mode bits (x = + /// 2 ) + MD2: u2, + /// Port x configuration bits (x = + /// 2) + CTL2: u2, + /// Port x mode bits (x = + /// 3 ) + MD3: u2, + /// Port x configuration bits (x = + /// 3) + CTL3: u2, + /// Port x mode bits (x = + /// 4) + MD4: u2, + /// Port x configuration bits (x = + /// 4) + CTL4: u2, + /// Port x mode bits (x = + /// 5) + MD5: u2, + /// Port x configuration bits (x = + /// 5) + CTL5: u2, + /// Port x mode bits (x = + /// 6) + MD6: u2, + /// Port x configuration bits (x = + /// 6) + CTL6: u2, + /// Port x mode bits (x = + /// 7) + MD7: u2, + /// Port x configuration bits (x = + /// 7) + CTL7: u2, + }), base_address + 0x0); + + /// address: 0x40011404 + /// port control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 8) + MD8: u2, + /// Port x configuration bits (x = + /// 8) + CTL8: u2, + /// Port x mode bits (x = + /// 9) + MD9: u2, + /// Port x configuration bits (x = + /// 9) + CTL9: u2, + /// Port x mode bits (x = + /// 10 ) + MD10: u2, + /// Port x configuration bits (x = + /// 10) + CTL10: u2, + /// Port x mode bits (x = + /// 11 ) + MD11: u2, + /// Port x configuration bits (x = + /// 11) + CTL11: u2, + /// Port x mode bits (x = + /// 12) + MD12: u2, + /// Port x configuration bits (x = + /// 12) + CTL12: u2, + /// Port x mode bits (x = + /// 13) + MD13: u2, + /// Port x configuration bits (x = + /// 13) + CTL13: u2, + /// Port x mode bits (x = + /// 14) + MD14: u2, + /// Port x configuration bits (x = + /// 14) + CTL14: u2, + /// Port x mode bits (x = + /// 15) + MD15: u2, + /// Port x configuration bits (x = + /// 15) + CTL15: u2, + }), base_address + 0x4); + + /// address: 0x40011408 + /// Port input status register + pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001140c + /// Port output control register + pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011410 + /// Port bit operate register + pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), base_address + 0x10); + + /// address: 0x40011414 + /// Port bit clear register + pub const BC = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011418 + /// GPIO port configuration lock + /// register + pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + pub const GPIOE = struct { + pub const base_address = 0x40011800; + + /// address: 0x40011800 + /// port control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 0) + MD0: u2, + /// Port x configuration bits (x = + /// 0) + CTL0: u2, + /// Port x mode bits (x = + /// 1) + MD1: u2, + /// Port x configuration bits (x = + /// 1) + CTL1: u2, + /// Port x mode bits (x = + /// 2 ) + MD2: u2, + /// Port x configuration bits (x = + /// 2) + CTL2: u2, + /// Port x mode bits (x = + /// 3 ) + MD3: u2, + /// Port x configuration bits (x = + /// 3) + CTL3: u2, + /// Port x mode bits (x = + /// 4) + MD4: u2, + /// Port x configuration bits (x = + /// 4) + CTL4: u2, + /// Port x mode bits (x = + /// 5) + MD5: u2, + /// Port x configuration bits (x = + /// 5) + CTL5: u2, + /// Port x mode bits (x = + /// 6) + MD6: u2, + /// Port x configuration bits (x = + /// 6) + CTL6: u2, + /// Port x mode bits (x = + /// 7) + MD7: u2, + /// Port x configuration bits (x = + /// 7) + CTL7: u2, + }), base_address + 0x0); + + /// address: 0x40011804 + /// port control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Port x mode bits (x = + /// 8) + MD8: u2, + /// Port x configuration bits (x = + /// 8) + CTL8: u2, + /// Port x mode bits (x = + /// 9) + MD9: u2, + /// Port x configuration bits (x = + /// 9) + CTL9: u2, + /// Port x mode bits (x = + /// 10 ) + MD10: u2, + /// Port x configuration bits (x = + /// 10) + CTL10: u2, + /// Port x mode bits (x = + /// 11 ) + MD11: u2, + /// Port x configuration bits (x = + /// 11) + CTL11: u2, + /// Port x mode bits (x = + /// 12) + MD12: u2, + /// Port x configuration bits (x = + /// 12) + CTL12: u2, + /// Port x mode bits (x = + /// 13) + MD13: u2, + /// Port x configuration bits (x = + /// 13) + CTL13: u2, + /// Port x mode bits (x = + /// 14) + MD14: u2, + /// Port x configuration bits (x = + /// 14) + CTL14: u2, + /// Port x mode bits (x = + /// 15) + MD15: u2, + /// Port x configuration bits (x = + /// 15) + CTL15: u2, + }), base_address + 0x4); + + /// address: 0x40011808 + /// Port input status register + pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001180c + /// Port output control register + pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40011810 + /// Port bit operate register + pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), base_address + 0x10); + + /// address: 0x40011814 + /// Port bit clear register + pub const BC = @intToPtr(*volatile Mmio(32, packed struct { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40011818 + /// GPIO port configuration lock + /// register + pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + }; + + /// Inter integrated circuit + pub const I2C0 = struct { + pub const base_address = 0x40005400; + + /// address: 0x40005400 + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C peripheral enable + I2CEN: u1, + /// SMBus/I2C mode switch + SMBEN: u1, + reserved0: u1, + /// SMBusType Selection + SMBSEL: u1, + /// ARP protocol in SMBus switch + ARPEN: u1, + /// PEC Calculation Switch + PECEN: u1, + /// Whether or not to response to a General Call (0x00) + GCEN: u1, + /// Whether to stretch SCL low when data is not ready in slave mode + SS: u1, + /// Generate a START condition on I2C bus + START: u1, + /// Generate a STOP condition on I2C bus + STOP: u1, + /// Whether or not to send an ACK + ACKEN: u1, + /// Position of ACK and PEC when receiving + POAP: u1, + /// PEC Transfer + PECTRANS: u1, + /// SMBus alert + SALT: u1, + reserved1: u1, + /// Software reset + SRESET: u1, + }), base_address + 0x0); + + /// address: 0x40005404 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C Peripheral clock frequency + I2CCLK: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// Event interrupt enable + EVIE: u1, + /// Buffer interrupt enable + BUFIE: u1, + /// DMA mode switch + DMAON: u1, + /// Flag indicating DMA last transfer + DMALST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x40005408 + /// Slave address register 0 + pub const SADDR0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Bit 0 of a 10-bit address + ADDRESS0: u1, + /// 7-bit address or bits 7:1 of a 10-bit address + ADDRESS7_1: u7, + /// Highest two bits of a 10-bit address + ADDRESS9_8: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Address mode for the I2C slave + ADDFORMAT: u1, + }), base_address + 0x8); + + /// address: 0x4000540c + /// Slave address register 1 + pub const SADDR1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Dual-Address mode switch + DUADEN: u1, + /// Second I2C address for the slave in Dual-Address mode + ADDRESS2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40005410 + /// Transfer buffer register + pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { + /// Transmission or reception data buffer register + TRB: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x10); + + /// address: 0x40005414 + /// Transfer status register 0 + pub const STAT0 = @intToPtr(*volatile Mmio(16, packed struct { + /// START condition sent out in master mode + SBSEND: u1, + /// Address is sent in master mode or received and matches in slave mode + ADDSEND: u1, + /// Byte transmission completed + BTC: u1, + /// Header of 10-bit address is sent in master mode + ADD10SEND: u1, + /// STOP condition detected in slave mode + STPDET: u1, + reserved0: u1, + /// I2C_DATA is not Empty during receiving + RBNE: u1, + /// I2C_DATA is Empty during transmitting + TBE: u1, + /// A bus error occurs indication a unexpected START or STOP condition on I2C bus + BERR: u1, + /// Arbitration Lost in master mode + LOSTARB: u1, + /// Acknowledge error + AERR: u1, + /// Over-run or under-run situation occurs in slave mode + OUERR: u1, + /// PEC error when receiving data + PECERR: u1, + reserved1: u1, + /// Timeout signal in SMBus mode + SMBTO: u1, + /// SMBus Alert status + SMBALT: u1, + }), base_address + 0x14); + + /// address: 0x40005418 + /// Transfer status register 1 + pub const STAT1 = @intToPtr(*volatile Mmio(16, packed struct { + /// A flag indicating whether I2C block is in master or slave mode + MASTER: u1, + /// Busy flag + I2CBSY: u1, + /// Whether the I2C is a transmitter or a receiver + TR: u1, + reserved0: u1, + /// General call address (00h) received + RXGC: u1, + /// Default address of SMBusDevice + DEFSMB: u1, + /// SMBus Host Header detected in slave mode + HSTSMB: u1, + /// Dual Flag in slave mode + DUMODF: u1, + /// Packet Error Checking Value that calculated by hardware when PEC is enabled + PECV: u8, + }), base_address + 0x18); + + /// address: 0x4000541c + /// Clock configure register + pub const CKCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C Clock control in master mode + CLKC: u12, + reserved0: u1, + reserved1: u1, + /// Duty cycle in fast mode + DTCY: u1, + /// I2C speed selection in master mode + FAST: u1, + }), base_address + 0x1c); + + /// address: 0x40005420 + /// Rise time register + pub const RT = @intToPtr(*volatile Mmio(16, packed struct { + /// Maximum rise time in master mode + RISETIME: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40005490 + /// Fast mode plus configure register + pub const FMPCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Fast mode plus enable + FMPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x90); + }; + pub const I2C1 = struct { + pub const base_address = 0x40005800; + + /// address: 0x40005800 + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C peripheral enable + I2CEN: u1, + /// SMBus/I2C mode switch + SMBEN: u1, + reserved0: u1, + /// SMBusType Selection + SMBSEL: u1, + /// ARP protocol in SMBus switch + ARPEN: u1, + /// PEC Calculation Switch + PECEN: u1, + /// Whether or not to response to a General Call (0x00) + GCEN: u1, + /// Whether to stretch SCL low when data is not ready in slave mode + SS: u1, + /// Generate a START condition on I2C bus + START: u1, + /// Generate a STOP condition on I2C bus + STOP: u1, + /// Whether or not to send an ACK + ACKEN: u1, + /// Position of ACK and PEC when receiving + POAP: u1, + /// PEC Transfer + PECTRANS: u1, + /// SMBus alert + SALT: u1, + reserved1: u1, + /// Software reset + SRESET: u1, + }), base_address + 0x0); + + /// address: 0x40005804 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C Peripheral clock frequency + I2CCLK: u6, + reserved0: u1, + reserved1: u1, + /// Error interrupt enable + ERRIE: u1, + /// Event interrupt enable + EVIE: u1, + /// Buffer interrupt enable + BUFIE: u1, + /// DMA mode switch + DMAON: u1, + /// Flag indicating DMA last transfer + DMALST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x40005808 + /// Slave address register 0 + pub const SADDR0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Bit 0 of a 10-bit address + ADDRESS0: u1, + /// 7-bit address or bits 7:1 of a 10-bit address + ADDRESS7_1: u7, + /// Highest two bits of a 10-bit address + ADDRESS9_8: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Address mode for the I2C slave + ADDFORMAT: u1, + }), base_address + 0x8); + + /// address: 0x4000580c + /// Slave address register 1 + pub const SADDR1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Dual-Address mode switch + DUADEN: u1, + /// Second I2C address for the slave in Dual-Address mode + ADDRESS2: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x40005810 + /// Transfer buffer register + pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { + /// Transmission or reception data buffer register + TRB: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x10); + + /// address: 0x40005814 + /// Transfer status register 0 + pub const STAT0 = @intToPtr(*volatile Mmio(16, packed struct { + /// START condition sent out in master mode + SBSEND: u1, + /// Address is sent in master mode or received and matches in slave mode + ADDSEND: u1, + /// Byte transmission completed + BTC: u1, + /// Header of 10-bit address is sent in master mode + ADD10SEND: u1, + /// STOP condition detected in slave mode + STPDET: u1, + reserved0: u1, + /// I2C_DATA is not Empty during receiving + RBNE: u1, + /// I2C_DATA is Empty during transmitting + TBE: u1, + /// A bus error occurs indication a unexpected START or STOP condition on I2C bus + BERR: u1, + /// Arbitration Lost in master mode + LOSTARB: u1, + /// Acknowledge error + AERR: u1, + /// Over-run or under-run situation occurs in slave mode + OUERR: u1, + /// PEC error when receiving data + PECERR: u1, + reserved1: u1, + /// Timeout signal in SMBus mode + SMBTO: u1, + /// SMBus Alert status + SMBALT: u1, + }), base_address + 0x14); + + /// address: 0x40005818 + /// Transfer status register 1 + pub const STAT1 = @intToPtr(*volatile Mmio(16, packed struct { + /// A flag indicating whether I2C block is in master or slave mode + MASTER: u1, + /// Busy flag + I2CBSY: u1, + /// Whether the I2C is a transmitter or a receiver + TR: u1, + reserved0: u1, + /// General call address (00h) received + RXGC: u1, + /// Default address of SMBusDevice + DEFSMB: u1, + /// SMBus Host Header detected in slave mode + HSTSMB: u1, + /// Dual Flag in slave mode + DUMODF: u1, + /// Packet Error Checking Value that calculated by hardware when PEC is enabled + PECV: u8, + }), base_address + 0x18); + + /// address: 0x4000581c + /// Clock configure register + pub const CKCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// I2C Clock control in master mode + CLKC: u12, + reserved0: u1, + reserved1: u1, + /// Duty cycle in fast mode + DTCY: u1, + /// I2C speed selection in master mode + FAST: u1, + }), base_address + 0x1c); + + /// address: 0x40005820 + /// Rise time register + pub const RT = @intToPtr(*volatile Mmio(16, packed struct { + /// Maximum rise time in master mode + RISETIME: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x20); + + /// address: 0x40005890 + /// Fast mode plus configure register + pub const FMPCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Fast mode plus enable + FMPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x90); + }; + + /// Enhanced Core Local Interrupt Controller + pub const ECLIC = struct { + pub const base_address = 0xd2000000; + + /// address: 0xd2000000 + /// cliccfg Register + pub const CLICCFG = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// NLBITS + NLBITS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0xd2000004 + /// clicinfo Register + pub const CLICINFO = @intToPtr(*volatile Mmio(32, packed struct { + /// NUM_INTERRUPT + NUM_INTERRUPT: u13, + /// VERSION + VERSION: u8, + /// CLICINTCTLBITS + CLICINTCTLBITS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0xd200000b + /// MTH Register + pub const MTH = @intToPtr(*volatile u8, base_address + 0xb); + }; + + /// Power management unit + pub const PMU = struct { + pub const base_address = 0x40007000; + + /// address: 0x40007000 + /// power control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// LDO Low Power Mode + LDOLP: u1, + /// Standby Mode + STBMOD: u1, + /// Wakeup Flag Reset + WURST: u1, + /// Standby Flag Reset + STBRST: u1, + /// Low Voltage Detector Enable + LVDEN: u1, + /// Low Voltage Detector Threshold + LVDT: u3, + /// Backup Domain Write Enable + BKPWEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40007004 + /// power control/status register + pub const CS = @intToPtr(*volatile Mmio(32, packed struct { + /// Wakeup flag + WUF: u1, + /// Standby flag + STBF: u1, + /// Low Voltage Detector Status Flag + LVDF: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Enable WKUP pin + WUPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x4); + }; + + /// Reset and clock unit + pub const RCU = struct { + pub const base_address = 0x40021000; + + /// address: 0x40021000 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Internal 8MHz RC oscillator Enable + IRC8MEN: u1, + /// IRC8M Internal 8MHz RC Oscillator stabilization Flag + IRC8MSTB: u1, + reserved0: u1, + /// Internal 8MHz RC Oscillator clock trim adjust value + IRC8MADJ: u5, + /// Internal 8MHz RC Oscillator calibration value register + IRC8MCALIB: u8, + /// External High Speed oscillator Enable + HXTALEN: u1, + /// External crystal oscillator (HXTAL) clock stabilization flag + HXTALSTB: u1, + /// External crystal oscillator (HXTAL) clock bypass mode enable + HXTALBPS: u1, + /// HXTAL Clock Monitor Enable + CKMEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// PLL enable + PLLEN: u1, + /// PLL Clock Stabilization Flag + PLLSTB: u1, + /// PLL1 enable + PLL1EN: u1, + /// PLL1 Clock Stabilization Flag + PLL1STB: u1, + /// PLL2 enable + PLL2EN: u1, + /// PLL2 Clock Stabilization Flag + PLL2STB: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x40021004 + /// Clock configuration register 0 + /// (RCU_CFG0) + pub const CFG0 = @intToPtr(*volatile Mmio(32, packed struct { + /// System clock switch + SCS: u2, + /// System clock switch status + SCSS: u2, + /// AHB prescaler selection + AHBPSC: u4, + /// APB1 prescaler selection + APB1PSC: u3, + /// APB2 prescaler selection + APB2PSC: u3, + /// ADC clock prescaler selection + ADCPSC_1_0: u2, + /// PLL Clock Source Selection + PLLSEL: u1, + /// The LSB of PREDV0 division factor + PREDV0_LSB: u1, + /// The PLL clock multiplication factor + PLLMF_3_0: u4, + /// USBFS clock prescaler selection + USBFSPSC: u2, + /// CKOUT0 Clock Source Selection + CKOUT0SEL: u4, + /// Bit 2 of ADCPSC + ADCPSC_2: u1, + /// Bit 4 of PLLMF + PLLMF_4: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0x40021008 + /// Clock interrupt register + /// (RCU_INT) + pub const INT = @intToPtr(*volatile Mmio(32, packed struct { + /// IRC40K stabilization interrupt flag + IRC40KSTBIF: u1, + /// LXTAL stabilization interrupt flag + LXTALSTBIF: u1, + /// IRC8M stabilization interrupt flag + IRC8MSTBIF: u1, + /// HXTAL stabilization interrupt flag + HXTALSTBIF: u1, + /// PLL stabilization interrupt flag + PLLSTBIF: u1, + /// PLL1 stabilization interrupt flag + PLL1STBIF: u1, + /// PLL2 stabilization interrupt flag + PLL2STBIF: u1, + /// HXTAL Clock Stuck Interrupt Flag + CKMIF: u1, + /// IRC40K Stabilization interrupt enable + IRC40KSTBIE: u1, + /// LXTAL Stabilization Interrupt Enable + LXTALSTBIE: u1, + /// IRC8M Stabilization Interrupt Enable + IRC8MSTBIE: u1, + /// HXTAL Stabilization Interrupt Enable + HXTALSTBIE: u1, + /// PLL Stabilization Interrupt Enable + PLLSTBIE: u1, + /// PLL1 Stabilization Interrupt Enable + PLL1STBIE: u1, + /// PLL2 Stabilization Interrupt Enable + PLL2STBIE: u1, + reserved0: u1, + /// IRC40K Stabilization Interrupt Clear + IRC40KSTBIC: u1, + /// LXTAL Stabilization Interrupt Clear + LXTALSTBIC: u1, + /// IRC8M Stabilization Interrupt Clear + IRC8MSTBIC: u1, + /// HXTAL Stabilization Interrupt Clear + HXTALSTBIC: u1, + /// PLL stabilization Interrupt Clear + PLLSTBIC: u1, + /// PLL1 stabilization Interrupt Clear + PLL1STBIC: u1, + /// PLL2 stabilization Interrupt Clear + PLL2STBIC: u1, + /// HXTAL Clock Stuck Interrupt Clear + CKMIC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4002100c + /// APB2 reset register + /// (RCU_APB2RST) + pub const APB2RST = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function I/O reset + AFRST: u1, + reserved0: u1, + /// GPIO port A reset + PARST: u1, + /// GPIO port B reset + PBRST: u1, + /// GPIO port C reset + PCRST: u1, + /// GPIO port D reset + PDRST: u1, + /// GPIO port E reset + PERST: u1, + reserved1: u1, + reserved2: u1, + /// ADC0 reset + ADC0RST: u1, + /// ADC1 reset + ADC1RST: u1, + /// Timer 0 reset + TIMER0RST: u1, + /// SPI0 reset + SPI0RST: u1, + reserved3: u1, + /// USART0 Reset + USART0RST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0xc); + + /// address: 0x40021010 + /// APB1 reset register + /// (RCU_APB1RST) + pub const APB1RST = @intToPtr(*volatile Mmio(32, packed struct { + /// TIMER1 timer reset + TIMER1RST: u1, + /// TIMER2 timer reset + TIMER2RST: u1, + /// TIMER3 timer reset + TIMER3RST: u1, + /// TIMER4 timer reset + TIMER4RST: u1, + /// TIMER5 timer reset + TIMER5RST: u1, + /// TIMER6 timer reset + TIMER6RST: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window watchdog timer reset + WWDGTRST: u1, + reserved5: u1, + reserved6: u1, + /// SPI1 reset + SPI1RST: u1, + /// SPI2 reset + SPI2RST: u1, + reserved7: u1, + /// USART1 reset + USART1RST: u1, + /// USART2 reset + USART2RST: u1, + /// UART3 reset + UART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// I2C0 reset + I2C0RST: u1, + /// I2C1 reset + I2C1RST: u1, + reserved8: u1, + reserved9: u1, + /// CAN0 reset + CAN0RST: u1, + /// CAN1 reset + CAN1RST: u1, + /// Backup interface reset + BKPIRST: u1, + /// Power control reset + PMURST: u1, + /// DAC reset + DACRST: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x40021014 + /// AHB enable register + pub const AHBEN = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA0 clock enable + DMA0EN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// SRAM interface clock enable when sleep mode + SRAMSPEN: u1, + reserved0: u1, + /// FMC clock enable when sleep mode + FMCSPEN: u1, + reserved1: u1, + /// CRC clock enable + CRCEN: u1, + reserved2: u1, + /// EXMC clock enable + EXMCEN: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// USBFS clock enable + USBFSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x14); + + /// address: 0x40021018 + /// APB2 clock enable register + /// (RCU_APB2EN) + pub const APB2EN = @intToPtr(*volatile Mmio(32, packed struct { + /// Alternate function IO clock enable + AFEN: u1, + reserved0: u1, + /// GPIO port A clock enable + PAEN: u1, + /// GPIO port B clock enable + PBEN: u1, + /// GPIO port C clock enable + PCEN: u1, + /// GPIO port D clock enable + PDEN: u1, + /// GPIO port E clock enable + PEEN: u1, + reserved1: u1, + reserved2: u1, + /// ADC0 clock enable + ADC0EN: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// TIMER0 clock enable + TIMER0EN: u1, + /// SPI0 clock enable + SPI0EN: u1, + reserved3: u1, + /// USART0 clock enable + USART0EN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x18); + + /// address: 0x4002101c + /// APB1 clock enable register + /// (RCU_APB1EN) + pub const APB1EN = @intToPtr(*volatile Mmio(32, packed struct { + /// TIMER1 timer clock enable + TIMER1EN: u1, + /// TIMER2 timer clock enable + TIMER2EN: u1, + /// TIMER3 timer clock enable + TIMER3EN: u1, + /// TIMER4 timer clock enable + TIMER4EN: u1, + /// TIMER5 timer clock enable + TIMER5EN: u1, + /// TIMER6 timer clock enable + TIMER6EN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Window watchdog timer clock enable + WWDGTEN: u1, + reserved5: u1, + reserved6: u1, + /// SPI1 clock enable + SPI1EN: u1, + /// SPI2 clock enable + SPI2EN: u1, + reserved7: u1, + /// USART1 clock enable + USART1EN: u1, + /// USART2 clock enable + USART2EN: u1, + /// UART3 clock enable + UART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// I2C0 clock enable + I2C0EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + reserved8: u1, + reserved9: u1, + /// CAN0 clock enable + CAN0EN: u1, + /// CAN1 clock enable + CAN1EN: u1, + /// Backup interface clock enable + BKPIEN: u1, + /// Power control clock enable + PMUEN: u1, + /// DAC clock enable + DACEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x1c); + + /// address: 0x40021020 + /// Backup domain control register + /// (RCU_BDCTL) + pub const BDCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// LXTAL enable + LXTALEN: u1, + /// External low-speed oscillator stabilization + LXTALSTB: u1, + /// LXTAL bypass mode enable + LXTALBPS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// RTC clock entry selection + RTCSRC: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// RTC clock enable + RTCEN: u1, + /// Backup domain reset + BKPRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x20); + + /// address: 0x40021024 + /// Reset source /clock register + /// (RCU_RSTSCK) + pub const RSTSCK = @intToPtr(*volatile Mmio(32, packed struct { + /// IRC40K enable + IRC40KEN: u1, + /// IRC40K stabilization + IRC40KSTB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Reset flag clear + RSTFC: u1, + reserved22: u1, + /// External PIN reset flag + EPRSTF: u1, + /// Power reset flag + PORRSTF: u1, + /// Software reset flag + SWRSTF: u1, + /// Free Watchdog timer reset flag + FWDGTRSTF: u1, + /// Window watchdog timer reset flag + WWDGTRSTF: u1, + /// Low-power reset flag + LPRSTF: u1, + }), base_address + 0x24); + + /// address: 0x40021028 + /// AHB reset register + pub const AHBRST = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// USBFS reset + USBFSRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x28); + + /// address: 0x4002102c + /// Clock Configuration register 1 + pub const CFG1 = @intToPtr(*volatile Mmio(32, packed struct { + /// PREDV0 division factor + PREDV0: u4, + /// PREDV1 division factor + PREDV1: u4, + /// The PLL1 clock multiplication factor + PLL1MF: u4, + /// The PLL2 clock multiplication factor + PLL2MF: u4, + /// PREDV0 input Clock Source Selection + PREDV0SEL: u1, + /// I2S1 Clock Source Selection + I2S1SEL: u1, + /// I2S2 Clock Source Selection + I2S2SEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + + /// address: 0x40021034 + /// Deep sleep mode Voltage register + pub const DSV = @intToPtr(*volatile Mmio(32, packed struct { + /// Deep-sleep mode voltage select + DSLPVS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x34); + }; + + /// Real-time clock + pub const RTC = struct { + pub const base_address = 0x40002800; + + /// address: 0x40002800 + /// RTC interrupt enable register + pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Second interrupt + SCIE: u1, + /// Alarm interrupt enable + ALRMIE: u1, + /// Overflow interrupt enable + OVIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40002804 + /// control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Sencond interrupt flag + SCIF: u1, + /// Alarm interrupt flag + ALRMIF: u1, + /// Overflow interrupt flag + OVIF: u1, + /// Registers synchronized flag + RSYNF: u1, + /// Configuration mode flag + CMF: u1, + /// Last write operation finished flag + LWOFF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// RTC prescaler high register + pub const PSCH = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC prescaler value high + PSC: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// RTC prescaler low + /// register + pub const PSCL = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC prescaler value low + PSC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// RTC divider high register + pub const DIVH = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC divider value high + DIV: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// RTC divider low register + pub const DIVL = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC divider value low + DIV: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// RTC counter high register + pub const CNTH = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC counter value high + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4000281c + /// RTC counter low register + pub const CNTL = @intToPtr(*volatile Mmio(32, packed struct { + /// RTC counter value low + CNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + + /// address: 0x40002820 + /// Alarm high register + pub const ALRMH = @intToPtr(*volatile Mmio(32, packed struct { + /// Alarm value high + ALRM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x20); + + /// address: 0x40002824 + /// RTC alarm low register + pub const ALRML = @intToPtr(*volatile Mmio(32, packed struct { + /// alarm value low + ALRM: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + }; + + /// Serial peripheral interface + pub const SPI0 = struct { + pub const base_address = 0x40013000; + + /// address: 0x40013000 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Clock Phase Selection + CKPH: u1, + /// Clock polarity Selection + CKPL: u1, + /// Master Mode Enable + MSTMOD: u1, + /// Master Clock Prescaler Selection + PSC: u3, + /// SPI enable + SPIEN: u1, + /// LSB First Mode + LF: u1, + /// NSS Pin Selection In NSS Software Mode + SWNSS: u1, + /// NSS Software Mode Selection + SWNSSEN: u1, + /// Receive only + RO: u1, + /// Data frame format + FF16: u1, + /// CRC Next Transfer + CRCNT: u1, + /// CRC Calculation Enable + CRCEN: u1, + /// Bidirectional Transmit output enable + BDOEN: u1, + /// Bidirectional + /// enable + BDEN: u1, + }), base_address + 0x0); + + /// address: 0x40013004 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Rx buffer DMA enable + DMAREN: u1, + /// Transmit Buffer DMA Enable + DMATEN: u1, + /// Drive NSS Output + NSSDRV: u1, + /// SPI NSS pulse mode enable + NSSP: u1, + /// SPI TI mode enable + TMOD: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RBNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TBEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40013008 + /// status register + pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Buffer Not Empty + RBNE: u1, + /// Transmit Buffer Empty + TBE: u1, + /// I2S channel side + I2SCH: u1, + /// Transmission underrun error bit + TXURERR: u1, + /// SPI CRC Error Bit + CRCERR: u1, + /// SPI Configuration error + CONFERR: u1, + /// Reception Overrun Error Bit + RXORERR: u1, + /// Transmitting On-going Bit + TRANS: u1, + /// Format error + FERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4001300c + /// data register + pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { + /// Data transfer register + SPI_DATA: u16, + }), base_address + 0xc); + + /// address: 0x40013010 + /// CRC polynomial register + pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); + + /// address: 0x40013014 + /// RX CRC register + pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); + + /// address: 0x40013018 + /// TX CRC register + pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); + + /// address: 0x4001301c + /// I2S control register + pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length + DTLEN: u2, + /// Idle state clock polarity + CKPL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization mode + PCMSMOD: u1, + /// I2S operation mode + I2SOPMOD: u2, + /// I2S Enable + I2SEN: u1, + /// I2S mode selection + I2SSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1c); + + /// address: 0x40013020 + /// I2S prescaler register + pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { + /// Dividing factor for the prescaler + DIV: u8, + /// Odd factor for the + /// prescaler + OF: u1, + /// I2S_MCK output enable + MCKOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x20); + }; + pub const SPI1 = struct { + pub const base_address = 0x40003800; + + /// address: 0x40003800 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Clock Phase Selection + CKPH: u1, + /// Clock polarity Selection + CKPL: u1, + /// Master Mode Enable + MSTMOD: u1, + /// Master Clock Prescaler Selection + PSC: u3, + /// SPI enable + SPIEN: u1, + /// LSB First Mode + LF: u1, + /// NSS Pin Selection In NSS Software Mode + SWNSS: u1, + /// NSS Software Mode Selection + SWNSSEN: u1, + /// Receive only + RO: u1, + /// Data frame format + FF16: u1, + /// CRC Next Transfer + CRCNT: u1, + /// CRC Calculation Enable + CRCEN: u1, + /// Bidirectional Transmit output enable + BDOEN: u1, + /// Bidirectional + /// enable + BDEN: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Rx buffer DMA enable + DMAREN: u1, + /// Transmit Buffer DMA Enable + DMATEN: u1, + /// Drive NSS Output + NSSDRV: u1, + /// SPI NSS pulse mode enable + NSSP: u1, + /// SPI TI mode enable + TMOD: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RBNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TBEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40003808 + /// status register + pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Buffer Not Empty + RBNE: u1, + /// Transmit Buffer Empty + TBE: u1, + /// I2S channel side + I2SCH: u1, + /// Transmission underrun error bit + TXURERR: u1, + /// SPI CRC Error Bit + CRCERR: u1, + /// SPI Configuration error + CONFERR: u1, + /// Reception Overrun Error Bit + RXORERR: u1, + /// Transmitting On-going Bit + TRANS: u1, + /// Format error + FERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000380c + /// data register + pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { + /// Data transfer register + SPI_DATA: u16, + }), base_address + 0xc); + + /// address: 0x40003810 + /// CRC polynomial register + pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); + + /// address: 0x40003814 + /// RX CRC register + pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); + + /// address: 0x40003818 + /// TX CRC register + pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); + + /// address: 0x4000381c + /// I2S control register + pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length + DTLEN: u2, + /// Idle state clock polarity + CKPL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization mode + PCMSMOD: u1, + /// I2S operation mode + I2SOPMOD: u2, + /// I2S Enable + I2SEN: u1, + /// I2S mode selection + I2SSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1c); + + /// address: 0x40003820 + /// I2S prescaler register + pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { + /// Dividing factor for the prescaler + DIV: u8, + /// Odd factor for the + /// prescaler + OF: u1, + /// I2S_MCK output enable + MCKOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x20); + }; + pub const SPI2 = struct { + pub const base_address = 0x40003c00; + + /// address: 0x40003c00 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Clock Phase Selection + CKPH: u1, + /// Clock polarity Selection + CKPL: u1, + /// Master Mode Enable + MSTMOD: u1, + /// Master Clock Prescaler Selection + PSC: u3, + /// SPI enable + SPIEN: u1, + /// LSB First Mode + LF: u1, + /// NSS Pin Selection In NSS Software Mode + SWNSS: u1, + /// NSS Software Mode Selection + SWNSSEN: u1, + /// Receive only + RO: u1, + /// Data frame format + FF16: u1, + /// CRC Next Transfer + CRCNT: u1, + /// CRC Calculation Enable + CRCEN: u1, + /// Bidirectional Transmit output enable + BDOEN: u1, + /// Bidirectional + /// enable + BDEN: u1, + }), base_address + 0x0); + + /// address: 0x40003c04 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Rx buffer DMA enable + DMAREN: u1, + /// Transmit Buffer DMA Enable + DMATEN: u1, + /// Drive NSS Output + NSSDRV: u1, + /// SPI NSS pulse mode enable + NSSP: u1, + /// SPI TI mode enable + TMOD: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt + /// enable + RBNEIE: u1, + /// Tx buffer empty interrupt + /// enable + TBEIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40003c08 + /// status register + pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Buffer Not Empty + RBNE: u1, + /// Transmit Buffer Empty + TBE: u1, + /// I2S channel side + I2SCH: u1, + /// Transmission underrun error bit + TXURERR: u1, + /// SPI CRC Error Bit + CRCERR: u1, + /// SPI Configuration error + CONFERR: u1, + /// Reception Overrun Error Bit + RXORERR: u1, + /// Transmitting On-going Bit + TRANS: u1, + /// Format error + FERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40003c0c + /// data register + pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { + /// Data transfer register + SPI_DATA: u16, + }), base_address + 0xc); + + /// address: 0x40003c10 + /// CRC polynomial register + pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); + + /// address: 0x40003c14 + /// RX CRC register + pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); + + /// address: 0x40003c18 + /// TX CRC register + pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); + + /// address: 0x40003c1c + /// I2S control register + pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel length (number of bits per audio + /// channel) + CHLEN: u1, + /// Data length + DTLEN: u2, + /// Idle state clock polarity + CKPL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved0: u1, + /// PCM frame synchronization mode + PCMSMOD: u1, + /// I2S operation mode + I2SOPMOD: u2, + /// I2S Enable + I2SEN: u1, + /// I2S mode selection + I2SSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1c); + + /// address: 0x40003c20 + /// I2S prescaler register + pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { + /// Dividing factor for the prescaler + DIV: u8, + /// Odd factor for the + /// prescaler + OF: u1, + /// I2S_MCK output enable + MCKOEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x20); + }; + + /// Advanced-timers + pub const TIMER0 = struct { + pub const base_address = 0x40012c00; + + /// address: 0x40012c00 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode + /// selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40012c04 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + /// Commutation control shadow enable + CCSE: u1, + reserved0: u1, + /// Commutation control shadow register update control + CCUC: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + /// Idle state of channel 0 output + ISO0: u1, + /// Idle state of channel 0 complementary output + ISO0N: u1, + /// Idle state of channel 1 output + ISO1: u1, + /// Idle state of channel 1 complementary output + ISO1N: u1, + /// Idle state of channel 2 output + ISO2: u1, + /// Idle state of channel 2 complementary output + ISO2N: u1, + /// Idle state of channel 3 output + ISO3: u1, + padding0: u1, + }), base_address + 0x4); + + /// address: 0x40012c08 + /// slave mode configuration register + pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Slave mode selection + SMC: u3, + reserved0: u1, + /// Trigger selection + TRGS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), base_address + 0x8); + + /// address: 0x40012c0c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + /// commutation interrupt enable + CMTIE: u1, + /// Trigger interrupt enable + TRGIE: u1, + /// Break interrupt enable + BRKIE: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + /// Commutation DMA request enable + CMTDEN: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x40012c10 + /// Interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt flag + CH2IF: u1, + /// Channel 3 capture/compare interrupt flag + CH3IF: u1, + /// Channel commutation interrupt flag + CMTIF: u1, + /// Trigger interrupt flag + TRGIF: u1, + /// Break interrupt flag + BRKIF: u1, + reserved0: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0x40012c14 + /// Software event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update event generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + /// Channel commutation event generation + CMTG: u1, + /// Trigger event generation + TRGG: u1, + /// Break event generation + BRKG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x14); + + /// address: 0x40012c18 + /// Channel control register 0 (output + /// mode) + pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), base_address + 0x18); + + /// address: 0x40012c18 + /// Channel control register 0 (input + /// mode) + pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 mode selection + CH0MS: u2, + /// Channel 0 input capture prescaler + CH0CAPPSC: u2, + /// Channel 0 input capture filter control + CH0CAPFLT: u4, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 input capture prescaler + CH1CAPPSC: u2, + /// Channel 1 input capture filter control + CH1CAPFLT: u4, + }), base_address + 0x18); + + /// address: 0x40012c1c + /// Channel control register 1 (output + /// mode) + pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), base_address + 0x1c); + + /// address: 0x40012c1c + /// Channel control register 1 (input + /// mode) + pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 mode selection + CH2MS: u2, + /// Channel 2 input capture prescaler + CH2CAPPSC: u2, + /// Channel 2 input capture filter control + CH2CAPFLT: u4, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 input capture prescaler + CH3CAPPSC: u2, + /// Channel 3 input capture filter control + CH3CAPFLT: u4, + }), base_address + 0x1c); + + /// address: 0x40012c20 + /// Channel control register 2 + pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + /// Channel 0 complementary output enable + CH0NEN: u1, + /// Channel 0 complementary output polarity + CH0NP: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + /// Channel 1 complementary output enable + CH1NEN: u1, + /// Channel 1 complementary output polarity + CH1NP: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + /// Channel 2 complementary output enable + CH2NEN: u1, + /// Channel 2 complementary output polarity + CH2NP: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40012c24 + /// counter + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40012c28 + /// prescaler + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x40012c2c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + + /// address: 0x40012c30 + /// Counter repetition register + pub const CREP = @intToPtr(*volatile MmioInt(16, u8), base_address + 0x30); + + /// address: 0x40012c34 + /// Channel 0 capture/compare value register + pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel0 + CH0VAL: u16, + }), base_address + 0x34); + + /// address: 0x40012c38 + /// Channel 1 capture/compare value register + pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), base_address + 0x38); + + /// address: 0x40012c3c + /// Channel 2 capture/compare value register + pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), base_address + 0x3c); + + /// address: 0x40012c40 + /// Channel 3 capture/compare value register + pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), base_address + 0x40); + + /// address: 0x40012c44 + /// channel complementary protection register + pub const CCHP = @intToPtr(*volatile Mmio(16, packed struct { + /// Dead time configure + DTCFG: u8, + /// Complementary register protect control + PROT: u2, + /// Idle mode off-state configure + IOS: u1, + /// Run mode off-state configure + ROS: u1, + /// Break enable + BRKEN: u1, + /// Break polarity + BRKP: u1, + /// Output automatic enable + OAEN: u1, + /// Primary output enable + POEN: u1, + }), base_address + 0x44); + + /// address: 0x40012c48 + /// DMA configuration register + pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA transfer access start address + DMATA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA transfer count + DMATC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x48); + + /// address: 0x40012c4c + /// DMA transfer buffer register + pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); + }; + + /// General-purpose-timers + pub const TIMER1 = struct { + pub const base_address = 0x40000000; + + /// address: 0x40000000 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// slave mode control register + pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Slave mode control + SMC: u3, + reserved0: u1, + /// Trigger selection + TRGS: u3, + /// Master-slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), base_address + 0x8); + + /// address: 0x4000000c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TRGIE: u1, + reserved1: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + reserved2: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x40000010 + /// interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt enable + CH2IF: u1, + /// Channel 3 capture/compare interrupt enable + CH3IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TRGIF: u1, + reserved1: u1, + reserved2: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + reserved0: u1, + /// Trigger event generation + TRGG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// Channel control register 0 (output + /// mode) + pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), base_address + 0x18); + + /// address: 0x40000018 + /// Channel control register 0 (input + /// mode) + pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 mode selection + CH0MS: u2, + /// Channel 0 input capture prescaler + CH0CAPPSC: u2, + /// Channel 0 input capture filter control + CH0CAPFLT: u4, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 input capture prescaler + CH1CAPPSC: u2, + /// Channel 1 input capture filter control + CH1CAPFLT: u4, + }), base_address + 0x18); + + /// address: 0x4000001c + /// Channel control register 1 (output mode) + pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), base_address + 0x1c); + + /// address: 0x4000001c + /// Channel control register 1 (input + /// mode) + pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 mode selection + CH2MS: u2, + /// Channel 2 input capture prescaler + CH2CAPPSC: u2, + /// Channel 2 input capture filter control + CH2CAPFLT: u4, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 input capture prescaler + CH3CAPPSC: u2, + /// Channel 3 input capture filter control + CH3CAPFLT: u4, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// Channel control register 2 + pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + reserved0: u1, + reserved1: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + reserved2: u1, + reserved3: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + reserved4: u1, + reserved5: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40000024 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40000028 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x4000002c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + + /// address: 0x40000034 + /// Channel 0 capture/compare value register + pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 0 + CH0VAL: u16, + }), base_address + 0x34); + + /// address: 0x40000038 + /// Channel 1 capture/compare value register + pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), base_address + 0x38); + + /// address: 0x4000003c + /// Channel 2 capture/compare value register + pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// Channel 3 capture/compare value register + pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), base_address + 0x40); + + /// address: 0x40000048 + /// DMA configuration register + pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA transfer access start address + DMATA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA transfer count + DMATC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x48); + + /// address: 0x4000004c + /// DMA transfer buffer register + pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); + }; + pub const TIMER2 = struct { + pub const base_address = 0x40000400; + + /// address: 0x40000400 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40000404 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40000408 + /// slave mode control register + pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Slave mode control + SMC: u3, + reserved0: u1, + /// Trigger selection + TRGS: u3, + /// Master-slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), base_address + 0x8); + + /// address: 0x4000040c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TRGIE: u1, + reserved1: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + reserved2: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x40000410 + /// interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt enable + CH2IF: u1, + /// Channel 3 capture/compare interrupt enable + CH3IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TRGIF: u1, + reserved1: u1, + reserved2: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0x40000414 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + reserved0: u1, + /// Trigger event generation + TRGG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + + /// address: 0x40000418 + /// Channel control register 0 (output + /// mode) + pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), base_address + 0x18); + + /// address: 0x40000418 + /// Channel control register 0 (input + /// mode) + pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 mode selection + CH0MS: u2, + /// Channel 0 input capture prescaler + CH0CAPPSC: u2, + /// Channel 0 input capture filter control + CH0CAPFLT: u4, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 input capture prescaler + CH1CAPPSC: u2, + /// Channel 1 input capture filter control + CH1CAPFLT: u4, + }), base_address + 0x18); + + /// address: 0x4000041c + /// Channel control register 1 (output mode) + pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), base_address + 0x1c); + + /// address: 0x4000041c + /// Channel control register 1 (input + /// mode) + pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 mode selection + CH2MS: u2, + /// Channel 2 input capture prescaler + CH2CAPPSC: u2, + /// Channel 2 input capture filter control + CH2CAPFLT: u4, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 input capture prescaler + CH3CAPPSC: u2, + /// Channel 3 input capture filter control + CH3CAPFLT: u4, + }), base_address + 0x1c); + + /// address: 0x40000420 + /// Channel control register 2 + pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + reserved0: u1, + reserved1: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + reserved2: u1, + reserved3: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + reserved4: u1, + reserved5: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40000424 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40000428 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x4000042c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + + /// address: 0x40000434 + /// Channel 0 capture/compare value register + pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 0 + CH0VAL: u16, + }), base_address + 0x34); + + /// address: 0x40000438 + /// Channel 1 capture/compare value register + pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), base_address + 0x38); + + /// address: 0x4000043c + /// Channel 2 capture/compare value register + pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), base_address + 0x3c); + + /// address: 0x40000440 + /// Channel 3 capture/compare value register + pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), base_address + 0x40); + + /// address: 0x40000448 + /// DMA configuration register + pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA transfer access start address + DMATA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA transfer count + DMATC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x48); + + /// address: 0x4000044c + /// DMA transfer buffer register + pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); + }; + pub const TIMER3 = struct { + pub const base_address = 0x40000800; + + /// address: 0x40000800 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40000804 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40000808 + /// slave mode control register + pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Slave mode control + SMC: u3, + reserved0: u1, + /// Trigger selection + TRGS: u3, + /// Master-slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), base_address + 0x8); + + /// address: 0x4000080c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TRGIE: u1, + reserved1: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + reserved2: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x40000810 + /// interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt enable + CH2IF: u1, + /// Channel 3 capture/compare interrupt enable + CH3IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TRGIF: u1, + reserved1: u1, + reserved2: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + reserved0: u1, + /// Trigger event generation + TRGG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// Channel control register 0 (output + /// mode) + pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), base_address + 0x18); + + /// address: 0x40000818 + /// Channel control register 0 (input + /// mode) + pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 mode selection + CH0MS: u2, + /// Channel 0 input capture prescaler + CH0CAPPSC: u2, + /// Channel 0 input capture filter control + CH0CAPFLT: u4, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 input capture prescaler + CH1CAPPSC: u2, + /// Channel 1 input capture filter control + CH1CAPFLT: u4, + }), base_address + 0x18); + + /// address: 0x4000081c + /// Channel control register 1 (output mode) + pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), base_address + 0x1c); + + /// address: 0x4000081c + /// Channel control register 1 (input + /// mode) + pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 mode selection + CH2MS: u2, + /// Channel 2 input capture prescaler + CH2CAPPSC: u2, + /// Channel 2 input capture filter control + CH2CAPFLT: u4, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 input capture prescaler + CH3CAPPSC: u2, + /// Channel 3 input capture filter control + CH3CAPFLT: u4, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// Channel control register 2 + pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + reserved0: u1, + reserved1: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + reserved2: u1, + reserved3: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + reserved4: u1, + reserved5: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40000824 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40000828 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x4000082c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + + /// address: 0x40000834 + /// Channel 0 capture/compare value register + pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 0 + CH0VAL: u16, + }), base_address + 0x34); + + /// address: 0x40000838 + /// Channel 1 capture/compare value register + pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), base_address + 0x38); + + /// address: 0x4000083c + /// Channel 2 capture/compare value register + pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), base_address + 0x3c); + + /// address: 0x40000840 + /// Channel 3 capture/compare value register + pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), base_address + 0x40); + + /// address: 0x40000848 + /// DMA configuration register + pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA transfer access start address + DMATA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA transfer count + DMATC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x48); + + /// address: 0x4000084c + /// DMA transfer buffer register + pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); + }; + pub const TIMER4 = struct { + pub const base_address = 0x40000c00; + + /// address: 0x40000c00 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40000c04 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x4); + + /// address: 0x40000c08 + /// slave mode control register + pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { + /// Slave mode control + SMC: u3, + reserved0: u1, + /// Trigger selection + TRGS: u3, + /// Master-slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), base_address + 0x8); + + /// address: 0x40000c0c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + reserved0: u1, + /// Trigger interrupt enable + TRGIE: u1, + reserved1: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + reserved2: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x40000c10 + /// interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt enable + CH2IF: u1, + /// Channel 3 capture/compare interrupt enable + CH3IF: u1, + reserved0: u1, + /// Trigger interrupt flag + TRGIF: u1, + reserved1: u1, + reserved2: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0x40000c14 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + reserved0: u1, + /// Trigger event generation + TRGG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x14); + + /// address: 0x40000c18 + /// Channel control register 0 (output + /// mode) + pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), base_address + 0x18); + + /// address: 0x40000c18 + /// Channel control register 0 (input + /// mode) + pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 mode selection + CH0MS: u2, + /// Channel 0 input capture prescaler + CH0CAPPSC: u2, + /// Channel 0 input capture filter control + CH0CAPFLT: u4, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 input capture prescaler + CH1CAPPSC: u2, + /// Channel 1 input capture filter control + CH1CAPFLT: u4, + }), base_address + 0x18); + + /// address: 0x40000c1c + /// Channel control register 1 (output mode) + pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), base_address + 0x1c); + + /// address: 0x40000c1c + /// Channel control register 1 (input + /// mode) + pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 2 mode selection + CH2MS: u2, + /// Channel 2 input capture prescaler + CH2CAPPSC: u2, + /// Channel 2 input capture filter control + CH2CAPFLT: u4, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 input capture prescaler + CH3CAPPSC: u2, + /// Channel 3 input capture filter control + CH3CAPFLT: u4, + }), base_address + 0x1c); + + /// address: 0x40000c20 + /// Channel control register 2 + pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + reserved0: u1, + reserved1: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + reserved2: u1, + reserved3: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + reserved4: u1, + reserved5: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x40000c24 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40000c28 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x40000c2c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + + /// address: 0x40000c34 + /// Channel 0 capture/compare value register + pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 0 + CH0VAL: u16, + }), base_address + 0x34); + + /// address: 0x40000c38 + /// Channel 1 capture/compare value register + pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), base_address + 0x38); + + /// address: 0x40000c3c + /// Channel 2 capture/compare value register + pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), base_address + 0x3c); + + /// address: 0x40000c40 + /// Channel 3 capture/compare value register + pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), base_address + 0x40); + + /// address: 0x40000c48 + /// DMA configuration register + pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA transfer access start address + DMATA: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// DMA transfer count + DMATC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x48); + + /// address: 0x40000c4c + /// DMA transfer buffer register + pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); + }; + + /// Basic-timers + pub const TIMER5 = struct { + pub const base_address = 0x40001000; + + /// address: 0x40001000 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload shadow enable + ARSE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode control + MMC: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x4); + + /// address: 0x4000100c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UPDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// Interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x14); + + /// address: 0x40001024 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40001028 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x4000102c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + }; + pub const TIMER6 = struct { + pub const base_address = 0x40001400; + + /// address: 0x40001400 + /// control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Auto-reload shadow enable + ARSE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Master mode control + MMC: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x4); + + /// address: 0x4000140c + /// DMA/Interrupt enable register + pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt enable + UPIE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Update DMA request enable + UPDEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// Interrupt flag register + pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { + /// Update interrupt flag + UPIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// event generation register + pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { + /// Update generation + UPG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x14); + + /// address: 0x40001424 + /// Counter register + pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); + + /// address: 0x40001428 + /// Prescaler register + pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); + + /// address: 0x4000142c + /// Counter auto reload register + pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { + /// Counter auto reload value + CARL: u16, + }), base_address + 0x2c); + }; + + /// Universal synchronous asynchronous receiver + /// transmitter + pub const USART0 = struct { + pub const base_address = 0x40013800; + + /// address: 0x40013800 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS change flag + CTSF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40013804 + /// Data register + pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40013808 + /// Baud rate register + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4001380c + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40013810 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART + ADDR: u4, + reserved0: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// CK Length + CLEN: u1, + /// Clock phase + CPH: u1, + /// Clock polarity + CPL: u1, + /// CK pin enable + CKEN: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40013814 + /// Control register 2 + pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + /// Smartcard NACK enable + NKEN: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + /// RTS enable + RTSEN: u1, + /// CTS enable + CTSEN: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40013818 + /// Guard time and prescaler + /// register + pub const GP = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value in Smartcard mode + GUAT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART1 = struct { + pub const base_address = 0x40004400; + + /// address: 0x40004400 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS change flag + CTSF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004404 + /// Data register + pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004408 + /// Baud rate register + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000440c + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004410 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART + ADDR: u4, + reserved0: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// CK Length + CLEN: u1, + /// Clock phase + CPH: u1, + /// Clock polarity + CPL: u1, + /// CK pin enable + CKEN: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004414 + /// Control register 2 + pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + /// Smartcard NACK enable + NKEN: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + /// RTS enable + RTSEN: u1, + /// CTS enable + CTSEN: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004418 + /// Guard time and prescaler + /// register + pub const GP = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value in Smartcard mode + GUAT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + pub const USART2 = struct { + pub const base_address = 0x40004800; + + /// address: 0x40004800 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS change flag + CTSF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x0); + + /// address: 0x40004804 + /// Data register + pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004808 + /// Baud rate register + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000480c + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004810 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART + ADDR: u4, + reserved0: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + /// CK Length + CLEN: u1, + /// Clock phase + CPH: u1, + /// Clock polarity + CPL: u1, + /// CK pin enable + CKEN: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004814 + /// Control register 2 + pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + /// Smartcard NACK enable + NKEN: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + /// RTS enable + RTSEN: u1, + /// CTS enable + CTSEN: u1, + /// CTS interrupt enable + CTSIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x40004818 + /// Guard time and prescaler + /// register + pub const GP = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + /// Guard time value in Smartcard mode + GUAT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + }; + + /// Universal asynchronous receiver + /// transmitter + pub const UART3 = struct { + pub const base_address = 0x40004c00; + + /// address: 0x40004c00 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40004c04 + /// Data register + pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40004c08 + /// Baud rate register + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x40004c0c + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40004c10 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART + ADDR: u4, + reserved0: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40004c14 + /// Control register 2 + pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + reserved0: u1, + reserved1: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40004c18 + /// Guard time and prescaler + /// register + pub const GP = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + }; + pub const UART4 = struct { + pub const base_address = 0x40005000; + + /// address: 0x40005000 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x0); + + /// address: 0x40005004 + /// Data register + pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); + + /// address: 0x40005008 + /// Baud rate register + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000500c + /// Control register 0 + pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0xc); + + /// address: 0x40005010 + /// Control register 1 + pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address of the USART + ADDR: u4, + reserved0: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt + /// enable + LBDIE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x10); + + /// address: 0x40005014 + /// Control register 2 + pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + reserved0: u1, + reserved1: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x14); + + /// address: 0x40005018 + /// Guard time and prescaler + /// register + pub const GP = @intToPtr(*volatile Mmio(32, packed struct { + /// Prescaler value + PSC: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + }; + + /// USB full speed global registers + pub const USBFS_GLOBAL = struct { + pub const base_address = 0x50000000; + + /// address: 0x50000000 + /// Global OTG control and status register + /// (USBFS_GOTGCS) + pub const GOTGCS = @intToPtr(*volatile Mmio(32, packed struct { + /// SRP success + SRPS: u1, + /// SRP request + SRPREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Host success + HNPS: u1, + /// HNP request + HNPREQ: u1, + /// Host HNP enable + HHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// ID pin status + IDPS: u1, + /// Debounce interval + DI: u1, + /// A-session valid + ASV: u1, + /// B-session valid + BSV: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x50000004 + /// Global OTG interrupt flag register + /// (USBFS_GOTGINTF) + pub const GOTGINTF = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + /// Session end + SESEND: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Session request success status + /// change + SRPEND: u1, + /// HNP end + HNPEND: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Host negotiation request detected + HNPDET: u1, + /// A-device timeout + ADTO: u1, + /// Debounce finish + DF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x4); + + /// address: 0x50000008 + /// Global AHB control and status register + /// (USBFS_GAHBCS) + pub const GAHBCS = @intToPtr(*volatile Mmio(32, packed struct { + /// Global interrupt enable + GINTEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tx FIFO threshold + TXFTH: u1, + /// Periodic Tx FIFO threshold + PTXFTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x8); + + /// address: 0x5000000c + /// Global USB control and status register + /// (USBFS_GUSBCSR) + pub const GUSBCS = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout calibration + TOC: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// SRP capability enable + SRPCEN: u1, + /// HNP capability enable + HNPCEN: u1, + /// USB turnaround time + UTT: u4, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Force host mode + FHM: u1, + /// Force device mode + FDM: u1, + padding0: u1, + }), base_address + 0xc); + + /// address: 0x50000010 + /// Global reset control register (USBFS_GRSTCTL) + pub const GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HCSRST: u1, + /// Host frame counter reset + HFCRST: u1, + reserved0: u1, + /// RxFIFO flush + RXFF: u1, + /// TxFIFO flush + TXFF: u1, + /// TxFIFO number + TXFNUM: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10); + + /// address: 0x50000014 + /// Global interrupt flag register (USBFS_GINTF) + pub const GINTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Current operation mode + COPM: u1, + /// Mode fault interrupt flag + MFIF: u1, + /// OTG interrupt flag + OTGIF: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty interrupt flag + RXFNEIF: u1, + /// Non-periodic TxFIFO empty interrupt flag + NPTXFEIF: u1, + /// Global Non-Periodic IN NAK effective + GNPINAK: u1, + /// Global OUT NAK effective + GONAK: u1, + reserved0: u1, + reserved1: u1, + /// Early suspend + ESP: u1, + /// USB suspend + SP: u1, + /// USB reset + RST: u1, + /// Enumeration finished + ENUMF: u1, + /// Isochronous OUT packet dropped + /// interrupt + ISOOPDIF: u1, + /// End of periodic frame + /// interrupt flag + EOPFIF: u1, + reserved2: u1, + reserved3: u1, + /// IN endpoint interrupt flag + IEPIF: u1, + /// OUT endpoint interrupt flag + OEPIF: u1, + /// Isochronous IN transfer Not Complete Interrupt Flag + ISOINCIF: u1, + /// periodic transfer not complete interrupt flag(Host + /// mode)/isochronous OUT transfer not complete interrupt flag(Device + /// mode) + PXNCIF_ISOONCIF: u1, + reserved4: u1, + reserved5: u1, + /// Host port interrupt flag + HPIF: u1, + /// Host channels interrupt flag + HCIF: u1, + /// Periodic TxFIFO empty interrupt flag + PTXFEIF: u1, + reserved6: u1, + /// ID pin status change + IDPSC: u1, + /// Disconnect interrupt flag + DISCIF: u1, + /// Session interrupt flag + SESIF: u1, + /// Wakeup interrupt flag + WKUPIF: u1, + }), base_address + 0x14); + + /// address: 0x50000018 + /// Global interrupt enable register + /// (USBFS_GINTEN) + pub const GINTEN = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Mode fault interrupt + /// enable + MFIE: u1, + /// OTG interrupt enable + OTGIE: u1, + /// Start of frame interrupt enable + SOFIE: u1, + /// Receive FIFO non-empty + /// interrupt enable + RXFNEIE: u1, + /// Non-periodic TxFIFO empty + /// interrupt enable + NPTXFEIE: u1, + /// Global non-periodic IN NAK effective interrupt enable + GNPINAKIE: u1, + /// Global OUT NAK effective + /// interrupt enable + GONAKIE: u1, + reserved1: u1, + reserved2: u1, + /// Early suspend interrupt enable + ESPIE: u1, + /// USB suspend interrupt enable + SPIE: u1, + /// USB reset interrupt enable + RSTIE: u1, + /// Enumeration finish interrupt enable + ENUMFIE: u1, + /// Isochronous OUT packet dropped interrupt enable + ISOOPDIE: u1, + /// End of periodic frame interrupt enable + EOPFIE: u1, + reserved3: u1, + reserved4: u1, + /// IN endpoints interrupt enable + IEPIE: u1, + /// OUT endpoints interrupt enable + OEPIE: u1, + /// isochronous IN transfer not complete + /// interrupt enable + ISOINCIE: u1, + /// periodic transfer not compelete Interrupt enable(Host + /// mode)/isochronous OUT transfer not complete interrupt enable(Device + /// mode) + PXNCIE_ISOONCIE: u1, + reserved5: u1, + reserved6: u1, + /// Host port interrupt enable + HPIE: u1, + /// Host channels interrupt enable + HCIE: u1, + /// Periodic TxFIFO empty interrupt enable + PTXFEIE: u1, + reserved7: u1, + /// ID pin status change interrupt enable + IDPSCIE: u1, + /// Disconnect interrupt enable + DISCIE: u1, + /// Session interrupt enable + SESIE: u1, + /// Wakeup interrupt enable + WKUPIE: u1, + }), base_address + 0x18); + + /// address: 0x5000001c + /// Global Receive status read(Device + /// mode) + pub const GRSTATR_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Recieve packet status + RPCKST: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x1c); + + /// address: 0x5000001c + /// Global Receive status read(Host + /// mode) + pub const GRSTATR_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Reivece packet status + RPCKST: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x1c); + + /// address: 0x50000020 + /// Global Receive status pop(Device + /// mode) + pub const GRSTATP_Device = @intToPtr(*volatile Mmio(32, packed struct { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Recieve packet status + RPCKST: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x50000020 + /// Global Receive status pop(Host + /// mode) + pub const GRSTATP_Host = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel number + CNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Reivece packet status + RPCKST: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x20); + + /// address: 0x50000024 + /// Global Receive FIFO size register + /// (USBFS_GRFLEN) + pub const GRFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO depth + RXFD: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x50000028 + /// Host non-periodic transmit FIFO length register + /// (Host mode) + pub const HNPTFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// host non-periodic transmit Tx RAM start + /// address + HNPTXRSAR: u16, + /// host non-periodic TxFIFO depth + HNPTXFD: u16, + }), base_address + 0x28); + + /// address: 0x50000028 + /// Device IN endpoint 0 transmit FIFO length + /// (Device mode) + pub const DIEP0TFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// in endpoint 0 Tx RAM start address + IEP0TXRSAR: u16, + /// in endpoint 0 Tx FIFO depth + IEP0TXFD: u16, + }), base_address + 0x28); + + /// address: 0x5000002c + /// Host non-periodic transmit FIFO/queue + /// status register (HNPTFQSTAT) + pub const HNPTFQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-periodic TxFIFO space + NPTXFS: u16, + /// Non-periodic transmit request queue + /// space + NPTXRQS: u8, + /// Top of the non-periodic transmit request + /// queue + NPTXRQTOP: u7, + padding0: u1, + }), base_address + 0x2c); + + /// address: 0x50000038 + /// Global core configuration register (USBFS_GCCFG) + pub const GCCFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Power on + PWRON: u1, + reserved16: u1, + /// The VBUS A-device Comparer enable + VBUSACEN: u1, + /// The VBUS B-device Comparer enable + VBUSBCEN: u1, + /// SOF output enable + SOFOEN: u1, + /// VBUS ignored + VBUSIG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x38); + + /// address: 0x5000003c + /// core ID register + pub const CID = @intToPtr(*volatile u32, base_address + 0x3c); + + /// address: 0x50000100 + /// Host periodic transmit FIFO length register (HPTFLEN) + pub const HPTFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Host periodic TxFIFO start + /// address + HPTXFSAR: u16, + /// Host periodic TxFIFO depth + HPTXFD: u16, + }), base_address + 0x100); + + /// address: 0x50000104 + /// device IN endpoint transmit FIFO size + /// register (DIEP1TFLEN) + pub const DIEP1TFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO transmit RAM start + /// address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), base_address + 0x104); + + /// address: 0x50000108 + /// device IN endpoint transmit FIFO size + /// register (DIEP2TFLEN) + pub const DIEP2TFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO transmit RAM start + /// address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), base_address + 0x108); + + /// address: 0x5000010c + /// device IN endpoint transmit FIFO size + /// register (FS_DIEP3TXFLEN) + pub const DIEP3TFLEN = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint FIFO4 transmit RAM start + /// address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), base_address + 0x10c); + }; + + /// USB on the go full speed host + pub const USBFS_HOST = struct { + pub const base_address = 0x50000400; + + /// address: 0x50000400 + /// host configuration register + /// (HCTL) + pub const HCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// clock select for USB clock + CLKSEL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + + /// address: 0x50000404 + /// Host frame interval + /// register + pub const HFT = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame interval + FRI: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x50000408 + /// FS host frame number/frame time + /// remaining register (HFINFR) + pub const HFINFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Frame number + FRNUM: u16, + /// Frame remaining time + FRT: u16, + }), base_address + 0x8); + + /// address: 0x50000410 + /// Host periodic transmit FIFO/queue + /// status register (HPTFQSTAT) + pub const HPTFQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic transmit data FIFO space + /// available + PTXFS: u16, + /// Periodic transmit request queue space + /// available + PTXREQS: u8, + /// Top of the periodic transmit request + /// queue + PTXREQT: u8, + }), base_address + 0x10); + + /// address: 0x50000414 + /// Host all channels interrupt + /// register + pub const HACHINT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x14); + + /// address: 0x50000418 + /// host all channels interrupt mask + /// register + pub const HACHINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel interrupt enable + CINTEN: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x18); + + /// address: 0x50000440 + /// Host port control and status register (USBFS_HPCS) + pub const HPCS = @intToPtr(*volatile Mmio(32, packed struct { + /// Port connect status + PCST: u1, + /// Port connect detected + PCD: u1, + /// Port enable + PE: u1, + /// Port enable/disable change + PEDC: u1, + reserved0: u1, + reserved1: u1, + /// Port resume + PREM: u1, + /// Port suspend + PSP: u1, + /// Port reset + PRST: u1, + reserved2: u1, + /// Port line status + PLST: u2, + /// Port power + PP: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Port speed + PS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x40); + + /// address: 0x50000500 + /// host channel-0 characteristics + /// register (HCH0CTL) + pub const HCH0CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x100); + + /// address: 0x50000520 + /// host channel-1 characteristics + /// register (HCH1CTL) + pub const HCH1CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x120); + + /// address: 0x50000540 + /// host channel-2 characteristics + /// register (HCH2CTL) + pub const HCH2CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x140); + + /// address: 0x50000560 + /// host channel-3 characteristics + /// register (HCH3CTL) + pub const HCH3CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x160); + + /// address: 0x50000580 + /// host channel-4 characteristics + /// register (HCH4CTL) + pub const HCH4CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x180); + + /// address: 0x500005a0 + /// host channel-5 characteristics + /// register (HCH5CTL) + pub const HCH5CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x1a0); + + /// address: 0x500005c0 + /// host channel-6 characteristics + /// register (HCH6CTL) + pub const HCH6CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x1c0); + + /// address: 0x500005e0 + /// host channel-7 characteristics + /// register (HCH7CTL) + pub const HCH7CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved0: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved1: u1, + reserved2: u1, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), base_address + 0x1e0); + + /// address: 0x50000508 + /// host channel-0 interrupt register + /// (USBFS_HCHxINTF) + pub const HCH0INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x108); + + /// address: 0x50000528 + /// host channel-1 interrupt register + /// (HCH1INTF) + pub const HCH1INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x128); + + /// address: 0x50000548 + /// host channel-2 interrupt register + /// (HCH2INTF) + pub const HCH2INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x148); + + /// address: 0x50000568 + /// host channel-3 interrupt register + /// (HCH3INTF) + pub const HCH3INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x168); + + /// address: 0x50000588 + /// host channel-4 interrupt register + /// (HCH4INTF) + pub const HCH4INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x188); + + /// address: 0x500005a8 + /// host channel-5 interrupt register + /// (HCH5INTF) + pub const HCH5INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1a8); + + /// address: 0x500005c8 + /// host channel-6 interrupt register + /// (HCH6INTF) + pub const HCH6INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c8); + + /// address: 0x500005e8 + /// host channel-7 interrupt register + /// (HCH7INTF) + pub const HCH7INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved0: u1, + /// STALL response received + /// interrupt + STALL: u1, + /// NAK response received + /// interrupt + NAK: u1, + /// ACK response received/transmitted + /// interrupt + ACK: u1, + reserved1: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1e8); + + /// address: 0x5000050c + /// host channel-0 interrupt enable register + /// (HCH0INTEN) + pub const HCH0INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x10c); + + /// address: 0x5000052c + /// host channel-1 interrupt enable register + /// (HCH1INTEN) + pub const HCH1INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x12c); + + /// address: 0x5000054c + /// host channel-2 interrupt enable register + /// (HCH2INTEN) + pub const HCH2INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14c); + + /// address: 0x5000056c + /// host channel-3 interrupt enable register + /// (HCH3INTEN) + pub const HCH3INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x16c); + + /// address: 0x5000058c + /// host channel-4 interrupt enable register + /// (HCH4INTEN) + pub const HCH4INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18c); + + /// address: 0x500005ac + /// host channel-5 interrupt enable register + /// (HCH5INTEN) + pub const HCH5INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ac); + + /// address: 0x500005cc + /// host channel-6 interrupt enable register + /// (HCH6INTEN) + pub const HCH6INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1cc); + + /// address: 0x500005ec + /// host channel-7 interrupt enable register + /// (HCH7INTEN) + pub const HCH7INTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved0: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved1: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1ec); + + /// address: 0x50000510 + /// host channel-0 transfer length + /// register + pub const HCH0LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x110); + + /// address: 0x50000530 + /// host channel-1 transfer length + /// register + pub const HCH1LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000550 + /// host channel-2 transfer length + /// register + pub const HCH2LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000570 + /// host channel-3 transfer length + /// register + pub const HCH3LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000590 + /// host channel-4 transfer length + /// register + pub const HCH4LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x190); + + /// address: 0x500005b0 + /// host channel-5 transfer length + /// register + pub const HCH5LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1b0); + + /// address: 0x500005d0 + /// host channel-6 transfer length + /// register + pub const HCH6LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1d0); + + /// address: 0x500005f0 + /// host channel-7 transfer length + /// register + pub const HCH7LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding0: u1, + }), base_address + 0x1f0); + }; + + /// USB on the go full speed device + pub const USBFS_DEVICE = struct { + pub const base_address = 0x50000800; + + /// address: 0x50000800 + /// device configuration register + /// (DCFG) + pub const DCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Device speed + DS: u2, + /// Non-zero-length status OUT + /// handshake + NZLSOH: u1, + reserved0: u1, + /// Device address + DAR: u7, + /// end of periodic frame time + EOPFT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x0); + + /// address: 0x50000804 + /// device control register + /// (DCTL) + pub const DCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Remote wakeup + RWKUP: u1, + /// Soft disconnect + SD: u1, + /// Global IN NAK status + GINS: u1, + /// Global OUT NAK status + GONS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on initialization flag + POIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x4); + + /// address: 0x50000808 + /// device status register + /// (DSTAT) + pub const DSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Suspend status + SPST: u1, + /// Enumerated speed + ES: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Frame number of the received + /// SOF + FNRSOF: u14, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x8); + + /// address: 0x50000810 + /// device IN endpoint common interrupt + /// mask register (DIEPINTEN) + pub const DIEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished interrupt + /// enable + TFEN: u1, + /// Endpoint disabled interrupt + /// enable + EPDISEN: u1, + reserved0: u1, + /// Control IN timeout condition interrupt enable (Non-isochronous + /// endpoints) + CITOEN: u1, + /// Endpoint Tx FIFO underrun interrupt enable bit + EPTXFUDEN: u1, + reserved1: u1, + /// IN endpoint NAK effective + /// interrupt enable + IEPNEEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x10); + + /// address: 0x50000814 + /// device OUT endpoint common interrupt + /// enable register (DOEPINTEN) + pub const DOEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished interrupt + /// enable + TFEN: u1, + /// Endpoint disabled interrupt + /// enable + EPDISEN: u1, + reserved0: u1, + /// SETUP phase finished interrupt enable + STPFEN: u1, + /// Endpoint Rx FIFO overrun interrupt enable + EPRXFOVREN: u1, + reserved1: u1, + /// Back-to-back SETUP packets + /// interrupt enable + BTBSTPEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x14); + + /// address: 0x50000818 + /// device all endpoints interrupt + /// register (DAEPINT) + pub const DAEPINT = @intToPtr(*volatile Mmio(32, packed struct { + /// Device all IN endpoint interrupt bits + IEPITB: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Device all OUT endpoint interrupt bits + OEPITB: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x18); + + /// address: 0x5000081c + /// Device all endpoints interrupt enable register + /// (DAEPINTEN) + pub const DAEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP interrupt interrupt enable bits + IEPIE: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// OUT endpoint interrupt enable bits + OEPIE: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x1c); + + /// address: 0x50000828 + /// device VBUS discharge time + /// register + pub const DVBUSDT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); + + /// address: 0x5000082c + /// device VBUS pulsing time + /// register + pub const DVBUSPT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x2c); + + /// address: 0x50000834 + /// device IN endpoint FIFO empty + /// interrupt enable register + pub const DIEPFEINTEN = @intToPtr(*volatile Mmio(32, packed struct { + /// IN EP Tx FIFO empty interrupt enable + /// bits + IEPTXFEIE: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x34); + + /// address: 0x50000900 + /// device IN endpoint 0 control + /// register (DIEP0CTL) + pub const DIEP0CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet length + MPL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// endpoint active + EPACT: u1, + reserved13: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved14: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved15: u1, + reserved16: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x100); + + /// address: 0x50000920 + /// device in endpoint-1 control + /// register + pub const DIEP1CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved4: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x120); + + /// address: 0x50000940 + /// device endpoint-2 control + /// register + pub const DIEP2CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved4: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x140); + + /// address: 0x50000960 + /// device endpoint-3 control + /// register + pub const DIEP3CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved4: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x160); + + /// address: 0x50000b00 + /// device endpoint-0 control + /// register + pub const DOEP0CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum packet length + MPL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Endpoint active + EPACT: u1, + reserved13: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved18: u1, + reserved19: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x300); + + /// address: 0x50000b20 + /// device endpoint-1 control + /// register + pub const DOEP1CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x320); + + /// address: 0x50000b40 + /// device endpoint-2 control + /// register + pub const DOEP2CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x340); + + /// address: 0x50000b60 + /// device endpoint-3 control + /// register + pub const DOEP3CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// maximum packet length + MPL: u11, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), base_address + 0x360); + + /// address: 0x50000908 + /// device endpoint-0 interrupt + /// register + pub const DIEP0INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved0: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved1: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x108); + + /// address: 0x50000928 + /// device endpoint-1 interrupt + /// register + pub const DIEP1INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved0: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved1: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x128); + + /// address: 0x50000948 + /// device endpoint-2 interrupt + /// register + pub const DIEP2INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved0: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved1: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x148); + + /// address: 0x50000968 + /// device endpoint-3 interrupt + /// register + pub const DIEP3INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved0: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved1: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x168); + + /// address: 0x50000b08 + /// device out endpoint-0 interrupt flag + /// register + pub const DOEP0INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved0: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved1: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x308); + + /// address: 0x50000b28 + /// device out endpoint-1 interrupt flag + /// register + pub const DOEP1INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved0: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved1: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x328); + + /// address: 0x50000b48 + /// device out endpoint-2 interrupt flag + /// register + pub const DOEP2INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved0: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved1: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x348); + + /// address: 0x50000b68 + /// device out endpoint-3 interrupt flag + /// register + pub const DOEP3INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved0: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved1: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x368); + + /// address: 0x50000910 + /// device IN endpoint-0 transfer length + /// register + pub const DIEP0LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PCNT: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x110); + + /// address: 0x50000b10 + /// device OUT endpoint-0 transfer length + /// register + pub const DOEP0LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u7, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Packet count + PCNT: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + /// SETUP packet count + STPCNT: u2, + padding0: u1, + }), base_address + 0x310); + + /// address: 0x50000930 + /// device IN endpoint-1 transfer length + /// register + pub const DIEP1LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding0: u1, + }), base_address + 0x130); + + /// address: 0x50000950 + /// device IN endpoint-2 transfer length + /// register + pub const DIEP2LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding0: u1, + }), base_address + 0x150); + + /// address: 0x50000970 + /// device IN endpoint-3 transfer length + /// register + pub const DIEP3LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding0: u1, + }), base_address + 0x170); + + /// address: 0x50000b30 + /// device OUT endpoint-1 transfer length + /// register + pub const DOEP1LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding0: u1, + }), base_address + 0x330); + + /// address: 0x50000b50 + /// device OUT endpoint-2 transfer length + /// register + pub const DOEP2LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding0: u1, + }), base_address + 0x350); + + /// address: 0x50000b70 + /// device OUT endpoint-3 transfer length + /// register + pub const DOEP3LEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding0: u1, + }), base_address + 0x370); + + /// address: 0x50000918 + /// device IN endpoint 0 transmit FIFO + /// status register + pub const DIEP0TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// remaining + IEPTFS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x118); + + /// address: 0x50000938 + /// device IN endpoint 1 transmit FIFO + /// status register + pub const DIEP1TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// remaining + IEPTFS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x138); + + /// address: 0x50000958 + /// device IN endpoint 2 transmit FIFO + /// status register + pub const DIEP2TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// remaining + IEPTFS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x158); + + /// address: 0x50000978 + /// device IN endpoint 3 transmit FIFO + /// status register + pub const DIEP3TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// IN endpoint TxFIFO space + /// remaining + IEPTFS: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x178); + }; + + /// USB on the go full speed + pub const USBFS_PWRCLK = struct { + pub const base_address = 0x50000e00; + + /// address: 0x50000e00 + /// power and clock gating control + /// register (PWRCLKCTL) + pub const PWRCLKCTL = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop the USB clock + SUCLK: u1, + /// Stop HCLK + SHCLK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x0); + }; + + /// Window watchdog timer + pub const WWDGT = struct { + pub const base_address = 0x40002c00; + + /// address: 0x40002c00 + /// Control register + pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit counter + CNT: u7, + /// Activation bit + WDGTEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0x40002c04 + /// Configuration register + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// 7-bit window value + WIN: u7, + /// Prescaler + PSC: u2, + /// Early wakeup interrupt + EWIE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x4); + + /// address: 0x40002c08 + /// Status register + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Early wakeup interrupt + /// flag + EWIF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + }; + + /// Core timer + pub const CTIMER = struct { + pub const base_address = 0xd1000000; + + /// address: 0xd1000000 + /// Timer value (lower half) + pub const mtime_lo = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0xd1000004 + /// Timer value (upper half) + pub const mtime_hi = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xd1000008 + /// Timer comparison value (lower half) + pub const mtimecmp_lo = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0xd100000c + /// Timer comparison value (upper half) + pub const mtimecmp_hi = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0xd1000ff8 + /// Timer control register + pub const mstop = @intToPtr(*volatile Mmio(32, packed struct { + /// Pause (1) or run (0) the timer + TIMESTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xff8); + + /// address: 0xd1000ffc + /// Software interrupt register + pub const msip = @intToPtr(*volatile Mmio(32, packed struct { + /// Generate software interrupts + MSIP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xffc); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +pub const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 3c739c1..f8f5574 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -50,3 +50,14 @@ pub const cortex_m4 = Cpu{ .abi = .none, }, }; + +pub const riscv32_imac = Cpu{ + .name = "RISC-V 32-bit", + .path = root_path ++ "cpus/rv32-imac/riscv32.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, + .os_tag = .freestanding, + .abi = .none, + }, +}; diff --git a/src/modules/cpus/rv32-imac/riscv32.zig b/src/modules/cpus/rv32-imac/riscv32.zig new file mode 100644 index 0000000..57d0bcc --- /dev/null +++ b/src/modules/cpus/rv32-imac/riscv32.zig @@ -0,0 +1,903 @@ +const std = @import("std"); +const root = @import("root"); +const microzig = @import("microzig"); +const app = microzig.app; + +pub fn sei() void { + // asm volatile ("sei"); +} + +pub fn cli() void { + // asm volatile ("cli"); +} + +pub fn wfi() void { + asm volatile ("wfi"); +} + +pub fn wfe() void { + asm volatile ("csrs 0x810, 0x1"); + wfi(); + asm volatile ("csrs 0x810, 0x1"); +} + +pub fn pmpOpenAllSpace() void { + // Config entry0 addr to all 1s to make the range cover all space + asm volatile ("li x6, 0xffffffff" ::: "x6"); + asm volatile ("csrw pmpaddr0, x6"); + // Config entry0 cfg to make it NAPOT address mode, and R/W/X okay + asm volatile ("li x6, 0x7f" ::: "x6"); + asm volatile ("csrw pmpcfg0, x6"); +} + +pub fn switchM2uMode() void { + asm volatile ("la x6, 1f " ::: "x6"); + asm volatile ("csrw mepc, x6"); + asm volatile ("mret"); + asm volatile ("1:"); +} + +// riscv_xlen < 64 +pub const STORE = "sw"; +pub const LOAD = "lw"; +pub const LOG_REGBYTES = 2; +pub const REGBYTES = (1 << LOG_REGBYTES); + +pub const startup_logic = struct { + extern fn microzig_main() noreturn; + + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; + + pub fn _start() callconv(.C) noreturn { + + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, µzig_bss_start); + const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, µzig_data_start); + const data_end = @ptrCast([*]u8, µzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, µzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } + + microzig_main(); + } +}; + +pub const MSTATUS_UIE = 0x00000001; +pub const MSTATUS_SIE = 0x00000002; +pub const MSTATUS_HIE = 0x00000004; +pub const MSTATUS_MIE = 0x00000008; +pub const MSTATUS_UPIE = 0x00000010; +pub const MSTATUS_SPIE = 0x00000020; +pub const MSTATUS_HPIE = 0x00000040; +pub const MSTATUS_MPIE = 0x00000080; +pub const MSTATUS_SPP = 0x00000100; +pub const MSTATUS_MPP = 0x00001800; +pub const MSTATUS_FS = 0x00006000; +pub const MSTATUS_XS = 0x00018000; +pub const MSTATUS_MPRV = 0x00020000; +pub const MSTATUS_PUM = 0x00040000; +pub const MSTATUS_MXR = 0x00080000; +pub const MSTATUS_VM = 0x1F000000; +pub const MSTATUS32_SD = 0x80000000; +pub const MSTATUS64_SD = 0x8000000000000000; +pub const SSTATUS_UIE = 0x00000001; +pub const SSTATUS_SIE = 0x00000002; +pub const SSTATUS_UPIE = 0x00000010; +pub const SSTATUS_SPIE = 0x00000020; +pub const SSTATUS_SPP = 0x00000100; +pub const SSTATUS_FS = 0x00006000; +pub const SSTATUS_XS = 0x00018000; +pub const SSTATUS_PUM = 0x00040000; +pub const SSTATUS32_SD = 0x80000000; +pub const SSTATUS64_SD = 0x8000000000000000; +pub const DCSR_XDEBUGVER = 3 << 30; +pub const DCSR_NDRESET = 1 << 29; +pub const DCSR_FULLRESET = 1 << 28; +pub const DCSR_EBREAKM = 1 << 15; +pub const DCSR_EBREAKH = 1 << 14; +pub const DCSR_EBREAKS = 1 << 13; +pub const DCSR_EBREAKU = 1 << 12; +pub const DCSR_STOPCYCLE = 1 << 10; +pub const DCSR_STOPTIME = 1 << 9; +pub const DCSR_CAUSE = 7 << 6; +pub const DCSR_DEBUGINT = 1 << 5; +pub const DCSR_HALT = 1 << 3; +pub const DCSR_STEP = 1 << 2; +pub const DCSR_PRV = 3 << 0; +pub const DCSR_CAUSE_NONE = 0; +pub const DCSR_CAUSE_SWBP = 1; +pub const DCSR_CAUSE_HWBP = 2; +pub const DCSR_CAUSE_DEBUGINT = 3; +pub const DCSR_CAUSE_STEP = 4; +pub const DCSR_CAUSE_HALT = 5; +pub inline fn MCONTROL_TYPE(xlen: anytype) @TypeOf(0xf << (xlen - 4)) { + return 0xf << (xlen - 4); +} +pub inline fn MCONTROL_DMODE(xlen: anytype) @TypeOf(1 << (xlen - 5)) { + return 1 << (xlen - 5); +} +pub inline fn MCONTROL_MASKMAX(xlen: anytype) @TypeOf(0x3f << (xlen - 11)) { + return @as(c_ulonglong, 0x3f) << (xlen - 11); +} +pub const MCONTROL_SELECT = 1 << 19; +pub const MCONTROL_TIMING = 1 << 18; +pub const MCONTROL_ACTION = 0x3f << 12; +pub const MCONTROL_CHAIN = 1 << 11; +pub const MCONTROL_MATCH = 0xf << 7; +pub const MCONTROL_M = 1 << 6; +pub const MCONTROL_H = 1 << 5; +pub const MCONTROL_S = 1 << 4; +pub const MCONTROL_U = 1 << 3; +pub const MCONTROL_EXECUTE = 1 << 2; +pub const MCONTROL_STORE = 1 << 1; +pub const MCONTROL_LOAD = 1 << 0; +pub const MCONTROL_TYPE_NONE = 0; +pub const MCONTROL_TYPE_MATCH = 2; +pub const MCONTROL_ACTION_DEBUG_EXCEPTION = 0; +pub const MCONTROL_ACTION_DEBUG_MODE = 1; +pub const MCONTROL_ACTION_TRACE_START = 2; +pub const MCONTROL_ACTION_TRACE_STOP = 3; +pub const MCONTROL_ACTION_TRACE_EMIT = 4; +pub const MCONTROL_MATCH_EQUAL = 0; +pub const MCONTROL_MATCH_NAPOT = 1; +pub const MCONTROL_MATCH_GE = 2; +pub const MCONTROL_MATCH_LT = 3; +pub const MCONTROL_MATCH_MASK_LOW = 4; +pub const MCONTROL_MATCH_MASK_HIGH = 5; +pub const MIP_SSIP = 1 << IRQ_S_SOFT; +pub const MIP_HSIP = 1 << IRQ_H_SOFT; +pub const MIP_MSIP = 1 << IRQ_M_SOFT; +pub const MIP_STIP = 1 << IRQ_S_TIMER; +pub const MIP_HTIP = 1 << IRQ_H_TIMER; +pub const MIP_MTIP = 1 << IRQ_M_TIMER; +pub const MIP_SEIP = 1 << IRQ_S_EXT; +pub const MIP_HEIP = 1 << IRQ_H_EXT; +pub const MIP_MEIP = 1 << IRQ_M_EXT; +pub const MIE_SSIE = MIP_SSIP; +pub const MIE_HSIE = MIP_HSIP; +pub const MIE_MSIE = MIP_MSIP; +pub const MIE_STIE = MIP_STIP; +pub const MIE_HTIE = MIP_HTIP; +pub const MIE_MTIE = MIP_MTIP; +pub const MIE_SEIE = MIP_SEIP; +pub const MIE_HEIE = MIP_HEIP; +pub const MIE_MEIE = MIP_MEIP; +pub const SIP_SSIP = MIP_SSIP; +pub const SIP_STIP = MIP_STIP; +pub const PRV_U = 0; +pub const PRV_S = 1; +pub const PRV_H = 2; +pub const PRV_M = 3; +pub const VM_MBARE = 0; +pub const VM_MBB = 1; +pub const VM_MBBID = 2; +pub const VM_SV32 = 8; +pub const VM_SV39 = 9; +pub const VM_SV48 = 10; +pub const IRQ_S_SOFT = 1; +pub const IRQ_H_SOFT = 2; +pub const IRQ_M_SOFT = 3; +pub const IRQ_S_TIMER = 5; +pub const IRQ_H_TIMER = 6; +pub const IRQ_M_TIMER = 7; +pub const IRQ_S_EXT = 9; +pub const IRQ_H_EXT = 10; +pub const IRQ_M_EXT = 11; +pub const IRQ_COP = 12; +pub const IRQ_HOST = 13; +pub const DEFAULT_RSTVEC = 0x00001000; +pub const DEFAULT_NMIVEC = 0x00001004; +pub const DEFAULT_MTVEC = 0x00001010; +pub const CONFIG_STRING_ADDR = 0x0000100C; +pub const EXT_IO_BASE = 0x40000000; +pub const DRAM_BASE = 0x80000000; +pub const PTE_V = 0x001; +pub const PTE_R = 0x002; +pub const PTE_W = 0x004; +pub const PTE_X = 0x008; +pub const PTE_U = 0x010; +pub const PTE_G = 0x020; +pub const PTE_A = 0x040; +pub const PTE_D = 0x080; +pub const PTE_SOFT = 0x300; +pub const PTE_PPN_SHIFT = 10; +pub inline fn PTE_TABLE(PTE: anytype) @TypeOf((PTE & (((PTE_V | PTE_R) | PTE_W) | PTE_X)) == PTE_V) { + return (PTE & (((PTE_V | PTE_R) | PTE_W) | PTE_X)) == PTE_V; +} +pub const MSTATUS_SD = MSTATUS32_SD; +pub const SSTATUS_SD = SSTATUS32_SD; +pub const RISCV_PGLEVEL_BITS = 10; +pub const RISCV_PGSHIFT = 12; +pub const RISCV_PGSIZE = 1 << RISCV_PGSHIFT; +pub const RISCV_ENCODING_H = ""; +pub const MATCH_BEQ = 0x63; +pub const MASK_BEQ = 0x707f; +pub const MATCH_BNE = 0x1063; +pub const MASK_BNE = 0x707f; +pub const MATCH_BLT = 0x4063; +pub const MASK_BLT = 0x707f; +pub const MATCH_BGE = 0x5063; +pub const MASK_BGE = 0x707f; +pub const MATCH_BLTU = 0x6063; +pub const MASK_BLTU = 0x707f; +pub const MATCH_BGEU = 0x7063; +pub const MASK_BGEU = 0x707f; +pub const MATCH_JALR = 0x67; +pub const MASK_JALR = 0x707f; +pub const MATCH_JAL = 0x6f; +pub const MASK_JAL = 0x7f; +pub const MATCH_LUI = 0x37; +pub const MASK_LUI = 0x7f; +pub const MATCH_AUIPC = 0x17; +pub const MASK_AUIPC = 0x7f; +pub const MATCH_ADDI = 0x13; +pub const MASK_ADDI = 0x707f; +pub const MATCH_SLLI = 0x1013; +pub const MASK_SLLI = 0xfc00707f; +pub const MATCH_SLTI = 0x2013; +pub const MASK_SLTI = 0x707f; +pub const MATCH_SLTIU = 0x3013; +pub const MASK_SLTIU = 0x707f; +pub const MATCH_XORI = 0x4013; +pub const MASK_XORI = 0x707f; +pub const MATCH_SRLI = 0x5013; +pub const MASK_SRLI = 0xfc00707f; +pub const MATCH_SRAI = 0x40005013; +pub const MASK_SRAI = 0xfc00707f; +pub const MATCH_ORI = 0x6013; +pub const MASK_ORI = 0x707f; +pub const MATCH_ANDI = 0x7013; +pub const MASK_ANDI = 0x707f; +pub const MATCH_ADD = 0x33; +pub const MASK_ADD = 0xfe00707f; +pub const MATCH_SUB = 0x40000033; +pub const MASK_SUB = 0xfe00707f; +pub const MATCH_SLL = 0x1033; +pub const MASK_SLL = 0xfe00707f; +pub const MATCH_SLT = 0x2033; +pub const MASK_SLT = 0xfe00707f; +pub const MATCH_SLTU = 0x3033; +pub const MASK_SLTU = 0xfe00707f; +pub const MATCH_XOR = 0x4033; +pub const MASK_XOR = 0xfe00707f; +pub const MATCH_SRL = 0x5033; +pub const MASK_SRL = 0xfe00707f; +pub const MATCH_SRA = 0x40005033; +pub const MASK_SRA = 0xfe00707f; +pub const MATCH_OR = 0x6033; +pub const MASK_OR = 0xfe00707f; +pub const MATCH_AND = 0x7033; +pub const MASK_AND = 0xfe00707f; +pub const MATCH_ADDIW = 0x1b; +pub const MASK_ADDIW = 0x707f; +pub const MATCH_SLLIW = 0x101b; +pub const MASK_SLLIW = 0xfe00707f; +pub const MATCH_SRLIW = 0x501b; +pub const MASK_SRLIW = 0xfe00707f; +pub const MATCH_SRAIW = 0x4000501b; +pub const MASK_SRAIW = 0xfe00707f; +pub const MATCH_ADDW = 0x3b; +pub const MASK_ADDW = 0xfe00707f; +pub const MATCH_SUBW = 0x4000003b; +pub const MASK_SUBW = 0xfe00707f; +pub const MATCH_SLLW = 0x103b; +pub const MASK_SLLW = 0xfe00707f; +pub const MATCH_SRLW = 0x503b; +pub const MASK_SRLW = 0xfe00707f; +pub const MATCH_SRAW = 0x4000503b; +pub const MASK_SRAW = 0xfe00707f; +pub const MATCH_LB = 0x3; +pub const MASK_LB = 0x707f; +pub const MATCH_LH = 0x1003; +pub const MASK_LH = 0x707f; +pub const MATCH_LW = 0x2003; +pub const MASK_LW = 0x707f; +pub const MATCH_LD = 0x3003; +pub const MASK_LD = 0x707f; +pub const MATCH_LBU = 0x4003; +pub const MASK_LBU = 0x707f; +pub const MATCH_LHU = 0x5003; +pub const MASK_LHU = 0x707f; +pub const MATCH_LWU = 0x6003; +pub const MASK_LWU = 0x707f; +pub const MATCH_SB = 0x23; +pub const MASK_SB = 0x707f; +pub const MATCH_SH = 0x1023; +pub const MASK_SH = 0x707f; +pub const MATCH_SW = 0x2023; +pub const MASK_SW = 0x707f; +pub const MATCH_SD = 0x3023; +pub const MASK_SD = 0x707f; +pub const MATCH_FENCE = 0xf; +pub const MASK_FENCE = 0x707f; +pub const MATCH_FENCE_I = 0x100f; +pub const MASK_FENCE_I = 0x707f; +pub const MATCH_MUL = 0x2000033; +pub const MASK_MUL = 0xfe00707f; +pub const MATCH_MULH = 0x2001033; +pub const MASK_MULH = 0xfe00707f; +pub const MATCH_MULHSU = 0x2002033; +pub const MASK_MULHSU = 0xfe00707f; +pub const MATCH_MULHU = 0x2003033; +pub const MASK_MULHU = 0xfe00707f; +pub const MATCH_DIV = 0x2004033; +pub const MASK_DIV = 0xfe00707f; +pub const MATCH_DIVU = 0x2005033; +pub const MASK_DIVU = 0xfe00707f; +pub const MATCH_REM = 0x2006033; +pub const MASK_REM = 0xfe00707f; +pub const MATCH_REMU = 0x2007033; +pub const MASK_REMU = 0xfe00707f; +pub const MATCH_MULW = 0x200003b; +pub const MASK_MULW = 0xfe00707f; +pub const MATCH_DIVW = 0x200403b; +pub const MASK_DIVW = 0xfe00707f; +pub const MATCH_DIVUW = 0x200503b; +pub const MASK_DIVUW = 0xfe00707f; +pub const MATCH_REMW = 0x200603b; +pub const MASK_REMW = 0xfe00707f; +pub const MATCH_REMUW = 0x200703b; +pub const MASK_REMUW = 0xfe00707f; +pub const MATCH_AMOADD_W = 0x202f; +pub const MASK_AMOADD_W = 0xf800707f; +pub const MATCH_AMOXOR_W = 0x2000202f; +pub const MASK_AMOXOR_W = 0xf800707f; +pub const MATCH_AMOOR_W = 0x4000202f; +pub const MASK_AMOOR_W = 0xf800707f; +pub const MATCH_AMOAND_W = 0x6000202f; +pub const MASK_AMOAND_W = 0xf800707f; +pub const MATCH_AMOMIN_W = 0x8000202f; +pub const MASK_AMOMIN_W = 0xf800707f; +pub const MATCH_AMOMAX_W = 0xa000202f; +pub const MASK_AMOMAX_W = 0xf800707f; +pub const MATCH_AMOMINU_W = 0xc000202f; +pub const MASK_AMOMINU_W = 0xf800707f; +pub const MATCH_AMOMAXU_W = 0xe000202f; +pub const MASK_AMOMAXU_W = 0xf800707f; +pub const MATCH_AMOSWAP_W = 0x800202f; +pub const MASK_AMOSWAP_W = 0xf800707f; +pub const MATCH_LR_W = 0x1000202f; +pub const MASK_LR_W = 0xf9f0707f; +pub const MATCH_SC_W = 0x1800202f; +pub const MASK_SC_W = 0xf800707f; +pub const MATCH_AMOADD_D = 0x302f; +pub const MASK_AMOADD_D = 0xf800707f; +pub const MATCH_AMOXOR_D = 0x2000302f; +pub const MASK_AMOXOR_D = 0xf800707f; +pub const MATCH_AMOOR_D = 0x4000302f; +pub const MASK_AMOOR_D = 0xf800707f; +pub const MATCH_AMOAND_D = 0x6000302f; +pub const MASK_AMOAND_D = 0xf800707f; +pub const MATCH_AMOMIN_D = 0x8000302f; +pub const MASK_AMOMIN_D = 0xf800707f; +pub const MATCH_AMOMAX_D = 0xa000302f; +pub const MASK_AMOMAX_D = 0xf800707f; +pub const MATCH_AMOMINU_D = 0xc000302f; +pub const MASK_AMOMINU_D = 0xf800707f; +pub const MATCH_AMOMAXU_D = 0xe000302f; +pub const MASK_AMOMAXU_D = 0xf800707f; +pub const MATCH_AMOSWAP_D = 0x800302f; +pub const MASK_AMOSWAP_D = 0xf800707f; +pub const MATCH_LR_D = 0x1000302f; +pub const MASK_LR_D = 0xf9f0707f; +pub const MATCH_SC_D = 0x1800302f; +pub const MASK_SC_D = 0xf800707f; +pub const MATCH_ECALL = 0x73; +pub const MASK_ECALL = 0xffffffff; +pub const MATCH_EBREAK = 0x100073; +pub const MASK_EBREAK = 0xffffffff; +pub const MATCH_URET = 0x200073; +pub const MASK_URET = 0xffffffff; +pub const MATCH_SRET = 0x10200073; +pub const MASK_SRET = 0xffffffff; +pub const MATCH_HRET = 0x20200073; +pub const MASK_HRET = 0xffffffff; +pub const MATCH_MRET = 0x30200073; +pub const MASK_MRET = 0xffffffff; +pub const MATCH_DRET = 0x7b200073; +pub const MASK_DRET = 0xffffffff; +pub const MATCH_SFENCE_VM = 0x10400073; +pub const MASK_SFENCE_VM = 0xfff07fff; +pub const MATCH_WFI = 0x10500073; +pub const MASK_WFI = 0xffffffff; +pub const MATCH_CSRRW = 0x1073; +pub const MASK_CSRRW = 0x707f; +pub const MATCH_CSRRS = 0x2073; +pub const MASK_CSRRS = 0x707f; +pub const MATCH_CSRRC = 0x3073; +pub const MASK_CSRRC = 0x707f; +pub const MATCH_CSRRWI = 0x5073; +pub const MASK_CSRRWI = 0x707f; +pub const MATCH_CSRRSI = 0x6073; +pub const MASK_CSRRSI = 0x707f; +pub const MATCH_CSRRCI = 0x7073; +pub const MASK_CSRRCI = 0x707f; +pub const MATCH_FADD_S = 0x53; +pub const MASK_FADD_S = 0xfe00007f; +pub const MATCH_FSUB_S = 0x8000053; +pub const MASK_FSUB_S = 0xfe00007f; +pub const MATCH_FMUL_S = 0x10000053; +pub const MASK_FMUL_S = 0xfe00007f; +pub const MATCH_FDIV_S = 0x18000053; +pub const MASK_FDIV_S = 0xfe00007f; +pub const MATCH_FSGNJ_S = 0x20000053; +pub const MASK_FSGNJ_S = 0xfe00707f; +pub const MATCH_FSGNJN_S = 0x20001053; +pub const MASK_FSGNJN_S = 0xfe00707f; +pub const MATCH_FSGNJX_S = 0x20002053; +pub const MASK_FSGNJX_S = 0xfe00707f; +pub const MATCH_FMIN_S = 0x28000053; +pub const MASK_FMIN_S = 0xfe00707f; +pub const MATCH_FMAX_S = 0x28001053; +pub const MASK_FMAX_S = 0xfe00707f; +pub const MATCH_FSQRT_S = 0x58000053; +pub const MASK_FSQRT_S = 0xfff0007f; +pub const MATCH_FADD_D = 0x2000053; +pub const MASK_FADD_D = 0xfe00007f; +pub const MATCH_FSUB_D = 0xa000053; +pub const MASK_FSUB_D = 0xfe00007f; +pub const MATCH_FMUL_D = 0x12000053; +pub const MASK_FMUL_D = 0xfe00007f; +pub const MATCH_FDIV_D = 0x1a000053; +pub const MASK_FDIV_D = 0xfe00007f; +pub const MATCH_FSGNJ_D = 0x22000053; +pub const MASK_FSGNJ_D = 0xfe00707f; +pub const MATCH_FSGNJN_D = 0x22001053; +pub const MASK_FSGNJN_D = 0xfe00707f; +pub const MATCH_FSGNJX_D = 0x22002053; +pub const MASK_FSGNJX_D = 0xfe00707f; +pub const MATCH_FMIN_D = 0x2a000053; +pub const MASK_FMIN_D = 0xfe00707f; +pub const MATCH_FMAX_D = 0x2a001053; +pub const MASK_FMAX_D = 0xfe00707f; +pub const MATCH_FCVT_S_D = 0x40100053; +pub const MASK_FCVT_S_D = 0xfff0007f; +pub const MATCH_FCVT_D_S = 0x42000053; +pub const MASK_FCVT_D_S = 0xfff0007f; +pub const MATCH_FSQRT_D = 0x5a000053; +pub const MASK_FSQRT_D = 0xfff0007f; +pub const MATCH_FLE_S = 0xa0000053; +pub const MASK_FLE_S = 0xfe00707f; +pub const MATCH_FLT_S = 0xa0001053; +pub const MASK_FLT_S = 0xfe00707f; +pub const MATCH_FEQ_S = 0xa0002053; +pub const MASK_FEQ_S = 0xfe00707f; +pub const MATCH_FLE_D = 0xa2000053; +pub const MASK_FLE_D = 0xfe00707f; +pub const MATCH_FLT_D = 0xa2001053; +pub const MASK_FLT_D = 0xfe00707f; +pub const MATCH_FEQ_D = 0xa2002053; +pub const MASK_FEQ_D = 0xfe00707f; +pub const MATCH_FCVT_W_S = 0xc0000053; +pub const MASK_FCVT_W_S = 0xfff0007f; +pub const MATCH_FCVT_WU_S = 0xc0100053; +pub const MASK_FCVT_WU_S = 0xfff0007f; +pub const MATCH_FCVT_L_S = 0xc0200053; +pub const MASK_FCVT_L_S = 0xfff0007f; +pub const MATCH_FCVT_LU_S = 0xc0300053; +pub const MASK_FCVT_LU_S = 0xfff0007f; +pub const MATCH_FMV_X_S = 0xe0000053; +pub const MASK_FMV_X_S = 0xfff0707f; +pub const MATCH_FCLASS_S = 0xe0001053; +pub const MASK_FCLASS_S = 0xfff0707f; +pub const MATCH_FCVT_W_D = 0xc2000053; +pub const MASK_FCVT_W_D = 0xfff0007f; +pub const MATCH_FCVT_WU_D = 0xc2100053; +pub const MASK_FCVT_WU_D = 0xfff0007f; +pub const MATCH_FCVT_L_D = 0xc2200053; +pub const MASK_FCVT_L_D = 0xfff0007f; +pub const MATCH_FCVT_LU_D = 0xc2300053; +pub const MASK_FCVT_LU_D = 0xfff0007f; +pub const MATCH_FMV_X_D = 0xe2000053; +pub const MASK_FMV_X_D = 0xfff0707f; +pub const MATCH_FCLASS_D = 0xe2001053; +pub const MASK_FCLASS_D = 0xfff0707f; +pub const MATCH_FCVT_S_W = 0xd0000053; +pub const MASK_FCVT_S_W = 0xfff0007f; +pub const MATCH_FCVT_S_WU = 0xd0100053; +pub const MASK_FCVT_S_WU = 0xfff0007f; +pub const MATCH_FCVT_S_L = 0xd0200053; +pub const MASK_FCVT_S_L = 0xfff0007f; +pub const MATCH_FCVT_S_LU = 0xd0300053; +pub const MASK_FCVT_S_LU = 0xfff0007f; +pub const MATCH_FMV_S_X = 0xf0000053; +pub const MASK_FMV_S_X = 0xfff0707f; +pub const MATCH_FCVT_D_W = 0xd2000053; +pub const MASK_FCVT_D_W = 0xfff0007f; +pub const MATCH_FCVT_D_WU = 0xd2100053; +pub const MASK_FCVT_D_WU = 0xfff0007f; +pub const MATCH_FCVT_D_L = 0xd2200053; +pub const MASK_FCVT_D_L = 0xfff0007f; +pub const MATCH_FCVT_D_LU = 0xd2300053; +pub const MASK_FCVT_D_LU = 0xfff0007f; +pub const MATCH_FMV_D_X = 0xf2000053; +pub const MASK_FMV_D_X = 0xfff0707f; +pub const MATCH_FLW = 0x2007; +pub const MASK_FLW = 0x707f; +pub const MATCH_FLD = 0x3007; +pub const MASK_FLD = 0x707f; +pub const MATCH_FSW = 0x2027; +pub const MASK_FSW = 0x707f; +pub const MATCH_FSD = 0x3027; +pub const MASK_FSD = 0x707f; +pub const MATCH_FMADD_S = 0x43; +pub const MASK_FMADD_S = 0x600007f; +pub const MATCH_FMSUB_S = 0x47; +pub const MASK_FMSUB_S = 0x600007f; +pub const MATCH_FNMSUB_S = 0x4b; +pub const MASK_FNMSUB_S = 0x600007f; +pub const MATCH_FNMADD_S = 0x4f; +pub const MASK_FNMADD_S = 0x600007f; +pub const MATCH_FMADD_D = 0x2000043; +pub const MASK_FMADD_D = 0x600007f; +pub const MATCH_FMSUB_D = 0x2000047; +pub const MASK_FMSUB_D = 0x600007f; +pub const MATCH_FNMSUB_D = 0x200004b; +pub const MASK_FNMSUB_D = 0x600007f; +pub const MATCH_FNMADD_D = 0x200004f; +pub const MASK_FNMADD_D = 0x600007f; +pub const MATCH_C_NOP = 0x1; +pub const MASK_C_NOP = 0xffff; +pub const MATCH_C_ADDI16SP = 0x6101; +pub const MASK_C_ADDI16SP = 0xef83; +pub const MATCH_C_JR = 0x8002; +pub const MASK_C_JR = 0xf07f; +pub const MATCH_C_JALR = 0x9002; +pub const MASK_C_JALR = 0xf07f; +pub const MATCH_C_EBREAK = 0x9002; +pub const MASK_C_EBREAK = 0xffff; +pub const MATCH_C_LD = 0x6000; +pub const MASK_C_LD = 0xe003; +pub const MATCH_C_SD = 0xe000; +pub const MASK_C_SD = 0xe003; +pub const MATCH_C_ADDIW = 0x2001; +pub const MASK_C_ADDIW = 0xe003; +pub const MATCH_C_LDSP = 0x6002; +pub const MASK_C_LDSP = 0xe003; +pub const MATCH_C_SDSP = 0xe002; +pub const MASK_C_SDSP = 0xe003; +pub const MATCH_C_ADDI4SPN = 0x0; +pub const MASK_C_ADDI4SPN = 0xe003; +pub const MATCH_C_FLD = 0x2000; +pub const MASK_C_FLD = 0xe003; +pub const MATCH_C_LW = 0x4000; +pub const MASK_C_LW = 0xe003; +pub const MATCH_C_FLW = 0x6000; +pub const MASK_C_FLW = 0xe003; +pub const MATCH_C_FSD = 0xa000; +pub const MASK_C_FSD = 0xe003; +pub const MATCH_C_SW = 0xc000; +pub const MASK_C_SW = 0xe003; +pub const MATCH_C_FSW = 0xe000; +pub const MASK_C_FSW = 0xe003; +pub const MATCH_C_ADDI = 0x1; +pub const MASK_C_ADDI = 0xe003; +pub const MATCH_C_JAL = 0x2001; +pub const MASK_C_JAL = 0xe003; +pub const MATCH_C_LI = 0x4001; +pub const MASK_C_LI = 0xe003; +pub const MATCH_C_LUI = 0x6001; +pub const MASK_C_LUI = 0xe003; +pub const MATCH_C_SRLI = 0x8001; +pub const MASK_C_SRLI = 0xec03; +pub const MATCH_C_SRAI = 0x8401; +pub const MASK_C_SRAI = 0xec03; +pub const MATCH_C_ANDI = 0x8801; +pub const MASK_C_ANDI = 0xec03; +pub const MATCH_C_SUB = 0x8c01; +pub const MASK_C_SUB = 0xfc63; +pub const MATCH_C_XOR = 0x8c21; +pub const MASK_C_XOR = 0xfc63; +pub const MATCH_C_OR = 0x8c41; +pub const MASK_C_OR = 0xfc63; +pub const MATCH_C_AND = 0x8c61; +pub const MASK_C_AND = 0xfc63; +pub const MATCH_C_SUBW = 0x9c01; +pub const MASK_C_SUBW = 0xfc63; +pub const MATCH_C_ADDW = 0x9c21; +pub const MASK_C_ADDW = 0xfc63; +pub const MATCH_C_J = 0xa001; +pub const MASK_C_J = 0xe003; +pub const MATCH_C_BEQZ = 0xc001; +pub const MASK_C_BEQZ = 0xe003; +pub const MATCH_C_BNEZ = 0xe001; +pub const MASK_C_BNEZ = 0xe003; +pub const MATCH_C_SLLI = 0x2; +pub const MASK_C_SLLI = 0xe003; +pub const MATCH_C_FLDSP = 0x2002; +pub const MASK_C_FLDSP = 0xe003; +pub const MATCH_C_LWSP = 0x4002; +pub const MASK_C_LWSP = 0xe003; +pub const MATCH_C_FLWSP = 0x6002; +pub const MASK_C_FLWSP = 0xe003; +pub const MATCH_C_MV = 0x8002; +pub const MASK_C_MV = 0xf003; +pub const MATCH_C_ADD = 0x9002; +pub const MASK_C_ADD = 0xf003; +pub const MATCH_C_FSDSP = 0xa002; +pub const MASK_C_FSDSP = 0xe003; +pub const MATCH_C_SWSP = 0xc002; +pub const MASK_C_SWSP = 0xe003; +pub const MATCH_C_FSWSP = 0xe002; +pub const MASK_C_FSWSP = 0xe003; +pub const MATCH_CUSTOM0 = 0xb; +pub const MASK_CUSTOM0 = 0x707f; +pub const MATCH_CUSTOM0_RS1 = 0x200b; +pub const MASK_CUSTOM0_RS1 = 0x707f; +pub const MATCH_CUSTOM0_RS1_RS2 = 0x300b; +pub const MASK_CUSTOM0_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM0_RD = 0x400b; +pub const MASK_CUSTOM0_RD = 0x707f; +pub const MATCH_CUSTOM0_RD_RS1 = 0x600b; +pub const MASK_CUSTOM0_RD_RS1 = 0x707f; +pub const MATCH_CUSTOM0_RD_RS1_RS2 = 0x700b; +pub const MASK_CUSTOM0_RD_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM1 = 0x2b; +pub const MASK_CUSTOM1 = 0x707f; +pub const MATCH_CUSTOM1_RS1 = 0x202b; +pub const MASK_CUSTOM1_RS1 = 0x707f; +pub const MATCH_CUSTOM1_RS1_RS2 = 0x302b; +pub const MASK_CUSTOM1_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM1_RD = 0x402b; +pub const MASK_CUSTOM1_RD = 0x707f; +pub const MATCH_CUSTOM1_RD_RS1 = 0x602b; +pub const MASK_CUSTOM1_RD_RS1 = 0x707f; +pub const MATCH_CUSTOM1_RD_RS1_RS2 = 0x702b; +pub const MASK_CUSTOM1_RD_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM2 = 0x5b; +pub const MASK_CUSTOM2 = 0x707f; +pub const MATCH_CUSTOM2_RS1 = 0x205b; +pub const MASK_CUSTOM2_RS1 = 0x707f; +pub const MATCH_CUSTOM2_RS1_RS2 = 0x305b; +pub const MASK_CUSTOM2_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM2_RD = 0x405b; +pub const MASK_CUSTOM2_RD = 0x707f; +pub const MATCH_CUSTOM2_RD_RS1 = 0x605b; +pub const MASK_CUSTOM2_RD_RS1 = 0x707f; +pub const MATCH_CUSTOM2_RD_RS1_RS2 = 0x705b; +pub const MASK_CUSTOM2_RD_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM3 = 0x7b; +pub const MASK_CUSTOM3 = 0x707f; +pub const MATCH_CUSTOM3_RS1 = 0x207b; +pub const MASK_CUSTOM3_RS1 = 0x707f; +pub const MATCH_CUSTOM3_RS1_RS2 = 0x307b; +pub const MASK_CUSTOM3_RS1_RS2 = 0x707f; +pub const MATCH_CUSTOM3_RD = 0x407b; +pub const MASK_CUSTOM3_RD = 0x707f; +pub const MATCH_CUSTOM3_RD_RS1 = 0x607b; +pub const MASK_CUSTOM3_RD_RS1 = 0x707f; +pub const MATCH_CUSTOM3_RD_RS1_RS2 = 0x707b; +pub const MASK_CUSTOM3_RD_RS1_RS2 = 0x707f; +pub const CSR_FFLAGS = 0x1; +pub const CSR_FRM = 0x2; +pub const CSR_FCSR = 0x3; +pub const CSR_CYCLE = 0xc00; +pub const CSR_TIME = 0xc01; +pub const CSR_INSTRET = 0xc02; +pub const CSR_HPMCOUNTER3 = 0xc03; +pub const CSR_HPMCOUNTER4 = 0xc04; +pub const CSR_HPMCOUNTER5 = 0xc05; +pub const CSR_HPMCOUNTER6 = 0xc06; +pub const CSR_HPMCOUNTER7 = 0xc07; +pub const CSR_HPMCOUNTER8 = 0xc08; +pub const CSR_HPMCOUNTER9 = 0xc09; +pub const CSR_HPMCOUNTER10 = 0xc0a; +pub const CSR_HPMCOUNTER11 = 0xc0b; +pub const CSR_HPMCOUNTER12 = 0xc0c; +pub const CSR_HPMCOUNTER13 = 0xc0d; +pub const CSR_HPMCOUNTER14 = 0xc0e; +pub const CSR_HPMCOUNTER15 = 0xc0f; +pub const CSR_HPMCOUNTER16 = 0xc10; +pub const CSR_HPMCOUNTER17 = 0xc11; +pub const CSR_HPMCOUNTER18 = 0xc12; +pub const CSR_HPMCOUNTER19 = 0xc13; +pub const CSR_HPMCOUNTER20 = 0xc14; +pub const CSR_HPMCOUNTER21 = 0xc15; +pub const CSR_HPMCOUNTER22 = 0xc16; +pub const CSR_HPMCOUNTER23 = 0xc17; +pub const CSR_HPMCOUNTER24 = 0xc18; +pub const CSR_HPMCOUNTER25 = 0xc19; +pub const CSR_HPMCOUNTER26 = 0xc1a; +pub const CSR_HPMCOUNTER27 = 0xc1b; +pub const CSR_HPMCOUNTER28 = 0xc1c; +pub const CSR_HPMCOUNTER29 = 0xc1d; +pub const CSR_HPMCOUNTER30 = 0xc1e; +pub const CSR_HPMCOUNTER31 = 0xc1f; +pub const CSR_SSTATUS = 0x100; +pub const CSR_SIE = 0x104; +pub const CSR_STVEC = 0x105; +pub const CSR_SSCRATCH = 0x140; +pub const CSR_SEPC = 0x141; +pub const CSR_SCAUSE = 0x142; +pub const CSR_SBADADDR = 0x143; +pub const CSR_SIP = 0x144; +pub const CSR_SPTBR = 0x180; +pub const CSR_MSTATUS = 0x300; +pub const CSR_MISA = 0x301; +pub const CSR_MEDELEG = 0x302; +pub const CSR_MIDELEG = 0x303; +pub const CSR_MIE = 0x304; +pub const CSR_MTVEC = 0x305; +pub const CSR_MCOUNTEREN = 0x306; +pub const CSR_MSCRATCH = 0x340; +pub const CSR_MEPC = 0x341; +pub const CSR_MCAUSE = 0x342; +pub const CSR_MBADADDR = 0x343; +pub const CSR_MIP = 0x344; +pub const CSR_TSELECT = 0x7a0; +pub const CSR_TDATA1 = 0x7a1; +pub const CSR_TDATA2 = 0x7a2; +pub const CSR_TDATA3 = 0x7a3; +pub const CSR_DCSR = 0x7b0; +pub const CSR_DPC = 0x7b1; +pub const CSR_DSCRATCH = 0x7b2; +pub const CSR_MCYCLE = 0xb00; +pub const CSR_MINSTRET = 0xb02; +pub const CSR_MHPMCOUNTER3 = 0xb03; +pub const CSR_MHPMCOUNTER4 = 0xb04; +pub const CSR_MHPMCOUNTER5 = 0xb05; +pub const CSR_MHPMCOUNTER6 = 0xb06; +pub const CSR_MHPMCOUNTER7 = 0xb07; +pub const CSR_MHPMCOUNTER8 = 0xb08; +pub const CSR_MHPMCOUNTER9 = 0xb09; +pub const CSR_MHPMCOUNTER10 = 0xb0a; +pub const CSR_MHPMCOUNTER11 = 0xb0b; +pub const CSR_MHPMCOUNTER12 = 0xb0c; +pub const CSR_MHPMCOUNTER13 = 0xb0d; +pub const CSR_MHPMCOUNTER14 = 0xb0e; +pub const CSR_MHPMCOUNTER15 = 0xb0f; +pub const CSR_MHPMCOUNTER16 = 0xb10; +pub const CSR_MHPMCOUNTER17 = 0xb11; +pub const CSR_MHPMCOUNTER18 = 0xb12; +pub const CSR_MHPMCOUNTER19 = 0xb13; +pub const CSR_MHPMCOUNTER20 = 0xb14; +pub const CSR_MHPMCOUNTER21 = 0xb15; +pub const CSR_MHPMCOUNTER22 = 0xb16; +pub const CSR_MHPMCOUNTER23 = 0xb17; +pub const CSR_MHPMCOUNTER24 = 0xb18; +pub const CSR_MHPMCOUNTER25 = 0xb19; +pub const CSR_MHPMCOUNTER26 = 0xb1a; +pub const CSR_MHPMCOUNTER27 = 0xb1b; +pub const CSR_MHPMCOUNTER28 = 0xb1c; +pub const CSR_MHPMCOUNTER29 = 0xb1d; +pub const CSR_MHPMCOUNTER30 = 0xb1e; +pub const CSR_MHPMCOUNTER31 = 0xb1f; +pub const CSR_MUCOUNTEREN = 0x320; +pub const CSR_MSCOUNTEREN = 0x321; +pub const CSR_MHPMEVENT3 = 0x323; +pub const CSR_MHPMEVENT4 = 0x324; +pub const CSR_MHPMEVENT5 = 0x325; +pub const CSR_MHPMEVENT6 = 0x326; +pub const CSR_MHPMEVENT7 = 0x327; +pub const CSR_MHPMEVENT8 = 0x328; +pub const CSR_MHPMEVENT9 = 0x329; +pub const CSR_MHPMEVENT10 = 0x32a; +pub const CSR_MHPMEVENT11 = 0x32b; +pub const CSR_MHPMEVENT12 = 0x32c; +pub const CSR_MHPMEVENT13 = 0x32d; +pub const CSR_MHPMEVENT14 = 0x32e; +pub const CSR_MHPMEVENT15 = 0x32f; +pub const CSR_MHPMEVENT16 = 0x330; +pub const CSR_MHPMEVENT17 = 0x331; +pub const CSR_MHPMEVENT18 = 0x332; +pub const CSR_MHPMEVENT19 = 0x333; +pub const CSR_MHPMEVENT20 = 0x334; +pub const CSR_MHPMEVENT21 = 0x335; +pub const CSR_MHPMEVENT22 = 0x336; +pub const CSR_MHPMEVENT23 = 0x337; +pub const CSR_MHPMEVENT24 = 0x338; +pub const CSR_MHPMEVENT25 = 0x339; +pub const CSR_MHPMEVENT26 = 0x33a; +pub const CSR_MHPMEVENT27 = 0x33b; +pub const CSR_MHPMEVENT28 = 0x33c; +pub const CSR_MHPMEVENT29 = 0x33d; +pub const CSR_MHPMEVENT30 = 0x33e; +pub const CSR_MHPMEVENT31 = 0x33f; +pub const CSR_MVENDORID = 0xf11; +pub const CSR_MARCHID = 0xf12; +pub const CSR_MIMPID = 0xf13; +pub const CSR_MHARTID = 0xf14; +pub const CSR_CYCLEH = 0xc80; +pub const CSR_TIMEH = 0xc81; +pub const CSR_INSTRETH = 0xc82; +pub const CSR_HPMCOUNTER3H = 0xc83; +pub const CSR_HPMCOUNTER4H = 0xc84; +pub const CSR_HPMCOUNTER5H = 0xc85; +pub const CSR_HPMCOUNTER6H = 0xc86; +pub const CSR_HPMCOUNTER7H = 0xc87; +pub const CSR_HPMCOUNTER8H = 0xc88; +pub const CSR_HPMCOUNTER9H = 0xc89; +pub const CSR_HPMCOUNTER10H = 0xc8a; +pub const CSR_HPMCOUNTER11H = 0xc8b; +pub const CSR_HPMCOUNTER12H = 0xc8c; +pub const CSR_HPMCOUNTER13H = 0xc8d; +pub const CSR_HPMCOUNTER14H = 0xc8e; +pub const CSR_HPMCOUNTER15H = 0xc8f; +pub const CSR_HPMCOUNTER16H = 0xc90; +pub const CSR_HPMCOUNTER17H = 0xc91; +pub const CSR_HPMCOUNTER18H = 0xc92; +pub const CSR_HPMCOUNTER19H = 0xc93; +pub const CSR_HPMCOUNTER20H = 0xc94; +pub const CSR_HPMCOUNTER21H = 0xc95; +pub const CSR_HPMCOUNTER22H = 0xc96; +pub const CSR_HPMCOUNTER23H = 0xc97; +pub const CSR_HPMCOUNTER24H = 0xc98; +pub const CSR_HPMCOUNTER25H = 0xc99; +pub const CSR_HPMCOUNTER26H = 0xc9a; +pub const CSR_HPMCOUNTER27H = 0xc9b; +pub const CSR_HPMCOUNTER28H = 0xc9c; +pub const CSR_HPMCOUNTER29H = 0xc9d; +pub const CSR_HPMCOUNTER30H = 0xc9e; +pub const CSR_HPMCOUNTER31H = 0xc9f; +pub const CSR_MCYCLEH = 0xb80; +pub const CSR_MINSTRETH = 0xb82; +pub const CSR_MHPMCOUNTER3H = 0xb83; +pub const CSR_MHPMCOUNTER4H = 0xb84; +pub const CSR_MHPMCOUNTER5H = 0xb85; +pub const CSR_MHPMCOUNTER6H = 0xb86; +pub const CSR_MHPMCOUNTER7H = 0xb87; +pub const CSR_MHPMCOUNTER8H = 0xb88; +pub const CSR_MHPMCOUNTER9H = 0xb89; +pub const CSR_MHPMCOUNTER10H = 0xb8a; +pub const CSR_MHPMCOUNTER11H = 0xb8b; +pub const CSR_MHPMCOUNTER12H = 0xb8c; +pub const CSR_MHPMCOUNTER13H = 0xb8d; +pub const CSR_MHPMCOUNTER14H = 0xb8e; +pub const CSR_MHPMCOUNTER15H = 0xb8f; +pub const CSR_MHPMCOUNTER16H = 0xb90; +pub const CSR_MHPMCOUNTER17H = 0xb91; +pub const CSR_MHPMCOUNTER18H = 0xb92; +pub const CSR_MHPMCOUNTER19H = 0xb93; +pub const CSR_MHPMCOUNTER20H = 0xb94; +pub const CSR_MHPMCOUNTER21H = 0xb95; +pub const CSR_MHPMCOUNTER22H = 0xb96; +pub const CSR_MHPMCOUNTER23H = 0xb97; +pub const CSR_MHPMCOUNTER24H = 0xb98; +pub const CSR_MHPMCOUNTER25H = 0xb99; +pub const CSR_MHPMCOUNTER26H = 0xb9a; +pub const CSR_MHPMCOUNTER27H = 0xb9b; +pub const CSR_MHPMCOUNTER28H = 0xb9c; +pub const CSR_MHPMCOUNTER29H = 0xb9d; +pub const CSR_MHPMCOUNTER30H = 0xb9e; +pub const CSR_MHPMCOUNTER31H = 0xb9f; +pub const CSR_MTVT = 0x307; +pub const CSR_MNXTI = 0x345; +pub const CSR_MCOUNTINHIBIT = 0x320; +pub const CSR_MNVEC = 0x7C3; +pub const CSR_MTVT2 = 0x7EC; +pub const CSR_JALMNXTI = 0x7ED; +pub const CSR_PUSHMCAUSE = 0x7EE; +pub const CSR_PUSHMEPC = 0x7EF; +pub const CSR_PUSHMSUBM = 0x7EB; +pub const CSR_WFE = 0x810; +pub const CSR_SLEEPVALUE = 0x811; +pub const CSR_TXEVT = 0x812; +pub const CSR_MMISC_CTL = 0x7d0; +pub const CSR_MSUBM = 0x7c4; +pub const CAUSE_MISALIGNED_FETCH = 0x0; +pub const CAUSE_FAULT_FETCH = 0x1; +pub const CAUSE_ILLEGAL_INSTRUCTION = 0x2; +pub const CAUSE_BREAKPOINT = 0x3; +pub const CAUSE_MISALIGNED_LOAD = 0x4; +pub const CAUSE_FAULT_LOAD = 0x5; +pub const CAUSE_MISALIGNED_STORE = 0x6; +pub const CAUSE_FAULT_STORE = 0x7; +pub const CAUSE_USER_ECALL = 0x8; +pub const CAUSE_SUPERVISOR_ECALL = 0x9; +pub const CAUSE_HYPERVISOR_ECALL = 0xa; +pub const CAUSE_MACHINE_ECALL = 0xb; diff --git a/tests/blinky.zig b/tests/blinky.zig index bac49c8..4c3c2b1 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -8,12 +8,14 @@ const led_pin = if (micro.config.has_board) .@"STM32F3DISCOVERY" => micro.Pin("LD3"), .@"STM32F4DISCOVERY" => micro.Pin("LD5"), .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), + .@"Longan Nano" => micro.Pin("PA2"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) { .@"ATmega328p" => micro.Pin("PB5"), .@"NXP LPC1768" => micro.Pin("P1.18"), .@"STM32F103x8" => micro.Pin("PC13"), + .@"GD32VF103x8" => micro.Pin("PA2"), else => @compileError("unknown chip"), }; diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 83378a9..116bc44 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -18,10 +18,16 @@ const cfg = if (micro.config.has_board) .uart_idx = 2, .pins = .{ .tx = micro.Pin("PA2"), .rx = micro.Pin("PA3") }, }, + .@"Longan Nano" => .{ + .led_pin = micro.Pin("PA2"), + .uart_idx = 1, + .pins = .{ .tx = null, .rx = null }, + }, else => @compileError("unknown board"), } else switch (micro.config.chip_name) { .@"NXP LPC1768" => .{ .led_pin = micro.Pin("P1.18"), .uart_idx = 1, .pins = .{} }, + .@"GD32VF103x8" => .{ .led_pin = micro.Pin("PA2"), .uart_idx = 1, .pins = .{} }, else => @compileError("unknown chip"), }; From 0936dfb05c86ca47cc30914329046143c2657d24 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 27 Jul 2022 01:08:27 -0700 Subject: [PATCH 072/138] improve build api (#70) --- build.zig | 12 +++---- src/main.zig | 90 ++++++++++++++++++++++++++++------------------------ 2 files changed, 54 insertions(+), 48 deletions(-) diff --git a/build.zig b/build.zig index 0253d08..c751dea 100644 --- a/build.zig +++ b/build.zig @@ -46,7 +46,7 @@ pub fn build(b: *std.build.Builder) !void { if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue; if (!tst.on_riscv32) continue; - const exe = try microzig.addEmbeddedExecutable( + const exe = microzig.addEmbeddedExecutable( b, b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }), tst.source, @@ -54,14 +54,14 @@ pub fn build(b: *std.build.Builder) !void { .{}, ); - if (filter == null or exe.target.cpu_arch.? == filter.?) { - exe.setBuildMode(mode); - exe.install(); + if (filter == null or exe.inner.target.cpu_arch.? == filter.?) { + exe.inner.setBuildMode(mode); + exe.inner.install(); - test_step.dependOn(&exe.step); + test_step.dependOn(&exe.inner.step); const bin = b.addInstallRaw( - exe, + exe.inner, b.fmt("test-{s}-{s}.bin", .{ tst.name, cfg.name }), .{}, ); diff --git a/src/main.zig b/src/main.zig index af23dbf..90b0949 100644 --- a/src/main.zig +++ b/src/main.zig @@ -8,6 +8,8 @@ pub const Board = @import("modules/Board.zig"); pub const Chip = @import("modules/Chip.zig"); pub const Cpu = @import("modules/Cpu.zig"); +const LibExeObjStep = std.build.LibExeObjStep; + pub const Backing = union(enum) { board: Board, chip: Chip, @@ -27,20 +29,34 @@ fn root() []const u8 { } pub const BuildOptions = struct { - packages: ?[]const Pkg = null, - // a hal package is a package with ergonomic wrappers for registers for a // given mcu, it's only dependency can be microzig hal_package_path: ?std.build.FileSource = null, }; +pub const EmbeddedExecutable = struct { + inner: *LibExeObjStep, + app_packages: std.ArrayList(Pkg), + + pub fn addPackage(exe: *EmbeddedExecutable, pkg: Pkg) void { + exe.app_packages.append(pkg) catch @panic("failed to append"); + + for (exe.inner.packages.items) |*entry| { + if (std.mem.eql(u8, "app", entry.name)) { + entry.dependencies = exe.app_packages.items; + break; + } + } else @panic("app package not found"); + } +}; + pub fn addEmbeddedExecutable( builder: *std.build.Builder, name: []const u8, source: []const u8, backing: Backing, options: BuildOptions, -) !*std.build.LibExeObjStep { +) EmbeddedExecutable { const has_board = (backing == .board); const chip = switch (backing) { .chip => |c| c, @@ -70,11 +86,11 @@ pub fn addEmbeddedExecutable( const file_suffix = ".zig"; var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = try std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ file_prefix, std.fmt.fmtSliceHexLower(&hash), file_suffix, - }); + }) catch unreachable; break :blk builder.dupe(filename); }; @@ -86,24 +102,21 @@ pub fn addEmbeddedExecutable( for (chip.memory_regions) |region| { if (region.kind == .ram) break :blk region; - } else { - std.log.err("no ram memory region found for setting the end-of-stack address", .{}); - return error.NoRam; - } + } else @panic("no ram memory region found for setting the end-of-stack address"); }; std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; - var config_file = try std.fs.cwd().createFile(config_file_name, .{}); + var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; defer config_file.close(); var writer = config_file.writer(); - try writer.print("pub const has_board = {};\n", .{has_board}); + writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; if (has_board) - try writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}); + writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; - try writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}); - try writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}); - try writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}); + writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; + writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; } const config_pkg = Pkg{ @@ -123,44 +136,31 @@ pub fn addEmbeddedExecutable( .dependencies = &.{pkgs.microzig}, }; - const exe = builder.addExecutable(name, root_path ++ "core/microzig.zig"); + var exe = EmbeddedExecutable{ + .inner = builder.addExecutable(name, root_path ++ "core/microzig.zig"), + .app_packages = std.ArrayList(Pkg).init(builder.allocator), + }; // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) - exe.single_threaded = true; - exe.setTarget(chip.cpu.target); + exe.inner.single_threaded = true; + exe.inner.setTarget(chip.cpu.target); - const linkerscript = try LinkerScriptStep.create(builder, chip); - exe.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; + exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); // TODO: // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.bundle_compiler_rt = (exe.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now - - const app_pkg = blk: { - var app_pkgs = std.ArrayList(Pkg).init(builder.allocator); - - try app_pkgs.append(pkgs.microzig); // proxy package - if (options.packages) |packages| - try app_pkgs.appendSlice(packages); - - break :blk std.build.Pkg{ - .name = "app", - .source = .{ .path = source }, - .dependencies = app_pkgs.items, - }; - }; + exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now // these packages will be re-exported from core/microzig.zig + exe.inner.addPackage(config_pkg); + exe.inner.addPackage(chip_pkg); + exe.inner.addPackage(cpu_pkg); - exe.addPackage(app_pkg); - exe.addPackage(config_pkg); - exe.addPackage(chip_pkg); - exe.addPackage(cpu_pkg); - - exe.addPackage(.{ + exe.inner.addPackage(.{ .name = "hal", .source = if (options.hal_package_path) |hal_package_path| hal_package_path @@ -170,7 +170,7 @@ pub fn addEmbeddedExecutable( switch (backing) { .board => |board| { - exe.addPackage(std.build.Pkg{ + exe.inner.addPackage(std.build.Pkg{ .name = "board", .source = .{ .path = board.path }, .dependencies = &.{pkgs.microzig}, @@ -179,6 +179,12 @@ pub fn addEmbeddedExecutable( else => {}, } + exe.inner.addPackage(.{ + .name = "app", + .source = .{ .path = source }, + }); + exe.addPackage(pkgs.microzig); + return exe; } From a2dd362ce7d1239b120e0aa6210a7dbf14902d7e Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 27 Jul 2022 01:58:46 -0700 Subject: [PATCH 073/138] Asciidoc (#71) use asciidoc for the automatic toc --- README.md => README.adoc | 268 +++++++++++++++++++-------------------- 1 file changed, 133 insertions(+), 135 deletions(-) rename README.md => README.adoc (60%) diff --git a/README.md b/README.adoc similarity index 60% rename from README.md rename to README.adoc index 0aaf896..163b0d8 100644 --- a/README.md +++ b/README.adoc @@ -1,135 +1,133 @@ -![microzig logo](design/logo-text-auto.svg) - -[![discord](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](https://discord.gg/ShUWykk38X) - -## NOTE: in development - -APIs will likely break in the future - -# Table of Contents - -- [Contributing](#contributing) -- [Introduction](#introduction) -- [How to](#how-to) - - [Embedded project with "supported" chip/board](#embedded-project-with-supported-chipboard) - - [Embedded project with "unsupported" chip](#embedded-project-with-unsupported-chip) - - [Interrupts](#interrupts) - - - -## Contributing - -Please see the [project page](https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1), its used as a place to brainstorm and organize work in ZEG. -There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. - -## Introduction - -This repo contains the infrastructure for getting started in an embedded Zig project, as well as some code to interact with some chips/boards. Specifically it offers: - -- a single easy-to-use builder function that: - - generates your linker script - - sets up packages and start code -- generalized interfaces for common devices, such as UART. -- device drivers for interacting with external hardware -- an uncomplicated method to define [interrupts](#interrupts) - -## How to - -Here's a number of things you might be interested in doing, and how to achieve them with microzig and other ZEG tools. - -### Embedded project with "supported" chip/board - -Start with an empty Zig project by running `zig init-exe`, and add microzig as a git submodule (or your choice of package manager). -Then in your `build.zig`: - -```zig -const std = @import("std"); -const microzig = @import("path/to/microzig/src/main.zig"); - -pub fn build(b: *std.build.Builder) !void { - const backing = .{ - .board = microzig.boards.arduino_nano, - - // if you don't have one of the boards, but do have one of the - // "supported" chips: - // .chip = microzig.chips.atmega328p, - }; - - const exe = try microzig.addEmbeddedExecutable( - b, - "my-executable", - "src/main.zig", - backing, - .{ - // optional slice of packages that can be imported into your app: - // .packages = &my_packages, - }, - ); - exe.setBuildMode(.ReleaseSmall); - exe.install(); -} -``` - -`zig build` and now you have an executable for an Arduino Nano. -In your application you can import `microzig` in order to interact with the hardware: - -```zig -const microzig = @import("microzig"); - -// `microzig.chip.registers`: access to register definitions - -pub fn main() !void { - // your program here -} -``` - -### Embedded project with "unsupported" chip - -If you have a board/chip that isn't defined in microzig, you can set it up yourself! -You need to have: - -- SVD or ATDF file defining registers -- flash and ram address and sizes - -First use [regz](https://github.com/ZigEmbeddedGroup/regz) to generate the register definitions for your chip and save them to a file. -Then your `build.zig` is going to be the same, but you'll define the chip yourself: - -```zig -const nrf52832 = Chip{ - .name = "nRF52832", - .path = "path/to/generated/file.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, -}; - -const backing = .{ - .chip = nrf52832, -}; -``` - -NOTE: `regz` is also still in development, and while it tends to generate code well, it's possible that there will be errors in the generated code! -Please create an issue if you run into anything fishy. - -### Interrupts - -The current supported architectures for interrupt vector generation are ARM and AVR. -To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace: - -```zig - -pub const interrupts = struct { - pub fn PCINT0() void { - // interrupt handling code - } -}; - -pub fn main() !void { - // my application -} -``` - -We're using compile-time checks along with the generated code to determine the list of interrupts. -If a function is defined whose name is not in this list, you'll get a compiler error with the list of interrupts/valid names. +:imagesdir: design +:toc: macro + +image::logo-text-auto.svg[] + +image::https://img.shields.io/discord/824493524413710336.svg?logo=discord[link=https://discord.gg/ShUWykk38X] + +[NOTE] +This is in development, breaks in the API are bound to happen + +toc::[] + +== Contributing + +Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], its used as a place to brainstorm and organize work in ZEG. +There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. + +== Introduction + +This repo contains the infrastructure for getting started in an embedded Zig project, as well as some code to interact with some chips/boards. +Specifically it offers: + +* a single easy-to-use builder function that: +** generates your linker script +** sets up packages and start code +* generalized interfaces for common devices, such as UART. +* device drivers for interacting with external hardware +* an uncomplicated method to define xref:interrupts[interrupts] + +== How to + +Here's a number of things you might be interested in doing, and how to achieve them with microzig and other ZEG tools. + +=== Embedded project with "supported" chip/board + +Start with an empty Zig project by running `zig init-exe`, and add microzig as a git submodule (or your choice of package manager). +Then in your `build.zig`: + +[source,zig] +---- +const std = @import("std"); +const microzig = @import("path/to/microzig/src/main.zig"); + +pub fn build(b: *std.build.Builder) !void { + const backing = .{ + .board = microzig.boards.arduino_nano, + + // if you don't have one of the boards, but do have one of the + // "supported" chips: + // .chip = microzig.chips.atmega328p, + }; + + const exe = try microzig.addEmbeddedExecutable( + b, + "my-executable", + "src/main.zig", + backing, + .{ + // optional slice of packages that can be imported into your app: + // .packages = &my_packages, + }, + ); + exe.setBuildMode(.ReleaseSmall); + exe.install(); +} +---- + +`zig build` and now you have an executable for an Arduino Nano. +In your application you can import `microzig` in order to interact with the hardware: + +[source,zig] +---- +const microzig = @import("microzig"); + +// `microzig.chip.registers`: access to register definitions + +pub fn main() !void { + // your program here +} +---- + +=== Embedded project with "unsupported" chip + +If you have a board/chip that isn't defined in microzig, you can set it up yourself! +You need to have: + +* SVD or ATDF file defining registers +* flash and ram address and sizes + +First use https://github.com/ZigEmbeddedGroup/regz[regz] to generate the register definitions for your chip and save them to a file. +Then your `build.zig` is going to be the same, but you'll define the chip yourself: + +[source,zig] +---- +const nrf52832 = Chip{ + .name = "nRF52832", + .path = "path/to/generated/file.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, + }, +}; + +const backing = .{ + .chip = nrf52832, +}; +---- + +[NOTE] +`regz` is also still in development, and while it tends to generate code well, it's possible that there will be errors in the generated code! +Please create an issue if you run into anything fishy. + +=== Interrupts + +The current supported architectures for interrupt vector generation are ARM and AVR. +To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace: + +[source,zig] +---- +pub const interrupts = struct { + pub fn PCINT0() void { + // interrupt handling code + } +}; + +pub fn main() !void { + // my application +} +---- + +We're using compile-time checks along with the generated code to determine the list of interrupts. +If a function is defined whose name is not in this list, you'll get a compiler error with the list of interrupts/valid names. From b8d92b25399c9b877afd5ddb1725f748bf5c0272 Mon Sep 17 00:00:00 2001 From: Nicolas Goy Date: Tue, 2 Aug 2022 04:02:01 +0200 Subject: [PATCH 074/138] Make the microzig package public to allow it to be passed as dependency. (#73) --- src/main.zig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main.zig b/src/main.zig index 90b0949..cd26858 100644 --- a/src/main.zig +++ b/src/main.zig @@ -188,13 +188,13 @@ pub fn addEmbeddedExecutable( return exe; } -const pkgs = struct { +pub const pkgs = struct { const mmio = std.build.Pkg{ .name = "microzig-mmio", .source = .{ .path = root_path ++ "core/mmio.zig" }, }; - const microzig = std.build.Pkg{ + pub const microzig = std.build.Pkg{ .name = "microzig", .source = .{ .path = root_path ++ "core/import-package.zig" }, }; From e1244177fa8e561c0f652af42504a8e6f62aae63 Mon Sep 17 00:00:00 2001 From: Nicolas Goy Date: Wed, 10 Aug 2022 08:02:08 +0200 Subject: [PATCH 075/138] Add comment about microzig.config (#74) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Add comment about microzig.config When writing a HAL, having the chip name is very important to switch features and select pinout. Mention the config in the README in a concise manner. Co-authored-by: Felix Queißner --- README.adoc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.adoc b/README.adoc index 163b0d8..2bf1f5c 100644 --- a/README.adoc +++ b/README.adoc @@ -73,6 +73,11 @@ In your application you can import `microzig` in order to interact with the hard const microzig = @import("microzig"); // `microzig.chip.registers`: access to register definitions +// `microzig.config`: comptime access to configuration +// - chip_name: name of the chip +// - has_board: true if board is configured +// - board_name: name of the board is has_board is true +// - cpu_name: name of the CPU pub fn main() !void { // your program here From 68314b8f7ec7dbdfa2c63c1edcf2cd12dca28293 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 24 Aug 2022 23:17:08 -0700 Subject: [PATCH 076/138] use stage1 until stage3 is ready (#75) --- src/main.zig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main.zig b/src/main.zig index cd26858..1e8d285 100644 --- a/src/main.zig +++ b/src/main.zig @@ -141,6 +141,8 @@ pub fn addEmbeddedExecutable( .app_packages = std.ArrayList(Pkg).init(builder.allocator), }; + exe.inner.use_stage1 = true; + // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) exe.inner.single_threaded = true; From 20deb2cc3e1a3e2cd724881c24017074f8541953 Mon Sep 17 00:00:00 2001 From: Vesim Date: Thu, 1 Sep 2022 15:53:49 +0200 Subject: [PATCH 077/138] Allow to specify VectorTable in app and hal. (#76) --- src/modules/cpus.zig | 11 +++++++++++ src/modules/cpus/cortex-m/cortex-m.zig | 18 +++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index f8f5574..3cee7c7 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -18,6 +18,17 @@ pub const avr5 = Cpu{ }, }; +pub const cortex_m0 = Cpu{ + .name = "ARM Cortex-M0", + .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .none, + }, +}; + pub const cortex_m0plus = Cpu{ .name = "ARM Cortex-M0+", .path = root_path ++ "cpus/cortex-m/cortex-m.zig", diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m/cortex-m.zig index c2c6bc7..2c15dd6 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m/cortex-m.zig @@ -82,11 +82,16 @@ fn isValidField(field_name: []const u8) bool { !std.mem.eql(u8, field_name, "reset"); } -const VectorTable = microzig.chip.VectorTable; +const VectorTable = if (@hasDecl(microzig.app, "VectorTable")) + microzig.app.VectorTable +else if (@hasDecl(microzig.hal, "VectorTable")) + microzig.hal.VectorTable +else + microzig.chip.VectorTable; // will be imported by microzig.zig to allow system startup. pub var vector_table: VectorTable = blk: { - var tmp: microzig.chip.VectorTable = .{ + var tmp: VectorTable = .{ .initial_stack_pointer = microzig.config.end_of_stack, .Reset = .{ .C = microzig.cpu.startup_logic._start }, }; @@ -117,9 +122,16 @@ pub var vector_table: VectorTable = blk: { break :blk tmp; }; +const InterruptVector = if (@hasDecl(microzig.app, "InterruptVector")) + microzig.app.InterruptVector +else if (@hasDecl(microzig.hal, "InterruptVector")) + microzig.hal.InterruptVector +else + microzig.chip.InterruptVector; + fn createInterruptVector( comptime function: anytype, -) microzig.chip.InterruptVector { +) InterruptVector { const calling_convention = @typeInfo(@TypeOf(function)).Fn.calling_convention; return switch (calling_convention) { .C => .{ .C = function }, From 3617b8b25f69377b9e64ab7a02029a7489870689 Mon Sep 17 00:00:00 2001 From: David Sugar Date: Wed, 14 Sep 2022 19:56:31 +0200 Subject: [PATCH 078/138] Added some function wrappers to EmbeddedExecutable that expose commonly used functionalities of LibExeObjStep (#77) --- src/main.zig | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/main.zig b/src/main.zig index 1e8d285..0f65b62 100644 --- a/src/main.zig +++ b/src/main.zig @@ -48,6 +48,37 @@ pub const EmbeddedExecutable = struct { } } else @panic("app package not found"); } + + pub fn addPackagePath(exe: *EmbeddedExecutable, name: []const u8, pkg_index_path: []const u8) void { + exe.addPackage(Pkg{ + .name = exe.inner.builder.allocator.dupe(u8, name) catch unreachable, + .source = .{ .path = exe.inner.builder.allocator.dupe(u8, pkg_index_path) catch unreachable }, + }); + } + + pub fn setBuildMode(exe: *EmbeddedExecutable, mode: std.builtin.Mode) void { + exe.inner.setBuildMode(mode); + } + + pub fn install(exe: *EmbeddedExecutable) void { + exe.inner.install(); + } + + pub fn installRaw(exe: *EmbeddedExecutable, dest_filename: []const u8, options: std.build.InstallRawStep.CreateOptions) *std.build.InstallRawStep { + return exe.inner.installRaw(dest_filename, options); + } + + pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + exe.addIncludePath(path); + } + + pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + return exe.inner.addSystemIncludePath(path); + } + + pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { + exe.inner.addCSourceFile(file, flags); + } }; pub fn addEmbeddedExecutable( From 4159581b4848bfb8bbdf91dabdebd15ecd503427 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 16 Sep 2022 00:26:08 -0700 Subject: [PATCH 079/138] remove pointless discard (#80) --- src/modules/chips/stm32f303/stm32f303.zig | 1 - src/modules/chips/stm32f407/stm32f407.zig | 1 - src/modules/chips/stm32f429/stm32f429.zig | 1 - 3 files changed, 3 deletions(-) diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index e9cc706..bb92d41 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -103,7 +103,6 @@ pub const gpio = struct { } pub fn write(comptime pin: type, state: micro.gpio.State) void { - _ = pin; switch (state) { .low => setRegField(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1), .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig index c07582c..7c3566c 100644 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ b/src/modules/chips/stm32f407/stm32f407.zig @@ -126,7 +126,6 @@ pub const gpio = struct { } pub fn write(comptime pin: type, state: micro.gpio.State) void { - _ = pin; switch (state) { .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), diff --git a/src/modules/chips/stm32f429/stm32f429.zig b/src/modules/chips/stm32f429/stm32f429.zig index d40d92b..3fa26c1 100644 --- a/src/modules/chips/stm32f429/stm32f429.zig +++ b/src/modules/chips/stm32f429/stm32f429.zig @@ -86,7 +86,6 @@ pub const gpio = struct { } pub fn write(comptime pin: type, state: micro.gpio.State) void { - _ = pin; switch (state) { .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), From bebf6cf92d729981b5394bc7e9168492189c5bcb Mon Sep 17 00:00:00 2001 From: Nicolas Goy Date: Fri, 23 Sep 2022 09:06:55 +0200 Subject: [PATCH 080/138] Add executable method (addOptions, addObjectFile) and fix recursive call in addIncludePath (#79) --- src/main.zig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/main.zig b/src/main.zig index 0f65b62..c4fa6e5 100644 --- a/src/main.zig +++ b/src/main.zig @@ -69,7 +69,7 @@ pub const EmbeddedExecutable = struct { } pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { - exe.addIncludePath(path); + exe.inner.addIncludePath(path); } pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { @@ -79,6 +79,15 @@ pub const EmbeddedExecutable = struct { pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { exe.inner.addCSourceFile(file, flags); } + + pub fn addOptions(exe: *EmbeddedExecutable, package_name: []const u8, options: *std.build.OptionsStep) void { + exe.inner.addOptions(package_name, options); + exe.addPackage(.{ .name = package_name, .source = options.getSource() }); + } + + pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { + exe.inner.addObjectFile(source_file); + } }; pub fn addEmbeddedExecutable( From 4cc682cece7b4217261fec59d9c199a83ff8f90c Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 23 Sep 2022 00:10:27 -0700 Subject: [PATCH 081/138] Revert "Add executable method (addOptions, addObjectFile) and fix recursive call in addIncludePath (#79)" (#81) This reverts commit bebf6cf92d729981b5394bc7e9168492189c5bcb. --- src/main.zig | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/src/main.zig b/src/main.zig index c4fa6e5..0f65b62 100644 --- a/src/main.zig +++ b/src/main.zig @@ -69,7 +69,7 @@ pub const EmbeddedExecutable = struct { } pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { - exe.inner.addIncludePath(path); + exe.addIncludePath(path); } pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { @@ -79,15 +79,6 @@ pub const EmbeddedExecutable = struct { pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { exe.inner.addCSourceFile(file, flags); } - - pub fn addOptions(exe: *EmbeddedExecutable, package_name: []const u8, options: *std.build.OptionsStep) void { - exe.inner.addOptions(package_name, options); - exe.addPackage(.{ .name = package_name, .source = options.getSource() }); - } - - pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { - exe.inner.addObjectFile(source_file); - } }; pub fn addEmbeddedExecutable( From e280cca9b63021b8f3289b9172d7fc7a78edd2f0 Mon Sep 17 00:00:00 2001 From: David Sugar Date: Fri, 23 Sep 2022 09:12:08 +0200 Subject: [PATCH 082/138] ATSAME51J20A chip (#78) * Added some function wrappers to EmbeddedExecutable that expose commonly used functionalities of LibExeObjStep * atsame51j20a chip added. GPIO support. UART support over SERCOM5. * added support for true random numbers to atsame51j20a chip --- src/modules/chips.zig | 11 + .../chips/atsame51j20a/ATSAME51J20A.svd | 45092 ++++++++++++++++ .../chips/atsame51j20a/atsame51j20a.zig | 333 + src/modules/chips/atsame51j20a/registers.zig | 25436 +++++++++ 4 files changed, 70872 insertions(+) create mode 100644 src/modules/chips/atsame51j20a/ATSAME51J20A.svd create mode 100644 src/modules/chips/atsame51j20a/atsame51j20a.zig create mode 100644 src/modules/chips/atsame51j20a/registers.zig diff --git a/src/modules/chips.zig b/src/modules/chips.zig index 1794e12..4419d2d 100644 --- a/src/modules/chips.zig +++ b/src/modules/chips.zig @@ -103,3 +103,14 @@ pub const nrf52832 = Chip{ MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, }, }; + +pub const atsame51j20a = Chip{ + .name = "ATSAME51J20A", + .path = root_path ++ "chips/atsame51j20a/atsame51j20a.zig", + .cpu = cpus.cortex_m4, + .memory_regions = &.{ + // SAM D5x/E5x Family Data Sheet page 53 + MemoryRegion{ .offset = 0x00000000, .length = 1024 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 256 * 1024, .kind = .ram }, + }, +}; \ No newline at end of file diff --git a/src/modules/chips/atsame51j20a/ATSAME51J20A.svd b/src/modules/chips/atsame51j20a/ATSAME51J20A.svd new file mode 100644 index 0000000..10353bd --- /dev/null +++ b/src/modules/chips/atsame51j20a/ATSAME51J20A.svd @@ -0,0 +1,45092 @@ + + + + Microchip Technology + MCHP + ATSAME51J20A + SAME51 + 0 + Microchip ATSAME51J20A Microcontroller + + CM4 + r0p1 + selectable + true + true + 3 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U25011.0.0 + Analog Comparators + AC + AC_ + 0x42002000 + + 0 + 0x26 + registers + + + AC + 122 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 2 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 2 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + HYST + Hysteresis Level + 20 + 2 + + HYSTSelect + + HYST50 + 50mV + 0 + + + HYST100 + 100mV + 1 + + + HYST150 + 150mV + 2 + + + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + + + CALIB + Calibration + 0x24 + 16 + 0x0101 + + + BIAS0 + COMP0/1 Bias Scaling + 0 + 2 + + + + + + + ADC0 + U25001.0.0 + Analog Digital Converter + ADC + ADC_ + 0x43001C00 + + 0 + 0x4A + registers + + + ADC0_OTHER + 118 + + + ADC0_RESRDY + 119 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + DUALSEL + Dual Mode Trigger Selection + 3 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0 + + + INTERLEAVE + START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 + 1 + + + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0 + + + DIV4 + Peripheral clock divided by 4 + 1 + + + DIV8 + Peripheral clock divided by 8 + 2 + + + DIV16 + Peripheral clock divided by 16 + 3 + + + DIV32 + Peripheral clock divided by 32 + 4 + + + DIV64 + Peripheral clock divided by 64 + 5 + + + DIV128 + Peripheral clock divided by 128 + 6 + + + DIV256 + Peripheral clock divided by 256 + 7 + + + + + R2R + Rail to Rail Operation Enable + 15 + 1 + + + + + EVCTRL + Event Control + 0x2 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x3 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + INPUTCTRL + Input Control + 0x4 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + AIN12 + ADC AIN12 Pin + 0xC + + + AIN13 + ADC AIN13 Pin + 0xD + + + AIN14 + ADC AIN14 Pin + 0xE + + + AIN15 + ADC AIN15 Pin + 0xF + + + AIN16 + ADC AIN16 Pin + 0x10 + + + AIN17 + ADC AIN17 Pin + 0x11 + + + AIN18 + ADC AIN18 Pin + 0x12 + + + AIN19 + ADC AIN19 Pin + 0x13 + + + AIN20 + ADC AIN20 Pin + 0x14 + + + AIN21 + ADC AIN21 Pin + 0x15 + + + AIN22 + ADC AIN22 Pin + 0x16 + + + AIN23 + ADC AIN23 Pin + 0x17 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x18 + + + SCALEDVBAT + 1/4 Scaled VBAT Supply + 0x19 + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1A + + + BANDGAP + Bandgap Voltage + 0x1B + + + PTAT + Temperature Sensor TSENSP + 0x1C + + + CTAT + Temperature Sensor TSENSC + 0x1D + + + DAC + DAC Output + 0x1E + + + PTC + PTC output (only on ADC0) + 0x1F + + + + + DIFFMODE + Differential Mode + 7 + 1 + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + + + DSEQSTOP + Stop DMA Sequencing + 15 + 1 + + + + + CTRLB + Control B + 0x6 + 16 + 0x0000 + + + LEFTADJ + Left-Adjusted Result + 0 + 1 + + + FREERUN + Free Running Mode + 1 + 1 + + + CORREN + Digital Correction Logic Enable + 2 + 1 + + + RESSEL + Conversion Result Resolution + 3 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + For averaging mode output + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + WINSS + Window Single Sample + 11 + 1 + + + + + REFCTRL + Reference Control + 0x8 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/2 VDDANA + 0x2 + + + INTVCC1 + VDDANA + 0x3 + + + AREFA + External Reference A + 0x4 + + + AREFB + External Reference B + 0x5 + + + AREFC + External Reference C (only on ADC1) + 0x6 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0xA + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xB + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0xE + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x10 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x12 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x14 + 8 + 0x00 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x2C + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2D + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2E + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + STATUS + Status + 0x2F + 8 + read-only + 0x00 + + + ADCBUSY + ADC Busy Status + 0 + 1 + + + WCC + Window Comparator Counter + 2 + 6 + + + + + SYNCBUSY + Synchronization Busy + 0x30 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + Input Control Synchronization Busy + 2 + 1 + + + CTRLB + Control B Synchronization Busy + 3 + 1 + + + REFCTRL + Reference Control Synchronization Busy + 4 + 1 + + + AVGCTRL + Average Control Synchronization Busy + 5 + 1 + + + SAMPCTRL + Sampling Time Control Synchronization Busy + 6 + 1 + + + WINLT + Window Monitor Lower Threshold Synchronization Busy + 7 + 1 + + + WINUT + Window Monitor Upper Threshold Synchronization Busy + 8 + 1 + + + GAINCORR + Gain Correction Synchronization Busy + 9 + 1 + + + OFFSETCORR + Offset Correction Synchronization Busy + 10 + 1 + + + SWTRIG + Software Trigger Synchronization Busy + 11 + 1 + + + + + DSEQDATA + DMA Sequencial Data + 0x34 + 32 + write-only + 0x00000000 + + + DATA + DMA Sequential Data + 0 + 32 + + + + + DSEQCTRL + DMA Sequential Control + 0x38 + 32 + 0x00000000 + + + INPUTCTRL + Input Control + 0 + 1 + + + CTRLB + Control B + 1 + 1 + + + REFCTRL + Reference Control + 2 + 1 + + + AVGCTRL + Average Control + 3 + 1 + + + SAMPCTRL + Sampling Time Control + 4 + 1 + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + + + GAINCORR + Gain Correction + 7 + 1 + + + OFFSETCORR + Offset Correction + 8 + 1 + + + AUTOSTART + ADC Auto-Start Conversion + 31 + 1 + + + + + DSEQSTAT + DMA Sequencial Status + 0x3C + 32 + read-only + 0x00000000 + + + INPUTCTRL + Input Control + 0 + 1 + + + CTRLB + Control B + 1 + 1 + + + REFCTRL + Reference Control + 2 + 1 + + + AVGCTRL + Average Control + 3 + 1 + + + SAMPCTRL + Sampling Time Control + 4 + 1 + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + + + GAINCORR + Gain Correction + 7 + 1 + + + OFFSETCORR + Offset Correction + 8 + 1 + + + BUSY + DMA Sequencing Busy + 31 + 1 + + + + + RESULT + Result Conversion Value + 0x40 + 16 + read-only + 0x0000 + + + RESULT + Result Conversion Value + 0 + 16 + + + + + RESS + Last Sample Result + 0x44 + 16 + read-only + 0x0000 + + + RESS + Last ADC conversion result + 0 + 16 + + + + + CALIB + Calibration + 0x48 + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASR2R + Bias R2R Ampli scaling + 4 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + ADC1 + 0x43002000 + + ADC1_OTHER + 120 + + + ADC1_RESRDY + 121 + + + + AES + U22382.2.0 + Advanced Encryption Standard + AES + AES_ + 0x42002400 + + 0 + 0x88 + registers + + + AES + 130 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + AESMODE + AES Modes of operation + 2 + 3 + + AESMODESelect + + ECB + Electronic code book mode + 0x0 + + + CBC + Cipher block chaining mode + 0x1 + + + OFB + Output feedback mode + 0x2 + + + CFB + Cipher feedback mode + 0x3 + + + COUNTER + Counter mode + 0x4 + + + CCM + CCM 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10-beats burst length + 9 + + + 11BEAT + 11-beats burst length + 10 + + + 12BEAT + 12-beats burst length + 11 + + + 13BEAT + 13-beats burst length + 12 + + + 14BEAT + 14-beats burst length + 13 + + + 15BEAT + 15-beats burst length + 14 + + + 16BEAT + 16-beats burst length + 15 + + + + + THRESHOLD + FIFO Threshold + 28 + 2 + + THRESHOLDSelect + + 1BEAT + Destination write starts after each beat source address read + 0 + + + 2BEATS + Destination write starts after 2-beats source address read + 1 + + + 4BEATS + Destination write starts after 4-beats source address read + 2 + + + 8BEATS + Destination write starts after 8-beats source address read + 3 + + + + + + + CHCTRLB + Channel n Control B + 0x4 + 8 + 0x00 + + + CMD + Software Command + 0 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHPRILVL + Channel n Priority Level + 0x5 + 8 + 0x00 + + + PRILVL + Channel Priority Level + 0 + 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URAD + Undefined Register Access Detection Interrupt Mask + 24 + 1 + + + + + ISR + Interrupt Status + 0x1C + 32 + read-only + 0x00000000 + + + RHC + Region Hash Completed + 0 + 4 + + + RDM + Region Digest Mismatch + 4 + 4 + + + RBE + Region Bus Error + 8 + 4 + + + RWC + Region Wrap Condition Detected + 12 + 4 + + + REC + Region End bit Condition Detected + 16 + 4 + + + RSU + Region Status Updated Detected + 20 + 4 + + + URAD + Undefined Register Access Detection Status + 24 + 1 + + + + + UASR + Undefined Access Status + 0x20 + 32 + read-only + 0x00000000 + + + URAT + Undefined Register Access Trace + 0 + 3 + + URATSelect + + UNSPEC_STRUCT_MEMBER + Unspecified structure member set to one detected when the descriptor is loaded + 0x0 + + + CFG_MODIFIED + CFG modified during active monitoring + 0x1 + + + DSCR_MODIFIED + DSCR modified during active monitoring + 0x2 + + + HASH_MODIFIED + HASH modified during active monitoring + 0x3 + + + READ_ACCESS + Write-only register read access + 0x4 + + + + + + + DSCR + Region Descriptor Area Start Address + 0x30 + 32 + 0x00000000 + + + DASA + Descriptor Area Start Address + 6 + 26 + + + + + HASH + Region Hash Area Start Address + 0x34 + 32 + 0x00000000 + + + HASA + Hash Area Start Address + 7 + 25 + + + + + 8 + 4 + UIHVAL[%s] + User Initial Hash Value n + 0x38 + 32 + write-only + 0x00000000 + + + VAL + Initial Hash Value + 0 + 32 + + + + + + + I2S + U22242.0.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x43002800 + + 0 + 0x38 + registers + + + I2S + 128 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + TXEN + Tx Serializer Enable + 4 + 1 + + + RXEN + Rx Serializer Enable + 5 + 1 + + + + + 2 + 4 + CLKCTRL[%s] + Clock Unit n Control + 0x4 + 32 + 0x00000000 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 9 + 1 + + + FSOUTINV + Frame Sync Output Invert + 10 + 1 + + + SCKSEL + Serial Clock Select + 11 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + SCKOUTINV + Serial Clock Output Invert + 12 + 1 + + + MCKSEL + Master Clock Select + 13 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 14 + 1 + + + MCKOUTINV + Master Clock Output Invert + 15 + 1 + + + MCKDIV + Master Clock Division Factor + 16 + 6 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 6 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + 0x0000 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + 0x0000 + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + TXEN + Tx Serializer Enable Synchronization Status + 4 + 1 + + + RXEN + Rx Serializer Enable Synchronization Status + 5 + 1 + + + TXDATA + Tx Data Synchronization Status + 8 + 1 + + + RXDATA + Rx Data Synchronization Status + 9 + 1 + + + + + TXCTRL + Tx Serializer Control + 0x20 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + TX + Transmit + 0x1 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + + + RXCTRL + Rx Serializer Control + 0x24 + 32 + 0x00000000 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + TXDATA + Tx Data + 0x30 + 32 + write-only + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + RXDATA + Rx Data + 0x34 + 32 + read-only + 0x00000000 + + + DATA + Sample Data + 0 + 32 + + + + + + + MCLK + U24081.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x24 + registers + + + MCLK + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + HSDIV + HS Clock Division + 0x4 + 8 + read-only + 0x01 + + + DIV + CPU Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x01 + + + + + + + CPUDIV + CPU Clock Division + 0x5 + 8 + 0x01 + + + DIV + Low-Power Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00FFFFFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + HPB3_ + HPB3 AHB Clock Mask + 3 + 1 + + + DSU_ + DSU AHB Clock Mask + 4 + 1 + + + HMATRIX_ + HMATRIX AHB Clock Mask + 5 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 6 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 7 + 1 + + + CMCC_ + CMCC AHB Clock Mask + 8 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 9 + 1 + + + USB_ + USB AHB Clock Mask + 10 + 1 + + + BKUPRAM_ + BKUPRAM AHB Clock Mask + 11 + 1 + + + PAC_ + PAC AHB Clock Mask + 12 + 1 + + + QSPI_ + QSPI AHB Clock Mask + 13 + 1 + + + SDHC0_ + SDHC0 AHB Clock Mask + 15 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 17 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 18 + 1 + + + ICM_ + ICM AHB Clock Mask + 19 + 1 + + + PUKCC_ + PUKCC AHB Clock Mask + 20 + 1 + + + QSPI_2X_ + QSPI_2X AHB Clock Mask + 21 + 1 + + + NVMCTRL_SMEEPROM_ + NVMCTRL_SMEEPROM AHB Clock Mask + 22 + 1 + + + NVMCTRL_CACHE_ + NVMCTRL_CACHE AHB Clock Mask + 23 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x000007FF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 13 + 1 + + + TC0_ + TC0 APB Clock Enable + 14 + 1 + + + TC1_ + TC1 APB Clock Enable + 15 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00018056 + + + USB_ + USB APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 4 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 10 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 11 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 12 + 1 + + + TC2_ + TC2 APB Clock Enable + 13 + 1 + + + TC3_ + TC3 APB Clock Enable + 14 + 1 + + + RAMECC_ + RAMECC APB Clock Enable + 16 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00002000 + + + TCC2_ + TCC2 APB Clock Enable + 3 + 1 + + + TCC3_ + TCC3 APB Clock Enable + 4 + 1 + + + TC4_ + TC4 APB Clock Enable + 5 + 1 + + + TC5_ + TC5 APB Clock Enable + 6 + 1 + + + PDEC_ + PDEC APB Clock Enable + 7 + 1 + + + AC_ + AC APB Clock Enable + 8 + 1 + + + AES_ + AES APB Clock Enable + 9 + 1 + + + TRNG_ + TRNG APB Clock Enable + 10 + 1 + + + ICM_ + ICM APB Clock Enable + 11 + 1 + + + QSPI_ + QSPI APB Clock Enable + 13 + 1 + + + CCL_ + CCL APB Clock Enable + 14 + 1 + + + + + APBDMASK + APBD Mask + 0x20 + 32 + 0x00000000 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 1 + 1 + + + TCC4_ + TCC4 APB Clock Enable + 4 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 7 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 8 + 1 + + + DAC_ + DAC APB Clock Enable + 9 + 1 + + + I2S_ + I2S APB Clock Enable + 10 + 1 + + + PCC_ + PCC APB Clock Enable + 11 + 1 + + + + + + + NVMCTRL + U24091.0.0 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL_0 + 29 + + + NVMCTRL_1 + 30 + + + + CTRLA + Control A + 0x0 + 16 + 0x0004 + + + AUTOWS + Auto Wait State Enable + 2 + 1 + + + SUSPEN + Suspend Enable + 3 + 1 + + + WMODE + Write Mode + 4 + 2 + + WMODESelect + + MAN + Manual Write + 0 + + + ADW + Automatic Double Word Write + 1 + + + AQW + Automatic Quad Word + 2 + + + AP + Automatic Page Write + 3 + + + + + PRM + Power Reduction Mode during Sleep + 6 + 2 + + PRMSelect + + SEMIAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 0 + + + FULLAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. + 1 + + + MANUAL + NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 3 + + + + + RWS + NVM Read Wait States + 8 + 4 + + + AHBNS0 + Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated + 12 + 1 + + + AHBNS1 + Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated + 13 + 1 + + + CACHEDIS0 + AHB0 Cache Disable + 14 + 1 + + + CACHEDIS1 + AHB1 Cache Disable + 15 + 1 + + + + + CTRLB + Control B + 0x4 + 16 + write-only + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + EP + Erase Page - Only supported in the USER and AUX pages. + 0x0 + + + EB + Erase Block - Erases the block addressed by the ADDR register, not supported in the user page + 0x1 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page + 0x3 + + + WQW + Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. + 0x4 + + + SWRST + Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers + 0x10 + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x11 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x12 + + + SPRM + Sets the power reduction mode. + 0x13 + + + CPRM + Clears the power reduction mode. + 0x14 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x15 + + + SSB + Set Security Bit + 0x16 + + + BKSWRST + Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK + 0x17 + + + CELCK + Chip Erase Lock - DSU.CE command is not available + 0x18 + + + CEULCK + Chip Erase Unlock - DSU.CE command is available + 0x19 + + + SBPDIS + Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence + 0x1A + + + CBPDIS + Clears STATUS.BPDIS, Boot loader protection is not discarded + 0x1B + + + ASEES0 + Activate SmartEEPROM Sector 0, deactivate Sector 1 + 0x30 + + + ASEES1 + Activate SmartEEPROM Sector 1, deactivate Sector 0 + 0x31 + + + SEERALOC + Starts SmartEEPROM sector reallocation algorithm + 0x32 + + + SEEFLUSH + Flush SMEE data when in buffered mode + 0x33 + + + LSEE + Lock access to SmartEEPROM data from any mean + 0x34 + + + USEE + Unlock access to SmartEEPROM data + 0x35 + + + LSEER + Lock access to the SmartEEPROM Register Address Space (above 64KB) + 0x36 + + + USEER + Unlock access to the SmartEEPROM Register Address Space (above 64KB) + 0x37 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + PARAM + NVM Parameter + 0x8 + 32 + read-only + 0x00060000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + SEE + SmartEEPROM Supported + 31 + 1 + + SEESelect + + A + 163840 bytes + 0xA + + + 9 + 147456 bytes + 0x9 + + + 8 + 131072 bytes + 0x8 + + + 7 + 114688 bytes + 0x7 + + + 6 + 98304 bytes + 0x6 + + + 5 + 81920 bytes + 0x5 + + + 4 + 65536 bytes + 0x4 + + + 3 + 49152 bytes + 0x3 + + + 2 + 32768 bytes + 0x2 + + + 1 + 16384 bytes + 0x1 + + + 0 + 0 bytes + 0x0 + + + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 16 + 0x0000 + + + DONE + Command Done Interrupt Clear + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error Interrupt Clear + 2 + 1 + + + LOCKE + Lock Error Interrupt Clear + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Clear + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Clear + 5 + 1 + + + NVME + NVM Error Interrupt Clear + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Clear + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Clear + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Clear + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Clear + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0xE + 16 + 0x0000 + + + DONE + Command Done Interrupt Enable + 0 + 1 + + + ADDRE + Address Error Interrupt Enable + 1 + 1 + + + PROGE + Programming Error Interrupt Enable + 2 + 1 + + + LOCKE + Lock Error Interrupt Enable + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Enable + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Enable + 5 + 1 + + + NVME + NVM Error Interrupt Enable + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Enable + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Enable + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Enable + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 16 + 0x0000 + + + DONE + Command Done + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error + 2 + 1 + + + LOCKE + Lock Error + 3 + 1 + + + ECCSE + ECC Single Error + 4 + 1 + + + ECCDE + ECC Dual Error + 5 + 1 + + + NVME + NVM Error + 6 + 1 + + + SUSP + Suspended Write Or Erase Operation + 7 + 1 + + + SEESFULL + Active SEES Full + 8 + 1 + + + SEESOVF + Active SEES Overflow + 9 + 1 + + + SEEWRC + SEE Write Completed + 10 + 1 + + + + + STATUS + Status + 0x12 + 16 + read-only + 0x0000 + + + READY + Ready to accept a command + 0 + 1 + + + PRM + Power Reduction Mode + 1 + 1 + + + LOAD + NVM Page Buffer Active Loading + 2 + 1 + + + SUSP + NVM Write Or Erase Operation Is Suspended + 3 + 1 + + + AFIRST + BANKA First + 4 + 1 + + + BPDIS + Boot Loader Protection Disable + 5 + 1 + + + BOOTPROT + Boot Loader Protection Size + 8 + 4 + + BOOTPROTSelect + + 0 + 0 kbytes + 0xF + + + 8 + 8 kbytes + 0xE + + + 16 + 16 kbytes + 0xD + + + 24 + 24 kbytes + 0xC + + + 32 + 32 kbytes + 0xB + + + 40 + 40 kbytes + 0xA + + + 48 + 48 kbytes + 0x9 + + + 56 + 56 kbytes + 0x8 + + + 64 + 64 kbytes + 0x7 + + + 72 + 72 kbytes + 0x6 + + + 80 + 80 kbytes + 0x5 + + + 88 + 88 kbytes + 0x4 + + + 96 + 96 kbytes + 0x3 + + + 104 + 104 kbytes + 0x2 + + + 112 + 112 kbytes + 0x1 + + + 120 + 120 kbytes + 0x0 + + + + + + + ADDR + Address + 0x14 + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 24 + + + + + RUNLOCK + Lock Section + 0x18 + 32 + read-only + 0x00000000 + + + RUNLOCK + Region Un-Lock Bits + 0 + 32 + + + + + 2 + 4 + PBLDATA[%s] + Page Buffer Load Data x + 0x1C + 32 + read-only + 0xFFFFFFFF + + + DATA + Page Buffer Data + 0 + 32 + + + + + ECCERR + ECC Error Status Register + 0x24 + 32 + read-only + 0x00000000 + + + ADDR + Error Address + 0 + 24 + + + TYPEL + Low Double-Word Error Type + 28 + 2 + + TYPELSelect + + None + No Error Detected Since Last Read + 0 + + + Single + At Least One Single Error Detected Since last Read + 1 + + + Dual + At Least One Dual Error Detected Since Last Read + 2 + + + + + TYPEH + High Double-Word Error Type + 30 + 2 + + TYPEHSelect + + None + No Error Detected Since Last Read + 0 + + + Single + At Least One Single Error Detected Since last Read + 1 + + + Dual + At Least One Dual Error Detected Since Last Read + 2 + + + + + + + DBGCTRL + Debug Control + 0x28 + 8 + 0x00 + + + ECCDIS + Debugger ECC Read Disable + 0 + 1 + + + ECCELOG + Debugger ECC Error Tracking Mode + 1 + 1 + + + + + SEECFG + SmartEEPROM Configuration Register + 0x2A + 8 + 0x00 + + + WMODE + Write Mode + 0 + 1 + + WMODESelect + + UNBUFFERED + A NVM write command is issued after each write in the pagebuffer + 0 + + + BUFFERED + A NVM write command is issued when a write to a new page is requested + 1 + + + + + APRDIS + Automatic Page Reallocation Disable + 1 + 1 + + + + + SEESTAT + SmartEEPROM Status Register + 0x2C + 32 + read-only + 0x00000000 + + + ASEES + Active SmartEEPROM Sector + 0 + 1 + + + LOAD + Page Buffer Loaded + 1 + 1 + + + BUSY + Busy + 2 + 1 + + + LOCK + SmartEEPROM Write Access Is Locked + 3 + 1 + + + RLOCK + SmartEEPROM Write Access To Register Address Space Is Locked + 4 + 1 + + + SBLK + Blocks Number In a Sector + 8 + 4 + + + PSZ + SmartEEPROM Page Size + 16 + 3 + + + + + + + OSCCTRL + U24011.0.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x58 + registers + + + OSCCTRL_XOSC0 + 2 + + + OSCCTRL_XOSC1 + 3 + + + OSCCTRL_DFLL + 4 + + + OSCCTRL_DPLL0 + 5 + + + OSCCTRL_DPLL1 + 6 + + + + EVCTRL + Event Control + 0x0 + 8 + 0x00 + + + CFDEO0 + Clock 0 Failure Detector Event Output Enable + 0 + 1 + + + CFDEO1 + Clock 1 Failure Detector Event Output Enable + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x8 + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xC + 32 + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x00000000 + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + + + XOSCCKSW0 + XOSC 0 Clock Switch + 4 + 1 + + + XOSCCKSW1 + XOSC 1 Clock Switch + 5 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + + + DPLL0TO + DPLL0 Timeout + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + + + DPLL1TO + DPLL1 Timeout + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + + + + + 2 + 4 + XOSCCTRL[%s] + External Multipurpose Crystal Oscillator Control + 0x14 + 32 + 0x00000080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + LOWBUFGAIN + Low Buffer Gain Enable + 8 + 1 + + + IPTAT + Oscillator Current Reference + 9 + 2 + + + IMULT + Oscillator Current Multiplier + 11 + 4 + + + ENALC + Automatic Loop Control Enable + 15 + 1 + + + CFDEN + Clock Failure Detector Enable + 16 + 1 + + + SWBEN + Xosc Clock Switch Enable + 17 + 1 + + + STARTUP + Start-Up Time + 20 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + CFDPRESC + Clock Failure Detector Prescaler + 24 + 4 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + DFLLCTRLA + DFLL48M Control A + 0x1C + 8 + 0x82 + + + ENABLE + DFLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DFLLCTRLB + DFLL48M Control B + 0x20 + 8 + 0x00 + + + MODE + Operating Mode Selection + 0 + 1 + + + STABLE + Stable DFLL Frequency + 1 + 1 + + + LLAW + Lose Lock After Wake + 2 + 1 + + + USBCRM + USB Clock Recovery Mode + 3 + 1 + + + CCDIS + Chill Cycle Disable + 4 + 1 + + + QLDIS + Quick Lock Disable + 5 + 1 + + + BPLCKC + Bypass Coarse Lock + 6 + 1 + + + WAITLOCK + Wait Lock + 7 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x24 + 32 + 0x00000000 + + + FINE + Fine Value + 0 + 8 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + + + + + DFLLMUL + DFLL48M Multiplier + 0x28 + 32 + 0x00000000 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 8 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x2C + 8 + 0x00 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + DFLLCTRLB + DFLLCTRLB Synchronization Busy + 2 + 1 + + + DFLLVAL + DFLLVAL Synchronization Busy + 3 + 1 + + + DFLLMUL + DFLLMUL Synchronization Busy + 4 + 1 + + + + + 2 + 0x14 + DPLL[%s] + + 0x30 + + DPLLCTRLA + DPLL Control A + 0x0 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x4 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 13 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 5 + + + + + DPLLCTRLB + DPLL Control B + 0x8 + 32 + 0x00000020 + + + FILTER + Proportional Integral Filter Selection + 0 + 4 + + FILTERSelect + + FILTER1 + Bandwidth = 92.7Khz and Damping Factor = 0.76 + 0 + + + FILTER2 + Bandwidth = 131Khz and Damping Factor = 1.08 + 1 + + + FILTER3 + Bandwidth = 46.4Khz and Damping Factor = 0.38 + 2 + + + FILTER4 + Bandwidth = 65.6Khz and Damping Factor = 0.54 + 3 + + + FILTER5 + Bandwidth = 131Khz and Damping Factor = 0.56 + 4 + + + FILTER6 + Bandwidth = 185Khz and Damping Factor = 0.79 + 5 + + + FILTER7 + Bandwidth = 65.6Khz and Damping Factor = 0.28 + 6 + + + FILTER8 + Bandwidth = 92.7Khz and Damping Factor = 0.39 + 7 + + + FILTER9 + Bandwidth = 46.4Khz and Damping Factor = 1.49 + 8 + + + FILTER10 + Bandwidth = 65.6Khz and Damping Factor = 2.11 + 9 + + + FILTER11 + Bandwidth = 23.2Khz and Damping Factor = 0.75 + 10 + + + FILTER12 + Bandwidth = 32.8Khz and Damping Factor = 1.06 + 11 + + + FILTER13 + Bandwidth = 65.6Khz and Damping Factor = 1.07 + 12 + + + FILTER14 + Bandwidth = 92.7Khz and Damping Factor = 1.51 + 13 + + + FILTER15 + Bandwidth = 32.8Khz and Damping Factor = 0.53 + 14 + + + FILTER16 + Bandwidth = 46.4Khz and Damping Factor = 0.75 + 15 + + + + + WUF + Wake Up Fast + 4 + 1 + + + REFCLK + Reference Clock Selection + 5 + 3 + + REFCLKSelect + + GCLK + Dedicated GCLK clock reference + 0x0 + + + XOSC32 + XOSC32K clock reference + 0x1 + + + XOSC0 + XOSC0 clock reference + 0x2 + + + XOSC1 + XOSC1 clock reference + 0x3 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock + 0x0 + + + 800US + Time-out if no lock within 800us + 0x4 + + + 900US + Time-out if no lock within 900us + 0x5 + + + 1MS + Time-out if no lock within 1ms + 0x6 + + + 1P1MS + Time-out if no lock within 1.1ms + 0x7 + + + + + LBYPASS + Lock Bypass + 11 + 1 + + + DCOFILTER + Sigma-Delta DCO Filter Selection + 12 + 3 + + DCOFILTERSelect + + FILTER1 + Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 + 0 + + + FILTER2 + Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 + 1 + + + FILTER3 + Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 + 2 + + + FILTER4 + Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 + 3 + + + FILTER5 + Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 + 4 + + + FILTER6 + Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 + 5 + + + FILTER7 + Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 + 6 + + + FILTER8 + Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 + 7 + + + + + DCOEN + DCO Filter Enable + 15 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0xC + 32 + read-only + 0x00000000 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Loop Divider Ratio Synchronization Status + 2 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x10 + 32 + read-only + 0x00000000 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + + + + OSC32KCTRL + U24001.0.0 + 32kHz Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + OSC32KCTRL + 7 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + XOSC32KSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + RTC Clock Selection + 0x10 + 8 + 0x00 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x2080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE2048 + 62.6 ms + 0 + + + CYCLE4096 + 125 ms + 1 + + + CYCLE16384 + 500 ms + 2 + + + CYCLE32768 + 1000 ms + 3 + + + CYCLE65536 + 2000 ms + 4 + + + CYCLE131072 + 4000 ms + 5 + + + CYCLE262144 + 8000 ms + 6 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CGM + Control Gain Mode + 13 + 2 + + CGMSelect + + XT + Standard mode + 1 + + + HS + High Speed mode + 2 + + + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + 0x00000000 + + + EN32K + Enable Out 32k + 1 + 1 + + + EN1K + Enable Out 1k + 2 + 1 + + + CALIB + Oscillator Calibration + 8 + 6 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.2.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x44 + registers + + + PAC + 41 + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + FLASH_ALT_ + FLASH_ALT + 1 + 1 + + + SEEPROM_ + SEEPROM + 2 + 1 + + + RAMCM4S_ + RAMCM4S + 3 + 1 + + + RAMPPPDSU_ + RAMPPPDSU + 4 + 1 + + + RAMDMAWR_ + RAMDMAWR + 5 + 1 + + + RAMDMACICM_ + RAMDMACICM + 6 + 1 + + + HPB0_ + HPB0 + 7 + 1 + + + HPB1_ + HPB1 + 8 + 1 + + + HPB2_ + HPB2 + 9 + 1 + + + HPB3_ + HPB3 + 10 + 1 + + + PUKCC_ + PUKCC + 11 + 1 + + + SDHC0_ + SDHC0 + 12 + 1 + + + QSPI_ + QSPI + 14 + 1 + + + BKUPRAM_ + BKUPRAM + 15 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + SERCOM0_ + SERCOM0 + 12 + 1 + + + SERCOM1_ + SERCOM1 + 13 + 1 + + + TC0_ + TC0 + 14 + 1 + + + TC1_ + TC1 + 15 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + USB_ + USB + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + CMCC_ + CMCC + 3 + 1 + + + PORT_ + PORT + 4 + 1 + + + DMAC_ + DMAC + 5 + 1 + + + HMATRIX_ + HMATRIX + 6 + 1 + + + EVSYS_ + EVSYS + 7 + 1 + + + SERCOM2_ + SERCOM2 + 9 + 1 + + + SERCOM3_ + SERCOM3 + 10 + 1 + + + TCC0_ + TCC0 + 11 + 1 + + + TCC1_ + TCC1 + 12 + 1 + + + TC2_ + TC2 + 13 + 1 + + + TC3_ + TC3 + 14 + 1 + + + RAMECC_ + RAMECC + 16 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + CAN0_ + CAN0 + 0 + 1 + + + CAN1_ + CAN1 + 1 + 1 + + + TCC2_ + TCC2 + 3 + 1 + + + TCC3_ + TCC3 + 4 + 1 + + + TC4_ + TC4 + 5 + 1 + + + TC5_ + TC5 + 6 + 1 + + + PDEC_ + PDEC + 7 + 1 + + + AC_ + AC + 8 + 1 + + + AES_ + AES + 9 + 1 + + + TRNG_ + TRNG + 10 + 1 + + + ICM_ + ICM + 11 + 1 + + + PUKCC_ + PUKCC + 12 + 1 + + + QSPI_ + QSPI + 13 + 1 + + + CCL_ + CCL + 14 + 1 + + + + + INTFLAGD + Peripheral interrupt flag status - Bridge D + 0x20 + 32 + 0x00000000 + + + SERCOM4_ + SERCOM4 + 0 + 1 + + + SERCOM5_ + SERCOM5 + 1 + 1 + + + TCC4_ + TCC4 + 4 + 1 + + + ADC0_ + ADC0 + 7 + 1 + + + ADC1_ + ADC1 + 8 + 1 + + + DAC_ + DAC + 9 + 1 + + + I2S_ + I2S + 10 + 1 + + + PCC_ + PCC + 11 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00010000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 13 + 1 + + + TC0_ + TC0 APB Protect Enable + 14 + 1 + + + TC1_ + TC1 APB Protect Enable + 15 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + USB_ + USB APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + CMCC_ + CMCC APB Protect Enable + 3 + 1 + + + PORT_ + PORT APB Protect Enable + 4 + 1 + + + DMAC_ + DMAC APB Protect Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Protect Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Protect Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 10 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 11 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 12 + 1 + + + TC2_ + TC2 APB Protect Enable + 13 + 1 + + + TC3_ + TC3 APB Protect Enable + 14 + 1 + + + RAMECC_ + RAMECC APB Protect Enable + 16 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x00000000 + + + CAN0_ + CAN0 APB Protect Enable + 0 + 1 + + + CAN1_ + CAN1 APB Protect Enable + 1 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 3 + 1 + + + TCC3_ + TCC3 APB Protect Enable + 4 + 1 + + + TC4_ + TC4 APB Protect Enable + 5 + 1 + + + TC5_ + TC5 APB Protect Enable + 6 + 1 + + + PDEC_ + PDEC APB Protect Enable + 7 + 1 + + + AC_ + AC APB Protect Enable + 8 + 1 + + + AES_ + AES APB Protect Enable + 9 + 1 + + + TRNG_ + TRNG APB Protect Enable + 10 + 1 + + + ICM_ + ICM APB Protect Enable + 11 + 1 + + + PUKCC_ + PUKCC APB Protect Enable + 12 + 1 + + + QSPI_ + QSPI APB Protect Enable + 13 + 1 + + + CCL_ + CCL APB Protect Enable + 14 + 1 + + + + + STATUSD + Peripheral write protection status - Bridge D + 0x40 + 32 + read-only + 0x00000000 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 1 + 1 + + + TCC4_ + TCC4 APB Protect Enable + 4 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 7 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 8 + 1 + + + DAC_ + DAC APB Protect Enable + 9 + 1 + + + I2S_ + I2S APB Protect Enable + 10 + 1 + + + PCC_ + PCC APB Protect Enable + 11 + 1 + + + + + + + PCC + U20171.1.0 + Parallel Capture Controller + PCC + PCC_ + 0x43002C00 + + 0 + 0xE8 + registers + + + PCC + 129 + + + + MR + Mode Register + 0x0 + 32 + 0x00000000 + + + PCEN + Parallel Capture Enable + 0 + 1 + + + DSIZE + Data size + 4 + 2 + + + SCALE + Scale data + 8 + 1 + + + ALWYS + Always Sampling + 9 + 1 + + + HALFS + Half Sampling + 10 + 1 + + + FRSTS + First sample + 11 + 1 + + + ISIZE + Input Data Size + 16 + 3 + + + CID + Clear If Disabled + 30 + 2 + + + + + IER + Interrupt Enable Register + 0x4 + 32 + write-only + 0x00000000 + + + DRDY + Data Ready Interrupt Enable + 0 + 1 + + + OVRE + Overrun Error Interrupt Enable + 1 + 1 + + + + + IDR + Interrupt Disable Register + 0x8 + 32 + write-only + 0x00000000 + + + DRDY + Data Ready Interrupt Disable + 0 + 1 + + + OVRE + Overrun Error Interrupt Disable + 1 + 1 + + + + + IMR + Interrupt Mask Register + 0xC + 32 + read-only + 0x00000000 + + + DRDY + Data Ready Interrupt Mask + 0 + 1 + + + OVRE + Overrun Error Interrupt Mask + 1 + 1 + + + + + ISR + Interrupt Status Register + 0x10 + 32 + read-only + 0x00000000 + + + DRDY + Data Ready Interrupt Status + 0 + 1 + + + OVRE + Overrun Error Interrupt Status + 1 + 1 + + + + + RHR + Reception Holding Register + 0x14 + 32 + read-only + 0x00000000 + + + RDATA + Reception Data + 0 + 32 + + + + + WPMR + Write Protection Mode Register + 0xE0 + 32 + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + + + WPKEY + Write Protection Key + 8 + 24 + + + + + WPSR + Write Protection Status Register + 0xE4 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Source + 0 + 1 + + + WPVSRC + Write Protection Violation Status + 8 + 16 + + + + + + + PDEC + U22631.0.0 + Quadrature Decodeur + PDEC + PDEC_ + 0x42001C00 + + 0 + 0x38 + registers + + + PDEC_OTHER + 115 + + + PDEC_MC0 + 116 + + + PDEC_MC1 + 117 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operation Mode + 2 + 2 + + MODESelect + + QDEC + QDEC operating mode + 0 + + + HALL + HALL operating mode + 1 + + + COUNTER + COUNTER operating mode + 2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + CONF + PDEC Configuration + 8 + 3 + + CONFSelect + + X4 + Quadrature decoder direction + 0 + + + X4S + Secure Quadrature decoder direction + 1 + + + X2 + Decoder direction + 2 + + + X2S + Secure decoder direction + 3 + + + AUTOC + Auto correction mode + 4 + + + + + ALOCK + Auto Lock + 11 + 1 + + + SWAP + PDEC Phase A and B Swap + 14 + 1 + + + PEREN + Period Enable + 15 + 1 + + + PINEN0 + PDEC Input From Pin 0 Enable + 16 + 1 + + + PINEN1 + PDEC Input From Pin 1 Enable + 17 + 1 + + + PINEN2 + PDEC Input From Pin 2 Enable + 18 + 1 + + + PINVEN0 + IO Pin 0 Invert Enable + 20 + 1 + + + PINVEN1 + IO Pin 1 Invert Enable + 21 + 1 + + + PINVEN2 + IO Pin 2 Invert Enable + 22 + 1 + + + ANGULAR + Angular Counter Length + 24 + 3 + + + MAXCMP + Maximum Consecutive Missing Pulses + 28 + 4 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a counter restart or retrigger + 1 + + + UPDATE + Force update of double buffered registers + 2 + + + READSYNC + Force a read synchronization of COUNT + 3 + + + START + Start QDEC/HALL + 4 + + + STOP + Stop QDEC/HALL + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a counter restart or retrigger + 1 + + + UPDATE + Force update of double buffered registers + 2 + + + READSYNC + Force a read synchronization of COUNT + 3 + + + START + Start QDEC/HALL + 4 + + + STOP + Stop QDEC/HALL + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 2 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger on event + 1 + + + COUNT + Count on event + 2 + + + + + EVINV + Inverted Event Input Enable + 2 + 3 + + + EVEI + Event Input Enable + 5 + 3 + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + ERREO + Error Output Event Enable + 9 + 1 + + + DIREO + Direction Output Event Enable + 10 + 1 + + + VLCEO + Velocity Output Event Enable + 11 + 1 + + + MCEO0 + Match Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + Overflow/Underflow Interrupt Disable + 0 + 1 + + + ERR + Error Interrupt Disable + 1 + 1 + + + DIR + Direction Interrupt Disable + 2 + 1 + + + VLC + Velocity Interrupt Disable + 3 + 1 + + + MC0 + Channel 0 Compare Match Disable + 4 + 1 + + + MC1 + Channel 1 Compare Match Disable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + Overflow/Underflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + DIR + Direction Interrupt Enable + 2 + 1 + + + VLC + Velocity Interrupt Enable + 3 + 1 + + + MC0 + Channel 0 Compare Match Enable + 4 + 1 + + + MC1 + Channel 1 Compare Match Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + Overflow/Underflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + DIR + Direction Change + 2 + 1 + + + VLC + Velocity + 3 + 1 + + + MC0 + Channel 0 Compare Match + 4 + 1 + + + MC1 + Channel 1 Compare Match + 5 + 1 + + + + + STATUS + Status + 0xC + 16 + 0x0040 + + + QERR + Quadrature Error Flag + 0 + 1 + + + IDXERR + Index Error Flag + 1 + 1 + + + MPERR + Missing Pulse Error flag + 2 + 1 + + + WINERR + Window Error Flag + 4 + 1 + + + HERR + Hall Error Flag + 5 + 1 + + + STOP + Stop + 6 + 1 + + + DIR + Direction Status Flag + 7 + 1 + + + PRESCBUFV + Prescaler Buffer Valid + 8 + 1 + + + FILTERBUFV + Filter Buffer Valid + 9 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 12 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 13 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + CTRLB + Control B Synchronization Busy + 2 + 1 + + + STATUS + Status Synchronization Busy + 3 + 1 + + + PRESC + Prescaler Synchronization Busy + 4 + 1 + + + FILTER + Filter Synchronization Busy + 5 + 1 + + + COUNT + Count Synchronization Busy + 6 + 1 + + + CC0 + Compare Channel 0 Synchronization Busy + 7 + 1 + + + CC1 + Compare Channel 1 Synchronization Busy + 8 + 1 + + + + + PRESC + Prescaler Value + 0x14 + 8 + 0x00 + + + PRESC + Prescaler Value + 0 + 4 + + PRESCSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + DIV256 + Divide by 256 + 8 + + + DIV512 + Divide by 512 + 9 + + + DIV1024 + Divide by 1024 + 10 + + + + + + + FILTER + Filter Value + 0x15 + 8 + 0x00 + + + FILTER + Filter Value + 0 + 8 + + + + + PRESCBUF + Prescaler Buffer Value + 0x18 + 8 + 0x00 + + + PRESCBUF + Prescaler Buffer Value + 0 + 4 + + PRESCBUFSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV32 + Divide by 32 + 5 + + + DIV64 + Divide by 64 + 6 + + + DIV128 + Divide by 128 + 7 + + + DIV256 + Divide by 256 + 8 + + + DIV512 + Divide by 512 + 9 + + + DIV1024 + Divide by 1024 + 10 + + + + + + + FILTERBUF + Filter Buffer Value + 0x19 + 8 + 0x00 + + + FILTERBUF + Filter Buffer Value + 0 + 8 + + + + + COUNT + Counter Value + 0x1C + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 4 + CC[%s] + Channel n Compare Value + 0x20 + 32 + 0x00000000 + + + CC + Channel Compare Value + 0 + 16 + + + + + 2 + 4 + CCBUF[%s] + Channel Compare Buffer Value + 0x30 + 32 + 0x00000000 + + + CCBUF + Channel Compare Buffer Value + 0 + 16 + + + + + + + PM + U24061.0.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x13 + registers + + + PM + 0 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + IORET + I/O Retention + 2 + 1 + + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x02 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE + CPU, AHBx, and APBx clocks are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + HIBERNATE + Backup domain is ON as well as some PDRAMs + 5 + + + BACKUP + Only Backup domain is powered ON + 6 + + + OFF + All power domains are powered OFF + 7 + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + SLEEPRDY + Sleep Mode Entry Ready + 0 + 1 + + + + + STDBYCFG + Standby Configuration + 0x8 + 8 + 0x00 + + + RAMCFG + Ram Configuration + 0 + 2 + + RAMCFGSelect + + RET + All the system RAM is retained + 0 + + + PARTIAL + Only the first 32Kbytes of the system RAM is retained + 1 + + + OFF + All the system RAM is turned OFF + 2 + + + + + FASTWKUP + Fast Wakeup + 4 + 2 + + FASTWKUPSelect + + NO + Fast Wakeup is disabled + 0 + + + NVM + Fast Wakeup is enabled on NVM + 1 + + + MAINVREG + Fast Wakeup is enabled on the main voltage regulator (MAINVREG) + 2 + + + BOTH + Fast Wakeup is enabled on both NVM and MAINVREG + 3 + + + + + + + HIBCFG + Hibernate Configuration + 0x9 + 8 + 0x00 + + + RAMCFG + Ram Configuration + 0 + 2 + + RAMCFGSelect + + RET + All the system RAM is retained + 0 + + + PARTIAL + Only the first 32Kbytes of the system RAM is retained + 1 + + + OFF + All the system RAM is turned OFF + 2 + + + + + BRAMCFG + Backup Ram Configuration + 2 + 2 + + BRAMCFGSelect + + RET + All the backup RAM is retained + 0 + + + PARTIAL + Only the first 4Kbytes of the backup RAM is retained + 1 + + + OFF + All the backup RAM is turned OFF + 2 + + + + + + + BKUPCFG + Backup Configuration + 0xA + 8 + 0x00 + + + BRAMCFG + Ram Configuration + 0 + 2 + + BRAMCFGSelect + + RET + All the backup RAM is retained + 0 + + + PARTIAL + Only the first 4Kbytes of the backup RAM is retained + 1 + + + OFF + All the backup RAM is turned OFF + 2 + + + + + + + PWSAKDLY + Power Switch Acknowledge Delay + 0x12 + 8 + 0x00 + + + DLYVAL + Delay Value + 0 + 7 + + + IGNACK + Ignore Acknowledge + 7 + 1 + + + + + + + PORT + U22102.2.0 + Port Module + PORT + PORT_ + 0x41008000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIR + Port Data Direction + 0 + 32 + + + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUT + PORT Data Output Value + 0 + 32 + + + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTCLR + PORT Data Output Value Clear + 0 + 32 + + + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTSET + PORT Data Output Value Set + 0 + 32 + + + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + OUTTGL + PORT Data Output Value Toggle + 0 + 32 + + + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + IN + PORT Data Input Value + 0 + 32 + + + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing + 24 + 4 + + + WRPMUX + Write PMUX + 28 + 1 + + + WRPINCFG + Write PINCFG + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + PORT Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + PORT Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + PORT Event Input Enable 0 + 7 + 1 + + + PID1 + PORT Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + PORT Event Action 1 + 13 + 2 + + + PORTEI1 + PORT Event Input Enable 1 + 15 + 1 + + + PID2 + PORT Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + PORT Event Action 2 + 21 + 2 + + + PORTEI2 + PORT Event Input Enable 2 + 23 + 1 + + + PID3 + PORT Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + PORT Event Action 3 + 29 + 2 + + + PORTEI3 + PORT Event Input Enable 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration + 0x40 + 8 + 0x00 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + QSPI + U20081.6.3 + Quad SPI interface + QSPI + QSPI_ + 0x42003400 + + 0 + 0x48 + registers + + + QSPI + 134 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + LASTXFER + Last Transfer + 24 + 1 + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000000 + + + MODE + Serial Memory Mode + 0 + 1 + + MODESelect + + SPI + SPI operating mode + 0 + + + MEMORY + Serial Memory operating mode + 1 + + + + + LOOPEN + Local Loopback Enable + 1 + 1 + + + WDRBT + Wait Data Read Before Transfer + 2 + 1 + + + SMEMREG + Serial Memory reg + 3 + 1 + + + CSMODE + Chip Select Mode + 4 + 2 + + CSMODESelect + + NORELOAD + The chip select is deasserted if TD has not been reloaded before the end of the current transfer. + 0x0 + + + LASTXFER + The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. + 0x1 + + + SYSTEMATICALLY + The chip select is deasserted systematically after each transfer. + 0x2 + + + + + DATALEN + Data Length + 8 + 4 + + DATALENSelect + + 8BITS + 8-bits transfer + 0x0 + + + 9BITS + 9 bits transfer + 0x1 + + + 10BITS + 10-bits transfer + 0x2 + + + 11BITS + 11-bits transfer + 0x3 + + + 12BITS + 12-bits transfer + 0x4 + + + 13BITS + 13-bits transfer + 0x5 + + + 14BITS + 14-bits transfer + 0x6 + + + 15BITS + 15-bits transfer + 0x7 + + + 16BITS + 16-bits transfer + 0x8 + + + + + DLYBCT + Delay Between Consecutive Transfers + 16 + 8 + + + DLYCS + Minimum Inactive CS Delay + 24 + 8 + + + + + BAUD + Baud Rate + 0x8 + 32 + 0x00000000 + + + CPOL + Clock Polarity + 0 + 1 + + + CPHA + Clock Phase + 1 + 1 + + + BAUD + Serial Clock Baud Rate + 8 + 8 + + + DLYBS + Delay Before SCK + 16 + 8 + + + + + RXDATA + Receive Data + 0xC + 32 + read-only + 0x00000000 + + + DATA + Receive Data + 0 + 16 + + + + + TXDATA + Transmit Data + 0x10 + 32 + write-only + 0x00000000 + + + DATA + Transmit Data + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0x14 + 32 + 0x00000000 + + + RXC + Receive Data Register Full Interrupt Disable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Disable + 1 + 1 + + + TXC + Transmission Complete Interrupt Disable + 2 + 1 + + + ERROR + Overrun Error Interrupt Disable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Disable + 8 + 1 + + + INSTREND + Instruction End Interrupt Disable + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x18 + 32 + 0x00000000 + + + RXC + Receive Data Register Full Interrupt Enable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Enable + 1 + 1 + + + TXC + Transmission Complete Interrupt Enable + 2 + 1 + + + ERROR + Overrun Error Interrupt Enable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Enable + 8 + 1 + + + INSTREND + Instruction End Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x1C + 32 + 0x00000000 + + + RXC + Receive Data Register Full + 0 + 1 + + + DRE + Transmit Data Register Empty + 1 + 1 + + + TXC + Transmission Complete + 2 + 1 + + + ERROR + Overrun Error + 3 + 1 + + + CSRISE + Chip Select Rise + 8 + 1 + + + INSTREND + Instruction End + 10 + 1 + + + + + STATUS + Status Register + 0x20 + 32 + read-only + 0x00000200 + + + ENABLE + Enable + 1 + 1 + + + CSSTATUS + Chip Select + 9 + 1 + + + + + INSTRADDR + Instruction Address + 0x30 + 32 + 0x00000000 + + + ADDR + Instruction Address + 0 + 32 + + + + + INSTRCTRL + Instruction Code + 0x34 + 32 + 0x00000000 + + + INSTR + Instruction Code + 0 + 8 + + + OPTCODE + Option Code + 16 + 8 + + + + + INSTRFRAME + Instruction Frame + 0x38 + 32 + 0x00000000 + + + WIDTH + Instruction Code, Address, Option Code and Data Width + 0 + 3 + + WIDTHSelect + + SINGLE_BIT_SPI + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI + 0x0 + + + DUAL_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI + 0x1 + + + QUAD_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI + 0x2 + + + DUAL_IO + Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x3 + + + QUAD_IO + Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x4 + + + DUAL_CMD + Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x5 + + + QUAD_CMD + Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x6 + + + + + INSTREN + Instruction Enable + 4 + 1 + + + ADDREN + Address Enable + 5 + 1 + + + OPTCODEEN + Option Enable + 6 + 1 + + + DATAEN + Data Enable + 7 + 1 + + + OPTCODELEN + Option Code Length + 8 + 2 + + OPTCODELENSelect + + 1BIT + 1-bit length option code + 0x0 + + + 2BITS + 2-bits length option code + 0x1 + + + 4BITS + 4-bits length option code + 0x2 + + + 8BITS + 8-bits length option code + 0x3 + + + + + ADDRLEN + Address Length + 10 + 1 + + ADDRLENSelect + + 24BITS + 24-bits address length + 0 + + + 32BITS + 32-bits address length + 1 + + + + + TFRTYPE + Data Transfer Type + 12 + 2 + + TFRTYPESelect + + READ + Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. + 0x0 + + + READMEMORY + Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. + 0x1 + + + WRITE + Write transfer into the serial memory.Scrambling is not performed. + 0x2 + + + WRITEMEMORY + Write data transfer into the serial memory.If enabled, scrambling is performed. + 0x3 + + + + + CRMODE + Continuous Read Mode + 14 + 1 + + + DDREN + Double Data Rate Enable + 15 + 1 + + + DUMMYLEN + Dummy Cycles Length + 16 + 5 + + + + + SCRAMBCTRL + Scrambling Mode + 0x40 + 32 + 0x00000000 + + + ENABLE + Scrambling/Unscrambling Enable + 0 + 1 + + + RANDOMDIS + Scrambling/Unscrambling Random Value Disable + 1 + 1 + + + + + SCRAMBKEY + Scrambling Key + 0x44 + 32 + write-only + 0x00000000 + + + KEY + Scrambling User Key + 0 + 32 + + + + + + + RAMECC + U22681.0.0 + RAM ECC + RAMECC + RAMECC_ + 0x41020000 + + 0 + 0x10 + registers + + + RAMECC + 45 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Clear + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Clear + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x1 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Set + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Set + 1 + 1 + + + + + INTFLAG + Interrupt Flag + 0x2 + 8 + 0x00 + + + SINGLEE + Single Bit ECC Error Interrupt + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt + 1 + 1 + + + + + STATUS + Status + 0x3 + 8 + read-only + 0x00 + + + ECCDIS + ECC Disable + 0 + 1 + + + + + ERRADDR + Error Address + 0x4 + 32 + read-only + 0x00000000 + + + ERRADDR + Error Address + 0 + 17 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + ECCDIS + ECC Disable + 0 + 1 + + + ECCELOG + ECC Error Log + 1 + 1 + + + + + + + RSTC + U22394.0.0 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x3 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + NVM + NVM Reset + 3 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + BACKUP + Backup Reset + 7 + 1 + + + + + BKUPEXIT + Backup Exit Source + 0x2 + 8 + read-only + 0x00 + + + RTC + Real Timer Counter Interrupt + 1 + 1 + + + BBPS + Battery Backup Power Switch + 2 + 1 + + + HIB + Hibernate + 7 + 1 + + + + + + + RTC + U22502.1.0 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0xA0 + registers + + + RTC + 11 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE0 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + COMP[%s] + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE0 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + COUNT + Count Timestamp Value + 0 + 32 + + + + + TAMPID + Tamper ID + 0x68 + 32 + 0x00000000 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 4 + BKUP[%s] + Backup + 0x80 + 32 + 0x00000000 + + + BKUP + Backup + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE1 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + CMPEO2 + Compare 2 Event Output Enable + 10 + 1 + + + CMPEO3 + Compare 3 Event Output Enable + 11 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + CMP2 + Compare 2 + 10 + 1 + + + CMP3 + Compare 3 + 11 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COMP2 + COMP 2 Register Busy + 7 + 1 + + + COMP3 + COMP 3 Register Busy + 8 + 1 + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 4 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE1 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + COUNT + Count Timestamp Value + 0 + 16 + + + + + TAMPID + Tamper ID + 0x68 + 32 + 0x00000000 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 4 + BKUP[%s] + Backup + 0x80 + 32 + 0x00000000 + + + BKUP + Backup + 0 + 32 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE2 Control B + 0x2 + 16 + 0x0000 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + ALARMEO1 + Alarm 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + ALARM1 + Alarm 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + ALARM1 + ALARM 1 Register Busy + 6 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + MASK1 + MASK 1 Register Busy + 12 + 1 + + + CLOCKSYNC + Clock Synchronization Enable Bit Busy + 15 + 1 + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 4 + 4 + GP[%s] + General Purpose + 0x40 + 32 + 0x00000000 + + + GP + General Purpose + 0 + 32 + + + + + ALARM0 + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK0 + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + ALARM1 + MODE2_ALARM Alarm n Value + 0x28 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK1 + MODE2_ALARM Alarm n Mask + 0x2C + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + 0x00000000 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE2 Timestamp + 0x64 + 32 + read-only + 0x00000000 + + + SECOND + Second Timestamp Value + 0 + 6 + + + MINUTE + Minute Timestamp Value + 6 + 6 + + + HOUR + Hour Timestamp Value + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day Timestamp Value + 17 + 5 + + + MONTH + Month Timestamp Value + 22 + 4 + + + YEAR + Year Timestamp Value + 26 + 6 + + + + + TAMPID + Tamper ID + 0x68 + 32 + 0x00000000 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 4 + BKUP[%s] + Backup + 0x80 + 32 + 0x00000000 + + + BKUP + Backup + 0 + 32 + + + + + + + + SDHC0 + U20111.8.3 + SD/MMC Host Controller + SDHC + SDHC_ + 0x45000000 + + 0 + 0x235 + registers + + + SDHC0 + 135 + + + + SSAR + SDMA System Address / Argument 2 + 0x0 + 32 + 0x00000000 + + + ADDR + SDMA System Address + 0 + 32 + + + + + SSAR_CMD23_MODE + SDMA System Address / Argument 2 + SSAR + 0x0 + 32 + 0x00000000 + + + ARG2 + Argument 2 + 0 + 32 + + + + + BSR + Block Size + 0x4 + 16 + 0x0000 + + + BLOCKSIZE + Transfer Block Size + 0 + 10 + + + BOUNDARY + SDMA Buffer Boundary + 12 + 3 + + BOUNDARYSelect + + 4K + 4k bytes + 0 + + + 8K + 8k bytes + 1 + + + 16K + 16k bytes + 2 + + + 32K + 32k bytes + 3 + + + 64K + 64k bytes + 4 + + + 128K + 128k bytes + 5 + + + 256K + 256k bytes + 6 + + + 512K + 512k bytes + 7 + + + + + + + BCR + Block Count + 0x6 + 16 + 0x0000 + + + BCNT + Blocks Count for Current Transfer + 0 + 16 + + + + + ARG1R + Argument 1 + 0x8 + 32 + 0x00000000 + + + ARG + Argument 1 + 0 + 32 + + + + + TMR + Transfer Mode + 0xC + 16 + 0x0000 + + + DMAEN + DMA Enable + 0 + 1 + + DMAENSelect + + DISABLE + No data transfer or Non DMA data transfer + 0 + + + ENABLE + DMA data transfer + 1 + + + + + BCEN + Block Count Enable + 1 + 1 + + BCENSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + ACMDEN + Auto Command Enable + 2 + 2 + + ACMDENSelect + + DISABLED + Auto Command Disabled + 0 + + + CMD12 + Auto CMD12 Enable + 1 + + + CMD23 + Auto CMD23 Enable + 2 + + + + + DTDSEL + Data Transfer Direction Selection + 4 + 1 + + DTDSELSelect + + WRITE + Write (Host to Card) + 0 + + + READ + Read (Card to Host) + 1 + + + + + MSBSEL + Multi/Single Block Selection + 5 + 1 + + MSBSELSelect + + SINGLE + Single Block + 0 + + + MULTIPLE + Multiple Block + 1 + + + + + + + CR + Command + 0xE + 16 + 0x0000 + + + RESPTYP + Response Type + 0 + 2 + + RESPTYPSelect + + NONE + No response + 0 + + + 136_BIT + 136-bit response + 1 + + + 48_BIT + 48-bit response + 2 + + + 48_BIT_BUSY + 48-bit response check busy after response + 3 + + + + + CMDCCEN + Command CRC Check Enable + 3 + 1 + + CMDCCENSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CMDICEN + Command Index Check Enable + 4 + 1 + + CMDICENSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + DPSEL + Data Present Select + 5 + 1 + + DPSELSelect + + NO_DATA + No Data Present + 0 + + + DATA + Data Present + 1 + + + + + CMDTYP + Command Type + 6 + 2 + + CMDTYPSelect + + NORMAL + Other commands + 0 + + + SUSPEND + CMD52 for writing Bus Suspend in CCCR + 1 + + + RESUME + CMD52 for writing Function Select in CCCR + 2 + + + ABORT + CMD12, CMD52 for writing I/O Abort in CCCR + 3 + + + + + CMDIDX + Command Index + 8 + 6 + + + + + 4 + 4 + RR[%s] + Response + 0x10 + 32 + read-only + 0x00000000 + + + CMDRESP + Command Response + 0 + 32 + + + + + BDPR + Buffer Data Port + 0x20 + 32 + 0x00000000 + + + BUFDATA + Buffer Data + 0 + 32 + + + + + PSR + Present State + 0x24 + 32 + read-only + 0x00F80000 + + + CMDINHC + Command Inhibit (CMD) + 0 + 1 + + CMDINHCSelect + + CAN + Can issue command using only CMD line + 0 + + + CANNOT + Cannot issue command + 1 + + + + + CMDINHD + Command Inhibit (DAT) + 1 + 1 + + CMDINHDSelect + + CAN + Can issue command which uses the DAT line + 0 + + + CANNOT + Cannot issue command which uses the DAT line + 1 + + + + + DLACT + DAT Line Active + 2 + 1 + + DLACTSelect + + INACTIVE + DAT Line Inactive + 0 + + + ACTIVE + DAT Line Active + 1 + + + + + RTREQ + Re-Tuning Request + 3 + 1 + + RTREQSelect + + OK + Fixed or well-tuned sampling clock + 0 + + + REQUIRED + Sampling clock needs re-tuning + 1 + + + + + WTACT + Write Transfer Active + 8 + 1 + + WTACTSelect + + NO + No valid data + 0 + + + YES + Transferring data + 1 + + + + + RTACT + Read Transfer Active + 9 + 1 + + RTACTSelect + + NO + No valid data + 0 + + + YES + Transferring data + 1 + + + + + BUFWREN + Buffer Write Enable + 10 + 1 + + BUFWRENSelect + + DISABLE + Write disable + 0 + + + ENABLE + Write enable + 1 + + + + + BUFRDEN + Buffer Read Enable + 11 + 1 + + BUFRDENSelect + + DISABLE + Read disable + 0 + + + ENABLE + Read enable + 1 + + + + + CARDINS + Card Inserted + 16 + 1 + + CARDINSSelect + + NO + Reset or Debouncing or No Card + 0 + + + YES + Card inserted + 1 + + + + + CARDSS + Card State Stable + 17 + 1 + + CARDSSSelect + + NO + Reset or Debouncing + 0 + + + YES + No Card or Insered + 1 + + + + + CARDDPL + Card Detect Pin Level + 18 + 1 + + CARDDPLSelect + + NO + No card present (SDCD#=1) + 0 + + + YES + Card present (SDCD#=0) + 1 + + + + + WRPPL + Write Protect Pin Level + 19 + 1 + + WRPPLSelect + + PROTECTED + Write protected (SDWP#=0) + 0 + + + ENABLED + Write enabled (SDWP#=1) + 1 + + + + + DATLL + DAT[3:0] Line Level + 20 + 4 + + + CMDLL + CMD Line Level + 24 + 1 + + + + + HC1R + Host Control 1 + 0x28 + 8 + 0xE00 + + + LEDCTRL + LED Control + 0 + 1 + + LEDCTRLSelect + + OFF + LED off + 0 + + + ON + LED on + 1 + + + + + DW + Data Width + 1 + 1 + + DWSelect + + 1BIT + 1-bit mode + 0 + + + 4BIT + 4-bit mode + 1 + + + + + HSEN + High Speed Enable + 2 + 1 + + HSENSelect + + NORMAL + Normal Speed mode + 0 + + + HIGH + High Speed mode + 1 + + + + + DMASEL + DMA Select + 3 + 2 + + DMASELSelect + + SDMA + SDMA is selected + 0 + + + 32BIT + 32-bit Address ADMA2 is selected + 2 + + + + + CARDDTL + Card Detect Test Level + 6 + 1 + + CARDDTLSelect + + NO + No Card + 0 + + + YES + Card Inserted + 1 + + + + + CARDDSEL + Card Detect Signal Selection + 7 + 1 + + CARDDSELSelect + + NORMAL + SDCD# is selected (for normal use) + 0 + + + TEST + The Card Select Test Level is selected (for test purpose) + 1 + + + + + + + HC1R_EMMC_MODE + Host Control 1 + HC1R + 0x28 + 8 + 0xE00 + + + DW + Data Width + 1 + 1 + + DWSelect + + 1BIT + 1-bit mode + 0 + + + 4BIT + 4-bit mode + 1 + + + + + HSEN + High Speed Enable + 2 + 1 + + HSENSelect + + NORMAL + Normal Speed mode + 0 + + + HIGH + High Speed mode + 1 + + + + + DMASEL + DMA Select + 3 + 2 + + DMASELSelect + + SDMA + SDMA is selected + 0 + + + 32BIT + 32-bit Address ADMA2 is selected + 2 + + + + + + + PCR + Power Control + 0x29 + 8 + 0x0E + + + SDBPWR + SD Bus Power + 0 + 1 + + SDBPWRSelect + + OFF + Power off + 0 + + + ON + Power on + 1 + + + + + SDBVSEL + SD Bus Voltage Select + 1 + 3 + + SDBVSELSelect + + 1V8 + 1.8V (Typ.) + 5 + + + 3V0 + 3.0V (Typ.) + 6 + + + 3V3 + 3.3V (Typ.) + 7 + + + + + + + BGCR + Block Gap Control + 0x2A + 8 + 0x00 + + + STPBGR + Stop at Block Gap Request + 0 + 1 + + STPBGRSelect + + TRANSFER + Transfer + 0 + + + STOP + Stop + 1 + + + + + CONTR + Continue Request + 1 + 1 + + CONTRSelect + + GO_ON + Not affected + 0 + + + RESTART + Restart + 1 + + + + + RWCTRL + Read Wait Control + 2 + 1 + + RWCTRLSelect + + DISABLE + Disable Read Wait Control + 0 + + + ENABLE + Enable Read Wait Control + 1 + + + + + INTBG + Interrupt at Block Gap + 3 + 1 + + INTBGSelect + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 1 + + + + + + + BGCR_EMMC_MODE + Block Gap Control + BGCR + 0x2A + 8 + 0x00 + + + STPBGR + Stop at Block Gap Request + 0 + 1 + + STPBGRSelect + + TRANSFER + Transfer + 0 + + + STOP + Stop + 1 + + + + + CONTR + Continue Request + 1 + 1 + + CONTRSelect + + GO_ON + Not affected + 0 + + + RESTART + Restart + 1 + + + + + + + WCR + Wakeup Control + 0x2B + 8 + 0x00 + + + WKENCINT + Wakeup Event Enable on Card Interrupt + 0 + 1 + + WKENCINTSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + WKENCINS + Wakeup Event Enable on Card Insertion + 1 + 1 + + WKENCINSSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + WKENCREM + Wakeup Event Enable on Card Removal + 2 + 1 + + WKENCREMSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + + + CCR + Clock Control + 0x2C + 16 + 0x0000 + + + INTCLKEN + Internal Clock Enable + 0 + 1 + + INTCLKENSelect + + OFF + Stop + 0 + + + ON + Oscillate + 1 + + + + + INTCLKS + Internal Clock Stable + 1 + 1 + + INTCLKSSelect + + NOT_READY + Not Ready + 0 + + + READY + Ready + 1 + + + + + SDCLKEN + SD Clock Enable + 2 + 1 + + SDCLKENSelect + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CLKGSEL + Clock Generator Select + 5 + 1 + + CLKGSELSelect + + DIV + Divided Clock Mode + 0 + + + PROG + Programmable Clock Mode + 1 + + + + + USDCLKFSEL + Upper Bits of SDCLK Frequency Select + 6 + 2 + + + SDCLKFSEL + SDCLK Frequency Select + 8 + 8 + + + + + TCR + Timeout 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Driver Type C is Not Supported + 0 + + + YES + Driver Type C is Supported + 1 + + + + + DRVDSUP + Driver Type D Support + 6 + 1 + + DRVDSUPSelect + + NO + Driver Type D is Not Supported + 0 + + + YES + Driver Type D is Supported + 1 + + + + + TCNTRT + Timer Count for Re-Tuning + 8 + 4 + + TCNTRTSelect + + DISABLED + Re-Tuning Timer disabled + 0 + + + 1S + 1 second + 1 + + + 2S + 2 seconds + 2 + + + 4S + 4 seconds + 3 + + + 8S + 8 seconds + 4 + + + 16S + 16 seconds + 5 + + + 32S + 32 seconds + 6 + + + 64S + 64 seconds + 7 + + + 128S + 128 seconds + 8 + + + 256S + 256 seconds + 9 + + + 512S + 512 seconds + 10 + + + 1024S + 1024 seconds + 11 + + + OTHER + Get information from other source + 15 + + + + + TSDR50 + Use Tuning for SDR50 + 13 + 1 + + TSDR50Select + + NO + SDR50 does not require tuning + 0 + + + YES + SDR50 requires tuning + 1 + + + + + CLKMULT + Clock Multiplier + 16 + 8 + + CLKMULTSelect + + NO + Clock Multiplier is Not Supported + 0 + + + + + + + MCCAR + Maximum Current Capabilities + 0x48 + 32 + read-only + 0x00000000 + + + MAXCUR33V + Maximum Current for 3.3V + 0 + 8 + + MAXCUR33VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + MAXCUR30V + Maximum Current for 3.0V + 8 + 8 + + MAXCUR30VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + MAXCUR18V + Maximum Current for 1.8V + 16 + 8 + + MAXCUR18VSelect + + OTHER + Get information via another method + 0 + + + 4MA + 4mA + 1 + + + 8MA + 8mA + 2 + + + 12MA + 12mA + 3 + + + + + + + FERACES + Force Event for Auto CMD Error Status + 0x50 + 16 + write-only + 0x0000 + + + ACMD12NE + Force Event for Auto CMD12 Not Executed + 0 + 1 + + ACMD12NESelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMDTEO + Force Event for Auto CMD Timeout Error + 1 + 1 + + ACMDTEOSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMDCRC + Force Event for Auto CMD CRC Error + 2 + 1 + + ACMDCRCSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMDEND + Force Event for Auto CMD End Bit Error + 3 + 1 + + ACMDENDSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMDIDX + Force Event for Auto CMD Index Error + 4 + 1 + + ACMDIDXSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + CMDNI + Force Event for Command Not Issued By Auto CMD12 Error + 7 + 1 + + CMDNISelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + + + FEREIS + Force Event for Error Interrupt Status + 0x52 + 16 + write-only + 0x0000 + + + CMDTEO + Force Event for Command Timeout Error + 0 + 1 + + CMDTEOSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + CMDCRC + Force Event for Command CRC Error + 1 + 1 + + CMDCRCSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + CMDEND + Force Event for Command End Bit Error + 2 + 1 + + CMDENDSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + CMDIDX + Force Event for Command Index Error + 3 + 1 + + CMDIDXSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + DATTEO + Force Event for Data Timeout Error + 4 + 1 + + DATTEOSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + DATCRC + Force Event for Data CRC Error + 5 + 1 + + DATCRCSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + DATEND + Force Event for Data End Bit Error + 6 + 1 + + DATENDSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + CURLIM + Force Event for Current Limit Error + 7 + 1 + + CURLIMSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ACMD + Force Event for Auto CMD Error + 8 + 1 + + ACMDSelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + ADMA + Force Event for ADMA Error + 9 + 1 + + ADMASelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + BOOTAE + Force Event for Boot Acknowledge Error + 12 + 1 + + BOOTAESelect + + NO + No Interrupt + 0 + + + YES + Interrupt is generated + 1 + + + + + + + AESR + ADMA Error Status + 0x54 + 8 + read-only + 0x00 + + + ERRST + ADMA Error State + 0 + 2 + + ERRSTSelect + + STOP + ST_STOP (Stop DMA) + 0 + + + FDS + ST_FDS (Fetch Descriptor) + 1 + + + TFR + ST_TFR (Transfer Data) + 3 + + + + + LMIS + ADMA Length Mismatch Error + 2 + 1 + + LMISSelect + + NO + No Error + 0 + + + YES + Error + 1 + + + + + + + 1 + 4 + ASAR[%s] + ADMA System Address n + 0x58 + 32 + 0x00000000 + + + ADMASA + ADMA System Address + 0 + 32 + + + + + 8 + 2 + PVR[%s] + Preset Value n + 0x60 + 16 + 0x0000 + + + SDCLKFSEL + SDCLK Frequency Select Value for Initialization + 0 + 10 + + + CLKGSEL + Clock Generator Select Value for Initialization + 10 + 1 + + CLKGSELSelect + + DIV + Host Controller Ver2.00 Compatible Clock Generator (Divider) + 0 + + + PROG + Programmable Clock Generator + 1 + + + + + DRVSEL + Driver Strength Select Value for Initialization + 14 + 2 + + DRVSELSelect + + B + Driver Type B is Selected + 0 + + + A + Driver Type A is Selected + 1 + + + C + Driver Type C is Selected + 2 + + + D + Driver Type D is Selected + 3 + + + + + + + SISR + Slot Interrupt Status + 0xFC + 16 + read-only + 0x20000 + + + INTSSL + Interrupt Signal for Each Slot + 0 + 1 + + + + + HCVR + Host Controller Version + 0xFE + 16 + read-only + 0x1802 + + + SVER + Spec Version + 0 + 8 + + + VVER + Vendor Version + 8 + 8 + + + + + MC1R + MMC Control 1 + 0x204 + 8 + 0x00 + + + CMDTYP + e.MMC Command Type + 0 + 2 + + CMDTYPSelect + + NORMAL + Not a MMC specific command + 0 + + + WAITIRQ + Wait IRQ Command + 1 + + + STREAM + Stream Command + 2 + + + BOOT + Boot Command + 3 + + + + + DDR + e.MMC HSDDR Mode + 3 + 1 + + + OPD + e.MMC Open Drain Mode + 4 + 1 + + + BOOTA + e.MMC Boot Acknowledge Enable + 5 + 1 + + + RSTN + e.MMC Reset Signal + 6 + 1 + + + FCD + e.MMC Force Card Detect + 7 + 1 + + + + + MC2R + MMC Control 2 + 0x205 + 8 + write-only + 0x00 + + + SRESP + e.MMC Abort Wait IRQ + 0 + 1 + + + ABOOT + e.MMC Abort Boot + 1 + 1 + + + + + ACR + AHB Control + 0x208 + 32 + 0x00000000 + + + BMAX + AHB Maximum Burst + 0 + 2 + + BMAXSelect + + INCR16 + 0 + + + INCR8 + 1 + + + INCR4 + 2 + + + SINGLE + 3 + + + + + + + CC2R + Clock Control 2 + 0x20C + 32 + 0x00000000 + + + FSDCLKD + Force SDCK Disabled + 0 + 1 + + FSDCLKDSelect + + NOEFFECT + No effect + 0 + + + DISABLE + SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled + 1 + + + + + + + CACR + Capabilities Control + 0x230 + 32 + 0x00000000 + + + CAPWREN + Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) + 0 + 1 + + + KEY + Key (0x46) + 8 + 8 + + + + + DBGR + Debug + 0x234 + 8 + 0x00 + + + NIDBG + Non-intrusive debug enable + 0 + 1 + + NIDBGSelect + + IDBG + Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) + 0 + + + NIDBG + Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) + 1 + + + + + + + + + SERCOM0 + U22015.0.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x40003000 + + 0 + 0x31 + registers + + + SERCOM0_0 + 46 + + + SERCOM0_1 + 47 + + + SERCOM0_2 + 48 + + + SERCOM0_OTHER + 49 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + CTRLC + I2CM Control C + 0x8 + 32 + 0x00000000 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Data transaction from/to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Data transaction from/to DATA register are 32-bit + 0x1 + + + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + LENGTH + Length Synchronization Busy + 4 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + CTRLC + I2CS Control C + 0x8 + 32 + 0x00000000 + + + SDASETUP + SDA Setup Time + 0 + 4 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Data transaction from/to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Data transaction from/to DATA register are 32-bit + 0x1 + + + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + LENGTH + Length Synchronization Busy + 4 + 1 + + + + + LENGTH + I2CS Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] is used as data input + 0x0 + + + PAD1 + SERCOM PAD[1] is used as data input + 0x1 + + + PAD2 + SERCOM PAD[2] is used as data input + 0x2 + + + PAD3 + SERCOM PAD[3] is used as data input + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + SPIS Control C + 0x8 + 32 + 0x00000000 + + + ICSPACE + Inter-Character Spacing + 0 + 6 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Transaction from and to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Transaction from and to DATA register are 32-bit + 0x1 + + + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + LENGTH + SPIS Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] is used as data input + 0x0 + + + PAD1 + SERCOM PAD[1] is used as data input + 0x1 + + + PAD2 + SERCOM PAD[2] is used as data input + 0x2 + + + PAD3 + SERCOM PAD[3] is used as data input + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + SPIM Control C + 0x8 + 32 + 0x00000000 + + + ICSPACE + Inter-Character Spacing + 0 + 6 + + + DATA32B + Data 32 Bit + 24 + 1 + + DATA32BSelect + + DATA_TRANS_8BIT + Transaction from and to DATA register are 8-bit + 0x0 + + + DATA_TRANS_32BIT + Transaction from and to DATA register are 32-bit + 0x1 + + + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + LENGTH + SPIM Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD3 + SERCOM_PAD[0] is used for data transmission + 0x3 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + USART_FRAME_ISO_7816 + ISO 7816 + 0x7 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + DATA32B + Data 32 Bit + 24 + 2 + + DATA32BSelect + + DATA_READ_WRITE_CHSIZE + Data reads and writes according CTRLB.CHSIZE + 0x0 + + + DATA_READ_CHSIZE_WRITE_32BIT + Data reads according CTRLB.CHSIZE and writes according 32-bit extension + 0x1 + + + DATA_READ_32BIT_WRITE_CHSIZE + Data reads according 32-bit extension and writes according CTRLB.CHSIZE + 0x2 + + + DATA_READ_WRITE_32BIT + Data reads and writes according 32-bit extension + 0x3 + + + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + RXERRCNT + RXERRCNT Synchronization Busy + 3 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + RXERRCNT + USART_EXT Receive Error Count + 0x20 + 8 + read-only + 0x00 + + + LENGTH + USART_EXT Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 2 + + + + + DATA + USART_EXT Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD3 + SERCOM_PAD[0] is used for data transmission + 0x3 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + USART_FRAME_ISO_7816 + ISO 7816 + 0x7 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + DATA32B + Data 32 Bit + 24 + 2 + + DATA32BSelect + + DATA_READ_WRITE_CHSIZE + Data reads and writes according CTRLB.CHSIZE + 0x0 + + + DATA_READ_CHSIZE_WRITE_32BIT + Data reads according CTRLB.CHSIZE and writes according 32-bit extension + 0x1 + + + DATA_READ_32BIT_WRITE_CHSIZE + Data reads according 32-bit extension and writes according CTRLB.CHSIZE + 0x2 + + + DATA_READ_WRITE_32BIT + Data reads and writes according 32-bit extension + 0x3 + + + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + RXERRCNT + RXERRCNT Synchronization Busy + 3 + 1 + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + + + + + RXERRCNT + USART_INT Receive Error Count + 0x20 + 8 + read-only + 0x00 + + + LENGTH + USART_INT Length + 0x22 + 16 + 0x0000 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 2 + + + + + DATA + USART_INT Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x40003400 + + SERCOM1_0 + 50 + + + SERCOM1_1 + 51 + + + SERCOM1_2 + 52 + + + SERCOM1_OTHER + 53 + + + + SERCOM2 + 0x41012000 + + SERCOM2_0 + 54 + + + SERCOM2_1 + 55 + + + SERCOM2_2 + 56 + + + SERCOM2_OTHER + 57 + + + + SERCOM3 + 0x41014000 + + SERCOM3_0 + 58 + + + SERCOM3_1 + 59 + + + SERCOM3_2 + 60 + + + SERCOM3_OTHER + 61 + + + + SERCOM4 + 0x43000000 + + SERCOM4_0 + 62 + + + SERCOM4_1 + 63 + + + SERCOM4_2 + 64 + + + SERCOM4_OTHER + 65 + + + + SERCOM5 + 0x43000400 + + SERCOM5_0 + 66 + + + SERCOM5_1 + 67 + + + SERCOM5_2 + 68 + + + SERCOM5_OTHER + 69 + + + + SUPC + U24071.1.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x2C + registers + + + SUPC_OTHER + 8 + + + SUPC_BODDET + 9 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + BOD33 + BOD33 Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + ACTION + Action when Threshold Crossed + 2 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INT + The BOD33 generates an interrupt + 0x2 + + + BKUP + The BOD33 puts the device in backup sleep mode + 0x3 + + + + + STDBYCFG + Configuration in Standby mode + 4 + 1 + + + RUNSTDBY + Run in Standby mode + 5 + 1 + + + RUNHIB + Run in Hibernate mode + 6 + 1 + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + HYST + Hysteresis value + 8 + 4 + + + PSEL + Prescaler Select + 12 + 3 + + PSELSelect + + NODIV + Not divided + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + + + LEVEL + Threshold Level for VDD + 16 + 8 + + + VBATLEVEL + Threshold Level in battery backup sleep mode for VBAT + 24 + 8 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000002 + + + ENABLE + Enable + 1 + 1 + + + SEL + Voltage Regulator Selection + 2 + 1 + + SELSelect + + LDO + LDO selection + 0x0 + + + BUCK + Buck selection + 0x1 + + + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + VSEN + Voltage Scaling Enable + 16 + 1 + + + VSPER + Voltage Scaling Period + 24 + 3 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + TSSEL + Temperature Sensor Selection + 3 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V0 + 1.0V voltage reference typical value + 0x0 + + + 1V1 + 1.1V voltage reference typical value + 0x1 + + + 1V2 + 1.2V voltage reference typical value + 0x2 + + + 1V25 + 1.25V voltage reference typical value + 0x3 + + + 2V0 + 2.0V voltage reference typical value + 0x4 + + + 2V2 + 2.2V voltage reference typical value + 0x5 + + + 2V4 + 2.4V voltage reference typical value + 0x6 + + + 2V5 + 2.5V voltage reference typical value + 0x7 + + + + + + + BBPS + Battery Backup Power Switch + 0x20 + 32 + 0x00000000 + + + CONF + Battery Backup Configuration + 0 + 1 + + CONFSelect + + BOD33 + The power switch is handled by the BOD33 + 0x0 + + + FORCED + In Backup Domain, the backup domain is always supplied by battery backup power + 0x1 + + + + + WAKEEN + Wake Enable + 2 + 1 + + + + + BKOUT + Backup Output Control + 0x24 + 32 + 0x00000000 + + + ENOUT0 + Enable OUT0 + 0 + 1 + + + ENOUT1 + Enable OUT1 + 1 + 1 + + + CLROUT0 + Clear OUT0 + 8 + 1 + + + CLROUT1 + Clear OUT1 + 9 + 1 + + + SETOUT0 + Set OUT0 + 16 + 1 + + + SETOUT1 + Set OUT1 + 17 + 1 + + + RTCTGLOUT0 + RTC Toggle OUT0 + 24 + 1 + + + RTCTGLOUT1 + RTC Toggle OUT1 + 25 + 1 + + + + + BKIN + Backup Input Control + 0x28 + 32 + read-only + 0x00000000 + + + BKIN0 + Backup Input 0 + 0 + 1 + + + BKIN1 + Backup Input 1 + 1 + 1 + + + + + + + TC0 + U22493.0.0 + Basic Timer Counter + TC + TC_ + 0x40003800 + + 0 + 0x38 + registers + + + TC0 + 107 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x40003C00 + + TC1 + 108 + + + + TC2 + 0x4101A000 + + TC2 + 109 + + + + TC3 + 0x4101C000 + + TC3 + 110 + + + + TC4 + 0x42001400 + + TC4 + 111 + + + + TC5 + 0x42001800 + + TC5 + 112 + + + + TCC0 + U22133.1.0 + Timer Counter Control + TCC + TCC_ + 0x41016000 + + 0 + 0x88 + registers + + + TCC0_OTHER + 85 + + + TCC0_MC0 + 86 + + + TCC0_MC1 + 87 + + + TCC0_MC2 + 88 + + + TCC0_MC3 + 89 + + + TCC0_MC4 + 90 + + + TCC0_MC5 + 91 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + CPTEN4 + Capture Channel 4 Enable + 28 + 1 + + + CPTEN5 + Capture Channel 5 Enable + 29 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + CC4 + Compare Channel 4 Busy + 12 + 1 + + + CC5 + Compare Channel 5 Busy + 13 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEI4 + Match or Capture Channel 4 Event Input Enable + 20 + 1 + + + MCEI5 + Match or Capture Channel 5 Event Input Enable + 21 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + MCEO4 + Match or Capture Channel 4 Event Output Enable + 28 + 1 + + + MCEO5 + Match or Capture Channel 5 Event Output Enable + 29 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + MC4 + Match or Capture 4 + 20 + 1 + + + MC5 + Match or Capture 5 + 21 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CCBUFV4 + Compare Channel 4 Buffer Valid + 20 + 1 + + + CCBUFV5 + Compare Channel 5 Buffer Valid + 21 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + CMP4 + Compare Channel 4 Value + 28 + 1 + + + CMP5 + Compare Channel 5 Value + 29 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + POL4 + Channel 4 Polarity + 20 + 1 + + + POL5 + Channel 5 Polarity + 21 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 6 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 6 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 6 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 6 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 6 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 6 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 6 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 6 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x41018000 + + TCC1_OTHER + 92 + + + TCC1_MC0 + 93 + + + TCC1_MC1 + 94 + + + TCC1_MC2 + 95 + + + TCC1_MC3 + 96 + + + + TCC2 + 0x42000C00 + + TCC2_OTHER + 97 + + + TCC2_MC0 + 98 + + + TCC2_MC1 + 99 + + + TCC2_MC2 + 100 + + + + TCC3 + 0x42001000 + + TCC3_OTHER + 101 + + + TCC3_MC0 + 102 + + + TCC3_MC1 + 103 + + + + TCC4 + 0x43001000 + + TCC4_OTHER + 104 + + + TCC4_MC0 + 105 + + + TCC4_MC1 + 106 + + + + TRNG + U22421.1.0 + True Random Generator + TRNG + TRNG_ + 0x42002800 + + 0 + 0x24 + registers + + + TRNG + 131 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + DATARDYEO + Data Ready Event Output + 0 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + DATARDY + Data Ready Interrupt Flag + 0 + 1 + + + + + DATA + Output Data + 0x20 + 32 + read-only + 0x00000000 + + + DATA + Output Data + 0 + 32 + + + + + + + USB + U22221.2.0 + Universal Serial Bus + USB + USB_ + 0x41000000 + + 0 + 0x200 + registers + + + USB_OTHER + 80 + + + USB_SOF_HSOF + 81 + + + USB_TRCPT0 + 82 + + + USB_TRCPT1 + 83 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + DEVICE Control B + 0x8 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0 + + + ACK + ACK + 1 + + + NYET + NYET + 2 + + + STALL + STALL + 3 + + + + + + + DADD + DEVICE Device Address + 0xA + 8 + 0x00 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0xC + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + LS + Low-speed mode + 0x1 + + + HS + High-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x10 + 16 + read-only + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + FNCERR + Frame Number CRC Error + 15 + 1 + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x1C + 16 + 0x0000 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + DEVICE_ENDPOINT[%s] + + 0x100 + + EPCFG + DEVICE_ENDPOINT End Point Configuration + 0x0 + 8 + 0x00 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + EPSTATUSCLR + DEVICE_ENDPOINT End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + + + CURBK + Current Bank Clear + 2 + 1 + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + EPSTATUSSET + DEVICE_ENDPOINT End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + + + DTGLIN + Data Toggle IN Set + 1 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + EPSTATUS + DEVICE_ENDPOINT End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGLOUT + Data Toggle Out + 0 + 1 + + + DTGLIN + Data Toggle In + 1 + 1 + + + CURBK + Current Bank + 2 + 1 + + + STALLRQ0 + Stall 0 Request + 4 + 1 + + + STALLRQ1 + Stall 1 Request + 5 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + EPINTFLAG + DEVICE_ENDPOINT End Point Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + EPINTENCLR + DEVICE_ENDPOINT End Point Interrupt Clear Flag + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + EPINTENSET + DEVICE_ENDPOINT End Point Interrupt Set Flag + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0 + + + HOST + Host Mode + 1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x2 + 8 + read-only + 0x00 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + + + QOSCTRL + USB Quality Of Service + 0x3 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + HOST Control B + 0x8 + 16 + 0x0000 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + AUTORESUME + Auto Resume Enable + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0xA + 8 + 0x00 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0xC + 8 + 0x00 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + + + + + FSMSTATUS + Finite State Machine Status + 0xD + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x10 + 16 + 0x0000 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x12 + 8 + read-only + 0x00 + + + FLENHIGH + Frame Length + 0 + 8 + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x14 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x18 + 16 + 0x0000 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x1C + 16 + 0x0000 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x20 + 16 + read-only + 0x0000 + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + + + + + DESCADD + Descriptor Address + 0x24 + 32 + 0x00000000 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x28 + 16 + 0x0000 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + HOST_PIPE[%s] + + 0x100 + + PCFG + HOST_PIPE End Point Configuration + 0x0 + 8 + 0x00 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + BINTERVAL + HOST_PIPE Bus Access Period of Pipe + 0x3 + 8 + 0x00 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + PSTATUSCLR + HOST_PIPE End Point Pipe Status Clear + 0x4 + 8 + write-only + 0x00 + + + DTGL + Data Toggle clear + 0 + 1 + + + CURBK + Curren Bank clear + 2 + 1 + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + + + + + PSTATUSSET + HOST_PIPE End Point Pipe Status Set + 0x5 + 8 + write-only + 0x00 + + + DTGL + Data Toggle Set + 0 + 1 + + + CURBK + Current Bank Set + 2 + 1 + + + PFREEZE + Pipe Freeze Set + 4 + 1 + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + + + + + PSTATUS + HOST_PIPE End Point Pipe Status + 0x6 + 8 + read-only + 0x00 + + + DTGL + Data Toggle + 0 + 1 + + + CURBK + Current Bank + 2 + 1 + + + PFREEZE + Pipe Freeze + 4 + 1 + + + BK0RDY + Bank 0 ready + 6 + 1 + + + BK1RDY + Bank 1 ready + 7 + 1 + + + + + PINTFLAG + HOST_PIPE Pipe Interrupt Flag + 0x7 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + PINTENCLR + HOST_PIPE Pipe Interrupt Flag Clear + 0x8 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Inetrrupt Disable + 5 + 1 + + + + + PINTENSET + HOST_PIPE Pipe Interrupt Flag Set + 0x9 + 8 + 0x00 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + + WDT + U22511.1.0 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 10 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WEN + Window Enable Synchronization Busy + 2 + 1 + + + ALWAYSON + Always-On Synchronization Busy + 3 + 1 + + + CLEAR + Clear Synchronization Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + CoreDebug + Core Debug Register + CoreDebug + CoreDebug_ + 0xE000EDF0 + + 0 + 0x10 + registers + + + + DHCSR + Debug Halting Control and Status Register + 0x0 + 32 + + + C_DEBUGEN + 0 + 1 + + + C_HALT + 1 + 1 + + + C_STEP + 2 + 1 + + + C_MASKINTS + 3 + 1 + + + C_SNAPSTALL + 5 + 1 + + + S_REGRDY + 16 + 1 + read-only + + + S_HALT + 17 + 1 + read-only + + + S_SLEEP + 18 + 1 + read-only + + + S_LOCKUP + 19 + 1 + read-only + + + S_RETIRE_ST + 24 + 1 + read-only + + + S_RESET_ST + 25 + 1 + read-only + + + DBGKEY + 16 + 16 + write-only + + + + + DCRSR + Debug Core Register Selector Register + 0x4 + 32 + write-only + + + REGSEL + 0 + 5 + + + REGWnR + 16 + 1 + + + + + DCRDR + Debug Core Register Data Register + 0x8 + 32 + + + DEMCR + Debug Exception and Monitor Control Register + 0xC + 32 + + + VC_CORERESET + 0 + 1 + + + VC_MMERR + 4 + 1 + + + VC_NOCPERR + 5 + 1 + + + VC_CHKERR + 6 + 1 + + + VC_STATERR + 7 + 1 + + + VC_BUSERR + 8 + 1 + + + VC_INTERR + 9 + 1 + + + VC_HARDERR + 10 + 1 + + + MON_EN + 16 + 1 + + + MON_PEND + 17 + 1 + + + MON_STEP + 18 + 1 + + + MON_REQ + 19 + 1 + + + TRCENA + 24 + 1 + + + + + + + DWT + Data Watchpoint and Trace Register + DWT + DWT_ + 0xE0001000 + + 0 + 0x5C + registers + + + + CTRL + Control Register + 0x0 + 32 + + + CYCCNTENA + 0 + 1 + + + POSTPRESET + 1 + 4 + + + POSTINIT + 5 + 4 + + + CYCTAP + 9 + 1 + + + SYNCTAP + 10 + 2 + + + PCSAMPLENA + 12 + 1 + + + EXCTRCENA + 16 + 1 + + + CPIEVTENA + 17 + 1 + + + EXCEVTENA + 18 + 1 + + + SLEEPEVTENA + 19 + 1 + + + LSUEVTENA + 20 + 1 + + + FOLDEVTENA + 21 + 1 + + + CYCEVTENA + 22 + 1 + + + NOPRFCNT + 24 + 1 + + + NOCYCCNT + 25 + 1 + + + NOEXTTRIG + 26 + 1 + + + NOTRCPKT + 27 + 1 + + + NUMCOMP + 28 + 4 + + + + + CYCCNT + Cycle Count Register + 0x4 + 32 + + + CPICNT + CPI Count Register + 0x8 + 32 + + + CPICNT + 0 + 8 + + + + + EXCCNT + Exception Overhead Count Register + 0xC + 32 + + + EXCCNT + 0 + 8 + + + + + SLEEPCNT + Sleep Count Register + 0x10 + 32 + + + SLEEPCNT + 0 + 8 + + + + + LSUCNT + LSU Count Register + 0x14 + 32 + + + LSUCNT + 0 + 8 + + + + + FOLDCNT + Folded-instruction Count Register + 0x18 + 32 + + + FOLDCNT + 0 + 8 + + + + + PCSR + Program Counter Sample Register + 0x1C + 32 + read-only + + + COMP0 + Comparator Register 0 + 0x20 + 32 + + + MASK0 + Mask Register 0 + 0x24 + 32 + + + MASK + 0 + 5 + + + + + FUNCTION0 + Function Register 0 + 0x28 + 32 + + + FUNCTION + 0 + 4 + + + EMITRANGE + 5 + 1 + + + CYCMATCH + 7 + 1 + + + DATAVMATCH + 8 + 1 + + + LNK1ENA + 9 + 1 + + + DATAVSIZE + 10 + 2 + + + DATAVADDR0 + 12 + 4 + + + DATAVADDR1 + 16 + 4 + + + MATCHED + 24 + 1 + + + + + COMP1 + Comparator Register 1 + 0x30 + 32 + + + MASK1 + Mask Register 1 + 0x34 + 32 + + + MASK + 0 + 5 + + + + + FUNCTION1 + Function Register 1 + 0x38 + 32 + + + FUNCTION + 0 + 4 + + + EMITRANGE + 5 + 1 + + + CYCMATCH + 7 + 1 + + + DATAVMATCH + 8 + 1 + + + LNK1ENA + 9 + 1 + + + DATAVSIZE + 10 + 2 + + + DATAVADDR0 + 12 + 4 + + + DATAVADDR1 + 16 + 4 + + + MATCHED + 24 + 1 + + + + + COMP2 + Comparator Register 2 + 0x40 + 32 + + + MASK2 + Mask Register 2 + 0x44 + 32 + + + MASK + 0 + 5 + + + + + FUNCTION2 + Function Register 2 + 0x48 + 32 + + + FUNCTION + 0 + 4 + + + EMITRANGE + 5 + 1 + + + CYCMATCH + 7 + 1 + + + DATAVMATCH + 8 + 1 + + + LNK1ENA + 9 + 1 + + + DATAVSIZE + 10 + 2 + + + DATAVADDR0 + 12 + 4 + + + DATAVADDR1 + 16 + 4 + + + MATCHED + 24 + 1 + + + + + COMP3 + Comparator Register 3 + 0x50 + 32 + + + MASK3 + Mask Register 3 + 0x54 + 32 + + + MASK + 0 + 5 + + + + + FUNCTION3 + Function Register 3 + 0x58 + 32 + + + FUNCTION + 0 + 4 + + + EMITRANGE + 5 + 1 + + + CYCMATCH + 7 + 1 + + + DATAVMATCH + 8 + 1 + + + LNK1ENA + 9 + 1 + + + DATAVSIZE + 10 + 2 + + + DATAVADDR0 + 12 + 4 + + + DATAVADDR1 + 16 + 4 + + + MATCHED + 24 + 1 + + + + + + + ETM + Embedded Trace Macrocell + ETM + ETM_ + 0xE0041000 + + 0 + 0x1000 + registers + + + + CR + ETM Main Control Register + 0x0 + 32 + 0x00000411 + + + ETMPD + ETM Power Down + 0 + 1 + + + PORTSIZE + Port Size bits 2:0 + 4 + 3 + + + STALL + Stall Processor + 7 + 1 + + + BROUT + Branch Output + 8 + 1 + + + DBGRQ + Debug Request Control + 9 + 1 + + + PROG + ETM Programming + 10 + 1 + + + PORTSEL + ETM Port Select + 11 + 1 + + + PORTMODE2 + Port Mode bit 2 + 13 + 1 + + + PORTMODE + Port Mode bits 1:0 + 16 + 2 + + + PORTSIZE3 + Port Size bit 3 + 21 + 1 + + + TSEN + TimeStamp Enable + 28 + 1 + + + + + CCR + ETM Configuration Code Register + 0x4 + 32 + read-only + 0x8C802000 + + + TRIGGER + ETM Trigger Event Register + 0x8 + 32 + + + SR + ETM Status Register + 0x10 + 32 + + + SCR + ETM System Configuration Register + 0x14 + 32 + read-only + 0x00020D09 + + + TEEVR + ETM TraceEnable Event Register + 0x20 + 32 + + + TECR1 + ETM TraceEnable Control 1 Register + 0x24 + 32 + + + FFLR + ETM FIFO Full Level Register + 0x28 + 32 + + + CNTRLDVR1 + ETM Free-running Counter Reload Value + 0x140 + 32 + + + SYNCFR + ETM Synchronization Frequency Register + 0x1E0 + 32 + read-only + 0x00000400 + + + IDR + ETM ID Register + 0x1E4 + 32 + read-only + 0x4114F250 + + + CCER + ETM Configuration Code Extension Register + 0x1E8 + 32 + read-only + 0x18541800 + + + TESSEICR + ETM TraceEnable Start/Stop EmbeddedICE Control Register + 0x1F0 + 32 + + + TSEVT + ETM TimeStamp Event Register + 0x1F8 + 32 + + + TRACEIDR + ETM CoreSight Trace ID Register + 0x200 + 32 + 0x00000000 + + + IDR2 + ETM ID Register 2 + 0x208 + 32 + read-only + 0x00000000 + + + PDSR + ETM Device Power-Down Status Register + 0x314 + 32 + read-only + 0x00000001 + + + ITMISCIN + ETM Integration Test Miscellaneous Inputs + 0xEE0 + 32 + read-only + + + ITTRIGOUT + ETM Integration Test Trigger Out + 0xEE8 + 32 + write-only + + + ITATBCTR2 + ETM Integration Test ATB Control 2 + 0xEF0 + 32 + read-only + + + ITATBCTR0 + ETM Integration Test ATB Control 0 + 0xEF8 + 32 + write-only + + + ITCTRL + ETM Integration Mode Control Register + 0xF00 + 32 + 0x00000000 + + + INTEGRATION + 0 + 1 + + + + + CLAIMSET + ETM Claim Tag Set Register + 0xFA0 + 32 + + + CLAIMCLR + ETM Claim Tag Clear Register + 0xFA4 + 32 + + + LAR + ETM Lock Access Register + 0xFB0 + 32 + write-only + + + LSR + ETM Lock Status Register + 0xFB4 + 32 + read-only + + + Present + 0 + 1 + + + Access + 1 + 1 + + + ByteAcc + 2 + 1 + + + + + AUTHSTATUS + ETM Authentication Status Register + 0xFB8 + 32 + read-only + + + DEVTYPE + ETM CoreSight Device Type Register + 0xFCC + 32 + read-only + 0x00000013 + + + PIDR4 + ETM Peripheral Identification Register #4 + 0xFD0 + 32 + read-only + 0x00000004 + + + PIDR5 + ETM Peripheral Identification Register #5 + 0xFD4 + 32 + read-only + 0x00000000 + + + PIDR6 + ETM Peripheral Identification Register #6 + 0xFD8 + 32 + read-only + 0x00000000 + + + PIDR7 + ETM Peripheral Identification Register #7 + 0xFDC + 32 + read-only + 0x00000000 + + + PIDR0 + ETM Peripheral Identification Register #0 + 0xFE0 + 32 + read-only + 0x00000025 + + + PIDR1 + ETM Peripheral Identification Register #1 + 0xFE4 + 32 + read-only + 0x000000B9 + + + PIDR2 + ETM Peripheral Identification Register #2 + 0xFE8 + 32 + read-only + 0x0000000B + + + PIDR3 + ETM Peripheral Identification Register #3 + 0xFEC + 32 + read-only + 0x00000000 + + + CIDR0 + ETM Component Identification Register #0 + 0xFF0 + 32 + read-only + 0x0000000D + + + CIDR1 + ETM Component Identification Register #1 + 0xFF4 + 32 + read-only + 0x00000090 + + + CIDR2 + ETM Component Identification Register #2 + 0xFF8 + 32 + read-only + 0x00000005 + + + CIDR3 + ETM Component Identification Register #3 + 0xFFC + 32 + read-only + 0x000000B1 + + + + + FPU + Floating Point Unit + FPU + FPU_ + 0xE000EF30 + + 0 + 0x18 + registers + + + + FPCCR + Floating-Point Context Control Register + 0x4 + 32 + 0xC0000000 + + + LSPACT + 0 + 1 + + + USER + 1 + 1 + + + THREAD + 3 + 1 + + + HFRDY + 4 + 1 + + + MMRDY + 5 + 1 + + + BFRDY + 6 + 1 + + + MONRDY + 8 + 1 + + + LSPEN + 30 + 1 + + + ASPEN + 31 + 1 + + + + + FPCAR + Floating-Point Context Address Register + 0x8 + 32 + + + ADDRESS + Address for FP registers in exception stack frame + 3 + 29 + + + + + FPDSCR + Floating-Point Default Status Control Register + 0xC + 32 + 0x00000000 + + + RMODE + Default value for FPSCR.RMODE + 22 + 2 + + RMODESelect + + RN + Round to Nearest + 0x0 + + + RP + Round towards Positive Infinity + 0x1 + + + RM + Round towards Negative Infinity + 0x2 + + + RZ + Round towards Zero + 0x3 + + + + + FZ + Default value for FPSCR.FZ + 24 + 1 + + + DN + Default value for FPSCR.DN + 25 + 1 + + + AHP + Default value for FPSCR.AHP + 26 + 1 + + + + + MVFR0 + Media and FP Feature Register 0 + 0x10 + 32 + read-only + + + A_SIMD_registers + 0 + 4 + + + Single_precision + 4 + 4 + + + Double_precision + 8 + 4 + + + FP_excep_trapping + 12 + 4 + + + Divide + 16 + 4 + + + Square_root + 20 + 4 + + + Short_vectors + 24 + 4 + + + FP_rounding_modes + 28 + 4 + + + + + MVFR1 + Media and FP Feature Register 1 + 0x14 + 32 + read-only + + + FtZ_mode + 0 + 4 + + + D_NaN_mode + 4 + 4 + + + FP_HPFP + 24 + 4 + + + FP_fused_MAC + 28 + 4 + + + + + + + ITM + Instrumentation Trace Macrocell + ITM + ITM_ + 0xE0000000 + + 0 + 0xF00 + registers + + + + 32 + 4 + PORT_WORD_MODE[%s] + ITM Stimulus Port Registers + 0x0 + 32 + write-only + + + PORT + 0 + 32 + + + + + 32 + 4 + PORT_BYTE_MODE[%s] + ITM Stimulus Port Registers + PORT_WORD_MODE[%s] + 0x0 + 32 + write-only + + + PORT + 0 + 8 + + + + + 32 + 4 + PORT_HWORD_MODE[%s] + ITM Stimulus Port Registers + PORT_WORD_MODE[%s] + 0x0 + 32 + write-only + + + PORT + 0 + 16 + + + + + TER + ITM Trace Enable Register + 0xE00 + 32 + + + TPR + ITM Trace Privilege Register + 0xE40 + 32 + + + PRIVMASK + 0 + 4 + + + + + TCR + ITM Trace Control Register + 0xE80 + 32 + + + ITMENA + 0 + 1 + + + TSENA + 1 + 1 + + + SYNCENA + 2 + 1 + + + DWTENA + 3 + 1 + + + SWOENA + 4 + 1 + + + STALLENA + 5 + 1 + + + TSPrescale + 8 + 2 + + + GTSFREQ + 10 + 2 + + + TraceBusID + 16 + 7 + + + BUSY + 23 + 1 + + + + + IWR + ITM Integration Write Register + 0xEF8 + 32 + write-only + + + ATVALIDM + 0 + 1 + + + + + IRR + ITM Integration Read Register + 0xEFC + 32 + read-only + + + ATREADYM + 0 + 1 + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x2C + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A1 + MPU Alias 1 Region Base Address Register + 0x14 + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A1 + MPU Alias 1 Region Attribute and Size Register + 0x18 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A2 + MPU Alias 2 Region Base Address Register + 0x1C + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A2 + MPU Alias 2 Region Attribute and Size Register + 0x20 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + RBAR_A3 + MPU Alias 3 Region Base Address Register + 0x24 + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR_A3 + MPU Alias 3 Region Attribute and Size Register + 0x28 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 1 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0xE04 + registers + + + + 5 + 4 + ISER[%s] + Interrupt Set Enable Register + 0x0 + 32 + 0 + + + SETENA + Interrupt set enable bits + 0 + 32 + + + + + 5 + 4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + 0 + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + + + + + 5 + 4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + 0 + + + SETPEND + Interrupt set-pending bits + 0 + 32 + + + + + 5 + 4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + 0 + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + + + + + 5 + 4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + 0 + + + ACTIVE + Interrupt active bits + 0 + 32 + + + + + 35 + 1 + IP[%s] + Interrupt Priority Register n + 0x300 + 8 + 0 + + + PRI0 + Priority of interrupt n + 0 + 3 + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + write-only + + + INTID + Interrupt ID to trigger + 0 + 9 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD8C + registers + + + + ICTR + Interrupt Controller Type Register + 0x4 + 32 + read-only + + + INTLINESNUM + 0 + 4 + + + + + ACTLR + Auxiliary Control Register + 0x8 + 32 + + + DISMCYCINT + Disable interruption of LDM/STM instructions + 0 + 1 + + + DISDEFWBUF + Disable wruite buffer use during default memory map accesses + 1 + 1 + + + DISFOLD + Disable IT folding + 2 + 1 + + + DISFPCA + Disable automatic update of CONTROL.FPCA + 8 + 1 + + + DISOOFP + Disable out-of-order FP instructions + 9 + 1 + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + + + REVISION + Processor revision number + 0 + 4 + + + PARTNO + Process Part Number, 0xC24=Cortex-M4 + 4 + 12 + + + CONSTANT + Constant + 16 + 4 + + + VARIANT + Variant number + 20 + 4 + + + IMPLEMENTER + Implementer code, 0x41=ARM + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0 + + + VECTACTIVE + Active exception number + 0 + 9 + + + RETTOBASE + No preempted active exceptions to execute + 11 + 1 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + ISRPREEMPT + Debug only + 23 + 1 + + + PENDSTCLR + SysTick clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0xFA050000 + + + VECTRESET + Must write 0 + 0 + 1 + + + VECTCLRACTIVE + Must write 0 + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + PRIGROUP + Interrupt priority grouping + 8 + 3 + + + ENDIANNESS + Data endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0 + + + SLEEPONEXIT + Sleep-on-exit on handler return + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + Do not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Deep Sleep used as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + 0x00000200 + + + NONBASETHRDENA + Indicates how processor enters Thread mode + 0 + 1 + + + USERSETMPEND + Enables unprivileged software access to STIR register + 1 + 1 + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + DIV_0_TRP + Enables divide by 0 trap + 4 + 1 + + + BFHFNMIGN + Ignore LDM/STM BusFault for -1/-2 priority handlers + 8 + 1 + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + + + SVCALLACT + SVCall active bit + 7 + 1 + + + MONITORACT + DebugMonitor exception active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + + + IACCVIOL + Instruction access violation + 0 + 1 + + + DACCVIOL + Data access violation + 1 + 1 + + + MUNSTKERR + MemManage Fault on unstacking for exception return + 3 + 1 + + + MSTKERR + MemManage Fault on stacking for exception entry + 4 + 1 + + + MLSPERR + MemManager Fault occured during FP lazy state preservation + 5 + 1 + + + MMARVALID + MemManage Fault Address Register valid + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + BusFault on unstacking for exception return + 11 + 1 + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + + + LSPERR + BusFault occured during FP lazy state preservation + 13 + 1 + + + BFARVALID + BusFault Address Register valid + 15 + 1 + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + + + INVSTATE + Invalid state UsageFault + 17 + 1 + + + INVPC + Invalid PC load UsageFault + 18 + 1 + + + NOCP + No coprocessor UsageFault + 19 + 1 + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + + + + + HFSR + HardFault Status Register + 0xD2C + 32 + + + VECTTBL + BusFault on a Vector Table read during exception processing + 1 + 1 + + + FORCED + Forced Hard Fault + 30 + 1 + + + DEBUGEVT + Debug: always write 0 + 31 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + + + HALTED + 0 + 1 + + + BKPT + 1 + 1 + + + DWTTRAP + 2 + 1 + + + VCATCH + 3 + 1 + + + EXTERNAL + 4 + 1 + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + + + ADDRESS + Address that generated the MemManage fault + 0 + 32 + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + + + ADDRESS + Address that generated the BusFault + 0 + 32 + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + + + IMPDEF + AUXFAULT input signals + 0 + 32 + + + + + 2 + 4 + PFR[%s] + Processor Feature Register + 0xD40 + 32 + + + DFR + Debug Feature Register + 0xD48 + 32 + read-only + + + ADR + Auxiliary Feature Register + 0xD4C + 32 + read-only + + + 4 + 4 + MMFR[%s] + Memory Model Feature Register + 0xD50 + 32 + read-only + + + 5 + 4 + ISAR[%s] + Instruction Set Attributes Register + 0xD60 + 32 + read-only + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + + + CP10 + Access privileges for coprocessor 10 + 20 + 2 + + CP10Select + + DENIED + Access denied + 0x0 + + + PRIV + Privileged access only + 0x1 + + + FULL + Full access + 0x3 + + + + + CP11 + Access privileges for coprocessor 11 + 22 + 2 + + CP11Select + + DENIED + Access denied + 0x0 + + + PRIV + Privileged access only + 0x1 + + + FULL + Full access + 0x3 + + + + + + + + + TPI + Trace Port Interface Register + TPI + TPI_ + 0xE0040000 + + 0 + 0xFD0 + registers + + + + SSPSR + Supported Parallel Port Size Register + 0x0 + 32 + read-only + + + CSPSR + Current Parallel Port Size Register + 0x4 + 32 + + + ACPR + Asynchronous Clock Prescaler Register + 0x10 + 32 + + + PRESCALER + 0 + 13 + + + + + SPPR + Selected Pin Protocol Register + 0xF0 + 32 + + + TXMODE + 0 + 2 + + + + + FFSR + Formatter and Flush Status Register + 0x300 + 32 + read-only + + + FlInProg + 0 + 1 + + + FtStopped + 1 + 1 + + + TCPresent + 2 + 1 + + + FtNonStop + 3 + 1 + + + + + FFCR + Formatter and Flush Control Register + 0x304 + 32 + + + EnFCont + 1 + 1 + + + TrigIn + 8 + 1 + + + + + FSCR + Formatter Synchronization Counter Register + 0x308 + 32 + read-only + + + TRIGGER + TRIGGER + 0xEE8 + 32 + read-only + + + TRIGGER + 0 + 1 + + + + + FIFO0 + Integration ETM Data + 0xEEC + 32 + read-only + + + ETM0 + 0 + 8 + + + ETM1 + 8 + 8 + + + ETM2 + 16 + 8 + + + ETM_bytecount + 24 + 2 + + + ETM_ATVALID + 26 + 1 + + + ITM_bytecount + 27 + 2 + + + ITM_ATVALID + 29 + 1 + + + + + ITATBCTR2 + ITATBCTR2 + 0xEF0 + 32 + read-only + + + ATREADY + 0 + 1 + + + + + ITATBCTR0 + ITATBCTR0 + 0xEF8 + 32 + read-only + + + ATREADY + 0 + 1 + + + + + FIFO1 + Integration ITM Data + 0xEFC + 32 + read-only + + + ITM0 + 0 + 8 + + + ITM1 + 8 + 8 + + + ITM2 + 16 + 8 + + + ETM_bytecount + 24 + 2 + + + ETM_ATVALID + 26 + 1 + + + ITM_bytecount + 27 + 2 + + + ITM_ATVALID + 29 + 1 + + + + + ITCTRL + Integration Mode Control + 0xF00 + 32 + + + Mode + 0 + 1 + + + + + CLAIMSET + Claim tag set + 0xFA0 + 32 + + + CLAIMCLR + Claim tag clear + 0xFA4 + 32 + + + DEVID + TPIU_DEVID + 0xFC8 + 32 + read-only + + + NrTraceInput + 0 + 1 + + + AsynClkIn + 5 + 1 + + + MinBufSz + 6 + 3 + + + PTINVALID + 9 + 1 + + + MANCVALID + 10 + 1 + + + NRZVALID + 11 + 1 + + + + + DEVTYPE + TPIU_DEVTYPE + 0xFCC + 32 + read-only + + + SubType + 0 + 4 + + + MajorType + 4 + 4 + + + + + + + diff --git a/src/modules/chips/atsame51j20a/atsame51j20a.zig b/src/modules/chips/atsame51j20a/atsame51j20a.zig new file mode 100644 index 0000000..094644f --- /dev/null +++ b/src/modules/chips/atsame51j20a/atsame51j20a.zig @@ -0,0 +1,333 @@ +pub const std = @import("std"); +pub const cpu = @import("cpu"); +pub const micro = @import("microzig"); +pub const chip = @import("registers.zig"); + +const regs = chip.registers; +pub usingnamespace chip; + +pub const chip_name = "ATSAME51J20A"; + +pub const clock_frequencies = .{ + // On any reset the synchronous clocks start to their initial state: + // * DFLL48M is enabled and configured to run at 48 MHz + // * Generic Generator 0 uses DFLL48M as source and generates GCLK_MAIN + // * CPU and BUS clocks are undivided + // i.e. GENCTRL0 = 0x00000106 + .cpu = 48_000_000, +}; + +/// Get access to the pin specified by `spec`. +/// +/// - `spec`: P{port}{pin} +/// - `port`: A, B +/// - `pin`: 0..31 +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'B') // J = 64 Pins; 2 Ports + @compileError("Unknown port '" ++ spec[1..2] ++ "'. Supported ports: A, B."); + + return struct { + // Try to parse the given pin number as u5, i.e. a value in '0'..'31'. + const pin_number: u5 = @import("std").fmt.parseInt(u5, spec[2..], 10) catch @compileError(invalid_format_msg); + const pin_mask: u32 = (1 << pin_number); + // Port is either 'A' or 'B'. + const port_number: usize = if (spec[1] == 'A') 0 else 1; + const gpio_port = @field(regs.PORT, "GROUP"); + }; +} + +pub const gpio = struct { + // See SAM D5x/E5x Family Data Sheet page 807. + + /// Configure the given pin as output with input disabled. + pub fn setOutput(comptime pin: type) void { + // To use pin Pxy as an output, write bit y of the DIR register to '1'. This + // can also be done by writing bit y int the DIRSET register to '1' - this + // will avoid disturbing the configuration of other pins (datasheet p. 803). + pin.gpio_port[pin.port_number].DIRSET = pin.pin_mask; + // Disable input for the given pin. + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 0 }); + } + + /// Configure the given pin as input. + pub fn setInput(comptime pin: type) void { + // To use pin Pxy as an input, bit y in the DIR register must be written to '0'. + // This can also be done by writing bit y in the DIRCLR register to '1'. + pin.gpio_port[pin.port_number].DIRCLR = pin.pin_mask; + // The input value can be read from bit y in register IN as soon as the INEN bit in the pin + // configuratation register is written to '1' to enable the pins input buffer. + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 1 }); + } + + /// Configure the given pin as input with pull-up. + pub fn setInputPullUp(comptime pin: type) void { + setInput(pin); + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); + // When enabling input with pull-up, bit y must be set to '1'. + write(pin, .high); + } + + /// Configure the given pin as input with pull-down. + pub fn setInputPullDown(comptime pin: type) void { + setInput(pin); + pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); + // When enabling input with pull-down, bit y must be set to '0'. + write(pin, .low); + } + + /// Check if the given pin is configured as output. + /// Returns true on success, false otherwise. + pub fn isOutput(comptime pin: type) bool { + return (pin.gpio_port[pin.port_number].DIR & pin.pin_mask) != 0; + } + + pub fn read(comptime pin: type) micro.gpio.State { + return if ((pin.gpio_port[pin.port_number].IN & pin.pin_mask) != 0) + micro.gpio.State.high + else + micro.gpio.State.low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + switch (state) { + .high => pin.gpio_port[pin.port_number].OUTSET = pin.pin_mask, + .low => pin.gpio_port[pin.port_number].OUTCLR = pin.pin_mask, + } + } + + pub fn toggle(comptime pin: type) void { + pin.gpio_port[pin.port_number].OUTTGL = pin.pin_mask; + } +}; + +// ############################################################################# +// Nonvolotile Memory Controller - NVMCTRL +// ############################################################################# + +pub fn nvmctrlInit() void { + regs.NVMCTRL.CTRLA.modify(.{ + .RWS = 5, // Number of wait states for a read operation + .AUTOWS = 1, // Enable wait states + }); +} + +// ############################################################################# +// Generic Clock Controller - GCLK +// ############################################################################# + +pub fn gclk2Init() void { + regs.GCLK.GENCTRL[2].modify(.{ + .DIV = 1, + .SRC = 6, // DFLL48M generator clock source + .GENEN = 1, // Enable generator + }); + + while (regs.GCLK.SYNCBUSY.read().GENCTRL & 2 != 0) { + // wait for sync + } +} + +// ############################################################################# +// UART +// ############################################################################# + +/// Calculate the BAUD register value based on the the expected output frequency +/// `fbaud` and the baud reference frequency `fref` (see data sheet p. 830). +pub fn asyncArithmeticBaudToRegister(fbaud: u32, fref: u32) u16 { + const fb = @intToFloat(f64, fbaud); + const fr = @intToFloat(f64, fref); + const res = 65536.0 * (1.0 - 16.0 * (fb / fr)); + + return @floatToInt(u16, res); +} + +/// Unique definitions for the chip, used by the microzig.uart.Config struct. +pub const uart = struct { + /// USART character size (p. 859). + pub const DataBits = enum(u3) { + eight = 0, + nine = 1, + five = 5, + six = 6, + seven = 7, + }; + + /// USART stop bits (p. 859). + pub const StopBits = enum(u1) { + one = 0, + tow = 1, + }; + + /// USART parity mode (p. 858). + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; +}; + +/// Instantiate a new USART interface. +/// +/// * `index` - SERCOM{index} should be used for UART +/// * `pins` - Not supported. Please use `.{ .tx = null, .rx = null }` +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (pins.tx != null or pins.rx != null) + @compileError("SAMD/E5x doesn't support custom pins"); + + return struct { + const UARTn = switch (index) { + 5 => regs.SERCOM5.USART_INT, + else => @compileError("Currently only SERCOM5:USART_INT supported."), + }; + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + switch (index) { + 5 => { + gclk2Init(); + + regs.GCLK.PCHCTRL[35].modify(.{ + .GEN = 2, // Generic clock generator 2 (see p. 156) + .CHEN = 1, // Enable peripheral channel + }); + + // When the APB clock is not provided to a module, its + // registers cannot be read or written. + regs.MCLK.APBDMASK.modify(.{ .SERCOM5_ = 1 }); + + // Enable the peripheral multiplexer selection. + regs.PORT.GROUP[1].PINCFG[16].modify(.{ .PMUXEN = 1 }); + regs.PORT.GROUP[1].PINCFG[17].modify(.{ .PMUXEN = 1 }); + + // Multiplex PB16 and PB17 to peripheral function C, i.e. + // SERCOM5 (see page 32 and 823). + regs.PORT.GROUP[1].PMUX[8].modify(.{ .PMUXE = 2, .PMUXO = 2 }); + }, + else => unreachable, + } + + // Some of the registers are enable-protected, meaning they can only + // be written when the USART is disabled. + UARTn.CTRLA.modify(.{ .ENABLE = 0 }); + + // Wait until synchronized. + while (UARTn.SYNCBUSY.read().ENABLE != 0) {} + + // Select USART with internal clock (0x1). + UARTn.CTRLA.modify(.{ + .MODE = 1, // Select USART with internal clock (0x01) + .CMODE = 0, // Select asynchronous communication mode (0x00) + // Pin selection (data sheet p. 854) + .RXPO = 1, // SERCOM PAD[1] is used for data reception + .TXPO = 0, // SERCOM PAD[0] is used for data transmition + .DORD = 1, // Configure data order (MSB = 0, LSB = 1) + .IBON = 1, // Immediate buffer overflow notification + .SAMPR = 0, // 16x over-sampling using arithmetic baud rate generation + }); + + // Configure parity mode. + if (config.parity != null) { + // Enable parity mode. + UARTn.CTRLA.modify(.{ .FORM = 1 }); // USART frame with parity + UARTn.CTRLB.modify(.{ .PMODE = @enumToInt(config.parity.?) }); + } else { + // Disable parity mode. + UARTn.CTRLA.modify(.{ .FORM = 0 }); // USART frame + } + + // Write the Baud register (internal clock mode) to generate the + // desired baud rate. + UARTn.BAUD.* = asyncArithmeticBaudToRegister(config.baud_rate, 48_000_000); //@intCast(u16, config.baud_rate); + + UARTn.CTRLB.modify(.{ + .CHSIZE = @enumToInt(config.data_bits), // Configure the character size filed. + .SBMODE = @enumToInt(config.stop_bits), // Configure the number of stop bits. + .RXEN = 1, // Enable the receiver + .TXEN = 1, // Enable the transmitter + }); + + //UARTn.INTENSET.modify(.{ .DRE = 1, .TXC = 1, .RXC = 1, .CTSIC = 1 }); + + while (UARTn.SYNCBUSY.raw != 0) {} + + // Enable the peripheral. + UARTn.CTRLA.modify(.{ .ENABLE = 1 }); + while (UARTn.SYNCBUSY.raw != 0) {} + + return Self{}; + } + + pub fn canWrite(self: Self) bool { + _ = self; + // The DRE flag ist set when DATA is empty and ready to be written. + // The DATA register should only be written to when INTFLAG.DRE is set. + return UARTn.INTFLAG.read().DRE == 1; + } + pub fn tx(self: Self, ch: u8) void { + while (!self.canWrite()) {} // Wait for Previous transmission + UARTn.DATA.* = ch; // Load the data to be transmitted + } + + pub fn canRead(self: Self) bool { + _ = self; + // The RXC flag ist set when there are unread data in DATA. + return UARTn.INTFLAG.read().RXC == 1; + } + pub fn rx(self: Self) u8 { + while (!self.canRead()) {} // Wait till the data is received + return @intCast(u8, UARTn.DATA.*); // Read received data + } + }; +} + +// ############################################################################# +// Crypto +// ############################################################################# + +pub fn enableTrng() void { + // Enable the TRNG bus clock. + regs.MCLK.APBCMASK.modify(.{ .TRNG_ = 1 }); +} + +pub const crypto = struct { + pub const random = struct { + /// Fill the given slice with random data. + pub fn getBlock(buffer: []u8) void { + var rand: u32 = undefined; + + var i: usize = 0; + while (i < buffer.len) : (i += 1) { + if (i % 4 == 0) { + // Get a fresh 32 bit integer every 4th iteration. + rand = getWord(); + } + + // The shift value is always between 0 and 24, i.e. int cast will always succeed. + buffer[i] = @intCast(u8, (rand >> @intCast(u5, (8 * (i % 4)))) & 0xff); + } + } + + /// Get a real 32 bit random integer. + /// + /// In most cases you'll want to use `getBlock` instead. + pub fn getWord() u32 { + regs.TRNG.CTRLA.modify(.{ .ENABLE = 1 }); + while (regs.TRNG.INTFLAG.read().DATARDY == 0) { + // a new random number is generated every + // 84 CLK_TRNG_APB clock cycles (p. 1421). + } + regs.TRNG.CTRLA.modify(.{ .ENABLE = 0 }); + return regs.TRNG.DATA.*; + } + + /// Get a real 8 bit random integer. + /// + /// In most cases you'll want to use `getBlock` instead. + pub fn getByte() u8 { + return @intCast(u8, getWord() & 0xFF); + } + }; +}; diff --git a/src/modules/chips/atsame51j20a/registers.zig b/src/modules/chips/atsame51j20a/registers.zig new file mode 100644 index 0000000..de11221 --- /dev/null +++ b/src/modules/chips/atsame51j20a/registers.zig @@ -0,0 +1,25436 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 4b04e50cf14a3df87662dc79863e9b7e3dfc6591 +// +// vendor: Microchip Technology +// device: ATSAME51J20A +// cpu: CM4 + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + MemManage: InterruptVector = unhandled, + BusFault: InterruptVector = unhandled, + UsageFault: InterruptVector = unhandled, + reserved0: [4]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + PM: InterruptVector = unhandled, + MCLK: InterruptVector = unhandled, + OSCCTRL_XOSC0: InterruptVector = unhandled, + OSCCTRL_XOSC1: InterruptVector = unhandled, + OSCCTRL_DFLL: InterruptVector = unhandled, + OSCCTRL_DPLL0: InterruptVector = unhandled, + OSCCTRL_DPLL1: InterruptVector = unhandled, + OSC32KCTRL: InterruptVector = unhandled, + SUPC_OTHER: InterruptVector = unhandled, + SUPC_BODDET: InterruptVector = unhandled, + WDT: InterruptVector = unhandled, + RTC: InterruptVector = unhandled, + EIC_EXTINT_0: InterruptVector = unhandled, + EIC_EXTINT_1: InterruptVector = unhandled, + EIC_EXTINT_2: InterruptVector = unhandled, + EIC_EXTINT_3: InterruptVector = unhandled, + EIC_EXTINT_4: InterruptVector = unhandled, + EIC_EXTINT_5: InterruptVector = unhandled, + EIC_EXTINT_6: InterruptVector = unhandled, + EIC_EXTINT_7: InterruptVector = unhandled, + EIC_EXTINT_8: InterruptVector = unhandled, + EIC_EXTINT_9: InterruptVector = unhandled, + EIC_EXTINT_10: InterruptVector = unhandled, + EIC_EXTINT_11: InterruptVector = unhandled, + EIC_EXTINT_12: InterruptVector = unhandled, + EIC_EXTINT_13: InterruptVector = unhandled, + EIC_EXTINT_14: InterruptVector = unhandled, + EIC_EXTINT_15: InterruptVector = unhandled, + FREQM: InterruptVector = unhandled, + NVMCTRL_0: InterruptVector = unhandled, + NVMCTRL_1: InterruptVector = unhandled, + DMAC_0: InterruptVector = unhandled, + DMAC_1: InterruptVector = unhandled, + DMAC_2: InterruptVector = unhandled, + DMAC_3: InterruptVector = unhandled, + DMAC_OTHER: InterruptVector = unhandled, + EVSYS_0: InterruptVector = unhandled, + EVSYS_1: InterruptVector = unhandled, + EVSYS_2: InterruptVector = unhandled, + EVSYS_3: InterruptVector = unhandled, + EVSYS_OTHER: InterruptVector = unhandled, + PAC: InterruptVector = unhandled, + reserved2: u32 = undefined, + reserved3: u32 = undefined, + reserved4: u32 = undefined, + RAMECC: InterruptVector = unhandled, + SERCOM0_0: InterruptVector = unhandled, + SERCOM0_1: InterruptVector = unhandled, + SERCOM0_2: InterruptVector = unhandled, + SERCOM0_OTHER: InterruptVector = unhandled, + SERCOM1_0: InterruptVector = unhandled, + SERCOM1_1: InterruptVector = unhandled, + SERCOM1_2: InterruptVector = unhandled, + SERCOM1_OTHER: InterruptVector = unhandled, + SERCOM2_0: InterruptVector = unhandled, + SERCOM2_1: InterruptVector = unhandled, + SERCOM2_2: InterruptVector = unhandled, + SERCOM2_OTHER: InterruptVector = unhandled, + SERCOM3_0: InterruptVector = unhandled, + SERCOM3_1: InterruptVector = unhandled, + SERCOM3_2: InterruptVector = unhandled, + SERCOM3_OTHER: InterruptVector = unhandled, + SERCOM4_0: InterruptVector = unhandled, + SERCOM4_1: InterruptVector = unhandled, + SERCOM4_2: InterruptVector = unhandled, + SERCOM4_OTHER: InterruptVector = unhandled, + SERCOM5_0: InterruptVector = unhandled, + SERCOM5_1: InterruptVector = unhandled, + SERCOM5_2: InterruptVector = unhandled, + SERCOM5_OTHER: InterruptVector = unhandled, + reserved5: u32 = undefined, + reserved6: u32 = undefined, + reserved7: u32 = undefined, + reserved8: u32 = undefined, + reserved9: u32 = undefined, + reserved10: u32 = undefined, + reserved11: u32 = undefined, + reserved12: u32 = undefined, + CAN0: InterruptVector = unhandled, + CAN1: InterruptVector = unhandled, + USB_OTHER: InterruptVector = unhandled, + USB_SOF_HSOF: InterruptVector = unhandled, + USB_TRCPT0: InterruptVector = unhandled, + USB_TRCPT1: InterruptVector = unhandled, + reserved13: u32 = undefined, + TCC0_OTHER: InterruptVector = unhandled, + TCC0_MC0: InterruptVector = unhandled, + TCC0_MC1: InterruptVector = unhandled, + TCC0_MC2: InterruptVector = unhandled, + TCC0_MC3: InterruptVector = unhandled, + TCC0_MC4: InterruptVector = unhandled, + TCC0_MC5: InterruptVector = unhandled, + TCC1_OTHER: InterruptVector = unhandled, + TCC1_MC0: InterruptVector = unhandled, + TCC1_MC1: InterruptVector = unhandled, + TCC1_MC2: InterruptVector = unhandled, + TCC1_MC3: InterruptVector = unhandled, + TCC2_OTHER: InterruptVector = unhandled, + TCC2_MC0: InterruptVector = unhandled, + TCC2_MC1: InterruptVector = unhandled, + TCC2_MC2: InterruptVector = unhandled, + TCC3_OTHER: InterruptVector = unhandled, + TCC3_MC0: InterruptVector = unhandled, + TCC3_MC1: InterruptVector = unhandled, + TCC4_OTHER: InterruptVector = unhandled, + TCC4_MC0: InterruptVector = unhandled, + TCC4_MC1: InterruptVector = unhandled, + TC0: InterruptVector = unhandled, + TC1: InterruptVector = unhandled, + TC2: InterruptVector = unhandled, + TC3: InterruptVector = unhandled, + TC4: InterruptVector = unhandled, + TC5: InterruptVector = unhandled, + reserved14: u32 = undefined, + reserved15: u32 = undefined, + PDEC_OTHER: InterruptVector = unhandled, + PDEC_MC0: InterruptVector = unhandled, + PDEC_MC1: InterruptVector = unhandled, + ADC0_OTHER: InterruptVector = unhandled, + ADC0_RESRDY: InterruptVector = unhandled, + ADC1_OTHER: InterruptVector = unhandled, + ADC1_RESRDY: InterruptVector = unhandled, + AC: InterruptVector = unhandled, + DAC_OTHER: InterruptVector = unhandled, + DAC_EMPTY_0: InterruptVector = unhandled, + DAC_EMPTY_1: InterruptVector = unhandled, + DAC_RESRDY_0: InterruptVector = unhandled, + DAC_RESRDY_1: InterruptVector = unhandled, + I2S: InterruptVector = unhandled, + PCC: InterruptVector = unhandled, + AES: InterruptVector = unhandled, + TRNG: InterruptVector = unhandled, + ICM: InterruptVector = unhandled, + reserved16: u32 = undefined, + QSPI: InterruptVector = unhandled, + SDHC0: InterruptVector = unhandled, +}; + +pub const registers = struct { + /// System Control Space + pub const SCS = struct { + pub const base_address = 0xe000e000; + + /// System Tick Timer + pub const SysTick = struct { + /// address: 0xe000e010 + /// SysTick Control and Status Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + COUNTFLAG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x10); + + /// address: 0xe000e014 + /// SysTick Reload Value Register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + RELOAD: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x14); + + /// address: 0xe000e018 + /// SysTick Current Value Register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + CURRENT: u24, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x18); + + /// address: 0xe000e01c + /// SysTick Calibration Register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + TENMS: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + SKEW: u1, + NOREF: u1, + }), base_address + 0x1c); + }; + }; + + /// Analog Comparators + pub const AC = struct { + pub const base_address = 0x42002000; + pub const version = "U25011.0.0"; + + /// address: 0x42002000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x42002001 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Start Comparison + START0: u1, + /// Comparator 1 Start Comparison + START1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1); + + /// address: 0x42002002 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Comparator 0 Event Output Enable + COMPEO0: u1, + /// Comparator 1 Event Output Enable + COMPEO1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Event Output Enable + WINEO0: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Comparator 0 Event Input Enable + COMPEI0: u1, + /// Comparator 1 Event Input Enable + COMPEI1: u1, + reserved5: u1, + reserved6: u1, + /// Comparator 0 Input Event Invert Enable + INVEI0: u1, + /// Comparator 1 Input Event Invert Enable + INVEI1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x42002004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Interrupt Enable + COMP0: u1, + /// Comparator 1 Interrupt Enable + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Interrupt Enable + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x4); + + /// address: 0x42002005 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Interrupt Enable + COMP0: u1, + /// Comparator 1 Interrupt Enable + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Interrupt Enable + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x5); + + /// address: 0x42002006 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 + COMP0: u1, + /// Comparator 1 + COMP1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 + WIN0: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x6); + + /// address: 0x42002007 + /// Status A + pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Current State + STATE0: u1, + /// Comparator 1 Current State + STATE1: u1, + reserved0: u1, + reserved1: u1, + /// Window 0 Current State + WSTATE0: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x7); + + /// address: 0x42002008 + /// Status B + pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { + /// Comparator 0 Ready + READY0: u1, + /// Comparator 1 Ready + READY1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x42002009 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200200a + /// Window Control + pub const WINCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Window 0 Mode Enable + WEN0: u1, + /// Window 0 Interrupt Selection + WINTSEL0: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xa); + + /// address: 0x4200200c + /// Scaler n + pub const SCALER = @intToPtr(*volatile [2]Mmio(8, packed struct { + /// Scaler Value + VALUE: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x42002010 + /// Comparator Control n + pub const COMPCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Single-Shot Mode + SINGLE: u1, + /// Interrupt Selection + INTSEL: u2, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + /// Negative Input Mux Selection + MUXNEG: u3, + reserved3: u1, + /// Positive Input Mux Selection + MUXPOS: u3, + /// Swap Inputs and Invert + SWAP: u1, + /// Speed Selection + SPEED: u2, + reserved4: u1, + /// Hysteresis Enable + HYSTEN: u1, + /// Hysteresis Level + HYST: u2, + reserved5: u1, + reserved6: u1, + /// Filter Length + FLEN: u3, + reserved7: u1, + /// Output + OUT: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x42002020 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// WINCTRL Synchronization Busy + WINCTRL: u1, + /// COMPCTRL 0 Synchronization Busy + COMPCTRL0: u1, + /// COMPCTRL 1 Synchronization Busy + COMPCTRL1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x20); + + /// address: 0x42002024 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// COMP0/1 Bias Scaling + BIAS0: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x24); + }; + + /// Analog Digital Converter + pub const ADC0 = struct { + pub const base_address = 0x43001c00; + pub const version = "U25001.0.0"; + + /// address: 0x43001c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + /// Dual Mode Trigger Selection + DUALSEL: u2, + /// Slave Enable + SLAVEEN: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Prescaler Configuration + PRESCALER: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Rail to Rail Operation Enable + R2R: u1, + }), base_address + 0x0); + + /// address: 0x43001c02 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Flush Event Input Enable + FLUSHEI: u1, + /// Start Conversion Event Input Enable + STARTEI: u1, + /// Flush Event Invert Enable + FLUSHINV: u1, + /// Start Conversion Event Invert Enable + STARTINV: u1, + /// Result Ready Event Out + RESRDYEO: u1, + /// Window Monitor Event Out + WINMONEO: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x43001c03 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x43001c04 + /// Input Control + pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Positive Mux Input Selection + MUXPOS: u5, + reserved0: u1, + reserved1: u1, + /// Differential Mode + DIFFMODE: u1, + /// Negative Mux Input Selection + MUXNEG: u5, + reserved2: u1, + reserved3: u1, + /// Stop DMA Sequencing + DSEQSTOP: u1, + }), base_address + 0x4); + + /// address: 0x43001c06 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Left-Adjusted Result + LEFTADJ: u1, + /// Free Running Mode + FREERUN: u1, + /// Digital Correction Logic Enable + CORREN: u1, + /// Conversion Result Resolution + RESSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Window Monitor Mode + WINMODE: u3, + /// Window Single Sample + WINSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x6); + + /// address: 0x43001c08 + /// Reference Control + pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Reference Selection + REFSEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Reference Buffer Offset Compensation Enable + REFCOMP: u1, + }), base_address + 0x8); + + /// address: 0x43001c0a + /// Average Control + pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Number of Samples to be Collected + SAMPLENUM: u4, + /// Adjusting Result / Division Coefficient + ADJRES: u3, + padding0: u1, + }), base_address + 0xa); + + /// address: 0x43001c0b + /// Sample Time Control + pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Sampling Time Length + SAMPLEN: u6, + reserved0: u1, + /// Comparator Offset Compensation Enable + OFFCOMP: u1, + }), base_address + 0xb); + + /// address: 0x43001c0c + /// Window Monitor Lower Threshold + pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x43001c0e + /// Window Monitor Upper Threshold + pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); + + /// address: 0x43001c10 + /// Gain Correction + pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); + + /// address: 0x43001c12 + /// Offset Correction + pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); + + /// address: 0x43001c14 + /// Software Trigger + pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Conversion Flush + FLUSH: u1, + /// Start ADC Conversion + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x43001c2c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Disable + RESRDY: u1, + /// Overrun Interrupt Disable + OVERRUN: u1, + /// Window Monitor Interrupt Disable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x43001c2d + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Enable + RESRDY: u1, + /// Overrun Interrupt Enable + OVERRUN: u1, + /// Window Monitor Interrupt Enable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2d); + + /// address: 0x43001c2e + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Flag + RESRDY: u1, + /// Overrun Interrupt Flag + OVERRUN: u1, + /// Window Monitor Interrupt Flag + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2e); + + /// address: 0x43001c2f + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Busy Status + ADCBUSY: u1, + reserved0: u1, + /// Window Comparator Counter + WCC: u6, + }), base_address + 0x2f); + + /// address: 0x43001c30 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// SWRST Synchronization Busy + SWRST: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// Input Control Synchronization Busy + INPUTCTRL: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Reference Control Synchronization Busy + REFCTRL: u1, + /// Average Control Synchronization Busy + AVGCTRL: u1, + /// Sampling Time Control Synchronization Busy + SAMPCTRL: u1, + /// Window Monitor Lower Threshold Synchronization Busy + WINLT: u1, + /// Window Monitor Upper Threshold Synchronization Busy + WINUT: u1, + /// Gain Correction Synchronization Busy + GAINCORR: u1, + /// Offset Correction Synchronization Busy + OFFSETCORR: u1, + /// Software Trigger Synchronization Busy + SWTRIG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x43001c34 + /// DMA Sequencial Data + pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Sequential Data + DATA: u32, + }), base_address + 0x34); + + /// address: 0x43001c38 + /// DMA Sequential Control + pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADC Auto-Start Conversion + AUTOSTART: u1, + }), base_address + 0x38); + + /// address: 0x43001c3c + /// DMA Sequencial Status + pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// DMA Sequencing Busy + BUSY: u1, + }), base_address + 0x3c); + + /// address: 0x43001c40 + /// Result Conversion Value + pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); + + /// address: 0x43001c44 + /// Last Sample Result + pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); + + /// address: 0x43001c48 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// Bias Comparator Scaling + BIASCOMP: u3, + reserved0: u1, + /// Bias R2R Ampli scaling + BIASR2R: u3, + reserved1: u1, + /// Bias Reference Buffer Scaling + BIASREFBUF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x48); + }; + pub const ADC1 = struct { + pub const base_address = 0x43002000; + + /// address: 0x43002000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + /// Dual Mode Trigger Selection + DUALSEL: u2, + /// Slave Enable + SLAVEEN: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Prescaler Configuration + PRESCALER: u3, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Rail to Rail Operation Enable + R2R: u1, + }), base_address + 0x0); + + /// address: 0x43002002 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Flush Event Input Enable + FLUSHEI: u1, + /// Start Conversion Event Input Enable + STARTEI: u1, + /// Flush Event Invert Enable + FLUSHINV: u1, + /// Start Conversion Event Invert Enable + STARTINV: u1, + /// Result Ready Event Out + RESRDYEO: u1, + /// Window Monitor Event Out + WINMONEO: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x2); + + /// address: 0x43002003 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x43002004 + /// Input Control + pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Positive Mux Input Selection + MUXPOS: u5, + reserved0: u1, + reserved1: u1, + /// Differential Mode + DIFFMODE: u1, + /// Negative Mux Input Selection + MUXNEG: u5, + reserved2: u1, + reserved3: u1, + /// Stop DMA Sequencing + DSEQSTOP: u1, + }), base_address + 0x4); + + /// address: 0x43002006 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Left-Adjusted Result + LEFTADJ: u1, + /// Free Running Mode + FREERUN: u1, + /// Digital Correction Logic Enable + CORREN: u1, + /// Conversion Result Resolution + RESSEL: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Window Monitor Mode + WINMODE: u3, + /// Window Single Sample + WINSS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x6); + + /// address: 0x43002008 + /// Reference Control + pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Reference Selection + REFSEL: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Reference Buffer Offset Compensation Enable + REFCOMP: u1, + }), base_address + 0x8); + + /// address: 0x4300200a + /// Average Control + pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Number of Samples to be Collected + SAMPLENUM: u4, + /// Adjusting Result / Division Coefficient + ADJRES: u3, + padding0: u1, + }), base_address + 0xa); + + /// address: 0x4300200b + /// Sample Time Control + pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Sampling Time Length + SAMPLEN: u6, + reserved0: u1, + /// Comparator Offset Compensation Enable + OFFCOMP: u1, + }), base_address + 0xb); + + /// address: 0x4300200c + /// Window Monitor Lower Threshold + pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4300200e + /// Window Monitor Upper Threshold + pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); + + /// address: 0x43002010 + /// Gain Correction + pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); + + /// address: 0x43002012 + /// Offset Correction + pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); + + /// address: 0x43002014 + /// Software Trigger + pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Conversion Flush + FLUSH: u1, + /// Start ADC Conversion + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x4300202c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Disable + RESRDY: u1, + /// Overrun Interrupt Disable + OVERRUN: u1, + /// Window Monitor Interrupt Disable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x4300202d + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Enable + RESRDY: u1, + /// Overrun Interrupt Enable + OVERRUN: u1, + /// Window Monitor Interrupt Enable + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2d); + + /// address: 0x4300202e + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result Ready Interrupt Flag + RESRDY: u1, + /// Overrun Interrupt Flag + OVERRUN: u1, + /// Window Monitor Interrupt Flag + WINMON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2e); + + /// address: 0x4300202f + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ADC Busy Status + ADCBUSY: u1, + reserved0: u1, + /// Window Comparator Counter + WCC: u6, + }), base_address + 0x2f); + + /// address: 0x43002030 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// SWRST Synchronization Busy + SWRST: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// Input Control Synchronization Busy + INPUTCTRL: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Reference Control Synchronization Busy + REFCTRL: u1, + /// Average Control Synchronization Busy + AVGCTRL: u1, + /// Sampling Time Control Synchronization Busy + SAMPCTRL: u1, + /// Window Monitor Lower Threshold Synchronization Busy + WINLT: u1, + /// Window Monitor Upper Threshold Synchronization Busy + WINUT: u1, + /// Gain Correction Synchronization Busy + GAINCORR: u1, + /// Offset Correction Synchronization Busy + OFFSETCORR: u1, + /// Software Trigger Synchronization Busy + SWTRIG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x30); + + /// address: 0x43002034 + /// DMA Sequencial Data + pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Sequential Data + DATA: u32, + }), base_address + 0x34); + + /// address: 0x43002038 + /// DMA Sequential Control + pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// ADC Auto-Start Conversion + AUTOSTART: u1, + }), base_address + 0x38); + + /// address: 0x4300203c + /// DMA Sequencial Status + pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Input Control + INPUTCTRL: u1, + /// Control B + CTRLB: u1, + /// Reference Control + REFCTRL: u1, + /// Average Control + AVGCTRL: u1, + /// Sampling Time Control + SAMPCTRL: u1, + /// Window Monitor Lower Threshold + WINLT: u1, + /// Window Monitor Upper Threshold + WINUT: u1, + /// Gain Correction + GAINCORR: u1, + /// Offset Correction + OFFSETCORR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// DMA Sequencing Busy + BUSY: u1, + }), base_address + 0x3c); + + /// address: 0x43002040 + /// Result Conversion Value + pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); + + /// address: 0x43002044 + /// Last Sample Result + pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); + + /// address: 0x43002048 + /// Calibration + pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { + /// Bias Comparator Scaling + BIASCOMP: u3, + reserved0: u1, + /// Bias R2R Ampli scaling + BIASR2R: u3, + reserved1: u1, + /// Bias Reference Buffer Scaling + BIASREFBUF: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x48); + }; + + /// Advanced Encryption Standard + pub const AES = struct { + pub const base_address = 0x42002400; + pub const version = "U22382.2.0"; + + /// address: 0x42002400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// AES Modes of operation + AESMODE: u3, + /// Cipher Feedback Block Size + CFBS: u3, + /// Encryption Key Size + KEYSIZE: u2, + /// Cipher Mode + CIPHER: u1, + /// Start Mode Select + STARTMODE: u1, + /// Last Output Data Mode + LOD: u1, + /// Last Key Generation + KEYGEN: u1, + /// XOR Key Operation + XORKEY: u1, + reserved0: u1, + /// Counter Measure Type + CTYPE: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x0); + + /// address: 0x42002404 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Encryption/Decryption + START: u1, + /// New message + NEWMSG: u1, + /// End of message + EOM: u1, + /// GF Multiplication + GFMUL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x42002405 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete Interrupt Enable + ENCCMP: u1, + /// GF Multiplication Complete Interrupt Enable + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x5); + + /// address: 0x42002406 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete Interrupt Enable + ENCCMP: u1, + /// GF Multiplication Complete Interrupt Enable + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x6); + + /// address: 0x42002407 + /// Interrupt Flag Status + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Encryption Complete + ENCCMP: u1, + /// GF Multiplication Complete + GFMCMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x7); + + /// address: 0x42002408 + /// Data buffer pointer + pub const DATABUFPTR = @intToPtr(*volatile Mmio(8, packed struct { + /// Input Data Pointer + INDATAPTR: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x42002409 + /// Debug control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200240c + /// Keyword n + pub const KEYWORD = @intToPtr(*volatile [8]u32, base_address + 0xc); + + /// address: 0x42002438 + /// Indata + pub const INDATA = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x4200243c + /// Initialisation Vector n + pub const INTVECTV = @intToPtr(*volatile [4]u32, base_address + 0x3c); + + /// address: 0x4200245c + /// Hash key n + pub const HASHKEY = @intToPtr(*volatile [4]u32, base_address + 0x5c); + + /// address: 0x4200246c + /// Galois Hash n + pub const GHASH = @intToPtr(*volatile [4]u32, base_address + 0x6c); + + /// address: 0x42002480 + /// Cipher Length + pub const CIPLEN = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x42002484 + /// Random Seed + pub const RANDSEED = @intToPtr(*volatile u32, base_address + 0x84); + }; + + /// Control Area Network + pub const CAN0 = struct { + pub const base_address = 0x42000000; + pub const version = "U20033.2.1"; + + /// address: 0x42000000 + /// Core Release + pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Sub-step of Core Release + SUBSTEP: u4, + /// Step of Core Release + STEP: u4, + /// Core Release + REL: u4, + }), base_address + 0x0); + + /// address: 0x42000004 + /// Endian + pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { + /// Endianness Test Value + ETV: u32, + }), base_address + 0x4); + + /// address: 0x42000008 + /// Message RAM Configuration + pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Quality of Service + QOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4200000c + /// Fast Bit Timing and Prescaler + pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Data (Re)Synchronization Jump Width + DSJW: u4, + /// Data time segment after sample point + DTSEG2: u4, + /// Data time segment before sample point + DTSEG1: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Baud Rate Prescaler + DBRP: u5, + reserved3: u1, + reserved4: u1, + /// Tranceiver Delay Compensation + TDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x42000010 + /// Test + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Loop Back Mode + LBCK: u1, + /// Control of Transmit Pin + TX: u2, + /// Receive Pin + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x42000014 + /// RAM Watchdog + pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog Configuration + WDC: u8, + /// Watchdog Value + WDV: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x42000018 + /// CC Control + pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Initialization + INIT: u1, + /// Configuration Change Enable + CCE: u1, + /// ASM Restricted Operation Mode + ASM: u1, + /// Clock Stop Acknowledge + CSA: u1, + /// Clock Stop Request + CSR: u1, + /// Bus Monitoring Mode + MON: u1, + /// Disable Automatic Retransmission + DAR: u1, + /// Test Mode Enable + TEST: u1, + /// FD Operation Enable + FDOE: u1, + /// Bit Rate Switch Enable + BRSE: u1, + reserved0: u1, + reserved1: u1, + /// Protocol Exception Handling Disable + PXHD: u1, + /// Edge Filtering during Bus Integration + EFBI: u1, + /// Transmit Pause + TXP: u1, + /// Non ISO Operation + NISO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4200001c + /// Nominal Bit Timing and Prescaler + pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Nominal Time segment after sample point + NTSEG2: u7, + reserved0: u1, + /// Nominal Time segment before sample point + NTSEG1: u8, + /// Nominal Baud Rate Prescaler + NBRP: u9, + /// Nominal (Re)Synchronization Jump Width + NSJW: u7, + }), base_address + 0x1c); + + /// address: 0x42000020 + /// Timestamp Counter Configuration + pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Select + TSS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Timestamp Counter Prescaler + TCP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x20); + + /// address: 0x42000024 + /// Timestamp Counter Value + pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Counter + TSC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x42000028 + /// Timeout Counter Configuration + pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Timeout Counter + ETOC: u1, + /// Timeout Select + TOS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Timeout Period + TOP: u16, + }), base_address + 0x28); + + /// address: 0x4200002c + /// Timeout Counter Value + pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Counter + TOC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x42000040 + /// Error Counter + pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Error Counter + TEC: u8, + /// Receive Error Counter + REC: u7, + /// Receive Error Passive + RP: u1, + /// CAN Error Logging + CEL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000044 + /// Protocol Status + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Last Error Code + LEC: u3, + /// Activity + ACT: u2, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Data Phase Last Error Code + DLEC: u3, + /// ESI flag of last received CAN FD Message + RESI: u1, + /// BRS flag of last received CAN FD Message + RBRS: u1, + /// Received a CAN FD Message + RFDF: u1, + /// Protocol Exception Event + PXE: u1, + reserved0: u1, + /// Transmitter Delay Compensation Value + TDCV: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x44); + + /// address: 0x42000048 + /// Extended ID Filter Configuration + pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmitter Delay Compensation Filter Length + TDCF: u7, + reserved0: u1, + /// Transmitter Delay Compensation Offset + TDCO: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x48); + + /// address: 0x42000050 + /// Interrupt + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message + RF0N: u1, + /// Rx FIFO 0 Watermark Reached + RF0W: u1, + /// Rx FIFO 0 Full + RF0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + /// Rx FIFO 1 New Message + RF1N: u1, + /// Rx FIFO 1 Watermark Reached + RF1W: u1, + /// Rx FIFO 1 FIFO Full + RF1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + /// High Priority Message + HPM: u1, + /// Timestamp Completed + TC: u1, + /// Transmission Cancellation Finished + TCF: u1, + /// Tx FIFO Empty + TFE: u1, + /// Tx Event FIFO New Entry + TEFN: u1, + /// Tx Event FIFO Watermark Reached + TEFW: u1, + /// Tx Event FIFO Full + TEFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + /// Timestamp Wraparound + TSW: u1, + /// Message RAM Access Failure + MRAF: u1, + /// Timeout Occurred + TOO: u1, + /// Message stored to Dedicated Rx Buffer + DRX: u1, + /// Bit Error Corrected + BEC: u1, + /// Bit Error Uncorrected + BEU: u1, + /// Error Logging Overflow + ELO: u1, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Watchdog Interrupt + WDI: u1, + /// Protocol Error in Arbitration Phase + PEA: u1, + /// Protocol Error in Data Phase + PED: u1, + /// Access to Reserved Address + ARA: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x50); + + /// address: 0x42000054 + /// Interrupt Enable + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Enable + RF0NE: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Enable + RF0WE: u1, + /// Rx FIFO 0 Full Interrupt Enable + RF0FE: u1, + /// Rx FIFO 0 Message Lost Interrupt Enable + RF0LE: u1, + /// Rx FIFO 1 New Message Interrupt Enable + RF1NE: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Enable + RF1WE: u1, + /// Rx FIFO 1 FIFO Full Interrupt Enable + RF1FE: u1, + /// Rx FIFO 1 Message Lost Interrupt Enable + RF1LE: u1, + /// High Priority Message Interrupt Enable + HPME: u1, + /// Timestamp Completed Interrupt Enable + TCE: u1, + /// Transmission Cancellation Finished Interrupt Enable + TCFE: u1, + /// Tx FIFO Empty Interrupt Enable + TFEE: u1, + /// Tx Event FIFO New Entry Interrupt Enable + TEFNE: u1, + /// Tx Event FIFO Watermark Reached Interrupt Enable + TEFWE: u1, + /// Tx Event FIFO Full Interrupt Enable + TEFFE: u1, + /// Tx Event FIFO Element Lost Interrupt Enable + TEFLE: u1, + /// Timestamp Wraparound Interrupt Enable + TSWE: u1, + /// Message RAM Access Failure Interrupt Enable + MRAFE: u1, + /// Timeout Occurred Interrupt Enable + TOOE: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Enable + DRXE: u1, + /// Bit Error Corrected Interrupt Enable + BECE: u1, + /// Bit Error Uncorrected Interrupt Enable + BEUE: u1, + /// Error Logging Overflow Interrupt Enable + ELOE: u1, + /// Error Passive Interrupt Enable + EPE: u1, + /// Warning Status Interrupt Enable + EWE: u1, + /// Bus_Off Status Interrupt Enable + BOE: u1, + /// Watchdog Interrupt Interrupt Enable + WDIE: u1, + /// Protocol Error in Arbitration Phase Enable + PEAE: u1, + /// Protocol Error in Data Phase Enable + PEDE: u1, + /// Access to Reserved Address Enable + ARAE: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x54); + + /// address: 0x42000058 + /// Interrupt Line Select + pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Line + RF0NL: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Line + RF0WL: u1, + /// Rx FIFO 0 Full Interrupt Line + RF0FL: u1, + /// Rx FIFO 0 Message Lost Interrupt Line + RF0LL: u1, + /// Rx FIFO 1 New Message Interrupt Line + RF1NL: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Line + RF1WL: u1, + /// Rx FIFO 1 FIFO Full Interrupt Line + RF1FL: u1, + /// Rx FIFO 1 Message Lost Interrupt Line + RF1LL: u1, + /// High Priority Message Interrupt Line + HPML: u1, + /// Timestamp Completed Interrupt Line + TCL: u1, + /// Transmission Cancellation Finished Interrupt Line + TCFL: u1, + /// Tx FIFO Empty Interrupt Line + TFEL: u1, + /// Tx Event FIFO New Entry Interrupt Line + TEFNL: u1, + /// Tx Event FIFO Watermark Reached Interrupt Line + TEFWL: u1, + /// Tx Event FIFO Full Interrupt Line + TEFFL: u1, + /// Tx Event FIFO Element Lost Interrupt Line + TEFLL: u1, + /// Timestamp Wraparound Interrupt Line + TSWL: u1, + /// Message RAM Access Failure Interrupt Line + MRAFL: u1, + /// Timeout Occurred Interrupt Line + TOOL: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Line + DRXL: u1, + /// Bit Error Corrected Interrupt Line + BECL: u1, + /// Bit Error Uncorrected Interrupt Line + BEUL: u1, + /// Error Logging Overflow Interrupt Line + ELOL: u1, + /// Error Passive Interrupt Line + EPL: u1, + /// Warning Status Interrupt Line + EWL: u1, + /// Bus_Off Status Interrupt Line + BOL: u1, + /// Watchdog Interrupt Interrupt Line + WDIL: u1, + /// Protocol Error in Arbitration Phase Line + PEAL: u1, + /// Protocol Error in Data Phase Line + PEDL: u1, + /// Access to Reserved Address Line + ARAL: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x58); + + /// address: 0x4200005c + /// Interrupt Line Enable + pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Interrupt Line 0 + EINT0: u1, + /// Enable Interrupt Line 1 + EINT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x5c); + + /// address: 0x42000080 + /// Global Filter Configuration + pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Reject Remote Frames Extended + RRFE: u1, + /// Reject Remote Frames Standard + RRFS: u1, + /// Accept Non-matching Frames Extended + ANFE: u2, + /// Accept Non-matching Frames Standard + ANFS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x80); + + /// address: 0x42000084 + /// Standard ID Filter Configuration + pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Standard Start Address + FLSSA: u16, + /// List Size Standard + LSS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x84); + + /// address: 0x42000088 + /// Extended ID Filter Configuration + pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Extended Start Address + FLESA: u16, + /// List Size Extended + LSE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x88); + + /// address: 0x42000090 + /// Extended ID AND Mask + pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { + /// Extended ID Mask + EIDM: u29, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x90); + + /// address: 0x42000094 + /// High Priority Message Status + pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Index + BIDX: u6, + /// Message Storage Indicator + MSI: u2, + /// Filter Index + FIDX: u7, + /// Filter List + FLST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x42000098 + /// New Data 1 + pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 0 + ND0: u1, + /// New Data 1 + ND1: u1, + /// New Data 2 + ND2: u1, + /// New Data 3 + ND3: u1, + /// New Data 4 + ND4: u1, + /// New Data 5 + ND5: u1, + /// New Data 6 + ND6: u1, + /// New Data 7 + ND7: u1, + /// New Data 8 + ND8: u1, + /// New Data 9 + ND9: u1, + /// New Data 10 + ND10: u1, + /// New Data 11 + ND11: u1, + /// New Data 12 + ND12: u1, + /// New Data 13 + ND13: u1, + /// New Data 14 + ND14: u1, + /// New Data 15 + ND15: u1, + /// New Data 16 + ND16: u1, + /// New Data 17 + ND17: u1, + /// New Data 18 + ND18: u1, + /// New Data 19 + ND19: u1, + /// New Data 20 + ND20: u1, + /// New Data 21 + ND21: u1, + /// New Data 22 + ND22: u1, + /// New Data 23 + ND23: u1, + /// New Data 24 + ND24: u1, + /// New Data 25 + ND25: u1, + /// New Data 26 + ND26: u1, + /// New Data 27 + ND27: u1, + /// New Data 28 + ND28: u1, + /// New Data 29 + ND29: u1, + /// New Data 30 + ND30: u1, + /// New Data 31 + ND31: u1, + }), base_address + 0x98); + + /// address: 0x4200009c + /// New Data 2 + pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 32 + ND32: u1, + /// New Data 33 + ND33: u1, + /// New Data 34 + ND34: u1, + /// New Data 35 + ND35: u1, + /// New Data 36 + ND36: u1, + /// New Data 37 + ND37: u1, + /// New Data 38 + ND38: u1, + /// New Data 39 + ND39: u1, + /// New Data 40 + ND40: u1, + /// New Data 41 + ND41: u1, + /// New Data 42 + ND42: u1, + /// New Data 43 + ND43: u1, + /// New Data 44 + ND44: u1, + /// New Data 45 + ND45: u1, + /// New Data 46 + ND46: u1, + /// New Data 47 + ND47: u1, + /// New Data 48 + ND48: u1, + /// New Data 49 + ND49: u1, + /// New Data 50 + ND50: u1, + /// New Data 51 + ND51: u1, + /// New Data 52 + ND52: u1, + /// New Data 53 + ND53: u1, + /// New Data 54 + ND54: u1, + /// New Data 55 + ND55: u1, + /// New Data 56 + ND56: u1, + /// New Data 57 + ND57: u1, + /// New Data 58 + ND58: u1, + /// New Data 59 + ND59: u1, + /// New Data 60 + ND60: u1, + /// New Data 61 + ND61: u1, + /// New Data 62 + ND62: u1, + /// New Data 63 + ND63: u1, + }), base_address + 0x9c); + + /// address: 0x420000a0 + /// Rx FIFO 0 Configuration + pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Start Address + F0SA: u16, + /// Rx FIFO 0 Size + F0S: u7, + reserved0: u1, + /// Rx FIFO 0 Watermark + F0WM: u7, + /// FIFO 0 Operation Mode + F0OM: u1, + }), base_address + 0xa0); + + /// address: 0x420000a4 + /// Rx FIFO 0 Status + pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Fill Level + F0FL: u7, + reserved0: u1, + /// Rx FIFO 0 Get Index + F0GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 0 Put Index + F0PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 0 Full + F0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa4); + + /// address: 0x420000a8 + /// Rx FIFO 0 Acknowledge + pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Acknowledge Index + F0AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xa8); + + /// address: 0x420000ac + /// Rx Buffer Configuration + pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx Buffer Start Address + RBSA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x420000b0 + /// Rx FIFO 1 Configuration + pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Start Address + F1SA: u16, + /// Rx FIFO 1 Size + F1S: u7, + reserved0: u1, + /// Rx FIFO 1 Watermark + F1WM: u7, + /// FIFO 1 Operation Mode + F1OM: u1, + }), base_address + 0xb0); + + /// address: 0x420000b4 + /// Rx FIFO 1 Status + pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Fill Level + F1FL: u7, + reserved0: u1, + /// Rx FIFO 1 Get Index + F1GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 1 Put Index + F1PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 1 Full + F1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debug Message Status + DMS: u2, + }), base_address + 0xb4); + + /// address: 0x420000b8 + /// Rx FIFO 1 Acknowledge + pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Acknowledge Index + F1AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xb8); + + /// address: 0x420000bc + /// Rx Buffer / FIFO Element Size Configuration + pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Data Field Size + F0DS: u3, + reserved0: u1, + /// Rx FIFO 1 Data Field Size + F1DS: u3, + reserved1: u1, + /// Rx Buffer Data Field Size + RBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xbc); + + /// address: 0x420000c0 + /// Tx Buffer Configuration + pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffers Start Address + TBSA: u16, + /// Number of Dedicated Transmit Buffers + NDTB: u6, + reserved0: u1, + reserved1: u1, + /// Transmit FIFO/Queue Size + TFQS: u6, + /// Tx FIFO/Queue Mode + TFQM: u1, + padding0: u1, + }), base_address + 0xc0); + + /// address: 0x420000c4 + /// Tx FIFO / Queue Status + pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx FIFO Free Level + TFFL: u6, + reserved0: u1, + reserved1: u1, + /// Tx FIFO Get Index + TFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tx FIFO/Queue Put Index + TFQPI: u5, + /// Tx FIFO/Queue Full + TFQF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc4); + + /// address: 0x420000c8 + /// Tx Buffer Element Size Configuration + pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Data Field Size + TBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc8); + + /// address: 0x420000cc + /// Tx Buffer Request Pending + pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request Pending 0 + TRP0: u1, + /// Transmission Request Pending 1 + TRP1: u1, + /// Transmission Request Pending 2 + TRP2: u1, + /// Transmission Request Pending 3 + TRP3: u1, + /// Transmission Request Pending 4 + TRP4: u1, + /// Transmission Request Pending 5 + TRP5: u1, + /// Transmission Request Pending 6 + TRP6: u1, + /// Transmission Request Pending 7 + TRP7: u1, + /// Transmission Request Pending 8 + TRP8: u1, + /// Transmission Request Pending 9 + TRP9: u1, + /// Transmission Request Pending 10 + TRP10: u1, + /// Transmission Request Pending 11 + TRP11: u1, + /// Transmission Request Pending 12 + TRP12: u1, + /// Transmission Request Pending 13 + TRP13: u1, + /// Transmission Request Pending 14 + TRP14: u1, + /// Transmission Request Pending 15 + TRP15: u1, + /// Transmission Request Pending 16 + TRP16: u1, + /// Transmission Request Pending 17 + TRP17: u1, + /// Transmission Request Pending 18 + TRP18: u1, + /// Transmission Request Pending 19 + TRP19: u1, + /// Transmission Request Pending 20 + TRP20: u1, + /// Transmission Request Pending 21 + TRP21: u1, + /// Transmission Request Pending 22 + TRP22: u1, + /// Transmission Request Pending 23 + TRP23: u1, + /// Transmission Request Pending 24 + TRP24: u1, + /// Transmission Request Pending 25 + TRP25: u1, + /// Transmission Request Pending 26 + TRP26: u1, + /// Transmission Request Pending 27 + TRP27: u1, + /// Transmission Request Pending 28 + TRP28: u1, + /// Transmission Request Pending 29 + TRP29: u1, + /// Transmission Request Pending 30 + TRP30: u1, + /// Transmission Request Pending 31 + TRP31: u1, + }), base_address + 0xcc); + + /// address: 0x420000d0 + /// Tx Buffer Add Request + pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Add Request 0 + AR0: u1, + /// Add Request 1 + AR1: u1, + /// Add Request 2 + AR2: u1, + /// Add Request 3 + AR3: u1, + /// Add Request 4 + AR4: u1, + /// Add Request 5 + AR5: u1, + /// Add Request 6 + AR6: u1, + /// Add Request 7 + AR7: u1, + /// Add Request 8 + AR8: u1, + /// Add Request 9 + AR9: u1, + /// Add Request 10 + AR10: u1, + /// Add Request 11 + AR11: u1, + /// Add Request 12 + AR12: u1, + /// Add Request 13 + AR13: u1, + /// Add Request 14 + AR14: u1, + /// Add Request 15 + AR15: u1, + /// Add Request 16 + AR16: u1, + /// Add Request 17 + AR17: u1, + /// Add Request 18 + AR18: u1, + /// Add Request 19 + AR19: u1, + /// Add Request 20 + AR20: u1, + /// Add Request 21 + AR21: u1, + /// Add Request 22 + AR22: u1, + /// Add Request 23 + AR23: u1, + /// Add Request 24 + AR24: u1, + /// Add Request 25 + AR25: u1, + /// Add Request 26 + AR26: u1, + /// Add Request 27 + AR27: u1, + /// Add Request 28 + AR28: u1, + /// Add Request 29 + AR29: u1, + /// Add Request 30 + AR30: u1, + /// Add Request 31 + AR31: u1, + }), base_address + 0xd0); + + /// address: 0x420000d4 + /// Tx Buffer Cancellation Request + pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Request 0 + CR0: u1, + /// Cancellation Request 1 + CR1: u1, + /// Cancellation Request 2 + CR2: u1, + /// Cancellation Request 3 + CR3: u1, + /// Cancellation Request 4 + CR4: u1, + /// Cancellation Request 5 + CR5: u1, + /// Cancellation Request 6 + CR6: u1, + /// Cancellation Request 7 + CR7: u1, + /// Cancellation Request 8 + CR8: u1, + /// Cancellation Request 9 + CR9: u1, + /// Cancellation Request 10 + CR10: u1, + /// Cancellation Request 11 + CR11: u1, + /// Cancellation Request 12 + CR12: u1, + /// Cancellation Request 13 + CR13: u1, + /// Cancellation Request 14 + CR14: u1, + /// Cancellation Request 15 + CR15: u1, + /// Cancellation Request 16 + CR16: u1, + /// Cancellation Request 17 + CR17: u1, + /// Cancellation Request 18 + CR18: u1, + /// Cancellation Request 19 + CR19: u1, + /// Cancellation Request 20 + CR20: u1, + /// Cancellation Request 21 + CR21: u1, + /// Cancellation Request 22 + CR22: u1, + /// Cancellation Request 23 + CR23: u1, + /// Cancellation Request 24 + CR24: u1, + /// Cancellation Request 25 + CR25: u1, + /// Cancellation Request 26 + CR26: u1, + /// Cancellation Request 27 + CR27: u1, + /// Cancellation Request 28 + CR28: u1, + /// Cancellation Request 29 + CR29: u1, + /// Cancellation Request 30 + CR30: u1, + /// Cancellation Request 31 + CR31: u1, + }), base_address + 0xd4); + + /// address: 0x420000d8 + /// Tx Buffer Transmission Occurred + pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Occurred 0 + TO0: u1, + /// Transmission Occurred 1 + TO1: u1, + /// Transmission Occurred 2 + TO2: u1, + /// Transmission Occurred 3 + TO3: u1, + /// Transmission Occurred 4 + TO4: u1, + /// Transmission Occurred 5 + TO5: u1, + /// Transmission Occurred 6 + TO6: u1, + /// Transmission Occurred 7 + TO7: u1, + /// Transmission Occurred 8 + TO8: u1, + /// Transmission Occurred 9 + TO9: u1, + /// Transmission Occurred 10 + TO10: u1, + /// Transmission Occurred 11 + TO11: u1, + /// Transmission Occurred 12 + TO12: u1, + /// Transmission Occurred 13 + TO13: u1, + /// Transmission Occurred 14 + TO14: u1, + /// Transmission Occurred 15 + TO15: u1, + /// Transmission Occurred 16 + TO16: u1, + /// Transmission Occurred 17 + TO17: u1, + /// Transmission Occurred 18 + TO18: u1, + /// Transmission Occurred 19 + TO19: u1, + /// Transmission Occurred 20 + TO20: u1, + /// Transmission Occurred 21 + TO21: u1, + /// Transmission Occurred 22 + TO22: u1, + /// Transmission Occurred 23 + TO23: u1, + /// Transmission Occurred 24 + TO24: u1, + /// Transmission Occurred 25 + TO25: u1, + /// Transmission Occurred 26 + TO26: u1, + /// Transmission Occurred 27 + TO27: u1, + /// Transmission Occurred 28 + TO28: u1, + /// Transmission Occurred 29 + TO29: u1, + /// Transmission Occurred 30 + TO30: u1, + /// Transmission Occurred 31 + TO31: u1, + }), base_address + 0xd8); + + /// address: 0x420000dc + /// Tx Buffer Cancellation Finished + pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Cancellation Finished 0 + CF0: u1, + /// Tx Buffer Cancellation Finished 1 + CF1: u1, + /// Tx Buffer Cancellation Finished 2 + CF2: u1, + /// Tx Buffer Cancellation Finished 3 + CF3: u1, + /// Tx Buffer Cancellation Finished 4 + CF4: u1, + /// Tx Buffer Cancellation Finished 5 + CF5: u1, + /// Tx Buffer Cancellation Finished 6 + CF6: u1, + /// Tx Buffer Cancellation Finished 7 + CF7: u1, + /// Tx Buffer Cancellation Finished 8 + CF8: u1, + /// Tx Buffer Cancellation Finished 9 + CF9: u1, + /// Tx Buffer Cancellation Finished 10 + CF10: u1, + /// Tx Buffer Cancellation Finished 11 + CF11: u1, + /// Tx Buffer Cancellation Finished 12 + CF12: u1, + /// Tx Buffer Cancellation Finished 13 + CF13: u1, + /// Tx Buffer Cancellation Finished 14 + CF14: u1, + /// Tx Buffer Cancellation Finished 15 + CF15: u1, + /// Tx Buffer Cancellation Finished 16 + CF16: u1, + /// Tx Buffer Cancellation Finished 17 + CF17: u1, + /// Tx Buffer Cancellation Finished 18 + CF18: u1, + /// Tx Buffer Cancellation Finished 19 + CF19: u1, + /// Tx Buffer Cancellation Finished 20 + CF20: u1, + /// Tx Buffer Cancellation Finished 21 + CF21: u1, + /// Tx Buffer Cancellation Finished 22 + CF22: u1, + /// Tx Buffer Cancellation Finished 23 + CF23: u1, + /// Tx Buffer Cancellation Finished 24 + CF24: u1, + /// Tx Buffer Cancellation Finished 25 + CF25: u1, + /// Tx Buffer Cancellation Finished 26 + CF26: u1, + /// Tx Buffer Cancellation Finished 27 + CF27: u1, + /// Tx Buffer Cancellation Finished 28 + CF28: u1, + /// Tx Buffer Cancellation Finished 29 + CF29: u1, + /// Tx Buffer Cancellation Finished 30 + CF30: u1, + /// Tx Buffer Cancellation Finished 31 + CF31: u1, + }), base_address + 0xdc); + + /// address: 0x420000e0 + /// Tx Buffer Transmission Interrupt Enable + pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Interrupt Enable 0 + TIE0: u1, + /// Transmission Interrupt Enable 1 + TIE1: u1, + /// Transmission Interrupt Enable 2 + TIE2: u1, + /// Transmission Interrupt Enable 3 + TIE3: u1, + /// Transmission Interrupt Enable 4 + TIE4: u1, + /// Transmission Interrupt Enable 5 + TIE5: u1, + /// Transmission Interrupt Enable 6 + TIE6: u1, + /// Transmission Interrupt Enable 7 + TIE7: u1, + /// Transmission Interrupt Enable 8 + TIE8: u1, + /// Transmission Interrupt Enable 9 + TIE9: u1, + /// Transmission Interrupt Enable 10 + TIE10: u1, + /// Transmission Interrupt Enable 11 + TIE11: u1, + /// Transmission Interrupt Enable 12 + TIE12: u1, + /// Transmission Interrupt Enable 13 + TIE13: u1, + /// Transmission Interrupt Enable 14 + TIE14: u1, + /// Transmission Interrupt Enable 15 + TIE15: u1, + /// Transmission Interrupt Enable 16 + TIE16: u1, + /// Transmission Interrupt Enable 17 + TIE17: u1, + /// Transmission Interrupt Enable 18 + TIE18: u1, + /// Transmission Interrupt Enable 19 + TIE19: u1, + /// Transmission Interrupt Enable 20 + TIE20: u1, + /// Transmission Interrupt Enable 21 + TIE21: u1, + /// Transmission Interrupt Enable 22 + TIE22: u1, + /// Transmission Interrupt Enable 23 + TIE23: u1, + /// Transmission Interrupt Enable 24 + TIE24: u1, + /// Transmission Interrupt Enable 25 + TIE25: u1, + /// Transmission Interrupt Enable 26 + TIE26: u1, + /// Transmission Interrupt Enable 27 + TIE27: u1, + /// Transmission Interrupt Enable 28 + TIE28: u1, + /// Transmission Interrupt Enable 29 + TIE29: u1, + /// Transmission Interrupt Enable 30 + TIE30: u1, + /// Transmission Interrupt Enable 31 + TIE31: u1, + }), base_address + 0xe0); + + /// address: 0x420000e4 + /// Tx Buffer Cancellation Finished Interrupt Enable + pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Finished Interrupt Enable 0 + CFIE0: u1, + /// Cancellation Finished Interrupt Enable 1 + CFIE1: u1, + /// Cancellation Finished Interrupt Enable 2 + CFIE2: u1, + /// Cancellation Finished Interrupt Enable 3 + CFIE3: u1, + /// Cancellation Finished Interrupt Enable 4 + CFIE4: u1, + /// Cancellation Finished Interrupt Enable 5 + CFIE5: u1, + /// Cancellation Finished Interrupt Enable 6 + CFIE6: u1, + /// Cancellation Finished Interrupt Enable 7 + CFIE7: u1, + /// Cancellation Finished Interrupt Enable 8 + CFIE8: u1, + /// Cancellation Finished Interrupt Enable 9 + CFIE9: u1, + /// Cancellation Finished Interrupt Enable 10 + CFIE10: u1, + /// Cancellation Finished Interrupt Enable 11 + CFIE11: u1, + /// Cancellation Finished Interrupt Enable 12 + CFIE12: u1, + /// Cancellation Finished Interrupt Enable 13 + CFIE13: u1, + /// Cancellation Finished Interrupt Enable 14 + CFIE14: u1, + /// Cancellation Finished Interrupt Enable 15 + CFIE15: u1, + /// Cancellation Finished Interrupt Enable 16 + CFIE16: u1, + /// Cancellation Finished Interrupt Enable 17 + CFIE17: u1, + /// Cancellation Finished Interrupt Enable 18 + CFIE18: u1, + /// Cancellation Finished Interrupt Enable 19 + CFIE19: u1, + /// Cancellation Finished Interrupt Enable 20 + CFIE20: u1, + /// Cancellation Finished Interrupt Enable 21 + CFIE21: u1, + /// Cancellation Finished Interrupt Enable 22 + CFIE22: u1, + /// Cancellation Finished Interrupt Enable 23 + CFIE23: u1, + /// Cancellation Finished Interrupt Enable 24 + CFIE24: u1, + /// Cancellation Finished Interrupt Enable 25 + CFIE25: u1, + /// Cancellation Finished Interrupt Enable 26 + CFIE26: u1, + /// Cancellation Finished Interrupt Enable 27 + CFIE27: u1, + /// Cancellation Finished Interrupt Enable 28 + CFIE28: u1, + /// Cancellation Finished Interrupt Enable 29 + CFIE29: u1, + /// Cancellation Finished Interrupt Enable 30 + CFIE30: u1, + /// Cancellation Finished Interrupt Enable 31 + CFIE31: u1, + }), base_address + 0xe4); + + /// address: 0x420000f0 + /// Tx Event FIFO Configuration + pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Start Address + EFSA: u16, + /// Event FIFO Size + EFS: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Watermark + EFWM: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xf0); + + /// address: 0x420000f4 + /// Tx Event FIFO Status + pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Fill Level + EFFL: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Get Index + EFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Event FIFO Put Index + EFPI: u5, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Event FIFO Full + EFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf4); + + /// address: 0x420000f8 + /// Tx Event FIFO Acknowledge + pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Acknowledge Index + EFAI: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xf8); + }; + pub const CAN1 = struct { + pub const base_address = 0x42000400; + + /// address: 0x42000400 + /// Core Release + pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Sub-step of Core Release + SUBSTEP: u4, + /// Step of Core Release + STEP: u4, + /// Core Release + REL: u4, + }), base_address + 0x0); + + /// address: 0x42000404 + /// Endian + pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { + /// Endianness Test Value + ETV: u32, + }), base_address + 0x4); + + /// address: 0x42000408 + /// Message RAM Configuration + pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Quality of Service + QOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x4200040c + /// Fast Bit Timing and Prescaler + pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Data (Re)Synchronization Jump Width + DSJW: u4, + /// Data time segment after sample point + DTSEG2: u4, + /// Data time segment before sample point + DTSEG1: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Baud Rate Prescaler + DBRP: u5, + reserved3: u1, + reserved4: u1, + /// Tranceiver Delay Compensation + TDC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xc); + + /// address: 0x42000410 + /// Test + pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Loop Back Mode + LBCK: u1, + /// Control of Transmit Pin + TX: u2, + /// Receive Pin + RX: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x42000414 + /// RAM Watchdog + pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { + /// Watchdog Configuration + WDC: u8, + /// Watchdog Value + WDV: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x42000418 + /// CC Control + pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Initialization + INIT: u1, + /// Configuration Change Enable + CCE: u1, + /// ASM Restricted Operation Mode + ASM: u1, + /// Clock Stop Acknowledge + CSA: u1, + /// Clock Stop Request + CSR: u1, + /// Bus Monitoring Mode + MON: u1, + /// Disable Automatic Retransmission + DAR: u1, + /// Test Mode Enable + TEST: u1, + /// FD Operation Enable + FDOE: u1, + /// Bit Rate Switch Enable + BRSE: u1, + reserved0: u1, + reserved1: u1, + /// Protocol Exception Handling Disable + PXHD: u1, + /// Edge Filtering during Bus Integration + EFBI: u1, + /// Transmit Pause + TXP: u1, + /// Non ISO Operation + NISO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x18); + + /// address: 0x4200041c + /// Nominal Bit Timing and Prescaler + pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { + /// Nominal Time segment after sample point + NTSEG2: u7, + reserved0: u1, + /// Nominal Time segment before sample point + NTSEG1: u8, + /// Nominal Baud Rate Prescaler + NBRP: u9, + /// Nominal (Re)Synchronization Jump Width + NSJW: u7, + }), base_address + 0x1c); + + /// address: 0x42000420 + /// Timestamp Counter Configuration + pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Select + TSS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Timestamp Counter Prescaler + TCP: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x20); + + /// address: 0x42000424 + /// Timestamp Counter Value + pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timestamp Counter + TSC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x24); + + /// address: 0x42000428 + /// Timeout Counter Configuration + pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Timeout Counter + ETOC: u1, + /// Timeout Select + TOS: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Timeout Period + TOP: u16, + }), base_address + 0x28); + + /// address: 0x4200042c + /// Timeout Counter Value + pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Counter + TOC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x2c); + + /// address: 0x42000440 + /// Error Counter + pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Error Counter + TEC: u8, + /// Receive Error Counter + REC: u7, + /// Receive Error Passive + RP: u1, + /// CAN Error Logging + CEL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000444 + /// Protocol Status + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Last Error Code + LEC: u3, + /// Activity + ACT: u2, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Data Phase Last Error Code + DLEC: u3, + /// ESI flag of last received CAN FD Message + RESI: u1, + /// BRS flag of last received CAN FD Message + RBRS: u1, + /// Received a CAN FD Message + RFDF: u1, + /// Protocol Exception Event + PXE: u1, + reserved0: u1, + /// Transmitter Delay Compensation Value + TDCV: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x44); + + /// address: 0x42000448 + /// Extended ID Filter Configuration + pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmitter Delay Compensation Filter Length + TDCF: u7, + reserved0: u1, + /// Transmitter Delay Compensation Offset + TDCO: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x48); + + /// address: 0x42000450 + /// Interrupt + pub const IR = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message + RF0N: u1, + /// Rx FIFO 0 Watermark Reached + RF0W: u1, + /// Rx FIFO 0 Full + RF0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + /// Rx FIFO 1 New Message + RF1N: u1, + /// Rx FIFO 1 Watermark Reached + RF1W: u1, + /// Rx FIFO 1 FIFO Full + RF1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + /// High Priority Message + HPM: u1, + /// Timestamp Completed + TC: u1, + /// Transmission Cancellation Finished + TCF: u1, + /// Tx FIFO Empty + TFE: u1, + /// Tx Event FIFO New Entry + TEFN: u1, + /// Tx Event FIFO Watermark Reached + TEFW: u1, + /// Tx Event FIFO Full + TEFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + /// Timestamp Wraparound + TSW: u1, + /// Message RAM Access Failure + MRAF: u1, + /// Timeout Occurred + TOO: u1, + /// Message stored to Dedicated Rx Buffer + DRX: u1, + /// Bit Error Corrected + BEC: u1, + /// Bit Error Uncorrected + BEU: u1, + /// Error Logging Overflow + ELO: u1, + /// Error Passive + EP: u1, + /// Warning Status + EW: u1, + /// Bus_Off Status + BO: u1, + /// Watchdog Interrupt + WDI: u1, + /// Protocol Error in Arbitration Phase + PEA: u1, + /// Protocol Error in Data Phase + PED: u1, + /// Access to Reserved Address + ARA: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x50); + + /// address: 0x42000454 + /// Interrupt Enable + pub const IE = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Enable + RF0NE: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Enable + RF0WE: u1, + /// Rx FIFO 0 Full Interrupt Enable + RF0FE: u1, + /// Rx FIFO 0 Message Lost Interrupt Enable + RF0LE: u1, + /// Rx FIFO 1 New Message Interrupt Enable + RF1NE: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Enable + RF1WE: u1, + /// Rx FIFO 1 FIFO Full Interrupt Enable + RF1FE: u1, + /// Rx FIFO 1 Message Lost Interrupt Enable + RF1LE: u1, + /// High Priority Message Interrupt Enable + HPME: u1, + /// Timestamp Completed Interrupt Enable + TCE: u1, + /// Transmission Cancellation Finished Interrupt Enable + TCFE: u1, + /// Tx FIFO Empty Interrupt Enable + TFEE: u1, + /// Tx Event FIFO New Entry Interrupt Enable + TEFNE: u1, + /// Tx Event FIFO Watermark Reached Interrupt Enable + TEFWE: u1, + /// Tx Event FIFO Full Interrupt Enable + TEFFE: u1, + /// Tx Event FIFO Element Lost Interrupt Enable + TEFLE: u1, + /// Timestamp Wraparound Interrupt Enable + TSWE: u1, + /// Message RAM Access Failure Interrupt Enable + MRAFE: u1, + /// Timeout Occurred Interrupt Enable + TOOE: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Enable + DRXE: u1, + /// Bit Error Corrected Interrupt Enable + BECE: u1, + /// Bit Error Uncorrected Interrupt Enable + BEUE: u1, + /// Error Logging Overflow Interrupt Enable + ELOE: u1, + /// Error Passive Interrupt Enable + EPE: u1, + /// Warning Status Interrupt Enable + EWE: u1, + /// Bus_Off Status Interrupt Enable + BOE: u1, + /// Watchdog Interrupt Interrupt Enable + WDIE: u1, + /// Protocol Error in Arbitration Phase Enable + PEAE: u1, + /// Protocol Error in Data Phase Enable + PEDE: u1, + /// Access to Reserved Address Enable + ARAE: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x54); + + /// address: 0x42000458 + /// Interrupt Line Select + pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 New Message Interrupt Line + RF0NL: u1, + /// Rx FIFO 0 Watermark Reached Interrupt Line + RF0WL: u1, + /// Rx FIFO 0 Full Interrupt Line + RF0FL: u1, + /// Rx FIFO 0 Message Lost Interrupt Line + RF0LL: u1, + /// Rx FIFO 1 New Message Interrupt Line + RF1NL: u1, + /// Rx FIFO 1 Watermark Reached Interrupt Line + RF1WL: u1, + /// Rx FIFO 1 FIFO Full Interrupt Line + RF1FL: u1, + /// Rx FIFO 1 Message Lost Interrupt Line + RF1LL: u1, + /// High Priority Message Interrupt Line + HPML: u1, + /// Timestamp Completed Interrupt Line + TCL: u1, + /// Transmission Cancellation Finished Interrupt Line + TCFL: u1, + /// Tx FIFO Empty Interrupt Line + TFEL: u1, + /// Tx Event FIFO New Entry Interrupt Line + TEFNL: u1, + /// Tx Event FIFO Watermark Reached Interrupt Line + TEFWL: u1, + /// Tx Event FIFO Full Interrupt Line + TEFFL: u1, + /// Tx Event FIFO Element Lost Interrupt Line + TEFLL: u1, + /// Timestamp Wraparound Interrupt Line + TSWL: u1, + /// Message RAM Access Failure Interrupt Line + MRAFL: u1, + /// Timeout Occurred Interrupt Line + TOOL: u1, + /// Message stored to Dedicated Rx Buffer Interrupt Line + DRXL: u1, + /// Bit Error Corrected Interrupt Line + BECL: u1, + /// Bit Error Uncorrected Interrupt Line + BEUL: u1, + /// Error Logging Overflow Interrupt Line + ELOL: u1, + /// Error Passive Interrupt Line + EPL: u1, + /// Warning Status Interrupt Line + EWL: u1, + /// Bus_Off Status Interrupt Line + BOL: u1, + /// Watchdog Interrupt Interrupt Line + WDIL: u1, + /// Protocol Error in Arbitration Phase Line + PEAL: u1, + /// Protocol Error in Data Phase Line + PEDL: u1, + /// Access to Reserved Address Line + ARAL: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x58); + + /// address: 0x4200045c + /// Interrupt Line Enable + pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable Interrupt Line 0 + EINT0: u1, + /// Enable Interrupt Line 1 + EINT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x5c); + + /// address: 0x42000480 + /// Global Filter Configuration + pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Reject Remote Frames Extended + RRFE: u1, + /// Reject Remote Frames Standard + RRFS: u1, + /// Accept Non-matching Frames Extended + ANFE: u2, + /// Accept Non-matching Frames Standard + ANFS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x80); + + /// address: 0x42000484 + /// Standard ID Filter Configuration + pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Standard Start Address + FLSSA: u16, + /// List Size Standard + LSS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x84); + + /// address: 0x42000488 + /// Extended ID Filter Configuration + pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Filter List Extended Start Address + FLESA: u16, + /// List Size Extended + LSE: u7, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + }), base_address + 0x88); + + /// address: 0x42000490 + /// Extended ID AND Mask + pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { + /// Extended ID Mask + EIDM: u29, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x90); + + /// address: 0x42000494 + /// High Priority Message Status + pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Index + BIDX: u6, + /// Message Storage Indicator + MSI: u2, + /// Filter Index + FIDX: u7, + /// Filter List + FLST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x94); + + /// address: 0x42000498 + /// New Data 1 + pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 0 + ND0: u1, + /// New Data 1 + ND1: u1, + /// New Data 2 + ND2: u1, + /// New Data 3 + ND3: u1, + /// New Data 4 + ND4: u1, + /// New Data 5 + ND5: u1, + /// New Data 6 + ND6: u1, + /// New Data 7 + ND7: u1, + /// New Data 8 + ND8: u1, + /// New Data 9 + ND9: u1, + /// New Data 10 + ND10: u1, + /// New Data 11 + ND11: u1, + /// New Data 12 + ND12: u1, + /// New Data 13 + ND13: u1, + /// New Data 14 + ND14: u1, + /// New Data 15 + ND15: u1, + /// New Data 16 + ND16: u1, + /// New Data 17 + ND17: u1, + /// New Data 18 + ND18: u1, + /// New Data 19 + ND19: u1, + /// New Data 20 + ND20: u1, + /// New Data 21 + ND21: u1, + /// New Data 22 + ND22: u1, + /// New Data 23 + ND23: u1, + /// New Data 24 + ND24: u1, + /// New Data 25 + ND25: u1, + /// New Data 26 + ND26: u1, + /// New Data 27 + ND27: u1, + /// New Data 28 + ND28: u1, + /// New Data 29 + ND29: u1, + /// New Data 30 + ND30: u1, + /// New Data 31 + ND31: u1, + }), base_address + 0x98); + + /// address: 0x4200049c + /// New Data 2 + pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { + /// New Data 32 + ND32: u1, + /// New Data 33 + ND33: u1, + /// New Data 34 + ND34: u1, + /// New Data 35 + ND35: u1, + /// New Data 36 + ND36: u1, + /// New Data 37 + ND37: u1, + /// New Data 38 + ND38: u1, + /// New Data 39 + ND39: u1, + /// New Data 40 + ND40: u1, + /// New Data 41 + ND41: u1, + /// New Data 42 + ND42: u1, + /// New Data 43 + ND43: u1, + /// New Data 44 + ND44: u1, + /// New Data 45 + ND45: u1, + /// New Data 46 + ND46: u1, + /// New Data 47 + ND47: u1, + /// New Data 48 + ND48: u1, + /// New Data 49 + ND49: u1, + /// New Data 50 + ND50: u1, + /// New Data 51 + ND51: u1, + /// New Data 52 + ND52: u1, + /// New Data 53 + ND53: u1, + /// New Data 54 + ND54: u1, + /// New Data 55 + ND55: u1, + /// New Data 56 + ND56: u1, + /// New Data 57 + ND57: u1, + /// New Data 58 + ND58: u1, + /// New Data 59 + ND59: u1, + /// New Data 60 + ND60: u1, + /// New Data 61 + ND61: u1, + /// New Data 62 + ND62: u1, + /// New Data 63 + ND63: u1, + }), base_address + 0x9c); + + /// address: 0x420004a0 + /// Rx FIFO 0 Configuration + pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Start Address + F0SA: u16, + /// Rx FIFO 0 Size + F0S: u7, + reserved0: u1, + /// Rx FIFO 0 Watermark + F0WM: u7, + /// FIFO 0 Operation Mode + F0OM: u1, + }), base_address + 0xa0); + + /// address: 0x420004a4 + /// Rx FIFO 0 Status + pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Fill Level + F0FL: u7, + reserved0: u1, + /// Rx FIFO 0 Get Index + F0GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 0 Put Index + F0PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 0 Full + F0F: u1, + /// Rx FIFO 0 Message Lost + RF0L: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa4); + + /// address: 0x420004a8 + /// Rx FIFO 0 Acknowledge + pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Acknowledge Index + F0AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xa8); + + /// address: 0x420004ac + /// Rx Buffer Configuration + pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx Buffer Start Address + RBSA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xac); + + /// address: 0x420004b0 + /// Rx FIFO 1 Configuration + pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Start Address + F1SA: u16, + /// Rx FIFO 1 Size + F1S: u7, + reserved0: u1, + /// Rx FIFO 1 Watermark + F1WM: u7, + /// FIFO 1 Operation Mode + F1OM: u1, + }), base_address + 0xb0); + + /// address: 0x420004b4 + /// Rx FIFO 1 Status + pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Fill Level + F1FL: u7, + reserved0: u1, + /// Rx FIFO 1 Get Index + F1GI: u6, + reserved1: u1, + reserved2: u1, + /// Rx FIFO 1 Put Index + F1PI: u6, + reserved3: u1, + reserved4: u1, + /// Rx FIFO 1 Full + F1F: u1, + /// Rx FIFO 1 Message Lost + RF1L: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debug Message Status + DMS: u2, + }), base_address + 0xb4); + + /// address: 0x420004b8 + /// Rx FIFO 1 Acknowledge + pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 1 Acknowledge Index + F1AI: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0xb8); + + /// address: 0x420004bc + /// Rx Buffer / FIFO Element Size Configuration + pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Rx FIFO 0 Data Field Size + F0DS: u3, + reserved0: u1, + /// Rx FIFO 1 Data Field Size + F1DS: u3, + reserved1: u1, + /// Rx Buffer Data Field Size + RBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xbc); + + /// address: 0x420004c0 + /// Tx Buffer Configuration + pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffers Start Address + TBSA: u16, + /// Number of Dedicated Transmit Buffers + NDTB: u6, + reserved0: u1, + reserved1: u1, + /// Transmit FIFO/Queue Size + TFQS: u6, + /// Tx FIFO/Queue Mode + TFQM: u1, + padding0: u1, + }), base_address + 0xc0); + + /// address: 0x420004c4 + /// Tx FIFO / Queue Status + pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx FIFO Free Level + TFFL: u6, + reserved0: u1, + reserved1: u1, + /// Tx FIFO Get Index + TFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Tx FIFO/Queue Put Index + TFQPI: u5, + /// Tx FIFO/Queue Full + TFQF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc4); + + /// address: 0x420004c8 + /// Tx Buffer Element Size Configuration + pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Data Field Size + TBDS: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xc8); + + /// address: 0x420004cc + /// Tx Buffer Request Pending + pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Request Pending 0 + TRP0: u1, + /// Transmission Request Pending 1 + TRP1: u1, + /// Transmission Request Pending 2 + TRP2: u1, + /// Transmission Request Pending 3 + TRP3: u1, + /// Transmission Request Pending 4 + TRP4: u1, + /// Transmission Request Pending 5 + TRP5: u1, + /// Transmission Request Pending 6 + TRP6: u1, + /// Transmission Request Pending 7 + TRP7: u1, + /// Transmission Request Pending 8 + TRP8: u1, + /// Transmission Request Pending 9 + TRP9: u1, + /// Transmission Request Pending 10 + TRP10: u1, + /// Transmission Request Pending 11 + TRP11: u1, + /// Transmission Request Pending 12 + TRP12: u1, + /// Transmission Request Pending 13 + TRP13: u1, + /// Transmission Request Pending 14 + TRP14: u1, + /// Transmission Request Pending 15 + TRP15: u1, + /// Transmission Request Pending 16 + TRP16: u1, + /// Transmission Request Pending 17 + TRP17: u1, + /// Transmission Request Pending 18 + TRP18: u1, + /// Transmission Request Pending 19 + TRP19: u1, + /// Transmission Request Pending 20 + TRP20: u1, + /// Transmission Request Pending 21 + TRP21: u1, + /// Transmission Request Pending 22 + TRP22: u1, + /// Transmission Request Pending 23 + TRP23: u1, + /// Transmission Request Pending 24 + TRP24: u1, + /// Transmission Request Pending 25 + TRP25: u1, + /// Transmission Request Pending 26 + TRP26: u1, + /// Transmission Request Pending 27 + TRP27: u1, + /// Transmission Request Pending 28 + TRP28: u1, + /// Transmission Request Pending 29 + TRP29: u1, + /// Transmission Request Pending 30 + TRP30: u1, + /// Transmission Request Pending 31 + TRP31: u1, + }), base_address + 0xcc); + + /// address: 0x420004d0 + /// Tx Buffer Add Request + pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Add Request 0 + AR0: u1, + /// Add Request 1 + AR1: u1, + /// Add Request 2 + AR2: u1, + /// Add Request 3 + AR3: u1, + /// Add Request 4 + AR4: u1, + /// Add Request 5 + AR5: u1, + /// Add Request 6 + AR6: u1, + /// Add Request 7 + AR7: u1, + /// Add Request 8 + AR8: u1, + /// Add Request 9 + AR9: u1, + /// Add Request 10 + AR10: u1, + /// Add Request 11 + AR11: u1, + /// Add Request 12 + AR12: u1, + /// Add Request 13 + AR13: u1, + /// Add Request 14 + AR14: u1, + /// Add Request 15 + AR15: u1, + /// Add Request 16 + AR16: u1, + /// Add Request 17 + AR17: u1, + /// Add Request 18 + AR18: u1, + /// Add Request 19 + AR19: u1, + /// Add Request 20 + AR20: u1, + /// Add Request 21 + AR21: u1, + /// Add Request 22 + AR22: u1, + /// Add Request 23 + AR23: u1, + /// Add Request 24 + AR24: u1, + /// Add Request 25 + AR25: u1, + /// Add Request 26 + AR26: u1, + /// Add Request 27 + AR27: u1, + /// Add Request 28 + AR28: u1, + /// Add Request 29 + AR29: u1, + /// Add Request 30 + AR30: u1, + /// Add Request 31 + AR31: u1, + }), base_address + 0xd0); + + /// address: 0x420004d4 + /// Tx Buffer Cancellation Request + pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Request 0 + CR0: u1, + /// Cancellation Request 1 + CR1: u1, + /// Cancellation Request 2 + CR2: u1, + /// Cancellation Request 3 + CR3: u1, + /// Cancellation Request 4 + CR4: u1, + /// Cancellation Request 5 + CR5: u1, + /// Cancellation Request 6 + CR6: u1, + /// Cancellation Request 7 + CR7: u1, + /// Cancellation Request 8 + CR8: u1, + /// Cancellation Request 9 + CR9: u1, + /// Cancellation Request 10 + CR10: u1, + /// Cancellation Request 11 + CR11: u1, + /// Cancellation Request 12 + CR12: u1, + /// Cancellation Request 13 + CR13: u1, + /// Cancellation Request 14 + CR14: u1, + /// Cancellation Request 15 + CR15: u1, + /// Cancellation Request 16 + CR16: u1, + /// Cancellation Request 17 + CR17: u1, + /// Cancellation Request 18 + CR18: u1, + /// Cancellation Request 19 + CR19: u1, + /// Cancellation Request 20 + CR20: u1, + /// Cancellation Request 21 + CR21: u1, + /// Cancellation Request 22 + CR22: u1, + /// Cancellation Request 23 + CR23: u1, + /// Cancellation Request 24 + CR24: u1, + /// Cancellation Request 25 + CR25: u1, + /// Cancellation Request 26 + CR26: u1, + /// Cancellation Request 27 + CR27: u1, + /// Cancellation Request 28 + CR28: u1, + /// Cancellation Request 29 + CR29: u1, + /// Cancellation Request 30 + CR30: u1, + /// Cancellation Request 31 + CR31: u1, + }), base_address + 0xd4); + + /// address: 0x420004d8 + /// Tx Buffer Transmission Occurred + pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Occurred 0 + TO0: u1, + /// Transmission Occurred 1 + TO1: u1, + /// Transmission Occurred 2 + TO2: u1, + /// Transmission Occurred 3 + TO3: u1, + /// Transmission Occurred 4 + TO4: u1, + /// Transmission Occurred 5 + TO5: u1, + /// Transmission Occurred 6 + TO6: u1, + /// Transmission Occurred 7 + TO7: u1, + /// Transmission Occurred 8 + TO8: u1, + /// Transmission Occurred 9 + TO9: u1, + /// Transmission Occurred 10 + TO10: u1, + /// Transmission Occurred 11 + TO11: u1, + /// Transmission Occurred 12 + TO12: u1, + /// Transmission Occurred 13 + TO13: u1, + /// Transmission Occurred 14 + TO14: u1, + /// Transmission Occurred 15 + TO15: u1, + /// Transmission Occurred 16 + TO16: u1, + /// Transmission Occurred 17 + TO17: u1, + /// Transmission Occurred 18 + TO18: u1, + /// Transmission Occurred 19 + TO19: u1, + /// Transmission Occurred 20 + TO20: u1, + /// Transmission Occurred 21 + TO21: u1, + /// Transmission Occurred 22 + TO22: u1, + /// Transmission Occurred 23 + TO23: u1, + /// Transmission Occurred 24 + TO24: u1, + /// Transmission Occurred 25 + TO25: u1, + /// Transmission Occurred 26 + TO26: u1, + /// Transmission Occurred 27 + TO27: u1, + /// Transmission Occurred 28 + TO28: u1, + /// Transmission Occurred 29 + TO29: u1, + /// Transmission Occurred 30 + TO30: u1, + /// Transmission Occurred 31 + TO31: u1, + }), base_address + 0xd8); + + /// address: 0x420004dc + /// Tx Buffer Cancellation Finished + pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { + /// Tx Buffer Cancellation Finished 0 + CF0: u1, + /// Tx Buffer Cancellation Finished 1 + CF1: u1, + /// Tx Buffer Cancellation Finished 2 + CF2: u1, + /// Tx Buffer Cancellation Finished 3 + CF3: u1, + /// Tx Buffer Cancellation Finished 4 + CF4: u1, + /// Tx Buffer Cancellation Finished 5 + CF5: u1, + /// Tx Buffer Cancellation Finished 6 + CF6: u1, + /// Tx Buffer Cancellation Finished 7 + CF7: u1, + /// Tx Buffer Cancellation Finished 8 + CF8: u1, + /// Tx Buffer Cancellation Finished 9 + CF9: u1, + /// Tx Buffer Cancellation Finished 10 + CF10: u1, + /// Tx Buffer Cancellation Finished 11 + CF11: u1, + /// Tx Buffer Cancellation Finished 12 + CF12: u1, + /// Tx Buffer Cancellation Finished 13 + CF13: u1, + /// Tx Buffer Cancellation Finished 14 + CF14: u1, + /// Tx Buffer Cancellation Finished 15 + CF15: u1, + /// Tx Buffer Cancellation Finished 16 + CF16: u1, + /// Tx Buffer Cancellation Finished 17 + CF17: u1, + /// Tx Buffer Cancellation Finished 18 + CF18: u1, + /// Tx Buffer Cancellation Finished 19 + CF19: u1, + /// Tx Buffer Cancellation Finished 20 + CF20: u1, + /// Tx Buffer Cancellation Finished 21 + CF21: u1, + /// Tx Buffer Cancellation Finished 22 + CF22: u1, + /// Tx Buffer Cancellation Finished 23 + CF23: u1, + /// Tx Buffer Cancellation Finished 24 + CF24: u1, + /// Tx Buffer Cancellation Finished 25 + CF25: u1, + /// Tx Buffer Cancellation Finished 26 + CF26: u1, + /// Tx Buffer Cancellation Finished 27 + CF27: u1, + /// Tx Buffer Cancellation Finished 28 + CF28: u1, + /// Tx Buffer Cancellation Finished 29 + CF29: u1, + /// Tx Buffer Cancellation Finished 30 + CF30: u1, + /// Tx Buffer Cancellation Finished 31 + CF31: u1, + }), base_address + 0xdc); + + /// address: 0x420004e0 + /// Tx Buffer Transmission Interrupt Enable + pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmission Interrupt Enable 0 + TIE0: u1, + /// Transmission Interrupt Enable 1 + TIE1: u1, + /// Transmission Interrupt Enable 2 + TIE2: u1, + /// Transmission Interrupt Enable 3 + TIE3: u1, + /// Transmission Interrupt Enable 4 + TIE4: u1, + /// Transmission Interrupt Enable 5 + TIE5: u1, + /// Transmission Interrupt Enable 6 + TIE6: u1, + /// Transmission Interrupt Enable 7 + TIE7: u1, + /// Transmission Interrupt Enable 8 + TIE8: u1, + /// Transmission Interrupt Enable 9 + TIE9: u1, + /// Transmission Interrupt Enable 10 + TIE10: u1, + /// Transmission Interrupt Enable 11 + TIE11: u1, + /// Transmission Interrupt Enable 12 + TIE12: u1, + /// Transmission Interrupt Enable 13 + TIE13: u1, + /// Transmission Interrupt Enable 14 + TIE14: u1, + /// Transmission Interrupt Enable 15 + TIE15: u1, + /// Transmission Interrupt Enable 16 + TIE16: u1, + /// Transmission Interrupt Enable 17 + TIE17: u1, + /// Transmission Interrupt Enable 18 + TIE18: u1, + /// Transmission Interrupt Enable 19 + TIE19: u1, + /// Transmission Interrupt Enable 20 + TIE20: u1, + /// Transmission Interrupt Enable 21 + TIE21: u1, + /// Transmission Interrupt Enable 22 + TIE22: u1, + /// Transmission Interrupt Enable 23 + TIE23: u1, + /// Transmission Interrupt Enable 24 + TIE24: u1, + /// Transmission Interrupt Enable 25 + TIE25: u1, + /// Transmission Interrupt Enable 26 + TIE26: u1, + /// Transmission Interrupt Enable 27 + TIE27: u1, + /// Transmission Interrupt Enable 28 + TIE28: u1, + /// Transmission Interrupt Enable 29 + TIE29: u1, + /// Transmission Interrupt Enable 30 + TIE30: u1, + /// Transmission Interrupt Enable 31 + TIE31: u1, + }), base_address + 0xe0); + + /// address: 0x420004e4 + /// Tx Buffer Cancellation Finished Interrupt Enable + pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { + /// Cancellation Finished Interrupt Enable 0 + CFIE0: u1, + /// Cancellation Finished Interrupt Enable 1 + CFIE1: u1, + /// Cancellation Finished Interrupt Enable 2 + CFIE2: u1, + /// Cancellation Finished Interrupt Enable 3 + CFIE3: u1, + /// Cancellation Finished Interrupt Enable 4 + CFIE4: u1, + /// Cancellation Finished Interrupt Enable 5 + CFIE5: u1, + /// Cancellation Finished Interrupt Enable 6 + CFIE6: u1, + /// Cancellation Finished Interrupt Enable 7 + CFIE7: u1, + /// Cancellation Finished Interrupt Enable 8 + CFIE8: u1, + /// Cancellation Finished Interrupt Enable 9 + CFIE9: u1, + /// Cancellation Finished Interrupt Enable 10 + CFIE10: u1, + /// Cancellation Finished Interrupt Enable 11 + CFIE11: u1, + /// Cancellation Finished Interrupt Enable 12 + CFIE12: u1, + /// Cancellation Finished Interrupt Enable 13 + CFIE13: u1, + /// Cancellation Finished Interrupt Enable 14 + CFIE14: u1, + /// Cancellation Finished Interrupt Enable 15 + CFIE15: u1, + /// Cancellation Finished Interrupt Enable 16 + CFIE16: u1, + /// Cancellation Finished Interrupt Enable 17 + CFIE17: u1, + /// Cancellation Finished Interrupt Enable 18 + CFIE18: u1, + /// Cancellation Finished Interrupt Enable 19 + CFIE19: u1, + /// Cancellation Finished Interrupt Enable 20 + CFIE20: u1, + /// Cancellation Finished Interrupt Enable 21 + CFIE21: u1, + /// Cancellation Finished Interrupt Enable 22 + CFIE22: u1, + /// Cancellation Finished Interrupt Enable 23 + CFIE23: u1, + /// Cancellation Finished Interrupt Enable 24 + CFIE24: u1, + /// Cancellation Finished Interrupt Enable 25 + CFIE25: u1, + /// Cancellation Finished Interrupt Enable 26 + CFIE26: u1, + /// Cancellation Finished Interrupt Enable 27 + CFIE27: u1, + /// Cancellation Finished Interrupt Enable 28 + CFIE28: u1, + /// Cancellation Finished Interrupt Enable 29 + CFIE29: u1, + /// Cancellation Finished Interrupt Enable 30 + CFIE30: u1, + /// Cancellation Finished Interrupt Enable 31 + CFIE31: u1, + }), base_address + 0xe4); + + /// address: 0x420004f0 + /// Tx Event FIFO Configuration + pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Start Address + EFSA: u16, + /// Event FIFO Size + EFS: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Watermark + EFWM: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xf0); + + /// address: 0x420004f4 + /// Tx Event FIFO Status + pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Fill Level + EFFL: u6, + reserved0: u1, + reserved1: u1, + /// Event FIFO Get Index + EFGI: u5, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Event FIFO Put Index + EFPI: u5, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Event FIFO Full + EFF: u1, + /// Tx Event FIFO Element Lost + TEFL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf4); + + /// address: 0x420004f8 + /// Tx Event FIFO Acknowledge + pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { + /// Event FIFO Acknowledge Index + EFAI: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xf8); + }; + + /// Configurable Custom Logic + pub const CCL = struct { + pub const base_address = 0x42003800; + pub const version = "U22251.1.0"; + + /// address: 0x42003800 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Run in Standby + RUNSTDBY: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x42003804 + /// SEQ Control x + pub const SEQCTRL = @intToPtr(*volatile [2]Mmio(8, packed struct { + /// Sequential Selection + SEQSEL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x42003808 + /// LUT Control x + pub const LUTCTRL = @intToPtr(*volatile [4]Mmio(32, packed struct { + reserved0: u1, + /// LUT Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + /// Filter Selection + FILTSEL: u2, + reserved3: u1, + /// Edge Selection + EDGESEL: u1, + /// Input Selection 0 + INSEL0: u4, + /// Input Selection 1 + INSEL1: u4, + /// Input Selection 2 + INSEL2: u4, + /// Inverted Event Input Enable + INVEI: u1, + /// LUT Event Input Enable + LUTEI: u1, + /// LUT Event Output Enable + LUTEO: u1, + reserved4: u1, + /// Truth Value + TRUTH: u8, + }), base_address + 0x8); + }; + + /// Cortex M Cache Controller + pub const CMCC = struct { + pub const base_address = 0x41006000; + pub const version = "U20156.0.0"; + + /// address: 0x41006000 + /// Cache Type Register + pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// dynamic Clock Gating supported + GCLK: u1, + reserved1: u1, + reserved2: u1, + /// Round Robin Policy supported + RRP: u1, + /// Number of Way + WAYNUM: u2, + /// Lock Down supported + LCKDOWN: u1, + /// Cache Size + CSIZE: u3, + /// Cache Line Size + CLSIZE: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x0); + + /// address: 0x41006004 + /// Cache Configuration Register + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Instruction Cache Disable + ICDIS: u1, + /// Data Cache Disable + DCDIS: u1, + reserved1: u1, + /// Cache size configured by software + CSIZESW: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + }), base_address + 0x4); + + /// address: 0x41006008 + /// Cache Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Enable + CEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x8); + + /// address: 0x4100600c + /// Cache Status Register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Status + CSTS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xc); + + /// address: 0x41006010 + /// Cache Lock per Way Register + pub const LCKWAY = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); + + /// address: 0x41006020 + /// Cache Maintenance Register 0 + pub const MAINT0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller invalidate All + INVALL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20); + + /// address: 0x41006024 + /// Cache Maintenance Register 1 + pub const MAINT1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Invalidate Index + INDEX: u8, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Invalidate Way + WAY: u4, + }), base_address + 0x24); + + /// address: 0x41006028 + /// Cache Monitor Configuration Register + pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Monitor Counter Mode + MODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + + /// address: 0x4100602c + /// Cache Monitor Enable Register + pub const MEN = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Monitor Enable + MENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x2c); + + /// address: 0x41006030 + /// Cache Monitor Control Register + pub const MCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Cache Controller Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x30); + + /// address: 0x41006034 + /// Cache Monitor Status Register + pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Monitor Event Counter + EVENT_CNT: u32, + }), base_address + 0x34); + }; + + /// Digital-to-Analog Converter + pub const DAC = struct { + pub const base_address = 0x43002400; + pub const version = "U25021.0.0"; + + /// address: 0x43002400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable DAC Controller + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x43002401 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Differential mode enable + DIFF: u1, + /// Reference Selection for DAC0/1 + REFSEL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1); + + /// address: 0x43002402 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Conversion Event Input DAC 0 + STARTEI0: u1, + /// Start Conversion Event Input DAC 1 + STARTEI1: u1, + /// Data Buffer Empty Event Output DAC 0 + EMPTYEO0: u1, + /// Data Buffer Empty Event Output DAC 1 + EMPTYEO1: u1, + /// Enable Invertion of DAC 0 input event + INVEI0: u1, + /// Enable Invertion of DAC 1 input event + INVEI1: u1, + /// Result Ready Event Output 0 + RESRDYEO0: u1, + /// Result Ready Event Output 1 + RESRDYEO1: u1, + }), base_address + 0x2); + + /// address: 0x43002404 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Underrun 0 Interrupt Enable + UNDERRUN0: u1, + /// Underrun 1 Interrupt Enable + UNDERRUN1: u1, + /// Data Buffer 0 Empty Interrupt Enable + EMPTY0: u1, + /// Data Buffer 1 Empty Interrupt Enable + EMPTY1: u1, + /// Result 0 Ready Interrupt Enable + RESRDY0: u1, + /// Result 1 Ready Interrupt Enable + RESRDY1: u1, + /// Overrun 0 Interrupt Enable + OVERRUN0: u1, + /// Overrun 1 Interrupt Enable + OVERRUN1: u1, + }), base_address + 0x4); + + /// address: 0x43002405 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Underrun 0 Interrupt Enable + UNDERRUN0: u1, + /// Underrun 1 Interrupt Enable + UNDERRUN1: u1, + /// Data Buffer 0 Empty Interrupt Enable + EMPTY0: u1, + /// Data Buffer 1 Empty Interrupt Enable + EMPTY1: u1, + /// Result 0 Ready Interrupt Enable + RESRDY0: u1, + /// Result 1 Ready Interrupt Enable + RESRDY1: u1, + /// Overrun 0 Interrupt Enable + OVERRUN0: u1, + /// Overrun 1 Interrupt Enable + OVERRUN1: u1, + }), base_address + 0x5); + + /// address: 0x43002406 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Result 0 Underrun + UNDERRUN0: u1, + /// Result 1 Underrun + UNDERRUN1: u1, + /// Data Buffer 0 Empty + EMPTY0: u1, + /// Data Buffer 1 Empty + EMPTY1: u1, + /// Result 0 Ready + RESRDY0: u1, + /// Result 1 Ready + RESRDY1: u1, + /// Result 0 Overrun + OVERRUN0: u1, + /// Result 1 Overrun + OVERRUN1: u1, + }), base_address + 0x6); + + /// address: 0x43002407 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// DAC 0 Startup Ready + READY0: u1, + /// DAC 1 Startup Ready + READY1: u1, + /// DAC 0 End of Conversion + EOC0: u1, + /// DAC 1 End of Conversion + EOC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x7); + + /// address: 0x43002408 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// DAC Enable Status + ENABLE: u1, + /// Data DAC 0 + DATA0: u1, + /// Data DAC 1 + DATA1: u1, + /// Data Buffer DAC 0 + DATABUF0: u1, + /// Data Buffer DAC 1 + DATABUF1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x8); + + /// address: 0x4300240c + /// DAC n Control + pub const DACCTRL = @intToPtr(*volatile [2]Mmio(16, packed struct { + /// Left Adjusted Data + LEFTADJ: u1, + /// Enable DAC0 + ENABLE: u1, + /// Current Control + CCTRL: u2, + reserved0: u1, + /// Standalone Filter + FEXT: u1, + /// Run in Standby + RUNSTDBY: u1, + /// Dithering Mode + DITHER: u1, + /// Refresh period + REFRESH: u4, + reserved1: u1, + /// Sampling Rate + OSR: u3, + }), base_address + 0xc); + + /// address: 0x43002410 + /// DAC n Data + pub const DATA = @intToPtr(*volatile [2]u16, base_address + 0x10); + + /// address: 0x43002414 + /// DAC n Data Buffer + pub const DATABUF = @intToPtr(*volatile [2]u16, base_address + 0x14); + + /// address: 0x43002418 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x4300241c + /// Filter Result + pub const RESULT = @intToPtr(*volatile [2]u16, base_address + 0x1c); + }; + + /// Direct Memory Access Controller + pub const DMAC = struct { + pub const base_address = 0x4100a000; + pub const version = "U25031.0.1"; + + /// address: 0x4100a000 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// DMA Enable + DMAENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Priority Level 0 Enable + LVLEN0: u1, + /// Priority Level 1 Enable + LVLEN1: u1, + /// Priority Level 2 Enable + LVLEN2: u1, + /// Priority Level 3 Enable + LVLEN3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x0); + + /// address: 0x4100a002 + /// CRC Control + pub const CRCCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// CRC Beat Size + CRCBEATSIZE: u2, + /// CRC Polynomial Type + CRCPOLY: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// CRC Input Source + CRCSRC: u6, + /// CRC Operating Mode + CRCMODE: u2, + }), base_address + 0x2); + + /// address: 0x4100a004 + /// CRC Data Input + pub const CRCDATAIN = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x4100a008 + /// CRC Checksum + pub const CRCCHKSUM = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4100a00c + /// CRC Status + pub const CRCSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// CRC Module Busy + CRCBUSY: u1, + /// CRC Zero + CRCZERO: u1, + /// CRC Error + CRCERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0x4100a00d + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xd); + + /// address: 0x4100a010 + /// Software Trigger Control + pub const SWTRIGCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Software Trigger + SWTRIG0: u1, + /// Channel 1 Software Trigger + SWTRIG1: u1, + /// Channel 2 Software Trigger + SWTRIG2: u1, + /// Channel 3 Software Trigger + SWTRIG3: u1, + /// Channel 4 Software Trigger + SWTRIG4: u1, + /// Channel 5 Software Trigger + SWTRIG5: u1, + /// Channel 6 Software Trigger + SWTRIG6: u1, + /// Channel 7 Software Trigger + SWTRIG7: u1, + /// Channel 8 Software Trigger + SWTRIG8: u1, + /// Channel 9 Software Trigger + SWTRIG9: u1, + /// Channel 10 Software Trigger + SWTRIG10: u1, + /// Channel 11 Software Trigger + SWTRIG11: u1, + /// Channel 12 Software Trigger + SWTRIG12: u1, + /// Channel 13 Software Trigger + SWTRIG13: u1, + /// Channel 14 Software Trigger + SWTRIG14: u1, + /// Channel 15 Software Trigger + SWTRIG15: u1, + /// Channel 16 Software Trigger + SWTRIG16: u1, + /// Channel 17 Software Trigger + SWTRIG17: u1, + /// Channel 18 Software Trigger + SWTRIG18: u1, + /// Channel 19 Software Trigger + SWTRIG19: u1, + /// Channel 20 Software Trigger + SWTRIG20: u1, + /// Channel 21 Software Trigger + SWTRIG21: u1, + /// Channel 22 Software Trigger + SWTRIG22: u1, + /// Channel 23 Software Trigger + SWTRIG23: u1, + /// Channel 24 Software Trigger + SWTRIG24: u1, + /// Channel 25 Software Trigger + SWTRIG25: u1, + /// Channel 26 Software Trigger + SWTRIG26: u1, + /// Channel 27 Software Trigger + SWTRIG27: u1, + /// Channel 28 Software Trigger + SWTRIG28: u1, + /// Channel 29 Software Trigger + SWTRIG29: u1, + /// Channel 30 Software Trigger + SWTRIG30: u1, + /// Channel 31 Software Trigger + SWTRIG31: u1, + }), base_address + 0x10); + + /// address: 0x4100a014 + /// Priority Control 0 + pub const PRICTRL0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Level 0 Channel Priority Number + LVLPRI0: u5, + /// Level 0 Quality of Service + QOS0: u2, + /// Level 0 Round-Robin Scheduling Enable + RRLVLEN0: u1, + /// Level 1 Channel Priority Number + LVLPRI1: u5, + /// Level 1 Quality of Service + QOS1: u2, + /// Level 1 Round-Robin Scheduling Enable + RRLVLEN1: u1, + /// Level 2 Channel Priority Number + LVLPRI2: u5, + /// Level 2 Quality of Service + QOS2: u2, + /// Level 2 Round-Robin Scheduling Enable + RRLVLEN2: u1, + /// Level 3 Channel Priority Number + LVLPRI3: u5, + /// Level 3 Quality of Service + QOS3: u2, + /// Level 3 Round-Robin Scheduling Enable + RRLVLEN3: u1, + }), base_address + 0x14); + + /// address: 0x4100a020 + /// Interrupt Pending + pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel ID + ID: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Transfer Error + TERR: u1, + /// Transfer Complete + TCMPL: u1, + /// Channel Suspend + SUSP: u1, + reserved3: u1, + /// CRC Error + CRCERR: u1, + /// Fetch Error + FERR: u1, + /// Busy + BUSY: u1, + /// Pending + PEND: u1, + }), base_address + 0x20); + + /// address: 0x4100a024 + /// Interrupt Status + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Pending Interrupt + CHINT0: u1, + /// Channel 1 Pending Interrupt + CHINT1: u1, + /// Channel 2 Pending Interrupt + CHINT2: u1, + /// Channel 3 Pending Interrupt + CHINT3: u1, + /// Channel 4 Pending Interrupt + CHINT4: u1, + /// Channel 5 Pending Interrupt + CHINT5: u1, + /// Channel 6 Pending Interrupt + CHINT6: u1, + /// Channel 7 Pending Interrupt + CHINT7: u1, + /// Channel 8 Pending Interrupt + CHINT8: u1, + /// Channel 9 Pending Interrupt + CHINT9: u1, + /// Channel 10 Pending Interrupt + CHINT10: u1, + /// Channel 11 Pending Interrupt + CHINT11: u1, + /// Channel 12 Pending Interrupt + CHINT12: u1, + /// Channel 13 Pending Interrupt + CHINT13: u1, + /// Channel 14 Pending Interrupt + CHINT14: u1, + /// Channel 15 Pending Interrupt + CHINT15: u1, + /// Channel 16 Pending Interrupt + CHINT16: u1, + /// Channel 17 Pending Interrupt + CHINT17: u1, + /// Channel 18 Pending Interrupt + CHINT18: u1, + /// Channel 19 Pending Interrupt + CHINT19: u1, + /// Channel 20 Pending Interrupt + CHINT20: u1, + /// Channel 21 Pending Interrupt + CHINT21: u1, + /// Channel 22 Pending Interrupt + CHINT22: u1, + /// Channel 23 Pending Interrupt + CHINT23: u1, + /// Channel 24 Pending Interrupt + CHINT24: u1, + /// Channel 25 Pending Interrupt + CHINT25: u1, + /// Channel 26 Pending Interrupt + CHINT26: u1, + /// Channel 27 Pending Interrupt + CHINT27: u1, + /// Channel 28 Pending Interrupt + CHINT28: u1, + /// Channel 29 Pending Interrupt + CHINT29: u1, + /// Channel 30 Pending Interrupt + CHINT30: u1, + /// Channel 31 Pending Interrupt + CHINT31: u1, + }), base_address + 0x24); + + /// address: 0x4100a028 + /// Busy Channels + pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Busy Channel 0 + BUSYCH0: u1, + /// Busy Channel 1 + BUSYCH1: u1, + /// Busy Channel 2 + BUSYCH2: u1, + /// Busy Channel 3 + BUSYCH3: u1, + /// Busy Channel 4 + BUSYCH4: u1, + /// Busy Channel 5 + BUSYCH5: u1, + /// Busy Channel 6 + BUSYCH6: u1, + /// Busy Channel 7 + BUSYCH7: u1, + /// Busy Channel 8 + BUSYCH8: u1, + /// Busy Channel 9 + BUSYCH9: u1, + /// Busy Channel 10 + BUSYCH10: u1, + /// Busy Channel 11 + BUSYCH11: u1, + /// Busy Channel 12 + BUSYCH12: u1, + /// Busy Channel 13 + BUSYCH13: u1, + /// Busy Channel 14 + BUSYCH14: u1, + /// Busy Channel 15 + BUSYCH15: u1, + /// Busy Channel 16 + BUSYCH16: u1, + /// Busy Channel 17 + BUSYCH17: u1, + /// Busy Channel 18 + BUSYCH18: u1, + /// Busy Channel 19 + BUSYCH19: u1, + /// Busy Channel 20 + BUSYCH20: u1, + /// Busy Channel 21 + BUSYCH21: u1, + /// Busy Channel 22 + BUSYCH22: u1, + /// Busy Channel 23 + BUSYCH23: u1, + /// Busy Channel 24 + BUSYCH24: u1, + /// Busy Channel 25 + BUSYCH25: u1, + /// Busy Channel 26 + BUSYCH26: u1, + /// Busy Channel 27 + BUSYCH27: u1, + /// Busy Channel 28 + BUSYCH28: u1, + /// Busy Channel 29 + BUSYCH29: u1, + /// Busy Channel 30 + BUSYCH30: u1, + /// Busy Channel 31 + BUSYCH31: u1, + }), base_address + 0x28); + + /// address: 0x4100a02c + /// Pending Channels + pub const PENDCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Pending Channel 0 + PENDCH0: u1, + /// Pending Channel 1 + PENDCH1: u1, + /// Pending Channel 2 + PENDCH2: u1, + /// Pending Channel 3 + PENDCH3: u1, + /// Pending Channel 4 + PENDCH4: u1, + /// Pending Channel 5 + PENDCH5: u1, + /// Pending Channel 6 + PENDCH6: u1, + /// Pending Channel 7 + PENDCH7: u1, + /// Pending Channel 8 + PENDCH8: u1, + /// Pending Channel 9 + PENDCH9: u1, + /// Pending Channel 10 + PENDCH10: u1, + /// Pending Channel 11 + PENDCH11: u1, + /// Pending Channel 12 + PENDCH12: u1, + /// Pending Channel 13 + PENDCH13: u1, + /// Pending Channel 14 + PENDCH14: u1, + /// Pending Channel 15 + PENDCH15: u1, + /// Pending Channel 16 + PENDCH16: u1, + /// Pending Channel 17 + PENDCH17: u1, + /// Pending Channel 18 + PENDCH18: u1, + /// Pending Channel 19 + PENDCH19: u1, + /// Pending Channel 20 + PENDCH20: u1, + /// Pending Channel 21 + PENDCH21: u1, + /// Pending Channel 22 + PENDCH22: u1, + /// Pending Channel 23 + PENDCH23: u1, + /// Pending Channel 24 + PENDCH24: u1, + /// Pending Channel 25 + PENDCH25: u1, + /// Pending Channel 26 + PENDCH26: u1, + /// Pending Channel 27 + PENDCH27: u1, + /// Pending Channel 28 + PENDCH28: u1, + /// Pending Channel 29 + PENDCH29: u1, + /// Pending Channel 30 + PENDCH30: u1, + /// Pending Channel 31 + PENDCH31: u1, + }), base_address + 0x2c); + + /// address: 0x4100a030 + /// Active Channel and Levels + pub const ACTIVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Level 0 Channel Trigger Request Executing + LVLEX0: u1, + /// Level 1 Channel Trigger Request Executing + LVLEX1: u1, + /// Level 2 Channel Trigger Request Executing + LVLEX2: u1, + /// Level 3 Channel Trigger Request Executing + LVLEX3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Active Channel ID + ID: u5, + reserved4: u1, + reserved5: u1, + /// Active Channel Busy + ABUSY: u1, + /// Active Channel Block Transfer Count + BTCNT: u16, + }), base_address + 0x30); + + /// address: 0x4100a034 + /// Descriptor Memory Section Base Address + pub const BASEADDR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x4100a038 + /// Write-Back Memory Section Base Address + pub const WRBADDR = @intToPtr(*volatile u32, base_address + 0x38); + + pub const CHANNEL = @ptrCast(*volatile [32]packed struct { + /// Channel n Control A + CHCTRLA: Mmio(32, packed struct { + /// Channel Software Reset + SWRST: u1, + /// Channel Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Channel Run in Standby + RUNSTDBY: u1, + reserved4: u1, + /// Trigger Source + TRIGSRC: u7, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Trigger Action + TRIGACT: u2, + reserved10: u1, + reserved11: u1, + /// Burst Length + BURSTLEN: u4, + /// FIFO Threshold + THRESHOLD: u2, + padding0: u1, + padding1: u1, + }), + + /// Channel n Control B + CHCTRLB: Mmio(8, packed struct { + /// Software Command + CMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Priority Level + CHPRILVL: Mmio(8, packed struct { + /// Channel Priority Level + PRILVL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Event Control + CHEVCTRL: Mmio(8, packed struct { + /// Channel Event Input Action + EVACT: u3, + reserved0: u1, + /// Channel Event Output Mode + EVOMODE: u2, + /// Channel Event Input Enable + EVIE: u1, + /// Channel Event Output Enable + EVOE: u1, + }), + + /// Channel n Interrupt Enable Clear + CHINTENCLR: Mmio(8, packed struct { + /// Channel Transfer Error Interrupt Enable + TERR: u1, + /// Channel Transfer Complete Interrupt Enable + TCMPL: u1, + /// Channel Suspend Interrupt Enable + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Interrupt Enable Set + CHINTENSET: Mmio(8, packed struct { + /// Channel Transfer Error Interrupt Enable + TERR: u1, + /// Channel Transfer Complete Interrupt Enable + TCMPL: u1, + /// Channel Suspend Interrupt Enable + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Interrupt Flag Status and Clear + CHINTFLAG: Mmio(8, packed struct { + /// Channel Transfer Error + TERR: u1, + /// Channel Transfer Complete + TCMPL: u1, + /// Channel Suspend + SUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// Channel n Status + CHSTATUS: Mmio(8, packed struct { + /// Channel Pending + PEND: u1, + /// Channel Busy + BUSY: u1, + /// Channel Fetch Error + FERR: u1, + /// Channel CRC Error + CRCERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), + padding0: u32, + }, base_address + 0x40); + }; + + /// Device Service Unit + pub const DSU = struct { + pub const base_address = 0x41002000; + pub const version = "U24101.0.0"; + + /// address: 0x41002000 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + reserved0: u1, + /// 32-bit Cyclic Redundancy Code + CRC: u1, + /// Memory built-in self-test + MBIST: u1, + /// Chip-Erase + CE: u1, + reserved1: u1, + /// Auxiliary Row Read + ARR: u1, + /// Start Memory Stream Access + SMSA: u1, + }), base_address + 0x0); + + /// address: 0x41002001 + /// Status A + pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { + /// Done + DONE: u1, + /// CPU Reset Phase Extension + CRSTEXT: u1, + /// Bus Error + BERR: u1, + /// Failure + FAIL: u1, + /// Protection Error + PERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x1); + + /// address: 0x41002002 + /// Status B + pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { + /// Protected + PROT: u1, + /// Debugger Present + DBGPRES: u1, + /// Debug Communication Channel 0 Dirty + DCCD0: u1, + /// Debug Communication Channel 1 Dirty + DCCD1: u1, + /// Hot-Plugging Enable + HPE: u1, + /// Chip Erase Locked + CELCK: u1, + /// Test Debug Communication Channel 0 Dirty + TDCCD0: u1, + /// Test Debug Communication Channel 1 Dirty + TDCCD1: u1, + }), base_address + 0x2); + + /// address: 0x41002004 + /// Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Access Mode + AMOD: u2, + /// Address + ADDR: u30, + }), base_address + 0x4); + + /// address: 0x41002008 + /// Length + pub const LENGTH = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x8); + + /// address: 0x4100200c + /// Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x41002010 + /// Debug Communication Channel n + pub const DCC = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Data + DATA: u32, + }), base_address + 0x10); + + /// address: 0x41002018 + /// Device Identification + pub const DID = @intToPtr(*volatile Mmio(32, packed struct { + /// Device Select + DEVSEL: u8, + /// Revision Number + REVISION: u4, + /// Die Number + DIE: u4, + /// Series + SERIES: u6, + reserved0: u1, + /// Family + FAMILY: u5, + /// Processor + PROCESSOR: u4, + }), base_address + 0x18); + + /// address: 0x4100201c + /// Configuration + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Latency Quality Of Service + LQOS: u2, + /// DMA Trigger Level + DCCDMALEVEL: u2, + /// Trace Control + ETBRAMEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x410020f0 + /// Device Configuration + pub const DCFG = @intToPtr(*volatile [2]u32, base_address + 0xf0); + + /// address: 0x41003000 + /// CoreSight ROM Table Entry 0 + pub const ENTRY0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Entry Present + EPRES: u1, + /// Format + FMT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Address Offset + ADDOFF: u20, + }), base_address + 0x1000); + + /// address: 0x41003004 + /// CoreSight ROM Table Entry 1 + pub const ENTRY1 = @intToPtr(*volatile u32, base_address + 0x1004); + + /// address: 0x41003008 + /// CoreSight ROM Table End + pub const END = @intToPtr(*volatile u32, base_address + 0x1008); + + /// address: 0x41003fcc + /// CoreSight ROM Table Memory Type + pub const MEMTYPE = @intToPtr(*volatile Mmio(32, packed struct { + /// System Memory Present + SMEMP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x1fcc); + + /// address: 0x41003fd0 + /// Peripheral Identification 4 + pub const PID4 = @intToPtr(*volatile Mmio(32, packed struct { + /// JEP-106 Continuation Code + JEPCC: u4, + /// 4KB count + FKBC: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fd0); + + /// address: 0x41003fd4 + /// Peripheral Identification 5 + pub const PID5 = @intToPtr(*volatile u32, base_address + 0x1fd4); + + /// address: 0x41003fd8 + /// Peripheral Identification 6 + pub const PID6 = @intToPtr(*volatile u32, base_address + 0x1fd8); + + /// address: 0x41003fdc + /// Peripheral Identification 7 + pub const PID7 = @intToPtr(*volatile u32, base_address + 0x1fdc); + + /// address: 0x41003fe0 + /// Peripheral Identification 0 + pub const PID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Part Number Low + PARTNBL: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe0); + + /// address: 0x41003fe4 + /// Peripheral Identification 1 + pub const PID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Part Number High + PARTNBH: u4, + /// Low part of the JEP-106 Identity Code + JEPIDCL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe4); + + /// address: 0x41003fe8 + /// Peripheral Identification 2 + pub const PID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// JEP-106 Identity Code High + JEPIDCH: u3, + /// JEP-106 Identity Code is used + JEPU: u1, + /// Revision Number + REVISION: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fe8); + + /// address: 0x41003fec + /// Peripheral Identification 3 + pub const PID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// ARM CUSMOD + CUSMOD: u4, + /// Revision Number + REVAND: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1fec); + + /// address: 0x41003ff0 + /// Component Identification 0 + pub const CID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 0 + PREAMBLEB0: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff0); + + /// address: 0x41003ff4 + /// Component Identification 1 + pub const CID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble + PREAMBLE: u4, + /// Component Class + CCLASS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff4); + + /// address: 0x41003ff8 + /// Component Identification 2 + pub const CID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 2 + PREAMBLEB2: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ff8); + + /// address: 0x41003ffc + /// Component Identification 3 + pub const CID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Preamble Byte 3 + PREAMBLEB3: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x1ffc); + }; + + /// External Interrupt Controller + pub const EIC = struct { + pub const base_address = 0x40002800; + pub const version = "U22543.0.0"; + + /// address: 0x40002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + /// Clock Selection + CKSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40002801 + /// Non-Maskable Interrupt Control + pub const NMICTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Non-Maskable Interrupt Sense Configuration + NMISENSE: u3, + /// Non-Maskable Interrupt Filter Enable + NMIFILTEN: u1, + /// Asynchronous Edge Detection Mode + NMIASYNCH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x1); + + /// address: 0x40002802 + /// Non-Maskable Interrupt Flag Status and Clear + pub const NMIFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Non-Maskable Interrupt + NMI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x2); + + /// address: 0x40002804 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy Status + SWRST: u1, + /// Enable Synchronization Busy Status + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x40002808 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Event Output Enable + EXTINTEO: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x4000280c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Enable + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x40002810 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt Enable + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40002814 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// External Interrupt + EXTINT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40002818 + /// External Interrupt Asynchronous Mode + pub const ASYNCH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4000281c + /// External Interrupt Sense Configuration + pub const CONFIG = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Input Sense Configuration 0 + SENSE0: u3, + /// Filter Enable 0 + FILTEN0: u1, + /// Input Sense Configuration 1 + SENSE1: u3, + /// Filter Enable 1 + FILTEN1: u1, + /// Input Sense Configuration 2 + SENSE2: u3, + /// Filter Enable 2 + FILTEN2: u1, + /// Input Sense Configuration 3 + SENSE3: u3, + /// Filter Enable 3 + FILTEN3: u1, + /// Input Sense Configuration 4 + SENSE4: u3, + /// Filter Enable 4 + FILTEN4: u1, + /// Input Sense Configuration 5 + SENSE5: u3, + /// Filter Enable 5 + FILTEN5: u1, + /// Input Sense Configuration 6 + SENSE6: u3, + /// Filter Enable 6 + FILTEN6: u1, + /// Input Sense Configuration 7 + SENSE7: u3, + /// Filter Enable 7 + FILTEN7: u1, + }), base_address + 0x1c); + + /// address: 0x40002830 + /// Debouncer Enable + pub const DEBOUNCEN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x30); + + /// address: 0x40002834 + /// Debouncer Prescaler + pub const DPRESCALER = @intToPtr(*volatile Mmio(32, packed struct { + /// Debouncer Prescaler + PRESCALER0: u3, + /// Debouncer number of states + STATES0: u1, + /// Debouncer Prescaler + PRESCALER1: u3, + /// Debouncer number of states + STATES1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Pin Sampler frequency selection + TICKON: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x34); + + /// address: 0x40002838 + /// Pin State + pub const PINSTATE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + }; + + /// Event System Interface + pub const EVSYS = struct { + pub const base_address = 0x4100e000; + pub const version = "U25041.0.0"; + + /// address: 0x4100e000 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x4100e004 + /// Software Event + pub const SWEVT = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Software Selection + CHANNEL0: u1, + /// Channel 1 Software Selection + CHANNEL1: u1, + /// Channel 2 Software Selection + CHANNEL2: u1, + /// Channel 3 Software Selection + CHANNEL3: u1, + /// Channel 4 Software Selection + CHANNEL4: u1, + /// Channel 5 Software Selection + CHANNEL5: u1, + /// Channel 6 Software Selection + CHANNEL6: u1, + /// Channel 7 Software Selection + CHANNEL7: u1, + /// Channel 8 Software Selection + CHANNEL8: u1, + /// Channel 9 Software Selection + CHANNEL9: u1, + /// Channel 10 Software Selection + CHANNEL10: u1, + /// Channel 11 Software Selection + CHANNEL11: u1, + /// Channel 12 Software Selection + CHANNEL12: u1, + /// Channel 13 Software Selection + CHANNEL13: u1, + /// Channel 14 Software Selection + CHANNEL14: u1, + /// Channel 15 Software Selection + CHANNEL15: u1, + /// Channel 16 Software Selection + CHANNEL16: u1, + /// Channel 17 Software Selection + CHANNEL17: u1, + /// Channel 18 Software Selection + CHANNEL18: u1, + /// Channel 19 Software Selection + CHANNEL19: u1, + /// Channel 20 Software Selection + CHANNEL20: u1, + /// Channel 21 Software Selection + CHANNEL21: u1, + /// Channel 22 Software Selection + CHANNEL22: u1, + /// Channel 23 Software Selection + CHANNEL23: u1, + /// Channel 24 Software Selection + CHANNEL24: u1, + /// Channel 25 Software Selection + CHANNEL25: u1, + /// Channel 26 Software Selection + CHANNEL26: u1, + /// Channel 27 Software Selection + CHANNEL27: u1, + /// Channel 28 Software Selection + CHANNEL28: u1, + /// Channel 29 Software Selection + CHANNEL29: u1, + /// Channel 30 Software Selection + CHANNEL30: u1, + /// Channel 31 Software Selection + CHANNEL31: u1, + }), base_address + 0x4); + + /// address: 0x4100e008 + /// Priority Control + pub const PRICTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Channel Priority Number + PRI: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Round-Robin Scheduling Enable + RREN: u1, + }), base_address + 0x8); + + /// address: 0x4100e010 + /// Channel Pending Interrupt + pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { + /// Channel ID + ID: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Channel Overrun + OVR: u1, + /// Channel Event Detected + EVD: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Ready + READY: u1, + /// Busy + BUSY: u1, + }), base_address + 0x10); + + /// address: 0x4100e014 + /// Interrupt Status + pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Channel 0 Pending Interrupt + CHINT0: u1, + /// Channel 1 Pending Interrupt + CHINT1: u1, + /// Channel 2 Pending Interrupt + CHINT2: u1, + /// Channel 3 Pending Interrupt + CHINT3: u1, + /// Channel 4 Pending Interrupt + CHINT4: u1, + /// Channel 5 Pending Interrupt + CHINT5: u1, + /// Channel 6 Pending Interrupt + CHINT6: u1, + /// Channel 7 Pending Interrupt + CHINT7: u1, + /// Channel 8 Pending Interrupt + CHINT8: u1, + /// Channel 9 Pending Interrupt + CHINT9: u1, + /// Channel 10 Pending Interrupt + CHINT10: u1, + /// Channel 11 Pending Interrupt + CHINT11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x14); + + /// address: 0x4100e018 + /// Busy Channels + pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { + /// Busy Channel 0 + BUSYCH0: u1, + /// Busy Channel 1 + BUSYCH1: u1, + /// Busy Channel 2 + BUSYCH2: u1, + /// Busy Channel 3 + BUSYCH3: u1, + /// Busy Channel 4 + BUSYCH4: u1, + /// Busy Channel 5 + BUSYCH5: u1, + /// Busy Channel 6 + BUSYCH6: u1, + /// Busy Channel 7 + BUSYCH7: u1, + /// Busy Channel 8 + BUSYCH8: u1, + /// Busy Channel 9 + BUSYCH9: u1, + /// Busy Channel 10 + BUSYCH10: u1, + /// Busy Channel 11 + BUSYCH11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x18); + + /// address: 0x4100e01c + /// Ready Users + pub const READYUSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Ready User for Channel 0 + READYUSR0: u1, + /// Ready User for Channel 1 + READYUSR1: u1, + /// Ready User for Channel 2 + READYUSR2: u1, + /// Ready User for Channel 3 + READYUSR3: u1, + /// Ready User for Channel 4 + READYUSR4: u1, + /// Ready User for Channel 5 + READYUSR5: u1, + /// Ready User for Channel 6 + READYUSR6: u1, + /// Ready User for Channel 7 + READYUSR7: u1, + /// Ready User for Channel 8 + READYUSR8: u1, + /// Ready User for Channel 9 + READYUSR9: u1, + /// Ready User for Channel 10 + READYUSR10: u1, + /// Ready User for Channel 11 + READYUSR11: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x1c); + + /// address: 0x4100e120 + /// User Multiplexer n + pub const USER = @intToPtr(*volatile [67]Mmio(32, packed struct { + /// Channel Event Selection + CHANNEL: u6, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + }), base_address + 0x120); + + pub const CHANNEL = @ptrCast(*volatile [32]packed struct { + /// Channel n Control + CHANNEL: Mmio(32, packed struct { + /// Event Generator Selection + EVGEN: u7, + reserved0: u1, + /// Path Selection + PATH: u2, + /// Edge Detection Selection + EDGSEL: u2, + reserved1: u1, + reserved2: u1, + /// Run in standby + RUNSTDBY: u1, + /// Generic Clock On Demand + ONDEMAND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), + + /// Channel n Interrupt Enable Clear + CHINTENCLR: Mmio(8, packed struct { + /// Channel Overrun Interrupt Disable + OVR: u1, + /// Channel Event Detected Interrupt Disable + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Interrupt Enable Set + CHINTENSET: Mmio(8, packed struct { + /// Channel Overrun Interrupt Enable + OVR: u1, + /// Channel Event Detected Interrupt Enable + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Interrupt Flag Status and Clear + CHINTFLAG: Mmio(8, packed struct { + /// Channel Overrun + OVR: u1, + /// Channel Event Detected + EVD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + + /// Channel n Status + CHSTATUS: Mmio(8, packed struct { + /// Ready User + RDYUSR: u1, + /// Busy Channel + BUSYCH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), + }, base_address + 0x20); + }; + + /// Frequency Meter + pub const FREQM = struct { + pub const base_address = 0x40002c00; + pub const version = "U22571.1.0"; + + /// address: 0x40002c00 + /// Control A Register + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40002c01 + /// Control B Register + pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Start Measurement + START: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1); + + /// address: 0x40002c02 + /// Config A register + pub const CFGA = @intToPtr(*volatile Mmio(16, packed struct { + /// Number of Reference Clock Cycles + REFNUM: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x2); + + /// address: 0x40002c08 + /// Interrupt Enable Clear Register + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done Interrupt Enable + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40002c09 + /// Interrupt Enable Set Register + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done Interrupt Enable + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x40002c0a + /// Interrupt Flag Register + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Measurement Done + DONE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xa); + + /// address: 0x40002c0b + /// Status Register + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// FREQM Status + BUSY: u1, + /// Sticky Count Value Overflow + OVF: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xb); + + /// address: 0x40002c0c + /// Synchronization Busy Register + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x40002c10 + /// Count Value Register + pub const VALUE = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x10); + }; + + /// Generic Clock Generator + pub const GCLK = struct { + pub const base_address = 0x40001c00; + pub const version = "U21221.2.0"; + + /// address: 0x40001c00 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x40001c04 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchroniation Busy bit + SWRST: u1, + reserved0: u1, + /// Generic Clock Generator Control n Synchronization Busy bits + GENCTRL: u12, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x4); + + /// address: 0x40001c20 + /// Generic Clock Generator Control + pub const GENCTRL = @intToPtr(*volatile [12]Mmio(32, packed struct { + /// Source Select + SRC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Generic Clock Generator Enable + GENEN: u1, + /// Improve Duty Cycle + IDC: u1, + /// Output Off Value + OOV: u1, + /// Output Enable + OE: u1, + /// Divide Selection + DIVSEL: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved4: u1, + reserved5: u1, + /// Division Factor + DIV: u16, + }), base_address + 0x20); + + /// address: 0x40001c80 + /// Peripheral Clock Control + pub const PCHCTRL = @intToPtr(*volatile [48]Mmio(32, packed struct { + /// Generic Clock Generator + GEN: u4, + reserved0: u1, + reserved1: u1, + /// Channel Enable + CHEN: u1, + /// Write Lock + WRTLOCK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x80); + }; + + /// HSB Matrix + pub const HMATRIX = struct { + pub const base_address = 0x4100c000; + pub const version = "I76382.1.4"; + + pub const PRS = @ptrCast(*volatile [16]packed struct { + /// Priority A for Slave + PRAS: u32, + + /// Priority B for Slave + PRBS: u32, + }, base_address + 0x80); + }; + + /// Integrity Check Monitor + pub const ICM = struct { + pub const base_address = 0x42002c00; + pub const version = "U20101.2.0"; + + /// address: 0x42002c00 + /// Configuration + pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Back Disable + WBDIS: u1, + /// End of Monitoring Disable + EOMDIS: u1, + /// Secondary List Branching Disable + SLBDIS: u1, + reserved0: u1, + /// Bus Burden Control + BBC: u4, + /// Automatic Switch To Compare Digest + ASCD: u1, + /// Dual Input Buffer + DUALBUFF: u1, + reserved1: u1, + reserved2: u1, + /// User Initial Hash Value + UIHASH: u1, + /// User SHA Algorithm + UALGO: u3, + /// Region Hash Area Protection + HAPROT: u6, + reserved3: u1, + reserved4: u1, + /// Region Descriptor Area Protection + DAPROT: u6, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42002c04 + /// Control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// ICM Enable + ENABLE: u1, + /// ICM Disable Register + DISABLE: u1, + /// Software Reset + SWRST: u1, + reserved0: u1, + /// Recompute Internal Hash + REHASH: u4, + /// Region Monitoring Disable + RMDIS: u4, + /// Region Monitoring Enable + RMEN: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x4); + + /// address: 0x42002c08 + /// Status + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// ICM Controller Enable Register + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// RAW Region Monitoring Disabled Status + RAWRMDIS: u4, + /// Region Monitoring Disabled Status + RMDIS: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x8); + + /// address: 0x42002c10 + /// Interrupt Enable + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Enable + RHC: u4, + /// Region Digest Mismatch Interrupt Enable + RDM: u4, + /// Region Bus Error Interrupt Enable + RBE: u4, + /// Region Wrap Condition detected Interrupt Enable + RWC: u4, + /// Region End bit Condition Detected Interrupt Enable + REC: u4, + /// Region Status Updated Interrupt Disable + RSU: u4, + /// Undefined Register Access Detection Interrupt Enable + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x10); + + /// address: 0x42002c14 + /// Interrupt Disable + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Disable + RHC: u4, + /// Region Digest Mismatch Interrupt Disable + RDM: u4, + /// Region Bus Error Interrupt Disable + RBE: u4, + /// Region Wrap Condition Detected Interrupt Disable + RWC: u4, + /// Region End bit Condition detected Interrupt Disable + REC: u4, + /// Region Status Updated Interrupt Disable + RSU: u4, + /// Undefined Register Access Detection Interrupt Disable + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x14); + + /// address: 0x42002c18 + /// Interrupt Mask + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed Interrupt Mask + RHC: u4, + /// Region Digest Mismatch Interrupt Mask + RDM: u4, + /// Region Bus Error Interrupt Mask + RBE: u4, + /// Region Wrap Condition Detected Interrupt Mask + RWC: u4, + /// Region End bit Condition Detected Interrupt Mask + REC: u4, + /// Region Status Updated Interrupt Mask + RSU: u4, + /// Undefined Register Access Detection Interrupt Mask + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x18); + + /// address: 0x42002c1c + /// Interrupt Status + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Hash Completed + RHC: u4, + /// Region Digest Mismatch + RDM: u4, + /// Region Bus Error + RBE: u4, + /// Region Wrap Condition Detected + RWC: u4, + /// Region End bit Condition Detected + REC: u4, + /// Region Status Updated Detected + RSU: u4, + /// Undefined Register Access Detection Status + URAD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1c); + + /// address: 0x42002c20 + /// Undefined Access Status + pub const UASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Undefined Register Access Trace + URAT: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x20); + + /// address: 0x42002c30 + /// Region Descriptor Area Start Address + pub const DSCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Descriptor Area Start Address + DASA: u26, + }), base_address + 0x30); + + /// address: 0x42002c34 + /// Region Hash Area Start Address + pub const HASH = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Hash Area Start Address + HASA: u25, + }), base_address + 0x34); + + /// address: 0x42002c38 + /// User Initial Hash Value n + pub const UIHVAL = @intToPtr(*volatile [8]Mmio(32, packed struct { + /// Initial Hash Value + VAL: u32, + }), base_address + 0x38); + }; + + /// Inter-IC Sound Interface + pub const I2S = struct { + pub const base_address = 0x43002800; + pub const version = "U22242.0.0"; + + /// address: 0x43002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Clock Unit 0 Enable + CKEN0: u1, + /// Clock Unit 1 Enable + CKEN1: u1, + /// Tx Serializer Enable + TXEN: u1, + /// Rx Serializer Enable + RXEN: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x43002804 + /// Clock Unit n Control + pub const CLKCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Slot Size + SLOTSIZE: u2, + /// Number of Slots in Frame + NBSLOTS: u3, + /// Frame Sync Width + FSWIDTH: u2, + /// Data Delay from Frame Sync + BITDELAY: u1, + /// Frame Sync Select + FSSEL: u1, + /// Frame Sync Invert + FSINV: u1, + /// Frame Sync Output Invert + FSOUTINV: u1, + /// Serial Clock Select + SCKSEL: u1, + /// Serial Clock Output Invert + SCKOUTINV: u1, + /// Master Clock Select + MCKSEL: u1, + /// Master Clock Enable + MCKEN: u1, + /// Master Clock Output Invert + MCKOUTINV: u1, + /// Master Clock Division Factor + MCKDIV: u6, + reserved0: u1, + reserved1: u1, + /// Master Clock Output Division Factor + MCKOUTDIV: u6, + padding0: u1, + padding1: u1, + }), base_address + 0x4); + + /// address: 0x4300280c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 Interrupt Enable + RXRDY0: u1, + /// Receive Ready 1 Interrupt Enable + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 Interrupt Enable + RXOR0: u1, + /// Receive Overrun 1 Interrupt Enable + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 Interrupt Enable + TXRDY0: u1, + /// Transmit Ready 1 Interrupt Enable + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 Interrupt Enable + TXUR0: u1, + /// Transmit Underrun 1 Interrupt Enable + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x43002810 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 Interrupt Enable + RXRDY0: u1, + /// Receive Ready 1 Interrupt Enable + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 Interrupt Enable + RXOR0: u1, + /// Receive Overrun 1 Interrupt Enable + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 Interrupt Enable + TXRDY0: u1, + /// Transmit Ready 1 Interrupt Enable + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 Interrupt Enable + TXUR0: u1, + /// Transmit Underrun 1 Interrupt Enable + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x43002814 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Receive Ready 0 + RXRDY0: u1, + /// Receive Ready 1 + RXRDY1: u1, + reserved0: u1, + reserved1: u1, + /// Receive Overrun 0 + RXOR0: u1, + /// Receive Overrun 1 + RXOR1: u1, + reserved2: u1, + reserved3: u1, + /// Transmit Ready 0 + TXRDY0: u1, + /// Transmit Ready 1 + TXRDY1: u1, + reserved4: u1, + reserved5: u1, + /// Transmit Underrun 0 + TXUR0: u1, + /// Transmit Underrun 1 + TXUR1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x14); + + /// address: 0x43002818 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset Synchronization Status + SWRST: u1, + /// Enable Synchronization Status + ENABLE: u1, + /// Clock Unit 0 Enable Synchronization Status + CKEN0: u1, + /// Clock Unit 1 Enable Synchronization Status + CKEN1: u1, + /// Tx Serializer Enable Synchronization Status + TXEN: u1, + /// Rx Serializer Enable Synchronization Status + RXEN: u1, + reserved0: u1, + reserved1: u1, + /// Tx Data Synchronization Status + TXDATA: u1, + /// Rx Data Synchronization Status + RXDATA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x43002820 + /// Tx Serializer Control + pub const TXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Serializer Mode + SERMODE: u2, + /// Line Default Line when Slot Disabled + TXDEFAULT: u2, + /// Transmit Data when Underrun + TXSAME: u1, + /// Clock Unit Selection + CLKSEL: u1, + reserved0: u1, + /// Data Slot Formatting Adjust + SLOTADJ: u1, + /// Data Word Size + DATASIZE: u3, + reserved1: u1, + /// Data Word Formatting Adjust + WORDADJ: u1, + /// Data Formatting Bit Extension + EXTEND: u2, + /// Data Formatting Bit Reverse + BITREV: u1, + /// Slot 0 Disabled for this Serializer + SLOTDIS0: u1, + /// Slot 1 Disabled for this Serializer + SLOTDIS1: u1, + /// Slot 2 Disabled for this Serializer + SLOTDIS2: u1, + /// Slot 3 Disabled for this Serializer + SLOTDIS3: u1, + /// Slot 4 Disabled for this Serializer + SLOTDIS4: u1, + /// Slot 5 Disabled for this Serializer + SLOTDIS5: u1, + /// Slot 6 Disabled for this Serializer + SLOTDIS6: u1, + /// Slot 7 Disabled for this Serializer + SLOTDIS7: u1, + /// Mono Mode + MONO: u1, + /// Single or Multiple DMA Channels + DMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x20); + + /// address: 0x43002824 + /// Rx Serializer Control + pub const RXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Serializer Mode + SERMODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Clock Unit Selection + CLKSEL: u1, + reserved3: u1, + /// Data Slot Formatting Adjust + SLOTADJ: u1, + /// Data Word Size + DATASIZE: u3, + reserved4: u1, + /// Data Word Formatting Adjust + WORDADJ: u1, + /// Data Formatting Bit Extension + EXTEND: u2, + /// Data Formatting Bit Reverse + BITREV: u1, + /// Slot 0 Disabled for this Serializer + SLOTDIS0: u1, + /// Slot 1 Disabled for this Serializer + SLOTDIS1: u1, + /// Slot 2 Disabled for this Serializer + SLOTDIS2: u1, + /// Slot 3 Disabled for this Serializer + SLOTDIS3: u1, + /// Slot 4 Disabled for this Serializer + SLOTDIS4: u1, + /// Slot 5 Disabled for this Serializer + SLOTDIS5: u1, + /// Slot 6 Disabled for this Serializer + SLOTDIS6: u1, + /// Slot 7 Disabled for this Serializer + SLOTDIS7: u1, + /// Mono Mode + MONO: u1, + /// Single or Multiple DMA Channels + DMA: u1, + /// Loop-back Test Mode + RXLOOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x43002830 + /// Tx Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample Data + DATA: u32, + }), base_address + 0x30); + + /// address: 0x43002834 + /// Rx Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Sample Data + DATA: u32, + }), base_address + 0x34); + }; + + /// Main Clock + pub const MCLK = struct { + pub const base_address: usize = 0x40000800; + pub const version = "U24081.0.0"; + + /// address: 0x40000801 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready Interrupt Enable + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x1); + + /// address: 0x40000802 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready Interrupt Enable + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x2); + + /// address: 0x40000803 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Ready + CKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x40000804 + /// HS Clock Division + pub const HSDIV = @intToPtr(*volatile Mmio(8, packed struct { + /// CPU Clock Division Factor + DIV: u8, + }), base_address + 0x4); + + /// address: 0x40000805 + /// CPU Clock Division + pub const CPUDIV = @intToPtr(*volatile Mmio(8, packed struct { + /// Low-Power Clock Division Factor + DIV: u8, + }), base_address + 0x5); + + /// address: 0x40000810 + /// AHB Mask + pub const AHBMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// HPB0 AHB Clock Mask + HPB0_: u1, + /// HPB1 AHB Clock Mask + HPB1_: u1, + /// HPB2 AHB Clock Mask + HPB2_: u1, + /// HPB3 AHB Clock Mask + HPB3_: u1, + /// DSU AHB Clock Mask + DSU_: u1, + /// HMATRIX AHB Clock Mask + HMATRIX_: u1, + /// NVMCTRL AHB Clock Mask + NVMCTRL_: u1, + /// HSRAM AHB Clock Mask + HSRAM_: u1, + /// CMCC AHB Clock Mask + CMCC_: u1, + /// DMAC AHB Clock Mask + DMAC_: u1, + /// USB AHB Clock Mask + USB_: u1, + /// BKUPRAM AHB Clock Mask + BKUPRAM_: u1, + /// PAC AHB Clock Mask + PAC_: u1, + /// QSPI AHB Clock Mask + QSPI_: u1, + reserved0: u1, + /// SDHC0 AHB Clock Mask + SDHC0_: u1, + reserved1: u1, + /// CAN0 AHB Clock Mask + CAN0_: u1, + /// CAN1 AHB Clock Mask + CAN1_: u1, + /// ICM AHB Clock Mask + ICM_: u1, + /// PUKCC AHB Clock Mask + PUKCC_: u1, + /// QSPI_2X AHB Clock Mask + QSPI_2X_: u1, + /// NVMCTRL_SMEEPROM AHB Clock Mask + NVMCTRL_SMEEPROM_: u1, + /// NVMCTRL_CACHE AHB Clock Mask + NVMCTRL_CACHE_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x10); + + /// address: 0x40000814 + /// APBA Mask + pub const APBAMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC APB Clock Enable + PAC_: u1, + /// PM APB Clock Enable + PM_: u1, + /// MCLK APB Clock Enable + MCLK_: u1, + /// RSTC APB Clock Enable + RSTC_: u1, + /// OSCCTRL APB Clock Enable + OSCCTRL_: u1, + /// OSC32KCTRL APB Clock Enable + OSC32KCTRL_: u1, + /// SUPC APB Clock Enable + SUPC_: u1, + /// GCLK APB Clock Enable + GCLK_: u1, + /// WDT APB Clock Enable + WDT_: u1, + /// RTC APB Clock Enable + RTC_: u1, + /// EIC APB Clock Enable + EIC_: u1, + /// FREQM APB Clock Enable + FREQM_: u1, + /// SERCOM0 APB Clock Enable + SERCOM0_: u1, + /// SERCOM1 APB Clock Enable + SERCOM1_: u1, + /// TC0 APB Clock Enable + TC0_: u1, + /// TC1 APB Clock Enable + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40000818 + /// APBB Mask + pub const APBBMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// USB APB Clock Enable + USB_: u1, + /// DSU APB Clock Enable + DSU_: u1, + /// NVMCTRL APB Clock Enable + NVMCTRL_: u1, + reserved0: u1, + /// PORT APB Clock Enable + PORT_: u1, + reserved1: u1, + /// HMATRIX APB Clock Enable + HMATRIX_: u1, + /// EVSYS APB Clock Enable + EVSYS_: u1, + reserved2: u1, + /// SERCOM2 APB Clock Enable + SERCOM2_: u1, + /// SERCOM3 APB Clock Enable + SERCOM3_: u1, + /// TCC0 APB Clock Enable + TCC0_: u1, + /// TCC1 APB Clock Enable + TCC1_: u1, + /// TC2 APB Clock Enable + TC2_: u1, + /// TC3 APB Clock Enable + TC3_: u1, + reserved3: u1, + /// RAMECC APB Clock Enable + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x4000081c + /// APBC Mask + pub const APBCMASK = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// TCC2 APB Clock Enable + TCC2_: u1, + /// TCC3 APB Clock Enable + TCC3_: u1, + /// TC4 APB Clock Enable + TC4_: u1, + /// TC5 APB Clock Enable + TC5_: u1, + /// PDEC APB Clock Enable + PDEC_: u1, + /// AC APB Clock Enable + AC_: u1, + /// AES APB Clock Enable + AES_: u1, + /// TRNG APB Clock Enable + TRNG_: u1, + /// ICM APB Clock Enable + ICM_: u1, + reserved3: u1, + /// QSPI APB Clock Enable + QSPI_: u1, + /// CCL APB Clock Enable + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40000820 + /// APBD Mask + pub const APBDMASK = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 APB Clock Enable + SERCOM4_: u1, + /// SERCOM5 APB Clock Enable + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 APB Clock Enable + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 APB Clock Enable + ADC0_: u1, + /// ADC1 APB Clock Enable + ADC1_: u1, + /// DAC APB Clock Enable + DAC_: u1, + /// I2S APB Clock Enable + I2S_: u1, + /// PCC APB Clock Enable + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + }; + + /// Non-Volatile Memory Controller + pub const NVMCTRL = struct { + pub const base_address = 0x41004000; + pub const version = "U24091.0.0"; + + /// address: 0x41004000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Auto Wait State Enable + AUTOWS: u1, + /// Suspend Enable + SUSPEN: u1, + /// Write Mode + WMODE: u2, + /// Power Reduction Mode during Sleep + PRM: u2, + /// NVM Read Wait States + RWS: u4, + /// Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated + AHBNS0: u1, + /// Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated + AHBNS1: u1, + /// AHB0 Cache Disable + CACHEDIS0: u1, + /// AHB1 Cache Disable + CACHEDIS1: u1, + }), base_address + 0x0); + + /// address: 0x41004004 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Command + CMD: u7, + reserved0: u1, + /// Command Execution + CMDEX: u8, + }), base_address + 0x4); + + /// address: 0x41004008 + /// NVM Parameter + pub const PARAM = @intToPtr(*volatile Mmio(32, packed struct { + /// NVM Pages + NVMP: u16, + /// Page Size + PSZ: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// SmartEEPROM Supported + SEE: u1, + }), base_address + 0x8); + + /// address: 0x4100400c + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done Interrupt Clear + DONE: u1, + /// Address Error + ADDRE: u1, + /// Programming Error Interrupt Clear + PROGE: u1, + /// Lock Error Interrupt Clear + LOCKE: u1, + /// ECC Single Error Interrupt Clear + ECCSE: u1, + /// ECC Dual Error Interrupt Clear + ECCDE: u1, + /// NVM Error Interrupt Clear + NVME: u1, + /// Suspended Write Or Erase Interrupt Clear + SUSP: u1, + /// Active SEES Full Interrupt Clear + SEESFULL: u1, + /// Active SEES Overflow Interrupt Clear + SEESOVF: u1, + /// SEE Write Completed Interrupt Clear + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0x4100400e + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done Interrupt Enable + DONE: u1, + /// Address Error Interrupt Enable + ADDRE: u1, + /// Programming Error Interrupt Enable + PROGE: u1, + /// Lock Error Interrupt Enable + LOCKE: u1, + /// ECC Single Error Interrupt Enable + ECCSE: u1, + /// ECC Dual Error Interrupt Enable + ECCDE: u1, + /// NVM Error Interrupt Enable + NVME: u1, + /// Suspended Write Or Erase Interrupt Enable + SUSP: u1, + /// Active SEES Full Interrupt Enable + SEESFULL: u1, + /// Active SEES Overflow Interrupt Enable + SEESOVF: u1, + /// SEE Write Completed Interrupt Enable + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xe); + + /// address: 0x41004010 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Done + DONE: u1, + /// Address Error + ADDRE: u1, + /// Programming Error + PROGE: u1, + /// Lock Error + LOCKE: u1, + /// ECC Single Error + ECCSE: u1, + /// ECC Dual Error + ECCDE: u1, + /// NVM Error + NVME: u1, + /// Suspended Write Or Erase Operation + SUSP: u1, + /// Active SEES Full + SEESFULL: u1, + /// Active SEES Overflow + SEESOVF: u1, + /// SEE Write Completed + SEEWRC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10); + + /// address: 0x41004012 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Ready to accept a command + READY: u1, + /// Power Reduction Mode + PRM: u1, + /// NVM Page Buffer Active Loading + LOAD: u1, + /// NVM Write Or Erase Operation Is Suspended + SUSP: u1, + /// BANKA First + AFIRST: u1, + /// Boot Loader Protection Disable + BPDIS: u1, + reserved0: u1, + reserved1: u1, + /// Boot Loader Protection Size + BOOTPROT: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x12); + + /// address: 0x41004014 + /// Address + pub const ADDR = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x14); + + /// address: 0x41004018 + /// Lock Section + pub const RUNLOCK = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4100401c + /// Page Buffer Load Data x + pub const PBLDATA = @intToPtr(*volatile [2]Mmio(32, packed struct { + /// Page Buffer Data + DATA: u32, + }), base_address + 0x1c); + + /// address: 0x41004024 + /// ECC Error Status Register + pub const ECCERR = @intToPtr(*volatile Mmio(32, packed struct { + /// Error Address + ADDR: u24, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Low Double-Word Error Type + TYPEL: u2, + /// High Double-Word Error Type + TYPEH: u2, + }), base_address + 0x24); + + /// address: 0x41004028 + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debugger ECC Read Disable + ECCDIS: u1, + /// Debugger ECC Error Tracking Mode + ECCELOG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x28); + + /// address: 0x4100402a + /// SmartEEPROM Configuration Register + pub const SEECFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Write Mode + WMODE: u1, + /// Automatic Page Reallocation Disable + APRDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2a); + + /// address: 0x4100402c + /// SmartEEPROM Status Register + pub const SEESTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Active SmartEEPROM Sector + ASEES: u1, + /// Page Buffer Loaded + LOAD: u1, + /// Busy + BUSY: u1, + /// SmartEEPROM Write Access Is Locked + LOCK: u1, + /// SmartEEPROM Write Access To Register Address Space Is Locked + RLOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Blocks Number In a Sector + SBLK: u4, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// SmartEEPROM Page Size + PSZ: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x2c); + }; + + /// Oscillators Control + pub const OSCCTRL = struct { + pub const base_address = 0x40001000; + pub const version = "U24011.0.0"; + + /// address: 0x40001000 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock 0 Failure Detector Event Output Enable + CFDEO0: u1, + /// Clock 1 Failure Detector Event Output Enable + CFDEO1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x40001004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready Interrupt Enable + XOSCRDY0: u1, + /// XOSC 1 Ready Interrupt Enable + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector Interrupt Enable + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector Interrupt Enable + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready Interrupt Enable + DFLLRDY: u1, + /// DFLL Out Of Bounds Interrupt Enable + DFLLOOB: u1, + /// DFLL Lock Fine Interrupt Enable + DFLLLCKF: u1, + /// DFLL Lock Coarse Interrupt Enable + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped Interrupt Enable + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise Interrupt Enable + DPLL0LCKR: u1, + /// DPLL0 Lock Fall Interrupt Enable + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout Interrupt Enable + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise Interrupt Enable + DPLL1LCKR: u1, + /// DPLL1 Lock Fall Interrupt Enable + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout Interrupt Enable + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x4); + + /// address: 0x40001008 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready Interrupt Enable + XOSCRDY0: u1, + /// XOSC 1 Ready Interrupt Enable + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector Interrupt Enable + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector Interrupt Enable + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready Interrupt Enable + DFLLRDY: u1, + /// DFLL Out Of Bounds Interrupt Enable + DFLLOOB: u1, + /// DFLL Lock Fine Interrupt Enable + DFLLLCKF: u1, + /// DFLL Lock Coarse Interrupt Enable + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped Interrupt Enable + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise Interrupt Enable + DPLL0LCKR: u1, + /// DPLL0 Lock Fall Interrupt Enable + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout Interrupt Enable + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise Interrupt Enable + DPLL1LCKR: u1, + /// DPLL1 Lock Fall Interrupt Enable + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout Interrupt Enable + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4000100c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready + XOSCRDY0: u1, + /// XOSC 1 Ready + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector + XOSCFAIL1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// DFLL Ready + DFLLRDY: u1, + /// DFLL Out Of Bounds + DFLLOOB: u1, + /// DFLL Lock Fine + DFLLLCKF: u1, + /// DFLL Lock Coarse + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped + DFLLRCS: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// DPLL0 Lock Rise + DPLL0LCKR: u1, + /// DPLL0 Lock Fall + DPLL0LCKF: u1, + /// DPLL0 Lock Timeout + DPLL0LTO: u1, + /// DPLL0 Loop Divider Ratio Update Complete + DPLL0LDRTO: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DPLL1 Lock Rise + DPLL1LCKR: u1, + /// DPLL1 Lock Fall + DPLL1LCKF: u1, + /// DPLL1 Lock Timeout + DPLL1LTO: u1, + /// DPLL1 Loop Divider Ratio Update Complete + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x40001010 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC 0 Ready + XOSCRDY0: u1, + /// XOSC 1 Ready + XOSCRDY1: u1, + /// XOSC 0 Clock Failure Detector + XOSCFAIL0: u1, + /// XOSC 1 Clock Failure Detector + XOSCFAIL1: u1, + /// XOSC 0 Clock Switch + XOSCCKSW0: u1, + /// XOSC 1 Clock Switch + XOSCCKSW1: u1, + reserved0: u1, + reserved1: u1, + /// DFLL Ready + DFLLRDY: u1, + /// DFLL Out Of Bounds + DFLLOOB: u1, + /// DFLL Lock Fine + DFLLLCKF: u1, + /// DFLL Lock Coarse + DFLLLCKC: u1, + /// DFLL Reference Clock Stopped + DFLLRCS: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// DPLL0 Lock Rise + DPLL0LCKR: u1, + /// DPLL0 Lock Fall + DPLL0LCKF: u1, + /// DPLL0 Timeout + DPLL0TO: u1, + /// DPLL0 Loop Divider Ratio Update Complete + DPLL0LDRTO: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// DPLL1 Lock Rise + DPLL1LCKR: u1, + /// DPLL1 Lock Fall + DPLL1LCKF: u1, + /// DPLL1 Timeout + DPLL1TO: u1, + /// DPLL1 Loop Divider Ratio Update Complete + DPLL1LDRTO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x40001014 + /// External Multipurpose Crystal Oscillator Control + pub const XOSCCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { + reserved0: u1, + /// Oscillator Enable + ENABLE: u1, + /// Crystal Oscillator Enable + XTALEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Low Buffer Gain Enable + LOWBUFGAIN: u1, + /// Oscillator Current Reference + IPTAT: u2, + /// Oscillator Current Multiplier + IMULT: u4, + /// Automatic Loop Control Enable + ENALC: u1, + /// Clock Failure Detector Enable + CFDEN: u1, + /// Xosc Clock Switch Enable + SWBEN: u1, + reserved4: u1, + reserved5: u1, + /// Start-Up Time + STARTUP: u4, + /// Clock Failure Detector Prescaler + CFDPRESC: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x14); + + /// address: 0x4000101c + /// DFLL48M Control A + pub const DFLLCTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// DFLL Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + }), base_address + 0x1c); + + /// address: 0x40001020 + /// DFLL48M Control B + pub const DFLLCTRLB = @intToPtr(*volatile Mmio(8, packed struct { + /// Operating Mode Selection + MODE: u1, + /// Stable DFLL Frequency + STABLE: u1, + /// Lose Lock After Wake + LLAW: u1, + /// USB Clock Recovery Mode + USBCRM: u1, + /// Chill Cycle Disable + CCDIS: u1, + /// Quick Lock Disable + QLDIS: u1, + /// Bypass Coarse Lock + BPLCKC: u1, + /// Wait Lock + WAITLOCK: u1, + }), base_address + 0x20); + + /// address: 0x40001024 + /// DFLL48M Value + pub const DFLLVAL = @intToPtr(*volatile Mmio(32, packed struct { + /// Fine Value + FINE: u8, + reserved0: u1, + reserved1: u1, + /// Coarse Value + COARSE: u6, + /// Multiplication Ratio Difference + DIFF: u16, + }), base_address + 0x24); + + /// address: 0x40001028 + /// DFLL48M Multiplier + pub const DFLLMUL = @intToPtr(*volatile Mmio(32, packed struct { + /// DFLL Multiply Factor + MUL: u16, + /// Fine Maximum Step + FSTEP: u8, + reserved0: u1, + reserved1: u1, + /// Coarse Maximum Step + CSTEP: u6, + }), base_address + 0x28); + + /// address: 0x4000102c + /// DFLL48M Synchronization + pub const DFLLSYNC = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// ENABLE Synchronization Busy + ENABLE: u1, + /// DFLLCTRLB Synchronization Busy + DFLLCTRLB: u1, + /// DFLLVAL Synchronization Busy + DFLLVAL: u1, + /// DFLLMUL Synchronization Busy + DFLLMUL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x2c); + + pub const DPLL = @ptrCast(*volatile [2]packed struct { + /// DPLL Control A + DPLLCTRLA: Mmio(8, packed struct { + reserved0: u1, + /// DPLL Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + }), + + /// DPLL Ratio Control + DPLLRATIO: Mmio(32, packed struct { + /// Loop Divider Ratio + LDR: u13, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Loop Divider Ratio Fractional Part + LDRFRAC: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), + + /// DPLL Control B + DPLLCTRLB: Mmio(32, packed struct { + /// Proportional Integral Filter Selection + FILTER: u4, + /// Wake Up Fast + WUF: u1, + /// Reference Clock Selection + REFCLK: u3, + /// Lock Time + LTIME: u3, + /// Lock Bypass + LBYPASS: u1, + /// Sigma-Delta DCO Filter Selection + DCOFILTER: u3, + /// DCO Filter Enable + DCOEN: u1, + /// Clock Divider + DIV: u11, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), + + /// DPLL Synchronization Busy + DPLLSYNCBUSY: Mmio(32, packed struct { + reserved0: u1, + /// DPLL Enable Synchronization Status + ENABLE: u1, + /// DPLL Loop Divider Ratio Synchronization Status + DPLLRATIO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), + + /// DPLL Status + DPLLSTATUS: Mmio(32, packed struct { + /// DPLL Lock Status + LOCK: u1, + /// DPLL Clock Ready + CLKRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), + }, base_address + 0x30); + }; + + /// 32kHz Oscillators Control + pub const OSC32KCTRL = struct { + pub const base_address = 0x40001400; + pub const version = "U24001.0.0"; + + /// address: 0x40001400 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready Interrupt Enable + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector Interrupt Enable + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x0); + + /// address: 0x40001404 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready Interrupt Enable + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector Interrupt Enable + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0x40001408 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector + XOSC32KFAIL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x8); + + /// address: 0x4000140c + /// Power and Clocks Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// XOSC32K Ready + XOSC32KRDY: u1, + reserved0: u1, + /// XOSC32K Clock Failure Detector + XOSC32KFAIL: u1, + /// XOSC32K Clock switch + XOSC32KSW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0xc); + + /// address: 0x40001410 + /// RTC Clock Selection + pub const RTCCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// RTC Clock Selection + RTCSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x10); + + /// address: 0x40001414 + /// 32kHz External Crystal Oscillator (XOSC32K) Control + pub const XOSC32K = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + /// Oscillator Enable + ENABLE: u1, + /// Crystal Oscillator Enable + XTALEN: u1, + /// 32kHz Output Enable + EN32K: u1, + /// 1kHz Output Enable + EN1K: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + /// On Demand Control + ONDEMAND: u1, + /// Oscillator Start-Up Time + STARTUP: u3, + reserved2: u1, + /// Write Lock + WRTLOCK: u1, + /// Control Gain Mode + CGM: u2, + padding0: u1, + }), base_address + 0x14); + + /// address: 0x40001416 + /// Clock Failure Detector Control + pub const CFDCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Failure Detector Enable + CFDEN: u1, + /// Clock Switch Back + SWBACK: u1, + /// Clock Failure Detector Prescaler + CFDPRESC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x16); + + /// address: 0x40001417 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Clock Failure Detector Event Output Enable + CFDEO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x17); + + /// address: 0x4000141c + /// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + pub const OSCULP32K = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable Out 32k + EN32K: u1, + /// Enable Out 1k + EN1K: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Oscillator Calibration + CALIB: u6, + reserved6: u1, + /// Write Lock + WRTLOCK: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x1c); + }; + + /// Peripheral Access Controller + pub const PAC = struct { + pub const base_address = 0x40000000; + pub const version = "U21201.2.0"; + + /// address: 0x40000000 + /// Write control + pub const WRCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral identifier + PERID: u16, + /// Peripheral access control key + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0x40000004 + /// Event control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral acess error event output + ERREO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40000008 + /// Interrupt enable clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral access error interrupt disable + ERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40000009 + /// Interrupt enable set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Peripheral access error interrupt enable + ERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x40000010 + /// Bridge interrupt flag status + pub const INTFLAGAHB = @intToPtr(*volatile Mmio(32, packed struct { + /// FLASH + FLASH_: u1, + /// FLASH_ALT + FLASH_ALT_: u1, + /// SEEPROM + SEEPROM_: u1, + /// RAMCM4S + RAMCM4S_: u1, + /// RAMPPPDSU + RAMPPPDSU_: u1, + /// RAMDMAWR + RAMDMAWR_: u1, + /// RAMDMACICM + RAMDMACICM_: u1, + /// HPB0 + HPB0_: u1, + /// HPB1 + HPB1_: u1, + /// HPB2 + HPB2_: u1, + /// HPB3 + HPB3_: u1, + /// PUKCC + PUKCC_: u1, + /// SDHC0 + SDHC0_: u1, + reserved0: u1, + /// QSPI + QSPI_: u1, + /// BKUPRAM + BKUPRAM_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x40000014 + /// Peripheral interrupt flag status - Bridge A + pub const INTFLAGA = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC + PAC_: u1, + /// PM + PM_: u1, + /// MCLK + MCLK_: u1, + /// RSTC + RSTC_: u1, + /// OSCCTRL + OSCCTRL_: u1, + /// OSC32KCTRL + OSC32KCTRL_: u1, + /// SUPC + SUPC_: u1, + /// GCLK + GCLK_: u1, + /// WDT + WDT_: u1, + /// RTC + RTC_: u1, + /// EIC + EIC_: u1, + /// FREQM + FREQM_: u1, + /// SERCOM0 + SERCOM0_: u1, + /// SERCOM1 + SERCOM1_: u1, + /// TC0 + TC0_: u1, + /// TC1 + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x14); + + /// address: 0x40000018 + /// Peripheral interrupt flag status - Bridge B + pub const INTFLAGB = @intToPtr(*volatile Mmio(32, packed struct { + /// USB + USB_: u1, + /// DSU + DSU_: u1, + /// NVMCTRL + NVMCTRL_: u1, + /// CMCC + CMCC_: u1, + /// PORT + PORT_: u1, + /// DMAC + DMAC_: u1, + /// HMATRIX + HMATRIX_: u1, + /// EVSYS + EVSYS_: u1, + reserved0: u1, + /// SERCOM2 + SERCOM2_: u1, + /// SERCOM3 + SERCOM3_: u1, + /// TCC0 + TCC0_: u1, + /// TCC1 + TCC1_: u1, + /// TC2 + TC2_: u1, + /// TC3 + TC3_: u1, + reserved1: u1, + /// RAMECC + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x18); + + /// address: 0x4000001c + /// Peripheral interrupt flag status - Bridge C + pub const INTFLAGC = @intToPtr(*volatile Mmio(32, packed struct { + /// CAN0 + CAN0_: u1, + /// CAN1 + CAN1_: u1, + reserved0: u1, + /// TCC2 + TCC2_: u1, + /// TCC3 + TCC3_: u1, + /// TC4 + TC4_: u1, + /// TC5 + TC5_: u1, + /// PDEC + PDEC_: u1, + /// AC + AC_: u1, + /// AES + AES_: u1, + /// TRNG + TRNG_: u1, + /// ICM + ICM_: u1, + /// PUKCC + PUKCC_: u1, + /// QSPI + QSPI_: u1, + /// CCL + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x1c); + + /// address: 0x40000020 + /// Peripheral interrupt flag status - Bridge D + pub const INTFLAGD = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 + SERCOM4_: u1, + /// SERCOM5 + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 + ADC0_: u1, + /// ADC1 + ADC1_: u1, + /// DAC + DAC_: u1, + /// I2S + I2S_: u1, + /// PCC + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x20); + + /// address: 0x40000034 + /// Peripheral write protection status - Bridge A + pub const STATUSA = @intToPtr(*volatile Mmio(32, packed struct { + /// PAC APB Protect Enable + PAC_: u1, + /// PM APB Protect Enable + PM_: u1, + /// MCLK APB Protect Enable + MCLK_: u1, + /// RSTC APB Protect Enable + RSTC_: u1, + /// OSCCTRL APB Protect Enable + OSCCTRL_: u1, + /// OSC32KCTRL APB Protect Enable + OSC32KCTRL_: u1, + /// SUPC APB Protect Enable + SUPC_: u1, + /// GCLK APB Protect Enable + GCLK_: u1, + /// WDT APB Protect Enable + WDT_: u1, + /// RTC APB Protect Enable + RTC_: u1, + /// EIC APB Protect Enable + EIC_: u1, + /// FREQM APB Protect Enable + FREQM_: u1, + /// SERCOM0 APB Protect Enable + SERCOM0_: u1, + /// SERCOM1 APB Protect Enable + SERCOM1_: u1, + /// TC0 APB Protect Enable + TC0_: u1, + /// TC1 APB Protect Enable + TC1_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x34); + + /// address: 0x40000038 + /// Peripheral write protection status - Bridge B + pub const STATUSB = @intToPtr(*volatile Mmio(32, packed struct { + /// USB APB Protect Enable + USB_: u1, + /// DSU APB Protect Enable + DSU_: u1, + /// NVMCTRL APB Protect Enable + NVMCTRL_: u1, + /// CMCC APB Protect Enable + CMCC_: u1, + /// PORT APB Protect Enable + PORT_: u1, + /// DMAC APB Protect Enable + DMAC_: u1, + /// HMATRIX APB Protect Enable + HMATRIX_: u1, + /// EVSYS APB Protect Enable + EVSYS_: u1, + reserved0: u1, + /// SERCOM2 APB Protect Enable + SERCOM2_: u1, + /// SERCOM3 APB Protect Enable + SERCOM3_: u1, + /// TCC0 APB Protect Enable + TCC0_: u1, + /// TCC1 APB Protect Enable + TCC1_: u1, + /// TC2 APB Protect Enable + TC2_: u1, + /// TC3 APB Protect Enable + TC3_: u1, + reserved1: u1, + /// RAMECC APB Protect Enable + RAMECC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x38); + + /// address: 0x4000003c + /// Peripheral write protection status - Bridge C + pub const STATUSC = @intToPtr(*volatile Mmio(32, packed struct { + /// CAN0 APB Protect Enable + CAN0_: u1, + /// CAN1 APB Protect Enable + CAN1_: u1, + reserved0: u1, + /// TCC2 APB Protect Enable + TCC2_: u1, + /// TCC3 APB Protect Enable + TCC3_: u1, + /// TC4 APB Protect Enable + TC4_: u1, + /// TC5 APB Protect Enable + TC5_: u1, + /// PDEC APB Protect Enable + PDEC_: u1, + /// AC APB Protect Enable + AC_: u1, + /// AES APB Protect Enable + AES_: u1, + /// TRNG APB Protect Enable + TRNG_: u1, + /// ICM APB Protect Enable + ICM_: u1, + /// PUKCC APB Protect Enable + PUKCC_: u1, + /// QSPI APB Protect Enable + QSPI_: u1, + /// CCL APB Protect Enable + CCL_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + }), base_address + 0x3c); + + /// address: 0x40000040 + /// Peripheral write protection status - Bridge D + pub const STATUSD = @intToPtr(*volatile Mmio(32, packed struct { + /// SERCOM4 APB Protect Enable + SERCOM4_: u1, + /// SERCOM5 APB Protect Enable + SERCOM5_: u1, + reserved0: u1, + reserved1: u1, + /// TCC4 APB Protect Enable + TCC4_: u1, + reserved2: u1, + reserved3: u1, + /// ADC0 APB Protect Enable + ADC0_: u1, + /// ADC1 APB Protect Enable + ADC1_: u1, + /// DAC APB Protect Enable + DAC_: u1, + /// I2S APB Protect Enable + I2S_: u1, + /// PCC APB Protect Enable + PCC_: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0x40); + }; + + /// Parallel Capture Controller + pub const PCC = struct { + pub const base_address = 0x43002c00; + pub const version = "U20171.1.0"; + + /// address: 0x43002c00 + /// Mode Register + pub const MR = @intToPtr(*volatile Mmio(32, packed struct { + /// Parallel Capture Enable + PCEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data size + DSIZE: u2, + reserved3: u1, + reserved4: u1, + /// Scale data + SCALE: u1, + /// Always Sampling + ALWYS: u1, + /// Half Sampling + HALFS: u1, + /// First sample + FRSTS: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Input Data Size + ISIZE: u3, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Clear If Disabled + CID: u2, + }), base_address + 0x0); + + /// address: 0x43002c04 + /// Interrupt Enable Register + pub const IER = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Enable + DRDY: u1, + /// Overrun Error Interrupt Enable + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x4); + + /// address: 0x43002c08 + /// Interrupt Disable Register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Disable + DRDY: u1, + /// Overrun Error Interrupt Disable + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x8); + + /// address: 0x43002c0c + /// Interrupt Mask Register + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Mask + DRDY: u1, + /// Overrun Error Interrupt Mask + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xc); + + /// address: 0x43002c10 + /// Interrupt Status Register + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Ready Interrupt Status + DRDY: u1, + /// Overrun Error Interrupt Status + OVRE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x10); + + /// address: 0x43002c14 + /// Reception Holding Register + pub const RHR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reception Data + RDATA: u32, + }), base_address + 0x14); + + /// address: 0x43002ce0 + /// Write Protection Mode Register + pub const WPMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Protection Enable + WPEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Write Protection Key + WPKEY: u24, + }), base_address + 0xe0); + + /// address: 0x43002ce4 + /// Write Protection Status Register + pub const WPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Write Protection Violation Source + WPVS: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Write Protection Violation Status + WPVSRC: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xe4); + }; + + /// Quadrature Decodeur + pub const PDEC = struct { + pub const base_address = 0x42001c00; + pub const version = "U22631.0.0"; + + /// address: 0x42001c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operation Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + /// PDEC Configuration + CONF: u3, + /// Auto Lock + ALOCK: u1, + reserved3: u1, + reserved4: u1, + /// PDEC Phase A and B Swap + SWAP: u1, + /// Period Enable + PEREN: u1, + /// PDEC Input From Pin 0 Enable + PINEN0: u1, + /// PDEC Input From Pin 1 Enable + PINEN1: u1, + /// PDEC Input From Pin 2 Enable + PINEN2: u1, + reserved5: u1, + /// IO Pin 0 Invert Enable + PINVEN0: u1, + /// IO Pin 1 Invert Enable + PINVEN1: u1, + /// IO Pin 2 Invert Enable + PINVEN2: u1, + reserved6: u1, + /// Angular Counter Length + ANGULAR: u3, + reserved7: u1, + /// Maximum Consecutive Missing Pulses + MAXCMP: u4, + }), base_address + 0x0); + + /// address: 0x42001c04 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Lock Update + LUPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42001c05 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Lock Update + LUPD: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42001c06 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u2, + /// Inverted Event Input Enable + EVINV: u3, + /// Event Input Enable + EVEI: u3, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Error Output Event Enable + ERREO: u1, + /// Direction Output Event Enable + DIREO: u1, + /// Velocity Output Event Enable + VLCEO: u1, + /// Match Channel 0 Event Output Enable + MCEO0: u1, + /// Match Channel 1 Event Output Enable + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x42001c08 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow Interrupt Disable + OVF: u1, + /// Error Interrupt Disable + ERR: u1, + /// Direction Interrupt Disable + DIR: u1, + /// Velocity Interrupt Disable + VLC: u1, + /// Channel 0 Compare Match Disable + MC0: u1, + /// Channel 1 Compare Match Disable + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x42001c09 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow Interrupt Enable + OVF: u1, + /// Error Interrupt Enable + ERR: u1, + /// Direction Interrupt Enable + DIR: u1, + /// Velocity Interrupt Enable + VLC: u1, + /// Channel 0 Compare Match Enable + MC0: u1, + /// Channel 1 Compare Match Enable + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x42001c0a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Overflow/Underflow + OVF: u1, + /// Error + ERR: u1, + /// Direction Change + DIR: u1, + /// Velocity + VLC: u1, + /// Channel 0 Compare Match + MC0: u1, + /// Channel 1 Compare Match + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x42001c0c + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Quadrature Error Flag + QERR: u1, + /// Index Error Flag + IDXERR: u1, + /// Missing Pulse Error flag + MPERR: u1, + reserved0: u1, + /// Window Error Flag + WINERR: u1, + /// Hall Error Flag + HERR: u1, + /// Stop + STOP: u1, + /// Direction Status Flag + DIR: u1, + /// Prescaler Buffer Valid + PRESCBUFV: u1, + /// Filter Buffer Valid + FILTERBUFV: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xc); + + /// address: 0x42001c0f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Run Mode + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x42001c10 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// Control B Synchronization Busy + CTRLB: u1, + /// Status Synchronization Busy + STATUS: u1, + /// Prescaler Synchronization Busy + PRESC: u1, + /// Filter Synchronization Busy + FILTER: u1, + /// Count Synchronization Busy + COUNT: u1, + /// Compare Channel 0 Synchronization Busy + CC0: u1, + /// Compare Channel 1 Synchronization Busy + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x10); + + /// address: 0x42001c14 + /// Prescaler Value + pub const PRESC = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x14); + + /// address: 0x42001c15 + /// Filter Value + pub const FILTER = @intToPtr(*volatile u8, base_address + 0x15); + + /// address: 0x42001c18 + /// Prescaler Buffer Value + pub const PRESCBUF = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x18); + + /// address: 0x42001c19 + /// Filter Buffer Value + pub const FILTERBUF = @intToPtr(*volatile u8, base_address + 0x19); + + /// address: 0x42001c1c + /// Counter Value + pub const COUNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x42001c20 + /// Channel n Compare Value + pub const CC = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x20); + + /// address: 0x42001c30 + /// Channel Compare Buffer Value + pub const CCBUF = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x30); + }; + + /// Power Manager + pub const PM = struct { + pub const base_address = 0x40000400; + pub const version = "U24061.0.0"; + + /// address: 0x40000400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// I/O Retention + IORET: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x0); + + /// address: 0x40000401 + /// Sleep Configuration + pub const SLEEPCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode + SLEEPMODE: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1); + + /// address: 0x40000404 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready Enable + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40000405 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready Enable + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x5); + + /// address: 0x40000406 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Sleep Mode Entry Ready + SLEEPRDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x6); + + /// address: 0x40000408 + /// Standby Configuration + pub const STDBYCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + RAMCFG: u2, + reserved0: u1, + reserved1: u1, + /// Fast Wakeup + FASTWKUP: u2, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40000409 + /// Hibernate Configuration + pub const HIBCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + RAMCFG: u2, + /// Backup Ram Configuration + BRAMCFG: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x9); + + /// address: 0x4000040a + /// Backup Configuration + pub const BKUPCFG = @intToPtr(*volatile Mmio(8, packed struct { + /// Ram Configuration + BRAMCFG: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xa); + + /// address: 0x40000412 + /// Power Switch Acknowledge Delay + pub const PWSAKDLY = @intToPtr(*volatile Mmio(8, packed struct { + /// Delay Value + DLYVAL: u7, + /// Ignore Acknowledge + IGNACK: u1, + }), base_address + 0x12); + }; + + /// Port Module + pub const PORT = struct { + pub const base_address = @intToPtr([*]u8, 0x41008000); + pub const version = "U22102.2.0"; + + pub const GROUP = @ptrCast(*volatile [2]packed struct { + /// Data Direction + DIR: u32, + + /// Data Direction Clear + DIRCLR: u32, + + /// Data Direction Set + DIRSET: u32, + + /// Data Direction Toggle + DIRTGL: u32, + + /// Data Output Value + OUT: u32, + + /// Data Output Value Clear + OUTCLR: u32, + + /// Data Output Value Set + OUTSET: u32, + + /// Data Output Value Toggle + OUTTGL: u32, + + /// Data Input Value + IN: u32, + + /// Control + CTRL: Mmio(32, packed struct { + /// Input Sampling Mode + SAMPLING: u32, + }), + + /// Write Configuration + WRCONFIG: Mmio(32, packed struct { + /// Pin Mask for Multiple Pin Configuration + PINMASK: u16, + /// Peripheral Multiplexer Enable + PMUXEN: u1, + /// Input Enable + INEN: u1, + /// Pull Enable + PULLEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Output Driver Strength Selection + DRVSTR: u1, + reserved3: u1, + /// Peripheral Multiplexing + PMUX: u4, + /// Write PMUX + WRPMUX: u1, + reserved4: u1, + /// Write PINCFG + WRPINCFG: u1, + /// Half-Word Select + HWSEL: u1, + }), + + /// Event Input Control + EVCTRL: Mmio(32, packed struct { + /// PORT Event Pin Identifier 0 + PID0: u5, + /// PORT Event Action 0 + EVACT0: u2, + /// PORT Event Input Enable 0 + PORTEI0: u1, + /// PORT Event Pin Identifier 1 + PID1: u5, + /// PORT Event Action 1 + EVACT1: u2, + /// PORT Event Input Enable 1 + PORTEI1: u1, + /// PORT Event Pin Identifier 2 + PID2: u5, + /// PORT Event Action 2 + EVACT2: u2, + /// PORT Event Input Enable 2 + PORTEI2: u1, + /// PORT Event Pin Identifier 3 + PID3: u5, + /// PORT Event Action 3 + EVACT3: u2, + /// PORT Event Input Enable 3 + PORTEI3: u1, + }), + + /// Peripheral Multiplexing + PMUX: [16]Mmio(8, packed struct { + /// Peripheral Multiplexing for Even-Numbered Pin + PMUXE: u4, + /// Peripheral Multiplexing for Odd-Numbered Pin + PMUXO: u4, + }), + + /// Pin Configuration + PINCFG: [32]Mmio(8, packed struct { + /// Peripheral Multiplexer Enable + PMUXEN: u1, + /// Input Enable + INEN: u1, + /// Pull Enable + PULLEN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Output Driver Strength Selection + DRVSTR: u1, + padding0: u1, + }), + padding0: u32, + padding1: u32, + padding2: u32, + padding3: u32, + padding4: u32, + padding5: u32, + padding6: u32, + padding7: u32, + //padding8: u32, + //padding9: u32, + //padding10: u32, + //padding11: u32, + //padding12: u32, + //padding13: u32, + //padding14: u32, + //padding15: u32, + //padding16: u32, + //padding17: u32, + //padding18: u32, + }, base_address); + }; + + /// Quad SPI interface + pub const QSPI = struct { + pub const base_address = 0x42003400; + pub const version = "U20081.6.3"; + + /// address: 0x42003400 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Last Transfer + LASTXFER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x0); + + /// address: 0x42003404 + /// Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Serial Memory Mode + MODE: u1, + /// Local Loopback Enable + LOOPEN: u1, + /// Wait Data Read Before Transfer + WDRBT: u1, + /// Serial Memory reg + SMEMREG: u1, + /// Chip Select Mode + CSMODE: u2, + reserved0: u1, + reserved1: u1, + /// Data Length + DATALEN: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Delay Between Consecutive Transfers + DLYBCT: u8, + /// Minimum Inactive CS Delay + DLYCS: u8, + }), base_address + 0x4); + + /// address: 0x42003408 + /// Baud Rate + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock Polarity + CPOL: u1, + /// Clock Phase + CPHA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Serial Clock Baud Rate + BAUD: u8, + /// Delay Before SCK + DLYBS: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x8); + + /// address: 0x4200340c + /// Receive Data + pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0xc); + + /// address: 0x42003410 + /// Transmit Data + pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data + DATA: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x10); + + /// address: 0x42003414 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full Interrupt Disable + RXC: u1, + /// Transmit Data Register Empty Interrupt Disable + DRE: u1, + /// Transmission Complete Interrupt Disable + TXC: u1, + /// Overrun Error Interrupt Disable + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise Interrupt Disable + CSRISE: u1, + reserved4: u1, + /// Instruction End Interrupt Disable + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x14); + + /// address: 0x42003418 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full Interrupt Enable + RXC: u1, + /// Transmit Data Register Empty Interrupt Enable + DRE: u1, + /// Transmission Complete Interrupt Enable + TXC: u1, + /// Overrun Error Interrupt Enable + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise Interrupt Enable + CSRISE: u1, + reserved4: u1, + /// Instruction End Interrupt Enable + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x18); + + /// address: 0x4200341c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Register Full + RXC: u1, + /// Transmit Data Register Empty + DRE: u1, + /// Transmission Complete + TXC: u1, + /// Overrun Error + ERROR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Chip Select Rise + CSRISE: u1, + reserved4: u1, + /// Instruction End + INSTREND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x1c); + + /// address: 0x42003420 + /// Status Register + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Chip Select + CSSTATUS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x20); + + /// address: 0x42003430 + /// Instruction Address + pub const INSTRADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Address + ADDR: u32, + }), base_address + 0x30); + + /// address: 0x42003434 + /// Instruction Code + pub const INSTRCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Code + INSTR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Option Code + OPTCODE: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42003438 + /// Instruction Frame + pub const INSTRFRAME = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction Code, Address, Option Code and Data Width + WIDTH: u3, + reserved0: u1, + /// Instruction Enable + INSTREN: u1, + /// Address Enable + ADDREN: u1, + /// Option Enable + OPTCODEEN: u1, + /// Data Enable + DATAEN: u1, + /// Option Code Length + OPTCODELEN: u2, + /// Address Length + ADDRLEN: u1, + reserved1: u1, + /// Data Transfer Type + TFRTYPE: u2, + /// Continuous Read Mode + CRMODE: u1, + /// Double Data Rate Enable + DDREN: u1, + /// Dummy Cycles Length + DUMMYLEN: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + }), base_address + 0x38); + + /// address: 0x42003440 + /// Scrambling Mode + pub const SCRAMBCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Scrambling/Unscrambling Enable + ENABLE: u1, + /// Scrambling/Unscrambling Random Value Disable + RANDOMDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x40); + + /// address: 0x42003444 + /// Scrambling Key + pub const SCRAMBKEY = @intToPtr(*volatile Mmio(32, packed struct { + /// Scrambling User Key + KEY: u32, + }), base_address + 0x44); + }; + + /// RAM ECC + pub const RAMECC = struct { + pub const base_address = 0x41020000; + pub const version = "U22681.0.0"; + + /// address: 0x41020000 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt Enable Clear + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt Enable Clear + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0x41020001 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt Enable Set + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt Enable Set + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1); + + /// address: 0x41020002 + /// Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Single Bit ECC Error Interrupt + SINGLEE: u1, + /// Dual Bit ECC Error Interrupt + DUALE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41020003 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// ECC Disable + ECCDIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x3); + + /// address: 0x41020004 + /// Error Address + pub const ERRADDR = @intToPtr(*volatile MmioInt(32, u17), base_address + 0x4); + + /// address: 0x4102000f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// ECC Disable + ECCDIS: u1, + /// ECC Error Log + ECCELOG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xf); + }; + + /// Reset Controller + pub const RSTC = struct { + pub const base_address = 0x40000c00; + pub const version = "U22394.0.0"; + + /// address: 0x40000c00 + /// Reset Cause + pub const RCAUSE = @intToPtr(*volatile Mmio(8, packed struct { + /// Power On Reset + POR: u1, + /// Brown Out CORE Detector Reset + BODCORE: u1, + /// Brown Out VDD Detector Reset + BODVDD: u1, + /// NVM Reset + NVM: u1, + /// External Reset + EXT: u1, + /// Watchdog Reset + WDT: u1, + /// System Reset Request + SYST: u1, + /// Backup Reset + BACKUP: u1, + }), base_address + 0x0); + + /// address: 0x40000c02 + /// Backup Exit Source + pub const BKUPEXIT = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Real Timer Counter Interrupt + RTC: u1, + /// Battery Backup Power Switch + BBPS: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Hibernate + HIB: u1, + }), base_address + 0x2); + }; + + /// Real-Time Counter + pub const RTC = struct { + pub const base_address = 0x40002400; + pub const version = "U22502.1.0"; + + /// 32-bit Counter with Single 32-bit Compare + pub const MODE0 = struct { + /// address: 0x40002400 + /// MODE0 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Clear on Match + MATCHCLR: u1, + /// Prescaler + PRESCALER: u4, + reserved3: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Count Read Synchronization Enable + COUNTSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE0 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE0 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Compare 0 Event Output Enable + CMPEO0: u1, + /// Compare 1 Event Output Enable + CMPEO1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE0 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE0 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE0 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Compare 0 + CMP0: u1, + /// Compare 1 + CMP1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE0 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// COUNT Register Busy + COUNT: u1, + reserved0: u1, + /// COMP 0 Register Busy + COMP0: u1, + /// COMP 1 Register Busy + COMP1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Count Synchronization Enable Bit Busy + COUNTSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE0 Counter Value + pub const COUNT = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x40002420 + /// MODE0 Compare n Value + pub const COMP = @intToPtr(*volatile [2]u32, base_address + 0x20); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE0 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Count Timestamp Value + COUNT: u32, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + + /// 16-bit Counter with Two 16-bit Compares + pub const MODE1 = struct { + /// address: 0x40002400 + /// MODE1 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Prescaler + PRESCALER: u4, + reserved4: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Count Read Synchronization Enable + COUNTSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE1 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE1 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Compare 0 Event Output Enable + CMPEO0: u1, + /// Compare 1 Event Output Enable + CMPEO1: u1, + /// Compare 2 Event Output Enable + CMPEO2: u1, + /// Compare 3 Event Output Enable + CMPEO3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE1 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + /// Compare 2 Interrupt Enable + CMP2: u1, + /// Compare 3 Interrupt Enable + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE1 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Compare 0 Interrupt Enable + CMP0: u1, + /// Compare 1 Interrupt Enable + CMP1: u1, + /// Compare 2 Interrupt Enable + CMP2: u1, + /// Compare 3 Interrupt Enable + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE1 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Compare 0 + CMP0: u1, + /// Compare 1 + CMP1: u1, + /// Compare 2 + CMP2: u1, + /// Compare 3 + CMP3: u1, + reserved0: u1, + reserved1: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE1 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Bit Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// COUNT Register Busy + COUNT: u1, + /// PER Register Busy + PER: u1, + /// COMP 0 Register Busy + COMP0: u1, + /// COMP 1 Register Busy + COMP1: u1, + /// COMP 2 Register Busy + COMP2: u1, + /// COMP 3 Register Busy + COMP3: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Count Synchronization Enable Bit Busy + COUNTSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE1 Counter Value + pub const COUNT = @intToPtr(*volatile u16, base_address + 0x18); + + /// address: 0x4000241c + /// MODE1 Counter Period + pub const PER = @intToPtr(*volatile u16, base_address + 0x1c); + + /// address: 0x40002420 + /// MODE1 Compare n Value + pub const COMP = @intToPtr(*volatile [4]u16, base_address + 0x20); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE1 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Count Timestamp Value + COUNT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + + /// Clock/Calendar with Alarm + pub const MODE2 = struct { + /// address: 0x40002400 + /// MODE2 Control A + pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u2, + reserved0: u1, + reserved1: u1, + /// Clock Representation + CLKREP: u1, + /// Clear on Match + MATCHCLR: u1, + /// Prescaler + PRESCALER: u4, + reserved2: u1, + /// BKUP Registers Reset On Tamper Enable + BKTRST: u1, + /// GP Registers Reset On Tamper Enable + GPTRST: u1, + /// Clock Read Synchronization Enable + CLOCKSYNC: u1, + }), base_address + 0x0); + + /// address: 0x40002402 + /// MODE2 Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// General Purpose 0 Enable + GP0EN: u1, + /// General Purpose 2 Enable + GP2EN: u1, + reserved0: u1, + reserved1: u1, + /// Debouncer Majority Enable + DEBMAJ: u1, + /// Debouncer Asynchronous Enable + DEBASYNC: u1, + /// RTC Output Enable + RTCOUT: u1, + /// DMA Enable + DMAEN: u1, + /// Debounce Freqnuency + DEBF: u3, + reserved2: u1, + /// Active Layer Freqnuency + ACTF: u3, + padding0: u1, + }), base_address + 0x2); + + /// address: 0x40002404 + /// MODE2 Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Periodic Interval 0 Event Output Enable + PEREO0: u1, + /// Periodic Interval 1 Event Output Enable + PEREO1: u1, + /// Periodic Interval 2 Event Output Enable + PEREO2: u1, + /// Periodic Interval 3 Event Output Enable + PEREO3: u1, + /// Periodic Interval 4 Event Output Enable + PEREO4: u1, + /// Periodic Interval 5 Event Output Enable + PEREO5: u1, + /// Periodic Interval 6 Event Output Enable + PEREO6: u1, + /// Periodic Interval 7 Event Output Enable + PEREO7: u1, + /// Alarm 0 Event Output Enable + ALARMEO0: u1, + /// Alarm 1 Event Output Enable + ALARMEO1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Event Output Enable + TAMPEREO: u1, + /// Overflow Event Output Enable + OVFEO: u1, + /// Tamper Event Input Enable + TAMPEVEI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0x40002408 + /// MODE2 Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Interrupt Enable + PER0: u1, + /// Periodic Interval 1 Interrupt Enable + PER1: u1, + /// Periodic Interval 2 Interrupt Enable + PER2: u1, + /// Periodic Interval 3 Interrupt Enable + PER3: u1, + /// Periodic Interval 4 Interrupt Enable + PER4: u1, + /// Periodic Interval 5 Interrupt Enable + PER5: u1, + /// Periodic Interval 6 Interrupt Enable + PER6: u1, + /// Periodic Interval 7 Interrupt Enable + PER7: u1, + /// Alarm 0 Interrupt Enable + ALARM0: u1, + /// Alarm 1 Interrupt Enable + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0x8); + + /// address: 0x4000240a + /// MODE2 Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 Enable + PER0: u1, + /// Periodic Interval 1 Enable + PER1: u1, + /// Periodic Interval 2 Enable + PER2: u1, + /// Periodic Interval 3 Enable + PER3: u1, + /// Periodic Interval 4 Enable + PER4: u1, + /// Periodic Interval 5 Enable + PER5: u1, + /// Periodic Interval 6 Enable + PER6: u1, + /// Periodic Interval 7 Enable + PER7: u1, + /// Alarm 0 Interrupt Enable + ALARM0: u1, + /// Alarm 1 Interrupt Enable + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper Enable + TAMPER: u1, + /// Overflow Interrupt Enable + OVF: u1, + }), base_address + 0xa); + + /// address: 0x4000240c + /// MODE2 Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Periodic Interval 0 + PER0: u1, + /// Periodic Interval 1 + PER1: u1, + /// Periodic Interval 2 + PER2: u1, + /// Periodic Interval 3 + PER3: u1, + /// Periodic Interval 4 + PER4: u1, + /// Periodic Interval 5 + PER5: u1, + /// Periodic Interval 6 + PER6: u1, + /// Periodic Interval 7 + PER7: u1, + /// Alarm 0 + ALARM0: u1, + /// Alarm 1 + ALARM1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Tamper + TAMPER: u1, + /// Overflow + OVF: u1, + }), base_address + 0xc); + + /// address: 0x4000240e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xe); + + /// address: 0x40002410 + /// MODE2 Synchronization Busy Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Bit Busy + SWRST: u1, + /// Enable Bit Busy + ENABLE: u1, + /// FREQCORR Register Busy + FREQCORR: u1, + /// CLOCK Register Busy + CLOCK: u1, + reserved0: u1, + /// ALARM 0 Register Busy + ALARM0: u1, + /// ALARM 1 Register Busy + ALARM1: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// MASK 0 Register Busy + MASK0: u1, + /// MASK 1 Register Busy + MASK1: u1, + reserved5: u1, + reserved6: u1, + /// Clock Synchronization Enable Bit Busy + CLOCKSYNC: u1, + /// General Purpose 0 Register Busy + GP0: u1, + /// General Purpose 1 Register Busy + GP1: u1, + /// General Purpose 2 Register Busy + GP2: u1, + /// General Purpose 3 Register Busy + GP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x10); + + /// address: 0x40002414 + /// Frequency Correction + pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { + /// Correction Value + VALUE: u7, + /// Correction Sign + SIGN: u1, + }), base_address + 0x14); + + /// address: 0x40002418 + /// MODE2 Clock Value + pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x18); + + /// address: 0x40002440 + /// General Purpose + pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); + + /// address: 0x40002420 + /// MODE2_ALARM Alarm n Value + pub const ALARM0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x20); + + /// address: 0x40002424 + /// MODE2_ALARM Alarm n Mask + pub const MASK0 = @intToPtr(*volatile Mmio(8, packed struct { + /// Alarm Mask Selection + SEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x40002428 + /// MODE2_ALARM Alarm n Value + pub const ALARM1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Second + SECOND: u6, + /// Minute + MINUTE: u6, + /// Hour + HOUR: u5, + /// Day + DAY: u5, + /// Month + MONTH: u4, + /// Year + YEAR: u6, + }), base_address + 0x28); + + /// address: 0x4000242c + /// MODE2_ALARM Alarm n Mask + pub const MASK1 = @intToPtr(*volatile Mmio(8, packed struct { + /// Alarm Mask Selection + SEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2c); + + /// address: 0x40002460 + /// Tamper Control + pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Action + IN0ACT: u2, + /// Tamper Input 1 Action + IN1ACT: u2, + /// Tamper Input 2 Action + IN2ACT: u2, + /// Tamper Input 3 Action + IN3ACT: u2, + /// Tamper Input 4 Action + IN4ACT: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Tamper Level Select 0 + TAMLVL0: u1, + /// Tamper Level Select 1 + TAMLVL1: u1, + /// Tamper Level Select 2 + TAMLVL2: u1, + /// Tamper Level Select 3 + TAMLVL3: u1, + /// Tamper Level Select 4 + TAMLVL4: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Debouncer Enable 0 + DEBNC0: u1, + /// Debouncer Enable 1 + DEBNC1: u1, + /// Debouncer Enable 2 + DEBNC2: u1, + /// Debouncer Enable 3 + DEBNC3: u1, + /// Debouncer Enable 4 + DEBNC4: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x60); + + /// address: 0x40002464 + /// MODE2 Timestamp + pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { + /// Second Timestamp Value + SECOND: u6, + /// Minute Timestamp Value + MINUTE: u6, + /// Hour Timestamp Value + HOUR: u5, + /// Day Timestamp Value + DAY: u5, + /// Month Timestamp Value + MONTH: u4, + /// Year Timestamp Value + YEAR: u6, + }), base_address + 0x64); + + /// address: 0x40002468 + /// Tamper ID + pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { + /// Tamper Input 0 Detected + TAMPID0: u1, + /// Tamper Input 1 Detected + TAMPID1: u1, + /// Tamper Input 2 Detected + TAMPID2: u1, + /// Tamper Input 3 Detected + TAMPID3: u1, + /// Tamper Input 4 Detected + TAMPID4: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + /// Tamper Event Detected + TAMPEVT: u1, + }), base_address + 0x68); + + /// address: 0x40002480 + /// Backup + pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); + }; + }; + + /// SD/MMC Host Controller + pub const SDHC0 = struct { + pub const base_address = 0x45000000; + pub const version = "U20111.8.3"; + + /// address: 0x45000000 + /// SDMA System Address / Argument 2 + pub const SSAR = @intToPtr(*volatile Mmio(32, packed struct { + /// SDMA System Address + ADDR: u32, + }), base_address + 0x0); + + /// address: 0x45000000 + /// SDMA System Address / Argument 2 + pub const SSAR_CMD23_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Argument 2 + ARG2: u32, + }), base_address + 0x0); + + /// address: 0x45000004 + /// Block Size + pub const BSR = @intToPtr(*volatile Mmio(16, packed struct { + /// Transfer Block Size + BLOCKSIZE: u10, + reserved0: u1, + reserved1: u1, + /// SDMA Buffer Boundary + BOUNDARY: u3, + padding0: u1, + }), base_address + 0x4); + + /// address: 0x45000006 + /// Block Count + pub const BCR = @intToPtr(*volatile Mmio(16, packed struct { + /// Blocks Count for Current Transfer + BCNT: u16, + }), base_address + 0x6); + + /// address: 0x45000008 + /// Argument 1 + pub const ARG1R = @intToPtr(*volatile Mmio(32, packed struct { + /// Argument 1 + ARG: u32, + }), base_address + 0x8); + + /// address: 0x4500000c + /// Transfer Mode + pub const TMR = @intToPtr(*volatile Mmio(16, packed struct { + /// DMA Enable + DMAEN: u1, + /// Block Count Enable + BCEN: u1, + /// Auto Command Enable + ACMDEN: u2, + /// Data Transfer Direction Selection + DTDSEL: u1, + /// Multi/Single Block Selection + MSBSEL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0xc); + + /// address: 0x4500000e + /// Command + pub const CR = @intToPtr(*volatile Mmio(16, packed struct { + /// Response Type + RESPTYP: u2, + reserved0: u1, + /// Command CRC Check Enable + CMDCCEN: u1, + /// Command Index Check Enable + CMDICEN: u1, + /// Data Present Select + DPSEL: u1, + /// Command Type + CMDTYP: u2, + /// Command Index + CMDIDX: u6, + padding0: u1, + padding1: u1, + }), base_address + 0xe); + + /// address: 0x45000010 + /// Response + pub const RR = @intToPtr(*volatile [4]Mmio(32, packed struct { + /// Command Response + CMDRESP: u32, + }), base_address + 0x10); + + /// address: 0x45000020 + /// Buffer Data Port + pub const BDPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Buffer Data + BUFDATA: u32, + }), base_address + 0x20); + + /// address: 0x45000024 + /// Present State + pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Command Inhibit (CMD) + CMDINHC: u1, + /// Command Inhibit (DAT) + CMDINHD: u1, + /// DAT Line Active + DLACT: u1, + /// Re-Tuning Request + RTREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Write Transfer Active + WTACT: u1, + /// Read Transfer Active + RTACT: u1, + /// Buffer Write Enable + BUFWREN: u1, + /// Buffer Read Enable + BUFRDEN: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Card Inserted + CARDINS: u1, + /// Card State Stable + CARDSS: u1, + /// Card Detect Pin Level + CARDDPL: u1, + /// Write Protect Pin Level + WRPPL: u1, + /// DAT[3:0] Line Level + DATLL: u4, + /// CMD Line Level + CMDLL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x24); + + /// address: 0x45000028 + /// Host Control 1 + pub const HC1R = @intToPtr(*volatile Mmio(8, packed struct { + /// LED Control + LEDCTRL: u1, + /// Data Width + DW: u1, + /// High Speed Enable + HSEN: u1, + /// DMA Select + DMASEL: u2, + reserved0: u1, + /// Card Detect Test Level + CARDDTL: u1, + /// Card Detect Signal Selection + CARDDSEL: u1, + }), base_address + 0x28); + + /// address: 0x45000028 + /// Host Control 1 + pub const HC1R_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Data Width + DW: u1, + /// High Speed Enable + HSEN: u1, + /// DMA Select + DMASEL: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x28); + + /// address: 0x45000029 + /// Power Control + pub const PCR = @intToPtr(*volatile Mmio(8, packed struct { + /// SD Bus Power + SDBPWR: u1, + /// SD Bus Voltage Select + SDBVSEL: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x29); + + /// address: 0x4500002a + /// Block Gap Control + pub const BGCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop at Block Gap Request + STPBGR: u1, + /// Continue Request + CONTR: u1, + /// Read Wait Control + RWCTRL: u1, + /// Interrupt at Block Gap + INTBG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2a); + + /// address: 0x4500002a + /// Block Gap Control + pub const BGCR_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop at Block Gap Request + STPBGR: u1, + /// Continue Request + CONTR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2a); + + /// address: 0x4500002b + /// Wakeup Control + pub const WCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Wakeup Event Enable on Card Interrupt + WKENCINT: u1, + /// Wakeup Event Enable on Card Insertion + WKENCINS: u1, + /// Wakeup Event Enable on Card Removal + WKENCREM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2b); + + /// address: 0x4500002c + /// Clock Control + pub const CCR = @intToPtr(*volatile Mmio(16, packed struct { + /// Internal Clock Enable + INTCLKEN: u1, + /// Internal Clock Stable + INTCLKS: u1, + /// SD Clock Enable + SDCLKEN: u1, + reserved0: u1, + reserved1: u1, + /// Clock Generator Select + CLKGSEL: u1, + /// Upper Bits of SDCLK Frequency Select + USDCLKFSEL: u2, + /// SDCLK Frequency Select + SDCLKFSEL: u8, + }), base_address + 0x2c); + + /// address: 0x4500002e + /// Timeout Control + pub const TCR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Timeout Counter Value + DTCVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2e); + + /// address: 0x4500002f + /// Software Reset + pub const SRR = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset For All + SWRSTALL: u1, + /// Software Reset For CMD Line + SWRSTCMD: u1, + /// Software Reset For DAT Line + SWRSTDAT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x2f); + + /// address: 0x45000030 + /// Normal Interrupt Status + pub const NISTR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete + CMDC: u1, + /// Transfer Complete + TRFC: u1, + /// Block Gap Event + BLKGE: u1, + /// DMA Interrupt + DMAINT: u1, + /// Buffer Write Ready + BWRRDY: u1, + /// Buffer Read Ready + BRDRDY: u1, + /// Card Insertion + CINS: u1, + /// Card Removal + CREM: u1, + /// Card Interrupt + CINT: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Error Interrupt + ERRINT: u1, + }), base_address + 0x30); + + /// address: 0x45000030 + /// Normal Interrupt Status + pub const NISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete + CMDC: u1, + /// Transfer Complete + TRFC: u1, + /// Block Gap Event + BLKGE: u1, + /// DMA Interrupt + DMAINT: u1, + /// Buffer Write Ready + BWRRDY: u1, + /// Buffer Read Ready + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received + BOOTAR: u1, + /// Error Interrupt + ERRINT: u1, + }), base_address + 0x30); + + /// address: 0x45000032 + /// Error Interrupt Status + pub const EISTR = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error + CMDTEO: u1, + /// Command CRC Error + CMDCRC: u1, + /// Command End Bit Error + CMDEND: u1, + /// Command Index Error + CMDIDX: u1, + /// Data Timeout Error + DATTEO: u1, + /// Data CRC Error + DATCRC: u1, + /// Data End Bit Error + DATEND: u1, + /// Current Limit Error + CURLIM: u1, + /// Auto CMD Error + ACMD: u1, + /// ADMA Error + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x32); + + /// address: 0x45000032 + /// Error Interrupt Status + pub const EISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error + CMDTEO: u1, + /// Command CRC Error + CMDCRC: u1, + /// Command End Bit Error + CMDEND: u1, + /// Command Index Error + CMDIDX: u1, + /// Data Timeout Error + DATTEO: u1, + /// Data CRC Error + DATCRC: u1, + /// Data End Bit Error + DATEND: u1, + /// Current Limit Error + CURLIM: u1, + /// Auto CMD Error + ACMD: u1, + /// ADMA Error + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x32); + + /// address: 0x45000034 + /// Normal Interrupt Status Enable + pub const NISTER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Status Enable + CMDC: u1, + /// Transfer Complete Status Enable + TRFC: u1, + /// Block Gap Event Status Enable + BLKGE: u1, + /// DMA Interrupt Status Enable + DMAINT: u1, + /// Buffer Write Ready Status Enable + BWRRDY: u1, + /// Buffer Read Ready Status Enable + BRDRDY: u1, + /// Card Insertion Status Enable + CINS: u1, + /// Card Removal Status Enable + CREM: u1, + /// Card Interrupt Status Enable + CINT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x34); + + /// address: 0x45000034 + /// Normal Interrupt Status Enable + pub const NISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Status Enable + CMDC: u1, + /// Transfer Complete Status Enable + TRFC: u1, + /// Block Gap Event Status Enable + BLKGE: u1, + /// DMA Interrupt Status Enable + DMAINT: u1, + /// Buffer Write Ready Status Enable + BWRRDY: u1, + /// Buffer Read Ready Status Enable + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received Status Enable + BOOTAR: u1, + padding0: u1, + }), base_address + 0x34); + + /// address: 0x45000036 + /// Error Interrupt Status Enable + pub const EISTER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Status Enable + CMDTEO: u1, + /// Command CRC Error Status Enable + CMDCRC: u1, + /// Command End Bit Error Status Enable + CMDEND: u1, + /// Command Index Error Status Enable + CMDIDX: u1, + /// Data Timeout Error Status Enable + DATTEO: u1, + /// Data CRC Error Status Enable + DATCRC: u1, + /// Data End Bit Error Status Enable + DATEND: u1, + /// Current Limit Error Status Enable + CURLIM: u1, + /// Auto CMD Error Status Enable + ACMD: u1, + /// ADMA Error Status Enable + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x36); + + /// address: 0x45000036 + /// Error Interrupt Status Enable + pub const EISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Status Enable + CMDTEO: u1, + /// Command CRC Error Status Enable + CMDCRC: u1, + /// Command End Bit Error Status Enable + CMDEND: u1, + /// Command Index Error Status Enable + CMDIDX: u1, + /// Data Timeout Error Status Enable + DATTEO: u1, + /// Data CRC Error Status Enable + DATCRC: u1, + /// Data End Bit Error Status Enable + DATEND: u1, + /// Current Limit Error Status Enable + CURLIM: u1, + /// Auto CMD Error Status Enable + ACMD: u1, + /// ADMA Error Status Enable + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error Status Enable + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x36); + + /// address: 0x45000038 + /// Normal Interrupt Signal Enable + pub const NISIER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Signal Enable + CMDC: u1, + /// Transfer Complete Signal Enable + TRFC: u1, + /// Block Gap Event Signal Enable + BLKGE: u1, + /// DMA Interrupt Signal Enable + DMAINT: u1, + /// Buffer Write Ready Signal Enable + BWRRDY: u1, + /// Buffer Read Ready Signal Enable + BRDRDY: u1, + /// Card Insertion Signal Enable + CINS: u1, + /// Card Removal Signal Enable + CREM: u1, + /// Card Interrupt Signal Enable + CINT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x38); + + /// address: 0x45000038 + /// Normal Interrupt Signal Enable + pub const NISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Complete Signal Enable + CMDC: u1, + /// Transfer Complete Signal Enable + TRFC: u1, + /// Block Gap Event Signal Enable + BLKGE: u1, + /// DMA Interrupt Signal Enable + DMAINT: u1, + /// Buffer Write Ready Signal Enable + BWRRDY: u1, + /// Buffer Read Ready Signal Enable + BRDRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Boot Acknowledge Received Signal Enable + BOOTAR: u1, + padding0: u1, + }), base_address + 0x38); + + /// address: 0x4500003a + /// Error Interrupt Signal Enable + pub const EISIER = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Signal Enable + CMDTEO: u1, + /// Command CRC Error Signal Enable + CMDCRC: u1, + /// Command End Bit Error Signal Enable + CMDEND: u1, + /// Command Index Error Signal Enable + CMDIDX: u1, + /// Data Timeout Error Signal Enable + DATTEO: u1, + /// Data CRC Error Signal Enable + DATCRC: u1, + /// Data End Bit Error Signal Enable + DATEND: u1, + /// Current Limit Error Signal Enable + CURLIM: u1, + /// Auto CMD Error Signal Enable + ACMD: u1, + /// ADMA Error Signal Enable + ADMA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x3a); + + /// address: 0x4500003a + /// Error Interrupt Signal Enable + pub const EISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Command Timeout Error Signal Enable + CMDTEO: u1, + /// Command CRC Error Signal Enable + CMDCRC: u1, + /// Command End Bit Error Signal Enable + CMDEND: u1, + /// Command Index Error Signal Enable + CMDIDX: u1, + /// Data Timeout Error Signal Enable + DATTEO: u1, + /// Data CRC Error Signal Enable + DATCRC: u1, + /// Data End Bit Error Signal Enable + DATEND: u1, + /// Current Limit Error Signal Enable + CURLIM: u1, + /// Auto CMD Error Signal Enable + ACMD: u1, + /// ADMA Error Signal Enable + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Boot Acknowledge Error Signal Enable + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x3a); + + /// address: 0x4500003c + /// Auto CMD Error Status + pub const ACESR = @intToPtr(*volatile Mmio(16, packed struct { + /// Auto CMD12 Not Executed + ACMD12NE: u1, + /// Auto CMD Timeout Error + ACMDTEO: u1, + /// Auto CMD CRC Error + ACMDCRC: u1, + /// Auto CMD End Bit Error + ACMDEND: u1, + /// Auto CMD Index Error + ACMDIDX: u1, + reserved0: u1, + reserved1: u1, + /// Command not Issued By Auto CMD12 Error + CMDNI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x3c); + + /// address: 0x4500003e + /// Host Control 2 + pub const HC2R = @intToPtr(*volatile Mmio(16, packed struct { + /// UHS Mode Select + UHSMS: u3, + /// 1.8V Signaling Enable + VS18EN: u1, + /// Driver Strength Select + DRVSEL: u2, + /// Execute Tuning + EXTUN: u1, + /// Sampling Clock Select + SLCKSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Asynchronous Interrupt Enable + ASINTEN: u1, + /// Preset Value Enable + PVALEN: u1, + }), base_address + 0x3e); + + /// address: 0x4500003e + /// Host Control 2 + pub const HC2R_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// HS200 Mode Enable + HS200EN: u4, + /// Driver Strength Select + DRVSEL: u2, + /// Execute Tuning + EXTUN: u1, + /// Sampling Clock Select + SLCKSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Preset Value Enable + PVALEN: u1, + }), base_address + 0x3e); + + /// address: 0x45000040 + /// Capabilities 0 + pub const CA0R = @intToPtr(*volatile Mmio(32, packed struct { + /// Timeout Clock Frequency + TEOCLKF: u6, + reserved0: u1, + /// Timeout Clock Unit + TEOCLKU: u1, + /// Base Clock Frequency + BASECLKF: u8, + /// Max Block Length + MAXBLKL: u2, + /// 8-bit Support for Embedded Device + ED8SUP: u1, + /// ADMA2 Support + ADMA2SUP: u1, + reserved1: u1, + /// High Speed Support + HSSUP: u1, + /// SDMA Support + SDMASUP: u1, + /// Suspend/Resume Support + SRSUP: u1, + /// Voltage Support 3.3V + V33VSUP: u1, + /// Voltage Support 3.0V + V30VSUP: u1, + /// Voltage Support 1.8V + V18VSUP: u1, + reserved2: u1, + /// 64-Bit System Bus Support + SB64SUP: u1, + /// Asynchronous Interrupt Support + ASINTSUP: u1, + /// Slot Type + SLTYPE: u2, + }), base_address + 0x40); + + /// address: 0x45000044 + /// Capabilities 1 + pub const CA1R = @intToPtr(*volatile Mmio(32, packed struct { + /// SDR50 Support + SDR50SUP: u1, + /// SDR104 Support + SDR104SUP: u1, + /// DDR50 Support + DDR50SUP: u1, + reserved0: u1, + /// Driver Type A Support + DRVASUP: u1, + /// Driver Type C Support + DRVCSUP: u1, + /// Driver Type D Support + DRVDSUP: u1, + reserved1: u1, + /// Timer Count for Re-Tuning + TCNTRT: u4, + reserved2: u1, + /// Use Tuning for SDR50 + TSDR50: u1, + reserved3: u1, + reserved4: u1, + /// Clock Multiplier + CLKMULT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x45000048 + /// Maximum Current Capabilities + pub const MCCAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Maximum Current for 3.3V + MAXCUR33V: u8, + /// Maximum Current for 3.0V + MAXCUR30V: u8, + /// Maximum Current for 1.8V + MAXCUR18V: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x48); + + /// address: 0x45000050 + /// Force Event for Auto CMD Error Status + pub const FERACES = @intToPtr(*volatile Mmio(16, packed struct { + /// Force Event for Auto CMD12 Not Executed + ACMD12NE: u1, + /// Force Event for Auto CMD Timeout Error + ACMDTEO: u1, + /// Force Event for Auto CMD CRC Error + ACMDCRC: u1, + /// Force Event for Auto CMD End Bit Error + ACMDEND: u1, + /// Force Event for Auto CMD Index Error + ACMDIDX: u1, + reserved0: u1, + reserved1: u1, + /// Force Event for Command Not Issued By Auto CMD12 Error + CMDNI: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x50); + + /// address: 0x45000052 + /// Force Event for Error Interrupt Status + pub const FEREIS = @intToPtr(*volatile Mmio(16, packed struct { + /// Force Event for Command Timeout Error + CMDTEO: u1, + /// Force Event for Command CRC Error + CMDCRC: u1, + /// Force Event for Command End Bit Error + CMDEND: u1, + /// Force Event for Command Index Error + CMDIDX: u1, + /// Force Event for Data Timeout Error + DATTEO: u1, + /// Force Event for Data CRC Error + DATCRC: u1, + /// Force Event for Data End Bit Error + DATEND: u1, + /// Force Event for Current Limit Error + CURLIM: u1, + /// Force Event for Auto CMD Error + ACMD: u1, + /// Force Event for ADMA Error + ADMA: u1, + reserved0: u1, + reserved1: u1, + /// Force Event for Boot Acknowledge Error + BOOTAE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x52); + + /// address: 0x45000054 + /// ADMA Error Status + pub const AESR = @intToPtr(*volatile Mmio(8, packed struct { + /// ADMA Error State + ERRST: u2, + /// ADMA Length Mismatch Error + LMIS: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x54); + + /// address: 0x45000058 + /// ADMA System Address n + pub const ASAR = @intToPtr(*volatile [1]Mmio(32, packed struct { + /// ADMA System Address + ADMASA: u32, + }), base_address + 0x58); + + /// address: 0x45000060 + /// Preset Value n + pub const PVR = @intToPtr(*volatile [8]Mmio(16, packed struct { + /// SDCLK Frequency Select Value for Initialization + SDCLKFSEL: u10, + /// Clock Generator Select Value for Initialization + CLKGSEL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Driver Strength Select Value for Initialization + DRVSEL: u2, + }), base_address + 0x60); + + /// address: 0x450000fc + /// Slot Interrupt Status + pub const SISR = @intToPtr(*volatile Mmio(16, packed struct { + /// Interrupt Signal for Each Slot + INTSSL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0xfc); + + /// address: 0x450000fe + /// Host Controller Version + pub const HCVR = @intToPtr(*volatile Mmio(16, packed struct { + /// Spec Version + SVER: u8, + /// Vendor Version + VVER: u8, + }), base_address + 0xfe); + + /// address: 0x45000204 + /// MMC Control 1 + pub const MC1R = @intToPtr(*volatile Mmio(8, packed struct { + /// e.MMC Command Type + CMDTYP: u2, + reserved0: u1, + /// e.MMC HSDDR Mode + DDR: u1, + /// e.MMC Open Drain Mode + OPD: u1, + /// e.MMC Boot Acknowledge Enable + BOOTA: u1, + /// e.MMC Reset Signal + RSTN: u1, + /// e.MMC Force Card Detect + FCD: u1, + }), base_address + 0x204); + + /// address: 0x45000205 + /// MMC Control 2 + pub const MC2R = @intToPtr(*volatile Mmio(8, packed struct { + /// e.MMC Abort Wait IRQ + SRESP: u1, + /// e.MMC Abort Boot + ABOOT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x205); + + /// address: 0x45000208 + /// AHB Control + pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { + /// AHB Maximum Burst + BMAX: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x208); + + /// address: 0x4500020c + /// Clock Control 2 + pub const CC2R = @intToPtr(*volatile Mmio(32, packed struct { + /// Force SDCK Disabled + FSDCLKD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0x20c); + + /// address: 0x45000230 + /// Capabilities Control + pub const CACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Capabilities Registers Write Enable (Required to write the correct frequencies + /// in the Capabilities Registers) + CAPWREN: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Key (0x46) + KEY: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x230); + + /// address: 0x45000234 + /// Debug + pub const DBGR = @intToPtr(*volatile Mmio(8, packed struct { + /// Non-intrusive debug enable + NIDBG: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x234); + }; + + /// Serial Communication Interface + pub const SERCOM0 = struct { + pub const base_address = 0x40003000; + pub const version = "U22015.0.0"; + + /// I2C Master Mode + pub const I2CM = struct { + /// address: 0x40003000 + /// I2CM Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run in Standby + RUNSTDBY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Pin Usage + PINOUT: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// SDA Hold Time + SDAHOLD: u2, + /// Master SCL Low Extend Timeout + MEXTTOEN: u1, + /// Slave SCL Low Extend Timeout + SEXTTOEN: u1, + /// Transfer Speed + SPEED: u2, + reserved13: u1, + /// SCL Clock Stretch Mode + SCLSM: u1, + /// Inactive Time-Out + INACTOUT: u2, + /// SCL Low Timeout Enable + LOWTOUTEN: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// I2CM Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Smart Mode Enable + SMEN: u1, + /// Quick Command Enable + QCEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// Command + CMD: u2, + /// Acknowledge Action + ACKACT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// I2CM Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// I2CM Baud Rate + pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { + /// Baud Rate Value + BAUD: u8, + /// Baud Rate Value Low + BAUDLOW: u8, + /// High Speed Baud Rate Value + HSBAUD: u8, + /// High Speed Baud Rate Value Low + HSBAUDLOW: u8, + }), base_address + 0xc); + + /// address: 0x40003014 + /// I2CM Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt Disable + MB: u1, + /// Slave On Bus Interrupt Disable + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// I2CM Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt Enable + MB: u1, + /// Slave On Bus Interrupt Enable + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// I2CM Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Master On Bus Interrupt + MB: u1, + /// Slave On Bus Interrupt + SB: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// I2CM Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Bus Error + BUSERR: u1, + /// Arbitration Lost + ARBLOST: u1, + /// Received Not Acknowledge + RXNACK: u1, + reserved0: u1, + /// Bus State + BUSSTATE: u2, + /// SCL Low Timeout + LOWTOUT: u1, + /// Clock Hold + CLKHOLD: u1, + /// Master SCL Low Extend Timeout + MEXTTOUT: u1, + /// Slave SCL Low Extend Timeout + SEXTTOUT: u1, + /// Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// I2CM Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// System Operation Synchronization Busy + SYSOP: u1, + reserved0: u1, + /// Length Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003024 + /// I2CM Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u11, + reserved0: u1, + reserved1: u1, + /// Length Enable + LENEN: u1, + /// High Speed Mode + HS: u1, + /// Ten Bit Addressing Enable + TENBITEN: u1, + /// Length + LEN: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// I2CM Data + pub const DATA = @intToPtr(*volatile u8, base_address + 0x28); + + /// address: 0x40003030 + /// I2CM Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// I2C Slave Mode + pub const I2CS = struct { + /// address: 0x40003000 + /// I2CS Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Pin Usage + PINOUT: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// SDA Hold Time + SDAHOLD: u2, + reserved13: u1, + /// Slave SCL Low Extend Timeout + SEXTTOEN: u1, + /// Transfer Speed + SPEED: u2, + reserved14: u1, + /// SCL Clock Stretch Mode + SCLSM: u1, + reserved15: u1, + reserved16: u1, + /// SCL Low Timeout Enable + LOWTOUTEN: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// I2CS Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Smart Mode Enable + SMEN: u1, + /// PMBus Group Command + GCMD: u1, + /// Automatic Address Acknowledge + AACKEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Address Mode + AMODE: u2, + /// Command + CMD: u2, + /// Acknowledge Action + ACKACT: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// I2CS Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// SDA Setup Time + SDASETUP: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x40003014 + /// I2CS Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt Disable + PREC: u1, + /// Address Match Interrupt Disable + AMATCH: u1, + /// Data Interrupt Disable + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// I2CS Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt Enable + PREC: u1, + /// Address Match Interrupt Enable + AMATCH: u1, + /// Data Interrupt Enable + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// I2CS Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Received Interrupt + PREC: u1, + /// Address Match Interrupt + AMATCH: u1, + /// Data Interrupt + DRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// I2CS Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Bus Error + BUSERR: u1, + /// Transmit Collision + COLL: u1, + /// Received Not Acknowledge + RXNACK: u1, + /// Read/Write Direction + DIR: u1, + /// Repeated Start + SR: u1, + reserved0: u1, + /// SCL Low Timeout + LOWTOUT: u1, + /// Clock Hold + CLKHOLD: u1, + reserved1: u1, + /// Slave SCL Low Extend Timeout + SEXTTOUT: u1, + /// High Speed + HS: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// I2CS Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + reserved0: u1, + reserved1: u1, + /// Length Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// I2CS Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// I2CS Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// General Call Address Enable + GENCEN: u1, + /// Address Value + ADDR: u10, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Ten Bit Addressing Enable + TENBITEN: u1, + reserved4: u1, + /// Address Mask + ADDRMASK: u10, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// I2CS Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + }; + + /// SPI Slave Mode + pub const SPIS = struct { + /// address: 0x40003000 + /// SPIS Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data Out Pinout + DOPO: u2, + reserved9: u1, + reserved10: u1, + /// Data In Pinout + DIPO: u2, + reserved11: u1, + reserved12: u1, + /// Frame Format + FORM: u4, + /// Clock Phase + CPHA: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// SPIS Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Preload Enable + PLOADEN: u1, + reserved3: u1, + reserved4: u1, + /// Slave Select Low Detect Enable + SSDE: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Master Slave Select Enable + MSSEN: u1, + /// Address Mode + AMODE: u2, + reserved8: u1, + /// Receiver Enable + RXEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// SPIS Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Inter-Character Spacing + ICSPACE: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// SPIS Baud Rate + pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); + + /// address: 0x40003014 + /// SPIS Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Slave Select Low Interrupt Disable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// SPIS Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Slave Select Low Interrupt Enable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// SPIS Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Slave Select Low Interrupt Flag + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// SPIS Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Buffer Overflow + BUFOVF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// SPIS Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + reserved0: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// SPIS Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// SPIS Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Address Mask + ADDRMASK: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// SPIS Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// SPIS Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// SPI Master Mode + pub const SPIM = struct { + /// address: 0x40003000 + /// SPIM Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data Out Pinout + DOPO: u2, + reserved9: u1, + reserved10: u1, + /// Data In Pinout + DIPO: u2, + reserved11: u1, + reserved12: u1, + /// Frame Format + FORM: u4, + /// Clock Phase + CPHA: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// SPIM Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Data Preload Enable + PLOADEN: u1, + reserved3: u1, + reserved4: u1, + /// Slave Select Low Detect Enable + SSDE: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Master Slave Select Enable + MSSEN: u1, + /// Address Mode + AMODE: u2, + reserved8: u1, + /// Receiver Enable + RXEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// SPIM Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Inter-Character Spacing + ICSPACE: u6, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// Data 32 Bit + DATA32B: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// SPIM Baud Rate + pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); + + /// address: 0x40003014 + /// SPIM Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Slave Select Low Interrupt Disable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// SPIM Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Slave Select Low Interrupt Enable + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// SPIM Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Slave Select Low Interrupt Flag + SSL: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// SPIM Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Buffer Overflow + BUFOVF: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Transaction Length Error + LENERR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// SPIM Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + reserved0: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003022 + /// SPIM Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x22); + + /// address: 0x40003024 + /// SPIM Address + pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address Value + ADDR: u8, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + /// Address Mask + ADDRMASK: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x24); + + /// address: 0x40003028 + /// SPIM Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// SPIM Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// USART EXTERNAL CLOCK Mode + pub const USART_EXT = struct { + /// address: 0x40003000 + /// USART_EXT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_EXT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_EXT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_EXT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_EXT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_EXT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_EXT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_EXT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_EXT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_EXT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_EXT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_EXT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_EXT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_EXT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + + /// USART INTERNAL CLOCK Mode + pub const USART_INT = struct { + /// address: 0x40003000 + /// USART_INT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_INT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_INT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_INT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_INT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_INT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_INT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_INT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_INT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_INT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_INT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_INT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_INT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + }; + pub const SERCOM1 = struct { + pub const base_address = 0x40003400; + }; + pub const SERCOM2 = struct { + pub const base_address = 0x41012000; + }; + pub const SERCOM3 = struct { + pub const base_address = 0x41014000; + }; + pub const SERCOM4 = struct { + pub const base_address = 0x43000000; + }; + pub const SERCOM5 = struct { + pub const base_address: usize = 0x43000400; + + pub const USART_INT = struct { + /// address: 0x40003000 + /// USART_INT Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Operating Mode + MODE: u3, + reserved0: u1, + reserved1: u1, + /// Run during Standby + RUNSTDBY: u1, + /// Immediate Buffer Overflow Notification + IBON: u1, + /// Transmit Data Invert + TXINV: u1, + /// Receive Data Invert + RXINV: u1, + reserved2: u1, + reserved3: u1, + /// Sample + SAMPR: u3, + /// Transmit Data Pinout + TXPO: u2, + reserved4: u1, + reserved5: u1, + /// Receive Data Pinout + RXPO: u2, + /// Sample Adjustment + SAMPA: u2, + /// Frame Format + FORM: u4, + /// Communication Mode + CMODE: u1, + /// Clock Polarity + CPOL: u1, + /// Data Order + DORD: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x40003004 + /// USART_INT Control B + pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Character Size + CHSIZE: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Stop Bit Mode + SBMODE: u1, + reserved3: u1, + /// Collision Detection Enable + COLDEN: u1, + /// Start of Frame Detection Enable + SFDE: u1, + /// Encoding Format + ENC: u1, + reserved4: u1, + reserved5: u1, + /// Parity Mode + PMODE: u1, + reserved6: u1, + reserved7: u1, + /// Transmitter Enable + TXEN: u1, + /// Receiver Enable + RXEN: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + /// LIN Command + LINCMD: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x4); + + /// address: 0x40003008 + /// USART_INT Control C + pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { + /// Guard Time + GTIME: u3, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// LIN Master Break Length + BRKLEN: u2, + /// LIN Master Header Delay + HDRDLY: u2, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Inhibit Not Acknowledge + INACK: u1, + /// Disable Successive NACK + DSNACK: u1, + reserved9: u1, + reserved10: u1, + /// Maximum Iterations + MAXITER: u3, + reserved11: u1, + /// Data 32 Bit + DATA32B: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x8); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u13, + /// Fractional Part + FP: u3, + }), base_address + 0xc); + + /// address: 0x4000300c + /// USART_INT Baud Rate + pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { + /// Baud Rate Value + BAUD: u16, + }), base_address + 0xc); + + /// address: 0x4000300e + /// USART_INT Receive Pulse Length + pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); + + /// address: 0x40003014 + /// USART_INT Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Disable + DRE: u1, + /// Transmit Complete Interrupt Disable + TXC: u1, + /// Receive Complete Interrupt Disable + RXC: u1, + /// Receive Start Interrupt Disable + RXS: u1, + /// Clear To Send Input Change Interrupt Disable + CTSIC: u1, + /// Break Received Interrupt Disable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Disable + ERROR: u1, + }), base_address + 0x14); + + /// address: 0x40003016 + /// USART_INT Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt Enable + DRE: u1, + /// Transmit Complete Interrupt Enable + TXC: u1, + /// Receive Complete Interrupt Enable + RXC: u1, + /// Receive Start Interrupt Enable + RXS: u1, + /// Clear To Send Input Change Interrupt Enable + CTSIC: u1, + /// Break Received Interrupt Enable + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt Enable + ERROR: u1, + }), base_address + 0x16); + + /// address: 0x40003018 + /// USART_INT Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Register Empty Interrupt + DRE: u1, + /// Transmit Complete Interrupt + TXC: u1, + /// Receive Complete Interrupt + RXC: u1, + /// Receive Start Interrupt + RXS: u1, + /// Clear To Send Input Change Interrupt + CTSIC: u1, + /// Break Received Interrupt + RXBRK: u1, + reserved0: u1, + /// Combined Error Interrupt + ERROR: u1, + }), base_address + 0x18); + + /// address: 0x4000301a + /// USART_INT Status + pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { + /// Parity Error + PERR: u1, + /// Frame Error + FERR: u1, + /// Buffer Overflow + BUFOVF: u1, + /// Clear To Send + CTS: u1, + /// Inconsistent Sync Field + ISF: u1, + /// Collision Detected + COLL: u1, + /// Transmitter Empty + TXE: u1, + /// Maximum Number of Repetitions Reached + ITER: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x1a); + + /// address: 0x4000301c + /// USART_INT Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// SERCOM Enable Synchronization Busy + ENABLE: u1, + /// CTRLB Synchronization Busy + CTRLB: u1, + /// RXERRCNT Synchronization Busy + RXERRCNT: u1, + /// LENGTH Synchronization Busy + LENGTH: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x1c); + + /// address: 0x40003020 + /// USART_INT Receive Error Count + pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); + + /// address: 0x40003022 + /// USART_INT Length + pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { + /// Data Length + LEN: u8, + /// Data Length Enable + LENEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x22); + + /// address: 0x40003028 + /// USART_INT Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x40003030 + /// USART_INT Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Mode + DBGSTOP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x30); + }; + }; + + /// Supply Controller + pub const SUPC = struct { + pub const base_address = 0x40001800; + pub const version = "U24071.1.0"; + + /// address: 0x40001800 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x0); + + /// address: 0x40001804 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x4); + + /// address: 0x40001808 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0x8); + + /// address: 0x4000180c + /// Power and Clocks Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// BOD33 Ready + BOD33RDY: u1, + /// BOD33 Detection + BOD33DET: u1, + /// BOD33 Synchronization Ready + B33SRDY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Voltage Regulator Ready + VREGRDY: u1, + reserved5: u1, + /// VDDCORE Ready + VCORERDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + }), base_address + 0xc); + + /// address: 0x40001810 + /// BOD33 Control + pub const BOD33 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Action when Threshold Crossed + ACTION: u2, + /// Configuration in Standby mode + STDBYCFG: u1, + /// Run in Standby mode + RUNSTDBY: u1, + /// Run in Hibernate mode + RUNHIB: u1, + /// Run in Backup mode + RUNBKUP: u1, + /// Hysteresis value + HYST: u4, + /// Prescaler Select + PSEL: u3, + reserved1: u1, + /// Threshold Level for VDD + LEVEL: u8, + /// Threshold Level in battery backup sleep mode for VBAT + VBATLEVEL: u8, + }), base_address + 0x10); + + /// address: 0x40001818 + /// VREG Control + pub const VREG = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Voltage Regulator Selection + SEL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Backup mode + RUNBKUP: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + /// Voltage Scaling Enable + VSEN: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Voltage Scaling Period + VSPER: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x18); + + /// address: 0x4000181c + /// VREF Control + pub const VREF = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Temperature Sensor Output Enable + TSEN: u1, + /// Voltage Reference Output Enable + VREFOE: u1, + /// Temperature Sensor Selection + TSSEL: u1, + reserved1: u1, + reserved2: u1, + /// Run during Standby + RUNSTDBY: u1, + /// On Demand Contrl + ONDEMAND: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// Voltage Reference Selection + SEL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + }), base_address + 0x1c); + + /// address: 0x40001820 + /// Battery Backup Power Switch + pub const BBPS = @intToPtr(*volatile Mmio(32, packed struct { + /// Battery Backup Configuration + CONF: u1, + reserved0: u1, + /// Wake Enable + WAKEEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x20); + + /// address: 0x40001824 + /// Backup Output Control + pub const BKOUT = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable OUT0 + ENOUT0: u1, + /// Enable OUT1 + ENOUT1: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Clear OUT0 + CLROUT0: u1, + /// Clear OUT1 + CLROUT1: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + /// Set OUT0 + SETOUT0: u1, + /// Set OUT1 + SETOUT1: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + /// RTC Toggle OUT0 + RTCTGLOUT0: u1, + /// RTC Toggle OUT1 + RTCTGLOUT1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x24); + + /// address: 0x40001828 + /// Backup Input Control + pub const BKIN = @intToPtr(*volatile Mmio(32, packed struct { + /// Backup Input 0 + BKIN0: u1, + /// Backup Input 1 + BKIN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0x28); + }; + + /// Basic Timer Counter + pub const TC0 = struct { + pub const base_address = 0x40003800; + pub const version = "U22493.0.0"; + + /// 8-bit Counter Mode + pub const COUNT8 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT8 Count + pub const COUNT = @intToPtr(*volatile u8, base_address + 0x14); + + /// address: 0x4000381b + /// COUNT8 Period + pub const PER = @intToPtr(*volatile u8, base_address + 0x1b); + + /// address: 0x4000381c + /// COUNT8 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u8, base_address + 0x1c); + + /// address: 0x4000382f + /// COUNT8 Period Buffer + pub const PERBUF = @intToPtr(*volatile u8, base_address + 0x2f); + + /// address: 0x40003830 + /// COUNT8 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u8, base_address + 0x30); + }; + + /// 16-bit Counter Mode + pub const COUNT16 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT16 Count + pub const COUNT = @intToPtr(*volatile u16, base_address + 0x14); + + /// address: 0x4000381c + /// COUNT16 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u16, base_address + 0x1c); + + /// address: 0x40003830 + /// COUNT16 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u16, base_address + 0x30); + }; + + /// 32-bit Counter Mode + pub const COUNT32 = struct { + /// address: 0x40003800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Timer Counter Mode + MODE: u2, + /// Prescaler and Counter Synchronization + PRESCSYNC: u2, + /// Run during Standby + RUNSTDBY: u1, + /// Clock On Demand + ONDEMAND: u1, + /// Prescaler + PRESCALER: u3, + /// Auto Lock + ALOCK: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Capture Channel 0 Enable + CAPTEN0: u1, + /// Capture Channel 1 Enable + CAPTEN1: u1, + reserved4: u1, + reserved5: u1, + /// Capture On Pin 0 Enable + COPEN0: u1, + /// Capture On Pin 1 Enable + COPEN1: u1, + reserved6: u1, + reserved7: u1, + /// Capture Mode Channel 0 + CAPTMODE0: u2, + reserved8: u1, + /// Capture mode Channel 1 + CAPTMODE1: u2, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0x40003804 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x40003805 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot on Counter + ONESHOT: u1, + reserved0: u1, + reserved1: u1, + /// Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x40003806 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { + /// Event Action + EVACT: u3, + reserved0: u1, + /// TC Event Input Polarity + TCINV: u1, + /// TC Event Enable + TCEI: u1, + reserved1: u1, + reserved2: u1, + /// Event Output Enable + OVFEO: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// MC Event Output Enable 0 + MCEO0: u1, + /// MC Event Output Enable 1 + MCEO1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x6); + + /// address: 0x40003808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Disable + OVF: u1, + /// ERR Interrupt Disable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Disable 0 + MC0: u1, + /// MC Interrupt Disable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x8); + + /// address: 0x40003809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Enable + OVF: u1, + /// ERR Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Enable 0 + MC0: u1, + /// MC Interrupt Enable 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x9); + + /// address: 0x4000380a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// OVF Interrupt Flag + OVF: u1, + /// ERR Interrupt Flag + ERR: u1, + reserved0: u1, + reserved1: u1, + /// MC Interrupt Flag 0 + MC0: u1, + /// MC Interrupt Flag 1 + MC1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xa); + + /// address: 0x4000380b + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Stop Status Flag + STOP: u1, + /// Slave Status Flag + SLAVE: u1, + reserved0: u1, + /// Synchronization Busy Status + PERBUFV: u1, + /// Compare channel buffer 0 valid + CCBUFV0: u1, + /// Compare channel buffer 1 valid + CCBUFV1: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xb); + + /// address: 0x4000380c + /// Waveform Generation Control + pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { + /// Waveform Generation Mode + WAVEGEN: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xc); + + /// address: 0x4000380d + /// Control C + pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Output Waveform Invert Enable 0 + INVEN0: u1, + /// Output Waveform Invert Enable 1 + INVEN1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd); + + /// address: 0x4000380f + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Run During Debug + DBGRUN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xf); + + /// address: 0x40003810 + /// Synchronization Status + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// swrst + SWRST: u1, + /// enable + ENABLE: u1, + /// CTRLB + CTRLB: u1, + /// STATUS + STATUS: u1, + /// Counter + COUNT: u1, + /// Period + PER: u1, + /// Compare Channel 0 + CC0: u1, + /// Compare Channel 1 + CC1: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x10); + + /// address: 0x40003814 + /// COUNT32 Count + pub const COUNT = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x4000381c + /// COUNT32 Compare and Capture + pub const CC = @intToPtr(*volatile [2]u32, base_address + 0x1c); + + /// address: 0x40003830 + /// COUNT32 Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [2]u32, base_address + 0x30); + }; + }; + pub const TC1 = struct { + pub const base_address = 0x40003c00; + }; + pub const TC2 = struct { + pub const base_address = 0x4101a000; + }; + pub const TC3 = struct { + pub const base_address = 0x4101c000; + }; + pub const TC4 = struct { + pub const base_address = 0x42001400; + }; + pub const TC5 = struct { + pub const base_address = 0x42001800; + }; + + /// Timer Counter Control + pub const TCC0 = struct { + pub const base_address = 0x41016000; + pub const version = "U22133.1.0"; + + /// address: 0x41016000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x41016004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x41016005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x41016008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4101600c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x41016010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x41016014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x41016018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4101601e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x41016020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x41016024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x41016028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4101602c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x41016030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x41016034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41016038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4101603c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x41016040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41016064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101606c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41016070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC1 = struct { + pub const base_address = 0x41018000; + + /// address: 0x41018000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x41018004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x41018005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x41018008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4101800c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x41018010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x41018014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x41018018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4101801e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x41018020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x41018024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x41018028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4101802c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x41018030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x41018034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x41018038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4101803c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x41018040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x41018064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4101806c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x41018070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC2 = struct { + pub const base_address = 0x42000c00; + + /// address: 0x42000c00 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42000c04 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42000c05 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42000c08 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x42000c0c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x42000c10 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x42000c14 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x42000c18 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x42000c1e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x42000c20 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x42000c24 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x42000c28 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x42000c2c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x42000c30 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x42000c34 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c34 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42000c38 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x42000c3c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x42000c40 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c40 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c44 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42000c64 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c6c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42000c70 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC3 = struct { + pub const base_address = 0x42001000; + + /// address: 0x42001000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x42001004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x42001005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x42001008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4200100c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x42001010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x42001014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x42001018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4200101e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x42001020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x42001024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x42001028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4200102c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x42001030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x42001034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x42001038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4200103c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x42001040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x42001064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4200106c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x42001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + pub const TCC4 = struct { + pub const base_address = 0x43001000; + + /// address: 0x43001000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Enhanced Resolution + RESOLUTION: u2, + reserved3: u1, + /// Prescaler + PRESCALER: u3, + /// Run in Standby + RUNSTDBY: u1, + /// Prescaler and Counter Synchronization Selection + PRESCSYNC: u2, + /// Auto Lock + ALOCK: u1, + /// Master Synchronization (only for TCC Slave Instance) + MSYNC: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + /// DMA One-shot Trigger Mode + DMAOS: u1, + /// Capture Channel 0 Enable + CPTEN0: u1, + /// Capture Channel 1 Enable + CPTEN1: u1, + /// Capture Channel 2 Enable + CPTEN2: u1, + /// Capture Channel 3 Enable + CPTEN3: u1, + /// Capture Channel 4 Enable + CPTEN4: u1, + /// Capture Channel 5 Enable + CPTEN5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x0); + + /// address: 0x43001004 + /// Control B Clear + pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x4); + + /// address: 0x43001005 + /// Control B Set + pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Counter Direction + DIR: u1, + /// Lock Update + LUPD: u1, + /// One-Shot + ONESHOT: u1, + /// Ramp Index Command + IDXCMD: u2, + /// TCC Command + CMD: u3, + }), base_address + 0x5); + + /// address: 0x43001008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + /// Swrst Busy + SWRST: u1, + /// Enable Busy + ENABLE: u1, + /// Ctrlb Busy + CTRLB: u1, + /// Status Busy + STATUS: u1, + /// Count Busy + COUNT: u1, + /// Pattern Busy + PATT: u1, + /// Wave Busy + WAVE: u1, + /// Period Busy + PER: u1, + /// Compare Channel 0 Busy + CC0: u1, + /// Compare Channel 1 Busy + CC1: u1, + /// Compare Channel 2 Busy + CC2: u1, + /// Compare Channel 3 Busy + CC3: u1, + /// Compare Channel 4 Busy + CC4: u1, + /// Compare Channel 5 Busy + CC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + }), base_address + 0x8); + + /// address: 0x4300100c + /// Recoverable Fault A Configuration + pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault A Source + SRC: u2, + reserved0: u1, + /// Fault A Keeper + KEEP: u1, + /// Fault A Qualification + QUAL: u1, + /// Fault A Blanking Mode + BLANK: u2, + /// Fault A Restart + RESTART: u1, + /// Fault A Halt Mode + HALT: u2, + /// Fault A Capture Channel + CHSEL: u2, + /// Fault A Capture Action + CAPTURE: u3, + /// Fault A Blanking Prescaler + BLANKPRESC: u1, + /// Fault A Blanking Time + BLANKVAL: u8, + /// Fault A Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0xc); + + /// address: 0x43001010 + /// Recoverable Fault B Configuration + pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { + /// Fault B Source + SRC: u2, + reserved0: u1, + /// Fault B Keeper + KEEP: u1, + /// Fault B Qualification + QUAL: u1, + /// Fault B Blanking Mode + BLANK: u2, + /// Fault B Restart + RESTART: u1, + /// Fault B Halt Mode + HALT: u2, + /// Fault B Capture Channel + CHSEL: u2, + /// Fault B Capture Action + CAPTURE: u3, + /// Fault B Blanking Prescaler + BLANKPRESC: u1, + /// Fault B Blanking Time + BLANKVAL: u8, + /// Fault B Filter Value + FILTERVAL: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x10); + + /// address: 0x43001014 + /// Waveform Extension Configuration + pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Output Matrix + OTMX: u2, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Dead-time Insertion Generator 0 Enable + DTIEN0: u1, + /// Dead-time Insertion Generator 1 Enable + DTIEN1: u1, + /// Dead-time Insertion Generator 2 Enable + DTIEN2: u1, + /// Dead-time Insertion Generator 3 Enable + DTIEN3: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + /// Dead-time Low Side Outputs Value + DTLS: u8, + /// Dead-time High Side Outputs Value + DTHS: u8, + }), base_address + 0x14); + + /// address: 0x43001018 + /// Driver Control + pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Non-Recoverable State 0 Output Enable + NRE0: u1, + /// Non-Recoverable State 1 Output Enable + NRE1: u1, + /// Non-Recoverable State 2 Output Enable + NRE2: u1, + /// Non-Recoverable State 3 Output Enable + NRE3: u1, + /// Non-Recoverable State 4 Output Enable + NRE4: u1, + /// Non-Recoverable State 5 Output Enable + NRE5: u1, + /// Non-Recoverable State 6 Output Enable + NRE6: u1, + /// Non-Recoverable State 7 Output Enable + NRE7: u1, + /// Non-Recoverable State 0 Output Value + NRV0: u1, + /// Non-Recoverable State 1 Output Value + NRV1: u1, + /// Non-Recoverable State 2 Output Value + NRV2: u1, + /// Non-Recoverable State 3 Output Value + NRV3: u1, + /// Non-Recoverable State 4 Output Value + NRV4: u1, + /// Non-Recoverable State 5 Output Value + NRV5: u1, + /// Non-Recoverable State 6 Output Value + NRV6: u1, + /// Non-Recoverable State 7 Output Value + NRV7: u1, + /// Output Waveform 0 Inversion + INVEN0: u1, + /// Output Waveform 1 Inversion + INVEN1: u1, + /// Output Waveform 2 Inversion + INVEN2: u1, + /// Output Waveform 3 Inversion + INVEN3: u1, + /// Output Waveform 4 Inversion + INVEN4: u1, + /// Output Waveform 5 Inversion + INVEN5: u1, + /// Output Waveform 6 Inversion + INVEN6: u1, + /// Output Waveform 7 Inversion + INVEN7: u1, + /// Non-Recoverable Fault Input 0 Filter Value + FILTERVAL0: u4, + /// Non-Recoverable Fault Input 1 Filter Value + FILTERVAL1: u4, + }), base_address + 0x18); + + /// address: 0x4300101e + /// Debug Control + pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Debug Running Mode + DBGRUN: u1, + reserved0: u1, + /// Fault Detection on Debug Break Detection + FDDBD: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x1e); + + /// address: 0x43001020 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Timer/counter Input Event0 Action + EVACT0: u3, + /// Timer/counter Input Event1 Action + EVACT1: u3, + /// Timer/counter Output Event Mode + CNTSEL: u2, + /// Overflow/Underflow Output Event Enable + OVFEO: u1, + /// Retrigger Output Event Enable + TRGEO: u1, + /// Timer/counter Output Event Enable + CNTEO: u1, + reserved0: u1, + /// Inverted Event 0 Input Enable + TCINV0: u1, + /// Inverted Event 1 Input Enable + TCINV1: u1, + /// Timer/counter Event 0 Input Enable + TCEI0: u1, + /// Timer/counter Event 1 Input Enable + TCEI1: u1, + /// Match or Capture Channel 0 Event Input Enable + MCEI0: u1, + /// Match or Capture Channel 1 Event Input Enable + MCEI1: u1, + /// Match or Capture Channel 2 Event Input Enable + MCEI2: u1, + /// Match or Capture Channel 3 Event Input Enable + MCEI3: u1, + /// Match or Capture Channel 4 Event Input Enable + MCEI4: u1, + /// Match or Capture Channel 5 Event Input Enable + MCEI5: u1, + reserved1: u1, + reserved2: u1, + /// Match or Capture Channel 0 Event Output Enable + MCEO0: u1, + /// Match or Capture Channel 1 Event Output Enable + MCEO1: u1, + /// Match or Capture Channel 2 Event Output Enable + MCEO2: u1, + /// Match or Capture Channel 3 Event Output Enable + MCEO3: u1, + /// Match or Capture Channel 4 Event Output Enable + MCEO4: u1, + /// Match or Capture Channel 5 Event Output Enable + MCEO5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x20); + + /// address: 0x43001024 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x24); + + /// address: 0x43001028 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow Interrupt Enable + OVF: u1, + /// Retrigger Interrupt Enable + TRG: u1, + /// Counter Interrupt Enable + CNT: u1, + /// Error Interrupt Enable + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault Interrupt Enable + UFS: u1, + /// Non-Recoverable Debug Fault Interrupt Enable + DFS: u1, + /// Recoverable Fault A Interrupt Enable + FAULTA: u1, + /// Recoverable Fault B Interrupt Enable + FAULTB: u1, + /// Non-Recoverable Fault 0 Interrupt Enable + FAULT0: u1, + /// Non-Recoverable Fault 1 Interrupt Enable + FAULT1: u1, + /// Match or Capture Channel 0 Interrupt Enable + MC0: u1, + /// Match or Capture Channel 1 Interrupt Enable + MC1: u1, + /// Match or Capture Channel 2 Interrupt Enable + MC2: u1, + /// Match or Capture Channel 3 Interrupt Enable + MC3: u1, + /// Match or Capture Channel 4 Interrupt Enable + MC4: u1, + /// Match or Capture Channel 5 Interrupt Enable + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x28); + + /// address: 0x4300102c + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { + /// Overflow + OVF: u1, + /// Retrigger + TRG: u1, + /// Counter + CNT: u1, + /// Error + ERR: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Non-Recoverable Update Fault + UFS: u1, + /// Non-Recoverable Debug Fault + DFS: u1, + /// Recoverable Fault A + FAULTA: u1, + /// Recoverable Fault B + FAULTB: u1, + /// Non-Recoverable Fault 0 + FAULT0: u1, + /// Non-Recoverable Fault 1 + FAULT1: u1, + /// Match or Capture 0 + MC0: u1, + /// Match or Capture 1 + MC1: u1, + /// Match or Capture 2 + MC2: u1, + /// Match or Capture 3 + MC3: u1, + /// Match or Capture 4 + MC4: u1, + /// Match or Capture 5 + MC5: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + }), base_address + 0x2c); + + /// address: 0x43001030 + /// Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Stop + STOP: u1, + /// Ramp + IDX: u1, + /// Non-recoverable Update Fault State + UFS: u1, + /// Non-Recoverable Debug Fault State + DFS: u1, + /// Slave + SLAVE: u1, + /// Pattern Buffer Valid + PATTBUFV: u1, + reserved0: u1, + /// Period Buffer Valid + PERBUFV: u1, + /// Recoverable Fault A Input + FAULTAIN: u1, + /// Recoverable Fault B Input + FAULTBIN: u1, + /// Non-Recoverable Fault0 Input + FAULT0IN: u1, + /// Non-Recoverable Fault1 Input + FAULT1IN: u1, + /// Recoverable Fault A State + FAULTA: u1, + /// Recoverable Fault B State + FAULTB: u1, + /// Non-Recoverable Fault 0 State + FAULT0: u1, + /// Non-Recoverable Fault 1 State + FAULT1: u1, + /// Compare Channel 0 Buffer Valid + CCBUFV0: u1, + /// Compare Channel 1 Buffer Valid + CCBUFV1: u1, + /// Compare Channel 2 Buffer Valid + CCBUFV2: u1, + /// Compare Channel 3 Buffer Valid + CCBUFV3: u1, + /// Compare Channel 4 Buffer Valid + CCBUFV4: u1, + /// Compare Channel 5 Buffer Valid + CCBUFV5: u1, + reserved1: u1, + reserved2: u1, + /// Compare Channel 0 Value + CMP0: u1, + /// Compare Channel 1 Value + CMP1: u1, + /// Compare Channel 2 Value + CMP2: u1, + /// Compare Channel 3 Value + CMP3: u1, + /// Compare Channel 4 Value + CMP4: u1, + /// Compare Channel 5 Value + CMP5: u1, + padding0: u1, + padding1: u1, + }), base_address + 0x30); + + /// address: 0x43001034 + /// Count + pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Counter Value + COUNT: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Counter Value + COUNT: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001034 + /// Count + pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Counter Value + COUNT: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x34); + + /// address: 0x43001038 + /// Pattern + pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable + PGE0: u1, + /// Pattern Generator 1 Output Enable + PGE1: u1, + /// Pattern Generator 2 Output Enable + PGE2: u1, + /// Pattern Generator 3 Output Enable + PGE3: u1, + /// Pattern Generator 4 Output Enable + PGE4: u1, + /// Pattern Generator 5 Output Enable + PGE5: u1, + /// Pattern Generator 6 Output Enable + PGE6: u1, + /// Pattern Generator 7 Output Enable + PGE7: u1, + /// Pattern Generator 0 Output Value + PGV0: u1, + /// Pattern Generator 1 Output Value + PGV1: u1, + /// Pattern Generator 2 Output Value + PGV2: u1, + /// Pattern Generator 3 Output Value + PGV3: u1, + /// Pattern Generator 4 Output Value + PGV4: u1, + /// Pattern Generator 5 Output Value + PGV5: u1, + /// Pattern Generator 6 Output Value + PGV6: u1, + /// Pattern Generator 7 Output Value + PGV7: u1, + }), base_address + 0x38); + + /// address: 0x4300103c + /// Waveform Control + pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { + /// Waveform Generation + WAVEGEN: u3, + reserved0: u1, + /// Ramp Mode + RAMP: u2, + reserved1: u1, + /// Circular period Enable + CIPEREN: u1, + /// Circular Channel 0 Enable + CICCEN0: u1, + /// Circular Channel 1 Enable + CICCEN1: u1, + /// Circular Channel 2 Enable + CICCEN2: u1, + /// Circular Channel 3 Enable + CICCEN3: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Channel 0 Polarity + POL0: u1, + /// Channel 1 Polarity + POL1: u1, + /// Channel 2 Polarity + POL2: u1, + /// Channel 3 Polarity + POL3: u1, + /// Channel 4 Polarity + POL4: u1, + /// Channel 5 Polarity + POL5: u1, + reserved6: u1, + reserved7: u1, + /// Swap DTI Output Pair 0 + SWAP0: u1, + /// Swap DTI Output Pair 1 + SWAP1: u1, + /// Swap DTI Output Pair 2 + SWAP2: u1, + /// Swap DTI Output Pair 3 + SWAP3: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3c); + + /// address: 0x43001040 + /// Period + pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Period Value + PER: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Period Value + PER: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001040 + /// Period + pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Period Value + PER: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x40); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u4, + /// Channel Compare/Capture Value + CC: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u5, + /// Channel Compare/Capture Value + CC: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001044 + /// Compare and Capture + pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Cycle Number + DITHER: u6, + /// Channel Compare/Capture Value + CC: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x44); + + /// address: 0x43001064 + /// Pattern Buffer + pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { + /// Pattern Generator 0 Output Enable Buffer + PGEB0: u1, + /// Pattern Generator 1 Output Enable Buffer + PGEB1: u1, + /// Pattern Generator 2 Output Enable Buffer + PGEB2: u1, + /// Pattern Generator 3 Output Enable Buffer + PGEB3: u1, + /// Pattern Generator 4 Output Enable Buffer + PGEB4: u1, + /// Pattern Generator 5 Output Enable Buffer + PGEB5: u1, + /// Pattern Generator 6 Output Enable Buffer + PGEB6: u1, + /// Pattern Generator 7 Output Enable Buffer + PGEB7: u1, + /// Pattern Generator 0 Output Enable + PGVB0: u1, + /// Pattern Generator 1 Output Enable + PGVB1: u1, + /// Pattern Generator 2 Output Enable + PGVB2: u1, + /// Pattern Generator 3 Output Enable + PGVB3: u1, + /// Pattern Generator 4 Output Enable + PGVB4: u1, + /// Pattern Generator 5 Output Enable + PGVB5: u1, + /// Pattern Generator 6 Output Enable + PGVB6: u1, + /// Pattern Generator 7 Output Enable + PGVB7: u1, + }), base_address + 0x64); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u4, + /// Period Buffer Value + PERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Period Buffer Value + PERBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x4300106c + /// Period Buffer + pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Period Buffer Value + PERBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x6c); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Channel Compare/Capture Buffer Value + CCBUF: u4, + /// Dithering Buffer Cycle Number + DITHERBUF: u20, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u5, + /// Channel Compare/Capture Buffer Value + CCBUF: u19, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + + /// address: 0x43001070 + /// Compare and Capture Buffer + pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { + /// Dithering Buffer Cycle Number + DITHERBUF: u6, + /// Channel Compare/Capture Buffer Value + CCBUF: u18, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x70); + }; + + /// True Random Generator + pub const TRNG = struct { + pub const base_address = 0x42002800; + pub const version = "U22421.1.0"; + + /// address: 0x42002800 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Run in Standby + RUNSTDBY: u1, + padding0: u1, + }), base_address + 0x0); + + /// address: 0x42002804 + /// Event Control + pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Event Output + DATARDYEO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x42002808 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Enable + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x8); + + /// address: 0x42002809 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Enable + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x9); + + /// address: 0x4200280a + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Data Ready Interrupt Flag + DATARDY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xa); + + /// address: 0x42002820 + /// Output Data + pub const DATA = @intToPtr(*volatile u32, base_address + 0x20); + }; + + /// Universal Serial Bus + pub const USB = struct { + pub const base_address = 0x41000000; + pub const version = "U22221.2.0"; + + /// USB is Device + pub const DEVICE = struct { + /// address: 0x41000000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Run in Standby Mode + RUNSTDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Operating Mode + MODE: u1, + }), base_address + 0x0); + + /// address: 0x41000002 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41000003 + /// USB Quality Of Service + pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Configuration Quality of Service + CQOS: u2, + /// Data Quality of Service + DQOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3); + + /// address: 0x41000008 + /// DEVICE Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + /// Detach + DETACH: u1, + /// Upstream Resume + UPRSM: u1, + /// Speed Configuration + SPDCONF: u2, + /// No Reply + NREPLY: u1, + /// Test mode J + TSTJ: u1, + /// Test mode K + TSTK: u1, + /// Test packet mode + TSTPCKT: u1, + /// Specific Operational Mode + OPMODE2: u1, + /// Global NAK + GNAK: u1, + /// Link Power Management Handshake + LPMHDSK: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4100000a + /// DEVICE Device Address + pub const DADD = @intToPtr(*volatile Mmio(8, packed struct { + /// Device Address + DADD: u7, + /// Device Address Enable + ADDEN: u1, + }), base_address + 0xa); + + /// address: 0x4100000c + /// DEVICE Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// Speed Status + SPEED: u2, + reserved2: u1, + reserved3: u1, + /// USB Line State Status + LINESTATE: u2, + }), base_address + 0xc); + + /// address: 0x4100000d + /// Finite State Machine Status + pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Fine State Machine Status + FSMSTATE: u7, + padding0: u1, + }), base_address + 0xd); + + /// address: 0x41000010 + /// DEVICE Device Frame Number + pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { + /// Micro Frame Number + MFNUM: u3, + /// Frame Number + FNUM: u11, + reserved0: u1, + /// Frame Number CRC Error + FNCERR: u1, + }), base_address + 0x10); + + /// address: 0x41000014 + /// DEVICE Device Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend Interrupt Enable + SUSPEND: u1, + /// Micro Start of Frame Interrupt Enable in High Speed Mode + MSOF: u1, + /// Start Of Frame Interrupt Enable + SOF: u1, + /// End of Reset Interrupt Enable + EORST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// End Of Resume Interrupt Enable + EORSM: u1, + /// Upstream Resume Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Not Yet Interrupt Enable + LPMNYET: u1, + /// Link Power Management Suspend Interrupt Enable + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x41000018 + /// DEVICE Device Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend Interrupt Enable + SUSPEND: u1, + /// Micro Start of Frame Interrupt Enable in High Speed Mode + MSOF: u1, + /// Start Of Frame Interrupt Enable + SOF: u1, + /// End of Reset Interrupt Enable + EORST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// End Of Resume Interrupt Enable + EORSM: u1, + /// Upstream Resume Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Not Yet Interrupt Enable + LPMNYET: u1, + /// Link Power Management Suspend Interrupt Enable + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x4100001c + /// DEVICE Device Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + /// Suspend + SUSPEND: u1, + /// Micro Start of Frame in High Speed Mode + MSOF: u1, + /// Start Of Frame + SOF: u1, + /// End of Reset + EORST: u1, + /// Wake Up + WAKEUP: u1, + /// End Of Resume + EORSM: u1, + /// Upstream Resume + UPRSM: u1, + /// Ram Access + RAMACER: u1, + /// Link Power Management Not Yet + LPMNYET: u1, + /// Link Power Management Suspend + LPMSUSP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x41000020 + /// DEVICE End Point Interrupt Summary + pub const EPINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { + /// End Point 0 Interrupt + EPINT0: u1, + /// End Point 1 Interrupt + EPINT1: u1, + /// End Point 2 Interrupt + EPINT2: u1, + /// End Point 3 Interrupt + EPINT3: u1, + /// End Point 4 Interrupt + EPINT4: u1, + /// End Point 5 Interrupt + EPINT5: u1, + /// End Point 6 Interrupt + EPINT6: u1, + /// End Point 7 Interrupt + EPINT7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x41000024 + /// Descriptor Address + pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x41000028 + /// USB PAD Calibration + pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { + /// USB Pad Transp calibration + TRANSP: u5, + reserved0: u1, + /// USB Pad Transn calibration + TRANSN: u5, + reserved1: u1, + /// USB Pad Trim calibration + TRIM: u3, + padding0: u1, + }), base_address + 0x28); + }; + + /// USB is Host + pub const HOST = struct { + /// address: 0x41000000 + /// Control A + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset + SWRST: u1, + /// Enable + ENABLE: u1, + /// Run in Standby Mode + RUNSTDBY: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Operating Mode + MODE: u1, + }), base_address + 0x0); + + /// address: 0x41000002 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { + /// Software Reset Synchronization Busy + SWRST: u1, + /// Enable Synchronization Busy + ENABLE: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x2); + + /// address: 0x41000003 + /// USB Quality Of Service + pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Configuration Quality of Service + CQOS: u2, + /// Data Quality of Service + DQOS: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x3); + + /// address: 0x41000008 + /// HOST Control B + pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + /// Send USB Resume + RESUME: u1, + /// Speed Configuration for Host + SPDCONF: u2, + /// Auto Resume Enable + AUTORESUME: u1, + /// Test mode J + TSTJ: u1, + /// Test mode K + TSTK: u1, + reserved1: u1, + /// Start of Frame Generation Enable + SOFE: u1, + /// Send USB Reset + BUSRESET: u1, + /// VBUS is OK + VBUSOK: u1, + /// Send L1 Resume + L1RESUME: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x8); + + /// address: 0x4100000a + /// HOST Host Start Of Frame Control + pub const HSOFC = @intToPtr(*volatile Mmio(8, packed struct { + /// Frame Length Control + FLENC: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Frame Length Control Enable + FLENCE: u1, + }), base_address + 0xa); + + /// address: 0x4100000c + /// HOST Status + pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + reserved1: u1, + /// Speed Status + SPEED: u2, + reserved2: u1, + reserved3: u1, + /// USB Line State Status + LINESTATE: u2, + }), base_address + 0xc); + + /// address: 0x4100000d + /// Finite State Machine Status + pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { + /// Fine State Machine Status + FSMSTATE: u7, + padding0: u1, + }), base_address + 0xd); + + /// address: 0x41000010 + /// HOST Host Frame Number + pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { + /// Micro Frame Number + MFNUM: u3, + /// Frame Number + FNUM: u11, + padding0: u1, + padding1: u1, + }), base_address + 0x10); + + /// address: 0x41000012 + /// HOST Host Frame Length + pub const FLENHIGH = @intToPtr(*volatile u8, base_address + 0x12); + + /// address: 0x41000014 + /// HOST Host Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame Interrupt Disable + HSOF: u1, + /// BUS Reset Interrupt Disable + RST: u1, + /// Wake Up Interrupt Disable + WAKEUP: u1, + /// DownStream to Device Interrupt Disable + DNRSM: u1, + /// Upstream Resume from Device Interrupt Disable + UPRSM: u1, + /// Ram Access Interrupt Disable + RAMACER: u1, + /// Device Connection Interrupt Disable + DCONN: u1, + /// Device Disconnection Interrupt Disable + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x14); + + /// address: 0x41000018 + /// HOST Host Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame Interrupt Enable + HSOF: u1, + /// Bus Reset Interrupt Enable + RST: u1, + /// Wake Up Interrupt Enable + WAKEUP: u1, + /// DownStream to the Device Interrupt Enable + DNRSM: u1, + /// Upstream Resume fromthe device Interrupt Enable + UPRSM: u1, + /// Ram Access Interrupt Enable + RAMACER: u1, + /// Link Power Management Interrupt Enable + DCONN: u1, + /// Device Disconnection Interrupt Enable + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x18); + + /// address: 0x4100001c + /// HOST Host Interrupt Flag + pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { + reserved0: u1, + reserved1: u1, + /// Host Start Of Frame + HSOF: u1, + /// Bus Reset + RST: u1, + /// Wake Up + WAKEUP: u1, + /// Downstream + DNRSM: u1, + /// Upstream Resume from the Device + UPRSM: u1, + /// Ram Access + RAMACER: u1, + /// Device Connection + DCONN: u1, + /// Device Disconnection + DDISC: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x1c); + + /// address: 0x41000020 + /// HOST Pipe Interrupt Summary + pub const PINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { + /// Pipe 0 Interrupt + EPINT0: u1, + /// Pipe 1 Interrupt + EPINT1: u1, + /// Pipe 2 Interrupt + EPINT2: u1, + /// Pipe 3 Interrupt + EPINT3: u1, + /// Pipe 4 Interrupt + EPINT4: u1, + /// Pipe 5 Interrupt + EPINT5: u1, + /// Pipe 6 Interrupt + EPINT6: u1, + /// Pipe 7 Interrupt + EPINT7: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x20); + + /// address: 0x41000024 + /// Descriptor Address + pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x41000028 + /// USB PAD Calibration + pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { + /// USB Pad Transp calibration + TRANSP: u5, + reserved0: u1, + /// USB Pad Transn calibration + TRANSN: u5, + reserved1: u1, + /// USB Pad Trim calibration + TRIM: u3, + padding0: u1, + }), base_address + 0x28); + }; + }; + + /// Watchdog Timer + pub const WDT = struct { + pub const base_address = 0x40002000; + pub const version = "U22511.1.0"; + + /// address: 0x40002000 + /// Control + pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { + reserved0: u1, + /// Enable + ENABLE: u1, + /// Watchdog Timer Window Mode Enable + WEN: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Always-On + ALWAYSON: u1, + }), base_address + 0x0); + + /// address: 0x40002001 + /// Configuration + pub const CONFIG = @intToPtr(*volatile Mmio(8, packed struct { + /// Time-Out Period + PER: u4, + /// Window Mode Time-Out Period + WINDOW: u4, + }), base_address + 0x1); + + /// address: 0x40002002 + /// Early Warning Interrupt Control + pub const EWCTRL = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Time Offset + EWOFFSET: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + }), base_address + 0x2); + + /// address: 0x40002004 + /// Interrupt Enable Clear + pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Enable + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x4); + + /// address: 0x40002005 + /// Interrupt Enable Set + pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning Interrupt Enable + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x5); + + /// address: 0x40002006 + /// Interrupt Flag Status and Clear + pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { + /// Early Warning + EW: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x6); + + /// address: 0x40002008 + /// Synchronization Busy + pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Enable Synchronization Busy + ENABLE: u1, + /// Window Enable Synchronization Busy + WEN: u1, + /// Always-On Synchronization Busy + ALWAYSON: u1, + /// Clear Synchronization Busy + CLEAR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x8); + + /// address: 0x4000200c + /// Clear + pub const CLEAR = @intToPtr(*volatile u8, base_address + 0xc); + }; + + /// Core Debug Register + pub const CoreDebug = struct { + pub const base_address = 0xe000edf0; + + /// address: 0xe000edf0 + /// Debug Halting Control and Status Register + pub const DHCSR = @intToPtr(*volatile Mmio(32, packed struct { + C_DEBUGEN: u1, + C_HALT: u1, + C_STEP: u1, + C_MASKINTS: u1, + reserved0: u1, + C_SNAPSTALL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + S_REGRDY: u1, + S_HALT: u1, + S_SLEEP: u1, + S_LOCKUP: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + S_RETIRE_ST: u1, + S_RESET_ST: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0x0); + + /// address: 0xe000edf4 + /// Debug Core Register Selector Register + pub const DCRSR = @intToPtr(*volatile Mmio(32, packed struct { + REGSEL: u5, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + REGWnR: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + }), base_address + 0x4); + + /// address: 0xe000edf8 + /// Debug Core Register Data Register + pub const DCRDR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0xe000edfc + /// Debug Exception and Monitor Control Register + pub const DEMCR = @intToPtr(*volatile Mmio(32, packed struct { + VC_CORERESET: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + VC_MMERR: u1, + VC_NOCPERR: u1, + VC_CHKERR: u1, + VC_STATERR: u1, + VC_BUSERR: u1, + VC_INTERR: u1, + VC_HARDERR: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + MON_EN: u1, + MON_PEND: u1, + MON_STEP: u1, + MON_REQ: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + TRCENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0xc); + }; + + /// Data Watchpoint and Trace Register + pub const DWT = struct { + pub const base_address = 0xe0001000; + + /// address: 0xe0001000 + /// Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + CYCCNTENA: u1, + POSTPRESET: u4, + POSTINIT: u4, + CYCTAP: u1, + SYNCTAP: u2, + PCSAMPLENA: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + EXCTRCENA: u1, + CPIEVTENA: u1, + EXCEVTENA: u1, + SLEEPEVTENA: u1, + LSUEVTENA: u1, + FOLDEVTENA: u1, + CYCEVTENA: u1, + reserved3: u1, + NOPRFCNT: u1, + NOCYCCNT: u1, + NOEXTTRIG: u1, + NOTRCPKT: u1, + NUMCOMP: u4, + }), base_address + 0x0); + + /// address: 0xe0001004 + /// Cycle Count Register + pub const CYCCNT = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0001008 + /// CPI Count Register + pub const CPICNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); + + /// address: 0xe000100c + /// Exception Overhead Count Register + pub const EXCCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xc); + + /// address: 0xe0001010 + /// Sleep Count Register + pub const SLEEPCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); + + /// address: 0xe0001014 + /// LSU Count Register + pub const LSUCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x14); + + /// address: 0xe0001018 + /// Folded-instruction Count Register + pub const FOLDCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x18); + + /// address: 0xe000101c + /// Program Counter Sample Register + pub const PCSR = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0xe0001020 + /// Comparator Register 0 + pub const COMP0 = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0xe0001024 + /// Mask Register 0 + pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x24); + + /// address: 0xe0001028 + /// Function Register 0 + pub const FUNCTION0 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x28); + + /// address: 0xe0001030 + /// Comparator Register 1 + pub const COMP1 = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0xe0001034 + /// Mask Register 1 + pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x34); + + /// address: 0xe0001038 + /// Function Register 1 + pub const FUNCTION1 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x38); + + /// address: 0xe0001040 + /// Comparator Register 2 + pub const COMP2 = @intToPtr(*volatile u32, base_address + 0x40); + + /// address: 0xe0001044 + /// Mask Register 2 + pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x44); + + /// address: 0xe0001048 + /// Function Register 2 + pub const FUNCTION2 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x48); + + /// address: 0xe0001050 + /// Comparator Register 3 + pub const COMP3 = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0xe0001054 + /// Mask Register 3 + pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { + MASK: u5, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0x54); + + /// address: 0xe0001058 + /// Function Register 3 + pub const FUNCTION3 = @intToPtr(*volatile Mmio(32, packed struct { + FUNCTION: u4, + reserved0: u1, + EMITRANGE: u1, + reserved1: u1, + CYCMATCH: u1, + DATAVMATCH: u1, + LNK1ENA: u1, + DATAVSIZE: u2, + DATAVADDR0: u4, + DATAVADDR1: u4, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + MATCHED: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + }), base_address + 0x58); + }; + + /// Embedded Trace Macrocell + pub const ETM = struct { + pub const base_address = 0xe0041000; + + /// address: 0xe0041000 + /// ETM Main Control Register + pub const CR = @intToPtr(*volatile Mmio(32, packed struct { + /// ETM Power Down + ETMPD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Port Size bits 2:0 + PORTSIZE: u3, + /// Stall Processor + STALL: u1, + /// Branch Output + BROUT: u1, + /// Debug Request Control + DBGRQ: u1, + /// ETM Programming + PROG: u1, + /// ETM Port Select + PORTSEL: u1, + reserved3: u1, + /// Port Mode bit 2 + PORTMODE2: u1, + reserved4: u1, + reserved5: u1, + /// Port Mode bits 1:0 + PORTMODE: u2, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Port Size bit 3 + PORTSIZE3: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + /// TimeStamp Enable + TSEN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x0); + + /// address: 0xe0041004 + /// ETM Configuration Code Register + pub const CCR = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0041008 + /// ETM Trigger Event Register + pub const TRIGGER = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0xe0041010 + /// ETM Status Register + pub const SR = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0xe0041014 + /// ETM System Configuration Register + pub const SCR = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0xe0041020 + /// ETM TraceEnable Event Register + pub const TEEVR = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0xe0041024 + /// ETM TraceEnable Control 1 Register + pub const TECR1 = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0xe0041028 + /// ETM FIFO Full Level Register + pub const FFLR = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0xe0041140 + /// ETM Free-running Counter Reload Value + pub const CNTRLDVR1 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0xe00411e0 + /// ETM Synchronization Frequency Register + pub const SYNCFR = @intToPtr(*volatile u32, base_address + 0x1e0); + + /// address: 0xe00411e4 + /// ETM ID Register + pub const IDR = @intToPtr(*volatile u32, base_address + 0x1e4); + + /// address: 0xe00411e8 + /// ETM Configuration Code Extension Register + pub const CCER = @intToPtr(*volatile u32, base_address + 0x1e8); + + /// address: 0xe00411f0 + /// ETM TraceEnable Start/Stop EmbeddedICE Control Register + pub const TESSEICR = @intToPtr(*volatile u32, base_address + 0x1f0); + + /// address: 0xe00411f8 + /// ETM TimeStamp Event Register + pub const TSEVT = @intToPtr(*volatile u32, base_address + 0x1f8); + + /// address: 0xe0041200 + /// ETM CoreSight Trace ID Register + pub const TRACEIDR = @intToPtr(*volatile u32, base_address + 0x200); + + /// address: 0xe0041208 + /// ETM ID Register 2 + pub const IDR2 = @intToPtr(*volatile u32, base_address + 0x208); + + /// address: 0xe0041314 + /// ETM Device Power-Down Status Register + pub const PDSR = @intToPtr(*volatile u32, base_address + 0x314); + + /// address: 0xe0041ee0 + /// ETM Integration Test Miscellaneous Inputs + pub const ITMISCIN = @intToPtr(*volatile u32, base_address + 0xee0); + + /// address: 0xe0041ee8 + /// ETM Integration Test Trigger Out + pub const ITTRIGOUT = @intToPtr(*volatile u32, base_address + 0xee8); + + /// address: 0xe0041ef0 + /// ETM Integration Test ATB Control 2 + pub const ITATBCTR2 = @intToPtr(*volatile u32, base_address + 0xef0); + + /// address: 0xe0041ef8 + /// ETM Integration Test ATB Control 0 + pub const ITATBCTR0 = @intToPtr(*volatile u32, base_address + 0xef8); + + /// address: 0xe0041f00 + /// ETM Integration Mode Control Register + pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { + INTEGRATION: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xf00); + + /// address: 0xe0041fa0 + /// ETM Claim Tag Set Register + pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); + + /// address: 0xe0041fa4 + /// ETM Claim Tag Clear Register + pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); + + /// address: 0xe0041fb0 + /// ETM Lock Access Register + pub const LAR = @intToPtr(*volatile u32, base_address + 0xfb0); + + /// address: 0xe0041fb4 + /// ETM Lock Status Register + pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { + Present: u1, + Access: u1, + ByteAcc: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0xfb4); + + /// address: 0xe0041fb8 + /// ETM Authentication Status Register + pub const AUTHSTATUS = @intToPtr(*volatile u32, base_address + 0xfb8); + + /// address: 0xe0041fcc + /// ETM CoreSight Device Type Register + pub const DEVTYPE = @intToPtr(*volatile u32, base_address + 0xfcc); + + /// address: 0xe0041fd0 + /// ETM Peripheral Identification Register #4 + pub const PIDR4 = @intToPtr(*volatile u32, base_address + 0xfd0); + + /// address: 0xe0041fd4 + /// ETM Peripheral Identification Register #5 + pub const PIDR5 = @intToPtr(*volatile u32, base_address + 0xfd4); + + /// address: 0xe0041fd8 + /// ETM Peripheral Identification Register #6 + pub const PIDR6 = @intToPtr(*volatile u32, base_address + 0xfd8); + + /// address: 0xe0041fdc + /// ETM Peripheral Identification Register #7 + pub const PIDR7 = @intToPtr(*volatile u32, base_address + 0xfdc); + + /// address: 0xe0041fe0 + /// ETM Peripheral Identification Register #0 + pub const PIDR0 = @intToPtr(*volatile u32, base_address + 0xfe0); + + /// address: 0xe0041fe4 + /// ETM Peripheral Identification Register #1 + pub const PIDR1 = @intToPtr(*volatile u32, base_address + 0xfe4); + + /// address: 0xe0041fe8 + /// ETM Peripheral Identification Register #2 + pub const PIDR2 = @intToPtr(*volatile u32, base_address + 0xfe8); + + /// address: 0xe0041fec + /// ETM Peripheral Identification Register #3 + pub const PIDR3 = @intToPtr(*volatile u32, base_address + 0xfec); + + /// address: 0xe0041ff0 + /// ETM Component Identification Register #0 + pub const CIDR0 = @intToPtr(*volatile u32, base_address + 0xff0); + + /// address: 0xe0041ff4 + /// ETM Component Identification Register #1 + pub const CIDR1 = @intToPtr(*volatile u32, base_address + 0xff4); + + /// address: 0xe0041ff8 + /// ETM Component Identification Register #2 + pub const CIDR2 = @intToPtr(*volatile u32, base_address + 0xff8); + + /// address: 0xe0041ffc + /// ETM Component Identification Register #3 + pub const CIDR3 = @intToPtr(*volatile u32, base_address + 0xffc); + }; + + /// Floating Point Unit + pub const FPU = struct { + pub const base_address = 0xe000ef30; + + /// address: 0xe000ef34 + /// Floating-Point Context Control Register + pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { + LSPACT: u1, + USER: u1, + reserved0: u1, + THREAD: u1, + HFRDY: u1, + MMRDY: u1, + BFRDY: u1, + reserved1: u1, + MONRDY: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + LSPEN: u1, + ASPEN: u1, + }), base_address + 0x4); + + /// address: 0xe000ef38 + /// Floating-Point Context Address Register + pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + /// Address for FP registers in exception stack frame + ADDRESS: u29, + }), base_address + 0x8); + + /// address: 0xe000ef3c + /// Floating-Point Default Status Control Register + pub const FPDSCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + /// Default value for FPSCR.RMODE + RMODE: u2, + /// Default value for FPSCR.FZ + FZ: u1, + /// Default value for FPSCR.DN + DN: u1, + /// Default value for FPSCR.AHP + AHP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0xc); + + /// address: 0xe000ef40 + /// Media and FP Feature Register 0 + pub const MVFR0 = @intToPtr(*volatile Mmio(32, packed struct { + A_SIMD_registers: u4, + Single_precision: u4, + Double_precision: u4, + FP_excep_trapping: u4, + Divide: u4, + Square_root: u4, + Short_vectors: u4, + FP_rounding_modes: u4, + }), base_address + 0x10); + + /// address: 0xe000ef44 + /// Media and FP Feature Register 1 + pub const MVFR1 = @intToPtr(*volatile Mmio(32, packed struct { + FtZ_mode: u4, + D_NaN_mode: u4, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + FP_HPFP: u4, + FP_fused_MAC: u4, + }), base_address + 0x14); + }; + + /// Instrumentation Trace Macrocell + pub const ITM = struct { + pub const base_address = 0xe0000000; + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_WORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u32, + }), base_address + 0x0); + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_BYTE_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x0); + + /// address: 0xe0000000 + /// ITM Stimulus Port Registers + pub const PORT_HWORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { + PORT: u16, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + }), base_address + 0x0); + + /// address: 0xe0000e00 + /// ITM Trace Enable Register + pub const TER = @intToPtr(*volatile u32, base_address + 0xe00); + + /// address: 0xe0000e40 + /// ITM Trace Privilege Register + pub const TPR = @intToPtr(*volatile Mmio(32, packed struct { + PRIVMASK: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0xe40); + + /// address: 0xe0000e80 + /// ITM Trace Control Register + pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { + ITMENA: u1, + TSENA: u1, + SYNCENA: u1, + DWTENA: u1, + SWOENA: u1, + STALLENA: u1, + reserved0: u1, + reserved1: u1, + TSPrescale: u2, + GTSFREQ: u2, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + TraceBusID: u7, + BUSY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xe80); + + /// address: 0xe0000ef8 + /// ITM Integration Write Register + pub const IWR = @intToPtr(*volatile Mmio(32, packed struct { + ATVALIDM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef8); + + /// address: 0xe0000efc + /// ITM Integration Read Register + pub const IRR = @intToPtr(*volatile Mmio(32, packed struct { + ATREADYM: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xefc); + }; + + /// Memory Protection Unit + pub const MPU = struct { + pub const base_address = 0xe000ed90; + + /// address: 0xe000ed90 + /// MPU Type Register + pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { + /// Separate instruction and Data Memory MapsRegions + SEPARATE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Number of Data Regions + DREGION: u8, + /// Number of Instruction Regions + IREGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0x0); + + /// address: 0xe000ed94 + /// MPU Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// MPU Enable + ENABLE: u1, + /// Enable Hard Fault and NMI handlers + HFNMIENA: u1, + /// Enables privileged software access to default memory map + PRIVDEFENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + }), base_address + 0x4); + + /// address: 0xe000ed98 + /// MPU Region Number Register + pub const RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region referenced by RBAR and RASR + REGION: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0x8); + + /// address: 0xe000ed9c + /// MPU Region Base Address Register + pub const RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0xc); + + /// address: 0xe000eda0 + /// MPU Region Attribute and Size Register + pub const RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x10); + + /// address: 0xe000eda4 + /// MPU Alias 1 Region Base Address Register + pub const RBAR_A1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x14); + + /// address: 0xe000eda8 + /// MPU Alias 1 Region Attribute and Size Register + pub const RASR_A1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x18); + + /// address: 0xe000edac + /// MPU Alias 2 Region Base Address Register + pub const RBAR_A2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x1c); + + /// address: 0xe000edb0 + /// MPU Alias 2 Region Attribute and Size Register + pub const RASR_A2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x20); + + /// address: 0xe000edb4 + /// MPU Alias 3 Region Base Address Register + pub const RBAR_A3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region number + REGION: u4, + /// Region number valid + VALID: u1, + /// Region base address + ADDR: u27, + }), base_address + 0x24); + + /// address: 0xe000edb8 + /// MPU Alias 3 Region Attribute and Size Register + pub const RASR_A3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Region Enable + ENABLE: u1, + /// Region Size + SIZE: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Sub-region disable + SRD: u8, + /// Bufferable bit + B: u1, + /// Cacheable bit + C: u1, + /// Shareable bit + S: u1, + /// TEX bit + TEX: u3, + reserved6: u1, + reserved7: u1, + /// Access Permission + AP: u3, + reserved8: u1, + /// Execute Never Attribute + XN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + }), base_address + 0x28); + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = struct { + pub const base_address = 0xe000e100; + + /// address: 0xe000e100 + /// Interrupt Set Enable Register + pub const ISER = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt set enable bits + SETENA: u32, + }), base_address + 0x0); + + /// address: 0xe000e180 + /// Interrupt Clear Enable Register + pub const ICER = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt clear-enable bits + CLRENA: u32, + }), base_address + 0x80); + + /// address: 0xe000e200 + /// Interrupt Set Pending Register + pub const ISPR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt set-pending bits + SETPEND: u32, + }), base_address + 0x100); + + /// address: 0xe000e280 + /// Interrupt Clear Pending Register + pub const ICPR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt clear-pending bits + CLRPEND: u32, + }), base_address + 0x180); + + /// address: 0xe000e300 + /// Interrupt Active Bit Register + pub const IABR = @intToPtr(*volatile [5]Mmio(32, packed struct { + /// Interrupt active bits + ACTIVE: u32, + }), base_address + 0x200); + + /// address: 0xe000e400 + /// Interrupt Priority Register n + pub const IP = @intToPtr(*volatile [35]Mmio(8, packed struct { + /// Priority of interrupt n + PRI0: u3, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + }), base_address + 0x300); + + /// address: 0xe000ef00 + /// Software Trigger Interrupt Register + pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt ID to trigger + INTID: u9, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0xe00); + }; + + /// System timer + pub const SysTick = struct { + pub const base_address = 0xe000e010; + }; + + /// System Control Registers + pub const SystemControl = struct { + pub const base_address = 0xe000e000; + + /// address: 0xe000e004 + /// Interrupt Controller Type Register + pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct { + INTLINESNUM: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x4); + + /// address: 0xe000e008 + /// Auxiliary Control Register + pub const ACTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Disable interruption of LDM/STM instructions + DISMCYCINT: u1, + /// Disable wruite buffer use during default memory map accesses + DISDEFWBUF: u1, + /// Disable IT folding + DISFOLD: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Disable automatic update of CONTROL.FPCA + DISFPCA: u1, + /// Disable out-of-order FP instructions + DISOOFP: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0x8); + + /// address: 0xe000ed00 + /// CPUID Base Register + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Processor revision number + REVISION: u4, + /// Process Part Number, 0xC24=Cortex-M4 + PARTNO: u12, + /// Constant + CONSTANT: u4, + /// Variant number + VARIANT: u4, + /// Implementer code, 0x41=ARM + IMPLEMENTER: u8, + }), base_address + 0xd00); + + /// address: 0xe000ed04 + /// Interrupt Control and State Register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active exception number + VECTACTIVE: u9, + reserved0: u1, + reserved1: u1, + /// No preempted active exceptions to execute + RETTOBASE: u1, + /// Exception number of the highest priority pending enabled exception + VECTPENDING: u6, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + /// Interrupt pending flag + ISRPENDING: u1, + /// Debug only + ISRPREEMPT: u1, + reserved6: u1, + /// SysTick clear-pending bit + PENDSTCLR: u1, + /// SysTick set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved7: u1, + reserved8: u1, + /// NMI set-pending bit + NMIPENDSET: u1, + }), base_address + 0xd04); + + /// address: 0xe000ed08 + /// Vector Table Offset Register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Vector table base offset + TBLOFF: u25, + }), base_address + 0xd08); + + /// address: 0xe000ed0c + /// Application Interrupt and Reset Control Register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Must write 0 + VECTRESET: u1, + /// Must write 0 + VECTCLRACTIVE: u1, + /// System Reset Request + SYSRESETREQ: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + /// Interrupt priority grouping + PRIGROUP: u3, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + /// Data endianness, 0=little, 1=big + ENDIANNESS: u1, + /// Register key + VECTKEY: u16, + }), base_address + 0xd0c); + + /// address: 0xe000ed10 + /// System Control Register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// Sleep-on-exit on handler return + SLEEPONEXIT: u1, + /// Deep Sleep used as low power mode + SLEEPDEEP: u1, + reserved1: u1, + /// Send Event on Pending bit + SEVONPEND: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xd10); + + /// address: 0xe000ed14 + /// Configuration and Control Register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates how processor enters Thread mode + NONBASETHRDENA: u1, + /// Enables unprivileged software access to STIR register + USERSETMPEND: u1, + reserved0: u1, + /// Enables unaligned access traps + UNALIGN_TRP: u1, + /// Enables divide by 0 trap + DIV_0_TRP: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// Ignore LDM/STM BusFault for -1/-2 priority handlers + BFHFNMIGN: u1, + /// Indicates stack alignment on exception entry + STKALIGN: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + }), base_address + 0xd14); + + /// address: 0xe000ed18 + /// System Handler Priority Register 1 + pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Priority of system handler 4, MemManage + PRI_4: u8, + /// Priority of system handler 5, BusFault + PRI_5: u8, + /// Priority of system handler 6, UsageFault + PRI_6: u8, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xd18); + + /// address: 0xe000ed1c + /// System Handler Priority Register 2 + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + /// Priority of system handler 11, SVCall + PRI_11: u8, + }), base_address + 0xd1c); + + /// address: 0xe000ed20 + /// System Handler Priority Register 3 + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + /// Priority of system handler 14, PendSV + PRI_14: u8, + /// Priority of system handler 15, SysTick exception + PRI_15: u8, + }), base_address + 0xd20); + + /// address: 0xe000ed24 + /// System Handler Control and State Register + pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { + /// MemManage exception active bit + MEMFAULTACT: u1, + /// BusFault exception active bit + BUSFAULTACT: u1, + reserved0: u1, + /// UsageFault exception active bit + USGFAULTACT: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + /// SVCall active bit + SVCALLACT: u1, + /// DebugMonitor exception active bit + MONITORACT: u1, + reserved4: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// UsageFault exception pending bit + USGFAULTPENDED: u1, + /// MemManage exception pending bit + MEMFAULTPENDED: u1, + /// BusFault exception pending bit + BUSFAULTPENDED: u1, + /// SVCall pending bit + SVCALLPENDED: u1, + /// MemManage enable bit + MEMFAULTENA: u1, + /// BusFault enable bit + BUSFAULTENA: u1, + /// UsageFault enable bit + USGFAULTENA: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + }), base_address + 0xd24); + + /// address: 0xe000ed28 + /// Configurable Fault Status Register + pub const CFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Instruction access violation + IACCVIOL: u1, + /// Data access violation + DACCVIOL: u1, + reserved0: u1, + /// MemManage Fault on unstacking for exception return + MUNSTKERR: u1, + /// MemManage Fault on stacking for exception entry + MSTKERR: u1, + /// MemManager Fault occured during FP lazy state preservation + MLSPERR: u1, + reserved1: u1, + /// MemManage Fault Address Register valid + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// BusFault on unstacking for exception return + UNSTKERR: u1, + /// BusFault on stacking for exception entry + STKERR: u1, + /// BusFault occured during FP lazy state preservation + LSPERR: u1, + reserved2: u1, + /// BusFault Address Register valid + BFARVALID: u1, + /// Undefined instruction UsageFault + UNDEFINSTR: u1, + /// Invalid state UsageFault + INVSTATE: u1, + /// Invalid PC load UsageFault + INVPC: u1, + /// No coprocessor UsageFault + NOCP: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + /// Unaligned access UsageFault + UNALIGNED: u1, + /// Divide by zero UsageFault + DIVBYZERO: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + }), base_address + 0xd28); + + /// address: 0xe000ed2c + /// HardFault Status Register + pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + /// BusFault on a Vector Table read during exception processing + VECTTBL: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + reserved20: u1, + reserved21: u1, + reserved22: u1, + reserved23: u1, + reserved24: u1, + reserved25: u1, + reserved26: u1, + reserved27: u1, + reserved28: u1, + /// Forced Hard Fault + FORCED: u1, + /// Debug: always write 0 + DEBUGEVT: u1, + }), base_address + 0xd2c); + + /// address: 0xe000ed30 + /// Debug Fault Status Register + pub const DFSR = @intToPtr(*volatile Mmio(32, packed struct { + HALTED: u1, + BKPT: u1, + DWTTRAP: u1, + VCATCH: u1, + EXTERNAL: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + }), base_address + 0xd30); + + /// address: 0xe000ed34 + /// MemManage Fault Address Register + pub const MMFAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address that generated the MemManage fault + ADDRESS: u32, + }), base_address + 0xd34); + + /// address: 0xe000ed38 + /// BusFault Address Register + pub const BFAR = @intToPtr(*volatile Mmio(32, packed struct { + /// Address that generated the BusFault + ADDRESS: u32, + }), base_address + 0xd38); + + /// address: 0xe000ed3c + /// Auxiliary Fault Status Register + pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { + /// AUXFAULT input signals + IMPDEF: u32, + }), base_address + 0xd3c); + + /// address: 0xe000ed40 + /// Processor Feature Register + pub const PFR = @intToPtr(*volatile [2]u32, base_address + 0xd40); + + /// address: 0xe000ed48 + /// Debug Feature Register + pub const DFR = @intToPtr(*volatile u32, base_address + 0xd48); + + /// address: 0xe000ed4c + /// Auxiliary Feature Register + pub const ADR = @intToPtr(*volatile u32, base_address + 0xd4c); + + /// address: 0xe000ed50 + /// Memory Model Feature Register + pub const MMFR = @intToPtr(*volatile [4]u32, base_address + 0xd50); + + /// address: 0xe000ed60 + /// Instruction Set Attributes Register + pub const ISAR = @intToPtr(*volatile [5]u32, base_address + 0xd60); + + /// address: 0xe000ed88 + /// Coprocessor Access Control Register + pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + reserved7: u1, + reserved8: u1, + reserved9: u1, + reserved10: u1, + reserved11: u1, + reserved12: u1, + reserved13: u1, + reserved14: u1, + reserved15: u1, + reserved16: u1, + reserved17: u1, + reserved18: u1, + reserved19: u1, + /// Access privileges for coprocessor 10 + CP10: u2, + /// Access privileges for coprocessor 11 + CP11: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + }), base_address + 0xd88); + }; + + /// Trace Port Interface Register + pub const TPI = struct { + pub const base_address = 0xe0040000; + + /// address: 0xe0040000 + /// Supported Parallel Port Size Register + pub const SSPSR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0xe0040004 + /// Current Parallel Port Size Register + pub const CSPSR = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0xe0040010 + /// Asynchronous Clock Prescaler Register + pub const ACPR = @intToPtr(*volatile Mmio(32, packed struct { + PRESCALER: u13, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + }), base_address + 0x10); + + /// address: 0xe00400f0 + /// Selected Pin Protocol Register + pub const SPPR = @intToPtr(*volatile Mmio(32, packed struct { + TXMODE: u2, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + }), base_address + 0xf0); + + /// address: 0xe0040300 + /// Formatter and Flush Status Register + pub const FFSR = @intToPtr(*volatile Mmio(32, packed struct { + FlInProg: u1, + FtStopped: u1, + TCPresent: u1, + FtNonStop: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + }), base_address + 0x300); + + /// address: 0xe0040304 + /// Formatter and Flush Control Register + pub const FFCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1, + EnFCont: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + reserved4: u1, + reserved5: u1, + reserved6: u1, + TrigIn: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + }), base_address + 0x304); + + /// address: 0xe0040308 + /// Formatter Synchronization Counter Register + pub const FSCR = @intToPtr(*volatile u32, base_address + 0x308); + + /// address: 0xe0040ee8 + /// TRIGGER + pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xee8); + + /// address: 0xe0040eec + /// Integration ETM Data + pub const FIFO0 = @intToPtr(*volatile Mmio(32, packed struct { + ETM0: u8, + ETM1: u8, + ETM2: u8, + ETM_bytecount: u2, + ETM_ATVALID: u1, + ITM_bytecount: u2, + ITM_ATVALID: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xeec); + + /// address: 0xe0040ef0 + /// ITATBCTR2 + pub const ITATBCTR2 = @intToPtr(*volatile Mmio(32, packed struct { + ATREADY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef0); + + /// address: 0xe0040ef8 + /// ITATBCTR0 + pub const ITATBCTR0 = @intToPtr(*volatile Mmio(32, packed struct { + ATREADY: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xef8); + + /// address: 0xe0040efc + /// Integration ITM Data + pub const FIFO1 = @intToPtr(*volatile Mmio(32, packed struct { + ITM0: u8, + ITM1: u8, + ITM2: u8, + ETM_bytecount: u2, + ETM_ATVALID: u1, + ITM_bytecount: u2, + ITM_ATVALID: u1, + padding0: u1, + padding1: u1, + }), base_address + 0xefc); + + /// address: 0xe0040f00 + /// Integration Mode Control + pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { + Mode: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + padding24: u1, + padding25: u1, + padding26: u1, + padding27: u1, + padding28: u1, + padding29: u1, + padding30: u1, + }), base_address + 0xf00); + + /// address: 0xe0040fa0 + /// Claim tag set + pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); + + /// address: 0xe0040fa4 + /// Claim tag clear + pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); + + /// address: 0xe0040fc8 + /// TPIU_DEVID + pub const DEVID = @intToPtr(*volatile Mmio(32, packed struct { + NrTraceInput: u1, + reserved0: u1, + reserved1: u1, + reserved2: u1, + reserved3: u1, + AsynClkIn: u1, + MinBufSz: u3, + PTINVALID: u1, + MANCVALID: u1, + NRZVALID: u1, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + }), base_address + 0xfc8); + + /// address: 0xe0040fcc + /// TPIU_DEVTYPE + pub const DEVTYPE = @intToPtr(*volatile Mmio(32, packed struct { + SubType: u4, + MajorType: u4, + padding0: u1, + padding1: u1, + padding2: u1, + padding3: u1, + padding4: u1, + padding5: u1, + padding6: u1, + padding7: u1, + padding8: u1, + padding9: u1, + padding10: u1, + padding11: u1, + padding12: u1, + padding13: u1, + padding14: u1, + padding15: u1, + padding16: u1, + padding17: u1, + padding18: u1, + padding19: u1, + padding20: u1, + padding21: u1, + padding22: u1, + padding23: u1, + }), base_address + 0xfcc); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +pub const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; From fa46be8ea2381289aec32ca651b6a44fb5289aaa Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 23 Sep 2022 00:16:01 -0700 Subject: [PATCH 083/138] Revert "Revert "Add executable method (addOptions, addObjectFile) and fix recursive call in addIncludePath (#79)" (#81)" (#82) This reverts commit 4cc682cece7b4217261fec59d9c199a83ff8f90c. --- src/main.zig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/main.zig b/src/main.zig index 0f65b62..c4fa6e5 100644 --- a/src/main.zig +++ b/src/main.zig @@ -69,7 +69,7 @@ pub const EmbeddedExecutable = struct { } pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { - exe.addIncludePath(path); + exe.inner.addIncludePath(path); } pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { @@ -79,6 +79,15 @@ pub const EmbeddedExecutable = struct { pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { exe.inner.addCSourceFile(file, flags); } + + pub fn addOptions(exe: *EmbeddedExecutable, package_name: []const u8, options: *std.build.OptionsStep) void { + exe.inner.addOptions(package_name, options); + exe.addPackage(.{ .name = package_name, .source = options.getSource() }); + } + + pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { + exe.inner.addObjectFile(source_file); + } }; pub fn addEmbeddedExecutable( From 681b3b0d7a6b2fc5d0f8918c583c790c646a31f1 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 23 Sep 2022 00:26:14 -0700 Subject: [PATCH 084/138] added param to panic function (#83) --- src/core/microzig.zig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index d3decbe..0c9dc6d 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -86,7 +86,7 @@ else }; /// The microzig default panic handler. Will disable interrupts and loop endlessly. -pub fn microzig_panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace) noreturn { +pub fn microzig_panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace, _: ?usize) noreturn { // utilize logging functions std.log.err("microzig PANIC: {s}", .{message}); @@ -165,7 +165,7 @@ export fn microzig_main() noreturn { @compileError("The root source file must provide a public function main!"); const main = @field(app, "main"); - const info: std.builtin.TypeInfo = @typeInfo(@TypeOf(main)); + const info: std.builtin.Type = @typeInfo(@TypeOf(main)); const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; if (info != .Fn or info.Fn.args.len > 0) From 15bc1fc06da3b6c622a21fa438e40be247d9dee1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Mon, 3 Oct 2022 19:11:16 +0200 Subject: [PATCH 085/138] Much improves the panic function, now prints a stack trace more often. (#86) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- src/core/microzig.zig | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 0c9dc6d..76ff4b1 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -86,27 +86,27 @@ else }; /// The microzig default panic handler. Will disable interrupts and loop endlessly. -pub fn microzig_panic(message: []const u8, maybe_stack_trace: ?*std.builtin.StackTrace, _: ?usize) noreturn { +pub fn microzig_panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { // utilize logging functions std.log.err("microzig PANIC: {s}", .{message}); if (builtin.cpu.arch != .avr) { - var writer = debug.writer(); - writer.print("microzig PANIC: {s}\r\n", .{message}) catch unreachable; - - if (maybe_stack_trace) |stack_trace| { - var frame_index: usize = 0; - var frames_left: usize = std.math.min(stack_trace.index, stack_trace.instruction_addresses.len); - while (frames_left != 0) : ({ - frames_left -= 1; - frame_index = (frame_index + 1) % stack_trace.instruction_addresses.len; - }) { - const return_address = stack_trace.instruction_addresses[frame_index]; - writer.print("0x{X:0>8}\r\n", .{return_address}) catch unreachable; + var index: usize = 0; + var iter = std.debug.StackIterator.init(@returnAddress(), null); + while (iter.next()) |address| : (index += 1) { + if (index == 0) { + std.log.err("stack trace:", .{}); } + std.log.err("{d: >3}: 0x{X:0>8}", .{ index, address }); } } + if (@import("builtin").mode == .Debug) { + // attach a breakpoint, this might trigger another + // panic internally, so only do that in debug mode. + std.log.info("triggering breakpoint...", .{}); + @breakpoint(); + } hang(); } From 0d9721d9070c356f4ffaf6f4a312bccdb574b8a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sat, 8 Oct 2022 13:01:40 +0200 Subject: [PATCH 086/138] Adds microzig.initializeSystemMemories (#87) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- src/core/microzig.zig | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index 76ff4b1..c755315 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -200,3 +200,36 @@ export fn microzig_main() noreturn { // main returned, just hang around here a bit hang(); } + +/// Contains references to the microzig .data and .bss sections, also +/// contains the initial load address for .data if it is in flash. +pub const sections = struct { + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; +}; + +pub fn initializeSystemMemories() void { + @setCold(true); + + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, §ions.microzig_bss_start); + const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, §ions.microzig_data_start); + const data_end = @ptrCast([*]u8, §ions.microzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } +} From c5f68cae635af375cbc83ec1bc41a29364196ada Mon Sep 17 00:00:00 2001 From: hollmmax Date: Tue, 18 Oct 2022 14:50:50 +0200 Subject: [PATCH 087/138] add stm3240g-eval board (#84) --- src/modules/boards.zig | 6 ++++++ src/modules/boards/stm3240geval/stm3240geval.zig | 13 +++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 src/modules/boards/stm3240geval/stm3240geval.zig diff --git a/src/modules/boards.zig b/src/modules/boards.zig index db1fa75..bf0eba1 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -32,6 +32,12 @@ pub const stm32f4discovery = Board{ .chip = chips.stm32f407vg, }; +pub const stm3240geval = Board{ + .name = "STM3240GEVAL", + .path = root_path ++ "boards/stm3240geval/stm3240geval.zig", + .chip = chips.stm32f407vg, +}; + pub const stm32f429idiscovery = Board{ .name = "STM32F429IDISCOVERY", .path = root_path ++ "boards/stm32f429idiscovery/stm32f429idiscovery.zig", diff --git a/src/modules/boards/stm3240geval/stm3240geval.zig b/src/modules/boards/stm3240geval/stm3240geval.zig new file mode 100644 index 0000000..b78162a --- /dev/null +++ b/src/modules/boards/stm3240geval/stm3240geval.zig @@ -0,0 +1,13 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const pin_map = .{ + // LD1 green + .@"LD1" = "PG6", + // LD2 orange + .@"LD2" = "PG8", + // LD3 red + .@"LD3" = "PI9", + // LD4 blue + .@"LD4" = "PC7", +}; From 696c32ff0de75ca1a36c9e76fa4a33ead38cc16f Mon Sep 17 00:00:00 2001 From: Philipp Wendel <41269321+PhilippWendel@users.noreply.github.com> Date: Fri, 21 Oct 2022 08:42:42 +0200 Subject: [PATCH 088/138] add arduino uno board (#89) * Updated fn to return optional instead of error * Added Arduino Uno Board * Updated comments --- build.zig | 1 + src/modules/boards.zig | 6 ++++ .../boards/arduino-uno/arduino-uno.zig | 32 +++++++++++++++++++ src/modules/chips/atmega328p/atmega328p.zig | 2 +- tests/blinky.zig | 1 + tests/uart-sync.zig | 5 +++ 6 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 src/modules/boards/arduino-uno/arduino-uno.zig diff --git a/build.zig b/build.zig index c751dea..5107db3 100644 --- a/build.zig +++ b/build.zig @@ -17,6 +17,7 @@ pub fn build(b: *std.build.Builder) !void { const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true }; const all_backings = [_]BuildConfig{ BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, + BuildConfig{ .name = "boards.arduino_uno", .backing = Backing{ .board = boards.arduino_uno } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, diff --git a/src/modules/boards.zig b/src/modules/boards.zig index bf0eba1..be08b0c 100644 --- a/src/modules/boards.zig +++ b/src/modules/boards.zig @@ -14,6 +14,12 @@ pub const arduino_nano = Board{ .chip = chips.atmega328p, }; +pub const arduino_uno = Board{ + .name = "Arduino Uno", + .path = root_path ++ "boards/arduino-uno/arduino-uno.zig", + .chip = chips.atmega328p, +}; + pub const mbed_lpc1768 = Board{ .name = "mbed LPC1768", .path = root_path ++ "boards/mbed-lpc1768/mbed-lpc1768.zig", diff --git a/src/modules/boards/arduino-uno/arduino-uno.zig b/src/modules/boards/arduino-uno/arduino-uno.zig new file mode 100644 index 0000000..9dd729c --- /dev/null +++ b/src/modules/boards/arduino-uno/arduino-uno.zig @@ -0,0 +1,32 @@ +pub const chip = @import("chip"); + +pub const clock_frequencies = .{ + .cpu = 16_000_000, +}; + +pub const pin_map = .{ + // Port D + .D0 = "PD0", + .D1 = "PD1", + .D2 = "PD2", + .D3 = "PD3", + .D4 = "PD4", + .D5 = "PD5", + .D6 = "PD6", + .D7 = "PD7", + // Port B + .D8 = "PB0", + .D9 = "PB1", + .D10 = "PB2", + .D11 = "PB3", + .D12 = "PB4", + // LED_BUILTIN + .D13 = "PB5", + // Port C (Analog) + .A0 = "PC0", + .A1 = "PC1", + .A2 = "PC2", + .A3 = "PC3", + .A4 = "PC4", + .A5 = "PC5", +}; diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig index 0a24481..b836c65 100644 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ b/src/modules/chips/atmega328p/atmega328p.zig @@ -106,7 +106,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { const pclk = micro.clock.get().cpu; const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; - return std.math.cast(u12, divider) catch return error.UnsupportedBaudRate; + return std.math.cast(u12, divider) orelse return error.UnsupportedBaudRate; } fn computeBaudRate(divider: u12) u32 { diff --git a/tests/blinky.zig b/tests/blinky.zig index 4c3c2b1..d84cf96 100644 --- a/tests/blinky.zig +++ b/tests/blinky.zig @@ -4,6 +4,7 @@ const micro = @import("microzig"); const led_pin = if (micro.config.has_board) switch (micro.config.board_name) { .@"Arduino Nano" => micro.Pin("D13"), + .@"Arduino Uno" => micro.Pin("D13"), .@"mbed LPC1768" => micro.Pin("LED-1"), .@"STM32F3DISCOVERY" => micro.Pin("LD3"), .@"STM32F4DISCOVERY" => micro.Pin("LD5"), diff --git a/tests/uart-sync.zig b/tests/uart-sync.zig index 116bc44..019b328 100644 --- a/tests/uart-sync.zig +++ b/tests/uart-sync.zig @@ -23,6 +23,11 @@ const cfg = if (micro.config.has_board) .uart_idx = 1, .pins = .{ .tx = null, .rx = null }, }, + .@"Arduino Uno" => .{ + .led_pin = micro.Pin("D13"), + .uart_idx = 0, + .pins = .{}, + }, else => @compileError("unknown board"), } else switch (micro.config.chip_name) { From 248388d6e84d4fe92648aa39449a303ab980c022 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sun, 23 Oct 2022 13:55:09 +0200 Subject: [PATCH 089/138] Update README.adoc (#90) --- README.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index 2bf1f5c..8d093a4 100644 --- a/README.adoc +++ b/README.adoc @@ -50,7 +50,7 @@ pub fn build(b: *std.build.Builder) !void { // .chip = microzig.chips.atmega328p, }; - const exe = try microzig.addEmbeddedExecutable( + var exe = microzig.addEmbeddedExecutable( b, "my-executable", "src/main.zig", From 31070c1530b70a4d3631fdaa8f52f81171071f04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Thu, 10 Nov 2022 00:20:51 +0100 Subject: [PATCH 090/138] Makes executable files never stripped, we want that sweet debug info. Makes empty.zig less empty, so the compiler finds the file. (#91) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- src/core/empty.zig | 1 + src/main.zig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/core/empty.zig b/src/core/empty.zig index e69de29..8337712 100644 --- a/src/core/empty.zig +++ b/src/core/empty.zig @@ -0,0 +1 @@ +// diff --git a/src/main.zig b/src/main.zig index c4fa6e5..7781f25 100644 --- a/src/main.zig +++ b/src/main.zig @@ -182,6 +182,7 @@ pub fn addEmbeddedExecutable( }; exe.inner.use_stage1 = true; + exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) From 680b6282f30505d9531d4ca579aa35e23843bde2 Mon Sep 17 00:00:00 2001 From: Connor Rigby Date: Thu, 22 Dec 2022 14:05:31 -0800 Subject: [PATCH 091/138] stdlib: allow app to override the zig os layer (#93) --- src/core/microzig.zig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index c755315..cc3b7b5 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -48,6 +48,12 @@ pub const debug = @import("debug.zig"); pub const mmio = @import("mmio.zig"); +// Allow app to override the os API layer +pub const os = if (@hasDecl(app, "os")) + app.os +else + struct {}; + // Allow app to override the panic handler pub const panic = if (@hasDecl(app, "panic")) app.panic From 4f0d25220ec8f0501f8e0e9f6765689eb32faa5f Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 28 Dec 2022 12:50:50 -0800 Subject: [PATCH 092/138] catchup to self hosted (#96) --- build.zig | 6 +++--- src/core/gpio.zig | 2 +- src/core/microzig.zig | 18 ++++++++---------- src/main.zig | 1 - src/modules/chips/atmega328p/registers.zig | 4 ++-- src/modules/chips/lpc1768/registers.zig | 4 ++-- src/modules/chips/stm32f303/registers.zig | 4 ++-- src/modules/chips/stm32f407/registers.zig | 4 ++-- src/modules/chips/stm32f429/registers.zig | 4 ++-- 9 files changed, 22 insertions(+), 25 deletions(-) diff --git a/build.zig b/build.zig index 5107db3..86b4f48 100644 --- a/build.zig +++ b/build.zig @@ -16,10 +16,10 @@ pub fn build(b: *std.build.Builder) !void { const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true }; const all_backings = [_]BuildConfig{ - BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, - BuildConfig{ .name = "boards.arduino_uno", .backing = Backing{ .board = boards.arduino_uno } }, + //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, + //BuildConfig{ .name = "boards.arduino_uno", .backing = Backing{ .board = boards.arduino_uno } }, BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, - BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, + //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery } }, diff --git a/src/core/gpio.zig b/src/core/gpio.zig index 75089eb..3636eb9 100644 --- a/src/core/gpio.zig +++ b/src/core/gpio.zig @@ -30,7 +30,7 @@ pub const Direction = enum(u1) { output = 1, }; -pub fn Gpio(comptime pin: type, config: anytype) type { +pub fn Gpio(comptime pin: type, comptime config: anytype) type { const mode = @as(Mode, config.mode); const Generic = struct { // all pins: diff --git a/src/core/microzig.zig b/src/core/microzig.zig index cc3b7b5..b5325b7 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -69,16 +69,14 @@ else struct {}; // Conditionally export log() if the app has it defined. -usingnamespace if (@hasDecl(app, "log")) - struct { - pub const log = app.log; - } +pub const log = if (@hasDecl(app, "log")) + app.log else + // log is a no-op by default. Parts of microzig use the stdlib logging + // facility and compilations will now fail on freestanding systems that + // use it but do not explicitly set `root.log` struct { - // log is a no-op by default. Parts of microzig use the stdlib logging - // facility and compilations will now fail on freestanding systems that - // use it but do not explicitly set `root.log` - pub fn log( + fn log( comptime message_level: std.log.Level, comptime scope: @Type(.EnumLiteral), comptime format: []const u8, @@ -89,7 +87,7 @@ else _ = format; _ = args; } - }; + }.log; /// The microzig default panic handler. Will disable interrupts and loop endlessly. pub fn microzig_panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { @@ -174,7 +172,7 @@ export fn microzig_main() noreturn { const info: std.builtin.Type = @typeInfo(@TypeOf(main)); const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; - if (info != .Fn or info.Fn.args.len > 0) + if (info != .Fn or info.Fn.params.len > 0) @compileError(invalid_main_msg); const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); diff --git a/src/main.zig b/src/main.zig index 7781f25..289502f 100644 --- a/src/main.zig +++ b/src/main.zig @@ -181,7 +181,6 @@ pub fn addEmbeddedExecutable( .app_packages = std.ArrayList(Pkg).init(builder.allocator), }; - exe.inner.use_stage1 = true; exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded // might not be true for all machines (Pi Pico), but diff --git a/src/modules/chips/atmega328p/registers.zig b/src/modules/chips/atmega328p/registers.zig index 53e47b2..d43ad4f 100644 --- a/src/modules/chips/atmega328p/registers.zig +++ b/src/modules/chips/atmega328p/registers.zig @@ -1295,8 +1295,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm } pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, // Interrupt is not supported on arm }; diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig index 0cd697c..a30184d 100644 --- a/src/modules/chips/lpc1768/registers.zig +++ b/src/modules/chips/lpc1768/registers.zig @@ -18797,8 +18797,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm } pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, // Interrupt is not supported on arm }; diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig index a4bf055..4ce8ebe 100644 --- a/src/modules/chips/stm32f303/registers.zig +++ b/src/modules/chips/stm32f303/registers.zig @@ -34398,8 +34398,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm } pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, // Interrupt is not supported on arm }; diff --git a/src/modules/chips/stm32f407/registers.zig b/src/modules/chips/stm32f407/registers.zig index 2b24c31..9992f7f 100644 --- a/src/modules/chips/stm32f407/registers.zig +++ b/src/modules/chips/stm32f407/registers.zig @@ -52830,8 +52830,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm } pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, // Interrupt is not supported on arm }; diff --git a/src/modules/chips/stm32f429/registers.zig b/src/modules/chips/stm32f429/registers.zig index 077fcae..b6b5223 100644 --- a/src/modules/chips/stm32f429/registers.zig +++ b/src/modules/chips/stm32f429/registers.zig @@ -53872,8 +53872,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm } pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, // Interrupt is not supported on arm }; From db78794f010ce32aad18e11c2f59b8f7acc2b879 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Thu, 5 Jan 2023 11:48:00 +0100 Subject: [PATCH 093/138] Adds social media preview. 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zNZrsAL9qs}bifXcay$1B>9=h{6Shsf!M2GY*fs(6xXr64TH@xDTF+&cR|rm6*>p^I z#!bPgH?(ac(x%<8G+XS_nvgR%{o@IaR1gLAx`iWdY}@#rZ5xNOZQ~-gZNjs0n^#Y^ z$4zi5COBd4(lN804w{0~fU<4ko2H#z+EpZxfdD2rz4ru%8fZ<7(!vpiv~8S=wvETo zws8X5Ho?BQ&8w$+;%17|V?i-ZAt8toCyTIbGW*X2Ylswj)-t;fdC4P_aR|+%6KMS@ z`4QNJZn{2;QGtN5c_TGwHW3fjBbAjGkx$k{X0OFGUxX5rIY6$h4n9WLW`_U9Wr$oc zednrzDnwc8A$lHzJIM?A*7UCm)(5XqS!+E;zjjX`Ndp9eBjZ)UB??tz3z@fji5~>_ z4p8Mn3=u)+%-?6UmbkN@?g1q3wuR1M7m&{GeMT34nBox+=bhET*XS~yx%&*8#F@eO zGCP1>taHbL4X8oR#zn7xBml+u89+gaaDivtuAsENm}YYjVu z%GrAA8qejL64cAQ0Frq4LQl9Cf;tNog8neuA|B4WwITDvcfUc z3t%DW$*`4$)mftu^pWrk<7WWpITVAH)3ZY%s4Aw36?ov|6be>M2zp*Mi;?SA0|@G+ zR7}R<7ZYXI`m$=e20`6Y0YQbUZ8k+4^EKkZ`k#%8+2+;}hBVEhH~~=rx!J5FK+Ng_ zLDRg6Yo_l~R%NG|p^2RdLDOsr<{$Sqsx4{=f?E3$f_nK8AfP_TWz{GIjjc=G?xjOu z65|m&Z{io8*BXL;KM4XzJaG&Cik)*k{~`qaVd6tPocEg*t|i~`2tnh)_Yxj}g`j6u zwg literal 0 HcmV?d00001 From 1c3e04baa1847554d546a36cbef4c7d2866860d5 Mon Sep 17 00:00:00 2001 From: Aidan Oldershaw Date: Mon, 16 Jan 2023 10:38:49 -0800 Subject: [PATCH 094/138] Use `root.std_options` to override log behaviour (#99) ziglang/zig#14181 changed the interface for overriding the log function. Previously, you would define a public `root.log` function. Now, you define a `root.std_options` namespace that has a `logFn` decl. Signed-off-by: Aidan Oldershaw --- src/core/microzig.zig | 55 ++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/src/core/microzig.zig b/src/core/microzig.zig index b5325b7..fe7b648 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -48,6 +48,32 @@ pub const debug = @import("debug.zig"); pub const mmio = @import("mmio.zig"); +const options_override = if (@hasDecl(app, "std_options")) app.std_options else struct {}; +pub const std_options = struct { + pub usingnamespace options_override; + + // Conditionally provide a default no-op logFn if app does not have one + // defined. Parts of microzig use the stdlib logging facility and + // compilations will now fail on freestanding systems that use it but do + // not explicitly set `root.std_options.logFn` + pub usingnamespace if (!@hasDecl(options_override, "logFn")) + struct { + pub fn logFn( + comptime message_level: std.log.Level, + comptime scope: @Type(.EnumLiteral), + comptime format: []const u8, + args: anytype, + ) void { + _ = message_level; + _ = scope; + _ = format; + _ = args; + } + } + else + struct {}; +}; + // Allow app to override the os API layer pub const os = if (@hasDecl(app, "os")) app.os @@ -60,35 +86,6 @@ pub const panic = if (@hasDecl(app, "panic")) else microzig_panic; -// Conditionally export log_level if the app has it defined. -usingnamespace if (@hasDecl(app, "log_level")) - struct { - pub const log_level = app.log_level; - } -else - struct {}; - -// Conditionally export log() if the app has it defined. -pub const log = if (@hasDecl(app, "log")) - app.log -else - // log is a no-op by default. Parts of microzig use the stdlib logging - // facility and compilations will now fail on freestanding systems that - // use it but do not explicitly set `root.log` - struct { - fn log( - comptime message_level: std.log.Level, - comptime scope: @Type(.EnumLiteral), - comptime format: []const u8, - args: anytype, - ) void { - _ = message_level; - _ = scope; - _ = format; - _ = args; - } - }.log; - /// The microzig default panic handler. Will disable interrupts and loop endlessly. pub fn microzig_panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { From e1c1466d9ee0cc9e4e1303002fd00e88b0932434 Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Wed, 1 Feb 2023 18:54:37 +0100 Subject: [PATCH 095/138] Initial partial SPI support (#97) * build.zig: Trivial rename around UART test * mmio: Add writeRaw() to set a full register * UART: Add TODO for auto baud rate detection * STM32F30x Initial USART1 output/transmit support All code assumes default chip clock configuration. Code assumes STM32F303xB / STM32F3030xC. Code supports only 8 data bits, 1 stop bit. * stm32f3discovery @panic() to UART1 This is done by implementing `debugWrite()` for the board, which only initializes UART1 if that was not yet done, and flushes afterwards to make sure the host receives all. * stm32f303: Support UART1 reader This is done by implementing `rx()` and `canRead()`. * stm32f303 UART1 correctly support 7 and 8 bits This includes correctly masking the parity bit on reads. * stm32f3 UART1 support 0.5/1.5/2 stop bits * stm32f303 UART1 simplify parity code * stm32f303 I2C rough initial code Allows only writing and reading single bytes. * stm32f3 i2c: enable debug 'logging' * Add a few comments * I2C API changes, STM32F303 I2C multi-byte transfers Now using controller/device terminology, instead of master/slave. Now using 'transfer objects' to make STOPs and re-STARTs explicit, and allow using Writer and Reader APIs. Added 'register' abstraction. STM32F303 I2C now supports this new API, and multi-byte transfers. Now waiting for I2C_ISR.BUSY == 0, after setting I2C_CR2.STOP == 1. Without this, the sequence write-stop-write caused an additional STOP to be sent immediately the START and address of the second write. * Make work with regz-generated registers.zig change * Updated to match regz-generated update * After #23 repair Reset on stm32, lpc1768 * Clean-up I2C `readRegisters()`. * Refactor to separate read/write states * On STM32F303, make second read call fail Also doc comments to clarify the new API. * STM32 I2C: Properly support multiple write calls * I2C STM32: Fix release mode compile error ...on top of an earlier commit on this branch. * I2C Add 'write register' shorthand functions * Make sure vector_table is correctly exported It needs to be a non-`comptime` `var` for `@export` to work properly. The only 'documentation' for this behavior currently seems GitHub comment https://github.com/ziglang/zig/issues/5157#issuecomment-618933196 . This issue was introduced in 1c17304 for PR #27, which broke at least ARM-based STM32F303. * fix missing vector table on ARM * Revert "Merge branch 'fix-vector_table-export' into marnix-master" This reverts commit 8ea0a74e1031cd0b88abe0283f179f0cf20f450c, reversing changes made to 355a3618080d28c5da6e044773e6449989355fe5. * Temp commit for SPI * Check new I2C target_speed config setting * Corrected incorrect doc comment * Initial SPI transfer support for STM32F303 * SPI device CS pin is now used * Revert accidentally committed debug flag. * SPI: Add shorthands for 'register-based' devices. * Additional fix to remove PE3 pin dependency * SPI: Renames, comments, extracted device-specific code Specifically, top-level `Spi` is now `SpiBus`; and the internal API has an additional `switchToDevice()`, and receives `DeviceConfig` in more places. * SPI device: Add `transceive()` method. --------- Co-authored-by: Matt Knight --- src/core/microzig.zig | 3 + src/core/spi.zig | 146 ++++++++++++++++++++++ src/modules/chips/stm32f303/stm32f303.zig | 129 ++++++++++++++++++- 3 files changed, 277 insertions(+), 1 deletion(-) create mode 100644 src/core/spi.zig diff --git a/src/core/microzig.zig b/src/core/microzig.zig index fe7b648..5440e24 100644 --- a/src/core/microzig.zig +++ b/src/core/microzig.zig @@ -41,6 +41,9 @@ pub const Pin = pin.Pin; pub const uart = @import("uart.zig"); pub const Uart = uart.Uart; +pub const spi = @import("spi.zig"); +pub const SpiBus = spi.SpiBus; + pub const i2c = @import("i2c.zig"); pub const I2CController = i2c.I2CController; diff --git a/src/core/spi.zig b/src/core/spi.zig new file mode 100644 index 0000000..af8e3c5 --- /dev/null +++ b/src/core/spi.zig @@ -0,0 +1,146 @@ +const std = @import("std"); +const micro = @import("microzig.zig"); +const chip = @import("chip"); + +/// The SPI bus with the given environment-specific number. +/// Only 'master' mode is supported currently. +pub fn SpiBus(comptime index: usize) type { + const SystemSpi = chip.SpiBus(index); + + return struct { + /// A SPI 'slave' device, selected via the given CS pin. + /// (Default is CS=low to select.) + pub fn SpiDevice(comptime cs_pin: type, config: DeviceConfig) type { + return struct { + const SelfSpiDevice = @This(); + + internal: SystemSpi, + + /// A 'transfer' is defined as a sequence of reads/writes that require + /// the SPI device to be continuously enabled via its 'chip select' (CS) line. + const Transfer = struct { + const SelfTransfer = @This(); + + device: SelfSpiDevice, + + fn transceiveByte(self: *SelfTransfer, write_byte: u8, read_pointer: *u8) !void { + try self.device.internal.transceiveByte(write_byte, read_pointer); + } + + pub const Writer = std.io.Writer(*SelfTransfer, WriteError, writeSome); + + /// Return a standard Writer (which ignores the bytes read). + pub fn writer(self: *SelfTransfer) Writer { + return Writer{ .context = self }; + } + + fn writeSome(self: *SelfTransfer, buffer: []const u8) WriteError!usize { + try self.device.internal.writeAll(buffer); + return buffer.len; + } + + pub const Reader = std.io.Reader(*SelfTransfer, ReadError, readSome); + + /// Return a standard Reader (which writes arbitrary bytes). + pub fn reader(self: *SelfTransfer) Reader { + return Reader{ .context = self }; + } + + fn readSome(self: *SelfTransfer, buffer: []u8) ReadError!usize { + try self.device.internal.readInto(buffer); + return buffer.len; + } + + /// end the current transfer, releasing via the CS pin + pub fn end(self: *SelfTransfer) void { + self.device.internal.endTransfer(cs_pin, config); + } + }; + + /// start a new transfer, selecting using the CS pin + pub fn beginTransfer(self: SelfSpiDevice) !Transfer { + self.internal.switchToDevice(cs_pin, config); + self.internal.beginTransfer(cs_pin, config); + return Transfer{ .device = self }; + } + + pub fn transceive(self: SelfSpiDevice, write_buffer: []const u8, read_buffer: []u8) !void { + std.debug.assert(write_buffer.len == read_buffer.len); + var transfer = try self.beginTransfer(); + defer transfer.end(); + for (write_buffer) |_, i| { + try transfer.transceiveByte(write_buffer[i], &read_buffer[i]); + } + } + + /// Shorthand for 'register-based' devices + pub fn writeRegister(self: SelfSpiDevice, register_address: u8, byte: u8) ReadError!void { + try self.writeRegisters(register_address, &.{byte}); + } + + /// Shorthand for 'register-based' devices + pub fn writeRegisters(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { + var transfer = try self.beginTransfer(); + defer transfer.end(); + // write auto-increment, starting at given register + try transfer.writer().writeByte(0b01_000000 | register_address); + try transfer.writer().writeAll(buffer); + } + + /// Shorthand for 'register-based' devices + pub fn readRegister(self: SelfSpiDevice, register_address: u8) ReadError!u8 { + var buffer: [1]u8 = undefined; + try self.readRegisters(register_address, &buffer); + return buffer[0]; + } + + /// Shorthand for 'register-based' devices + pub fn readRegisters(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { + var transfer = try self.beginTransfer(); + defer transfer.end(); + // read auto-increment, starting at given register + try transfer.writer().writeByte(0b11_000000 | register_address); + try transfer.reader().readNoEof(buffer); + } + }; + } + + const SelfSpiBus = @This(); + + internal: SystemSpi, + + /// Initialize this SPI bus and return a handle to it. + pub fn init(config: BusConfig) InitError!SelfSpiBus { + micro.clock.ensure(); // TODO: Wat? + return SelfSpiBus{ + .internal = try SystemSpi.init(config), + }; + } + + /// Create (a descriptor for) a device on this SPI bus. + pub fn device(self: SelfSpiBus, comptime cs_pin: type, config: DeviceConfig) SpiDevice(cs_pin, config) { + return SpiDevice(cs_pin, config){ .internal = self.internal }; + } + }; +} + +/// A SPI bus configuration. +/// (There are no bus configuration options yet.) +pub const BusConfig = struct { + // Later: add common options +}; + +/// A SPI device configuration (excluding the CS pin). +/// (There are no device configuration options yet.) +pub const DeviceConfig = struct { + // TODO: add common options, like clock polarity and phase, and CS polarity +}; + +pub const InitError = error{ +// TODO: add common options +}; + +pub const WriteError = error{}; +pub const ReadError = error{ + EndOfStream, +}; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig index bb92d41..a4cfb53 100644 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ b/src/modules/chips/stm32f303/stm32f303.zig @@ -281,7 +281,6 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type regs.RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); regs.RCC.AHBENR.modify(.{ .IOPBEN = 1 }); debugPrint("I2C1 configuration step 1 complete\r\n", .{}); - // 2. Configure the I2C PINs for ALternate Functions // a) Select Alternate Function in MODER Register regs.GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 }); @@ -469,3 +468,131 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type }; }; } + +/// An STM32F303 SPI bus +pub fn SpiBus(comptime index: usize) type { + if (!(index == 1)) @compileError("TODO: only SPI1 is currently supported"); + + return struct { + const Self = @This(); + + /// Initialize and enable the bus. + pub fn init(config: micro.spi.BusConfig) !Self { + _ = config; // unused for now + + // CONFIGURE SPI1 + // connected to APB2, MCU pins PA5 + PA7 + PA6 = SPC + SDI + SDO, + // if GPIO port A is configured for alternate function 5 for these PA pins. + + // Enable the GPIO CLOCK + regs.RCC.AHBENR.modify(.{ .IOPAEN = 1 }); + + // Configure the I2C PINs for ALternate Functions + // - Select Alternate Function in MODER Register + regs.GPIOA.MODER.modify(.{ .MODER5 = 0b10, .MODER6 = 0b10, .MODER7 = 0b10 }); + // - Select High SPEED for the PINs + regs.GPIOA.OSPEEDR.modify(.{ .OSPEEDR5 = 0b11, .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); + // - Configure the Alternate Function in AFR Register + regs.GPIOA.AFRL.modify(.{ .AFRL5 = 5, .AFRL6 = 5, .AFRL7 = 5 }); + + // Enable the SPI1 CLOCK + regs.RCC.APB2ENR.modify(.{ .SPI1EN = 1 }); + + regs.SPI1.CR1.modify(.{ + .MSTR = 1, + .SSM = 1, + .SSI = 1, + .RXONLY = 0, + .SPE = 1, + }); + // the following configuration is assumed in `transceiveByte()` + regs.SPI1.CR2.raw = 0; + regs.SPI1.CR2.modify(.{ + .DS = 0b0111, // 8-bit data frames, seems default via '0b0000 is interpreted as 0b0111' + .FRXTH = 1, // RXNE event after 1 byte received + }); + + return Self{}; + } + + /// Switch this SPI bus to the given device. + pub fn switchToDevice(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + + regs.SPI1.CR1.modify(.{ + .CPOL = 1, // TODO: make configurable + .CPHA = 1, // TODO: make configurable + .BR = 0b111, // 1/256 the of PCLK TODO: make configurable + .LSBFIRST = 0, // MSB first TODO: make configurable + }); + gpio.setOutput(cs_pin); + } + + /// Begin a transfer to the given device. (Assumes `switchToDevice()` was called.) + pub fn beginTransfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + gpio.write(cs_pin, .low); // select the given device, TODO: support inverse CS devices + debugPrint("enabled SPI1\r\n", .{}); + } + + /// The basic operation in the current simplistic implementation: + /// send+receive a single byte. + /// Writing `null` writes an arbitrary byte (`undefined`), and + /// reading into `null` ignores the value received. + pub fn transceiveByte(_: Self, optional_write_byte: ?u8, optional_read_pointer: ?*u8) !void { + + // SPIx_DR's least significant byte is `@bitCast([dr_byte_size]u8, ...)[0]` + const dr_byte_size = @sizeOf(@TypeOf(regs.SPI1.DR.raw)); + + // wait unril ready for write + while (regs.SPI1.SR.read().TXE == 0) { + debugPrint("SPI1 TXE == 0\r\n", .{}); + } + debugPrint("SPI1 TXE == 1\r\n", .{}); + + // write + const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value + @bitCast([dr_byte_size]u8, regs.SPI1.DR.*)[0] = write_byte; + debugPrint("Sent: {X:2}.\r\n", .{write_byte}); + + // wait until read processed + while (regs.SPI1.SR.read().RXNE == 0) { + debugPrint("SPI1 RXNE == 0\r\n", .{}); + } + debugPrint("SPI1 RXNE == 1\r\n", .{}); + + // read + var data_read = regs.SPI1.DR.raw; + _ = regs.SPI1.SR.read(); // clear overrun flag + const dr_lsb = @bitCast([dr_byte_size]u8, data_read)[0]; + debugPrint("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read }); + if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb; + } + + /// Write all given bytes on the bus, not reading anything back. + pub fn writeAll(self: Self, bytes: []const u8) !void { + for (bytes) |b| { + try self.transceiveByte(b, null); + } + } + + /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`). + pub fn readInto(self: Self, buffer: []u8) !void { + for (buffer) |_, i| { + try self.transceiveByte(null, &buffer[i]); + } + } + + pub fn endTransfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + // no delay should be needed here, since we know SPIx_SR's TXE is 1 + debugPrint("(disabling SPI1)\r\n", .{}); + gpio.write(cs_pin, .high); // deselect the given device, TODO: support inverse CS devices + // HACK: wait long enough to make any device end an ongoing transfer + var i: u8 = 255; // with the default clock, this seems to delay ~185 microseconds + while (i > 0) : (i -= 1) { + asm volatile ("nop"); + } + } + }; +} From e63558330b06095cd359bd69bfa655628364ebce Mon Sep 17 00:00:00 2001 From: Philipp Wendel <41269321+PhilippWendel@users.noreply.github.com> Date: Mon, 6 Feb 2023 12:36:45 +0100 Subject: [PATCH 096/138] Catchup to changes introduced by ziglang/zig#14498 (#101) --- .github/workflows/build.yml | 2 +- build.zig | 8 +++++--- src/main.zig | 8 ++------ 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4ddce88..1026e82 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -29,4 +29,4 @@ jobs: version: master - name: Build tests - run: zig build -Drelease-small + run: zig build -Doptimize=ReleaseSmall diff --git a/build.zig b/build.zig index 86b4f48..304c3d7 100644 --- a/build.zig +++ b/build.zig @@ -10,7 +10,10 @@ const chips = microzig.chips; const Backing = microzig.Backing; pub fn build(b: *std.build.Builder) !void { - const mode = b.standardReleaseOptions(); + // Standard optimization options allow the person running `zig build -Doptimize=...` to select + // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall. Here we do not + // set a preferred release mode, allowing the user to decide how to optimize. + const optimize = b.standardOptimizeOption(.{}); const test_step = b.step("test", "Builds and runs the library test suite"); @@ -52,11 +55,10 @@ pub fn build(b: *std.build.Builder) !void { b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }), tst.source, cfg.backing, - .{}, + .{.optimize = optimize }, ); if (filter == null or exe.inner.target.cpu_arch.? == filter.?) { - exe.inner.setBuildMode(mode); exe.inner.install(); test_step.dependOn(&exe.inner.step); diff --git a/src/main.zig b/src/main.zig index 289502f..ff4c6f9 100644 --- a/src/main.zig +++ b/src/main.zig @@ -32,6 +32,7 @@ pub const BuildOptions = struct { // a hal package is a package with ergonomic wrappers for registers for a // given mcu, it's only dependency can be microzig hal_package_path: ?std.build.FileSource = null, + optimize: std.builtin.OptimizeMode = std.builtin.OptimizeMode.Debug, }; pub const EmbeddedExecutable = struct { @@ -56,10 +57,6 @@ pub const EmbeddedExecutable = struct { }); } - pub fn setBuildMode(exe: *EmbeddedExecutable, mode: std.builtin.Mode) void { - exe.inner.setBuildMode(mode); - } - pub fn install(exe: *EmbeddedExecutable) void { exe.inner.install(); } @@ -177,7 +174,7 @@ pub fn addEmbeddedExecutable( }; var exe = EmbeddedExecutable{ - .inner = builder.addExecutable(name, root_path ++ "core/microzig.zig"), + .inner = builder.addExecutable(.{ .name = name, .root_source_file = .{ .path = root_path ++ "core/microzig.zig" }, .target = chip.cpu.target, .optimize = options.optimize }), .app_packages = std.ArrayList(Pkg).init(builder.allocator), }; @@ -186,7 +183,6 @@ pub fn addEmbeddedExecutable( // might not be true for all machines (Pi Pico), but // for the HAL it's true (it doesn't know the concept of threading) exe.inner.single_threaded = true; - exe.inner.setTarget(chip.cpu.target); const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); From 9ccde9ff371b355394f65eacb6b51c5880768505 Mon Sep 17 00:00:00 2001 From: Vesim Date: Sun, 12 Feb 2023 15:58:29 +0100 Subject: [PATCH 097/138] Update to latest zig with modules (#102) --- build.zig | 16 +- .../{import-package.zig => import-module.zig} | 0 src/main.zig | 155 +++++++++--------- 3 files changed, 92 insertions(+), 79 deletions(-) rename src/core/{import-package.zig => import-module.zig} (100%) diff --git a/build.zig b/build.zig index 304c3d7..21e990a 100644 --- a/build.zig +++ b/build.zig @@ -3,11 +3,14 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); -const microzig = @import("src/main.zig"); -const boards = microzig.boards; -const chips = microzig.chips; -const Backing = microzig.Backing; +pub const microzig = @import("src/main.zig"); + +// alias for packages +pub const addEmbeddedExecutable = microzig.addEmbeddedExecutable; +pub const boards = microzig.boards; +pub const chips = microzig.chips; +pub const Backing = microzig.Backing; pub fn build(b: *std.build.Builder) !void { // Standard optimization options allow the person running `zig build -Doptimize=...` to select @@ -50,13 +53,14 @@ pub fn build(b: *std.build.Builder) !void { if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue; if (!tst.on_riscv32) continue; - const exe = microzig.addEmbeddedExecutable( + var exe = microzig.addEmbeddedExecutable( b, b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }), tst.source, cfg.backing, - .{.optimize = optimize }, + .{ .optimize = optimize }, ); + exe.addDriver(microzig.drivers.button); if (filter == null or exe.inner.target.cpu_arch.? == filter.?) { exe.inner.install(); diff --git a/src/core/import-package.zig b/src/core/import-module.zig similarity index 100% rename from src/core/import-package.zig rename to src/core/import-module.zig diff --git a/src/main.zig b/src/main.zig index ff4c6f9..80713c5 100644 --- a/src/main.zig +++ b/src/main.zig @@ -22,39 +22,46 @@ pub const Backing = union(enum) { } }; -const Pkg = std.build.Pkg; +const Module = std.build.Module; const root_path = root() ++ "/"; fn root() []const u8 { return std.fs.path.dirname(@src().file) orelse unreachable; } pub const BuildOptions = struct { - // a hal package is a package with ergonomic wrappers for registers for a + // a hal module is a module with ergonomic wrappers for registers for a // given mcu, it's only dependency can be microzig - hal_package_path: ?std.build.FileSource = null, + hal_module_path: ?std.build.FileSource = null, optimize: std.builtin.OptimizeMode = std.builtin.OptimizeMode.Debug, }; pub const EmbeddedExecutable = struct { inner: *LibExeObjStep, - app_packages: std.ArrayList(Pkg), - pub fn addPackage(exe: *EmbeddedExecutable, pkg: Pkg) void { - exe.app_packages.append(pkg) catch @panic("failed to append"); - - for (exe.inner.packages.items) |*entry| { - if (std.mem.eql(u8, "app", entry.name)) { - entry.dependencies = exe.app_packages.items; - break; - } - } else @panic("app package not found"); + pub fn addModule(exe: *EmbeddedExecutable, name: []const u8, module: *Module) void { + exe.inner.addModule(name, module); } - pub fn addPackagePath(exe: *EmbeddedExecutable, name: []const u8, pkg_index_path: []const u8) void { - exe.addPackage(Pkg{ - .name = exe.inner.builder.allocator.dupe(u8, name) catch unreachable, - .source = .{ .path = exe.inner.builder.allocator.dupe(u8, pkg_index_path) catch unreachable }, + pub fn addDriver(exe: *EmbeddedExecutable, driver: Driver) void { + var dependencies = std.ArrayList(std.Build.ModuleDependency).init(exe.inner.builder.allocator); + + for (driver.dependencies) |dep| { + dependencies.append(.{ + .name = dep, + .module = exe.inner.builder.modules.get(dep).?, + }) catch @panic("OOM"); + } + + // TODO: this is not perfect but should work for now + exe.inner.addAnonymousModule(driver.name, .{ + .source_file = driver.source_file, + .dependencies = dependencies.toOwnedSlice() catch @panic("OOM"), }); + + const app_module = exe.inner.modules.get("app").?; + const driver_module = exe.inner.modules.get(driver.name).?; + + app_module.dependencies.put(driver.name, driver_module) catch @panic("OOM"); } pub fn install(exe: *EmbeddedExecutable) void { @@ -77,9 +84,8 @@ pub const EmbeddedExecutable = struct { exe.inner.addCSourceFile(file, flags); } - pub fn addOptions(exe: *EmbeddedExecutable, package_name: []const u8, options: *std.build.OptionsStep) void { - exe.inner.addOptions(package_name, options); - exe.addPackage(.{ .name = package_name, .source = options.getSource() }); + pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *std.build.OptionsStep) void { + exe.inner.addOptions(module_name, options); } pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { @@ -156,26 +162,32 @@ pub fn addEmbeddedExecutable( writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; } - const config_pkg = Pkg{ - .name = "microzig-config", - .source = .{ .path = config_file_name }, - }; + builder.addModule(.{ + .name = "microzig", + .source_file = .{ .path = root_path ++ "core/import-module.zig" }, + }); + const microzig = builder.modules.get("microzig").?; - const chip_pkg = Pkg{ - .name = "chip", - .source = .{ .path = chip.path }, - .dependencies = &.{pkgs.microzig}, - }; + const config_module = builder.createModule(.{ + .source_file = .{ .path = config_file_name }, + }); - const cpu_pkg = Pkg{ - .name = "cpu", - .source = .{ .path = chip.cpu.path }, - .dependencies = &.{pkgs.microzig}, - }; + const chip_module = builder.createModule(.{ + .source_file = .{ .path = chip.path }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig }, + }, + }); + + const cpu_module = builder.createModule(.{ + .source_file = .{ .path = chip.cpu.path }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig }, + }, + }); var exe = EmbeddedExecutable{ .inner = builder.addExecutable(.{ .name = name, .root_source_file = .{ .path = root_path ++ "core/microzig.zig" }, .target = chip.cpu.target, .optimize = options.optimize }), - .app_packages = std.ArrayList(Pkg).init(builder.allocator), }; exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded @@ -188,67 +200,64 @@ pub fn addEmbeddedExecutable( exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); // TODO: - // - Generate the linker scripts from the "chip" or "board" package instead of using hardcoded ones. + // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now - // these packages will be re-exported from core/microzig.zig - exe.inner.addPackage(config_pkg); - exe.inner.addPackage(chip_pkg); - exe.inner.addPackage(cpu_pkg); + // these modules will be re-exported from core/microzig.zig + exe.inner.addModule("microzig-config", config_module); + exe.inner.addModule("chip", chip_module); + exe.inner.addModule("cpu", cpu_module); - exe.inner.addPackage(.{ - .name = "hal", - .source = if (options.hal_package_path) |hal_package_path| - hal_package_path + exe.inner.addModule("hal", builder.createModule(.{ + .source_file = if (options.hal_module_path) |hal_module_path| + hal_module_path else .{ .path = root_path ++ "core/empty.zig" }, - .dependencies = &.{pkgs.microzig}, - }); + .dependencies = &.{ + .{ .name = "microzig", .module = microzig }, + }, + })); switch (backing) { .board => |board| { - exe.inner.addPackage(std.build.Pkg{ - .name = "board", - .source = .{ .path = board.path }, - .dependencies = &.{pkgs.microzig}, - }); + exe.inner.addModule("board", builder.createModule(.{ + .source_file = .{ .path = board.path }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig }, + }, + })); }, else => {}, } - exe.inner.addPackage(.{ - .name = "app", - .source = .{ .path = source }, - }); - exe.addPackage(pkgs.microzig); + exe.inner.addModule("app", builder.createModule(.{ + .source_file = .{ .path = source }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig }, + }, + })); return exe; } -pub const pkgs = struct { - const mmio = std.build.Pkg{ - .name = "microzig-mmio", - .source = .{ .path = root_path ++ "core/mmio.zig" }, - }; - - pub const microzig = std.build.Pkg{ - .name = "microzig", - .source = .{ .path = root_path ++ "core/import-package.zig" }, - }; +pub const Driver = struct { + name: []const u8, + source_file: std.build.FileSource, + dependencies: []const []const u8, }; -/// Generic purpose drivers shipped with microzig +// Generic purpose drivers shipped with microzig pub const drivers = struct { - pub const quadrature = std.build.Pkg{ + pub const quadrature = Driver{ .name = "microzig.quadrature", - .source = .{ .path = root_path ++ "drivers/quadrature.zig" }, - .dependencies = &.{pkgs.microzig}, + .source_file = .{ .path = root_path ++ "drivers/quadrature.zig" }, + .dependencies = &.{"microzig"}, }; - pub const button = std.build.Pkg{ + pub const button = Driver{ .name = "microzig.button", - .source = .{ .path = root_path ++ "drivers/button.zig" }, - .dependencies = &.{pkgs.microzig}, + .source_file = .{ .path = root_path ++ "drivers/button.zig" }, + .dependencies = &.{"microzig"}, }; }; From 97ca5497da0f22d025e18bced9311efed088d893 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 11:25:38 -0500 Subject: [PATCH 098/138] Regz rewrite (#103) * wip * remove tools * reorganized * move hardware into their own repos * snake_case * use FileSource for board/chip/cpu descriptors * are_globally_enabled -> globally_enabled * rearrange --- build.zig | 63 +- src/core.zig | 1 + src/core/empty.zig | 1 - src/core/experimental.zig | 12 + src/core/{ => experimental}/clock.zig | 2 +- src/core/{ => experimental}/debug.zig | 10 +- src/core/{ => experimental}/gpio.zig | 26 +- src/core/{ => experimental}/i2c.zig | 24 +- src/core/{ => experimental}/pin.zig | 15 +- src/core/{ => experimental}/spi.zig | 22 +- src/core/{ => experimental}/uart.zig | 16 +- src/core/import-module.zig | 2 +- src/drivers.zig | 1 + src/drivers/experimental.zig | 7 + src/drivers/{ => experimental}/button.zig | 4 +- src/drivers/{ => experimental}/quadrature.zig | 0 src/{core/interrupts.zig => interrupt.zig} | 23 +- src/main.zig | 94 +- src/{core => }/microzig.zig | 40 +- src/{core => }/mmio.zig | 18 +- src/modules/Board.zig | 3 +- src/modules/Chip.zig | 39 +- src/modules/Cpu.zig | 2 +- src/modules/LinkerScriptStep.zig | 4 +- src/modules/boards.zig | 57 - .../boards/arduino-nano/arduino-nano.zig | 33 - .../boards/arduino-uno/arduino-uno.zig | 32 - .../boards/longan-nano/longan-nano.zig | 112 - .../boards/mbed-lpc1768/mbed-lpc1768.zig | 84 - .../boards/stm3240geval/stm3240geval.zig | 13 - .../stm32f3discovery/stm32f3discovery.zig | 38 - .../stm32f429idiscovery.zig | 15 - .../stm32f4discovery/stm32f4discovery.zig | 17 - src/modules/chips.zig | 116 - src/modules/chips/atmega328p/atmega328p.zig | 191 - src/modules/chips/atmega328p/registers.zig | 1309 - .../chips/atsame51j20a/ATSAME51J20A.svd | 45092 ------------- .../chips/atsame51j20a/atsame51j20a.zig | 333 - src/modules/chips/atsame51j20a/registers.zig | 25436 -------- src/modules/chips/gd32vf103/gd32vf103.zig | 114 - src/modules/chips/gd32vf103/registers.zig | 24637 ------- src/modules/chips/lpc1768/lpc1768.zig | 205 - src/modules/chips/lpc1768/registers.zig | 18811 ------ src/modules/chips/nrf52/nrf52.zig | 3 - src/modules/chips/nrf52/registers.zig | 16816 ----- src/modules/chips/stm32f103/registers.zig | 23820 ------- src/modules/chips/stm32f103/stm32f103.zig | 2 - src/modules/chips/stm32f303/registers.zig | 34412 ---------- src/modules/chips/stm32f303/stm32f303.zig | 598 - src/modules/chips/stm32f407/registers.zig | 52844 --------------- src/modules/chips/stm32f407/stm32f407.zig | 625 - src/modules/chips/stm32f429/registers.zig | 53886 ---------------- src/modules/chips/stm32f429/stm32f429.zig | 94 - src/modules/cpus.zig | 30 +- src/modules/cpus/{avr => }/avr5.zig | 2 +- src/modules/cpus/{cortex-m => }/cortex-m.zig | 10 +- src/modules/cpus/{rv32-imac => }/riscv32.zig | 4 +- src/tools/README.md | 10 - src/tools/svd2zig.py | 410 - test/README.adoc | 3 + {tests => test/programs}/blinky.zig | 0 {tests => test/programs}/interrupt.zig | 0 {tests => test/programs}/minimal.zig | 0 {tests => test/programs}/uart-sync.zig | 0 64 files changed, 226 insertions(+), 300417 deletions(-) create mode 100644 src/core.zig create mode 100644 src/core/experimental.zig rename src/core/{ => experimental}/clock.zig (98%) rename src/core/{ => experimental}/debug.zig (72%) rename src/core/{ => experimental}/gpio.zig (87%) rename src/core/{ => experimental}/i2c.zig (86%) rename src/core/{ => experimental}/pin.zig (79%) rename src/core/{ => experimental}/spi.zig (86%) rename src/core/{ => experimental}/uart.zig (88%) create mode 100644 src/drivers.zig create mode 100644 src/drivers/experimental.zig rename src/drivers/{ => experimental}/button.zig (95%) rename src/drivers/{ => experimental}/quadrature.zig (100%) rename src/{core/interrupts.zig => interrupt.zig} (74%) rename src/{core => }/microzig.zig (91%) rename src/{core => }/mmio.zig (74%) delete mode 100644 src/modules/boards.zig delete mode 100644 src/modules/boards/arduino-nano/arduino-nano.zig delete mode 100644 src/modules/boards/arduino-uno/arduino-uno.zig delete mode 100644 src/modules/boards/longan-nano/longan-nano.zig delete mode 100644 src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig delete mode 100644 src/modules/boards/stm3240geval/stm3240geval.zig delete mode 100644 src/modules/boards/stm32f3discovery/stm32f3discovery.zig delete mode 100644 src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig delete mode 100644 src/modules/boards/stm32f4discovery/stm32f4discovery.zig delete mode 100644 src/modules/chips.zig delete mode 100644 src/modules/chips/atmega328p/atmega328p.zig delete mode 100644 src/modules/chips/atmega328p/registers.zig delete mode 100644 src/modules/chips/atsame51j20a/ATSAME51J20A.svd delete mode 100644 src/modules/chips/atsame51j20a/atsame51j20a.zig delete mode 100644 src/modules/chips/atsame51j20a/registers.zig delete mode 100644 src/modules/chips/gd32vf103/gd32vf103.zig delete mode 100644 src/modules/chips/gd32vf103/registers.zig delete mode 100644 src/modules/chips/lpc1768/lpc1768.zig delete mode 100644 src/modules/chips/lpc1768/registers.zig delete mode 100644 src/modules/chips/nrf52/nrf52.zig delete mode 100644 src/modules/chips/nrf52/registers.zig delete mode 100644 src/modules/chips/stm32f103/registers.zig delete mode 100644 src/modules/chips/stm32f103/stm32f103.zig delete mode 100644 src/modules/chips/stm32f303/registers.zig delete mode 100644 src/modules/chips/stm32f303/stm32f303.zig delete mode 100644 src/modules/chips/stm32f407/registers.zig delete mode 100644 src/modules/chips/stm32f407/stm32f407.zig delete mode 100644 src/modules/chips/stm32f429/registers.zig delete mode 100644 src/modules/chips/stm32f429/stm32f429.zig rename src/modules/cpus/{avr => }/avr5.zig (98%) rename src/modules/cpus/{cortex-m => }/cortex-m.zig (95%) rename src/modules/cpus/{rv32-imac => }/riscv32.zig (99%) delete mode 100644 src/tools/README.md delete mode 100755 src/tools/svd2zig.py create mode 100644 test/README.adoc rename {tests => test/programs}/blinky.zig (100%) rename {tests => test/programs}/interrupt.zig (100%) rename {tests => test/programs}/minimal.zig (100%) rename {tests => test/programs}/uart-sync.zig (100%) diff --git a/build.zig b/build.zig index 21e990a..75b7de7 100644 --- a/build.zig +++ b/build.zig @@ -9,71 +9,12 @@ pub const microzig = @import("src/main.zig"); // alias for packages pub const addEmbeddedExecutable = microzig.addEmbeddedExecutable; pub const boards = microzig.boards; -pub const chips = microzig.chips; pub const Backing = microzig.Backing; pub fn build(b: *std.build.Builder) !void { - // Standard optimization options allow the person running `zig build -Doptimize=...` to select - // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall. Here we do not - // set a preferred release mode, allowing the user to decide how to optimize. const optimize = b.standardOptimizeOption(.{}); - const test_step = b.step("test", "Builds and runs the library test suite"); - const BuildConfig = struct { name: []const u8, backing: Backing, supports_uart_test: bool = true }; - const all_backings = [_]BuildConfig{ - //BuildConfig{ .name = "boards.arduino_nano", .backing = Backing{ .board = boards.arduino_nano } }, - //BuildConfig{ .name = "boards.arduino_uno", .backing = Backing{ .board = boards.arduino_uno } }, - BuildConfig{ .name = "boards.mbed_lpc1768", .backing = Backing{ .board = boards.mbed_lpc1768 } }, - //BuildConfig{ .name = "chips.atmega328p", .backing = Backing{ .chip = chips.atmega328p } }, - BuildConfig{ .name = "chips.lpc1768", .backing = Backing{ .chip = chips.lpc1768 } }, - //BuildConfig{ .name = "chips.stm32f103x8", .backing = Backing{ .chip = chips.stm32f103x8 } }, - BuildConfig{ .name = "boards.stm32f3discovery", .backing = Backing{ .board = boards.stm32f3discovery } }, - BuildConfig{ .name = "boards.stm32f4discovery", .backing = Backing{ .board = boards.stm32f4discovery } }, - BuildConfig{ .name = "boards.stm32f429idiscovery", .backing = Backing{ .board = boards.stm32f429idiscovery }, .supports_uart_test = false }, - BuildConfig{ .name = "chips.gd32vf103x8", .backing = Backing{ .chip = chips.gd32vf103x8 } }, - BuildConfig{ .name = "boards.longan_nano", .backing = Backing{ .board = boards.longan_nano } }, - }; - - const Test = struct { name: []const u8, source: []const u8, uses_uart: bool = false, on_riscv32: bool = true, on_avr: bool = true }; - const all_tests = [_]Test{ - Test{ .name = "minimal", .source = "tests/minimal.zig" }, - Test{ .name = "blinky", .source = "tests/blinky.zig" }, - Test{ .name = "uart-sync", .source = "tests/uart-sync.zig", .uses_uart = true, .on_avr = false }, - - // Note: this example uses the systick interrupt and therefore only for arm microcontrollers - Test{ .name = "interrupt", .source = "tests/interrupt.zig", .on_riscv32 = false, .on_avr = true }, - }; - - const filter = b.option(std.Target.Cpu.Arch, "filter-target", "Filters for a certain cpu target"); - - for (all_backings) |cfg| { - for (all_tests) |tst| { - if (tst.uses_uart and !cfg.supports_uart_test) continue; - if ((cfg.backing.getTarget().cpu_arch.?) == .avr and tst.on_avr == false) continue; - if (!tst.on_riscv32) continue; - - var exe = microzig.addEmbeddedExecutable( - b, - b.fmt("test-{s}-{s}.elf", .{ tst.name, cfg.name }), - tst.source, - cfg.backing, - .{ .optimize = optimize }, - ); - exe.addDriver(microzig.drivers.button); - - if (filter == null or exe.inner.target.cpu_arch.? == filter.?) { - exe.inner.install(); - - test_step.dependOn(&exe.inner.step); - - const bin = b.addInstallRaw( - exe.inner, - b.fmt("test-{s}-{s}.bin", .{ tst.name, cfg.name }), - .{}, - ); - b.getInstallStep().dependOn(&bin.step); - } - } - } + _ = optimize; + _ = test_step; } diff --git a/src/core.zig b/src/core.zig new file mode 100644 index 0000000..c4b9cdd --- /dev/null +++ b/src/core.zig @@ -0,0 +1 @@ +pub const experimental = @import("core/experimental.zig"); diff --git a/src/core/empty.zig b/src/core/empty.zig index 8337712..e69de29 100644 --- a/src/core/empty.zig +++ b/src/core/empty.zig @@ -1 +0,0 @@ -// diff --git a/src/core/experimental.zig b/src/core/experimental.zig new file mode 100644 index 0000000..e0058f8 --- /dev/null +++ b/src/core/experimental.zig @@ -0,0 +1,12 @@ +//! These are experimental generic interfaces. We want to see more use and +//! discussion of them before committing them to microzig's "official" API. +//! +//! They are bound to have breaking changes in the future, or even disappear, +//! so use at your own risk. +pub const clock = @import("experimental/clock.zig"); +pub const debug = @import("experimental/debug.zig"); +pub const gpio = @import("experimental/gpio.zig"); +pub const i2c = @import("experimental/i2c.zig"); +pub const Pin = @import("experimental/pin.zig").Pin; +pub const spi = @import("experimental/spi.zig"); +pub const uart = @import("experimental/uart.zig"); diff --git a/src/core/clock.zig b/src/core/experimental/clock.zig similarity index 98% rename from src/core/clock.zig rename to src/core/experimental/clock.zig index 71056bd..f0d5df2 100644 --- a/src/core/clock.zig +++ b/src/core/experimental/clock.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); /// An enumeration of clock sources. diff --git a/src/core/debug.zig b/src/core/experimental/debug.zig similarity index 72% rename from src/core/debug.zig rename to src/core/experimental/debug.zig index 8f27bb3..e3cee22 100644 --- a/src/core/debug.zig +++ b/src/core/experimental/debug.zig @@ -1,7 +1,7 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); -pub fn busySleep(comptime limit: comptime_int) void { +pub fn busy_sleep(comptime limit: comptime_int) void { if (limit <= 0) @compileError("limit must be non-negative!"); comptime var bits = 0; @@ -18,13 +18,13 @@ pub fn busySleep(comptime limit: comptime_int) void { } const DebugErr = error{}; -fn writerWrite(ctx: void, string: []const u8) DebugErr!usize { +fn writer_write(ctx: void, string: []const u8) DebugErr!usize { _ = ctx; write(string); return string.len; } -const DebugWriter = std.io.Writer(void, DebugErr, writerWrite); +const DebugWriter = std.io.Writer(void, DebugErr, writer_write); pub fn write(string: []const u8) void { if (!micro.config.has_board) @@ -32,7 +32,7 @@ pub fn write(string: []const u8) void { if (!@hasDecl(micro.board, "debugWrite")) return; - micro.board.debugWrite(string); + micro.board.debug_write(string); } pub fn writer() DebugWriter { diff --git a/src/core/gpio.zig b/src/core/experimental/gpio.zig similarity index 87% rename from src/core/gpio.zig rename to src/core/experimental/gpio.zig index 3636eb9..552bdde 100644 --- a/src/core/gpio.zig +++ b/src/core/experimental/gpio.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); pub const Mode = enum { @@ -37,12 +37,12 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { fn init() void { switch (mode) { .input, .generic, .input_output => { - setDirection(.input, undefined); + set_direction(.input, undefined); }, .output => { if (comptime !@hasField(@TypeOf(config), "initial_state")) @compileError("An output pin requires initial_state to be either .high or .low"); - setDirection(.output, switch (config.initial_state) { + set_direction(.output, switch (config.initial_state) { .low => State.low, .high => State.high, else => @compileError("An output pin requires initial_state to be either .high or .low"), @@ -51,8 +51,8 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { .open_drain => { if (comptime !@hasField(@TypeOf(config), "initial_state")) @compileError("An open_drain pin requires initial_state to be either .floating or .driven"); - setDirection(.input, undefined); - setDrive(switch (config.initial_state) { + set_direction(.input, undefined); + set_drive(switch (config.initial_state) { .floating => Drive.disabled, .driven => Drive.enabled, else => @compileError("An open_drain pin requires initial_state to be either .floating or .driven"), @@ -61,7 +61,7 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { .alternate_function => { if (comptime @hasDecl(chip.gpio, "AlternateFunction")) { const alternate_function = @as(chip.gpio.AlternateFunction, config.alternate_function); - setAlternateFunction(alternate_function); + set_alternate_function(alternate_function); } else { @compileError("Alternate Function not supported yet"); } @@ -78,10 +78,10 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { chip.gpio.write(pin.source_pin, state); } - fn setToHigh() void { + fn set_to_high() void { write(.high); } - fn setToLow() void { + fn set_to_low() void { write(.low); } fn toggle() void { @@ -96,7 +96,7 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { } // bi-di: - fn setDirection(dir: Direction, output_state: State) void { + fn set_direction(dir: Direction, output_state: State) void { switch (dir) { .output => { chip.gpio.setOutput(pin.source_pin); @@ -105,7 +105,7 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { .input => chip.gpio.setInput(pin.source_pin), } } - fn getDirection() Direction { + fn get_direction() Direction { if (chip.gpio.isOutput(pin.source_pin)) { return .output; } else { @@ -114,16 +114,16 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { } // open drain - fn setDrive(drive: Drive) void { + fn set_drive(drive: Drive) void { _ = drive; @compileError("open drain not implemented yet!"); } - fn getDrive() Drive { + fn get_drive() Drive { @compileError("open drain not implemented yet!"); } // alternate function - fn setAlternateFunction(af: chip.gpio.AlternateFunction) void { + fn set_alternate_function(af: chip.gpio.AlternateFunction) void { chip.gpio.setAlternateFunction(pin.source_pin, af); } }; diff --git a/src/core/i2c.zig b/src/core/experimental/i2c.zig similarity index 86% rename from src/core/i2c.zig rename to src/core/experimental/i2c.zig index 2aa89f6..20b0f61 100644 --- a/src/core/i2c.zig +++ b/src/core/experimental/i2c.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); pub fn I2CController(comptime index: usize, comptime pins: Pins) type { @@ -19,7 +19,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { state: SystemI2CController.ReadState, - pub const Reader = std.io.Reader(*Self, ReadError, readSome); + pub const Reader = std.io.Reader(*Self, ReadError, read_some); /// NOTE that some platforms, notably most (all?) STM32 microcontrollers, /// allow only a single read call per transfer. @@ -27,7 +27,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { return Reader{ .context = self }; } - fn readSome(self: *Self, buffer: []u8) ReadError!usize { + fn read_some(self: *Self, buffer: []u8) ReadError!usize { try self.state.readNoEof(buffer); return buffer.len; } @@ -40,7 +40,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// RESTART to a new transfer, invalidating this object. /// Note that some platforms set the repeated START condition /// on the first read or write call. - pub fn restartTransfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { + pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { return Transfer(direction){ .state = try self.state.restartTransfer(new_direction) }; } }, @@ -49,7 +49,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { state: SystemI2CController.WriteState, - pub const Writer = std.io.Writer(*Self, WriteError, writeSome); + pub const Writer = std.io.Writer(*Self, WriteError, write_some); /// NOTE that some platforms, notably most (all?) STM32 microcontrollers, /// will not immediately write all bytes, but postpone that @@ -58,7 +58,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { return Writer{ .context = self }; } - fn writeSome(self: *Self, buffer: []const u8) WriteError!usize { + fn write_some(self: *Self, buffer: []const u8) WriteError!usize { try self.state.writeAll(buffer); return buffer.len; } @@ -71,7 +71,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// RESTART to a new transfer, invalidating this object. /// Note that some platforms set the repeated START condition /// on the first read or write call. - pub fn restartTransfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { + pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { return switch (new_direction) { .read => Transfer(new_direction){ .state = try self.state.restartRead() }, .write => Transfer(new_direction){ .state = try self.state.restartWrite() }, @@ -84,7 +84,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// START a new transfer. /// Note that some platforms set the START condition /// on the first read or write call. - pub fn startTransfer(self: Device, comptime direction: Direction) !Transfer(direction) { + pub fn start_transfer(self: Device, comptime direction: Direction) !Transfer(direction) { return switch (direction) { .read => Transfer(direction){ .state = try SystemI2CController.ReadState.start(self.address) }, .write => Transfer(direction){ .state = try SystemI2CController.WriteState.start(self.address) }, @@ -92,12 +92,12 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { } /// Shorthand for 'register-based' devices - pub fn writeRegister(self: Device, register_address: u8, byte: u8) ReadError!void { + pub fn write_register(self: Device, register_address: u8, byte: u8) ReadError!void { try self.writeRegisters(register_address, &.{byte}); } /// Shorthand for 'register-based' devices - pub fn writeRegisters(self: Device, register_address: u8, buffer: []u8) ReadError!void { + pub fn write_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void { var wt = try self.startTransfer(.write); defer wt.stop() catch {}; try wt.writer().writeByte(register_address); @@ -105,14 +105,14 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { } /// Shorthand for 'register-based' devices - pub fn readRegister(self: Device, register_address: u8) ReadError!u8 { + pub fn read_register(self: Device, register_address: u8) ReadError!u8 { var buffer: [1]u8 = undefined; try self.readRegisters(register_address, &buffer); return buffer[0]; } /// Shorthand for 'register-based' devices - pub fn readRegisters(self: Device, register_address: u8, buffer: []u8) ReadError!void { + pub fn read_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void { var rt = write_and_restart: { var wt = try self.startTransfer(.write); errdefer wt.stop() catch {}; diff --git a/src/core/pin.zig b/src/core/experimental/pin.zig similarity index 79% rename from src/core/pin.zig rename to src/core/experimental/pin.zig index 5fccbaf..ae049e9 100644 --- a/src/core/pin.zig +++ b/src/core/experimental/pin.zig @@ -1,7 +1,8 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); const board = @import("board"); +const hal = @import("hal"); /// Returns a type that will manage the Pin defined by `spec`. /// Spec is either the pin as named in the datasheet of the chip @@ -17,15 +18,15 @@ pub fn Pin(comptime spec: []const u8) type { const chip_namespace = "chip:"; // Pins can be namespaced with "board:" for board and "chip:" for chip - // These namespaces are not passed to chip.parsePin + // These namespaces are not passed to hal.parse_pin() const pin = if (std.mem.startsWith(u8, spec, board_namespace)) - chip.parsePin(@field(board.pin_map, spec[board_namespace.len..])) + hal.parse_pin(@field(board.pin_map, spec[board_namespace.len..])) else if (std.mem.startsWith(u8, spec, chip_namespace)) - chip.parsePin(spec[chip_namespace.len..]) + hal.parse_pin(spec[chip_namespace.len..]) else if (micro.config.has_board and @hasField(@TypeOf(board.pin_map), spec)) - chip.parsePin(@field(board.pin_map, spec)) + hal.parse_pin(@field(board.pin_map, spec)) else - chip.parsePin(spec); + hal.parse_pin(spec); return struct { pub const name = if (std.mem.startsWith(u8, spec, board_namespace)) @@ -40,7 +41,7 @@ pub fn Pin(comptime spec: []const u8) type { pub const source_pin = pin; pub fn route(target: pin.Targets) void { - chip.routePin(source_pin, target); + hal.route_pin(source_pin, target); } }; } diff --git a/src/core/spi.zig b/src/core/experimental/spi.zig similarity index 86% rename from src/core/spi.zig rename to src/core/experimental/spi.zig index af8e3c5..e5d9ad3 100644 --- a/src/core/spi.zig +++ b/src/core/experimental/spi.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); /// The SPI bus with the given environment-specific number. @@ -23,30 +23,30 @@ pub fn SpiBus(comptime index: usize) type { device: SelfSpiDevice, - fn transceiveByte(self: *SelfTransfer, write_byte: u8, read_pointer: *u8) !void { + fn transceive_byte(self: *SelfTransfer, write_byte: u8, read_pointer: *u8) !void { try self.device.internal.transceiveByte(write_byte, read_pointer); } - pub const Writer = std.io.Writer(*SelfTransfer, WriteError, writeSome); + pub const Writer = std.io.Writer(*SelfTransfer, WriteError, write_some); /// Return a standard Writer (which ignores the bytes read). pub fn writer(self: *SelfTransfer) Writer { return Writer{ .context = self }; } - fn writeSome(self: *SelfTransfer, buffer: []const u8) WriteError!usize { + fn write_some(self: *SelfTransfer, buffer: []const u8) WriteError!usize { try self.device.internal.writeAll(buffer); return buffer.len; } - pub const Reader = std.io.Reader(*SelfTransfer, ReadError, readSome); + pub const Reader = std.io.Reader(*SelfTransfer, ReadError, read_some); /// Return a standard Reader (which writes arbitrary bytes). pub fn reader(self: *SelfTransfer) Reader { return Reader{ .context = self }; } - fn readSome(self: *SelfTransfer, buffer: []u8) ReadError!usize { + fn read_some(self: *SelfTransfer, buffer: []u8) ReadError!usize { try self.device.internal.readInto(buffer); return buffer.len; } @@ -58,7 +58,7 @@ pub fn SpiBus(comptime index: usize) type { }; /// start a new transfer, selecting using the CS pin - pub fn beginTransfer(self: SelfSpiDevice) !Transfer { + pub fn begin_transfer(self: SelfSpiDevice) !Transfer { self.internal.switchToDevice(cs_pin, config); self.internal.beginTransfer(cs_pin, config); return Transfer{ .device = self }; @@ -74,12 +74,12 @@ pub fn SpiBus(comptime index: usize) type { } /// Shorthand for 'register-based' devices - pub fn writeRegister(self: SelfSpiDevice, register_address: u8, byte: u8) ReadError!void { + pub fn write_register(self: SelfSpiDevice, register_address: u8, byte: u8) ReadError!void { try self.writeRegisters(register_address, &.{byte}); } /// Shorthand for 'register-based' devices - pub fn writeRegisters(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { + pub fn write_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { var transfer = try self.beginTransfer(); defer transfer.end(); // write auto-increment, starting at given register @@ -88,14 +88,14 @@ pub fn SpiBus(comptime index: usize) type { } /// Shorthand for 'register-based' devices - pub fn readRegister(self: SelfSpiDevice, register_address: u8) ReadError!u8 { + pub fn read_register(self: SelfSpiDevice, register_address: u8) ReadError!u8 { var buffer: [1]u8 = undefined; try self.readRegisters(register_address, &buffer); return buffer[0]; } /// Shorthand for 'register-based' devices - pub fn readRegisters(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { + pub fn read_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { var transfer = try self.beginTransfer(); defer transfer.end(); // read auto-increment, starting at given register diff --git a/src/core/uart.zig b/src/core/experimental/uart.zig similarity index 88% rename from src/core/uart.zig rename to src/core/experimental/uart.zig index 13b1485..b9c385c 100644 --- a/src/core/uart.zig +++ b/src/core/experimental/uart.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig.zig"); +const micro = @import("microzig"); const chip = @import("chip"); pub fn Uart(comptime index: usize, comptime pins: Pins) type { @@ -19,7 +19,7 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type { /// If the UART is already initialized, try to return a handle to it, /// else initialize with the given config. - pub fn getOrInit(config: Config) InitError!Self { + pub fn get_or_init(config: Config) InitError!Self { if (!@hasDecl(SystemUart, "getOrInit")) { // fallback to reinitializing the UART return init(config); @@ -29,11 +29,11 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type { }; } - pub fn canRead(self: Self) bool { + pub fn can_read(self: Self) bool { return self.internal.canRead(); } - pub fn canWrite(self: Self) bool { + pub fn can_write(self: Self) bool { return self.internal.canWrite(); } @@ -45,16 +45,16 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type { return Writer{ .context = self }; } - pub const Reader = std.io.Reader(Self, ReadError, readSome); - pub const Writer = std.io.Writer(Self, WriteError, writeSome); + pub const Reader = std.io.Reader(Self, ReadError, read_some); + pub const Writer = std.io.Writer(Self, WriteError, write_some); - fn readSome(self: Self, buffer: []u8) ReadError!usize { + fn read_some(self: Self, buffer: []u8) ReadError!usize { for (buffer) |*c| { c.* = self.internal.rx(); } return buffer.len; } - fn writeSome(self: Self, buffer: []const u8) WriteError!usize { + fn write_some(self: Self, buffer: []const u8) WriteError!usize { for (buffer) |c| { self.internal.tx(c); } diff --git a/src/core/import-module.zig b/src/core/import-module.zig index 79581ff..6f7d6f0 100644 --- a/src/core/import-module.zig +++ b/src/core/import-module.zig @@ -1,7 +1,7 @@ //! This file is meant as a dependency for the "app" package. //! It will only re-export all symbols from "root" under the name "microzig" //! So we have a flattened and simplified dependency tree. -//! +//! //! Each config/module of microzig will also just depend on this file, so we can use //! the same benefits there. diff --git a/src/drivers.zig b/src/drivers.zig new file mode 100644 index 0000000..6ed2897 --- /dev/null +++ b/src/drivers.zig @@ -0,0 +1 @@ +pub const experimental = @import("drivers/experimental.zig"); diff --git a/src/drivers/experimental.zig b/src/drivers/experimental.zig new file mode 100644 index 0000000..a3ec727 --- /dev/null +++ b/src/drivers/experimental.zig @@ -0,0 +1,7 @@ +//! These are experimental driver interfaces. We want to see more use and +//! discussion of them before committing them to microzig's "official" API. +//! +//! They are bound to have breaking changes in the future, or even disappear, +//! so use at your own risk. +pub const button = @import("experimental/button.zig"); +pub const quadrature = @import("experimental/quadrature.zig"); diff --git a/src/drivers/button.zig b/src/drivers/experimental/button.zig similarity index 95% rename from src/drivers/button.zig rename to src/drivers/experimental/button.zig index be519db..7667ac6 100644 --- a/src/drivers/button.zig +++ b/src/drivers/experimental/button.zig @@ -19,7 +19,7 @@ pub fn Button( comptime gpio: type, /// The active state for the button. Use `.high` for active-high, `.low` for active-low. comptime active_state: micro.gpio.State, - /// Optional filter depth for debouncing. If `null` is passed, 16 samples are used to debounce the button, + /// Optional filter depth for debouncing. If `null` is passed, 16 samples are used to debounce the button, /// otherwise the given number of samples is used. comptime filter_depth: ?comptime_int, ) type { @@ -60,7 +60,7 @@ pub fn Button( /// Returns `true` when the button is pressed. /// Will only be updated when `poll` is regularly called. - pub fn isPressed(self: *Self) bool { + pub fn is_pressed(self: *Self) bool { return (self.debounce != 0); } }; diff --git a/src/drivers/quadrature.zig b/src/drivers/experimental/quadrature.zig similarity index 100% rename from src/drivers/quadrature.zig rename to src/drivers/experimental/quadrature.zig diff --git a/src/core/interrupts.zig b/src/interrupt.zig similarity index 74% rename from src/core/interrupts.zig rename to src/interrupt.zig index dd67e8c..b08e8df 100644 --- a/src/core/interrupts.zig +++ b/src/interrupt.zig @@ -15,7 +15,7 @@ pub fn disable(comptime interrupt: anytype) void { } /// Returns true when the given interrupt is unmasked. -pub fn isEnabled(comptime interrupt: anytype) bool { +pub fn is_enabled(comptime interrupt: anytype) bool { _ = interrupt; @compileError("not implemented yet!"); } @@ -33,15 +33,15 @@ pub fn cli() void { } /// Returns true, when interrupts are globally enabled via `sei()`. -pub fn areGloballyEnabled() bool { +pub fn globally_enabled() bool { @compileError("not implemented yet!"); } /// Enters a critical section and disables interrupts globally. /// Call `.leave()` on the return value to restore the previous state. -pub fn enterCriticalSection() CriticalSection { +pub fn enter_critical_section() CriticalSection { var section = CriticalSection{ - .enable_on_leave = areGloballyEnabled(), + .enable_on_leave = globally_enabled(), }; cli(); return section; @@ -59,3 +59,18 @@ const CriticalSection = struct { } } }; + +// TODO: update with arch specifics +pub const Handler = extern union { + C: *const fn () callconv(.C) void, + Naked: *const fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +pub const unhandled = Handler{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; diff --git a/src/main.zig b/src/main.zig index 80713c5..7eb1afc 100644 --- a/src/main.zig +++ b/src/main.zig @@ -1,12 +1,11 @@ const std = @import("std"); pub const LinkerScriptStep = @import("modules/LinkerScriptStep.zig"); -pub const boards = @import("modules/boards.zig"); -pub const chips = @import("modules/chips.zig"); pub const cpus = @import("modules/cpus.zig"); pub const Board = @import("modules/Board.zig"); pub const Chip = @import("modules/Chip.zig"); pub const Cpu = @import("modules/Cpu.zig"); +pub const MemoryRegion = @import("modules/MemoryRegion.zig"); const LibExeObjStep = std.build.LibExeObjStep; @@ -14,7 +13,7 @@ pub const Backing = union(enum) { board: Board, chip: Chip, - pub fn getTarget(self: @This()) std.zig.CrossTarget { + pub fn get_target(self: @This()) std.zig.CrossTarget { return switch (self) { .board => |brd| brd.chip.cpu.target, .chip => |chip| chip.cpu.target, @@ -29,10 +28,7 @@ fn root() []const u8 { } pub const BuildOptions = struct { - // a hal module is a module with ergonomic wrappers for registers for a - // given mcu, it's only dependency can be microzig - hal_module_path: ?std.build.FileSource = null, - optimize: std.builtin.OptimizeMode = std.builtin.OptimizeMode.Debug, + optimize: std.builtin.OptimizeMode = .Debug, }; pub const EmbeddedExecutable = struct { @@ -42,28 +38,6 @@ pub const EmbeddedExecutable = struct { exe.inner.addModule(name, module); } - pub fn addDriver(exe: *EmbeddedExecutable, driver: Driver) void { - var dependencies = std.ArrayList(std.Build.ModuleDependency).init(exe.inner.builder.allocator); - - for (driver.dependencies) |dep| { - dependencies.append(.{ - .name = dep, - .module = exe.inner.builder.modules.get(dep).?, - }) catch @panic("OOM"); - } - - // TODO: this is not perfect but should work for now - exe.inner.addAnonymousModule(driver.name, .{ - .source_file = driver.source_file, - .dependencies = dependencies.toOwnedSlice() catch @panic("OOM"), - }); - - const app_module = exe.inner.modules.get("app").?; - const driver_module = exe.inner.modules.get(driver.name).?; - - app_module.dependencies.put(driver.name, driver_module) catch @panic("OOM"); - } - pub fn install(exe: *EmbeddedExecutable) void { exe.inner.install(); } @@ -99,7 +73,7 @@ pub fn addEmbeddedExecutable( source: []const u8, backing: Backing, options: BuildOptions, -) EmbeddedExecutable { +) *EmbeddedExecutable { const has_board = (backing == .board); const chip = switch (backing) { .chip => |c| c, @@ -111,13 +85,16 @@ pub fn addEmbeddedExecutable( var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); hasher.update(chip.name); - hasher.update(chip.path); + // TODO: this will likely crash for generated sources, need to + // properly hook this up to the build cache api + hasher.update(chip.source.getPath(builder)); hasher.update(chip.cpu.name); - hasher.update(chip.cpu.path); + hasher.update(chip.cpu.source.getPath(builder)); if (backing == .board) { hasher.update(backing.board.name); - hasher.update(backing.board.path); + // TODO: see above + hasher.update(backing.board.source.getPath(builder)); } var mac: [16]u8 = undefined; @@ -155,10 +132,10 @@ pub fn addEmbeddedExecutable( var writer = config_file.writer(); writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; if (has_board) - writer.print("pub const board_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; + writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; - writer.print("pub const chip_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; - writer.print("pub const cpu_name = .@\"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; + writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; } @@ -173,21 +150,28 @@ pub fn addEmbeddedExecutable( }); const chip_module = builder.createModule(.{ - .source_file = .{ .path = chip.path }, + .source_file = chip.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig }, }, }); const cpu_module = builder.createModule(.{ - .source_file = .{ .path = chip.cpu.path }, + .source_file = chip.cpu.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig }, }, }); - var exe = EmbeddedExecutable{ - .inner = builder.addExecutable(.{ .name = name, .root_source_file = .{ .path = root_path ++ "core/microzig.zig" }, .target = chip.cpu.target, .optimize = options.optimize }), + const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; + + exe.* = EmbeddedExecutable{ + .inner = builder.addExecutable(.{ + .name = name, + .root_source_file = .{ .path = root_path ++ "microzig.zig" }, + .target = chip.cpu.target, + .optimize = options.optimize, + }), }; exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded @@ -206,14 +190,15 @@ pub fn addEmbeddedExecutable( exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now // these modules will be re-exported from core/microzig.zig - exe.inner.addModule("microzig-config", config_module); + exe.inner.addModule("config", config_module); exe.inner.addModule("chip", chip_module); exe.inner.addModule("cpu", cpu_module); exe.inner.addModule("hal", builder.createModule(.{ - .source_file = if (options.hal_module_path) |hal_module_path| + .source_file = if (chip.hal) |hal_module_path| hal_module_path - else .{ .path = root_path ++ "core/empty.zig" }, + else + .{ .path = root_path ++ "core/empty.zig" }, .dependencies = &.{ .{ .name = "microzig", .module = microzig }, }, @@ -222,7 +207,7 @@ pub fn addEmbeddedExecutable( switch (backing) { .board => |board| { exe.inner.addModule("board", builder.createModule(.{ - .source_file = .{ .path = board.path }, + .source_file = board.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig }, }, @@ -240,24 +225,3 @@ pub fn addEmbeddedExecutable( return exe; } - -pub const Driver = struct { - name: []const u8, - source_file: std.build.FileSource, - dependencies: []const []const u8, -}; - -// Generic purpose drivers shipped with microzig -pub const drivers = struct { - pub const quadrature = Driver{ - .name = "microzig.quadrature", - .source_file = .{ .path = root_path ++ "drivers/quadrature.zig" }, - .dependencies = &.{"microzig"}, - }; - - pub const button = Driver{ - .name = "microzig.button", - .source_file = .{ .path = root_path ++ "drivers/button.zig" }, - .dependencies = &.{"microzig"}, - }; -}; diff --git a/src/core/microzig.zig b/src/microzig.zig similarity index 91% rename from src/core/microzig.zig rename to src/microzig.zig index 5440e24..701704d 100644 --- a/src/core/microzig.zig +++ b/src/microzig.zig @@ -13,43 +13,27 @@ pub const app = @import("app"); /// Contains build-time generated configuration options for microzig. /// Contains a CPU target description, chip, board and cpu information /// and so on. -pub const config = @import("microzig-config"); +pub const config = @import("config"); /// Provides access to the low level features of the current microchip. -pub const chip = @import("chip"); +pub const chip = struct { + const inner = @import("chip"); + pub const types = inner.types; + pub usingnamespace @field(inner.devices, config.chip_name); +}; /// Provides access to board features or is `void` when no board is present. pub const board = if (config.has_board) @import("board") else void; /// Provides access to the low level features of the CPU. pub const cpu = @import("cpu"); +pub const mmio = @import("mmio.zig"); +pub const interrupt = @import("interrupt.zig"); pub const hal = @import("hal"); -/// Module that helps with interrupt handling. -pub const interrupts = @import("interrupts.zig"); - -/// Module that provides clock related functions -pub const clock = @import("clock.zig"); - -pub const gpio = @import("gpio.zig"); -pub const Gpio = gpio.Gpio; - -pub const pin = @import("pin.zig"); -pub const Pin = pin.Pin; - -pub const uart = @import("uart.zig"); -pub const Uart = uart.Uart; - -pub const spi = @import("spi.zig"); -pub const SpiBus = spi.SpiBus; - -pub const i2c = @import("i2c.zig"); -pub const I2CController = i2c.I2CController; - -pub const debug = @import("debug.zig"); - -pub const mmio = @import("mmio.zig"); +pub const core = @import("core.zig"); +pub const drivers = @import("drivers.zig"); const options_override = if (@hasDecl(app, "std_options")) app.std_options else struct {}; pub const std_options = struct { @@ -117,7 +101,7 @@ pub fn microzig_panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usiz /// Hangs the processor and will stop doing anything useful. Use with caution! pub fn hang() noreturn { while (true) { - interrupts.cli(); + interrupt.cli(); // "this loop has side effects, don't optimize the endless loop away please. thanks!" asm volatile ("" ::: "memory"); @@ -215,7 +199,7 @@ pub const sections = struct { extern const microzig_data_load_start: anyopaque; }; -pub fn initializeSystemMemories() void { +pub fn initialize_system_memories() void { @setCold(true); // fill .bss with zeroes diff --git a/src/core/mmio.zig b/src/mmio.zig similarity index 74% rename from src/core/mmio.zig rename to src/mmio.zig index cb6b347..2d6b760 100644 --- a/src/core/mmio.zig +++ b/src/mmio.zig @@ -1,10 +1,8 @@ const std = @import("std"); +const assert = std.debug.assert; -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile MMIO(size, PackedT) { - return @intToPtr(*volatile MMIO(size, PackedT), addr); -} - -pub fn MMIO(comptime size: u8, comptime PackedT: type) type { +pub fn Mmio(comptime PackedT: type) type { + const size = @bitSizeOf(PackedT); if ((size % 8) != 0) @compileError("size must be divisible by 8!"); @@ -28,13 +26,13 @@ pub fn MMIO(comptime size: u8, comptime PackedT: type) type { } pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.writeRaw(tmp); + comptime { + assert(@bitSizeOf(PackedT) == @bitSizeOf(IntT)); + } + addr.write_raw(@bitCast(IntT, val)); } - pub fn writeRaw(addr: *volatile Self, val: IntT) void { + pub fn write_raw(addr: *volatile Self, val: IntT) void { addr.raw = val; } diff --git a/src/modules/Board.zig b/src/modules/Board.zig index 8074bb6..eb114bf 100644 --- a/src/modules/Board.zig +++ b/src/modules/Board.zig @@ -1,5 +1,6 @@ +const std = @import("std"); const Chip = @import("Chip.zig"); name: []const u8, -path: []const u8, +source: std.build.FileSource, chip: Chip, diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig index 1df23e9..909b389 100644 --- a/src/modules/Chip.zig +++ b/src/modules/Chip.zig @@ -1,7 +1,44 @@ +const std = @import("std"); +const FileSource = std.build.FileSource; + const MemoryRegion = @import("MemoryRegion.zig"); const Cpu = @import("Cpu.zig"); +const Chip = @This(); + name: []const u8, -path: []const u8, +source: FileSource, cpu: Cpu, +hal: ?FileSource = null, +json_register_schema: ?FileSource = null, memory_regions: []const MemoryRegion, + +pub fn from_standard_paths(comptime root_dir: []const u8, args: struct { + name: []const u8, + cpu: Cpu, + memory_regions: []const MemoryRegion, +}) Chip { + return Chip{ + .name = args.name, + .cpu = args.cpu, + .memory_regions = args.memory_regions, + .source = .{ + .path = std.fmt.comptimePrint("{s}/chips/{s}.zig", .{ + root_dir, + args.name, + }), + }, + .hal = .{ + .path = std.fmt.comptimePrint("{s}/chips/{s}.zig", .{ + root_dir, + args.name, + }), + }, + .json_register_schema = .{ + .path = std.fmt.comptimePrint("{s}/chips/{s}.json", .{ + root_dir, + args.name, + }), + }, + }; +} diff --git a/src/modules/Cpu.zig b/src/modules/Cpu.zig index 0f06a77..4f9bcb9 100644 --- a/src/modules/Cpu.zig +++ b/src/modules/Cpu.zig @@ -1,5 +1,5 @@ const std = @import("std"); name: []const u8, -path: []const u8, +source: std.build.FileSource, target: std.zig.CrossTarget, diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig index 9357af6..eb6df1d 100644 --- a/src/modules/LinkerScriptStep.zig +++ b/src/modules/LinkerScriptStep.zig @@ -16,9 +16,9 @@ pub fn create(builder: *Builder, chip: Chip) !*LinkerscriptStep { var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); hasher.update(chip.name); - hasher.update(chip.path); + hasher.update(chip.source.getPath(builder)); hasher.update(chip.cpu.name); - hasher.update(chip.cpu.path); + hasher.update(chip.cpu.source.getPath(builder)); var mac: [16]u8 = undefined; hasher.final(&mac); diff --git a/src/modules/boards.zig b/src/modules/boards.zig deleted file mode 100644 index be08b0c..0000000 --- a/src/modules/boards.zig +++ /dev/null @@ -1,57 +0,0 @@ -const std = @import("std"); -const chips = @import("chips.zig"); -const Board = @import("Board.zig"); - -fn root() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} - -const root_path = root() ++ "/"; - -pub const arduino_nano = Board{ - .name = "Arduino Nano", - .path = root_path ++ "boards/arduino-nano/arduino-nano.zig", - .chip = chips.atmega328p, -}; - -pub const arduino_uno = Board{ - .name = "Arduino Uno", - .path = root_path ++ "boards/arduino-uno/arduino-uno.zig", - .chip = chips.atmega328p, -}; - -pub const mbed_lpc1768 = Board{ - .name = "mbed LPC1768", - .path = root_path ++ "boards/mbed-lpc1768/mbed-lpc1768.zig", - .chip = chips.lpc1768, -}; - -pub const stm32f3discovery = Board{ - .name = "STM32F3DISCOVERY", - .path = root_path ++ "boards/stm32f3discovery/stm32f3discovery.zig", - .chip = chips.stm32f303vc, -}; - -pub const stm32f4discovery = Board{ - .name = "STM32F4DISCOVERY", - .path = root_path ++ "boards/stm32f4discovery/stm32f4discovery.zig", - .chip = chips.stm32f407vg, -}; - -pub const stm3240geval = Board{ - .name = "STM3240GEVAL", - .path = root_path ++ "boards/stm3240geval/stm3240geval.zig", - .chip = chips.stm32f407vg, -}; - -pub const stm32f429idiscovery = Board{ - .name = "STM32F429IDISCOVERY", - .path = root_path ++ "boards/stm32f429idiscovery/stm32f429idiscovery.zig", - .chip = chips.stm32f429zit6u, -}; - -pub const longan_nano = Board{ - .name = "Longan Nano", - .path = root_path ++ "boards/longan-nano/longan-nano.zig", - .chip = chips.gd32vf103xb, -}; diff --git a/src/modules/boards/arduino-nano/arduino-nano.zig b/src/modules/boards/arduino-nano/arduino-nano.zig deleted file mode 100644 index 96490f8..0000000 --- a/src/modules/boards/arduino-nano/arduino-nano.zig +++ /dev/null @@ -1,33 +0,0 @@ -pub const chip = @import("chip"); - -pub const clock_frequencies = .{ - .cpu = 16_000_000, -}; - -pub const pin_map = .{ - // Port A - .D0 = "PD0", - .D1 = "PD1", - .D2 = "PD2", - .D3 = "PD3", - .D4 = "PD4", - .D5 = "PD5", - .D6 = "PD6", - .D7 = "PD7", - // Port B - .D8 = "PB0", - .D9 = "PB1", - .D10 = "PB2", - .D11 = "PB3", - .D12 = "PB4", - .D13 = "PB5", - // Port C (Analog) - .A0 = "PC0", - .A1 = "PC1", - .A2 = "PC2", - .A3 = "PC3", - .A4 = "PC4", - .A5 = "PC5", - .A6 = "ADC6", - .A7 = "ADC7", -}; diff --git a/src/modules/boards/arduino-uno/arduino-uno.zig b/src/modules/boards/arduino-uno/arduino-uno.zig deleted file mode 100644 index 9dd729c..0000000 --- a/src/modules/boards/arduino-uno/arduino-uno.zig +++ /dev/null @@ -1,32 +0,0 @@ -pub const chip = @import("chip"); - -pub const clock_frequencies = .{ - .cpu = 16_000_000, -}; - -pub const pin_map = .{ - // Port D - .D0 = "PD0", - .D1 = "PD1", - .D2 = "PD2", - .D3 = "PD3", - .D4 = "PD4", - .D5 = "PD5", - .D6 = "PD6", - .D7 = "PD7", - // Port B - .D8 = "PB0", - .D9 = "PB1", - .D10 = "PB2", - .D11 = "PB3", - .D12 = "PB4", - // LED_BUILTIN - .D13 = "PB5", - // Port C (Analog) - .A0 = "PC0", - .A1 = "PC1", - .A2 = "PC2", - .A3 = "PC3", - .A4 = "PC4", - .A5 = "PC5", -}; diff --git a/src/modules/boards/longan-nano/longan-nano.zig b/src/modules/boards/longan-nano/longan-nano.zig deleted file mode 100644 index e042be1..0000000 --- a/src/modules/boards/longan-nano/longan-nano.zig +++ /dev/null @@ -1,112 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const cpu_frequency = 8_000_000; // 8 MHz - -pub const pin_map = .{ - - // Port A - .PA0 = "PA0", - .PA1 = "PA1", - .PA2 = "PA2", - .PA3 = "PA3", - .PA4 = "PA4", - .PA5 = "PA5", - .PA6 = "PA6", - .PA7 = "PA7", - .PA8 = "PA8", - .PA9 = "PA9", - .PA10 = "PA10", - .PA11 = "PA11", - .PA12 = "PA12", - .PA13 = "PA13", - - // Port B - .PB0 = "PB0", - .PB1 = "PB1", - .PB2 = "PB2", - .PB3 = "PB3", - .PB4 = "PB4", - .PB5 = "PB5", - .PB6 = "PB6", - .PB7 = "PB7", - .PB8 = "PB8", - .PB9 = "PB9", - .PB10 = "PB10", - .PB11 = "PB11", - .PB12 = "PB12", - .PB13 = "PB13", - .PB14 = "PB14", - .PB15 = "PB15", - - // Port C - .PC0 = "PC0", - .PC1 = "PC1", - .PC2 = "PC2", - .PC3 = "PC3", - .PC4 = "PC4", - .PC5 = "PC5", - .PC6 = "PC6", - .PC7 = "PC7", - .PC8 = "PC8", - .PC9 = "PC9", - .PC10 = "PC10", - .PC11 = "PC11", - .PC12 = "PC12", - .PC13 = "PC13", - .PC14 = "PC14", - .PC15 = "PC15", - - // Port D - .PD0 = "PD0", - .PD1 = "PD1", - .PD2 = "PD2", - .PD3 = "PD3", - .PD4 = "PD4", - .PD5 = "PD5", - .PD6 = "PD6", - .PD7 = "PD7", - .PD8 = "PD8", - .PD9 = "PD9", - .PD10 = "PD10", - .PD11 = "PD11", - .PD12 = "PD12", - .PD13 = "PD13", - .PD14 = "PD14", - .PD15 = "PD15", - - // Port E - .PE0 = "PE0", - .PE1 = "PE1", - .PE2 = "PE2", - .PE3 = "PE3", - .PE4 = "PE4", - .PE5 = "PE5", - .PE6 = "PE6", - .PE7 = "PE7", - .PE8 = "PE8", - .PE9 = "PE9", - .PE10 = "PE10", - .PE11 = "PE11", - .PE12 = "PE12", - .PE13 = "PE13", - .PE14 = "PE14", - .PE15 = "PE15", - - // Colors LED - // LCD_COLOR_WHITE 0xFFFF - // LCD_COLOR_BLACK 0x0000 - // LCD_COLOR_GREY 0xF7DE - // LCD_COLOR_BLUE 0x001F - // LCD_COLOR_BLUE2 0x051F - // LCD_COLOR_RED 0xF800 - // LCD_COLOR_MAGENTA 0xF81F - // LCD_COLOR_GREEN 0x07E0 - // LCD_COLOR_CYAN 0x7FFF - // LCD_COLOR_YELLOW 0xFFE0 -}; - -pub fn debugWrite(string: []const u8) void { - _ = string; - // TODO: implement -} diff --git a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig b/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig deleted file mode 100644 index 6c5ff9d..0000000 --- a/src/modules/boards/mbed-lpc1768/mbed-lpc1768.zig +++ /dev/null @@ -1,84 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const clock_frequencies = .{ - .cpu = 100_000_000, // 100 Mhz -}; - -pub fn debugWrite(string: []const u8) void { - const clk_pin = micro.Pin("DIP5"); - const dat_pin = micro.Pin("DIP6"); - - const clk = micro.Gpio(clk_pin, .{ .mode = .output, .initial_state = .low }); - const dat = micro.Gpio(dat_pin, .{ .mode = .output, .initial_state = .low }); - - clk.init(); - dat.init(); - - micro.debug.busySleep(1_000); - - for (string) |c| { - comptime var i: usize = 128; - inline while (i > 0) : (i = i >> 1) { - if ((c & i) != 0) { - dat.write(.high); - } else { - dat.write(.low); - } - clk.write(.high); - micro.debug.busySleep(1_000); - clk.write(.low); - micro.debug.busySleep(1_000); - } - } - dat.write(.low); - clk.write(.low); -} - -pub const pin_map = .{ - // Onboard-LEDs - .@"LED-1" = "P1.18", - .@"LED-2" = "P1.20", - .@"LED-3" = "P1.21", - .@"LED-4" = "P1.23", - .@"LED_LINK" = "P1.25", - .@"LED_SPEED" = "P1.26", - - // Ethernet - .@"TD+" = "P1.0", - .@"TD-" = "P1.1", - .@"RD+" = "P1.9", - .@"RD-" = "P1.10", - - // USB - .@"D+" = "P0.29", - .@"D-" = "P0.30", - - // GPIO pins - .@"DIP5" = "P0.9", - .@"DIP6" = "P0.8", - .@"DIP7" = "P0.7", - .@"DIP8" = "P0.6", - .@"DIP9" = "P0.0", - .@"DIP10" = "P0.1", - .@"DIP11" = "P0.18", - .@"DIP12" = "P0.17", - .@"DIP13" = "P0.15", - .@"DIP14" = "P0.16", - .@"DIP15" = "P0.23", - .@"DIP16" = "P0.24", - .@"DIP17" = "P0.25", - .@"DIP18" = "P0.26", - .@"DIP19" = "P1.30", - .@"DIP20" = "P1.31", - .@"DIP21" = "P2.5", - .@"DIP22" = "P2.4", - .@"DIP23" = "P2.3", - .@"DIP24" = "P2.2", - .@"DIP25" = "P2.1", - .@"DIP26" = "P2.0", - .@"DIP27" = "P0.11", - .@"DIP28" = "P0.10", - .@"DIP29" = "P0.5", - .@"DIP30" = "P0.4", -}; diff --git a/src/modules/boards/stm3240geval/stm3240geval.zig b/src/modules/boards/stm3240geval/stm3240geval.zig deleted file mode 100644 index b78162a..0000000 --- a/src/modules/boards/stm3240geval/stm3240geval.zig +++ /dev/null @@ -1,13 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const pin_map = .{ - // LD1 green - .@"LD1" = "PG6", - // LD2 orange - .@"LD2" = "PG8", - // LD3 red - .@"LD3" = "PI9", - // LD4 blue - .@"LD4" = "PC7", -}; diff --git a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig b/src/modules/boards/stm32f3discovery/stm32f3discovery.zig deleted file mode 100644 index 56d249e..0000000 --- a/src/modules/boards/stm32f3discovery/stm32f3discovery.zig +++ /dev/null @@ -1,38 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const cpu_frequency = 8_000_000; - -pub const pin_map = .{ - // circle of LEDs, connected to GPIOE bits 8..15 - - // NW blue - .@"LD4" = "PE8", - // N red - .@"LD3" = "PE9", - // NE orange - .@"LD5" = "PE10", - // E green - .@"LD7" = "PE11", - // SE blue - .@"LD9" = "PE12", - // S red - .@"LD10" = "PE13", - // SW orange - .@"LD8" = "PE14", - // W green - .@"LD6" = "PE15", -}; - -pub fn debugWrite(string: []const u8) void { - const uart1 = micro.Uart(1, .{}).getOrInit(.{ - .baud_rate = 9600, - .data_bits = .eight, - .parity = null, - .stop_bits = .one, - }) catch unreachable; - - const writer = uart1.writer(); - _ = writer.write(string) catch unreachable; - uart1.internal.txflush(); -} diff --git a/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig b/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig deleted file mode 100644 index 35418d6..0000000 --- a/src/modules/boards/stm32f429idiscovery/stm32f429idiscovery.zig +++ /dev/null @@ -1,15 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const cpu_frequency = 16_000_000; - -pub const pin_map = .{ - // LEDs, connected to GPIOG bits 13, 14 - // green - .@"LD3" = "PG13", - // red - .@"LD4" = "PG14", - - // User button - .@"B1" = "PA0", -}; diff --git a/src/modules/boards/stm32f4discovery/stm32f4discovery.zig b/src/modules/boards/stm32f4discovery/stm32f4discovery.zig deleted file mode 100644 index 7703b1d..0000000 --- a/src/modules/boards/stm32f4discovery/stm32f4discovery.zig +++ /dev/null @@ -1,17 +0,0 @@ -pub const chip = @import("chip"); -pub const micro = @import("microzig"); - -pub const pin_map = .{ - // LED cross, connected to GPIOD bits 12..15 - // N orange - .@"LD3" = "PD13", - // E red - .@"LD5" = "PD14", - // S blue - .@"LD6" = "PD15", - // W green - .@"LD4" = "PD12", - - // User button - .@"B2" = "PA0", -}; diff --git a/src/modules/chips.zig b/src/modules/chips.zig deleted file mode 100644 index 4419d2d..0000000 --- a/src/modules/chips.zig +++ /dev/null @@ -1,116 +0,0 @@ -const std = @import("std"); -const cpus = @import("cpus.zig"); -const Chip = @import("Chip.zig"); -const MemoryRegion = @import("MemoryRegion.zig"); - -fn root() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} - -const root_path = root() ++ "/"; - -pub const atmega328p = Chip{ - .name = "ATmega328p", - .path = root_path ++ "chips/atmega328p/atmega328p.zig", - .cpu = cpus.avr5, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram }, - }, -}; - -pub const lpc1768 = Chip{ - .name = "NXP LPC1768", - .path = root_path ++ "chips/lpc1768/lpc1768.zig", - .cpu = cpus.cortex_m3, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram }, - MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram }, - }, -}; - -pub const gd32vf103xb = Chip{ - .name = "GD32VF103xB", - .path = root_path ++ "chips/gd32vf103/gd32vf103.zig", - .cpu = cpus.riscv32_imac, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, - }, -}; - -pub const gd32vf103x8 = Chip{ - .name = "GD32VF103x8", - .path = root_path ++ "chips/gd32vf103/gd32vf103.zig", - .cpu = cpus.riscv32_imac, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, - }, -}; - -pub const stm32f103x8 = Chip{ - .name = "STM32F103x8", - .path = root_path ++ "chips/stm32f103/stm32f103.zig", - .cpu = cpus.cortex_m3, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, - }, -}; - -pub const stm32f303vc = Chip{ - .name = "STM32F303VC", - .path = root_path ++ "chips/stm32f303/stm32f303.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram }, - }, -}; - -pub const stm32f407vg = Chip{ - .name = "STM32F407VG", - .path = root_path ++ "chips/stm32f407/stm32f407.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram }, - // CCM RAM - MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, - }, -}; - -pub const stm32f429zit6u = Chip{ - .name = "STM32F429ZIT6U", - .path = root_path ++ "chips/stm32f429/stm32f429.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram }, - // CCM RAM - MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, - }, -}; - -pub const nrf52832 = Chip{ - .name = "nRF52832", - .path = root_path ++ "chips/nrf52/nrf52.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram }, - }, -}; - -pub const atsame51j20a = Chip{ - .name = "ATSAME51J20A", - .path = root_path ++ "chips/atsame51j20a/atsame51j20a.zig", - .cpu = cpus.cortex_m4, - .memory_regions = &.{ - // SAM D5x/E5x Family Data Sheet page 53 - MemoryRegion{ .offset = 0x00000000, .length = 1024 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 256 * 1024, .kind = .ram }, - }, -}; \ No newline at end of file diff --git a/src/modules/chips/atmega328p/atmega328p.zig b/src/modules/chips/atmega328p/atmega328p.zig deleted file mode 100644 index b836c65..0000000 --- a/src/modules/chips/atmega328p/atmega328p.zig +++ /dev/null @@ -1,191 +0,0 @@ -const std = @import("std"); -const micro = @import("microzig"); - -pub usingnamespace @import("registers.zig"); -const regz = @import("registers.zig").registers; - -pub const cpu = micro.cpu; -const Port = enum(u8) { - B = 1, - C = 2, - D = 3, -}; - -pub const clock = struct { - pub const Domain = enum { - cpu, - }; -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec.len != 3) - @compileError(invalid_format_msg); - if (spec[0] != 'P') - @compileError(invalid_format_msg); - - return struct { - pub const port: Port = std.meta.stringToEnum(Port, spec[1..2]) orelse @compileError(invalid_format_msg); - pub const pin: u3 = std.fmt.parseInt(u3, spec[2..3], 10) catch @compileError(invalid_format_msg); - }; -} - -pub const gpio = struct { - fn regs(comptime desc: type) type { - return struct { - // io address - const pin_addr: u5 = 3 * @enumToInt(desc.port) + 0x00; - const dir_addr: u5 = 3 * @enumToInt(desc.port) + 0x01; - const port_addr: u5 = 3 * @enumToInt(desc.port) + 0x02; - - // ram mapping - const pin = @intToPtr(*volatile u8, 0x20 + @as(usize, pin_addr)); - const dir = @intToPtr(*volatile u8, 0x20 + @as(usize, dir_addr)); - const port = @intToPtr(*volatile u8, 0x20 + @as(usize, port_addr)); - }; - } - - pub fn setOutput(comptime pin: type) void { - cpu.sbi(regs(pin).dir_addr, pin.pin); - } - - pub fn setInput(comptime pin: type) void { - cpu.cbi(regs(pin).dir_addr, pin.pin); - } - - pub fn read(comptime pin: type) micro.gpio.State { - return if ((regs(pin).pin.* & (1 << pin.pin)) != 0) - .high - else - .low; - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - if (state == .high) { - cpu.sbi(regs(pin).port_addr, pin.pin); - } else { - cpu.cbi(regs(pin).port_addr, pin.pin); - } - } - - pub fn toggle(comptime pin: type) void { - cpu.sbi(regs(pin).pin_addr, pin.pin); - } -}; - -pub const uart = struct { - pub const DataBits = enum { - five, - six, - seven, - eight, - nine, - }; - - pub const StopBits = enum { - one, - two, - }; - - pub const Parity = enum { - odd, - even, - }; -}; - -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (index != 0) @compileError("Atmega328p only has a single uart!"); - if (pins.tx != null or pins.rx != null) - @compileError("Atmega328p has fixed pins for uart!"); - - return struct { - const Self = @This(); - - fn computeDivider(baud_rate: u32) !u12 { - const pclk = micro.clock.get().cpu; - const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1; - - return std.math.cast(u12, divider) orelse return error.UnsupportedBaudRate; - } - - fn computeBaudRate(divider: u12) u32 { - return micro.clock.get().cpu / (16 * @as(u32, divider) + 1); - } - - pub fn init(config: micro.uart.Config) !Self { - const ucsz: u3 = switch (config.data_bits) { - .five => 0b000, - .six => 0b001, - .seven => 0b010, - .eight => 0b011, - .nine => return error.UnsupportedWordSize, // 0b111 - }; - - const upm: u2 = if (config.parity) |parity| switch (parity) { - .even => @as(u2, 0b10), // even - .odd => @as(u2, 0b11), // odd - } else 0b00; // parity disabled - - const usbs: u1 = switch (config.stop_bits) { - .one => 0b0, - .two => 0b1, - }; - - const umsel: u2 = 0b00; // Asynchronous USART - - // baud is computed like this: - // f(osc) - // BAUD = ---------------- - // 16 * (UBRRn + 1) - - const ubrr_val = try computeDivider(config.baud_rate); - - regz.USART0.UCSR0A.modify(.{ - .MPCM0 = 0, - .U2X0 = 0, - }); - regz.USART0.UCSR0B.write(.{ - .TXB80 = 0, // we don't care about these btw - .RXB80 = 0, // we don't care about these btw - .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2), - .TXEN0 = 1, - .RXEN0 = 1, - .UDRIE0 = 0, // no interrupts - .TXCIE0 = 0, // no interrupts - .RXCIE0 = 0, // no interrupts - }); - regz.USART0.UCSR0C.write(.{ - .UCPOL0 = 0, // async mode - .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0), - .USBS0 = usbs, - .UPM0 = upm, - .UMSEL0 = umsel, - }); - - regz.USART0.UBRR0.modify(ubrr_val); - - return Self{}; - } - - pub fn canWrite(self: Self) bool { - _ = self; - return (regz.USART0.UCSR0A.read().UDRE0 == 1); - } - - pub fn tx(self: Self, ch: u8) void { - while (!self.canWrite()) {} // Wait for Previous transmission - regz.USART0.UDR0.* = ch; // Load the data to be transmitted - } - - pub fn canRead(self: Self) bool { - _ = self; - return (regz.USART0.UCSR0A.read().RXC0 == 1); - } - - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - return regz.USART0.UDR0.*; // Read received data - } - }; -} diff --git a/src/modules/chips/atmega328p/registers.zig b/src/modules/chips/atmega328p/registers.zig deleted file mode 100644 index d43ad4f..0000000 --- a/src/modules/chips/atmega328p/registers.zig +++ /dev/null @@ -1,1309 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 6376709051af4d8920d5c8bb48945ca688af32ae -// -// vendor: Atmel -// device: ATmega328P -// cpu: AVR8 - -pub const VectorTable = extern struct { - /// External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - RESET: InterruptVector = unhandled, - /// External Interrupt Request 0 - INT0: InterruptVector = unhandled, - /// External Interrupt Request 1 - INT1: InterruptVector = unhandled, - /// Pin Change Interrupt Request 0 - PCINT0: InterruptVector = unhandled, - /// Pin Change Interrupt Request 1 - PCINT1: InterruptVector = unhandled, - /// Pin Change Interrupt Request 2 - PCINT2: InterruptVector = unhandled, - /// Watchdog Time-out Interrupt - WDT: InterruptVector = unhandled, - /// Timer/Counter2 Compare Match A - TIMER2_COMPA: InterruptVector = unhandled, - /// Timer/Counter2 Compare Match B - TIMER2_COMPB: InterruptVector = unhandled, - /// Timer/Counter2 Overflow - TIMER2_OVF: InterruptVector = unhandled, - /// Timer/Counter1 Capture Event - TIMER1_CAPT: InterruptVector = unhandled, - /// Timer/Counter1 Compare Match A - TIMER1_COMPA: InterruptVector = unhandled, - /// Timer/Counter1 Compare Match B - TIMER1_COMPB: InterruptVector = unhandled, - /// Timer/Counter1 Overflow - TIMER1_OVF: InterruptVector = unhandled, - /// TimerCounter0 Compare Match A - TIMER0_COMPA: InterruptVector = unhandled, - /// TimerCounter0 Compare Match B - TIMER0_COMPB: InterruptVector = unhandled, - /// Timer/Couner0 Overflow - TIMER0_OVF: InterruptVector = unhandled, - /// SPI Serial Transfer Complete - SPI_STC: InterruptVector = unhandled, - /// USART Rx Complete - USART_RX: InterruptVector = unhandled, - /// USART, Data Register Empty - USART_UDRE: InterruptVector = unhandled, - /// USART Tx Complete - USART_TX: InterruptVector = unhandled, - /// ADC Conversion Complete - ADC: InterruptVector = unhandled, - /// EEPROM Ready - EE_READY: InterruptVector = unhandled, - /// Analog Comparator - ANALOG_COMP: InterruptVector = unhandled, - /// Two-wire Serial Interface - TWI: InterruptVector = unhandled, - /// Store Program Memory Read - SPM_Ready: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// Fuses - pub const FUSE = struct { - /// address: 0x2 - pub const EXTENDED = @intToPtr(*volatile Mmio(8, packed struct { - /// Brown-out Detector trigger level - /// - /// 0x4: Brown-out detection at VCC=4.3 V - /// 0x5: Brown-out detection at VCC=2.7 V - /// 0x6: Brown-out detection at VCC=1.8 V - /// 0x7: Brown-out detection disabled - BODLEVEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x2); - - /// address: 0x1 - pub const HIGH = @intToPtr(*volatile Mmio(8, packed struct { - /// Boot Reset vector Enabled - BOOTRST: u1, - /// Select boot size - /// - /// 0x0: Boot Flash size=2048 words start address=$3800 - /// 0x1: Boot Flash size=1024 words start address=$3C00 - /// 0x2: Boot Flash size=512 words start address=$3E00 - /// 0x3: Boot Flash size=256 words start address=$3F00 - BOOTSZ: u2, - /// Preserve EEPROM through the Chip Erase cycle - EESAVE: u1, - /// Watch-dog Timer always on - WDTON: u1, - /// Serial program downloading (SPI) enabled - SPIEN: u1, - /// Debug Wire enable - DWEN: u1, - /// Reset Disabled (Enable PC6 as i/o pin) - RSTDISBL: u1, - }), 0x1); - - /// address: 0x0 - pub const LOW = @intToPtr(*volatile Mmio(8, packed struct { - /// Select Clock Source - /// - /// 0x0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - /// 0x2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - /// 0x3: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - /// 0x4: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - /// 0x5: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms - /// 0x6: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - /// 0x7: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - /// 0x8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - /// 0x9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - /// 0xa: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - /// 0xb: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - /// 0xc: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - /// 0xd: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - /// 0xe: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - /// 0xf: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - /// 0x10: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - /// 0x12: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - /// 0x13: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - /// 0x14: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms - /// 0x15: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms - /// 0x16: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - /// 0x17: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - /// 0x18: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - /// 0x19: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - /// 0x1a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - /// 0x1b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - /// 0x1c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - /// 0x1d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - /// 0x1e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - /// 0x1f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - /// 0x20: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - /// 0x22: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - /// 0x23: Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - /// 0x24: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms - /// 0x25: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms - /// 0x26: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - /// 0x27: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - /// 0x28: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - /// 0x29: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - /// 0x2a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - /// 0x2b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - /// 0x2c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - /// 0x2d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - /// 0x2e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - /// 0x2f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - /// 0x36: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - /// 0x37: Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - /// 0x38: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - /// 0x39: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - /// 0x3a: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - /// 0x3b: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - /// 0x3c: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - /// 0x3d: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - /// 0x3e: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - /// 0x3f: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - SUT_CKSEL: u6, - /// Clock output on PORTB0 - CKOUT: u1, - /// Divide clock by 8 internally - CKDIV8: u1, - }), 0x0); - }; - - /// Lockbits - pub const LOCKBIT = struct { - /// address: 0x0 - pub const LOCKBIT = @intToPtr(*volatile Mmio(8, packed struct { - /// Memory Lock - /// - /// 0x0: Further programming and verification disabled - /// 0x2: Further programming disabled - /// 0x3: No memory lock features enabled - LB: u2, - /// Boot Loader Protection Mode - /// - /// 0x0: LPM and SPM prohibited in Application Section - /// 0x1: LPM prohibited in Application Section - /// 0x2: SPM prohibited in Application Section - /// 0x3: No lock on SPM and LPM in Application Section - BLB0: u2, - /// Boot Loader Protection Mode - /// - /// 0x0: LPM and SPM prohibited in Boot Section - /// 0x1: LPM prohibited in Boot Section - /// 0x2: SPM prohibited in Boot Section - /// 0x3: No lock on SPM and LPM in Boot Section - BLB1: u2, - padding0: u1, - padding1: u1, - }), 0x0); - }; - - /// USART - pub const USART0 = struct { - /// address: 0xc6 - /// USART I/O Data Register - pub const UDR0 = @intToPtr(*volatile u8, 0xc6); - - /// address: 0xc0 - /// USART Control and Status Register A - pub const UCSR0A = @intToPtr(*volatile Mmio(8, packed struct { - /// Multi-processor Communication Mode - MPCM0: u1, - /// Double the USART transmission speed - U2X0: u1, - /// Parity Error - UPE0: u1, - /// Data overRun - DOR0: u1, - /// Framing Error - FE0: u1, - /// USART Data Register Empty - UDRE0: u1, - /// USART Transmitt Complete - TXC0: u1, - /// USART Receive Complete - RXC0: u1, - }), 0xc0); - - /// address: 0xc1 - /// USART Control and Status Register B - pub const UCSR0B = @intToPtr(*volatile Mmio(8, packed struct { - /// Transmit Data Bit 8 - TXB80: u1, - /// Receive Data Bit 8 - RXB80: u1, - /// Character Size - together with UCSZ0 in UCSR0C - UCSZ02: u1, - /// Transmitter Enable - TXEN0: u1, - /// Receiver Enable - RXEN0: u1, - /// USART Data register Empty Interrupt Enable - UDRIE0: u1, - /// TX Complete Interrupt Enable - TXCIE0: u1, - /// RX Complete Interrupt Enable - RXCIE0: u1, - }), 0xc1); - - /// address: 0xc2 - /// USART Control and Status Register C - pub const UCSR0C = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Polarity - UCPOL0: u1, - /// Character Size - together with UCSZ2 in UCSR0B - UCSZ0: u2, - /// Stop Bit Select - /// - /// 0x0: 1-bit - /// 0x1: 2-bit - USBS0: u1, - /// Parity Mode Bits - /// - /// 0x0: Disabled - /// 0x1: Reserved - /// 0x2: Enabled, Even Parity - /// 0x3: Enabled, Odd Parity - UPM0: u2, - /// USART Mode Select - /// - /// 0x0: Asynchronous USART - /// 0x1: Synchronous USART - /// 0x3: Master SPI - UMSEL0: u2, - }), 0xc2); - - /// address: 0xc4 - /// USART Baud Rate Register Bytes - pub const UBRR0 = @intToPtr(*volatile MmioInt(16, u12), 0xc4); - }; - - /// Two Wire Serial Interface - pub const TWI = struct { - /// address: 0xbd - /// TWI (Slave) Address Mask Register - pub const TWAMR = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - TWAM: u7, - }), 0xbd); - - /// address: 0xb8 - /// TWI Bit Rate register - pub const TWBR = @intToPtr(*volatile u8, 0xb8); - - /// address: 0xbc - /// TWI Control Register - pub const TWCR = @intToPtr(*volatile Mmio(8, packed struct { - /// TWI Interrupt Enable - TWIE: u1, - reserved0: u1, - /// TWI Enable Bit - TWEN: u1, - /// TWI Write Collition Flag - TWWC: u1, - /// TWI Stop Condition Bit - TWSTO: u1, - /// TWI Start Condition Bit - TWSTA: u1, - /// TWI Enable Acknowledge Bit - TWEA: u1, - /// TWI Interrupt Flag - TWINT: u1, - }), 0xbc); - - /// address: 0xb9 - /// TWI Status Register - pub const TWSR = @intToPtr(*volatile Mmio(8, packed struct { - /// TWI Prescaler - /// - /// 0x0: 1 - /// 0x1: 4 - /// 0x2: 16 - /// 0x3: 64 - TWPS: u2, - reserved0: u1, - /// TWI Status - TWS: u5, - }), 0xb9); - - /// address: 0xbb - /// TWI Data register - pub const TWDR = @intToPtr(*volatile u8, 0xbb); - - /// address: 0xba - /// TWI (Slave) Address register - pub const TWAR = @intToPtr(*volatile Mmio(8, packed struct { - /// TWI General Call Recognition Enable Bit - TWGCE: u1, - /// TWI (Slave) Address register Bits - TWA: u7, - }), 0xba); - }; - - /// Timer/Counter, 16-bit - pub const TC1 = struct { - /// address: 0x6f - /// Timer/Counter Interrupt Mask Register - pub const TIMSK1 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter1 Overflow Interrupt Enable - TOIE1: u1, - /// Timer/Counter1 Output CompareA Match Interrupt Enable - OCIE1A: u1, - /// Timer/Counter1 Output CompareB Match Interrupt Enable - OCIE1B: u1, - reserved0: u1, - reserved1: u1, - /// Timer/Counter1 Input Capture Interrupt Enable - ICIE1: u1, - padding0: u1, - padding1: u1, - }), 0x6f); - - /// address: 0x36 - /// Timer/Counter Interrupt Flag register - pub const TIFR1 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter1 Overflow Flag - TOV1: u1, - /// Output Compare Flag 1A - OCF1A: u1, - /// Output Compare Flag 1B - OCF1B: u1, - reserved0: u1, - reserved1: u1, - /// Input Capture Flag 1 - ICF1: u1, - padding0: u1, - padding1: u1, - }), 0x36); - - /// address: 0x80 - /// Timer/Counter1 Control Register A - pub const TCCR1A = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Generation Mode - WGM1: u2, - reserved0: u1, - reserved1: u1, - /// Compare Output Mode 1B, bits - COM1B: u2, - /// Compare Output Mode 1A, bits - COM1A: u2, - }), 0x80); - - /// address: 0x81 - /// Timer/Counter1 Control Register B - pub const TCCR1B = @intToPtr(*volatile Mmio(8, packed struct { - /// Prescaler source of Timer/Counter 1 - /// - /// 0x0: No Clock Source (Stopped) - /// 0x1: Running, No Prescaling - /// 0x2: Running, CLK/8 - /// 0x3: Running, CLK/64 - /// 0x4: Running, CLK/256 - /// 0x5: Running, CLK/1024 - /// 0x6: Running, ExtClk Tn Falling Edge - /// 0x7: Running, ExtClk Tn Rising Edge - CS1: u3, - /// Waveform Generation Mode - WGM1: u2, - reserved0: u1, - /// Input Capture 1 Edge Select - ICES1: u1, - /// Input Capture 1 Noise Canceler - ICNC1: u1, - }), 0x81); - - /// address: 0x82 - /// Timer/Counter1 Control Register C - pub const TCCR1C = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - FOC1B: u1, - FOC1A: u1, - }), 0x82); - - /// address: 0x84 - /// Timer/Counter1 Bytes - pub const TCNT1 = @intToPtr(*volatile u16, 0x84); - - /// address: 0x88 - /// Timer/Counter1 Output Compare Register Bytes - pub const OCR1A = @intToPtr(*volatile u16, 0x88); - - /// address: 0x8a - /// Timer/Counter1 Output Compare Register Bytes - pub const OCR1B = @intToPtr(*volatile u16, 0x8a); - - /// address: 0x86 - /// Timer/Counter1 Input Capture Register Bytes - pub const ICR1 = @intToPtr(*volatile u16, 0x86); - - /// address: 0x43 - /// General Timer/Counter Control Register - pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Prescaler Reset Timer/Counter1 and Timer/Counter0 - PSRSYNC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Timer/Counter Synchronization Mode - TSM: u1, - }), 0x43); - }; - - /// Timer/Counter, 8-bit Async - pub const TC2 = struct { - /// address: 0x70 - /// Timer/Counter Interrupt Mask register - pub const TIMSK2 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter2 Overflow Interrupt Enable - TOIE2: u1, - /// Timer/Counter2 Output Compare Match A Interrupt Enable - OCIE2A: u1, - /// Timer/Counter2 Output Compare Match B Interrupt Enable - OCIE2B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x70); - - /// address: 0x37 - /// Timer/Counter Interrupt Flag Register - pub const TIFR2 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter2 Overflow Flag - TOV2: u1, - /// Output Compare Flag 2A - OCF2A: u1, - /// Output Compare Flag 2B - OCF2B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x37); - - /// address: 0xb0 - /// Timer/Counter2 Control Register A - pub const TCCR2A = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Genration Mode - WGM2: u2, - reserved0: u1, - reserved1: u1, - /// Compare Output Mode bits - COM2B: u2, - /// Compare Output Mode bits - COM2A: u2, - }), 0xb0); - - /// address: 0xb1 - /// Timer/Counter2 Control Register B - pub const TCCR2B = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Select bits - /// - /// 0x0: No Clock Source (Stopped) - /// 0x1: Running, No Prescaling - /// 0x2: Running, CLK/8 - /// 0x3: Running, CLK/32 - /// 0x4: Running, CLK/64 - /// 0x5: Running, CLK/128 - /// 0x6: Running, CLK/256 - /// 0x7: Running, CLK/1024 - CS2: u3, - /// Waveform Generation Mode - WGM22: u1, - reserved0: u1, - reserved1: u1, - /// Force Output Compare B - FOC2B: u1, - /// Force Output Compare A - FOC2A: u1, - }), 0xb1); - - /// address: 0xb2 - /// Timer/Counter2 - pub const TCNT2 = @intToPtr(*volatile u8, 0xb2); - - /// address: 0xb4 - /// Timer/Counter2 Output Compare Register B - pub const OCR2B = @intToPtr(*volatile u8, 0xb4); - - /// address: 0xb3 - /// Timer/Counter2 Output Compare Register A - pub const OCR2A = @intToPtr(*volatile u8, 0xb3); - - /// address: 0xb6 - /// Asynchronous Status Register - pub const ASSR = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter Control Register2 Update Busy - TCR2BUB: u1, - /// Timer/Counter Control Register2 Update Busy - TCR2AUB: u1, - /// Output Compare Register 2 Update Busy - OCR2BUB: u1, - /// Output Compare Register2 Update Busy - OCR2AUB: u1, - /// Timer/Counter2 Update Busy - TCN2UB: u1, - /// Asynchronous Timer/Counter2 - AS2: u1, - /// Enable External Clock Input - EXCLK: u1, - padding0: u1, - }), 0xb6); - - /// address: 0x43 - /// General Timer Counter Control register - pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Prescaler Reset Timer/Counter2 - PSRASY: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Timer/Counter Synchronization Mode - TSM: u1, - }), 0x43); - }; - - /// Analog-to-Digital Converter - pub const ADC = struct { - /// address: 0x7c - /// The ADC multiplexer Selection Register - pub const ADMUX = @intToPtr(*volatile Mmio(8, packed struct { - /// Analog Channel Selection Bits - /// - /// 0x0: ADC Single Ended Input pin 0 - /// 0x1: ADC Single Ended Input pin 1 - /// 0x2: ADC Single Ended Input pin 2 - /// 0x3: ADC Single Ended Input pin 3 - /// 0x4: ADC Single Ended Input pin 4 - /// 0x5: ADC Single Ended Input pin 5 - /// 0x6: ADC Single Ended Input pin 6 - /// 0x7: ADC Single Ended Input pin 7 - /// 0x8: Temperature sensor - /// 0xe: Internal Reference (VBG) - /// 0xf: 0V (GND) - MUX: u4, - reserved0: u1, - /// Left Adjust Result - ADLAR: u1, - /// Reference Selection Bits - /// - /// 0x0: AREF, Internal Vref turned off - /// 0x1: AVCC with external capacitor at AREF pin - /// 0x2: Reserved - /// 0x3: Internal 1.1V Voltage Reference with external capacitor at AREF pin - REFS: u2, - }), 0x7c); - - /// address: 0x78 - /// ADC Data Register Bytes - pub const ADC = @intToPtr(*volatile u16, 0x78); - - /// address: 0x7a - /// The ADC Control and Status register A - pub const ADCSRA = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Prescaler Select Bits - /// - /// 0x0: 2 - /// 0x1: 2 - /// 0x2: 4 - /// 0x3: 8 - /// 0x4: 16 - /// 0x5: 32 - /// 0x6: 64 - /// 0x7: 128 - ADPS: u3, - /// ADC Interrupt Enable - ADIE: u1, - /// ADC Interrupt Flag - ADIF: u1, - /// ADC Auto Trigger Enable - ADATE: u1, - /// ADC Start Conversion - ADSC: u1, - /// ADC Enable - ADEN: u1, - }), 0x7a); - - /// address: 0x7b - /// The ADC Control and Status register B - pub const ADCSRB = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Auto Trigger Source bits - /// - /// 0x0: Free Running mode - /// 0x1: Analog Comparator - /// 0x2: External Interrupt Request 0 - /// 0x3: Timer/Counter0 Compare Match A - /// 0x4: Timer/Counter0 Overflow - /// 0x5: Timer/Counter1 Compare Match B - /// 0x6: Timer/Counter1 Overflow - /// 0x7: Timer/Counter1 Capture Event - ADTS: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - ACME: u1, - padding0: u1, - }), 0x7b); - - /// address: 0x7e - /// Digital Input Disable Register - pub const DIDR0 = @intToPtr(*volatile Mmio(8, packed struct { - ADC0D: u1, - ADC1D: u1, - ADC2D: u1, - ADC3D: u1, - ADC4D: u1, - ADC5D: u1, - padding0: u1, - padding1: u1, - }), 0x7e); - }; - - /// Analog Comparator - pub const AC = struct { - /// address: 0x50 - /// Analog Comparator Control And Status Register - pub const ACSR = @intToPtr(*volatile Mmio(8, packed struct { - /// Analog Comparator Interrupt Mode Select bits - /// - /// 0x0: Interrupt on Toggle - /// 0x1: Reserved - /// 0x2: Interrupt on Falling Edge - /// 0x3: Interrupt on Rising Edge - ACIS: u2, - /// Analog Comparator Input Capture Enable - ACIC: u1, - /// Analog Comparator Interrupt Enable - ACIE: u1, - /// Analog Comparator Interrupt Flag - ACI: u1, - /// Analog Compare Output - ACO: u1, - /// Analog Comparator Bandgap Select - ACBG: u1, - /// Analog Comparator Disable - ACD: u1, - }), 0x50); - - /// address: 0x7f - /// Digital Input Disable Register 1 - pub const DIDR1 = @intToPtr(*volatile Mmio(8, packed struct { - /// AIN0 Digital Input Disable - AIN0D: u1, - /// AIN1 Digital Input Disable - AIN1D: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), 0x7f); - }; - - /// I/O Port - pub const PORTB = struct { - /// address: 0x25 - /// Port B Data Register - pub const PORTB = @intToPtr(*volatile u8, 0x25); - - /// address: 0x24 - /// Port B Data Direction Register - pub const DDRB = @intToPtr(*volatile u8, 0x24); - - /// address: 0x23 - /// Port B Input Pins - pub const PINB = @intToPtr(*volatile u8, 0x23); - }; - - /// I/O Port - pub const PORTC = struct { - /// address: 0x28 - /// Port C Data Register - pub const PORTC = @intToPtr(*volatile u7, 0x28); - - /// address: 0x27 - /// Port C Data Direction Register - pub const DDRC = @intToPtr(*volatile u7, 0x27); - - /// address: 0x26 - /// Port C Input Pins - pub const PINC = @intToPtr(*volatile u7, 0x26); - }; - - /// I/O Port - pub const PORTD = struct { - /// address: 0x2b - /// Port D Data Register - pub const PORTD = @intToPtr(*volatile u8, 0x2b); - - /// address: 0x2a - /// Port D Data Direction Register - pub const DDRD = @intToPtr(*volatile u8, 0x2a); - - /// address: 0x29 - /// Port D Input Pins - pub const PIND = @intToPtr(*volatile u8, 0x29); - }; - - /// Timer/Counter, 8-bit - pub const TC0 = struct { - /// address: 0x48 - /// Timer/Counter0 Output Compare Register - pub const OCR0B = @intToPtr(*volatile u8, 0x48); - - /// address: 0x47 - /// Timer/Counter0 Output Compare Register - pub const OCR0A = @intToPtr(*volatile u8, 0x47); - - /// address: 0x46 - /// Timer/Counter0 - pub const TCNT0 = @intToPtr(*volatile u8, 0x46); - - /// address: 0x45 - /// Timer/Counter Control Register B - pub const TCCR0B = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Select - /// - /// 0x0: No Clock Source (Stopped) - /// 0x1: Running, No Prescaling - /// 0x2: Running, CLK/8 - /// 0x3: Running, CLK/64 - /// 0x4: Running, CLK/256 - /// 0x5: Running, CLK/1024 - /// 0x6: Running, ExtClk Tn Falling Edge - /// 0x7: Running, ExtClk Tn Rising Edge - CS0: u3, - WGM02: u1, - reserved0: u1, - reserved1: u1, - /// Force Output Compare B - FOC0B: u1, - /// Force Output Compare A - FOC0A: u1, - }), 0x45); - - /// address: 0x44 - /// Timer/Counter Control Register A - pub const TCCR0A = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Generation Mode - WGM0: u2, - reserved0: u1, - reserved1: u1, - /// Compare Output Mode, Fast PWm - COM0B: u2, - /// Compare Output Mode, Phase Correct PWM Mode - COM0A: u2, - }), 0x44); - - /// address: 0x6e - /// Timer/Counter0 Interrupt Mask Register - pub const TIMSK0 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter0 Overflow Interrupt Enable - TOIE0: u1, - /// Timer/Counter0 Output Compare Match A Interrupt Enable - OCIE0A: u1, - /// Timer/Counter0 Output Compare Match B Interrupt Enable - OCIE0B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x6e); - - /// address: 0x35 - /// Timer/Counter0 Interrupt Flag register - pub const TIFR0 = @intToPtr(*volatile Mmio(8, packed struct { - /// Timer/Counter0 Overflow Flag - TOV0: u1, - /// Timer/Counter0 Output Compare Flag 0A - OCF0A: u1, - /// Timer/Counter0 Output Compare Flag 0B - OCF0B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x35); - - /// address: 0x43 - /// General Timer/Counter Control Register - pub const GTCCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Prescaler Reset Timer/Counter1 and Timer/Counter0 - PSRSYNC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Timer/Counter Synchronization Mode - TSM: u1, - }), 0x43); - }; - - /// External Interrupts - pub const EXINT = struct { - /// address: 0x69 - /// External Interrupt Control Register - pub const EICRA = @intToPtr(*volatile Mmio(8, packed struct { - /// External Interrupt Sense Control 0 Bits - /// - /// 0x0: Low Level of INTX - /// 0x1: Any Logical Change of INTX - /// 0x2: Falling Edge of INTX - /// 0x3: Rising Edge of INTX - ISC0: u2, - /// External Interrupt Sense Control 1 Bits - /// - /// 0x0: Low Level of INTX - /// 0x1: Any Logical Change of INTX - /// 0x2: Falling Edge of INTX - /// 0x3: Rising Edge of INTX - ISC1: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), 0x69); - - /// address: 0x3d - /// External Interrupt Mask Register - pub const EIMSK = @intToPtr(*volatile Mmio(8, packed struct { - /// External Interrupt Request 1 Enable - INT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), 0x3d); - - /// address: 0x3c - /// External Interrupt Flag Register - pub const EIFR = @intToPtr(*volatile Mmio(8, packed struct { - /// External Interrupt Flags - INTF: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), 0x3c); - - /// address: 0x68 - /// Pin Change Interrupt Control Register - pub const PCICR = @intToPtr(*volatile Mmio(8, packed struct { - /// Pin Change Interrupt Enables - PCIE: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x68); - - /// address: 0x6d - /// Pin Change Mask Register 2 - pub const PCMSK2 = @intToPtr(*volatile Mmio(8, packed struct { - /// Pin Change Enable Masks - PCINT: u8, - }), 0x6d); - - /// address: 0x6c - /// Pin Change Mask Register 1 - pub const PCMSK1 = @intToPtr(*volatile Mmio(8, packed struct { - /// Pin Change Enable Masks - PCINT: u7, - padding0: u1, - }), 0x6c); - - /// address: 0x6b - /// Pin Change Mask Register 0 - pub const PCMSK0 = @intToPtr(*volatile Mmio(8, packed struct { - /// Pin Change Enable Masks - PCINT: u8, - }), 0x6b); - - /// address: 0x3b - /// Pin Change Interrupt Flag Register - pub const PCIFR = @intToPtr(*volatile Mmio(8, packed struct { - /// Pin Change Interrupt Flags - PCIF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), 0x3b); - }; - - /// Serial Peripheral Interface - pub const SPI = struct { - /// address: 0x4e - /// SPI Data Register - pub const SPDR = @intToPtr(*volatile u8, 0x4e); - - /// address: 0x4d - /// SPI Status Register - pub const SPSR = @intToPtr(*volatile Mmio(8, packed struct { - /// Double SPI Speed Bit - SPI2X: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Write Collision Flag - WCOL: u1, - /// SPI Interrupt Flag - SPIF: u1, - }), 0x4d); - - /// address: 0x4c - /// SPI Control Register - pub const SPCR = @intToPtr(*volatile Mmio(8, packed struct { - /// SPI Clock Rate Selects - /// - /// 0x0: fosc/2 or fosc/4 - /// 0x1: fosc/8 or fosc/16 - /// 0x2: fosc/32 or fosc/64 - /// 0x3: fosc/64 or fosc/128 - SPR: u2, - /// Clock Phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master/Slave Select - MSTR: u1, - /// Data Order - DORD: u1, - /// SPI Enable - SPE: u1, - /// SPI Interrupt Enable - SPIE: u1, - }), 0x4c); - }; - - /// Watchdog Timer - pub const WDT = struct { - /// address: 0x60 - /// Watchdog Timer Control Register - pub const WDTCSR = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Watch Dog Enable - WDE: u1, - /// Watchdog Change Enable - WDCE: u1, - reserved3: u1, - /// Watchdog Timeout Interrupt Enable - WDIE: u1, - /// Watchdog Timeout Interrupt Flag - WDIF: u1, - }), 0x60); - }; - - /// CPU Registers - pub const CPU = struct { - /// address: 0x64 - /// Power Reduction Register - pub const PRR = @intToPtr(*volatile Mmio(8, packed struct { - /// Power Reduction ADC - PRADC: u1, - /// Power Reduction USART - PRUSART0: u1, - /// Power Reduction Serial Peripheral Interface - PRSPI: u1, - /// Power Reduction Timer/Counter1 - PRTIM1: u1, - reserved0: u1, - /// Power Reduction Timer/Counter0 - PRTIM0: u1, - /// Power Reduction Timer/Counter2 - PRTIM2: u1, - /// Power Reduction TWI - PRTWI: u1, - }), 0x64); - - /// address: 0x66 - /// Oscillator Calibration Value - pub const OSCCAL = @intToPtr(*volatile u8, 0x66); - - /// address: 0x61 - /// Clock Prescale Register - pub const CLKPR = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Prescaler Select Bits - /// - /// 0x0: 1 - /// 0x1: 2 - /// 0x2: 4 - /// 0x3: 8 - /// 0x4: 16 - /// 0x5: 32 - /// 0x6: 64 - /// 0x7: 128 - /// 0x8: 256 - CLKPS: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Clock Prescaler Change Enable - CLKPCE: u1, - }), 0x61); - - /// address: 0x5f - /// Status Register - pub const SREG = @intToPtr(*volatile Mmio(8, packed struct { - /// Carry Flag - C: u1, - /// Zero Flag - Z: u1, - /// Negative Flag - N: u1, - /// Two's Complement Overflow Flag - V: u1, - /// Sign Bit - S: u1, - /// Half Carry Flag - H: u1, - /// Bit Copy Storage - T: u1, - /// Global Interrupt Enable - I: u1, - }), 0x5f); - - /// address: 0x5d - /// Stack Pointer - pub const SP = @intToPtr(*volatile MmioInt(16, u12), 0x5d); - - /// address: 0x57 - /// Store Program Memory Control and Status Register - pub const SPMCSR = @intToPtr(*volatile Mmio(8, packed struct { - /// Store Program Memory - SPMEN: u1, - /// Page Erase - PGERS: u1, - /// Page Write - PGWRT: u1, - /// Boot Lock Bit Set - BLBSET: u1, - /// Read-While-Write section read enable - RWWSRE: u1, - /// Signature Row Read - SIGRD: u1, - /// Read-While-Write Section Busy - RWWSB: u1, - /// SPM Interrupt Enable - SPMIE: u1, - }), 0x57); - - /// address: 0x55 - /// MCU Control Register - pub const MCUCR = @intToPtr(*volatile Mmio(8, packed struct { - IVCE: u1, - IVSEL: u1, - reserved0: u1, - reserved1: u1, - PUD: u1, - /// BOD Sleep Enable - BODSE: u1, - /// BOD Sleep - BODS: u1, - padding0: u1, - }), 0x55); - - /// address: 0x54 - /// MCU Status Register - pub const MCUSR = @intToPtr(*volatile Mmio(8, packed struct { - /// Power-on reset flag - PORF: u1, - /// External Reset Flag - EXTRF: u1, - /// Brown-out Reset Flag - BORF: u1, - /// Watchdog Reset Flag - WDRF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), 0x54); - - /// address: 0x53 - /// Sleep Mode Control Register - pub const SMCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Sleep Enable - SE: u1, - /// Sleep Mode Select Bits - /// - /// 0x0: Idle - /// 0x1: ADC Noise Reduction (If Available) - /// 0x2: Power Down - /// 0x3: Power Save - /// 0x4: Reserved - /// 0x5: Reserved - /// 0x6: Standby - /// 0x7: Extended Standby - SM: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), 0x53); - - /// address: 0x4b - /// General Purpose I/O Register 2 - pub const GPIOR2 = @intToPtr(*volatile u8, 0x4b); - - /// address: 0x4a - /// General Purpose I/O Register 1 - pub const GPIOR1 = @intToPtr(*volatile u8, 0x4a); - - /// address: 0x3e - /// General Purpose I/O Register 0 - pub const GPIOR0 = @intToPtr(*volatile u8, 0x3e); - }; - - /// EEPROM - pub const EEPROM = struct { - /// address: 0x41 - /// EEPROM Address Register Bytes - pub const EEAR = @intToPtr(*volatile u10, 0x41); - - /// address: 0x40 - /// EEPROM Data Register - pub const EEDR = @intToPtr(*volatile u8, 0x40); - - /// address: 0x3f - /// EEPROM Control Register - pub const EECR = @intToPtr(*volatile Mmio(8, packed struct { - /// EEPROM Read Enable - EERE: u1, - /// EEPROM Write Enable - EEPE: u1, - /// EEPROM Master Write Enable - EEMPE: u1, - /// EEPROM Ready Interrupt Enable - EERIE: u1, - /// EEPROM Programming Mode Bits - /// - /// 0x0: Erase and Write in one operation - /// 0x1: Erase Only - /// 0x2: Write Only - EEPM: u2, - padding0: u1, - padding1: u1, - }), 0x3f); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: *const fn () callconv(.C) void, - Naked: *const fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/atsame51j20a/ATSAME51J20A.svd b/src/modules/chips/atsame51j20a/ATSAME51J20A.svd deleted file mode 100644 index 10353bd..0000000 --- a/src/modules/chips/atsame51j20a/ATSAME51J20A.svd +++ /dev/null @@ -1,45092 +0,0 @@ - - - - Microchip Technology - MCHP - ATSAME51J20A - SAME51 - 0 - Microchip ATSAME51J20A Microcontroller - - CM4 - r0p1 - selectable - true - true - 3 - false - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - AC - U25011.0.0 - Analog Comparators - AC - AC_ - 0x42002000 - - 0 - 0x26 - registers - - - AC - 122 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - write-only - 0x00 - - - START0 - Comparator 0 Start Comparison - 0 - 1 - - - START1 - Comparator 1 Start Comparison - 1 - 1 - - - - - EVCTRL - Event Control - 0x2 - 16 - 0x0000 - - - COMPEO0 - Comparator 0 Event Output Enable - 0 - 1 - - - COMPEO1 - Comparator 1 Event Output Enable - 1 - 1 - - - WINEO0 - Window 0 Event Output Enable - 4 - 1 - - - COMPEI0 - Comparator 0 Event Input Enable - 8 - 1 - - - COMPEI1 - Comparator 1 Event Input Enable - 9 - 1 - - - INVEI0 - Comparator 0 Input Event Invert Enable - 12 - 1 - - - INVEI1 - Comparator 1 Input Event Invert Enable - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - COMP0 - Comparator 0 - 0 - 1 - - - COMP1 - Comparator 1 - 1 - 1 - - - WIN0 - Window 0 - 4 - 1 - - - - - STATUSA - Status A - 0x7 - 8 - read-only - 0x00 - - - STATE0 - Comparator 0 Current State - 0 - 1 - - - STATE1 - Comparator 1 Current State - 1 - 1 - - - WSTATE0 - Window 0 Current State - 4 - 2 - - WSTATE0Select - - ABOVE - Signal is above window - 0 - - - INSIDE - Signal is inside window - 1 - - - BELOW - Signal is below window - 2 - - - - - - - STATUSB - Status B - 0x8 - 8 - read-only - 0x00 - - - READY0 - Comparator 0 Ready - 0 - 1 - - - READY1 - Comparator 1 Ready - 1 - 1 - - - - - DBGCTRL - Debug Control - 0x9 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - WINCTRL - Window Control - 0xA - 8 - 0x00 - - - WEN0 - Window 0 Mode Enable - 0 - 1 - - - WINTSEL0 - Window 0 Interrupt Selection - 1 - 2 - - WINTSEL0Select - - ABOVE - Interrupt on signal above window - 0 - - - INSIDE - Interrupt on signal inside window - 1 - - - BELOW - Interrupt on signal below window - 2 - - - OUTSIDE - Interrupt on signal outside window - 3 - - - - - - - 2 - 1 - SCALER[%s] - Scaler n - 0xC - 8 - 0x00 - - - VALUE - Scaler Value - 0 - 6 - - - - - 2 - 4 - COMPCTRL[%s] - Comparator Control n - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - SINGLE - Single-Shot Mode - 2 - 1 - - - INTSEL - Interrupt Selection - 3 - 2 - - INTSELSelect - - TOGGLE - Interrupt on comparator output toggle - 0 - - - RISING - Interrupt on comparator output rising - 1 - - - FALLING - Interrupt on comparator output falling - 2 - - - EOC - Interrupt on end of comparison (single-shot mode only) - 3 - - - - - RUNSTDBY - Run in Standby - 6 - 1 - - - MUXNEG - Negative Input Mux Selection - 8 - 3 - - MUXNEGSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - GND - Ground - 4 - - - VSCALE - VDD scaler - 5 - - - BANDGAP - Internal bandgap voltage - 6 - - - DAC - DAC output - 7 - - - - - MUXPOS - Positive Input Mux Selection - 12 - 3 - - MUXPOSSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - VSCALE - VDD Scaler - 4 - - - - - SWAP - Swap Inputs and Invert - 15 - 1 - - - SPEED - Speed Selection - 16 - 2 - - SPEEDSelect - - HIGH - High speed - 3 - - - - - HYSTEN - Hysteresis Enable - 19 - 1 - - - HYST - Hysteresis Level - 20 - 2 - - HYSTSelect - - HYST50 - 50mV - 0 - - - HYST100 - 100mV - 1 - - - HYST150 - 150mV - 2 - - - - - FLEN - Filter Length - 24 - 3 - - FLENSelect - - OFF - No filtering - 0 - - - MAJ3 - 3-bit majority function (2 of 3) - 1 - - - MAJ5 - 5-bit majority function (3 of 5) - 2 - - - - - OUT - Output - 28 - 2 - - OUTSelect - - OFF - The output of COMPn is not routed to the COMPn I/O port - 0 - - - ASYNC - The asynchronous output of COMPn is routed to the COMPn I/O port - 1 - - - SYNC - The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port - 2 - - - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - WINCTRL - WINCTRL Synchronization Busy - 2 - 1 - - - COMPCTRL0 - COMPCTRL 0 Synchronization Busy - 3 - 1 - - - COMPCTRL1 - COMPCTRL 1 Synchronization Busy - 4 - 1 - - - - - CALIB - Calibration - 0x24 - 16 - 0x0101 - - - BIAS0 - COMP0/1 Bias Scaling - 0 - 2 - - - - - - - ADC0 - U25001.0.0 - Analog Digital Converter - ADC - ADC_ - 0x43001C00 - - 0 - 0x4A - registers - - - ADC0_OTHER - 118 - - - ADC0_RESRDY - 119 - - - - CTRLA - Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - DUALSEL - Dual Mode Trigger Selection - 3 - 2 - - DUALSELSelect - - BOTH - Start event or software trigger will start a conversion on both ADCs - 0 - - - INTERLEAVE - START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 - 1 - - - - - SLAVEEN - Slave Enable - 5 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - PRESCALER - Prescaler Configuration - 8 - 3 - - PRESCALERSelect - - DIV2 - Peripheral clock divided by 2 - 0 - - - DIV4 - Peripheral clock divided by 4 - 1 - - - DIV8 - Peripheral clock divided by 8 - 2 - - - DIV16 - Peripheral clock divided by 16 - 3 - - - DIV32 - Peripheral clock divided by 32 - 4 - - - DIV64 - Peripheral clock divided by 64 - 5 - - - DIV128 - Peripheral clock divided by 128 - 6 - - - DIV256 - Peripheral clock divided by 256 - 7 - - - - - R2R - Rail to Rail Operation Enable - 15 - 1 - - - - - EVCTRL - Event Control - 0x2 - 8 - 0x00 - - - FLUSHEI - Flush Event Input Enable - 0 - 1 - - - STARTEI - Start Conversion Event Input Enable - 1 - 1 - - - FLUSHINV - Flush Event Invert Enable - 2 - 1 - - - STARTINV - Start Conversion Event Invert Enable - 3 - 1 - - - RESRDYEO - Result Ready Event Out - 4 - 1 - - - WINMONEO - Window Monitor Event Out - 5 - 1 - - - - - DBGCTRL - Debug Control - 0x3 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - INPUTCTRL - Input Control - 0x4 - 16 - 0x0000 - - - MUXPOS - Positive Mux Input Selection - 0 - 5 - - MUXPOSSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - AIN6 - ADC AIN6 Pin - 0x6 - - - AIN7 - ADC AIN7 Pin - 0x7 - - - AIN8 - ADC AIN8 Pin - 0x8 - - - AIN9 - ADC AIN9 Pin - 0x9 - - - AIN10 - ADC AIN10 Pin - 0xA - - - AIN11 - ADC AIN11 Pin - 0xB - - - AIN12 - ADC AIN12 Pin - 0xC - - - AIN13 - ADC AIN13 Pin - 0xD - - - AIN14 - ADC AIN14 Pin - 0xE - - - AIN15 - ADC AIN15 Pin - 0xF - - - AIN16 - ADC AIN16 Pin - 0x10 - - - AIN17 - ADC AIN17 Pin - 0x11 - - - AIN18 - ADC AIN18 Pin - 0x12 - - - AIN19 - ADC AIN19 Pin - 0x13 - - - AIN20 - ADC AIN20 Pin - 0x14 - - - AIN21 - ADC AIN21 Pin - 0x15 - - - AIN22 - ADC AIN22 Pin - 0x16 - - - AIN23 - ADC AIN23 Pin - 0x17 - - - SCALEDCOREVCC - 1/4 Scaled Core Supply - 0x18 - - - SCALEDVBAT - 1/4 Scaled VBAT Supply - 0x19 - - - SCALEDIOVCC - 1/4 Scaled I/O Supply - 0x1A - - - BANDGAP - Bandgap Voltage - 0x1B - - - PTAT - Temperature Sensor TSENSP - 0x1C - - - CTAT - Temperature Sensor TSENSC - 0x1D - - - DAC - DAC Output - 0x1E - - - PTC - PTC output (only on ADC0) - 0x1F - - - - - DIFFMODE - Differential Mode - 7 - 1 - - - MUXNEG - Negative Mux Input Selection - 8 - 5 - - MUXNEGSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - AIN6 - ADC AIN6 Pin - 0x6 - - - AIN7 - ADC AIN7 Pin - 0x7 - - - GND - Internal Ground - 0x18 - - - - - DSEQSTOP - Stop DMA Sequencing - 15 - 1 - - - - - CTRLB - Control B - 0x6 - 16 - 0x0000 - - - LEFTADJ - Left-Adjusted Result - 0 - 1 - - - FREERUN - Free Running Mode - 1 - 1 - - - CORREN - Digital Correction Logic Enable - 2 - 1 - - - RESSEL - Conversion Result Resolution - 3 - 2 - - RESSELSelect - - 12BIT - 12-bit result - 0x0 - - - 16BIT - For averaging mode output - 0x1 - - - 10BIT - 10-bit result - 0x2 - - - 8BIT - 8-bit result - 0x3 - - - - - WINMODE - Window Monitor Mode - 8 - 3 - - WINMODESelect - - DISABLE - No window mode (default) - 0 - - - MODE1 - RESULT > WINLT - 1 - - - MODE2 - RESULT < WINUT - 2 - - - MODE3 - WINLT < RESULT < WINUT - 3 - - - MODE4 - !(WINLT < RESULT < WINUT) - 4 - - - - - WINSS - Window Single Sample - 11 - 1 - - - - - REFCTRL - Reference Control - 0x8 - 8 - 0x00 - - - REFSEL - Reference Selection - 0 - 4 - - REFSELSelect - - INTREF - Internal Bandgap Reference - 0x0 - - - INTVCC0 - 1/2 VDDANA - 0x2 - - - INTVCC1 - VDDANA - 0x3 - - - AREFA - External Reference A - 0x4 - - - AREFB - External Reference B - 0x5 - - - AREFC - External Reference C (only on ADC1) - 0x6 - - - - - REFCOMP - Reference Buffer Offset Compensation Enable - 7 - 1 - - - - - AVGCTRL - Average Control - 0xA - 8 - 0x00 - - - SAMPLENUM - Number of Samples to be Collected - 0 - 4 - - SAMPLENUMSelect - - 1 - 1 sample - 0x0 - - - 2 - 2 samples - 0x1 - - - 4 - 4 samples - 0x2 - - - 8 - 8 samples - 0x3 - - - 16 - 16 samples - 0x4 - - - 32 - 32 samples - 0x5 - - - 64 - 64 samples - 0x6 - - - 128 - 128 samples - 0x7 - - - 256 - 256 samples - 0x8 - - - 512 - 512 samples - 0x9 - - - 1024 - 1024 samples - 0xA - - - - - ADJRES - Adjusting Result / Division Coefficient - 4 - 3 - - - - - SAMPCTRL - Sample Time Control - 0xB - 8 - 0x00 - - - SAMPLEN - Sampling Time Length - 0 - 6 - - - OFFCOMP - Comparator Offset Compensation Enable - 7 - 1 - - - - - WINLT - Window Monitor Lower Threshold - 0xC - 16 - 0x0000 - - - WINLT - Window Lower Threshold - 0 - 16 - - - - - WINUT - Window Monitor Upper Threshold - 0xE - 16 - 0x0000 - - - WINUT - Window Upper Threshold - 0 - 16 - - - - - GAINCORR - Gain Correction - 0x10 - 16 - 0x0000 - - - GAINCORR - Gain Correction Value - 0 - 12 - - - - - OFFSETCORR - Offset Correction - 0x12 - 16 - 0x0000 - - - OFFSETCORR - Offset Correction Value - 0 - 12 - - - - - SWTRIG - Software Trigger - 0x14 - 8 - 0x00 - - - FLUSH - ADC Conversion Flush - 0 - 1 - - - START - Start ADC Conversion - 1 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x2C - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Disable - 0 - 1 - - - OVERRUN - Overrun Interrupt Disable - 1 - 1 - - - WINMON - Window Monitor Interrupt Disable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x2D - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x2E - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Flag - 0 - 1 - - - OVERRUN - Overrun Interrupt Flag - 1 - 1 - - - WINMON - Window Monitor Interrupt Flag - 2 - 1 - - - - - STATUS - Status - 0x2F - 8 - read-only - 0x00 - - - ADCBUSY - ADC Busy Status - 0 - 1 - - - WCC - Window Comparator Counter - 2 - 6 - - - - - SYNCBUSY - Synchronization Busy - 0x30 - 32 - read-only - 0x00000000 - - - SWRST - SWRST Synchronization Busy - 0 - 1 - - - ENABLE - ENABLE Synchronization Busy - 1 - 1 - - - INPUTCTRL - Input Control Synchronization Busy - 2 - 1 - - - CTRLB - Control B Synchronization Busy - 3 - 1 - - - REFCTRL - Reference Control Synchronization Busy - 4 - 1 - - - AVGCTRL - Average Control Synchronization Busy - 5 - 1 - - - SAMPCTRL - Sampling Time Control Synchronization Busy - 6 - 1 - - - WINLT - Window Monitor Lower Threshold Synchronization Busy - 7 - 1 - - - WINUT - Window Monitor Upper Threshold Synchronization Busy - 8 - 1 - - - GAINCORR - Gain Correction Synchronization Busy - 9 - 1 - - - OFFSETCORR - Offset Correction Synchronization Busy - 10 - 1 - - - SWTRIG - Software Trigger Synchronization Busy - 11 - 1 - - - - - DSEQDATA - DMA Sequencial Data - 0x34 - 32 - write-only - 0x00000000 - - - DATA - DMA Sequential Data - 0 - 32 - - - - - DSEQCTRL - DMA Sequential Control - 0x38 - 32 - 0x00000000 - - - INPUTCTRL - Input Control - 0 - 1 - - - CTRLB - Control B - 1 - 1 - - - REFCTRL - Reference Control - 2 - 1 - - - AVGCTRL - Average Control - 3 - 1 - - - SAMPCTRL - Sampling Time Control - 4 - 1 - - - WINLT - Window Monitor Lower Threshold - 5 - 1 - - - WINUT - Window Monitor Upper Threshold - 6 - 1 - - - GAINCORR - Gain Correction - 7 - 1 - - - OFFSETCORR - Offset Correction - 8 - 1 - - - AUTOSTART - ADC Auto-Start Conversion - 31 - 1 - - - - - DSEQSTAT - DMA Sequencial Status - 0x3C - 32 - read-only - 0x00000000 - - - INPUTCTRL - Input Control - 0 - 1 - - - CTRLB - Control B - 1 - 1 - - - REFCTRL - Reference Control - 2 - 1 - - - AVGCTRL - Average Control - 3 - 1 - - - SAMPCTRL - Sampling Time Control - 4 - 1 - - - WINLT - Window Monitor Lower Threshold - 5 - 1 - - - WINUT - Window Monitor Upper Threshold - 6 - 1 - - - GAINCORR - Gain Correction - 7 - 1 - - - OFFSETCORR - Offset Correction - 8 - 1 - - - BUSY - DMA Sequencing Busy - 31 - 1 - - - - - RESULT - Result Conversion Value - 0x40 - 16 - read-only - 0x0000 - - - RESULT - Result Conversion Value - 0 - 16 - - - - - RESS - Last Sample Result - 0x44 - 16 - read-only - 0x0000 - - - RESS - Last ADC conversion result - 0 - 16 - - - - - CALIB - Calibration - 0x48 - 16 - 0x0000 - - - BIASCOMP - Bias Comparator Scaling - 0 - 3 - - - BIASR2R - Bias R2R Ampli scaling - 4 - 3 - - - BIASREFBUF - Bias Reference Buffer Scaling - 8 - 3 - - - - - - - ADC1 - 0x43002000 - - ADC1_OTHER - 120 - - - ADC1_RESRDY - 121 - - - - AES - U22382.2.0 - Advanced Encryption Standard - AES - AES_ - 0x42002400 - - 0 - 0x88 - registers - - - AES - 130 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - AESMODE - AES Modes of operation - 2 - 3 - - AESMODESelect - - ECB - Electronic code book mode - 0x0 - - - CBC - Cipher block chaining mode - 0x1 - - - OFB - Output feedback mode - 0x2 - - - CFB - Cipher feedback mode - 0x3 - - - COUNTER - Counter mode - 0x4 - - - CCM - CCM mode - 0x5 - - - GCM - Galois counter mode - 0x6 - - - - - CFBS - Cipher Feedback Block Size - 5 - 3 - - CFBSSelect - - 128BIT - 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode - 0x0 - - - 64BIT - 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode - 0x1 - - - 32BIT - 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode - 0x2 - - - 16BIT - 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode - 0x3 - - - 8BIT - 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode - 0x4 - - - - - KEYSIZE - Encryption Key Size - 8 - 2 - - KEYSIZESelect - - 128BIT - 128-bit Key for Encryption / Decryption - 0x0 - - - 192BIT - 192-bit Key for Encryption / Decryption - 0x1 - - - 256BIT - 256-bit Key for Encryption / Decryption - 0x2 - - - - - CIPHER - Cipher Mode - 10 - 1 - - CIPHERSelect - - DEC - Decryption - 0x0 - - - ENC - Encryption - 0x1 - - - - - STARTMODE - Start Mode Select - 11 - 1 - - STARTMODESelect - - MANUAL - Start Encryption / Decryption in Manual mode - 0x0 - - - AUTO - Start Encryption / Decryption in Auto mode - 0x1 - - - - - LOD - Last Output Data Mode - 12 - 1 - - LODSelect - - NONE - No effect - 0x0 - - - LAST - Start encryption in Last Output Data mode - 0x1 - - - - - KEYGEN - Last Key Generation - 13 - 1 - - KEYGENSelect - - NONE - No effect - 0x0 - - - LAST - Start Computation of the last NK words of the expanded key - 0x1 - - - - - XORKEY - XOR Key Operation - 14 - 1 - - XORKEYSelect - - NONE - No effect - 0x0 - - - XOR - The user keyword gets XORed with the previous keyword register content. - 0x1 - - - - - CTYPE - Counter Measure Type - 16 - 4 - - - - - CTRLB - Control B - 0x4 - 8 - 0x00 - - - START - Start Encryption/Decryption - 0 - 1 - - - NEWMSG - New message - 1 - 1 - - - EOM - End of message - 2 - 1 - - - GFMUL - GF Multiplication - 3 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x5 - 8 - 0x00 - - - ENCCMP - Encryption Complete Interrupt Enable - 0 - 1 - - - GFMCMP - GF Multiplication Complete Interrupt Enable - 1 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x6 - 8 - 0x00 - - - ENCCMP - Encryption Complete Interrupt Enable - 0 - 1 - - - GFMCMP - GF Multiplication Complete Interrupt Enable - 1 - 1 - - - - - INTFLAG - Interrupt Flag Status - 0x7 - 8 - 0x00 - - - ENCCMP - Encryption Complete - 0 - 1 - - - GFMCMP - GF Multiplication Complete - 1 - 1 - - - - - DATABUFPTR - Data buffer pointer - 0x8 - 8 - 0x00 - - - INDATAPTR - Input Data Pointer - 0 - 2 - - - - - DBGCTRL - Debug control - 0x9 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - 8 - 4 - KEYWORD[%s] - Keyword n - 0xC - 32 - write-only - 0x00000000 - - - INDATA - Indata - 0x38 - 32 - 0x00000000 - - - 4 - 4 - INTVECTV[%s] - Initialisation Vector n - 0x3C - 32 - write-only - 0x00000000 - - - 4 - 4 - HASHKEY[%s] - Hash key n - 0x5C - 32 - 0x00000000 - - - 4 - 4 - GHASH[%s] - Galois Hash n - 0x6C - 32 - 0x00000000 - - - CIPLEN - Cipher Length - 0x80 - 32 - 0x00000000 - - - RANDSEED - Random Seed - 0x84 - 32 - 0x00000000 - - - - - CAN0 - U20033.2.1 - Control Area Network - CAN - CAN_ - 0x42000000 - - 0 - 0xFC - registers - - - CAN0 - 78 - - - - CREL - Core Release - 0x0 - 32 - read-only - 0x32100000 - - - SUBSTEP - Sub-step of Core Release - 20 - 4 - - - STEP - Step of Core Release - 24 - 4 - - - REL - Core Release - 28 - 4 - - - - - ENDN - Endian - 0x4 - 32 - read-only - 0x87654321 - - - ETV - Endianness Test Value - 0 - 32 - - - - - MRCFG - Message RAM Configuration - 0x8 - 32 - 0x00000002 - - - QOS - Quality of Service - 0 - 2 - - QOSSelect - - DISABLE - Background (no sensitive operation) - 0 - - - LOW - Sensitive Bandwidth - 1 - - - MEDIUM - Sensitive Latency - 2 - - - HIGH - Critical Latency - 3 - - - - - - - DBTP - Fast Bit Timing and Prescaler - 0xC - 32 - 0x00000A33 - - - DSJW - Data (Re)Synchronization Jump Width - 0 - 4 - - - DTSEG2 - Data time segment after sample point - 4 - 4 - - - DTSEG1 - Data time segment before sample point - 8 - 5 - - - DBRP - Data Baud Rate Prescaler - 16 - 5 - - - TDC - Tranceiver Delay Compensation - 23 - 1 - - - - - TEST - Test - 0x10 - 32 - 0x00000000 - - - LBCK - Loop Back Mode - 4 - 1 - - - TX - Control of Transmit Pin - 5 - 2 - - TXSelect - - CORE - TX controlled by CAN core - 0 - - - SAMPLE - TX monitoring sample point - 1 - - - DOMINANT - Dominant (0) level at pin CAN_TX - 2 - - - RECESSIVE - Recessive (1) level at pin CAN_TX - 3 - - - - - RX - Receive Pin - 7 - 1 - - - - - RWD - RAM Watchdog - 0x14 - 32 - 0x00000000 - - - WDC - Watchdog Configuration - 0 - 8 - - - WDV - Watchdog Value - 8 - 8 - - - - - CCCR - CC Control - 0x18 - 32 - 0x00000001 - - - INIT - Initialization - 0 - 1 - - - CCE - Configuration Change Enable - 1 - 1 - - - ASM - ASM Restricted Operation Mode - 2 - 1 - - - CSA - Clock Stop Acknowledge - 3 - 1 - - - CSR - Clock Stop Request - 4 - 1 - - - MON - Bus Monitoring Mode - 5 - 1 - - - DAR - Disable Automatic Retransmission - 6 - 1 - - - TEST - Test Mode Enable - 7 - 1 - - - FDOE - FD Operation Enable - 8 - 1 - - - BRSE - Bit Rate Switch Enable - 9 - 1 - - - PXHD - Protocol Exception Handling Disable - 12 - 1 - - - EFBI - Edge Filtering during Bus Integration - 13 - 1 - - - TXP - Transmit Pause - 14 - 1 - - - NISO - Non ISO Operation - 15 - 1 - - - - - NBTP - Nominal Bit Timing and Prescaler - 0x1C - 32 - 0x06000A03 - - - NTSEG2 - Nominal Time segment after sample point - 0 - 7 - - - NTSEG1 - Nominal Time segment before sample point - 8 - 8 - - - NBRP - Nominal Baud Rate Prescaler - 16 - 9 - - - NSJW - Nominal (Re)Synchronization Jump Width - 25 - 7 - - - - - TSCC - Timestamp Counter Configuration - 0x20 - 32 - 0x00000000 - - - TSS - Timestamp Select - 0 - 2 - - TSSSelect - - ZERO - Timestamp counter value always 0x0000 - 0 - - - INC - Timestamp counter value incremented by TCP - 1 - - - EXT - External timestamp counter value used - 2 - - - - - TCP - Timestamp Counter Prescaler - 16 - 4 - - - - - TSCV - Timestamp Counter Value - 0x24 - 32 - read-only - 0x00000000 - - - TSC - Timestamp Counter - 0 - 16 - - - - - TOCC - Timeout Counter Configuration - 0x28 - 32 - 0xFFFF0000 - - - ETOC - Enable Timeout Counter - 0 - 1 - - - TOS - Timeout Select - 1 - 2 - - TOSSelect - - CONT - Continuout operation - 0 - - - TXEF - Timeout controlled by TX Event FIFO - 1 - - - RXF0 - Timeout controlled by Rx FIFO 0 - 2 - - - RXF1 - Timeout controlled by Rx FIFO 1 - 3 - - - - - TOP - Timeout Period - 16 - 16 - - - - - TOCV - Timeout Counter Value - 0x2C - 32 - 0x0000FFFF - - - TOC - Timeout Counter - 0 - 16 - - - - - ECR - Error Counter - 0x40 - 32 - read-only - 0x00000000 - - - TEC - Transmit Error Counter - 0 - 8 - - - REC - Receive Error Counter - 8 - 7 - - - RP - Receive Error Passive - 15 - 1 - - - CEL - CAN Error Logging - 16 - 8 - - - - - PSR - Protocol Status - 0x44 - 32 - read-only - 0x00000707 - - - LEC - Last Error Code - 0 - 3 - - LECSelect - - NONE - No Error - 0 - - - STUFF - Stuff Error - 1 - - - FORM - Form Error - 2 - - - ACK - Ack Error - 3 - - - BIT1 - Bit1 Error - 4 - - - BIT0 - Bit0 Error - 5 - - - CRC - CRC Error - 6 - - - NC - No Change - 7 - - - - - ACT - Activity - 3 - 2 - - ACTSelect - - SYNC - Node is synchronizing on CAN communication - 0 - - - IDLE - Node is neither receiver nor transmitter - 1 - - - RX - Node is operating as receiver - 2 - - - TX - Node is operating as transmitter - 3 - - - - - EP - Error Passive - 5 - 1 - - - EW - Warning Status - 6 - 1 - - - BO - Bus_Off Status - 7 - 1 - - - DLEC - Data Phase Last Error Code - 8 - 3 - - DLECSelect - - NONE - No Error - 0 - - - STUFF - Stuff Error - 1 - - - FORM - Form Error - 2 - - - ACK - Ack Error - 3 - - - BIT1 - Bit1 Error - 4 - - - BIT0 - Bit0 Error - 5 - - - CRC - CRC Error - 6 - - - NC - No Change - 7 - - - - - RESI - ESI flag of last received CAN FD Message - 11 - 1 - - - RBRS - BRS flag of last received CAN FD Message - 12 - 1 - - - RFDF - Received a CAN FD Message - 13 - 1 - - - PXE - Protocol Exception Event - 14 - 1 - - - TDCV - Transmitter Delay Compensation Value - 16 - 7 - - - - - TDCR - Extended ID Filter Configuration - 0x48 - 32 - 0x00000000 - - - TDCF - Transmitter Delay Compensation Filter Length - 0 - 7 - - - TDCO - Transmitter Delay Compensation Offset - 8 - 7 - - - - - IR - Interrupt - 0x50 - 32 - 0x00000000 - - - RF0N - Rx FIFO 0 New Message - 0 - 1 - - - RF0W - Rx FIFO 0 Watermark Reached - 1 - 1 - - - RF0F - Rx FIFO 0 Full - 2 - 1 - - - RF0L - Rx FIFO 0 Message Lost - 3 - 1 - - - RF1N - Rx FIFO 1 New Message - 4 - 1 - - - RF1W - Rx FIFO 1 Watermark Reached - 5 - 1 - - - RF1F - Rx FIFO 1 FIFO Full - 6 - 1 - - - RF1L - Rx FIFO 1 Message Lost - 7 - 1 - - - HPM - High Priority Message - 8 - 1 - - - TC - Timestamp Completed - 9 - 1 - - - TCF - Transmission Cancellation Finished - 10 - 1 - - - TFE - Tx FIFO Empty - 11 - 1 - - - TEFN - Tx Event FIFO New Entry - 12 - 1 - - - TEFW - Tx Event FIFO Watermark Reached - 13 - 1 - - - TEFF - Tx Event FIFO Full - 14 - 1 - - - TEFL - Tx Event FIFO Element Lost - 15 - 1 - - - TSW - Timestamp Wraparound - 16 - 1 - - - MRAF - Message RAM Access Failure - 17 - 1 - - - TOO - Timeout Occurred - 18 - 1 - - - DRX - Message stored to Dedicated Rx Buffer - 19 - 1 - - - BEC - Bit Error Corrected - 20 - 1 - - - BEU - Bit Error Uncorrected - 21 - 1 - - - ELO - Error Logging Overflow - 22 - 1 - - - EP - Error Passive - 23 - 1 - - - EW - Warning Status - 24 - 1 - - - BO - Bus_Off Status - 25 - 1 - - - WDI - Watchdog Interrupt - 26 - 1 - - - PEA - Protocol Error in Arbitration Phase - 27 - 1 - - - PED - Protocol Error in Data Phase - 28 - 1 - - - ARA - Access to Reserved Address - 29 - 1 - - - - - IE - Interrupt Enable - 0x54 - 32 - 0x00000000 - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - - - RF1FE - Rx FIFO 1 FIFO Full Interrupt Enable - 6 - 1 - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - - - TCE - Timestamp Completed Interrupt Enable - 9 - 1 - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - - - TEFLE - Tx Event FIFO Element Lost Interrupt Enable - 15 - 1 - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - - - EPE - Error Passive Interrupt Enable - 23 - 1 - - - EWE - Warning Status Interrupt Enable - 24 - 1 - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - - - WDIE - Watchdog Interrupt Interrupt Enable - 26 - 1 - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - - - ARAE - Access to Reserved Address Enable - 29 - 1 - - - - - ILS - Interrupt Line Select - 0x58 - 32 - 0x00000000 - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - - - RF1FL - Rx FIFO 1 FIFO Full Interrupt Line - 6 - 1 - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - - - HPML - High Priority Message Interrupt Line - 8 - 1 - - - TCL - Timestamp Completed Interrupt Line - 9 - 1 - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - - - TEFLL - Tx Event FIFO Element Lost Interrupt Line - 15 - 1 - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - - - EPL - Error Passive Interrupt Line - 23 - 1 - - - EWL - Warning Status Interrupt Line - 24 - 1 - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - - - WDIL - Watchdog Interrupt Interrupt Line - 26 - 1 - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - - - ARAL - Access to Reserved Address Line - 29 - 1 - - - - - ILE - Interrupt Line Enable - 0x5C - 32 - 0x00000000 - - - EINT0 - Enable Interrupt Line 0 - 0 - 1 - - - EINT1 - Enable Interrupt Line 1 - 1 - 1 - - - - - GFC - Global Filter Configuration - 0x80 - 32 - 0x00000000 - - - RRFE - Reject Remote Frames Extended - 0 - 1 - - - RRFS - Reject Remote Frames Standard - 1 - 1 - - - ANFE - Accept Non-matching Frames Extended - 2 - 2 - - ANFESelect - - RXF0 - Accept in Rx FIFO 0 - 0 - - - RXF1 - Accept in Rx FIFO 1 - 1 - - - REJECT - Reject - 2 - - - - - ANFS - Accept Non-matching Frames Standard - 4 - 2 - - ANFSSelect - - RXF0 - Accept in Rx FIFO 0 - 0 - - - RXF1 - Accept in Rx FIFO 1 - 1 - - - REJECT - Reject - 2 - - - - - - - SIDFC - Standard ID Filter Configuration - 0x84 - 32 - 0x00000000 - - - FLSSA - Filter List Standard Start Address - 0 - 16 - - - LSS - List Size Standard - 16 - 8 - - - - - XIDFC - Extended ID Filter Configuration - 0x88 - 32 - 0x00000000 - - - FLESA - Filter List Extended Start Address - 0 - 16 - - - LSE - List Size Extended - 16 - 7 - - - - - XIDAM - Extended ID AND Mask - 0x90 - 32 - 0x1FFFFFFF - - - EIDM - Extended ID Mask - 0 - 29 - - - - - HPMS - High Priority Message Status - 0x94 - 32 - read-only - 0x00000000 - - - BIDX - Buffer Index - 0 - 6 - - - MSI - Message Storage Indicator - 6 - 2 - - MSISelect - - NONE - No FIFO selected - 0 - - - LOST - FIFO message lost - 1 - - - FIFO0 - Message stored in FIFO 0 - 2 - - - FIFO1 - Message stored in FIFO 1 - 3 - - - - - FIDX - Filter Index - 8 - 7 - - - FLST - Filter List - 15 - 1 - - - - - NDAT1 - New Data 1 - 0x98 - 32 - 0x00000000 - - - ND0 - New Data 0 - 0 - 1 - - - ND1 - New Data 1 - 1 - 1 - - - ND2 - New Data 2 - 2 - 1 - - - ND3 - New Data 3 - 3 - 1 - - - ND4 - New Data 4 - 4 - 1 - - - ND5 - New Data 5 - 5 - 1 - - - ND6 - New Data 6 - 6 - 1 - - - ND7 - New Data 7 - 7 - 1 - - - ND8 - New Data 8 - 8 - 1 - - - ND9 - New Data 9 - 9 - 1 - - - ND10 - New Data 10 - 10 - 1 - - - ND11 - New Data 11 - 11 - 1 - - - ND12 - New Data 12 - 12 - 1 - - - ND13 - New Data 13 - 13 - 1 - - - ND14 - New Data 14 - 14 - 1 - - - ND15 - New Data 15 - 15 - 1 - - - ND16 - New Data 16 - 16 - 1 - - - ND17 - New Data 17 - 17 - 1 - - - ND18 - New Data 18 - 18 - 1 - - - ND19 - New Data 19 - 19 - 1 - - - ND20 - New Data 20 - 20 - 1 - - - ND21 - New Data 21 - 21 - 1 - - - ND22 - New Data 22 - 22 - 1 - - - ND23 - New Data 23 - 23 - 1 - - - ND24 - New Data 24 - 24 - 1 - - - ND25 - New Data 25 - 25 - 1 - - - ND26 - New Data 26 - 26 - 1 - - - ND27 - New Data 27 - 27 - 1 - - - ND28 - New Data 28 - 28 - 1 - - - ND29 - New Data 29 - 29 - 1 - - - ND30 - New Data 30 - 30 - 1 - - - ND31 - New Data 31 - 31 - 1 - - - - - NDAT2 - New Data 2 - 0x9C - 32 - 0x00000000 - - - ND32 - New Data 32 - 0 - 1 - - - ND33 - New Data 33 - 1 - 1 - - - ND34 - New Data 34 - 2 - 1 - - - ND35 - New Data 35 - 3 - 1 - - - ND36 - New Data 36 - 4 - 1 - - - ND37 - New Data 37 - 5 - 1 - - - ND38 - New Data 38 - 6 - 1 - - - ND39 - New Data 39 - 7 - 1 - - - ND40 - New Data 40 - 8 - 1 - - - ND41 - New Data 41 - 9 - 1 - - - ND42 - New Data 42 - 10 - 1 - - - ND43 - New Data 43 - 11 - 1 - - - ND44 - New Data 44 - 12 - 1 - - - ND45 - New Data 45 - 13 - 1 - - - ND46 - New Data 46 - 14 - 1 - - - ND47 - New Data 47 - 15 - 1 - - - ND48 - New Data 48 - 16 - 1 - - - ND49 - New Data 49 - 17 - 1 - - - ND50 - New Data 50 - 18 - 1 - - - ND51 - New Data 51 - 19 - 1 - - - ND52 - New Data 52 - 20 - 1 - - - ND53 - New Data 53 - 21 - 1 - - - ND54 - New Data 54 - 22 - 1 - - - ND55 - New Data 55 - 23 - 1 - - - ND56 - New Data 56 - 24 - 1 - - - ND57 - New Data 57 - 25 - 1 - - - ND58 - New Data 58 - 26 - 1 - - - ND59 - New Data 59 - 27 - 1 - - - ND60 - New Data 60 - 28 - 1 - - - ND61 - New Data 61 - 29 - 1 - - - ND62 - New Data 62 - 30 - 1 - - - ND63 - New Data 63 - 31 - 1 - - - - - RXF0C - Rx FIFO 0 Configuration - 0xA0 - 32 - 0x00000000 - - - F0SA - Rx FIFO 0 Start Address - 0 - 16 - - - F0S - Rx FIFO 0 Size - 16 - 7 - - - F0WM - Rx FIFO 0 Watermark - 24 - 7 - - - F0OM - FIFO 0 Operation Mode - 31 - 1 - - - - - RXF0S - Rx FIFO 0 Status - 0xA4 - 32 - read-only - 0x00000000 - - - F0FL - Rx FIFO 0 Fill Level - 0 - 7 - - - F0GI - Rx FIFO 0 Get Index - 8 - 6 - - - F0PI - Rx FIFO 0 Put Index - 16 - 6 - - - F0F - Rx FIFO 0 Full - 24 - 1 - - - RF0L - Rx FIFO 0 Message Lost - 25 - 1 - - - - - RXF0A - Rx FIFO 0 Acknowledge - 0xA8 - 32 - 0x00000000 - - - F0AI - Rx FIFO 0 Acknowledge Index - 0 - 6 - - - - - RXBC - Rx Buffer Configuration - 0xAC - 32 - 0x00000000 - - - RBSA - Rx Buffer Start Address - 0 - 16 - - - - - RXF1C - Rx FIFO 1 Configuration - 0xB0 - 32 - 0x00000000 - - - F1SA - Rx FIFO 1 Start Address - 0 - 16 - - - F1S - Rx FIFO 1 Size - 16 - 7 - - - F1WM - Rx FIFO 1 Watermark - 24 - 7 - - - F1OM - FIFO 1 Operation Mode - 31 - 1 - - - - - RXF1S - Rx FIFO 1 Status - 0xB4 - 32 - read-only - 0x00000000 - - - F1FL - Rx FIFO 1 Fill Level - 0 - 7 - - - F1GI - Rx FIFO 1 Get Index - 8 - 6 - - - F1PI - Rx FIFO 1 Put Index - 16 - 6 - - - F1F - Rx FIFO 1 Full - 24 - 1 - - - RF1L - Rx FIFO 1 Message Lost - 25 - 1 - - - DMS - Debug Message Status - 30 - 2 - - DMSSelect - - IDLE - Idle state - 0 - - - DBGA - Debug message A received - 1 - - - DBGB - Debug message A/B received - 2 - - - DBGC - Debug message A/B/C received, DMA request set - 3 - - - - - - - RXF1A - Rx FIFO 1 Acknowledge - 0xB8 - 32 - 0x00000000 - - - F1AI - Rx FIFO 1 Acknowledge Index - 0 - 6 - - - - - RXESC - Rx Buffer / FIFO Element Size Configuration - 0xBC - 32 - 0x00000000 - - - F0DS - Rx FIFO 0 Data Field Size - 0 - 3 - - F0DSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - F1DS - Rx FIFO 1 Data Field Size - 4 - 3 - - F1DSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - RBDS - Rx Buffer Data Field Size - 8 - 3 - - RBDSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - - - TXBC - Tx Buffer Configuration - 0xC0 - 32 - 0x00000000 - - - TBSA - Tx Buffers Start Address - 0 - 16 - - - NDTB - Number of Dedicated Transmit Buffers - 16 - 6 - - - TFQS - Transmit FIFO/Queue Size - 24 - 6 - - - TFQM - Tx FIFO/Queue Mode - 30 - 1 - - - - - TXFQS - Tx FIFO / Queue Status - 0xC4 - 32 - read-only - 0x00000000 - - - TFFL - Tx FIFO Free Level - 0 - 6 - - - TFGI - Tx FIFO Get Index - 8 - 5 - - - TFQPI - Tx FIFO/Queue Put Index - 16 - 5 - - - TFQF - Tx FIFO/Queue Full - 21 - 1 - - - - - TXESC - Tx Buffer Element Size Configuration - 0xC8 - 32 - 0x00000000 - - - TBDS - Tx Buffer Data Field Size - 0 - 3 - - TBDSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - - - TXBRP - Tx Buffer Request Pending - 0xCC - 32 - read-only - 0x00000000 - - - TRP0 - Transmission Request Pending 0 - 0 - 1 - - - TRP1 - Transmission Request Pending 1 - 1 - 1 - - - TRP2 - Transmission Request Pending 2 - 2 - 1 - - - TRP3 - Transmission Request Pending 3 - 3 - 1 - - - TRP4 - Transmission Request Pending 4 - 4 - 1 - - - TRP5 - Transmission Request Pending 5 - 5 - 1 - - - TRP6 - Transmission Request Pending 6 - 6 - 1 - - - TRP7 - Transmission Request Pending 7 - 7 - 1 - - - TRP8 - Transmission Request Pending 8 - 8 - 1 - - - TRP9 - Transmission Request Pending 9 - 9 - 1 - - - TRP10 - Transmission Request Pending 10 - 10 - 1 - - - TRP11 - Transmission Request Pending 11 - 11 - 1 - - - TRP12 - Transmission Request Pending 12 - 12 - 1 - - - TRP13 - Transmission Request Pending 13 - 13 - 1 - - - TRP14 - Transmission Request Pending 14 - 14 - 1 - - - TRP15 - Transmission Request Pending 15 - 15 - 1 - - - TRP16 - Transmission Request Pending 16 - 16 - 1 - - - TRP17 - Transmission Request Pending 17 - 17 - 1 - - - TRP18 - Transmission Request Pending 18 - 18 - 1 - - - TRP19 - Transmission Request Pending 19 - 19 - 1 - - - TRP20 - Transmission Request Pending 20 - 20 - 1 - - - TRP21 - Transmission Request Pending 21 - 21 - 1 - - - TRP22 - Transmission Request Pending 22 - 22 - 1 - - - TRP23 - Transmission Request Pending 23 - 23 - 1 - - - TRP24 - Transmission Request Pending 24 - 24 - 1 - - - TRP25 - Transmission Request Pending 25 - 25 - 1 - - - TRP26 - Transmission Request Pending 26 - 26 - 1 - - - TRP27 - Transmission Request Pending 27 - 27 - 1 - - - TRP28 - Transmission Request Pending 28 - 28 - 1 - - - TRP29 - Transmission Request Pending 29 - 29 - 1 - - - TRP30 - Transmission Request Pending 30 - 30 - 1 - - - TRP31 - Transmission Request Pending 31 - 31 - 1 - - - - - TXBAR - Tx Buffer Add Request - 0xD0 - 32 - 0x00000000 - - - AR0 - Add Request 0 - 0 - 1 - - - AR1 - Add Request 1 - 1 - 1 - - - AR2 - Add Request 2 - 2 - 1 - - - AR3 - Add Request 3 - 3 - 1 - - - AR4 - Add Request 4 - 4 - 1 - - - AR5 - Add Request 5 - 5 - 1 - - - AR6 - Add Request 6 - 6 - 1 - - - AR7 - Add Request 7 - 7 - 1 - - - AR8 - Add Request 8 - 8 - 1 - - - AR9 - Add Request 9 - 9 - 1 - - - AR10 - Add Request 10 - 10 - 1 - - - AR11 - Add Request 11 - 11 - 1 - - - AR12 - Add Request 12 - 12 - 1 - - - AR13 - Add Request 13 - 13 - 1 - - - AR14 - Add Request 14 - 14 - 1 - - - AR15 - Add Request 15 - 15 - 1 - - - AR16 - Add Request 16 - 16 - 1 - - - AR17 - Add Request 17 - 17 - 1 - - - AR18 - Add Request 18 - 18 - 1 - - - AR19 - Add Request 19 - 19 - 1 - - - AR20 - Add Request 20 - 20 - 1 - - - AR21 - Add Request 21 - 21 - 1 - - - AR22 - Add Request 22 - 22 - 1 - - - AR23 - Add Request 23 - 23 - 1 - - - AR24 - Add Request 24 - 24 - 1 - - - AR25 - Add Request 25 - 25 - 1 - - - AR26 - Add Request 26 - 26 - 1 - - - AR27 - Add Request 27 - 27 - 1 - - - AR28 - Add Request 28 - 28 - 1 - - - AR29 - Add Request 29 - 29 - 1 - - - AR30 - Add Request 30 - 30 - 1 - - - AR31 - Add Request 31 - 31 - 1 - - - - - TXBCR - Tx Buffer Cancellation Request - 0xD4 - 32 - 0x00000000 - - - CR0 - Cancellation Request 0 - 0 - 1 - - - CR1 - Cancellation Request 1 - 1 - 1 - - - CR2 - Cancellation Request 2 - 2 - 1 - - - CR3 - Cancellation Request 3 - 3 - 1 - - - CR4 - Cancellation Request 4 - 4 - 1 - - - CR5 - Cancellation Request 5 - 5 - 1 - - - CR6 - Cancellation Request 6 - 6 - 1 - - - CR7 - Cancellation Request 7 - 7 - 1 - - - CR8 - Cancellation Request 8 - 8 - 1 - - - CR9 - Cancellation Request 9 - 9 - 1 - - - CR10 - Cancellation Request 10 - 10 - 1 - - - CR11 - Cancellation Request 11 - 11 - 1 - - - CR12 - Cancellation Request 12 - 12 - 1 - - - CR13 - Cancellation Request 13 - 13 - 1 - - - CR14 - Cancellation Request 14 - 14 - 1 - - - CR15 - Cancellation Request 15 - 15 - 1 - - - CR16 - Cancellation Request 16 - 16 - 1 - - - CR17 - Cancellation Request 17 - 17 - 1 - - - CR18 - Cancellation Request 18 - 18 - 1 - - - CR19 - Cancellation Request 19 - 19 - 1 - - - CR20 - Cancellation Request 20 - 20 - 1 - - - CR21 - Cancellation Request 21 - 21 - 1 - - - CR22 - Cancellation Request 22 - 22 - 1 - - - CR23 - Cancellation Request 23 - 23 - 1 - - - CR24 - Cancellation Request 24 - 24 - 1 - - - CR25 - Cancellation Request 25 - 25 - 1 - - - CR26 - Cancellation Request 26 - 26 - 1 - - - CR27 - Cancellation Request 27 - 27 - 1 - - - CR28 - Cancellation Request 28 - 28 - 1 - - - CR29 - Cancellation Request 29 - 29 - 1 - - - CR30 - Cancellation Request 30 - 30 - 1 - - - CR31 - Cancellation Request 31 - 31 - 1 - - - - - TXBTO - Tx Buffer Transmission Occurred - 0xD8 - 32 - read-only - 0x00000000 - - - TO0 - Transmission Occurred 0 - 0 - 1 - - - TO1 - Transmission Occurred 1 - 1 - 1 - - - TO2 - Transmission Occurred 2 - 2 - 1 - - - TO3 - Transmission Occurred 3 - 3 - 1 - - - TO4 - Transmission Occurred 4 - 4 - 1 - - - TO5 - Transmission Occurred 5 - 5 - 1 - - - TO6 - Transmission Occurred 6 - 6 - 1 - - - TO7 - Transmission Occurred 7 - 7 - 1 - - - TO8 - Transmission Occurred 8 - 8 - 1 - - - TO9 - Transmission Occurred 9 - 9 - 1 - - - TO10 - Transmission Occurred 10 - 10 - 1 - - - TO11 - Transmission Occurred 11 - 11 - 1 - - - TO12 - Transmission Occurred 12 - 12 - 1 - - - TO13 - Transmission Occurred 13 - 13 - 1 - - - TO14 - Transmission Occurred 14 - 14 - 1 - - - TO15 - Transmission Occurred 15 - 15 - 1 - - - TO16 - Transmission Occurred 16 - 16 - 1 - - - TO17 - Transmission Occurred 17 - 17 - 1 - - - TO18 - Transmission Occurred 18 - 18 - 1 - - - TO19 - Transmission Occurred 19 - 19 - 1 - - - TO20 - Transmission Occurred 20 - 20 - 1 - - - TO21 - Transmission Occurred 21 - 21 - 1 - - - TO22 - Transmission Occurred 22 - 22 - 1 - - - TO23 - Transmission Occurred 23 - 23 - 1 - - - TO24 - Transmission Occurred 24 - 24 - 1 - - - TO25 - Transmission Occurred 25 - 25 - 1 - - - TO26 - Transmission Occurred 26 - 26 - 1 - - - TO27 - Transmission Occurred 27 - 27 - 1 - - - TO28 - Transmission Occurred 28 - 28 - 1 - - - TO29 - Transmission Occurred 29 - 29 - 1 - - - TO30 - Transmission Occurred 30 - 30 - 1 - - - TO31 - Transmission Occurred 31 - 31 - 1 - - - - - TXBCF - Tx Buffer Cancellation Finished - 0xDC - 32 - read-only - 0x00000000 - - - CF0 - Tx Buffer Cancellation Finished 0 - 0 - 1 - - - CF1 - Tx Buffer Cancellation Finished 1 - 1 - 1 - - - CF2 - Tx Buffer Cancellation Finished 2 - 2 - 1 - - - CF3 - Tx Buffer Cancellation Finished 3 - 3 - 1 - - - CF4 - Tx Buffer Cancellation Finished 4 - 4 - 1 - - - CF5 - Tx Buffer Cancellation Finished 5 - 5 - 1 - - - CF6 - Tx Buffer Cancellation Finished 6 - 6 - 1 - - - CF7 - Tx Buffer Cancellation Finished 7 - 7 - 1 - - - CF8 - Tx Buffer Cancellation Finished 8 - 8 - 1 - - - CF9 - Tx Buffer Cancellation Finished 9 - 9 - 1 - - - CF10 - Tx Buffer Cancellation Finished 10 - 10 - 1 - - - CF11 - Tx Buffer Cancellation Finished 11 - 11 - 1 - - - CF12 - Tx Buffer Cancellation Finished 12 - 12 - 1 - - - CF13 - Tx Buffer Cancellation Finished 13 - 13 - 1 - - - CF14 - Tx Buffer Cancellation Finished 14 - 14 - 1 - - - CF15 - Tx Buffer Cancellation Finished 15 - 15 - 1 - - - CF16 - Tx Buffer Cancellation Finished 16 - 16 - 1 - - - CF17 - Tx Buffer Cancellation Finished 17 - 17 - 1 - - - CF18 - Tx Buffer Cancellation Finished 18 - 18 - 1 - - - CF19 - Tx Buffer Cancellation Finished 19 - 19 - 1 - - - CF20 - Tx Buffer Cancellation Finished 20 - 20 - 1 - - - CF21 - Tx Buffer Cancellation Finished 21 - 21 - 1 - - - CF22 - Tx Buffer Cancellation Finished 22 - 22 - 1 - - - CF23 - Tx Buffer Cancellation Finished 23 - 23 - 1 - - - CF24 - Tx Buffer Cancellation Finished 24 - 24 - 1 - - - CF25 - Tx Buffer Cancellation Finished 25 - 25 - 1 - - - CF26 - Tx Buffer Cancellation Finished 26 - 26 - 1 - - - CF27 - Tx Buffer Cancellation Finished 27 - 27 - 1 - - - CF28 - Tx Buffer Cancellation Finished 28 - 28 - 1 - - - CF29 - Tx Buffer Cancellation Finished 29 - 29 - 1 - - - CF30 - Tx Buffer Cancellation Finished 30 - 30 - 1 - - - CF31 - Tx Buffer Cancellation Finished 31 - 31 - 1 - - - - - TXBTIE - Tx Buffer Transmission Interrupt Enable - 0xE0 - 32 - 0x00000000 - - - TIE0 - Transmission Interrupt Enable 0 - 0 - 1 - - - TIE1 - Transmission Interrupt Enable 1 - 1 - 1 - - - TIE2 - Transmission Interrupt Enable 2 - 2 - 1 - - - TIE3 - Transmission Interrupt Enable 3 - 3 - 1 - - - TIE4 - Transmission Interrupt Enable 4 - 4 - 1 - - - TIE5 - Transmission Interrupt Enable 5 - 5 - 1 - - - TIE6 - Transmission Interrupt Enable 6 - 6 - 1 - - - TIE7 - Transmission Interrupt Enable 7 - 7 - 1 - - - TIE8 - Transmission Interrupt Enable 8 - 8 - 1 - - - TIE9 - Transmission Interrupt Enable 9 - 9 - 1 - - - TIE10 - Transmission Interrupt Enable 10 - 10 - 1 - - - TIE11 - Transmission Interrupt Enable 11 - 11 - 1 - - - TIE12 - Transmission Interrupt Enable 12 - 12 - 1 - - - TIE13 - Transmission Interrupt Enable 13 - 13 - 1 - - - TIE14 - Transmission Interrupt Enable 14 - 14 - 1 - - - TIE15 - Transmission Interrupt Enable 15 - 15 - 1 - - - TIE16 - Transmission Interrupt Enable 16 - 16 - 1 - - - TIE17 - Transmission Interrupt Enable 17 - 17 - 1 - - - TIE18 - Transmission Interrupt Enable 18 - 18 - 1 - - - TIE19 - Transmission Interrupt Enable 19 - 19 - 1 - - - TIE20 - Transmission Interrupt Enable 20 - 20 - 1 - - - TIE21 - Transmission Interrupt Enable 21 - 21 - 1 - - - TIE22 - Transmission Interrupt Enable 22 - 22 - 1 - - - TIE23 - Transmission Interrupt Enable 23 - 23 - 1 - - - TIE24 - Transmission Interrupt Enable 24 - 24 - 1 - - - TIE25 - Transmission Interrupt Enable 25 - 25 - 1 - - - TIE26 - Transmission Interrupt Enable 26 - 26 - 1 - - - TIE27 - Transmission Interrupt Enable 27 - 27 - 1 - - - TIE28 - Transmission Interrupt Enable 28 - 28 - 1 - - - TIE29 - Transmission Interrupt Enable 29 - 29 - 1 - - - TIE30 - Transmission Interrupt Enable 30 - 30 - 1 - - - TIE31 - Transmission Interrupt Enable 31 - 31 - 1 - - - - - TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable - 0xE4 - 32 - 0x00000000 - - - CFIE0 - Cancellation Finished Interrupt Enable 0 - 0 - 1 - - - CFIE1 - Cancellation Finished Interrupt Enable 1 - 1 - 1 - - - CFIE2 - Cancellation Finished Interrupt Enable 2 - 2 - 1 - - - CFIE3 - Cancellation Finished Interrupt Enable 3 - 3 - 1 - - - CFIE4 - Cancellation Finished Interrupt Enable 4 - 4 - 1 - - - CFIE5 - Cancellation Finished Interrupt Enable 5 - 5 - 1 - - - CFIE6 - Cancellation Finished Interrupt Enable 6 - 6 - 1 - - - CFIE7 - Cancellation Finished Interrupt Enable 7 - 7 - 1 - - - CFIE8 - Cancellation Finished Interrupt Enable 8 - 8 - 1 - - - CFIE9 - Cancellation Finished Interrupt Enable 9 - 9 - 1 - - - CFIE10 - Cancellation Finished Interrupt Enable 10 - 10 - 1 - - - CFIE11 - Cancellation Finished Interrupt Enable 11 - 11 - 1 - - - CFIE12 - Cancellation Finished Interrupt Enable 12 - 12 - 1 - - - CFIE13 - Cancellation Finished Interrupt Enable 13 - 13 - 1 - - - CFIE14 - Cancellation Finished Interrupt Enable 14 - 14 - 1 - - - CFIE15 - Cancellation Finished Interrupt Enable 15 - 15 - 1 - - - CFIE16 - Cancellation Finished Interrupt Enable 16 - 16 - 1 - - - CFIE17 - Cancellation Finished Interrupt Enable 17 - 17 - 1 - - - CFIE18 - Cancellation Finished Interrupt Enable 18 - 18 - 1 - - - CFIE19 - Cancellation Finished Interrupt Enable 19 - 19 - 1 - - - CFIE20 - Cancellation Finished Interrupt Enable 20 - 20 - 1 - - - CFIE21 - Cancellation Finished Interrupt Enable 21 - 21 - 1 - - - CFIE22 - Cancellation Finished Interrupt Enable 22 - 22 - 1 - - - CFIE23 - Cancellation Finished Interrupt Enable 23 - 23 - 1 - - - CFIE24 - Cancellation Finished Interrupt Enable 24 - 24 - 1 - - - CFIE25 - Cancellation Finished Interrupt Enable 25 - 25 - 1 - - - CFIE26 - Cancellation Finished Interrupt Enable 26 - 26 - 1 - - - CFIE27 - Cancellation Finished Interrupt Enable 27 - 27 - 1 - - - CFIE28 - Cancellation Finished Interrupt Enable 28 - 28 - 1 - - - CFIE29 - Cancellation Finished Interrupt Enable 29 - 29 - 1 - - - CFIE30 - Cancellation Finished Interrupt Enable 30 - 30 - 1 - - - CFIE31 - Cancellation Finished Interrupt Enable 31 - 31 - 1 - - - - - TXEFC - Tx Event FIFO Configuration - 0xF0 - 32 - 0x00000000 - - - EFSA - Event FIFO Start Address - 0 - 16 - - - EFS - Event FIFO Size - 16 - 6 - - - EFWM - Event FIFO Watermark - 24 - 6 - - - - - TXEFS - Tx Event FIFO Status - 0xF4 - 32 - read-only - 0x00000000 - - - EFFL - Event FIFO Fill Level - 0 - 6 - - - EFGI - Event FIFO Get Index - 8 - 5 - - - EFPI - Event FIFO Put Index - 16 - 5 - - - EFF - Event FIFO Full - 24 - 1 - - - TEFL - Tx Event FIFO Element Lost - 25 - 1 - - - - - TXEFA - Tx Event FIFO Acknowledge - 0xF8 - 32 - 0x00000000 - - - EFAI - Event FIFO Acknowledge Index - 0 - 5 - - - - - - - CAN1 - 0x42000400 - - CAN1 - 79 - - - - CCL - U22251.1.0 - Configurable Custom Logic - CCL - CCL_ - 0x42003800 - - 0 - 0x18 - registers - - - - CTRL - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - SWRSTSelect - - DISABLE - The peripheral is not reset - 0 - - - ENABLE - The peripheral is reset - 1 - - - - - ENABLE - Enable - 1 - 1 - - ENABLESelect - - DISABLE - The peripheral is disabled - 0 - - - ENABLE - The peripheral is enabled - 1 - - - - - RUNSTDBY - Run in Standby - 6 - 1 - - RUNSTDBYSelect - - DISABLE - Generic clock is not required in standby sleep mode - 0 - - - ENABLE - Generic clock is required in standby sleep mode - 1 - - - - - - - 2 - 1 - SEQCTRL[%s] - SEQ Control x - 0x4 - 8 - 0x00 - - - SEQSEL - Sequential Selection - 0 - 4 - - SEQSELSelect - - DISABLE - Sequential logic is disabled - 0 - - - DFF - D flip flop - 1 - - - JK - JK flip flop - 2 - - - LATCH - D latch - 3 - - - RS - RS latch - 4 - - - - - - - 4 - 4 - LUTCTRL[%s] - LUT Control x - 0x8 - 32 - 0x00000000 - - - ENABLE - LUT Enable - 1 - 1 - - ENABLESelect - - DISABLE - LUT block is disabled - 0 - - - ENABLE - LUT block is enabled - 1 - - - - - FILTSEL - Filter Selection - 4 - 2 - - FILTSELSelect - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - EDGESEL - Edge Selection - 7 - 1 - - EDGESELSelect - - DISABLE - Edge detector is disabled - 0 - - - ENABLE - Edge detector is enabled - 1 - - - - - INSEL0 - Input Selection 0 - 8 - 4 - - INSEL0Select - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENT - Event input source - 3 - - - IO - I/O pin input source - 4 - - - AC - AC input source - 5 - - - TC - TC input source - 6 - - - ALTTC - Alternate TC input source - 7 - - - TCC - TCC input source - 8 - - - SERCOM - SERCOM input source - 9 - - - - - INSEL1 - Input Selection 1 - 12 - 4 - - INSEL1Select - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENT - Event input source - 3 - - - IO - I/O pin input source - 4 - - - AC - AC input source - 5 - - - TC - TC input source - 6 - - - ALTTC - Alternate TC input source - 7 - - - TCC - TCC input source - 8 - - - SERCOM - SERCOM input source - 9 - - - - - INSEL2 - Input Selection 2 - 16 - 4 - - INSEL2Select - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENT - Event input source - 3 - - - IO - I/O pin input source - 4 - - - AC - AC input source - 5 - - - TC - TC input source - 6 - - - ALTTC - Alternate TC input source - 7 - - - TCC - TCC input source - 8 - - - SERCOM - SERCOM input source - 9 - - - - - INVEI - Inverted Event Input Enable - 20 - 1 - - INVEISelect - - DISABLE - Incoming event is not inverted - 0 - - - ENABLE - Incoming event is inverted - 1 - - - - - LUTEI - LUT Event Input Enable - 21 - 1 - - LUTEISelect - - DISABLE - LUT incoming event is disabled - 0 - - - ENABLE - LUT incoming event is enabled - 1 - - - - - LUTEO - LUT Event Output Enable - 22 - 1 - - LUTEOSelect - - DISABLE - LUT event output is disabled - 0 - - - ENABLE - LUT event output is enabled - 1 - - - - - TRUTH - Truth Value - 24 - 8 - - - - - - - CMCC - U20156.0.0 - Cortex M Cache Controller - CMCC - CMCC_ - 0x41006000 - - 0 - 0x38 - registers - - - - TYPE - Cache Type Register - 0x0 - 32 - read-only - 0x000012D2 - - - GCLK - dynamic Clock Gating supported - 1 - 1 - - - RRP - Round Robin Policy supported - 4 - 1 - - - WAYNUM - Number of Way - 5 - 2 - - WAYNUMSelect - - DMAPPED - Direct Mapped Cache - 0 - - - ARCH2WAY - 2-WAY set associative - 1 - - - ARCH4WAY - 4-WAY set associative - 2 - - - - - LCKDOWN - Lock Down supported - 7 - 1 - - - CSIZE - Cache Size - 8 - 3 - - CSIZESelect - - CSIZE_1KB - Cache Size is 1 KB - 0 - - - CSIZE_2KB - Cache Size is 2 KB - 1 - - - CSIZE_4KB - Cache Size is 4 KB - 2 - - - CSIZE_8KB - Cache Size is 8 KB - 3 - - - CSIZE_16KB - Cache Size is 16 KB - 4 - - - CSIZE_32KB - Cache Size is 32 KB - 5 - - - CSIZE_64KB - Cache Size is 64 KB - 6 - - - - - CLSIZE - Cache Line Size - 11 - 3 - - CLSIZESelect - - CLSIZE_4B - Cache Line Size is 4 bytes - 0 - - - CLSIZE_8B - Cache Line Size is 8 bytes - 1 - - - CLSIZE_16B - Cache Line Size is 16 bytes - 2 - - - CLSIZE_32B - Cache Line Size is 32 bytes - 3 - - - CLSIZE_64B - Cache Line Size is 64 bytes - 4 - - - CLSIZE_128B - Cache Line Size is 128 bytes - 5 - - - - - - - CFG - Cache Configuration Register - 0x4 - 32 - 0x00000020 - - - ICDIS - Instruction Cache Disable - 1 - 1 - - - DCDIS - Data Cache Disable - 2 - 1 - - - CSIZESW - Cache size configured by software - 4 - 3 - - CSIZESWSelect - - CONF_CSIZE_1KB - The Cache Size is configured to 1KB - 0 - - - CONF_CSIZE_2KB - The Cache Size is configured to 2KB - 1 - - - CONF_CSIZE_4KB - The Cache Size is configured to 4KB - 2 - - - CONF_CSIZE_8KB - The Cache Size is configured to 8KB - 3 - - - CONF_CSIZE_16KB - The Cache Size is configured to 16KB - 4 - - - CONF_CSIZE_32KB - The Cache Size is configured to 32KB - 5 - - - CONF_CSIZE_64KB - The Cache Size is configured to 64KB - 6 - - - - - - - CTRL - Cache Control Register - 0x8 - 32 - write-only - 0x00000000 - - - CEN - Cache Controller Enable - 0 - 1 - - - - - SR - Cache Status Register - 0xC - 32 - read-only - 0x00000000 - - - CSTS - Cache Controller Status - 0 - 1 - - - - - LCKWAY - Cache Lock per Way Register - 0x10 - 32 - 0x00000000 - - - LCKWAY - Lockdown way Register - 0 - 4 - - - - - MAINT0 - Cache Maintenance Register 0 - 0x20 - 32 - write-only - 0x00000000 - - - INVALL - Cache Controller invalidate All - 0 - 1 - - - - - MAINT1 - Cache Maintenance Register 1 - 0x24 - 32 - write-only - 0x00000000 - - - INDEX - Invalidate Index - 4 - 8 - - - WAY - Invalidate Way - 28 - 4 - - WAYSelect - - WAY0 - Way 0 is selection for index invalidation - 0 - - - WAY1 - Way 1 is selection for index invalidation - 1 - - - WAY2 - Way 2 is selection for index invalidation - 2 - - - WAY3 - Way 3 is selection for index invalidation - 3 - - - - - - - MCFG - Cache Monitor Configuration Register - 0x28 - 32 - 0x00000000 - - - MODE - Cache Controller Monitor Counter Mode - 0 - 2 - - MODESelect - - CYCLE_COUNT - Cycle counter - 0 - - - IHIT_COUNT - Instruction hit counter - 1 - - - DHIT_COUNT - Data hit counter - 2 - - - - - - - MEN - Cache Monitor Enable Register - 0x2C - 32 - 0x00000000 - - - MENABLE - Cache Controller Monitor Enable - 0 - 1 - - - - - MCTRL - Cache Monitor Control Register - 0x30 - 32 - write-only - 0x00000000 - - - SWRST - Cache Controller Software Reset - 0 - 1 - - - - - MSR - Cache Monitor Status Register - 0x34 - 32 - read-only - 0x00000000 - - - EVENT_CNT - Monitor Event Counter - 0 - 32 - - - - - - - DAC - U25021.0.0 - Digital-to-Analog Converter - DAC - DAC_ - 0x43002400 - - 0 - 0x20 - registers - - - DAC_OTHER - 123 - - - DAC_EMPTY_0 - 124 - - - DAC_EMPTY_1 - 125 - - - DAC_RESRDY_0 - 126 - - - DAC_RESRDY_1 - 127 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable DAC Controller - 1 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - 0x02 - - - DIFF - Differential mode enable - 0 - 1 - - - REFSEL - Reference Selection for DAC0/1 - 1 - 2 - - REFSELSelect - - VREFPU - External reference unbuffered - 0 - - - VDDANA - Analog supply - 1 - - - VREFPB - External reference buffered - 2 - - - INTREF - Internal bandgap reference - 3 - - - - - - - EVCTRL - Event Control - 0x2 - 8 - 0x00 - - - STARTEI0 - Start Conversion Event Input DAC 0 - 0 - 1 - - - STARTEI1 - Start Conversion Event Input DAC 1 - 1 - 1 - - - EMPTYEO0 - Data Buffer Empty Event Output DAC 0 - 2 - 1 - - - EMPTYEO1 - Data Buffer Empty Event Output DAC 1 - 3 - 1 - - - INVEI0 - Enable Invertion of DAC 0 input event - 4 - 1 - - - INVEI1 - Enable Invertion of DAC 1 input event - 5 - 1 - - - RESRDYEO0 - Result Ready Event Output 0 - 6 - 1 - - - RESRDYEO1 - Result Ready Event Output 1 - 7 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - UNDERRUN0 - Underrun 0 Interrupt Enable - 0 - 1 - - - UNDERRUN1 - Underrun 1 Interrupt Enable - 1 - 1 - - - EMPTY0 - Data Buffer 0 Empty Interrupt Enable - 2 - 1 - - - EMPTY1 - Data Buffer 1 Empty Interrupt Enable - 3 - 1 - - - RESRDY0 - Result 0 Ready Interrupt Enable - 4 - 1 - - - RESRDY1 - Result 1 Ready Interrupt Enable - 5 - 1 - - - OVERRUN0 - Overrun 0 Interrupt Enable - 6 - 1 - - - OVERRUN1 - Overrun 1 Interrupt Enable - 7 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - UNDERRUN0 - Underrun 0 Interrupt Enable - 0 - 1 - - - UNDERRUN1 - Underrun 1 Interrupt Enable - 1 - 1 - - - EMPTY0 - Data Buffer 0 Empty Interrupt Enable - 2 - 1 - - - EMPTY1 - Data Buffer 1 Empty Interrupt Enable - 3 - 1 - - - RESRDY0 - Result 0 Ready Interrupt Enable - 4 - 1 - - - RESRDY1 - Result 1 Ready Interrupt Enable - 5 - 1 - - - OVERRUN0 - Overrun 0 Interrupt Enable - 6 - 1 - - - OVERRUN1 - Overrun 1 Interrupt Enable - 7 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - UNDERRUN0 - Result 0 Underrun - 0 - 1 - - - UNDERRUN1 - Result 1 Underrun - 1 - 1 - - - EMPTY0 - Data Buffer 0 Empty - 2 - 1 - - - EMPTY1 - Data Buffer 1 Empty - 3 - 1 - - - RESRDY0 - Result 0 Ready - 4 - 1 - - - RESRDY1 - Result 1 Ready - 5 - 1 - - - OVERRUN0 - Result 0 Overrun - 6 - 1 - - - OVERRUN1 - Result 1 Overrun - 7 - 1 - - - - - STATUS - Status - 0x7 - 8 - read-only - 0x00 - - - READY0 - DAC 0 Startup Ready - 0 - 1 - - - READY1 - DAC 1 Startup Ready - 1 - 1 - - - EOC0 - DAC 0 End of Conversion - 2 - 1 - - - EOC1 - DAC 1 End of Conversion - 3 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - DAC Enable Status - 1 - 1 - - - DATA0 - Data DAC 0 - 2 - 1 - - - DATA1 - Data DAC 1 - 3 - 1 - - - DATABUF0 - Data Buffer DAC 0 - 4 - 1 - - - DATABUF1 - Data Buffer DAC 1 - 5 - 1 - - - - - 2 - 2 - DACCTRL[%s] - DAC n Control - 0xC - 16 - 0x0000 - - - LEFTADJ - Left Adjusted Data - 0 - 1 - - - ENABLE - Enable DAC0 - 1 - 1 - - - CCTRL - Current Control - 2 - 2 - - CCTRLSelect - - CC100K - 100kSPS - 0x0 - - - CC1M - 500kSPS - 0x1 - - - CC12M - 1MSPS - 0x2 - - - - - FEXT - Standalone Filter - 5 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - DITHER - Dithering Mode - 7 - 1 - - - REFRESH - Refresh period - 8 - 4 - - REFRESHSelect - - REFRESH_0 - Do not Refresh - 0 - - - REFRESH_1 - Refresh every 30 us - 1 - - - REFRESH_2 - Refresh every 60 us - 2 - - - REFRESH_3 - Refresh every 90 us - 3 - - - REFRESH_4 - Refresh every 120 us - 4 - - - REFRESH_5 - Refresh every 150 us - 5 - - - REFRESH_6 - Refresh every 180 us - 6 - - - REFRESH_7 - Refresh every 210 us - 7 - - - REFRESH_8 - Refresh every 240 us - 8 - - - REFRESH_9 - Refresh every 270 us - 9 - - - REFRESH_10 - Refresh every 300 us - 10 - - - REFRESH_11 - Refresh every 330 us - 11 - - - REFRESH_12 - Refresh every 360 us - 12 - - - REFRESH_13 - Refresh every 390 us - 13 - - - REFRESH_14 - Refresh every 420 us - 14 - - - REFRESH_15 - Refresh every 450 us - 15 - - - - - OSR - Sampling Rate - 13 - 3 - - OSRSelect - - OSR_1 - No Over Sampling - 0 - - - OSR_2 - 2x Over Sampling Ratio - 1 - - - OSR_4 - 4x Over Sampling Ratio - 2 - - - OSR_8 - 8x Over Sampling Ratio - 3 - - - OSR_16 - 16x Over Sampling Ratio - 4 - - - OSR_32 - 32x Over Sampling Ratio - 5 - - - - - - - 2 - 2 - DATA[%s] - DAC n Data - 0x10 - 16 - write-only - 0x0000 - - - DATA - DAC0 Data - 0 - 16 - - - - - 2 - 2 - DATABUF[%s] - DAC n Data Buffer - 0x14 - 16 - write-only - 0x0000 - - - DATABUF - DAC0 Data Buffer - 0 - 16 - - - - - DBGCTRL - Debug Control - 0x18 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - 2 - 2 - RESULT[%s] - Filter Result - 0x1C - 16 - read-only - 0x0000 - - - RESULT - Filter Result - 0 - 16 - - - - - - - DMAC - U25031.0.1 - Direct Memory Access Controller - DMAC - DMAC_ - 0x4100A000 - - 0 - 0x360 - registers - - - DMAC_0 - 31 - - - DMAC_1 - 32 - - - DMAC_2 - 33 - - - DMAC_3 - 34 - - - DMAC_OTHER - 35 - - - - CTRL - Control - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - DMAENABLE - DMA Enable - 1 - 1 - - - LVLEN0 - Priority Level 0 Enable - 8 - 1 - - - LVLEN1 - Priority Level 1 Enable - 9 - 1 - - - LVLEN2 - Priority Level 2 Enable - 10 - 1 - - - LVLEN3 - Priority Level 3 Enable - 11 - 1 - - - - - CRCCTRL - CRC Control - 0x2 - 16 - 0x0000 - - - CRCBEATSIZE - CRC Beat Size - 0 - 2 - - CRCBEATSIZESelect - - BYTE - 8-bit bus transfer - 0x0 - - - HWORD - 16-bit bus transfer - 0x1 - - - WORD - 32-bit bus transfer - 0x2 - - - - - CRCPOLY - CRC Polynomial Type - 2 - 2 - - CRCPOLYSelect - - CRC16 - CRC-16 (CRC-CCITT) - 0x0 - - - CRC32 - CRC32 (IEEE 802.3) - 0x1 - - - - - CRCSRC - CRC Input Source - 8 - 6 - - CRCSRCSelect - - DISABLE - CRC Disabled - 0x00 - - - IO - I/O interface - 0x01 - - - - - CRCMODE - CRC Operating Mode - 14 - 2 - - CRCMODESelect - - DEFAULT - Default operating mode - 0 - - - CRCMON - Memory CRC monitor operating mode - 2 - - - CRCGEN - Memory CRC generation operating mode - 3 - - - - - - - CRCDATAIN - CRC Data Input - 0x4 - 32 - 0x00000000 - - - CRCDATAIN - CRC Data Input - 0 - 32 - - - - - CRCCHKSUM - CRC Checksum - 0x8 - 32 - 0x00000000 - - - CRCCHKSUM - CRC Checksum - 0 - 32 - - - - - CRCSTATUS - CRC Status - 0xC - 8 - 0x00 - - - CRCBUSY - CRC Module Busy - 0 - 1 - - - CRCZERO - CRC Zero - 1 - 1 - - - CRCERR - CRC Error - 2 - 1 - - - - - DBGCTRL - Debug Control - 0xD - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - SWTRIGCTRL - Software Trigger Control - 0x10 - 32 - 0x00000000 - - - SWTRIG0 - Channel 0 Software Trigger - 0 - 1 - - - SWTRIG1 - Channel 1 Software Trigger - 1 - 1 - - - SWTRIG2 - Channel 2 Software Trigger - 2 - 1 - - - SWTRIG3 - Channel 3 Software Trigger - 3 - 1 - - - SWTRIG4 - Channel 4 Software Trigger - 4 - 1 - - - SWTRIG5 - Channel 5 Software Trigger - 5 - 1 - - - SWTRIG6 - Channel 6 Software Trigger - 6 - 1 - - - SWTRIG7 - Channel 7 Software Trigger - 7 - 1 - - - SWTRIG8 - Channel 8 Software Trigger - 8 - 1 - - - SWTRIG9 - Channel 9 Software Trigger - 9 - 1 - - - SWTRIG10 - Channel 10 Software Trigger - 10 - 1 - - - SWTRIG11 - Channel 11 Software Trigger - 11 - 1 - - - SWTRIG12 - Channel 12 Software Trigger - 12 - 1 - - - SWTRIG13 - Channel 13 Software Trigger - 13 - 1 - - - SWTRIG14 - Channel 14 Software Trigger - 14 - 1 - - - SWTRIG15 - Channel 15 Software Trigger - 15 - 1 - - - SWTRIG16 - Channel 16 Software Trigger - 16 - 1 - - - SWTRIG17 - Channel 17 Software Trigger - 17 - 1 - - - SWTRIG18 - Channel 18 Software Trigger - 18 - 1 - - - SWTRIG19 - Channel 19 Software Trigger - 19 - 1 - - - SWTRIG20 - Channel 20 Software Trigger - 20 - 1 - - - SWTRIG21 - Channel 21 Software Trigger - 21 - 1 - - - SWTRIG22 - Channel 22 Software Trigger - 22 - 1 - - - SWTRIG23 - Channel 23 Software Trigger - 23 - 1 - - - SWTRIG24 - Channel 24 Software Trigger - 24 - 1 - - - SWTRIG25 - Channel 25 Software Trigger - 25 - 1 - - - SWTRIG26 - Channel 26 Software Trigger - 26 - 1 - - - SWTRIG27 - Channel 27 Software Trigger - 27 - 1 - - - SWTRIG28 - Channel 28 Software Trigger - 28 - 1 - - - SWTRIG29 - Channel 29 Software Trigger - 29 - 1 - - - SWTRIG30 - Channel 30 Software Trigger - 30 - 1 - - - SWTRIG31 - Channel 31 Software Trigger - 31 - 1 - - - - - PRICTRL0 - Priority Control 0 - 0x14 - 32 - 0x40404040 - - - LVLPRI0 - Level 0 Channel Priority Number - 0 - 5 - - - QOS0 - Level 0 Quality of Service - 5 - 2 - - QOS0Select - - REGULAR - Regular delivery - 0 - - - SHORTAGE - Bandwidth shortage - 1 - - - SENSITIVE - Latency sensitive - 2 - - - CRITICAL - Latency critical - 3 - - - - - RRLVLEN0 - Level 0 Round-Robin Scheduling Enable - 7 - 1 - - - LVLPRI1 - Level 1 Channel Priority Number - 8 - 5 - - - QOS1 - Level 1 Quality of Service - 13 - 2 - - QOS1Select - - REGULAR - Regular delivery - 0 - - - SHORTAGE - Bandwidth shortage - 1 - - - SENSITIVE - Latency sensitive - 2 - - - CRITICAL - Latency critical - 3 - - - - - RRLVLEN1 - Level 1 Round-Robin Scheduling Enable - 15 - 1 - - - LVLPRI2 - Level 2 Channel Priority Number - 16 - 5 - - - QOS2 - Level 2 Quality of Service - 21 - 2 - - QOS2Select - - REGULAR - Regular delivery - 0 - - - SHORTAGE - Bandwidth shortage - 1 - - - SENSITIVE - Latency sensitive - 2 - - - CRITICAL - Latency critical - 3 - - - - - RRLVLEN2 - Level 2 Round-Robin Scheduling Enable - 23 - 1 - - - LVLPRI3 - Level 3 Channel Priority Number - 24 - 5 - - - QOS3 - Level 3 Quality of Service - 29 - 2 - - QOS3Select - - REGULAR - Regular delivery - 0 - - - SHORTAGE - Bandwidth shortage - 1 - - - SENSITIVE - Latency sensitive - 2 - - - CRITICAL - Latency critical - 3 - - - - - RRLVLEN3 - Level 3 Round-Robin Scheduling Enable - 31 - 1 - - - - - INTPEND - Interrupt Pending - 0x20 - 16 - 0x0000 - - - ID - Channel ID - 0 - 5 - - - TERR - Transfer Error - 8 - 1 - - - TCMPL - Transfer Complete - 9 - 1 - - - SUSP - Channel Suspend - 10 - 1 - - - CRCERR - CRC Error - 12 - 1 - - - FERR - Fetch Error - 13 - 1 - - - BUSY - Busy - 14 - 1 - - - PEND - Pending - 15 - 1 - - - - - INTSTATUS - Interrupt Status - 0x24 - 32 - read-only - 0x00000000 - - - CHINT0 - Channel 0 Pending Interrupt - 0 - 1 - - - CHINT1 - Channel 1 Pending Interrupt - 1 - 1 - - - CHINT2 - Channel 2 Pending Interrupt - 2 - 1 - - - CHINT3 - Channel 3 Pending Interrupt - 3 - 1 - - - CHINT4 - Channel 4 Pending Interrupt - 4 - 1 - - - CHINT5 - Channel 5 Pending Interrupt - 5 - 1 - - - CHINT6 - Channel 6 Pending Interrupt - 6 - 1 - - - CHINT7 - Channel 7 Pending Interrupt - 7 - 1 - - - CHINT8 - Channel 8 Pending Interrupt - 8 - 1 - - - CHINT9 - Channel 9 Pending Interrupt - 9 - 1 - - - CHINT10 - Channel 10 Pending Interrupt - 10 - 1 - - - CHINT11 - Channel 11 Pending Interrupt - 11 - 1 - - - CHINT12 - Channel 12 Pending Interrupt - 12 - 1 - - - CHINT13 - Channel 13 Pending Interrupt - 13 - 1 - - - CHINT14 - Channel 14 Pending Interrupt - 14 - 1 - - - CHINT15 - Channel 15 Pending Interrupt - 15 - 1 - - - CHINT16 - Channel 16 Pending Interrupt - 16 - 1 - - - CHINT17 - Channel 17 Pending Interrupt - 17 - 1 - - - CHINT18 - Channel 18 Pending Interrupt - 18 - 1 - - - CHINT19 - Channel 19 Pending Interrupt - 19 - 1 - - - CHINT20 - Channel 20 Pending Interrupt - 20 - 1 - - - CHINT21 - Channel 21 Pending Interrupt - 21 - 1 - - - CHINT22 - Channel 22 Pending Interrupt - 22 - 1 - - - CHINT23 - Channel 23 Pending Interrupt - 23 - 1 - - - CHINT24 - Channel 24 Pending Interrupt - 24 - 1 - - - CHINT25 - Channel 25 Pending Interrupt - 25 - 1 - - - CHINT26 - Channel 26 Pending Interrupt - 26 - 1 - - - CHINT27 - Channel 27 Pending Interrupt - 27 - 1 - - - CHINT28 - Channel 28 Pending Interrupt - 28 - 1 - - - CHINT29 - Channel 29 Pending Interrupt - 29 - 1 - - - CHINT30 - Channel 30 Pending Interrupt - 30 - 1 - - - CHINT31 - Channel 31 Pending Interrupt - 31 - 1 - - - - - BUSYCH - Busy Channels - 0x28 - 32 - read-only - 0x00000000 - - - BUSYCH0 - Busy Channel 0 - 0 - 1 - - - BUSYCH1 - Busy Channel 1 - 1 - 1 - - - BUSYCH2 - Busy Channel 2 - 2 - 1 - - - BUSYCH3 - Busy Channel 3 - 3 - 1 - - - BUSYCH4 - Busy Channel 4 - 4 - 1 - - - BUSYCH5 - Busy Channel 5 - 5 - 1 - - - BUSYCH6 - Busy Channel 6 - 6 - 1 - - - BUSYCH7 - Busy Channel 7 - 7 - 1 - - - BUSYCH8 - Busy Channel 8 - 8 - 1 - - - BUSYCH9 - Busy Channel 9 - 9 - 1 - - - BUSYCH10 - Busy Channel 10 - 10 - 1 - - - BUSYCH11 - Busy Channel 11 - 11 - 1 - - - BUSYCH12 - Busy Channel 12 - 12 - 1 - - - BUSYCH13 - Busy Channel 13 - 13 - 1 - - - BUSYCH14 - Busy Channel 14 - 14 - 1 - - - BUSYCH15 - Busy Channel 15 - 15 - 1 - - - BUSYCH16 - Busy Channel 16 - 16 - 1 - - - BUSYCH17 - Busy Channel 17 - 17 - 1 - - - BUSYCH18 - Busy Channel 18 - 18 - 1 - - - BUSYCH19 - Busy Channel 19 - 19 - 1 - - - BUSYCH20 - Busy Channel 20 - 20 - 1 - - - BUSYCH21 - Busy Channel 21 - 21 - 1 - - - BUSYCH22 - Busy Channel 22 - 22 - 1 - - - BUSYCH23 - Busy Channel 23 - 23 - 1 - - - BUSYCH24 - Busy Channel 24 - 24 - 1 - - - BUSYCH25 - Busy Channel 25 - 25 - 1 - - - BUSYCH26 - Busy Channel 26 - 26 - 1 - - - BUSYCH27 - Busy Channel 27 - 27 - 1 - - - BUSYCH28 - Busy Channel 28 - 28 - 1 - - - BUSYCH29 - Busy Channel 29 - 29 - 1 - - - BUSYCH30 - Busy Channel 30 - 30 - 1 - - - BUSYCH31 - Busy Channel 31 - 31 - 1 - - - - - PENDCH - Pending Channels - 0x2C - 32 - read-only - 0x00000000 - - - PENDCH0 - Pending Channel 0 - 0 - 1 - - - PENDCH1 - Pending Channel 1 - 1 - 1 - - - PENDCH2 - Pending Channel 2 - 2 - 1 - - - PENDCH3 - Pending Channel 3 - 3 - 1 - - - PENDCH4 - Pending Channel 4 - 4 - 1 - - - PENDCH5 - Pending Channel 5 - 5 - 1 - - - PENDCH6 - Pending Channel 6 - 6 - 1 - - - PENDCH7 - Pending Channel 7 - 7 - 1 - - - PENDCH8 - Pending Channel 8 - 8 - 1 - - - PENDCH9 - Pending Channel 9 - 9 - 1 - - - PENDCH10 - Pending Channel 10 - 10 - 1 - - - PENDCH11 - Pending Channel 11 - 11 - 1 - - - PENDCH12 - Pending Channel 12 - 12 - 1 - - - PENDCH13 - Pending Channel 13 - 13 - 1 - - - PENDCH14 - Pending Channel 14 - 14 - 1 - - - PENDCH15 - Pending Channel 15 - 15 - 1 - - - PENDCH16 - Pending Channel 16 - 16 - 1 - - - PENDCH17 - Pending Channel 17 - 17 - 1 - - - PENDCH18 - Pending Channel 18 - 18 - 1 - - - PENDCH19 - Pending Channel 19 - 19 - 1 - - - PENDCH20 - Pending Channel 20 - 20 - 1 - - - PENDCH21 - Pending Channel 21 - 21 - 1 - - - PENDCH22 - Pending Channel 22 - 22 - 1 - - - PENDCH23 - Pending Channel 23 - 23 - 1 - - - PENDCH24 - Pending Channel 24 - 24 - 1 - - - PENDCH25 - Pending Channel 25 - 25 - 1 - - - PENDCH26 - Pending Channel 26 - 26 - 1 - - - PENDCH27 - Pending Channel 27 - 27 - 1 - - - PENDCH28 - Pending Channel 28 - 28 - 1 - - - PENDCH29 - Pending Channel 29 - 29 - 1 - - - PENDCH30 - Pending Channel 30 - 30 - 1 - - - PENDCH31 - Pending Channel 31 - 31 - 1 - - - - - ACTIVE - Active Channel and Levels - 0x30 - 32 - read-only - 0x00000000 - - - LVLEX0 - Level 0 Channel Trigger Request Executing - 0 - 1 - - - LVLEX1 - Level 1 Channel Trigger Request Executing - 1 - 1 - - - LVLEX2 - Level 2 Channel Trigger Request Executing - 2 - 1 - - - LVLEX3 - Level 3 Channel Trigger Request Executing - 3 - 1 - - - ID - Active Channel ID - 8 - 5 - - - ABUSY - Active Channel Busy - 15 - 1 - - - BTCNT - Active Channel Block Transfer Count - 16 - 16 - - - - - BASEADDR - Descriptor Memory Section Base Address - 0x34 - 32 - 0x00000000 - - - BASEADDR - Descriptor Memory Base Address - 0 - 32 - - - - - WRBADDR - Write-Back Memory Section Base Address - 0x38 - 32 - 0x00000000 - - - WRBADDR - Write-Back Memory Base Address - 0 - 32 - - - - - 32 - 0x10 - CHANNEL[%s] - - 0x40 - - CHCTRLA - Channel n Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Channel Software Reset - 0 - 1 - - - ENABLE - Channel Enable - 1 - 1 - - - RUNSTDBY - Channel Run in Standby - 6 - 1 - - - TRIGSRC - Trigger Source - 8 - 7 - - TRIGSRCSelect - - DISABLE - Only software/event triggers - 0 - - - - - TRIGACT - Trigger Action - 20 - 2 - - TRIGACTSelect - - BLOCK - One trigger required for each block transfer - 0 - - - BURST - One trigger required for each burst transfer - 2 - - - TRANSACTION - One trigger required for each transaction - 3 - - - - - BURSTLEN - Burst Length - 24 - 4 - - BURSTLENSelect - - SINGLE - Single-beat burst length - 0 - - - 2BEAT - 2-beats burst length - 1 - - - 3BEAT - 3-beats burst length - 2 - - - 4BEAT - 4-beats burst length - 3 - - - 5BEAT - 5-beats burst length - 4 - - - 6BEAT - 6-beats burst length - 5 - - - 7BEAT - 7-beats burst length - 6 - - - 8BEAT - 8-beats burst length - 7 - - - 9BEAT - 9-beats burst length - 8 - - - 10BEAT - 10-beats burst length - 9 - - - 11BEAT - 11-beats burst length - 10 - - - 12BEAT - 12-beats burst length - 11 - - - 13BEAT - 13-beats burst length - 12 - - - 14BEAT - 14-beats burst length - 13 - - - 15BEAT - 15-beats burst length - 14 - - - 16BEAT - 16-beats burst length - 15 - - - - - THRESHOLD - FIFO Threshold - 28 - 2 - - THRESHOLDSelect - - 1BEAT - Destination write starts after each beat source address read - 0 - - - 2BEATS - Destination write starts after 2-beats source address read - 1 - - - 4BEATS - Destination write starts after 4-beats source address read - 2 - - - 8BEATS - Destination write starts after 8-beats source address read - 3 - - - - - - - CHCTRLB - Channel n Control B - 0x4 - 8 - 0x00 - - - CMD - Software Command - 0 - 2 - - CMDSelect - - NOACT - No action - 0x0 - - - SUSPEND - Channel suspend operation - 0x1 - - - RESUME - Channel resume operation - 0x2 - - - - - - - CHPRILVL - Channel n Priority Level - 0x5 - 8 - 0x00 - - - PRILVL - Channel Priority Level - 0 - 2 - - PRILVLSelect - - LVL0 - Channel Priority Level 0 (Lowest Level) - 0 - - - LVL1 - Channel Priority Level 1 - 1 - - - LVL2 - Channel Priority Level 2 - 2 - - - LVL3 - Channel Priority Level 3 (Highest Level) - 3 - - - - - - - CHEVCTRL - Channel n Event Control - 0x6 - 8 - 0x00 - - - EVACT - Channel Event Input Action - 0 - 3 - - EVACTSelect - - NOACT - No action - 0 - - - TRIG - Transfer and periodic transfer trigger - 1 - - - CTRIG - Conditional transfer trigger - 2 - - - CBLOCK - Conditional block transfer - 3 - - - SUSPEND - Channel suspend operation - 4 - - - RESUME - Channel resume operation - 5 - - - SSKIP - Skip next block suspend action - 6 - - - INCPRI - Increase priority - 7 - - - - - EVOMODE - Channel Event Output Mode - 4 - 2 - - EVOMODESelect - - DEFAULT - Block event output selection. Refer to BTCTRL.EVOSEL for available selections. - 0 - - - TRIGACT - Ongoing trigger action - 1 - - - - - EVIE - Channel Event Input Enable - 6 - 1 - - - EVOE - Channel Event Output Enable - 7 - 1 - - - - - CHINTENCLR - Channel n Interrupt Enable Clear - 0xC - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTENSET - Channel n Interrupt Enable Set - 0xD - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTFLAG - Channel n Interrupt Flag Status and Clear - 0xE - 8 - 0x00 - - - TERR - Channel Transfer Error - 0 - 1 - - - TCMPL - Channel Transfer Complete - 1 - 1 - - - SUSP - Channel Suspend - 2 - 1 - - - - - CHSTATUS - Channel n Status - 0xF - 8 - 0x00 - - - PEND - Channel Pending - 0 - 1 - - - BUSY - Channel Busy - 1 - 1 - - - FERR - Channel Fetch Error - 2 - 1 - - - CRCERR - Channel CRC Error - 3 - 1 - - - - - - - - DSU - U24101.0.0 - Device Service Unit - DSU - DSU_ - 0x41002000 - - 0 - 0x2000 - registers - - - - CTRL - Control - 0x0 - 8 - write-only - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - CRC - 32-bit Cyclic Redundancy Code - 2 - 1 - - - MBIST - Memory built-in self-test - 3 - 1 - - - CE - Chip-Erase - 4 - 1 - - - ARR - Auxiliary Row Read - 6 - 1 - - - SMSA - Start Memory Stream Access - 7 - 1 - - - - - STATUSA - Status A - 0x1 - 8 - 0x00 - - - DONE - Done - 0 - 1 - - - CRSTEXT - CPU Reset Phase Extension - 1 - 1 - - - BERR - Bus Error - 2 - 1 - - - FAIL - Failure - 3 - 1 - - - PERR - Protection Error - 4 - 1 - - - - - STATUSB - Status B - 0x2 - 8 - read-only - 0x00 - - - PROT - Protected - 0 - 1 - - - DBGPRES - Debugger Present - 1 - 1 - - - DCCD0 - Debug Communication Channel 0 Dirty - 2 - 1 - - - DCCD1 - Debug Communication Channel 1 Dirty - 3 - 1 - - - HPE - Hot-Plugging Enable - 4 - 1 - - - CELCK - Chip Erase Locked - 5 - 1 - - - TDCCD0 - Test Debug Communication Channel 0 Dirty - 6 - 1 - - - TDCCD1 - Test Debug Communication Channel 1 Dirty - 7 - 1 - - - - - ADDR - Address - 0x4 - 32 - 0x00000000 - - - AMOD - Access Mode - 0 - 2 - - - ADDR - Address - 2 - 30 - - - - - LENGTH - Length - 0x8 - 32 - 0x00000000 - - - LENGTH - Length - 2 - 30 - - - - - DATA - Data - 0xC - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - 2 - 4 - DCC[%s] - Debug Communication Channel n - 0x10 - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - DID - Device Identification - 0x18 - 32 - read-only - 0x61810304 - - - DEVSEL - Device Select - 0 - 8 - - - REVISION - Revision Number - 8 - 4 - - - DIE - Die Number - 12 - 4 - - - SERIES - Series - 16 - 6 - - SERIESSelect - - 0 - Cortex-M0+ processor, basic feature set - 0 - - - 1 - Cortex-M0+ processor, USB - 1 - - - - - FAMILY - Family - 23 - 5 - - FAMILYSelect - - 0 - General purpose microcontroller - 0 - - - 1 - PicoPower - 1 - - - - - PROCESSOR - Processor - 28 - 4 - - PROCESSORSelect - - CM0P - Cortex-M0+ - 0x1 - - - CM23 - Cortex-M23 - 0x2 - - - CM3 - Cortex-M3 - 0x3 - - - CM4 - Cortex-M4 - 0x5 - - - CM4F - Cortex-M4 with FPU - 0x6 - - - CM33 - Cortex-M33 - 0x7 - - - - - - - CFG - Configuration - 0x1C - 32 - 0x00000002 - - - LQOS - Latency Quality Of Service - 0 - 2 - - - DCCDMALEVEL - DMA Trigger Level - 2 - 2 - - DCCDMALEVELSelect - - EMPTY - Trigger rises when DCC is empty - 0 - - - FULL - Trigger rises when DCC is full - 1 - - - - - ETBRAMEN - Trace Control - 4 - 1 - - - - - 2 - 4 - DCFG[%s] - Device Configuration - 0xF0 - 32 - 0x00000000 - - - DCFG - Device Configuration - 0 - 32 - - - - - ENTRY0 - CoreSight ROM Table Entry 0 - 0x1000 - 32 - read-only - 0x9F0FC002 - - - EPRES - Entry Present - 0 - 1 - - - FMT - Format - 1 - 1 - - - ADDOFF - Address Offset - 12 - 20 - - - - - ENTRY1 - CoreSight ROM Table Entry 1 - 0x1004 - 32 - read-only - 0x00000000 - - - END - CoreSight ROM Table End - 0x1008 - 32 - read-only - 0x00000000 - - - END - End Marker - 0 - 32 - - - - - MEMTYPE - CoreSight ROM Table Memory Type - 0x1FCC - 32 - read-only - 0x00000000 - - - SMEMP - System Memory Present - 0 - 1 - - - - - PID4 - Peripheral Identification 4 - 0x1FD0 - 32 - read-only - 0x00000000 - - - JEPCC - JEP-106 Continuation Code - 0 - 4 - - - FKBC - 4KB count - 4 - 4 - - - - - PID5 - Peripheral Identification 5 - 0x1FD4 - 32 - read-only - 0x00000000 - - - PID6 - Peripheral Identification 6 - 0x1FD8 - 32 - read-only - 0x00000000 - - - PID7 - Peripheral Identification 7 - 0x1FDC - 32 - read-only - 0x00000000 - - - PID0 - Peripheral Identification 0 - 0x1FE0 - 32 - read-only - 0x000000D0 - - - PARTNBL - Part Number Low - 0 - 8 - - - - - PID1 - Peripheral Identification 1 - 0x1FE4 - 32 - read-only - 0x000000FC - - - PARTNBH - Part Number High - 0 - 4 - - - JEPIDCL - Low part of the JEP-106 Identity Code - 4 - 4 - - - - - PID2 - Peripheral Identification 2 - 0x1FE8 - 32 - read-only - 0x00000009 - - - JEPIDCH - JEP-106 Identity Code High - 0 - 3 - - - JEPU - JEP-106 Identity Code is used - 3 - 1 - - - REVISION - Revision Number - 4 - 4 - - - - - PID3 - Peripheral Identification 3 - 0x1FEC - 32 - read-only - 0x00000000 - - - CUSMOD - ARM CUSMOD - 0 - 4 - - - REVAND - Revision Number - 4 - 4 - - - - - CID0 - Component Identification 0 - 0x1FF0 - 32 - read-only - 0x0000000D - - - PREAMBLEB0 - Preamble Byte 0 - 0 - 8 - - - - - CID1 - Component Identification 1 - 0x1FF4 - 32 - read-only - 0x00000010 - - - PREAMBLE - Preamble - 0 - 4 - - - CCLASS - Component Class - 4 - 4 - - - - - CID2 - Component Identification 2 - 0x1FF8 - 32 - read-only - 0x00000005 - - - PREAMBLEB2 - Preamble Byte 2 - 0 - 8 - - - - - CID3 - Component Identification 3 - 0x1FFC - 32 - read-only - 0x000000B1 - - - PREAMBLEB3 - Preamble Byte 3 - 0 - 8 - - - - - - - EIC - U22543.0.0 - External Interrupt Controller - EIC - EIC_ - 0x40002800 - - 0 - 0x3C - registers - - - EIC_EXTINT_0 - 12 - - - EIC_EXTINT_1 - 13 - - - EIC_EXTINT_2 - 14 - - - EIC_EXTINT_3 - 15 - - - EIC_EXTINT_4 - 16 - - - EIC_EXTINT_5 - 17 - - - EIC_EXTINT_6 - 18 - - - EIC_EXTINT_7 - 19 - - - EIC_EXTINT_8 - 20 - - - EIC_EXTINT_9 - 21 - - - EIC_EXTINT_10 - 22 - - - EIC_EXTINT_11 - 23 - - - EIC_EXTINT_12 - 24 - - - EIC_EXTINT_13 - 25 - - - EIC_EXTINT_14 - 26 - - - EIC_EXTINT_15 - 27 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - CKSEL - Clock Selection - 4 - 1 - - CKSELSelect - - CLK_GCLK - Clocked by GCLK - 0 - - - CLK_ULP32K - Clocked by ULP32K - 1 - - - - - - - NMICTRL - Non-Maskable Interrupt Control - 0x1 - 8 - 0x00 - - - NMISENSE - Non-Maskable Interrupt Sense Configuration - 0 - 3 - - NMISENSESelect - - NONE - No detection - 0 - - - RISE - Rising-edge detection - 1 - - - FALL - Falling-edge detection - 2 - - - BOTH - Both-edges detection - 3 - - - HIGH - High-level detection - 4 - - - LOW - Low-level detection - 5 - - - - - NMIFILTEN - Non-Maskable Interrupt Filter Enable - 3 - 1 - - - NMIASYNCH - Asynchronous Edge Detection Mode - 4 - 1 - - NMIASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - NMIFLAG - Non-Maskable Interrupt Flag Status and Clear - 0x2 - 16 - 0x0000 - - - NMI - Non-Maskable Interrupt - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy Status - 0 - 1 - - - ENABLE - Enable Synchronization Busy Status - 1 - 1 - - - - - EVCTRL - Event Control - 0x8 - 32 - 0x00000000 - - - EXTINTEO - External Interrupt Event Output Enable - 0 - 16 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 32 - 0x00000000 - - - EXTINT - External Interrupt Enable - 0 - 16 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 32 - 0x00000000 - - - EXTINT - External Interrupt Enable - 0 - 16 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 32 - 0x00000000 - - - EXTINT - External Interrupt - 0 - 16 - - - - - ASYNCH - External Interrupt Asynchronous Mode - 0x18 - 32 - 0x00000000 - - - ASYNCH - Asynchronous Edge Detection Mode - 0 - 16 - - ASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - 2 - 4 - CONFIG[%s] - External Interrupt Sense Configuration - 0x1C - 32 - 0x00000000 - - - SENSE0 - Input Sense Configuration 0 - 0 - 3 - - SENSE0Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN0 - Filter Enable 0 - 3 - 1 - - - SENSE1 - Input Sense Configuration 1 - 4 - 3 - - SENSE1Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN1 - Filter Enable 1 - 7 - 1 - - - SENSE2 - Input Sense Configuration 2 - 8 - 3 - - SENSE2Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN2 - Filter Enable 2 - 11 - 1 - - - SENSE3 - Input Sense Configuration 3 - 12 - 3 - - SENSE3Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN3 - Filter Enable 3 - 15 - 1 - - - SENSE4 - Input Sense Configuration 4 - 16 - 3 - - SENSE4Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN4 - Filter Enable 4 - 19 - 1 - - - SENSE5 - Input Sense Configuration 5 - 20 - 3 - - SENSE5Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN5 - Filter Enable 5 - 23 - 1 - - - SENSE6 - Input Sense Configuration 6 - 24 - 3 - - SENSE6Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN6 - Filter Enable 6 - 27 - 1 - - - SENSE7 - Input Sense Configuration 7 - 28 - 3 - - SENSE7Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN7 - Filter Enable 7 - 31 - 1 - - - - - DEBOUNCEN - Debouncer Enable - 0x30 - 32 - 0x00000000 - - - DEBOUNCEN - Debouncer Enable - 0 - 16 - - - - - DPRESCALER - Debouncer Prescaler - 0x34 - 32 - 0x00000000 - - - PRESCALER0 - Debouncer Prescaler - 0 - 3 - - PRESCALER0Select - - DIV2 - EIC clock divided by 2 - 0 - - - DIV4 - EIC clock divided by 4 - 1 - - - DIV8 - EIC clock divided by 8 - 2 - - - DIV16 - EIC clock divided by 16 - 3 - - - DIV32 - EIC clock divided by 32 - 4 - - - DIV64 - EIC clock divided by 64 - 5 - - - DIV128 - EIC clock divided by 128 - 6 - - - DIV256 - EIC clock divided by 256 - 7 - - - - - STATES0 - Debouncer number of states - 3 - 1 - - STATES0Select - - LFREQ3 - 3 low frequency samples - 0 - - - LFREQ7 - 7 low frequency samples - 1 - - - - - PRESCALER1 - Debouncer Prescaler - 4 - 3 - - PRESCALER1Select - - DIV2 - EIC clock divided by 2 - 0 - - - DIV4 - EIC clock divided by 4 - 1 - - - DIV8 - EIC clock divided by 8 - 2 - - - DIV16 - EIC clock divided by 16 - 3 - - - DIV32 - EIC clock divided by 32 - 4 - - - DIV64 - EIC clock divided by 64 - 5 - - - DIV128 - EIC clock divided by 128 - 6 - - - DIV256 - EIC clock divided by 256 - 7 - - - - - STATES1 - Debouncer number of states - 7 - 1 - - STATES1Select - - LFREQ3 - 3 low frequency samples - 0 - - - LFREQ7 - 7 low frequency samples - 1 - - - - - TICKON - Pin Sampler frequency selection - 16 - 1 - - TICKONSelect - - CLK_GCLK_EIC - Clocked by GCLK - 0 - - - CLK_LFREQ - Clocked by Low Frequency Clock - 1 - - - - - - - PINSTATE - Pin State - 0x38 - 32 - read-only - 0x00000000 - - - PINSTATE - Pin State - 0 - 16 - - - - - - - EVSYS - U25041.0.0 - Event System Interface - EVSYS - EVSYS_ - 0x4100E000 - - 0 - 0x2BC - registers - - - EVSYS_0 - 36 - - - EVSYS_1 - 37 - - - EVSYS_2 - 38 - - - EVSYS_3 - 39 - - - EVSYS_OTHER - 40 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - SWEVT - Software Event - 0x4 - 32 - write-only - 0x00000000 - - - CHANNEL0 - Channel 0 Software Selection - 0 - 1 - - - CHANNEL1 - Channel 1 Software Selection - 1 - 1 - - - CHANNEL2 - Channel 2 Software Selection - 2 - 1 - - - CHANNEL3 - Channel 3 Software Selection - 3 - 1 - - - CHANNEL4 - Channel 4 Software Selection - 4 - 1 - - - CHANNEL5 - Channel 5 Software Selection - 5 - 1 - - - CHANNEL6 - Channel 6 Software Selection - 6 - 1 - - - CHANNEL7 - Channel 7 Software Selection - 7 - 1 - - - CHANNEL8 - Channel 8 Software Selection - 8 - 1 - - - CHANNEL9 - Channel 9 Software Selection - 9 - 1 - - - CHANNEL10 - Channel 10 Software Selection - 10 - 1 - - - CHANNEL11 - Channel 11 Software Selection - 11 - 1 - - - CHANNEL12 - Channel 12 Software Selection - 12 - 1 - - - CHANNEL13 - Channel 13 Software Selection - 13 - 1 - - - CHANNEL14 - Channel 14 Software Selection - 14 - 1 - - - CHANNEL15 - Channel 15 Software Selection - 15 - 1 - - - CHANNEL16 - Channel 16 Software Selection - 16 - 1 - - - CHANNEL17 - Channel 17 Software Selection - 17 - 1 - - - CHANNEL18 - Channel 18 Software Selection - 18 - 1 - - - CHANNEL19 - Channel 19 Software Selection - 19 - 1 - - - CHANNEL20 - Channel 20 Software Selection - 20 - 1 - - - CHANNEL21 - Channel 21 Software Selection - 21 - 1 - - - CHANNEL22 - Channel 22 Software Selection - 22 - 1 - - - CHANNEL23 - Channel 23 Software Selection - 23 - 1 - - - CHANNEL24 - Channel 24 Software Selection - 24 - 1 - - - CHANNEL25 - Channel 25 Software Selection - 25 - 1 - - - CHANNEL26 - Channel 26 Software Selection - 26 - 1 - - - CHANNEL27 - Channel 27 Software Selection - 27 - 1 - - - CHANNEL28 - Channel 28 Software Selection - 28 - 1 - - - CHANNEL29 - Channel 29 Software Selection - 29 - 1 - - - CHANNEL30 - Channel 30 Software Selection - 30 - 1 - - - CHANNEL31 - Channel 31 Software Selection - 31 - 1 - - - - - PRICTRL - Priority Control - 0x8 - 8 - 0x00 - - - PRI - Channel Priority Number - 0 - 4 - - - RREN - Round-Robin Scheduling Enable - 7 - 1 - - - - - INTPEND - Channel Pending Interrupt - 0x10 - 16 - 0x4000 - - - ID - Channel ID - 0 - 4 - - - OVR - Channel Overrun - 8 - 1 - - - EVD - Channel Event Detected - 9 - 1 - - - READY - Ready - 14 - 1 - - - BUSY - Busy - 15 - 1 - - - - - INTSTATUS - Interrupt Status - 0x14 - 32 - read-only - 0x00000000 - - - CHINT0 - Channel 0 Pending Interrupt - 0 - 1 - - - CHINT1 - Channel 1 Pending Interrupt - 1 - 1 - - - CHINT2 - Channel 2 Pending Interrupt - 2 - 1 - - - CHINT3 - Channel 3 Pending Interrupt - 3 - 1 - - - CHINT4 - Channel 4 Pending Interrupt - 4 - 1 - - - CHINT5 - Channel 5 Pending Interrupt - 5 - 1 - - - CHINT6 - Channel 6 Pending Interrupt - 6 - 1 - - - CHINT7 - Channel 7 Pending Interrupt - 7 - 1 - - - CHINT8 - Channel 8 Pending Interrupt - 8 - 1 - - - CHINT9 - Channel 9 Pending Interrupt - 9 - 1 - - - CHINT10 - Channel 10 Pending Interrupt - 10 - 1 - - - CHINT11 - Channel 11 Pending Interrupt - 11 - 1 - - - - - BUSYCH - Busy Channels - 0x18 - 32 - read-only - 0x00000000 - - - BUSYCH0 - Busy Channel 0 - 0 - 1 - - - BUSYCH1 - Busy Channel 1 - 1 - 1 - - - BUSYCH2 - Busy Channel 2 - 2 - 1 - - - BUSYCH3 - Busy Channel 3 - 3 - 1 - - - BUSYCH4 - Busy Channel 4 - 4 - 1 - - - BUSYCH5 - Busy Channel 5 - 5 - 1 - - - BUSYCH6 - Busy Channel 6 - 6 - 1 - - - BUSYCH7 - Busy Channel 7 - 7 - 1 - - - BUSYCH8 - Busy Channel 8 - 8 - 1 - - - BUSYCH9 - Busy Channel 9 - 9 - 1 - - - BUSYCH10 - Busy Channel 10 - 10 - 1 - - - BUSYCH11 - Busy Channel 11 - 11 - 1 - - - - - READYUSR - Ready Users - 0x1C - 32 - read-only - 0xFFFFFFFF - - - READYUSR0 - Ready User for Channel 0 - 0 - 1 - - - READYUSR1 - Ready User for Channel 1 - 1 - 1 - - - READYUSR2 - Ready User for Channel 2 - 2 - 1 - - - READYUSR3 - Ready User for Channel 3 - 3 - 1 - - - READYUSR4 - Ready User for Channel 4 - 4 - 1 - - - READYUSR5 - Ready User for Channel 5 - 5 - 1 - - - READYUSR6 - Ready User for Channel 6 - 6 - 1 - - - READYUSR7 - Ready User for Channel 7 - 7 - 1 - - - READYUSR8 - Ready User for Channel 8 - 8 - 1 - - - READYUSR9 - Ready User for Channel 9 - 9 - 1 - - - READYUSR10 - Ready User for Channel 10 - 10 - 1 - - - READYUSR11 - Ready User for Channel 11 - 11 - 1 - - - - - 32 - 0x8 - CHANNEL[%s] - - 0x020 - - CHANNEL - Channel n Control - 0x0 - 32 - 0x00008000 - - - EVGEN - Event Generator Selection - 0 - 7 - - - PATH - Path Selection - 8 - 2 - - PATHSelect - - SYNCHRONOUS - Synchronous path - 0 - - - RESYNCHRONIZED - Resynchronized path - 1 - - - ASYNCHRONOUS - Asynchronous path - 2 - - - - - EDGSEL - Edge Detection Selection - 10 - 2 - - EDGSELSelect - - NO_EVT_OUTPUT - No event output when using the resynchronized or synchronous path - 0 - - - RISING_EDGE - Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path - 1 - - - FALLING_EDGE - Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path - 2 - - - BOTH_EDGES - Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path - 3 - - - - - RUNSTDBY - Run in standby - 14 - 1 - - - ONDEMAND - Generic Clock On Demand - 15 - 1 - - - - - CHINTENCLR - Channel n Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - OVR - Channel Overrun Interrupt Disable - 0 - 1 - - - EVD - Channel Event Detected Interrupt Disable - 1 - 1 - - - - - CHINTENSET - Channel n Interrupt Enable Set - 0x5 - 8 - 0x00 - - - OVR - Channel Overrun Interrupt Enable - 0 - 1 - - - EVD - Channel Event Detected Interrupt Enable - 1 - 1 - - - - - CHINTFLAG - Channel n Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - OVR - Channel Overrun - 0 - 1 - - - EVD - Channel Event Detected - 1 - 1 - - - - - CHSTATUS - Channel n Status - 0x7 - 8 - read-only - 0x01 - - - RDYUSR - Ready User - 0 - 1 - - - BUSYCH - Busy Channel - 1 - 1 - - - - - - 67 - 4 - USER[%s] - User Multiplexer n - 0x120 - 32 - 0x00000000 - - - CHANNEL - Channel Event Selection - 0 - 6 - - - - - - - FREQM - U22571.1.0 - Frequency Meter - FREQM - FREQM_ - 0x40002C00 - - 0 - 0x14 - registers - - - FREQM - 28 - - - - CTRLA - Control A Register - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B Register - 0x1 - 8 - write-only - 0x00 - - - START - Start Measurement - 0 - 1 - - - - - CFGA - Config A register - 0x2 - 16 - 0x0000 - - - REFNUM - Number of Reference Clock Cycles - 0 - 8 - - - - - INTENCLR - Interrupt Enable Clear Register - 0x8 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set Register - 0x9 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Register - 0xA - 8 - 0x00 - - - DONE - Measurement Done - 0 - 1 - - - - - STATUS - Status Register - 0xB - 8 - 0x00 - - - BUSY - FREQM Status - 0 - 1 - - - OVF - Sticky Count Value Overflow - 1 - 1 - - - - - SYNCBUSY - Synchronization Busy Register - 0xC - 32 - read-only - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - VALUE - Count Value Register - 0x10 - 32 - read-only - 0x00000000 - - - VALUE - Measurement Value - 0 - 24 - - - - - - - GCLK - U21221.2.0 - Generic Clock Generator - GCLK - GCLK_ - 0x40001C00 - - 0 - 0x1A0 - registers - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchroniation Busy bit - 0 - 1 - - - GENCTRL - Generic Clock Generator Control n Synchronization Busy bits - 2 - 12 - - GENCTRLSelect - - GCLK0 - Generic clock generator 0 - 0x0001 - - - GCLK1 - Generic clock generator 1 - 0x0002 - - - GCLK2 - Generic clock generator 2 - 0x0004 - - - GCLK3 - Generic clock generator 3 - 0x0008 - - - GCLK4 - Generic clock generator 4 - 0x0010 - - - GCLK5 - Generic clock generator 5 - 0x0020 - - - GCLK6 - Generic clock generator 6 - 0x0040 - - - GCLK7 - Generic clock generator 7 - 0x0080 - - - GCLK8 - Generic clock generator 8 - 0x0100 - - - GCLK9 - Generic clock generator 9 - 0x0200 - - - GCLK10 - Generic clock generator 10 - 0x0400 - - - GCLK11 - Generic clock generator 11 - 0x0800 - - - - - - - 12 - 4 - GENCTRL[%s] - Generic Clock Generator Control - 0x20 - 32 - 0x00000000 - - - SRC - Source Select - 0 - 4 - - SRCSelect - - XOSC0 - XOSC0 oscillator output - 0 - - - XOSC1 - XOSC1 oscillator output - 1 - - - GCLKIN - Generator input pad - 2 - - - GCLKGEN1 - Generic clock generator 1 output - 3 - - - OSCULP32K - OSCULP32K oscillator output - 4 - - - XOSC32K - XOSC32K oscillator output - 5 - - - DFLL - DFLL output - 6 - - - DPLL0 - DPLL0 output - 7 - - - DPLL1 - DPLL1 output - 8 - - - - - GENEN - Generic Clock Generator Enable - 8 - 1 - - - IDC - Improve Duty Cycle - 9 - 1 - - - OOV - Output Off Value - 10 - 1 - - - OE - Output Enable - 11 - 1 - - - DIVSEL - Divide Selection - 12 - 1 - - DIVSELSelect - - DIV1 - Divide input directly by divider factor - 0x0 - - - DIV2 - Divide input by 2^(divider factor+ 1) - 0x1 - - - - - RUNSTDBY - Run in Standby - 13 - 1 - - - DIV - Division Factor - 16 - 16 - - - - - 48 - 4 - PCHCTRL[%s] - Peripheral Clock Control - 0x80 - 32 - 0x00000000 - - - GEN - Generic Clock Generator - 0 - 4 - - GENSelect - - GCLK0 - Generic clock generator 0 - 0x0 - - - GCLK1 - Generic clock generator 1 - 0x1 - - - GCLK2 - Generic clock generator 2 - 0x2 - - - GCLK3 - Generic clock generator 3 - 0x3 - - - GCLK4 - Generic clock generator 4 - 0x4 - - - GCLK5 - Generic clock generator 5 - 0x5 - - - GCLK6 - Generic clock generator 6 - 0x6 - - - GCLK7 - Generic clock generator 7 - 0x7 - - - GCLK8 - Generic clock generator 8 - 0x8 - - - GCLK9 - Generic clock generator 9 - 0x9 - - - GCLK10 - Generic clock generator 10 - 0xA - - - GCLK11 - Generic clock generator 11 - 0xB - - - - - CHEN - Channel Enable - 6 - 1 - - - WRTLOCK - Write Lock - 7 - 1 - - - - - - - HMATRIX - I76382.1.4 - HSB Matrix - HMATRIXB - HMATRIXB_ - 0x4100C000 - - 0 - 0xB0 - registers - - - - 16 - 0x8 - PRS[%s] - - 0x080 - - PRAS - Priority A for Slave - 0x0 - 32 - 0x00000000 - - - PRBS - Priority B for Slave - 0x4 - 32 - 0x00000000 - - - - - - ICM - U20101.2.0 - Integrity Check Monitor - ICM - ICM_ - 0x42002C00 - - 0 - 0x58 - registers - - - ICM - 132 - - - - CFG - Configuration - 0x0 - 32 - 0x00000000 - - - WBDIS - Write Back Disable - 0 - 1 - - - EOMDIS - End of Monitoring Disable - 1 - 1 - - - SLBDIS - Secondary List Branching Disable - 2 - 1 - - - BBC - Bus Burden Control - 4 - 4 - - - ASCD - Automatic Switch To Compare Digest - 8 - 1 - - - DUALBUFF - Dual Input Buffer - 9 - 1 - - - UIHASH - User Initial Hash Value - 12 - 1 - - - UALGO - User SHA Algorithm - 13 - 3 - - UALGOSelect - - SHA1 - SHA1 Algorithm - 0x0 - - - SHA256 - SHA256 Algorithm - 0x1 - - - SHA224 - SHA224 Algorithm - 0x4 - - - - - HAPROT - Region Hash Area Protection - 16 - 6 - - - DAPROT - Region Descriptor Area Protection - 24 - 6 - - - - - CTRL - Control - 0x4 - 32 - write-only - - - ENABLE - ICM Enable - 0 - 1 - - - DISABLE - ICM Disable Register - 1 - 1 - - - SWRST - Software Reset - 2 - 1 - - - REHASH - Recompute Internal Hash - 4 - 4 - - - RMDIS - Region Monitoring Disable - 8 - 4 - - - RMEN - Region Monitoring Enable - 12 - 4 - - - - - SR - Status - 0x8 - 32 - read-only - 0x00000000 - - - ENABLE - ICM Controller Enable Register - 0 - 1 - - - RAWRMDIS - RAW Region Monitoring Disabled Status - 8 - 4 - - - RMDIS - Region Monitoring Disabled Status - 12 - 4 - - - - - IER - Interrupt Enable - 0x10 - 32 - write-only - - - RHC - Region Hash Completed Interrupt Enable - 0 - 4 - - - RDM - Region Digest Mismatch Interrupt Enable - 4 - 4 - - - RBE - Region Bus Error Interrupt Enable - 8 - 4 - - - RWC - Region Wrap Condition detected Interrupt Enable - 12 - 4 - - - REC - Region End bit Condition Detected Interrupt Enable - 16 - 4 - - - RSU - Region Status Updated Interrupt Disable - 20 - 4 - - - URAD - Undefined Register Access Detection Interrupt Enable - 24 - 1 - - - - - IDR - Interrupt Disable - 0x14 - 32 - write-only - 0x00000000 - - - RHC - Region Hash Completed Interrupt Disable - 0 - 4 - - - RDM - Region Digest Mismatch Interrupt Disable - 4 - 4 - - - RBE - Region Bus Error Interrupt Disable - 8 - 4 - - - RWC - Region Wrap Condition Detected Interrupt Disable - 12 - 4 - - - REC - Region End bit Condition detected Interrupt Disable - 16 - 4 - - - RSU - Region Status Updated Interrupt Disable - 20 - 4 - - - URAD - Undefined Register Access Detection Interrupt Disable - 24 - 1 - - - - - IMR - Interrupt Mask - 0x18 - 32 - read-only - 0x00000000 - - - RHC - Region Hash Completed Interrupt Mask - 0 - 4 - - - RDM - Region Digest Mismatch Interrupt Mask - 4 - 4 - - - RBE - Region Bus Error Interrupt Mask - 8 - 4 - - - RWC - Region Wrap Condition Detected Interrupt Mask - 12 - 4 - - - REC - Region End bit Condition Detected Interrupt Mask - 16 - 4 - - - RSU - Region Status Updated Interrupt Mask - 20 - 4 - - - URAD - Undefined Register Access Detection Interrupt Mask - 24 - 1 - - - - - ISR - Interrupt Status - 0x1C - 32 - read-only - 0x00000000 - - - RHC - Region Hash Completed - 0 - 4 - - - RDM - Region Digest Mismatch - 4 - 4 - - - RBE - Region Bus Error - 8 - 4 - - - RWC - Region Wrap Condition Detected - 12 - 4 - - - REC - Region End bit Condition Detected - 16 - 4 - - - RSU - Region Status Updated Detected - 20 - 4 - - - URAD - Undefined Register Access Detection Status - 24 - 1 - - - - - UASR - Undefined Access Status - 0x20 - 32 - read-only - 0x00000000 - - - URAT - Undefined Register Access Trace - 0 - 3 - - URATSelect - - UNSPEC_STRUCT_MEMBER - Unspecified structure member set to one detected when the descriptor is loaded - 0x0 - - - CFG_MODIFIED - CFG modified during active monitoring - 0x1 - - - DSCR_MODIFIED - DSCR modified during active monitoring - 0x2 - - - HASH_MODIFIED - HASH modified during active monitoring - 0x3 - - - READ_ACCESS - Write-only register read access - 0x4 - - - - - - - DSCR - Region Descriptor Area Start Address - 0x30 - 32 - 0x00000000 - - - DASA - Descriptor Area Start Address - 6 - 26 - - - - - HASH - Region Hash Area Start Address - 0x34 - 32 - 0x00000000 - - - HASA - Hash Area Start Address - 7 - 25 - - - - - 8 - 4 - UIHVAL[%s] - User Initial Hash Value n - 0x38 - 32 - write-only - 0x00000000 - - - VAL - Initial Hash Value - 0 - 32 - - - - - - - I2S - U22242.0.0 - Inter-IC Sound Interface - I2S - I2S_ - 0x43002800 - - 0 - 0x38 - registers - - - I2S - 128 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - CKEN0 - Clock Unit 0 Enable - 2 - 1 - - - CKEN1 - Clock Unit 1 Enable - 3 - 1 - - - TXEN - Tx Serializer Enable - 4 - 1 - - - RXEN - Rx Serializer Enable - 5 - 1 - - - - - 2 - 4 - CLKCTRL[%s] - Clock Unit n Control - 0x4 - 32 - 0x00000000 - - - SLOTSIZE - Slot Size - 0 - 2 - - SLOTSIZESelect - - 8 - 8-bit Slot for Clock Unit n - 0x0 - - - 16 - 16-bit Slot for Clock Unit n - 0x1 - - - 24 - 24-bit Slot for Clock Unit n - 0x2 - - - 32 - 32-bit Slot for Clock Unit n - 0x3 - - - - - NBSLOTS - Number of Slots in Frame - 2 - 3 - - - FSWIDTH - Frame Sync Width - 5 - 2 - - FSWIDTHSelect - - SLOT - Frame Sync Pulse is 1 Slot wide (default for I2S protocol) - 0x0 - - - HALF - Frame Sync Pulse is half a Frame wide - 0x1 - - - BIT - Frame Sync Pulse is 1 Bit wide - 0x2 - - - BURST - Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested - 0x3 - - - - - BITDELAY - Data Delay from Frame Sync - 7 - 1 - - BITDELAYSelect - - LJ - Left Justified (0 Bit Delay) - 0x0 - - - I2S - I2S (1 Bit Delay) - 0x1 - - - - - FSSEL - Frame Sync Select - 8 - 1 - - FSSELSelect - - SCKDIV - Divided Serial Clock n is used as Frame Sync n source - 0x0 - - - FSPIN - FSn input pin is used as Frame Sync n source - 0x1 - - - - - FSINV - Frame Sync Invert - 9 - 1 - - - FSOUTINV - Frame Sync Output Invert - 10 - 1 - - - SCKSEL - Serial Clock Select - 11 - 1 - - SCKSELSelect - - MCKDIV - Divided Master Clock n is used as Serial Clock n source - 0x0 - - - SCKPIN - SCKn input pin is used as Serial Clock n source - 0x1 - - - - - SCKOUTINV - Serial Clock Output Invert - 12 - 1 - - - MCKSEL - Master Clock Select - 13 - 1 - - MCKSELSelect - - GCLK - GCLK_I2S_n is used as Master Clock n source - 0x0 - - - MCKPIN - MCKn input pin is used as Master Clock n source - 0x1 - - - - - MCKEN - Master Clock Enable - 14 - 1 - - - MCKOUTINV - Master Clock Output Invert - 15 - 1 - - - MCKDIV - Master Clock Division Factor - 16 - 6 - - - MCKOUTDIV - Master Clock Output Division Factor - 24 - 6 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 16 - 0x0000 - - - RXRDY0 - Receive Ready 0 Interrupt Enable - 0 - 1 - - - RXRDY1 - Receive Ready 1 Interrupt Enable - 1 - 1 - - - RXOR0 - Receive Overrun 0 Interrupt Enable - 4 - 1 - - - RXOR1 - Receive Overrun 1 Interrupt Enable - 5 - 1 - - - TXRDY0 - Transmit Ready 0 Interrupt Enable - 8 - 1 - - - TXRDY1 - Transmit Ready 1 Interrupt Enable - 9 - 1 - - - TXUR0 - Transmit Underrun 0 Interrupt Enable - 12 - 1 - - - TXUR1 - Transmit Underrun 1 Interrupt Enable - 13 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 16 - 0x0000 - - - RXRDY0 - Receive Ready 0 Interrupt Enable - 0 - 1 - - - RXRDY1 - Receive Ready 1 Interrupt Enable - 1 - 1 - - - RXOR0 - Receive Overrun 0 Interrupt Enable - 4 - 1 - - - RXOR1 - Receive Overrun 1 Interrupt Enable - 5 - 1 - - - TXRDY0 - Transmit Ready 0 Interrupt Enable - 8 - 1 - - - TXRDY1 - Transmit Ready 1 Interrupt Enable - 9 - 1 - - - TXUR0 - Transmit Underrun 0 Interrupt Enable - 12 - 1 - - - TXUR1 - Transmit Underrun 1 Interrupt Enable - 13 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 16 - 0x0000 - - - RXRDY0 - Receive Ready 0 - 0 - 1 - - - RXRDY1 - Receive Ready 1 - 1 - 1 - - - RXOR0 - Receive Overrun 0 - 4 - 1 - - - RXOR1 - Receive Overrun 1 - 5 - 1 - - - TXRDY0 - Transmit Ready 0 - 8 - 1 - - - TXRDY1 - Transmit Ready 1 - 9 - 1 - - - TXUR0 - Transmit Underrun 0 - 12 - 1 - - - TXUR1 - Transmit Underrun 1 - 13 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x18 - 16 - read-only - 0x0000 - - - SWRST - Software Reset Synchronization Status - 0 - 1 - - - ENABLE - Enable Synchronization Status - 1 - 1 - - - CKEN0 - Clock Unit 0 Enable Synchronization Status - 2 - 1 - - - CKEN1 - Clock Unit 1 Enable Synchronization Status - 3 - 1 - - - TXEN - Tx Serializer Enable Synchronization Status - 4 - 1 - - - RXEN - Rx Serializer Enable Synchronization Status - 5 - 1 - - - TXDATA - Tx Data Synchronization Status - 8 - 1 - - - RXDATA - Rx Data Synchronization Status - 9 - 1 - - - - - TXCTRL - Tx Serializer Control - 0x20 - 32 - 0x00000000 - - - SERMODE - Serializer Mode - 0 - 2 - - SERMODESelect - - RX - Receive - 0x0 - - - TX - Transmit - 0x1 - - - PDM2 - Receive one PDM data on each serial clock edge - 0x2 - - - - - TXDEFAULT - Line Default Line when Slot Disabled - 2 - 2 - - TXDEFAULTSelect - - ZERO - Output Default Value is 0 - 0x0 - - - ONE - Output Default Value is 1 - 0x1 - - - HIZ - Output Default Value is high impedance - 0x3 - - - - - TXSAME - Transmit Data when Underrun - 4 - 1 - - TXSAMESelect - - ZERO - Zero data transmitted in case of underrun - 0x0 - - - SAME - Last data transmitted in case of underrun - 0x1 - - - - - CLKSEL - Clock Unit Selection - 5 - 1 - - CLKSELSelect - - CLK0 - Use Clock Unit 0 - 0x0 - - - CLK1 - Use Clock Unit 1 - 0x1 - - - - - SLOTADJ - Data Slot Formatting Adjust - 7 - 1 - - SLOTADJSelect - - RIGHT - Data is right adjusted in slot - 0x0 - - - LEFT - Data is left adjusted in slot - 0x1 - - - - - DATASIZE - Data Word Size - 8 - 3 - - DATASIZESelect - - 32 - 32 bits - 0x0 - - - 24 - 24 bits - 0x1 - - - 20 - 20 bits - 0x2 - - - 18 - 18 bits - 0x3 - - - 16 - 16 bits - 0x4 - - - 16C - 16 bits compact stereo - 0x5 - - - 8 - 8 bits - 0x6 - - - 8C - 8 bits compact stereo - 0x7 - - - - - WORDADJ - Data Word Formatting Adjust - 12 - 1 - - WORDADJSelect - - RIGHT - Data is right adjusted in word - 0x0 - - - LEFT - Data is left adjusted in word - 0x1 - - - - - EXTEND - Data Formatting Bit Extension - 13 - 2 - - EXTENDSelect - - ZERO - Extend with zeroes - 0x0 - - - ONE - Extend with ones - 0x1 - - - MSBIT - Extend with Most Significant Bit - 0x2 - - - LSBIT - Extend with Least Significant Bit - 0x3 - - - - - BITREV - Data Formatting Bit Reverse - 15 - 1 - - BITREVSelect - - MSBIT - Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) - 0x0 - - - LSBIT - Transfer Data Least Significant Bit (LSB) first - 0x1 - - - - - SLOTDIS0 - Slot 0 Disabled for this Serializer - 16 - 1 - - - SLOTDIS1 - Slot 1 Disabled for this Serializer - 17 - 1 - - - SLOTDIS2 - Slot 2 Disabled for this Serializer - 18 - 1 - - - SLOTDIS3 - Slot 3 Disabled for this Serializer - 19 - 1 - - - SLOTDIS4 - Slot 4 Disabled for this Serializer - 20 - 1 - - - SLOTDIS5 - Slot 5 Disabled for this Serializer - 21 - 1 - - - SLOTDIS6 - Slot 6 Disabled for this Serializer - 22 - 1 - - - SLOTDIS7 - Slot 7 Disabled for this Serializer - 23 - 1 - - - MONO - Mono Mode - 24 - 1 - - MONOSelect - - STEREO - Normal mode - 0x0 - - - MONO - Left channel data is duplicated to right channel - 0x1 - - - - - DMA - Single or Multiple DMA Channels - 25 - 1 - - DMASelect - - SINGLE - Single DMA channel - 0x0 - - - MULTIPLE - One DMA channel per data channel - 0x1 - - - - - - - RXCTRL - Rx Serializer Control - 0x24 - 32 - 0x00000000 - - - SERMODE - Serializer Mode - 0 - 2 - - SERMODESelect - - RX - Receive - 0x0 - - - PDM2 - Receive one PDM data on each serial clock edge - 0x2 - - - - - CLKSEL - Clock Unit Selection - 5 - 1 - - CLKSELSelect - - CLK0 - Use Clock Unit 0 - 0x0 - - - CLK1 - Use Clock Unit 1 - 0x1 - - - - - SLOTADJ - Data Slot Formatting Adjust - 7 - 1 - - SLOTADJSelect - - RIGHT - Data is right adjusted in slot - 0x0 - - - LEFT - Data is left adjusted in slot - 0x1 - - - - - DATASIZE - Data Word Size - 8 - 3 - - DATASIZESelect - - 32 - 32 bits - 0x0 - - - 24 - 24 bits - 0x1 - - - 20 - 20 bits - 0x2 - - - 18 - 18 bits - 0x3 - - - 16 - 16 bits - 0x4 - - - 16C - 16 bits compact stereo - 0x5 - - - 8 - 8 bits - 0x6 - - - 8C - 8 bits compact stereo - 0x7 - - - - - WORDADJ - Data Word Formatting Adjust - 12 - 1 - - WORDADJSelect - - RIGHT - Data is right adjusted in word - 0x0 - - - LEFT - Data is left adjusted in word - 0x1 - - - - - EXTEND - Data Formatting Bit Extension - 13 - 2 - - EXTENDSelect - - ZERO - Extend with zeroes - 0x0 - - - ONE - Extend with ones - 0x1 - - - MSBIT - Extend with Most Significant Bit - 0x2 - - - LSBIT - Extend with Least Significant Bit - 0x3 - - - - - BITREV - Data Formatting Bit Reverse - 15 - 1 - - BITREVSelect - - MSBIT - Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) - 0x0 - - - LSBIT - Transfer Data Least Significant Bit (LSB) first - 0x1 - - - - - SLOTDIS0 - Slot 0 Disabled for this Serializer - 16 - 1 - - - SLOTDIS1 - Slot 1 Disabled for this Serializer - 17 - 1 - - - SLOTDIS2 - Slot 2 Disabled for this Serializer - 18 - 1 - - - SLOTDIS3 - Slot 3 Disabled for this Serializer - 19 - 1 - - - SLOTDIS4 - Slot 4 Disabled for this Serializer - 20 - 1 - - - SLOTDIS5 - Slot 5 Disabled for this Serializer - 21 - 1 - - - SLOTDIS6 - Slot 6 Disabled for this Serializer - 22 - 1 - - - SLOTDIS7 - Slot 7 Disabled for this Serializer - 23 - 1 - - - MONO - Mono Mode - 24 - 1 - - MONOSelect - - STEREO - Normal mode - 0x0 - - - MONO - Left channel data is duplicated to right channel - 0x1 - - - - - DMA - Single or Multiple DMA Channels - 25 - 1 - - DMASelect - - SINGLE - Single DMA channel - 0x0 - - - MULTIPLE - One DMA channel per data channel - 0x1 - - - - - RXLOOP - Loop-back Test Mode - 26 - 1 - - - - - TXDATA - Tx Data - 0x30 - 32 - write-only - 0x00000000 - - - DATA - Sample Data - 0 - 32 - - - - - RXDATA - Rx Data - 0x34 - 32 - read-only - 0x00000000 - - - DATA - Sample Data - 0 - 32 - - - - - - - MCLK - U24081.0.0 - Main Clock - MCLK - MCLK_ - 0x40000800 - - 0 - 0x24 - registers - - - MCLK - 1 - - - - INTENCLR - Interrupt Enable Clear - 0x1 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x2 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x3 - 8 - 0x01 - - - CKRDY - Clock Ready - 0 - 1 - - - - - HSDIV - HS Clock Division - 0x4 - 8 - read-only - 0x01 - - - DIV - CPU Clock Division Factor - 0 - 8 - - DIVSelect - - DIV1 - Divide by 1 - 0x01 - - - - - - - CPUDIV - CPU Clock Division - 0x5 - 8 - 0x01 - - - DIV - Low-Power Clock Division Factor - 0 - 8 - - DIVSelect - - DIV1 - Divide by 1 - 0x01 - - - DIV2 - Divide by 2 - 0x02 - - - DIV4 - Divide by 4 - 0x04 - - - DIV8 - Divide by 8 - 0x08 - - - DIV16 - Divide by 16 - 0x10 - - - DIV32 - Divide by 32 - 0x20 - - - DIV64 - Divide by 64 - 0x40 - - - DIV128 - Divide by 128 - 0x80 - - - - - - - AHBMASK - AHB Mask - 0x10 - 32 - 0x00FFFFFF - - - HPB0_ - HPB0 AHB Clock Mask - 0 - 1 - - - HPB1_ - HPB1 AHB Clock Mask - 1 - 1 - - - HPB2_ - HPB2 AHB Clock Mask - 2 - 1 - - - HPB3_ - HPB3 AHB Clock Mask - 3 - 1 - - - DSU_ - DSU AHB Clock Mask - 4 - 1 - - - HMATRIX_ - HMATRIX AHB Clock Mask - 5 - 1 - - - NVMCTRL_ - NVMCTRL AHB Clock Mask - 6 - 1 - - - HSRAM_ - HSRAM AHB Clock Mask - 7 - 1 - - - CMCC_ - CMCC AHB Clock Mask - 8 - 1 - - - DMAC_ - DMAC AHB Clock Mask - 9 - 1 - - - USB_ - USB AHB Clock Mask - 10 - 1 - - - BKUPRAM_ - BKUPRAM AHB Clock Mask - 11 - 1 - - - PAC_ - PAC AHB Clock Mask - 12 - 1 - - - QSPI_ - QSPI AHB Clock Mask - 13 - 1 - - - SDHC0_ - SDHC0 AHB Clock Mask - 15 - 1 - - - CAN0_ - CAN0 AHB Clock Mask - 17 - 1 - - - CAN1_ - CAN1 AHB Clock Mask - 18 - 1 - - - ICM_ - ICM AHB Clock Mask - 19 - 1 - - - PUKCC_ - PUKCC AHB Clock Mask - 20 - 1 - - - QSPI_2X_ - QSPI_2X AHB Clock Mask - 21 - 1 - - - NVMCTRL_SMEEPROM_ - NVMCTRL_SMEEPROM AHB Clock Mask - 22 - 1 - - - NVMCTRL_CACHE_ - NVMCTRL_CACHE AHB Clock Mask - 23 - 1 - - - - - APBAMASK - APBA Mask - 0x14 - 32 - 0x000007FF - - - PAC_ - PAC APB Clock Enable - 0 - 1 - - - PM_ - PM APB Clock Enable - 1 - 1 - - - MCLK_ - MCLK APB Clock Enable - 2 - 1 - - - RSTC_ - RSTC APB Clock Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Clock Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Clock Enable - 5 - 1 - - - SUPC_ - SUPC APB Clock Enable - 6 - 1 - - - GCLK_ - GCLK APB Clock Enable - 7 - 1 - - - WDT_ - WDT APB Clock Enable - 8 - 1 - - - RTC_ - RTC APB Clock Enable - 9 - 1 - - - EIC_ - EIC APB Clock Enable - 10 - 1 - - - FREQM_ - FREQM APB Clock Enable - 11 - 1 - - - SERCOM0_ - SERCOM0 APB Clock Enable - 12 - 1 - - - SERCOM1_ - SERCOM1 APB Clock Enable - 13 - 1 - - - TC0_ - TC0 APB Clock Enable - 14 - 1 - - - TC1_ - TC1 APB Clock Enable - 15 - 1 - - - - - APBBMASK - APBB Mask - 0x18 - 32 - 0x00018056 - - - USB_ - USB APB Clock Enable - 0 - 1 - - - DSU_ - DSU APB Clock Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Clock Enable - 2 - 1 - - - PORT_ - PORT APB Clock Enable - 4 - 1 - - - HMATRIX_ - HMATRIX APB Clock Enable - 6 - 1 - - - EVSYS_ - EVSYS APB Clock Enable - 7 - 1 - - - SERCOM2_ - SERCOM2 APB Clock Enable - 9 - 1 - - - SERCOM3_ - SERCOM3 APB Clock Enable - 10 - 1 - - - TCC0_ - TCC0 APB Clock Enable - 11 - 1 - - - TCC1_ - TCC1 APB Clock Enable - 12 - 1 - - - TC2_ - TC2 APB Clock Enable - 13 - 1 - - - TC3_ - TC3 APB Clock Enable - 14 - 1 - - - RAMECC_ - RAMECC APB Clock Enable - 16 - 1 - - - - - APBCMASK - APBC Mask - 0x1C - 32 - 0x00002000 - - - TCC2_ - TCC2 APB Clock Enable - 3 - 1 - - - TCC3_ - TCC3 APB Clock Enable - 4 - 1 - - - TC4_ - TC4 APB Clock Enable - 5 - 1 - - - TC5_ - TC5 APB Clock Enable - 6 - 1 - - - PDEC_ - PDEC APB Clock Enable - 7 - 1 - - - AC_ - AC APB Clock Enable - 8 - 1 - - - AES_ - AES APB Clock Enable - 9 - 1 - - - TRNG_ - TRNG APB Clock Enable - 10 - 1 - - - ICM_ - ICM APB Clock Enable - 11 - 1 - - - QSPI_ - QSPI APB Clock Enable - 13 - 1 - - - CCL_ - CCL APB Clock Enable - 14 - 1 - - - - - APBDMASK - APBD Mask - 0x20 - 32 - 0x00000000 - - - SERCOM4_ - SERCOM4 APB Clock Enable - 0 - 1 - - - SERCOM5_ - SERCOM5 APB Clock Enable - 1 - 1 - - - TCC4_ - TCC4 APB Clock Enable - 4 - 1 - - - ADC0_ - ADC0 APB Clock Enable - 7 - 1 - - - ADC1_ - ADC1 APB Clock Enable - 8 - 1 - - - DAC_ - DAC APB Clock Enable - 9 - 1 - - - I2S_ - I2S APB Clock Enable - 10 - 1 - - - PCC_ - PCC APB Clock Enable - 11 - 1 - - - - - - - NVMCTRL - U24091.0.0 - Non-Volatile Memory Controller - NVMCTRL - NVMCTRL_ - 0x41004000 - - 0 - 0x30 - registers - - - NVMCTRL_0 - 29 - - - NVMCTRL_1 - 30 - - - - CTRLA - Control A - 0x0 - 16 - 0x0004 - - - AUTOWS - Auto Wait State Enable - 2 - 1 - - - SUSPEN - Suspend Enable - 3 - 1 - - - WMODE - Write Mode - 4 - 2 - - WMODESelect - - MAN - Manual Write - 0 - - - ADW - Automatic Double Word Write - 1 - - - AQW - Automatic Quad Word - 2 - - - AP - Automatic Page Write - 3 - - - - - PRM - Power Reduction Mode during Sleep - 6 - 2 - - PRMSelect - - SEMIAUTO - NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. - 0 - - - FULLAUTO - NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. - 1 - - - MANUAL - NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. - 3 - - - - - RWS - NVM Read Wait States - 8 - 4 - - - AHBNS0 - Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated - 12 - 1 - - - AHBNS1 - Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated - 13 - 1 - - - CACHEDIS0 - AHB0 Cache Disable - 14 - 1 - - - CACHEDIS1 - AHB1 Cache Disable - 15 - 1 - - - - - CTRLB - Control B - 0x4 - 16 - write-only - 0x0000 - - - CMD - Command - 0 - 7 - - CMDSelect - - EP - Erase Page - Only supported in the USER and AUX pages. - 0x0 - - - EB - Erase Block - Erases the block addressed by the ADDR register, not supported in the user page - 0x1 - - - WP - Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page - 0x3 - - - WQW - Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. - 0x4 - - - SWRST - Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers - 0x10 - - - LR - Lock Region - Locks the region containing the address location in the ADDR register. - 0x11 - - - UR - Unlock Region - Unlocks the region containing the address location in the ADDR register. - 0x12 - - - SPRM - Sets the power reduction mode. - 0x13 - - - CPRM - Clears the power reduction mode. - 0x14 - - - PBC - Page Buffer Clear - Clears the page buffer. - 0x15 - - - SSB - Set Security Bit - 0x16 - - - BKSWRST - Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK - 0x17 - - - CELCK - Chip Erase Lock - DSU.CE command is not available - 0x18 - - - CEULCK - Chip Erase Unlock - DSU.CE command is available - 0x19 - - - SBPDIS - Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence - 0x1A - - - CBPDIS - Clears STATUS.BPDIS, Boot loader protection is not discarded - 0x1B - - - ASEES0 - Activate SmartEEPROM Sector 0, deactivate Sector 1 - 0x30 - - - ASEES1 - Activate SmartEEPROM Sector 1, deactivate Sector 0 - 0x31 - - - SEERALOC - Starts SmartEEPROM sector reallocation algorithm - 0x32 - - - SEEFLUSH - Flush SMEE data when in buffered mode - 0x33 - - - LSEE - Lock access to SmartEEPROM data from any mean - 0x34 - - - USEE - Unlock access to SmartEEPROM data - 0x35 - - - LSEER - Lock access to the SmartEEPROM Register Address Space (above 64KB) - 0x36 - - - USEER - Unlock access to the SmartEEPROM Register Address Space (above 64KB) - 0x37 - - - - - CMDEX - Command Execution - 8 - 8 - - CMDEXSelect - - KEY - Execution Key - 0xA5 - - - - - - - PARAM - NVM Parameter - 0x8 - 32 - read-only - 0x00060000 - - - NVMP - NVM Pages - 0 - 16 - - - PSZ - Page Size - 16 - 3 - - PSZSelect - - 8 - 8 bytes - 0x0 - - - 16 - 16 bytes - 0x1 - - - 32 - 32 bytes - 0x2 - - - 64 - 64 bytes - 0x3 - - - 128 - 128 bytes - 0x4 - - - 256 - 256 bytes - 0x5 - - - 512 - 512 bytes - 0x6 - - - 1024 - 1024 bytes - 0x7 - - - - - SEE - SmartEEPROM Supported - 31 - 1 - - SEESelect - - A - 163840 bytes - 0xA - - - 9 - 147456 bytes - 0x9 - - - 8 - 131072 bytes - 0x8 - - - 7 - 114688 bytes - 0x7 - - - 6 - 98304 bytes - 0x6 - - - 5 - 81920 bytes - 0x5 - - - 4 - 65536 bytes - 0x4 - - - 3 - 49152 bytes - 0x3 - - - 2 - 32768 bytes - 0x2 - - - 1 - 16384 bytes - 0x1 - - - 0 - 0 bytes - 0x0 - - - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 16 - 0x0000 - - - DONE - Command Done Interrupt Clear - 0 - 1 - - - ADDRE - Address Error - 1 - 1 - - - PROGE - Programming Error Interrupt Clear - 2 - 1 - - - LOCKE - Lock Error Interrupt Clear - 3 - 1 - - - ECCSE - ECC Single Error Interrupt Clear - 4 - 1 - - - ECCDE - ECC Dual Error Interrupt Clear - 5 - 1 - - - NVME - NVM Error Interrupt Clear - 6 - 1 - - - SUSP - Suspended Write Or Erase Interrupt Clear - 7 - 1 - - - SEESFULL - Active SEES Full Interrupt Clear - 8 - 1 - - - SEESOVF - Active SEES Overflow Interrupt Clear - 9 - 1 - - - SEEWRC - SEE Write Completed Interrupt Clear - 10 - 1 - - - - - INTENSET - Interrupt Enable Set - 0xE - 16 - 0x0000 - - - DONE - Command Done Interrupt Enable - 0 - 1 - - - ADDRE - Address Error Interrupt Enable - 1 - 1 - - - PROGE - Programming Error Interrupt Enable - 2 - 1 - - - LOCKE - Lock Error Interrupt Enable - 3 - 1 - - - ECCSE - ECC Single Error Interrupt Enable - 4 - 1 - - - ECCDE - ECC Dual Error Interrupt Enable - 5 - 1 - - - NVME - NVM Error Interrupt Enable - 6 - 1 - - - SUSP - Suspended Write Or Erase Interrupt Enable - 7 - 1 - - - SEESFULL - Active SEES Full Interrupt Enable - 8 - 1 - - - SEESOVF - Active SEES Overflow Interrupt Enable - 9 - 1 - - - SEEWRC - SEE Write Completed Interrupt Enable - 10 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x10 - 16 - 0x0000 - - - DONE - Command Done - 0 - 1 - - - ADDRE - Address Error - 1 - 1 - - - PROGE - Programming Error - 2 - 1 - - - LOCKE - Lock Error - 3 - 1 - - - ECCSE - ECC Single Error - 4 - 1 - - - ECCDE - ECC Dual Error - 5 - 1 - - - NVME - NVM Error - 6 - 1 - - - SUSP - Suspended Write Or Erase Operation - 7 - 1 - - - SEESFULL - Active SEES Full - 8 - 1 - - - SEESOVF - Active SEES Overflow - 9 - 1 - - - SEEWRC - SEE Write Completed - 10 - 1 - - - - - STATUS - Status - 0x12 - 16 - read-only - 0x0000 - - - READY - Ready to accept a command - 0 - 1 - - - PRM - Power Reduction Mode - 1 - 1 - - - LOAD - NVM Page Buffer Active Loading - 2 - 1 - - - SUSP - NVM Write Or Erase Operation Is Suspended - 3 - 1 - - - AFIRST - BANKA First - 4 - 1 - - - BPDIS - Boot Loader Protection Disable - 5 - 1 - - - BOOTPROT - Boot Loader Protection Size - 8 - 4 - - BOOTPROTSelect - - 0 - 0 kbytes - 0xF - - - 8 - 8 kbytes - 0xE - - - 16 - 16 kbytes - 0xD - - - 24 - 24 kbytes - 0xC - - - 32 - 32 kbytes - 0xB - - - 40 - 40 kbytes - 0xA - - - 48 - 48 kbytes - 0x9 - - - 56 - 56 kbytes - 0x8 - - - 64 - 64 kbytes - 0x7 - - - 72 - 72 kbytes - 0x6 - - - 80 - 80 kbytes - 0x5 - - - 88 - 88 kbytes - 0x4 - - - 96 - 96 kbytes - 0x3 - - - 104 - 104 kbytes - 0x2 - - - 112 - 112 kbytes - 0x1 - - - 120 - 120 kbytes - 0x0 - - - - - - - ADDR - Address - 0x14 - 32 - 0x00000000 - - - ADDR - NVM Address - 0 - 24 - - - - - RUNLOCK - Lock Section - 0x18 - 32 - read-only - 0x00000000 - - - RUNLOCK - Region Un-Lock Bits - 0 - 32 - - - - - 2 - 4 - PBLDATA[%s] - Page Buffer Load Data x - 0x1C - 32 - read-only - 0xFFFFFFFF - - - DATA - Page Buffer Data - 0 - 32 - - - - - ECCERR - ECC Error Status Register - 0x24 - 32 - read-only - 0x00000000 - - - ADDR - Error Address - 0 - 24 - - - TYPEL - Low Double-Word Error Type - 28 - 2 - - TYPELSelect - - None - No Error Detected Since Last Read - 0 - - - Single - At Least One Single Error Detected Since last Read - 1 - - - Dual - At Least One Dual Error Detected Since Last Read - 2 - - - - - TYPEH - High Double-Word Error Type - 30 - 2 - - TYPEHSelect - - None - No Error Detected Since Last Read - 0 - - - Single - At Least One Single Error Detected Since last Read - 1 - - - Dual - At Least One Dual Error Detected Since Last Read - 2 - - - - - - - DBGCTRL - Debug Control - 0x28 - 8 - 0x00 - - - ECCDIS - Debugger ECC Read Disable - 0 - 1 - - - ECCELOG - Debugger ECC Error Tracking Mode - 1 - 1 - - - - - SEECFG - SmartEEPROM Configuration Register - 0x2A - 8 - 0x00 - - - WMODE - Write Mode - 0 - 1 - - WMODESelect - - UNBUFFERED - A NVM write command is issued after each write in the pagebuffer - 0 - - - BUFFERED - A NVM write command is issued when a write to a new page is requested - 1 - - - - - APRDIS - Automatic Page Reallocation Disable - 1 - 1 - - - - - SEESTAT - SmartEEPROM Status Register - 0x2C - 32 - read-only - 0x00000000 - - - ASEES - Active SmartEEPROM Sector - 0 - 1 - - - LOAD - Page Buffer Loaded - 1 - 1 - - - BUSY - Busy - 2 - 1 - - - LOCK - SmartEEPROM Write Access Is Locked - 3 - 1 - - - RLOCK - SmartEEPROM Write Access To Register Address Space Is Locked - 4 - 1 - - - SBLK - Blocks Number In a Sector - 8 - 4 - - - PSZ - SmartEEPROM Page Size - 16 - 3 - - - - - - - OSCCTRL - U24011.0.0 - Oscillators Control - OSCCTRL - OSCCTRL_ - 0x40001000 - - 0 - 0x58 - registers - - - OSCCTRL_XOSC0 - 2 - - - OSCCTRL_XOSC1 - 3 - - - OSCCTRL_DFLL - 4 - - - OSCCTRL_DPLL0 - 5 - - - OSCCTRL_DPLL1 - 6 - - - - EVCTRL - Event Control - 0x0 - 8 - 0x00 - - - CFDEO0 - Clock 0 Failure Detector Event Output Enable - 0 - 1 - - - CFDEO1 - Clock 1 Failure Detector Event Output Enable - 1 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 32 - 0x00000000 - - - XOSCRDY0 - XOSC 0 Ready Interrupt Enable - 0 - 1 - - - XOSCRDY1 - XOSC 1 Ready Interrupt Enable - 1 - 1 - - - XOSCFAIL0 - XOSC 0 Clock Failure Detector Interrupt Enable - 2 - 1 - - - XOSCFAIL1 - XOSC 1 Clock Failure Detector Interrupt Enable - 3 - 1 - - - DFLLRDY - DFLL Ready Interrupt Enable - 8 - 1 - - - DFLLOOB - DFLL Out Of Bounds Interrupt Enable - 9 - 1 - - - DFLLLCKF - DFLL Lock Fine Interrupt Enable - 10 - 1 - - - DFLLLCKC - DFLL Lock Coarse Interrupt Enable - 11 - 1 - - - DFLLRCS - DFLL Reference Clock Stopped Interrupt Enable - 12 - 1 - - - DPLL0LCKR - DPLL0 Lock Rise Interrupt Enable - 16 - 1 - - - DPLL0LCKF - DPLL0 Lock Fall Interrupt Enable - 17 - 1 - - - DPLL0LTO - DPLL0 Lock Timeout Interrupt Enable - 18 - 1 - - - DPLL0LDRTO - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable - 19 - 1 - - - DPLL1LCKR - DPLL1 Lock Rise Interrupt Enable - 24 - 1 - - - DPLL1LCKF - DPLL1 Lock Fall Interrupt Enable - 25 - 1 - - - DPLL1LTO - DPLL1 Lock Timeout Interrupt Enable - 26 - 1 - - - DPLL1LDRTO - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable - 27 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x8 - 32 - 0x00000000 - - - XOSCRDY0 - XOSC 0 Ready Interrupt Enable - 0 - 1 - - - XOSCRDY1 - XOSC 1 Ready Interrupt Enable - 1 - 1 - - - XOSCFAIL0 - XOSC 0 Clock Failure Detector Interrupt Enable - 2 - 1 - - - XOSCFAIL1 - XOSC 1 Clock Failure Detector Interrupt Enable - 3 - 1 - - - DFLLRDY - DFLL Ready Interrupt Enable - 8 - 1 - - - DFLLOOB - DFLL Out Of Bounds Interrupt Enable - 9 - 1 - - - DFLLLCKF - DFLL Lock Fine Interrupt Enable - 10 - 1 - - - DFLLLCKC - DFLL Lock Coarse Interrupt Enable - 11 - 1 - - - DFLLRCS - DFLL Reference Clock Stopped Interrupt Enable - 12 - 1 - - - DPLL0LCKR - DPLL0 Lock Rise Interrupt Enable - 16 - 1 - - - DPLL0LCKF - DPLL0 Lock Fall Interrupt Enable - 17 - 1 - - - DPLL0LTO - DPLL0 Lock Timeout Interrupt Enable - 18 - 1 - - - DPLL0LDRTO - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable - 19 - 1 - - - DPLL1LCKR - DPLL1 Lock Rise Interrupt Enable - 24 - 1 - - - DPLL1LCKF - DPLL1 Lock Fall Interrupt Enable - 25 - 1 - - - DPLL1LTO - DPLL1 Lock Timeout Interrupt Enable - 26 - 1 - - - DPLL1LDRTO - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable - 27 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xC - 32 - 0x00000000 - - - XOSCRDY0 - XOSC 0 Ready - 0 - 1 - - - XOSCRDY1 - XOSC 1 Ready - 1 - 1 - - - XOSCFAIL0 - XOSC 0 Clock Failure Detector - 2 - 1 - - - XOSCFAIL1 - XOSC 1 Clock Failure Detector - 3 - 1 - - - DFLLRDY - DFLL Ready - 8 - 1 - - - DFLLOOB - DFLL Out Of Bounds - 9 - 1 - - - DFLLLCKF - DFLL Lock Fine - 10 - 1 - - - DFLLLCKC - DFLL Lock Coarse - 11 - 1 - - - DFLLRCS - DFLL Reference Clock Stopped - 12 - 1 - - - DPLL0LCKR - DPLL0 Lock Rise - 16 - 1 - - - DPLL0LCKF - DPLL0 Lock Fall - 17 - 1 - - - DPLL0LTO - DPLL0 Lock Timeout - 18 - 1 - - - DPLL0LDRTO - DPLL0 Loop Divider Ratio Update Complete - 19 - 1 - - - DPLL1LCKR - DPLL1 Lock Rise - 24 - 1 - - - DPLL1LCKF - DPLL1 Lock Fall - 25 - 1 - - - DPLL1LTO - DPLL1 Lock Timeout - 26 - 1 - - - DPLL1LDRTO - DPLL1 Loop Divider Ratio Update Complete - 27 - 1 - - - - - STATUS - Status - 0x10 - 32 - read-only - 0x00000000 - - - XOSCRDY0 - XOSC 0 Ready - 0 - 1 - - - XOSCRDY1 - XOSC 1 Ready - 1 - 1 - - - XOSCFAIL0 - XOSC 0 Clock Failure Detector - 2 - 1 - - - XOSCFAIL1 - XOSC 1 Clock Failure Detector - 3 - 1 - - - XOSCCKSW0 - XOSC 0 Clock Switch - 4 - 1 - - - XOSCCKSW1 - XOSC 1 Clock Switch - 5 - 1 - - - DFLLRDY - DFLL Ready - 8 - 1 - - - DFLLOOB - DFLL Out Of Bounds - 9 - 1 - - - DFLLLCKF - DFLL Lock Fine - 10 - 1 - - - DFLLLCKC - DFLL Lock Coarse - 11 - 1 - - - DFLLRCS - DFLL Reference Clock Stopped - 12 - 1 - - - DPLL0LCKR - DPLL0 Lock Rise - 16 - 1 - - - DPLL0LCKF - DPLL0 Lock Fall - 17 - 1 - - - DPLL0TO - DPLL0 Timeout - 18 - 1 - - - DPLL0LDRTO - DPLL0 Loop Divider Ratio Update Complete - 19 - 1 - - - DPLL1LCKR - DPLL1 Lock Rise - 24 - 1 - - - DPLL1LCKF - DPLL1 Lock Fall - 25 - 1 - - - DPLL1TO - DPLL1 Timeout - 26 - 1 - - - DPLL1LDRTO - DPLL1 Loop Divider Ratio Update Complete - 27 - 1 - - - - - 2 - 4 - XOSCCTRL[%s] - External Multipurpose Crystal Oscillator Control - 0x14 - 32 - 0x00000080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - LOWBUFGAIN - Low Buffer Gain Enable - 8 - 1 - - - IPTAT - Oscillator Current Reference - 9 - 2 - - - IMULT - Oscillator Current Multiplier - 11 - 4 - - - ENALC - Automatic Loop Control Enable - 15 - 1 - - - CFDEN - Clock Failure Detector Enable - 16 - 1 - - - SWBEN - Xosc Clock Switch Enable - 17 - 1 - - - STARTUP - Start-Up Time - 20 - 4 - - STARTUPSelect - - CYCLE1 - 31 us - 0 - - - CYCLE2 - 61 us - 1 - - - CYCLE4 - 122 us - 2 - - - CYCLE8 - 244 us - 3 - - - CYCLE16 - 488 us - 4 - - - CYCLE32 - 977 us - 5 - - - CYCLE64 - 1953 us - 6 - - - CYCLE128 - 3906 us - 7 - - - CYCLE256 - 7813 us - 8 - - - CYCLE512 - 15625 us - 9 - - - CYCLE1024 - 31250 us - 10 - - - CYCLE2048 - 62500 us - 11 - - - CYCLE4096 - 125000 us - 12 - - - CYCLE8192 - 250000 us - 13 - - - CYCLE16384 - 500000 us - 14 - - - CYCLE32768 - 1000000 us - 15 - - - - - CFDPRESC - Clock Failure Detector Prescaler - 24 - 4 - - CFDPRESCSelect - - DIV1 - 48 MHz - 0 - - - DIV2 - 24 MHz - 1 - - - DIV4 - 12 MHz - 2 - - - DIV8 - 6 MHz - 3 - - - DIV16 - 3 MHz - 4 - - - DIV32 - 1.5 MHz - 5 - - - DIV64 - 0.75 MHz - 6 - - - DIV128 - 0.3125 MHz - 7 - - - - - - - DFLLCTRLA - DFLL48M Control A - 0x1C - 8 - 0x82 - - - ENABLE - DFLL Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - DFLLCTRLB - DFLL48M Control B - 0x20 - 8 - 0x00 - - - MODE - Operating Mode Selection - 0 - 1 - - - STABLE - Stable DFLL Frequency - 1 - 1 - - - LLAW - Lose Lock After Wake - 2 - 1 - - - USBCRM - USB Clock Recovery Mode - 3 - 1 - - - CCDIS - Chill Cycle Disable - 4 - 1 - - - QLDIS - Quick Lock Disable - 5 - 1 - - - BPLCKC - Bypass Coarse Lock - 6 - 1 - - - WAITLOCK - Wait Lock - 7 - 1 - - - - - DFLLVAL - DFLL48M Value - 0x24 - 32 - 0x00000000 - - - FINE - Fine Value - 0 - 8 - - - COARSE - Coarse Value - 10 - 6 - - - DIFF - Multiplication Ratio Difference - 16 - 16 - - - - - DFLLMUL - DFLL48M Multiplier - 0x28 - 32 - 0x00000000 - - - MUL - DFLL Multiply Factor - 0 - 16 - - - FSTEP - Fine Maximum Step - 16 - 8 - - - CSTEP - Coarse Maximum Step - 26 - 6 - - - - - DFLLSYNC - DFLL48M Synchronization - 0x2C - 8 - 0x00 - - - ENABLE - ENABLE Synchronization Busy - 1 - 1 - - - DFLLCTRLB - DFLLCTRLB Synchronization Busy - 2 - 1 - - - DFLLVAL - DFLLVAL Synchronization Busy - 3 - 1 - - - DFLLMUL - DFLLMUL Synchronization Busy - 4 - 1 - - - - - 2 - 0x14 - DPLL[%s] - - 0x30 - - DPLLCTRLA - DPLL Control A - 0x0 - 8 - 0x80 - - - ENABLE - DPLL Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - DPLLRATIO - DPLL Ratio Control - 0x4 - 32 - 0x00000000 - - - LDR - Loop Divider Ratio - 0 - 13 - - - LDRFRAC - Loop Divider Ratio Fractional Part - 16 - 5 - - - - - DPLLCTRLB - DPLL Control B - 0x8 - 32 - 0x00000020 - - - FILTER - Proportional Integral Filter Selection - 0 - 4 - - FILTERSelect - - FILTER1 - Bandwidth = 92.7Khz and Damping Factor = 0.76 - 0 - - - FILTER2 - Bandwidth = 131Khz and Damping Factor = 1.08 - 1 - - - FILTER3 - Bandwidth = 46.4Khz and Damping Factor = 0.38 - 2 - - - FILTER4 - Bandwidth = 65.6Khz and Damping Factor = 0.54 - 3 - - - FILTER5 - Bandwidth = 131Khz and Damping Factor = 0.56 - 4 - - - FILTER6 - Bandwidth = 185Khz and Damping Factor = 0.79 - 5 - - - FILTER7 - Bandwidth = 65.6Khz and Damping Factor = 0.28 - 6 - - - FILTER8 - Bandwidth = 92.7Khz and Damping Factor = 0.39 - 7 - - - FILTER9 - Bandwidth = 46.4Khz and Damping Factor = 1.49 - 8 - - - FILTER10 - Bandwidth = 65.6Khz and Damping Factor = 2.11 - 9 - - - FILTER11 - Bandwidth = 23.2Khz and Damping Factor = 0.75 - 10 - - - FILTER12 - Bandwidth = 32.8Khz and Damping Factor = 1.06 - 11 - - - FILTER13 - Bandwidth = 65.6Khz and Damping Factor = 1.07 - 12 - - - FILTER14 - Bandwidth = 92.7Khz and Damping Factor = 1.51 - 13 - - - FILTER15 - Bandwidth = 32.8Khz and Damping Factor = 0.53 - 14 - - - FILTER16 - Bandwidth = 46.4Khz and Damping Factor = 0.75 - 15 - - - - - WUF - Wake Up Fast - 4 - 1 - - - REFCLK - Reference Clock Selection - 5 - 3 - - REFCLKSelect - - GCLK - Dedicated GCLK clock reference - 0x0 - - - XOSC32 - XOSC32K clock reference - 0x1 - - - XOSC0 - XOSC0 clock reference - 0x2 - - - XOSC1 - XOSC1 clock reference - 0x3 - - - - - LTIME - Lock Time - 8 - 3 - - LTIMESelect - - DEFAULT - No time-out. Automatic lock - 0x0 - - - 800US - Time-out if no lock within 800us - 0x4 - - - 900US - Time-out if no lock within 900us - 0x5 - - - 1MS - Time-out if no lock within 1ms - 0x6 - - - 1P1MS - Time-out if no lock within 1.1ms - 0x7 - - - - - LBYPASS - Lock Bypass - 11 - 1 - - - DCOFILTER - Sigma-Delta DCO Filter Selection - 12 - 3 - - DCOFILTERSelect - - FILTER1 - Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 - 0 - - - FILTER2 - Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 - 1 - - - FILTER3 - Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 - 2 - - - FILTER4 - Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 - 3 - - - FILTER5 - Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 - 4 - - - FILTER6 - Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 - 5 - - - FILTER7 - Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 - 6 - - - FILTER8 - Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 - 7 - - - - - DCOEN - DCO Filter Enable - 15 - 1 - - - DIV - Clock Divider - 16 - 11 - - - - - DPLLSYNCBUSY - DPLL Synchronization Busy - 0xC - 32 - read-only - 0x00000000 - - - ENABLE - DPLL Enable Synchronization Status - 1 - 1 - - - DPLLRATIO - DPLL Loop Divider Ratio Synchronization Status - 2 - 1 - - - - - DPLLSTATUS - DPLL Status - 0x10 - 32 - read-only - 0x00000000 - - - LOCK - DPLL Lock Status - 0 - 1 - - - CLKRDY - DPLL Clock Ready - 1 - 1 - - - - - - - - OSC32KCTRL - U24001.0.0 - 32kHz Oscillators Control - OSC32KCTRL - OSC32KCTRL_ - 0x40001400 - - 0 - 0x20 - registers - - - OSC32KCTRL - 7 - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - XOSC32KFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - XOSC32KFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - XOSC32KFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - XOSC32KFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - XOSC32KSW - XOSC32K Clock switch - 3 - 1 - - - - - RTCCTRL - RTC Clock Selection - 0x10 - 8 - 0x00 - - - RTCSEL - RTC Clock Selection - 0 - 3 - - RTCSELSelect - - ULP1K - 1.024kHz from 32kHz internal ULP oscillator - 0 - - - ULP32K - 32.768kHz from 32kHz internal ULP oscillator - 1 - - - XOSC1K - 1.024kHz from 32.768kHz internal oscillator - 4 - - - XOSC32K - 32.768kHz from 32.768kHz external crystal oscillator - 5 - - - - - - - XOSC32K - 32kHz External Crystal Oscillator (XOSC32K) Control - 0x14 - 16 - 0x2080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - EN32K - 32kHz Output Enable - 3 - 1 - - - EN1K - 1kHz Output Enable - 4 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - STARTUP - Oscillator Start-Up Time - 8 - 3 - - STARTUPSelect - - CYCLE2048 - 62.6 ms - 0 - - - CYCLE4096 - 125 ms - 1 - - - CYCLE16384 - 500 ms - 2 - - - CYCLE32768 - 1000 ms - 3 - - - CYCLE65536 - 2000 ms - 4 - - - CYCLE131072 - 4000 ms - 5 - - - CYCLE262144 - 8000 ms - 6 - - - - - WRTLOCK - Write Lock - 12 - 1 - - - CGM - Control Gain Mode - 13 - 2 - - CGMSelect - - XT - Standard mode - 1 - - - HS - High Speed mode - 2 - - - - - - - CFDCTRL - Clock Failure Detector Control - 0x16 - 8 - 0x00 - - - CFDEN - Clock Failure Detector Enable - 0 - 1 - - - SWBACK - Clock Switch Back - 1 - 1 - - - CFDPRESC - Clock Failure Detector Prescaler - 2 - 1 - - - - - EVCTRL - Event Control - 0x17 - 8 - 0x00 - - - CFDEO - Clock Failure Detector Event Output Enable - 0 - 1 - - - - - OSCULP32K - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control - 0x1C - 32 - 0x00000000 - - - EN32K - Enable Out 32k - 1 - 1 - - - EN1K - Enable Out 1k - 2 - 1 - - - CALIB - Oscillator Calibration - 8 - 6 - - - WRTLOCK - Write Lock - 15 - 1 - - - - - - - PAC - U21201.2.0 - Peripheral Access Controller - PAC - PAC_ - 0x40000000 - - 0 - 0x44 - registers - - - PAC - 41 - - - - WRCTRL - Write control - 0x0 - 32 - 0x00000000 - - - PERID - Peripheral identifier - 0 - 16 - - - KEY - Peripheral access control key - 16 - 8 - - KEYSelect - - OFF - No action - 0 - - - CLR - Clear protection - 1 - - - SET - Set protection - 2 - - - SETLCK - Set and lock protection - 3 - - - - - - - EVCTRL - Event control - 0x4 - 8 - 0x00 - - - ERREO - Peripheral acess error event output - 0 - 1 - - - - - INTENCLR - Interrupt enable clear - 0x8 - 8 - 0x00 - - - ERR - Peripheral access error interrupt disable - 0 - 1 - - - - - INTENSET - Interrupt enable set - 0x9 - 8 - 0x00 - - - ERR - Peripheral access error interrupt enable - 0 - 1 - - - - - INTFLAGAHB - Bridge interrupt flag status - 0x10 - 32 - 0x00000000 - - - FLASH_ - FLASH - 0 - 1 - - - FLASH_ALT_ - FLASH_ALT - 1 - 1 - - - SEEPROM_ - SEEPROM - 2 - 1 - - - RAMCM4S_ - RAMCM4S - 3 - 1 - - - RAMPPPDSU_ - RAMPPPDSU - 4 - 1 - - - RAMDMAWR_ - RAMDMAWR - 5 - 1 - - - RAMDMACICM_ - RAMDMACICM - 6 - 1 - - - HPB0_ - HPB0 - 7 - 1 - - - HPB1_ - HPB1 - 8 - 1 - - - HPB2_ - HPB2 - 9 - 1 - - - HPB3_ - HPB3 - 10 - 1 - - - PUKCC_ - PUKCC - 11 - 1 - - - SDHC0_ - SDHC0 - 12 - 1 - - - QSPI_ - QSPI - 14 - 1 - - - BKUPRAM_ - BKUPRAM - 15 - 1 - - - - - INTFLAGA - Peripheral interrupt flag status - Bridge A - 0x14 - 32 - 0x00000000 - - - PAC_ - PAC - 0 - 1 - - - PM_ - PM - 1 - 1 - - - MCLK_ - MCLK - 2 - 1 - - - RSTC_ - RSTC - 3 - 1 - - - OSCCTRL_ - OSCCTRL - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL - 5 - 1 - - - SUPC_ - SUPC - 6 - 1 - - - GCLK_ - GCLK - 7 - 1 - - - WDT_ - WDT - 8 - 1 - - - RTC_ - RTC - 9 - 1 - - - EIC_ - EIC - 10 - 1 - - - FREQM_ - FREQM - 11 - 1 - - - SERCOM0_ - SERCOM0 - 12 - 1 - - - SERCOM1_ - SERCOM1 - 13 - 1 - - - TC0_ - TC0 - 14 - 1 - - - TC1_ - TC1 - 15 - 1 - - - - - INTFLAGB - Peripheral interrupt flag status - Bridge B - 0x18 - 32 - 0x00000000 - - - USB_ - USB - 0 - 1 - - - DSU_ - DSU - 1 - 1 - - - NVMCTRL_ - NVMCTRL - 2 - 1 - - - CMCC_ - CMCC - 3 - 1 - - - PORT_ - PORT - 4 - 1 - - - DMAC_ - DMAC - 5 - 1 - - - HMATRIX_ - HMATRIX - 6 - 1 - - - EVSYS_ - EVSYS - 7 - 1 - - - SERCOM2_ - SERCOM2 - 9 - 1 - - - SERCOM3_ - SERCOM3 - 10 - 1 - - - TCC0_ - TCC0 - 11 - 1 - - - TCC1_ - TCC1 - 12 - 1 - - - TC2_ - TC2 - 13 - 1 - - - TC3_ - TC3 - 14 - 1 - - - RAMECC_ - RAMECC - 16 - 1 - - - - - INTFLAGC - Peripheral interrupt flag status - Bridge C - 0x1C - 32 - 0x00000000 - - - CAN0_ - CAN0 - 0 - 1 - - - CAN1_ - CAN1 - 1 - 1 - - - TCC2_ - TCC2 - 3 - 1 - - - TCC3_ - TCC3 - 4 - 1 - - - TC4_ - TC4 - 5 - 1 - - - TC5_ - TC5 - 6 - 1 - - - PDEC_ - PDEC - 7 - 1 - - - AC_ - AC - 8 - 1 - - - AES_ - AES - 9 - 1 - - - TRNG_ - TRNG - 10 - 1 - - - ICM_ - ICM - 11 - 1 - - - PUKCC_ - PUKCC - 12 - 1 - - - QSPI_ - QSPI - 13 - 1 - - - CCL_ - CCL - 14 - 1 - - - - - INTFLAGD - Peripheral interrupt flag status - Bridge D - 0x20 - 32 - 0x00000000 - - - SERCOM4_ - SERCOM4 - 0 - 1 - - - SERCOM5_ - SERCOM5 - 1 - 1 - - - TCC4_ - TCC4 - 4 - 1 - - - ADC0_ - ADC0 - 7 - 1 - - - ADC1_ - ADC1 - 8 - 1 - - - DAC_ - DAC - 9 - 1 - - - I2S_ - I2S - 10 - 1 - - - PCC_ - PCC - 11 - 1 - - - - - STATUSA - Peripheral write protection status - Bridge A - 0x34 - 32 - read-only - 0x00010000 - - - PAC_ - PAC APB Protect Enable - 0 - 1 - - - PM_ - PM APB Protect Enable - 1 - 1 - - - MCLK_ - MCLK APB Protect Enable - 2 - 1 - - - RSTC_ - RSTC APB Protect Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Protect Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Protect Enable - 5 - 1 - - - SUPC_ - SUPC APB Protect Enable - 6 - 1 - - - GCLK_ - GCLK APB Protect Enable - 7 - 1 - - - WDT_ - WDT APB Protect Enable - 8 - 1 - - - RTC_ - RTC APB Protect Enable - 9 - 1 - - - EIC_ - EIC APB Protect Enable - 10 - 1 - - - FREQM_ - FREQM APB Protect Enable - 11 - 1 - - - SERCOM0_ - SERCOM0 APB Protect Enable - 12 - 1 - - - SERCOM1_ - SERCOM1 APB Protect Enable - 13 - 1 - - - TC0_ - TC0 APB Protect Enable - 14 - 1 - - - TC1_ - TC1 APB Protect Enable - 15 - 1 - - - - - STATUSB - Peripheral write protection status - Bridge B - 0x38 - 32 - read-only - 0x00000002 - - - USB_ - USB APB Protect Enable - 0 - 1 - - - DSU_ - DSU APB Protect Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Protect Enable - 2 - 1 - - - CMCC_ - CMCC APB Protect Enable - 3 - 1 - - - PORT_ - PORT APB Protect Enable - 4 - 1 - - - DMAC_ - DMAC APB Protect Enable - 5 - 1 - - - HMATRIX_ - HMATRIX APB Protect Enable - 6 - 1 - - - EVSYS_ - EVSYS APB Protect Enable - 7 - 1 - - - SERCOM2_ - SERCOM2 APB Protect Enable - 9 - 1 - - - SERCOM3_ - SERCOM3 APB Protect Enable - 10 - 1 - - - TCC0_ - TCC0 APB Protect Enable - 11 - 1 - - - TCC1_ - TCC1 APB Protect Enable - 12 - 1 - - - TC2_ - TC2 APB Protect Enable - 13 - 1 - - - TC3_ - TC3 APB Protect Enable - 14 - 1 - - - RAMECC_ - RAMECC APB Protect Enable - 16 - 1 - - - - - STATUSC - Peripheral write protection status - Bridge C - 0x3C - 32 - read-only - 0x00000000 - - - CAN0_ - CAN0 APB Protect Enable - 0 - 1 - - - CAN1_ - CAN1 APB Protect Enable - 1 - 1 - - - TCC2_ - TCC2 APB Protect Enable - 3 - 1 - - - TCC3_ - TCC3 APB Protect Enable - 4 - 1 - - - TC4_ - TC4 APB Protect Enable - 5 - 1 - - - TC5_ - TC5 APB Protect Enable - 6 - 1 - - - PDEC_ - PDEC APB Protect Enable - 7 - 1 - - - AC_ - AC APB Protect Enable - 8 - 1 - - - AES_ - AES APB Protect Enable - 9 - 1 - - - TRNG_ - TRNG APB Protect Enable - 10 - 1 - - - ICM_ - ICM APB Protect Enable - 11 - 1 - - - PUKCC_ - PUKCC APB Protect Enable - 12 - 1 - - - QSPI_ - QSPI APB Protect Enable - 13 - 1 - - - CCL_ - CCL APB Protect Enable - 14 - 1 - - - - - STATUSD - Peripheral write protection status - Bridge D - 0x40 - 32 - read-only - 0x00000000 - - - SERCOM4_ - SERCOM4 APB Protect Enable - 0 - 1 - - - SERCOM5_ - SERCOM5 APB Protect Enable - 1 - 1 - - - TCC4_ - TCC4 APB Protect Enable - 4 - 1 - - - ADC0_ - ADC0 APB Protect Enable - 7 - 1 - - - ADC1_ - ADC1 APB Protect Enable - 8 - 1 - - - DAC_ - DAC APB Protect Enable - 9 - 1 - - - I2S_ - I2S APB Protect Enable - 10 - 1 - - - PCC_ - PCC APB Protect Enable - 11 - 1 - - - - - - - PCC - U20171.1.0 - Parallel Capture Controller - PCC - PCC_ - 0x43002C00 - - 0 - 0xE8 - registers - - - PCC - 129 - - - - MR - Mode Register - 0x0 - 32 - 0x00000000 - - - PCEN - Parallel Capture Enable - 0 - 1 - - - DSIZE - Data size - 4 - 2 - - - SCALE - Scale data - 8 - 1 - - - ALWYS - Always Sampling - 9 - 1 - - - HALFS - Half Sampling - 10 - 1 - - - FRSTS - First sample - 11 - 1 - - - ISIZE - Input Data Size - 16 - 3 - - - CID - Clear If Disabled - 30 - 2 - - - - - IER - Interrupt Enable Register - 0x4 - 32 - write-only - 0x00000000 - - - DRDY - Data Ready Interrupt Enable - 0 - 1 - - - OVRE - Overrun Error Interrupt Enable - 1 - 1 - - - - - IDR - Interrupt Disable Register - 0x8 - 32 - write-only - 0x00000000 - - - DRDY - Data Ready Interrupt Disable - 0 - 1 - - - OVRE - Overrun Error Interrupt Disable - 1 - 1 - - - - - IMR - Interrupt Mask Register - 0xC - 32 - read-only - 0x00000000 - - - DRDY - Data Ready Interrupt Mask - 0 - 1 - - - OVRE - Overrun Error Interrupt Mask - 1 - 1 - - - - - ISR - Interrupt Status Register - 0x10 - 32 - read-only - 0x00000000 - - - DRDY - Data Ready Interrupt Status - 0 - 1 - - - OVRE - Overrun Error Interrupt Status - 1 - 1 - - - - - RHR - Reception Holding Register - 0x14 - 32 - read-only - 0x00000000 - - - RDATA - Reception Data - 0 - 32 - - - - - WPMR - Write Protection Mode Register - 0xE0 - 32 - 0x00000000 - - - WPEN - Write Protection Enable - 0 - 1 - - - WPKEY - Write Protection Key - 8 - 24 - - - - - WPSR - Write Protection Status Register - 0xE4 - 32 - read-only - 0x00000000 - - - WPVS - Write Protection Violation Source - 0 - 1 - - - WPVSRC - Write Protection Violation Status - 8 - 16 - - - - - - - PDEC - U22631.0.0 - Quadrature Decodeur - PDEC - PDEC_ - 0x42001C00 - - 0 - 0x38 - registers - - - PDEC_OTHER - 115 - - - PDEC_MC0 - 116 - - - PDEC_MC1 - 117 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operation Mode - 2 - 2 - - MODESelect - - QDEC - QDEC operating mode - 0 - - - HALL - HALL operating mode - 1 - - - COUNTER - COUNTER operating mode - 2 - - - - - RUNSTDBY - Run in Standby - 6 - 1 - - - CONF - PDEC Configuration - 8 - 3 - - CONFSelect - - X4 - Quadrature decoder direction - 0 - - - X4S - Secure Quadrature decoder direction - 1 - - - X2 - Decoder direction - 2 - - - X2S - Secure decoder direction - 3 - - - AUTOC - Auto correction mode - 4 - - - - - ALOCK - Auto Lock - 11 - 1 - - - SWAP - PDEC Phase A and B Swap - 14 - 1 - - - PEREN - Period Enable - 15 - 1 - - - PINEN0 - PDEC Input From Pin 0 Enable - 16 - 1 - - - PINEN1 - PDEC Input From Pin 1 Enable - 17 - 1 - - - PINEN2 - PDEC Input From Pin 2 Enable - 18 - 1 - - - PINVEN0 - IO Pin 0 Invert Enable - 20 - 1 - - - PINVEN1 - IO Pin 1 Invert Enable - 21 - 1 - - - PINVEN2 - IO Pin 2 Invert Enable - 22 - 1 - - - ANGULAR - Angular Counter Length - 24 - 3 - - - MAXCMP - Maximum Consecutive Missing Pulses - 28 - 4 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - LUPD - Lock Update - 1 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a counter restart or retrigger - 1 - - - UPDATE - Force update of double buffered registers - 2 - - - READSYNC - Force a read synchronization of COUNT - 3 - - - START - Start QDEC/HALL - 4 - - - STOP - Stop QDEC/HALL - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - LUPD - Lock Update - 1 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a counter restart or retrigger - 1 - - - UPDATE - Force update of double buffered registers - 2 - - - READSYNC - Force a read synchronization of COUNT - 3 - - - START - Start QDEC/HALL - 4 - - - STOP - Stop QDEC/HALL - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 2 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger on event - 1 - - - COUNT - Count on event - 2 - - - - - EVINV - Inverted Event Input Enable - 2 - 3 - - - EVEI - Event Input Enable - 5 - 3 - - - OVFEO - Overflow/Underflow Output Event Enable - 8 - 1 - - - ERREO - Error Output Event Enable - 9 - 1 - - - DIREO - Direction Output Event Enable - 10 - 1 - - - VLCEO - Velocity Output Event Enable - 11 - 1 - - - MCEO0 - Match Channel 0 Event Output Enable - 12 - 1 - - - MCEO1 - Match Channel 1 Event Output Enable - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - Overflow/Underflow Interrupt Disable - 0 - 1 - - - ERR - Error Interrupt Disable - 1 - 1 - - - DIR - Direction Interrupt Disable - 2 - 1 - - - VLC - Velocity Interrupt Disable - 3 - 1 - - - MC0 - Channel 0 Compare Match Disable - 4 - 1 - - - MC1 - Channel 1 Compare Match Disable - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - Overflow/Underflow Interrupt Enable - 0 - 1 - - - ERR - Error Interrupt Enable - 1 - 1 - - - DIR - Direction Interrupt Enable - 2 - 1 - - - VLC - Velocity Interrupt Enable - 3 - 1 - - - MC0 - Channel 0 Compare Match Enable - 4 - 1 - - - MC1 - Channel 1 Compare Match Enable - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - Overflow/Underflow - 0 - 1 - - - ERR - Error - 1 - 1 - - - DIR - Direction Change - 2 - 1 - - - VLC - Velocity - 3 - 1 - - - MC0 - Channel 0 Compare Match - 4 - 1 - - - MC1 - Channel 1 Compare Match - 5 - 1 - - - - - STATUS - Status - 0xC - 16 - 0x0040 - - - QERR - Quadrature Error Flag - 0 - 1 - - - IDXERR - Index Error Flag - 1 - 1 - - - MPERR - Missing Pulse Error flag - 2 - 1 - - - WINERR - Window Error Flag - 4 - 1 - - - HERR - Hall Error Flag - 5 - 1 - - - STOP - Stop - 6 - 1 - - - DIR - Direction Status Flag - 7 - 1 - - - PRESCBUFV - Prescaler Buffer Valid - 8 - 1 - - - FILTERBUFV - Filter Buffer Valid - 9 - 1 - - - CCBUFV0 - Compare Channel 0 Buffer Valid - 12 - 1 - - - CCBUFV1 - Compare Channel 1 Buffer Valid - 13 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Debug Run Mode - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - CTRLB - Control B Synchronization Busy - 2 - 1 - - - STATUS - Status Synchronization Busy - 3 - 1 - - - PRESC - Prescaler Synchronization Busy - 4 - 1 - - - FILTER - Filter Synchronization Busy - 5 - 1 - - - COUNT - Count Synchronization Busy - 6 - 1 - - - CC0 - Compare Channel 0 Synchronization Busy - 7 - 1 - - - CC1 - Compare Channel 1 Synchronization Busy - 8 - 1 - - - - - PRESC - Prescaler Value - 0x14 - 8 - 0x00 - - - PRESC - Prescaler Value - 0 - 4 - - PRESCSelect - - DIV1 - No division - 0 - - - DIV2 - Divide by 2 - 1 - - - DIV4 - Divide by 4 - 2 - - - DIV8 - Divide by 8 - 3 - - - DIV16 - Divide by 16 - 4 - - - DIV32 - Divide by 32 - 5 - - - DIV64 - Divide by 64 - 6 - - - DIV128 - Divide by 128 - 7 - - - DIV256 - Divide by 256 - 8 - - - DIV512 - Divide by 512 - 9 - - - DIV1024 - Divide by 1024 - 10 - - - - - - - FILTER - Filter Value - 0x15 - 8 - 0x00 - - - FILTER - Filter Value - 0 - 8 - - - - - PRESCBUF - Prescaler Buffer Value - 0x18 - 8 - 0x00 - - - PRESCBUF - Prescaler Buffer Value - 0 - 4 - - PRESCBUFSelect - - DIV1 - No division - 0 - - - DIV2 - Divide by 2 - 1 - - - DIV4 - Divide by 4 - 2 - - - DIV8 - Divide by 8 - 3 - - - DIV16 - Divide by 16 - 4 - - - DIV32 - Divide by 32 - 5 - - - DIV64 - Divide by 64 - 6 - - - DIV128 - Divide by 128 - 7 - - - DIV256 - Divide by 256 - 8 - - - DIV512 - Divide by 512 - 9 - - - DIV1024 - Divide by 1024 - 10 - - - - - - - FILTERBUF - Filter Buffer Value - 0x19 - 8 - 0x00 - - - FILTERBUF - Filter Buffer Value - 0 - 8 - - - - - COUNT - Counter Value - 0x1C - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 16 - - - - - 2 - 4 - CC[%s] - Channel n Compare Value - 0x20 - 32 - 0x00000000 - - - CC - Channel Compare Value - 0 - 16 - - - - - 2 - 4 - CCBUF[%s] - Channel Compare Buffer Value - 0x30 - 32 - 0x00000000 - - - CCBUF - Channel Compare Buffer Value - 0 - 16 - - - - - - - PM - U24061.0.0 - Power Manager - PM - PM_ - 0x40000400 - - 0 - 0x13 - registers - - - PM - 0 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - IORET - I/O Retention - 2 - 1 - - - - - SLEEPCFG - Sleep Configuration - 0x1 - 8 - 0x02 - - - SLEEPMODE - Sleep Mode - 0 - 3 - - SLEEPMODESelect - - IDLE - CPU, AHBx, and APBx clocks are OFF - 2 - - - STANDBY - All Clocks are OFF - 4 - - - HIBERNATE - Backup domain is ON as well as some PDRAMs - 5 - - - BACKUP - Only Backup domain is powered ON - 6 - - - OFF - All power domains are powered OFF - 7 - - - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - SLEEPRDY - Sleep Mode Entry Ready Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - SLEEPRDY - Sleep Mode Entry Ready Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - SLEEPRDY - Sleep Mode Entry Ready - 0 - 1 - - - - - STDBYCFG - Standby Configuration - 0x8 - 8 - 0x00 - - - RAMCFG - Ram Configuration - 0 - 2 - - RAMCFGSelect - - RET - All the system RAM is retained - 0 - - - PARTIAL - Only the first 32Kbytes of the system RAM is retained - 1 - - - OFF - All the system RAM is turned OFF - 2 - - - - - FASTWKUP - Fast Wakeup - 4 - 2 - - FASTWKUPSelect - - NO - Fast Wakeup is disabled - 0 - - - NVM - Fast Wakeup is enabled on NVM - 1 - - - MAINVREG - Fast Wakeup is enabled on the main voltage regulator (MAINVREG) - 2 - - - BOTH - Fast Wakeup is enabled on both NVM and MAINVREG - 3 - - - - - - - HIBCFG - Hibernate Configuration - 0x9 - 8 - 0x00 - - - RAMCFG - Ram Configuration - 0 - 2 - - RAMCFGSelect - - RET - All the system RAM is retained - 0 - - - PARTIAL - Only the first 32Kbytes of the system RAM is retained - 1 - - - OFF - All the system RAM is turned OFF - 2 - - - - - BRAMCFG - Backup Ram Configuration - 2 - 2 - - BRAMCFGSelect - - RET - All the backup RAM is retained - 0 - - - PARTIAL - Only the first 4Kbytes of the backup RAM is retained - 1 - - - OFF - All the backup RAM is turned OFF - 2 - - - - - - - BKUPCFG - Backup Configuration - 0xA - 8 - 0x00 - - - BRAMCFG - Ram Configuration - 0 - 2 - - BRAMCFGSelect - - RET - All the backup RAM is retained - 0 - - - PARTIAL - Only the first 4Kbytes of the backup RAM is retained - 1 - - - OFF - All the backup RAM is turned OFF - 2 - - - - - - - PWSAKDLY - Power Switch Acknowledge Delay - 0x12 - 8 - 0x00 - - - DLYVAL - Delay Value - 0 - 7 - - - IGNACK - Ignore Acknowledge - 7 - 1 - - - - - - - PORT - U22102.2.0 - Port Module - PORT - PORT_ - 0x41008000 - - 0 - 0x100 - registers - - - - 2 - 0x80 - GROUP[%s] - - 0x00 - - DIR - Data Direction - 0x0 - 32 - 0x00000000 - - - DIR - Port Data Direction - 0 - 32 - - - - - DIRCLR - Data Direction Clear - 0x4 - 32 - 0x00000000 - - - DIRCLR - Port Data Direction Clear - 0 - 32 - - - - - DIRSET - Data Direction Set - 0x8 - 32 - 0x00000000 - - - DIRSET - Port Data Direction Set - 0 - 32 - - - - - DIRTGL - Data Direction Toggle - 0xC - 32 - 0x00000000 - - - DIRTGL - Port Data Direction Toggle - 0 - 32 - - - - - OUT - Data Output Value - 0x10 - 32 - 0x00000000 - - - OUT - PORT Data Output Value - 0 - 32 - - - - - OUTCLR - Data Output Value Clear - 0x14 - 32 - 0x00000000 - - - OUTCLR - PORT Data Output Value Clear - 0 - 32 - - - - - OUTSET - Data Output Value Set - 0x18 - 32 - 0x00000000 - - - OUTSET - PORT Data Output Value Set - 0 - 32 - - - - - OUTTGL - Data Output Value Toggle - 0x1C - 32 - 0x00000000 - - - OUTTGL - PORT Data Output Value Toggle - 0 - 32 - - - - - IN - Data Input Value - 0x20 - 32 - read-only - 0x00000000 - - - IN - PORT Data Input Value - 0 - 32 - - - - - CTRL - Control - 0x24 - 32 - 0x00000000 - - - SAMPLING - Input Sampling Mode - 0 - 32 - - - - - WRCONFIG - Write Configuration - 0x28 - 32 - write-only - 0x00000000 - - - PINMASK - Pin Mask for Multiple Pin Configuration - 0 - 16 - - - PMUXEN - Peripheral Multiplexer Enable - 16 - 1 - - - INEN - Input Enable - 17 - 1 - - - PULLEN - Pull Enable - 18 - 1 - - - DRVSTR - Output Driver Strength Selection - 22 - 1 - - - PMUX - Peripheral Multiplexing - 24 - 4 - - - WRPMUX - Write PMUX - 28 - 1 - - - WRPINCFG - Write PINCFG - 30 - 1 - - - HWSEL - Half-Word Select - 31 - 1 - - - - - EVCTRL - Event Input Control - 0x2C - 32 - 0x00000000 - - - PID0 - PORT Event Pin Identifier 0 - 0 - 5 - - - EVACT0 - PORT Event Action 0 - 5 - 2 - - EVACT0Select - - OUT - Event output to pin - 0x0 - - - SET - Set output register of pin on event - 0x1 - - - CLR - Clear output register of pin on event - 0x2 - - - TGL - Toggle output register of pin on event - 0x3 - - - - - PORTEI0 - PORT Event Input Enable 0 - 7 - 1 - - - PID1 - PORT Event Pin Identifier 1 - 8 - 5 - - - EVACT1 - PORT Event Action 1 - 13 - 2 - - - PORTEI1 - PORT Event Input Enable 1 - 15 - 1 - - - PID2 - PORT Event Pin Identifier 2 - 16 - 5 - - - EVACT2 - PORT Event Action 2 - 21 - 2 - - - PORTEI2 - PORT Event Input Enable 2 - 23 - 1 - - - PID3 - PORT Event Pin Identifier 3 - 24 - 5 - - - EVACT3 - PORT Event Action 3 - 29 - 2 - - - PORTEI3 - PORT Event Input Enable 3 - 31 - 1 - - - - - 16 - 1 - PMUX[%s] - Peripheral Multiplexing - 0x30 - 8 - 0x00 - - - PMUXE - Peripheral Multiplexing for Even-Numbered Pin - 0 - 4 - - - PMUXO - Peripheral Multiplexing for Odd-Numbered Pin - 4 - 4 - - - - - 32 - 1 - PINCFG[%s] - Pin Configuration - 0x40 - 8 - 0x00 - - - PMUXEN - Peripheral Multiplexer Enable - 0 - 1 - - - INEN - Input Enable - 1 - 1 - - - PULLEN - Pull Enable - 2 - 1 - - - DRVSTR - Output Driver Strength Selection - 6 - 1 - - - - - - - - QSPI - U20081.6.3 - Quad SPI interface - QSPI - QSPI_ - 0x42003400 - - 0 - 0x48 - registers - - - QSPI - 134 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - LASTXFER - Last Transfer - 24 - 1 - - - - - CTRLB - Control B - 0x4 - 32 - 0x00000000 - - - MODE - Serial Memory Mode - 0 - 1 - - MODESelect - - SPI - SPI operating mode - 0 - - - MEMORY - Serial Memory operating mode - 1 - - - - - LOOPEN - Local Loopback Enable - 1 - 1 - - - WDRBT - Wait Data Read Before Transfer - 2 - 1 - - - SMEMREG - Serial Memory reg - 3 - 1 - - - CSMODE - Chip Select Mode - 4 - 2 - - CSMODESelect - - NORELOAD - The chip select is deasserted if TD has not been reloaded before the end of the current transfer. - 0x0 - - - LASTXFER - The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. - 0x1 - - - SYSTEMATICALLY - The chip select is deasserted systematically after each transfer. - 0x2 - - - - - DATALEN - Data Length - 8 - 4 - - DATALENSelect - - 8BITS - 8-bits transfer - 0x0 - - - 9BITS - 9 bits transfer - 0x1 - - - 10BITS - 10-bits transfer - 0x2 - - - 11BITS - 11-bits transfer - 0x3 - - - 12BITS - 12-bits transfer - 0x4 - - - 13BITS - 13-bits transfer - 0x5 - - - 14BITS - 14-bits transfer - 0x6 - - - 15BITS - 15-bits transfer - 0x7 - - - 16BITS - 16-bits transfer - 0x8 - - - - - DLYBCT - Delay Between Consecutive Transfers - 16 - 8 - - - DLYCS - Minimum Inactive CS Delay - 24 - 8 - - - - - BAUD - Baud Rate - 0x8 - 32 - 0x00000000 - - - CPOL - Clock Polarity - 0 - 1 - - - CPHA - Clock Phase - 1 - 1 - - - BAUD - Serial Clock Baud Rate - 8 - 8 - - - DLYBS - Delay Before SCK - 16 - 8 - - - - - RXDATA - Receive Data - 0xC - 32 - read-only - 0x00000000 - - - DATA - Receive Data - 0 - 16 - - - - - TXDATA - Transmit Data - 0x10 - 32 - write-only - 0x00000000 - - - DATA - Transmit Data - 0 - 16 - - - - - INTENCLR - Interrupt Enable Clear - 0x14 - 32 - 0x00000000 - - - RXC - Receive Data Register Full Interrupt Disable - 0 - 1 - - - DRE - Transmit Data Register Empty Interrupt Disable - 1 - 1 - - - TXC - Transmission Complete Interrupt Disable - 2 - 1 - - - ERROR - Overrun Error Interrupt Disable - 3 - 1 - - - CSRISE - Chip Select Rise Interrupt Disable - 8 - 1 - - - INSTREND - Instruction End Interrupt Disable - 10 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x18 - 32 - 0x00000000 - - - RXC - Receive Data Register Full Interrupt Enable - 0 - 1 - - - DRE - Transmit Data Register Empty Interrupt Enable - 1 - 1 - - - TXC - Transmission Complete Interrupt Enable - 2 - 1 - - - ERROR - Overrun Error Interrupt Enable - 3 - 1 - - - CSRISE - Chip Select Rise Interrupt Enable - 8 - 1 - - - INSTREND - Instruction End Interrupt Enable - 10 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x1C - 32 - 0x00000000 - - - RXC - Receive Data Register Full - 0 - 1 - - - DRE - Transmit Data Register Empty - 1 - 1 - - - TXC - Transmission Complete - 2 - 1 - - - ERROR - Overrun Error - 3 - 1 - - - CSRISE - Chip Select Rise - 8 - 1 - - - INSTREND - Instruction End - 10 - 1 - - - - - STATUS - Status Register - 0x20 - 32 - read-only - 0x00000200 - - - ENABLE - Enable - 1 - 1 - - - CSSTATUS - Chip Select - 9 - 1 - - - - - INSTRADDR - Instruction Address - 0x30 - 32 - 0x00000000 - - - ADDR - Instruction Address - 0 - 32 - - - - - INSTRCTRL - Instruction Code - 0x34 - 32 - 0x00000000 - - - INSTR - Instruction Code - 0 - 8 - - - OPTCODE - Option Code - 16 - 8 - - - - - INSTRFRAME - Instruction Frame - 0x38 - 32 - 0x00000000 - - - WIDTH - Instruction Code, Address, Option Code and Data Width - 0 - 3 - - WIDTHSelect - - SINGLE_BIT_SPI - Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI - 0x0 - - - DUAL_OUTPUT - Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI - 0x1 - - - QUAD_OUTPUT - Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI - 0x2 - - - DUAL_IO - Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI - 0x3 - - - QUAD_IO - Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI - 0x4 - - - DUAL_CMD - Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI - 0x5 - - - QUAD_CMD - Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI - 0x6 - - - - - INSTREN - Instruction Enable - 4 - 1 - - - ADDREN - Address Enable - 5 - 1 - - - OPTCODEEN - Option Enable - 6 - 1 - - - DATAEN - Data Enable - 7 - 1 - - - OPTCODELEN - Option Code Length - 8 - 2 - - OPTCODELENSelect - - 1BIT - 1-bit length option code - 0x0 - - - 2BITS - 2-bits length option code - 0x1 - - - 4BITS - 4-bits length option code - 0x2 - - - 8BITS - 8-bits length option code - 0x3 - - - - - ADDRLEN - Address Length - 10 - 1 - - ADDRLENSelect - - 24BITS - 24-bits address length - 0 - - - 32BITS - 32-bits address length - 1 - - - - - TFRTYPE - Data Transfer Type - 12 - 2 - - TFRTYPESelect - - READ - Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. - 0x0 - - - READMEMORY - Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. - 0x1 - - - WRITE - Write transfer into the serial memory.Scrambling is not performed. - 0x2 - - - WRITEMEMORY - Write data transfer into the serial memory.If enabled, scrambling is performed. - 0x3 - - - - - CRMODE - Continuous Read Mode - 14 - 1 - - - DDREN - Double Data Rate Enable - 15 - 1 - - - DUMMYLEN - Dummy Cycles Length - 16 - 5 - - - - - SCRAMBCTRL - Scrambling Mode - 0x40 - 32 - 0x00000000 - - - ENABLE - Scrambling/Unscrambling Enable - 0 - 1 - - - RANDOMDIS - Scrambling/Unscrambling Random Value Disable - 1 - 1 - - - - - SCRAMBKEY - Scrambling Key - 0x44 - 32 - write-only - 0x00000000 - - - KEY - Scrambling User Key - 0 - 32 - - - - - - - RAMECC - U22681.0.0 - RAM ECC - RAMECC - RAMECC_ - 0x41020000 - - 0 - 0x10 - registers - - - RAMECC - 45 - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 8 - 0x00 - - - SINGLEE - Single Bit ECC Error Interrupt Enable Clear - 0 - 1 - - - DUALE - Dual Bit ECC Error Interrupt Enable Clear - 1 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x1 - 8 - 0x00 - - - SINGLEE - Single Bit ECC Error Interrupt Enable Set - 0 - 1 - - - DUALE - Dual Bit ECC Error Interrupt Enable Set - 1 - 1 - - - - - INTFLAG - Interrupt Flag - 0x2 - 8 - 0x00 - - - SINGLEE - Single Bit ECC Error Interrupt - 0 - 1 - - - DUALE - Dual Bit ECC Error Interrupt - 1 - 1 - - - - - STATUS - Status - 0x3 - 8 - read-only - 0x00 - - - ECCDIS - ECC Disable - 0 - 1 - - - - - ERRADDR - Error Address - 0x4 - 32 - read-only - 0x00000000 - - - ERRADDR - Error Address - 0 - 17 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - ECCDIS - ECC Disable - 0 - 1 - - - ECCELOG - ECC Error Log - 1 - 1 - - - - - - - RSTC - U22394.0.0 - Reset Controller - RSTC - RSTC_ - 0x40000C00 - - 0 - 0x3 - registers - - - - RCAUSE - Reset Cause - 0x0 - 8 - read-only - - - POR - Power On Reset - 0 - 1 - - - BODCORE - Brown Out CORE Detector Reset - 1 - 1 - - - BODVDD - Brown Out VDD Detector Reset - 2 - 1 - - - NVM - NVM Reset - 3 - 1 - - - EXT - External Reset - 4 - 1 - - - WDT - Watchdog Reset - 5 - 1 - - - SYST - System Reset Request - 6 - 1 - - - BACKUP - Backup Reset - 7 - 1 - - - - - BKUPEXIT - Backup Exit Source - 0x2 - 8 - read-only - 0x00 - - - RTC - Real Timer Counter Interrupt - 1 - 1 - - - BBPS - Battery Backup Power Switch - 2 - 1 - - - HIB - Hibernate - 7 - 1 - - - - - - - RTC - U22502.1.0 - Real-Time Counter - RTC - RTC_ - 0x40002400 - - 0 - 0xA0 - registers - - - RTC - 11 - - - - MODE0 - 32-bit Counter with Single 32-bit Compare - RtcMode0 - 0x0 - - CTRLA - MODE0 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0x0 - - - COUNT16 - Mode 1: 16-bit Counter - 0x1 - - - CLOCK - Mode 2: Clock/Calendar - 0x2 - - - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - BKTRST - BKUP Registers Reset On Tamper Enable - 13 - 1 - - - GPTRST - GP Registers Reset On Tamper Enable - 14 - 1 - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - CTRLB - MODE0 Control B - 0x2 - 16 - 0x0000 - - - GP0EN - General Purpose 0 Enable - 0 - 1 - - - GP2EN - General Purpose 2 Enable - 1 - 1 - - - DEBMAJ - Debouncer Majority Enable - 4 - 1 - - - DEBASYNC - Debouncer Asynchronous Enable - 5 - 1 - - - RTCOUT - RTC Output Enable - 6 - 1 - - - DMAEN - DMA Enable - 7 - 1 - - - DEBF - Debounce Freqnuency - 8 - 3 - - DEBFSelect - - DIV2 - CLK_RTC_DEB = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_DEB = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_DEB = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_DEB = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_DEB = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_DEB = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_DEB = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_DEB = CLK_RTC/256 - 0x7 - - - - - ACTF - Active Layer Freqnuency - 12 - 3 - - ACTFSelect - - DIV2 - CLK_RTC_OUT = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_OUT = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_OUT = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_OUT = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_OUT = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_OUT = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_OUT = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_OUT = CLK_RTC/256 - 0x7 - - - - - - - EVCTRL - MODE0 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - CMPEO1 - Compare 1 Event Output Enable - 9 - 1 - - - TAMPEREO - Tamper Event Output Enable - 14 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - TAMPEVEI - Tamper Event Input Enable - 16 - 1 - - - - - INTENCLR - MODE0 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE0 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE0 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - CMP1 - Compare 1 - 9 - 1 - - - TAMPER - Tamper - 14 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE0 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COMP1 - COMP 1 Register Busy - 6 - 1 - - - COUNTSYNC - Count Synchronization Enable Bit Busy - 15 - 1 - - - GP0 - General Purpose 0 Register Busy - 16 - 1 - - - GP1 - General Purpose 1 Register Busy - 17 - 1 - - - GP2 - General Purpose 2 Register Busy - 18 - 1 - - - GP3 - General Purpose 3 Register Busy - 19 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE0 Counter Value - 0x18 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - 2 - 4 - COMP[%s] - MODE0 Compare n Value - 0x20 - 32 - 0x00000000 - - - COMP - Compare Value - 0 - 32 - - - - - 4 - 4 - GP[%s] - General Purpose - 0x40 - 32 - 0x00000000 - - - GP - General Purpose - 0 - 32 - - - - - TAMPCTRL - Tamper Control - 0x60 - 32 - 0x00000000 - - - IN0ACT - Tamper Input 0 Action - 0 - 2 - - IN0ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN0 to OUT - 0x3 - - - - - IN1ACT - Tamper Input 1 Action - 2 - 2 - - IN1ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN1 to OUT - 0x3 - - - - - IN2ACT - Tamper Input 2 Action - 4 - 2 - - IN2ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN2 to OUT - 0x3 - - - - - IN3ACT - Tamper Input 3 Action - 6 - 2 - - IN3ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN3 to OUT - 0x3 - - - - - IN4ACT - Tamper Input 4 Action - 8 - 2 - - IN4ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN4 to OUT - 0x3 - - - - - TAMLVL0 - Tamper Level Select 0 - 16 - 1 - - - TAMLVL1 - Tamper Level Select 1 - 17 - 1 - - - TAMLVL2 - Tamper Level Select 2 - 18 - 1 - - - TAMLVL3 - Tamper Level Select 3 - 19 - 1 - - - TAMLVL4 - Tamper Level Select 4 - 20 - 1 - - - DEBNC0 - Debouncer Enable 0 - 24 - 1 - - - DEBNC1 - Debouncer Enable 1 - 25 - 1 - - - DEBNC2 - Debouncer Enable 2 - 26 - 1 - - - DEBNC3 - Debouncer Enable 3 - 27 - 1 - - - DEBNC4 - Debouncer Enable 4 - 28 - 1 - - - - - TIMESTAMP - MODE0 Timestamp - 0x64 - 32 - read-only - 0x00000000 - - - COUNT - Count Timestamp Value - 0 - 32 - - - - - TAMPID - Tamper ID - 0x68 - 32 - 0x00000000 - - - TAMPID0 - Tamper Input 0 Detected - 0 - 1 - - - TAMPID1 - Tamper Input 1 Detected - 1 - 1 - - - TAMPID2 - Tamper Input 2 Detected - 2 - 1 - - - TAMPID3 - Tamper Input 3 Detected - 3 - 1 - - - TAMPID4 - Tamper Input 4 Detected - 4 - 1 - - - TAMPEVT - Tamper Event Detected - 31 - 1 - - - - - 8 - 4 - BKUP[%s] - Backup - 0x80 - 32 - 0x00000000 - - - BKUP - Backup - 0 - 32 - - - - - - MODE1 - 16-bit Counter with Two 16-bit Compares - MODE0 - RtcMode1 - 0x0 - - CTRLA - MODE1 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - BKTRST - BKUP Registers Reset On Tamper Enable - 13 - 1 - - - GPTRST - GP Registers Reset On Tamper Enable - 14 - 1 - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - CTRLB - MODE1 Control B - 0x2 - 16 - 0x0000 - - - GP0EN - General Purpose 0 Enable - 0 - 1 - - - GP2EN - General Purpose 2 Enable - 1 - 1 - - - DEBMAJ - Debouncer Majority Enable - 4 - 1 - - - DEBASYNC - Debouncer Asynchronous Enable - 5 - 1 - - - RTCOUT - RTC Output Enable - 6 - 1 - - - DMAEN - DMA Enable - 7 - 1 - - - DEBF - Debounce Freqnuency - 8 - 3 - - DEBFSelect - - DIV2 - CLK_RTC_DEB = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_DEB = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_DEB = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_DEB = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_DEB = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_DEB = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_DEB = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_DEB = CLK_RTC/256 - 0x7 - - - - - ACTF - Active Layer Freqnuency - 12 - 3 - - ACTFSelect - - DIV2 - CLK_RTC_OUT = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_OUT = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_OUT = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_OUT = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_OUT = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_OUT = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_OUT = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_OUT = CLK_RTC/256 - 0x7 - - - - - - - EVCTRL - MODE1 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - CMPEO1 - Compare 1 Event Output Enable - 9 - 1 - - - CMPEO2 - Compare 2 Event Output Enable - 10 - 1 - - - CMPEO3 - Compare 3 Event Output Enable - 11 - 1 - - - TAMPEREO - Tamper Event Output Enable - 14 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - TAMPEVEI - Tamper Event Input Enable - 16 - 1 - - - - - INTENCLR - MODE1 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - CMP2 - Compare 2 Interrupt Enable - 10 - 1 - - - CMP3 - Compare 3 Interrupt Enable - 11 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE1 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - CMP2 - Compare 2 Interrupt Enable - 10 - 1 - - - CMP3 - Compare 3 Interrupt Enable - 11 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE1 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - CMP1 - Compare 1 - 9 - 1 - - - CMP2 - Compare 2 - 10 - 1 - - - CMP3 - Compare 3 - 11 - 1 - - - TAMPER - Tamper - 14 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE1 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - PER - PER Register Busy - 4 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COMP1 - COMP 1 Register Busy - 6 - 1 - - - COMP2 - COMP 2 Register Busy - 7 - 1 - - - COMP3 - COMP 3 Register Busy - 8 - 1 - - - COUNTSYNC - Count Synchronization Enable Bit Busy - 15 - 1 - - - GP0 - General Purpose 0 Register Busy - 16 - 1 - - - GP1 - General Purpose 1 Register Busy - 17 - 1 - - - GP2 - General Purpose 2 Register Busy - 18 - 1 - - - GP3 - General Purpose 3 Register Busy - 19 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE1 Counter Value - 0x18 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - PER - MODE1 Counter Period - 0x1C - 16 - 0x0000 - - - PER - Counter Period - 0 - 16 - - - - - 4 - 2 - COMP[%s] - MODE1 Compare n Value - 0x20 - 16 - 0x0000 - - - COMP - Compare Value - 0 - 16 - - - - - 4 - 4 - GP[%s] - General Purpose - 0x40 - 32 - 0x00000000 - - - GP - General Purpose - 0 - 32 - - - - - TAMPCTRL - Tamper Control - 0x60 - 32 - 0x00000000 - - - IN0ACT - Tamper Input 0 Action - 0 - 2 - - IN0ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN0 to OUT - 0x3 - - - - - IN1ACT - Tamper Input 1 Action - 2 - 2 - - IN1ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN1 to OUT - 0x3 - - - - - IN2ACT - Tamper Input 2 Action - 4 - 2 - - IN2ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN2 to OUT - 0x3 - - - - - IN3ACT - Tamper Input 3 Action - 6 - 2 - - IN3ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN3 to OUT - 0x3 - - - - - IN4ACT - Tamper Input 4 Action - 8 - 2 - - IN4ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN4 to OUT - 0x3 - - - - - TAMLVL0 - Tamper Level Select 0 - 16 - 1 - - - TAMLVL1 - Tamper Level Select 1 - 17 - 1 - - - TAMLVL2 - Tamper Level Select 2 - 18 - 1 - - - TAMLVL3 - Tamper Level Select 3 - 19 - 1 - - - TAMLVL4 - Tamper Level Select 4 - 20 - 1 - - - DEBNC0 - Debouncer Enable 0 - 24 - 1 - - - DEBNC1 - Debouncer Enable 1 - 25 - 1 - - - DEBNC2 - Debouncer Enable 2 - 26 - 1 - - - DEBNC3 - Debouncer Enable 3 - 27 - 1 - - - DEBNC4 - Debouncer Enable 4 - 28 - 1 - - - - - TIMESTAMP - MODE1 Timestamp - 0x64 - 32 - read-only - 0x00000000 - - - COUNT - Count Timestamp Value - 0 - 16 - - - - - TAMPID - Tamper ID - 0x68 - 32 - 0x00000000 - - - TAMPID0 - Tamper Input 0 Detected - 0 - 1 - - - TAMPID1 - Tamper Input 1 Detected - 1 - 1 - - - TAMPID2 - Tamper Input 2 Detected - 2 - 1 - - - TAMPID3 - Tamper Input 3 Detected - 3 - 1 - - - TAMPID4 - Tamper Input 4 Detected - 4 - 1 - - - TAMPEVT - Tamper Event Detected - 31 - 1 - - - - - 8 - 4 - BKUP[%s] - Backup - 0x80 - 32 - 0x00000000 - - - BKUP - Backup - 0 - 32 - - - - - - MODE2 - Clock/Calendar with Alarm - MODE0 - RtcMode2 - 0x0 - - CTRLA - MODE2 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - CLKREP - Clock Representation - 6 - 1 - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - BKTRST - BKUP Registers Reset On Tamper Enable - 13 - 1 - - - GPTRST - GP Registers Reset On Tamper Enable - 14 - 1 - - - CLOCKSYNC - Clock Read Synchronization Enable - 15 - 1 - - - - - CTRLB - MODE2 Control B - 0x2 - 16 - 0x0000 - - - GP0EN - General Purpose 0 Enable - 0 - 1 - - - GP2EN - General Purpose 2 Enable - 1 - 1 - - - DEBMAJ - Debouncer Majority Enable - 4 - 1 - - - DEBASYNC - Debouncer Asynchronous Enable - 5 - 1 - - - RTCOUT - RTC Output Enable - 6 - 1 - - - DMAEN - DMA Enable - 7 - 1 - - - DEBF - Debounce Freqnuency - 8 - 3 - - DEBFSelect - - DIV2 - CLK_RTC_DEB = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_DEB = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_DEB = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_DEB = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_DEB = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_DEB = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_DEB = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_DEB = CLK_RTC/256 - 0x7 - - - - - ACTF - Active Layer Freqnuency - 12 - 3 - - ACTFSelect - - DIV2 - CLK_RTC_OUT = CLK_RTC/2 - 0x0 - - - DIV4 - CLK_RTC_OUT = CLK_RTC/4 - 0x1 - - - DIV8 - CLK_RTC_OUT = CLK_RTC/8 - 0x2 - - - DIV16 - CLK_RTC_OUT = CLK_RTC/16 - 0x3 - - - DIV32 - CLK_RTC_OUT = CLK_RTC/32 - 0x4 - - - DIV64 - CLK_RTC_OUT = CLK_RTC/64 - 0x5 - - - DIV128 - CLK_RTC_OUT = CLK_RTC/128 - 0x6 - - - DIV256 - CLK_RTC_OUT = CLK_RTC/256 - 0x7 - - - - - - - EVCTRL - MODE2 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - ALARMEO0 - Alarm 0 Event Output Enable - 8 - 1 - - - ALARMEO1 - Alarm 1 Event Output Enable - 9 - 1 - - - TAMPEREO - Tamper Event Output Enable - 14 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - TAMPEVEI - Tamper Event Input Enable - 16 - 1 - - - - - INTENCLR - MODE2 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - ALARM1 - Alarm 1 Interrupt Enable - 9 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE2 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - ALARM1 - Alarm 1 Interrupt Enable - 9 - 1 - - - TAMPER - Tamper Enable - 14 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE2 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - ALARM0 - Alarm 0 - 8 - 1 - - - ALARM1 - Alarm 1 - 9 - 1 - - - TAMPER - Tamper - 14 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE2 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - CLOCK - CLOCK Register Busy - 3 - 1 - - - ALARM0 - ALARM 0 Register Busy - 5 - 1 - - - ALARM1 - ALARM 1 Register Busy - 6 - 1 - - - MASK0 - MASK 0 Register Busy - 11 - 1 - - - MASK1 - MASK 1 Register Busy - 12 - 1 - - - CLOCKSYNC - Clock Synchronization Enable Bit Busy - 15 - 1 - - - GP0 - General Purpose 0 Register Busy - 16 - 1 - - - GP1 - General Purpose 1 Register Busy - 17 - 1 - - - GP2 - General Purpose 2 Register Busy - 18 - 1 - - - GP3 - General Purpose 3 Register Busy - 19 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - CLOCK - MODE2 Clock Value - 0x18 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - AM when CLKREP in 12-hour - 0x00 - - - PM - PM when CLKREP in 12-hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - 4 - 4 - GP[%s] - General Purpose - 0x40 - 32 - 0x00000000 - - - GP - General Purpose - 0 - 32 - - - - - ALARM0 - MODE2_ALARM Alarm n Value - 0x20 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - Morning hour - 0x00 - - - PM - Afternoon hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - MASK0 - MODE2_ALARM Alarm n Mask - 0x24 - 8 - 0x00 - - - SEL - Alarm Mask Selection - 0 - 3 - - SELSelect - - OFF - Alarm Disabled - 0x0 - - - SS - Match seconds only - 0x1 - - - MMSS - Match seconds and minutes only - 0x2 - - - HHMMSS - Match seconds, minutes, and hours only - 0x3 - - - DDHHMMSS - Match seconds, minutes, hours, and days only - 0x4 - - - MMDDHHMMSS - Match seconds, minutes, hours, days, and months only - 0x5 - - - YYMMDDHHMMSS - Match seconds, minutes, hours, days, months, and years - 0x6 - - - - - - - ALARM1 - MODE2_ALARM Alarm n Value - 0x28 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - Morning hour - 0x00 - - - PM - Afternoon hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - MASK1 - MODE2_ALARM Alarm n Mask - 0x2C - 8 - 0x00 - - - SEL - Alarm Mask Selection - 0 - 3 - - SELSelect - - OFF - Alarm Disabled - 0x0 - - - SS - Match seconds only - 0x1 - - - MMSS - Match seconds and minutes only - 0x2 - - - HHMMSS - Match seconds, minutes, and hours only - 0x3 - - - DDHHMMSS - Match seconds, minutes, hours, and days only - 0x4 - - - MMDDHHMMSS - Match seconds, minutes, hours, days, and months only - 0x5 - - - YYMMDDHHMMSS - Match seconds, minutes, hours, days, months, and years - 0x6 - - - - - - - TAMPCTRL - Tamper Control - 0x60 - 32 - 0x00000000 - - - IN0ACT - Tamper Input 0 Action - 0 - 2 - - IN0ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN0 to OUT - 0x3 - - - - - IN1ACT - Tamper Input 1 Action - 2 - 2 - - IN1ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN1 to OUT - 0x3 - - - - - IN2ACT - Tamper Input 2 Action - 4 - 2 - - IN2ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN2 to OUT - 0x3 - - - - - IN3ACT - Tamper Input 3 Action - 6 - 2 - - IN3ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN3 to OUT - 0x3 - - - - - IN4ACT - Tamper Input 4 Action - 8 - 2 - - IN4ACTSelect - - OFF - Off (Disabled) - 0x0 - - - WAKE - Wake without timestamp - 0x1 - - - CAPTURE - Capture timestamp - 0x2 - - - ACTL - Compare IN4 to OUT - 0x3 - - - - - TAMLVL0 - Tamper Level Select 0 - 16 - 1 - - - TAMLVL1 - Tamper Level Select 1 - 17 - 1 - - - TAMLVL2 - Tamper Level Select 2 - 18 - 1 - - - TAMLVL3 - Tamper Level Select 3 - 19 - 1 - - - TAMLVL4 - Tamper Level Select 4 - 20 - 1 - - - DEBNC0 - Debouncer Enable 0 - 24 - 1 - - - DEBNC1 - Debouncer Enable 1 - 25 - 1 - - - DEBNC2 - Debouncer Enable 2 - 26 - 1 - - - DEBNC3 - Debouncer Enable 3 - 27 - 1 - - - DEBNC4 - Debouncer Enable 4 - 28 - 1 - - - - - TIMESTAMP - MODE2 Timestamp - 0x64 - 32 - read-only - 0x00000000 - - - SECOND - Second Timestamp Value - 0 - 6 - - - MINUTE - Minute Timestamp Value - 6 - 6 - - - HOUR - Hour Timestamp Value - 12 - 5 - - HOURSelect - - AM - AM when CLKREP in 12-hour - 0x00 - - - PM - PM when CLKREP in 12-hour - 0x10 - - - - - DAY - Day Timestamp Value - 17 - 5 - - - MONTH - Month Timestamp Value - 22 - 4 - - - YEAR - Year Timestamp Value - 26 - 6 - - - - - TAMPID - Tamper ID - 0x68 - 32 - 0x00000000 - - - TAMPID0 - Tamper Input 0 Detected - 0 - 1 - - - TAMPID1 - Tamper Input 1 Detected - 1 - 1 - - - TAMPID2 - Tamper Input 2 Detected - 2 - 1 - - - TAMPID3 - Tamper Input 3 Detected - 3 - 1 - - - TAMPID4 - Tamper Input 4 Detected - 4 - 1 - - - TAMPEVT - Tamper Event Detected - 31 - 1 - - - - - 8 - 4 - BKUP[%s] - Backup - 0x80 - 32 - 0x00000000 - - - BKUP - Backup - 0 - 32 - - - - - - - - SDHC0 - U20111.8.3 - SD/MMC Host Controller - SDHC - SDHC_ - 0x45000000 - - 0 - 0x235 - registers - - - SDHC0 - 135 - - - - SSAR - SDMA System Address / Argument 2 - 0x0 - 32 - 0x00000000 - - - ADDR - SDMA System Address - 0 - 32 - - - - - SSAR_CMD23_MODE - SDMA System Address / Argument 2 - SSAR - 0x0 - 32 - 0x00000000 - - - ARG2 - Argument 2 - 0 - 32 - - - - - BSR - Block Size - 0x4 - 16 - 0x0000 - - - BLOCKSIZE - Transfer Block Size - 0 - 10 - - - BOUNDARY - SDMA Buffer Boundary - 12 - 3 - - BOUNDARYSelect - - 4K - 4k bytes - 0 - - - 8K - 8k bytes - 1 - - - 16K - 16k bytes - 2 - - - 32K - 32k bytes - 3 - - - 64K - 64k bytes - 4 - - - 128K - 128k bytes - 5 - - - 256K - 256k bytes - 6 - - - 512K - 512k bytes - 7 - - - - - - - BCR - Block Count - 0x6 - 16 - 0x0000 - - - BCNT - Blocks Count for Current Transfer - 0 - 16 - - - - - ARG1R - Argument 1 - 0x8 - 32 - 0x00000000 - - - ARG - Argument 1 - 0 - 32 - - - - - TMR - Transfer Mode - 0xC - 16 - 0x0000 - - - DMAEN - DMA Enable - 0 - 1 - - DMAENSelect - - DISABLE - No data transfer or Non DMA data transfer - 0 - - - ENABLE - DMA data transfer - 1 - - - - - BCEN - Block Count Enable - 1 - 1 - - BCENSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - ACMDEN - Auto Command Enable - 2 - 2 - - ACMDENSelect - - DISABLED - Auto Command Disabled - 0 - - - CMD12 - Auto CMD12 Enable - 1 - - - CMD23 - Auto CMD23 Enable - 2 - - - - - DTDSEL - Data Transfer Direction Selection - 4 - 1 - - DTDSELSelect - - WRITE - Write (Host to Card) - 0 - - - READ - Read (Card to Host) - 1 - - - - - MSBSEL - Multi/Single Block Selection - 5 - 1 - - MSBSELSelect - - SINGLE - Single Block - 0 - - - MULTIPLE - Multiple Block - 1 - - - - - - - CR - Command - 0xE - 16 - 0x0000 - - - RESPTYP - Response Type - 0 - 2 - - RESPTYPSelect - - NONE - No response - 0 - - - 136_BIT - 136-bit response - 1 - - - 48_BIT - 48-bit response - 2 - - - 48_BIT_BUSY - 48-bit response check busy after response - 3 - - - - - CMDCCEN - Command CRC Check Enable - 3 - 1 - - CMDCCENSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - CMDICEN - Command Index Check Enable - 4 - 1 - - CMDICENSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - DPSEL - Data Present Select - 5 - 1 - - DPSELSelect - - NO_DATA - No Data Present - 0 - - - DATA - Data Present - 1 - - - - - CMDTYP - Command Type - 6 - 2 - - CMDTYPSelect - - NORMAL - Other commands - 0 - - - SUSPEND - CMD52 for writing Bus Suspend in CCCR - 1 - - - RESUME - CMD52 for writing Function Select in CCCR - 2 - - - ABORT - CMD12, CMD52 for writing I/O Abort in CCCR - 3 - - - - - CMDIDX - Command Index - 8 - 6 - - - - - 4 - 4 - RR[%s] - Response - 0x10 - 32 - read-only - 0x00000000 - - - CMDRESP - Command Response - 0 - 32 - - - - - BDPR - Buffer Data Port - 0x20 - 32 - 0x00000000 - - - BUFDATA - Buffer Data - 0 - 32 - - - - - PSR - Present State - 0x24 - 32 - read-only - 0x00F80000 - - - CMDINHC - Command Inhibit (CMD) - 0 - 1 - - CMDINHCSelect - - CAN - Can issue command using only CMD line - 0 - - - CANNOT - Cannot issue command - 1 - - - - - CMDINHD - Command Inhibit (DAT) - 1 - 1 - - CMDINHDSelect - - CAN - Can issue command which uses the DAT line - 0 - - - CANNOT - Cannot issue command which uses the DAT line - 1 - - - - - DLACT - DAT Line Active - 2 - 1 - - DLACTSelect - - INACTIVE - DAT Line Inactive - 0 - - - ACTIVE - DAT Line Active - 1 - - - - - RTREQ - Re-Tuning Request - 3 - 1 - - RTREQSelect - - OK - Fixed or well-tuned sampling clock - 0 - - - REQUIRED - Sampling clock needs re-tuning - 1 - - - - - WTACT - Write Transfer Active - 8 - 1 - - WTACTSelect - - NO - No valid data - 0 - - - YES - Transferring data - 1 - - - - - RTACT - Read Transfer Active - 9 - 1 - - RTACTSelect - - NO - No valid data - 0 - - - YES - Transferring data - 1 - - - - - BUFWREN - Buffer Write Enable - 10 - 1 - - BUFWRENSelect - - DISABLE - Write disable - 0 - - - ENABLE - Write enable - 1 - - - - - BUFRDEN - Buffer Read Enable - 11 - 1 - - BUFRDENSelect - - DISABLE - Read disable - 0 - - - ENABLE - Read enable - 1 - - - - - CARDINS - Card Inserted - 16 - 1 - - CARDINSSelect - - NO - Reset or Debouncing or No Card - 0 - - - YES - Card inserted - 1 - - - - - CARDSS - Card State Stable - 17 - 1 - - CARDSSSelect - - NO - Reset or Debouncing - 0 - - - YES - No Card or Insered - 1 - - - - - CARDDPL - Card Detect Pin Level - 18 - 1 - - CARDDPLSelect - - NO - No card present (SDCD#=1) - 0 - - - YES - Card present (SDCD#=0) - 1 - - - - - WRPPL - Write Protect Pin Level - 19 - 1 - - WRPPLSelect - - PROTECTED - Write protected (SDWP#=0) - 0 - - - ENABLED - Write enabled (SDWP#=1) - 1 - - - - - DATLL - DAT[3:0] Line Level - 20 - 4 - - - CMDLL - CMD Line Level - 24 - 1 - - - - - HC1R - Host Control 1 - 0x28 - 8 - 0xE00 - - - LEDCTRL - LED Control - 0 - 1 - - LEDCTRLSelect - - OFF - LED off - 0 - - - ON - LED on - 1 - - - - - DW - Data Width - 1 - 1 - - DWSelect - - 1BIT - 1-bit mode - 0 - - - 4BIT - 4-bit mode - 1 - - - - - HSEN - High Speed Enable - 2 - 1 - - HSENSelect - - NORMAL - Normal Speed mode - 0 - - - HIGH - High Speed mode - 1 - - - - - DMASEL - DMA Select - 3 - 2 - - DMASELSelect - - SDMA - SDMA is selected - 0 - - - 32BIT - 32-bit Address ADMA2 is selected - 2 - - - - - CARDDTL - Card Detect Test Level - 6 - 1 - - CARDDTLSelect - - NO - No Card - 0 - - - YES - Card Inserted - 1 - - - - - CARDDSEL - Card Detect Signal Selection - 7 - 1 - - CARDDSELSelect - - NORMAL - SDCD# is selected (for normal use) - 0 - - - TEST - The Card Select Test Level is selected (for test purpose) - 1 - - - - - - - HC1R_EMMC_MODE - Host Control 1 - HC1R - 0x28 - 8 - 0xE00 - - - DW - Data Width - 1 - 1 - - DWSelect - - 1BIT - 1-bit mode - 0 - - - 4BIT - 4-bit mode - 1 - - - - - HSEN - High Speed Enable - 2 - 1 - - HSENSelect - - NORMAL - Normal Speed mode - 0 - - - HIGH - High Speed mode - 1 - - - - - DMASEL - DMA Select - 3 - 2 - - DMASELSelect - - SDMA - SDMA is selected - 0 - - - 32BIT - 32-bit Address ADMA2 is selected - 2 - - - - - - - PCR - Power Control - 0x29 - 8 - 0x0E - - - SDBPWR - SD Bus Power - 0 - 1 - - SDBPWRSelect - - OFF - Power off - 0 - - - ON - Power on - 1 - - - - - SDBVSEL - SD Bus Voltage Select - 1 - 3 - - SDBVSELSelect - - 1V8 - 1.8V (Typ.) - 5 - - - 3V0 - 3.0V (Typ.) - 6 - - - 3V3 - 3.3V (Typ.) - 7 - - - - - - - BGCR - Block Gap Control - 0x2A - 8 - 0x00 - - - STPBGR - Stop at Block Gap Request - 0 - 1 - - STPBGRSelect - - TRANSFER - Transfer - 0 - - - STOP - Stop - 1 - - - - - CONTR - Continue Request - 1 - 1 - - CONTRSelect - - GO_ON - Not affected - 0 - - - RESTART - Restart - 1 - - - - - RWCTRL - Read Wait Control - 2 - 1 - - RWCTRLSelect - - DISABLE - Disable Read Wait Control - 0 - - - ENABLE - Enable Read Wait Control - 1 - - - - - INTBG - Interrupt at Block Gap - 3 - 1 - - INTBGSelect - - DISABLED - Disabled - 0 - - - ENABLED - Enabled - 1 - - - - - - - BGCR_EMMC_MODE - Block Gap Control - BGCR - 0x2A - 8 - 0x00 - - - STPBGR - Stop at Block Gap Request - 0 - 1 - - STPBGRSelect - - TRANSFER - Transfer - 0 - - - STOP - Stop - 1 - - - - - CONTR - Continue Request - 1 - 1 - - CONTRSelect - - GO_ON - Not affected - 0 - - - RESTART - Restart - 1 - - - - - - - WCR - Wakeup Control - 0x2B - 8 - 0x00 - - - WKENCINT - Wakeup Event Enable on Card Interrupt - 0 - 1 - - WKENCINTSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - WKENCINS - Wakeup Event Enable on Card Insertion - 1 - 1 - - WKENCINSSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - WKENCREM - Wakeup Event Enable on Card Removal - 2 - 1 - - WKENCREMSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - - - CCR - Clock Control - 0x2C - 16 - 0x0000 - - - INTCLKEN - Internal Clock Enable - 0 - 1 - - INTCLKENSelect - - OFF - Stop - 0 - - - ON - Oscillate - 1 - - - - - INTCLKS - Internal Clock Stable - 1 - 1 - - INTCLKSSelect - - NOT_READY - Not Ready - 0 - - - READY - Ready - 1 - - - - - SDCLKEN - SD Clock Enable - 2 - 1 - - SDCLKENSelect - - DISABLE - Disable - 0 - - - ENABLE - Enable - 1 - - - - - CLKGSEL - Clock Generator Select - 5 - 1 - - CLKGSELSelect - - DIV - Divided Clock Mode - 0 - - - PROG - Programmable Clock Mode - 1 - - - - - USDCLKFSEL - Upper Bits of SDCLK Frequency Select - 6 - 2 - - - SDCLKFSEL - SDCLK Frequency Select - 8 - 8 - - - - - TCR - Timeout Control - 0x2E - 8 - 0x00 - - - DTCVAL - Data Timeout Counter Value - 0 - 4 - - - - - SRR - Software Reset - 0x2F - 8 - 0x00 - - - SWRSTALL - Software Reset For All - 0 - 1 - - SWRSTALLSelect - - WORK - Work - 0 - - - RESET - Reset - 1 - - - - - SWRSTCMD - Software Reset For CMD Line - 1 - 1 - - SWRSTCMDSelect - - WORK - Work - 0 - - - RESET - Reset - 1 - - - - - SWRSTDAT - Software Reset For DAT Line - 2 - 1 - - SWRSTDATSelect - - WORK - Work - 0 - - - RESET - Reset - 1 - - - - - - - NISTR - Normal Interrupt Status - 0x30 - 16 - 0x0000 - - - CMDC - Command Complete - 0 - 1 - - CMDCSelect - - NO - No command complete - 0 - - - YES - Command complete - 1 - - - - - TRFC - Transfer Complete - 1 - 1 - - TRFCSelect - - NO - Not complete - 0 - - - YES - Command execution is completed - 1 - - - - - BLKGE - Block Gap Event - 2 - 1 - - BLKGESelect - - NO - No Block Gap Event - 0 - - - STOP - Transaction stopped at block gap - 1 - - - - - DMAINT - DMA Interrupt - 3 - 1 - - DMAINTSelect - - NO - No DMA Interrupt - 0 - - - YES - DMA Interrupt is generated - 1 - - - - - BWRRDY - Buffer Write Ready - 4 - 1 - - BWRRDYSelect - - NO - Not ready to write buffer - 0 - - - YES - Ready to write buffer - 1 - - - - - BRDRDY - Buffer Read Ready - 5 - 1 - - BRDRDYSelect - - NO - Not ready to read buffer - 0 - - - YES - Ready to read buffer - 1 - - - - - CINS - Card Insertion - 6 - 1 - - CINSSelect - - NO - Card state stable or Debouncing - 0 - - - YES - Card inserted - 1 - - - - - CREM - Card Removal - 7 - 1 - - CREMSelect - - NO - Card state stable or Debouncing - 0 - - - YES - Card Removed - 1 - - - - - CINT - Card Interrupt - 8 - 1 - - CINTSelect - - NO - No Card Interrupt - 0 - - - YES - Generate Card Interrupt - 1 - - - - - ERRINT - Error Interrupt - 15 - 1 - - ERRINTSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - - - NISTR_EMMC_MODE - Normal Interrupt Status - NISTR - 0x30 - 16 - 0x0000 - - - CMDC - Command Complete - 0 - 1 - - CMDCSelect - - NO - No command complete - 0 - - - YES - Command complete - 1 - - - - - TRFC - Transfer Complete - 1 - 1 - - TRFCSelect - - NO - Not complete - 0 - - - YES - Command execution is completed - 1 - - - - - BLKGE - Block Gap Event - 2 - 1 - - BLKGESelect - - NO - No Block Gap Event - 0 - - - STOP - Transaction stopped at block gap - 1 - - - - - DMAINT - DMA Interrupt - 3 - 1 - - DMAINTSelect - - NO - No DMA Interrupt - 0 - - - YES - DMA Interrupt is generated - 1 - - - - - BWRRDY - Buffer Write Ready - 4 - 1 - - BWRRDYSelect - - NO - Not ready to write buffer - 0 - - - YES - Ready to write buffer - 1 - - - - - BRDRDY - Buffer Read Ready - 5 - 1 - - BRDRDYSelect - - NO - Not ready to read buffer - 0 - - - YES - Ready to read buffer - 1 - - - - - BOOTAR - Boot Acknowledge Received - 14 - 1 - - - ERRINT - Error Interrupt - 15 - 1 - - ERRINTSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - - - EISTR - Error Interrupt Status - 0x32 - 16 - 0x0000 - - - CMDTEO - Command Timeout Error - 0 - 1 - - CMDTEOSelect - - NO - No Error - 0 - - - YES - Timeout - 1 - - - - - CMDCRC - Command CRC Error - 1 - 1 - - CMDCRCSelect - - NO - No Error - 0 - - - YES - CRC Error Generated - 1 - - - - - CMDEND - Command End Bit Error - 2 - 1 - - CMDENDSelect - - NO - No error - 0 - - - YES - End Bit Error Generated - 1 - - - - - CMDIDX - Command Index Error - 3 - 1 - - CMDIDXSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - DATTEO - Data Timeout Error - 4 - 1 - - DATTEOSelect - - NO - No Error - 0 - - - YES - Timeout - 1 - - - - - DATCRC - Data CRC Error - 5 - 1 - - DATCRCSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - DATEND - Data End Bit Error - 6 - 1 - - DATENDSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - CURLIM - Current Limit Error - 7 - 1 - - CURLIMSelect - - NO - No Error - 0 - - - YES - Power Fail - 1 - - - - - ACMD - Auto CMD Error - 8 - 1 - - ACMDSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - ADMA - ADMA Error - 9 - 1 - - ADMASelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - - - EISTR_EMMC_MODE - Error Interrupt Status - EISTR - 0x32 - 16 - 0x0000 - - - CMDTEO - Command Timeout Error - 0 - 1 - - CMDTEOSelect - - NO - No Error - 0 - - - YES - Timeout - 1 - - - - - CMDCRC - Command CRC Error - 1 - 1 - - CMDCRCSelect - - NO - No Error - 0 - - - YES - CRC Error Generated - 1 - - - - - CMDEND - Command End Bit Error - 2 - 1 - - CMDENDSelect - - NO - No error - 0 - - - YES - End Bit Error Generated - 1 - - - - - CMDIDX - Command Index Error - 3 - 1 - - CMDIDXSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - DATTEO - Data Timeout Error - 4 - 1 - - DATTEOSelect - - NO - No Error - 0 - - - YES - Timeout - 1 - - - - - DATCRC - Data CRC Error - 5 - 1 - - DATCRCSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - DATEND - Data End Bit Error - 6 - 1 - - DATENDSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - CURLIM - Current Limit Error - 7 - 1 - - CURLIMSelect - - NO - No Error - 0 - - - YES - Power Fail - 1 - - - - - ACMD - Auto CMD Error - 8 - 1 - - ACMDSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - ADMA - ADMA Error - 9 - 1 - - ADMASelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - BOOTAE - Boot Acknowledge Error - 12 - 1 - - BOOTAESelect - - 0 - FIFO contains at least one byte - 0 - - - 1 - FIFO is empty - 1 - - - - - - - NISTER - Normal Interrupt Status Enable - 0x34 - 16 - 0x0000 - - - CMDC - Command Complete Status Enable - 0 - 1 - - CMDCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - TRFC - Transfer Complete Status Enable - 1 - 1 - - TRFCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BLKGE - Block Gap Event Status Enable - 2 - 1 - - BLKGESelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DMAINT - DMA Interrupt Status Enable - 3 - 1 - - DMAINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BWRRDY - Buffer Write Ready Status Enable - 4 - 1 - - BWRRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BRDRDY - Buffer Read Ready Status Enable - 5 - 1 - - BRDRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CINS - Card Insertion Status Enable - 6 - 1 - - CINSSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CREM - Card Removal Status Enable - 7 - 1 - - CREMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CINT - Card Interrupt Status Enable - 8 - 1 - - CINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - - - NISTER_EMMC_MODE - Normal Interrupt Status Enable - NISTER - 0x34 - 16 - 0x0000 - - - CMDC - Command Complete Status Enable - 0 - 1 - - CMDCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - TRFC - Transfer Complete Status Enable - 1 - 1 - - TRFCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BLKGE - Block Gap Event Status Enable - 2 - 1 - - BLKGESelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DMAINT - DMA Interrupt Status Enable - 3 - 1 - - DMAINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BWRRDY - Buffer Write Ready Status Enable - 4 - 1 - - BWRRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BRDRDY - Buffer Read Ready Status Enable - 5 - 1 - - BRDRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BOOTAR - Boot Acknowledge Received Status Enable - 14 - 1 - - - - - EISTER - Error Interrupt Status Enable - 0x36 - 16 - 0x0000 - - - CMDTEO - Command Timeout Error Status Enable - 0 - 1 - - CMDTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDCRC - Command CRC Error Status Enable - 1 - 1 - - CMDCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDEND - Command End Bit Error Status Enable - 2 - 1 - - CMDENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDIDX - Command Index Error Status Enable - 3 - 1 - - CMDIDXSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATTEO - Data Timeout Error Status Enable - 4 - 1 - - DATTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATCRC - Data CRC Error Status Enable - 5 - 1 - - DATCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATEND - Data End Bit Error Status Enable - 6 - 1 - - DATENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CURLIM - Current Limit Error Status Enable - 7 - 1 - - CURLIMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ACMD - Auto CMD Error Status Enable - 8 - 1 - - ACMDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ADMA - ADMA Error Status Enable - 9 - 1 - - ADMASelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - - - EISTER_EMMC_MODE - Error Interrupt Status Enable - EISTER - 0x36 - 16 - 0x0000 - - - CMDTEO - Command Timeout Error Status Enable - 0 - 1 - - CMDTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDCRC - Command CRC Error Status Enable - 1 - 1 - - CMDCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDEND - Command End Bit Error Status Enable - 2 - 1 - - CMDENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDIDX - Command Index Error Status Enable - 3 - 1 - - CMDIDXSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATTEO - Data Timeout Error Status Enable - 4 - 1 - - DATTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATCRC - Data CRC Error Status Enable - 5 - 1 - - DATCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATEND - Data End Bit Error Status Enable - 6 - 1 - - DATENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CURLIM - Current Limit Error Status Enable - 7 - 1 - - CURLIMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ACMD - Auto CMD Error Status Enable - 8 - 1 - - ACMDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ADMA - ADMA Error Status Enable - 9 - 1 - - ADMASelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BOOTAE - Boot Acknowledge Error Status Enable - 12 - 1 - - - - - NISIER - Normal Interrupt Signal Enable - 0x38 - 16 - 0x0000 - - - CMDC - Command Complete Signal Enable - 0 - 1 - - CMDCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - TRFC - Transfer Complete Signal Enable - 1 - 1 - - TRFCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BLKGE - Block Gap Event Signal Enable - 2 - 1 - - BLKGESelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DMAINT - DMA Interrupt Signal Enable - 3 - 1 - - DMAINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BWRRDY - Buffer Write Ready Signal Enable - 4 - 1 - - BWRRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BRDRDY - Buffer Read Ready Signal Enable - 5 - 1 - - BRDRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CINS - Card Insertion Signal Enable - 6 - 1 - - CINSSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CREM - Card Removal Signal Enable - 7 - 1 - - CREMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CINT - Card Interrupt Signal Enable - 8 - 1 - - CINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - - - NISIER_EMMC_MODE - Normal Interrupt Signal Enable - NISIER - 0x38 - 16 - 0x0000 - - - CMDC - Command Complete Signal Enable - 0 - 1 - - CMDCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - TRFC - Transfer Complete Signal Enable - 1 - 1 - - TRFCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BLKGE - Block Gap Event Signal Enable - 2 - 1 - - BLKGESelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DMAINT - DMA Interrupt Signal Enable - 3 - 1 - - DMAINTSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BWRRDY - Buffer Write Ready Signal Enable - 4 - 1 - - BWRRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BRDRDY - Buffer Read Ready Signal Enable - 5 - 1 - - BRDRDYSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BOOTAR - Boot Acknowledge Received Signal Enable - 14 - 1 - - - - - EISIER - Error Interrupt Signal Enable - 0x3A - 16 - 0x0000 - - - CMDTEO - Command Timeout Error Signal Enable - 0 - 1 - - CMDTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDCRC - Command CRC Error Signal Enable - 1 - 1 - - CMDCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDEND - Command End Bit Error Signal Enable - 2 - 1 - - CMDENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDIDX - Command Index Error Signal Enable - 3 - 1 - - CMDIDXSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATTEO - Data Timeout Error Signal Enable - 4 - 1 - - DATTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATCRC - Data CRC Error Signal Enable - 5 - 1 - - DATCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATEND - Data End Bit Error Signal Enable - 6 - 1 - - DATENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CURLIM - Current Limit Error Signal Enable - 7 - 1 - - CURLIMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ACMD - Auto CMD Error Signal Enable - 8 - 1 - - ACMDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ADMA - ADMA Error Signal Enable - 9 - 1 - - ADMASelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - - - EISIER_EMMC_MODE - Error Interrupt Signal Enable - EISIER - 0x3A - 16 - 0x0000 - - - CMDTEO - Command Timeout Error Signal Enable - 0 - 1 - - CMDTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDCRC - Command CRC Error Signal Enable - 1 - 1 - - CMDCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDEND - Command End Bit Error Signal Enable - 2 - 1 - - CMDENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CMDIDX - Command Index Error Signal Enable - 3 - 1 - - CMDIDXSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATTEO - Data Timeout Error Signal Enable - 4 - 1 - - DATTEOSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATCRC - Data CRC Error Signal Enable - 5 - 1 - - DATCRCSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - DATEND - Data End Bit Error Signal Enable - 6 - 1 - - DATENDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - CURLIM - Current Limit Error Signal Enable - 7 - 1 - - CURLIMSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ACMD - Auto CMD Error Signal Enable - 8 - 1 - - ACMDSelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - ADMA - ADMA Error Signal Enable - 9 - 1 - - ADMASelect - - MASKED - Masked - 0 - - - ENABLED - Enabled - 1 - - - - - BOOTAE - Boot Acknowledge Error Signal Enable - 12 - 1 - - - - - ACESR - Auto CMD Error Status - 0x3C - 16 - read-only - 0x0000 - - - ACMD12NE - Auto CMD12 Not Executed - 0 - 1 - - ACMD12NESelect - - EXEC - Executed - 0 - - - NOT_EXEC - Not executed - 1 - - - - - ACMDTEO - Auto CMD Timeout Error - 1 - 1 - - ACMDTEOSelect - - NO - No error - 0 - - - YES - Timeout - 1 - - - - - ACMDCRC - Auto CMD CRC Error - 2 - 1 - - ACMDCRCSelect - - NO - No error - 0 - - - YES - CRC Error Generated - 1 - - - - - ACMDEND - Auto CMD End Bit Error - 3 - 1 - - ACMDENDSelect - - NO - No error - 0 - - - YES - End Bit Error Generated - 1 - - - - - ACMDIDX - Auto CMD Index Error - 4 - 1 - - ACMDIDXSelect - - NO - No error - 0 - - - YES - Error - 1 - - - - - CMDNI - Command not Issued By Auto CMD12 Error - 7 - 1 - - CMDNISelect - - OK - No error - 0 - - - NOT_ISSUED - Not Issued - 1 - - - - - - - HC2R - Host Control 2 - 0x3E - 16 - 0x0000 - - - UHSMS - UHS Mode Select - 0 - 3 - - UHSMSSelect - - SDR12 - SDR12 - 0 - - - SDR25 - SDR25 - 1 - - - SDR50 - SDR50 - 2 - - - SDR104 - SDR104 - 3 - - - DDR50 - DDR50 - 4 - - - - - VS18EN - 1.8V Signaling Enable - 3 - 1 - - VS18ENSelect - - S33V - 3.3V Signaling - 0 - - - S18V - 1.8V Signaling - 1 - - - - - DRVSEL - Driver Strength Select - 4 - 2 - - DRVSELSelect - - B - Driver Type B is Selected (Default) - 0 - - - A - Driver Type A is Selected - 1 - - - C - Driver Type C is Selected - 2 - - - D - Driver Type D is Selected - 3 - - - - - EXTUN - Execute Tuning - 6 - 1 - - EXTUNSelect - - NO - Not Tuned or Tuning Completed - 0 - - - REQUESTED - Execute Tuning - 1 - - - - - SLCKSEL - Sampling Clock Select - 7 - 1 - - SLCKSELSelect - - FIXED - Fixed clock is used to sample data - 0 - - - TUNED - Tuned clock is used to sample data - 1 - - - - - ASINTEN - Asynchronous Interrupt Enable - 14 - 1 - - ASINTENSelect - - DISABLED - Disabled - 0 - - - ENABLED - Enabled - 1 - - - - - PVALEN - Preset Value Enable - 15 - 1 - - PVALENSelect - - HOST - SDCLK and Driver Strength are controlled by Host Controller - 0 - - - AUTO - Automatic Selection by Preset Value is Enabled - 1 - - - - - - - HC2R_EMMC_MODE - Host Control 2 - HC2R - 0x3E - 16 - 0x0000 - - - HS200EN - HS200 Mode Enable - 0 - 4 - - HS200ENSelect - - SDR12 - SDR12 - 0 - - - SDR25 - SDR25 - 1 - - - SDR50 - SDR50 - 2 - - - SDR104 - SDR104 - 3 - - - DDR50 - DDR50 - 4 - - - - - DRVSEL - Driver Strength Select - 4 - 2 - - DRVSELSelect - - B - Driver Type B is Selected (Default) - 0 - - - A - Driver Type A is Selected - 1 - - - C - Driver Type C is Selected - 2 - - - D - Driver Type D is Selected - 3 - - - - - EXTUN - Execute Tuning - 6 - 1 - - EXTUNSelect - - NO - Not Tuned or Tuning Completed - 0 - - - REQUESTED - Execute Tuning - 1 - - - - - SLCKSEL - Sampling Clock Select - 7 - 1 - - SLCKSELSelect - - FIXED - Fixed clock is used to sample data - 0 - - - TUNED - Tuned clock is used to sample data - 1 - - - - - PVALEN - Preset Value Enable - 15 - 1 - - PVALENSelect - - HOST - SDCLK and Driver Strength are controlled by Host Controller - 0 - - - AUTO - Automatic Selection by Preset Value is Enabled - 1 - - - - - - - CA0R - Capabilities 0 - 0x40 - 32 - read-only - 0x27E80080 - - - TEOCLKF - Timeout Clock Frequency - 0 - 6 - - TEOCLKFSelect - - OTHER - Get information via another method - 0 - - - - - TEOCLKU - Timeout Clock Unit - 7 - 1 - - TEOCLKUSelect - - KHZ - KHz - 0 - - - MHZ - MHz - 1 - - - - - BASECLKF - Base Clock Frequency - 8 - 8 - - BASECLKFSelect - - OTHER - Get information via another method - 0 - - - - - MAXBLKL - Max Block Length - 16 - 2 - - MAXBLKLSelect - - 512 - 512 bytes - 0 - - - 1024 - 1024 bytes - 1 - - - 2048 - 2048 bytes - 2 - - - - - ED8SUP - 8-bit Support for Embedded Device - 18 - 1 - - ED8SUPSelect - - NO - 8-bit Bus Width not Supported - 0 - - - YES - 8-bit Bus Width Supported - 1 - - - - - ADMA2SUP - ADMA2 Support - 19 - 1 - - ADMA2SUPSelect - - NO - ADMA2 not Supported - 0 - - - YES - ADMA2 Supported - 1 - - - - - HSSUP - High Speed Support - 21 - 1 - - HSSUPSelect - - NO - High Speed not Supported - 0 - - - YES - High Speed Supported - 1 - - - - - SDMASUP - SDMA Support - 22 - 1 - - SDMASUPSelect - - NO - SDMA not Supported - 0 - - - YES - SDMA Supported - 1 - - - - - SRSUP - Suspend/Resume Support - 23 - 1 - - SRSUPSelect - - NO - Suspend/Resume not Supported - 0 - - - YES - Suspend/Resume Supported - 1 - - - - - V33VSUP - Voltage Support 3.3V - 24 - 1 - - V33VSUPSelect - - NO - 3.3V Not Supported - 0 - - - YES - 3.3V Supported - 1 - - - - - V30VSUP - Voltage Support 3.0V - 25 - 1 - - V30VSUPSelect - - NO - 3.0V Not Supported - 0 - - - YES - 3.0V Supported - 1 - - - - - V18VSUP - Voltage Support 1.8V - 26 - 1 - - V18VSUPSelect - - NO - 1.8V Not Supported - 0 - - - YES - 1.8V Supported - 1 - - - - - SB64SUP - 64-Bit System Bus Support - 28 - 1 - - SB64SUPSelect - - NO - 32-bit Address Descriptors and System Bus - 0 - - - YES - 64-bit Address Descriptors and System Bus - 1 - - - - - ASINTSUP - Asynchronous Interrupt Support - 29 - 1 - - ASINTSUPSelect - - NO - Asynchronous Interrupt not Supported - 0 - - - YES - Asynchronous Interrupt supported - 1 - - - - - SLTYPE - Slot Type - 30 - 2 - - SLTYPESelect - - REMOVABLE - Removable Card Slot - 0 - - - EMBEDDED - Embedded Slot for One Device - 1 - - - - - - - CA1R - Capabilities 1 - 0x44 - 32 - read-only - 0x00000070 - - - SDR50SUP - SDR50 Support - 0 - 1 - - SDR50SUPSelect - - NO - SDR50 is Not Supported - 0 - - - YES - SDR50 is Supported - 1 - - - - - SDR104SUP - SDR104 Support - 1 - 1 - - SDR104SUPSelect - - NO - SDR104 is Not Supported - 0 - - - YES - SDR104 is Supported - 1 - - - - - DDR50SUP - DDR50 Support - 2 - 1 - - DDR50SUPSelect - - NO - DDR50 is Not Supported - 0 - - - YES - DDR50 is Supported - 1 - - - - - DRVASUP - Driver Type A Support - 4 - 1 - - DRVASUPSelect - - NO - Driver Type A is Not Supported - 0 - - - YES - Driver Type A is Supported - 1 - - - - - DRVCSUP - Driver Type C Support - 5 - 1 - - DRVCSUPSelect - - NO - Driver Type C is Not Supported - 0 - - - YES - Driver Type C is Supported - 1 - - - - - DRVDSUP - Driver Type D Support - 6 - 1 - - DRVDSUPSelect - - NO - Driver Type D is Not Supported - 0 - - - YES - Driver Type D is Supported - 1 - - - - - TCNTRT - Timer Count for Re-Tuning - 8 - 4 - - TCNTRTSelect - - DISABLED - Re-Tuning Timer disabled - 0 - - - 1S - 1 second - 1 - - - 2S - 2 seconds - 2 - - - 4S - 4 seconds - 3 - - - 8S - 8 seconds - 4 - - - 16S - 16 seconds - 5 - - - 32S - 32 seconds - 6 - - - 64S - 64 seconds - 7 - - - 128S - 128 seconds - 8 - - - 256S - 256 seconds - 9 - - - 512S - 512 seconds - 10 - - - 1024S - 1024 seconds - 11 - - - OTHER - Get information from other source - 15 - - - - - TSDR50 - Use Tuning for SDR50 - 13 - 1 - - TSDR50Select - - NO - SDR50 does not require tuning - 0 - - - YES - SDR50 requires tuning - 1 - - - - - CLKMULT - Clock Multiplier - 16 - 8 - - CLKMULTSelect - - NO - Clock Multiplier is Not Supported - 0 - - - - - - - MCCAR - Maximum Current Capabilities - 0x48 - 32 - read-only - 0x00000000 - - - MAXCUR33V - Maximum Current for 3.3V - 0 - 8 - - MAXCUR33VSelect - - OTHER - Get information via another method - 0 - - - 4MA - 4mA - 1 - - - 8MA - 8mA - 2 - - - 12MA - 12mA - 3 - - - - - MAXCUR30V - Maximum Current for 3.0V - 8 - 8 - - MAXCUR30VSelect - - OTHER - Get information via another method - 0 - - - 4MA - 4mA - 1 - - - 8MA - 8mA - 2 - - - 12MA - 12mA - 3 - - - - - MAXCUR18V - Maximum Current for 1.8V - 16 - 8 - - MAXCUR18VSelect - - OTHER - Get information via another method - 0 - - - 4MA - 4mA - 1 - - - 8MA - 8mA - 2 - - - 12MA - 12mA - 3 - - - - - - - FERACES - Force Event for Auto CMD Error Status - 0x50 - 16 - write-only - 0x0000 - - - ACMD12NE - Force Event for Auto CMD12 Not Executed - 0 - 1 - - ACMD12NESelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ACMDTEO - Force Event for Auto CMD Timeout Error - 1 - 1 - - ACMDTEOSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ACMDCRC - Force Event for Auto CMD CRC Error - 2 - 1 - - ACMDCRCSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ACMDEND - Force Event for Auto CMD End Bit Error - 3 - 1 - - ACMDENDSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ACMDIDX - Force Event for Auto CMD Index Error - 4 - 1 - - ACMDIDXSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - CMDNI - Force Event for Command Not Issued By Auto CMD12 Error - 7 - 1 - - CMDNISelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - - - FEREIS - Force Event for Error Interrupt Status - 0x52 - 16 - write-only - 0x0000 - - - CMDTEO - Force Event for Command Timeout Error - 0 - 1 - - CMDTEOSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - CMDCRC - Force Event for Command CRC Error - 1 - 1 - - CMDCRCSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - CMDEND - Force Event for Command End Bit Error - 2 - 1 - - CMDENDSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - CMDIDX - Force Event for Command Index Error - 3 - 1 - - CMDIDXSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - DATTEO - Force Event for Data Timeout Error - 4 - 1 - - DATTEOSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - DATCRC - Force Event for Data CRC Error - 5 - 1 - - DATCRCSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - DATEND - Force Event for Data End Bit Error - 6 - 1 - - DATENDSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - CURLIM - Force Event for Current Limit Error - 7 - 1 - - CURLIMSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ACMD - Force Event for Auto CMD Error - 8 - 1 - - ACMDSelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - ADMA - Force Event for ADMA Error - 9 - 1 - - ADMASelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - BOOTAE - Force Event for Boot Acknowledge Error - 12 - 1 - - BOOTAESelect - - NO - No Interrupt - 0 - - - YES - Interrupt is generated - 1 - - - - - - - AESR - ADMA Error Status - 0x54 - 8 - read-only - 0x00 - - - ERRST - ADMA Error State - 0 - 2 - - ERRSTSelect - - STOP - ST_STOP (Stop DMA) - 0 - - - FDS - ST_FDS (Fetch Descriptor) - 1 - - - TFR - ST_TFR (Transfer Data) - 3 - - - - - LMIS - ADMA Length Mismatch Error - 2 - 1 - - LMISSelect - - NO - No Error - 0 - - - YES - Error - 1 - - - - - - - 1 - 4 - ASAR[%s] - ADMA System Address n - 0x58 - 32 - 0x00000000 - - - ADMASA - ADMA System Address - 0 - 32 - - - - - 8 - 2 - PVR[%s] - Preset Value n - 0x60 - 16 - 0x0000 - - - SDCLKFSEL - SDCLK Frequency Select Value for Initialization - 0 - 10 - - - CLKGSEL - Clock Generator Select Value for Initialization - 10 - 1 - - CLKGSELSelect - - DIV - Host Controller Ver2.00 Compatible Clock Generator (Divider) - 0 - - - PROG - Programmable Clock Generator - 1 - - - - - DRVSEL - Driver Strength Select Value for Initialization - 14 - 2 - - DRVSELSelect - - B - Driver Type B is Selected - 0 - - - A - Driver Type A is Selected - 1 - - - C - Driver Type C is Selected - 2 - - - D - Driver Type D is Selected - 3 - - - - - - - SISR - Slot Interrupt Status - 0xFC - 16 - read-only - 0x20000 - - - INTSSL - Interrupt Signal for Each Slot - 0 - 1 - - - - - HCVR - Host Controller Version - 0xFE - 16 - read-only - 0x1802 - - - SVER - Spec Version - 0 - 8 - - - VVER - Vendor Version - 8 - 8 - - - - - MC1R - MMC Control 1 - 0x204 - 8 - 0x00 - - - CMDTYP - e.MMC Command Type - 0 - 2 - - CMDTYPSelect - - NORMAL - Not a MMC specific command - 0 - - - WAITIRQ - Wait IRQ Command - 1 - - - STREAM - Stream Command - 2 - - - BOOT - Boot Command - 3 - - - - - DDR - e.MMC HSDDR Mode - 3 - 1 - - - OPD - e.MMC Open Drain Mode - 4 - 1 - - - BOOTA - e.MMC Boot Acknowledge Enable - 5 - 1 - - - RSTN - e.MMC Reset Signal - 6 - 1 - - - FCD - e.MMC Force Card Detect - 7 - 1 - - - - - MC2R - MMC Control 2 - 0x205 - 8 - write-only - 0x00 - - - SRESP - e.MMC Abort Wait IRQ - 0 - 1 - - - ABOOT - e.MMC Abort Boot - 1 - 1 - - - - - ACR - AHB Control - 0x208 - 32 - 0x00000000 - - - BMAX - AHB Maximum Burst - 0 - 2 - - BMAXSelect - - INCR16 - 0 - - - INCR8 - 1 - - - INCR4 - 2 - - - SINGLE - 3 - - - - - - - CC2R - Clock Control 2 - 0x20C - 32 - 0x00000000 - - - FSDCLKD - Force SDCK Disabled - 0 - 1 - - FSDCLKDSelect - - NOEFFECT - No effect - 0 - - - DISABLE - SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled - 1 - - - - - - - CACR - Capabilities Control - 0x230 - 32 - 0x00000000 - - - CAPWREN - Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) - 0 - 1 - - - KEY - Key (0x46) - 8 - 8 - - - - - DBGR - Debug - 0x234 - 8 - 0x00 - - - NIDBG - Non-intrusive debug enable - 0 - 1 - - NIDBGSelect - - IDBG - Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) - 0 - - - NIDBG - Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) - 1 - - - - - - - - - SERCOM0 - U22015.0.0 - Serial Communication Interface - SERCOM - SERCOM_ - 0x40003000 - - 0 - 0x31 - registers - - - SERCOM0_0 - 46 - - - SERCOM0_1 - 47 - - - SERCOM0_2 - 48 - - - SERCOM0_OTHER - 49 - - - - I2CM - I2C Master Mode - SercomI2cm - 0x0 - - CTRLA - I2CM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run in Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - MEXTTOEN - Master SCL Low Extend Timeout - 22 - 1 - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - INACTOUT - Inactive Time-Out - 28 - 2 - - INACTOUTSelect - - DISABLE - Disabled - 0x0 - - - 55US - 5-6 SCL Time-Out(50-60us) - 0x1 - - - 105US - 10-11 SCL Time-Out(100-110us) - 0x2 - - - 205US - 20-21 SCL Time-Out(200-210us) - 0x3 - - - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CM Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - QCEN - Quick Command Enable - 9 - 1 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - CTRLC - I2CM Control C - 0x8 - 32 - 0x00000000 - - - DATA32B - Data 32 Bit - 24 - 1 - - DATA32BSelect - - DATA_TRANS_8BIT - Data transaction from/to DATA register are 8-bit - 0x0 - - - DATA_TRANS_32BIT - Data transaction from/to DATA register are 32-bit - 0x1 - - - - - - - BAUD - I2CM Baud Rate - 0xC - 32 - 0x00000000 - - - BAUD - Baud Rate Value - 0 - 8 - - - BAUDLOW - Baud Rate Value Low - 8 - 8 - - - HSBAUD - High Speed Baud Rate Value - 16 - 8 - - - HSBAUDLOW - High Speed Baud Rate Value Low - 24 - 8 - - - - - INTENCLR - I2CM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - MB - Master On Bus Interrupt Disable - 0 - 1 - - - SB - Slave On Bus Interrupt Disable - 1 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - MB - Master On Bus Interrupt Enable - 0 - 1 - - - SB - Slave On Bus Interrupt Enable - 1 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - MB - Master On Bus Interrupt - 0 - 1 - - - SB - Slave On Bus Interrupt - 1 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CM Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - ARBLOST - Arbitration Lost - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - BUSSTATE - Bus State - 4 - 2 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - MEXTTOUT - Master SCL Low Extend Timeout - 8 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - LENERR - Length Error - 10 - 1 - - - - - SYNCBUSY - I2CM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - SYSOP - System Operation Synchronization Busy - 2 - 1 - - - LENGTH - Length Synchronization Busy - 4 - 1 - - - - - ADDR - I2CM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 11 - - - LENEN - Length Enable - 13 - 1 - - - HS - High Speed Mode - 14 - 1 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - LEN - Length - 16 - 8 - - - - - DATA - I2CM Data - 0x28 - 8 - 0x00 - - - DATA - Data Value - 0 - 8 - - - - - DBGCTRL - I2CM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - I2CS - I2C Slave Mode - I2CM - SercomI2cs - 0x0 - - CTRLA - I2CS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CS Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - GCMD - PMBus Group Command - 9 - 1 - - - AACKEN - Automatic Address Acknowledge - 10 - 1 - - - AMODE - Address Mode - 14 - 2 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - CTRLC - I2CS Control C - 0x8 - 32 - 0x00000000 - - - SDASETUP - SDA Setup Time - 0 - 4 - - - DATA32B - Data 32 Bit - 24 - 1 - - DATA32BSelect - - DATA_TRANS_8BIT - Data transaction from/to DATA register are 8-bit - 0x0 - - - DATA_TRANS_32BIT - Data transaction from/to DATA register are 32-bit - 0x1 - - - - - - - INTENCLR - I2CS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - PREC - Stop Received Interrupt Disable - 0 - 1 - - - AMATCH - Address Match Interrupt Disable - 1 - 1 - - - DRDY - Data Interrupt Disable - 2 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - PREC - Stop Received Interrupt Enable - 0 - 1 - - - AMATCH - Address Match Interrupt Enable - 1 - 1 - - - DRDY - Data Interrupt Enable - 2 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - PREC - Stop Received Interrupt - 0 - 1 - - - AMATCH - Address Match Interrupt - 1 - 1 - - - DRDY - Data Interrupt - 2 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CS Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - COLL - Transmit Collision - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - DIR - Read/Write Direction - 3 - 1 - - - SR - Repeated Start - 4 - 1 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - HS - High Speed - 10 - 1 - - - LENERR - Transaction Length Error - 11 - 1 - - - - - SYNCBUSY - I2CS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - LENGTH - Length Synchronization Busy - 4 - 1 - - - - - LENGTH - I2CS Length - 0x22 - 16 - 0x0000 - - - LEN - Data Length - 0 - 8 - - - LENEN - Data Length Enable - 8 - 1 - - - - - ADDR - I2CS Address - 0x24 - 32 - 0x00000000 - - - GENCEN - General Call Address Enable - 0 - 1 - - - ADDR - Address Value - 1 - 10 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - ADDRMASK - Address Mask - 17 - 10 - - - - - DATA - I2CS Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 32 - - - - - - SPIS - SPI Slave Mode - I2CM - SercomSpis - 0x0 - - CTRLA - SPIS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] is used as data input - 0x0 - - - PAD1 - SERCOM PAD[1] is used as data input - 0x1 - - - PAD2 - SERCOM PAD[2] is used as data input - 0x2 - - - PAD3 - SERCOM PAD[3] is used as data input - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIS Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - CTRLC - SPIS Control C - 0x8 - 32 - 0x00000000 - - - ICSPACE - Inter-Character Spacing - 0 - 6 - - - DATA32B - Data 32 Bit - 24 - 1 - - DATA32BSelect - - DATA_TRANS_8BIT - Transaction from and to DATA register are 8-bit - 0x0 - - - DATA_TRANS_32BIT - Transaction from and to DATA register are 32-bit - 0x1 - - - - - - - BAUD - SPIS Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIS Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - LENERR - Transaction Length Error - 11 - 1 - - - - - SYNCBUSY - SPIS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - LENGTH - LENGTH Synchronization Busy - 4 - 1 - - - - - LENGTH - SPIS Length - 0x22 - 16 - 0x0000 - - - LEN - Data Length - 0 - 8 - - - LENEN - Data Length Enable - 8 - 1 - - - - - ADDR - SPIS Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIS Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 32 - - - - - DBGCTRL - SPIS Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - SPIM - SPI Master Mode - I2CM - SercomSpim - 0x0 - - CTRLA - SPIM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] is used as data input - 0x0 - - - PAD1 - SERCOM PAD[1] is used as data input - 0x1 - - - PAD2 - SERCOM PAD[2] is used as data input - 0x2 - - - PAD3 - SERCOM PAD[3] is used as data input - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIM Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - CTRLC - SPIM Control C - 0x8 - 32 - 0x00000000 - - - ICSPACE - Inter-Character Spacing - 0 - 6 - - - DATA32B - Data 32 Bit - 24 - 1 - - DATA32BSelect - - DATA_TRANS_8BIT - Transaction from and to DATA register are 8-bit - 0x0 - - - DATA_TRANS_32BIT - Transaction from and to DATA register are 32-bit - 0x1 - - - - - - - BAUD - SPIM Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIM Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - LENERR - Transaction Length Error - 11 - 1 - - - - - SYNCBUSY - SPIM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - LENGTH - LENGTH Synchronization Busy - 4 - 1 - - - - - LENGTH - SPIM Length - 0x22 - 16 - 0x0000 - - - LEN - Data Length - 0 - 8 - - - LENEN - Data Length Enable - 8 - 1 - - - - - ADDR - SPIM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIM Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 32 - - - - - DBGCTRL - SPIM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_EXT - USART EXTERNAL CLOCK Mode - I2CM - SercomUsart_ext - 0x0 - - CTRLA - USART_EXT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - TXINV - Transmit Data Invert - 9 - 1 - - - RXINV - Receive Data Invert - 10 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD3 - SERCOM_PAD[0] is used for data transmission - 0x3 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - USART_FRAME_ISO_7816 - ISO 7816 - 0x7 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_EXT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_EXT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - INACK - Inhibit Not Acknowledge - 16 - 1 - - - DSNACK - Disable Successive NACK - 17 - 1 - - - MAXITER - Maximum Iterations - 20 - 3 - - - DATA32B - Data 32 Bit - 24 - 2 - - DATA32BSelect - - DATA_READ_WRITE_CHSIZE - Data reads and writes according CTRLB.CHSIZE - 0x0 - - - DATA_READ_CHSIZE_WRITE_32BIT - Data reads according CTRLB.CHSIZE and writes according 32-bit extension - 0x1 - - - DATA_READ_32BIT_WRITE_CHSIZE - Data reads according 32-bit extension and writes according CTRLB.CHSIZE - 0x2 - - - DATA_READ_WRITE_32BIT - Data reads and writes according 32-bit extension - 0x3 - - - - - - - BAUD - USART_EXT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_EXT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_EXT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_EXT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_EXT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_EXT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - ITER - Maximum Number of Repetitions Reached - 7 - 1 - - - - - SYNCBUSY - USART_EXT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - RXERRCNT - RXERRCNT Synchronization Busy - 3 - 1 - - - LENGTH - LENGTH Synchronization Busy - 4 - 1 - - - - - RXERRCNT - USART_EXT Receive Error Count - 0x20 - 8 - read-only - 0x00 - - - LENGTH - USART_EXT Length - 0x22 - 16 - 0x0000 - - - LEN - Data Length - 0 - 8 - - - LENEN - Data Length Enable - 8 - 2 - - - - - DATA - USART_EXT Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 32 - - - - - DBGCTRL - USART_EXT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_INT - USART INTERNAL CLOCK Mode - I2CM - SercomUsart_int - 0x0 - - CTRLA - USART_INT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - TXINV - Transmit Data Invert - 9 - 1 - - - RXINV - Receive Data Invert - 10 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD3 - SERCOM_PAD[0] is used for data transmission - 0x3 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - USART_FRAME_ISO_7816 - ISO 7816 - 0x7 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_INT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_INT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - INACK - Inhibit Not Acknowledge - 16 - 1 - - - DSNACK - Disable Successive NACK - 17 - 1 - - - MAXITER - Maximum Iterations - 20 - 3 - - - DATA32B - Data 32 Bit - 24 - 2 - - DATA32BSelect - - DATA_READ_WRITE_CHSIZE - Data reads and writes according CTRLB.CHSIZE - 0x0 - - - DATA_READ_CHSIZE_WRITE_32BIT - Data reads according CTRLB.CHSIZE and writes according 32-bit extension - 0x1 - - - DATA_READ_32BIT_WRITE_CHSIZE - Data reads according 32-bit extension and writes according CTRLB.CHSIZE - 0x2 - - - DATA_READ_WRITE_32BIT - Data reads and writes according 32-bit extension - 0x3 - - - - - - - BAUD - USART_INT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_INT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_INT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_INT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_INT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_INT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - ITER - Maximum Number of Repetitions Reached - 7 - 1 - - - - - SYNCBUSY - USART_INT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - RXERRCNT - RXERRCNT Synchronization Busy - 3 - 1 - - - LENGTH - LENGTH Synchronization Busy - 4 - 1 - - - - - RXERRCNT - USART_INT Receive Error Count - 0x20 - 8 - read-only - 0x00 - - - LENGTH - USART_INT Length - 0x22 - 16 - 0x0000 - - - LEN - Data Length - 0 - 8 - - - LENEN - Data Length Enable - 8 - 2 - - - - - DATA - USART_INT Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 32 - - - - - DBGCTRL - USART_INT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - - - SERCOM1 - 0x40003400 - - SERCOM1_0 - 50 - - - SERCOM1_1 - 51 - - - SERCOM1_2 - 52 - - - SERCOM1_OTHER - 53 - - - - SERCOM2 - 0x41012000 - - SERCOM2_0 - 54 - - - SERCOM2_1 - 55 - - - SERCOM2_2 - 56 - - - SERCOM2_OTHER - 57 - - - - SERCOM3 - 0x41014000 - - SERCOM3_0 - 58 - - - SERCOM3_1 - 59 - - - SERCOM3_2 - 60 - - - SERCOM3_OTHER - 61 - - - - SERCOM4 - 0x43000000 - - SERCOM4_0 - 62 - - - SERCOM4_1 - 63 - - - SERCOM4_2 - 64 - - - SERCOM4_OTHER - 65 - - - - SERCOM5 - 0x43000400 - - SERCOM5_0 - 66 - - - SERCOM5_1 - 67 - - - SERCOM5_2 - 68 - - - SERCOM5_OTHER - 69 - - - - SUPC - U24071.1.0 - Supply Controller - SUPC - SUPC_ - 0x40001800 - - 0 - 0x2C - registers - - - SUPC_OTHER - 8 - - - SUPC_BODDET - 9 - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - BOD33RDY - BOD33 Ready - 0 - 1 - - - BOD33DET - BOD33 Detection - 1 - 1 - - - B33SRDY - BOD33 Synchronization Ready - 2 - 1 - - - VREGRDY - Voltage Regulator Ready - 8 - 1 - - - VCORERDY - VDDCORE Ready - 10 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - BOD33RDY - BOD33 Ready - 0 - 1 - - - BOD33DET - BOD33 Detection - 1 - 1 - - - B33SRDY - BOD33 Synchronization Ready - 2 - 1 - - - VREGRDY - Voltage Regulator Ready - 8 - 1 - - - VCORERDY - VDDCORE Ready - 10 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - BOD33RDY - BOD33 Ready - 0 - 1 - - - BOD33DET - BOD33 Detection - 1 - 1 - - - B33SRDY - BOD33 Synchronization Ready - 2 - 1 - - - VREGRDY - Voltage Regulator Ready - 8 - 1 - - - VCORERDY - VDDCORE Ready - 10 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - BOD33RDY - BOD33 Ready - 0 - 1 - - - BOD33DET - BOD33 Detection - 1 - 1 - - - B33SRDY - BOD33 Synchronization Ready - 2 - 1 - - - VREGRDY - Voltage Regulator Ready - 8 - 1 - - - VCORERDY - VDDCORE Ready - 10 - 1 - - - - - BOD33 - BOD33 Control - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - ACTION - Action when Threshold Crossed - 2 - 2 - - ACTIONSelect - - NONE - No action - 0x0 - - - RESET - The BOD33 generates a reset - 0x1 - - - INT - The BOD33 generates an interrupt - 0x2 - - - BKUP - The BOD33 puts the device in backup sleep mode - 0x3 - - - - - STDBYCFG - Configuration in Standby mode - 4 - 1 - - - RUNSTDBY - Run in Standby mode - 5 - 1 - - - RUNHIB - Run in Hibernate mode - 6 - 1 - - - RUNBKUP - Run in Backup mode - 7 - 1 - - - HYST - Hysteresis value - 8 - 4 - - - PSEL - Prescaler Select - 12 - 3 - - PSELSelect - - NODIV - Not divided - 0x0 - - - DIV4 - Divide clock by 4 - 0x1 - - - DIV8 - Divide clock by 8 - 0x2 - - - DIV16 - Divide clock by 16 - 0x3 - - - DIV32 - Divide clock by 32 - 0x4 - - - DIV64 - Divide clock by 64 - 0x5 - - - DIV128 - Divide clock by 128 - 0x6 - - - DIV256 - Divide clock by 256 - 0x7 - - - - - LEVEL - Threshold Level for VDD - 16 - 8 - - - VBATLEVEL - Threshold Level in battery backup sleep mode for VBAT - 24 - 8 - - - - - VREG - VREG Control - 0x18 - 32 - 0x00000002 - - - ENABLE - Enable - 1 - 1 - - - SEL - Voltage Regulator Selection - 2 - 1 - - SELSelect - - LDO - LDO selection - 0x0 - - - BUCK - Buck selection - 0x1 - - - - - RUNBKUP - Run in Backup mode - 7 - 1 - - - VSEN - Voltage Scaling Enable - 16 - 1 - - - VSPER - Voltage Scaling Period - 24 - 3 - - - - - VREF - VREF Control - 0x1C - 32 - 0x00000000 - - - TSEN - Temperature Sensor Output Enable - 1 - 1 - - - VREFOE - Voltage Reference Output Enable - 2 - 1 - - - TSSEL - Temperature Sensor Selection - 3 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - On Demand Contrl - 7 - 1 - - - SEL - Voltage Reference Selection - 16 - 4 - - SELSelect - - 1V0 - 1.0V voltage reference typical value - 0x0 - - - 1V1 - 1.1V voltage reference typical value - 0x1 - - - 1V2 - 1.2V voltage reference typical value - 0x2 - - - 1V25 - 1.25V voltage reference typical value - 0x3 - - - 2V0 - 2.0V voltage reference typical value - 0x4 - - - 2V2 - 2.2V voltage reference typical value - 0x5 - - - 2V4 - 2.4V voltage reference typical value - 0x6 - - - 2V5 - 2.5V voltage reference typical value - 0x7 - - - - - - - BBPS - Battery Backup Power Switch - 0x20 - 32 - 0x00000000 - - - CONF - Battery Backup Configuration - 0 - 1 - - CONFSelect - - BOD33 - The power switch is handled by the BOD33 - 0x0 - - - FORCED - In Backup Domain, the backup domain is always supplied by battery backup power - 0x1 - - - - - WAKEEN - Wake Enable - 2 - 1 - - - - - BKOUT - Backup Output Control - 0x24 - 32 - 0x00000000 - - - ENOUT0 - Enable OUT0 - 0 - 1 - - - ENOUT1 - Enable OUT1 - 1 - 1 - - - CLROUT0 - Clear OUT0 - 8 - 1 - - - CLROUT1 - Clear OUT1 - 9 - 1 - - - SETOUT0 - Set OUT0 - 16 - 1 - - - SETOUT1 - Set OUT1 - 17 - 1 - - - RTCTGLOUT0 - RTC Toggle OUT0 - 24 - 1 - - - RTCTGLOUT1 - RTC Toggle OUT1 - 25 - 1 - - - - - BKIN - Backup Input Control - 0x28 - 32 - read-only - 0x00000000 - - - BKIN0 - Backup Input 0 - 0 - 1 - - - BKIN1 - Backup Input 1 - 1 - 1 - - - - - - - TC0 - U22493.0.0 - Basic Timer Counter - TC - TC_ - 0x40003800 - - 0 - 0x38 - registers - - - TC0 - 107 - - - - COUNT8 - 8-bit Counter Mode - TcCount8 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - CAPTMODE0 - Capture Mode Channel 0 - 24 - 2 - - CAPTMODE0Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - CAPTMODE1 - Capture mode Channel 1 - 27 - 2 - - CAPTMODE1Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT8 Count - 0x14 - 8 - 0x00 - - - COUNT - Counter Value - 0 - 8 - - - - - PER - COUNT8 Period - 0x1B - 8 - 0xFF - - - PER - Period Value - 0 - 8 - - - - - 2 - 1 - CC[%s] - COUNT8 Compare and Capture - 0x1C - 8 - 0x00 - - - CC - Counter/Compare Value - 0 - 8 - - - - - PERBUF - COUNT8 Period Buffer - 0x2F - 8 - 0xFF - - - PERBUF - Period Buffer Value - 0 - 8 - - - - - 2 - 1 - CCBUF[%s] - COUNT8 Compare and Capture Buffer - 0x30 - 8 - 0x00 - - - CCBUF - Counter/Compare Buffer Value - 0 - 8 - - - - - - COUNT16 - 16-bit Counter Mode - COUNT8 - TcCount16 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - CAPTMODE0 - Capture Mode Channel 0 - 24 - 2 - - CAPTMODE0Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - CAPTMODE1 - Capture mode Channel 1 - 27 - 2 - - CAPTMODE1Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT16 Count - 0x14 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - 2 - 2 - CC[%s] - COUNT16 Compare and Capture - 0x1C - 16 - 0x0000 - - - CC - Counter/Compare Value - 0 - 16 - - - - - 2 - 2 - CCBUF[%s] - COUNT16 Compare and Capture Buffer - 0x30 - 16 - 0x0000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 16 - - - - - - COUNT32 - 32-bit Counter Mode - COUNT8 - TcCount32 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - CAPTMODE0 - Capture Mode Channel 0 - 24 - 2 - - CAPTMODE0Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - CAPTMODE1 - Capture mode Channel 1 - 27 - 2 - - CAPTMODE1Select - - DEFAULT - Default capture - 0 - - - CAPTMIN - Minimum capture - 1 - - - CAPTMAX - Maximum capture - 2 - - - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT32 Count - 0x14 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - 2 - 4 - CC[%s] - COUNT32 Compare and Capture - 0x1C - 32 - 0x00000000 - - - CC - Counter/Compare Value - 0 - 32 - - - - - 2 - 4 - CCBUF[%s] - COUNT32 Compare and Capture Buffer - 0x30 - 32 - 0x00000000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 32 - - - - - - - - TC1 - 0x40003C00 - - TC1 - 108 - - - - TC2 - 0x4101A000 - - TC2 - 109 - - - - TC3 - 0x4101C000 - - TC3 - 110 - - - - TC4 - 0x42001400 - - TC4 - 111 - - - - TC5 - 0x42001800 - - TC5 - 112 - - - - TCC0 - U22133.1.0 - Timer Counter Control - TCC - TCC_ - 0x41016000 - - 0 - 0x88 - registers - - - TCC0_OTHER - 85 - - - TCC0_MC0 - 86 - - - TCC0_MC1 - 87 - - - TCC0_MC2 - 88 - - - TCC0_MC3 - 89 - - - TCC0_MC4 - 90 - - - TCC0_MC5 - 91 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RESOLUTION - Enhanced Resolution - 5 - 2 - - RESOLUTIONSelect - - NONE - Dithering is disabled - 0 - - - DITH4 - Dithering is done every 16 PWM frames - 1 - - - DITH5 - Dithering is done every 32 PWM frames - 2 - - - DITH6 - Dithering is done every 64 PWM frames - 3 - - - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - No division - 0 - - - DIV2 - Divide by 2 - 1 - - - DIV4 - Divide by 4 - 2 - - - DIV8 - Divide by 8 - 3 - - - DIV16 - Divide by 16 - 4 - - - DIV64 - Divide by 64 - 5 - - - DIV256 - Divide by 256 - 6 - - - DIV1024 - Divide by 1024 - 7 - - - - - RUNSTDBY - Run in Standby - 11 - 1 - - - PRESCSYNC - Prescaler and Counter Synchronization Selection - 12 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset counter on next GCLK - 0 - - - PRESC - Reload or reset counter on next prescaler clock - 1 - - - RESYNC - Reload or reset counter on next GCLK and reset prescaler counter - 2 - - - - - ALOCK - Auto Lock - 14 - 1 - - - MSYNC - Master Synchronization (only for TCC Slave Instance) - 15 - 1 - - - DMAOS - DMA One-shot Trigger Mode - 23 - 1 - - - CPTEN0 - Capture Channel 0 Enable - 24 - 1 - - - CPTEN1 - Capture Channel 1 Enable - 25 - 1 - - - CPTEN2 - Capture Channel 2 Enable - 26 - 1 - - - CPTEN3 - Capture Channel 3 Enable - 27 - 1 - - - CPTEN4 - Capture Channel 4 Enable - 28 - 1 - - - CPTEN5 - Capture Channel 5 Enable - 29 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - SWRST - Swrst Busy - 0 - 1 - - - ENABLE - Enable Busy - 1 - 1 - - - CTRLB - Ctrlb Busy - 2 - 1 - - - STATUS - Status Busy - 3 - 1 - - - COUNT - Count Busy - 4 - 1 - - - PATT - Pattern Busy - 5 - 1 - - - WAVE - Wave Busy - 6 - 1 - - - PER - Period Busy - 7 - 1 - - - CC0 - Compare Channel 0 Busy - 8 - 1 - - - CC1 - Compare Channel 1 Busy - 9 - 1 - - - CC2 - Compare Channel 2 Busy - 10 - 1 - - - CC3 - Compare Channel 3 Busy - 11 - 1 - - - CC4 - Compare Channel 4 Busy - 12 - 1 - - - CC5 - Compare Channel 5 Busy - 13 - 1 - - - - - FCTRLA - Recoverable Fault A Configuration - 0xC - 32 - 0x00000000 - - - SRC - Fault A Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault A Keeper - 3 - 1 - - - QUAL - Fault A Qualification - 4 - 1 - - - BLANK - Fault A Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault A Restart - 7 - 1 - - - HALT - Fault A Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault A Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault A Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault A Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault A Blanking Time - 16 - 8 - - - FILTERVAL - Fault A Filter Value - 24 - 4 - - - - - FCTRLB - Recoverable Fault B Configuration - 0x10 - 32 - 0x00000000 - - - SRC - Fault B Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault B Keeper - 3 - 1 - - - QUAL - Fault B Qualification - 4 - 1 - - - BLANK - Fault B Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault B Restart - 7 - 1 - - - HALT - Fault B Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault B Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault B Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault B Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault B Blanking Time - 16 - 8 - - - FILTERVAL - Fault B Filter Value - 24 - 4 - - - - - WEXCTRL - Waveform Extension Configuration - 0x14 - 32 - 0x00000000 - - - OTMX - Output Matrix - 0 - 2 - - - DTIEN0 - Dead-time Insertion Generator 0 Enable - 8 - 1 - - - DTIEN1 - Dead-time Insertion Generator 1 Enable - 9 - 1 - - - DTIEN2 - Dead-time Insertion Generator 2 Enable - 10 - 1 - - - DTIEN3 - Dead-time Insertion Generator 3 Enable - 11 - 1 - - - DTLS - Dead-time Low Side Outputs Value - 16 - 8 - - - DTHS - Dead-time High Side Outputs Value - 24 - 8 - - - - - DRVCTRL - Driver Control - 0x18 - 32 - 0x00000000 - - - NRE0 - Non-Recoverable State 0 Output Enable - 0 - 1 - - - NRE1 - Non-Recoverable State 1 Output Enable - 1 - 1 - - - NRE2 - Non-Recoverable State 2 Output Enable - 2 - 1 - - - NRE3 - Non-Recoverable State 3 Output Enable - 3 - 1 - - - NRE4 - Non-Recoverable State 4 Output Enable - 4 - 1 - - - NRE5 - Non-Recoverable State 5 Output Enable - 5 - 1 - - - NRE6 - Non-Recoverable State 6 Output Enable - 6 - 1 - - - NRE7 - Non-Recoverable State 7 Output Enable - 7 - 1 - - - NRV0 - Non-Recoverable State 0 Output Value - 8 - 1 - - - NRV1 - Non-Recoverable State 1 Output Value - 9 - 1 - - - NRV2 - Non-Recoverable State 2 Output Value - 10 - 1 - - - NRV3 - Non-Recoverable State 3 Output Value - 11 - 1 - - - NRV4 - Non-Recoverable State 4 Output Value - 12 - 1 - - - NRV5 - Non-Recoverable State 5 Output Value - 13 - 1 - - - NRV6 - Non-Recoverable State 6 Output Value - 14 - 1 - - - NRV7 - Non-Recoverable State 7 Output Value - 15 - 1 - - - INVEN0 - Output Waveform 0 Inversion - 16 - 1 - - - INVEN1 - Output Waveform 1 Inversion - 17 - 1 - - - INVEN2 - Output Waveform 2 Inversion - 18 - 1 - - - INVEN3 - Output Waveform 3 Inversion - 19 - 1 - - - INVEN4 - Output Waveform 4 Inversion - 20 - 1 - - - INVEN5 - Output Waveform 5 Inversion - 21 - 1 - - - INVEN6 - Output Waveform 6 Inversion - 22 - 1 - - - INVEN7 - Output Waveform 7 Inversion - 23 - 1 - - - FILTERVAL0 - Non-Recoverable Fault Input 0 Filter Value - 24 - 4 - - - FILTERVAL1 - Non-Recoverable Fault Input 1 Filter Value - 28 - 4 - - - - - DBGCTRL - Debug Control - 0x1E - 8 - 0x00 - - - DBGRUN - Debug Running Mode - 0 - 1 - - - FDDBD - Fault Detection on Debug Break Detection - 2 - 1 - - - - - EVCTRL - Event Control - 0x20 - 32 - 0x00000000 - - - EVACT0 - Timer/counter Input Event0 Action - 0 - 3 - - EVACT0Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or re-trigger counter on event - 1 - - - COUNTEV - Count on event - 2 - - - START - Start counter on event - 3 - - - INC - Increment counter on event - 4 - - - COUNT - Count on active state of asynchronous event - 5 - - - STAMP - Stamp capture - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - EVACT1 - Timer/counter Input Event1 Action - 3 - 3 - - EVACT1Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Re-trigger counter on event - 1 - - - DIR - Direction control - 2 - - - STOP - Stop counter on event - 3 - - - DEC - Decrement counter on event - 4 - - - PPW - Period capture value in CC0 register, pulse width capture value in CC1 register - 5 - - - PWP - Period capture value in CC1 register, pulse width capture value in CC0 register - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - CNTSEL - Timer/counter Output Event Mode - 6 - 2 - - CNTSELSelect - - START - An interrupt/event is generated when a new counter cycle starts - 0 - - - END - An interrupt/event is generated when a counter cycle ends - 1 - - - BETWEEN - An interrupt/event is generated when a counter cycle ends, except for the first and last cycles - 2 - - - BOUNDARY - An interrupt/event is generated when a new counter cycle starts or a counter cycle ends - 3 - - - - - OVFEO - Overflow/Underflow Output Event Enable - 8 - 1 - - - TRGEO - Retrigger Output Event Enable - 9 - 1 - - - CNTEO - Timer/counter Output Event Enable - 10 - 1 - - - TCINV0 - Inverted Event 0 Input Enable - 12 - 1 - - - TCINV1 - Inverted Event 1 Input Enable - 13 - 1 - - - TCEI0 - Timer/counter Event 0 Input Enable - 14 - 1 - - - TCEI1 - Timer/counter Event 1 Input Enable - 15 - 1 - - - MCEI0 - Match or Capture Channel 0 Event Input Enable - 16 - 1 - - - MCEI1 - Match or Capture Channel 1 Event Input Enable - 17 - 1 - - - MCEI2 - Match or Capture Channel 2 Event Input Enable - 18 - 1 - - - MCEI3 - Match or Capture Channel 3 Event Input Enable - 19 - 1 - - - MCEI4 - Match or Capture Channel 4 Event Input Enable - 20 - 1 - - - MCEI5 - Match or Capture Channel 5 Event Input Enable - 21 - 1 - - - MCEO0 - Match or Capture Channel 0 Event Output Enable - 24 - 1 - - - MCEO1 - Match or Capture Channel 1 Event Output Enable - 25 - 1 - - - MCEO2 - Match or Capture Channel 2 Event Output Enable - 26 - 1 - - - MCEO3 - Match or Capture Channel 3 Event Output Enable - 27 - 1 - - - MCEO4 - Match or Capture Channel 4 Event Output Enable - 28 - 1 - - - MCEO5 - Match or Capture Channel 5 Event Output Enable - 29 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x24 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - MC4 - Match or Capture Channel 4 Interrupt Enable - 20 - 1 - - - MC5 - Match or Capture Channel 5 Interrupt Enable - 21 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x28 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - MC4 - Match or Capture Channel 4 Interrupt Enable - 20 - 1 - - - MC5 - Match or Capture Channel 5 Interrupt Enable - 21 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x2C - 32 - 0x00000000 - - - OVF - Overflow - 0 - 1 - - - TRG - Retrigger - 1 - 1 - - - CNT - Counter - 2 - 1 - - - ERR - Error - 3 - 1 - - - UFS - Non-Recoverable Update Fault - 10 - 1 - - - DFS - Non-Recoverable Debug Fault - 11 - 1 - - - FAULTA - Recoverable Fault A - 12 - 1 - - - FAULTB - Recoverable Fault B - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 - 15 - 1 - - - MC0 - Match or Capture 0 - 16 - 1 - - - MC1 - Match or Capture 1 - 17 - 1 - - - MC2 - Match or Capture 2 - 18 - 1 - - - MC3 - Match or Capture 3 - 19 - 1 - - - MC4 - Match or Capture 4 - 20 - 1 - - - MC5 - Match or Capture 5 - 21 - 1 - - - - - STATUS - Status - 0x30 - 32 - 0x00000001 - - - STOP - Stop - 0 - 1 - - - IDX - Ramp - 1 - 1 - - - UFS - Non-recoverable Update Fault State - 2 - 1 - - - DFS - Non-Recoverable Debug Fault State - 3 - 1 - - - SLAVE - Slave - 4 - 1 - - - PATTBUFV - Pattern Buffer Valid - 5 - 1 - - - PERBUFV - Period Buffer Valid - 7 - 1 - - - FAULTAIN - Recoverable Fault A Input - 8 - 1 - - - FAULTBIN - Recoverable Fault B Input - 9 - 1 - - - FAULT0IN - Non-Recoverable Fault0 Input - 10 - 1 - - - FAULT1IN - Non-Recoverable Fault1 Input - 11 - 1 - - - FAULTA - Recoverable Fault A State - 12 - 1 - - - FAULTB - Recoverable Fault B State - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 State - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 State - 15 - 1 - - - CCBUFV0 - Compare Channel 0 Buffer Valid - 16 - 1 - - - CCBUFV1 - Compare Channel 1 Buffer Valid - 17 - 1 - - - CCBUFV2 - Compare Channel 2 Buffer Valid - 18 - 1 - - - CCBUFV3 - Compare Channel 3 Buffer Valid - 19 - 1 - - - CCBUFV4 - Compare Channel 4 Buffer Valid - 20 - 1 - - - CCBUFV5 - Compare Channel 5 Buffer Valid - 21 - 1 - - - CMP0 - Compare Channel 0 Value - 24 - 1 - - - CMP1 - Compare Channel 1 Value - 25 - 1 - - - CMP2 - Compare Channel 2 Value - 26 - 1 - - - CMP3 - Compare Channel 3 Value - 27 - 1 - - - CMP4 - Compare Channel 4 Value - 28 - 1 - - - CMP5 - Compare Channel 5 Value - 29 - 1 - - - - - COUNT - Count - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 24 - - - - - COUNT_DITH4_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 4 - 20 - - - - - COUNT_DITH5_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 5 - 19 - - - - - COUNT_DITH6_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 6 - 18 - - - - - PATT - Pattern - 0x38 - 16 - 0x0000 - - - PGE0 - Pattern Generator 0 Output Enable - 0 - 1 - - - PGE1 - Pattern Generator 1 Output Enable - 1 - 1 - - - PGE2 - Pattern Generator 2 Output Enable - 2 - 1 - - - PGE3 - Pattern Generator 3 Output Enable - 3 - 1 - - - PGE4 - Pattern Generator 4 Output Enable - 4 - 1 - - - PGE5 - Pattern Generator 5 Output Enable - 5 - 1 - - - PGE6 - Pattern Generator 6 Output Enable - 6 - 1 - - - PGE7 - Pattern Generator 7 Output Enable - 7 - 1 - - - PGV0 - Pattern Generator 0 Output Value - 8 - 1 - - - PGV1 - Pattern Generator 1 Output Value - 9 - 1 - - - PGV2 - Pattern Generator 2 Output Value - 10 - 1 - - - PGV3 - Pattern Generator 3 Output Value - 11 - 1 - - - PGV4 - Pattern Generator 4 Output Value - 12 - 1 - - - PGV5 - Pattern Generator 5 Output Value - 13 - 1 - - - PGV6 - Pattern Generator 6 Output Value - 14 - 1 - - - PGV7 - Pattern Generator 7 Output Value - 15 - 1 - - - - - WAVE - Waveform Control - 0x3C - 32 - 0x00000000 - - - WAVEGEN - Waveform Generation - 0 - 3 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - DSCRITICAL - Dual-slope critical - 4 - - - DSBOTTOM - Dual-slope with interrupt/event condition when COUNT reaches ZERO - 5 - - - DSBOTH - Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP - 6 - - - DSTOP - Dual-slope with interrupt/event condition when COUNT reaches TOP - 7 - - - - - RAMP - Ramp Mode - 4 - 2 - - RAMPSelect - - RAMP1 - RAMP1 operation - 0 - - - RAMP2A - Alternative RAMP2 operation - 1 - - - RAMP2 - RAMP2 operation - 2 - - - RAMP2C - Critical RAMP2 operation - 3 - - - - - CIPEREN - Circular period Enable - 7 - 1 - - - CICCEN0 - Circular Channel 0 Enable - 8 - 1 - - - CICCEN1 - Circular Channel 1 Enable - 9 - 1 - - - CICCEN2 - Circular Channel 2 Enable - 10 - 1 - - - CICCEN3 - Circular Channel 3 Enable - 11 - 1 - - - POL0 - Channel 0 Polarity - 16 - 1 - - - POL1 - Channel 1 Polarity - 17 - 1 - - - POL2 - Channel 2 Polarity - 18 - 1 - - - POL3 - Channel 3 Polarity - 19 - 1 - - - POL4 - Channel 4 Polarity - 20 - 1 - - - POL5 - Channel 5 Polarity - 21 - 1 - - - SWAP0 - Swap DTI Output Pair 0 - 24 - 1 - - - SWAP1 - Swap DTI Output Pair 1 - 25 - 1 - - - SWAP2 - Swap DTI Output Pair 2 - 26 - 1 - - - SWAP3 - Swap DTI Output Pair 3 - 27 - 1 - - - - - PER - Period - 0x40 - 32 - 0xFFFFFFFF - - - PER - Period Value - 0 - 24 - - - - - PER_DITH4_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 4 - - - PER - Period Value - 4 - 20 - - - - - PER_DITH5_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 5 - - - PER - Period Value - 5 - 19 - - - - - PER_DITH6_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 6 - - - PER - Period Value - 6 - 18 - - - - - 6 - 4 - CC[%s] - Compare and Capture - 0x44 - 32 - 0x00000000 - - - CC - Channel Compare/Capture Value - 0 - 24 - - - - - 6 - 4 - CC_DITH4_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 4 - - - CC - Channel Compare/Capture Value - 4 - 20 - - - - - 6 - 4 - CC_DITH5_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 5 - - - CC - Channel Compare/Capture Value - 5 - 19 - - - - - 6 - 4 - CC_DITH6_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 6 - - - CC - Channel Compare/Capture Value - 6 - 18 - - - - - PATTBUF - Pattern Buffer - 0x64 - 16 - 0x0000 - - - PGEB0 - Pattern Generator 0 Output Enable Buffer - 0 - 1 - - - PGEB1 - Pattern Generator 1 Output Enable Buffer - 1 - 1 - - - PGEB2 - Pattern Generator 2 Output Enable Buffer - 2 - 1 - - - PGEB3 - Pattern Generator 3 Output Enable Buffer - 3 - 1 - - - PGEB4 - Pattern Generator 4 Output Enable Buffer - 4 - 1 - - - PGEB5 - Pattern Generator 5 Output Enable Buffer - 5 - 1 - - - PGEB6 - Pattern Generator 6 Output Enable Buffer - 6 - 1 - - - PGEB7 - Pattern Generator 7 Output Enable Buffer - 7 - 1 - - - PGVB0 - Pattern Generator 0 Output Enable - 8 - 1 - - - PGVB1 - Pattern Generator 1 Output Enable - 9 - 1 - - - PGVB2 - Pattern Generator 2 Output Enable - 10 - 1 - - - PGVB3 - Pattern Generator 3 Output Enable - 11 - 1 - - - PGVB4 - Pattern Generator 4 Output Enable - 12 - 1 - - - PGVB5 - Pattern Generator 5 Output Enable - 13 - 1 - - - PGVB6 - Pattern Generator 6 Output Enable - 14 - 1 - - - PGVB7 - Pattern Generator 7 Output Enable - 15 - 1 - - - - - PERBUF - Period Buffer - 0x6C - 32 - 0xFFFFFFFF - - - PERBUF - Period Buffer Value - 0 - 24 - - - - - PERBUF_DITH4_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 4 - - - PERBUF - Period Buffer Value - 4 - 20 - - - - - PERBUF_DITH5_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - PERBUF - Period Buffer Value - 5 - 19 - - - - - PERBUF_DITH6_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - PERBUF - Period Buffer Value - 6 - 18 - - - - - 6 - 4 - CCBUF[%s] - Compare and Capture Buffer - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 24 - - - - - 6 - 4 - CCBUF_DITH4_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 4 - - - DITHERBUF - Dithering Buffer Cycle Number - 4 - 20 - - - - - 6 - 4 - CCBUF_DITH5_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - CCBUF - Channel Compare/Capture Buffer Value - 5 - 19 - - - - - 6 - 4 - CCBUF_DITH6_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - CCBUF - Channel Compare/Capture Buffer Value - 6 - 18 - - - - - - - TCC1 - 0x41018000 - - TCC1_OTHER - 92 - - - TCC1_MC0 - 93 - - - TCC1_MC1 - 94 - - - TCC1_MC2 - 95 - - - TCC1_MC3 - 96 - - - - TCC2 - 0x42000C00 - - TCC2_OTHER - 97 - - - TCC2_MC0 - 98 - - - TCC2_MC1 - 99 - - - TCC2_MC2 - 100 - - - - TCC3 - 0x42001000 - - TCC3_OTHER - 101 - - - TCC3_MC0 - 102 - - - TCC3_MC1 - 103 - - - - TCC4 - 0x43001000 - - TCC4_OTHER - 104 - - - TCC4_MC0 - 105 - - - TCC4_MC1 - 106 - - - - TRNG - U22421.1.0 - True Random Generator - TRNG - TRNG_ - 0x42002800 - - 0 - 0x24 - registers - - - TRNG - 131 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - - - EVCTRL - Event Control - 0x4 - 8 - 0x00 - - - DATARDYEO - Data Ready Event Output - 0 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - DATARDY - Data Ready Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - DATARDY - Data Ready Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - DATARDY - Data Ready Interrupt Flag - 0 - 1 - - - - - DATA - Output Data - 0x20 - 32 - read-only - 0x00000000 - - - DATA - Output Data - 0 - 32 - - - - - - - USB - U22221.2.0 - Universal Serial Bus - USB - USB_ - 0x41000000 - - 0 - 0x200 - registers - - - USB_OTHER - 80 - - - USB_SOF_HSOF - 81 - - - USB_TRCPT0 - 82 - - - USB_TRCPT1 - 83 - - - - DEVICE - USB is Device - UsbDevice - 0x0 - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby Mode - 2 - 1 - - - MODE - Operating Mode - 7 - 1 - - MODESelect - - DEVICE - Device Mode - 0 - - - HOST - Host Mode - 1 - - - - - - - SYNCBUSY - Synchronization Busy - 0x2 - 8 - read-only - 0x00 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - - - QOSCTRL - USB Quality Of Service - 0x3 - 8 - 0x0F - - - CQOS - Configuration Quality of Service - 0 - 2 - - - DQOS - Data Quality of Service - 2 - 2 - - - - - CTRLB - DEVICE Control B - 0x8 - 16 - 0x0001 - - - DETACH - Detach - 0 - 1 - - - UPRSM - Upstream Resume - 1 - 1 - - - SPDCONF - Speed Configuration - 2 - 2 - - SPDCONFSelect - - FS - FS : Full Speed - 0x0 - - - LS - LS : Low Speed - 0x1 - - - HS - HS : High Speed capable - 0x2 - - - HSTM - HSTM: High Speed Test Mode (force high-speed mode for test mode) - 0x3 - - - - - NREPLY - No Reply - 4 - 1 - - - TSTJ - Test mode J - 5 - 1 - - - TSTK - Test mode K - 6 - 1 - - - TSTPCKT - Test packet mode - 7 - 1 - - - OPMODE2 - Specific Operational Mode - 8 - 1 - - - GNAK - Global NAK - 9 - 1 - - - LPMHDSK - Link Power Management Handshake - 10 - 2 - - LPMHDSKSelect - - NO - No handshake. LPM is not supported - 0 - - - ACK - ACK - 1 - - - NYET - NYET - 2 - - - STALL - STALL - 3 - - - - - - - DADD - DEVICE Device Address - 0xA - 8 - 0x00 - - - DADD - Device Address - 0 - 7 - - - ADDEN - Device Address Enable - 7 - 1 - - - - - STATUS - DEVICE Status - 0xC - 8 - read-only - 0x40 - - - SPEED - Speed Status - 2 - 2 - - SPEEDSelect - - FS - Full-speed mode - 0x0 - - - LS - Low-speed mode - 0x1 - - - HS - High-speed mode - 0x2 - - - - - LINESTATE - USB Line State Status - 6 - 2 - - LINESTATESelect - - 0 - SE0/RESET - 0x0 - - - 1 - FS-J or LS-K State - 0x1 - - - 2 - FS-K or LS-J State - 0x2 - - - - - - - FSMSTATUS - Finite State Machine Status - 0xD - 8 - read-only - 0x01 - - - FSMSTATE - Fine State Machine Status - 0 - 7 - - FSMSTATESelect - - OFF - OFF (L3). It corresponds to the powered-off, disconnected, and disabled state - 0x1 - - - ON - ON (L0). It corresponds to the Idle and Active states - 0x2 - - - SUSPEND - SUSPEND (L2) - 0x4 - - - SLEEP - SLEEP (L1) - 0x8 - - - DNRESUME - DNRESUME. Down Stream Resume. - 0x10 - - - UPRESUME - UPRESUME. Up Stream Resume. - 0x20 - - - RESET - RESET. USB lines Reset. - 0x40 - - - - - - - FNUM - DEVICE Device Frame Number - 0x10 - 16 - read-only - 0x0000 - - - MFNUM - Micro Frame Number - 0 - 3 - - - FNUM - Frame Number - 3 - 11 - - - FNCERR - Frame Number CRC Error - 15 - 1 - - - - - INTENCLR - DEVICE Device Interrupt Enable Clear - 0x14 - 16 - 0x0000 - - - SUSPEND - Suspend Interrupt Enable - 0 - 1 - - - MSOF - Micro Start of Frame Interrupt Enable in High Speed Mode - 1 - 1 - - - SOF - Start Of Frame Interrupt Enable - 2 - 1 - - - EORST - End of Reset Interrupt Enable - 3 - 1 - - - WAKEUP - Wake Up Interrupt Enable - 4 - 1 - - - EORSM - End Of Resume Interrupt Enable - 5 - 1 - - - UPRSM - Upstream Resume Interrupt Enable - 6 - 1 - - - RAMACER - Ram Access Interrupt Enable - 7 - 1 - - - LPMNYET - Link Power Management Not Yet Interrupt Enable - 8 - 1 - - - LPMSUSP - Link Power Management Suspend Interrupt Enable - 9 - 1 - - - - - INTENSET - DEVICE Device Interrupt Enable Set - 0x18 - 16 - 0x0000 - - - SUSPEND - Suspend Interrupt Enable - 0 - 1 - - - MSOF - Micro Start of Frame Interrupt Enable in High Speed Mode - 1 - 1 - - - SOF - Start Of Frame Interrupt Enable - 2 - 1 - - - EORST - End of Reset Interrupt Enable - 3 - 1 - - - WAKEUP - Wake Up Interrupt Enable - 4 - 1 - - - EORSM - End Of Resume Interrupt Enable - 5 - 1 - - - UPRSM - Upstream Resume Interrupt Enable - 6 - 1 - - - RAMACER - Ram Access Interrupt Enable - 7 - 1 - - - LPMNYET - Link Power Management Not Yet Interrupt Enable - 8 - 1 - - - LPMSUSP - Link Power Management Suspend Interrupt Enable - 9 - 1 - - - - - INTFLAG - DEVICE Device Interrupt Flag - 0x1C - 16 - 0x0000 - - - SUSPEND - Suspend - 0 - 1 - - - MSOF - Micro Start of Frame in High Speed Mode - 1 - 1 - - - SOF - Start Of Frame - 2 - 1 - - - EORST - End of Reset - 3 - 1 - - - WAKEUP - Wake Up - 4 - 1 - - - EORSM - End Of Resume - 5 - 1 - - - UPRSM - Upstream Resume - 6 - 1 - - - RAMACER - Ram Access - 7 - 1 - - - LPMNYET - Link Power Management Not Yet - 8 - 1 - - - LPMSUSP - Link Power Management Suspend - 9 - 1 - - - - - EPINTSMRY - DEVICE End Point Interrupt Summary - 0x20 - 16 - read-only - 0x0000 - - - EPINT0 - End Point 0 Interrupt - 0 - 1 - - - EPINT1 - End Point 1 Interrupt - 1 - 1 - - - EPINT2 - End Point 2 Interrupt - 2 - 1 - - - EPINT3 - End Point 3 Interrupt - 3 - 1 - - - EPINT4 - End Point 4 Interrupt - 4 - 1 - - - EPINT5 - End Point 5 Interrupt - 5 - 1 - - - EPINT6 - End Point 6 Interrupt - 6 - 1 - - - EPINT7 - End Point 7 Interrupt - 7 - 1 - - - - - DESCADD - Descriptor Address - 0x24 - 32 - 0x00000000 - - - DESCADD - Descriptor Address Value - 0 - 32 - - - - - PADCAL - USB PAD Calibration - 0x28 - 16 - 0x0000 - - - TRANSP - USB Pad Transp calibration - 0 - 5 - - - TRANSN - USB Pad Transn calibration - 6 - 5 - - - TRIM - USB Pad Trim calibration - 12 - 3 - - - - - 8 - 0x20 - DEVICE_ENDPOINT[%s] - - 0x100 - - EPCFG - DEVICE_ENDPOINT End Point Configuration - 0x0 - 8 - 0x00 - - - EPTYPE0 - End Point Type0 - 0 - 3 - - - EPTYPE1 - End Point Type1 - 4 - 3 - - - NYETDIS - NYET Token Disable - 7 - 1 - - - - - EPSTATUSCLR - DEVICE_ENDPOINT End Point Pipe Status Clear - 0x4 - 8 - write-only - 0x00 - - - DTGLOUT - Data Toggle OUT Clear - 0 - 1 - - - DTGLIN - Data Toggle IN Clear - 1 - 1 - - - CURBK - Current Bank Clear - 2 - 1 - - - STALLRQ0 - Stall 0 Request Clear - 4 - 1 - - - STALLRQ1 - Stall 1 Request Clear - 5 - 1 - - - BK0RDY - Bank 0 Ready Clear - 6 - 1 - - - BK1RDY - Bank 1 Ready Clear - 7 - 1 - - - - - EPSTATUSSET - DEVICE_ENDPOINT End Point Pipe Status Set - 0x5 - 8 - write-only - 0x00 - - - DTGLOUT - Data Toggle OUT Set - 0 - 1 - - - DTGLIN - Data Toggle IN Set - 1 - 1 - - - CURBK - Current Bank Set - 2 - 1 - - - STALLRQ0 - Stall 0 Request Set - 4 - 1 - - - STALLRQ1 - Stall 1 Request Set - 5 - 1 - - - BK0RDY - Bank 0 Ready Set - 6 - 1 - - - BK1RDY - Bank 1 Ready Set - 7 - 1 - - - - - EPSTATUS - DEVICE_ENDPOINT End Point Pipe Status - 0x6 - 8 - read-only - 0x00 - - - DTGLOUT - Data Toggle Out - 0 - 1 - - - DTGLIN - Data Toggle In - 1 - 1 - - - CURBK - Current Bank - 2 - 1 - - - STALLRQ0 - Stall 0 Request - 4 - 1 - - - STALLRQ1 - Stall 1 Request - 5 - 1 - - - BK0RDY - Bank 0 ready - 6 - 1 - - - BK1RDY - Bank 1 ready - 7 - 1 - - - - - EPINTFLAG - DEVICE_ENDPOINT End Point Interrupt Flag - 0x7 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 - 0 - 1 - - - TRCPT1 - Transfer Complete 1 - 1 - 1 - - - TRFAIL0 - Error Flow 0 - 2 - 1 - - - TRFAIL1 - Error Flow 1 - 3 - 1 - - - RXSTP - Received Setup - 4 - 1 - - - STALL0 - Stall 0 In/out - 5 - 1 - - - STALL1 - Stall 1 In/out - 6 - 1 - - - - - EPINTENCLR - DEVICE_ENDPOINT End Point Interrupt Clear Flag - 0x8 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 Interrupt Disable - 0 - 1 - - - TRCPT1 - Transfer Complete 1 Interrupt Disable - 1 - 1 - - - TRFAIL0 - Error Flow 0 Interrupt Disable - 2 - 1 - - - TRFAIL1 - Error Flow 1 Interrupt Disable - 3 - 1 - - - RXSTP - Received Setup Interrupt Disable - 4 - 1 - - - STALL0 - Stall 0 In/Out Interrupt Disable - 5 - 1 - - - STALL1 - Stall 1 In/Out Interrupt Disable - 6 - 1 - - - - - EPINTENSET - DEVICE_ENDPOINT End Point Interrupt Set Flag - 0x9 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 Interrupt Enable - 0 - 1 - - - TRCPT1 - Transfer Complete 1 Interrupt Enable - 1 - 1 - - - TRFAIL0 - Error Flow 0 Interrupt Enable - 2 - 1 - - - TRFAIL1 - Error Flow 1 Interrupt Enable - 3 - 1 - - - RXSTP - Received Setup Interrupt Enable - 4 - 1 - - - STALL0 - Stall 0 In/out Interrupt enable - 5 - 1 - - - STALL1 - Stall 1 In/out Interrupt enable - 6 - 1 - - - - - - - HOST - USB is Host - DEVICE - UsbHost - 0x0 - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby Mode - 2 - 1 - - - MODE - Operating Mode - 7 - 1 - - MODESelect - - DEVICE - Device Mode - 0 - - - HOST - Host Mode - 1 - - - - - - - SYNCBUSY - Synchronization Busy - 0x2 - 8 - read-only - 0x00 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - - - QOSCTRL - USB Quality Of Service - 0x3 - 8 - 0x0F - - - CQOS - Configuration Quality of Service - 0 - 2 - - - DQOS - Data Quality of Service - 2 - 2 - - - - - CTRLB - HOST Control B - 0x8 - 16 - 0x0000 - - - RESUME - Send USB Resume - 1 - 1 - - - SPDCONF - Speed Configuration for Host - 2 - 2 - - SPDCONFSelect - - NORMAL - Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. - 0x0 - - - FS - Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. - 0x3 - - - - - AUTORESUME - Auto Resume Enable - 4 - 1 - - - TSTJ - Test mode J - 5 - 1 - - - TSTK - Test mode K - 6 - 1 - - - SOFE - Start of Frame Generation Enable - 8 - 1 - - - BUSRESET - Send USB Reset - 9 - 1 - - - VBUSOK - VBUS is OK - 10 - 1 - - - L1RESUME - Send L1 Resume - 11 - 1 - - - - - HSOFC - HOST Host Start Of Frame Control - 0xA - 8 - 0x00 - - - FLENC - Frame Length Control - 0 - 4 - - - FLENCE - Frame Length Control Enable - 7 - 1 - - - - - STATUS - HOST Status - 0xC - 8 - 0x00 - - - SPEED - Speed Status - 2 - 2 - - - LINESTATE - USB Line State Status - 6 - 2 - - - - - FSMSTATUS - Finite State Machine Status - 0xD - 8 - read-only - 0x01 - - - FSMSTATE - Fine State Machine Status - 0 - 7 - - FSMSTATESelect - - OFF - OFF (L3). It corresponds to the powered-off, disconnected, and disabled state - 0x1 - - - ON - ON (L0). It corresponds to the Idle and Active states - 0x2 - - - SUSPEND - SUSPEND (L2) - 0x4 - - - SLEEP - SLEEP (L1) - 0x8 - - - DNRESUME - DNRESUME. Down Stream Resume. - 0x10 - - - UPRESUME - UPRESUME. Up Stream Resume. - 0x20 - - - RESET - RESET. USB lines Reset. - 0x40 - - - - - - - FNUM - HOST Host Frame Number - 0x10 - 16 - 0x0000 - - - MFNUM - Micro Frame Number - 0 - 3 - - - FNUM - Frame Number - 3 - 11 - - - - - FLENHIGH - HOST Host Frame Length - 0x12 - 8 - read-only - 0x00 - - - FLENHIGH - Frame Length - 0 - 8 - - - - - INTENCLR - HOST Host Interrupt Enable Clear - 0x14 - 16 - 0x0000 - - - HSOF - Host Start Of Frame Interrupt Disable - 2 - 1 - - - RST - BUS Reset Interrupt Disable - 3 - 1 - - - WAKEUP - Wake Up Interrupt Disable - 4 - 1 - - - DNRSM - DownStream to Device Interrupt Disable - 5 - 1 - - - UPRSM - Upstream Resume from Device Interrupt Disable - 6 - 1 - - - RAMACER - Ram Access Interrupt Disable - 7 - 1 - - - DCONN - Device Connection Interrupt Disable - 8 - 1 - - - DDISC - Device Disconnection Interrupt Disable - 9 - 1 - - - - - INTENSET - HOST Host Interrupt Enable Set - 0x18 - 16 - 0x0000 - - - HSOF - Host Start Of Frame Interrupt Enable - 2 - 1 - - - RST - Bus Reset Interrupt Enable - 3 - 1 - - - WAKEUP - Wake Up Interrupt Enable - 4 - 1 - - - DNRSM - DownStream to the Device Interrupt Enable - 5 - 1 - - - UPRSM - Upstream Resume fromthe device Interrupt Enable - 6 - 1 - - - RAMACER - Ram Access Interrupt Enable - 7 - 1 - - - DCONN - Link Power Management Interrupt Enable - 8 - 1 - - - DDISC - Device Disconnection Interrupt Enable - 9 - 1 - - - - - INTFLAG - HOST Host Interrupt Flag - 0x1C - 16 - 0x0000 - - - HSOF - Host Start Of Frame - 2 - 1 - - - RST - Bus Reset - 3 - 1 - - - WAKEUP - Wake Up - 4 - 1 - - - DNRSM - Downstream - 5 - 1 - - - UPRSM - Upstream Resume from the Device - 6 - 1 - - - RAMACER - Ram Access - 7 - 1 - - - DCONN - Device Connection - 8 - 1 - - - DDISC - Device Disconnection - 9 - 1 - - - - - PINTSMRY - HOST Pipe Interrupt Summary - 0x20 - 16 - read-only - 0x0000 - - - EPINT0 - Pipe 0 Interrupt - 0 - 1 - - - EPINT1 - Pipe 1 Interrupt - 1 - 1 - - - EPINT2 - Pipe 2 Interrupt - 2 - 1 - - - EPINT3 - Pipe 3 Interrupt - 3 - 1 - - - EPINT4 - Pipe 4 Interrupt - 4 - 1 - - - EPINT5 - Pipe 5 Interrupt - 5 - 1 - - - EPINT6 - Pipe 6 Interrupt - 6 - 1 - - - EPINT7 - Pipe 7 Interrupt - 7 - 1 - - - - - DESCADD - Descriptor Address - 0x24 - 32 - 0x00000000 - - - DESCADD - Descriptor Address Value - 0 - 32 - - - - - PADCAL - USB PAD Calibration - 0x28 - 16 - 0x0000 - - - TRANSP - USB Pad Transp calibration - 0 - 5 - - - TRANSN - USB Pad Transn calibration - 6 - 5 - - - TRIM - USB Pad Trim calibration - 12 - 3 - - - - - 8 - 0x20 - HOST_PIPE[%s] - - 0x100 - - PCFG - HOST_PIPE End Point Configuration - 0x0 - 8 - 0x00 - - - PTOKEN - Pipe Token - 0 - 2 - - - BK - Pipe Bank - 2 - 1 - - - PTYPE - Pipe Type - 3 - 3 - - - - - BINTERVAL - HOST_PIPE Bus Access Period of Pipe - 0x3 - 8 - 0x00 - - - BITINTERVAL - Bit Interval - 0 - 8 - - - - - PSTATUSCLR - HOST_PIPE End Point Pipe Status Clear - 0x4 - 8 - write-only - 0x00 - - - DTGL - Data Toggle clear - 0 - 1 - - - CURBK - Curren Bank clear - 2 - 1 - - - PFREEZE - Pipe Freeze Clear - 4 - 1 - - - BK0RDY - Bank 0 Ready Clear - 6 - 1 - - - BK1RDY - Bank 1 Ready Clear - 7 - 1 - - - - - PSTATUSSET - HOST_PIPE End Point Pipe Status Set - 0x5 - 8 - write-only - 0x00 - - - DTGL - Data Toggle Set - 0 - 1 - - - CURBK - Current Bank Set - 2 - 1 - - - PFREEZE - Pipe Freeze Set - 4 - 1 - - - BK0RDY - Bank 0 Ready Set - 6 - 1 - - - BK1RDY - Bank 1 Ready Set - 7 - 1 - - - - - PSTATUS - HOST_PIPE End Point Pipe Status - 0x6 - 8 - read-only - 0x00 - - - DTGL - Data Toggle - 0 - 1 - - - CURBK - Current Bank - 2 - 1 - - - PFREEZE - Pipe Freeze - 4 - 1 - - - BK0RDY - Bank 0 ready - 6 - 1 - - - BK1RDY - Bank 1 ready - 7 - 1 - - - - - PINTFLAG - HOST_PIPE Pipe Interrupt Flag - 0x7 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 Interrupt Flag - 0 - 1 - - - TRCPT1 - Transfer Complete 1 Interrupt Flag - 1 - 1 - - - TRFAIL - Error Flow Interrupt Flag - 2 - 1 - - - PERR - Pipe Error Interrupt Flag - 3 - 1 - - - TXSTP - Transmit Setup Interrupt Flag - 4 - 1 - - - STALL - Stall Interrupt Flag - 5 - 1 - - - - - PINTENCLR - HOST_PIPE Pipe Interrupt Flag Clear - 0x8 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 Disable - 0 - 1 - - - TRCPT1 - Transfer Complete 1 Disable - 1 - 1 - - - TRFAIL - Error Flow Interrupt Disable - 2 - 1 - - - PERR - Pipe Error Interrupt Disable - 3 - 1 - - - TXSTP - Transmit Setup Interrupt Disable - 4 - 1 - - - STALL - Stall Inetrrupt Disable - 5 - 1 - - - - - PINTENSET - HOST_PIPE Pipe Interrupt Flag Set - 0x9 - 8 - 0x00 - - - TRCPT0 - Transfer Complete 0 Interrupt Enable - 0 - 1 - - - TRCPT1 - Transfer Complete 1 Interrupt Enable - 1 - 1 - - - TRFAIL - Error Flow Interrupt Enable - 2 - 1 - - - PERR - Pipe Error Interrupt Enable - 3 - 1 - - - TXSTP - Transmit Setup Interrupt Enable - 4 - 1 - - - STALL - Stall Interrupt Enable - 5 - 1 - - - - - - - - - WDT - U22511.1.0 - Watchdog Timer - WDT - WDT_ - 0x40002000 - - 0 - 0xD - registers - - - WDT - 10 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - ENABLE - Enable - 1 - 1 - - - WEN - Watchdog Timer Window Mode Enable - 2 - 1 - - - ALWAYSON - Always-On - 7 - 1 - - - - - CONFIG - Configuration - 0x1 - 8 - 0xBB - - - PER - Time-Out Period - 0 - 4 - - PERSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - WINDOW - Window Mode Time-Out Period - 4 - 4 - - WINDOWSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - EWCTRL - Early Warning Interrupt Control - 0x2 - 8 - 0x0B - - - EWOFFSET - Early Warning Interrupt Time Offset - 0 - 4 - - EWOFFSETSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - EW - Early Warning - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - WEN - Window Enable Synchronization Busy - 2 - 1 - - - ALWAYSON - Always-On Synchronization Busy - 3 - 1 - - - CLEAR - Clear Synchronization Busy - 4 - 1 - - - - - CLEAR - Clear - 0xC - 8 - write-only - 0x00 - - - CLEAR - Watchdog Clear - 0 - 8 - - CLEARSelect - - KEY - Clear Key - 0xA5 - - - - - - - - - CoreDebug - Core Debug Register - CoreDebug - CoreDebug_ - 0xE000EDF0 - - 0 - 0x10 - registers - - - - DHCSR - Debug Halting Control and Status Register - 0x0 - 32 - - - C_DEBUGEN - 0 - 1 - - - C_HALT - 1 - 1 - - - C_STEP - 2 - 1 - - - C_MASKINTS - 3 - 1 - - - C_SNAPSTALL - 5 - 1 - - - S_REGRDY - 16 - 1 - read-only - - - S_HALT - 17 - 1 - read-only - - - S_SLEEP - 18 - 1 - read-only - - - S_LOCKUP - 19 - 1 - read-only - - - S_RETIRE_ST - 24 - 1 - read-only - - - S_RESET_ST - 25 - 1 - read-only - - - DBGKEY - 16 - 16 - write-only - - - - - DCRSR - Debug Core Register Selector Register - 0x4 - 32 - write-only - - - REGSEL - 0 - 5 - - - REGWnR - 16 - 1 - - - - - DCRDR - Debug Core Register Data Register - 0x8 - 32 - - - DEMCR - Debug Exception and Monitor Control Register - 0xC - 32 - - - VC_CORERESET - 0 - 1 - - - VC_MMERR - 4 - 1 - - - VC_NOCPERR - 5 - 1 - - - VC_CHKERR - 6 - 1 - - - VC_STATERR - 7 - 1 - - - VC_BUSERR - 8 - 1 - - - VC_INTERR - 9 - 1 - - - VC_HARDERR - 10 - 1 - - - MON_EN - 16 - 1 - - - MON_PEND - 17 - 1 - - - MON_STEP - 18 - 1 - - - MON_REQ - 19 - 1 - - - TRCENA - 24 - 1 - - - - - - - DWT - Data Watchpoint and Trace Register - DWT - DWT_ - 0xE0001000 - - 0 - 0x5C - registers - - - - CTRL - Control Register - 0x0 - 32 - - - CYCCNTENA - 0 - 1 - - - POSTPRESET - 1 - 4 - - - POSTINIT - 5 - 4 - - - CYCTAP - 9 - 1 - - - SYNCTAP - 10 - 2 - - - PCSAMPLENA - 12 - 1 - - - EXCTRCENA - 16 - 1 - - - CPIEVTENA - 17 - 1 - - - EXCEVTENA - 18 - 1 - - - SLEEPEVTENA - 19 - 1 - - - LSUEVTENA - 20 - 1 - - - FOLDEVTENA - 21 - 1 - - - CYCEVTENA - 22 - 1 - - - NOPRFCNT - 24 - 1 - - - NOCYCCNT - 25 - 1 - - - NOEXTTRIG - 26 - 1 - - - NOTRCPKT - 27 - 1 - - - NUMCOMP - 28 - 4 - - - - - CYCCNT - Cycle Count Register - 0x4 - 32 - - - CPICNT - CPI Count Register - 0x8 - 32 - - - CPICNT - 0 - 8 - - - - - EXCCNT - Exception Overhead Count Register - 0xC - 32 - - - EXCCNT - 0 - 8 - - - - - SLEEPCNT - Sleep Count Register - 0x10 - 32 - - - SLEEPCNT - 0 - 8 - - - - - LSUCNT - LSU Count Register - 0x14 - 32 - - - LSUCNT - 0 - 8 - - - - - FOLDCNT - Folded-instruction Count Register - 0x18 - 32 - - - FOLDCNT - 0 - 8 - - - - - PCSR - Program Counter Sample Register - 0x1C - 32 - read-only - - - COMP0 - Comparator Register 0 - 0x20 - 32 - - - MASK0 - Mask Register 0 - 0x24 - 32 - - - MASK - 0 - 5 - - - - - FUNCTION0 - Function Register 0 - 0x28 - 32 - - - FUNCTION - 0 - 4 - - - EMITRANGE - 5 - 1 - - - CYCMATCH - 7 - 1 - - - DATAVMATCH - 8 - 1 - - - LNK1ENA - 9 - 1 - - - DATAVSIZE - 10 - 2 - - - DATAVADDR0 - 12 - 4 - - - DATAVADDR1 - 16 - 4 - - - MATCHED - 24 - 1 - - - - - COMP1 - Comparator Register 1 - 0x30 - 32 - - - MASK1 - Mask Register 1 - 0x34 - 32 - - - MASK - 0 - 5 - - - - - FUNCTION1 - Function Register 1 - 0x38 - 32 - - - FUNCTION - 0 - 4 - - - EMITRANGE - 5 - 1 - - - CYCMATCH - 7 - 1 - - - DATAVMATCH - 8 - 1 - - - LNK1ENA - 9 - 1 - - - DATAVSIZE - 10 - 2 - - - DATAVADDR0 - 12 - 4 - - - DATAVADDR1 - 16 - 4 - - - MATCHED - 24 - 1 - - - - - COMP2 - Comparator Register 2 - 0x40 - 32 - - - MASK2 - Mask Register 2 - 0x44 - 32 - - - MASK - 0 - 5 - - - - - FUNCTION2 - Function Register 2 - 0x48 - 32 - - - FUNCTION - 0 - 4 - - - EMITRANGE - 5 - 1 - - - CYCMATCH - 7 - 1 - - - DATAVMATCH - 8 - 1 - - - LNK1ENA - 9 - 1 - - - DATAVSIZE - 10 - 2 - - - DATAVADDR0 - 12 - 4 - - - DATAVADDR1 - 16 - 4 - - - MATCHED - 24 - 1 - - - - - COMP3 - Comparator Register 3 - 0x50 - 32 - - - MASK3 - Mask Register 3 - 0x54 - 32 - - - MASK - 0 - 5 - - - - - FUNCTION3 - Function Register 3 - 0x58 - 32 - - - FUNCTION - 0 - 4 - - - EMITRANGE - 5 - 1 - - - CYCMATCH - 7 - 1 - - - DATAVMATCH - 8 - 1 - - - LNK1ENA - 9 - 1 - - - DATAVSIZE - 10 - 2 - - - DATAVADDR0 - 12 - 4 - - - DATAVADDR1 - 16 - 4 - - - MATCHED - 24 - 1 - - - - - - - ETM - Embedded Trace Macrocell - ETM - ETM_ - 0xE0041000 - - 0 - 0x1000 - registers - - - - CR - ETM Main Control Register - 0x0 - 32 - 0x00000411 - - - ETMPD - ETM Power Down - 0 - 1 - - - PORTSIZE - Port Size bits 2:0 - 4 - 3 - - - STALL - Stall Processor - 7 - 1 - - - BROUT - Branch Output - 8 - 1 - - - DBGRQ - Debug Request Control - 9 - 1 - - - PROG - ETM Programming - 10 - 1 - - - PORTSEL - ETM Port Select - 11 - 1 - - - PORTMODE2 - Port Mode bit 2 - 13 - 1 - - - PORTMODE - Port Mode bits 1:0 - 16 - 2 - - - PORTSIZE3 - Port Size bit 3 - 21 - 1 - - - TSEN - TimeStamp Enable - 28 - 1 - - - - - CCR - ETM Configuration Code Register - 0x4 - 32 - read-only - 0x8C802000 - - - TRIGGER - ETM Trigger Event Register - 0x8 - 32 - - - SR - ETM Status Register - 0x10 - 32 - - - SCR - ETM System Configuration Register - 0x14 - 32 - read-only - 0x00020D09 - - - TEEVR - ETM TraceEnable Event Register - 0x20 - 32 - - - TECR1 - ETM TraceEnable Control 1 Register - 0x24 - 32 - - - FFLR - ETM FIFO Full Level Register - 0x28 - 32 - - - CNTRLDVR1 - ETM Free-running Counter Reload Value - 0x140 - 32 - - - SYNCFR - ETM Synchronization Frequency Register - 0x1E0 - 32 - read-only - 0x00000400 - - - IDR - ETM ID Register - 0x1E4 - 32 - read-only - 0x4114F250 - - - CCER - ETM Configuration Code Extension Register - 0x1E8 - 32 - read-only - 0x18541800 - - - TESSEICR - ETM TraceEnable Start/Stop EmbeddedICE Control Register - 0x1F0 - 32 - - - TSEVT - ETM TimeStamp Event Register - 0x1F8 - 32 - - - TRACEIDR - ETM CoreSight Trace ID Register - 0x200 - 32 - 0x00000000 - - - IDR2 - ETM ID Register 2 - 0x208 - 32 - read-only - 0x00000000 - - - PDSR - ETM Device Power-Down Status Register - 0x314 - 32 - read-only - 0x00000001 - - - ITMISCIN - ETM Integration Test Miscellaneous Inputs - 0xEE0 - 32 - read-only - - - ITTRIGOUT - ETM Integration Test Trigger Out - 0xEE8 - 32 - write-only - - - ITATBCTR2 - ETM Integration Test ATB Control 2 - 0xEF0 - 32 - read-only - - - ITATBCTR0 - ETM Integration Test ATB Control 0 - 0xEF8 - 32 - write-only - - - ITCTRL - ETM Integration Mode Control Register - 0xF00 - 32 - 0x00000000 - - - INTEGRATION - 0 - 1 - - - - - CLAIMSET - ETM Claim Tag Set Register - 0xFA0 - 32 - - - CLAIMCLR - ETM Claim Tag Clear Register - 0xFA4 - 32 - - - LAR - ETM Lock Access Register - 0xFB0 - 32 - write-only - - - LSR - ETM Lock Status Register - 0xFB4 - 32 - read-only - - - Present - 0 - 1 - - - Access - 1 - 1 - - - ByteAcc - 2 - 1 - - - - - AUTHSTATUS - ETM Authentication Status Register - 0xFB8 - 32 - read-only - - - DEVTYPE - ETM CoreSight Device Type Register - 0xFCC - 32 - read-only - 0x00000013 - - - PIDR4 - ETM Peripheral Identification Register #4 - 0xFD0 - 32 - read-only - 0x00000004 - - - PIDR5 - ETM Peripheral Identification Register #5 - 0xFD4 - 32 - read-only - 0x00000000 - - - PIDR6 - ETM Peripheral Identification Register #6 - 0xFD8 - 32 - read-only - 0x00000000 - - - PIDR7 - ETM Peripheral Identification Register #7 - 0xFDC - 32 - read-only - 0x00000000 - - - PIDR0 - ETM Peripheral Identification Register #0 - 0xFE0 - 32 - read-only - 0x00000025 - - - PIDR1 - ETM Peripheral Identification Register #1 - 0xFE4 - 32 - read-only - 0x000000B9 - - - PIDR2 - ETM Peripheral Identification Register #2 - 0xFE8 - 32 - read-only - 0x0000000B - - - PIDR3 - ETM Peripheral Identification Register #3 - 0xFEC - 32 - read-only - 0x00000000 - - - CIDR0 - ETM Component Identification Register #0 - 0xFF0 - 32 - read-only - 0x0000000D - - - CIDR1 - ETM Component Identification Register #1 - 0xFF4 - 32 - read-only - 0x00000090 - - - CIDR2 - ETM Component Identification Register #2 - 0xFF8 - 32 - read-only - 0x00000005 - - - CIDR3 - ETM Component Identification Register #3 - 0xFFC - 32 - read-only - 0x000000B1 - - - - - FPU - Floating Point Unit - FPU - FPU_ - 0xE000EF30 - - 0 - 0x18 - registers - - - - FPCCR - Floating-Point Context Control Register - 0x4 - 32 - 0xC0000000 - - - LSPACT - 0 - 1 - - - USER - 1 - 1 - - - THREAD - 3 - 1 - - - HFRDY - 4 - 1 - - - MMRDY - 5 - 1 - - - BFRDY - 6 - 1 - - - MONRDY - 8 - 1 - - - LSPEN - 30 - 1 - - - ASPEN - 31 - 1 - - - - - FPCAR - Floating-Point Context Address Register - 0x8 - 32 - - - ADDRESS - Address for FP registers in exception stack frame - 3 - 29 - - - - - FPDSCR - Floating-Point Default Status Control Register - 0xC - 32 - 0x00000000 - - - RMODE - Default value for FPSCR.RMODE - 22 - 2 - - RMODESelect - - RN - Round to Nearest - 0x0 - - - RP - Round towards Positive Infinity - 0x1 - - - RM - Round towards Negative Infinity - 0x2 - - - RZ - Round towards Zero - 0x3 - - - - - FZ - Default value for FPSCR.FZ - 24 - 1 - - - DN - Default value for FPSCR.DN - 25 - 1 - - - AHP - Default value for FPSCR.AHP - 26 - 1 - - - - - MVFR0 - Media and FP Feature Register 0 - 0x10 - 32 - read-only - - - A_SIMD_registers - 0 - 4 - - - Single_precision - 4 - 4 - - - Double_precision - 8 - 4 - - - FP_excep_trapping - 12 - 4 - - - Divide - 16 - 4 - - - Square_root - 20 - 4 - - - Short_vectors - 24 - 4 - - - FP_rounding_modes - 28 - 4 - - - - - MVFR1 - Media and FP Feature Register 1 - 0x14 - 32 - read-only - - - FtZ_mode - 0 - 4 - - - D_NaN_mode - 4 - 4 - - - FP_HPFP - 24 - 4 - - - FP_fused_MAC - 28 - 4 - - - - - - - ITM - Instrumentation Trace Macrocell - ITM - ITM_ - 0xE0000000 - - 0 - 0xF00 - registers - - - - 32 - 4 - PORT_WORD_MODE[%s] - ITM Stimulus Port Registers - 0x0 - 32 - write-only - - - PORT - 0 - 32 - - - - - 32 - 4 - PORT_BYTE_MODE[%s] - ITM Stimulus Port Registers - PORT_WORD_MODE[%s] - 0x0 - 32 - write-only - - - PORT - 0 - 8 - - - - - 32 - 4 - PORT_HWORD_MODE[%s] - ITM Stimulus Port Registers - PORT_WORD_MODE[%s] - 0x0 - 32 - write-only - - - PORT - 0 - 16 - - - - - TER - ITM Trace Enable Register - 0xE00 - 32 - - - TPR - ITM Trace Privilege Register - 0xE40 - 32 - - - PRIVMASK - 0 - 4 - - - - - TCR - ITM Trace Control Register - 0xE80 - 32 - - - ITMENA - 0 - 1 - - - TSENA - 1 - 1 - - - SYNCENA - 2 - 1 - - - DWTENA - 3 - 1 - - - SWOENA - 4 - 1 - - - STALLENA - 5 - 1 - - - TSPrescale - 8 - 2 - - - GTSFREQ - 10 - 2 - - - TraceBusID - 16 - 7 - - - BUSY - 23 - 1 - - - - - IWR - ITM Integration Write Register - 0xEF8 - 32 - write-only - - - ATVALIDM - 0 - 1 - - - - - IRR - ITM Integration Read Register - 0xEFC - 32 - read-only - - - ATREADYM - 0 - 1 - - - - - - - MPU - Memory Protection Unit - MPU - MPU_ - 0xE000ED90 - - 0 - 0x2C - registers - - - - TYPE - MPU Type Register - 0x0 - 32 - read-only - - - SEPARATE - Separate instruction and Data Memory MapsRegions - 0 - 1 - - - DREGION - Number of Data Regions - 8 - 8 - - - IREGION - Number of Instruction Regions - 16 - 8 - - - - - CTRL - MPU Control Register - 0x4 - 32 - - - ENABLE - MPU Enable - 0 - 1 - - - HFNMIENA - Enable Hard Fault and NMI handlers - 1 - 1 - - - PRIVDEFENA - Enables privileged software access to default memory map - 2 - 1 - - - - - RNR - MPU Region Number Register - 0x8 - 32 - - - REGION - Region referenced by RBAR and RASR - 0 - 8 - - - - - RBAR - MPU Region Base Address Register - 0xC - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR - MPU Region Attribute and Size Register - 0x10 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 1 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - RBAR_A1 - MPU Alias 1 Region Base Address Register - 0x14 - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR_A1 - MPU Alias 1 Region Attribute and Size Register - 0x18 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 1 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - RBAR_A2 - MPU Alias 2 Region Base Address Register - 0x1C - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR_A2 - MPU Alias 2 Region Attribute and Size Register - 0x20 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 1 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - RBAR_A3 - MPU Alias 3 Region Base Address Register - 0x24 - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR_A3 - MPU Alias 3 Region Attribute and Size Register - 0x28 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 1 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - - - NVIC - Nested Vectored Interrupt Controller - NVIC - NVIC_ - 0xE000E100 - - 0 - 0xE04 - registers - - - - 5 - 4 - ISER[%s] - Interrupt Set Enable Register - 0x0 - 32 - 0 - - - SETENA - Interrupt set enable bits - 0 - 32 - - - - - 5 - 4 - ICER[%s] - Interrupt Clear Enable Register - 0x80 - 32 - 0 - - - CLRENA - Interrupt clear-enable bits - 0 - 32 - - - - - 5 - 4 - ISPR[%s] - Interrupt Set Pending Register - 0x100 - 32 - 0 - - - SETPEND - Interrupt set-pending bits - 0 - 32 - - - - - 5 - 4 - ICPR[%s] - Interrupt Clear Pending Register - 0x180 - 32 - 0 - - - CLRPEND - Interrupt clear-pending bits - 0 - 32 - - - - - 5 - 4 - IABR[%s] - Interrupt Active Bit Register - 0x200 - 32 - 0 - - - ACTIVE - Interrupt active bits - 0 - 32 - - - - - 35 - 1 - IP[%s] - Interrupt Priority Register n - 0x300 - 8 - 0 - - - PRI0 - Priority of interrupt n - 0 - 3 - - - - - STIR - Software Trigger Interrupt Register - 0xE00 - 32 - write-only - - - INTID - Interrupt ID to trigger - 0 - 9 - - - - - - - SysTick - System timer - SysTick - SysTick_ - 0xE000E010 - - 0 - 0x10 - registers - - - - CSR - SysTick Control and Status Register - 0x0 - 32 - 0x4 - - - ENABLE - SysTick Counter Enable - 0 - 1 - - ENABLESelect - - VALUE_0 - Counter disabled - 0 - - - VALUE_1 - Counter enabled - 1 - - - - - TICKINT - SysTick Exception Request Enable - 1 - 1 - - TICKINTSelect - - VALUE_0 - Counting down to 0 does not assert the SysTick exception request - 0 - - - VALUE_1 - Counting down to 0 asserts the SysTick exception request - 1 - - - - - CLKSOURCE - Clock Source 0=external, 1=processor - 2 - 1 - - CLKSOURCESelect - - VALUE_0 - External clock - 0 - - - VALUE_1 - Processor clock - 1 - - - - - COUNTFLAG - Timer counted to 0 since last read of register - 16 - 1 - - - - - RVR - SysTick Reload Value Register - 0x4 - 32 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0 - 0 - 24 - - - - - CVR - SysTick Current Value Register - 0x8 - 32 - - - CURRENT - Current value at the time the register is accessed - 0 - 24 - - - - - CALIB - SysTick Calibration Value Register - 0xC - 32 - read-only - 0 - - - TENMS - Reload value to use for 10ms timing - 0 - 24 - - - SKEW - TENMS is rounded from non-integer ratio - 30 - 1 - - SKEWSelect - - VALUE_0 - 10ms calibration value is exact - 0 - - - VALUE_1 - 10ms calibration value is inexact, because of the clock frequency - 1 - - - - - NOREF - No Separate Reference Clock - 31 - 1 - - NOREFSelect - - VALUE_0 - The reference clock is provided - 0 - - - VALUE_1 - The reference clock is not provided - 1 - - - - - - - - - SystemControl - System Control Registers - SystemControl - SystemControl_ - 0xE000E000 - - 0 - 0xD8C - registers - - - - ICTR - Interrupt Controller Type Register - 0x4 - 32 - read-only - - - INTLINESNUM - 0 - 4 - - - - - ACTLR - Auxiliary Control Register - 0x8 - 32 - - - DISMCYCINT - Disable interruption of LDM/STM instructions - 0 - 1 - - - DISDEFWBUF - Disable wruite buffer use during default memory map accesses - 1 - 1 - - - DISFOLD - Disable IT folding - 2 - 1 - - - DISFPCA - Disable automatic update of CONTROL.FPCA - 8 - 1 - - - DISOOFP - Disable out-of-order FP instructions - 9 - 1 - - - - - CPUID - CPUID Base Register - 0xD00 - 32 - read-only - 0x410FC240 - - - REVISION - Processor revision number - 0 - 4 - - - PARTNO - Process Part Number, 0xC24=Cortex-M4 - 4 - 12 - - - CONSTANT - Constant - 16 - 4 - - - VARIANT - Variant number - 20 - 4 - - - IMPLEMENTER - Implementer code, 0x41=ARM - 24 - 8 - - - - - ICSR - Interrupt Control and State Register - 0xD04 - 32 - 0 - - - VECTACTIVE - Active exception number - 0 - 9 - - - RETTOBASE - No preempted active exceptions to execute - 11 - 1 - - - VECTPENDING - Exception number of the highest priority pending enabled exception - 12 - 6 - - - ISRPENDING - Interrupt pending flag - 22 - 1 - - - ISRPREEMPT - Debug only - 23 - 1 - - - PENDSTCLR - SysTick clear-pending bit - 25 - 1 - - PENDSTCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the SysTick exception - 1 - - - - - PENDSTSET - SysTick set-pending bit - 26 - 1 - - PENDSTSETSelect - - VALUE_0 - Write: no effect; read: SysTick exception is not pending - 0 - - - VALUE_1 - Write: changes SysTick exception state to pending; read: SysTick exception is pending - 1 - - - - - PENDSVCLR - PendSV clear-pending bit - 27 - 1 - - PENDSVCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the PendSV exception - 1 - - - - - PENDSVSET - PendSV set-pending bit - 28 - 1 - - PENDSVSETSelect - - VALUE_0 - Write: no effect; read: PendSV exception is not pending - 0 - - - VALUE_1 - Write: changes PendSV exception state to pending; read: PendSV exception is pending - 1 - - - - - NMIPENDSET - NMI set-pending bit - 31 - 1 - - NMIPENDSETSelect - - VALUE_0 - Write: no effect; read: NMI exception is not pending - 0 - - - VALUE_1 - Write: changes NMI exception state to pending; read: NMI exception is pending - 1 - - - - - - - VTOR - Vector Table Offset Register - 0xD08 - 32 - 0x00000000 - - - TBLOFF - Vector table base offset - 7 - 25 - - - - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - 32 - 0xFA050000 - - - VECTRESET - Must write 0 - 0 - 1 - - - VECTCLRACTIVE - Must write 0 - 1 - 1 - - - SYSRESETREQ - System Reset Request - 2 - 1 - - SYSRESETREQSelect - - VALUE_0 - No system reset request - 0 - - - VALUE_1 - Asserts a signal to the outer system that requests a reset - 1 - - - - - PRIGROUP - Interrupt priority grouping - 8 - 3 - - - ENDIANNESS - Data endianness, 0=little, 1=big - 15 - 1 - - ENDIANNESSSelect - - VALUE_0 - Little-endian - 0 - - - VALUE_1 - Big-endian - 1 - - - - - VECTKEY - Register key - 16 - 16 - - - - - SCR - System Control Register - 0xD10 - 32 - 0 - - - SLEEPONEXIT - Sleep-on-exit on handler return - 1 - 1 - - SLEEPONEXITSelect - - VALUE_0 - Do not sleep when returning to Thread mode - 0 - - - VALUE_1 - Enter sleep, or deep sleep, on return from an ISR - 1 - - - - - SLEEPDEEP - Deep Sleep used as low power mode - 2 - 1 - - SLEEPDEEPSelect - - VALUE_0 - Sleep - 0 - - - VALUE_1 - Deep sleep - 1 - - - - - SEVONPEND - Send Event on Pending bit - 4 - 1 - - SEVONPENDSelect - - VALUE_0 - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded - 0 - - - VALUE_1 - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 1 - - - - - - - CCR - Configuration and Control Register - 0xD14 - 32 - 0x00000200 - - - NONBASETHRDENA - Indicates how processor enters Thread mode - 0 - 1 - - - USERSETMPEND - Enables unprivileged software access to STIR register - 1 - 1 - - - UNALIGN_TRP - Enables unaligned access traps - 3 - 1 - - UNALIGN_TRPSelect - - VALUE_0 - Do not trap unaligned halfword and word accesses - 0 - - - VALUE_1 - Trap unaligned halfword and word accesses - 1 - - - - - DIV_0_TRP - Enables divide by 0 trap - 4 - 1 - - - BFHFNMIGN - Ignore LDM/STM BusFault for -1/-2 priority handlers - 8 - 1 - - - STKALIGN - Indicates stack alignment on exception entry - 9 - 1 - - STKALIGNSelect - - VALUE_0 - 4-byte aligned - 0 - - - VALUE_1 - 8-byte aligned - 1 - - - - - - - SHPR1 - System Handler Priority Register 1 - 0xD18 - 32 - - - PRI_4 - Priority of system handler 4, MemManage - 0 - 8 - - - PRI_5 - Priority of system handler 5, BusFault - 8 - 8 - - - PRI_6 - Priority of system handler 6, UsageFault - 16 - 8 - - - - - SHPR2 - System Handler Priority Register 2 - 0xD1C - 32 - 0 - - - PRI_11 - Priority of system handler 11, SVCall - 24 - 8 - - - - - SHPR3 - System Handler Priority Register 3 - 0xD20 - 32 - 0 - - - PRI_14 - Priority of system handler 14, PendSV - 16 - 8 - - - PRI_15 - Priority of system handler 15, SysTick exception - 24 - 8 - - - - - SHCSR - System Handler Control and State Register - 0xD24 - 32 - - - MEMFAULTACT - MemManage exception active bit - 0 - 1 - - - BUSFAULTACT - BusFault exception active bit - 1 - 1 - - - USGFAULTACT - UsageFault exception active bit - 3 - 1 - - - SVCALLACT - SVCall active bit - 7 - 1 - - - MONITORACT - DebugMonitor exception active bit - 8 - 1 - - - PENDSVACT - PendSV exception active bit - 10 - 1 - - - SYSTICKACT - SysTick exception active bit - 11 - 1 - - - USGFAULTPENDED - UsageFault exception pending bit - 12 - 1 - - - MEMFAULTPENDED - MemManage exception pending bit - 13 - 1 - - - BUSFAULTPENDED - BusFault exception pending bit - 14 - 1 - - - SVCALLPENDED - SVCall pending bit - 15 - 1 - - - MEMFAULTENA - MemManage enable bit - 16 - 1 - - - BUSFAULTENA - BusFault enable bit - 17 - 1 - - - USGFAULTENA - UsageFault enable bit - 18 - 1 - - - - - CFSR - Configurable Fault Status Register - 0xD28 - 32 - - - IACCVIOL - Instruction access violation - 0 - 1 - - - DACCVIOL - Data access violation - 1 - 1 - - - MUNSTKERR - MemManage Fault on unstacking for exception return - 3 - 1 - - - MSTKERR - MemManage Fault on stacking for exception entry - 4 - 1 - - - MLSPERR - MemManager Fault occured during FP lazy state preservation - 5 - 1 - - - MMARVALID - MemManage Fault Address Register valid - 7 - 1 - - - IBUSERR - Instruction bus error - 8 - 1 - - - PRECISERR - Precise data bus error - 9 - 1 - - - IMPRECISERR - Imprecise data bus error - 10 - 1 - - - UNSTKERR - BusFault on unstacking for exception return - 11 - 1 - - - STKERR - BusFault on stacking for exception entry - 12 - 1 - - - LSPERR - BusFault occured during FP lazy state preservation - 13 - 1 - - - BFARVALID - BusFault Address Register valid - 15 - 1 - - - UNDEFINSTR - Undefined instruction UsageFault - 16 - 1 - - - INVSTATE - Invalid state UsageFault - 17 - 1 - - - INVPC - Invalid PC load UsageFault - 18 - 1 - - - NOCP - No coprocessor UsageFault - 19 - 1 - - - UNALIGNED - Unaligned access UsageFault - 24 - 1 - - - DIVBYZERO - Divide by zero UsageFault - 25 - 1 - - - - - HFSR - HardFault Status Register - 0xD2C - 32 - - - VECTTBL - BusFault on a Vector Table read during exception processing - 1 - 1 - - - FORCED - Forced Hard Fault - 30 - 1 - - - DEBUGEVT - Debug: always write 0 - 31 - 1 - - - - - DFSR - Debug Fault Status Register - 0xD30 - 32 - - - HALTED - 0 - 1 - - - BKPT - 1 - 1 - - - DWTTRAP - 2 - 1 - - - VCATCH - 3 - 1 - - - EXTERNAL - 4 - 1 - - - - - MMFAR - MemManage Fault Address Register - 0xD34 - 32 - - - ADDRESS - Address that generated the MemManage fault - 0 - 32 - - - - - BFAR - BusFault Address Register - 0xD38 - 32 - - - ADDRESS - Address that generated the BusFault - 0 - 32 - - - - - AFSR - Auxiliary Fault Status Register - 0xD3C - 32 - - - IMPDEF - AUXFAULT input signals - 0 - 32 - - - - - 2 - 4 - PFR[%s] - Processor Feature Register - 0xD40 - 32 - - - DFR - Debug Feature Register - 0xD48 - 32 - read-only - - - ADR - Auxiliary Feature Register - 0xD4C - 32 - read-only - - - 4 - 4 - MMFR[%s] - Memory Model Feature Register - 0xD50 - 32 - read-only - - - 5 - 4 - ISAR[%s] - Instruction Set Attributes Register - 0xD60 - 32 - read-only - - - CPACR - Coprocessor Access Control Register - 0xD88 - 32 - - - CP10 - Access privileges for coprocessor 10 - 20 - 2 - - CP10Select - - DENIED - Access denied - 0x0 - - - PRIV - Privileged access only - 0x1 - - - FULL - Full access - 0x3 - - - - - CP11 - Access privileges for coprocessor 11 - 22 - 2 - - CP11Select - - DENIED - Access denied - 0x0 - - - PRIV - Privileged access only - 0x1 - - - FULL - Full access - 0x3 - - - - - - - - - TPI - Trace Port Interface Register - TPI - TPI_ - 0xE0040000 - - 0 - 0xFD0 - registers - - - - SSPSR - Supported Parallel Port Size Register - 0x0 - 32 - read-only - - - CSPSR - Current Parallel Port Size Register - 0x4 - 32 - - - ACPR - Asynchronous Clock Prescaler Register - 0x10 - 32 - - - PRESCALER - 0 - 13 - - - - - SPPR - Selected Pin Protocol Register - 0xF0 - 32 - - - TXMODE - 0 - 2 - - - - - FFSR - Formatter and Flush Status Register - 0x300 - 32 - read-only - - - FlInProg - 0 - 1 - - - FtStopped - 1 - 1 - - - TCPresent - 2 - 1 - - - FtNonStop - 3 - 1 - - - - - FFCR - Formatter and Flush Control Register - 0x304 - 32 - - - EnFCont - 1 - 1 - - - TrigIn - 8 - 1 - - - - - FSCR - Formatter Synchronization Counter Register - 0x308 - 32 - read-only - - - TRIGGER - TRIGGER - 0xEE8 - 32 - read-only - - - TRIGGER - 0 - 1 - - - - - FIFO0 - Integration ETM Data - 0xEEC - 32 - read-only - - - ETM0 - 0 - 8 - - - ETM1 - 8 - 8 - - - ETM2 - 16 - 8 - - - ETM_bytecount - 24 - 2 - - - ETM_ATVALID - 26 - 1 - - - ITM_bytecount - 27 - 2 - - - ITM_ATVALID - 29 - 1 - - - - - ITATBCTR2 - ITATBCTR2 - 0xEF0 - 32 - read-only - - - ATREADY - 0 - 1 - - - - - ITATBCTR0 - ITATBCTR0 - 0xEF8 - 32 - read-only - - - ATREADY - 0 - 1 - - - - - FIFO1 - Integration ITM Data - 0xEFC - 32 - read-only - - - ITM0 - 0 - 8 - - - ITM1 - 8 - 8 - - - ITM2 - 16 - 8 - - - ETM_bytecount - 24 - 2 - - - ETM_ATVALID - 26 - 1 - - - ITM_bytecount - 27 - 2 - - - ITM_ATVALID - 29 - 1 - - - - - ITCTRL - Integration Mode Control - 0xF00 - 32 - - - Mode - 0 - 1 - - - - - CLAIMSET - Claim tag set - 0xFA0 - 32 - - - CLAIMCLR - Claim tag clear - 0xFA4 - 32 - - - DEVID - TPIU_DEVID - 0xFC8 - 32 - read-only - - - NrTraceInput - 0 - 1 - - - AsynClkIn - 5 - 1 - - - MinBufSz - 6 - 3 - - - PTINVALID - 9 - 1 - - - MANCVALID - 10 - 1 - - - NRZVALID - 11 - 1 - - - - - DEVTYPE - TPIU_DEVTYPE - 0xFCC - 32 - read-only - - - SubType - 0 - 4 - - - MajorType - 4 - 4 - - - - - - - diff --git a/src/modules/chips/atsame51j20a/atsame51j20a.zig b/src/modules/chips/atsame51j20a/atsame51j20a.zig deleted file mode 100644 index 094644f..0000000 --- a/src/modules/chips/atsame51j20a/atsame51j20a.zig +++ /dev/null @@ -1,333 +0,0 @@ -pub const std = @import("std"); -pub const cpu = @import("cpu"); -pub const micro = @import("microzig"); -pub const chip = @import("registers.zig"); - -const regs = chip.registers; -pub usingnamespace chip; - -pub const chip_name = "ATSAME51J20A"; - -pub const clock_frequencies = .{ - // On any reset the synchronous clocks start to their initial state: - // * DFLL48M is enabled and configured to run at 48 MHz - // * Generic Generator 0 uses DFLL48M as source and generates GCLK_MAIN - // * CPU and BUS clocks are undivided - // i.e. GENCTRL0 = 0x00000106 - .cpu = 48_000_000, -}; - -/// Get access to the pin specified by `spec`. -/// -/// - `spec`: P{port}{pin} -/// - `port`: A, B -/// - `pin`: 0..31 -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec[0] != 'P') - @compileError(invalid_format_msg); - if (spec[1] < 'A' or spec[1] > 'B') // J = 64 Pins; 2 Ports - @compileError("Unknown port '" ++ spec[1..2] ++ "'. Supported ports: A, B."); - - return struct { - // Try to parse the given pin number as u5, i.e. a value in '0'..'31'. - const pin_number: u5 = @import("std").fmt.parseInt(u5, spec[2..], 10) catch @compileError(invalid_format_msg); - const pin_mask: u32 = (1 << pin_number); - // Port is either 'A' or 'B'. - const port_number: usize = if (spec[1] == 'A') 0 else 1; - const gpio_port = @field(regs.PORT, "GROUP"); - }; -} - -pub const gpio = struct { - // See SAM D5x/E5x Family Data Sheet page 807. - - /// Configure the given pin as output with input disabled. - pub fn setOutput(comptime pin: type) void { - // To use pin Pxy as an output, write bit y of the DIR register to '1'. This - // can also be done by writing bit y int the DIRSET register to '1' - this - // will avoid disturbing the configuration of other pins (datasheet p. 803). - pin.gpio_port[pin.port_number].DIRSET = pin.pin_mask; - // Disable input for the given pin. - pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 0 }); - } - - /// Configure the given pin as input. - pub fn setInput(comptime pin: type) void { - // To use pin Pxy as an input, bit y in the DIR register must be written to '0'. - // This can also be done by writing bit y in the DIRCLR register to '1'. - pin.gpio_port[pin.port_number].DIRCLR = pin.pin_mask; - // The input value can be read from bit y in register IN as soon as the INEN bit in the pin - // configuratation register is written to '1' to enable the pins input buffer. - pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .INEN = 1 }); - } - - /// Configure the given pin as input with pull-up. - pub fn setInputPullUp(comptime pin: type) void { - setInput(pin); - pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); - // When enabling input with pull-up, bit y must be set to '1'. - write(pin, .high); - } - - /// Configure the given pin as input with pull-down. - pub fn setInputPullDown(comptime pin: type) void { - setInput(pin); - pin.gpio_port[pin.port_number].PINCFG[pin.pin_number].modify(.{ .PULLEN = 1 }); - // When enabling input with pull-down, bit y must be set to '0'. - write(pin, .low); - } - - /// Check if the given pin is configured as output. - /// Returns true on success, false otherwise. - pub fn isOutput(comptime pin: type) bool { - return (pin.gpio_port[pin.port_number].DIR & pin.pin_mask) != 0; - } - - pub fn read(comptime pin: type) micro.gpio.State { - return if ((pin.gpio_port[pin.port_number].IN & pin.pin_mask) != 0) - micro.gpio.State.high - else - micro.gpio.State.low; - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - switch (state) { - .high => pin.gpio_port[pin.port_number].OUTSET = pin.pin_mask, - .low => pin.gpio_port[pin.port_number].OUTCLR = pin.pin_mask, - } - } - - pub fn toggle(comptime pin: type) void { - pin.gpio_port[pin.port_number].OUTTGL = pin.pin_mask; - } -}; - -// ############################################################################# -// Nonvolotile Memory Controller - NVMCTRL -// ############################################################################# - -pub fn nvmctrlInit() void { - regs.NVMCTRL.CTRLA.modify(.{ - .RWS = 5, // Number of wait states for a read operation - .AUTOWS = 1, // Enable wait states - }); -} - -// ############################################################################# -// Generic Clock Controller - GCLK -// ############################################################################# - -pub fn gclk2Init() void { - regs.GCLK.GENCTRL[2].modify(.{ - .DIV = 1, - .SRC = 6, // DFLL48M generator clock source - .GENEN = 1, // Enable generator - }); - - while (regs.GCLK.SYNCBUSY.read().GENCTRL & 2 != 0) { - // wait for sync - } -} - -// ############################################################################# -// UART -// ############################################################################# - -/// Calculate the BAUD register value based on the the expected output frequency -/// `fbaud` and the baud reference frequency `fref` (see data sheet p. 830). -pub fn asyncArithmeticBaudToRegister(fbaud: u32, fref: u32) u16 { - const fb = @intToFloat(f64, fbaud); - const fr = @intToFloat(f64, fref); - const res = 65536.0 * (1.0 - 16.0 * (fb / fr)); - - return @floatToInt(u16, res); -} - -/// Unique definitions for the chip, used by the microzig.uart.Config struct. -pub const uart = struct { - /// USART character size (p. 859). - pub const DataBits = enum(u3) { - eight = 0, - nine = 1, - five = 5, - six = 6, - seven = 7, - }; - - /// USART stop bits (p. 859). - pub const StopBits = enum(u1) { - one = 0, - tow = 1, - }; - - /// USART parity mode (p. 858). - pub const Parity = enum(u1) { - even = 0, - odd = 1, - }; -}; - -/// Instantiate a new USART interface. -/// -/// * `index` - SERCOM{index} should be used for UART -/// * `pins` - Not supported. Please use `.{ .tx = null, .rx = null }` -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (pins.tx != null or pins.rx != null) - @compileError("SAMD/E5x doesn't support custom pins"); - - return struct { - const UARTn = switch (index) { - 5 => regs.SERCOM5.USART_INT, - else => @compileError("Currently only SERCOM5:USART_INT supported."), - }; - const Self = @This(); - - pub fn init(config: micro.uart.Config) !Self { - switch (index) { - 5 => { - gclk2Init(); - - regs.GCLK.PCHCTRL[35].modify(.{ - .GEN = 2, // Generic clock generator 2 (see p. 156) - .CHEN = 1, // Enable peripheral channel - }); - - // When the APB clock is not provided to a module, its - // registers cannot be read or written. - regs.MCLK.APBDMASK.modify(.{ .SERCOM5_ = 1 }); - - // Enable the peripheral multiplexer selection. - regs.PORT.GROUP[1].PINCFG[16].modify(.{ .PMUXEN = 1 }); - regs.PORT.GROUP[1].PINCFG[17].modify(.{ .PMUXEN = 1 }); - - // Multiplex PB16 and PB17 to peripheral function C, i.e. - // SERCOM5 (see page 32 and 823). - regs.PORT.GROUP[1].PMUX[8].modify(.{ .PMUXE = 2, .PMUXO = 2 }); - }, - else => unreachable, - } - - // Some of the registers are enable-protected, meaning they can only - // be written when the USART is disabled. - UARTn.CTRLA.modify(.{ .ENABLE = 0 }); - - // Wait until synchronized. - while (UARTn.SYNCBUSY.read().ENABLE != 0) {} - - // Select USART with internal clock (0x1). - UARTn.CTRLA.modify(.{ - .MODE = 1, // Select USART with internal clock (0x01) - .CMODE = 0, // Select asynchronous communication mode (0x00) - // Pin selection (data sheet p. 854) - .RXPO = 1, // SERCOM PAD[1] is used for data reception - .TXPO = 0, // SERCOM PAD[0] is used for data transmition - .DORD = 1, // Configure data order (MSB = 0, LSB = 1) - .IBON = 1, // Immediate buffer overflow notification - .SAMPR = 0, // 16x over-sampling using arithmetic baud rate generation - }); - - // Configure parity mode. - if (config.parity != null) { - // Enable parity mode. - UARTn.CTRLA.modify(.{ .FORM = 1 }); // USART frame with parity - UARTn.CTRLB.modify(.{ .PMODE = @enumToInt(config.parity.?) }); - } else { - // Disable parity mode. - UARTn.CTRLA.modify(.{ .FORM = 0 }); // USART frame - } - - // Write the Baud register (internal clock mode) to generate the - // desired baud rate. - UARTn.BAUD.* = asyncArithmeticBaudToRegister(config.baud_rate, 48_000_000); //@intCast(u16, config.baud_rate); - - UARTn.CTRLB.modify(.{ - .CHSIZE = @enumToInt(config.data_bits), // Configure the character size filed. - .SBMODE = @enumToInt(config.stop_bits), // Configure the number of stop bits. - .RXEN = 1, // Enable the receiver - .TXEN = 1, // Enable the transmitter - }); - - //UARTn.INTENSET.modify(.{ .DRE = 1, .TXC = 1, .RXC = 1, .CTSIC = 1 }); - - while (UARTn.SYNCBUSY.raw != 0) {} - - // Enable the peripheral. - UARTn.CTRLA.modify(.{ .ENABLE = 1 }); - while (UARTn.SYNCBUSY.raw != 0) {} - - return Self{}; - } - - pub fn canWrite(self: Self) bool { - _ = self; - // The DRE flag ist set when DATA is empty and ready to be written. - // The DATA register should only be written to when INTFLAG.DRE is set. - return UARTn.INTFLAG.read().DRE == 1; - } - pub fn tx(self: Self, ch: u8) void { - while (!self.canWrite()) {} // Wait for Previous transmission - UARTn.DATA.* = ch; // Load the data to be transmitted - } - - pub fn canRead(self: Self) bool { - _ = self; - // The RXC flag ist set when there are unread data in DATA. - return UARTn.INTFLAG.read().RXC == 1; - } - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - return @intCast(u8, UARTn.DATA.*); // Read received data - } - }; -} - -// ############################################################################# -// Crypto -// ############################################################################# - -pub fn enableTrng() void { - // Enable the TRNG bus clock. - regs.MCLK.APBCMASK.modify(.{ .TRNG_ = 1 }); -} - -pub const crypto = struct { - pub const random = struct { - /// Fill the given slice with random data. - pub fn getBlock(buffer: []u8) void { - var rand: u32 = undefined; - - var i: usize = 0; - while (i < buffer.len) : (i += 1) { - if (i % 4 == 0) { - // Get a fresh 32 bit integer every 4th iteration. - rand = getWord(); - } - - // The shift value is always between 0 and 24, i.e. int cast will always succeed. - buffer[i] = @intCast(u8, (rand >> @intCast(u5, (8 * (i % 4)))) & 0xff); - } - } - - /// Get a real 32 bit random integer. - /// - /// In most cases you'll want to use `getBlock` instead. - pub fn getWord() u32 { - regs.TRNG.CTRLA.modify(.{ .ENABLE = 1 }); - while (regs.TRNG.INTFLAG.read().DATARDY == 0) { - // a new random number is generated every - // 84 CLK_TRNG_APB clock cycles (p. 1421). - } - regs.TRNG.CTRLA.modify(.{ .ENABLE = 0 }); - return regs.TRNG.DATA.*; - } - - /// Get a real 8 bit random integer. - /// - /// In most cases you'll want to use `getBlock` instead. - pub fn getByte() u8 { - return @intCast(u8, getWord() & 0xFF); - } - }; -}; diff --git a/src/modules/chips/atsame51j20a/registers.zig b/src/modules/chips/atsame51j20a/registers.zig deleted file mode 100644 index de11221..0000000 --- a/src/modules/chips/atsame51j20a/registers.zig +++ /dev/null @@ -1,25436 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 4b04e50cf14a3df87662dc79863e9b7e3dfc6591 -// -// vendor: Microchip Technology -// device: ATSAME51J20A -// cpu: CM4 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - PM: InterruptVector = unhandled, - MCLK: InterruptVector = unhandled, - OSCCTRL_XOSC0: InterruptVector = unhandled, - OSCCTRL_XOSC1: InterruptVector = unhandled, - OSCCTRL_DFLL: InterruptVector = unhandled, - OSCCTRL_DPLL0: InterruptVector = unhandled, - OSCCTRL_DPLL1: InterruptVector = unhandled, - OSC32KCTRL: InterruptVector = unhandled, - SUPC_OTHER: InterruptVector = unhandled, - SUPC_BODDET: InterruptVector = unhandled, - WDT: InterruptVector = unhandled, - RTC: InterruptVector = unhandled, - EIC_EXTINT_0: InterruptVector = unhandled, - EIC_EXTINT_1: InterruptVector = unhandled, - EIC_EXTINT_2: InterruptVector = unhandled, - EIC_EXTINT_3: InterruptVector = unhandled, - EIC_EXTINT_4: InterruptVector = unhandled, - EIC_EXTINT_5: InterruptVector = unhandled, - EIC_EXTINT_6: InterruptVector = unhandled, - EIC_EXTINT_7: InterruptVector = unhandled, - EIC_EXTINT_8: InterruptVector = unhandled, - EIC_EXTINT_9: InterruptVector = unhandled, - EIC_EXTINT_10: InterruptVector = unhandled, - EIC_EXTINT_11: InterruptVector = unhandled, - EIC_EXTINT_12: InterruptVector = unhandled, - EIC_EXTINT_13: InterruptVector = unhandled, - EIC_EXTINT_14: InterruptVector = unhandled, - EIC_EXTINT_15: InterruptVector = unhandled, - FREQM: InterruptVector = unhandled, - NVMCTRL_0: InterruptVector = unhandled, - NVMCTRL_1: InterruptVector = unhandled, - DMAC_0: InterruptVector = unhandled, - DMAC_1: InterruptVector = unhandled, - DMAC_2: InterruptVector = unhandled, - DMAC_3: InterruptVector = unhandled, - DMAC_OTHER: InterruptVector = unhandled, - EVSYS_0: InterruptVector = unhandled, - EVSYS_1: InterruptVector = unhandled, - EVSYS_2: InterruptVector = unhandled, - EVSYS_3: InterruptVector = unhandled, - EVSYS_OTHER: InterruptVector = unhandled, - PAC: InterruptVector = unhandled, - reserved2: u32 = undefined, - reserved3: u32 = undefined, - reserved4: u32 = undefined, - RAMECC: InterruptVector = unhandled, - SERCOM0_0: InterruptVector = unhandled, - SERCOM0_1: InterruptVector = unhandled, - SERCOM0_2: InterruptVector = unhandled, - SERCOM0_OTHER: InterruptVector = unhandled, - SERCOM1_0: InterruptVector = unhandled, - SERCOM1_1: InterruptVector = unhandled, - SERCOM1_2: InterruptVector = unhandled, - SERCOM1_OTHER: InterruptVector = unhandled, - SERCOM2_0: InterruptVector = unhandled, - SERCOM2_1: InterruptVector = unhandled, - SERCOM2_2: InterruptVector = unhandled, - SERCOM2_OTHER: InterruptVector = unhandled, - SERCOM3_0: InterruptVector = unhandled, - SERCOM3_1: InterruptVector = unhandled, - SERCOM3_2: InterruptVector = unhandled, - SERCOM3_OTHER: InterruptVector = unhandled, - SERCOM4_0: InterruptVector = unhandled, - SERCOM4_1: InterruptVector = unhandled, - SERCOM4_2: InterruptVector = unhandled, - SERCOM4_OTHER: InterruptVector = unhandled, - SERCOM5_0: InterruptVector = unhandled, - SERCOM5_1: InterruptVector = unhandled, - SERCOM5_2: InterruptVector = unhandled, - SERCOM5_OTHER: InterruptVector = unhandled, - reserved5: u32 = undefined, - reserved6: u32 = undefined, - reserved7: u32 = undefined, - reserved8: u32 = undefined, - reserved9: u32 = undefined, - reserved10: u32 = undefined, - reserved11: u32 = undefined, - reserved12: u32 = undefined, - CAN0: InterruptVector = unhandled, - CAN1: InterruptVector = unhandled, - USB_OTHER: InterruptVector = unhandled, - USB_SOF_HSOF: InterruptVector = unhandled, - USB_TRCPT0: InterruptVector = unhandled, - USB_TRCPT1: InterruptVector = unhandled, - reserved13: u32 = undefined, - TCC0_OTHER: InterruptVector = unhandled, - TCC0_MC0: InterruptVector = unhandled, - TCC0_MC1: InterruptVector = unhandled, - TCC0_MC2: InterruptVector = unhandled, - TCC0_MC3: InterruptVector = unhandled, - TCC0_MC4: InterruptVector = unhandled, - TCC0_MC5: InterruptVector = unhandled, - TCC1_OTHER: InterruptVector = unhandled, - TCC1_MC0: InterruptVector = unhandled, - TCC1_MC1: InterruptVector = unhandled, - TCC1_MC2: InterruptVector = unhandled, - TCC1_MC3: InterruptVector = unhandled, - TCC2_OTHER: InterruptVector = unhandled, - TCC2_MC0: InterruptVector = unhandled, - TCC2_MC1: InterruptVector = unhandled, - TCC2_MC2: InterruptVector = unhandled, - TCC3_OTHER: InterruptVector = unhandled, - TCC3_MC0: InterruptVector = unhandled, - TCC3_MC1: InterruptVector = unhandled, - TCC4_OTHER: InterruptVector = unhandled, - TCC4_MC0: InterruptVector = unhandled, - TCC4_MC1: InterruptVector = unhandled, - TC0: InterruptVector = unhandled, - TC1: InterruptVector = unhandled, - TC2: InterruptVector = unhandled, - TC3: InterruptVector = unhandled, - TC4: InterruptVector = unhandled, - TC5: InterruptVector = unhandled, - reserved14: u32 = undefined, - reserved15: u32 = undefined, - PDEC_OTHER: InterruptVector = unhandled, - PDEC_MC0: InterruptVector = unhandled, - PDEC_MC1: InterruptVector = unhandled, - ADC0_OTHER: InterruptVector = unhandled, - ADC0_RESRDY: InterruptVector = unhandled, - ADC1_OTHER: InterruptVector = unhandled, - ADC1_RESRDY: InterruptVector = unhandled, - AC: InterruptVector = unhandled, - DAC_OTHER: InterruptVector = unhandled, - DAC_EMPTY_0: InterruptVector = unhandled, - DAC_EMPTY_1: InterruptVector = unhandled, - DAC_RESRDY_0: InterruptVector = unhandled, - DAC_RESRDY_1: InterruptVector = unhandled, - I2S: InterruptVector = unhandled, - PCC: InterruptVector = unhandled, - AES: InterruptVector = unhandled, - TRNG: InterruptVector = unhandled, - ICM: InterruptVector = unhandled, - reserved16: u32 = undefined, - QSPI: InterruptVector = unhandled, - SDHC0: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// System Control Space - pub const SCS = struct { - pub const base_address = 0xe000e000; - - /// System Tick Timer - pub const SysTick = struct { - /// address: 0xe000e010 - /// SysTick Control and Status Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0xe000e014 - /// SysTick Reload Value Register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x14); - - /// address: 0xe000e018 - /// SysTick Current Value Register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000e01c - /// SysTick Calibration Register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - SKEW: u1, - NOREF: u1, - }), base_address + 0x1c); - }; - }; - - /// Analog Comparators - pub const AC = struct { - pub const base_address = 0x42002000; - pub const version = "U25011.0.0"; - - /// address: 0x42002000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x42002001 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 Start Comparison - START0: u1, - /// Comparator 1 Start Comparison - START1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1); - - /// address: 0x42002002 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Comparator 0 Event Output Enable - COMPEO0: u1, - /// Comparator 1 Event Output Enable - COMPEO1: u1, - reserved0: u1, - reserved1: u1, - /// Window 0 Event Output Enable - WINEO0: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Comparator 0 Event Input Enable - COMPEI0: u1, - /// Comparator 1 Event Input Enable - COMPEI1: u1, - reserved5: u1, - reserved6: u1, - /// Comparator 0 Input Event Invert Enable - INVEI0: u1, - /// Comparator 1 Input Event Invert Enable - INVEI1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x2); - - /// address: 0x42002004 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 Interrupt Enable - COMP0: u1, - /// Comparator 1 Interrupt Enable - COMP1: u1, - reserved0: u1, - reserved1: u1, - /// Window 0 Interrupt Enable - WIN0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x4); - - /// address: 0x42002005 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 Interrupt Enable - COMP0: u1, - /// Comparator 1 Interrupt Enable - COMP1: u1, - reserved0: u1, - reserved1: u1, - /// Window 0 Interrupt Enable - WIN0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x5); - - /// address: 0x42002006 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 - COMP0: u1, - /// Comparator 1 - COMP1: u1, - reserved0: u1, - reserved1: u1, - /// Window 0 - WIN0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x6); - - /// address: 0x42002007 - /// Status A - pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 Current State - STATE0: u1, - /// Comparator 1 Current State - STATE1: u1, - reserved0: u1, - reserved1: u1, - /// Window 0 Current State - WSTATE0: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x7); - - /// address: 0x42002008 - /// Status B - pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { - /// Comparator 0 Ready - READY0: u1, - /// Comparator 1 Ready - READY1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x42002009 - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x9); - - /// address: 0x4200200a - /// Window Control - pub const WINCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Window 0 Mode Enable - WEN0: u1, - /// Window 0 Interrupt Selection - WINTSEL0: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0xa); - - /// address: 0x4200200c - /// Scaler n - pub const SCALER = @intToPtr(*volatile [2]Mmio(8, packed struct { - /// Scaler Value - VALUE: u6, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0x42002010 - /// Comparator Control n - pub const COMPCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - /// Single-Shot Mode - SINGLE: u1, - /// Interrupt Selection - INTSEL: u2, - reserved1: u1, - /// Run in Standby - RUNSTDBY: u1, - reserved2: u1, - /// Negative Input Mux Selection - MUXNEG: u3, - reserved3: u1, - /// Positive Input Mux Selection - MUXPOS: u3, - /// Swap Inputs and Invert - SWAP: u1, - /// Speed Selection - SPEED: u2, - reserved4: u1, - /// Hysteresis Enable - HYSTEN: u1, - /// Hysteresis Level - HYST: u2, - reserved5: u1, - reserved6: u1, - /// Filter Length - FLEN: u3, - reserved7: u1, - /// Output - OUT: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x42002020 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// Enable Synchronization Busy - ENABLE: u1, - /// WINCTRL Synchronization Busy - WINCTRL: u1, - /// COMPCTRL 0 Synchronization Busy - COMPCTRL0: u1, - /// COMPCTRL 1 Synchronization Busy - COMPCTRL1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x20); - - /// address: 0x42002024 - /// Calibration - pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { - /// COMP0/1 Bias Scaling - BIAS0: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x24); - }; - - /// Analog Digital Converter - pub const ADC0 = struct { - pub const base_address = 0x43001c00; - pub const version = "U25001.0.0"; - - /// address: 0x43001c00 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - /// Dual Mode Trigger Selection - DUALSEL: u2, - /// Slave Enable - SLAVEEN: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - /// Prescaler Configuration - PRESCALER: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Rail to Rail Operation Enable - R2R: u1, - }), base_address + 0x0); - - /// address: 0x43001c02 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Flush Event Input Enable - FLUSHEI: u1, - /// Start Conversion Event Input Enable - STARTEI: u1, - /// Flush Event Invert Enable - FLUSHINV: u1, - /// Start Conversion Event Invert Enable - STARTINV: u1, - /// Result Ready Event Out - RESRDYEO: u1, - /// Window Monitor Event Out - WINMONEO: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x2); - - /// address: 0x43001c03 - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x3); - - /// address: 0x43001c04 - /// Input Control - pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Positive Mux Input Selection - MUXPOS: u5, - reserved0: u1, - reserved1: u1, - /// Differential Mode - DIFFMODE: u1, - /// Negative Mux Input Selection - MUXNEG: u5, - reserved2: u1, - reserved3: u1, - /// Stop DMA Sequencing - DSEQSTOP: u1, - }), base_address + 0x4); - - /// address: 0x43001c06 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// Left-Adjusted Result - LEFTADJ: u1, - /// Free Running Mode - FREERUN: u1, - /// Digital Correction Logic Enable - CORREN: u1, - /// Conversion Result Resolution - RESSEL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Window Monitor Mode - WINMODE: u3, - /// Window Single Sample - WINSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x6); - - /// address: 0x43001c08 - /// Reference Control - pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Reference Selection - REFSEL: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Reference Buffer Offset Compensation Enable - REFCOMP: u1, - }), base_address + 0x8); - - /// address: 0x43001c0a - /// Average Control - pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Number of Samples to be Collected - SAMPLENUM: u4, - /// Adjusting Result / Division Coefficient - ADJRES: u3, - padding0: u1, - }), base_address + 0xa); - - /// address: 0x43001c0b - /// Sample Time Control - pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Sampling Time Length - SAMPLEN: u6, - reserved0: u1, - /// Comparator Offset Compensation Enable - OFFCOMP: u1, - }), base_address + 0xb); - - /// address: 0x43001c0c - /// Window Monitor Lower Threshold - pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); - - /// address: 0x43001c0e - /// Window Monitor Upper Threshold - pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); - - /// address: 0x43001c10 - /// Gain Correction - pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); - - /// address: 0x43001c12 - /// Offset Correction - pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); - - /// address: 0x43001c14 - /// Software Trigger - pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Conversion Flush - FLUSH: u1, - /// Start ADC Conversion - START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x43001c2c - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Disable - RESRDY: u1, - /// Overrun Interrupt Disable - OVERRUN: u1, - /// Window Monitor Interrupt Disable - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2c); - - /// address: 0x43001c2d - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Enable - RESRDY: u1, - /// Overrun Interrupt Enable - OVERRUN: u1, - /// Window Monitor Interrupt Enable - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2d); - - /// address: 0x43001c2e - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Flag - RESRDY: u1, - /// Overrun Interrupt Flag - OVERRUN: u1, - /// Window Monitor Interrupt Flag - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2e); - - /// address: 0x43001c2f - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Busy Status - ADCBUSY: u1, - reserved0: u1, - /// Window Comparator Counter - WCC: u6, - }), base_address + 0x2f); - - /// address: 0x43001c30 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// SWRST Synchronization Busy - SWRST: u1, - /// ENABLE Synchronization Busy - ENABLE: u1, - /// Input Control Synchronization Busy - INPUTCTRL: u1, - /// Control B Synchronization Busy - CTRLB: u1, - /// Reference Control Synchronization Busy - REFCTRL: u1, - /// Average Control Synchronization Busy - AVGCTRL: u1, - /// Sampling Time Control Synchronization Busy - SAMPCTRL: u1, - /// Window Monitor Lower Threshold Synchronization Busy - WINLT: u1, - /// Window Monitor Upper Threshold Synchronization Busy - WINUT: u1, - /// Gain Correction Synchronization Busy - GAINCORR: u1, - /// Offset Correction Synchronization Busy - OFFSETCORR: u1, - /// Software Trigger Synchronization Busy - SWTRIG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - - /// address: 0x43001c34 - /// DMA Sequencial Data - pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Sequential Data - DATA: u32, - }), base_address + 0x34); - - /// address: 0x43001c38 - /// DMA Sequential Control - pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Input Control - INPUTCTRL: u1, - /// Control B - CTRLB: u1, - /// Reference Control - REFCTRL: u1, - /// Average Control - AVGCTRL: u1, - /// Sampling Time Control - SAMPCTRL: u1, - /// Window Monitor Lower Threshold - WINLT: u1, - /// Window Monitor Upper Threshold - WINUT: u1, - /// Gain Correction - GAINCORR: u1, - /// Offset Correction - OFFSETCORR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADC Auto-Start Conversion - AUTOSTART: u1, - }), base_address + 0x38); - - /// address: 0x43001c3c - /// DMA Sequencial Status - pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Input Control - INPUTCTRL: u1, - /// Control B - CTRLB: u1, - /// Reference Control - REFCTRL: u1, - /// Average Control - AVGCTRL: u1, - /// Sampling Time Control - SAMPCTRL: u1, - /// Window Monitor Lower Threshold - WINLT: u1, - /// Window Monitor Upper Threshold - WINUT: u1, - /// Gain Correction - GAINCORR: u1, - /// Offset Correction - OFFSETCORR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// DMA Sequencing Busy - BUSY: u1, - }), base_address + 0x3c); - - /// address: 0x43001c40 - /// Result Conversion Value - pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); - - /// address: 0x43001c44 - /// Last Sample Result - pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); - - /// address: 0x43001c48 - /// Calibration - pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { - /// Bias Comparator Scaling - BIASCOMP: u3, - reserved0: u1, - /// Bias R2R Ampli scaling - BIASR2R: u3, - reserved1: u1, - /// Bias Reference Buffer Scaling - BIASREFBUF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x48); - }; - pub const ADC1 = struct { - pub const base_address = 0x43002000; - - /// address: 0x43002000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - /// Dual Mode Trigger Selection - DUALSEL: u2, - /// Slave Enable - SLAVEEN: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - /// Prescaler Configuration - PRESCALER: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Rail to Rail Operation Enable - R2R: u1, - }), base_address + 0x0); - - /// address: 0x43002002 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Flush Event Input Enable - FLUSHEI: u1, - /// Start Conversion Event Input Enable - STARTEI: u1, - /// Flush Event Invert Enable - FLUSHINV: u1, - /// Start Conversion Event Invert Enable - STARTINV: u1, - /// Result Ready Event Out - RESRDYEO: u1, - /// Window Monitor Event Out - WINMONEO: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x2); - - /// address: 0x43002003 - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x3); - - /// address: 0x43002004 - /// Input Control - pub const INPUTCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Positive Mux Input Selection - MUXPOS: u5, - reserved0: u1, - reserved1: u1, - /// Differential Mode - DIFFMODE: u1, - /// Negative Mux Input Selection - MUXNEG: u5, - reserved2: u1, - reserved3: u1, - /// Stop DMA Sequencing - DSEQSTOP: u1, - }), base_address + 0x4); - - /// address: 0x43002006 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// Left-Adjusted Result - LEFTADJ: u1, - /// Free Running Mode - FREERUN: u1, - /// Digital Correction Logic Enable - CORREN: u1, - /// Conversion Result Resolution - RESSEL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Window Monitor Mode - WINMODE: u3, - /// Window Single Sample - WINSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x6); - - /// address: 0x43002008 - /// Reference Control - pub const REFCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Reference Selection - REFSEL: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Reference Buffer Offset Compensation Enable - REFCOMP: u1, - }), base_address + 0x8); - - /// address: 0x4300200a - /// Average Control - pub const AVGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Number of Samples to be Collected - SAMPLENUM: u4, - /// Adjusting Result / Division Coefficient - ADJRES: u3, - padding0: u1, - }), base_address + 0xa); - - /// address: 0x4300200b - /// Sample Time Control - pub const SAMPCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Sampling Time Length - SAMPLEN: u6, - reserved0: u1, - /// Comparator Offset Compensation Enable - OFFCOMP: u1, - }), base_address + 0xb); - - /// address: 0x4300200c - /// Window Monitor Lower Threshold - pub const WINLT = @intToPtr(*volatile u16, base_address + 0xc); - - /// address: 0x4300200e - /// Window Monitor Upper Threshold - pub const WINUT = @intToPtr(*volatile u16, base_address + 0xe); - - /// address: 0x43002010 - /// Gain Correction - pub const GAINCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x10); - - /// address: 0x43002012 - /// Offset Correction - pub const OFFSETCORR = @intToPtr(*volatile MmioInt(16, u12), base_address + 0x12); - - /// address: 0x43002014 - /// Software Trigger - pub const SWTRIG = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Conversion Flush - FLUSH: u1, - /// Start ADC Conversion - START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x4300202c - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Disable - RESRDY: u1, - /// Overrun Interrupt Disable - OVERRUN: u1, - /// Window Monitor Interrupt Disable - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2c); - - /// address: 0x4300202d - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Enable - RESRDY: u1, - /// Overrun Interrupt Enable - OVERRUN: u1, - /// Window Monitor Interrupt Enable - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2d); - - /// address: 0x4300202e - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Result Ready Interrupt Flag - RESRDY: u1, - /// Overrun Interrupt Flag - OVERRUN: u1, - /// Window Monitor Interrupt Flag - WINMON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2e); - - /// address: 0x4300202f - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// ADC Busy Status - ADCBUSY: u1, - reserved0: u1, - /// Window Comparator Counter - WCC: u6, - }), base_address + 0x2f); - - /// address: 0x43002030 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// SWRST Synchronization Busy - SWRST: u1, - /// ENABLE Synchronization Busy - ENABLE: u1, - /// Input Control Synchronization Busy - INPUTCTRL: u1, - /// Control B Synchronization Busy - CTRLB: u1, - /// Reference Control Synchronization Busy - REFCTRL: u1, - /// Average Control Synchronization Busy - AVGCTRL: u1, - /// Sampling Time Control Synchronization Busy - SAMPCTRL: u1, - /// Window Monitor Lower Threshold Synchronization Busy - WINLT: u1, - /// Window Monitor Upper Threshold Synchronization Busy - WINUT: u1, - /// Gain Correction Synchronization Busy - GAINCORR: u1, - /// Offset Correction Synchronization Busy - OFFSETCORR: u1, - /// Software Trigger Synchronization Busy - SWTRIG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - - /// address: 0x43002034 - /// DMA Sequencial Data - pub const DSEQDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Sequential Data - DATA: u32, - }), base_address + 0x34); - - /// address: 0x43002038 - /// DMA Sequential Control - pub const DSEQCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Input Control - INPUTCTRL: u1, - /// Control B - CTRLB: u1, - /// Reference Control - REFCTRL: u1, - /// Average Control - AVGCTRL: u1, - /// Sampling Time Control - SAMPCTRL: u1, - /// Window Monitor Lower Threshold - WINLT: u1, - /// Window Monitor Upper Threshold - WINUT: u1, - /// Gain Correction - GAINCORR: u1, - /// Offset Correction - OFFSETCORR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADC Auto-Start Conversion - AUTOSTART: u1, - }), base_address + 0x38); - - /// address: 0x4300203c - /// DMA Sequencial Status - pub const DSEQSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Input Control - INPUTCTRL: u1, - /// Control B - CTRLB: u1, - /// Reference Control - REFCTRL: u1, - /// Average Control - AVGCTRL: u1, - /// Sampling Time Control - SAMPCTRL: u1, - /// Window Monitor Lower Threshold - WINLT: u1, - /// Window Monitor Upper Threshold - WINUT: u1, - /// Gain Correction - GAINCORR: u1, - /// Offset Correction - OFFSETCORR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// DMA Sequencing Busy - BUSY: u1, - }), base_address + 0x3c); - - /// address: 0x43002040 - /// Result Conversion Value - pub const RESULT = @intToPtr(*volatile u16, base_address + 0x40); - - /// address: 0x43002044 - /// Last Sample Result - pub const RESS = @intToPtr(*volatile u16, base_address + 0x44); - - /// address: 0x43002048 - /// Calibration - pub const CALIB = @intToPtr(*volatile Mmio(16, packed struct { - /// Bias Comparator Scaling - BIASCOMP: u3, - reserved0: u1, - /// Bias R2R Ampli scaling - BIASR2R: u3, - reserved1: u1, - /// Bias Reference Buffer Scaling - BIASREFBUF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x48); - }; - - /// Advanced Encryption Standard - pub const AES = struct { - pub const base_address = 0x42002400; - pub const version = "U22382.2.0"; - - /// address: 0x42002400 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// AES Modes of operation - AESMODE: u3, - /// Cipher Feedback Block Size - CFBS: u3, - /// Encryption Key Size - KEYSIZE: u2, - /// Cipher Mode - CIPHER: u1, - /// Start Mode Select - STARTMODE: u1, - /// Last Output Data Mode - LOD: u1, - /// Last Key Generation - KEYGEN: u1, - /// XOR Key Operation - XORKEY: u1, - reserved0: u1, - /// Counter Measure Type - CTYPE: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x42002404 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { - /// Start Encryption/Decryption - START: u1, - /// New message - NEWMSG: u1, - /// End of message - EOM: u1, - /// GF Multiplication - GFMUL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x42002405 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Encryption Complete Interrupt Enable - ENCCMP: u1, - /// GF Multiplication Complete Interrupt Enable - GFMCMP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x5); - - /// address: 0x42002406 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Encryption Complete Interrupt Enable - ENCCMP: u1, - /// GF Multiplication Complete Interrupt Enable - GFMCMP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x6); - - /// address: 0x42002407 - /// Interrupt Flag Status - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Encryption Complete - ENCCMP: u1, - /// GF Multiplication Complete - GFMCMP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x7); - - /// address: 0x42002408 - /// Data buffer pointer - pub const DATABUFPTR = @intToPtr(*volatile Mmio(8, packed struct { - /// Input Data Pointer - INDATAPTR: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x42002409 - /// Debug control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x9); - - /// address: 0x4200240c - /// Keyword n - pub const KEYWORD = @intToPtr(*volatile [8]u32, base_address + 0xc); - - /// address: 0x42002438 - /// Indata - pub const INDATA = @intToPtr(*volatile u32, base_address + 0x38); - - /// address: 0x4200243c - /// Initialisation Vector n - pub const INTVECTV = @intToPtr(*volatile [4]u32, base_address + 0x3c); - - /// address: 0x4200245c - /// Hash key n - pub const HASHKEY = @intToPtr(*volatile [4]u32, base_address + 0x5c); - - /// address: 0x4200246c - /// Galois Hash n - pub const GHASH = @intToPtr(*volatile [4]u32, base_address + 0x6c); - - /// address: 0x42002480 - /// Cipher Length - pub const CIPLEN = @intToPtr(*volatile u32, base_address + 0x80); - - /// address: 0x42002484 - /// Random Seed - pub const RANDSEED = @intToPtr(*volatile u32, base_address + 0x84); - }; - - /// Control Area Network - pub const CAN0 = struct { - pub const base_address = 0x42000000; - pub const version = "U20033.2.1"; - - /// address: 0x42000000 - /// Core Release - pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Sub-step of Core Release - SUBSTEP: u4, - /// Step of Core Release - STEP: u4, - /// Core Release - REL: u4, - }), base_address + 0x0); - - /// address: 0x42000004 - /// Endian - pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { - /// Endianness Test Value - ETV: u32, - }), base_address + 0x4); - - /// address: 0x42000008 - /// Message RAM Configuration - pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Quality of Service - QOS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x8); - - /// address: 0x4200000c - /// Fast Bit Timing and Prescaler - pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { - /// Data (Re)Synchronization Jump Width - DSJW: u4, - /// Data time segment after sample point - DTSEG2: u4, - /// Data time segment before sample point - DTSEG1: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Data Baud Rate Prescaler - DBRP: u5, - reserved3: u1, - reserved4: u1, - /// Tranceiver Delay Compensation - TDC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x42000010 - /// Test - pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Loop Back Mode - LBCK: u1, - /// Control of Transmit Pin - TX: u2, - /// Receive Pin - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x42000014 - /// RAM Watchdog - pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog Configuration - WDC: u8, - /// Watchdog Value - WDV: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x42000018 - /// CC Control - pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Initialization - INIT: u1, - /// Configuration Change Enable - CCE: u1, - /// ASM Restricted Operation Mode - ASM: u1, - /// Clock Stop Acknowledge - CSA: u1, - /// Clock Stop Request - CSR: u1, - /// Bus Monitoring Mode - MON: u1, - /// Disable Automatic Retransmission - DAR: u1, - /// Test Mode Enable - TEST: u1, - /// FD Operation Enable - FDOE: u1, - /// Bit Rate Switch Enable - BRSE: u1, - reserved0: u1, - reserved1: u1, - /// Protocol Exception Handling Disable - PXHD: u1, - /// Edge Filtering during Bus Integration - EFBI: u1, - /// Transmit Pause - TXP: u1, - /// Non ISO Operation - NISO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4200001c - /// Nominal Bit Timing and Prescaler - pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { - /// Nominal Time segment after sample point - NTSEG2: u7, - reserved0: u1, - /// Nominal Time segment before sample point - NTSEG1: u8, - /// Nominal Baud Rate Prescaler - NBRP: u9, - /// Nominal (Re)Synchronization Jump Width - NSJW: u7, - }), base_address + 0x1c); - - /// address: 0x42000020 - /// Timestamp Counter Configuration - pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { - /// Timestamp Select - TSS: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Timestamp Counter Prescaler - TCP: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x20); - - /// address: 0x42000024 - /// Timestamp Counter Value - pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { - /// Timestamp Counter - TSC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x42000028 - /// Timeout Counter Configuration - pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Timeout Counter - ETOC: u1, - /// Timeout Select - TOS: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Timeout Period - TOP: u16, - }), base_address + 0x28); - - /// address: 0x4200002c - /// Timeout Counter Value - pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { - /// Timeout Counter - TOC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x42000040 - /// Error Counter - pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit Error Counter - TEC: u8, - /// Receive Error Counter - REC: u7, - /// Receive Error Passive - RP: u1, - /// CAN Error Logging - CEL: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42000044 - /// Protocol Status - pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Last Error Code - LEC: u3, - /// Activity - ACT: u2, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Data Phase Last Error Code - DLEC: u3, - /// ESI flag of last received CAN FD Message - RESI: u1, - /// BRS flag of last received CAN FD Message - RBRS: u1, - /// Received a CAN FD Message - RFDF: u1, - /// Protocol Exception Event - PXE: u1, - reserved0: u1, - /// Transmitter Delay Compensation Value - TDCV: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x44); - - /// address: 0x42000048 - /// Extended ID Filter Configuration - pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmitter Delay Compensation Filter Length - TDCF: u7, - reserved0: u1, - /// Transmitter Delay Compensation Offset - TDCO: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x48); - - /// address: 0x42000050 - /// Interrupt - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message - RF0N: u1, - /// Rx FIFO 0 Watermark Reached - RF0W: u1, - /// Rx FIFO 0 Full - RF0F: u1, - /// Rx FIFO 0 Message Lost - RF0L: u1, - /// Rx FIFO 1 New Message - RF1N: u1, - /// Rx FIFO 1 Watermark Reached - RF1W: u1, - /// Rx FIFO 1 FIFO Full - RF1F: u1, - /// Rx FIFO 1 Message Lost - RF1L: u1, - /// High Priority Message - HPM: u1, - /// Timestamp Completed - TC: u1, - /// Transmission Cancellation Finished - TCF: u1, - /// Tx FIFO Empty - TFE: u1, - /// Tx Event FIFO New Entry - TEFN: u1, - /// Tx Event FIFO Watermark Reached - TEFW: u1, - /// Tx Event FIFO Full - TEFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - /// Timestamp Wraparound - TSW: u1, - /// Message RAM Access Failure - MRAF: u1, - /// Timeout Occurred - TOO: u1, - /// Message stored to Dedicated Rx Buffer - DRX: u1, - /// Bit Error Corrected - BEC: u1, - /// Bit Error Uncorrected - BEU: u1, - /// Error Logging Overflow - ELO: u1, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Watchdog Interrupt - WDI: u1, - /// Protocol Error in Arbitration Phase - PEA: u1, - /// Protocol Error in Data Phase - PED: u1, - /// Access to Reserved Address - ARA: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x50); - - /// address: 0x42000054 - /// Interrupt Enable - pub const IE = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message Interrupt Enable - RF0NE: u1, - /// Rx FIFO 0 Watermark Reached Interrupt Enable - RF0WE: u1, - /// Rx FIFO 0 Full Interrupt Enable - RF0FE: u1, - /// Rx FIFO 0 Message Lost Interrupt Enable - RF0LE: u1, - /// Rx FIFO 1 New Message Interrupt Enable - RF1NE: u1, - /// Rx FIFO 1 Watermark Reached Interrupt Enable - RF1WE: u1, - /// Rx FIFO 1 FIFO Full Interrupt Enable - RF1FE: u1, - /// Rx FIFO 1 Message Lost Interrupt Enable - RF1LE: u1, - /// High Priority Message Interrupt Enable - HPME: u1, - /// Timestamp Completed Interrupt Enable - TCE: u1, - /// Transmission Cancellation Finished Interrupt Enable - TCFE: u1, - /// Tx FIFO Empty Interrupt Enable - TFEE: u1, - /// Tx Event FIFO New Entry Interrupt Enable - TEFNE: u1, - /// Tx Event FIFO Watermark Reached Interrupt Enable - TEFWE: u1, - /// Tx Event FIFO Full Interrupt Enable - TEFFE: u1, - /// Tx Event FIFO Element Lost Interrupt Enable - TEFLE: u1, - /// Timestamp Wraparound Interrupt Enable - TSWE: u1, - /// Message RAM Access Failure Interrupt Enable - MRAFE: u1, - /// Timeout Occurred Interrupt Enable - TOOE: u1, - /// Message stored to Dedicated Rx Buffer Interrupt Enable - DRXE: u1, - /// Bit Error Corrected Interrupt Enable - BECE: u1, - /// Bit Error Uncorrected Interrupt Enable - BEUE: u1, - /// Error Logging Overflow Interrupt Enable - ELOE: u1, - /// Error Passive Interrupt Enable - EPE: u1, - /// Warning Status Interrupt Enable - EWE: u1, - /// Bus_Off Status Interrupt Enable - BOE: u1, - /// Watchdog Interrupt Interrupt Enable - WDIE: u1, - /// Protocol Error in Arbitration Phase Enable - PEAE: u1, - /// Protocol Error in Data Phase Enable - PEDE: u1, - /// Access to Reserved Address Enable - ARAE: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x54); - - /// address: 0x42000058 - /// Interrupt Line Select - pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message Interrupt Line - RF0NL: u1, - /// Rx FIFO 0 Watermark Reached Interrupt Line - RF0WL: u1, - /// Rx FIFO 0 Full Interrupt Line - RF0FL: u1, - /// Rx FIFO 0 Message Lost Interrupt Line - RF0LL: u1, - /// Rx FIFO 1 New Message Interrupt Line - RF1NL: u1, - /// Rx FIFO 1 Watermark Reached Interrupt Line - RF1WL: u1, - /// Rx FIFO 1 FIFO Full Interrupt Line - RF1FL: u1, - /// Rx FIFO 1 Message Lost Interrupt Line - RF1LL: u1, - /// High Priority Message Interrupt Line - HPML: u1, - /// Timestamp Completed Interrupt Line - TCL: u1, - /// Transmission Cancellation Finished Interrupt Line - TCFL: u1, - /// Tx FIFO Empty Interrupt Line - TFEL: u1, - /// Tx Event FIFO New Entry Interrupt Line - TEFNL: u1, - /// Tx Event FIFO Watermark Reached Interrupt Line - TEFWL: u1, - /// Tx Event FIFO Full Interrupt Line - TEFFL: u1, - /// Tx Event FIFO Element Lost Interrupt Line - TEFLL: u1, - /// Timestamp Wraparound Interrupt Line - TSWL: u1, - /// Message RAM Access Failure Interrupt Line - MRAFL: u1, - /// Timeout Occurred Interrupt Line - TOOL: u1, - /// Message stored to Dedicated Rx Buffer Interrupt Line - DRXL: u1, - /// Bit Error Corrected Interrupt Line - BECL: u1, - /// Bit Error Uncorrected Interrupt Line - BEUL: u1, - /// Error Logging Overflow Interrupt Line - ELOL: u1, - /// Error Passive Interrupt Line - EPL: u1, - /// Warning Status Interrupt Line - EWL: u1, - /// Bus_Off Status Interrupt Line - BOL: u1, - /// Watchdog Interrupt Interrupt Line - WDIL: u1, - /// Protocol Error in Arbitration Phase Line - PEAL: u1, - /// Protocol Error in Data Phase Line - PEDL: u1, - /// Access to Reserved Address Line - ARAL: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x58); - - /// address: 0x4200005c - /// Interrupt Line Enable - pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Interrupt Line 0 - EINT0: u1, - /// Enable Interrupt Line 1 - EINT1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x5c); - - /// address: 0x42000080 - /// Global Filter Configuration - pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Reject Remote Frames Extended - RRFE: u1, - /// Reject Remote Frames Standard - RRFS: u1, - /// Accept Non-matching Frames Extended - ANFE: u2, - /// Accept Non-matching Frames Standard - ANFS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x80); - - /// address: 0x42000084 - /// Standard ID Filter Configuration - pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter List Standard Start Address - FLSSA: u16, - /// List Size Standard - LSS: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x84); - - /// address: 0x42000088 - /// Extended ID Filter Configuration - pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter List Extended Start Address - FLESA: u16, - /// List Size Extended - LSE: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x88); - - /// address: 0x42000090 - /// Extended ID AND Mask - pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { - /// Extended ID Mask - EIDM: u29, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x90); - - /// address: 0x42000094 - /// High Priority Message Status - pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { - /// Buffer Index - BIDX: u6, - /// Message Storage Indicator - MSI: u2, - /// Filter Index - FIDX: u7, - /// Filter List - FLST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x94); - - /// address: 0x42000098 - /// New Data 1 - pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// New Data 0 - ND0: u1, - /// New Data 1 - ND1: u1, - /// New Data 2 - ND2: u1, - /// New Data 3 - ND3: u1, - /// New Data 4 - ND4: u1, - /// New Data 5 - ND5: u1, - /// New Data 6 - ND6: u1, - /// New Data 7 - ND7: u1, - /// New Data 8 - ND8: u1, - /// New Data 9 - ND9: u1, - /// New Data 10 - ND10: u1, - /// New Data 11 - ND11: u1, - /// New Data 12 - ND12: u1, - /// New Data 13 - ND13: u1, - /// New Data 14 - ND14: u1, - /// New Data 15 - ND15: u1, - /// New Data 16 - ND16: u1, - /// New Data 17 - ND17: u1, - /// New Data 18 - ND18: u1, - /// New Data 19 - ND19: u1, - /// New Data 20 - ND20: u1, - /// New Data 21 - ND21: u1, - /// New Data 22 - ND22: u1, - /// New Data 23 - ND23: u1, - /// New Data 24 - ND24: u1, - /// New Data 25 - ND25: u1, - /// New Data 26 - ND26: u1, - /// New Data 27 - ND27: u1, - /// New Data 28 - ND28: u1, - /// New Data 29 - ND29: u1, - /// New Data 30 - ND30: u1, - /// New Data 31 - ND31: u1, - }), base_address + 0x98); - - /// address: 0x4200009c - /// New Data 2 - pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// New Data 32 - ND32: u1, - /// New Data 33 - ND33: u1, - /// New Data 34 - ND34: u1, - /// New Data 35 - ND35: u1, - /// New Data 36 - ND36: u1, - /// New Data 37 - ND37: u1, - /// New Data 38 - ND38: u1, - /// New Data 39 - ND39: u1, - /// New Data 40 - ND40: u1, - /// New Data 41 - ND41: u1, - /// New Data 42 - ND42: u1, - /// New Data 43 - ND43: u1, - /// New Data 44 - ND44: u1, - /// New Data 45 - ND45: u1, - /// New Data 46 - ND46: u1, - /// New Data 47 - ND47: u1, - /// New Data 48 - ND48: u1, - /// New Data 49 - ND49: u1, - /// New Data 50 - ND50: u1, - /// New Data 51 - ND51: u1, - /// New Data 52 - ND52: u1, - /// New Data 53 - ND53: u1, - /// New Data 54 - ND54: u1, - /// New Data 55 - ND55: u1, - /// New Data 56 - ND56: u1, - /// New Data 57 - ND57: u1, - /// New Data 58 - ND58: u1, - /// New Data 59 - ND59: u1, - /// New Data 60 - ND60: u1, - /// New Data 61 - ND61: u1, - /// New Data 62 - ND62: u1, - /// New Data 63 - ND63: u1, - }), base_address + 0x9c); - - /// address: 0x420000a0 - /// Rx FIFO 0 Configuration - pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Start Address - F0SA: u16, - /// Rx FIFO 0 Size - F0S: u7, - reserved0: u1, - /// Rx FIFO 0 Watermark - F0WM: u7, - /// FIFO 0 Operation Mode - F0OM: u1, - }), base_address + 0xa0); - - /// address: 0x420000a4 - /// Rx FIFO 0 Status - pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Fill Level - F0FL: u7, - reserved0: u1, - /// Rx FIFO 0 Get Index - F0GI: u6, - reserved1: u1, - reserved2: u1, - /// Rx FIFO 0 Put Index - F0PI: u6, - reserved3: u1, - reserved4: u1, - /// Rx FIFO 0 Full - F0F: u1, - /// Rx FIFO 0 Message Lost - RF0L: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xa4); - - /// address: 0x420000a8 - /// Rx FIFO 0 Acknowledge - pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Acknowledge Index - F0AI: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xa8); - - /// address: 0x420000ac - /// Rx Buffer Configuration - pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx Buffer Start Address - RBSA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xac); - - /// address: 0x420000b0 - /// Rx FIFO 1 Configuration - pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Start Address - F1SA: u16, - /// Rx FIFO 1 Size - F1S: u7, - reserved0: u1, - /// Rx FIFO 1 Watermark - F1WM: u7, - /// FIFO 1 Operation Mode - F1OM: u1, - }), base_address + 0xb0); - - /// address: 0x420000b4 - /// Rx FIFO 1 Status - pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Fill Level - F1FL: u7, - reserved0: u1, - /// Rx FIFO 1 Get Index - F1GI: u6, - reserved1: u1, - reserved2: u1, - /// Rx FIFO 1 Put Index - F1PI: u6, - reserved3: u1, - reserved4: u1, - /// Rx FIFO 1 Full - F1F: u1, - /// Rx FIFO 1 Message Lost - RF1L: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Debug Message Status - DMS: u2, - }), base_address + 0xb4); - - /// address: 0x420000b8 - /// Rx FIFO 1 Acknowledge - pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Acknowledge Index - F1AI: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xb8); - - /// address: 0x420000bc - /// Rx Buffer / FIFO Element Size Configuration - pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Data Field Size - F0DS: u3, - reserved0: u1, - /// Rx FIFO 1 Data Field Size - F1DS: u3, - reserved1: u1, - /// Rx Buffer Data Field Size - RBDS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xbc); - - /// address: 0x420000c0 - /// Tx Buffer Configuration - pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffers Start Address - TBSA: u16, - /// Number of Dedicated Transmit Buffers - NDTB: u6, - reserved0: u1, - reserved1: u1, - /// Transmit FIFO/Queue Size - TFQS: u6, - /// Tx FIFO/Queue Mode - TFQM: u1, - padding0: u1, - }), base_address + 0xc0); - - /// address: 0x420000c4 - /// Tx FIFO / Queue Status - pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx FIFO Free Level - TFFL: u6, - reserved0: u1, - reserved1: u1, - /// Tx FIFO Get Index - TFGI: u5, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Tx FIFO/Queue Put Index - TFQPI: u5, - /// Tx FIFO/Queue Full - TFQF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0xc4); - - /// address: 0x420000c8 - /// Tx Buffer Element Size Configuration - pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffer Data Field Size - TBDS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0xc8); - - /// address: 0x420000cc - /// Tx Buffer Request Pending - pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Request Pending 0 - TRP0: u1, - /// Transmission Request Pending 1 - TRP1: u1, - /// Transmission Request Pending 2 - TRP2: u1, - /// Transmission Request Pending 3 - TRP3: u1, - /// Transmission Request Pending 4 - TRP4: u1, - /// Transmission Request Pending 5 - TRP5: u1, - /// Transmission Request Pending 6 - TRP6: u1, - /// Transmission Request Pending 7 - TRP7: u1, - /// Transmission Request Pending 8 - TRP8: u1, - /// Transmission Request Pending 9 - TRP9: u1, - /// Transmission Request Pending 10 - TRP10: u1, - /// Transmission Request Pending 11 - TRP11: u1, - /// Transmission Request Pending 12 - TRP12: u1, - /// Transmission Request Pending 13 - TRP13: u1, - /// Transmission Request Pending 14 - TRP14: u1, - /// Transmission Request Pending 15 - TRP15: u1, - /// Transmission Request Pending 16 - TRP16: u1, - /// Transmission Request Pending 17 - TRP17: u1, - /// Transmission Request Pending 18 - TRP18: u1, - /// Transmission Request Pending 19 - TRP19: u1, - /// Transmission Request Pending 20 - TRP20: u1, - /// Transmission Request Pending 21 - TRP21: u1, - /// Transmission Request Pending 22 - TRP22: u1, - /// Transmission Request Pending 23 - TRP23: u1, - /// Transmission Request Pending 24 - TRP24: u1, - /// Transmission Request Pending 25 - TRP25: u1, - /// Transmission Request Pending 26 - TRP26: u1, - /// Transmission Request Pending 27 - TRP27: u1, - /// Transmission Request Pending 28 - TRP28: u1, - /// Transmission Request Pending 29 - TRP29: u1, - /// Transmission Request Pending 30 - TRP30: u1, - /// Transmission Request Pending 31 - TRP31: u1, - }), base_address + 0xcc); - - /// address: 0x420000d0 - /// Tx Buffer Add Request - pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Add Request 0 - AR0: u1, - /// Add Request 1 - AR1: u1, - /// Add Request 2 - AR2: u1, - /// Add Request 3 - AR3: u1, - /// Add Request 4 - AR4: u1, - /// Add Request 5 - AR5: u1, - /// Add Request 6 - AR6: u1, - /// Add Request 7 - AR7: u1, - /// Add Request 8 - AR8: u1, - /// Add Request 9 - AR9: u1, - /// Add Request 10 - AR10: u1, - /// Add Request 11 - AR11: u1, - /// Add Request 12 - AR12: u1, - /// Add Request 13 - AR13: u1, - /// Add Request 14 - AR14: u1, - /// Add Request 15 - AR15: u1, - /// Add Request 16 - AR16: u1, - /// Add Request 17 - AR17: u1, - /// Add Request 18 - AR18: u1, - /// Add Request 19 - AR19: u1, - /// Add Request 20 - AR20: u1, - /// Add Request 21 - AR21: u1, - /// Add Request 22 - AR22: u1, - /// Add Request 23 - AR23: u1, - /// Add Request 24 - AR24: u1, - /// Add Request 25 - AR25: u1, - /// Add Request 26 - AR26: u1, - /// Add Request 27 - AR27: u1, - /// Add Request 28 - AR28: u1, - /// Add Request 29 - AR29: u1, - /// Add Request 30 - AR30: u1, - /// Add Request 31 - AR31: u1, - }), base_address + 0xd0); - - /// address: 0x420000d4 - /// Tx Buffer Cancellation Request - pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Cancellation Request 0 - CR0: u1, - /// Cancellation Request 1 - CR1: u1, - /// Cancellation Request 2 - CR2: u1, - /// Cancellation Request 3 - CR3: u1, - /// Cancellation Request 4 - CR4: u1, - /// Cancellation Request 5 - CR5: u1, - /// Cancellation Request 6 - CR6: u1, - /// Cancellation Request 7 - CR7: u1, - /// Cancellation Request 8 - CR8: u1, - /// Cancellation Request 9 - CR9: u1, - /// Cancellation Request 10 - CR10: u1, - /// Cancellation Request 11 - CR11: u1, - /// Cancellation Request 12 - CR12: u1, - /// Cancellation Request 13 - CR13: u1, - /// Cancellation Request 14 - CR14: u1, - /// Cancellation Request 15 - CR15: u1, - /// Cancellation Request 16 - CR16: u1, - /// Cancellation Request 17 - CR17: u1, - /// Cancellation Request 18 - CR18: u1, - /// Cancellation Request 19 - CR19: u1, - /// Cancellation Request 20 - CR20: u1, - /// Cancellation Request 21 - CR21: u1, - /// Cancellation Request 22 - CR22: u1, - /// Cancellation Request 23 - CR23: u1, - /// Cancellation Request 24 - CR24: u1, - /// Cancellation Request 25 - CR25: u1, - /// Cancellation Request 26 - CR26: u1, - /// Cancellation Request 27 - CR27: u1, - /// Cancellation Request 28 - CR28: u1, - /// Cancellation Request 29 - CR29: u1, - /// Cancellation Request 30 - CR30: u1, - /// Cancellation Request 31 - CR31: u1, - }), base_address + 0xd4); - - /// address: 0x420000d8 - /// Tx Buffer Transmission Occurred - pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Occurred 0 - TO0: u1, - /// Transmission Occurred 1 - TO1: u1, - /// Transmission Occurred 2 - TO2: u1, - /// Transmission Occurred 3 - TO3: u1, - /// Transmission Occurred 4 - TO4: u1, - /// Transmission Occurred 5 - TO5: u1, - /// Transmission Occurred 6 - TO6: u1, - /// Transmission Occurred 7 - TO7: u1, - /// Transmission Occurred 8 - TO8: u1, - /// Transmission Occurred 9 - TO9: u1, - /// Transmission Occurred 10 - TO10: u1, - /// Transmission Occurred 11 - TO11: u1, - /// Transmission Occurred 12 - TO12: u1, - /// Transmission Occurred 13 - TO13: u1, - /// Transmission Occurred 14 - TO14: u1, - /// Transmission Occurred 15 - TO15: u1, - /// Transmission Occurred 16 - TO16: u1, - /// Transmission Occurred 17 - TO17: u1, - /// Transmission Occurred 18 - TO18: u1, - /// Transmission Occurred 19 - TO19: u1, - /// Transmission Occurred 20 - TO20: u1, - /// Transmission Occurred 21 - TO21: u1, - /// Transmission Occurred 22 - TO22: u1, - /// Transmission Occurred 23 - TO23: u1, - /// Transmission Occurred 24 - TO24: u1, - /// Transmission Occurred 25 - TO25: u1, - /// Transmission Occurred 26 - TO26: u1, - /// Transmission Occurred 27 - TO27: u1, - /// Transmission Occurred 28 - TO28: u1, - /// Transmission Occurred 29 - TO29: u1, - /// Transmission Occurred 30 - TO30: u1, - /// Transmission Occurred 31 - TO31: u1, - }), base_address + 0xd8); - - /// address: 0x420000dc - /// Tx Buffer Cancellation Finished - pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffer Cancellation Finished 0 - CF0: u1, - /// Tx Buffer Cancellation Finished 1 - CF1: u1, - /// Tx Buffer Cancellation Finished 2 - CF2: u1, - /// Tx Buffer Cancellation Finished 3 - CF3: u1, - /// Tx Buffer Cancellation Finished 4 - CF4: u1, - /// Tx Buffer Cancellation Finished 5 - CF5: u1, - /// Tx Buffer Cancellation Finished 6 - CF6: u1, - /// Tx Buffer Cancellation Finished 7 - CF7: u1, - /// Tx Buffer Cancellation Finished 8 - CF8: u1, - /// Tx Buffer Cancellation Finished 9 - CF9: u1, - /// Tx Buffer Cancellation Finished 10 - CF10: u1, - /// Tx Buffer Cancellation Finished 11 - CF11: u1, - /// Tx Buffer Cancellation Finished 12 - CF12: u1, - /// Tx Buffer Cancellation Finished 13 - CF13: u1, - /// Tx Buffer Cancellation Finished 14 - CF14: u1, - /// Tx Buffer Cancellation Finished 15 - CF15: u1, - /// Tx Buffer Cancellation Finished 16 - CF16: u1, - /// Tx Buffer Cancellation Finished 17 - CF17: u1, - /// Tx Buffer Cancellation Finished 18 - CF18: u1, - /// Tx Buffer Cancellation Finished 19 - CF19: u1, - /// Tx Buffer Cancellation Finished 20 - CF20: u1, - /// Tx Buffer Cancellation Finished 21 - CF21: u1, - /// Tx Buffer Cancellation Finished 22 - CF22: u1, - /// Tx Buffer Cancellation Finished 23 - CF23: u1, - /// Tx Buffer Cancellation Finished 24 - CF24: u1, - /// Tx Buffer Cancellation Finished 25 - CF25: u1, - /// Tx Buffer Cancellation Finished 26 - CF26: u1, - /// Tx Buffer Cancellation Finished 27 - CF27: u1, - /// Tx Buffer Cancellation Finished 28 - CF28: u1, - /// Tx Buffer Cancellation Finished 29 - CF29: u1, - /// Tx Buffer Cancellation Finished 30 - CF30: u1, - /// Tx Buffer Cancellation Finished 31 - CF31: u1, - }), base_address + 0xdc); - - /// address: 0x420000e0 - /// Tx Buffer Transmission Interrupt Enable - pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Interrupt Enable 0 - TIE0: u1, - /// Transmission Interrupt Enable 1 - TIE1: u1, - /// Transmission Interrupt Enable 2 - TIE2: u1, - /// Transmission Interrupt Enable 3 - TIE3: u1, - /// Transmission Interrupt Enable 4 - TIE4: u1, - /// Transmission Interrupt Enable 5 - TIE5: u1, - /// Transmission Interrupt Enable 6 - TIE6: u1, - /// Transmission Interrupt Enable 7 - TIE7: u1, - /// Transmission Interrupt Enable 8 - TIE8: u1, - /// Transmission Interrupt Enable 9 - TIE9: u1, - /// Transmission Interrupt Enable 10 - TIE10: u1, - /// Transmission Interrupt Enable 11 - TIE11: u1, - /// Transmission Interrupt Enable 12 - TIE12: u1, - /// Transmission Interrupt Enable 13 - TIE13: u1, - /// Transmission Interrupt Enable 14 - TIE14: u1, - /// Transmission Interrupt Enable 15 - TIE15: u1, - /// Transmission Interrupt Enable 16 - TIE16: u1, - /// Transmission Interrupt Enable 17 - TIE17: u1, - /// Transmission Interrupt Enable 18 - TIE18: u1, - /// Transmission Interrupt Enable 19 - TIE19: u1, - /// Transmission Interrupt Enable 20 - TIE20: u1, - /// Transmission Interrupt Enable 21 - TIE21: u1, - /// Transmission Interrupt Enable 22 - TIE22: u1, - /// Transmission Interrupt Enable 23 - TIE23: u1, - /// Transmission Interrupt Enable 24 - TIE24: u1, - /// Transmission Interrupt Enable 25 - TIE25: u1, - /// Transmission Interrupt Enable 26 - TIE26: u1, - /// Transmission Interrupt Enable 27 - TIE27: u1, - /// Transmission Interrupt Enable 28 - TIE28: u1, - /// Transmission Interrupt Enable 29 - TIE29: u1, - /// Transmission Interrupt Enable 30 - TIE30: u1, - /// Transmission Interrupt Enable 31 - TIE31: u1, - }), base_address + 0xe0); - - /// address: 0x420000e4 - /// Tx Buffer Cancellation Finished Interrupt Enable - pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { - /// Cancellation Finished Interrupt Enable 0 - CFIE0: u1, - /// Cancellation Finished Interrupt Enable 1 - CFIE1: u1, - /// Cancellation Finished Interrupt Enable 2 - CFIE2: u1, - /// Cancellation Finished Interrupt Enable 3 - CFIE3: u1, - /// Cancellation Finished Interrupt Enable 4 - CFIE4: u1, - /// Cancellation Finished Interrupt Enable 5 - CFIE5: u1, - /// Cancellation Finished Interrupt Enable 6 - CFIE6: u1, - /// Cancellation Finished Interrupt Enable 7 - CFIE7: u1, - /// Cancellation Finished Interrupt Enable 8 - CFIE8: u1, - /// Cancellation Finished Interrupt Enable 9 - CFIE9: u1, - /// Cancellation Finished Interrupt Enable 10 - CFIE10: u1, - /// Cancellation Finished Interrupt Enable 11 - CFIE11: u1, - /// Cancellation Finished Interrupt Enable 12 - CFIE12: u1, - /// Cancellation Finished Interrupt Enable 13 - CFIE13: u1, - /// Cancellation Finished Interrupt Enable 14 - CFIE14: u1, - /// Cancellation Finished Interrupt Enable 15 - CFIE15: u1, - /// Cancellation Finished Interrupt Enable 16 - CFIE16: u1, - /// Cancellation Finished Interrupt Enable 17 - CFIE17: u1, - /// Cancellation Finished Interrupt Enable 18 - CFIE18: u1, - /// Cancellation Finished Interrupt Enable 19 - CFIE19: u1, - /// Cancellation Finished Interrupt Enable 20 - CFIE20: u1, - /// Cancellation Finished Interrupt Enable 21 - CFIE21: u1, - /// Cancellation Finished Interrupt Enable 22 - CFIE22: u1, - /// Cancellation Finished Interrupt Enable 23 - CFIE23: u1, - /// Cancellation Finished Interrupt Enable 24 - CFIE24: u1, - /// Cancellation Finished Interrupt Enable 25 - CFIE25: u1, - /// Cancellation Finished Interrupt Enable 26 - CFIE26: u1, - /// Cancellation Finished Interrupt Enable 27 - CFIE27: u1, - /// Cancellation Finished Interrupt Enable 28 - CFIE28: u1, - /// Cancellation Finished Interrupt Enable 29 - CFIE29: u1, - /// Cancellation Finished Interrupt Enable 30 - CFIE30: u1, - /// Cancellation Finished Interrupt Enable 31 - CFIE31: u1, - }), base_address + 0xe4); - - /// address: 0x420000f0 - /// Tx Event FIFO Configuration - pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Start Address - EFSA: u16, - /// Event FIFO Size - EFS: u6, - reserved0: u1, - reserved1: u1, - /// Event FIFO Watermark - EFWM: u6, - padding0: u1, - padding1: u1, - }), base_address + 0xf0); - - /// address: 0x420000f4 - /// Tx Event FIFO Status - pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Fill Level - EFFL: u6, - reserved0: u1, - reserved1: u1, - /// Event FIFO Get Index - EFGI: u5, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Event FIFO Put Index - EFPI: u5, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Event FIFO Full - EFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xf4); - - /// address: 0x420000f8 - /// Tx Event FIFO Acknowledge - pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Acknowledge Index - EFAI: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xf8); - }; - pub const CAN1 = struct { - pub const base_address = 0x42000400; - - /// address: 0x42000400 - /// Core Release - pub const CREL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Sub-step of Core Release - SUBSTEP: u4, - /// Step of Core Release - STEP: u4, - /// Core Release - REL: u4, - }), base_address + 0x0); - - /// address: 0x42000404 - /// Endian - pub const ENDN = @intToPtr(*volatile Mmio(32, packed struct { - /// Endianness Test Value - ETV: u32, - }), base_address + 0x4); - - /// address: 0x42000408 - /// Message RAM Configuration - pub const MRCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Quality of Service - QOS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x8); - - /// address: 0x4200040c - /// Fast Bit Timing and Prescaler - pub const DBTP = @intToPtr(*volatile Mmio(32, packed struct { - /// Data (Re)Synchronization Jump Width - DSJW: u4, - /// Data time segment after sample point - DTSEG2: u4, - /// Data time segment before sample point - DTSEG1: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Data Baud Rate Prescaler - DBRP: u5, - reserved3: u1, - reserved4: u1, - /// Tranceiver Delay Compensation - TDC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x42000410 - /// Test - pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Loop Back Mode - LBCK: u1, - /// Control of Transmit Pin - TX: u2, - /// Receive Pin - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x42000414 - /// RAM Watchdog - pub const RWD = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog Configuration - WDC: u8, - /// Watchdog Value - WDV: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x42000418 - /// CC Control - pub const CCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Initialization - INIT: u1, - /// Configuration Change Enable - CCE: u1, - /// ASM Restricted Operation Mode - ASM: u1, - /// Clock Stop Acknowledge - CSA: u1, - /// Clock Stop Request - CSR: u1, - /// Bus Monitoring Mode - MON: u1, - /// Disable Automatic Retransmission - DAR: u1, - /// Test Mode Enable - TEST: u1, - /// FD Operation Enable - FDOE: u1, - /// Bit Rate Switch Enable - BRSE: u1, - reserved0: u1, - reserved1: u1, - /// Protocol Exception Handling Disable - PXHD: u1, - /// Edge Filtering during Bus Integration - EFBI: u1, - /// Transmit Pause - TXP: u1, - /// Non ISO Operation - NISO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4200041c - /// Nominal Bit Timing and Prescaler - pub const NBTP = @intToPtr(*volatile Mmio(32, packed struct { - /// Nominal Time segment after sample point - NTSEG2: u7, - reserved0: u1, - /// Nominal Time segment before sample point - NTSEG1: u8, - /// Nominal Baud Rate Prescaler - NBRP: u9, - /// Nominal (Re)Synchronization Jump Width - NSJW: u7, - }), base_address + 0x1c); - - /// address: 0x42000420 - /// Timestamp Counter Configuration - pub const TSCC = @intToPtr(*volatile Mmio(32, packed struct { - /// Timestamp Select - TSS: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Timestamp Counter Prescaler - TCP: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x20); - - /// address: 0x42000424 - /// Timestamp Counter Value - pub const TSCV = @intToPtr(*volatile Mmio(32, packed struct { - /// Timestamp Counter - TSC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x42000428 - /// Timeout Counter Configuration - pub const TOCC = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Timeout Counter - ETOC: u1, - /// Timeout Select - TOS: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Timeout Period - TOP: u16, - }), base_address + 0x28); - - /// address: 0x4200042c - /// Timeout Counter Value - pub const TOCV = @intToPtr(*volatile Mmio(32, packed struct { - /// Timeout Counter - TOC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x42000440 - /// Error Counter - pub const ECR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit Error Counter - TEC: u8, - /// Receive Error Counter - REC: u7, - /// Receive Error Passive - RP: u1, - /// CAN Error Logging - CEL: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42000444 - /// Protocol Status - pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Last Error Code - LEC: u3, - /// Activity - ACT: u2, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Data Phase Last Error Code - DLEC: u3, - /// ESI flag of last received CAN FD Message - RESI: u1, - /// BRS flag of last received CAN FD Message - RBRS: u1, - /// Received a CAN FD Message - RFDF: u1, - /// Protocol Exception Event - PXE: u1, - reserved0: u1, - /// Transmitter Delay Compensation Value - TDCV: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x44); - - /// address: 0x42000448 - /// Extended ID Filter Configuration - pub const TDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmitter Delay Compensation Filter Length - TDCF: u7, - reserved0: u1, - /// Transmitter Delay Compensation Offset - TDCO: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x48); - - /// address: 0x42000450 - /// Interrupt - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message - RF0N: u1, - /// Rx FIFO 0 Watermark Reached - RF0W: u1, - /// Rx FIFO 0 Full - RF0F: u1, - /// Rx FIFO 0 Message Lost - RF0L: u1, - /// Rx FIFO 1 New Message - RF1N: u1, - /// Rx FIFO 1 Watermark Reached - RF1W: u1, - /// Rx FIFO 1 FIFO Full - RF1F: u1, - /// Rx FIFO 1 Message Lost - RF1L: u1, - /// High Priority Message - HPM: u1, - /// Timestamp Completed - TC: u1, - /// Transmission Cancellation Finished - TCF: u1, - /// Tx FIFO Empty - TFE: u1, - /// Tx Event FIFO New Entry - TEFN: u1, - /// Tx Event FIFO Watermark Reached - TEFW: u1, - /// Tx Event FIFO Full - TEFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - /// Timestamp Wraparound - TSW: u1, - /// Message RAM Access Failure - MRAF: u1, - /// Timeout Occurred - TOO: u1, - /// Message stored to Dedicated Rx Buffer - DRX: u1, - /// Bit Error Corrected - BEC: u1, - /// Bit Error Uncorrected - BEU: u1, - /// Error Logging Overflow - ELO: u1, - /// Error Passive - EP: u1, - /// Warning Status - EW: u1, - /// Bus_Off Status - BO: u1, - /// Watchdog Interrupt - WDI: u1, - /// Protocol Error in Arbitration Phase - PEA: u1, - /// Protocol Error in Data Phase - PED: u1, - /// Access to Reserved Address - ARA: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x50); - - /// address: 0x42000454 - /// Interrupt Enable - pub const IE = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message Interrupt Enable - RF0NE: u1, - /// Rx FIFO 0 Watermark Reached Interrupt Enable - RF0WE: u1, - /// Rx FIFO 0 Full Interrupt Enable - RF0FE: u1, - /// Rx FIFO 0 Message Lost Interrupt Enable - RF0LE: u1, - /// Rx FIFO 1 New Message Interrupt Enable - RF1NE: u1, - /// Rx FIFO 1 Watermark Reached Interrupt Enable - RF1WE: u1, - /// Rx FIFO 1 FIFO Full Interrupt Enable - RF1FE: u1, - /// Rx FIFO 1 Message Lost Interrupt Enable - RF1LE: u1, - /// High Priority Message Interrupt Enable - HPME: u1, - /// Timestamp Completed Interrupt Enable - TCE: u1, - /// Transmission Cancellation Finished Interrupt Enable - TCFE: u1, - /// Tx FIFO Empty Interrupt Enable - TFEE: u1, - /// Tx Event FIFO New Entry Interrupt Enable - TEFNE: u1, - /// Tx Event FIFO Watermark Reached Interrupt Enable - TEFWE: u1, - /// Tx Event FIFO Full Interrupt Enable - TEFFE: u1, - /// Tx Event FIFO Element Lost Interrupt Enable - TEFLE: u1, - /// Timestamp Wraparound Interrupt Enable - TSWE: u1, - /// Message RAM Access Failure Interrupt Enable - MRAFE: u1, - /// Timeout Occurred Interrupt Enable - TOOE: u1, - /// Message stored to Dedicated Rx Buffer Interrupt Enable - DRXE: u1, - /// Bit Error Corrected Interrupt Enable - BECE: u1, - /// Bit Error Uncorrected Interrupt Enable - BEUE: u1, - /// Error Logging Overflow Interrupt Enable - ELOE: u1, - /// Error Passive Interrupt Enable - EPE: u1, - /// Warning Status Interrupt Enable - EWE: u1, - /// Bus_Off Status Interrupt Enable - BOE: u1, - /// Watchdog Interrupt Interrupt Enable - WDIE: u1, - /// Protocol Error in Arbitration Phase Enable - PEAE: u1, - /// Protocol Error in Data Phase Enable - PEDE: u1, - /// Access to Reserved Address Enable - ARAE: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x54); - - /// address: 0x42000458 - /// Interrupt Line Select - pub const ILS = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 New Message Interrupt Line - RF0NL: u1, - /// Rx FIFO 0 Watermark Reached Interrupt Line - RF0WL: u1, - /// Rx FIFO 0 Full Interrupt Line - RF0FL: u1, - /// Rx FIFO 0 Message Lost Interrupt Line - RF0LL: u1, - /// Rx FIFO 1 New Message Interrupt Line - RF1NL: u1, - /// Rx FIFO 1 Watermark Reached Interrupt Line - RF1WL: u1, - /// Rx FIFO 1 FIFO Full Interrupt Line - RF1FL: u1, - /// Rx FIFO 1 Message Lost Interrupt Line - RF1LL: u1, - /// High Priority Message Interrupt Line - HPML: u1, - /// Timestamp Completed Interrupt Line - TCL: u1, - /// Transmission Cancellation Finished Interrupt Line - TCFL: u1, - /// Tx FIFO Empty Interrupt Line - TFEL: u1, - /// Tx Event FIFO New Entry Interrupt Line - TEFNL: u1, - /// Tx Event FIFO Watermark Reached Interrupt Line - TEFWL: u1, - /// Tx Event FIFO Full Interrupt Line - TEFFL: u1, - /// Tx Event FIFO Element Lost Interrupt Line - TEFLL: u1, - /// Timestamp Wraparound Interrupt Line - TSWL: u1, - /// Message RAM Access Failure Interrupt Line - MRAFL: u1, - /// Timeout Occurred Interrupt Line - TOOL: u1, - /// Message stored to Dedicated Rx Buffer Interrupt Line - DRXL: u1, - /// Bit Error Corrected Interrupt Line - BECL: u1, - /// Bit Error Uncorrected Interrupt Line - BEUL: u1, - /// Error Logging Overflow Interrupt Line - ELOL: u1, - /// Error Passive Interrupt Line - EPL: u1, - /// Warning Status Interrupt Line - EWL: u1, - /// Bus_Off Status Interrupt Line - BOL: u1, - /// Watchdog Interrupt Interrupt Line - WDIL: u1, - /// Protocol Error in Arbitration Phase Line - PEAL: u1, - /// Protocol Error in Data Phase Line - PEDL: u1, - /// Access to Reserved Address Line - ARAL: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x58); - - /// address: 0x4200045c - /// Interrupt Line Enable - pub const ILE = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Interrupt Line 0 - EINT0: u1, - /// Enable Interrupt Line 1 - EINT1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x5c); - - /// address: 0x42000480 - /// Global Filter Configuration - pub const GFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Reject Remote Frames Extended - RRFE: u1, - /// Reject Remote Frames Standard - RRFS: u1, - /// Accept Non-matching Frames Extended - ANFE: u2, - /// Accept Non-matching Frames Standard - ANFS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x80); - - /// address: 0x42000484 - /// Standard ID Filter Configuration - pub const SIDFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter List Standard Start Address - FLSSA: u16, - /// List Size Standard - LSS: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x84); - - /// address: 0x42000488 - /// Extended ID Filter Configuration - pub const XIDFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter List Extended Start Address - FLESA: u16, - /// List Size Extended - LSE: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x88); - - /// address: 0x42000490 - /// Extended ID AND Mask - pub const XIDAM = @intToPtr(*volatile Mmio(32, packed struct { - /// Extended ID Mask - EIDM: u29, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x90); - - /// address: 0x42000494 - /// High Priority Message Status - pub const HPMS = @intToPtr(*volatile Mmio(32, packed struct { - /// Buffer Index - BIDX: u6, - /// Message Storage Indicator - MSI: u2, - /// Filter Index - FIDX: u7, - /// Filter List - FLST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x94); - - /// address: 0x42000498 - /// New Data 1 - pub const NDAT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// New Data 0 - ND0: u1, - /// New Data 1 - ND1: u1, - /// New Data 2 - ND2: u1, - /// New Data 3 - ND3: u1, - /// New Data 4 - ND4: u1, - /// New Data 5 - ND5: u1, - /// New Data 6 - ND6: u1, - /// New Data 7 - ND7: u1, - /// New Data 8 - ND8: u1, - /// New Data 9 - ND9: u1, - /// New Data 10 - ND10: u1, - /// New Data 11 - ND11: u1, - /// New Data 12 - ND12: u1, - /// New Data 13 - ND13: u1, - /// New Data 14 - ND14: u1, - /// New Data 15 - ND15: u1, - /// New Data 16 - ND16: u1, - /// New Data 17 - ND17: u1, - /// New Data 18 - ND18: u1, - /// New Data 19 - ND19: u1, - /// New Data 20 - ND20: u1, - /// New Data 21 - ND21: u1, - /// New Data 22 - ND22: u1, - /// New Data 23 - ND23: u1, - /// New Data 24 - ND24: u1, - /// New Data 25 - ND25: u1, - /// New Data 26 - ND26: u1, - /// New Data 27 - ND27: u1, - /// New Data 28 - ND28: u1, - /// New Data 29 - ND29: u1, - /// New Data 30 - ND30: u1, - /// New Data 31 - ND31: u1, - }), base_address + 0x98); - - /// address: 0x4200049c - /// New Data 2 - pub const NDAT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// New Data 32 - ND32: u1, - /// New Data 33 - ND33: u1, - /// New Data 34 - ND34: u1, - /// New Data 35 - ND35: u1, - /// New Data 36 - ND36: u1, - /// New Data 37 - ND37: u1, - /// New Data 38 - ND38: u1, - /// New Data 39 - ND39: u1, - /// New Data 40 - ND40: u1, - /// New Data 41 - ND41: u1, - /// New Data 42 - ND42: u1, - /// New Data 43 - ND43: u1, - /// New Data 44 - ND44: u1, - /// New Data 45 - ND45: u1, - /// New Data 46 - ND46: u1, - /// New Data 47 - ND47: u1, - /// New Data 48 - ND48: u1, - /// New Data 49 - ND49: u1, - /// New Data 50 - ND50: u1, - /// New Data 51 - ND51: u1, - /// New Data 52 - ND52: u1, - /// New Data 53 - ND53: u1, - /// New Data 54 - ND54: u1, - /// New Data 55 - ND55: u1, - /// New Data 56 - ND56: u1, - /// New Data 57 - ND57: u1, - /// New Data 58 - ND58: u1, - /// New Data 59 - ND59: u1, - /// New Data 60 - ND60: u1, - /// New Data 61 - ND61: u1, - /// New Data 62 - ND62: u1, - /// New Data 63 - ND63: u1, - }), base_address + 0x9c); - - /// address: 0x420004a0 - /// Rx FIFO 0 Configuration - pub const RXF0C = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Start Address - F0SA: u16, - /// Rx FIFO 0 Size - F0S: u7, - reserved0: u1, - /// Rx FIFO 0 Watermark - F0WM: u7, - /// FIFO 0 Operation Mode - F0OM: u1, - }), base_address + 0xa0); - - /// address: 0x420004a4 - /// Rx FIFO 0 Status - pub const RXF0S = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Fill Level - F0FL: u7, - reserved0: u1, - /// Rx FIFO 0 Get Index - F0GI: u6, - reserved1: u1, - reserved2: u1, - /// Rx FIFO 0 Put Index - F0PI: u6, - reserved3: u1, - reserved4: u1, - /// Rx FIFO 0 Full - F0F: u1, - /// Rx FIFO 0 Message Lost - RF0L: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xa4); - - /// address: 0x420004a8 - /// Rx FIFO 0 Acknowledge - pub const RXF0A = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Acknowledge Index - F0AI: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xa8); - - /// address: 0x420004ac - /// Rx Buffer Configuration - pub const RXBC = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx Buffer Start Address - RBSA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xac); - - /// address: 0x420004b0 - /// Rx FIFO 1 Configuration - pub const RXF1C = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Start Address - F1SA: u16, - /// Rx FIFO 1 Size - F1S: u7, - reserved0: u1, - /// Rx FIFO 1 Watermark - F1WM: u7, - /// FIFO 1 Operation Mode - F1OM: u1, - }), base_address + 0xb0); - - /// address: 0x420004b4 - /// Rx FIFO 1 Status - pub const RXF1S = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Fill Level - F1FL: u7, - reserved0: u1, - /// Rx FIFO 1 Get Index - F1GI: u6, - reserved1: u1, - reserved2: u1, - /// Rx FIFO 1 Put Index - F1PI: u6, - reserved3: u1, - reserved4: u1, - /// Rx FIFO 1 Full - F1F: u1, - /// Rx FIFO 1 Message Lost - RF1L: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Debug Message Status - DMS: u2, - }), base_address + 0xb4); - - /// address: 0x420004b8 - /// Rx FIFO 1 Acknowledge - pub const RXF1A = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 1 Acknowledge Index - F1AI: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xb8); - - /// address: 0x420004bc - /// Rx Buffer / FIFO Element Size Configuration - pub const RXESC = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO 0 Data Field Size - F0DS: u3, - reserved0: u1, - /// Rx FIFO 1 Data Field Size - F1DS: u3, - reserved1: u1, - /// Rx Buffer Data Field Size - RBDS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xbc); - - /// address: 0x420004c0 - /// Tx Buffer Configuration - pub const TXBC = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffers Start Address - TBSA: u16, - /// Number of Dedicated Transmit Buffers - NDTB: u6, - reserved0: u1, - reserved1: u1, - /// Transmit FIFO/Queue Size - TFQS: u6, - /// Tx FIFO/Queue Mode - TFQM: u1, - padding0: u1, - }), base_address + 0xc0); - - /// address: 0x420004c4 - /// Tx FIFO / Queue Status - pub const TXFQS = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx FIFO Free Level - TFFL: u6, - reserved0: u1, - reserved1: u1, - /// Tx FIFO Get Index - TFGI: u5, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Tx FIFO/Queue Put Index - TFQPI: u5, - /// Tx FIFO/Queue Full - TFQF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0xc4); - - /// address: 0x420004c8 - /// Tx Buffer Element Size Configuration - pub const TXESC = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffer Data Field Size - TBDS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0xc8); - - /// address: 0x420004cc - /// Tx Buffer Request Pending - pub const TXBRP = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Request Pending 0 - TRP0: u1, - /// Transmission Request Pending 1 - TRP1: u1, - /// Transmission Request Pending 2 - TRP2: u1, - /// Transmission Request Pending 3 - TRP3: u1, - /// Transmission Request Pending 4 - TRP4: u1, - /// Transmission Request Pending 5 - TRP5: u1, - /// Transmission Request Pending 6 - TRP6: u1, - /// Transmission Request Pending 7 - TRP7: u1, - /// Transmission Request Pending 8 - TRP8: u1, - /// Transmission Request Pending 9 - TRP9: u1, - /// Transmission Request Pending 10 - TRP10: u1, - /// Transmission Request Pending 11 - TRP11: u1, - /// Transmission Request Pending 12 - TRP12: u1, - /// Transmission Request Pending 13 - TRP13: u1, - /// Transmission Request Pending 14 - TRP14: u1, - /// Transmission Request Pending 15 - TRP15: u1, - /// Transmission Request Pending 16 - TRP16: u1, - /// Transmission Request Pending 17 - TRP17: u1, - /// Transmission Request Pending 18 - TRP18: u1, - /// Transmission Request Pending 19 - TRP19: u1, - /// Transmission Request Pending 20 - TRP20: u1, - /// Transmission Request Pending 21 - TRP21: u1, - /// Transmission Request Pending 22 - TRP22: u1, - /// Transmission Request Pending 23 - TRP23: u1, - /// Transmission Request Pending 24 - TRP24: u1, - /// Transmission Request Pending 25 - TRP25: u1, - /// Transmission Request Pending 26 - TRP26: u1, - /// Transmission Request Pending 27 - TRP27: u1, - /// Transmission Request Pending 28 - TRP28: u1, - /// Transmission Request Pending 29 - TRP29: u1, - /// Transmission Request Pending 30 - TRP30: u1, - /// Transmission Request Pending 31 - TRP31: u1, - }), base_address + 0xcc); - - /// address: 0x420004d0 - /// Tx Buffer Add Request - pub const TXBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Add Request 0 - AR0: u1, - /// Add Request 1 - AR1: u1, - /// Add Request 2 - AR2: u1, - /// Add Request 3 - AR3: u1, - /// Add Request 4 - AR4: u1, - /// Add Request 5 - AR5: u1, - /// Add Request 6 - AR6: u1, - /// Add Request 7 - AR7: u1, - /// Add Request 8 - AR8: u1, - /// Add Request 9 - AR9: u1, - /// Add Request 10 - AR10: u1, - /// Add Request 11 - AR11: u1, - /// Add Request 12 - AR12: u1, - /// Add Request 13 - AR13: u1, - /// Add Request 14 - AR14: u1, - /// Add Request 15 - AR15: u1, - /// Add Request 16 - AR16: u1, - /// Add Request 17 - AR17: u1, - /// Add Request 18 - AR18: u1, - /// Add Request 19 - AR19: u1, - /// Add Request 20 - AR20: u1, - /// Add Request 21 - AR21: u1, - /// Add Request 22 - AR22: u1, - /// Add Request 23 - AR23: u1, - /// Add Request 24 - AR24: u1, - /// Add Request 25 - AR25: u1, - /// Add Request 26 - AR26: u1, - /// Add Request 27 - AR27: u1, - /// Add Request 28 - AR28: u1, - /// Add Request 29 - AR29: u1, - /// Add Request 30 - AR30: u1, - /// Add Request 31 - AR31: u1, - }), base_address + 0xd0); - - /// address: 0x420004d4 - /// Tx Buffer Cancellation Request - pub const TXBCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Cancellation Request 0 - CR0: u1, - /// Cancellation Request 1 - CR1: u1, - /// Cancellation Request 2 - CR2: u1, - /// Cancellation Request 3 - CR3: u1, - /// Cancellation Request 4 - CR4: u1, - /// Cancellation Request 5 - CR5: u1, - /// Cancellation Request 6 - CR6: u1, - /// Cancellation Request 7 - CR7: u1, - /// Cancellation Request 8 - CR8: u1, - /// Cancellation Request 9 - CR9: u1, - /// Cancellation Request 10 - CR10: u1, - /// Cancellation Request 11 - CR11: u1, - /// Cancellation Request 12 - CR12: u1, - /// Cancellation Request 13 - CR13: u1, - /// Cancellation Request 14 - CR14: u1, - /// Cancellation Request 15 - CR15: u1, - /// Cancellation Request 16 - CR16: u1, - /// Cancellation Request 17 - CR17: u1, - /// Cancellation Request 18 - CR18: u1, - /// Cancellation Request 19 - CR19: u1, - /// Cancellation Request 20 - CR20: u1, - /// Cancellation Request 21 - CR21: u1, - /// Cancellation Request 22 - CR22: u1, - /// Cancellation Request 23 - CR23: u1, - /// Cancellation Request 24 - CR24: u1, - /// Cancellation Request 25 - CR25: u1, - /// Cancellation Request 26 - CR26: u1, - /// Cancellation Request 27 - CR27: u1, - /// Cancellation Request 28 - CR28: u1, - /// Cancellation Request 29 - CR29: u1, - /// Cancellation Request 30 - CR30: u1, - /// Cancellation Request 31 - CR31: u1, - }), base_address + 0xd4); - - /// address: 0x420004d8 - /// Tx Buffer Transmission Occurred - pub const TXBTO = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Occurred 0 - TO0: u1, - /// Transmission Occurred 1 - TO1: u1, - /// Transmission Occurred 2 - TO2: u1, - /// Transmission Occurred 3 - TO3: u1, - /// Transmission Occurred 4 - TO4: u1, - /// Transmission Occurred 5 - TO5: u1, - /// Transmission Occurred 6 - TO6: u1, - /// Transmission Occurred 7 - TO7: u1, - /// Transmission Occurred 8 - TO8: u1, - /// Transmission Occurred 9 - TO9: u1, - /// Transmission Occurred 10 - TO10: u1, - /// Transmission Occurred 11 - TO11: u1, - /// Transmission Occurred 12 - TO12: u1, - /// Transmission Occurred 13 - TO13: u1, - /// Transmission Occurred 14 - TO14: u1, - /// Transmission Occurred 15 - TO15: u1, - /// Transmission Occurred 16 - TO16: u1, - /// Transmission Occurred 17 - TO17: u1, - /// Transmission Occurred 18 - TO18: u1, - /// Transmission Occurred 19 - TO19: u1, - /// Transmission Occurred 20 - TO20: u1, - /// Transmission Occurred 21 - TO21: u1, - /// Transmission Occurred 22 - TO22: u1, - /// Transmission Occurred 23 - TO23: u1, - /// Transmission Occurred 24 - TO24: u1, - /// Transmission Occurred 25 - TO25: u1, - /// Transmission Occurred 26 - TO26: u1, - /// Transmission Occurred 27 - TO27: u1, - /// Transmission Occurred 28 - TO28: u1, - /// Transmission Occurred 29 - TO29: u1, - /// Transmission Occurred 30 - TO30: u1, - /// Transmission Occurred 31 - TO31: u1, - }), base_address + 0xd8); - - /// address: 0x420004dc - /// Tx Buffer Cancellation Finished - pub const TXBCF = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx Buffer Cancellation Finished 0 - CF0: u1, - /// Tx Buffer Cancellation Finished 1 - CF1: u1, - /// Tx Buffer Cancellation Finished 2 - CF2: u1, - /// Tx Buffer Cancellation Finished 3 - CF3: u1, - /// Tx Buffer Cancellation Finished 4 - CF4: u1, - /// Tx Buffer Cancellation Finished 5 - CF5: u1, - /// Tx Buffer Cancellation Finished 6 - CF6: u1, - /// Tx Buffer Cancellation Finished 7 - CF7: u1, - /// Tx Buffer Cancellation Finished 8 - CF8: u1, - /// Tx Buffer Cancellation Finished 9 - CF9: u1, - /// Tx Buffer Cancellation Finished 10 - CF10: u1, - /// Tx Buffer Cancellation Finished 11 - CF11: u1, - /// Tx Buffer Cancellation Finished 12 - CF12: u1, - /// Tx Buffer Cancellation Finished 13 - CF13: u1, - /// Tx Buffer Cancellation Finished 14 - CF14: u1, - /// Tx Buffer Cancellation Finished 15 - CF15: u1, - /// Tx Buffer Cancellation Finished 16 - CF16: u1, - /// Tx Buffer Cancellation Finished 17 - CF17: u1, - /// Tx Buffer Cancellation Finished 18 - CF18: u1, - /// Tx Buffer Cancellation Finished 19 - CF19: u1, - /// Tx Buffer Cancellation Finished 20 - CF20: u1, - /// Tx Buffer Cancellation Finished 21 - CF21: u1, - /// Tx Buffer Cancellation Finished 22 - CF22: u1, - /// Tx Buffer Cancellation Finished 23 - CF23: u1, - /// Tx Buffer Cancellation Finished 24 - CF24: u1, - /// Tx Buffer Cancellation Finished 25 - CF25: u1, - /// Tx Buffer Cancellation Finished 26 - CF26: u1, - /// Tx Buffer Cancellation Finished 27 - CF27: u1, - /// Tx Buffer Cancellation Finished 28 - CF28: u1, - /// Tx Buffer Cancellation Finished 29 - CF29: u1, - /// Tx Buffer Cancellation Finished 30 - CF30: u1, - /// Tx Buffer Cancellation Finished 31 - CF31: u1, - }), base_address + 0xdc); - - /// address: 0x420004e0 - /// Tx Buffer Transmission Interrupt Enable - pub const TXBTIE = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Interrupt Enable 0 - TIE0: u1, - /// Transmission Interrupt Enable 1 - TIE1: u1, - /// Transmission Interrupt Enable 2 - TIE2: u1, - /// Transmission Interrupt Enable 3 - TIE3: u1, - /// Transmission Interrupt Enable 4 - TIE4: u1, - /// Transmission Interrupt Enable 5 - TIE5: u1, - /// Transmission Interrupt Enable 6 - TIE6: u1, - /// Transmission Interrupt Enable 7 - TIE7: u1, - /// Transmission Interrupt Enable 8 - TIE8: u1, - /// Transmission Interrupt Enable 9 - TIE9: u1, - /// Transmission Interrupt Enable 10 - TIE10: u1, - /// Transmission Interrupt Enable 11 - TIE11: u1, - /// Transmission Interrupt Enable 12 - TIE12: u1, - /// Transmission Interrupt Enable 13 - TIE13: u1, - /// Transmission Interrupt Enable 14 - TIE14: u1, - /// Transmission Interrupt Enable 15 - TIE15: u1, - /// Transmission Interrupt Enable 16 - TIE16: u1, - /// Transmission Interrupt Enable 17 - TIE17: u1, - /// Transmission Interrupt Enable 18 - TIE18: u1, - /// Transmission Interrupt Enable 19 - TIE19: u1, - /// Transmission Interrupt Enable 20 - TIE20: u1, - /// Transmission Interrupt Enable 21 - TIE21: u1, - /// Transmission Interrupt Enable 22 - TIE22: u1, - /// Transmission Interrupt Enable 23 - TIE23: u1, - /// Transmission Interrupt Enable 24 - TIE24: u1, - /// Transmission Interrupt Enable 25 - TIE25: u1, - /// Transmission Interrupt Enable 26 - TIE26: u1, - /// Transmission Interrupt Enable 27 - TIE27: u1, - /// Transmission Interrupt Enable 28 - TIE28: u1, - /// Transmission Interrupt Enable 29 - TIE29: u1, - /// Transmission Interrupt Enable 30 - TIE30: u1, - /// Transmission Interrupt Enable 31 - TIE31: u1, - }), base_address + 0xe0); - - /// address: 0x420004e4 - /// Tx Buffer Cancellation Finished Interrupt Enable - pub const TXBCIE = @intToPtr(*volatile Mmio(32, packed struct { - /// Cancellation Finished Interrupt Enable 0 - CFIE0: u1, - /// Cancellation Finished Interrupt Enable 1 - CFIE1: u1, - /// Cancellation Finished Interrupt Enable 2 - CFIE2: u1, - /// Cancellation Finished Interrupt Enable 3 - CFIE3: u1, - /// Cancellation Finished Interrupt Enable 4 - CFIE4: u1, - /// Cancellation Finished Interrupt Enable 5 - CFIE5: u1, - /// Cancellation Finished Interrupt Enable 6 - CFIE6: u1, - /// Cancellation Finished Interrupt Enable 7 - CFIE7: u1, - /// Cancellation Finished Interrupt Enable 8 - CFIE8: u1, - /// Cancellation Finished Interrupt Enable 9 - CFIE9: u1, - /// Cancellation Finished Interrupt Enable 10 - CFIE10: u1, - /// Cancellation Finished Interrupt Enable 11 - CFIE11: u1, - /// Cancellation Finished Interrupt Enable 12 - CFIE12: u1, - /// Cancellation Finished Interrupt Enable 13 - CFIE13: u1, - /// Cancellation Finished Interrupt Enable 14 - CFIE14: u1, - /// Cancellation Finished Interrupt Enable 15 - CFIE15: u1, - /// Cancellation Finished Interrupt Enable 16 - CFIE16: u1, - /// Cancellation Finished Interrupt Enable 17 - CFIE17: u1, - /// Cancellation Finished Interrupt Enable 18 - CFIE18: u1, - /// Cancellation Finished Interrupt Enable 19 - CFIE19: u1, - /// Cancellation Finished Interrupt Enable 20 - CFIE20: u1, - /// Cancellation Finished Interrupt Enable 21 - CFIE21: u1, - /// Cancellation Finished Interrupt Enable 22 - CFIE22: u1, - /// Cancellation Finished Interrupt Enable 23 - CFIE23: u1, - /// Cancellation Finished Interrupt Enable 24 - CFIE24: u1, - /// Cancellation Finished Interrupt Enable 25 - CFIE25: u1, - /// Cancellation Finished Interrupt Enable 26 - CFIE26: u1, - /// Cancellation Finished Interrupt Enable 27 - CFIE27: u1, - /// Cancellation Finished Interrupt Enable 28 - CFIE28: u1, - /// Cancellation Finished Interrupt Enable 29 - CFIE29: u1, - /// Cancellation Finished Interrupt Enable 30 - CFIE30: u1, - /// Cancellation Finished Interrupt Enable 31 - CFIE31: u1, - }), base_address + 0xe4); - - /// address: 0x420004f0 - /// Tx Event FIFO Configuration - pub const TXEFC = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Start Address - EFSA: u16, - /// Event FIFO Size - EFS: u6, - reserved0: u1, - reserved1: u1, - /// Event FIFO Watermark - EFWM: u6, - padding0: u1, - padding1: u1, - }), base_address + 0xf0); - - /// address: 0x420004f4 - /// Tx Event FIFO Status - pub const TXEFS = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Fill Level - EFFL: u6, - reserved0: u1, - reserved1: u1, - /// Event FIFO Get Index - EFGI: u5, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Event FIFO Put Index - EFPI: u5, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Event FIFO Full - EFF: u1, - /// Tx Event FIFO Element Lost - TEFL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xf4); - - /// address: 0x420004f8 - /// Tx Event FIFO Acknowledge - pub const TXEFA = @intToPtr(*volatile Mmio(32, packed struct { - /// Event FIFO Acknowledge Index - EFAI: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xf8); - }; - - /// Configurable Custom Logic - pub const CCL = struct { - pub const base_address = 0x42003800; - pub const version = "U22251.1.0"; - - /// address: 0x42003800 - /// Control - pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Run in Standby - RUNSTDBY: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x42003804 - /// SEQ Control x - pub const SEQCTRL = @intToPtr(*volatile [2]Mmio(8, packed struct { - /// Sequential Selection - SEQSEL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x42003808 - /// LUT Control x - pub const LUTCTRL = @intToPtr(*volatile [4]Mmio(32, packed struct { - reserved0: u1, - /// LUT Enable - ENABLE: u1, - reserved1: u1, - reserved2: u1, - /// Filter Selection - FILTSEL: u2, - reserved3: u1, - /// Edge Selection - EDGESEL: u1, - /// Input Selection 0 - INSEL0: u4, - /// Input Selection 1 - INSEL1: u4, - /// Input Selection 2 - INSEL2: u4, - /// Inverted Event Input Enable - INVEI: u1, - /// LUT Event Input Enable - LUTEI: u1, - /// LUT Event Output Enable - LUTEO: u1, - reserved4: u1, - /// Truth Value - TRUTH: u8, - }), base_address + 0x8); - }; - - /// Cortex M Cache Controller - pub const CMCC = struct { - pub const base_address = 0x41006000; - pub const version = "U20156.0.0"; - - /// address: 0x41006000 - /// Cache Type Register - pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// dynamic Clock Gating supported - GCLK: u1, - reserved1: u1, - reserved2: u1, - /// Round Robin Policy supported - RRP: u1, - /// Number of Way - WAYNUM: u2, - /// Lock Down supported - LCKDOWN: u1, - /// Cache Size - CSIZE: u3, - /// Cache Line Size - CLSIZE: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x0); - - /// address: 0x41006004 - /// Cache Configuration Register - pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Instruction Cache Disable - ICDIS: u1, - /// Data Cache Disable - DCDIS: u1, - reserved1: u1, - /// Cache size configured by software - CSIZESW: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x41006008 - /// Cache Control Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller Enable - CEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - - /// address: 0x4100600c - /// Cache Status Register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller Status - CSTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xc); - - /// address: 0x41006010 - /// Cache Lock per Way Register - pub const LCKWAY = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); - - /// address: 0x41006020 - /// Cache Maintenance Register 0 - pub const MAINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller invalidate All - INVALL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x20); - - /// address: 0x41006024 - /// Cache Maintenance Register 1 - pub const MAINT1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Invalidate Index - INDEX: u8, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Invalidate Way - WAY: u4, - }), base_address + 0x24); - - /// address: 0x41006028 - /// Cache Monitor Configuration Register - pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller Monitor Counter Mode - MODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x28); - - /// address: 0x4100602c - /// Cache Monitor Enable Register - pub const MEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller Monitor Enable - MENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x2c); - - /// address: 0x41006030 - /// Cache Monitor Control Register - pub const MCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache Controller Software Reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x30); - - /// address: 0x41006034 - /// Cache Monitor Status Register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Monitor Event Counter - EVENT_CNT: u32, - }), base_address + 0x34); - }; - - /// Digital-to-Analog Converter - pub const DAC = struct { - pub const base_address = 0x43002400; - pub const version = "U25021.0.0"; - - /// address: 0x43002400 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable DAC Controller - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x43002401 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { - /// Differential mode enable - DIFF: u1, - /// Reference Selection for DAC0/1 - REFSEL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1); - - /// address: 0x43002402 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Start Conversion Event Input DAC 0 - STARTEI0: u1, - /// Start Conversion Event Input DAC 1 - STARTEI1: u1, - /// Data Buffer Empty Event Output DAC 0 - EMPTYEO0: u1, - /// Data Buffer Empty Event Output DAC 1 - EMPTYEO1: u1, - /// Enable Invertion of DAC 0 input event - INVEI0: u1, - /// Enable Invertion of DAC 1 input event - INVEI1: u1, - /// Result Ready Event Output 0 - RESRDYEO0: u1, - /// Result Ready Event Output 1 - RESRDYEO1: u1, - }), base_address + 0x2); - - /// address: 0x43002404 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Underrun 0 Interrupt Enable - UNDERRUN0: u1, - /// Underrun 1 Interrupt Enable - UNDERRUN1: u1, - /// Data Buffer 0 Empty Interrupt Enable - EMPTY0: u1, - /// Data Buffer 1 Empty Interrupt Enable - EMPTY1: u1, - /// Result 0 Ready Interrupt Enable - RESRDY0: u1, - /// Result 1 Ready Interrupt Enable - RESRDY1: u1, - /// Overrun 0 Interrupt Enable - OVERRUN0: u1, - /// Overrun 1 Interrupt Enable - OVERRUN1: u1, - }), base_address + 0x4); - - /// address: 0x43002405 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Underrun 0 Interrupt Enable - UNDERRUN0: u1, - /// Underrun 1 Interrupt Enable - UNDERRUN1: u1, - /// Data Buffer 0 Empty Interrupt Enable - EMPTY0: u1, - /// Data Buffer 1 Empty Interrupt Enable - EMPTY1: u1, - /// Result 0 Ready Interrupt Enable - RESRDY0: u1, - /// Result 1 Ready Interrupt Enable - RESRDY1: u1, - /// Overrun 0 Interrupt Enable - OVERRUN0: u1, - /// Overrun 1 Interrupt Enable - OVERRUN1: u1, - }), base_address + 0x5); - - /// address: 0x43002406 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Result 0 Underrun - UNDERRUN0: u1, - /// Result 1 Underrun - UNDERRUN1: u1, - /// Data Buffer 0 Empty - EMPTY0: u1, - /// Data Buffer 1 Empty - EMPTY1: u1, - /// Result 0 Ready - RESRDY0: u1, - /// Result 1 Ready - RESRDY1: u1, - /// Result 0 Overrun - OVERRUN0: u1, - /// Result 1 Overrun - OVERRUN1: u1, - }), base_address + 0x6); - - /// address: 0x43002407 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// DAC 0 Startup Ready - READY0: u1, - /// DAC 1 Startup Ready - READY1: u1, - /// DAC 0 End of Conversion - EOC0: u1, - /// DAC 1 End of Conversion - EOC1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x7); - - /// address: 0x43002408 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// DAC Enable Status - ENABLE: u1, - /// Data DAC 0 - DATA0: u1, - /// Data DAC 1 - DATA1: u1, - /// Data Buffer DAC 0 - DATABUF0: u1, - /// Data Buffer DAC 1 - DATABUF1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x8); - - /// address: 0x4300240c - /// DAC n Control - pub const DACCTRL = @intToPtr(*volatile [2]Mmio(16, packed struct { - /// Left Adjusted Data - LEFTADJ: u1, - /// Enable DAC0 - ENABLE: u1, - /// Current Control - CCTRL: u2, - reserved0: u1, - /// Standalone Filter - FEXT: u1, - /// Run in Standby - RUNSTDBY: u1, - /// Dithering Mode - DITHER: u1, - /// Refresh period - REFRESH: u4, - reserved1: u1, - /// Sampling Rate - OSR: u3, - }), base_address + 0xc); - - /// address: 0x43002410 - /// DAC n Data - pub const DATA = @intToPtr(*volatile [2]u16, base_address + 0x10); - - /// address: 0x43002414 - /// DAC n Data Buffer - pub const DATABUF = @intToPtr(*volatile [2]u16, base_address + 0x14); - - /// address: 0x43002418 - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x4300241c - /// Filter Result - pub const RESULT = @intToPtr(*volatile [2]u16, base_address + 0x1c); - }; - - /// Direct Memory Access Controller - pub const DMAC = struct { - pub const base_address = 0x4100a000; - pub const version = "U25031.0.1"; - - /// address: 0x4100a000 - /// Control - pub const CTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// DMA Enable - DMAENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Priority Level 0 Enable - LVLEN0: u1, - /// Priority Level 1 Enable - LVLEN1: u1, - /// Priority Level 2 Enable - LVLEN2: u1, - /// Priority Level 3 Enable - LVLEN3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x4100a002 - /// CRC Control - pub const CRCCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// CRC Beat Size - CRCBEATSIZE: u2, - /// CRC Polynomial Type - CRCPOLY: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CRC Input Source - CRCSRC: u6, - /// CRC Operating Mode - CRCMODE: u2, - }), base_address + 0x2); - - /// address: 0x4100a004 - /// CRC Data Input - pub const CRCDATAIN = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4100a008 - /// CRC Checksum - pub const CRCCHKSUM = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4100a00c - /// CRC Status - pub const CRCSTATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// CRC Module Busy - CRCBUSY: u1, - /// CRC Zero - CRCZERO: u1, - /// CRC Error - CRCERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0xc); - - /// address: 0x4100a00d - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xd); - - /// address: 0x4100a010 - /// Software Trigger Control - pub const SWTRIGCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 Software Trigger - SWTRIG0: u1, - /// Channel 1 Software Trigger - SWTRIG1: u1, - /// Channel 2 Software Trigger - SWTRIG2: u1, - /// Channel 3 Software Trigger - SWTRIG3: u1, - /// Channel 4 Software Trigger - SWTRIG4: u1, - /// Channel 5 Software Trigger - SWTRIG5: u1, - /// Channel 6 Software Trigger - SWTRIG6: u1, - /// Channel 7 Software Trigger - SWTRIG7: u1, - /// Channel 8 Software Trigger - SWTRIG8: u1, - /// Channel 9 Software Trigger - SWTRIG9: u1, - /// Channel 10 Software Trigger - SWTRIG10: u1, - /// Channel 11 Software Trigger - SWTRIG11: u1, - /// Channel 12 Software Trigger - SWTRIG12: u1, - /// Channel 13 Software Trigger - SWTRIG13: u1, - /// Channel 14 Software Trigger - SWTRIG14: u1, - /// Channel 15 Software Trigger - SWTRIG15: u1, - /// Channel 16 Software Trigger - SWTRIG16: u1, - /// Channel 17 Software Trigger - SWTRIG17: u1, - /// Channel 18 Software Trigger - SWTRIG18: u1, - /// Channel 19 Software Trigger - SWTRIG19: u1, - /// Channel 20 Software Trigger - SWTRIG20: u1, - /// Channel 21 Software Trigger - SWTRIG21: u1, - /// Channel 22 Software Trigger - SWTRIG22: u1, - /// Channel 23 Software Trigger - SWTRIG23: u1, - /// Channel 24 Software Trigger - SWTRIG24: u1, - /// Channel 25 Software Trigger - SWTRIG25: u1, - /// Channel 26 Software Trigger - SWTRIG26: u1, - /// Channel 27 Software Trigger - SWTRIG27: u1, - /// Channel 28 Software Trigger - SWTRIG28: u1, - /// Channel 29 Software Trigger - SWTRIG29: u1, - /// Channel 30 Software Trigger - SWTRIG30: u1, - /// Channel 31 Software Trigger - SWTRIG31: u1, - }), base_address + 0x10); - - /// address: 0x4100a014 - /// Priority Control 0 - pub const PRICTRL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Level 0 Channel Priority Number - LVLPRI0: u5, - /// Level 0 Quality of Service - QOS0: u2, - /// Level 0 Round-Robin Scheduling Enable - RRLVLEN0: u1, - /// Level 1 Channel Priority Number - LVLPRI1: u5, - /// Level 1 Quality of Service - QOS1: u2, - /// Level 1 Round-Robin Scheduling Enable - RRLVLEN1: u1, - /// Level 2 Channel Priority Number - LVLPRI2: u5, - /// Level 2 Quality of Service - QOS2: u2, - /// Level 2 Round-Robin Scheduling Enable - RRLVLEN2: u1, - /// Level 3 Channel Priority Number - LVLPRI3: u5, - /// Level 3 Quality of Service - QOS3: u2, - /// Level 3 Round-Robin Scheduling Enable - RRLVLEN3: u1, - }), base_address + 0x14); - - /// address: 0x4100a020 - /// Interrupt Pending - pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel ID - ID: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Transfer Error - TERR: u1, - /// Transfer Complete - TCMPL: u1, - /// Channel Suspend - SUSP: u1, - reserved3: u1, - /// CRC Error - CRCERR: u1, - /// Fetch Error - FERR: u1, - /// Busy - BUSY: u1, - /// Pending - PEND: u1, - }), base_address + 0x20); - - /// address: 0x4100a024 - /// Interrupt Status - pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 Pending Interrupt - CHINT0: u1, - /// Channel 1 Pending Interrupt - CHINT1: u1, - /// Channel 2 Pending Interrupt - CHINT2: u1, - /// Channel 3 Pending Interrupt - CHINT3: u1, - /// Channel 4 Pending Interrupt - CHINT4: u1, - /// Channel 5 Pending Interrupt - CHINT5: u1, - /// Channel 6 Pending Interrupt - CHINT6: u1, - /// Channel 7 Pending Interrupt - CHINT7: u1, - /// Channel 8 Pending Interrupt - CHINT8: u1, - /// Channel 9 Pending Interrupt - CHINT9: u1, - /// Channel 10 Pending Interrupt - CHINT10: u1, - /// Channel 11 Pending Interrupt - CHINT11: u1, - /// Channel 12 Pending Interrupt - CHINT12: u1, - /// Channel 13 Pending Interrupt - CHINT13: u1, - /// Channel 14 Pending Interrupt - CHINT14: u1, - /// Channel 15 Pending Interrupt - CHINT15: u1, - /// Channel 16 Pending Interrupt - CHINT16: u1, - /// Channel 17 Pending Interrupt - CHINT17: u1, - /// Channel 18 Pending Interrupt - CHINT18: u1, - /// Channel 19 Pending Interrupt - CHINT19: u1, - /// Channel 20 Pending Interrupt - CHINT20: u1, - /// Channel 21 Pending Interrupt - CHINT21: u1, - /// Channel 22 Pending Interrupt - CHINT22: u1, - /// Channel 23 Pending Interrupt - CHINT23: u1, - /// Channel 24 Pending Interrupt - CHINT24: u1, - /// Channel 25 Pending Interrupt - CHINT25: u1, - /// Channel 26 Pending Interrupt - CHINT26: u1, - /// Channel 27 Pending Interrupt - CHINT27: u1, - /// Channel 28 Pending Interrupt - CHINT28: u1, - /// Channel 29 Pending Interrupt - CHINT29: u1, - /// Channel 30 Pending Interrupt - CHINT30: u1, - /// Channel 31 Pending Interrupt - CHINT31: u1, - }), base_address + 0x24); - - /// address: 0x4100a028 - /// Busy Channels - pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Busy Channel 0 - BUSYCH0: u1, - /// Busy Channel 1 - BUSYCH1: u1, - /// Busy Channel 2 - BUSYCH2: u1, - /// Busy Channel 3 - BUSYCH3: u1, - /// Busy Channel 4 - BUSYCH4: u1, - /// Busy Channel 5 - BUSYCH5: u1, - /// Busy Channel 6 - BUSYCH6: u1, - /// Busy Channel 7 - BUSYCH7: u1, - /// Busy Channel 8 - BUSYCH8: u1, - /// Busy Channel 9 - BUSYCH9: u1, - /// Busy Channel 10 - BUSYCH10: u1, - /// Busy Channel 11 - BUSYCH11: u1, - /// Busy Channel 12 - BUSYCH12: u1, - /// Busy Channel 13 - BUSYCH13: u1, - /// Busy Channel 14 - BUSYCH14: u1, - /// Busy Channel 15 - BUSYCH15: u1, - /// Busy Channel 16 - BUSYCH16: u1, - /// Busy Channel 17 - BUSYCH17: u1, - /// Busy Channel 18 - BUSYCH18: u1, - /// Busy Channel 19 - BUSYCH19: u1, - /// Busy Channel 20 - BUSYCH20: u1, - /// Busy Channel 21 - BUSYCH21: u1, - /// Busy Channel 22 - BUSYCH22: u1, - /// Busy Channel 23 - BUSYCH23: u1, - /// Busy Channel 24 - BUSYCH24: u1, - /// Busy Channel 25 - BUSYCH25: u1, - /// Busy Channel 26 - BUSYCH26: u1, - /// Busy Channel 27 - BUSYCH27: u1, - /// Busy Channel 28 - BUSYCH28: u1, - /// Busy Channel 29 - BUSYCH29: u1, - /// Busy Channel 30 - BUSYCH30: u1, - /// Busy Channel 31 - BUSYCH31: u1, - }), base_address + 0x28); - - /// address: 0x4100a02c - /// Pending Channels - pub const PENDCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending Channel 0 - PENDCH0: u1, - /// Pending Channel 1 - PENDCH1: u1, - /// Pending Channel 2 - PENDCH2: u1, - /// Pending Channel 3 - PENDCH3: u1, - /// Pending Channel 4 - PENDCH4: u1, - /// Pending Channel 5 - PENDCH5: u1, - /// Pending Channel 6 - PENDCH6: u1, - /// Pending Channel 7 - PENDCH7: u1, - /// Pending Channel 8 - PENDCH8: u1, - /// Pending Channel 9 - PENDCH9: u1, - /// Pending Channel 10 - PENDCH10: u1, - /// Pending Channel 11 - PENDCH11: u1, - /// Pending Channel 12 - PENDCH12: u1, - /// Pending Channel 13 - PENDCH13: u1, - /// Pending Channel 14 - PENDCH14: u1, - /// Pending Channel 15 - PENDCH15: u1, - /// Pending Channel 16 - PENDCH16: u1, - /// Pending Channel 17 - PENDCH17: u1, - /// Pending Channel 18 - PENDCH18: u1, - /// Pending Channel 19 - PENDCH19: u1, - /// Pending Channel 20 - PENDCH20: u1, - /// Pending Channel 21 - PENDCH21: u1, - /// Pending Channel 22 - PENDCH22: u1, - /// Pending Channel 23 - PENDCH23: u1, - /// Pending Channel 24 - PENDCH24: u1, - /// Pending Channel 25 - PENDCH25: u1, - /// Pending Channel 26 - PENDCH26: u1, - /// Pending Channel 27 - PENDCH27: u1, - /// Pending Channel 28 - PENDCH28: u1, - /// Pending Channel 29 - PENDCH29: u1, - /// Pending Channel 30 - PENDCH30: u1, - /// Pending Channel 31 - PENDCH31: u1, - }), base_address + 0x2c); - - /// address: 0x4100a030 - /// Active Channel and Levels - pub const ACTIVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Level 0 Channel Trigger Request Executing - LVLEX0: u1, - /// Level 1 Channel Trigger Request Executing - LVLEX1: u1, - /// Level 2 Channel Trigger Request Executing - LVLEX2: u1, - /// Level 3 Channel Trigger Request Executing - LVLEX3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Active Channel ID - ID: u5, - reserved4: u1, - reserved5: u1, - /// Active Channel Busy - ABUSY: u1, - /// Active Channel Block Transfer Count - BTCNT: u16, - }), base_address + 0x30); - - /// address: 0x4100a034 - /// Descriptor Memory Section Base Address - pub const BASEADDR = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0x4100a038 - /// Write-Back Memory Section Base Address - pub const WRBADDR = @intToPtr(*volatile u32, base_address + 0x38); - - pub const CHANNEL = @ptrCast(*volatile [32]packed struct { - /// Channel n Control A - CHCTRLA: Mmio(32, packed struct { - /// Channel Software Reset - SWRST: u1, - /// Channel Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Channel Run in Standby - RUNSTDBY: u1, - reserved4: u1, - /// Trigger Source - TRIGSRC: u7, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Trigger Action - TRIGACT: u2, - reserved10: u1, - reserved11: u1, - /// Burst Length - BURSTLEN: u4, - /// FIFO Threshold - THRESHOLD: u2, - padding0: u1, - padding1: u1, - }), - - /// Channel n Control B - CHCTRLB: Mmio(8, packed struct { - /// Software Command - CMD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - - /// Channel n Priority Level - CHPRILVL: Mmio(8, packed struct { - /// Channel Priority Level - PRILVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - - /// Channel n Event Control - CHEVCTRL: Mmio(8, packed struct { - /// Channel Event Input Action - EVACT: u3, - reserved0: u1, - /// Channel Event Output Mode - EVOMODE: u2, - /// Channel Event Input Enable - EVIE: u1, - /// Channel Event Output Enable - EVOE: u1, - }), - - /// Channel n Interrupt Enable Clear - CHINTENCLR: Mmio(8, packed struct { - /// Channel Transfer Error Interrupt Enable - TERR: u1, - /// Channel Transfer Complete Interrupt Enable - TCMPL: u1, - /// Channel Suspend Interrupt Enable - SUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), - - /// Channel n Interrupt Enable Set - CHINTENSET: Mmio(8, packed struct { - /// Channel Transfer Error Interrupt Enable - TERR: u1, - /// Channel Transfer Complete Interrupt Enable - TCMPL: u1, - /// Channel Suspend Interrupt Enable - SUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), - - /// Channel n Interrupt Flag Status and Clear - CHINTFLAG: Mmio(8, packed struct { - /// Channel Transfer Error - TERR: u1, - /// Channel Transfer Complete - TCMPL: u1, - /// Channel Suspend - SUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), - - /// Channel n Status - CHSTATUS: Mmio(8, packed struct { - /// Channel Pending - PEND: u1, - /// Channel Busy - BUSY: u1, - /// Channel Fetch Error - FERR: u1, - /// Channel CRC Error - CRCERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), - padding0: u32, - }, base_address + 0x40); - }; - - /// Device Service Unit - pub const DSU = struct { - pub const base_address = 0x41002000; - pub const version = "U24101.0.0"; - - /// address: 0x41002000 - /// Control - pub const CTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - reserved0: u1, - /// 32-bit Cyclic Redundancy Code - CRC: u1, - /// Memory built-in self-test - MBIST: u1, - /// Chip-Erase - CE: u1, - reserved1: u1, - /// Auxiliary Row Read - ARR: u1, - /// Start Memory Stream Access - SMSA: u1, - }), base_address + 0x0); - - /// address: 0x41002001 - /// Status A - pub const STATUSA = @intToPtr(*volatile Mmio(8, packed struct { - /// Done - DONE: u1, - /// CPU Reset Phase Extension - CRSTEXT: u1, - /// Bus Error - BERR: u1, - /// Failure - FAIL: u1, - /// Protection Error - PERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x1); - - /// address: 0x41002002 - /// Status B - pub const STATUSB = @intToPtr(*volatile Mmio(8, packed struct { - /// Protected - PROT: u1, - /// Debugger Present - DBGPRES: u1, - /// Debug Communication Channel 0 Dirty - DCCD0: u1, - /// Debug Communication Channel 1 Dirty - DCCD1: u1, - /// Hot-Plugging Enable - HPE: u1, - /// Chip Erase Locked - CELCK: u1, - /// Test Debug Communication Channel 0 Dirty - TDCCD0: u1, - /// Test Debug Communication Channel 1 Dirty - TDCCD1: u1, - }), base_address + 0x2); - - /// address: 0x41002004 - /// Address - pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Access Mode - AMOD: u2, - /// Address - ADDR: u30, - }), base_address + 0x4); - - /// address: 0x41002008 - /// Length - pub const LENGTH = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x8); - - /// address: 0x4100200c - /// Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x41002010 - /// Debug Communication Channel n - pub const DCC = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Data - DATA: u32, - }), base_address + 0x10); - - /// address: 0x41002018 - /// Device Identification - pub const DID = @intToPtr(*volatile Mmio(32, packed struct { - /// Device Select - DEVSEL: u8, - /// Revision Number - REVISION: u4, - /// Die Number - DIE: u4, - /// Series - SERIES: u6, - reserved0: u1, - /// Family - FAMILY: u5, - /// Processor - PROCESSOR: u4, - }), base_address + 0x18); - - /// address: 0x4100201c - /// Configuration - pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Latency Quality Of Service - LQOS: u2, - /// DMA Trigger Level - DCCDMALEVEL: u2, - /// Trace Control - ETBRAMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x410020f0 - /// Device Configuration - pub const DCFG = @intToPtr(*volatile [2]u32, base_address + 0xf0); - - /// address: 0x41003000 - /// CoreSight ROM Table Entry 0 - pub const ENTRY0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Entry Present - EPRES: u1, - /// Format - FMT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Address Offset - ADDOFF: u20, - }), base_address + 0x1000); - - /// address: 0x41003004 - /// CoreSight ROM Table Entry 1 - pub const ENTRY1 = @intToPtr(*volatile u32, base_address + 0x1004); - - /// address: 0x41003008 - /// CoreSight ROM Table End - pub const END = @intToPtr(*volatile u32, base_address + 0x1008); - - /// address: 0x41003fcc - /// CoreSight ROM Table Memory Type - pub const MEMTYPE = @intToPtr(*volatile Mmio(32, packed struct { - /// System Memory Present - SMEMP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x1fcc); - - /// address: 0x41003fd0 - /// Peripheral Identification 4 - pub const PID4 = @intToPtr(*volatile Mmio(32, packed struct { - /// JEP-106 Continuation Code - JEPCC: u4, - /// 4KB count - FKBC: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1fd0); - - /// address: 0x41003fd4 - /// Peripheral Identification 5 - pub const PID5 = @intToPtr(*volatile u32, base_address + 0x1fd4); - - /// address: 0x41003fd8 - /// Peripheral Identification 6 - pub const PID6 = @intToPtr(*volatile u32, base_address + 0x1fd8); - - /// address: 0x41003fdc - /// Peripheral Identification 7 - pub const PID7 = @intToPtr(*volatile u32, base_address + 0x1fdc); - - /// address: 0x41003fe0 - /// Peripheral Identification 0 - pub const PID0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Part Number Low - PARTNBL: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1fe0); - - /// address: 0x41003fe4 - /// Peripheral Identification 1 - pub const PID1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Part Number High - PARTNBH: u4, - /// Low part of the JEP-106 Identity Code - JEPIDCL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1fe4); - - /// address: 0x41003fe8 - /// Peripheral Identification 2 - pub const PID2 = @intToPtr(*volatile Mmio(32, packed struct { - /// JEP-106 Identity Code High - JEPIDCH: u3, - /// JEP-106 Identity Code is used - JEPU: u1, - /// Revision Number - REVISION: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1fe8); - - /// address: 0x41003fec - /// Peripheral Identification 3 - pub const PID3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ARM CUSMOD - CUSMOD: u4, - /// Revision Number - REVAND: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1fec); - - /// address: 0x41003ff0 - /// Component Identification 0 - pub const CID0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Preamble Byte 0 - PREAMBLEB0: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1ff0); - - /// address: 0x41003ff4 - /// Component Identification 1 - pub const CID1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Preamble - PREAMBLE: u4, - /// Component Class - CCLASS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1ff4); - - /// address: 0x41003ff8 - /// Component Identification 2 - pub const CID2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Preamble Byte 2 - PREAMBLEB2: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1ff8); - - /// address: 0x41003ffc - /// Component Identification 3 - pub const CID3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Preamble Byte 3 - PREAMBLEB3: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1ffc); - }; - - /// External Interrupt Controller - pub const EIC = struct { - pub const base_address = 0x40002800; - pub const version = "U22543.0.0"; - - /// address: 0x40002800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - /// Clock Selection - CKSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40002801 - /// Non-Maskable Interrupt Control - pub const NMICTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Non-Maskable Interrupt Sense Configuration - NMISENSE: u3, - /// Non-Maskable Interrupt Filter Enable - NMIFILTEN: u1, - /// Asynchronous Edge Detection Mode - NMIASYNCH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x1); - - /// address: 0x40002802 - /// Non-Maskable Interrupt Flag Status and Clear - pub const NMIFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Non-Maskable Interrupt - NMI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x2); - - /// address: 0x40002804 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy Status - SWRST: u1, - /// Enable Synchronization Busy Status - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// External Interrupt Event Output Enable - EXTINTEO: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000280c - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Interrupt Enable - EXTINT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40002810 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// External Interrupt Enable - EXTINT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40002814 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// External Interrupt - EXTINT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40002818 - /// External Interrupt Asynchronous Mode - pub const ASYNCH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); - - /// address: 0x4000281c - /// External Interrupt Sense Configuration - pub const CONFIG = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Input Sense Configuration 0 - SENSE0: u3, - /// Filter Enable 0 - FILTEN0: u1, - /// Input Sense Configuration 1 - SENSE1: u3, - /// Filter Enable 1 - FILTEN1: u1, - /// Input Sense Configuration 2 - SENSE2: u3, - /// Filter Enable 2 - FILTEN2: u1, - /// Input Sense Configuration 3 - SENSE3: u3, - /// Filter Enable 3 - FILTEN3: u1, - /// Input Sense Configuration 4 - SENSE4: u3, - /// Filter Enable 4 - FILTEN4: u1, - /// Input Sense Configuration 5 - SENSE5: u3, - /// Filter Enable 5 - FILTEN5: u1, - /// Input Sense Configuration 6 - SENSE6: u3, - /// Filter Enable 6 - FILTEN6: u1, - /// Input Sense Configuration 7 - SENSE7: u3, - /// Filter Enable 7 - FILTEN7: u1, - }), base_address + 0x1c); - - /// address: 0x40002830 - /// Debouncer Enable - pub const DEBOUNCEN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x30); - - /// address: 0x40002834 - /// Debouncer Prescaler - pub const DPRESCALER = @intToPtr(*volatile Mmio(32, packed struct { - /// Debouncer Prescaler - PRESCALER0: u3, - /// Debouncer number of states - STATES0: u1, - /// Debouncer Prescaler - PRESCALER1: u3, - /// Debouncer number of states - STATES1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Pin Sampler frequency selection - TICKON: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x34); - - /// address: 0x40002838 - /// Pin State - pub const PINSTATE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - - /// Event System Interface - pub const EVSYS = struct { - pub const base_address = 0x4100e000; - pub const version = "U25041.0.0"; - - /// address: 0x4100e000 - /// Control - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x0); - - /// address: 0x4100e004 - /// Software Event - pub const SWEVT = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 Software Selection - CHANNEL0: u1, - /// Channel 1 Software Selection - CHANNEL1: u1, - /// Channel 2 Software Selection - CHANNEL2: u1, - /// Channel 3 Software Selection - CHANNEL3: u1, - /// Channel 4 Software Selection - CHANNEL4: u1, - /// Channel 5 Software Selection - CHANNEL5: u1, - /// Channel 6 Software Selection - CHANNEL6: u1, - /// Channel 7 Software Selection - CHANNEL7: u1, - /// Channel 8 Software Selection - CHANNEL8: u1, - /// Channel 9 Software Selection - CHANNEL9: u1, - /// Channel 10 Software Selection - CHANNEL10: u1, - /// Channel 11 Software Selection - CHANNEL11: u1, - /// Channel 12 Software Selection - CHANNEL12: u1, - /// Channel 13 Software Selection - CHANNEL13: u1, - /// Channel 14 Software Selection - CHANNEL14: u1, - /// Channel 15 Software Selection - CHANNEL15: u1, - /// Channel 16 Software Selection - CHANNEL16: u1, - /// Channel 17 Software Selection - CHANNEL17: u1, - /// Channel 18 Software Selection - CHANNEL18: u1, - /// Channel 19 Software Selection - CHANNEL19: u1, - /// Channel 20 Software Selection - CHANNEL20: u1, - /// Channel 21 Software Selection - CHANNEL21: u1, - /// Channel 22 Software Selection - CHANNEL22: u1, - /// Channel 23 Software Selection - CHANNEL23: u1, - /// Channel 24 Software Selection - CHANNEL24: u1, - /// Channel 25 Software Selection - CHANNEL25: u1, - /// Channel 26 Software Selection - CHANNEL26: u1, - /// Channel 27 Software Selection - CHANNEL27: u1, - /// Channel 28 Software Selection - CHANNEL28: u1, - /// Channel 29 Software Selection - CHANNEL29: u1, - /// Channel 30 Software Selection - CHANNEL30: u1, - /// Channel 31 Software Selection - CHANNEL31: u1, - }), base_address + 0x4); - - /// address: 0x4100e008 - /// Priority Control - pub const PRICTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Channel Priority Number - PRI: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Round-Robin Scheduling Enable - RREN: u1, - }), base_address + 0x8); - - /// address: 0x4100e010 - /// Channel Pending Interrupt - pub const INTPEND = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel ID - ID: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Channel Overrun - OVR: u1, - /// Channel Event Detected - EVD: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Ready - READY: u1, - /// Busy - BUSY: u1, - }), base_address + 0x10); - - /// address: 0x4100e014 - /// Interrupt Status - pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 Pending Interrupt - CHINT0: u1, - /// Channel 1 Pending Interrupt - CHINT1: u1, - /// Channel 2 Pending Interrupt - CHINT2: u1, - /// Channel 3 Pending Interrupt - CHINT3: u1, - /// Channel 4 Pending Interrupt - CHINT4: u1, - /// Channel 5 Pending Interrupt - CHINT5: u1, - /// Channel 6 Pending Interrupt - CHINT6: u1, - /// Channel 7 Pending Interrupt - CHINT7: u1, - /// Channel 8 Pending Interrupt - CHINT8: u1, - /// Channel 9 Pending Interrupt - CHINT9: u1, - /// Channel 10 Pending Interrupt - CHINT10: u1, - /// Channel 11 Pending Interrupt - CHINT11: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x4100e018 - /// Busy Channels - pub const BUSYCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Busy Channel 0 - BUSYCH0: u1, - /// Busy Channel 1 - BUSYCH1: u1, - /// Busy Channel 2 - BUSYCH2: u1, - /// Busy Channel 3 - BUSYCH3: u1, - /// Busy Channel 4 - BUSYCH4: u1, - /// Busy Channel 5 - BUSYCH5: u1, - /// Busy Channel 6 - BUSYCH6: u1, - /// Busy Channel 7 - BUSYCH7: u1, - /// Busy Channel 8 - BUSYCH8: u1, - /// Busy Channel 9 - BUSYCH9: u1, - /// Busy Channel 10 - BUSYCH10: u1, - /// Busy Channel 11 - BUSYCH11: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4100e01c - /// Ready Users - pub const READYUSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Ready User for Channel 0 - READYUSR0: u1, - /// Ready User for Channel 1 - READYUSR1: u1, - /// Ready User for Channel 2 - READYUSR2: u1, - /// Ready User for Channel 3 - READYUSR3: u1, - /// Ready User for Channel 4 - READYUSR4: u1, - /// Ready User for Channel 5 - READYUSR5: u1, - /// Ready User for Channel 6 - READYUSR6: u1, - /// Ready User for Channel 7 - READYUSR7: u1, - /// Ready User for Channel 8 - READYUSR8: u1, - /// Ready User for Channel 9 - READYUSR9: u1, - /// Ready User for Channel 10 - READYUSR10: u1, - /// Ready User for Channel 11 - READYUSR11: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x4100e120 - /// User Multiplexer n - pub const USER = @intToPtr(*volatile [67]Mmio(32, packed struct { - /// Channel Event Selection - CHANNEL: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x120); - - pub const CHANNEL = @ptrCast(*volatile [32]packed struct { - /// Channel n Control - CHANNEL: Mmio(32, packed struct { - /// Event Generator Selection - EVGEN: u7, - reserved0: u1, - /// Path Selection - PATH: u2, - /// Edge Detection Selection - EDGSEL: u2, - reserved1: u1, - reserved2: u1, - /// Run in standby - RUNSTDBY: u1, - /// Generic Clock On Demand - ONDEMAND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), - - /// Channel n Interrupt Enable Clear - CHINTENCLR: Mmio(8, packed struct { - /// Channel Overrun Interrupt Disable - OVR: u1, - /// Channel Event Detected Interrupt Disable - EVD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - - /// Channel n Interrupt Enable Set - CHINTENSET: Mmio(8, packed struct { - /// Channel Overrun Interrupt Enable - OVR: u1, - /// Channel Event Detected Interrupt Enable - EVD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - - /// Channel n Interrupt Flag Status and Clear - CHINTFLAG: Mmio(8, packed struct { - /// Channel Overrun - OVR: u1, - /// Channel Event Detected - EVD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - - /// Channel n Status - CHSTATUS: Mmio(8, packed struct { - /// Ready User - RDYUSR: u1, - /// Busy Channel - BUSYCH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), - }, base_address + 0x20); - }; - - /// Frequency Meter - pub const FREQM = struct { - pub const base_address = 0x40002c00; - pub const version = "U22571.1.0"; - - /// address: 0x40002c00 - /// Control A Register - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40002c01 - /// Control B Register - pub const CTRLB = @intToPtr(*volatile Mmio(8, packed struct { - /// Start Measurement - START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1); - - /// address: 0x40002c02 - /// Config A register - pub const CFGA = @intToPtr(*volatile Mmio(16, packed struct { - /// Number of Reference Clock Cycles - REFNUM: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2); - - /// address: 0x40002c08 - /// Interrupt Enable Clear Register - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Measurement Done Interrupt Enable - DONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x40002c09 - /// Interrupt Enable Set Register - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Measurement Done Interrupt Enable - DONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x9); - - /// address: 0x40002c0a - /// Interrupt Flag Register - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Measurement Done - DONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xa); - - /// address: 0x40002c0b - /// Status Register - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// FREQM Status - BUSY: u1, - /// Sticky Count Value Overflow - OVF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xb); - - /// address: 0x40002c0c - /// Synchronization Busy Register - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40002c10 - /// Count Value Register - pub const VALUE = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x10); - }; - - /// Generic Clock Generator - pub const GCLK = struct { - pub const base_address = 0x40001c00; - pub const version = "U21221.2.0"; - - /// address: 0x40001c00 - /// Control - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x0); - - /// address: 0x40001c04 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchroniation Busy bit - SWRST: u1, - reserved0: u1, - /// Generic Clock Generator Control n Synchronization Busy bits - GENCTRL: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x4); - - /// address: 0x40001c20 - /// Generic Clock Generator Control - pub const GENCTRL = @intToPtr(*volatile [12]Mmio(32, packed struct { - /// Source Select - SRC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Generic Clock Generator Enable - GENEN: u1, - /// Improve Duty Cycle - IDC: u1, - /// Output Off Value - OOV: u1, - /// Output Enable - OE: u1, - /// Divide Selection - DIVSEL: u1, - /// Run in Standby - RUNSTDBY: u1, - reserved4: u1, - reserved5: u1, - /// Division Factor - DIV: u16, - }), base_address + 0x20); - - /// address: 0x40001c80 - /// Peripheral Clock Control - pub const PCHCTRL = @intToPtr(*volatile [48]Mmio(32, packed struct { - /// Generic Clock Generator - GEN: u4, - reserved0: u1, - reserved1: u1, - /// Channel Enable - CHEN: u1, - /// Write Lock - WRTLOCK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x80); - }; - - /// HSB Matrix - pub const HMATRIX = struct { - pub const base_address = 0x4100c000; - pub const version = "I76382.1.4"; - - pub const PRS = @ptrCast(*volatile [16]packed struct { - /// Priority A for Slave - PRAS: u32, - - /// Priority B for Slave - PRBS: u32, - }, base_address + 0x80); - }; - - /// Integrity Check Monitor - pub const ICM = struct { - pub const base_address = 0x42002c00; - pub const version = "U20101.2.0"; - - /// address: 0x42002c00 - /// Configuration - pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Write Back Disable - WBDIS: u1, - /// End of Monitoring Disable - EOMDIS: u1, - /// Secondary List Branching Disable - SLBDIS: u1, - reserved0: u1, - /// Bus Burden Control - BBC: u4, - /// Automatic Switch To Compare Digest - ASCD: u1, - /// Dual Input Buffer - DUALBUFF: u1, - reserved1: u1, - reserved2: u1, - /// User Initial Hash Value - UIHASH: u1, - /// User SHA Algorithm - UALGO: u3, - /// Region Hash Area Protection - HAPROT: u6, - reserved3: u1, - reserved4: u1, - /// Region Descriptor Area Protection - DAPROT: u6, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x42002c04 - /// Control - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// ICM Enable - ENABLE: u1, - /// ICM Disable Register - DISABLE: u1, - /// Software Reset - SWRST: u1, - reserved0: u1, - /// Recompute Internal Hash - REHASH: u4, - /// Region Monitoring Disable - RMDIS: u4, - /// Region Monitoring Enable - RMEN: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x42002c08 - /// Status - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// ICM Controller Enable Register - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RAW Region Monitoring Disabled Status - RAWRMDIS: u4, - /// Region Monitoring Disabled Status - RMDIS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x42002c10 - /// Interrupt Enable - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Hash Completed Interrupt Enable - RHC: u4, - /// Region Digest Mismatch Interrupt Enable - RDM: u4, - /// Region Bus Error Interrupt Enable - RBE: u4, - /// Region Wrap Condition detected Interrupt Enable - RWC: u4, - /// Region End bit Condition Detected Interrupt Enable - REC: u4, - /// Region Status Updated Interrupt Disable - RSU: u4, - /// Undefined Register Access Detection Interrupt Enable - URAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x10); - - /// address: 0x42002c14 - /// Interrupt Disable - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Hash Completed Interrupt Disable - RHC: u4, - /// Region Digest Mismatch Interrupt Disable - RDM: u4, - /// Region Bus Error Interrupt Disable - RBE: u4, - /// Region Wrap Condition Detected Interrupt Disable - RWC: u4, - /// Region End bit Condition detected Interrupt Disable - REC: u4, - /// Region Status Updated Interrupt Disable - RSU: u4, - /// Undefined Register Access Detection Interrupt Disable - URAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x14); - - /// address: 0x42002c18 - /// Interrupt Mask - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Hash Completed Interrupt Mask - RHC: u4, - /// Region Digest Mismatch Interrupt Mask - RDM: u4, - /// Region Bus Error Interrupt Mask - RBE: u4, - /// Region Wrap Condition Detected Interrupt Mask - RWC: u4, - /// Region End bit Condition Detected Interrupt Mask - REC: u4, - /// Region Status Updated Interrupt Mask - RSU: u4, - /// Undefined Register Access Detection Interrupt Mask - URAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x42002c1c - /// Interrupt Status - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Hash Completed - RHC: u4, - /// Region Digest Mismatch - RDM: u4, - /// Region Bus Error - RBE: u4, - /// Region Wrap Condition Detected - RWC: u4, - /// Region End bit Condition Detected - REC: u4, - /// Region Status Updated Detected - RSU: u4, - /// Undefined Register Access Detection Status - URAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x42002c20 - /// Undefined Access Status - pub const UASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Undefined Register Access Trace - URAT: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x20); - - /// address: 0x42002c30 - /// Region Descriptor Area Start Address - pub const DSCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Descriptor Area Start Address - DASA: u26, - }), base_address + 0x30); - - /// address: 0x42002c34 - /// Region Hash Area Start Address - pub const HASH = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Hash Area Start Address - HASA: u25, - }), base_address + 0x34); - - /// address: 0x42002c38 - /// User Initial Hash Value n - pub const UIHVAL = @intToPtr(*volatile [8]Mmio(32, packed struct { - /// Initial Hash Value - VAL: u32, - }), base_address + 0x38); - }; - - /// Inter-IC Sound Interface - pub const I2S = struct { - pub const base_address = 0x43002800; - pub const version = "U22242.0.0"; - - /// address: 0x43002800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Clock Unit 0 Enable - CKEN0: u1, - /// Clock Unit 1 Enable - CKEN1: u1, - /// Tx Serializer Enable - TXEN: u1, - /// Rx Serializer Enable - RXEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x43002804 - /// Clock Unit n Control - pub const CLKCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Slot Size - SLOTSIZE: u2, - /// Number of Slots in Frame - NBSLOTS: u3, - /// Frame Sync Width - FSWIDTH: u2, - /// Data Delay from Frame Sync - BITDELAY: u1, - /// Frame Sync Select - FSSEL: u1, - /// Frame Sync Invert - FSINV: u1, - /// Frame Sync Output Invert - FSOUTINV: u1, - /// Serial Clock Select - SCKSEL: u1, - /// Serial Clock Output Invert - SCKOUTINV: u1, - /// Master Clock Select - MCKSEL: u1, - /// Master Clock Enable - MCKEN: u1, - /// Master Clock Output Invert - MCKOUTINV: u1, - /// Master Clock Division Factor - MCKDIV: u6, - reserved0: u1, - reserved1: u1, - /// Master Clock Output Division Factor - MCKOUTDIV: u6, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0x4300280c - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Ready 0 Interrupt Enable - RXRDY0: u1, - /// Receive Ready 1 Interrupt Enable - RXRDY1: u1, - reserved0: u1, - reserved1: u1, - /// Receive Overrun 0 Interrupt Enable - RXOR0: u1, - /// Receive Overrun 1 Interrupt Enable - RXOR1: u1, - reserved2: u1, - reserved3: u1, - /// Transmit Ready 0 Interrupt Enable - TXRDY0: u1, - /// Transmit Ready 1 Interrupt Enable - TXRDY1: u1, - reserved4: u1, - reserved5: u1, - /// Transmit Underrun 0 Interrupt Enable - TXUR0: u1, - /// Transmit Underrun 1 Interrupt Enable - TXUR1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0x43002810 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Ready 0 Interrupt Enable - RXRDY0: u1, - /// Receive Ready 1 Interrupt Enable - RXRDY1: u1, - reserved0: u1, - reserved1: u1, - /// Receive Overrun 0 Interrupt Enable - RXOR0: u1, - /// Receive Overrun 1 Interrupt Enable - RXOR1: u1, - reserved2: u1, - reserved3: u1, - /// Transmit Ready 0 Interrupt Enable - TXRDY0: u1, - /// Transmit Ready 1 Interrupt Enable - TXRDY1: u1, - reserved4: u1, - reserved5: u1, - /// Transmit Underrun 0 Interrupt Enable - TXUR0: u1, - /// Transmit Underrun 1 Interrupt Enable - TXUR1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x43002814 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Ready 0 - RXRDY0: u1, - /// Receive Ready 1 - RXRDY1: u1, - reserved0: u1, - reserved1: u1, - /// Receive Overrun 0 - RXOR0: u1, - /// Receive Overrun 1 - RXOR1: u1, - reserved2: u1, - reserved3: u1, - /// Transmit Ready 0 - TXRDY0: u1, - /// Transmit Ready 1 - TXRDY1: u1, - reserved4: u1, - reserved5: u1, - /// Transmit Underrun 0 - TXUR0: u1, - /// Transmit Underrun 1 - TXUR1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x43002818 - /// Synchronization Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset Synchronization Status - SWRST: u1, - /// Enable Synchronization Status - ENABLE: u1, - /// Clock Unit 0 Enable Synchronization Status - CKEN0: u1, - /// Clock Unit 1 Enable Synchronization Status - CKEN1: u1, - /// Tx Serializer Enable Synchronization Status - TXEN: u1, - /// Rx Serializer Enable Synchronization Status - RXEN: u1, - reserved0: u1, - reserved1: u1, - /// Tx Data Synchronization Status - TXDATA: u1, - /// Rx Data Synchronization Status - RXDATA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x18); - - /// address: 0x43002820 - /// Tx Serializer Control - pub const TXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Serializer Mode - SERMODE: u2, - /// Line Default Line when Slot Disabled - TXDEFAULT: u2, - /// Transmit Data when Underrun - TXSAME: u1, - /// Clock Unit Selection - CLKSEL: u1, - reserved0: u1, - /// Data Slot Formatting Adjust - SLOTADJ: u1, - /// Data Word Size - DATASIZE: u3, - reserved1: u1, - /// Data Word Formatting Adjust - WORDADJ: u1, - /// Data Formatting Bit Extension - EXTEND: u2, - /// Data Formatting Bit Reverse - BITREV: u1, - /// Slot 0 Disabled for this Serializer - SLOTDIS0: u1, - /// Slot 1 Disabled for this Serializer - SLOTDIS1: u1, - /// Slot 2 Disabled for this Serializer - SLOTDIS2: u1, - /// Slot 3 Disabled for this Serializer - SLOTDIS3: u1, - /// Slot 4 Disabled for this Serializer - SLOTDIS4: u1, - /// Slot 5 Disabled for this Serializer - SLOTDIS5: u1, - /// Slot 6 Disabled for this Serializer - SLOTDIS6: u1, - /// Slot 7 Disabled for this Serializer - SLOTDIS7: u1, - /// Mono Mode - MONO: u1, - /// Single or Multiple DMA Channels - DMA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x20); - - /// address: 0x43002824 - /// Rx Serializer Control - pub const RXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Serializer Mode - SERMODE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Clock Unit Selection - CLKSEL: u1, - reserved3: u1, - /// Data Slot Formatting Adjust - SLOTADJ: u1, - /// Data Word Size - DATASIZE: u3, - reserved4: u1, - /// Data Word Formatting Adjust - WORDADJ: u1, - /// Data Formatting Bit Extension - EXTEND: u2, - /// Data Formatting Bit Reverse - BITREV: u1, - /// Slot 0 Disabled for this Serializer - SLOTDIS0: u1, - /// Slot 1 Disabled for this Serializer - SLOTDIS1: u1, - /// Slot 2 Disabled for this Serializer - SLOTDIS2: u1, - /// Slot 3 Disabled for this Serializer - SLOTDIS3: u1, - /// Slot 4 Disabled for this Serializer - SLOTDIS4: u1, - /// Slot 5 Disabled for this Serializer - SLOTDIS5: u1, - /// Slot 6 Disabled for this Serializer - SLOTDIS6: u1, - /// Slot 7 Disabled for this Serializer - SLOTDIS7: u1, - /// Mono Mode - MONO: u1, - /// Single or Multiple DMA Channels - DMA: u1, - /// Loop-back Test Mode - RXLOOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x24); - - /// address: 0x43002830 - /// Tx Data - pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample Data - DATA: u32, - }), base_address + 0x30); - - /// address: 0x43002834 - /// Rx Data - pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample Data - DATA: u32, - }), base_address + 0x34); - }; - - /// Main Clock - pub const MCLK = struct { - pub const base_address: usize = 0x40000800; - pub const version = "U24081.0.0"; - - /// address: 0x40000801 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Ready Interrupt Enable - CKRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1); - - /// address: 0x40000802 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Ready Interrupt Enable - CKRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x2); - - /// address: 0x40000803 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Ready - CKRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x3); - - /// address: 0x40000804 - /// HS Clock Division - pub const HSDIV = @intToPtr(*volatile Mmio(8, packed struct { - /// CPU Clock Division Factor - DIV: u8, - }), base_address + 0x4); - - /// address: 0x40000805 - /// CPU Clock Division - pub const CPUDIV = @intToPtr(*volatile Mmio(8, packed struct { - /// Low-Power Clock Division Factor - DIV: u8, - }), base_address + 0x5); - - /// address: 0x40000810 - /// AHB Mask - pub const AHBMASK = @intToPtr(*volatile Mmio(32, packed struct { - /// HPB0 AHB Clock Mask - HPB0_: u1, - /// HPB1 AHB Clock Mask - HPB1_: u1, - /// HPB2 AHB Clock Mask - HPB2_: u1, - /// HPB3 AHB Clock Mask - HPB3_: u1, - /// DSU AHB Clock Mask - DSU_: u1, - /// HMATRIX AHB Clock Mask - HMATRIX_: u1, - /// NVMCTRL AHB Clock Mask - NVMCTRL_: u1, - /// HSRAM AHB Clock Mask - HSRAM_: u1, - /// CMCC AHB Clock Mask - CMCC_: u1, - /// DMAC AHB Clock Mask - DMAC_: u1, - /// USB AHB Clock Mask - USB_: u1, - /// BKUPRAM AHB Clock Mask - BKUPRAM_: u1, - /// PAC AHB Clock Mask - PAC_: u1, - /// QSPI AHB Clock Mask - QSPI_: u1, - reserved0: u1, - /// SDHC0 AHB Clock Mask - SDHC0_: u1, - reserved1: u1, - /// CAN0 AHB Clock Mask - CAN0_: u1, - /// CAN1 AHB Clock Mask - CAN1_: u1, - /// ICM AHB Clock Mask - ICM_: u1, - /// PUKCC AHB Clock Mask - PUKCC_: u1, - /// QSPI_2X AHB Clock Mask - QSPI_2X_: u1, - /// NVMCTRL_SMEEPROM AHB Clock Mask - NVMCTRL_SMEEPROM_: u1, - /// NVMCTRL_CACHE AHB Clock Mask - NVMCTRL_CACHE_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// APBA Mask - pub const APBAMASK = @intToPtr(*volatile Mmio(32, packed struct { - /// PAC APB Clock Enable - PAC_: u1, - /// PM APB Clock Enable - PM_: u1, - /// MCLK APB Clock Enable - MCLK_: u1, - /// RSTC APB Clock Enable - RSTC_: u1, - /// OSCCTRL APB Clock Enable - OSCCTRL_: u1, - /// OSC32KCTRL APB Clock Enable - OSC32KCTRL_: u1, - /// SUPC APB Clock Enable - SUPC_: u1, - /// GCLK APB Clock Enable - GCLK_: u1, - /// WDT APB Clock Enable - WDT_: u1, - /// RTC APB Clock Enable - RTC_: u1, - /// EIC APB Clock Enable - EIC_: u1, - /// FREQM APB Clock Enable - FREQM_: u1, - /// SERCOM0 APB Clock Enable - SERCOM0_: u1, - /// SERCOM1 APB Clock Enable - SERCOM1_: u1, - /// TC0 APB Clock Enable - TC0_: u1, - /// TC1 APB Clock Enable - TC1_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// APBB Mask - pub const APBBMASK = @intToPtr(*volatile Mmio(32, packed struct { - /// USB APB Clock Enable - USB_: u1, - /// DSU APB Clock Enable - DSU_: u1, - /// NVMCTRL APB Clock Enable - NVMCTRL_: u1, - reserved0: u1, - /// PORT APB Clock Enable - PORT_: u1, - reserved1: u1, - /// HMATRIX APB Clock Enable - HMATRIX_: u1, - /// EVSYS APB Clock Enable - EVSYS_: u1, - reserved2: u1, - /// SERCOM2 APB Clock Enable - SERCOM2_: u1, - /// SERCOM3 APB Clock Enable - SERCOM3_: u1, - /// TCC0 APB Clock Enable - TCC0_: u1, - /// TCC1 APB Clock Enable - TCC1_: u1, - /// TC2 APB Clock Enable - TC2_: u1, - /// TC3 APB Clock Enable - TC3_: u1, - reserved3: u1, - /// RAMECC APB Clock Enable - RAMECC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - - /// address: 0x4000081c - /// APBC Mask - pub const APBCMASK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TCC2 APB Clock Enable - TCC2_: u1, - /// TCC3 APB Clock Enable - TCC3_: u1, - /// TC4 APB Clock Enable - TC4_: u1, - /// TC5 APB Clock Enable - TC5_: u1, - /// PDEC APB Clock Enable - PDEC_: u1, - /// AC APB Clock Enable - AC_: u1, - /// AES APB Clock Enable - AES_: u1, - /// TRNG APB Clock Enable - TRNG_: u1, - /// ICM APB Clock Enable - ICM_: u1, - reserved3: u1, - /// QSPI APB Clock Enable - QSPI_: u1, - /// CCL APB Clock Enable - CCL_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// APBD Mask - pub const APBDMASK = @intToPtr(*volatile Mmio(32, packed struct { - /// SERCOM4 APB Clock Enable - SERCOM4_: u1, - /// SERCOM5 APB Clock Enable - SERCOM5_: u1, - reserved0: u1, - reserved1: u1, - /// TCC4 APB Clock Enable - TCC4_: u1, - reserved2: u1, - reserved3: u1, - /// ADC0 APB Clock Enable - ADC0_: u1, - /// ADC1 APB Clock Enable - ADC1_: u1, - /// DAC APB Clock Enable - DAC_: u1, - /// I2S APB Clock Enable - I2S_: u1, - /// PCC APB Clock Enable - PCC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - }; - - /// Non-Volatile Memory Controller - pub const NVMCTRL = struct { - pub const base_address = 0x41004000; - pub const version = "U24091.0.0"; - - /// address: 0x41004000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Auto Wait State Enable - AUTOWS: u1, - /// Suspend Enable - SUSPEN: u1, - /// Write Mode - WMODE: u2, - /// Power Reduction Mode during Sleep - PRM: u2, - /// NVM Read Wait States - RWS: u4, - /// Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated - AHBNS0: u1, - /// Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated - AHBNS1: u1, - /// AHB0 Cache Disable - CACHEDIS0: u1, - /// AHB1 Cache Disable - CACHEDIS1: u1, - }), base_address + 0x0); - - /// address: 0x41004004 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// Command - CMD: u7, - reserved0: u1, - /// Command Execution - CMDEX: u8, - }), base_address + 0x4); - - /// address: 0x41004008 - /// NVM Parameter - pub const PARAM = @intToPtr(*volatile Mmio(32, packed struct { - /// NVM Pages - NVMP: u16, - /// Page Size - PSZ: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// SmartEEPROM Supported - SEE: u1, - }), base_address + 0x8); - - /// address: 0x4100400c - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Done Interrupt Clear - DONE: u1, - /// Address Error - ADDRE: u1, - /// Programming Error Interrupt Clear - PROGE: u1, - /// Lock Error Interrupt Clear - LOCKE: u1, - /// ECC Single Error Interrupt Clear - ECCSE: u1, - /// ECC Dual Error Interrupt Clear - ECCDE: u1, - /// NVM Error Interrupt Clear - NVME: u1, - /// Suspended Write Or Erase Interrupt Clear - SUSP: u1, - /// Active SEES Full Interrupt Clear - SEESFULL: u1, - /// Active SEES Overflow Interrupt Clear - SEESOVF: u1, - /// SEE Write Completed Interrupt Clear - SEEWRC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0xc); - - /// address: 0x4100400e - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Done Interrupt Enable - DONE: u1, - /// Address Error Interrupt Enable - ADDRE: u1, - /// Programming Error Interrupt Enable - PROGE: u1, - /// Lock Error Interrupt Enable - LOCKE: u1, - /// ECC Single Error Interrupt Enable - ECCSE: u1, - /// ECC Dual Error Interrupt Enable - ECCDE: u1, - /// NVM Error Interrupt Enable - NVME: u1, - /// Suspended Write Or Erase Interrupt Enable - SUSP: u1, - /// Active SEES Full Interrupt Enable - SEESFULL: u1, - /// Active SEES Overflow Interrupt Enable - SEESOVF: u1, - /// SEE Write Completed Interrupt Enable - SEEWRC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0xe); - - /// address: 0x41004010 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Done - DONE: u1, - /// Address Error - ADDRE: u1, - /// Programming Error - PROGE: u1, - /// Lock Error - LOCKE: u1, - /// ECC Single Error - ECCSE: u1, - /// ECC Dual Error - ECCDE: u1, - /// NVM Error - NVME: u1, - /// Suspended Write Or Erase Operation - SUSP: u1, - /// Active SEES Full - SEESFULL: u1, - /// Active SEES Overflow - SEESOVF: u1, - /// SEE Write Completed - SEEWRC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x10); - - /// address: 0x41004012 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Ready to accept a command - READY: u1, - /// Power Reduction Mode - PRM: u1, - /// NVM Page Buffer Active Loading - LOAD: u1, - /// NVM Write Or Erase Operation Is Suspended - SUSP: u1, - /// BANKA First - AFIRST: u1, - /// Boot Loader Protection Disable - BPDIS: u1, - reserved0: u1, - reserved1: u1, - /// Boot Loader Protection Size - BOOTPROT: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x12); - - /// address: 0x41004014 - /// Address - pub const ADDR = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x14); - - /// address: 0x41004018 - /// Lock Section - pub const RUNLOCK = @intToPtr(*volatile u32, base_address + 0x18); - - /// address: 0x4100401c - /// Page Buffer Load Data x - pub const PBLDATA = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Page Buffer Data - DATA: u32, - }), base_address + 0x1c); - - /// address: 0x41004024 - /// ECC Error Status Register - pub const ECCERR = @intToPtr(*volatile Mmio(32, packed struct { - /// Error Address - ADDR: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Low Double-Word Error Type - TYPEL: u2, - /// High Double-Word Error Type - TYPEH: u2, - }), base_address + 0x24); - - /// address: 0x41004028 - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debugger ECC Read Disable - ECCDIS: u1, - /// Debugger ECC Error Tracking Mode - ECCELOG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x28); - - /// address: 0x4100402a - /// SmartEEPROM Configuration Register - pub const SEECFG = @intToPtr(*volatile Mmio(8, packed struct { - /// Write Mode - WMODE: u1, - /// Automatic Page Reallocation Disable - APRDIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2a); - - /// address: 0x4100402c - /// SmartEEPROM Status Register - pub const SEESTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Active SmartEEPROM Sector - ASEES: u1, - /// Page Buffer Loaded - LOAD: u1, - /// Busy - BUSY: u1, - /// SmartEEPROM Write Access Is Locked - LOCK: u1, - /// SmartEEPROM Write Access To Register Address Space Is Locked - RLOCK: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Blocks Number In a Sector - SBLK: u4, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// SmartEEPROM Page Size - PSZ: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x2c); - }; - - /// Oscillators Control - pub const OSCCTRL = struct { - pub const base_address = 0x40001000; - pub const version = "U24011.0.0"; - - /// address: 0x40001000 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock 0 Failure Detector Event Output Enable - CFDEO0: u1, - /// Clock 1 Failure Detector Event Output Enable - CFDEO1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC 0 Ready Interrupt Enable - XOSCRDY0: u1, - /// XOSC 1 Ready Interrupt Enable - XOSCRDY1: u1, - /// XOSC 0 Clock Failure Detector Interrupt Enable - XOSCFAIL0: u1, - /// XOSC 1 Clock Failure Detector Interrupt Enable - XOSCFAIL1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DFLL Ready Interrupt Enable - DFLLRDY: u1, - /// DFLL Out Of Bounds Interrupt Enable - DFLLOOB: u1, - /// DFLL Lock Fine Interrupt Enable - DFLLLCKF: u1, - /// DFLL Lock Coarse Interrupt Enable - DFLLLCKC: u1, - /// DFLL Reference Clock Stopped Interrupt Enable - DFLLRCS: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// DPLL0 Lock Rise Interrupt Enable - DPLL0LCKR: u1, - /// DPLL0 Lock Fall Interrupt Enable - DPLL0LCKF: u1, - /// DPLL0 Lock Timeout Interrupt Enable - DPLL0LTO: u1, - /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable - DPLL0LDRTO: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DPLL1 Lock Rise Interrupt Enable - DPLL1LCKR: u1, - /// DPLL1 Lock Fall Interrupt Enable - DPLL1LCKF: u1, - /// DPLL1 Lock Timeout Interrupt Enable - DPLL1LTO: u1, - /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable - DPLL1LDRTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40001008 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC 0 Ready Interrupt Enable - XOSCRDY0: u1, - /// XOSC 1 Ready Interrupt Enable - XOSCRDY1: u1, - /// XOSC 0 Clock Failure Detector Interrupt Enable - XOSCFAIL0: u1, - /// XOSC 1 Clock Failure Detector Interrupt Enable - XOSCFAIL1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DFLL Ready Interrupt Enable - DFLLRDY: u1, - /// DFLL Out Of Bounds Interrupt Enable - DFLLOOB: u1, - /// DFLL Lock Fine Interrupt Enable - DFLLLCKF: u1, - /// DFLL Lock Coarse Interrupt Enable - DFLLLCKC: u1, - /// DFLL Reference Clock Stopped Interrupt Enable - DFLLRCS: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// DPLL0 Lock Rise Interrupt Enable - DPLL0LCKR: u1, - /// DPLL0 Lock Fall Interrupt Enable - DPLL0LCKF: u1, - /// DPLL0 Lock Timeout Interrupt Enable - DPLL0LTO: u1, - /// DPLL0 Loop Divider Ratio Update Complete Interrupt Enable - DPLL0LDRTO: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DPLL1 Lock Rise Interrupt Enable - DPLL1LCKR: u1, - /// DPLL1 Lock Fall Interrupt Enable - DPLL1LCKF: u1, - /// DPLL1 Lock Timeout Interrupt Enable - DPLL1LTO: u1, - /// DPLL1 Loop Divider Ratio Update Complete Interrupt Enable - DPLL1LDRTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4000100c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC 0 Ready - XOSCRDY0: u1, - /// XOSC 1 Ready - XOSCRDY1: u1, - /// XOSC 0 Clock Failure Detector - XOSCFAIL0: u1, - /// XOSC 1 Clock Failure Detector - XOSCFAIL1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DFLL Ready - DFLLRDY: u1, - /// DFLL Out Of Bounds - DFLLOOB: u1, - /// DFLL Lock Fine - DFLLLCKF: u1, - /// DFLL Lock Coarse - DFLLLCKC: u1, - /// DFLL Reference Clock Stopped - DFLLRCS: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// DPLL0 Lock Rise - DPLL0LCKR: u1, - /// DPLL0 Lock Fall - DPLL0LCKF: u1, - /// DPLL0 Lock Timeout - DPLL0LTO: u1, - /// DPLL0 Loop Divider Ratio Update Complete - DPLL0LDRTO: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DPLL1 Lock Rise - DPLL1LCKR: u1, - /// DPLL1 Lock Fall - DPLL1LCKF: u1, - /// DPLL1 Lock Timeout - DPLL1LTO: u1, - /// DPLL1 Loop Divider Ratio Update Complete - DPLL1LDRTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC 0 Ready - XOSCRDY0: u1, - /// XOSC 1 Ready - XOSCRDY1: u1, - /// XOSC 0 Clock Failure Detector - XOSCFAIL0: u1, - /// XOSC 1 Clock Failure Detector - XOSCFAIL1: u1, - /// XOSC 0 Clock Switch - XOSCCKSW0: u1, - /// XOSC 1 Clock Switch - XOSCCKSW1: u1, - reserved0: u1, - reserved1: u1, - /// DFLL Ready - DFLLRDY: u1, - /// DFLL Out Of Bounds - DFLLOOB: u1, - /// DFLL Lock Fine - DFLLLCKF: u1, - /// DFLL Lock Coarse - DFLLLCKC: u1, - /// DFLL Reference Clock Stopped - DFLLRCS: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// DPLL0 Lock Rise - DPLL0LCKR: u1, - /// DPLL0 Lock Fall - DPLL0LCKF: u1, - /// DPLL0 Timeout - DPLL0TO: u1, - /// DPLL0 Loop Divider Ratio Update Complete - DPLL0LDRTO: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// DPLL1 Lock Rise - DPLL1LCKR: u1, - /// DPLL1 Lock Fall - DPLL1LCKF: u1, - /// DPLL1 Timeout - DPLL1TO: u1, - /// DPLL1 Loop Divider Ratio Update Complete - DPLL1LDRTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// External Multipurpose Crystal Oscillator Control - pub const XOSCCTRL = @intToPtr(*volatile [2]Mmio(32, packed struct { - reserved0: u1, - /// Oscillator Enable - ENABLE: u1, - /// Crystal Oscillator Enable - XTALEN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - /// Low Buffer Gain Enable - LOWBUFGAIN: u1, - /// Oscillator Current Reference - IPTAT: u2, - /// Oscillator Current Multiplier - IMULT: u4, - /// Automatic Loop Control Enable - ENALC: u1, - /// Clock Failure Detector Enable - CFDEN: u1, - /// Xosc Clock Switch Enable - SWBEN: u1, - reserved4: u1, - reserved5: u1, - /// Start-Up Time - STARTUP: u4, - /// Clock Failure Detector Prescaler - CFDPRESC: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x14); - - /// address: 0x4000101c - /// DFLL48M Control A - pub const DFLLCTRLA = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// DFLL Enable - ENABLE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - }), base_address + 0x1c); - - /// address: 0x40001020 - /// DFLL48M Control B - pub const DFLLCTRLB = @intToPtr(*volatile Mmio(8, packed struct { - /// Operating Mode Selection - MODE: u1, - /// Stable DFLL Frequency - STABLE: u1, - /// Lose Lock After Wake - LLAW: u1, - /// USB Clock Recovery Mode - USBCRM: u1, - /// Chill Cycle Disable - CCDIS: u1, - /// Quick Lock Disable - QLDIS: u1, - /// Bypass Coarse Lock - BPLCKC: u1, - /// Wait Lock - WAITLOCK: u1, - }), base_address + 0x20); - - /// address: 0x40001024 - /// DFLL48M Value - pub const DFLLVAL = @intToPtr(*volatile Mmio(32, packed struct { - /// Fine Value - FINE: u8, - reserved0: u1, - reserved1: u1, - /// Coarse Value - COARSE: u6, - /// Multiplication Ratio Difference - DIFF: u16, - }), base_address + 0x24); - - /// address: 0x40001028 - /// DFLL48M Multiplier - pub const DFLLMUL = @intToPtr(*volatile Mmio(32, packed struct { - /// DFLL Multiply Factor - MUL: u16, - /// Fine Maximum Step - FSTEP: u8, - reserved0: u1, - reserved1: u1, - /// Coarse Maximum Step - CSTEP: u6, - }), base_address + 0x28); - - /// address: 0x4000102c - /// DFLL48M Synchronization - pub const DFLLSYNC = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// ENABLE Synchronization Busy - ENABLE: u1, - /// DFLLCTRLB Synchronization Busy - DFLLCTRLB: u1, - /// DFLLVAL Synchronization Busy - DFLLVAL: u1, - /// DFLLMUL Synchronization Busy - DFLLMUL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x2c); - - pub const DPLL = @ptrCast(*volatile [2]packed struct { - /// DPLL Control A - DPLLCTRLA: Mmio(8, packed struct { - reserved0: u1, - /// DPLL Enable - ENABLE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - }), - - /// DPLL Ratio Control - DPLLRATIO: Mmio(32, packed struct { - /// Loop Divider Ratio - LDR: u13, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Loop Divider Ratio Fractional Part - LDRFRAC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), - - /// DPLL Control B - DPLLCTRLB: Mmio(32, packed struct { - /// Proportional Integral Filter Selection - FILTER: u4, - /// Wake Up Fast - WUF: u1, - /// Reference Clock Selection - REFCLK: u3, - /// Lock Time - LTIME: u3, - /// Lock Bypass - LBYPASS: u1, - /// Sigma-Delta DCO Filter Selection - DCOFILTER: u3, - /// DCO Filter Enable - DCOEN: u1, - /// Clock Divider - DIV: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), - - /// DPLL Synchronization Busy - DPLLSYNCBUSY: Mmio(32, packed struct { - reserved0: u1, - /// DPLL Enable Synchronization Status - ENABLE: u1, - /// DPLL Loop Divider Ratio Synchronization Status - DPLLRATIO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), - - /// DPLL Status - DPLLSTATUS: Mmio(32, packed struct { - /// DPLL Lock Status - LOCK: u1, - /// DPLL Clock Ready - CLKRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), - }, base_address + 0x30); - }; - - /// 32kHz Oscillators Control - pub const OSC32KCTRL = struct { - pub const base_address = 0x40001400; - pub const version = "U24001.0.0"; - - /// address: 0x40001400 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC32K Ready Interrupt Enable - XOSC32KRDY: u1, - reserved0: u1, - /// XOSC32K Clock Failure Detector Interrupt Enable - XOSC32KFAIL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC32K Ready Interrupt Enable - XOSC32KRDY: u1, - reserved0: u1, - /// XOSC32K Clock Failure Detector Interrupt Enable - XOSC32KFAIL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0x40001408 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC32K Ready - XOSC32KRDY: u1, - reserved0: u1, - /// XOSC32K Clock Failure Detector - XOSC32KFAIL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x8); - - /// address: 0x4000140c - /// Power and Clocks Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// XOSC32K Ready - XOSC32KRDY: u1, - reserved0: u1, - /// XOSC32K Clock Failure Detector - XOSC32KFAIL: u1, - /// XOSC32K Clock switch - XOSC32KSW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// RTC Clock Selection - pub const RTCCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// RTC Clock Selection - RTCSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// 32kHz External Crystal Oscillator (XOSC32K) Control - pub const XOSC32K = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - /// Oscillator Enable - ENABLE: u1, - /// Crystal Oscillator Enable - XTALEN: u1, - /// 32kHz Output Enable - EN32K: u1, - /// 1kHz Output Enable - EN1K: u1, - reserved1: u1, - /// Run in Standby - RUNSTDBY: u1, - /// On Demand Control - ONDEMAND: u1, - /// Oscillator Start-Up Time - STARTUP: u3, - reserved2: u1, - /// Write Lock - WRTLOCK: u1, - /// Control Gain Mode - CGM: u2, - padding0: u1, - }), base_address + 0x14); - - /// address: 0x40001416 - /// Clock Failure Detector Control - pub const CFDCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Failure Detector Enable - CFDEN: u1, - /// Clock Switch Back - SWBACK: u1, - /// Clock Failure Detector Prescaler - CFDPRESC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x16); - - /// address: 0x40001417 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Clock Failure Detector Event Output Enable - CFDEO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x17); - - /// address: 0x4000141c - /// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control - pub const OSCULP32K = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable Out 32k - EN32K: u1, - /// Enable Out 1k - EN1K: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Oscillator Calibration - CALIB: u6, - reserved6: u1, - /// Write Lock - WRTLOCK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - }; - - /// Peripheral Access Controller - pub const PAC = struct { - pub const base_address = 0x40000000; - pub const version = "U21201.2.0"; - - /// address: 0x40000000 - /// Write control - pub const WRCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral identifier - PERID: u16, - /// Peripheral access control key - KEY: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// Event control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Peripheral acess error event output - ERREO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// Interrupt enable clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Peripheral access error interrupt disable - ERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x40000009 - /// Interrupt enable set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Peripheral access error interrupt enable - ERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x9); - - /// address: 0x40000010 - /// Bridge interrupt flag status - pub const INTFLAGAHB = @intToPtr(*volatile Mmio(32, packed struct { - /// FLASH - FLASH_: u1, - /// FLASH_ALT - FLASH_ALT_: u1, - /// SEEPROM - SEEPROM_: u1, - /// RAMCM4S - RAMCM4S_: u1, - /// RAMPPPDSU - RAMPPPDSU_: u1, - /// RAMDMAWR - RAMDMAWR_: u1, - /// RAMDMACICM - RAMDMACICM_: u1, - /// HPB0 - HPB0_: u1, - /// HPB1 - HPB1_: u1, - /// HPB2 - HPB2_: u1, - /// HPB3 - HPB3_: u1, - /// PUKCC - PUKCC_: u1, - /// SDHC0 - SDHC0_: u1, - reserved0: u1, - /// QSPI - QSPI_: u1, - /// BKUPRAM - BKUPRAM_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// Peripheral interrupt flag status - Bridge A - pub const INTFLAGA = @intToPtr(*volatile Mmio(32, packed struct { - /// PAC - PAC_: u1, - /// PM - PM_: u1, - /// MCLK - MCLK_: u1, - /// RSTC - RSTC_: u1, - /// OSCCTRL - OSCCTRL_: u1, - /// OSC32KCTRL - OSC32KCTRL_: u1, - /// SUPC - SUPC_: u1, - /// GCLK - GCLK_: u1, - /// WDT - WDT_: u1, - /// RTC - RTC_: u1, - /// EIC - EIC_: u1, - /// FREQM - FREQM_: u1, - /// SERCOM0 - SERCOM0_: u1, - /// SERCOM1 - SERCOM1_: u1, - /// TC0 - TC0_: u1, - /// TC1 - TC1_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// Peripheral interrupt flag status - Bridge B - pub const INTFLAGB = @intToPtr(*volatile Mmio(32, packed struct { - /// USB - USB_: u1, - /// DSU - DSU_: u1, - /// NVMCTRL - NVMCTRL_: u1, - /// CMCC - CMCC_: u1, - /// PORT - PORT_: u1, - /// DMAC - DMAC_: u1, - /// HMATRIX - HMATRIX_: u1, - /// EVSYS - EVSYS_: u1, - reserved0: u1, - /// SERCOM2 - SERCOM2_: u1, - /// SERCOM3 - SERCOM3_: u1, - /// TCC0 - TCC0_: u1, - /// TCC1 - TCC1_: u1, - /// TC2 - TC2_: u1, - /// TC3 - TC3_: u1, - reserved1: u1, - /// RAMECC - RAMECC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - - /// address: 0x4000001c - /// Peripheral interrupt flag status - Bridge C - pub const INTFLAGC = @intToPtr(*volatile Mmio(32, packed struct { - /// CAN0 - CAN0_: u1, - /// CAN1 - CAN1_: u1, - reserved0: u1, - /// TCC2 - TCC2_: u1, - /// TCC3 - TCC3_: u1, - /// TC4 - TC4_: u1, - /// TC5 - TC5_: u1, - /// PDEC - PDEC_: u1, - /// AC - AC_: u1, - /// AES - AES_: u1, - /// TRNG - TRNG_: u1, - /// ICM - ICM_: u1, - /// PUKCC - PUKCC_: u1, - /// QSPI - QSPI_: u1, - /// CCL - CCL_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// Peripheral interrupt flag status - Bridge D - pub const INTFLAGD = @intToPtr(*volatile Mmio(32, packed struct { - /// SERCOM4 - SERCOM4_: u1, - /// SERCOM5 - SERCOM5_: u1, - reserved0: u1, - reserved1: u1, - /// TCC4 - TCC4_: u1, - reserved2: u1, - reserved3: u1, - /// ADC0 - ADC0_: u1, - /// ADC1 - ADC1_: u1, - /// DAC - DAC_: u1, - /// I2S - I2S_: u1, - /// PCC - PCC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40000034 - /// Peripheral write protection status - Bridge A - pub const STATUSA = @intToPtr(*volatile Mmio(32, packed struct { - /// PAC APB Protect Enable - PAC_: u1, - /// PM APB Protect Enable - PM_: u1, - /// MCLK APB Protect Enable - MCLK_: u1, - /// RSTC APB Protect Enable - RSTC_: u1, - /// OSCCTRL APB Protect Enable - OSCCTRL_: u1, - /// OSC32KCTRL APB Protect Enable - OSC32KCTRL_: u1, - /// SUPC APB Protect Enable - SUPC_: u1, - /// GCLK APB Protect Enable - GCLK_: u1, - /// WDT APB Protect Enable - WDT_: u1, - /// RTC APB Protect Enable - RTC_: u1, - /// EIC APB Protect Enable - EIC_: u1, - /// FREQM APB Protect Enable - FREQM_: u1, - /// SERCOM0 APB Protect Enable - SERCOM0_: u1, - /// SERCOM1 APB Protect Enable - SERCOM1_: u1, - /// TC0 APB Protect Enable - TC0_: u1, - /// TC1 APB Protect Enable - TC1_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40000038 - /// Peripheral write protection status - Bridge B - pub const STATUSB = @intToPtr(*volatile Mmio(32, packed struct { - /// USB APB Protect Enable - USB_: u1, - /// DSU APB Protect Enable - DSU_: u1, - /// NVMCTRL APB Protect Enable - NVMCTRL_: u1, - /// CMCC APB Protect Enable - CMCC_: u1, - /// PORT APB Protect Enable - PORT_: u1, - /// DMAC APB Protect Enable - DMAC_: u1, - /// HMATRIX APB Protect Enable - HMATRIX_: u1, - /// EVSYS APB Protect Enable - EVSYS_: u1, - reserved0: u1, - /// SERCOM2 APB Protect Enable - SERCOM2_: u1, - /// SERCOM3 APB Protect Enable - SERCOM3_: u1, - /// TCC0 APB Protect Enable - TCC0_: u1, - /// TCC1 APB Protect Enable - TCC1_: u1, - /// TC2 APB Protect Enable - TC2_: u1, - /// TC3 APB Protect Enable - TC3_: u1, - reserved1: u1, - /// RAMECC APB Protect Enable - RAMECC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x38); - - /// address: 0x4000003c - /// Peripheral write protection status - Bridge C - pub const STATUSC = @intToPtr(*volatile Mmio(32, packed struct { - /// CAN0 APB Protect Enable - CAN0_: u1, - /// CAN1 APB Protect Enable - CAN1_: u1, - reserved0: u1, - /// TCC2 APB Protect Enable - TCC2_: u1, - /// TCC3 APB Protect Enable - TCC3_: u1, - /// TC4 APB Protect Enable - TC4_: u1, - /// TC5 APB Protect Enable - TC5_: u1, - /// PDEC APB Protect Enable - PDEC_: u1, - /// AC APB Protect Enable - AC_: u1, - /// AES APB Protect Enable - AES_: u1, - /// TRNG APB Protect Enable - TRNG_: u1, - /// ICM APB Protect Enable - ICM_: u1, - /// PUKCC APB Protect Enable - PUKCC_: u1, - /// QSPI APB Protect Enable - QSPI_: u1, - /// CCL APB Protect Enable - CCL_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3c); - - /// address: 0x40000040 - /// Peripheral write protection status - Bridge D - pub const STATUSD = @intToPtr(*volatile Mmio(32, packed struct { - /// SERCOM4 APB Protect Enable - SERCOM4_: u1, - /// SERCOM5 APB Protect Enable - SERCOM5_: u1, - reserved0: u1, - reserved1: u1, - /// TCC4 APB Protect Enable - TCC4_: u1, - reserved2: u1, - reserved3: u1, - /// ADC0 APB Protect Enable - ADC0_: u1, - /// ADC1 APB Protect Enable - ADC1_: u1, - /// DAC APB Protect Enable - DAC_: u1, - /// I2S APB Protect Enable - I2S_: u1, - /// PCC APB Protect Enable - PCC_: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x40); - }; - - /// Parallel Capture Controller - pub const PCC = struct { - pub const base_address = 0x43002c00; - pub const version = "U20171.1.0"; - - /// address: 0x43002c00 - /// Mode Register - pub const MR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parallel Capture Enable - PCEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Data size - DSIZE: u2, - reserved3: u1, - reserved4: u1, - /// Scale data - SCALE: u1, - /// Always Sampling - ALWYS: u1, - /// Half Sampling - HALFS: u1, - /// First sample - FRSTS: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Input Data Size - ISIZE: u3, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Clear If Disabled - CID: u2, - }), base_address + 0x0); - - /// address: 0x43002c04 - /// Interrupt Enable Register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Ready Interrupt Enable - DRDY: u1, - /// Overrun Error Interrupt Enable - OVRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x43002c08 - /// Interrupt Disable Register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Ready Interrupt Disable - DRDY: u1, - /// Overrun Error Interrupt Disable - OVRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x8); - - /// address: 0x43002c0c - /// Interrupt Mask Register - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Ready Interrupt Mask - DRDY: u1, - /// Overrun Error Interrupt Mask - OVRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x43002c10 - /// Interrupt Status Register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Ready Interrupt Status - DRDY: u1, - /// Overrun Error Interrupt Status - OVRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x10); - - /// address: 0x43002c14 - /// Reception Holding Register - pub const RHR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reception Data - RDATA: u32, - }), base_address + 0x14); - - /// address: 0x43002ce0 - /// Write Protection Mode Register - pub const WPMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write Protection Enable - WPEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Write Protection Key - WPKEY: u24, - }), base_address + 0xe0); - - /// address: 0x43002ce4 - /// Write Protection Status Register - pub const WPSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write Protection Violation Source - WPVS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Write Protection Violation Status - WPVSRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xe4); - }; - - /// Quadrature Decodeur - pub const PDEC = struct { - pub const base_address = 0x42001c00; - pub const version = "U22631.0.0"; - - /// address: 0x42001c00 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operation Mode - MODE: u2, - reserved0: u1, - reserved1: u1, - /// Run in Standby - RUNSTDBY: u1, - reserved2: u1, - /// PDEC Configuration - CONF: u3, - /// Auto Lock - ALOCK: u1, - reserved3: u1, - reserved4: u1, - /// PDEC Phase A and B Swap - SWAP: u1, - /// Period Enable - PEREN: u1, - /// PDEC Input From Pin 0 Enable - PINEN0: u1, - /// PDEC Input From Pin 1 Enable - PINEN1: u1, - /// PDEC Input From Pin 2 Enable - PINEN2: u1, - reserved5: u1, - /// IO Pin 0 Invert Enable - PINVEN0: u1, - /// IO Pin 1 Invert Enable - PINVEN1: u1, - /// IO Pin 2 Invert Enable - PINVEN2: u1, - reserved6: u1, - /// Angular Counter Length - ANGULAR: u3, - reserved7: u1, - /// Maximum Consecutive Missing Pulses - MAXCMP: u4, - }), base_address + 0x0); - - /// address: 0x42001c04 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Lock Update - LUPD: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x42001c05 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Lock Update - LUPD: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x42001c06 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Event Action - EVACT: u2, - /// Inverted Event Input Enable - EVINV: u3, - /// Event Input Enable - EVEI: u3, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Error Output Event Enable - ERREO: u1, - /// Direction Output Event Enable - DIREO: u1, - /// Velocity Output Event Enable - VLCEO: u1, - /// Match Channel 0 Event Output Enable - MCEO0: u1, - /// Match Channel 1 Event Output Enable - MCEO1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x6); - - /// address: 0x42001c08 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Overflow/Underflow Interrupt Disable - OVF: u1, - /// Error Interrupt Disable - ERR: u1, - /// Direction Interrupt Disable - DIR: u1, - /// Velocity Interrupt Disable - VLC: u1, - /// Channel 0 Compare Match Disable - MC0: u1, - /// Channel 1 Compare Match Disable - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0x42001c09 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Overflow/Underflow Interrupt Enable - OVF: u1, - /// Error Interrupt Enable - ERR: u1, - /// Direction Interrupt Enable - DIR: u1, - /// Velocity Interrupt Enable - VLC: u1, - /// Channel 0 Compare Match Enable - MC0: u1, - /// Channel 1 Compare Match Enable - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x9); - - /// address: 0x42001c0a - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Overflow/Underflow - OVF: u1, - /// Error - ERR: u1, - /// Direction Change - DIR: u1, - /// Velocity - VLC: u1, - /// Channel 0 Compare Match - MC0: u1, - /// Channel 1 Compare Match - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xa); - - /// address: 0x42001c0c - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Quadrature Error Flag - QERR: u1, - /// Index Error Flag - IDXERR: u1, - /// Missing Pulse Error flag - MPERR: u1, - reserved0: u1, - /// Window Error Flag - WINERR: u1, - /// Hall Error Flag - HERR: u1, - /// Stop - STOP: u1, - /// Direction Status Flag - DIR: u1, - /// Prescaler Buffer Valid - PRESCBUFV: u1, - /// Filter Buffer Valid - FILTERBUFV: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0x42001c0f - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Run Mode - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xf); - - /// address: 0x42001c10 - /// Synchronization Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// Enable Synchronization Busy - ENABLE: u1, - /// Control B Synchronization Busy - CTRLB: u1, - /// Status Synchronization Busy - STATUS: u1, - /// Prescaler Synchronization Busy - PRESC: u1, - /// Filter Synchronization Busy - FILTER: u1, - /// Count Synchronization Busy - COUNT: u1, - /// Compare Channel 0 Synchronization Busy - CC0: u1, - /// Compare Channel 1 Synchronization Busy - CC1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x10); - - /// address: 0x42001c14 - /// Prescaler Value - pub const PRESC = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x14); - - /// address: 0x42001c15 - /// Filter Value - pub const FILTER = @intToPtr(*volatile u8, base_address + 0x15); - - /// address: 0x42001c18 - /// Prescaler Buffer Value - pub const PRESCBUF = @intToPtr(*volatile MmioInt(8, u4), base_address + 0x18); - - /// address: 0x42001c19 - /// Filter Buffer Value - pub const FILTERBUF = @intToPtr(*volatile u8, base_address + 0x19); - - /// address: 0x42001c1c - /// Counter Value - pub const COUNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); - - /// address: 0x42001c20 - /// Channel n Compare Value - pub const CC = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x20); - - /// address: 0x42001c30 - /// Channel Compare Buffer Value - pub const CCBUF = @intToPtr(*volatile [2]MmioInt(32, u16), base_address + 0x30); - }; - - /// Power Manager - pub const PM = struct { - pub const base_address = 0x40000400; - pub const version = "U24061.0.0"; - - /// address: 0x40000400 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - reserved1: u1, - /// I/O Retention - IORET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x0); - - /// address: 0x40000401 - /// Sleep Configuration - pub const SLEEPCFG = @intToPtr(*volatile Mmio(8, packed struct { - /// Sleep Mode - SLEEPMODE: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1); - - /// address: 0x40000404 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Sleep Mode Entry Ready Enable - SLEEPRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x4); - - /// address: 0x40000405 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Sleep Mode Entry Ready Enable - SLEEPRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x5); - - /// address: 0x40000406 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Sleep Mode Entry Ready - SLEEPRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x6); - - /// address: 0x40000408 - /// Standby Configuration - pub const STDBYCFG = @intToPtr(*volatile Mmio(8, packed struct { - /// Ram Configuration - RAMCFG: u2, - reserved0: u1, - reserved1: u1, - /// Fast Wakeup - FASTWKUP: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0x40000409 - /// Hibernate Configuration - pub const HIBCFG = @intToPtr(*volatile Mmio(8, packed struct { - /// Ram Configuration - RAMCFG: u2, - /// Backup Ram Configuration - BRAMCFG: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x9); - - /// address: 0x4000040a - /// Backup Configuration - pub const BKUPCFG = @intToPtr(*volatile Mmio(8, packed struct { - /// Ram Configuration - BRAMCFG: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xa); - - /// address: 0x40000412 - /// Power Switch Acknowledge Delay - pub const PWSAKDLY = @intToPtr(*volatile Mmio(8, packed struct { - /// Delay Value - DLYVAL: u7, - /// Ignore Acknowledge - IGNACK: u1, - }), base_address + 0x12); - }; - - /// Port Module - pub const PORT = struct { - pub const base_address = @intToPtr([*]u8, 0x41008000); - pub const version = "U22102.2.0"; - - pub const GROUP = @ptrCast(*volatile [2]packed struct { - /// Data Direction - DIR: u32, - - /// Data Direction Clear - DIRCLR: u32, - - /// Data Direction Set - DIRSET: u32, - - /// Data Direction Toggle - DIRTGL: u32, - - /// Data Output Value - OUT: u32, - - /// Data Output Value Clear - OUTCLR: u32, - - /// Data Output Value Set - OUTSET: u32, - - /// Data Output Value Toggle - OUTTGL: u32, - - /// Data Input Value - IN: u32, - - /// Control - CTRL: Mmio(32, packed struct { - /// Input Sampling Mode - SAMPLING: u32, - }), - - /// Write Configuration - WRCONFIG: Mmio(32, packed struct { - /// Pin Mask for Multiple Pin Configuration - PINMASK: u16, - /// Peripheral Multiplexer Enable - PMUXEN: u1, - /// Input Enable - INEN: u1, - /// Pull Enable - PULLEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Output Driver Strength Selection - DRVSTR: u1, - reserved3: u1, - /// Peripheral Multiplexing - PMUX: u4, - /// Write PMUX - WRPMUX: u1, - reserved4: u1, - /// Write PINCFG - WRPINCFG: u1, - /// Half-Word Select - HWSEL: u1, - }), - - /// Event Input Control - EVCTRL: Mmio(32, packed struct { - /// PORT Event Pin Identifier 0 - PID0: u5, - /// PORT Event Action 0 - EVACT0: u2, - /// PORT Event Input Enable 0 - PORTEI0: u1, - /// PORT Event Pin Identifier 1 - PID1: u5, - /// PORT Event Action 1 - EVACT1: u2, - /// PORT Event Input Enable 1 - PORTEI1: u1, - /// PORT Event Pin Identifier 2 - PID2: u5, - /// PORT Event Action 2 - EVACT2: u2, - /// PORT Event Input Enable 2 - PORTEI2: u1, - /// PORT Event Pin Identifier 3 - PID3: u5, - /// PORT Event Action 3 - EVACT3: u2, - /// PORT Event Input Enable 3 - PORTEI3: u1, - }), - - /// Peripheral Multiplexing - PMUX: [16]Mmio(8, packed struct { - /// Peripheral Multiplexing for Even-Numbered Pin - PMUXE: u4, - /// Peripheral Multiplexing for Odd-Numbered Pin - PMUXO: u4, - }), - - /// Pin Configuration - PINCFG: [32]Mmio(8, packed struct { - /// Peripheral Multiplexer Enable - PMUXEN: u1, - /// Input Enable - INEN: u1, - /// Pull Enable - PULLEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Output Driver Strength Selection - DRVSTR: u1, - padding0: u1, - }), - padding0: u32, - padding1: u32, - padding2: u32, - padding3: u32, - padding4: u32, - padding5: u32, - padding6: u32, - padding7: u32, - //padding8: u32, - //padding9: u32, - //padding10: u32, - //padding11: u32, - //padding12: u32, - //padding13: u32, - //padding14: u32, - //padding15: u32, - //padding16: u32, - //padding17: u32, - //padding18: u32, - }, base_address); - }; - - /// Quad SPI interface - pub const QSPI = struct { - pub const base_address = 0x42003400; - pub const version = "U20081.6.3"; - - /// address: 0x42003400 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Last Transfer - LASTXFER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x0); - - /// address: 0x42003404 - /// Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Serial Memory Mode - MODE: u1, - /// Local Loopback Enable - LOOPEN: u1, - /// Wait Data Read Before Transfer - WDRBT: u1, - /// Serial Memory reg - SMEMREG: u1, - /// Chip Select Mode - CSMODE: u2, - reserved0: u1, - reserved1: u1, - /// Data Length - DATALEN: u4, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Delay Between Consecutive Transfers - DLYBCT: u8, - /// Minimum Inactive CS Delay - DLYCS: u8, - }), base_address + 0x4); - - /// address: 0x42003408 - /// Baud Rate - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock Polarity - CPOL: u1, - /// Clock Phase - CPHA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Serial Clock Baud Rate - BAUD: u8, - /// Delay Before SCK - DLYBS: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4200340c - /// Receive Data - pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x42003410 - /// Transmit Data - pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit Data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x42003414 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Data Register Full Interrupt Disable - RXC: u1, - /// Transmit Data Register Empty Interrupt Disable - DRE: u1, - /// Transmission Complete Interrupt Disable - TXC: u1, - /// Overrun Error Interrupt Disable - ERROR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Chip Select Rise Interrupt Disable - CSRISE: u1, - reserved4: u1, - /// Instruction End Interrupt Disable - INSTREND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x42003418 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Data Register Full Interrupt Enable - RXC: u1, - /// Transmit Data Register Empty Interrupt Enable - DRE: u1, - /// Transmission Complete Interrupt Enable - TXC: u1, - /// Overrun Error Interrupt Enable - ERROR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Chip Select Rise Interrupt Enable - CSRISE: u1, - reserved4: u1, - /// Instruction End Interrupt Enable - INSTREND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18); - - /// address: 0x4200341c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Data Register Full - RXC: u1, - /// Transmit Data Register Empty - DRE: u1, - /// Transmission Complete - TXC: u1, - /// Overrun Error - ERROR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Chip Select Rise - CSRISE: u1, - reserved4: u1, - /// Instruction End - INSTREND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c); - - /// address: 0x42003420 - /// Status Register - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Chip Select - CSSTATUS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - - /// address: 0x42003430 - /// Instruction Address - pub const INSTRADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Instruction Address - ADDR: u32, - }), base_address + 0x30); - - /// address: 0x42003434 - /// Instruction Code - pub const INSTRCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Instruction Code - INSTR: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Option Code - OPTCODE: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42003438 - /// Instruction Frame - pub const INSTRFRAME = @intToPtr(*volatile Mmio(32, packed struct { - /// Instruction Code, Address, Option Code and Data Width - WIDTH: u3, - reserved0: u1, - /// Instruction Enable - INSTREN: u1, - /// Address Enable - ADDREN: u1, - /// Option Enable - OPTCODEEN: u1, - /// Data Enable - DATAEN: u1, - /// Option Code Length - OPTCODELEN: u2, - /// Address Length - ADDRLEN: u1, - reserved1: u1, - /// Data Transfer Type - TFRTYPE: u2, - /// Continuous Read Mode - CRMODE: u1, - /// Double Data Rate Enable - DDREN: u1, - /// Dummy Cycles Length - DUMMYLEN: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x38); - - /// address: 0x42003440 - /// Scrambling Mode - pub const SCRAMBCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Scrambling/Unscrambling Enable - ENABLE: u1, - /// Scrambling/Unscrambling Random Value Disable - RANDOMDIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x40); - - /// address: 0x42003444 - /// Scrambling Key - pub const SCRAMBKEY = @intToPtr(*volatile Mmio(32, packed struct { - /// Scrambling User Key - KEY: u32, - }), base_address + 0x44); - }; - - /// RAM ECC - pub const RAMECC = struct { - pub const base_address = 0x41020000; - pub const version = "U22681.0.0"; - - /// address: 0x41020000 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Single Bit ECC Error Interrupt Enable Clear - SINGLEE: u1, - /// Dual Bit ECC Error Interrupt Enable Clear - DUALE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x41020001 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Single Bit ECC Error Interrupt Enable Set - SINGLEE: u1, - /// Dual Bit ECC Error Interrupt Enable Set - DUALE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1); - - /// address: 0x41020002 - /// Interrupt Flag - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Single Bit ECC Error Interrupt - SINGLEE: u1, - /// Dual Bit ECC Error Interrupt - DUALE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2); - - /// address: 0x41020003 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// ECC Disable - ECCDIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x3); - - /// address: 0x41020004 - /// Error Address - pub const ERRADDR = @intToPtr(*volatile MmioInt(32, u17), base_address + 0x4); - - /// address: 0x4102000f - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// ECC Disable - ECCDIS: u1, - /// ECC Error Log - ECCELOG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xf); - }; - - /// Reset Controller - pub const RSTC = struct { - pub const base_address = 0x40000c00; - pub const version = "U22394.0.0"; - - /// address: 0x40000c00 - /// Reset Cause - pub const RCAUSE = @intToPtr(*volatile Mmio(8, packed struct { - /// Power On Reset - POR: u1, - /// Brown Out CORE Detector Reset - BODCORE: u1, - /// Brown Out VDD Detector Reset - BODVDD: u1, - /// NVM Reset - NVM: u1, - /// External Reset - EXT: u1, - /// Watchdog Reset - WDT: u1, - /// System Reset Request - SYST: u1, - /// Backup Reset - BACKUP: u1, - }), base_address + 0x0); - - /// address: 0x40000c02 - /// Backup Exit Source - pub const BKUPEXIT = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Real Timer Counter Interrupt - RTC: u1, - /// Battery Backup Power Switch - BBPS: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Hibernate - HIB: u1, - }), base_address + 0x2); - }; - - /// Real-Time Counter - pub const RTC = struct { - pub const base_address = 0x40002400; - pub const version = "U22502.1.0"; - - /// 32-bit Counter with Single 32-bit Compare - pub const MODE0 = struct { - /// address: 0x40002400 - /// MODE0 Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Clear on Match - MATCHCLR: u1, - /// Prescaler - PRESCALER: u4, - reserved3: u1, - /// BKUP Registers Reset On Tamper Enable - BKTRST: u1, - /// GP Registers Reset On Tamper Enable - GPTRST: u1, - /// Count Read Synchronization Enable - COUNTSYNC: u1, - }), base_address + 0x0); - - /// address: 0x40002402 - /// MODE0 Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// General Purpose 0 Enable - GP0EN: u1, - /// General Purpose 2 Enable - GP2EN: u1, - reserved0: u1, - reserved1: u1, - /// Debouncer Majority Enable - DEBMAJ: u1, - /// Debouncer Asynchronous Enable - DEBASYNC: u1, - /// RTC Output Enable - RTCOUT: u1, - /// DMA Enable - DMAEN: u1, - /// Debounce Freqnuency - DEBF: u3, - reserved2: u1, - /// Active Layer Freqnuency - ACTF: u3, - padding0: u1, - }), base_address + 0x2); - - /// address: 0x40002404 - /// MODE0 Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic Interval 0 Event Output Enable - PEREO0: u1, - /// Periodic Interval 1 Event Output Enable - PEREO1: u1, - /// Periodic Interval 2 Event Output Enable - PEREO2: u1, - /// Periodic Interval 3 Event Output Enable - PEREO3: u1, - /// Periodic Interval 4 Event Output Enable - PEREO4: u1, - /// Periodic Interval 5 Event Output Enable - PEREO5: u1, - /// Periodic Interval 6 Event Output Enable - PEREO6: u1, - /// Periodic Interval 7 Event Output Enable - PEREO7: u1, - /// Compare 0 Event Output Enable - CMPEO0: u1, - /// Compare 1 Event Output Enable - CMPEO1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Event Output Enable - TAMPEREO: u1, - /// Overflow Event Output Enable - OVFEO: u1, - /// Tamper Event Input Enable - TAMPEVEI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x4); - - /// address: 0x40002408 - /// MODE0 Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Interrupt Enable - PER0: u1, - /// Periodic Interval 1 Interrupt Enable - PER1: u1, - /// Periodic Interval 2 Interrupt Enable - PER2: u1, - /// Periodic Interval 3 Interrupt Enable - PER3: u1, - /// Periodic Interval 4 Interrupt Enable - PER4: u1, - /// Periodic Interval 5 Interrupt Enable - PER5: u1, - /// Periodic Interval 6 Interrupt Enable - PER6: u1, - /// Periodic Interval 7 Interrupt Enable - PER7: u1, - /// Compare 0 Interrupt Enable - CMP0: u1, - /// Compare 1 Interrupt Enable - CMP1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0x8); - - /// address: 0x4000240a - /// MODE0 Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Interrupt Enable - PER0: u1, - /// Periodic Interval 1 Interrupt Enable - PER1: u1, - /// Periodic Interval 2 Interrupt Enable - PER2: u1, - /// Periodic Interval 3 Interrupt Enable - PER3: u1, - /// Periodic Interval 4 Interrupt Enable - PER4: u1, - /// Periodic Interval 5 Interrupt Enable - PER5: u1, - /// Periodic Interval 6 Interrupt Enable - PER6: u1, - /// Periodic Interval 7 Interrupt Enable - PER7: u1, - /// Compare 0 Interrupt Enable - CMP0: u1, - /// Compare 1 Interrupt Enable - CMP1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0xa); - - /// address: 0x4000240c - /// MODE0 Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 - PER0: u1, - /// Periodic Interval 1 - PER1: u1, - /// Periodic Interval 2 - PER2: u1, - /// Periodic Interval 3 - PER3: u1, - /// Periodic Interval 4 - PER4: u1, - /// Periodic Interval 5 - PER5: u1, - /// Periodic Interval 6 - PER6: u1, - /// Periodic Interval 7 - PER7: u1, - /// Compare 0 - CMP0: u1, - /// Compare 1 - CMP1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper - TAMPER: u1, - /// Overflow - OVF: u1, - }), base_address + 0xc); - - /// address: 0x4000240e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xe); - - /// address: 0x40002410 - /// MODE0 Synchronization Busy Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Busy - SWRST: u1, - /// Enable Bit Busy - ENABLE: u1, - /// FREQCORR Register Busy - FREQCORR: u1, - /// COUNT Register Busy - COUNT: u1, - reserved0: u1, - /// COMP 0 Register Busy - COMP0: u1, - /// COMP 1 Register Busy - COMP1: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Count Synchronization Enable Bit Busy - COUNTSYNC: u1, - /// General Purpose 0 Register Busy - GP0: u1, - /// General Purpose 1 Register Busy - GP1: u1, - /// General Purpose 2 Register Busy - GP2: u1, - /// General Purpose 3 Register Busy - GP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0x40002414 - /// Frequency Correction - pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { - /// Correction Value - VALUE: u7, - /// Correction Sign - SIGN: u1, - }), base_address + 0x14); - - /// address: 0x40002418 - /// MODE0 Counter Value - pub const COUNT = @intToPtr(*volatile u32, base_address + 0x18); - - /// address: 0x40002420 - /// MODE0 Compare n Value - pub const COMP = @intToPtr(*volatile [2]u32, base_address + 0x20); - - /// address: 0x40002440 - /// General Purpose - pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); - - /// address: 0x40002460 - /// Tamper Control - pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Action - IN0ACT: u2, - /// Tamper Input 1 Action - IN1ACT: u2, - /// Tamper Input 2 Action - IN2ACT: u2, - /// Tamper Input 3 Action - IN3ACT: u2, - /// Tamper Input 4 Action - IN4ACT: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Tamper Level Select 0 - TAMLVL0: u1, - /// Tamper Level Select 1 - TAMLVL1: u1, - /// Tamper Level Select 2 - TAMLVL2: u1, - /// Tamper Level Select 3 - TAMLVL3: u1, - /// Tamper Level Select 4 - TAMLVL4: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Debouncer Enable 0 - DEBNC0: u1, - /// Debouncer Enable 1 - DEBNC1: u1, - /// Debouncer Enable 2 - DEBNC2: u1, - /// Debouncer Enable 3 - DEBNC3: u1, - /// Debouncer Enable 4 - DEBNC4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x60); - - /// address: 0x40002464 - /// MODE0 Timestamp - pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { - /// Count Timestamp Value - COUNT: u32, - }), base_address + 0x64); - - /// address: 0x40002468 - /// Tamper ID - pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Detected - TAMPID0: u1, - /// Tamper Input 1 Detected - TAMPID1: u1, - /// Tamper Input 2 Detected - TAMPID2: u1, - /// Tamper Input 3 Detected - TAMPID3: u1, - /// Tamper Input 4 Detected - TAMPID4: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Tamper Event Detected - TAMPEVT: u1, - }), base_address + 0x68); - - /// address: 0x40002480 - /// Backup - pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); - }; - - /// 16-bit Counter with Two 16-bit Compares - pub const MODE1 = struct { - /// address: 0x40002400 - /// MODE1 Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Prescaler - PRESCALER: u4, - reserved4: u1, - /// BKUP Registers Reset On Tamper Enable - BKTRST: u1, - /// GP Registers Reset On Tamper Enable - GPTRST: u1, - /// Count Read Synchronization Enable - COUNTSYNC: u1, - }), base_address + 0x0); - - /// address: 0x40002402 - /// MODE1 Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// General Purpose 0 Enable - GP0EN: u1, - /// General Purpose 2 Enable - GP2EN: u1, - reserved0: u1, - reserved1: u1, - /// Debouncer Majority Enable - DEBMAJ: u1, - /// Debouncer Asynchronous Enable - DEBASYNC: u1, - /// RTC Output Enable - RTCOUT: u1, - /// DMA Enable - DMAEN: u1, - /// Debounce Freqnuency - DEBF: u3, - reserved2: u1, - /// Active Layer Freqnuency - ACTF: u3, - padding0: u1, - }), base_address + 0x2); - - /// address: 0x40002404 - /// MODE1 Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic Interval 0 Event Output Enable - PEREO0: u1, - /// Periodic Interval 1 Event Output Enable - PEREO1: u1, - /// Periodic Interval 2 Event Output Enable - PEREO2: u1, - /// Periodic Interval 3 Event Output Enable - PEREO3: u1, - /// Periodic Interval 4 Event Output Enable - PEREO4: u1, - /// Periodic Interval 5 Event Output Enable - PEREO5: u1, - /// Periodic Interval 6 Event Output Enable - PEREO6: u1, - /// Periodic Interval 7 Event Output Enable - PEREO7: u1, - /// Compare 0 Event Output Enable - CMPEO0: u1, - /// Compare 1 Event Output Enable - CMPEO1: u1, - /// Compare 2 Event Output Enable - CMPEO2: u1, - /// Compare 3 Event Output Enable - CMPEO3: u1, - reserved0: u1, - reserved1: u1, - /// Tamper Event Output Enable - TAMPEREO: u1, - /// Overflow Event Output Enable - OVFEO: u1, - /// Tamper Event Input Enable - TAMPEVEI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x4); - - /// address: 0x40002408 - /// MODE1 Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Interrupt Enable - PER0: u1, - /// Periodic Interval 1 Interrupt Enable - PER1: u1, - /// Periodic Interval 2 Interrupt Enable - PER2: u1, - /// Periodic Interval 3 Interrupt Enable - PER3: u1, - /// Periodic Interval 4 Interrupt Enable - PER4: u1, - /// Periodic Interval 5 Interrupt Enable - PER5: u1, - /// Periodic Interval 6 Interrupt Enable - PER6: u1, - /// Periodic Interval 7 Interrupt Enable - PER7: u1, - /// Compare 0 Interrupt Enable - CMP0: u1, - /// Compare 1 Interrupt Enable - CMP1: u1, - /// Compare 2 Interrupt Enable - CMP2: u1, - /// Compare 3 Interrupt Enable - CMP3: u1, - reserved0: u1, - reserved1: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0x8); - - /// address: 0x4000240a - /// MODE1 Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Interrupt Enable - PER0: u1, - /// Periodic Interval 1 Interrupt Enable - PER1: u1, - /// Periodic Interval 2 Interrupt Enable - PER2: u1, - /// Periodic Interval 3 Interrupt Enable - PER3: u1, - /// Periodic Interval 4 Interrupt Enable - PER4: u1, - /// Periodic Interval 5 Interrupt Enable - PER5: u1, - /// Periodic Interval 6 Interrupt Enable - PER6: u1, - /// Periodic Interval 7 Interrupt Enable - PER7: u1, - /// Compare 0 Interrupt Enable - CMP0: u1, - /// Compare 1 Interrupt Enable - CMP1: u1, - /// Compare 2 Interrupt Enable - CMP2: u1, - /// Compare 3 Interrupt Enable - CMP3: u1, - reserved0: u1, - reserved1: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0xa); - - /// address: 0x4000240c - /// MODE1 Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 - PER0: u1, - /// Periodic Interval 1 - PER1: u1, - /// Periodic Interval 2 - PER2: u1, - /// Periodic Interval 3 - PER3: u1, - /// Periodic Interval 4 - PER4: u1, - /// Periodic Interval 5 - PER5: u1, - /// Periodic Interval 6 - PER6: u1, - /// Periodic Interval 7 - PER7: u1, - /// Compare 0 - CMP0: u1, - /// Compare 1 - CMP1: u1, - /// Compare 2 - CMP2: u1, - /// Compare 3 - CMP3: u1, - reserved0: u1, - reserved1: u1, - /// Tamper - TAMPER: u1, - /// Overflow - OVF: u1, - }), base_address + 0xc); - - /// address: 0x4000240e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xe); - - /// address: 0x40002410 - /// MODE1 Synchronization Busy Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Bit Busy - SWRST: u1, - /// Enable Bit Busy - ENABLE: u1, - /// FREQCORR Register Busy - FREQCORR: u1, - /// COUNT Register Busy - COUNT: u1, - /// PER Register Busy - PER: u1, - /// COMP 0 Register Busy - COMP0: u1, - /// COMP 1 Register Busy - COMP1: u1, - /// COMP 2 Register Busy - COMP2: u1, - /// COMP 3 Register Busy - COMP3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Count Synchronization Enable Bit Busy - COUNTSYNC: u1, - /// General Purpose 0 Register Busy - GP0: u1, - /// General Purpose 1 Register Busy - GP1: u1, - /// General Purpose 2 Register Busy - GP2: u1, - /// General Purpose 3 Register Busy - GP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0x40002414 - /// Frequency Correction - pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { - /// Correction Value - VALUE: u7, - /// Correction Sign - SIGN: u1, - }), base_address + 0x14); - - /// address: 0x40002418 - /// MODE1 Counter Value - pub const COUNT = @intToPtr(*volatile u16, base_address + 0x18); - - /// address: 0x4000241c - /// MODE1 Counter Period - pub const PER = @intToPtr(*volatile u16, base_address + 0x1c); - - /// address: 0x40002420 - /// MODE1 Compare n Value - pub const COMP = @intToPtr(*volatile [4]u16, base_address + 0x20); - - /// address: 0x40002440 - /// General Purpose - pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); - - /// address: 0x40002460 - /// Tamper Control - pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Action - IN0ACT: u2, - /// Tamper Input 1 Action - IN1ACT: u2, - /// Tamper Input 2 Action - IN2ACT: u2, - /// Tamper Input 3 Action - IN3ACT: u2, - /// Tamper Input 4 Action - IN4ACT: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Tamper Level Select 0 - TAMLVL0: u1, - /// Tamper Level Select 1 - TAMLVL1: u1, - /// Tamper Level Select 2 - TAMLVL2: u1, - /// Tamper Level Select 3 - TAMLVL3: u1, - /// Tamper Level Select 4 - TAMLVL4: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Debouncer Enable 0 - DEBNC0: u1, - /// Debouncer Enable 1 - DEBNC1: u1, - /// Debouncer Enable 2 - DEBNC2: u1, - /// Debouncer Enable 3 - DEBNC3: u1, - /// Debouncer Enable 4 - DEBNC4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x60); - - /// address: 0x40002464 - /// MODE1 Timestamp - pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { - /// Count Timestamp Value - COUNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x64); - - /// address: 0x40002468 - /// Tamper ID - pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Detected - TAMPID0: u1, - /// Tamper Input 1 Detected - TAMPID1: u1, - /// Tamper Input 2 Detected - TAMPID2: u1, - /// Tamper Input 3 Detected - TAMPID3: u1, - /// Tamper Input 4 Detected - TAMPID4: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Tamper Event Detected - TAMPEVT: u1, - }), base_address + 0x68); - - /// address: 0x40002480 - /// Backup - pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); - }; - - /// Clock/Calendar with Alarm - pub const MODE2 = struct { - /// address: 0x40002400 - /// MODE2 Control A - pub const CTRLA = @intToPtr(*volatile Mmio(16, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u2, - reserved0: u1, - reserved1: u1, - /// Clock Representation - CLKREP: u1, - /// Clear on Match - MATCHCLR: u1, - /// Prescaler - PRESCALER: u4, - reserved2: u1, - /// BKUP Registers Reset On Tamper Enable - BKTRST: u1, - /// GP Registers Reset On Tamper Enable - GPTRST: u1, - /// Clock Read Synchronization Enable - CLOCKSYNC: u1, - }), base_address + 0x0); - - /// address: 0x40002402 - /// MODE2 Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// General Purpose 0 Enable - GP0EN: u1, - /// General Purpose 2 Enable - GP2EN: u1, - reserved0: u1, - reserved1: u1, - /// Debouncer Majority Enable - DEBMAJ: u1, - /// Debouncer Asynchronous Enable - DEBASYNC: u1, - /// RTC Output Enable - RTCOUT: u1, - /// DMA Enable - DMAEN: u1, - /// Debounce Freqnuency - DEBF: u3, - reserved2: u1, - /// Active Layer Freqnuency - ACTF: u3, - padding0: u1, - }), base_address + 0x2); - - /// address: 0x40002404 - /// MODE2 Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic Interval 0 Event Output Enable - PEREO0: u1, - /// Periodic Interval 1 Event Output Enable - PEREO1: u1, - /// Periodic Interval 2 Event Output Enable - PEREO2: u1, - /// Periodic Interval 3 Event Output Enable - PEREO3: u1, - /// Periodic Interval 4 Event Output Enable - PEREO4: u1, - /// Periodic Interval 5 Event Output Enable - PEREO5: u1, - /// Periodic Interval 6 Event Output Enable - PEREO6: u1, - /// Periodic Interval 7 Event Output Enable - PEREO7: u1, - /// Alarm 0 Event Output Enable - ALARMEO0: u1, - /// Alarm 1 Event Output Enable - ALARMEO1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Event Output Enable - TAMPEREO: u1, - /// Overflow Event Output Enable - OVFEO: u1, - /// Tamper Event Input Enable - TAMPEVEI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x4); - - /// address: 0x40002408 - /// MODE2 Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Interrupt Enable - PER0: u1, - /// Periodic Interval 1 Interrupt Enable - PER1: u1, - /// Periodic Interval 2 Interrupt Enable - PER2: u1, - /// Periodic Interval 3 Interrupt Enable - PER3: u1, - /// Periodic Interval 4 Interrupt Enable - PER4: u1, - /// Periodic Interval 5 Interrupt Enable - PER5: u1, - /// Periodic Interval 6 Interrupt Enable - PER6: u1, - /// Periodic Interval 7 Interrupt Enable - PER7: u1, - /// Alarm 0 Interrupt Enable - ALARM0: u1, - /// Alarm 1 Interrupt Enable - ALARM1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0x8); - - /// address: 0x4000240a - /// MODE2 Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 Enable - PER0: u1, - /// Periodic Interval 1 Enable - PER1: u1, - /// Periodic Interval 2 Enable - PER2: u1, - /// Periodic Interval 3 Enable - PER3: u1, - /// Periodic Interval 4 Enable - PER4: u1, - /// Periodic Interval 5 Enable - PER5: u1, - /// Periodic Interval 6 Enable - PER6: u1, - /// Periodic Interval 7 Enable - PER7: u1, - /// Alarm 0 Interrupt Enable - ALARM0: u1, - /// Alarm 1 Interrupt Enable - ALARM1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper Enable - TAMPER: u1, - /// Overflow Interrupt Enable - OVF: u1, - }), base_address + 0xa); - - /// address: 0x4000240c - /// MODE2 Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Periodic Interval 0 - PER0: u1, - /// Periodic Interval 1 - PER1: u1, - /// Periodic Interval 2 - PER2: u1, - /// Periodic Interval 3 - PER3: u1, - /// Periodic Interval 4 - PER4: u1, - /// Periodic Interval 5 - PER5: u1, - /// Periodic Interval 6 - PER6: u1, - /// Periodic Interval 7 - PER7: u1, - /// Alarm 0 - ALARM0: u1, - /// Alarm 1 - ALARM1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Tamper - TAMPER: u1, - /// Overflow - OVF: u1, - }), base_address + 0xc); - - /// address: 0x4000240e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xe); - - /// address: 0x40002410 - /// MODE2 Synchronization Busy Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Bit Busy - SWRST: u1, - /// Enable Bit Busy - ENABLE: u1, - /// FREQCORR Register Busy - FREQCORR: u1, - /// CLOCK Register Busy - CLOCK: u1, - reserved0: u1, - /// ALARM 0 Register Busy - ALARM0: u1, - /// ALARM 1 Register Busy - ALARM1: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// MASK 0 Register Busy - MASK0: u1, - /// MASK 1 Register Busy - MASK1: u1, - reserved5: u1, - reserved6: u1, - /// Clock Synchronization Enable Bit Busy - CLOCKSYNC: u1, - /// General Purpose 0 Register Busy - GP0: u1, - /// General Purpose 1 Register Busy - GP1: u1, - /// General Purpose 2 Register Busy - GP2: u1, - /// General Purpose 3 Register Busy - GP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0x40002414 - /// Frequency Correction - pub const FREQCORR = @intToPtr(*volatile Mmio(8, packed struct { - /// Correction Value - VALUE: u7, - /// Correction Sign - SIGN: u1, - }), base_address + 0x14); - - /// address: 0x40002418 - /// MODE2 Clock Value - pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Second - SECOND: u6, - /// Minute - MINUTE: u6, - /// Hour - HOUR: u5, - /// Day - DAY: u5, - /// Month - MONTH: u4, - /// Year - YEAR: u6, - }), base_address + 0x18); - - /// address: 0x40002440 - /// General Purpose - pub const GP = @intToPtr(*volatile [4]u32, base_address + 0x40); - - /// address: 0x40002420 - /// MODE2_ALARM Alarm n Value - pub const ALARM0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Second - SECOND: u6, - /// Minute - MINUTE: u6, - /// Hour - HOUR: u5, - /// Day - DAY: u5, - /// Month - MONTH: u4, - /// Year - YEAR: u6, - }), base_address + 0x20); - - /// address: 0x40002424 - /// MODE2_ALARM Alarm n Mask - pub const MASK0 = @intToPtr(*volatile Mmio(8, packed struct { - /// Alarm Mask Selection - SEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x24); - - /// address: 0x40002428 - /// MODE2_ALARM Alarm n Value - pub const ALARM1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Second - SECOND: u6, - /// Minute - MINUTE: u6, - /// Hour - HOUR: u5, - /// Day - DAY: u5, - /// Month - MONTH: u4, - /// Year - YEAR: u6, - }), base_address + 0x28); - - /// address: 0x4000242c - /// MODE2_ALARM Alarm n Mask - pub const MASK1 = @intToPtr(*volatile Mmio(8, packed struct { - /// Alarm Mask Selection - SEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2c); - - /// address: 0x40002460 - /// Tamper Control - pub const TAMPCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Action - IN0ACT: u2, - /// Tamper Input 1 Action - IN1ACT: u2, - /// Tamper Input 2 Action - IN2ACT: u2, - /// Tamper Input 3 Action - IN3ACT: u2, - /// Tamper Input 4 Action - IN4ACT: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Tamper Level Select 0 - TAMLVL0: u1, - /// Tamper Level Select 1 - TAMLVL1: u1, - /// Tamper Level Select 2 - TAMLVL2: u1, - /// Tamper Level Select 3 - TAMLVL3: u1, - /// Tamper Level Select 4 - TAMLVL4: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Debouncer Enable 0 - DEBNC0: u1, - /// Debouncer Enable 1 - DEBNC1: u1, - /// Debouncer Enable 2 - DEBNC2: u1, - /// Debouncer Enable 3 - DEBNC3: u1, - /// Debouncer Enable 4 - DEBNC4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x60); - - /// address: 0x40002464 - /// MODE2 Timestamp - pub const TIMESTAMP = @intToPtr(*volatile Mmio(32, packed struct { - /// Second Timestamp Value - SECOND: u6, - /// Minute Timestamp Value - MINUTE: u6, - /// Hour Timestamp Value - HOUR: u5, - /// Day Timestamp Value - DAY: u5, - /// Month Timestamp Value - MONTH: u4, - /// Year Timestamp Value - YEAR: u6, - }), base_address + 0x64); - - /// address: 0x40002468 - /// Tamper ID - pub const TAMPID = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper Input 0 Detected - TAMPID0: u1, - /// Tamper Input 1 Detected - TAMPID1: u1, - /// Tamper Input 2 Detected - TAMPID2: u1, - /// Tamper Input 3 Detected - TAMPID3: u1, - /// Tamper Input 4 Detected - TAMPID4: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Tamper Event Detected - TAMPEVT: u1, - }), base_address + 0x68); - - /// address: 0x40002480 - /// Backup - pub const BKUP = @intToPtr(*volatile [8]u32, base_address + 0x80); - }; - }; - - /// SD/MMC Host Controller - pub const SDHC0 = struct { - pub const base_address = 0x45000000; - pub const version = "U20111.8.3"; - - /// address: 0x45000000 - /// SDMA System Address / Argument 2 - pub const SSAR = @intToPtr(*volatile Mmio(32, packed struct { - /// SDMA System Address - ADDR: u32, - }), base_address + 0x0); - - /// address: 0x45000000 - /// SDMA System Address / Argument 2 - pub const SSAR_CMD23_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Argument 2 - ARG2: u32, - }), base_address + 0x0); - - /// address: 0x45000004 - /// Block Size - pub const BSR = @intToPtr(*volatile Mmio(16, packed struct { - /// Transfer Block Size - BLOCKSIZE: u10, - reserved0: u1, - reserved1: u1, - /// SDMA Buffer Boundary - BOUNDARY: u3, - padding0: u1, - }), base_address + 0x4); - - /// address: 0x45000006 - /// Block Count - pub const BCR = @intToPtr(*volatile Mmio(16, packed struct { - /// Blocks Count for Current Transfer - BCNT: u16, - }), base_address + 0x6); - - /// address: 0x45000008 - /// Argument 1 - pub const ARG1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Argument 1 - ARG: u32, - }), base_address + 0x8); - - /// address: 0x4500000c - /// Transfer Mode - pub const TMR = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA Enable - DMAEN: u1, - /// Block Count Enable - BCEN: u1, - /// Auto Command Enable - ACMDEN: u2, - /// Data Transfer Direction Selection - DTDSEL: u1, - /// Multi/Single Block Selection - MSBSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0xc); - - /// address: 0x4500000e - /// Command - pub const CR = @intToPtr(*volatile Mmio(16, packed struct { - /// Response Type - RESPTYP: u2, - reserved0: u1, - /// Command CRC Check Enable - CMDCCEN: u1, - /// Command Index Check Enable - CMDICEN: u1, - /// Data Present Select - DPSEL: u1, - /// Command Type - CMDTYP: u2, - /// Command Index - CMDIDX: u6, - padding0: u1, - padding1: u1, - }), base_address + 0xe); - - /// address: 0x45000010 - /// Response - pub const RR = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Command Response - CMDRESP: u32, - }), base_address + 0x10); - - /// address: 0x45000020 - /// Buffer Data Port - pub const BDPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Buffer Data - BUFDATA: u32, - }), base_address + 0x20); - - /// address: 0x45000024 - /// Present State - pub const PSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Command Inhibit (CMD) - CMDINHC: u1, - /// Command Inhibit (DAT) - CMDINHD: u1, - /// DAT Line Active - DLACT: u1, - /// Re-Tuning Request - RTREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Write Transfer Active - WTACT: u1, - /// Read Transfer Active - RTACT: u1, - /// Buffer Write Enable - BUFWREN: u1, - /// Buffer Read Enable - BUFRDEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Card Inserted - CARDINS: u1, - /// Card State Stable - CARDSS: u1, - /// Card Detect Pin Level - CARDDPL: u1, - /// Write Protect Pin Level - WRPPL: u1, - /// DAT[3:0] Line Level - DATLL: u4, - /// CMD Line Level - CMDLL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x24); - - /// address: 0x45000028 - /// Host Control 1 - pub const HC1R = @intToPtr(*volatile Mmio(8, packed struct { - /// LED Control - LEDCTRL: u1, - /// Data Width - DW: u1, - /// High Speed Enable - HSEN: u1, - /// DMA Select - DMASEL: u2, - reserved0: u1, - /// Card Detect Test Level - CARDDTL: u1, - /// Card Detect Signal Selection - CARDDSEL: u1, - }), base_address + 0x28); - - /// address: 0x45000028 - /// Host Control 1 - pub const HC1R_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Data Width - DW: u1, - /// High Speed Enable - HSEN: u1, - /// DMA Select - DMASEL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x28); - - /// address: 0x45000029 - /// Power Control - pub const PCR = @intToPtr(*volatile Mmio(8, packed struct { - /// SD Bus Power - SDBPWR: u1, - /// SD Bus Voltage Select - SDBVSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x29); - - /// address: 0x4500002a - /// Block Gap Control - pub const BGCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop at Block Gap Request - STPBGR: u1, - /// Continue Request - CONTR: u1, - /// Read Wait Control - RWCTRL: u1, - /// Interrupt at Block Gap - INTBG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x2a); - - /// address: 0x4500002a - /// Block Gap Control - pub const BGCR_EMMC_MODE = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop at Block Gap Request - STPBGR: u1, - /// Continue Request - CONTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2a); - - /// address: 0x4500002b - /// Wakeup Control - pub const WCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Wakeup Event Enable on Card Interrupt - WKENCINT: u1, - /// Wakeup Event Enable on Card Insertion - WKENCINS: u1, - /// Wakeup Event Enable on Card Removal - WKENCREM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2b); - - /// address: 0x4500002c - /// Clock Control - pub const CCR = @intToPtr(*volatile Mmio(16, packed struct { - /// Internal Clock Enable - INTCLKEN: u1, - /// Internal Clock Stable - INTCLKS: u1, - /// SD Clock Enable - SDCLKEN: u1, - reserved0: u1, - reserved1: u1, - /// Clock Generator Select - CLKGSEL: u1, - /// Upper Bits of SDCLK Frequency Select - USDCLKFSEL: u2, - /// SDCLK Frequency Select - SDCLKFSEL: u8, - }), base_address + 0x2c); - - /// address: 0x4500002e - /// Timeout Control - pub const TCR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Timeout Counter Value - DTCVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x2e); - - /// address: 0x4500002f - /// Software Reset - pub const SRR = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset For All - SWRSTALL: u1, - /// Software Reset For CMD Line - SWRSTCMD: u1, - /// Software Reset For DAT Line - SWRSTDAT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x2f); - - /// address: 0x45000030 - /// Normal Interrupt Status - pub const NISTR = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete - CMDC: u1, - /// Transfer Complete - TRFC: u1, - /// Block Gap Event - BLKGE: u1, - /// DMA Interrupt - DMAINT: u1, - /// Buffer Write Ready - BWRRDY: u1, - /// Buffer Read Ready - BRDRDY: u1, - /// Card Insertion - CINS: u1, - /// Card Removal - CREM: u1, - /// Card Interrupt - CINT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Error Interrupt - ERRINT: u1, - }), base_address + 0x30); - - /// address: 0x45000030 - /// Normal Interrupt Status - pub const NISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete - CMDC: u1, - /// Transfer Complete - TRFC: u1, - /// Block Gap Event - BLKGE: u1, - /// DMA Interrupt - DMAINT: u1, - /// Buffer Write Ready - BWRRDY: u1, - /// Buffer Read Ready - BRDRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Boot Acknowledge Received - BOOTAR: u1, - /// Error Interrupt - ERRINT: u1, - }), base_address + 0x30); - - /// address: 0x45000032 - /// Error Interrupt Status - pub const EISTR = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error - CMDTEO: u1, - /// Command CRC Error - CMDCRC: u1, - /// Command End Bit Error - CMDEND: u1, - /// Command Index Error - CMDIDX: u1, - /// Data Timeout Error - DATTEO: u1, - /// Data CRC Error - DATCRC: u1, - /// Data End Bit Error - DATEND: u1, - /// Current Limit Error - CURLIM: u1, - /// Auto CMD Error - ACMD: u1, - /// ADMA Error - ADMA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x32); - - /// address: 0x45000032 - /// Error Interrupt Status - pub const EISTR_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error - CMDTEO: u1, - /// Command CRC Error - CMDCRC: u1, - /// Command End Bit Error - CMDEND: u1, - /// Command Index Error - CMDIDX: u1, - /// Data Timeout Error - DATTEO: u1, - /// Data CRC Error - DATCRC: u1, - /// Data End Bit Error - DATEND: u1, - /// Current Limit Error - CURLIM: u1, - /// Auto CMD Error - ACMD: u1, - /// ADMA Error - ADMA: u1, - reserved0: u1, - reserved1: u1, - /// Boot Acknowledge Error - BOOTAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x32); - - /// address: 0x45000034 - /// Normal Interrupt Status Enable - pub const NISTER = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete Status Enable - CMDC: u1, - /// Transfer Complete Status Enable - TRFC: u1, - /// Block Gap Event Status Enable - BLKGE: u1, - /// DMA Interrupt Status Enable - DMAINT: u1, - /// Buffer Write Ready Status Enable - BWRRDY: u1, - /// Buffer Read Ready Status Enable - BRDRDY: u1, - /// Card Insertion Status Enable - CINS: u1, - /// Card Removal Status Enable - CREM: u1, - /// Card Interrupt Status Enable - CINT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x34); - - /// address: 0x45000034 - /// Normal Interrupt Status Enable - pub const NISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete Status Enable - CMDC: u1, - /// Transfer Complete Status Enable - TRFC: u1, - /// Block Gap Event Status Enable - BLKGE: u1, - /// DMA Interrupt Status Enable - DMAINT: u1, - /// Buffer Write Ready Status Enable - BWRRDY: u1, - /// Buffer Read Ready Status Enable - BRDRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Boot Acknowledge Received Status Enable - BOOTAR: u1, - padding0: u1, - }), base_address + 0x34); - - /// address: 0x45000036 - /// Error Interrupt Status Enable - pub const EISTER = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error Status Enable - CMDTEO: u1, - /// Command CRC Error Status Enable - CMDCRC: u1, - /// Command End Bit Error Status Enable - CMDEND: u1, - /// Command Index Error Status Enable - CMDIDX: u1, - /// Data Timeout Error Status Enable - DATTEO: u1, - /// Data CRC Error Status Enable - DATCRC: u1, - /// Data End Bit Error Status Enable - DATEND: u1, - /// Current Limit Error Status Enable - CURLIM: u1, - /// Auto CMD Error Status Enable - ACMD: u1, - /// ADMA Error Status Enable - ADMA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x36); - - /// address: 0x45000036 - /// Error Interrupt Status Enable - pub const EISTER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error Status Enable - CMDTEO: u1, - /// Command CRC Error Status Enable - CMDCRC: u1, - /// Command End Bit Error Status Enable - CMDEND: u1, - /// Command Index Error Status Enable - CMDIDX: u1, - /// Data Timeout Error Status Enable - DATTEO: u1, - /// Data CRC Error Status Enable - DATCRC: u1, - /// Data End Bit Error Status Enable - DATEND: u1, - /// Current Limit Error Status Enable - CURLIM: u1, - /// Auto CMD Error Status Enable - ACMD: u1, - /// ADMA Error Status Enable - ADMA: u1, - reserved0: u1, - reserved1: u1, - /// Boot Acknowledge Error Status Enable - BOOTAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x36); - - /// address: 0x45000038 - /// Normal Interrupt Signal Enable - pub const NISIER = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete Signal Enable - CMDC: u1, - /// Transfer Complete Signal Enable - TRFC: u1, - /// Block Gap Event Signal Enable - BLKGE: u1, - /// DMA Interrupt Signal Enable - DMAINT: u1, - /// Buffer Write Ready Signal Enable - BWRRDY: u1, - /// Buffer Read Ready Signal Enable - BRDRDY: u1, - /// Card Insertion Signal Enable - CINS: u1, - /// Card Removal Signal Enable - CREM: u1, - /// Card Interrupt Signal Enable - CINT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x38); - - /// address: 0x45000038 - /// Normal Interrupt Signal Enable - pub const NISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Complete Signal Enable - CMDC: u1, - /// Transfer Complete Signal Enable - TRFC: u1, - /// Block Gap Event Signal Enable - BLKGE: u1, - /// DMA Interrupt Signal Enable - DMAINT: u1, - /// Buffer Write Ready Signal Enable - BWRRDY: u1, - /// Buffer Read Ready Signal Enable - BRDRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Boot Acknowledge Received Signal Enable - BOOTAR: u1, - padding0: u1, - }), base_address + 0x38); - - /// address: 0x4500003a - /// Error Interrupt Signal Enable - pub const EISIER = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error Signal Enable - CMDTEO: u1, - /// Command CRC Error Signal Enable - CMDCRC: u1, - /// Command End Bit Error Signal Enable - CMDEND: u1, - /// Command Index Error Signal Enable - CMDIDX: u1, - /// Data Timeout Error Signal Enable - DATTEO: u1, - /// Data CRC Error Signal Enable - DATCRC: u1, - /// Data End Bit Error Signal Enable - DATEND: u1, - /// Current Limit Error Signal Enable - CURLIM: u1, - /// Auto CMD Error Signal Enable - ACMD: u1, - /// ADMA Error Signal Enable - ADMA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x3a); - - /// address: 0x4500003a - /// Error Interrupt Signal Enable - pub const EISIER_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Command Timeout Error Signal Enable - CMDTEO: u1, - /// Command CRC Error Signal Enable - CMDCRC: u1, - /// Command End Bit Error Signal Enable - CMDEND: u1, - /// Command Index Error Signal Enable - CMDIDX: u1, - /// Data Timeout Error Signal Enable - DATTEO: u1, - /// Data CRC Error Signal Enable - DATCRC: u1, - /// Data End Bit Error Signal Enable - DATEND: u1, - /// Current Limit Error Signal Enable - CURLIM: u1, - /// Auto CMD Error Signal Enable - ACMD: u1, - /// ADMA Error Signal Enable - ADMA: u1, - reserved0: u1, - reserved1: u1, - /// Boot Acknowledge Error Signal Enable - BOOTAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x3a); - - /// address: 0x4500003c - /// Auto CMD Error Status - pub const ACESR = @intToPtr(*volatile Mmio(16, packed struct { - /// Auto CMD12 Not Executed - ACMD12NE: u1, - /// Auto CMD Timeout Error - ACMDTEO: u1, - /// Auto CMD CRC Error - ACMDCRC: u1, - /// Auto CMD End Bit Error - ACMDEND: u1, - /// Auto CMD Index Error - ACMDIDX: u1, - reserved0: u1, - reserved1: u1, - /// Command not Issued By Auto CMD12 Error - CMDNI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x3c); - - /// address: 0x4500003e - /// Host Control 2 - pub const HC2R = @intToPtr(*volatile Mmio(16, packed struct { - /// UHS Mode Select - UHSMS: u3, - /// 1.8V Signaling Enable - VS18EN: u1, - /// Driver Strength Select - DRVSEL: u2, - /// Execute Tuning - EXTUN: u1, - /// Sampling Clock Select - SLCKSEL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Asynchronous Interrupt Enable - ASINTEN: u1, - /// Preset Value Enable - PVALEN: u1, - }), base_address + 0x3e); - - /// address: 0x4500003e - /// Host Control 2 - pub const HC2R_EMMC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// HS200 Mode Enable - HS200EN: u4, - /// Driver Strength Select - DRVSEL: u2, - /// Execute Tuning - EXTUN: u1, - /// Sampling Clock Select - SLCKSEL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Preset Value Enable - PVALEN: u1, - }), base_address + 0x3e); - - /// address: 0x45000040 - /// Capabilities 0 - pub const CA0R = @intToPtr(*volatile Mmio(32, packed struct { - /// Timeout Clock Frequency - TEOCLKF: u6, - reserved0: u1, - /// Timeout Clock Unit - TEOCLKU: u1, - /// Base Clock Frequency - BASECLKF: u8, - /// Max Block Length - MAXBLKL: u2, - /// 8-bit Support for Embedded Device - ED8SUP: u1, - /// ADMA2 Support - ADMA2SUP: u1, - reserved1: u1, - /// High Speed Support - HSSUP: u1, - /// SDMA Support - SDMASUP: u1, - /// Suspend/Resume Support - SRSUP: u1, - /// Voltage Support 3.3V - V33VSUP: u1, - /// Voltage Support 3.0V - V30VSUP: u1, - /// Voltage Support 1.8V - V18VSUP: u1, - reserved2: u1, - /// 64-Bit System Bus Support - SB64SUP: u1, - /// Asynchronous Interrupt Support - ASINTSUP: u1, - /// Slot Type - SLTYPE: u2, - }), base_address + 0x40); - - /// address: 0x45000044 - /// Capabilities 1 - pub const CA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// SDR50 Support - SDR50SUP: u1, - /// SDR104 Support - SDR104SUP: u1, - /// DDR50 Support - DDR50SUP: u1, - reserved0: u1, - /// Driver Type A Support - DRVASUP: u1, - /// Driver Type C Support - DRVCSUP: u1, - /// Driver Type D Support - DRVDSUP: u1, - reserved1: u1, - /// Timer Count for Re-Tuning - TCNTRT: u4, - reserved2: u1, - /// Use Tuning for SDR50 - TSDR50: u1, - reserved3: u1, - reserved4: u1, - /// Clock Multiplier - CLKMULT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x45000048 - /// Maximum Current Capabilities - pub const MCCAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum Current for 3.3V - MAXCUR33V: u8, - /// Maximum Current for 3.0V - MAXCUR30V: u8, - /// Maximum Current for 1.8V - MAXCUR18V: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x48); - - /// address: 0x45000050 - /// Force Event for Auto CMD Error Status - pub const FERACES = @intToPtr(*volatile Mmio(16, packed struct { - /// Force Event for Auto CMD12 Not Executed - ACMD12NE: u1, - /// Force Event for Auto CMD Timeout Error - ACMDTEO: u1, - /// Force Event for Auto CMD CRC Error - ACMDCRC: u1, - /// Force Event for Auto CMD End Bit Error - ACMDEND: u1, - /// Force Event for Auto CMD Index Error - ACMDIDX: u1, - reserved0: u1, - reserved1: u1, - /// Force Event for Command Not Issued By Auto CMD12 Error - CMDNI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x50); - - /// address: 0x45000052 - /// Force Event for Error Interrupt Status - pub const FEREIS = @intToPtr(*volatile Mmio(16, packed struct { - /// Force Event for Command Timeout Error - CMDTEO: u1, - /// Force Event for Command CRC Error - CMDCRC: u1, - /// Force Event for Command End Bit Error - CMDEND: u1, - /// Force Event for Command Index Error - CMDIDX: u1, - /// Force Event for Data Timeout Error - DATTEO: u1, - /// Force Event for Data CRC Error - DATCRC: u1, - /// Force Event for Data End Bit Error - DATEND: u1, - /// Force Event for Current Limit Error - CURLIM: u1, - /// Force Event for Auto CMD Error - ACMD: u1, - /// Force Event for ADMA Error - ADMA: u1, - reserved0: u1, - reserved1: u1, - /// Force Event for Boot Acknowledge Error - BOOTAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x52); - - /// address: 0x45000054 - /// ADMA Error Status - pub const AESR = @intToPtr(*volatile Mmio(8, packed struct { - /// ADMA Error State - ERRST: u2, - /// ADMA Length Mismatch Error - LMIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x54); - - /// address: 0x45000058 - /// ADMA System Address n - pub const ASAR = @intToPtr(*volatile [1]Mmio(32, packed struct { - /// ADMA System Address - ADMASA: u32, - }), base_address + 0x58); - - /// address: 0x45000060 - /// Preset Value n - pub const PVR = @intToPtr(*volatile [8]Mmio(16, packed struct { - /// SDCLK Frequency Select Value for Initialization - SDCLKFSEL: u10, - /// Clock Generator Select Value for Initialization - CLKGSEL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Driver Strength Select Value for Initialization - DRVSEL: u2, - }), base_address + 0x60); - - /// address: 0x450000fc - /// Slot Interrupt Status - pub const SISR = @intToPtr(*volatile Mmio(16, packed struct { - /// Interrupt Signal for Each Slot - INTSSL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xfc); - - /// address: 0x450000fe - /// Host Controller Version - pub const HCVR = @intToPtr(*volatile Mmio(16, packed struct { - /// Spec Version - SVER: u8, - /// Vendor Version - VVER: u8, - }), base_address + 0xfe); - - /// address: 0x45000204 - /// MMC Control 1 - pub const MC1R = @intToPtr(*volatile Mmio(8, packed struct { - /// e.MMC Command Type - CMDTYP: u2, - reserved0: u1, - /// e.MMC HSDDR Mode - DDR: u1, - /// e.MMC Open Drain Mode - OPD: u1, - /// e.MMC Boot Acknowledge Enable - BOOTA: u1, - /// e.MMC Reset Signal - RSTN: u1, - /// e.MMC Force Card Detect - FCD: u1, - }), base_address + 0x204); - - /// address: 0x45000205 - /// MMC Control 2 - pub const MC2R = @intToPtr(*volatile Mmio(8, packed struct { - /// e.MMC Abort Wait IRQ - SRESP: u1, - /// e.MMC Abort Boot - ABOOT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x205); - - /// address: 0x45000208 - /// AHB Control - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// AHB Maximum Burst - BMAX: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x208); - - /// address: 0x4500020c - /// Clock Control 2 - pub const CC2R = @intToPtr(*volatile Mmio(32, packed struct { - /// Force SDCK Disabled - FSDCLKD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x20c); - - /// address: 0x45000230 - /// Capabilities Control - pub const CACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capabilities Registers Write Enable (Required to write the correct frequencies - /// in the Capabilities Registers) - CAPWREN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Key (0x46) - KEY: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x230); - - /// address: 0x45000234 - /// Debug - pub const DBGR = @intToPtr(*volatile Mmio(8, packed struct { - /// Non-intrusive debug enable - NIDBG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x234); - }; - - /// Serial Communication Interface - pub const SERCOM0 = struct { - pub const base_address = 0x40003000; - pub const version = "U22015.0.0"; - - /// I2C Master Mode - pub const I2CM = struct { - /// address: 0x40003000 - /// I2CM Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run in Standby - RUNSTDBY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Pin Usage - PINOUT: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// SDA Hold Time - SDAHOLD: u2, - /// Master SCL Low Extend Timeout - MEXTTOEN: u1, - /// Slave SCL Low Extend Timeout - SEXTTOEN: u1, - /// Transfer Speed - SPEED: u2, - reserved13: u1, - /// SCL Clock Stretch Mode - SCLSM: u1, - /// Inactive Time-Out - INACTOUT: u2, - /// SCL Low Timeout Enable - LOWTOUTEN: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// I2CM Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Smart Mode Enable - SMEN: u1, - /// Quick Command Enable - QCEN: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Command - CMD: u2, - /// Acknowledge Action - ACKACT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// I2CM Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - /// Data 32 Bit - DATA32B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// I2CM Baud Rate - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud Rate Value - BAUD: u8, - /// Baud Rate Value Low - BAUDLOW: u8, - /// High Speed Baud Rate Value - HSBAUD: u8, - /// High Speed Baud Rate Value Low - HSBAUDLOW: u8, - }), base_address + 0xc); - - /// address: 0x40003014 - /// I2CM Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Master On Bus Interrupt Disable - MB: u1, - /// Slave On Bus Interrupt Disable - SB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// I2CM Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Master On Bus Interrupt Enable - MB: u1, - /// Slave On Bus Interrupt Enable - SB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// I2CM Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Master On Bus Interrupt - MB: u1, - /// Slave On Bus Interrupt - SB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// I2CM Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Bus Error - BUSERR: u1, - /// Arbitration Lost - ARBLOST: u1, - /// Received Not Acknowledge - RXNACK: u1, - reserved0: u1, - /// Bus State - BUSSTATE: u2, - /// SCL Low Timeout - LOWTOUT: u1, - /// Clock Hold - CLKHOLD: u1, - /// Master SCL Low Extend Timeout - MEXTTOUT: u1, - /// Slave SCL Low Extend Timeout - SEXTTOUT: u1, - /// Length Error - LENERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// I2CM Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// System Operation Synchronization Busy - SYSOP: u1, - reserved0: u1, - /// Length Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003024 - /// I2CM Address - pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address Value - ADDR: u11, - reserved0: u1, - reserved1: u1, - /// Length Enable - LENEN: u1, - /// High Speed Mode - HS: u1, - /// Ten Bit Addressing Enable - TENBITEN: u1, - /// Length - LEN: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x40003028 - /// I2CM Data - pub const DATA = @intToPtr(*volatile u8, base_address + 0x28); - - /// address: 0x40003030 - /// I2CM Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - - /// I2C Slave Mode - pub const I2CS = struct { - /// address: 0x40003000 - /// I2CS Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Pin Usage - PINOUT: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// SDA Hold Time - SDAHOLD: u2, - reserved13: u1, - /// Slave SCL Low Extend Timeout - SEXTTOEN: u1, - /// Transfer Speed - SPEED: u2, - reserved14: u1, - /// SCL Clock Stretch Mode - SCLSM: u1, - reserved15: u1, - reserved16: u1, - /// SCL Low Timeout Enable - LOWTOUTEN: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// I2CS Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Smart Mode Enable - SMEN: u1, - /// PMBus Group Command - GCMD: u1, - /// Automatic Address Acknowledge - AACKEN: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Address Mode - AMODE: u2, - /// Command - CMD: u2, - /// Acknowledge Action - ACKACT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// I2CS Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// SDA Setup Time - SDASETUP: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Data 32 Bit - DATA32B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x40003014 - /// I2CS Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Received Interrupt Disable - PREC: u1, - /// Address Match Interrupt Disable - AMATCH: u1, - /// Data Interrupt Disable - DRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// I2CS Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Received Interrupt Enable - PREC: u1, - /// Address Match Interrupt Enable - AMATCH: u1, - /// Data Interrupt Enable - DRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// I2CS Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Received Interrupt - PREC: u1, - /// Address Match Interrupt - AMATCH: u1, - /// Data Interrupt - DRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// I2CS Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Bus Error - BUSERR: u1, - /// Transmit Collision - COLL: u1, - /// Received Not Acknowledge - RXNACK: u1, - /// Read/Write Direction - DIR: u1, - /// Repeated Start - SR: u1, - reserved0: u1, - /// SCL Low Timeout - LOWTOUT: u1, - /// Clock Hold - CLKHOLD: u1, - reserved1: u1, - /// Slave SCL Low Extend Timeout - SEXTTOUT: u1, - /// High Speed - HS: u1, - /// Transaction Length Error - LENERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// I2CS Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - reserved0: u1, - reserved1: u1, - /// Length Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003022 - /// I2CS Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x22); - - /// address: 0x40003024 - /// I2CS Address - pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call Address Enable - GENCEN: u1, - /// Address Value - ADDR: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Ten Bit Addressing Enable - TENBITEN: u1, - reserved4: u1, - /// Address Mask - ADDRMASK: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x24); - - /// address: 0x40003028 - /// I2CS Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - }; - - /// SPI Slave Mode - pub const SPIS = struct { - /// address: 0x40003000 - /// SPIS Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - /// Immediate Buffer Overflow Notification - IBON: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Data Out Pinout - DOPO: u2, - reserved9: u1, - reserved10: u1, - /// Data In Pinout - DIPO: u2, - reserved11: u1, - reserved12: u1, - /// Frame Format - FORM: u4, - /// Clock Phase - CPHA: u1, - /// Clock Polarity - CPOL: u1, - /// Data Order - DORD: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// SPIS Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Character Size - CHSIZE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Data Preload Enable - PLOADEN: u1, - reserved3: u1, - reserved4: u1, - /// Slave Select Low Detect Enable - SSDE: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Master Slave Select Enable - MSSEN: u1, - /// Address Mode - AMODE: u2, - reserved8: u1, - /// Receiver Enable - RXEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// SPIS Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// Inter-Character Spacing - ICSPACE: u6, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// Data 32 Bit - DATA32B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// SPIS Baud Rate - pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); - - /// address: 0x40003014 - /// SPIS Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Disable - DRE: u1, - /// Transmit Complete Interrupt Disable - TXC: u1, - /// Receive Complete Interrupt Disable - RXC: u1, - /// Slave Select Low Interrupt Disable - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// SPIS Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Enable - DRE: u1, - /// Transmit Complete Interrupt Enable - TXC: u1, - /// Receive Complete Interrupt Enable - RXC: u1, - /// Slave Select Low Interrupt Enable - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// SPIS Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt - DRE: u1, - /// Transmit Complete Interrupt - TXC: u1, - /// Receive Complete Interrupt - RXC: u1, - /// Slave Select Low Interrupt Flag - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// SPIS Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Buffer Overflow - BUFOVF: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Transaction Length Error - LENERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// SPIS Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// CTRLB Synchronization Busy - CTRLB: u1, - reserved0: u1, - /// LENGTH Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003022 - /// SPIS Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x22); - - /// address: 0x40003024 - /// SPIS Address - pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address Value - ADDR: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Address Mask - ADDRMASK: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x40003028 - /// SPIS Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003030 - /// SPIS Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - - /// SPI Master Mode - pub const SPIM = struct { - /// address: 0x40003000 - /// SPIM Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - /// Immediate Buffer Overflow Notification - IBON: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Data Out Pinout - DOPO: u2, - reserved9: u1, - reserved10: u1, - /// Data In Pinout - DIPO: u2, - reserved11: u1, - reserved12: u1, - /// Frame Format - FORM: u4, - /// Clock Phase - CPHA: u1, - /// Clock Polarity - CPOL: u1, - /// Data Order - DORD: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// SPIM Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Character Size - CHSIZE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Data Preload Enable - PLOADEN: u1, - reserved3: u1, - reserved4: u1, - /// Slave Select Low Detect Enable - SSDE: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Master Slave Select Enable - MSSEN: u1, - /// Address Mode - AMODE: u2, - reserved8: u1, - /// Receiver Enable - RXEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// SPIM Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// Inter-Character Spacing - ICSPACE: u6, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// Data 32 Bit - DATA32B: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// SPIM Baud Rate - pub const BAUD = @intToPtr(*volatile u8, base_address + 0xc); - - /// address: 0x40003014 - /// SPIM Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Disable - DRE: u1, - /// Transmit Complete Interrupt Disable - TXC: u1, - /// Receive Complete Interrupt Disable - RXC: u1, - /// Slave Select Low Interrupt Disable - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// SPIM Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Enable - DRE: u1, - /// Transmit Complete Interrupt Enable - TXC: u1, - /// Receive Complete Interrupt Enable - RXC: u1, - /// Slave Select Low Interrupt Enable - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// SPIM Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt - DRE: u1, - /// Transmit Complete Interrupt - TXC: u1, - /// Receive Complete Interrupt - RXC: u1, - /// Slave Select Low Interrupt Flag - SSL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// SPIM Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Buffer Overflow - BUFOVF: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Transaction Length Error - LENERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// SPIM Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// CTRLB Synchronization Busy - CTRLB: u1, - reserved0: u1, - /// LENGTH Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003022 - /// SPIM Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x22); - - /// address: 0x40003024 - /// SPIM Address - pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address Value - ADDR: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Address Mask - ADDRMASK: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x40003028 - /// SPIM Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003030 - /// SPIM Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - - /// USART EXTERNAL CLOCK Mode - pub const USART_EXT = struct { - /// address: 0x40003000 - /// USART_EXT Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - /// Immediate Buffer Overflow Notification - IBON: u1, - /// Transmit Data Invert - TXINV: u1, - /// Receive Data Invert - RXINV: u1, - reserved2: u1, - reserved3: u1, - /// Sample - SAMPR: u3, - /// Transmit Data Pinout - TXPO: u2, - reserved4: u1, - reserved5: u1, - /// Receive Data Pinout - RXPO: u2, - /// Sample Adjustment - SAMPA: u2, - /// Frame Format - FORM: u4, - /// Communication Mode - CMODE: u1, - /// Clock Polarity - CPOL: u1, - /// Data Order - DORD: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// USART_EXT Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Character Size - CHSIZE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Stop Bit Mode - SBMODE: u1, - reserved3: u1, - /// Collision Detection Enable - COLDEN: u1, - /// Start of Frame Detection Enable - SFDE: u1, - /// Encoding Format - ENC: u1, - reserved4: u1, - reserved5: u1, - /// Parity Mode - PMODE: u1, - reserved6: u1, - reserved7: u1, - /// Transmitter Enable - TXEN: u1, - /// Receiver Enable - RXEN: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// LIN Command - LINCMD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// USART_EXT Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// Guard Time - GTIME: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// LIN Master Break Length - BRKLEN: u2, - /// LIN Master Header Delay - HDRDLY: u2, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Inhibit Not Acknowledge - INACK: u1, - /// Disable Successive NACK - DSNACK: u1, - reserved9: u1, - reserved10: u1, - /// Maximum Iterations - MAXITER: u3, - reserved11: u1, - /// Data 32 Bit - DATA32B: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// USART_EXT Baud Rate - pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); - - /// address: 0x4000300c - /// USART_EXT Baud Rate - pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_EXT Baud Rate - pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_EXT Baud Rate - pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u16, - }), base_address + 0xc); - - /// address: 0x4000300e - /// USART_EXT Receive Pulse Length - pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); - - /// address: 0x40003014 - /// USART_EXT Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Disable - DRE: u1, - /// Transmit Complete Interrupt Disable - TXC: u1, - /// Receive Complete Interrupt Disable - RXC: u1, - /// Receive Start Interrupt Disable - RXS: u1, - /// Clear To Send Input Change Interrupt Disable - CTSIC: u1, - /// Break Received Interrupt Disable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// USART_EXT Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Enable - DRE: u1, - /// Transmit Complete Interrupt Enable - TXC: u1, - /// Receive Complete Interrupt Enable - RXC: u1, - /// Receive Start Interrupt Enable - RXS: u1, - /// Clear To Send Input Change Interrupt Enable - CTSIC: u1, - /// Break Received Interrupt Enable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// USART_EXT Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt - DRE: u1, - /// Transmit Complete Interrupt - TXC: u1, - /// Receive Complete Interrupt - RXC: u1, - /// Receive Start Interrupt - RXS: u1, - /// Clear To Send Input Change Interrupt - CTSIC: u1, - /// Break Received Interrupt - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// USART_EXT Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Parity Error - PERR: u1, - /// Frame Error - FERR: u1, - /// Buffer Overflow - BUFOVF: u1, - /// Clear To Send - CTS: u1, - /// Inconsistent Sync Field - ISF: u1, - /// Collision Detected - COLL: u1, - /// Transmitter Empty - TXE: u1, - /// Maximum Number of Repetitions Reached - ITER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// USART_EXT Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// CTRLB Synchronization Busy - CTRLB: u1, - /// RXERRCNT Synchronization Busy - RXERRCNT: u1, - /// LENGTH Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003020 - /// USART_EXT Receive Error Count - pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); - - /// address: 0x40003022 - /// USART_EXT Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x22); - - /// address: 0x40003028 - /// USART_EXT Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003030 - /// USART_EXT Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - - /// USART INTERNAL CLOCK Mode - pub const USART_INT = struct { - /// address: 0x40003000 - /// USART_INT Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - /// Immediate Buffer Overflow Notification - IBON: u1, - /// Transmit Data Invert - TXINV: u1, - /// Receive Data Invert - RXINV: u1, - reserved2: u1, - reserved3: u1, - /// Sample - SAMPR: u3, - /// Transmit Data Pinout - TXPO: u2, - reserved4: u1, - reserved5: u1, - /// Receive Data Pinout - RXPO: u2, - /// Sample Adjustment - SAMPA: u2, - /// Frame Format - FORM: u4, - /// Communication Mode - CMODE: u1, - /// Clock Polarity - CPOL: u1, - /// Data Order - DORD: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// USART_INT Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Character Size - CHSIZE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Stop Bit Mode - SBMODE: u1, - reserved3: u1, - /// Collision Detection Enable - COLDEN: u1, - /// Start of Frame Detection Enable - SFDE: u1, - /// Encoding Format - ENC: u1, - reserved4: u1, - reserved5: u1, - /// Parity Mode - PMODE: u1, - reserved6: u1, - reserved7: u1, - /// Transmitter Enable - TXEN: u1, - /// Receiver Enable - RXEN: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// LIN Command - LINCMD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// USART_INT Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// Guard Time - GTIME: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// LIN Master Break Length - BRKLEN: u2, - /// LIN Master Header Delay - HDRDLY: u2, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Inhibit Not Acknowledge - INACK: u1, - /// Disable Successive NACK - DSNACK: u1, - reserved9: u1, - reserved10: u1, - /// Maximum Iterations - MAXITER: u3, - reserved11: u1, - /// Data 32 Bit - DATA32B: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u16, - }), base_address + 0xc); - - /// address: 0x4000300e - /// USART_INT Receive Pulse Length - pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); - - /// address: 0x40003014 - /// USART_INT Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Disable - DRE: u1, - /// Transmit Complete Interrupt Disable - TXC: u1, - /// Receive Complete Interrupt Disable - RXC: u1, - /// Receive Start Interrupt Disable - RXS: u1, - /// Clear To Send Input Change Interrupt Disable - CTSIC: u1, - /// Break Received Interrupt Disable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// USART_INT Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Enable - DRE: u1, - /// Transmit Complete Interrupt Enable - TXC: u1, - /// Receive Complete Interrupt Enable - RXC: u1, - /// Receive Start Interrupt Enable - RXS: u1, - /// Clear To Send Input Change Interrupt Enable - CTSIC: u1, - /// Break Received Interrupt Enable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// USART_INT Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt - DRE: u1, - /// Transmit Complete Interrupt - TXC: u1, - /// Receive Complete Interrupt - RXC: u1, - /// Receive Start Interrupt - RXS: u1, - /// Clear To Send Input Change Interrupt - CTSIC: u1, - /// Break Received Interrupt - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// USART_INT Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Parity Error - PERR: u1, - /// Frame Error - FERR: u1, - /// Buffer Overflow - BUFOVF: u1, - /// Clear To Send - CTS: u1, - /// Inconsistent Sync Field - ISF: u1, - /// Collision Detected - COLL: u1, - /// Transmitter Empty - TXE: u1, - /// Maximum Number of Repetitions Reached - ITER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// USART_INT Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// CTRLB Synchronization Busy - CTRLB: u1, - /// RXERRCNT Synchronization Busy - RXERRCNT: u1, - /// LENGTH Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003020 - /// USART_INT Receive Error Count - pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); - - /// address: 0x40003022 - /// USART_INT Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x22); - - /// address: 0x40003028 - /// USART_INT Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003030 - /// USART_INT Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - }; - pub const SERCOM1 = struct { - pub const base_address = 0x40003400; - }; - pub const SERCOM2 = struct { - pub const base_address = 0x41012000; - }; - pub const SERCOM3 = struct { - pub const base_address = 0x41014000; - }; - pub const SERCOM4 = struct { - pub const base_address = 0x43000000; - }; - pub const SERCOM5 = struct { - pub const base_address: usize = 0x43000400; - - pub const USART_INT = struct { - /// address: 0x40003000 - /// USART_INT Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Operating Mode - MODE: u3, - reserved0: u1, - reserved1: u1, - /// Run during Standby - RUNSTDBY: u1, - /// Immediate Buffer Overflow Notification - IBON: u1, - /// Transmit Data Invert - TXINV: u1, - /// Receive Data Invert - RXINV: u1, - reserved2: u1, - reserved3: u1, - /// Sample - SAMPR: u3, - /// Transmit Data Pinout - TXPO: u2, - reserved4: u1, - reserved5: u1, - /// Receive Data Pinout - RXPO: u2, - /// Sample Adjustment - SAMPA: u2, - /// Frame Format - FORM: u4, - /// Communication Mode - CMODE: u1, - /// Clock Polarity - CPOL: u1, - /// Data Order - DORD: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// USART_INT Control B - pub const CTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Character Size - CHSIZE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Stop Bit Mode - SBMODE: u1, - reserved3: u1, - /// Collision Detection Enable - COLDEN: u1, - /// Start of Frame Detection Enable - SFDE: u1, - /// Encoding Format - ENC: u1, - reserved4: u1, - reserved5: u1, - /// Parity Mode - PMODE: u1, - reserved6: u1, - reserved7: u1, - /// Transmitter Enable - TXEN: u1, - /// Receiver Enable - RXEN: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// LIN Command - LINCMD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// USART_INT Control C - pub const CTRLC = @intToPtr(*volatile Mmio(32, packed struct { - /// Guard Time - GTIME: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// LIN Master Break Length - BRKLEN: u2, - /// LIN Master Header Delay - HDRDLY: u2, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Inhibit Not Acknowledge - INACK: u1, - /// Disable Successive NACK - DSNACK: u1, - reserved9: u1, - reserved10: u1, - /// Maximum Iterations - MAXITER: u3, - reserved11: u1, - /// Data 32 Bit - DATA32B: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD = @intToPtr(*volatile u16, base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_FRAC_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_FRACFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u13, - /// Fractional Part - FP: u3, - }), base_address + 0xc); - - /// address: 0x4000300c - /// USART_INT Baud Rate - pub const BAUD_USARTFP_MODE = @intToPtr(*volatile Mmio(16, packed struct { - /// Baud Rate Value - BAUD: u16, - }), base_address + 0xc); - - /// address: 0x4000300e - /// USART_INT Receive Pulse Length - pub const RXPL = @intToPtr(*volatile u8, base_address + 0xe); - - /// address: 0x40003014 - /// USART_INT Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Disable - DRE: u1, - /// Transmit Complete Interrupt Disable - TXC: u1, - /// Receive Complete Interrupt Disable - RXC: u1, - /// Receive Start Interrupt Disable - RXS: u1, - /// Clear To Send Input Change Interrupt Disable - CTSIC: u1, - /// Break Received Interrupt Disable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Disable - ERROR: u1, - }), base_address + 0x14); - - /// address: 0x40003016 - /// USART_INT Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt Enable - DRE: u1, - /// Transmit Complete Interrupt Enable - TXC: u1, - /// Receive Complete Interrupt Enable - RXC: u1, - /// Receive Start Interrupt Enable - RXS: u1, - /// Clear To Send Input Change Interrupt Enable - CTSIC: u1, - /// Break Received Interrupt Enable - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt Enable - ERROR: u1, - }), base_address + 0x16); - - /// address: 0x40003018 - /// USART_INT Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Register Empty Interrupt - DRE: u1, - /// Transmit Complete Interrupt - TXC: u1, - /// Receive Complete Interrupt - RXC: u1, - /// Receive Start Interrupt - RXS: u1, - /// Clear To Send Input Change Interrupt - CTSIC: u1, - /// Break Received Interrupt - RXBRK: u1, - reserved0: u1, - /// Combined Error Interrupt - ERROR: u1, - }), base_address + 0x18); - - /// address: 0x4000301a - /// USART_INT Status - pub const STATUS = @intToPtr(*volatile Mmio(16, packed struct { - /// Parity Error - PERR: u1, - /// Frame Error - FERR: u1, - /// Buffer Overflow - BUFOVF: u1, - /// Clear To Send - CTS: u1, - /// Inconsistent Sync Field - ISF: u1, - /// Collision Detected - COLL: u1, - /// Transmitter Empty - TXE: u1, - /// Maximum Number of Repetitions Reached - ITER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x1a); - - /// address: 0x4000301c - /// USART_INT Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// SERCOM Enable Synchronization Busy - ENABLE: u1, - /// CTRLB Synchronization Busy - CTRLB: u1, - /// RXERRCNT Synchronization Busy - RXERRCNT: u1, - /// LENGTH Synchronization Busy - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x1c); - - /// address: 0x40003020 - /// USART_INT Receive Error Count - pub const RXERRCNT = @intToPtr(*volatile u8, base_address + 0x20); - - /// address: 0x40003022 - /// USART_INT Length - pub const LENGTH = @intToPtr(*volatile Mmio(16, packed struct { - /// Data Length - LEN: u8, - /// Data Length Enable - LENEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x22); - - /// address: 0x40003028 - /// USART_INT Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003030 - /// USART_INT Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Mode - DBGSTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - }; - }; - - /// Supply Controller - pub const SUPC = struct { - pub const base_address = 0x40001800; - pub const version = "U24071.1.0"; - - /// address: 0x40001800 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// BOD33 Ready - BOD33RDY: u1, - /// BOD33 Detection - BOD33DET: u1, - /// BOD33 Synchronization Ready - B33SRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Voltage Regulator Ready - VREGRDY: u1, - reserved5: u1, - /// VDDCORE Ready - VCORERDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x0); - - /// address: 0x40001804 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// BOD33 Ready - BOD33RDY: u1, - /// BOD33 Detection - BOD33DET: u1, - /// BOD33 Synchronization Ready - B33SRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Voltage Regulator Ready - VREGRDY: u1, - reserved5: u1, - /// VDDCORE Ready - VCORERDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x40001808 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// BOD33 Ready - BOD33RDY: u1, - /// BOD33 Detection - BOD33DET: u1, - /// BOD33 Synchronization Ready - B33SRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Voltage Regulator Ready - VREGRDY: u1, - reserved5: u1, - /// VDDCORE Ready - VCORERDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x8); - - /// address: 0x4000180c - /// Power and Clocks Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// BOD33 Ready - BOD33RDY: u1, - /// BOD33 Detection - BOD33DET: u1, - /// BOD33 Synchronization Ready - B33SRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Voltage Regulator Ready - VREGRDY: u1, - reserved5: u1, - /// VDDCORE Ready - VCORERDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xc); - - /// address: 0x40001810 - /// BOD33 Control - pub const BOD33 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - /// Action when Threshold Crossed - ACTION: u2, - /// Configuration in Standby mode - STDBYCFG: u1, - /// Run in Standby mode - RUNSTDBY: u1, - /// Run in Hibernate mode - RUNHIB: u1, - /// Run in Backup mode - RUNBKUP: u1, - /// Hysteresis value - HYST: u4, - /// Prescaler Select - PSEL: u3, - reserved1: u1, - /// Threshold Level for VDD - LEVEL: u8, - /// Threshold Level in battery backup sleep mode for VBAT - VBATLEVEL: u8, - }), base_address + 0x10); - - /// address: 0x40001818 - /// VREG Control - pub const VREG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - /// Voltage Regulator Selection - SEL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Run in Backup mode - RUNBKUP: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Voltage Scaling Enable - VSEN: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Voltage Scaling Period - VSPER: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x4000181c - /// VREF Control - pub const VREF = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Temperature Sensor Output Enable - TSEN: u1, - /// Voltage Reference Output Enable - VREFOE: u1, - /// Temperature Sensor Selection - TSSEL: u1, - reserved1: u1, - reserved2: u1, - /// Run during Standby - RUNSTDBY: u1, - /// On Demand Contrl - ONDEMAND: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Voltage Reference Selection - SEL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x1c); - - /// address: 0x40001820 - /// Battery Backup Power Switch - pub const BBPS = @intToPtr(*volatile Mmio(32, packed struct { - /// Battery Backup Configuration - CONF: u1, - reserved0: u1, - /// Wake Enable - WAKEEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x20); - - /// address: 0x40001824 - /// Backup Output Control - pub const BKOUT = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable OUT0 - ENOUT0: u1, - /// Enable OUT1 - ENOUT1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Clear OUT0 - CLROUT0: u1, - /// Clear OUT1 - CLROUT1: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Set OUT0 - SETOUT0: u1, - /// Set OUT1 - SETOUT1: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// RTC Toggle OUT0 - RTCTGLOUT0: u1, - /// RTC Toggle OUT1 - RTCTGLOUT1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x24); - - /// address: 0x40001828 - /// Backup Input Control - pub const BKIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup Input 0 - BKIN0: u1, - /// Backup Input 1 - BKIN1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x28); - }; - - /// Basic Timer Counter - pub const TC0 = struct { - pub const base_address = 0x40003800; - pub const version = "U22493.0.0"; - - /// 8-bit Counter Mode - pub const COUNT8 = struct { - /// address: 0x40003800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Timer Counter Mode - MODE: u2, - /// Prescaler and Counter Synchronization - PRESCSYNC: u2, - /// Run during Standby - RUNSTDBY: u1, - /// Clock On Demand - ONDEMAND: u1, - /// Prescaler - PRESCALER: u3, - /// Auto Lock - ALOCK: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Capture Channel 0 Enable - CAPTEN0: u1, - /// Capture Channel 1 Enable - CAPTEN1: u1, - reserved4: u1, - reserved5: u1, - /// Capture On Pin 0 Enable - COPEN0: u1, - /// Capture On Pin 1 Enable - COPEN1: u1, - reserved6: u1, - reserved7: u1, - /// Capture Mode Channel 0 - CAPTMODE0: u2, - reserved8: u1, - /// Capture mode Channel 1 - CAPTMODE1: u2, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x40003805 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x40003806 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Event Action - EVACT: u3, - reserved0: u1, - /// TC Event Input Polarity - TCINV: u1, - /// TC Event Enable - TCEI: u1, - reserved1: u1, - reserved2: u1, - /// Event Output Enable - OVFEO: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// MC Event Output Enable 0 - MCEO0: u1, - /// MC Event Output Enable 1 - MCEO1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x6); - - /// address: 0x40003808 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Disable - OVF: u1, - /// ERR Interrupt Disable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Disable 0 - MC0: u1, - /// MC Interrupt Disable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0x40003809 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Enable - OVF: u1, - /// ERR Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Enable 0 - MC0: u1, - /// MC Interrupt Enable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x9); - - /// address: 0x4000380a - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Flag - OVF: u1, - /// ERR Interrupt Flag - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Flag 0 - MC0: u1, - /// MC Interrupt Flag 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xa); - - /// address: 0x4000380b - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Status Flag - STOP: u1, - /// Slave Status Flag - SLAVE: u1, - reserved0: u1, - /// Synchronization Busy Status - PERBUFV: u1, - /// Compare channel buffer 0 valid - CCBUFV0: u1, - /// Compare channel buffer 1 valid - CCBUFV1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xb); - - /// address: 0x4000380c - /// Waveform Generation Control - pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Generation Mode - WAVEGEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xc); - - /// address: 0x4000380d - /// Control C - pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Output Waveform Invert Enable 0 - INVEN0: u1, - /// Output Waveform Invert Enable 1 - INVEN1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xd); - - /// address: 0x4000380f - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xf); - - /// address: 0x40003810 - /// Synchronization Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// swrst - SWRST: u1, - /// enable - ENABLE: u1, - /// CTRLB - CTRLB: u1, - /// STATUS - STATUS: u1, - /// Counter - COUNT: u1, - /// Period - PER: u1, - /// Compare Channel 0 - CC0: u1, - /// Compare Channel 1 - CC1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// COUNT8 Count - pub const COUNT = @intToPtr(*volatile u8, base_address + 0x14); - - /// address: 0x4000381b - /// COUNT8 Period - pub const PER = @intToPtr(*volatile u8, base_address + 0x1b); - - /// address: 0x4000381c - /// COUNT8 Compare and Capture - pub const CC = @intToPtr(*volatile [2]u8, base_address + 0x1c); - - /// address: 0x4000382f - /// COUNT8 Period Buffer - pub const PERBUF = @intToPtr(*volatile u8, base_address + 0x2f); - - /// address: 0x40003830 - /// COUNT8 Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [2]u8, base_address + 0x30); - }; - - /// 16-bit Counter Mode - pub const COUNT16 = struct { - /// address: 0x40003800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Timer Counter Mode - MODE: u2, - /// Prescaler and Counter Synchronization - PRESCSYNC: u2, - /// Run during Standby - RUNSTDBY: u1, - /// Clock On Demand - ONDEMAND: u1, - /// Prescaler - PRESCALER: u3, - /// Auto Lock - ALOCK: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Capture Channel 0 Enable - CAPTEN0: u1, - /// Capture Channel 1 Enable - CAPTEN1: u1, - reserved4: u1, - reserved5: u1, - /// Capture On Pin 0 Enable - COPEN0: u1, - /// Capture On Pin 1 Enable - COPEN1: u1, - reserved6: u1, - reserved7: u1, - /// Capture Mode Channel 0 - CAPTMODE0: u2, - reserved8: u1, - /// Capture mode Channel 1 - CAPTMODE1: u2, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x40003805 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x40003806 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Event Action - EVACT: u3, - reserved0: u1, - /// TC Event Input Polarity - TCINV: u1, - /// TC Event Enable - TCEI: u1, - reserved1: u1, - reserved2: u1, - /// Event Output Enable - OVFEO: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// MC Event Output Enable 0 - MCEO0: u1, - /// MC Event Output Enable 1 - MCEO1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x6); - - /// address: 0x40003808 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Disable - OVF: u1, - /// ERR Interrupt Disable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Disable 0 - MC0: u1, - /// MC Interrupt Disable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0x40003809 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Enable - OVF: u1, - /// ERR Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Enable 0 - MC0: u1, - /// MC Interrupt Enable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x9); - - /// address: 0x4000380a - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Flag - OVF: u1, - /// ERR Interrupt Flag - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Flag 0 - MC0: u1, - /// MC Interrupt Flag 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xa); - - /// address: 0x4000380b - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Status Flag - STOP: u1, - /// Slave Status Flag - SLAVE: u1, - reserved0: u1, - /// Synchronization Busy Status - PERBUFV: u1, - /// Compare channel buffer 0 valid - CCBUFV0: u1, - /// Compare channel buffer 1 valid - CCBUFV1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xb); - - /// address: 0x4000380c - /// Waveform Generation Control - pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Generation Mode - WAVEGEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xc); - - /// address: 0x4000380d - /// Control C - pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Output Waveform Invert Enable 0 - INVEN0: u1, - /// Output Waveform Invert Enable 1 - INVEN1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xd); - - /// address: 0x4000380f - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xf); - - /// address: 0x40003810 - /// Synchronization Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// swrst - SWRST: u1, - /// enable - ENABLE: u1, - /// CTRLB - CTRLB: u1, - /// STATUS - STATUS: u1, - /// Counter - COUNT: u1, - /// Period - PER: u1, - /// Compare Channel 0 - CC0: u1, - /// Compare Channel 1 - CC1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// COUNT16 Count - pub const COUNT = @intToPtr(*volatile u16, base_address + 0x14); - - /// address: 0x4000381c - /// COUNT16 Compare and Capture - pub const CC = @intToPtr(*volatile [2]u16, base_address + 0x1c); - - /// address: 0x40003830 - /// COUNT16 Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [2]u16, base_address + 0x30); - }; - - /// 32-bit Counter Mode - pub const COUNT32 = struct { - /// address: 0x40003800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Timer Counter Mode - MODE: u2, - /// Prescaler and Counter Synchronization - PRESCSYNC: u2, - /// Run during Standby - RUNSTDBY: u1, - /// Clock On Demand - ONDEMAND: u1, - /// Prescaler - PRESCALER: u3, - /// Auto Lock - ALOCK: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Capture Channel 0 Enable - CAPTEN0: u1, - /// Capture Channel 1 Enable - CAPTEN1: u1, - reserved4: u1, - reserved5: u1, - /// Capture On Pin 0 Enable - COPEN0: u1, - /// Capture On Pin 1 Enable - COPEN1: u1, - reserved6: u1, - reserved7: u1, - /// Capture Mode Channel 0 - CAPTMODE0: u2, - reserved8: u1, - /// Capture mode Channel 1 - CAPTMODE1: u2, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x40003805 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot on Counter - ONESHOT: u1, - reserved0: u1, - reserved1: u1, - /// Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x40003806 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(16, packed struct { - /// Event Action - EVACT: u3, - reserved0: u1, - /// TC Event Input Polarity - TCINV: u1, - /// TC Event Enable - TCEI: u1, - reserved1: u1, - reserved2: u1, - /// Event Output Enable - OVFEO: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// MC Event Output Enable 0 - MCEO0: u1, - /// MC Event Output Enable 1 - MCEO1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x6); - - /// address: 0x40003808 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Disable - OVF: u1, - /// ERR Interrupt Disable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Disable 0 - MC0: u1, - /// MC Interrupt Disable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0x40003809 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Enable - OVF: u1, - /// ERR Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Enable 0 - MC0: u1, - /// MC Interrupt Enable 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x9); - - /// address: 0x4000380a - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// OVF Interrupt Flag - OVF: u1, - /// ERR Interrupt Flag - ERR: u1, - reserved0: u1, - reserved1: u1, - /// MC Interrupt Flag 0 - MC0: u1, - /// MC Interrupt Flag 1 - MC1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xa); - - /// address: 0x4000380b - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// Stop Status Flag - STOP: u1, - /// Slave Status Flag - SLAVE: u1, - reserved0: u1, - /// Synchronization Busy Status - PERBUFV: u1, - /// Compare channel buffer 0 valid - CCBUFV0: u1, - /// Compare channel buffer 1 valid - CCBUFV1: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xb); - - /// address: 0x4000380c - /// Waveform Generation Control - pub const WAVE = @intToPtr(*volatile Mmio(8, packed struct { - /// Waveform Generation Mode - WAVEGEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xc); - - /// address: 0x4000380d - /// Control C - pub const DRVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Output Waveform Invert Enable 0 - INVEN0: u1, - /// Output Waveform Invert Enable 1 - INVEN1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xd); - - /// address: 0x4000380f - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Run During Debug - DBGRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xf); - - /// address: 0x40003810 - /// Synchronization Status - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// swrst - SWRST: u1, - /// enable - ENABLE: u1, - /// CTRLB - CTRLB: u1, - /// STATUS - STATUS: u1, - /// Counter - COUNT: u1, - /// Period - PER: u1, - /// Compare Channel 0 - CC0: u1, - /// Compare Channel 1 - CC1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// COUNT32 Count - pub const COUNT = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000381c - /// COUNT32 Compare and Capture - pub const CC = @intToPtr(*volatile [2]u32, base_address + 0x1c); - - /// address: 0x40003830 - /// COUNT32 Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [2]u32, base_address + 0x30); - }; - }; - pub const TC1 = struct { - pub const base_address = 0x40003c00; - }; - pub const TC2 = struct { - pub const base_address = 0x4101a000; - }; - pub const TC3 = struct { - pub const base_address = 0x4101c000; - }; - pub const TC4 = struct { - pub const base_address = 0x42001400; - }; - pub const TC5 = struct { - pub const base_address = 0x42001800; - }; - - /// Timer Counter Control - pub const TCC0 = struct { - pub const base_address = 0x41016000; - pub const version = "U22133.1.0"; - - /// address: 0x41016000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Enhanced Resolution - RESOLUTION: u2, - reserved3: u1, - /// Prescaler - PRESCALER: u3, - /// Run in Standby - RUNSTDBY: u1, - /// Prescaler and Counter Synchronization Selection - PRESCSYNC: u2, - /// Auto Lock - ALOCK: u1, - /// Master Synchronization (only for TCC Slave Instance) - MSYNC: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA One-shot Trigger Mode - DMAOS: u1, - /// Capture Channel 0 Enable - CPTEN0: u1, - /// Capture Channel 1 Enable - CPTEN1: u1, - /// Capture Channel 2 Enable - CPTEN2: u1, - /// Capture Channel 3 Enable - CPTEN3: u1, - /// Capture Channel 4 Enable - CPTEN4: u1, - /// Capture Channel 5 Enable - CPTEN5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x41016004 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x41016005 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x41016008 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Swrst Busy - SWRST: u1, - /// Enable Busy - ENABLE: u1, - /// Ctrlb Busy - CTRLB: u1, - /// Status Busy - STATUS: u1, - /// Count Busy - COUNT: u1, - /// Pattern Busy - PATT: u1, - /// Wave Busy - WAVE: u1, - /// Period Busy - PER: u1, - /// Compare Channel 0 Busy - CC0: u1, - /// Compare Channel 1 Busy - CC1: u1, - /// Compare Channel 2 Busy - CC2: u1, - /// Compare Channel 3 Busy - CC3: u1, - /// Compare Channel 4 Busy - CC4: u1, - /// Compare Channel 5 Busy - CC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x8); - - /// address: 0x4101600c - /// Recoverable Fault A Configuration - pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault A Source - SRC: u2, - reserved0: u1, - /// Fault A Keeper - KEEP: u1, - /// Fault A Qualification - QUAL: u1, - /// Fault A Blanking Mode - BLANK: u2, - /// Fault A Restart - RESTART: u1, - /// Fault A Halt Mode - HALT: u2, - /// Fault A Capture Channel - CHSEL: u2, - /// Fault A Capture Action - CAPTURE: u3, - /// Fault A Blanking Prescaler - BLANKPRESC: u1, - /// Fault A Blanking Time - BLANKVAL: u8, - /// Fault A Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x41016010 - /// Recoverable Fault B Configuration - pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault B Source - SRC: u2, - reserved0: u1, - /// Fault B Keeper - KEEP: u1, - /// Fault B Qualification - QUAL: u1, - /// Fault B Blanking Mode - BLANK: u2, - /// Fault B Restart - RESTART: u1, - /// Fault B Halt Mode - HALT: u2, - /// Fault B Capture Channel - CHSEL: u2, - /// Fault B Capture Action - CAPTURE: u3, - /// Fault B Blanking Prescaler - BLANKPRESC: u1, - /// Fault B Blanking Time - BLANKVAL: u8, - /// Fault B Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x41016014 - /// Waveform Extension Configuration - pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Output Matrix - OTMX: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Dead-time Insertion Generator 0 Enable - DTIEN0: u1, - /// Dead-time Insertion Generator 1 Enable - DTIEN1: u1, - /// Dead-time Insertion Generator 2 Enable - DTIEN2: u1, - /// Dead-time Insertion Generator 3 Enable - DTIEN3: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Dead-time Low Side Outputs Value - DTLS: u8, - /// Dead-time High Side Outputs Value - DTHS: u8, - }), base_address + 0x14); - - /// address: 0x41016018 - /// Driver Control - pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-Recoverable State 0 Output Enable - NRE0: u1, - /// Non-Recoverable State 1 Output Enable - NRE1: u1, - /// Non-Recoverable State 2 Output Enable - NRE2: u1, - /// Non-Recoverable State 3 Output Enable - NRE3: u1, - /// Non-Recoverable State 4 Output Enable - NRE4: u1, - /// Non-Recoverable State 5 Output Enable - NRE5: u1, - /// Non-Recoverable State 6 Output Enable - NRE6: u1, - /// Non-Recoverable State 7 Output Enable - NRE7: u1, - /// Non-Recoverable State 0 Output Value - NRV0: u1, - /// Non-Recoverable State 1 Output Value - NRV1: u1, - /// Non-Recoverable State 2 Output Value - NRV2: u1, - /// Non-Recoverable State 3 Output Value - NRV3: u1, - /// Non-Recoverable State 4 Output Value - NRV4: u1, - /// Non-Recoverable State 5 Output Value - NRV5: u1, - /// Non-Recoverable State 6 Output Value - NRV6: u1, - /// Non-Recoverable State 7 Output Value - NRV7: u1, - /// Output Waveform 0 Inversion - INVEN0: u1, - /// Output Waveform 1 Inversion - INVEN1: u1, - /// Output Waveform 2 Inversion - INVEN2: u1, - /// Output Waveform 3 Inversion - INVEN3: u1, - /// Output Waveform 4 Inversion - INVEN4: u1, - /// Output Waveform 5 Inversion - INVEN5: u1, - /// Output Waveform 6 Inversion - INVEN6: u1, - /// Output Waveform 7 Inversion - INVEN7: u1, - /// Non-Recoverable Fault Input 0 Filter Value - FILTERVAL0: u4, - /// Non-Recoverable Fault Input 1 Filter Value - FILTERVAL1: u4, - }), base_address + 0x18); - - /// address: 0x4101601e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Running Mode - DBGRUN: u1, - reserved0: u1, - /// Fault Detection on Debug Break Detection - FDDBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1e); - - /// address: 0x41016020 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer/counter Input Event0 Action - EVACT0: u3, - /// Timer/counter Input Event1 Action - EVACT1: u3, - /// Timer/counter Output Event Mode - CNTSEL: u2, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Retrigger Output Event Enable - TRGEO: u1, - /// Timer/counter Output Event Enable - CNTEO: u1, - reserved0: u1, - /// Inverted Event 0 Input Enable - TCINV0: u1, - /// Inverted Event 1 Input Enable - TCINV1: u1, - /// Timer/counter Event 0 Input Enable - TCEI0: u1, - /// Timer/counter Event 1 Input Enable - TCEI1: u1, - /// Match or Capture Channel 0 Event Input Enable - MCEI0: u1, - /// Match or Capture Channel 1 Event Input Enable - MCEI1: u1, - /// Match or Capture Channel 2 Event Input Enable - MCEI2: u1, - /// Match or Capture Channel 3 Event Input Enable - MCEI3: u1, - /// Match or Capture Channel 4 Event Input Enable - MCEI4: u1, - /// Match or Capture Channel 5 Event Input Enable - MCEI5: u1, - reserved1: u1, - reserved2: u1, - /// Match or Capture Channel 0 Event Output Enable - MCEO0: u1, - /// Match or Capture Channel 1 Event Output Enable - MCEO1: u1, - /// Match or Capture Channel 2 Event Output Enable - MCEO2: u1, - /// Match or Capture Channel 3 Event Output Enable - MCEO3: u1, - /// Match or Capture Channel 4 Event Output Enable - MCEO4: u1, - /// Match or Capture Channel 5 Event Output Enable - MCEO5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x41016024 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x24); - - /// address: 0x41016028 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x28); - - /// address: 0x4101602c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow - OVF: u1, - /// Retrigger - TRG: u1, - /// Counter - CNT: u1, - /// Error - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault - UFS: u1, - /// Non-Recoverable Debug Fault - DFS: u1, - /// Recoverable Fault A - FAULTA: u1, - /// Recoverable Fault B - FAULTB: u1, - /// Non-Recoverable Fault 0 - FAULT0: u1, - /// Non-Recoverable Fault 1 - FAULT1: u1, - /// Match or Capture 0 - MC0: u1, - /// Match or Capture 1 - MC1: u1, - /// Match or Capture 2 - MC2: u1, - /// Match or Capture 3 - MC3: u1, - /// Match or Capture 4 - MC4: u1, - /// Match or Capture 5 - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x2c); - - /// address: 0x41016030 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop - STOP: u1, - /// Ramp - IDX: u1, - /// Non-recoverable Update Fault State - UFS: u1, - /// Non-Recoverable Debug Fault State - DFS: u1, - /// Slave - SLAVE: u1, - /// Pattern Buffer Valid - PATTBUFV: u1, - reserved0: u1, - /// Period Buffer Valid - PERBUFV: u1, - /// Recoverable Fault A Input - FAULTAIN: u1, - /// Recoverable Fault B Input - FAULTBIN: u1, - /// Non-Recoverable Fault0 Input - FAULT0IN: u1, - /// Non-Recoverable Fault1 Input - FAULT1IN: u1, - /// Recoverable Fault A State - FAULTA: u1, - /// Recoverable Fault B State - FAULTB: u1, - /// Non-Recoverable Fault 0 State - FAULT0: u1, - /// Non-Recoverable Fault 1 State - FAULT1: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - /// Compare Channel 2 Buffer Valid - CCBUFV2: u1, - /// Compare Channel 3 Buffer Valid - CCBUFV3: u1, - /// Compare Channel 4 Buffer Valid - CCBUFV4: u1, - /// Compare Channel 5 Buffer Valid - CCBUFV5: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Value - CMP0: u1, - /// Compare Channel 1 Value - CMP1: u1, - /// Compare Channel 2 Value - CMP2: u1, - /// Compare Channel 3 Value - CMP3: u1, - /// Compare Channel 4 Value - CMP4: u1, - /// Compare Channel 5 Value - CMP5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x41016034 - /// Count - pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); - - /// address: 0x41016034 - /// Count - pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Counter Value - COUNT: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41016034 - /// Count - pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Counter Value - COUNT: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41016034 - /// Count - pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Counter Value - COUNT: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41016038 - /// Pattern - pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable - PGE0: u1, - /// Pattern Generator 1 Output Enable - PGE1: u1, - /// Pattern Generator 2 Output Enable - PGE2: u1, - /// Pattern Generator 3 Output Enable - PGE3: u1, - /// Pattern Generator 4 Output Enable - PGE4: u1, - /// Pattern Generator 5 Output Enable - PGE5: u1, - /// Pattern Generator 6 Output Enable - PGE6: u1, - /// Pattern Generator 7 Output Enable - PGE7: u1, - /// Pattern Generator 0 Output Value - PGV0: u1, - /// Pattern Generator 1 Output Value - PGV1: u1, - /// Pattern Generator 2 Output Value - PGV2: u1, - /// Pattern Generator 3 Output Value - PGV3: u1, - /// Pattern Generator 4 Output Value - PGV4: u1, - /// Pattern Generator 5 Output Value - PGV5: u1, - /// Pattern Generator 6 Output Value - PGV6: u1, - /// Pattern Generator 7 Output Value - PGV7: u1, - }), base_address + 0x38); - - /// address: 0x4101603c - /// Waveform Control - pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Waveform Generation - WAVEGEN: u3, - reserved0: u1, - /// Ramp Mode - RAMP: u2, - reserved1: u1, - /// Circular period Enable - CIPEREN: u1, - /// Circular Channel 0 Enable - CICCEN0: u1, - /// Circular Channel 1 Enable - CICCEN1: u1, - /// Circular Channel 2 Enable - CICCEN2: u1, - /// Circular Channel 3 Enable - CICCEN3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Channel 0 Polarity - POL0: u1, - /// Channel 1 Polarity - POL1: u1, - /// Channel 2 Polarity - POL2: u1, - /// Channel 3 Polarity - POL3: u1, - /// Channel 4 Polarity - POL4: u1, - /// Channel 5 Polarity - POL5: u1, - reserved6: u1, - reserved7: u1, - /// Swap DTI Output Pair 0 - SWAP0: u1, - /// Swap DTI Output Pair 1 - SWAP1: u1, - /// Swap DTI Output Pair 2 - SWAP2: u1, - /// Swap DTI Output Pair 3 - SWAP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3c); - - /// address: 0x41016040 - /// Period - pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); - - /// address: 0x41016040 - /// Period - pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Period Value - PER: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41016040 - /// Period - pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Period Value - PER: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41016040 - /// Period - pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Period Value - PER: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41016044 - /// Compare and Capture - pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); - - /// address: 0x41016044 - /// Compare and Capture - pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Channel Compare/Capture Value - CC: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41016044 - /// Compare and Capture - pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Channel Compare/Capture Value - CC: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41016044 - /// Compare and Capture - pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Channel Compare/Capture Value - CC: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41016064 - /// Pattern Buffer - pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable Buffer - PGEB0: u1, - /// Pattern Generator 1 Output Enable Buffer - PGEB1: u1, - /// Pattern Generator 2 Output Enable Buffer - PGEB2: u1, - /// Pattern Generator 3 Output Enable Buffer - PGEB3: u1, - /// Pattern Generator 4 Output Enable Buffer - PGEB4: u1, - /// Pattern Generator 5 Output Enable Buffer - PGEB5: u1, - /// Pattern Generator 6 Output Enable Buffer - PGEB6: u1, - /// Pattern Generator 7 Output Enable Buffer - PGEB7: u1, - /// Pattern Generator 0 Output Enable - PGVB0: u1, - /// Pattern Generator 1 Output Enable - PGVB1: u1, - /// Pattern Generator 2 Output Enable - PGVB2: u1, - /// Pattern Generator 3 Output Enable - PGVB3: u1, - /// Pattern Generator 4 Output Enable - PGVB4: u1, - /// Pattern Generator 5 Output Enable - PGVB5: u1, - /// Pattern Generator 6 Output Enable - PGVB6: u1, - /// Pattern Generator 7 Output Enable - PGVB7: u1, - }), base_address + 0x64); - - /// address: 0x4101606c - /// Period Buffer - pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); - - /// address: 0x4101606c - /// Period Buffer - pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u4, - /// Period Buffer Value - PERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4101606c - /// Period Buffer - pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Period Buffer Value - PERBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4101606c - /// Period Buffer - pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Period Buffer Value - PERBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x41016070 - /// Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); - - /// address: 0x41016070 - /// Compare and Capture Buffer - pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Channel Compare/Capture Buffer Value - CCBUF: u4, - /// Dithering Buffer Cycle Number - DITHERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x41016070 - /// Compare and Capture Buffer - pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Channel Compare/Capture Buffer Value - CCBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x41016070 - /// Compare and Capture Buffer - pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Channel Compare/Capture Buffer Value - CCBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - }; - pub const TCC1 = struct { - pub const base_address = 0x41018000; - - /// address: 0x41018000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Enhanced Resolution - RESOLUTION: u2, - reserved3: u1, - /// Prescaler - PRESCALER: u3, - /// Run in Standby - RUNSTDBY: u1, - /// Prescaler and Counter Synchronization Selection - PRESCSYNC: u2, - /// Auto Lock - ALOCK: u1, - /// Master Synchronization (only for TCC Slave Instance) - MSYNC: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA One-shot Trigger Mode - DMAOS: u1, - /// Capture Channel 0 Enable - CPTEN0: u1, - /// Capture Channel 1 Enable - CPTEN1: u1, - /// Capture Channel 2 Enable - CPTEN2: u1, - /// Capture Channel 3 Enable - CPTEN3: u1, - /// Capture Channel 4 Enable - CPTEN4: u1, - /// Capture Channel 5 Enable - CPTEN5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x41018004 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x41018005 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x41018008 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Swrst Busy - SWRST: u1, - /// Enable Busy - ENABLE: u1, - /// Ctrlb Busy - CTRLB: u1, - /// Status Busy - STATUS: u1, - /// Count Busy - COUNT: u1, - /// Pattern Busy - PATT: u1, - /// Wave Busy - WAVE: u1, - /// Period Busy - PER: u1, - /// Compare Channel 0 Busy - CC0: u1, - /// Compare Channel 1 Busy - CC1: u1, - /// Compare Channel 2 Busy - CC2: u1, - /// Compare Channel 3 Busy - CC3: u1, - /// Compare Channel 4 Busy - CC4: u1, - /// Compare Channel 5 Busy - CC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x8); - - /// address: 0x4101800c - /// Recoverable Fault A Configuration - pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault A Source - SRC: u2, - reserved0: u1, - /// Fault A Keeper - KEEP: u1, - /// Fault A Qualification - QUAL: u1, - /// Fault A Blanking Mode - BLANK: u2, - /// Fault A Restart - RESTART: u1, - /// Fault A Halt Mode - HALT: u2, - /// Fault A Capture Channel - CHSEL: u2, - /// Fault A Capture Action - CAPTURE: u3, - /// Fault A Blanking Prescaler - BLANKPRESC: u1, - /// Fault A Blanking Time - BLANKVAL: u8, - /// Fault A Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x41018010 - /// Recoverable Fault B Configuration - pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault B Source - SRC: u2, - reserved0: u1, - /// Fault B Keeper - KEEP: u1, - /// Fault B Qualification - QUAL: u1, - /// Fault B Blanking Mode - BLANK: u2, - /// Fault B Restart - RESTART: u1, - /// Fault B Halt Mode - HALT: u2, - /// Fault B Capture Channel - CHSEL: u2, - /// Fault B Capture Action - CAPTURE: u3, - /// Fault B Blanking Prescaler - BLANKPRESC: u1, - /// Fault B Blanking Time - BLANKVAL: u8, - /// Fault B Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x41018014 - /// Waveform Extension Configuration - pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Output Matrix - OTMX: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Dead-time Insertion Generator 0 Enable - DTIEN0: u1, - /// Dead-time Insertion Generator 1 Enable - DTIEN1: u1, - /// Dead-time Insertion Generator 2 Enable - DTIEN2: u1, - /// Dead-time Insertion Generator 3 Enable - DTIEN3: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Dead-time Low Side Outputs Value - DTLS: u8, - /// Dead-time High Side Outputs Value - DTHS: u8, - }), base_address + 0x14); - - /// address: 0x41018018 - /// Driver Control - pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-Recoverable State 0 Output Enable - NRE0: u1, - /// Non-Recoverable State 1 Output Enable - NRE1: u1, - /// Non-Recoverable State 2 Output Enable - NRE2: u1, - /// Non-Recoverable State 3 Output Enable - NRE3: u1, - /// Non-Recoverable State 4 Output Enable - NRE4: u1, - /// Non-Recoverable State 5 Output Enable - NRE5: u1, - /// Non-Recoverable State 6 Output Enable - NRE6: u1, - /// Non-Recoverable State 7 Output Enable - NRE7: u1, - /// Non-Recoverable State 0 Output Value - NRV0: u1, - /// Non-Recoverable State 1 Output Value - NRV1: u1, - /// Non-Recoverable State 2 Output Value - NRV2: u1, - /// Non-Recoverable State 3 Output Value - NRV3: u1, - /// Non-Recoverable State 4 Output Value - NRV4: u1, - /// Non-Recoverable State 5 Output Value - NRV5: u1, - /// Non-Recoverable State 6 Output Value - NRV6: u1, - /// Non-Recoverable State 7 Output Value - NRV7: u1, - /// Output Waveform 0 Inversion - INVEN0: u1, - /// Output Waveform 1 Inversion - INVEN1: u1, - /// Output Waveform 2 Inversion - INVEN2: u1, - /// Output Waveform 3 Inversion - INVEN3: u1, - /// Output Waveform 4 Inversion - INVEN4: u1, - /// Output Waveform 5 Inversion - INVEN5: u1, - /// Output Waveform 6 Inversion - INVEN6: u1, - /// Output Waveform 7 Inversion - INVEN7: u1, - /// Non-Recoverable Fault Input 0 Filter Value - FILTERVAL0: u4, - /// Non-Recoverable Fault Input 1 Filter Value - FILTERVAL1: u4, - }), base_address + 0x18); - - /// address: 0x4101801e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Running Mode - DBGRUN: u1, - reserved0: u1, - /// Fault Detection on Debug Break Detection - FDDBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1e); - - /// address: 0x41018020 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer/counter Input Event0 Action - EVACT0: u3, - /// Timer/counter Input Event1 Action - EVACT1: u3, - /// Timer/counter Output Event Mode - CNTSEL: u2, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Retrigger Output Event Enable - TRGEO: u1, - /// Timer/counter Output Event Enable - CNTEO: u1, - reserved0: u1, - /// Inverted Event 0 Input Enable - TCINV0: u1, - /// Inverted Event 1 Input Enable - TCINV1: u1, - /// Timer/counter Event 0 Input Enable - TCEI0: u1, - /// Timer/counter Event 1 Input Enable - TCEI1: u1, - /// Match or Capture Channel 0 Event Input Enable - MCEI0: u1, - /// Match or Capture Channel 1 Event Input Enable - MCEI1: u1, - /// Match or Capture Channel 2 Event Input Enable - MCEI2: u1, - /// Match or Capture Channel 3 Event Input Enable - MCEI3: u1, - /// Match or Capture Channel 4 Event Input Enable - MCEI4: u1, - /// Match or Capture Channel 5 Event Input Enable - MCEI5: u1, - reserved1: u1, - reserved2: u1, - /// Match or Capture Channel 0 Event Output Enable - MCEO0: u1, - /// Match or Capture Channel 1 Event Output Enable - MCEO1: u1, - /// Match or Capture Channel 2 Event Output Enable - MCEO2: u1, - /// Match or Capture Channel 3 Event Output Enable - MCEO3: u1, - /// Match or Capture Channel 4 Event Output Enable - MCEO4: u1, - /// Match or Capture Channel 5 Event Output Enable - MCEO5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x41018024 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x24); - - /// address: 0x41018028 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x28); - - /// address: 0x4101802c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow - OVF: u1, - /// Retrigger - TRG: u1, - /// Counter - CNT: u1, - /// Error - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault - UFS: u1, - /// Non-Recoverable Debug Fault - DFS: u1, - /// Recoverable Fault A - FAULTA: u1, - /// Recoverable Fault B - FAULTB: u1, - /// Non-Recoverable Fault 0 - FAULT0: u1, - /// Non-Recoverable Fault 1 - FAULT1: u1, - /// Match or Capture 0 - MC0: u1, - /// Match or Capture 1 - MC1: u1, - /// Match or Capture 2 - MC2: u1, - /// Match or Capture 3 - MC3: u1, - /// Match or Capture 4 - MC4: u1, - /// Match or Capture 5 - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x2c); - - /// address: 0x41018030 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop - STOP: u1, - /// Ramp - IDX: u1, - /// Non-recoverable Update Fault State - UFS: u1, - /// Non-Recoverable Debug Fault State - DFS: u1, - /// Slave - SLAVE: u1, - /// Pattern Buffer Valid - PATTBUFV: u1, - reserved0: u1, - /// Period Buffer Valid - PERBUFV: u1, - /// Recoverable Fault A Input - FAULTAIN: u1, - /// Recoverable Fault B Input - FAULTBIN: u1, - /// Non-Recoverable Fault0 Input - FAULT0IN: u1, - /// Non-Recoverable Fault1 Input - FAULT1IN: u1, - /// Recoverable Fault A State - FAULTA: u1, - /// Recoverable Fault B State - FAULTB: u1, - /// Non-Recoverable Fault 0 State - FAULT0: u1, - /// Non-Recoverable Fault 1 State - FAULT1: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - /// Compare Channel 2 Buffer Valid - CCBUFV2: u1, - /// Compare Channel 3 Buffer Valid - CCBUFV3: u1, - /// Compare Channel 4 Buffer Valid - CCBUFV4: u1, - /// Compare Channel 5 Buffer Valid - CCBUFV5: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Value - CMP0: u1, - /// Compare Channel 1 Value - CMP1: u1, - /// Compare Channel 2 Value - CMP2: u1, - /// Compare Channel 3 Value - CMP3: u1, - /// Compare Channel 4 Value - CMP4: u1, - /// Compare Channel 5 Value - CMP5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x41018034 - /// Count - pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); - - /// address: 0x41018034 - /// Count - pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Counter Value - COUNT: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41018034 - /// Count - pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Counter Value - COUNT: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41018034 - /// Count - pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Counter Value - COUNT: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x41018038 - /// Pattern - pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable - PGE0: u1, - /// Pattern Generator 1 Output Enable - PGE1: u1, - /// Pattern Generator 2 Output Enable - PGE2: u1, - /// Pattern Generator 3 Output Enable - PGE3: u1, - /// Pattern Generator 4 Output Enable - PGE4: u1, - /// Pattern Generator 5 Output Enable - PGE5: u1, - /// Pattern Generator 6 Output Enable - PGE6: u1, - /// Pattern Generator 7 Output Enable - PGE7: u1, - /// Pattern Generator 0 Output Value - PGV0: u1, - /// Pattern Generator 1 Output Value - PGV1: u1, - /// Pattern Generator 2 Output Value - PGV2: u1, - /// Pattern Generator 3 Output Value - PGV3: u1, - /// Pattern Generator 4 Output Value - PGV4: u1, - /// Pattern Generator 5 Output Value - PGV5: u1, - /// Pattern Generator 6 Output Value - PGV6: u1, - /// Pattern Generator 7 Output Value - PGV7: u1, - }), base_address + 0x38); - - /// address: 0x4101803c - /// Waveform Control - pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Waveform Generation - WAVEGEN: u3, - reserved0: u1, - /// Ramp Mode - RAMP: u2, - reserved1: u1, - /// Circular period Enable - CIPEREN: u1, - /// Circular Channel 0 Enable - CICCEN0: u1, - /// Circular Channel 1 Enable - CICCEN1: u1, - /// Circular Channel 2 Enable - CICCEN2: u1, - /// Circular Channel 3 Enable - CICCEN3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Channel 0 Polarity - POL0: u1, - /// Channel 1 Polarity - POL1: u1, - /// Channel 2 Polarity - POL2: u1, - /// Channel 3 Polarity - POL3: u1, - /// Channel 4 Polarity - POL4: u1, - /// Channel 5 Polarity - POL5: u1, - reserved6: u1, - reserved7: u1, - /// Swap DTI Output Pair 0 - SWAP0: u1, - /// Swap DTI Output Pair 1 - SWAP1: u1, - /// Swap DTI Output Pair 2 - SWAP2: u1, - /// Swap DTI Output Pair 3 - SWAP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3c); - - /// address: 0x41018040 - /// Period - pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); - - /// address: 0x41018040 - /// Period - pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Period Value - PER: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41018040 - /// Period - pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Period Value - PER: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41018040 - /// Period - pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Period Value - PER: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x41018044 - /// Compare and Capture - pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); - - /// address: 0x41018044 - /// Compare and Capture - pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Channel Compare/Capture Value - CC: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41018044 - /// Compare and Capture - pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Channel Compare/Capture Value - CC: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41018044 - /// Compare and Capture - pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Channel Compare/Capture Value - CC: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x41018064 - /// Pattern Buffer - pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable Buffer - PGEB0: u1, - /// Pattern Generator 1 Output Enable Buffer - PGEB1: u1, - /// Pattern Generator 2 Output Enable Buffer - PGEB2: u1, - /// Pattern Generator 3 Output Enable Buffer - PGEB3: u1, - /// Pattern Generator 4 Output Enable Buffer - PGEB4: u1, - /// Pattern Generator 5 Output Enable Buffer - PGEB5: u1, - /// Pattern Generator 6 Output Enable Buffer - PGEB6: u1, - /// Pattern Generator 7 Output Enable Buffer - PGEB7: u1, - /// Pattern Generator 0 Output Enable - PGVB0: u1, - /// Pattern Generator 1 Output Enable - PGVB1: u1, - /// Pattern Generator 2 Output Enable - PGVB2: u1, - /// Pattern Generator 3 Output Enable - PGVB3: u1, - /// Pattern Generator 4 Output Enable - PGVB4: u1, - /// Pattern Generator 5 Output Enable - PGVB5: u1, - /// Pattern Generator 6 Output Enable - PGVB6: u1, - /// Pattern Generator 7 Output Enable - PGVB7: u1, - }), base_address + 0x64); - - /// address: 0x4101806c - /// Period Buffer - pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); - - /// address: 0x4101806c - /// Period Buffer - pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u4, - /// Period Buffer Value - PERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4101806c - /// Period Buffer - pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Period Buffer Value - PERBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4101806c - /// Period Buffer - pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Period Buffer Value - PERBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x41018070 - /// Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); - - /// address: 0x41018070 - /// Compare and Capture Buffer - pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Channel Compare/Capture Buffer Value - CCBUF: u4, - /// Dithering Buffer Cycle Number - DITHERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x41018070 - /// Compare and Capture Buffer - pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Channel Compare/Capture Buffer Value - CCBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x41018070 - /// Compare and Capture Buffer - pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Channel Compare/Capture Buffer Value - CCBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - }; - pub const TCC2 = struct { - pub const base_address = 0x42000c00; - - /// address: 0x42000c00 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Enhanced Resolution - RESOLUTION: u2, - reserved3: u1, - /// Prescaler - PRESCALER: u3, - /// Run in Standby - RUNSTDBY: u1, - /// Prescaler and Counter Synchronization Selection - PRESCSYNC: u2, - /// Auto Lock - ALOCK: u1, - /// Master Synchronization (only for TCC Slave Instance) - MSYNC: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA One-shot Trigger Mode - DMAOS: u1, - /// Capture Channel 0 Enable - CPTEN0: u1, - /// Capture Channel 1 Enable - CPTEN1: u1, - /// Capture Channel 2 Enable - CPTEN2: u1, - /// Capture Channel 3 Enable - CPTEN3: u1, - /// Capture Channel 4 Enable - CPTEN4: u1, - /// Capture Channel 5 Enable - CPTEN5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x42000c04 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x42000c05 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x42000c08 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Swrst Busy - SWRST: u1, - /// Enable Busy - ENABLE: u1, - /// Ctrlb Busy - CTRLB: u1, - /// Status Busy - STATUS: u1, - /// Count Busy - COUNT: u1, - /// Pattern Busy - PATT: u1, - /// Wave Busy - WAVE: u1, - /// Period Busy - PER: u1, - /// Compare Channel 0 Busy - CC0: u1, - /// Compare Channel 1 Busy - CC1: u1, - /// Compare Channel 2 Busy - CC2: u1, - /// Compare Channel 3 Busy - CC3: u1, - /// Compare Channel 4 Busy - CC4: u1, - /// Compare Channel 5 Busy - CC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x8); - - /// address: 0x42000c0c - /// Recoverable Fault A Configuration - pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault A Source - SRC: u2, - reserved0: u1, - /// Fault A Keeper - KEEP: u1, - /// Fault A Qualification - QUAL: u1, - /// Fault A Blanking Mode - BLANK: u2, - /// Fault A Restart - RESTART: u1, - /// Fault A Halt Mode - HALT: u2, - /// Fault A Capture Channel - CHSEL: u2, - /// Fault A Capture Action - CAPTURE: u3, - /// Fault A Blanking Prescaler - BLANKPRESC: u1, - /// Fault A Blanking Time - BLANKVAL: u8, - /// Fault A Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x42000c10 - /// Recoverable Fault B Configuration - pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault B Source - SRC: u2, - reserved0: u1, - /// Fault B Keeper - KEEP: u1, - /// Fault B Qualification - QUAL: u1, - /// Fault B Blanking Mode - BLANK: u2, - /// Fault B Restart - RESTART: u1, - /// Fault B Halt Mode - HALT: u2, - /// Fault B Capture Channel - CHSEL: u2, - /// Fault B Capture Action - CAPTURE: u3, - /// Fault B Blanking Prescaler - BLANKPRESC: u1, - /// Fault B Blanking Time - BLANKVAL: u8, - /// Fault B Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x42000c14 - /// Waveform Extension Configuration - pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Output Matrix - OTMX: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Dead-time Insertion Generator 0 Enable - DTIEN0: u1, - /// Dead-time Insertion Generator 1 Enable - DTIEN1: u1, - /// Dead-time Insertion Generator 2 Enable - DTIEN2: u1, - /// Dead-time Insertion Generator 3 Enable - DTIEN3: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Dead-time Low Side Outputs Value - DTLS: u8, - /// Dead-time High Side Outputs Value - DTHS: u8, - }), base_address + 0x14); - - /// address: 0x42000c18 - /// Driver Control - pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-Recoverable State 0 Output Enable - NRE0: u1, - /// Non-Recoverable State 1 Output Enable - NRE1: u1, - /// Non-Recoverable State 2 Output Enable - NRE2: u1, - /// Non-Recoverable State 3 Output Enable - NRE3: u1, - /// Non-Recoverable State 4 Output Enable - NRE4: u1, - /// Non-Recoverable State 5 Output Enable - NRE5: u1, - /// Non-Recoverable State 6 Output Enable - NRE6: u1, - /// Non-Recoverable State 7 Output Enable - NRE7: u1, - /// Non-Recoverable State 0 Output Value - NRV0: u1, - /// Non-Recoverable State 1 Output Value - NRV1: u1, - /// Non-Recoverable State 2 Output Value - NRV2: u1, - /// Non-Recoverable State 3 Output Value - NRV3: u1, - /// Non-Recoverable State 4 Output Value - NRV4: u1, - /// Non-Recoverable State 5 Output Value - NRV5: u1, - /// Non-Recoverable State 6 Output Value - NRV6: u1, - /// Non-Recoverable State 7 Output Value - NRV7: u1, - /// Output Waveform 0 Inversion - INVEN0: u1, - /// Output Waveform 1 Inversion - INVEN1: u1, - /// Output Waveform 2 Inversion - INVEN2: u1, - /// Output Waveform 3 Inversion - INVEN3: u1, - /// Output Waveform 4 Inversion - INVEN4: u1, - /// Output Waveform 5 Inversion - INVEN5: u1, - /// Output Waveform 6 Inversion - INVEN6: u1, - /// Output Waveform 7 Inversion - INVEN7: u1, - /// Non-Recoverable Fault Input 0 Filter Value - FILTERVAL0: u4, - /// Non-Recoverable Fault Input 1 Filter Value - FILTERVAL1: u4, - }), base_address + 0x18); - - /// address: 0x42000c1e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Running Mode - DBGRUN: u1, - reserved0: u1, - /// Fault Detection on Debug Break Detection - FDDBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1e); - - /// address: 0x42000c20 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer/counter Input Event0 Action - EVACT0: u3, - /// Timer/counter Input Event1 Action - EVACT1: u3, - /// Timer/counter Output Event Mode - CNTSEL: u2, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Retrigger Output Event Enable - TRGEO: u1, - /// Timer/counter Output Event Enable - CNTEO: u1, - reserved0: u1, - /// Inverted Event 0 Input Enable - TCINV0: u1, - /// Inverted Event 1 Input Enable - TCINV1: u1, - /// Timer/counter Event 0 Input Enable - TCEI0: u1, - /// Timer/counter Event 1 Input Enable - TCEI1: u1, - /// Match or Capture Channel 0 Event Input Enable - MCEI0: u1, - /// Match or Capture Channel 1 Event Input Enable - MCEI1: u1, - /// Match or Capture Channel 2 Event Input Enable - MCEI2: u1, - /// Match or Capture Channel 3 Event Input Enable - MCEI3: u1, - /// Match or Capture Channel 4 Event Input Enable - MCEI4: u1, - /// Match or Capture Channel 5 Event Input Enable - MCEI5: u1, - reserved1: u1, - reserved2: u1, - /// Match or Capture Channel 0 Event Output Enable - MCEO0: u1, - /// Match or Capture Channel 1 Event Output Enable - MCEO1: u1, - /// Match or Capture Channel 2 Event Output Enable - MCEO2: u1, - /// Match or Capture Channel 3 Event Output Enable - MCEO3: u1, - /// Match or Capture Channel 4 Event Output Enable - MCEO4: u1, - /// Match or Capture Channel 5 Event Output Enable - MCEO5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x42000c24 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x24); - - /// address: 0x42000c28 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x28); - - /// address: 0x42000c2c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow - OVF: u1, - /// Retrigger - TRG: u1, - /// Counter - CNT: u1, - /// Error - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault - UFS: u1, - /// Non-Recoverable Debug Fault - DFS: u1, - /// Recoverable Fault A - FAULTA: u1, - /// Recoverable Fault B - FAULTB: u1, - /// Non-Recoverable Fault 0 - FAULT0: u1, - /// Non-Recoverable Fault 1 - FAULT1: u1, - /// Match or Capture 0 - MC0: u1, - /// Match or Capture 1 - MC1: u1, - /// Match or Capture 2 - MC2: u1, - /// Match or Capture 3 - MC3: u1, - /// Match or Capture 4 - MC4: u1, - /// Match or Capture 5 - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x2c); - - /// address: 0x42000c30 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop - STOP: u1, - /// Ramp - IDX: u1, - /// Non-recoverable Update Fault State - UFS: u1, - /// Non-Recoverable Debug Fault State - DFS: u1, - /// Slave - SLAVE: u1, - /// Pattern Buffer Valid - PATTBUFV: u1, - reserved0: u1, - /// Period Buffer Valid - PERBUFV: u1, - /// Recoverable Fault A Input - FAULTAIN: u1, - /// Recoverable Fault B Input - FAULTBIN: u1, - /// Non-Recoverable Fault0 Input - FAULT0IN: u1, - /// Non-Recoverable Fault1 Input - FAULT1IN: u1, - /// Recoverable Fault A State - FAULTA: u1, - /// Recoverable Fault B State - FAULTB: u1, - /// Non-Recoverable Fault 0 State - FAULT0: u1, - /// Non-Recoverable Fault 1 State - FAULT1: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - /// Compare Channel 2 Buffer Valid - CCBUFV2: u1, - /// Compare Channel 3 Buffer Valid - CCBUFV3: u1, - /// Compare Channel 4 Buffer Valid - CCBUFV4: u1, - /// Compare Channel 5 Buffer Valid - CCBUFV5: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Value - CMP0: u1, - /// Compare Channel 1 Value - CMP1: u1, - /// Compare Channel 2 Value - CMP2: u1, - /// Compare Channel 3 Value - CMP3: u1, - /// Compare Channel 4 Value - CMP4: u1, - /// Compare Channel 5 Value - CMP5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x42000c34 - /// Count - pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); - - /// address: 0x42000c34 - /// Count - pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Counter Value - COUNT: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42000c34 - /// Count - pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Counter Value - COUNT: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42000c34 - /// Count - pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Counter Value - COUNT: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42000c38 - /// Pattern - pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable - PGE0: u1, - /// Pattern Generator 1 Output Enable - PGE1: u1, - /// Pattern Generator 2 Output Enable - PGE2: u1, - /// Pattern Generator 3 Output Enable - PGE3: u1, - /// Pattern Generator 4 Output Enable - PGE4: u1, - /// Pattern Generator 5 Output Enable - PGE5: u1, - /// Pattern Generator 6 Output Enable - PGE6: u1, - /// Pattern Generator 7 Output Enable - PGE7: u1, - /// Pattern Generator 0 Output Value - PGV0: u1, - /// Pattern Generator 1 Output Value - PGV1: u1, - /// Pattern Generator 2 Output Value - PGV2: u1, - /// Pattern Generator 3 Output Value - PGV3: u1, - /// Pattern Generator 4 Output Value - PGV4: u1, - /// Pattern Generator 5 Output Value - PGV5: u1, - /// Pattern Generator 6 Output Value - PGV6: u1, - /// Pattern Generator 7 Output Value - PGV7: u1, - }), base_address + 0x38); - - /// address: 0x42000c3c - /// Waveform Control - pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Waveform Generation - WAVEGEN: u3, - reserved0: u1, - /// Ramp Mode - RAMP: u2, - reserved1: u1, - /// Circular period Enable - CIPEREN: u1, - /// Circular Channel 0 Enable - CICCEN0: u1, - /// Circular Channel 1 Enable - CICCEN1: u1, - /// Circular Channel 2 Enable - CICCEN2: u1, - /// Circular Channel 3 Enable - CICCEN3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Channel 0 Polarity - POL0: u1, - /// Channel 1 Polarity - POL1: u1, - /// Channel 2 Polarity - POL2: u1, - /// Channel 3 Polarity - POL3: u1, - /// Channel 4 Polarity - POL4: u1, - /// Channel 5 Polarity - POL5: u1, - reserved6: u1, - reserved7: u1, - /// Swap DTI Output Pair 0 - SWAP0: u1, - /// Swap DTI Output Pair 1 - SWAP1: u1, - /// Swap DTI Output Pair 2 - SWAP2: u1, - /// Swap DTI Output Pair 3 - SWAP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3c); - - /// address: 0x42000c40 - /// Period - pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); - - /// address: 0x42000c40 - /// Period - pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Period Value - PER: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42000c40 - /// Period - pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Period Value - PER: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42000c40 - /// Period - pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Period Value - PER: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42000c44 - /// Compare and Capture - pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); - - /// address: 0x42000c44 - /// Compare and Capture - pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Channel Compare/Capture Value - CC: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42000c44 - /// Compare and Capture - pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Channel Compare/Capture Value - CC: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42000c44 - /// Compare and Capture - pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Channel Compare/Capture Value - CC: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42000c64 - /// Pattern Buffer - pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable Buffer - PGEB0: u1, - /// Pattern Generator 1 Output Enable Buffer - PGEB1: u1, - /// Pattern Generator 2 Output Enable Buffer - PGEB2: u1, - /// Pattern Generator 3 Output Enable Buffer - PGEB3: u1, - /// Pattern Generator 4 Output Enable Buffer - PGEB4: u1, - /// Pattern Generator 5 Output Enable Buffer - PGEB5: u1, - /// Pattern Generator 6 Output Enable Buffer - PGEB6: u1, - /// Pattern Generator 7 Output Enable Buffer - PGEB7: u1, - /// Pattern Generator 0 Output Enable - PGVB0: u1, - /// Pattern Generator 1 Output Enable - PGVB1: u1, - /// Pattern Generator 2 Output Enable - PGVB2: u1, - /// Pattern Generator 3 Output Enable - PGVB3: u1, - /// Pattern Generator 4 Output Enable - PGVB4: u1, - /// Pattern Generator 5 Output Enable - PGVB5: u1, - /// Pattern Generator 6 Output Enable - PGVB6: u1, - /// Pattern Generator 7 Output Enable - PGVB7: u1, - }), base_address + 0x64); - - /// address: 0x42000c6c - /// Period Buffer - pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); - - /// address: 0x42000c6c - /// Period Buffer - pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u4, - /// Period Buffer Value - PERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x42000c6c - /// Period Buffer - pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Period Buffer Value - PERBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x42000c6c - /// Period Buffer - pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Period Buffer Value - PERBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x42000c70 - /// Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); - - /// address: 0x42000c70 - /// Compare and Capture Buffer - pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Channel Compare/Capture Buffer Value - CCBUF: u4, - /// Dithering Buffer Cycle Number - DITHERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x42000c70 - /// Compare and Capture Buffer - pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Channel Compare/Capture Buffer Value - CCBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x42000c70 - /// Compare and Capture Buffer - pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Channel Compare/Capture Buffer Value - CCBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - }; - pub const TCC3 = struct { - pub const base_address = 0x42001000; - - /// address: 0x42001000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Enhanced Resolution - RESOLUTION: u2, - reserved3: u1, - /// Prescaler - PRESCALER: u3, - /// Run in Standby - RUNSTDBY: u1, - /// Prescaler and Counter Synchronization Selection - PRESCSYNC: u2, - /// Auto Lock - ALOCK: u1, - /// Master Synchronization (only for TCC Slave Instance) - MSYNC: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA One-shot Trigger Mode - DMAOS: u1, - /// Capture Channel 0 Enable - CPTEN0: u1, - /// Capture Channel 1 Enable - CPTEN1: u1, - /// Capture Channel 2 Enable - CPTEN2: u1, - /// Capture Channel 3 Enable - CPTEN3: u1, - /// Capture Channel 4 Enable - CPTEN4: u1, - /// Capture Channel 5 Enable - CPTEN5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x42001004 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x42001005 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x42001008 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Swrst Busy - SWRST: u1, - /// Enable Busy - ENABLE: u1, - /// Ctrlb Busy - CTRLB: u1, - /// Status Busy - STATUS: u1, - /// Count Busy - COUNT: u1, - /// Pattern Busy - PATT: u1, - /// Wave Busy - WAVE: u1, - /// Period Busy - PER: u1, - /// Compare Channel 0 Busy - CC0: u1, - /// Compare Channel 1 Busy - CC1: u1, - /// Compare Channel 2 Busy - CC2: u1, - /// Compare Channel 3 Busy - CC3: u1, - /// Compare Channel 4 Busy - CC4: u1, - /// Compare Channel 5 Busy - CC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x8); - - /// address: 0x4200100c - /// Recoverable Fault A Configuration - pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault A Source - SRC: u2, - reserved0: u1, - /// Fault A Keeper - KEEP: u1, - /// Fault A Qualification - QUAL: u1, - /// Fault A Blanking Mode - BLANK: u2, - /// Fault A Restart - RESTART: u1, - /// Fault A Halt Mode - HALT: u2, - /// Fault A Capture Channel - CHSEL: u2, - /// Fault A Capture Action - CAPTURE: u3, - /// Fault A Blanking Prescaler - BLANKPRESC: u1, - /// Fault A Blanking Time - BLANKVAL: u8, - /// Fault A Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x42001010 - /// Recoverable Fault B Configuration - pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault B Source - SRC: u2, - reserved0: u1, - /// Fault B Keeper - KEEP: u1, - /// Fault B Qualification - QUAL: u1, - /// Fault B Blanking Mode - BLANK: u2, - /// Fault B Restart - RESTART: u1, - /// Fault B Halt Mode - HALT: u2, - /// Fault B Capture Channel - CHSEL: u2, - /// Fault B Capture Action - CAPTURE: u3, - /// Fault B Blanking Prescaler - BLANKPRESC: u1, - /// Fault B Blanking Time - BLANKVAL: u8, - /// Fault B Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x42001014 - /// Waveform Extension Configuration - pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Output Matrix - OTMX: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Dead-time Insertion Generator 0 Enable - DTIEN0: u1, - /// Dead-time Insertion Generator 1 Enable - DTIEN1: u1, - /// Dead-time Insertion Generator 2 Enable - DTIEN2: u1, - /// Dead-time Insertion Generator 3 Enable - DTIEN3: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Dead-time Low Side Outputs Value - DTLS: u8, - /// Dead-time High Side Outputs Value - DTHS: u8, - }), base_address + 0x14); - - /// address: 0x42001018 - /// Driver Control - pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-Recoverable State 0 Output Enable - NRE0: u1, - /// Non-Recoverable State 1 Output Enable - NRE1: u1, - /// Non-Recoverable State 2 Output Enable - NRE2: u1, - /// Non-Recoverable State 3 Output Enable - NRE3: u1, - /// Non-Recoverable State 4 Output Enable - NRE4: u1, - /// Non-Recoverable State 5 Output Enable - NRE5: u1, - /// Non-Recoverable State 6 Output Enable - NRE6: u1, - /// Non-Recoverable State 7 Output Enable - NRE7: u1, - /// Non-Recoverable State 0 Output Value - NRV0: u1, - /// Non-Recoverable State 1 Output Value - NRV1: u1, - /// Non-Recoverable State 2 Output Value - NRV2: u1, - /// Non-Recoverable State 3 Output Value - NRV3: u1, - /// Non-Recoverable State 4 Output Value - NRV4: u1, - /// Non-Recoverable State 5 Output Value - NRV5: u1, - /// Non-Recoverable State 6 Output Value - NRV6: u1, - /// Non-Recoverable State 7 Output Value - NRV7: u1, - /// Output Waveform 0 Inversion - INVEN0: u1, - /// Output Waveform 1 Inversion - INVEN1: u1, - /// Output Waveform 2 Inversion - INVEN2: u1, - /// Output Waveform 3 Inversion - INVEN3: u1, - /// Output Waveform 4 Inversion - INVEN4: u1, - /// Output Waveform 5 Inversion - INVEN5: u1, - /// Output Waveform 6 Inversion - INVEN6: u1, - /// Output Waveform 7 Inversion - INVEN7: u1, - /// Non-Recoverable Fault Input 0 Filter Value - FILTERVAL0: u4, - /// Non-Recoverable Fault Input 1 Filter Value - FILTERVAL1: u4, - }), base_address + 0x18); - - /// address: 0x4200101e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Running Mode - DBGRUN: u1, - reserved0: u1, - /// Fault Detection on Debug Break Detection - FDDBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1e); - - /// address: 0x42001020 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer/counter Input Event0 Action - EVACT0: u3, - /// Timer/counter Input Event1 Action - EVACT1: u3, - /// Timer/counter Output Event Mode - CNTSEL: u2, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Retrigger Output Event Enable - TRGEO: u1, - /// Timer/counter Output Event Enable - CNTEO: u1, - reserved0: u1, - /// Inverted Event 0 Input Enable - TCINV0: u1, - /// Inverted Event 1 Input Enable - TCINV1: u1, - /// Timer/counter Event 0 Input Enable - TCEI0: u1, - /// Timer/counter Event 1 Input Enable - TCEI1: u1, - /// Match or Capture Channel 0 Event Input Enable - MCEI0: u1, - /// Match or Capture Channel 1 Event Input Enable - MCEI1: u1, - /// Match or Capture Channel 2 Event Input Enable - MCEI2: u1, - /// Match or Capture Channel 3 Event Input Enable - MCEI3: u1, - /// Match or Capture Channel 4 Event Input Enable - MCEI4: u1, - /// Match or Capture Channel 5 Event Input Enable - MCEI5: u1, - reserved1: u1, - reserved2: u1, - /// Match or Capture Channel 0 Event Output Enable - MCEO0: u1, - /// Match or Capture Channel 1 Event Output Enable - MCEO1: u1, - /// Match or Capture Channel 2 Event Output Enable - MCEO2: u1, - /// Match or Capture Channel 3 Event Output Enable - MCEO3: u1, - /// Match or Capture Channel 4 Event Output Enable - MCEO4: u1, - /// Match or Capture Channel 5 Event Output Enable - MCEO5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x42001024 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x24); - - /// address: 0x42001028 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x28); - - /// address: 0x4200102c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow - OVF: u1, - /// Retrigger - TRG: u1, - /// Counter - CNT: u1, - /// Error - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault - UFS: u1, - /// Non-Recoverable Debug Fault - DFS: u1, - /// Recoverable Fault A - FAULTA: u1, - /// Recoverable Fault B - FAULTB: u1, - /// Non-Recoverable Fault 0 - FAULT0: u1, - /// Non-Recoverable Fault 1 - FAULT1: u1, - /// Match or Capture 0 - MC0: u1, - /// Match or Capture 1 - MC1: u1, - /// Match or Capture 2 - MC2: u1, - /// Match or Capture 3 - MC3: u1, - /// Match or Capture 4 - MC4: u1, - /// Match or Capture 5 - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x2c); - - /// address: 0x42001030 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop - STOP: u1, - /// Ramp - IDX: u1, - /// Non-recoverable Update Fault State - UFS: u1, - /// Non-Recoverable Debug Fault State - DFS: u1, - /// Slave - SLAVE: u1, - /// Pattern Buffer Valid - PATTBUFV: u1, - reserved0: u1, - /// Period Buffer Valid - PERBUFV: u1, - /// Recoverable Fault A Input - FAULTAIN: u1, - /// Recoverable Fault B Input - FAULTBIN: u1, - /// Non-Recoverable Fault0 Input - FAULT0IN: u1, - /// Non-Recoverable Fault1 Input - FAULT1IN: u1, - /// Recoverable Fault A State - FAULTA: u1, - /// Recoverable Fault B State - FAULTB: u1, - /// Non-Recoverable Fault 0 State - FAULT0: u1, - /// Non-Recoverable Fault 1 State - FAULT1: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - /// Compare Channel 2 Buffer Valid - CCBUFV2: u1, - /// Compare Channel 3 Buffer Valid - CCBUFV3: u1, - /// Compare Channel 4 Buffer Valid - CCBUFV4: u1, - /// Compare Channel 5 Buffer Valid - CCBUFV5: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Value - CMP0: u1, - /// Compare Channel 1 Value - CMP1: u1, - /// Compare Channel 2 Value - CMP2: u1, - /// Compare Channel 3 Value - CMP3: u1, - /// Compare Channel 4 Value - CMP4: u1, - /// Compare Channel 5 Value - CMP5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x42001034 - /// Count - pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); - - /// address: 0x42001034 - /// Count - pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Counter Value - COUNT: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42001034 - /// Count - pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Counter Value - COUNT: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42001034 - /// Count - pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Counter Value - COUNT: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x42001038 - /// Pattern - pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable - PGE0: u1, - /// Pattern Generator 1 Output Enable - PGE1: u1, - /// Pattern Generator 2 Output Enable - PGE2: u1, - /// Pattern Generator 3 Output Enable - PGE3: u1, - /// Pattern Generator 4 Output Enable - PGE4: u1, - /// Pattern Generator 5 Output Enable - PGE5: u1, - /// Pattern Generator 6 Output Enable - PGE6: u1, - /// Pattern Generator 7 Output Enable - PGE7: u1, - /// Pattern Generator 0 Output Value - PGV0: u1, - /// Pattern Generator 1 Output Value - PGV1: u1, - /// Pattern Generator 2 Output Value - PGV2: u1, - /// Pattern Generator 3 Output Value - PGV3: u1, - /// Pattern Generator 4 Output Value - PGV4: u1, - /// Pattern Generator 5 Output Value - PGV5: u1, - /// Pattern Generator 6 Output Value - PGV6: u1, - /// Pattern Generator 7 Output Value - PGV7: u1, - }), base_address + 0x38); - - /// address: 0x4200103c - /// Waveform Control - pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Waveform Generation - WAVEGEN: u3, - reserved0: u1, - /// Ramp Mode - RAMP: u2, - reserved1: u1, - /// Circular period Enable - CIPEREN: u1, - /// Circular Channel 0 Enable - CICCEN0: u1, - /// Circular Channel 1 Enable - CICCEN1: u1, - /// Circular Channel 2 Enable - CICCEN2: u1, - /// Circular Channel 3 Enable - CICCEN3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Channel 0 Polarity - POL0: u1, - /// Channel 1 Polarity - POL1: u1, - /// Channel 2 Polarity - POL2: u1, - /// Channel 3 Polarity - POL3: u1, - /// Channel 4 Polarity - POL4: u1, - /// Channel 5 Polarity - POL5: u1, - reserved6: u1, - reserved7: u1, - /// Swap DTI Output Pair 0 - SWAP0: u1, - /// Swap DTI Output Pair 1 - SWAP1: u1, - /// Swap DTI Output Pair 2 - SWAP2: u1, - /// Swap DTI Output Pair 3 - SWAP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3c); - - /// address: 0x42001040 - /// Period - pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); - - /// address: 0x42001040 - /// Period - pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Period Value - PER: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42001040 - /// Period - pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Period Value - PER: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42001040 - /// Period - pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Period Value - PER: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x42001044 - /// Compare and Capture - pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); - - /// address: 0x42001044 - /// Compare and Capture - pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Channel Compare/Capture Value - CC: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42001044 - /// Compare and Capture - pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Channel Compare/Capture Value - CC: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42001044 - /// Compare and Capture - pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Channel Compare/Capture Value - CC: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x42001064 - /// Pattern Buffer - pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable Buffer - PGEB0: u1, - /// Pattern Generator 1 Output Enable Buffer - PGEB1: u1, - /// Pattern Generator 2 Output Enable Buffer - PGEB2: u1, - /// Pattern Generator 3 Output Enable Buffer - PGEB3: u1, - /// Pattern Generator 4 Output Enable Buffer - PGEB4: u1, - /// Pattern Generator 5 Output Enable Buffer - PGEB5: u1, - /// Pattern Generator 6 Output Enable Buffer - PGEB6: u1, - /// Pattern Generator 7 Output Enable Buffer - PGEB7: u1, - /// Pattern Generator 0 Output Enable - PGVB0: u1, - /// Pattern Generator 1 Output Enable - PGVB1: u1, - /// Pattern Generator 2 Output Enable - PGVB2: u1, - /// Pattern Generator 3 Output Enable - PGVB3: u1, - /// Pattern Generator 4 Output Enable - PGVB4: u1, - /// Pattern Generator 5 Output Enable - PGVB5: u1, - /// Pattern Generator 6 Output Enable - PGVB6: u1, - /// Pattern Generator 7 Output Enable - PGVB7: u1, - }), base_address + 0x64); - - /// address: 0x4200106c - /// Period Buffer - pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); - - /// address: 0x4200106c - /// Period Buffer - pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u4, - /// Period Buffer Value - PERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4200106c - /// Period Buffer - pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Period Buffer Value - PERBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4200106c - /// Period Buffer - pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Period Buffer Value - PERBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x42001070 - /// Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); - - /// address: 0x42001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Channel Compare/Capture Buffer Value - CCBUF: u4, - /// Dithering Buffer Cycle Number - DITHERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x42001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Channel Compare/Capture Buffer Value - CCBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x42001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Channel Compare/Capture Buffer Value - CCBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - }; - pub const TCC4 = struct { - pub const base_address = 0x43001000; - - /// address: 0x43001000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Enhanced Resolution - RESOLUTION: u2, - reserved3: u1, - /// Prescaler - PRESCALER: u3, - /// Run in Standby - RUNSTDBY: u1, - /// Prescaler and Counter Synchronization Selection - PRESCSYNC: u2, - /// Auto Lock - ALOCK: u1, - /// Master Synchronization (only for TCC Slave Instance) - MSYNC: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA One-shot Trigger Mode - DMAOS: u1, - /// Capture Channel 0 Enable - CPTEN0: u1, - /// Capture Channel 1 Enable - CPTEN1: u1, - /// Capture Channel 2 Enable - CPTEN2: u1, - /// Capture Channel 3 Enable - CPTEN3: u1, - /// Capture Channel 4 Enable - CPTEN4: u1, - /// Capture Channel 5 Enable - CPTEN5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x43001004 - /// Control B Clear - pub const CTRLBCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x4); - - /// address: 0x43001005 - /// Control B Set - pub const CTRLBSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Counter Direction - DIR: u1, - /// Lock Update - LUPD: u1, - /// One-Shot - ONESHOT: u1, - /// Ramp Index Command - IDXCMD: u2, - /// TCC Command - CMD: u3, - }), base_address + 0x5); - - /// address: 0x43001008 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - /// Swrst Busy - SWRST: u1, - /// Enable Busy - ENABLE: u1, - /// Ctrlb Busy - CTRLB: u1, - /// Status Busy - STATUS: u1, - /// Count Busy - COUNT: u1, - /// Pattern Busy - PATT: u1, - /// Wave Busy - WAVE: u1, - /// Period Busy - PER: u1, - /// Compare Channel 0 Busy - CC0: u1, - /// Compare Channel 1 Busy - CC1: u1, - /// Compare Channel 2 Busy - CC2: u1, - /// Compare Channel 3 Busy - CC3: u1, - /// Compare Channel 4 Busy - CC4: u1, - /// Compare Channel 5 Busy - CC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x8); - - /// address: 0x4300100c - /// Recoverable Fault A Configuration - pub const FCTRLA = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault A Source - SRC: u2, - reserved0: u1, - /// Fault A Keeper - KEEP: u1, - /// Fault A Qualification - QUAL: u1, - /// Fault A Blanking Mode - BLANK: u2, - /// Fault A Restart - RESTART: u1, - /// Fault A Halt Mode - HALT: u2, - /// Fault A Capture Channel - CHSEL: u2, - /// Fault A Capture Action - CAPTURE: u3, - /// Fault A Blanking Prescaler - BLANKPRESC: u1, - /// Fault A Blanking Time - BLANKVAL: u8, - /// Fault A Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x43001010 - /// Recoverable Fault B Configuration - pub const FCTRLB = @intToPtr(*volatile Mmio(32, packed struct { - /// Fault B Source - SRC: u2, - reserved0: u1, - /// Fault B Keeper - KEEP: u1, - /// Fault B Qualification - QUAL: u1, - /// Fault B Blanking Mode - BLANK: u2, - /// Fault B Restart - RESTART: u1, - /// Fault B Halt Mode - HALT: u2, - /// Fault B Capture Channel - CHSEL: u2, - /// Fault B Capture Action - CAPTURE: u3, - /// Fault B Blanking Prescaler - BLANKPRESC: u1, - /// Fault B Blanking Time - BLANKVAL: u8, - /// Fault B Filter Value - FILTERVAL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x43001014 - /// Waveform Extension Configuration - pub const WEXCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Output Matrix - OTMX: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Dead-time Insertion Generator 0 Enable - DTIEN0: u1, - /// Dead-time Insertion Generator 1 Enable - DTIEN1: u1, - /// Dead-time Insertion Generator 2 Enable - DTIEN2: u1, - /// Dead-time Insertion Generator 3 Enable - DTIEN3: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Dead-time Low Side Outputs Value - DTLS: u8, - /// Dead-time High Side Outputs Value - DTHS: u8, - }), base_address + 0x14); - - /// address: 0x43001018 - /// Driver Control - pub const DRVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-Recoverable State 0 Output Enable - NRE0: u1, - /// Non-Recoverable State 1 Output Enable - NRE1: u1, - /// Non-Recoverable State 2 Output Enable - NRE2: u1, - /// Non-Recoverable State 3 Output Enable - NRE3: u1, - /// Non-Recoverable State 4 Output Enable - NRE4: u1, - /// Non-Recoverable State 5 Output Enable - NRE5: u1, - /// Non-Recoverable State 6 Output Enable - NRE6: u1, - /// Non-Recoverable State 7 Output Enable - NRE7: u1, - /// Non-Recoverable State 0 Output Value - NRV0: u1, - /// Non-Recoverable State 1 Output Value - NRV1: u1, - /// Non-Recoverable State 2 Output Value - NRV2: u1, - /// Non-Recoverable State 3 Output Value - NRV3: u1, - /// Non-Recoverable State 4 Output Value - NRV4: u1, - /// Non-Recoverable State 5 Output Value - NRV5: u1, - /// Non-Recoverable State 6 Output Value - NRV6: u1, - /// Non-Recoverable State 7 Output Value - NRV7: u1, - /// Output Waveform 0 Inversion - INVEN0: u1, - /// Output Waveform 1 Inversion - INVEN1: u1, - /// Output Waveform 2 Inversion - INVEN2: u1, - /// Output Waveform 3 Inversion - INVEN3: u1, - /// Output Waveform 4 Inversion - INVEN4: u1, - /// Output Waveform 5 Inversion - INVEN5: u1, - /// Output Waveform 6 Inversion - INVEN6: u1, - /// Output Waveform 7 Inversion - INVEN7: u1, - /// Non-Recoverable Fault Input 0 Filter Value - FILTERVAL0: u4, - /// Non-Recoverable Fault Input 1 Filter Value - FILTERVAL1: u4, - }), base_address + 0x18); - - /// address: 0x4300101e - /// Debug Control - pub const DBGCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Debug Running Mode - DBGRUN: u1, - reserved0: u1, - /// Fault Detection on Debug Break Detection - FDDBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x1e); - - /// address: 0x43001020 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer/counter Input Event0 Action - EVACT0: u3, - /// Timer/counter Input Event1 Action - EVACT1: u3, - /// Timer/counter Output Event Mode - CNTSEL: u2, - /// Overflow/Underflow Output Event Enable - OVFEO: u1, - /// Retrigger Output Event Enable - TRGEO: u1, - /// Timer/counter Output Event Enable - CNTEO: u1, - reserved0: u1, - /// Inverted Event 0 Input Enable - TCINV0: u1, - /// Inverted Event 1 Input Enable - TCINV1: u1, - /// Timer/counter Event 0 Input Enable - TCEI0: u1, - /// Timer/counter Event 1 Input Enable - TCEI1: u1, - /// Match or Capture Channel 0 Event Input Enable - MCEI0: u1, - /// Match or Capture Channel 1 Event Input Enable - MCEI1: u1, - /// Match or Capture Channel 2 Event Input Enable - MCEI2: u1, - /// Match or Capture Channel 3 Event Input Enable - MCEI3: u1, - /// Match or Capture Channel 4 Event Input Enable - MCEI4: u1, - /// Match or Capture Channel 5 Event Input Enable - MCEI5: u1, - reserved1: u1, - reserved2: u1, - /// Match or Capture Channel 0 Event Output Enable - MCEO0: u1, - /// Match or Capture Channel 1 Event Output Enable - MCEO1: u1, - /// Match or Capture Channel 2 Event Output Enable - MCEO2: u1, - /// Match or Capture Channel 3 Event Output Enable - MCEO3: u1, - /// Match or Capture Channel 4 Event Output Enable - MCEO4: u1, - /// Match or Capture Channel 5 Event Output Enable - MCEO5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x43001024 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x24); - - /// address: 0x43001028 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow Interrupt Enable - OVF: u1, - /// Retrigger Interrupt Enable - TRG: u1, - /// Counter Interrupt Enable - CNT: u1, - /// Error Interrupt Enable - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault Interrupt Enable - UFS: u1, - /// Non-Recoverable Debug Fault Interrupt Enable - DFS: u1, - /// Recoverable Fault A Interrupt Enable - FAULTA: u1, - /// Recoverable Fault B Interrupt Enable - FAULTB: u1, - /// Non-Recoverable Fault 0 Interrupt Enable - FAULT0: u1, - /// Non-Recoverable Fault 1 Interrupt Enable - FAULT1: u1, - /// Match or Capture Channel 0 Interrupt Enable - MC0: u1, - /// Match or Capture Channel 1 Interrupt Enable - MC1: u1, - /// Match or Capture Channel 2 Interrupt Enable - MC2: u1, - /// Match or Capture Channel 3 Interrupt Enable - MC3: u1, - /// Match or Capture Channel 4 Interrupt Enable - MC4: u1, - /// Match or Capture Channel 5 Interrupt Enable - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x28); - - /// address: 0x4300102c - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(32, packed struct { - /// Overflow - OVF: u1, - /// Retrigger - TRG: u1, - /// Counter - CNT: u1, - /// Error - ERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Non-Recoverable Update Fault - UFS: u1, - /// Non-Recoverable Debug Fault - DFS: u1, - /// Recoverable Fault A - FAULTA: u1, - /// Recoverable Fault B - FAULTB: u1, - /// Non-Recoverable Fault 0 - FAULT0: u1, - /// Non-Recoverable Fault 1 - FAULT1: u1, - /// Match or Capture 0 - MC0: u1, - /// Match or Capture 1 - MC1: u1, - /// Match or Capture 2 - MC2: u1, - /// Match or Capture 3 - MC3: u1, - /// Match or Capture 4 - MC4: u1, - /// Match or Capture 5 - MC5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x2c); - - /// address: 0x43001030 - /// Status - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop - STOP: u1, - /// Ramp - IDX: u1, - /// Non-recoverable Update Fault State - UFS: u1, - /// Non-Recoverable Debug Fault State - DFS: u1, - /// Slave - SLAVE: u1, - /// Pattern Buffer Valid - PATTBUFV: u1, - reserved0: u1, - /// Period Buffer Valid - PERBUFV: u1, - /// Recoverable Fault A Input - FAULTAIN: u1, - /// Recoverable Fault B Input - FAULTBIN: u1, - /// Non-Recoverable Fault0 Input - FAULT0IN: u1, - /// Non-Recoverable Fault1 Input - FAULT1IN: u1, - /// Recoverable Fault A State - FAULTA: u1, - /// Recoverable Fault B State - FAULTB: u1, - /// Non-Recoverable Fault 0 State - FAULT0: u1, - /// Non-Recoverable Fault 1 State - FAULT1: u1, - /// Compare Channel 0 Buffer Valid - CCBUFV0: u1, - /// Compare Channel 1 Buffer Valid - CCBUFV1: u1, - /// Compare Channel 2 Buffer Valid - CCBUFV2: u1, - /// Compare Channel 3 Buffer Valid - CCBUFV3: u1, - /// Compare Channel 4 Buffer Valid - CCBUFV4: u1, - /// Compare Channel 5 Buffer Valid - CCBUFV5: u1, - reserved1: u1, - reserved2: u1, - /// Compare Channel 0 Value - CMP0: u1, - /// Compare Channel 1 Value - CMP1: u1, - /// Compare Channel 2 Value - CMP2: u1, - /// Compare Channel 3 Value - CMP3: u1, - /// Compare Channel 4 Value - CMP4: u1, - /// Compare Channel 5 Value - CMP5: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x43001034 - /// Count - pub const COUNT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x34); - - /// address: 0x43001034 - /// Count - pub const COUNT_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Counter Value - COUNT: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x43001034 - /// Count - pub const COUNT_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Counter Value - COUNT: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x43001034 - /// Count - pub const COUNT_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Counter Value - COUNT: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x43001038 - /// Pattern - pub const PATT = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable - PGE0: u1, - /// Pattern Generator 1 Output Enable - PGE1: u1, - /// Pattern Generator 2 Output Enable - PGE2: u1, - /// Pattern Generator 3 Output Enable - PGE3: u1, - /// Pattern Generator 4 Output Enable - PGE4: u1, - /// Pattern Generator 5 Output Enable - PGE5: u1, - /// Pattern Generator 6 Output Enable - PGE6: u1, - /// Pattern Generator 7 Output Enable - PGE7: u1, - /// Pattern Generator 0 Output Value - PGV0: u1, - /// Pattern Generator 1 Output Value - PGV1: u1, - /// Pattern Generator 2 Output Value - PGV2: u1, - /// Pattern Generator 3 Output Value - PGV3: u1, - /// Pattern Generator 4 Output Value - PGV4: u1, - /// Pattern Generator 5 Output Value - PGV5: u1, - /// Pattern Generator 6 Output Value - PGV6: u1, - /// Pattern Generator 7 Output Value - PGV7: u1, - }), base_address + 0x38); - - /// address: 0x4300103c - /// Waveform Control - pub const WAVE = @intToPtr(*volatile Mmio(32, packed struct { - /// Waveform Generation - WAVEGEN: u3, - reserved0: u1, - /// Ramp Mode - RAMP: u2, - reserved1: u1, - /// Circular period Enable - CIPEREN: u1, - /// Circular Channel 0 Enable - CICCEN0: u1, - /// Circular Channel 1 Enable - CICCEN1: u1, - /// Circular Channel 2 Enable - CICCEN2: u1, - /// Circular Channel 3 Enable - CICCEN3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Channel 0 Polarity - POL0: u1, - /// Channel 1 Polarity - POL1: u1, - /// Channel 2 Polarity - POL2: u1, - /// Channel 3 Polarity - POL3: u1, - /// Channel 4 Polarity - POL4: u1, - /// Channel 5 Polarity - POL5: u1, - reserved6: u1, - reserved7: u1, - /// Swap DTI Output Pair 0 - SWAP0: u1, - /// Swap DTI Output Pair 1 - SWAP1: u1, - /// Swap DTI Output Pair 2 - SWAP2: u1, - /// Swap DTI Output Pair 3 - SWAP3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3c); - - /// address: 0x43001040 - /// Period - pub const PER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40); - - /// address: 0x43001040 - /// Period - pub const PER_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Period Value - PER: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x43001040 - /// Period - pub const PER_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Period Value - PER: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x43001040 - /// Period - pub const PER_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Period Value - PER: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x43001044 - /// Compare and Capture - pub const CC = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x44); - - /// address: 0x43001044 - /// Compare and Capture - pub const CC_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u4, - /// Channel Compare/Capture Value - CC: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x43001044 - /// Compare and Capture - pub const CC_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u5, - /// Channel Compare/Capture Value - CC: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x43001044 - /// Compare and Capture - pub const CC_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Cycle Number - DITHER: u6, - /// Channel Compare/Capture Value - CC: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x44); - - /// address: 0x43001064 - /// Pattern Buffer - pub const PATTBUF = @intToPtr(*volatile Mmio(16, packed struct { - /// Pattern Generator 0 Output Enable Buffer - PGEB0: u1, - /// Pattern Generator 1 Output Enable Buffer - PGEB1: u1, - /// Pattern Generator 2 Output Enable Buffer - PGEB2: u1, - /// Pattern Generator 3 Output Enable Buffer - PGEB3: u1, - /// Pattern Generator 4 Output Enable Buffer - PGEB4: u1, - /// Pattern Generator 5 Output Enable Buffer - PGEB5: u1, - /// Pattern Generator 6 Output Enable Buffer - PGEB6: u1, - /// Pattern Generator 7 Output Enable Buffer - PGEB7: u1, - /// Pattern Generator 0 Output Enable - PGVB0: u1, - /// Pattern Generator 1 Output Enable - PGVB1: u1, - /// Pattern Generator 2 Output Enable - PGVB2: u1, - /// Pattern Generator 3 Output Enable - PGVB3: u1, - /// Pattern Generator 4 Output Enable - PGVB4: u1, - /// Pattern Generator 5 Output Enable - PGVB5: u1, - /// Pattern Generator 6 Output Enable - PGVB6: u1, - /// Pattern Generator 7 Output Enable - PGVB7: u1, - }), base_address + 0x64); - - /// address: 0x4300106c - /// Period Buffer - pub const PERBUF = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x6c); - - /// address: 0x4300106c - /// Period Buffer - pub const PERBUF_DITH4_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u4, - /// Period Buffer Value - PERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4300106c - /// Period Buffer - pub const PERBUF_DITH5_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Period Buffer Value - PERBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x4300106c - /// Period Buffer - pub const PERBUF_DITH6_MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Period Buffer Value - PERBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x6c); - - /// address: 0x43001070 - /// Compare and Capture Buffer - pub const CCBUF = @intToPtr(*volatile [6]MmioInt(32, u24), base_address + 0x70); - - /// address: 0x43001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH4_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Channel Compare/Capture Buffer Value - CCBUF: u4, - /// Dithering Buffer Cycle Number - DITHERBUF: u20, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x43001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH5_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u5, - /// Channel Compare/Capture Buffer Value - CCBUF: u19, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - - /// address: 0x43001070 - /// Compare and Capture Buffer - pub const CCBUF_DITH6_MODE = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Dithering Buffer Cycle Number - DITHERBUF: u6, - /// Channel Compare/Capture Buffer Value - CCBUF: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x70); - }; - - /// True Random Generator - pub const TRNG = struct { - pub const base_address = 0x42002800; - pub const version = "U22421.1.0"; - - /// address: 0x42002800 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Run in Standby - RUNSTDBY: u1, - padding0: u1, - }), base_address + 0x0); - - /// address: 0x42002804 - /// Event Control - pub const EVCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Ready Event Output - DATARDYEO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x4); - - /// address: 0x42002808 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Ready Interrupt Enable - DATARDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x42002809 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Ready Interrupt Enable - DATARDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x9); - - /// address: 0x4200280a - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Data Ready Interrupt Flag - DATARDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xa); - - /// address: 0x42002820 - /// Output Data - pub const DATA = @intToPtr(*volatile u32, base_address + 0x20); - }; - - /// Universal Serial Bus - pub const USB = struct { - pub const base_address = 0x41000000; - pub const version = "U22221.2.0"; - - /// USB is Device - pub const DEVICE = struct { - /// address: 0x41000000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Run in Standby Mode - RUNSTDBY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Operating Mode - MODE: u1, - }), base_address + 0x0); - - /// address: 0x41000002 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// Enable Synchronization Busy - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2); - - /// address: 0x41000003 - /// USB Quality Of Service - pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Configuration Quality of Service - CQOS: u2, - /// Data Quality of Service - DQOS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3); - - /// address: 0x41000008 - /// DEVICE Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - /// Detach - DETACH: u1, - /// Upstream Resume - UPRSM: u1, - /// Speed Configuration - SPDCONF: u2, - /// No Reply - NREPLY: u1, - /// Test mode J - TSTJ: u1, - /// Test mode K - TSTK: u1, - /// Test packet mode - TSTPCKT: u1, - /// Specific Operational Mode - OPMODE2: u1, - /// Global NAK - GNAK: u1, - /// Link Power Management Handshake - LPMHDSK: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4100000a - /// DEVICE Device Address - pub const DADD = @intToPtr(*volatile Mmio(8, packed struct { - /// Device Address - DADD: u7, - /// Device Address Enable - ADDEN: u1, - }), base_address + 0xa); - - /// address: 0x4100000c - /// DEVICE Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - reserved1: u1, - /// Speed Status - SPEED: u2, - reserved2: u1, - reserved3: u1, - /// USB Line State Status - LINESTATE: u2, - }), base_address + 0xc); - - /// address: 0x4100000d - /// Finite State Machine Status - pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// Fine State Machine Status - FSMSTATE: u7, - padding0: u1, - }), base_address + 0xd); - - /// address: 0x41000010 - /// DEVICE Device Frame Number - pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { - /// Micro Frame Number - MFNUM: u3, - /// Frame Number - FNUM: u11, - reserved0: u1, - /// Frame Number CRC Error - FNCERR: u1, - }), base_address + 0x10); - - /// address: 0x41000014 - /// DEVICE Device Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - /// Suspend Interrupt Enable - SUSPEND: u1, - /// Micro Start of Frame Interrupt Enable in High Speed Mode - MSOF: u1, - /// Start Of Frame Interrupt Enable - SOF: u1, - /// End of Reset Interrupt Enable - EORST: u1, - /// Wake Up Interrupt Enable - WAKEUP: u1, - /// End Of Resume Interrupt Enable - EORSM: u1, - /// Upstream Resume Interrupt Enable - UPRSM: u1, - /// Ram Access Interrupt Enable - RAMACER: u1, - /// Link Power Management Not Yet Interrupt Enable - LPMNYET: u1, - /// Link Power Management Suspend Interrupt Enable - LPMSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x41000018 - /// DEVICE Device Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - /// Suspend Interrupt Enable - SUSPEND: u1, - /// Micro Start of Frame Interrupt Enable in High Speed Mode - MSOF: u1, - /// Start Of Frame Interrupt Enable - SOF: u1, - /// End of Reset Interrupt Enable - EORST: u1, - /// Wake Up Interrupt Enable - WAKEUP: u1, - /// End Of Resume Interrupt Enable - EORSM: u1, - /// Upstream Resume Interrupt Enable - UPRSM: u1, - /// Ram Access Interrupt Enable - RAMACER: u1, - /// Link Power Management Not Yet Interrupt Enable - LPMNYET: u1, - /// Link Power Management Suspend Interrupt Enable - LPMSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x18); - - /// address: 0x4100001c - /// DEVICE Device Interrupt Flag - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - /// Suspend - SUSPEND: u1, - /// Micro Start of Frame in High Speed Mode - MSOF: u1, - /// Start Of Frame - SOF: u1, - /// End of Reset - EORST: u1, - /// Wake Up - WAKEUP: u1, - /// End Of Resume - EORSM: u1, - /// Upstream Resume - UPRSM: u1, - /// Ram Access - RAMACER: u1, - /// Link Power Management Not Yet - LPMNYET: u1, - /// Link Power Management Suspend - LPMSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1c); - - /// address: 0x41000020 - /// DEVICE End Point Interrupt Summary - pub const EPINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { - /// End Point 0 Interrupt - EPINT0: u1, - /// End Point 1 Interrupt - EPINT1: u1, - /// End Point 2 Interrupt - EPINT2: u1, - /// End Point 3 Interrupt - EPINT3: u1, - /// End Point 4 Interrupt - EPINT4: u1, - /// End Point 5 Interrupt - EPINT5: u1, - /// End Point 6 Interrupt - EPINT6: u1, - /// End Point 7 Interrupt - EPINT7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x20); - - /// address: 0x41000024 - /// Descriptor Address - pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x41000028 - /// USB PAD Calibration - pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { - /// USB Pad Transp calibration - TRANSP: u5, - reserved0: u1, - /// USB Pad Transn calibration - TRANSN: u5, - reserved1: u1, - /// USB Pad Trim calibration - TRIM: u3, - padding0: u1, - }), base_address + 0x28); - }; - - /// USB is Host - pub const HOST = struct { - /// address: 0x41000000 - /// Control A - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset - SWRST: u1, - /// Enable - ENABLE: u1, - /// Run in Standby Mode - RUNSTDBY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Operating Mode - MODE: u1, - }), base_address + 0x0); - - /// address: 0x41000002 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(8, packed struct { - /// Software Reset Synchronization Busy - SWRST: u1, - /// Enable Synchronization Busy - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2); - - /// address: 0x41000003 - /// USB Quality Of Service - pub const QOSCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Configuration Quality of Service - CQOS: u2, - /// Data Quality of Service - DQOS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x3); - - /// address: 0x41000008 - /// HOST Control B - pub const CTRLB = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - /// Send USB Resume - RESUME: u1, - /// Speed Configuration for Host - SPDCONF: u2, - /// Auto Resume Enable - AUTORESUME: u1, - /// Test mode J - TSTJ: u1, - /// Test mode K - TSTK: u1, - reserved1: u1, - /// Start of Frame Generation Enable - SOFE: u1, - /// Send USB Reset - BUSRESET: u1, - /// VBUS is OK - VBUSOK: u1, - /// Send L1 Resume - L1RESUME: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4100000a - /// HOST Host Start Of Frame Control - pub const HSOFC = @intToPtr(*volatile Mmio(8, packed struct { - /// Frame Length Control - FLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Frame Length Control Enable - FLENCE: u1, - }), base_address + 0xa); - - /// address: 0x4100000c - /// HOST Status - pub const STATUS = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - reserved1: u1, - /// Speed Status - SPEED: u2, - reserved2: u1, - reserved3: u1, - /// USB Line State Status - LINESTATE: u2, - }), base_address + 0xc); - - /// address: 0x4100000d - /// Finite State Machine Status - pub const FSMSTATUS = @intToPtr(*volatile Mmio(8, packed struct { - /// Fine State Machine Status - FSMSTATE: u7, - padding0: u1, - }), base_address + 0xd); - - /// address: 0x41000010 - /// HOST Host Frame Number - pub const FNUM = @intToPtr(*volatile Mmio(16, packed struct { - /// Micro Frame Number - MFNUM: u3, - /// Frame Number - FNUM: u11, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x41000012 - /// HOST Host Frame Length - pub const FLENHIGH = @intToPtr(*volatile u8, base_address + 0x12); - - /// address: 0x41000014 - /// HOST Host Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Host Start Of Frame Interrupt Disable - HSOF: u1, - /// BUS Reset Interrupt Disable - RST: u1, - /// Wake Up Interrupt Disable - WAKEUP: u1, - /// DownStream to Device Interrupt Disable - DNRSM: u1, - /// Upstream Resume from Device Interrupt Disable - UPRSM: u1, - /// Ram Access Interrupt Disable - RAMACER: u1, - /// Device Connection Interrupt Disable - DCONN: u1, - /// Device Disconnection Interrupt Disable - DDISC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x41000018 - /// HOST Host Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Host Start Of Frame Interrupt Enable - HSOF: u1, - /// Bus Reset Interrupt Enable - RST: u1, - /// Wake Up Interrupt Enable - WAKEUP: u1, - /// DownStream to the Device Interrupt Enable - DNRSM: u1, - /// Upstream Resume fromthe device Interrupt Enable - UPRSM: u1, - /// Ram Access Interrupt Enable - RAMACER: u1, - /// Link Power Management Interrupt Enable - DCONN: u1, - /// Device Disconnection Interrupt Enable - DDISC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x18); - - /// address: 0x4100001c - /// HOST Host Interrupt Flag - pub const INTFLAG = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - /// Host Start Of Frame - HSOF: u1, - /// Bus Reset - RST: u1, - /// Wake Up - WAKEUP: u1, - /// Downstream - DNRSM: u1, - /// Upstream Resume from the Device - UPRSM: u1, - /// Ram Access - RAMACER: u1, - /// Device Connection - DCONN: u1, - /// Device Disconnection - DDISC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1c); - - /// address: 0x41000020 - /// HOST Pipe Interrupt Summary - pub const PINTSMRY = @intToPtr(*volatile Mmio(16, packed struct { - /// Pipe 0 Interrupt - EPINT0: u1, - /// Pipe 1 Interrupt - EPINT1: u1, - /// Pipe 2 Interrupt - EPINT2: u1, - /// Pipe 3 Interrupt - EPINT3: u1, - /// Pipe 4 Interrupt - EPINT4: u1, - /// Pipe 5 Interrupt - EPINT5: u1, - /// Pipe 6 Interrupt - EPINT6: u1, - /// Pipe 7 Interrupt - EPINT7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x20); - - /// address: 0x41000024 - /// Descriptor Address - pub const DESCADD = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x41000028 - /// USB PAD Calibration - pub const PADCAL = @intToPtr(*volatile Mmio(16, packed struct { - /// USB Pad Transp calibration - TRANSP: u5, - reserved0: u1, - /// USB Pad Transn calibration - TRANSN: u5, - reserved1: u1, - /// USB Pad Trim calibration - TRIM: u3, - padding0: u1, - }), base_address + 0x28); - }; - }; - - /// Watchdog Timer - pub const WDT = struct { - pub const base_address = 0x40002000; - pub const version = "U22511.1.0"; - - /// address: 0x40002000 - /// Control - pub const CTRLA = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// Enable - ENABLE: u1, - /// Watchdog Timer Window Mode Enable - WEN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Always-On - ALWAYSON: u1, - }), base_address + 0x0); - - /// address: 0x40002001 - /// Configuration - pub const CONFIG = @intToPtr(*volatile Mmio(8, packed struct { - /// Time-Out Period - PER: u4, - /// Window Mode Time-Out Period - WINDOW: u4, - }), base_address + 0x1); - - /// address: 0x40002002 - /// Early Warning Interrupt Control - pub const EWCTRL = @intToPtr(*volatile Mmio(8, packed struct { - /// Early Warning Interrupt Time Offset - EWOFFSET: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x2); - - /// address: 0x40002004 - /// Interrupt Enable Clear - pub const INTENCLR = @intToPtr(*volatile Mmio(8, packed struct { - /// Early Warning Interrupt Enable - EW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x4); - - /// address: 0x40002005 - /// Interrupt Enable Set - pub const INTENSET = @intToPtr(*volatile Mmio(8, packed struct { - /// Early Warning Interrupt Enable - EW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x5); - - /// address: 0x40002006 - /// Interrupt Flag Status and Clear - pub const INTFLAG = @intToPtr(*volatile Mmio(8, packed struct { - /// Early Warning - EW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x6); - - /// address: 0x40002008 - /// Synchronization Busy - pub const SYNCBUSY = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable Synchronization Busy - ENABLE: u1, - /// Window Enable Synchronization Busy - WEN: u1, - /// Always-On Synchronization Busy - ALWAYSON: u1, - /// Clear Synchronization Busy - CLEAR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x8); - - /// address: 0x4000200c - /// Clear - pub const CLEAR = @intToPtr(*volatile u8, base_address + 0xc); - }; - - /// Core Debug Register - pub const CoreDebug = struct { - pub const base_address = 0xe000edf0; - - /// address: 0xe000edf0 - /// Debug Halting Control and Status Register - pub const DHCSR = @intToPtr(*volatile Mmio(32, packed struct { - C_DEBUGEN: u1, - C_HALT: u1, - C_STEP: u1, - C_MASKINTS: u1, - reserved0: u1, - C_SNAPSTALL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - S_REGRDY: u1, - S_HALT: u1, - S_SLEEP: u1, - S_LOCKUP: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - S_RETIRE_ST: u1, - S_RESET_ST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0xe000edf4 - /// Debug Core Register Selector Register - pub const DCRSR = @intToPtr(*volatile Mmio(32, packed struct { - REGSEL: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - REGWnR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x4); - - /// address: 0xe000edf8 - /// Debug Core Register Data Register - pub const DCRDR = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0xe000edfc - /// Debug Exception and Monitor Control Register - pub const DEMCR = @intToPtr(*volatile Mmio(32, packed struct { - VC_CORERESET: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - VC_MMERR: u1, - VC_NOCPERR: u1, - VC_CHKERR: u1, - VC_STATERR: u1, - VC_BUSERR: u1, - VC_INTERR: u1, - VC_HARDERR: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - MON_EN: u1, - MON_PEND: u1, - MON_STEP: u1, - MON_REQ: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - TRCENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xc); - }; - - /// Data Watchpoint and Trace Register - pub const DWT = struct { - pub const base_address = 0xe0001000; - - /// address: 0xe0001000 - /// Control Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - CYCCNTENA: u1, - POSTPRESET: u4, - POSTINIT: u4, - CYCTAP: u1, - SYNCTAP: u2, - PCSAMPLENA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - EXCTRCENA: u1, - CPIEVTENA: u1, - EXCEVTENA: u1, - SLEEPEVTENA: u1, - LSUEVTENA: u1, - FOLDEVTENA: u1, - CYCEVTENA: u1, - reserved3: u1, - NOPRFCNT: u1, - NOCYCCNT: u1, - NOEXTTRIG: u1, - NOTRCPKT: u1, - NUMCOMP: u4, - }), base_address + 0x0); - - /// address: 0xe0001004 - /// Cycle Count Register - pub const CYCCNT = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0xe0001008 - /// CPI Count Register - pub const CPICNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - - /// address: 0xe000100c - /// Exception Overhead Count Register - pub const EXCCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xc); - - /// address: 0xe0001010 - /// Sleep Count Register - pub const SLEEPCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0xe0001014 - /// LSU Count Register - pub const LSUCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x14); - - /// address: 0xe0001018 - /// Folded-instruction Count Register - pub const FOLDCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x18); - - /// address: 0xe000101c - /// Program Counter Sample Register - pub const PCSR = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0xe0001020 - /// Comparator Register 0 - pub const COMP0 = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0xe0001024 - /// Mask Register 0 - pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { - MASK: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x24); - - /// address: 0xe0001028 - /// Function Register 0 - pub const FUNCTION0 = @intToPtr(*volatile Mmio(32, packed struct { - FUNCTION: u4, - reserved0: u1, - EMITRANGE: u1, - reserved1: u1, - CYCMATCH: u1, - DATAVMATCH: u1, - LNK1ENA: u1, - DATAVSIZE: u2, - DATAVADDR0: u4, - DATAVADDR1: u4, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - MATCHED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x28); - - /// address: 0xe0001030 - /// Comparator Register 1 - pub const COMP1 = @intToPtr(*volatile u32, base_address + 0x30); - - /// address: 0xe0001034 - /// Mask Register 1 - pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { - MASK: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x34); - - /// address: 0xe0001038 - /// Function Register 1 - pub const FUNCTION1 = @intToPtr(*volatile Mmio(32, packed struct { - FUNCTION: u4, - reserved0: u1, - EMITRANGE: u1, - reserved1: u1, - CYCMATCH: u1, - DATAVMATCH: u1, - LNK1ENA: u1, - DATAVSIZE: u2, - DATAVADDR0: u4, - DATAVADDR1: u4, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - MATCHED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x38); - - /// address: 0xe0001040 - /// Comparator Register 2 - pub const COMP2 = @intToPtr(*volatile u32, base_address + 0x40); - - /// address: 0xe0001044 - /// Mask Register 2 - pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { - MASK: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x44); - - /// address: 0xe0001048 - /// Function Register 2 - pub const FUNCTION2 = @intToPtr(*volatile Mmio(32, packed struct { - FUNCTION: u4, - reserved0: u1, - EMITRANGE: u1, - reserved1: u1, - CYCMATCH: u1, - DATAVMATCH: u1, - LNK1ENA: u1, - DATAVSIZE: u2, - DATAVADDR0: u4, - DATAVADDR1: u4, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - MATCHED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x48); - - /// address: 0xe0001050 - /// Comparator Register 3 - pub const COMP3 = @intToPtr(*volatile u32, base_address + 0x50); - - /// address: 0xe0001054 - /// Mask Register 3 - pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { - MASK: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x54); - - /// address: 0xe0001058 - /// Function Register 3 - pub const FUNCTION3 = @intToPtr(*volatile Mmio(32, packed struct { - FUNCTION: u4, - reserved0: u1, - EMITRANGE: u1, - reserved1: u1, - CYCMATCH: u1, - DATAVMATCH: u1, - LNK1ENA: u1, - DATAVSIZE: u2, - DATAVADDR0: u4, - DATAVADDR1: u4, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - MATCHED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x58); - }; - - /// Embedded Trace Macrocell - pub const ETM = struct { - pub const base_address = 0xe0041000; - - /// address: 0xe0041000 - /// ETM Main Control Register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// ETM Power Down - ETMPD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Port Size bits 2:0 - PORTSIZE: u3, - /// Stall Processor - STALL: u1, - /// Branch Output - BROUT: u1, - /// Debug Request Control - DBGRQ: u1, - /// ETM Programming - PROG: u1, - /// ETM Port Select - PORTSEL: u1, - reserved3: u1, - /// Port Mode bit 2 - PORTMODE2: u1, - reserved4: u1, - reserved5: u1, - /// Port Mode bits 1:0 - PORTMODE: u2, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Port Size bit 3 - PORTSIZE3: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// TimeStamp Enable - TSEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0xe0041004 - /// ETM Configuration Code Register - pub const CCR = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0xe0041008 - /// ETM Trigger Event Register - pub const TRIGGER = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0xe0041010 - /// ETM Status Register - pub const SR = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0xe0041014 - /// ETM System Configuration Register - pub const SCR = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0xe0041020 - /// ETM TraceEnable Event Register - pub const TEEVR = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0xe0041024 - /// ETM TraceEnable Control 1 Register - pub const TECR1 = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0xe0041028 - /// ETM FIFO Full Level Register - pub const FFLR = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0xe0041140 - /// ETM Free-running Counter Reload Value - pub const CNTRLDVR1 = @intToPtr(*volatile u32, base_address + 0x140); - - /// address: 0xe00411e0 - /// ETM Synchronization Frequency Register - pub const SYNCFR = @intToPtr(*volatile u32, base_address + 0x1e0); - - /// address: 0xe00411e4 - /// ETM ID Register - pub const IDR = @intToPtr(*volatile u32, base_address + 0x1e4); - - /// address: 0xe00411e8 - /// ETM Configuration Code Extension Register - pub const CCER = @intToPtr(*volatile u32, base_address + 0x1e8); - - /// address: 0xe00411f0 - /// ETM TraceEnable Start/Stop EmbeddedICE Control Register - pub const TESSEICR = @intToPtr(*volatile u32, base_address + 0x1f0); - - /// address: 0xe00411f8 - /// ETM TimeStamp Event Register - pub const TSEVT = @intToPtr(*volatile u32, base_address + 0x1f8); - - /// address: 0xe0041200 - /// ETM CoreSight Trace ID Register - pub const TRACEIDR = @intToPtr(*volatile u32, base_address + 0x200); - - /// address: 0xe0041208 - /// ETM ID Register 2 - pub const IDR2 = @intToPtr(*volatile u32, base_address + 0x208); - - /// address: 0xe0041314 - /// ETM Device Power-Down Status Register - pub const PDSR = @intToPtr(*volatile u32, base_address + 0x314); - - /// address: 0xe0041ee0 - /// ETM Integration Test Miscellaneous Inputs - pub const ITMISCIN = @intToPtr(*volatile u32, base_address + 0xee0); - - /// address: 0xe0041ee8 - /// ETM Integration Test Trigger Out - pub const ITTRIGOUT = @intToPtr(*volatile u32, base_address + 0xee8); - - /// address: 0xe0041ef0 - /// ETM Integration Test ATB Control 2 - pub const ITATBCTR2 = @intToPtr(*volatile u32, base_address + 0xef0); - - /// address: 0xe0041ef8 - /// ETM Integration Test ATB Control 0 - pub const ITATBCTR0 = @intToPtr(*volatile u32, base_address + 0xef8); - - /// address: 0xe0041f00 - /// ETM Integration Mode Control Register - pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { - INTEGRATION: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xf00); - - /// address: 0xe0041fa0 - /// ETM Claim Tag Set Register - pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); - - /// address: 0xe0041fa4 - /// ETM Claim Tag Clear Register - pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); - - /// address: 0xe0041fb0 - /// ETM Lock Access Register - pub const LAR = @intToPtr(*volatile u32, base_address + 0xfb0); - - /// address: 0xe0041fb4 - /// ETM Lock Status Register - pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { - Present: u1, - Access: u1, - ByteAcc: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0xfb4); - - /// address: 0xe0041fb8 - /// ETM Authentication Status Register - pub const AUTHSTATUS = @intToPtr(*volatile u32, base_address + 0xfb8); - - /// address: 0xe0041fcc - /// ETM CoreSight Device Type Register - pub const DEVTYPE = @intToPtr(*volatile u32, base_address + 0xfcc); - - /// address: 0xe0041fd0 - /// ETM Peripheral Identification Register #4 - pub const PIDR4 = @intToPtr(*volatile u32, base_address + 0xfd0); - - /// address: 0xe0041fd4 - /// ETM Peripheral Identification Register #5 - pub const PIDR5 = @intToPtr(*volatile u32, base_address + 0xfd4); - - /// address: 0xe0041fd8 - /// ETM Peripheral Identification Register #6 - pub const PIDR6 = @intToPtr(*volatile u32, base_address + 0xfd8); - - /// address: 0xe0041fdc - /// ETM Peripheral Identification Register #7 - pub const PIDR7 = @intToPtr(*volatile u32, base_address + 0xfdc); - - /// address: 0xe0041fe0 - /// ETM Peripheral Identification Register #0 - pub const PIDR0 = @intToPtr(*volatile u32, base_address + 0xfe0); - - /// address: 0xe0041fe4 - /// ETM Peripheral Identification Register #1 - pub const PIDR1 = @intToPtr(*volatile u32, base_address + 0xfe4); - - /// address: 0xe0041fe8 - /// ETM Peripheral Identification Register #2 - pub const PIDR2 = @intToPtr(*volatile u32, base_address + 0xfe8); - - /// address: 0xe0041fec - /// ETM Peripheral Identification Register #3 - pub const PIDR3 = @intToPtr(*volatile u32, base_address + 0xfec); - - /// address: 0xe0041ff0 - /// ETM Component Identification Register #0 - pub const CIDR0 = @intToPtr(*volatile u32, base_address + 0xff0); - - /// address: 0xe0041ff4 - /// ETM Component Identification Register #1 - pub const CIDR1 = @intToPtr(*volatile u32, base_address + 0xff4); - - /// address: 0xe0041ff8 - /// ETM Component Identification Register #2 - pub const CIDR2 = @intToPtr(*volatile u32, base_address + 0xff8); - - /// address: 0xe0041ffc - /// ETM Component Identification Register #3 - pub const CIDR3 = @intToPtr(*volatile u32, base_address + 0xffc); - }; - - /// Floating Point Unit - pub const FPU = struct { - pub const base_address = 0xe000ef30; - - /// address: 0xe000ef34 - /// Floating-Point Context Control Register - pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { - LSPACT: u1, - USER: u1, - reserved0: u1, - THREAD: u1, - HFRDY: u1, - MMRDY: u1, - BFRDY: u1, - reserved1: u1, - MONRDY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - LSPEN: u1, - ASPEN: u1, - }), base_address + 0x4); - - /// address: 0xe000ef38 - /// Floating-Point Context Address Register - pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Address for FP registers in exception stack frame - ADDRESS: u29, - }), base_address + 0x8); - - /// address: 0xe000ef3c - /// Floating-Point Default Status Control Register - pub const FPDSCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Default value for FPSCR.RMODE - RMODE: u2, - /// Default value for FPSCR.FZ - FZ: u1, - /// Default value for FPSCR.DN - DN: u1, - /// Default value for FPSCR.AHP - AHP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0xc); - - /// address: 0xe000ef40 - /// Media and FP Feature Register 0 - pub const MVFR0 = @intToPtr(*volatile Mmio(32, packed struct { - A_SIMD_registers: u4, - Single_precision: u4, - Double_precision: u4, - FP_excep_trapping: u4, - Divide: u4, - Square_root: u4, - Short_vectors: u4, - FP_rounding_modes: u4, - }), base_address + 0x10); - - /// address: 0xe000ef44 - /// Media and FP Feature Register 1 - pub const MVFR1 = @intToPtr(*volatile Mmio(32, packed struct { - FtZ_mode: u4, - D_NaN_mode: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - FP_HPFP: u4, - FP_fused_MAC: u4, - }), base_address + 0x14); - }; - - /// Instrumentation Trace Macrocell - pub const ITM = struct { - pub const base_address = 0xe0000000; - - /// address: 0xe0000000 - /// ITM Stimulus Port Registers - pub const PORT_WORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { - PORT: u32, - }), base_address + 0x0); - - /// address: 0xe0000000 - /// ITM Stimulus Port Registers - pub const PORT_BYTE_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { - PORT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0xe0000000 - /// ITM Stimulus Port Registers - pub const PORT_HWORD_MODE = @intToPtr(*volatile [32]Mmio(32, packed struct { - PORT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0xe0000e00 - /// ITM Trace Enable Register - pub const TER = @intToPtr(*volatile u32, base_address + 0xe00); - - /// address: 0xe0000e40 - /// ITM Trace Privilege Register - pub const TPR = @intToPtr(*volatile Mmio(32, packed struct { - PRIVMASK: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0xe40); - - /// address: 0xe0000e80 - /// ITM Trace Control Register - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - ITMENA: u1, - TSENA: u1, - SYNCENA: u1, - DWTENA: u1, - SWOENA: u1, - STALLENA: u1, - reserved0: u1, - reserved1: u1, - TSPrescale: u2, - GTSFREQ: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - TraceBusID: u7, - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xe80); - - /// address: 0xe0000ef8 - /// ITM Integration Write Register - pub const IWR = @intToPtr(*volatile Mmio(32, packed struct { - ATVALIDM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xef8); - - /// address: 0xe0000efc - /// ITM Integration Read Register - pub const IRR = @intToPtr(*volatile Mmio(32, packed struct { - ATREADYM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xefc); - }; - - /// Memory Protection Unit - pub const MPU = struct { - pub const base_address = 0xe000ed90; - - /// address: 0xe000ed90 - /// MPU Type Register - pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { - /// Separate instruction and Data Memory MapsRegions - SEPARATE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Number of Data Regions - DREGION: u8, - /// Number of Instruction Regions - IREGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0xe000ed94 - /// MPU Control Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU Enable - ENABLE: u1, - /// Enable Hard Fault and NMI handlers - HFNMIENA: u1, - /// Enables privileged software access to default memory map - PRIVDEFENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0xe000ed98 - /// MPU Region Number Register - pub const RNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region referenced by RBAR and RASR - REGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0xe000ed9c - /// MPU Region Base Address Register - pub const RBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region number - REGION: u4, - /// Region number valid - VALID: u1, - /// Region base address - ADDR: u27, - }), base_address + 0xc); - - /// address: 0xe000eda0 - /// MPU Region Attribute and Size Register - pub const RASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Enable - ENABLE: u1, - /// Region Size - SIZE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Sub-region disable - SRD: u8, - /// Bufferable bit - B: u1, - /// Cacheable bit - C: u1, - /// Shareable bit - S: u1, - /// TEX bit - TEX: u3, - reserved6: u1, - reserved7: u1, - /// Access Permission - AP: u3, - reserved8: u1, - /// Execute Never Attribute - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0xe000eda4 - /// MPU Alias 1 Region Base Address Register - pub const RBAR_A1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region number - REGION: u4, - /// Region number valid - VALID: u1, - /// Region base address - ADDR: u27, - }), base_address + 0x14); - - /// address: 0xe000eda8 - /// MPU Alias 1 Region Attribute and Size Register - pub const RASR_A1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Enable - ENABLE: u1, - /// Region Size - SIZE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Sub-region disable - SRD: u8, - /// Bufferable bit - B: u1, - /// Cacheable bit - C: u1, - /// Shareable bit - S: u1, - /// TEX bit - TEX: u3, - reserved6: u1, - reserved7: u1, - /// Access Permission - AP: u3, - reserved8: u1, - /// Execute Never Attribute - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x18); - - /// address: 0xe000edac - /// MPU Alias 2 Region Base Address Register - pub const RBAR_A2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region number - REGION: u4, - /// Region number valid - VALID: u1, - /// Region base address - ADDR: u27, - }), base_address + 0x1c); - - /// address: 0xe000edb0 - /// MPU Alias 2 Region Attribute and Size Register - pub const RASR_A2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Enable - ENABLE: u1, - /// Region Size - SIZE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Sub-region disable - SRD: u8, - /// Bufferable bit - B: u1, - /// Cacheable bit - C: u1, - /// Shareable bit - S: u1, - /// TEX bit - TEX: u3, - reserved6: u1, - reserved7: u1, - /// Access Permission - AP: u3, - reserved8: u1, - /// Execute Never Attribute - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x20); - - /// address: 0xe000edb4 - /// MPU Alias 3 Region Base Address Register - pub const RBAR_A3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region number - REGION: u4, - /// Region number valid - VALID: u1, - /// Region base address - ADDR: u27, - }), base_address + 0x24); - - /// address: 0xe000edb8 - /// MPU Alias 3 Region Attribute and Size Register - pub const RASR_A3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Region Enable - ENABLE: u1, - /// Region Size - SIZE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Sub-region disable - SRD: u8, - /// Bufferable bit - B: u1, - /// Cacheable bit - C: u1, - /// Shareable bit - S: u1, - /// TEX bit - TEX: u3, - reserved6: u1, - reserved7: u1, - /// Access Permission - AP: u3, - reserved8: u1, - /// Execute Never Attribute - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x28); - }; - - /// Nested Vectored Interrupt Controller - pub const NVIC = struct { - pub const base_address = 0xe000e100; - - /// address: 0xe000e100 - /// Interrupt Set Enable Register - pub const ISER = @intToPtr(*volatile [5]Mmio(32, packed struct { - /// Interrupt set enable bits - SETENA: u32, - }), base_address + 0x0); - - /// address: 0xe000e180 - /// Interrupt Clear Enable Register - pub const ICER = @intToPtr(*volatile [5]Mmio(32, packed struct { - /// Interrupt clear-enable bits - CLRENA: u32, - }), base_address + 0x80); - - /// address: 0xe000e200 - /// Interrupt Set Pending Register - pub const ISPR = @intToPtr(*volatile [5]Mmio(32, packed struct { - /// Interrupt set-pending bits - SETPEND: u32, - }), base_address + 0x100); - - /// address: 0xe000e280 - /// Interrupt Clear Pending Register - pub const ICPR = @intToPtr(*volatile [5]Mmio(32, packed struct { - /// Interrupt clear-pending bits - CLRPEND: u32, - }), base_address + 0x180); - - /// address: 0xe000e300 - /// Interrupt Active Bit Register - pub const IABR = @intToPtr(*volatile [5]Mmio(32, packed struct { - /// Interrupt active bits - ACTIVE: u32, - }), base_address + 0x200); - - /// address: 0xe000e400 - /// Interrupt Priority Register n - pub const IP = @intToPtr(*volatile [35]Mmio(8, packed struct { - /// Priority of interrupt n - PRI0: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x300); - - /// address: 0xe000ef00 - /// Software Trigger Interrupt Register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt ID to trigger - INTID: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xe00); - }; - - /// System timer - pub const SysTick = struct { - pub const base_address = 0xe000e010; - }; - - /// System Control Registers - pub const SystemControl = struct { - pub const base_address = 0xe000e000; - - /// address: 0xe000e004 - /// Interrupt Controller Type Register - pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct { - INTLINESNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x4); - - /// address: 0xe000e008 - /// Auxiliary Control Register - pub const ACTLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Disable interruption of LDM/STM instructions - DISMCYCINT: u1, - /// Disable wruite buffer use during default memory map accesses - DISDEFWBUF: u1, - /// Disable IT folding - DISFOLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Disable automatic update of CONTROL.FPCA - DISFPCA: u1, - /// Disable out-of-order FP instructions - DISOOFP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x8); - - /// address: 0xe000ed00 - /// CPUID Base Register - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { - /// Processor revision number - REVISION: u4, - /// Process Part Number, 0xC24=Cortex-M4 - PARTNO: u12, - /// Constant - CONSTANT: u4, - /// Variant number - VARIANT: u4, - /// Implementer code, 0x41=ARM - IMPLEMENTER: u8, - }), base_address + 0xd00); - - /// address: 0xe000ed04 - /// Interrupt Control and State Register - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Active exception number - VECTACTIVE: u9, - reserved0: u1, - reserved1: u1, - /// No preempted active exceptions to execute - RETTOBASE: u1, - /// Exception number of the highest priority pending enabled exception - VECTPENDING: u6, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Interrupt pending flag - ISRPENDING: u1, - /// Debug only - ISRPREEMPT: u1, - reserved6: u1, - /// SysTick clear-pending bit - PENDSTCLR: u1, - /// SysTick set-pending bit - PENDSTSET: u1, - /// PendSV clear-pending bit - PENDSVCLR: u1, - /// PendSV set-pending bit - PENDSVSET: u1, - reserved7: u1, - reserved8: u1, - /// NMI set-pending bit - NMIPENDSET: u1, - }), base_address + 0xd04); - - /// address: 0xe000ed08 - /// Vector Table Offset Register - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Vector table base offset - TBLOFF: u25, - }), base_address + 0xd08); - - /// address: 0xe000ed0c - /// Application Interrupt and Reset Control Register - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Must write 0 - VECTRESET: u1, - /// Must write 0 - VECTCLRACTIVE: u1, - /// System Reset Request - SYSRESETREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Interrupt priority grouping - PRIGROUP: u3, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Data endianness, 0=little, 1=big - ENDIANNESS: u1, - /// Register key - VECTKEY: u16, - }), base_address + 0xd0c); - - /// address: 0xe000ed10 - /// System Control Register - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Sleep-on-exit on handler return - SLEEPONEXIT: u1, - /// Deep Sleep used as low power mode - SLEEPDEEP: u1, - reserved1: u1, - /// Send Event on Pending bit - SEVONPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xd10); - - /// address: 0xe000ed14 - /// Configuration and Control Register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Indicates how processor enters Thread mode - NONBASETHRDENA: u1, - /// Enables unprivileged software access to STIR register - USERSETMPEND: u1, - reserved0: u1, - /// Enables unaligned access traps - UNALIGN_TRP: u1, - /// Enables divide by 0 trap - DIV_0_TRP: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Ignore LDM/STM BusFault for -1/-2 priority handlers - BFHFNMIGN: u1, - /// Indicates stack alignment on exception entry - STKALIGN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0xd14); - - /// address: 0xe000ed18 - /// System Handler Priority Register 1 - pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Priority of system handler 4, MemManage - PRI_4: u8, - /// Priority of system handler 5, BusFault - PRI_5: u8, - /// Priority of system handler 6, UsageFault - PRI_6: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xd18); - - /// address: 0xe000ed1c - /// System Handler Priority Register 2 - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - /// Priority of system handler 11, SVCall - PRI_11: u8, - }), base_address + 0xd1c); - - /// address: 0xe000ed20 - /// System Handler Priority Register 3 - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Priority of system handler 14, PendSV - PRI_14: u8, - /// Priority of system handler 15, SysTick exception - PRI_15: u8, - }), base_address + 0xd20); - - /// address: 0xe000ed24 - /// System Handler Control and State Register - pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { - /// MemManage exception active bit - MEMFAULTACT: u1, - /// BusFault exception active bit - BUSFAULTACT: u1, - reserved0: u1, - /// UsageFault exception active bit - USGFAULTACT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// SVCall active bit - SVCALLACT: u1, - /// DebugMonitor exception active bit - MONITORACT: u1, - reserved4: u1, - /// PendSV exception active bit - PENDSVACT: u1, - /// SysTick exception active bit - SYSTICKACT: u1, - /// UsageFault exception pending bit - USGFAULTPENDED: u1, - /// MemManage exception pending bit - MEMFAULTPENDED: u1, - /// BusFault exception pending bit - BUSFAULTPENDED: u1, - /// SVCall pending bit - SVCALLPENDED: u1, - /// MemManage enable bit - MEMFAULTENA: u1, - /// BusFault enable bit - BUSFAULTENA: u1, - /// UsageFault enable bit - USGFAULTENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xd24); - - /// address: 0xe000ed28 - /// Configurable Fault Status Register - pub const CFSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Instruction access violation - IACCVIOL: u1, - /// Data access violation - DACCVIOL: u1, - reserved0: u1, - /// MemManage Fault on unstacking for exception return - MUNSTKERR: u1, - /// MemManage Fault on stacking for exception entry - MSTKERR: u1, - /// MemManager Fault occured during FP lazy state preservation - MLSPERR: u1, - reserved1: u1, - /// MemManage Fault Address Register valid - MMARVALID: u1, - /// Instruction bus error - IBUSERR: u1, - /// Precise data bus error - PRECISERR: u1, - /// Imprecise data bus error - IMPRECISERR: u1, - /// BusFault on unstacking for exception return - UNSTKERR: u1, - /// BusFault on stacking for exception entry - STKERR: u1, - /// BusFault occured during FP lazy state preservation - LSPERR: u1, - reserved2: u1, - /// BusFault Address Register valid - BFARVALID: u1, - /// Undefined instruction UsageFault - UNDEFINSTR: u1, - /// Invalid state UsageFault - INVSTATE: u1, - /// Invalid PC load UsageFault - INVPC: u1, - /// No coprocessor UsageFault - NOCP: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Unaligned access UsageFault - UNALIGNED: u1, - /// Divide by zero UsageFault - DIVBYZERO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xd28); - - /// address: 0xe000ed2c - /// HardFault Status Register - pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// BusFault on a Vector Table read during exception processing - VECTTBL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - reserved28: u1, - /// Forced Hard Fault - FORCED: u1, - /// Debug: always write 0 - DEBUGEVT: u1, - }), base_address + 0xd2c); - - /// address: 0xe000ed30 - /// Debug Fault Status Register - pub const DFSR = @intToPtr(*volatile Mmio(32, packed struct { - HALTED: u1, - BKPT: u1, - DWTTRAP: u1, - VCATCH: u1, - EXTERNAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xd30); - - /// address: 0xe000ed34 - /// MemManage Fault Address Register - pub const MMFAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address that generated the MemManage fault - ADDRESS: u32, - }), base_address + 0xd34); - - /// address: 0xe000ed38 - /// BusFault Address Register - pub const BFAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address that generated the BusFault - ADDRESS: u32, - }), base_address + 0xd38); - - /// address: 0xe000ed3c - /// Auxiliary Fault Status Register - pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { - /// AUXFAULT input signals - IMPDEF: u32, - }), base_address + 0xd3c); - - /// address: 0xe000ed40 - /// Processor Feature Register - pub const PFR = @intToPtr(*volatile [2]u32, base_address + 0xd40); - - /// address: 0xe000ed48 - /// Debug Feature Register - pub const DFR = @intToPtr(*volatile u32, base_address + 0xd48); - - /// address: 0xe000ed4c - /// Auxiliary Feature Register - pub const ADR = @intToPtr(*volatile u32, base_address + 0xd4c); - - /// address: 0xe000ed50 - /// Memory Model Feature Register - pub const MMFR = @intToPtr(*volatile [4]u32, base_address + 0xd50); - - /// address: 0xe000ed60 - /// Instruction Set Attributes Register - pub const ISAR = @intToPtr(*volatile [5]u32, base_address + 0xd60); - - /// address: 0xe000ed88 - /// Coprocessor Access Control Register - pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Access privileges for coprocessor 10 - CP10: u2, - /// Access privileges for coprocessor 11 - CP11: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xd88); - }; - - /// Trace Port Interface Register - pub const TPI = struct { - pub const base_address = 0xe0040000; - - /// address: 0xe0040000 - /// Supported Parallel Port Size Register - pub const SSPSR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0xe0040004 - /// Current Parallel Port Size Register - pub const CSPSR = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0xe0040010 - /// Asynchronous Clock Prescaler Register - pub const ACPR = @intToPtr(*volatile Mmio(32, packed struct { - PRESCALER: u13, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0xe00400f0 - /// Selected Pin Protocol Register - pub const SPPR = @intToPtr(*volatile Mmio(32, packed struct { - TXMODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xf0); - - /// address: 0xe0040300 - /// Formatter and Flush Status Register - pub const FFSR = @intToPtr(*volatile Mmio(32, packed struct { - FlInProg: u1, - FtStopped: u1, - TCPresent: u1, - FtNonStop: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x300); - - /// address: 0xe0040304 - /// Formatter and Flush Control Register - pub const FFCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - EnFCont: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - TrigIn: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x304); - - /// address: 0xe0040308 - /// Formatter Synchronization Counter Register - pub const FSCR = @intToPtr(*volatile u32, base_address + 0x308); - - /// address: 0xe0040ee8 - /// TRIGGER - pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xee8); - - /// address: 0xe0040eec - /// Integration ETM Data - pub const FIFO0 = @intToPtr(*volatile Mmio(32, packed struct { - ETM0: u8, - ETM1: u8, - ETM2: u8, - ETM_bytecount: u2, - ETM_ATVALID: u1, - ITM_bytecount: u2, - ITM_ATVALID: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xeec); - - /// address: 0xe0040ef0 - /// ITATBCTR2 - pub const ITATBCTR2 = @intToPtr(*volatile Mmio(32, packed struct { - ATREADY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xef0); - - /// address: 0xe0040ef8 - /// ITATBCTR0 - pub const ITATBCTR0 = @intToPtr(*volatile Mmio(32, packed struct { - ATREADY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xef8); - - /// address: 0xe0040efc - /// Integration ITM Data - pub const FIFO1 = @intToPtr(*volatile Mmio(32, packed struct { - ITM0: u8, - ITM1: u8, - ITM2: u8, - ETM_bytecount: u2, - ETM_ATVALID: u1, - ITM_bytecount: u2, - ITM_ATVALID: u1, - padding0: u1, - padding1: u1, - }), base_address + 0xefc); - - /// address: 0xe0040f00 - /// Integration Mode Control - pub const ITCTRL = @intToPtr(*volatile Mmio(32, packed struct { - Mode: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xf00); - - /// address: 0xe0040fa0 - /// Claim tag set - pub const CLAIMSET = @intToPtr(*volatile u32, base_address + 0xfa0); - - /// address: 0xe0040fa4 - /// Claim tag clear - pub const CLAIMCLR = @intToPtr(*volatile u32, base_address + 0xfa4); - - /// address: 0xe0040fc8 - /// TPIU_DEVID - pub const DEVID = @intToPtr(*volatile Mmio(32, packed struct { - NrTraceInput: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - AsynClkIn: u1, - MinBufSz: u3, - PTINVALID: u1, - MANCVALID: u1, - NRZVALID: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0xfc8); - - /// address: 0xe0040fcc - /// TPIU_DEVTYPE - pub const DEVTYPE = @intToPtr(*volatile Mmio(32, packed struct { - SubType: u4, - MajorType: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xfcc); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/gd32vf103/gd32vf103.zig b/src/modules/chips/gd32vf103/gd32vf103.zig deleted file mode 100644 index 0758d2f..0000000 --- a/src/modules/chips/gd32vf103/gd32vf103.zig +++ /dev/null @@ -1,114 +0,0 @@ -pub const cpu = @import("cpu"); -pub const micro = @import("microzig"); -pub const chip = @import("registers.zig"); -const regs = chip.registers; - -pub usingnamespace chip; - -pub const clock_frequencies = .{ - .cpu = 8_000_000, // 8 MHz -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec[0] != 'P') - @compileError(invalid_format_msg); - if (spec[1] < 'A' or spec[1] > 'E') - @compileError(invalid_format_msg); - - return struct { - const pin_number: comptime_int = @import("std").fmt.parseInt(u2, spec[2..], 10) catch @compileError(invalid_format_msg); - // 'A'...'E' - const gpio_port_name = spec[1..2]; - const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); - const suffix = @import("std").fmt.comptimePrint("{d}", .{pin_number}); - }; -} - -fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { - var temp = reg.read(); - @field(temp, field_name) = value; - reg.write(temp); -} - -pub const gpio = struct { - pub fn setOutput(comptime pin: type) void { - _ = pin; - // TODO: check if pin is already configured as output - } - pub fn setInput(comptime pin: type) void { - _ = pin; - // TODO: check if pin is already configured as input - } - - pub fn read(comptime pin: type) micro.gpio.State { - _ = pin; - // TODO: check if pin is configured as input - return .low; - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - _ = pin; - _ = state; - // TODO: check if pin is configured as output - } -}; - -pub const uart = struct { - pub const DataBits = enum(u2) { - five = 0, - six = 1, - seven = 2, - eight = 3, - }; - - pub const StopBits = enum(u1) { - one = 0, - two = 1, - }; - - pub const Parity = enum(u2) { - odd = 0, - even = 1, - mark = 2, - space = 3, - }; -}; - -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (pins.tx != null or pins.rx != null) - @compileError("TODO: custom pins are not currently supported"); - - return struct { - const UARTn = switch (index) { - 0 => regs.UART3, - 1 => regs.UART4, - else => @compileError("GD32VF103 has 2 UARTs available."), - }; - const Self = @This(); - - pub fn init(config: micro.uart.Config) !Self { - _ = config; - return Self{}; - } - - pub fn canWrite(self: Self) bool { - _ = self; - return false; - } - pub fn tx(self: Self, ch: u8) void { - _ = ch; - while (!self.canWrite()) {} // Wait for Previous transmission - } - - pub fn canRead(self: Self) bool { - _ = self; - return false; - } - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - return 1; // Read received data - } - }; -} diff --git a/src/modules/chips/gd32vf103/registers.zig b/src/modules/chips/gd32vf103/registers.zig deleted file mode 100644 index 356a07d..0000000 --- a/src/modules/chips/gd32vf103/registers.zig +++ /dev/null @@ -1,24637 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 341b0177d90a56f4307cc3226d552b39b048e7fa -// -// device: GD32VF103 -// cpu: CM3 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - reserved2: u32 = undefined, - reserved3: u32 = undefined, - reserved4: u32 = undefined, - /// Software interrupt - INT_SFT: InterruptVector = unhandled, - reserved5: u32 = undefined, - reserved6: u32 = undefined, - reserved7: u32 = undefined, - /// Timer interrupt - INT_TMR: InterruptVector = unhandled, - reserved8: u32 = undefined, - reserved9: u32 = undefined, - reserved10: u32 = undefined, - reserved11: u32 = undefined, - reserved12: u32 = undefined, - reserved13: u32 = undefined, - reserved14: u32 = undefined, - reserved15: u32 = undefined, - reserved16: u32 = undefined, - /// Bus Error interrupt - INT_BWEI: InterruptVector = unhandled, - /// Performance Monitor interrupt - INT_PMOVI: InterruptVector = unhandled, - WWDGT: InterruptVector = unhandled, - EXTI_LVD: InterruptVector = unhandled, - Tamper: InterruptVector = unhandled, - RTC: InterruptVector = unhandled, - FMC: InterruptVector = unhandled, - RCU: InterruptVector = unhandled, - EXTI_Line0: InterruptVector = unhandled, - EXTI_Line1: InterruptVector = unhandled, - EXTI_Line2: InterruptVector = unhandled, - EXTI_Line3: InterruptVector = unhandled, - EXTI_Line4: InterruptVector = unhandled, - DMA0_Channel0: InterruptVector = unhandled, - DMA0_Channel1: InterruptVector = unhandled, - DMA0_Channel2: InterruptVector = unhandled, - DMA0_Channel3: InterruptVector = unhandled, - DMA0_Channel4: InterruptVector = unhandled, - DMA0_Channel5: InterruptVector = unhandled, - DMA0_Channel6: InterruptVector = unhandled, - ADC0_1: InterruptVector = unhandled, - CAN0_TX: InterruptVector = unhandled, - CAN0_RX0: InterruptVector = unhandled, - CAN0_RX1: InterruptVector = unhandled, - CAN0_EWMC: InterruptVector = unhandled, - EXTI_line9_5: InterruptVector = unhandled, - TIMER0_BRK: InterruptVector = unhandled, - TIMER0_UP: InterruptVector = unhandled, - TIMER0_TRG_CMT: InterruptVector = unhandled, - TIMER0_Channel: InterruptVector = unhandled, - TIMER1: InterruptVector = unhandled, - TIMER2: InterruptVector = unhandled, - TIMER3: InterruptVector = unhandled, - I2C0_EV: InterruptVector = unhandled, - I2C0_ER: InterruptVector = unhandled, - I2C1_EV: InterruptVector = unhandled, - I2C1_ER: InterruptVector = unhandled, - SPI0: InterruptVector = unhandled, - SPI1: InterruptVector = unhandled, - USART0: InterruptVector = unhandled, - USART1: InterruptVector = unhandled, - USART2: InterruptVector = unhandled, - EXTI_line15_10: InterruptVector = unhandled, - RTC_Alarm: InterruptVector = unhandled, - USBFS_WKUP: InterruptVector = unhandled, - reserved17: u32 = undefined, - reserved18: u32 = undefined, - reserved19: u32 = undefined, - reserved20: u32 = undefined, - reserved21: u32 = undefined, - reserved22: u32 = undefined, - reserved23: u32 = undefined, - TIMER4: InterruptVector = unhandled, - SPI2: InterruptVector = unhandled, - UART3: InterruptVector = unhandled, - UART4: InterruptVector = unhandled, - TIMER5: InterruptVector = unhandled, - TIMER6: InterruptVector = unhandled, - DMA1_Channel0: InterruptVector = unhandled, - DMA1_Channel1: InterruptVector = unhandled, - DMA1_Channel2: InterruptVector = unhandled, - DMA1_Channel3: InterruptVector = unhandled, - DMA1_Channel4: InterruptVector = unhandled, - reserved24: u32 = undefined, - reserved25: u32 = undefined, - CAN1_TX: InterruptVector = unhandled, - CAN1_RX0: InterruptVector = unhandled, - CAN1_RX1: InterruptVector = unhandled, - CAN1_EWMC: InterruptVector = unhandled, - USBFS: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// System Control Space - pub const SCS = struct { - pub const base_address = 0xe000e000; - - /// System Tick Timer - pub const SysTick = struct { - /// address: 0xe000e010 - /// SysTick Control and Status Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0xe000e014 - /// SysTick Reload Value Register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x14); - - /// address: 0xe000e018 - /// SysTick Current Value Register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000e01c - /// SysTick Calibration Register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - SKEW: u1, - NOREF: u1, - }), base_address + 0x1c); - }; - }; - - /// Analog to digital converter - pub const ADC0 = struct { - pub const base_address = 0x40012400; - - /// address: 0x40012400 - /// status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog event flag - WDE: u1, - /// End of group conversion flag - EOC: u1, - /// End of inserted group conversion flag - EOIC: u1, - /// Start flag of inserted channel group - STIC: u1, - /// Start flag of regular channel group - STRC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40012404 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - WDCHSEL: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Interrupt enable for WDE - WDEIE: u1, - /// Interrupt enable for EOIC - EOICIE: u1, - /// Scan mode - SM: u1, - /// When in scan mode, analog watchdog - /// is effective on a single channel - WDSC: u1, - /// Inserted channel group convert - /// automatically - ICA: u1, - /// Discontinuous mode on regular - /// channels - DISRC: u1, - /// Discontinuous mode on - /// inserted channels - DISIC: u1, - /// Number of conversions in - /// discontinuous mode - DISNUM: u3, - /// sync mode selection - SYNCM: u4, - reserved0: u1, - reserved1: u1, - /// Inserted channel analog watchdog - /// enable - IWDEN: u1, - /// Regular channel analog watchdog enable - RWDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012408 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADC on - ADCON: u1, - /// Continuous mode - CTN: u1, - /// ADC calibration - CLB: u1, - /// Reset calibration - RSTCLB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DMA request enable - DMA: u1, - reserved4: u1, - reserved5: u1, - /// Data alignment - DAL: u1, - /// External trigger select for inserted channel - ETSIC: u3, - /// External trigger select for inserted channel - ETEIC: u1, - reserved6: u1, - /// External trigger select for regular channel - ETSRC: u3, - /// External trigger enable for regular channel - ETERC: u1, - /// Start on inserted channel - SWICST: u1, - /// Start on regular channel - SWRCST: u1, - /// Channel 16 and 17 enable of ADC0 - TSVREN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4001240c - /// Sample time register 0 - pub const SAMPT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 10 sample time - /// selection - SPT10: u3, - /// Channel 11 sample time - /// selection - SPT11: u3, - /// Channel 12 sample time - /// selection - SPT12: u3, - /// Channel 13 sample time - /// selection - SPT13: u3, - /// Channel 14 sample time - /// selection - SPT14: u3, - /// Channel 15 sample time - /// selection - SPT15: u3, - /// Channel 16 sample time - /// selection - SPT16: u3, - /// Channel 17 sample time - /// selection - SPT17: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40012410 - /// Sample time register 1 - pub const SAMPT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 sample time - /// selection - SPT0: u3, - /// Channel 1 sample time - /// selection - SPT1: u3, - /// Channel 2 sample time - /// selection - SPT2: u3, - /// Channel 3 sample time - /// selection - SPT3: u3, - /// Channel 4 sample time - /// selection - SPT4: u3, - /// Channel 5 sample time - /// selection - SPT5: u3, - /// Channel 6 sample time - /// selection - SPT6: u3, - /// Channel 7 sample time - /// selection - SPT7: u3, - /// Channel 8 sample time - /// selection - SPT8: u3, - /// Channel 9 sample time - /// selection - SPT9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40012414 - /// Inserted channel data offset register - /// 0 - pub const IOFF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 0 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012418 - /// Inserted channel data offset register - /// 1 - pub const IOFF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 1 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001241c - /// Inserted channel data offset register - /// 2 - pub const IOFF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 2 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012420 - /// Inserted channel data offset register - /// 3 - pub const IOFF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 3 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012424 - /// watchdog higher threshold - /// register - pub const WDHT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x24); - - /// address: 0x40012428 - /// watchdog lower threshold - /// register - pub const WDLT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x28); - - /// address: 0x4001242c - /// regular sequence register 0 - pub const RSQ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - RSQ12: u5, - /// 14th conversion in regular - /// sequence - RSQ13: u5, - /// 15th conversion in regular - /// sequence - RSQ14: u5, - /// 16th conversion in regular - /// sequence - RSQ15: u5, - /// Regular channel group - /// length - RL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012430 - /// regular sequence register 1 - pub const RSQ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - RSQ6: u5, - /// 8th conversion in regular - /// sequence - RSQ7: u5, - /// 9th conversion in regular - /// sequence - RSQ8: u5, - /// 10th conversion in regular - /// sequence - RSQ9: u5, - /// 11th conversion in regular - /// sequence - RSQ10: u5, - /// 12th conversion in regular - /// sequence - RSQ11: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012434 - /// regular sequence register 2 - pub const RSQ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - RSQ0: u5, - /// 2nd conversion in regular - /// sequence - RSQ1: u5, - /// 3rd conversion in regular - /// sequence - RSQ2: u5, - /// 4th conversion in regular - /// sequence - RSQ3: u5, - /// 5th conversion in regular - /// sequence - RSQ4: u5, - /// 6th conversion in regular - /// sequence - RSQ5: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012438 - /// Inserted sequence register - pub const ISQ = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in inserted - /// sequence - ISQ0: u5, - /// 2nd conversion in inserted - /// sequence - ISQ1: u5, - /// 3rd conversion in inserted - /// sequence - ISQ2: u5, - /// 4th conversion in inserted - /// sequence - ISQ3: u5, - /// Inserted channel group length - IL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001243c - /// Inserted data register 0 - pub const IDATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012440 - /// Inserted data register 1 - pub const IDATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012444 - /// Inserted data register 2 - pub const IDATA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012448 - /// Inserted data register 3 - pub const IDATA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001244c - /// regular data register - pub const RDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular channel data - RDATA: u16, - /// ADC regular channel data - ADC1RDTR: u16, - }), base_address + 0x4c); - - /// address: 0x40012480 - /// Oversample control register - pub const OVSAMPCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Oversampler Enable - OVSEN: u1, - reserved0: u1, - /// Oversampling ratio - OVSR: u3, - /// Oversampling shift - OVSS: u4, - /// Triggered Oversampling - TOVS: u1, - reserved1: u1, - reserved2: u1, - /// ADC resolution - DRES: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x80); - }; - - /// Analog to digital converter - pub const ADC1 = struct { - pub const base_address = 0x40012800; - - /// address: 0x40012800 - /// status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog event flag - WDE: u1, - /// End of group conversion flag - EOC: u1, - /// End of inserted group conversion flag - EOIC: u1, - /// Start flag of inserted channel group - STIC: u1, - /// Start flag of regular channel group - STRC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40012804 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - WDCHSEL: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Interrupt enable for WDE - WDEIE: u1, - /// Interrupt enable for EOIC - EOICIE: u1, - /// Scan mode - SM: u1, - /// When in scan mode, analog watchdog - /// is effective on a single channel - WDSC: u1, - /// Inserted channel group convert - /// automatically - ICA: u1, - /// Discontinuous mode on regular - /// channels - DISRC: u1, - /// Discontinuous mode on - /// inserted channels - DISIC: u1, - /// Number of conversions in - /// discontinuous mode - DISNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Inserted channel analog watchdog - /// enable - IWDEN: u1, - /// Regular channel analog watchdog - /// enable - RWDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012808 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADC on - ADCON: u1, - /// Continuous mode - CTN: u1, - /// ADC calibration - CLB: u1, - /// Reset calibration - RSTCLB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DMA request enable - DMA: u1, - reserved4: u1, - reserved5: u1, - /// Data alignment - DAL: u1, - /// External trigger select for inserted channel - ETSIC: u3, - /// External trigger enable for inserted channel - ETEIC: u1, - reserved6: u1, - /// External trigger select for regular channel - ETSRC: u3, - /// External trigger enable for regular channel - ETERC: u1, - /// Start on inserted channel - SWICST: u1, - /// Start on regular channel - SWRCST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x4001280c - /// Sample time register 0 - pub const SAMPT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 10 sample time - /// selection - SPT10: u3, - /// Channel 11 sample time - /// selection - SPT11: u3, - /// Channel 12 sample time - /// selection - SPT12: u3, - /// Channel 13 sample time - /// selection - SPT13: u3, - /// Channel 14 sample time - /// selection - SPT14: u3, - /// Channel 15 sample time - /// selection - SPT15: u3, - /// Channel 16 sample time - /// selection - SPT16: u3, - /// Channel 17 sample time - /// selection - SPT17: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40012810 - /// Sample time register 1 - pub const SAMPT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 sample time - /// selection - SPT0: u3, - /// Channel 1 sample time - /// selection - SPT1: u3, - /// Channel 2 sample time - /// selection - SPT2: u3, - /// Channel 3 sample time - /// selection - SPT3: u3, - /// Channel 4 sample time - /// selection - SPT4: u3, - /// Channel 5 sample time - /// selection - SPT5: u3, - /// Channel 6 sample time - /// selection - SPT6: u3, - /// Channel 7 sample time - /// selection - SPT7: u3, - /// Channel 8 sample time - /// selection - SPT8: u3, - /// Channel 9 sample time - /// selection - SPT9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40012814 - /// Inserted channel data offset register - /// 0 - pub const IOFF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 0 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012818 - /// Inserted channel data offset register - /// 1 - pub const IOFF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 1 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001281c - /// Inserted channel data offset register - /// 2 - pub const IOFF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 2 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012820 - /// Inserted channel data offset register - /// 3 - pub const IOFF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for inserted channel - /// 3 - IOFF: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012824 - /// watchdog higher threshold - /// register - pub const WDHT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x24); - - /// address: 0x40012828 - /// watchdog lower threshold - /// register - pub const WDLT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x28); - - /// address: 0x4001282c - /// regular sequence register 0 - pub const RSQ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - RSQ12: u5, - /// 14th conversion in regular - /// sequence - RSQ13: u5, - /// 15th conversion in regular - /// sequence - RSQ14: u5, - /// 16th conversion in regular - /// sequence - RSQ15: u5, - /// Regular channel group - /// length - RL: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012830 - /// regular sequence register 1 - pub const RSQ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - RSQ6: u5, - /// 8th conversion in regular - /// sequence - RSQ7: u5, - /// 9th conversion in regular - /// sequence - RSQ8: u5, - /// 10th conversion in regular - /// sequence - RSQ9: u5, - /// 11th conversion in regular - /// sequence - RSQ10: u5, - /// 12th conversion in regular - /// sequence - RSQ11: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012834 - /// regular sequence register 2 - pub const RSQ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - RSQ0: u5, - /// 2nd conversion in regular - /// sequence - RSQ1: u5, - /// 3rd conversion in regular - /// sequence - RSQ2: u5, - /// 4th conversion in regular - /// sequence - RSQ3: u5, - /// 5th conversion in regular - /// sequence - RSQ4: u5, - /// 6th conversion in regular - /// sequence - RSQ5: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012838 - /// Inserted sequence register - pub const ISQ = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in inserted - /// sequence - ISQ0: u5, - /// 2nd conversion in inserted - /// sequence - ISQ1: u5, - /// 3rd conversion in inserted - /// sequence - ISQ2: u5, - /// 4th conversion in inserted - /// sequence - ISQ3: u5, - /// Inserted channel group length - IL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001283c - /// Inserted data register 0 - pub const IDATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012840 - /// Inserted data register 1 - pub const IDATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012844 - /// Inserted data register 2 - pub const IDATA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012848 - /// Inserted data register 3 - pub const IDATA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Inserted number n conversion data - IDATAn: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001284c - /// regular data register - pub const RDATA = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c); - }; - - /// Alternate-function I/Os - pub const AFIO = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// Event control register - pub const EC = @intToPtr(*volatile Mmio(32, packed struct { - /// Event output pin selection - PIN: u4, - /// Event output port selection - PORT: u3, - /// Event output enable - EOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40010004 - /// AFIO port configuration register 0 - pub const PCF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SPI0 remapping - SPI0_REMAP: u1, - /// I2C0 remapping - I2C0_REMAP: u1, - /// USART0 remapping - USART0_REMAP: u1, - /// USART1 remapping - USART1_REMAP: u1, - /// USART2 remapping - USART2_REMAP: u2, - /// TIMER0 remapping - TIMER0_REMAP: u2, - /// TIMER1 remapping - TIMER1_REMAP: u2, - /// TIMER2 remapping - TIMER2_REMAP: u2, - /// TIMER3 remapping - TIMER3_REMAP: u1, - /// CAN0 alternate interface remapping - CAN0_REMAP: u2, - /// Port D0/Port D1 mapping on OSC_IN/OSC_OUT - PD01_REMAP: u1, - /// TIMER4 channel3 internal remapping - TIMER4CH3_IREMAP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// CAN1 I/O remapping - CAN1_REMAP: u1, - reserved5: u1, - /// Serial wire JTAG configuration - SWJ_CFG: u3, - reserved6: u1, - /// SPI2/I2S2 remapping - SPI2_REMAP: u1, - /// TIMER1 internal trigger 1 remapping - TIMER1ITI1_REMAP: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0x40010008 - /// EXTI sources selection register 0 - pub const EXTISS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 0 sources selection - EXTI0_SS: u4, - /// EXTI 1 sources selection - EXTI1_SS: u4, - /// EXTI 2 sources selection - EXTI2_SS: u4, - /// EXTI 3 sources selection - EXTI3_SS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001000c - /// EXTI sources selection register 1 - pub const EXTISS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 4 sources selection - EXTI4_SS: u4, - /// EXTI 5 sources selection - EXTI5_SS: u4, - /// EXTI 6 sources selection - EXTI6_SS: u4, - /// EXTI 7 sources selection - EXTI7_SS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// EXTI sources selection register 2 - pub const EXTISS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 8 sources selection - EXTI8_SS: u4, - /// EXTI 9 sources selection - EXTI9_SS: u4, - /// EXTI 10 sources selection - EXTI10_SS: u4, - /// EXTI 11 sources selection - EXTI11_SS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40010014 - /// EXTI sources selection register 3 - pub const EXTISS3 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 12 sources selection - EXTI12_SS: u4, - /// EXTI 13 sources selection - EXTI13_SS: u4, - /// EXTI 14 sources selection - EXTI14_SS: u4, - /// EXTI 15 sources selection - EXTI15_SS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x4001001c - /// AFIO port configuration register 1 - pub const PCF1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// EXMC_NADV connect/disconnect - EXMC_NADV: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c); - }; - - /// Backup registers - pub const BKP = struct { - pub const base_address = 0x40006c00; - - /// address: 0x40006c04 - /// Backup data register 0 - pub const DATA0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x4); - - /// address: 0x40006c08 - /// Backup data register 1 - pub const DATA1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x8); - - /// address: 0x40006c0c - /// Backup data register 2 - pub const DATA2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xc); - - /// address: 0x40006c10 - /// Backup data register 3 - pub const DATA3 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x10); - - /// address: 0x40006c14 - /// Backup data register 4 - pub const DATA4 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x14); - - /// address: 0x40006c18 - /// Backup data register 5 - pub const DATA5 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x18); - - /// address: 0x40006c1c - /// Backup data register 6 - pub const DATA6 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x1c); - - /// address: 0x40006c20 - /// Backup data register 7 - pub const DATA7 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x20); - - /// address: 0x40006c24 - /// Backup data register 8 - pub const DATA8 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x24); - - /// address: 0x40006c28 - /// Backup data register 9 - pub const DATA9 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x28); - - /// address: 0x40006c40 - /// Backup data register 10 - pub const DATA10 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x40); - - /// address: 0x40006c44 - /// Backup data register 11 - pub const DATA11 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x44); - - /// address: 0x40006c48 - /// Backup data register 12 - pub const DATA12 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x48); - - /// address: 0x40006c4c - /// Backup data register 13 - pub const DATA13 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x4c); - - /// address: 0x40006c50 - /// Backup data register 14 - pub const DATA14 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x50); - - /// address: 0x40006c54 - /// Backup data register 15 - pub const DATA15 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x54); - - /// address: 0x40006c58 - /// Backup data register 16 - pub const DATA16 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x58); - - /// address: 0x40006c5c - /// Backup data register 17 - pub const DATA17 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x5c); - - /// address: 0x40006c60 - /// Backup data register 18 - pub const DATA18 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x60); - - /// address: 0x40006c64 - /// Backup data register 19 - pub const DATA19 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x64); - - /// address: 0x40006c68 - /// Backup data register 20 - pub const DATA20 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x68); - - /// address: 0x40006c6c - /// Backup data register 21 - pub const DATA21 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x6c); - - /// address: 0x40006c70 - /// Backup data register 22 - pub const DATA22 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x70); - - /// address: 0x40006c74 - /// Backup data register 23 - pub const DATA23 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x74); - - /// address: 0x40006c78 - /// Backup data register 24 - pub const DATA24 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x78); - - /// address: 0x40006c7c - /// Backup data register 25 - pub const DATA25 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x7c); - - /// address: 0x40006c80 - /// Backup data register 26 - pub const DATA26 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x80); - - /// address: 0x40006c84 - /// Backup data register 27 - pub const DATA27 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x84); - - /// address: 0x40006c88 - /// Backup data register 28 - pub const DATA28 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x88); - - /// address: 0x40006c8c - /// Backup data register 29 - pub const DATA29 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x8c); - - /// address: 0x40006c90 - /// Backup data register 30 - pub const DATA30 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x90); - - /// address: 0x40006c94 - /// Backup data register 31 - pub const DATA31 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x94); - - /// address: 0x40006c98 - /// Backup data register 32 - pub const DATA32 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x98); - - /// address: 0x40006c9c - /// Backup data register 33 - pub const DATA33 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0x9c); - - /// address: 0x40006ca0 - /// Backup data register 34 - pub const DATA34 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xa0); - - /// address: 0x40006ca4 - /// Backup data register 35 - pub const DATA35 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xa4); - - /// address: 0x40006ca8 - /// Backup data register 36 - pub const DATA36 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xa8); - - /// address: 0x40006cac - /// Backup data register 37 - pub const DATA37 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xac); - - /// address: 0x40006cb0 - /// Backup data register 38 - pub const DATA38 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xb0); - - /// address: 0x40006cb4 - /// Backup data register 39 - pub const DATA39 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xb4); - - /// address: 0x40006cb8 - /// Backup data register 40 - pub const DATA40 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xb8); - - /// address: 0x40006cbc - /// Backup data register 41 - pub const DATA41 = @intToPtr(*volatile Mmio(16, packed struct { - /// Backup data - DATA: u16, - }), base_address + 0xbc); - - /// address: 0x40006c2c - /// RTC signal output control register - pub const OCTL = @intToPtr(*volatile Mmio(16, packed struct { - /// RTC clock calibration value - RCCV: u7, - /// RTC clock calibration output enable - COEN: u1, - /// RTC alarm or second signal output enable - ASOEN: u1, - /// RTC output selection - ROSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x2c); - - /// address: 0x40006c30 - /// Tamper pin control register - pub const TPCTL = @intToPtr(*volatile Mmio(16, packed struct { - /// TAMPER detection enable - TPEN: u1, - /// TAMPER pin active level - TPAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x30); - - /// address: 0x40006c34 - /// Tamper control and status register - pub const TPCS = @intToPtr(*volatile Mmio(16, packed struct { - /// Tamper event reset - TER: u1, - /// Tamper interrupt reset - TIR: u1, - /// Tamper interrupt enable - TPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Tamper event flag - TEF: u1, - /// Tamper interrupt flag - TIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x34); - }; - - /// Controller area network - pub const CAN0 = struct { - pub const base_address = 0x40006400; - - /// address: 0x40006400 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Initial working mode - IWMOD: u1, - /// Sleep working mode - SLPWMOD: u1, - /// Transmit FIFO order - TFO: u1, - /// Receive FIFO overwrite disable - RFOD: u1, - /// Automatic retransmission disable - ARD: u1, - /// Automatic wakeup - AWU: u1, - /// Automatic bus-off recovery - ABOR: u1, - /// Time-triggered communication - TTC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Software reset - SWRST: u1, - /// Debug freeze - DFZ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006404 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Initial working state - IWS: u1, - /// Sleep working state - SLPWS: u1, - /// Error interrupt flag - ERRIF: u1, - /// Status change interrupt flag of wakeup - /// from sleep working mode - WUIF: u1, - /// Status change interrupt flag of sleep - /// working mode entering - SLPIF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Transmitting state - TS: u1, - /// Receiving state - RS: u1, - /// Last sample value of RX pin - LASTRX: u1, - /// RX level - RXL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006408 - /// Transmit status register - pub const TSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Mailbox 0 transmit finished - MTF0: u1, - /// Mailbox 0 transmit finished and no error - MTFNERR0: u1, - /// Mailbox 0 arbitration lost - MAL0: u1, - /// Mailbox 0 transmit error - MTE0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Mailbox 0 stop transmitting - MST0: u1, - /// Mailbox 1 transmit finished - MTF1: u1, - /// Mailbox 1 transmit finished and no error - MTFNERR1: u1, - /// Mailbox 1 arbitration lost - MAL1: u1, - /// Mailbox 1 transmit error - MTE1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Mailbox 1 stop transmitting - MST1: u1, - /// Mailbox 2 transmit finished - MTF2: u1, - /// Mailbox 2 transmit finished and no error - MTFNERR2: u1, - /// Mailbox 2 arbitration lost - MAL2: u1, - /// Mailbox 2 transmit error - MTE2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mailbox 2 stop transmitting - MST2: u1, - /// number of the transmit FIFO mailbox in - /// which the frame will be transmitted if at least one mailbox is empty - NUM: u2, - /// Transmit mailbox 0 empty - TME0: u1, - /// Transmit mailbox 1 empty - TME1: u1, - /// Transmit mailbox 2 empty - TME2: u1, - /// Transmit mailbox 0 last sending - /// in transmit FIFO - TMLS0: u1, - /// Transmit mailbox 1 last sending - /// in transmit FIFO - TMLS1: u1, - /// Transmit mailbox 2 last sending - /// in transmit FIFO - TMLS2: u1, - }), base_address + 0x8); - - /// address: 0x4000640c - /// Receive message FIFO0 register - pub const RFIFO0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive FIFO0 length - RFL0: u2, - reserved0: u1, - /// Receive FIFO0 full - RFF0: u1, - /// Receive FIFO0 overfull - RFO0: u1, - /// Receive FIFO0 dequeue - RFD0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006410 - /// Receive message FIFO1 register - pub const RFIFO1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive FIFO1 length - RFL1: u2, - reserved0: u1, - /// Receive FIFO1 full - RFF1: u1, - /// Receive FIFO1 overfull - RFO1: u1, - /// Receive FIFO1 dequeue - RFD1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006414 - /// Interrupt enable register - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit mailbox empty interrupt enable - TMEIE: u1, - /// Receive FIFO0 not empty interrupt enable - RFNEIE0: u1, - /// Receive FIFO0 full interrupt enable - RFFIE0: u1, - /// Receive FIFO0 overfull interrupt enable - RFOIE0: u1, - /// Receive FIFO1 not empty interrupt enable - RFNEIE1: u1, - /// Receive FIFO1 full interrupt enable - RFFIE1: u1, - /// Receive FIFO1 overfull interrupt enable - RFOIE1: u1, - reserved0: u1, - /// Warning error interrupt enable - WERRIE: u1, - /// Passive error interrupt enable - PERRIE: u1, - /// Bus-off interrupt enable - BOIE: u1, - /// Error number interrupt enable - ERRNIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Error interrupt enable - ERRIE: u1, - /// Wakeup interrupt enable - WIE: u1, - /// Sleep working interrupt enable - SLPWIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006418 - /// Error register - pub const ERR = @intToPtr(*volatile Mmio(32, packed struct { - /// Warning error - WERR: u1, - /// Passive error - PERR: u1, - /// Bus-off error - BOERR: u1, - reserved0: u1, - /// Error number - ERRN: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Transmit Error Count defined - /// by the CAN standard - TECNT: u8, - /// Receive Error Count defined - /// by the CAN standard - RECNT: u8, - }), base_address + 0x18); - - /// address: 0x4000641c - /// Bit timing register - pub const BT = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud rate prescaler - BAUDPSC: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Bit segment 1 - BS1: u4, - /// Bit segment 2 - BS2: u3, - reserved6: u1, - /// Resynchronization jump width - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Loopback communication mode - LCMOD: u1, - /// Silent communication mode - SCMOD: u1, - }), base_address + 0x1c); - - /// address: 0x40006580 - /// Transmit mailbox identifier register 0 - pub const TMI0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x180); - - /// address: 0x40006584 - /// Transmit mailbox property register 0 - pub const TMP0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x184); - - /// address: 0x40006588 - /// Transmit mailbox data0 register - pub const TMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x188); - - /// address: 0x4000658c - /// Transmit mailbox data1 register - pub const TMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x18c); - - /// address: 0x40006590 - /// Transmit mailbox identifier register 1 - pub const TMI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x190); - - /// address: 0x40006594 - /// Transmit mailbox property register 1 - pub const TMP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x194); - - /// address: 0x40006598 - /// Transmit mailbox data0 register - pub const TMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x198); - - /// address: 0x4000659c - /// Transmit mailbox data1 register - pub const TMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x19c); - - /// address: 0x400065a0 - /// Transmit mailbox identifier register 2 - pub const TMI2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1a0); - - /// address: 0x400065a4 - /// Transmit mailbox property register 2 - pub const TMP2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x1a4); - - /// address: 0x400065a8 - /// Transmit mailbox data0 register - pub const TMDATA02 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1a8); - - /// address: 0x400065ac - /// Transmit mailbox data1 register - pub const TMDATA12 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1ac); - - /// address: 0x400065b0 - /// Receive FIFO mailbox identifier register - pub const RFIFOMI0 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1b0); - - /// address: 0x400065b4 - /// Receive FIFO0 mailbox property register - pub const RFIFOMP0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), base_address + 0x1b4); - - /// address: 0x400065b8 - /// Receive FIFO0 mailbox data0 register - pub const RFIFOMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1b8); - - /// address: 0x400065bc - /// Receive FIFO0 mailbox data1 register - pub const RFIFOMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1bc); - - /// address: 0x400065c0 - /// Receive FIFO1 mailbox identifier register - pub const RFIFOMI1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1c0); - - /// address: 0x400065c4 - /// Receive FIFO1 mailbox property register - pub const RFIFOMP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), base_address + 0x1c4); - - /// address: 0x400065c8 - /// Receive FIFO1 mailbox data0 register - pub const RFIFOMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1c8); - - /// address: 0x400065cc - /// Receive FIFO1 mailbox data1 register - pub const RFIFOMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006600 - /// Filter control register - pub const FCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter lock disable - FLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Header bank of CAN1 filter - HBC1F: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006604 - /// Filter mode configuration register - pub const FMCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FMOD0: u1, - /// Filter mode - FMOD1: u1, - /// Filter mode - FMOD2: u1, - /// Filter mode - FMOD3: u1, - /// Filter mode - FMOD4: u1, - /// Filter mode - FMOD5: u1, - /// Filter mode - FMOD6: u1, - /// Filter mode - FMOD7: u1, - /// Filter mode - FMOD8: u1, - /// Filter mode - FMOD9: u1, - /// Filter mode - FMOD10: u1, - /// Filter mode - FMOD11: u1, - /// Filter mode - FMOD12: u1, - /// Filter mode - FMOD13: u1, - /// Filter mode - FMOD14: u1, - /// Filter mode - FMOD15: u1, - /// Filter mode - FMOD16: u1, - /// Filter mode - FMOD17: u1, - /// Filter mode - FMOD18: u1, - /// Filter mode - FMOD19: u1, - /// Filter mode - FMOD20: u1, - /// Filter mode - FMOD21: u1, - /// Filter mode - FMOD22: u1, - /// Filter mode - FMOD23: u1, - /// Filter mode - FMOD24: u1, - /// Filter mode - FMOD25: u1, - /// Filter mode - FMOD26: u1, - /// Filter mode - FMOD27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x4000660c - /// Filter scale configuration register - pub const FSCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FS0: u1, - /// Filter scale configuration - FS1: u1, - /// Filter scale configuration - FS2: u1, - /// Filter scale configuration - FS3: u1, - /// Filter scale configuration - FS4: u1, - /// Filter scale configuration - FS5: u1, - /// Filter scale configuration - FS6: u1, - /// Filter scale configuration - FS7: u1, - /// Filter scale configuration - FS8: u1, - /// Filter scale configuration - FS9: u1, - /// Filter scale configuration - FS10: u1, - /// Filter scale configuration - FS11: u1, - /// Filter scale configuration - FS12: u1, - /// Filter scale configuration - FS13: u1, - /// Filter scale configuration - FS14: u1, - /// Filter scale configuration - FS15: u1, - /// Filter scale configuration - FS16: u1, - /// Filter scale configuration - FS17: u1, - /// Filter scale configuration - FS18: u1, - /// Filter scale configuration - FS19: u1, - /// Filter scale configuration - FS20: u1, - /// Filter scale configuration - FS21: u1, - /// Filter scale configuration - FS22: u1, - /// Filter scale configuration - FS23: u1, - /// Filter scale configuration - FS24: u1, - /// Filter scale configuration - FS25: u1, - /// Filter scale configuration - FS26: u1, - /// Filter scale configuration - FS27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006614 - /// Filter associated FIFO register - pub const FAFIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter 0 associated with FIFO - FAF0: u1, - /// Filter 1 associated with FIFO - FAF1: u1, - /// Filter 2 associated with FIFO - FAF2: u1, - /// Filter 3 associated with FIFO - FAF3: u1, - /// Filter 4 associated with FIFO - FAF4: u1, - /// Filter 5 associated with FIFO - FAF5: u1, - /// Filter 6 associated with FIFO - FAF6: u1, - /// Filter 7 associated with FIFO - FAF7: u1, - /// Filter 8 associated with FIFO - FAF8: u1, - /// Filter 9 associated with FIFO - FAF9: u1, - /// Filter 10 associated with FIFO - FAF10: u1, - /// Filter 11 associated with FIFO - FAF11: u1, - /// Filter 12 associated with FIFO - FAF12: u1, - /// Filter 13 associated with FIFO - FAF13: u1, - /// Filter 14 associated with FIFO - FAF14: u1, - /// Filter 15 associated with FIFO - FAF15: u1, - /// Filter 16 associated with FIFO - FAF16: u1, - /// Filter 17 associated with FIFO - FAF17: u1, - /// Filter 18 associated with FIFO - FAF18: u1, - /// Filter 19 associated with FIFO - FAF19: u1, - /// Filter 20 associated with FIFO - FAF20: u1, - /// Filter 21 associated with FIFO - FAF21: u1, - /// Filter 22 associated with FIFO - FAF22: u1, - /// Filter 23 associated with FIFO - FAF23: u1, - /// Filter 24 associated with FIFO - FAF24: u1, - /// Filter 25 associated with FIFO - FAF25: u1, - /// Filter 26 associated with FIFO - FAF26: u1, - /// Filter 27 associated with FIFO - FAF27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x4000661c - /// Filter working register - pub const FW = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter working - FW0: u1, - /// Filter working - FW1: u1, - /// Filter working - FW2: u1, - /// Filter working - FW3: u1, - /// Filter working - FW4: u1, - /// Filter working - FW5: u1, - /// Filter working - FW6: u1, - /// Filter working - FW7: u1, - /// Filter working - FW8: u1, - /// Filter working - FW9: u1, - /// Filter working - FW10: u1, - /// Filter working - FW11: u1, - /// Filter working - FW12: u1, - /// Filter working - FW13: u1, - /// Filter working - FW14: u1, - /// Filter working - FW15: u1, - /// Filter working - FW16: u1, - /// Filter working - FW17: u1, - /// Filter working - FW18: u1, - /// Filter working - FW19: u1, - /// Filter working - FW20: u1, - /// Filter working - FW21: u1, - /// Filter working - FW22: u1, - /// Filter working - FW23: u1, - /// Filter working - FW24: u1, - /// Filter working - FW25: u1, - /// Filter working - FW26: u1, - /// Filter working - FW27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006640 - /// Filter 0 data 0 register - pub const F0DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x240); - - /// address: 0x40006644 - /// Filter 0 data 1 register - pub const F0DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x244); - - /// address: 0x40006648 - /// Filter 1 data 0 register - pub const F1DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x248); - - /// address: 0x4000664c - /// Filter 1 data 1 register - pub const F1DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x24c); - - /// address: 0x40006650 - /// Filter 2 data 0 register - pub const F2DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x250); - - /// address: 0x40006654 - /// Filter 2 data 1 register - pub const F2DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x254); - - /// address: 0x40006658 - /// Filter 3 data 0 register - pub const F3DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x258); - - /// address: 0x4000665c - /// Filter 3 data 1 register - pub const F3DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x25c); - - /// address: 0x40006660 - /// Filter 4 data 0 register - pub const F4DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x260); - - /// address: 0x40006664 - /// Filter 4 data 1 register - pub const F4DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x264); - - /// address: 0x40006668 - /// Filter 5 data 0 register - pub const F5DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x268); - - /// address: 0x4000666c - /// Filter 5 data 1 register - pub const F5DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x26c); - - /// address: 0x40006670 - /// Filter 6 data 0 register - pub const F6DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x270); - - /// address: 0x40006674 - /// Filter 6 data 1 register - pub const F6DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x274); - - /// address: 0x40006678 - /// Filter 7 data 0 register - pub const F7DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x278); - - /// address: 0x4000667c - /// Filter 7 data 1 register - pub const F7DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x27c); - - /// address: 0x40006680 - /// Filter 8 data 0 register - pub const F8DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x280); - - /// address: 0x40006684 - /// Filter 8 data 1 register - pub const F8DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x284); - - /// address: 0x40006688 - /// Filter 9 data 0 register - pub const F9DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x288); - - /// address: 0x4000668c - /// Filter 9 data 1 register - pub const F9DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x28c); - - /// address: 0x40006690 - /// Filter 10 data 0 register - pub const F10DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x290); - - /// address: 0x40006694 - /// Filter 10 data 1 register - pub const F10DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x294); - - /// address: 0x40006698 - /// Filter 11 data 0 register - pub const F11DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x298); - - /// address: 0x4000669c - /// Filter 11 data 1 register - pub const F11DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x29c); - - /// address: 0x400066a0 - /// Filter 12 data 0 register - pub const F12DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a0); - - /// address: 0x400066a4 - /// Filter 12 data 1 register - pub const F12DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a4); - - /// address: 0x400066a8 - /// Filter 13 data 0 register - pub const F13DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a8); - - /// address: 0x400066ac - /// Filter 13 data 1 register - pub const F13DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2ac); - - /// address: 0x400066b0 - /// Filter 14 data 0 register - pub const F14DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b0); - - /// address: 0x400066b4 - /// Filter 14 data 1 register - pub const F14DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b4); - - /// address: 0x400066b8 - /// Filter 15 data 0 register - pub const F15DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b8); - - /// address: 0x400066bc - /// Filter 15 data 1 register - pub const F15DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2bc); - - /// address: 0x400066c0 - /// Filter 16 data 0 register - pub const F16DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c0); - - /// address: 0x400066c4 - /// Filter 16 data 1 register - pub const F16DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c4); - - /// address: 0x400066c8 - /// Filter 17 data 0 register - pub const F17DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c8); - - /// address: 0x400066cc - /// Filter 17 data 1 register - pub const F17DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2cc); - - /// address: 0x400066d0 - /// Filter 18 data 0 register - pub const F18DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d0); - - /// address: 0x400066d4 - /// Filter 18 data 1 register - pub const F18DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d4); - - /// address: 0x400066d8 - /// Filter 19 data 0 register - pub const F19DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d8); - - /// address: 0x400066dc - /// Filter 19 data 1 register - pub const F19DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2dc); - - /// address: 0x400066e0 - /// Filter 20 data 0 register - pub const F20DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e0); - - /// address: 0x400066e4 - /// Filter 20 data 1 register - pub const F20DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e4); - - /// address: 0x400066e8 - /// Filter 21 data 0 register - pub const F21DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e8); - - /// address: 0x400066ec - /// Filter 21 data 1 register - pub const F21DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2ec); - - /// address: 0x400066f0 - /// Filter 22 data 0 register - pub const F22DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f0); - - /// address: 0x400066f4 - /// Filter 22 data 1 register - pub const F22DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f4); - - /// address: 0x400066f8 - /// Filter 23 data 0 register - pub const F23DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f8); - - /// address: 0x400066fc - /// Filter 23 data 1 register - pub const F23DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006700 - /// Filter 24 data 0 register - pub const F24DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x300); - - /// address: 0x40006704 - /// Filter 24 data 1 register - pub const F24DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x304); - - /// address: 0x40006708 - /// Filter 25 data 0 register - pub const F25DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x308); - - /// address: 0x4000670c - /// Filter 25 data 1 register - pub const F25DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x30c); - - /// address: 0x40006710 - /// Filter 26 data 0 register - pub const F26DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x310); - - /// address: 0x40006714 - /// Filter 26 data 1 register - pub const F26DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x314); - - /// address: 0x40006718 - /// Filter 27 data 0 register - pub const F27DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x318); - - /// address: 0x4000671c - /// Filter 27 data 1 register - pub const F27DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x31c); - }; - pub const CAN1 = struct { - pub const base_address = 0x40006800; - - /// address: 0x40006800 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Initial working mode - IWMOD: u1, - /// Sleep working mode - SLPWMOD: u1, - /// Transmit FIFO order - TFO: u1, - /// Receive FIFO overwrite disable - RFOD: u1, - /// Automatic retransmission disable - ARD: u1, - /// Automatic wakeup - AWU: u1, - /// Automatic bus-off recovery - ABOR: u1, - /// Time-triggered communication - TTC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Software reset - SWRST: u1, - /// Debug freeze - DFZ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006804 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Initial working state - IWS: u1, - /// Sleep working state - SLPWS: u1, - /// Error interrupt flag - ERRIF: u1, - /// Status change interrupt flag of wakeup - /// from sleep working mode - WUIF: u1, - /// Status change interrupt flag of sleep - /// working mode entering - SLPIF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Transmitting state - TS: u1, - /// Receiving state - RS: u1, - /// Last sample value of RX pin - LASTRX: u1, - /// RX level - RXL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006808 - /// Transmit status register - pub const TSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Mailbox 0 transmit finished - MTF0: u1, - /// Mailbox 0 transmit finished and no error - MTFNERR0: u1, - /// Mailbox 0 arbitration lost - MAL0: u1, - /// Mailbox 0 transmit error - MTE0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Mailbox 0 stop transmitting - MST0: u1, - /// Mailbox 1 transmit finished - MTF1: u1, - /// Mailbox 1 transmit finished and no error - MTFNERR1: u1, - /// Mailbox 1 arbitration lost - MAL1: u1, - /// Mailbox 1 transmit error - MTE1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Mailbox 1 stop transmitting - MST1: u1, - /// Mailbox 2 transmit finished - MTF2: u1, - /// Mailbox 2 transmit finished and no error - MTFNERR2: u1, - /// Mailbox 2 arbitration lost - MAL2: u1, - /// Mailbox 2 transmit error - MTE2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mailbox 2 stop transmitting - MST2: u1, - /// number of the transmit FIFO mailbox in - /// which the frame will be transmitted if at least one mailbox is empty - NUM: u2, - /// Transmit mailbox 0 empty - TME0: u1, - /// Transmit mailbox 1 empty - TME1: u1, - /// Transmit mailbox 2 empty - TME2: u1, - /// Transmit mailbox 0 last sending - /// in transmit FIFO - TMLS0: u1, - /// Transmit mailbox 1 last sending - /// in transmit FIFO - TMLS1: u1, - /// Transmit mailbox 2 last sending - /// in transmit FIFO - TMLS2: u1, - }), base_address + 0x8); - - /// address: 0x4000680c - /// Receive message FIFO0 register - pub const RFIFO0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive FIFO0 length - RFL0: u2, - reserved0: u1, - /// Receive FIFO0 full - RFF0: u1, - /// Receive FIFO0 overfull - RFO0: u1, - /// Receive FIFO0 dequeue - RFD0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006810 - /// Receive message FIFO1 register - pub const RFIFO1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive FIFO1 length - RFL1: u2, - reserved0: u1, - /// Receive FIFO1 full - RFF1: u1, - /// Receive FIFO1 overfull - RFO1: u1, - /// Receive FIFO1 dequeue - RFD1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006814 - /// Interrupt enable register - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit mailbox empty interrupt enable - TMEIE: u1, - /// Receive FIFO0 not empty interrupt enable - RFNEIE0: u1, - /// Receive FIFO0 full interrupt enable - RFFIE0: u1, - /// Receive FIFO0 overfull interrupt enable - RFOIE0: u1, - /// Receive FIFO1 not empty interrupt enable - RFNEIE1: u1, - /// Receive FIFO1 full interrupt enable - RFFIE1: u1, - /// Receive FIFO1 overfull interrupt enable - RFOIE1: u1, - reserved0: u1, - /// Warning error interrupt enable - WERRIE: u1, - /// Passive error interrupt enable - PERRIE: u1, - /// Bus-off interrupt enable - BOIE: u1, - /// Error number interrupt enable - ERRNIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Error interrupt enable - ERRIE: u1, - /// Wakeup interrupt enable - WIE: u1, - /// Sleep working interrupt enable - SLPWIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006818 - /// Error register - pub const ERR = @intToPtr(*volatile Mmio(32, packed struct { - /// Warning error - WERR: u1, - /// Passive error - PERR: u1, - /// Bus-off error - BOERR: u1, - reserved0: u1, - /// Error number - ERRN: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Transmit Error Count defined - /// by the CAN standard - TECNT: u8, - /// Receive Error Count defined - /// by the CAN standard - RECNT: u8, - }), base_address + 0x18); - - /// address: 0x4000681c - /// Bit timing register - pub const BT = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud rate prescaler - BAUDPSC: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Bit segment 1 - BS1: u4, - /// Bit segment 2 - BS2: u3, - reserved6: u1, - /// Resynchronization jump width - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Loopback communication mode - LCMOD: u1, - /// Silent communication mode - SCMOD: u1, - }), base_address + 0x1c); - - /// address: 0x40006980 - /// Transmit mailbox identifier register 0 - pub const TMI0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x180); - - /// address: 0x40006984 - /// Transmit mailbox property register 0 - pub const TMP0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x184); - - /// address: 0x40006988 - /// Transmit mailbox data0 register - pub const TMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x188); - - /// address: 0x4000698c - /// Transmit mailbox data1 register - pub const TMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x18c); - - /// address: 0x40006990 - /// Transmit mailbox identifier register 1 - pub const TMI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x190); - - /// address: 0x40006994 - /// Transmit mailbox property register 1 - pub const TMP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x194); - - /// address: 0x40006998 - /// Transmit mailbox data0 register - pub const TMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x198); - - /// address: 0x4000699c - /// Transmit mailbox data1 register - pub const TMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x19c); - - /// address: 0x400069a0 - /// Transmit mailbox identifier register 2 - pub const TMI2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1a0); - - /// address: 0x400069a4 - /// Transmit mailbox property register 2 - pub const TMP2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Time stamp enable - TSEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Time stamp - TS: u16, - }), base_address + 0x1a4); - - /// address: 0x400069a8 - /// Transmit mailbox data0 register - pub const TMDATA02 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1a8); - - /// address: 0x400069ac - /// Transmit mailbox data1 register - pub const TMDATA12 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1ac); - - /// address: 0x400069b0 - /// Receive FIFO mailbox identifier register - pub const RFIFOMI0 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1b0); - - /// address: 0x400069b4 - /// Receive FIFO0 mailbox property register - pub const RFIFOMP0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), base_address + 0x1b4); - - /// address: 0x400069b8 - /// Receive FIFO0 mailbox data0 register - pub const RFIFOMDATA00 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1b8); - - /// address: 0x400069bc - /// Receive FIFO0 mailbox data1 register - pub const RFIFOMDATA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1bc); - - /// address: 0x400069c0 - /// Receive FIFO1 mailbox identifier register - pub const RFIFOMI1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), base_address + 0x1c0); - - /// address: 0x400069c4 - /// Receive FIFO1 mailbox property register - pub const RFIFOMP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length code - DLENC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), base_address + 0x1c4); - - /// address: 0x400069c8 - /// Receive FIFO1 mailbox data0 register - pub const RFIFOMDATA01 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), base_address + 0x1c8); - - /// address: 0x400069cc - /// Receive FIFO1 mailbox data1 register - pub const RFIFOMDATA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006a00 - /// Filter control register - pub const FCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter lock disable - FLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Header bank of CAN1 filter - HBC1F: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006a04 - /// Filter mode configuration register - pub const FMCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FMOD0: u1, - /// Filter mode - FMOD1: u1, - /// Filter mode - FMOD2: u1, - /// Filter mode - FMOD3: u1, - /// Filter mode - FMOD4: u1, - /// Filter mode - FMOD5: u1, - /// Filter mode - FMOD6: u1, - /// Filter mode - FMOD7: u1, - /// Filter mode - FMOD8: u1, - /// Filter mode - FMOD9: u1, - /// Filter mode - FMOD10: u1, - /// Filter mode - FMOD11: u1, - /// Filter mode - FMOD12: u1, - /// Filter mode - FMOD13: u1, - /// Filter mode - FMOD14: u1, - /// Filter mode - FMOD15: u1, - /// Filter mode - FMOD16: u1, - /// Filter mode - FMOD17: u1, - /// Filter mode - FMOD18: u1, - /// Filter mode - FMOD19: u1, - /// Filter mode - FMOD20: u1, - /// Filter mode - FMOD21: u1, - /// Filter mode - FMOD22: u1, - /// Filter mode - FMOD23: u1, - /// Filter mode - FMOD24: u1, - /// Filter mode - FMOD25: u1, - /// Filter mode - FMOD26: u1, - /// Filter mode - FMOD27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x40006a0c - /// Filter scale configuration register - pub const FSCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FS0: u1, - /// Filter scale configuration - FS1: u1, - /// Filter scale configuration - FS2: u1, - /// Filter scale configuration - FS3: u1, - /// Filter scale configuration - FS4: u1, - /// Filter scale configuration - FS5: u1, - /// Filter scale configuration - FS6: u1, - /// Filter scale configuration - FS7: u1, - /// Filter scale configuration - FS8: u1, - /// Filter scale configuration - FS9: u1, - /// Filter scale configuration - FS10: u1, - /// Filter scale configuration - FS11: u1, - /// Filter scale configuration - FS12: u1, - /// Filter scale configuration - FS13: u1, - /// Filter scale configuration - FS14: u1, - /// Filter scale configuration - FS15: u1, - /// Filter scale configuration - FS16: u1, - /// Filter scale configuration - FS17: u1, - /// Filter scale configuration - FS18: u1, - /// Filter scale configuration - FS19: u1, - /// Filter scale configuration - FS20: u1, - /// Filter scale configuration - FS21: u1, - /// Filter scale configuration - FS22: u1, - /// Filter scale configuration - FS23: u1, - /// Filter scale configuration - FS24: u1, - /// Filter scale configuration - FS25: u1, - /// Filter scale configuration - FS26: u1, - /// Filter scale configuration - FS27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006a14 - /// Filter associated FIFO register - pub const FAFIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter 0 associated with FIFO - FAF0: u1, - /// Filter 1 associated with FIFO - FAF1: u1, - /// Filter 2 associated with FIFO - FAF2: u1, - /// Filter 3 associated with FIFO - FAF3: u1, - /// Filter 4 associated with FIFO - FAF4: u1, - /// Filter 5 associated with FIFO - FAF5: u1, - /// Filter 6 associated with FIFO - FAF6: u1, - /// Filter 7 associated with FIFO - FAF7: u1, - /// Filter 8 associated with FIFO - FAF8: u1, - /// Filter 9 associated with FIFO - FAF9: u1, - /// Filter 10 associated with FIFO - FAF10: u1, - /// Filter 11 associated with FIFO - FAF11: u1, - /// Filter 12 associated with FIFO - FAF12: u1, - /// Filter 13 associated with FIFO - FAF13: u1, - /// Filter 14 associated with FIFO - FAF14: u1, - /// Filter 15 associated with FIFO - FAF15: u1, - /// Filter 16 associated with FIFO - FAF16: u1, - /// Filter 17 associated with FIFO - FAF17: u1, - /// Filter 18 associated with FIFO - FAF18: u1, - /// Filter 19 associated with FIFO - FAF19: u1, - /// Filter 20 associated with FIFO - FAF20: u1, - /// Filter 21 associated with FIFO - FAF21: u1, - /// Filter 22 associated with FIFO - FAF22: u1, - /// Filter 23 associated with FIFO - FAF23: u1, - /// Filter 24 associated with FIFO - FAF24: u1, - /// Filter 25 associated with FIFO - FAF25: u1, - /// Filter 26 associated with FIFO - FAF26: u1, - /// Filter 27 associated with FIFO - FAF27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x40006a1c - /// Filter working register - pub const FW = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter working - FW0: u1, - /// Filter working - FW1: u1, - /// Filter working - FW2: u1, - /// Filter working - FW3: u1, - /// Filter working - FW4: u1, - /// Filter working - FW5: u1, - /// Filter working - FW6: u1, - /// Filter working - FW7: u1, - /// Filter working - FW8: u1, - /// Filter working - FW9: u1, - /// Filter working - FW10: u1, - /// Filter working - FW11: u1, - /// Filter working - FW12: u1, - /// Filter working - FW13: u1, - /// Filter working - FW14: u1, - /// Filter working - FW15: u1, - /// Filter working - FW16: u1, - /// Filter working - FW17: u1, - /// Filter working - FW18: u1, - /// Filter working - FW19: u1, - /// Filter working - FW20: u1, - /// Filter working - FW21: u1, - /// Filter working - FW22: u1, - /// Filter working - FW23: u1, - /// Filter working - FW24: u1, - /// Filter working - FW25: u1, - /// Filter working - FW26: u1, - /// Filter working - FW27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006a40 - /// Filter 0 data 0 register - pub const F0DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x240); - - /// address: 0x40006a44 - /// Filter 0 data 1 register - pub const F0DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x244); - - /// address: 0x40006a48 - /// Filter 1 data 0 register - pub const F1DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x248); - - /// address: 0x40006a4c - /// Filter 1 data 1 register - pub const F1DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x24c); - - /// address: 0x40006a50 - /// Filter 2 data 0 register - pub const F2DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x250); - - /// address: 0x40006a54 - /// Filter 2 data 1 register - pub const F2DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x254); - - /// address: 0x40006a58 - /// Filter 3 data 0 register - pub const F3DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x258); - - /// address: 0x40006a5c - /// Filter 3 data 1 register - pub const F3DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x25c); - - /// address: 0x40006a60 - /// Filter 4 data 0 register - pub const F4DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x260); - - /// address: 0x40006a64 - /// Filter 4 data 1 register - pub const F4DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x264); - - /// address: 0x40006a68 - /// Filter 5 data 0 register - pub const F5DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x268); - - /// address: 0x40006a6c - /// Filter 5 data 1 register - pub const F5DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x26c); - - /// address: 0x40006a70 - /// Filter 6 data 0 register - pub const F6DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x270); - - /// address: 0x40006a74 - /// Filter 6 data 1 register - pub const F6DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x274); - - /// address: 0x40006a78 - /// Filter 7 data 0 register - pub const F7DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x278); - - /// address: 0x40006a7c - /// Filter 7 data 1 register - pub const F7DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x27c); - - /// address: 0x40006a80 - /// Filter 8 data 0 register - pub const F8DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x280); - - /// address: 0x40006a84 - /// Filter 8 data 1 register - pub const F8DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x284); - - /// address: 0x40006a88 - /// Filter 9 data 0 register - pub const F9DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x288); - - /// address: 0x40006a8c - /// Filter 9 data 1 register - pub const F9DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x28c); - - /// address: 0x40006a90 - /// Filter 10 data 0 register - pub const F10DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x290); - - /// address: 0x40006a94 - /// Filter 10 data 1 register - pub const F10DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x294); - - /// address: 0x40006a98 - /// Filter 11 data 0 register - pub const F11DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x298); - - /// address: 0x40006a9c - /// Filter 11 data 1 register - pub const F11DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x29c); - - /// address: 0x40006aa0 - /// Filter 12 data 0 register - pub const F12DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a0); - - /// address: 0x40006aa4 - /// Filter 12 data 1 register - pub const F12DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a4); - - /// address: 0x40006aa8 - /// Filter 13 data 0 register - pub const F13DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2a8); - - /// address: 0x40006aac - /// Filter 13 data 1 register - pub const F13DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2ac); - - /// address: 0x40006ab0 - /// Filter 14 data 0 register - pub const F14DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b0); - - /// address: 0x40006ab4 - /// Filter 14 data 1 register - pub const F14DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b4); - - /// address: 0x40006ab8 - /// Filter 15 data 0 register - pub const F15DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2b8); - - /// address: 0x40006abc - /// Filter 15 data 1 register - pub const F15DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2bc); - - /// address: 0x40006ac0 - /// Filter 16 data 0 register - pub const F16DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c0); - - /// address: 0x40006ac4 - /// Filter 16 data 1 register - pub const F16DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c4); - - /// address: 0x40006ac8 - /// Filter 17 data 0 register - pub const F17DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2c8); - - /// address: 0x40006acc - /// Filter 17 data 1 register - pub const F17DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2cc); - - /// address: 0x40006ad0 - /// Filter 18 data 0 register - pub const F18DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d0); - - /// address: 0x40006ad4 - /// Filter 18 data 1 register - pub const F18DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d4); - - /// address: 0x40006ad8 - /// Filter 19 data 0 register - pub const F19DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2d8); - - /// address: 0x40006adc - /// Filter 19 data 1 register - pub const F19DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2dc); - - /// address: 0x40006ae0 - /// Filter 20 data 0 register - pub const F20DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e0); - - /// address: 0x40006ae4 - /// Filter 20 data 1 register - pub const F20DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e4); - - /// address: 0x40006ae8 - /// Filter 21 data 0 register - pub const F21DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2e8); - - /// address: 0x40006aec - /// Filter 21 data 1 register - pub const F21DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2ec); - - /// address: 0x40006af0 - /// Filter 22 data 0 register - pub const F22DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f0); - - /// address: 0x40006af4 - /// Filter 22 data 1 register - pub const F22DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f4); - - /// address: 0x40006af8 - /// Filter 23 data 0 register - pub const F23DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2f8); - - /// address: 0x40006afc - /// Filter 23 data 1 register - pub const F23DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006b00 - /// Filter 24 data 0 register - pub const F24DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x300); - - /// address: 0x40006b04 - /// Filter 24 data 1 register - pub const F24DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x304); - - /// address: 0x40006b08 - /// Filter 25 data 0 register - pub const F25DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x308); - - /// address: 0x40006b0c - /// Filter 25 data 1 register - pub const F25DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x30c); - - /// address: 0x40006b10 - /// Filter 26 data 0 register - pub const F26DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x310); - - /// address: 0x40006b14 - /// Filter 26 data 1 register - pub const F26DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x314); - - /// address: 0x40006b18 - /// Filter 27 data 0 register - pub const F27DATA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x318); - - /// address: 0x40006b1c - /// Filter 27 data 1 register - pub const F27DATA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), base_address + 0x31c); - }; - - /// cyclic redundancy check calculation unit - pub const CRC = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023000 - /// Data register - pub const DATA = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40023004 - /// Free data register - pub const FDATA = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40023008 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// reset bit - RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// Digital-to-analog converter - pub const DAC = struct { - pub const base_address = 0x40007400; - - /// address: 0x40007400 - /// control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 enable - DEN0: u1, - /// DAC0 output buffer turn off - DBOFF0: u1, - /// DAC0 trigger enable - DTEN0: u1, - /// DAC0 trigger selection - DTSEL0: u3, - /// DAC0 noise wave mode - DWM0: u2, - /// DAC0 noise wave bit width - DWBW0: u4, - /// DAC0 DMA enable - DDMAEN0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DAC1 enable - DEN1: u1, - /// DAC1 output buffer turn off - DBOFF1: u1, - /// DAC1 trigger enable - DTEN1: u1, - /// DAC1 trigger selection - DTSEL1: u3, - /// DAC1 noise wave mode - DWM1: u2, - /// DAC1 noise wave bit width - DWBW1: u4, - /// DAC1 DMA enable - DDMAEN1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40007404 - /// software trigger register - pub const SWT = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 software trigger - SWTR0: u1, - /// DAC1 software trigger - SWTR1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40007408 - /// DAC0 12-bit right-aligned data holding register - pub const DAC0_R12DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 12-bit right-aligned - /// data - DAC0_DH: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000740c - /// DAC0 12-bit left-aligned data holding register - pub const DAC0_L12DH = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC0 12-bit left-aligned - /// data - DAC0_DH: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007410 - /// DAC0 8-bit right aligned data holding - /// register - pub const DAC0_R8DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 8-bit right-aligned - /// data - DAC0_DH: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40007414 - /// DAC1 12-bit right-aligned data holding - /// register - pub const DAC1_R12DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC1 12-bit right-aligned - /// data - DAC1_DH: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007418 - /// DAC1 12-bit left aligned data holding - /// register - pub const DAC1_L12DH = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC1 12-bit left-aligned - /// data - DAC1_DH: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000741c - /// DAC1 8-bit right aligned data holding - /// register - pub const DAC1_R8DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC1 8-bit right-aligned - /// data - DAC1_DH: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1c); - - /// address: 0x40007420 - /// DAC concurrent mode 12-bit right-aligned data holding - /// register - pub const DACC_R12DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 12-bit right-aligned - /// data - DAC0_DH: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC1 12-bit right-aligned - /// data - DAC1_DH: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x40007424 - /// DAC concurrent mode 12-bit left aligned data holding - /// register - pub const DACC_L12DH = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC0 12-bit left-aligned - /// data - DAC0_DH: u12, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// DAC1 12-bit left-aligned - /// data - DAC1_DH: u12, - }), base_address + 0x24); - - /// address: 0x40007428 - /// DAC concurrent mode 8-bit right aligned data holding - /// register - pub const DACC_R8DH = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC0 8-bit right-aligned - /// data - DAC0_DH: u8, - /// DAC1 8-bit right-aligned - /// data - DAC1_DH: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000742c - /// DAC0 data output register - pub const DAC0_DO = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x2c); - - /// address: 0x40007430 - /// DAC1 data output register - pub const DAC1_DO = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x30); - }; - - /// Debug support - pub const DBG = struct { - pub const base_address = 0xe0042000; - - /// address: 0xe0042000 - /// ID code register - pub const ID = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG ID code register - ID_CODE: u32, - }), base_address + 0x0); - - /// address: 0xe0042004 - /// Control register 0 - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Sleep mode hold register - SLP_HOLD: u1, - /// Deep-sleep mode hold register - DSLP_HOLD: u1, - /// Standby mode hold register - STB_HOLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// FWDGT hold bit - FWDGT_HOLD: u1, - /// WWDGT hold bit - WWDGT_HOLD: u1, - /// TIMER 0 hold bit - TIMER0_HOLD: u1, - /// TIMER 1 hold bit - TIMER1_HOLD: u1, - /// TIMER 2 hold bit - TIMER2_HOLD: u1, - /// TIMER 23 hold bit - TIMER3_HOLD: u1, - /// CAN0 hold bit - CAN0_HOLD: u1, - /// I2C0 hold bit - I2C0_HOLD: u1, - /// I2C1 hold bit - I2C1_HOLD: u1, - reserved5: u1, - /// TIMER4_HOLD - TIMER4_HOLD: u1, - /// TIMER 5 hold bit - TIMER5_HOLD: u1, - /// TIMER 6 hold bit - TIMER6_HOLD: u1, - /// CAN1 hold bit - CAN1_HOLD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x4); - }; - - /// DMA controller - pub const DMA0 = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// Interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt flag of channel 0 - GIF0: u1, - /// Full Transfer finish flag of channe 0 - FTFIF0: u1, - /// Half transfer finish flag of channel 0 - HTFIF0: u1, - /// Error flag of channel 0 - ERRIF0: u1, - /// Global interrupt flag of channel 1 - GIF1: u1, - /// Full Transfer finish flag of channe 1 - FTFIF1: u1, - /// Half transfer finish flag of channel 1 - HTFIF1: u1, - /// Error flag of channel 1 - ERRIF1: u1, - /// Global interrupt flag of channel 2 - GIF2: u1, - /// Full Transfer finish flag of channe 2 - FTFIF2: u1, - /// Half transfer finish flag of channel 2 - HTFIF2: u1, - /// Error flag of channel 2 - ERRIF2: u1, - /// Global interrupt flag of channel 3 - GIF3: u1, - /// Full Transfer finish flag of channe 3 - FTFIF3: u1, - /// Half transfer finish flag of channel 3 - HTFIF3: u1, - /// Error flag of channel 3 - ERRIF3: u1, - /// Global interrupt flag of channel 4 - GIF4: u1, - /// Full Transfer finish flag of channe 4 - FTFIF4: u1, - /// Half transfer finish flag of channel 4 - HTFIF4: u1, - /// Error flag of channel 4 - ERRIF4: u1, - /// Global interrupt flag of channel 5 - GIF5: u1, - /// Full Transfer finish flag of channe 5 - FTFIF5: u1, - /// Half transfer finish flag of channel 5 - HTFIF5: u1, - /// Error flag of channel 5 - ERRIF5: u1, - /// Global interrupt flag of channel 6 - GIF6: u1, - /// Full Transfer finish flag of channe 6 - FTFIF6: u1, - /// Half transfer finish flag of channel 6 - HTFIF6: u1, - /// Error flag of channel 6 - ERRIF6: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40020004 - /// Interrupt flag clear register - pub const INTC = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear global interrupt flag of channel 0 - GIFC0: u1, - /// Clear bit for full transfer finish flag of channel 0 - FTFIFC0: u1, - /// Clear bit for half transfer finish flag of channel 0 - HTFIFC0: u1, - /// Clear bit for error flag of channel 0 - ERRIFC0: u1, - /// Clear global interrupt flag of channel 1 - GIFC1: u1, - /// Clear bit for full transfer finish flag of channel 1 - FTFIFC1: u1, - /// Clear bit for half transfer finish flag of channel 1 - HTFIFC1: u1, - /// Clear bit for error flag of channel 1 - ERRIFC1: u1, - /// Clear global interrupt flag of channel 2 - GIFC2: u1, - /// Clear bit for full transfer finish flag of channel 2 - FTFIFC2: u1, - /// Clear bit for half transfer finish flag of channel 2 - HTFIFC2: u1, - /// Clear bit for error flag of channel 2 - ERRIFC2: u1, - /// Clear global interrupt flag of channel 3 - GIFC3: u1, - /// Clear bit for full transfer finish flag of channel 3 - FTFIFC3: u1, - /// Clear bit for half transfer finish flag of channel 3 - HTFIFC3: u1, - /// Clear bit for error flag of channel 3 - ERRIFC3: u1, - /// Clear global interrupt flag of channel 4 - GIFC4: u1, - /// Clear bit for full transfer finish flag of channel 4 - FTFIFC4: u1, - /// Clear bit for half transfer finish flag of channel 4 - HTFIFC4: u1, - /// Clear bit for error flag of channel 4 - ERRIFC4: u1, - /// Clear global interrupt flag of channel 5 - GIFC5: u1, - /// Clear bit for full transfer finish flag of channel 5 - FTFIFC5: u1, - /// Clear bit for half transfer finish flag of channel 5 - HTFIFC5: u1, - /// Clear bit for error flag of channel 5 - ERRIFC5: u1, - /// Clear global interrupt flag of channel 6 - GIFC6: u1, - /// Clear bit for full transfer finish flag of channel 6 - FTFIFC6: u1, - /// Clear bit for half transfer finish flag of channel 6 - HTFIFC6: u1, - /// Clear bit for error flag of channel 6 - ERRIFC6: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// Channel 0 control register - pub const CH0CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002000c - /// Channel 0 counter register - pub const CH0CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020010 - /// Channel 0 peripheral base address register - pub const CH0PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x10); - - /// address: 0x40020014 - /// Channel 0 memory base address register - pub const CH0MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x14); - - /// address: 0x4002001c - /// Channel 1 control register - pub const CH1CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// Channel 1 counter register - pub const CH1CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020024 - /// Channel 1 peripheral base address register - pub const CH1PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x24); - - /// address: 0x40020028 - /// Channel 1 memory base address register - pub const CH1MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x28); - - /// address: 0x40020030 - /// Channel 2 control register - pub const CH2CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020034 - /// Channel 2 counter register - pub const CH2CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020038 - /// Channel 2 peripheral base address register - pub const CH2PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x38); - - /// address: 0x4002003c - /// Channel 2 memory base address register - pub const CH2MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x3c); - - /// address: 0x40020044 - /// Channel 3 control register - pub const CH3CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020048 - /// Channel 3 counter register - pub const CH3CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002004c - /// Channel 3 peripheral base address register - pub const CH3PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x4c); - - /// address: 0x40020050 - /// Channel 3 memory base address register - pub const CH3MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x50); - - /// address: 0x40020058 - /// Channel 4 control register - pub const CH4CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002005c - /// Channel 4 counter register - pub const CH4CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020060 - /// Channel 4 peripheral base address register - pub const CH4PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x60); - - /// address: 0x40020064 - /// Channel 4 memory base address register - pub const CH4MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x64); - - /// address: 0x4002006c - /// Channel 5 control register - pub const CH5CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x6c); - - /// address: 0x40020070 - /// Channel 5 counter register - pub const CH5CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40020074 - /// Channel 5 peripheral base address register - pub const CH5PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x74); - - /// address: 0x40020078 - /// Channel 5 memory base address register - pub const CH5MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x78); - - /// address: 0x40020080 - /// Channel 6 control register - pub const CH6CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40020084 - /// Channel 6 counter register - pub const CH6CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40020088 - /// Channel 6 peripheral base address register - pub const CH6PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x88); - - /// address: 0x4002008c - /// Channel 6 memory base address register - pub const CH6MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x8c); - }; - - /// Direct memory access controller - pub const DMA1 = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// Interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt flag of channel 0 - GIF0: u1, - /// Full Transfer finish flag of channe 0 - FTFIF0: u1, - /// Half transfer finish flag of channel 0 - HTFIF0: u1, - /// Error flag of channel 0 - ERRIF0: u1, - /// Global interrupt flag of channel 1 - GIF1: u1, - /// Full Transfer finish flag of channe 1 - FTFIF1: u1, - /// Half transfer finish flag of channel 1 - HTFIF1: u1, - /// Error flag of channel 1 - ERRIF1: u1, - /// Global interrupt flag of channel 2 - GIF2: u1, - /// Full Transfer finish flag of channe 2 - FTFIF2: u1, - /// Half transfer finish flag of channel 2 - HTFIF2: u1, - /// Error flag of channel 2 - ERRIF2: u1, - /// Global interrupt flag of channel 3 - GIF3: u1, - /// Full Transfer finish flag of channe 3 - FTFIF3: u1, - /// Half transfer finish flag of channel 3 - HTFIF3: u1, - /// Error flag of channel 3 - ERRIF3: u1, - /// Global interrupt flag of channel 4 - GIF4: u1, - /// Full Transfer finish flag of channe 4 - FTFIF4: u1, - /// Half transfer finish flag of channel 4 - HTFIF4: u1, - /// Error flag of channel 4 - ERRIF4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x40020004 - /// Interrupt flag clear register - pub const INTC = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear global interrupt flag of channel 0 - GIFC0: u1, - /// Clear bit for full transfer finish flag of channel 0 - FTFIFC0: u1, - /// Clear bit for half transfer finish flag of channel 0 - HTFIFC0: u1, - /// Clear bit for error flag of channel 0 - ERRIFC0: u1, - /// Clear global interrupt flag of channel 1 - GIFC1: u1, - /// Clear bit for full transfer finish flag of channel 1 - FTFIFC1: u1, - /// Clear bit for half transfer finish flag of channel 1 - HTFIFC1: u1, - /// Clear bit for error flag of channel 1 - ERRIFC1: u1, - /// Clear global interrupt flag of channel 2 - GIFC2: u1, - /// Clear bit for full transfer finish flag of channel 2 - FTFIFC2: u1, - /// Clear bit for half transfer finish flag of channel 2 - HTFIFC2: u1, - /// Clear bit for error flag of channel 2 - ERRIFC2: u1, - /// Clear global interrupt flag of channel 3 - GIFC3: u1, - /// Clear bit for full transfer finish flag of channel 3 - FTFIFC3: u1, - /// Clear bit for half transfer finish flag of channel 3 - HTFIFC3: u1, - /// Clear bit for error flag of channel 3 - ERRIFC3: u1, - /// Clear global interrupt flag of channel 4 - GIFC4: u1, - /// Clear bit for full transfer finish flag of channel 4 - FTFIFC4: u1, - /// Clear bit for half transfer finish flag of channel 4 - HTFIFC4: u1, - /// Clear bit for error flag of channel 4 - ERRIFC4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// Channel 0 control register - pub const CH0CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002000c - /// Channel 0 counter register - pub const CH0CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020010 - /// Channel 0 peripheral base address register - pub const CH0PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x10); - - /// address: 0x40020014 - /// Channel 0 memory base address register - pub const CH0MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x14); - - /// address: 0x4002001c - /// Channel 1 control register - pub const CH1CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// Channel 1 counter register - pub const CH1CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020024 - /// Channel 1 peripheral base address register - pub const CH1PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x24); - - /// address: 0x40020028 - /// Channel 1 memory base address register - pub const CH1MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x28); - - /// address: 0x40020030 - /// Channel 2 control register - pub const CH2CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020034 - /// Channel 2 counter register - pub const CH2CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020038 - /// Channel 2 peripheral base address register - pub const CH2PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x38); - - /// address: 0x4002003c - /// Channel 2 memory base address register - pub const CH2MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x3c); - - /// address: 0x40020044 - /// Channel 3 control register - pub const CH3CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020048 - /// Channel 3 counter register - pub const CH3CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002004c - /// Channel 3 peripheral base address register - pub const CH3PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x4c); - - /// address: 0x40020050 - /// Channel 3 memory base address register - pub const CH3MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x50); - - /// address: 0x40020058 - /// Channel 4 control register - pub const CH4CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002005c - /// Channel 4 counter register - pub const CH4CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer counter - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020060 - /// Channel 4 peripheral base address register - pub const CH4PADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral base address - PADDR: u32, - }), base_address + 0x60); - - /// address: 0x40020064 - /// Channel 4 memory base address register - pub const CH4MADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory base address - MADDR: u32, - }), base_address + 0x64); - }; - - /// External memory controller - pub const EXMC = struct { - pub const base_address = 0xa0000000; - - /// address: 0xa0000000 - /// SRAM/NOR flash control register 0 - pub const SNCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// NOR bank enable - NRBKEN: u1, - /// NOR bank memory address/data multiplexing - NRMUX: u1, - /// NOR bank memory type - NRTP: u2, - /// NOR bank memory data bus width - NRW: u2, - /// NOR Flash access enable - NREN: u1, - reserved0: u1, - reserved1: u1, - /// NWAIT signal polarity - NRWTPOL: u1, - reserved2: u1, - reserved3: u1, - /// Write enable - WREN: u1, - /// NWAIT signal enable - NRWTEN: u1, - reserved4: u1, - /// Asynchronous wait - ASYNCWAIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0xa0000004 - /// SRAM/NOR flash timing configuration register 0 - pub const SNTCFG0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address setup time - ASET: u4, - /// Address hold time - AHLD: u4, - /// Data setup time - DSET: u8, - /// Bus latency - BUSLAT: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0xa0000008 - /// SRAM/NOR flash control register 1 - pub const SNCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// NOR bank enable - NRBKEN: u1, - /// NOR bank memory address/data multiplexing - NRMUX: u1, - /// NOR bank memory type - NRTP: u2, - /// NOR bank memory data bus width - NRW: u2, - /// NOR Flash access enable - NREN: u1, - reserved0: u1, - reserved1: u1, - /// NWAIT signal polarity - NRWTPOL: u1, - reserved2: u1, - reserved3: u1, - /// Write enable - WREN: u1, - /// NWAIT signal enable - NRWTEN: u1, - reserved4: u1, - /// Asynchronous wait - ASYNCWAIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - }; - - /// External interrupt/event - /// controller - pub const EXTI = struct { - pub const base_address = 0x40010400; - - /// address: 0x40010400 - /// Interrupt enable register - /// (EXTI_INTEN) - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Interrupt on line 0 - INTEN0: u1, - /// Enable Interrupt on line 1 - INTEN1: u1, - /// Enable Interrupt on line 2 - INTEN2: u1, - /// Enable Interrupt on line 3 - INTEN3: u1, - /// Enable Interrupt on line 4 - INTEN4: u1, - /// Enable Interrupt on line 5 - INTEN5: u1, - /// Enable Interrupt on line 6 - INTEN6: u1, - /// Enable Interrupt on line 7 - INTEN7: u1, - /// Enable Interrupt on line 8 - INTEN8: u1, - /// Enable Interrupt on line 9 - INTEN9: u1, - /// Enable Interrupt on line 10 - INTEN10: u1, - /// Enable Interrupt on line 11 - INTEN11: u1, - /// Enable Interrupt on line 12 - INTEN12: u1, - /// Enable Interrupt on line 13 - INTEN13: u1, - /// Enable Interrupt on line 14 - INTEN14: u1, - /// Enable Interrupt on line 15 - INTEN15: u1, - /// Enable Interrupt on line 16 - INTEN16: u1, - /// Enable Interrupt on line 17 - INTEN17: u1, - /// Enable Interrupt on line 18 - INTEN18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x40010404 - /// Event enable register (EXTI_EVEN) - pub const EVEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable Event on line 0 - EVEN0: u1, - /// Enable Event on line 1 - EVEN1: u1, - /// Enable Event on line 2 - EVEN2: u1, - /// Enable Event on line 3 - EVEN3: u1, - /// Enable Event on line 4 - EVEN4: u1, - /// Enable Event on line 5 - EVEN5: u1, - /// Enable Event on line 6 - EVEN6: u1, - /// Enable Event on line 7 - EVEN7: u1, - /// Enable Event on line 8 - EVEN8: u1, - /// Enable Event on line 9 - EVEN9: u1, - /// Enable Event on line 10 - EVEN10: u1, - /// Enable Event on line 11 - EVEN11: u1, - /// Enable Event on line 12 - EVEN12: u1, - /// Enable Event on line 13 - EVEN13: u1, - /// Enable Event on line 14 - EVEN14: u1, - /// Enable Event on line 15 - EVEN15: u1, - /// Enable Event on line 16 - EVEN16: u1, - /// Enable Event on line 17 - EVEN17: u1, - /// Enable Event on line 18 - EVEN18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x4); - - /// address: 0x40010408 - /// Rising Edge Trigger Enable register - /// (EXTI_RTEN) - pub const RTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising edge trigger enable of - /// line 0 - RTEN0: u1, - /// Rising edge trigger enable of - /// line 1 - RTEN1: u1, - /// Rising edge trigger enable of - /// line 2 - RTEN2: u1, - /// Rising edge trigger enable of - /// line 3 - RTEN3: u1, - /// Rising edge trigger enable of - /// line 4 - RTEN4: u1, - /// Rising edge trigger enable of - /// line 5 - RTEN5: u1, - /// Rising edge trigger enable of - /// line 6 - RTEN6: u1, - /// Rising edge trigger enable of - /// line 7 - RTEN7: u1, - /// Rising edge trigger enable of - /// line 8 - RTEN8: u1, - /// Rising edge trigger enable of - /// line 9 - RTEN9: u1, - /// Rising edge trigger enable of - /// line 10 - RTEN10: u1, - /// Rising edge trigger enable of - /// line 11 - RTEN11: u1, - /// Rising edge trigger enable of - /// line 12 - RTEN12: u1, - /// Rising edge trigger enable of - /// line 13 - RTEN13: u1, - /// Rising edge trigger enable of - /// line 14 - RTEN14: u1, - /// Rising edge trigger enable of - /// line 15 - RTEN15: u1, - /// Rising edge trigger enable of - /// line 16 - RTEN16: u1, - /// Rising edge trigger enable of - /// line 17 - RTEN17: u1, - /// Rising edge trigger enable of - /// line 18 - RTEN18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x8); - - /// address: 0x4001040c - /// Falling Egde Trigger Enable register - /// (EXTI_FTEN) - pub const FTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling edge trigger enable of - /// line 0 - FTEN0: u1, - /// Falling edge trigger enable of - /// line 1 - FTEN1: u1, - /// Falling edge trigger enable of - /// line 2 - FTEN2: u1, - /// Falling edge trigger enable of - /// line 3 - FTEN3: u1, - /// Falling edge trigger enable of - /// line 4 - FTEN4: u1, - /// Falling edge trigger enable of - /// line 5 - FTEN5: u1, - /// Falling edge trigger enable of - /// line 6 - FTEN6: u1, - /// Falling edge trigger enable of - /// line 7 - FTEN7: u1, - /// Falling edge trigger enable of - /// line 8 - FTEN8: u1, - /// Falling edge trigger enable of - /// line 9 - FTEN9: u1, - /// Falling edge trigger enable of - /// line 10 - FTEN10: u1, - /// Falling edge trigger enable of - /// line 11 - FTEN11: u1, - /// Falling edge trigger enable of - /// line 12 - FTEN12: u1, - /// Falling edge trigger enable of - /// line 13 - FTEN13: u1, - /// Falling edge trigger enable of - /// line 14 - FTEN14: u1, - /// Falling edge trigger enable of - /// line 15 - FTEN15: u1, - /// Falling edge trigger enable of - /// line 16 - FTEN16: u1, - /// Falling edge trigger enable of - /// line 17 - FTEN17: u1, - /// Falling edge trigger enable of - /// line 18 - FTEN18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - - /// address: 0x40010410 - /// Software interrupt event register - /// (EXTI_SWIEV) - pub const SWIEV = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt/Event software trigger on line - /// 0 - SWIEV0: u1, - /// Interrupt/Event software trigger on line - /// 1 - SWIEV1: u1, - /// Interrupt/Event software trigger on line - /// 2 - SWIEV2: u1, - /// Interrupt/Event software trigger on line - /// 3 - SWIEV3: u1, - /// Interrupt/Event software trigger on line - /// 4 - SWIEV4: u1, - /// Interrupt/Event software trigger on line - /// 5 - SWIEV5: u1, - /// Interrupt/Event software trigger on line - /// 6 - SWIEV6: u1, - /// Interrupt/Event software trigger on line - /// 7 - SWIEV7: u1, - /// Interrupt/Event software trigger on line - /// 8 - SWIEV8: u1, - /// Interrupt/Event software trigger on line - /// 9 - SWIEV9: u1, - /// Interrupt/Event software trigger on line - /// 10 - SWIEV10: u1, - /// Interrupt/Event software trigger on line - /// 11 - SWIEV11: u1, - /// Interrupt/Event software trigger on line - /// 12 - SWIEV12: u1, - /// Interrupt/Event software trigger on line - /// 13 - SWIEV13: u1, - /// Interrupt/Event software trigger on line - /// 14 - SWIEV14: u1, - /// Interrupt/Event software trigger on line - /// 15 - SWIEV15: u1, - /// Interrupt/Event software trigger on line - /// 16 - SWIEV16: u1, - /// Interrupt/Event software trigger on line - /// 17 - SWIEV17: u1, - /// Interrupt/Event software trigger on line - /// 18 - SWIEV18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x10); - - /// address: 0x40010414 - /// Pending register (EXTI_PD) - pub const PD = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt pending status of line 0 - PD0: u1, - /// Interrupt pending status of line 1 - PD1: u1, - /// Interrupt pending status of line 2 - PD2: u1, - /// Interrupt pending status of line 3 - PD3: u1, - /// Interrupt pending status of line 4 - PD4: u1, - /// Interrupt pending status of line 5 - PD5: u1, - /// Interrupt pending status of line 6 - PD6: u1, - /// Interrupt pending status of line 7 - PD7: u1, - /// Interrupt pending status of line 8 - PD8: u1, - /// Interrupt pending status of line 9 - PD9: u1, - /// Interrupt pending status of line 10 - PD10: u1, - /// Interrupt pending status of line 11 - PD11: u1, - /// Interrupt pending status of line 12 - PD12: u1, - /// Interrupt pending status of line 13 - PD13: u1, - /// Interrupt pending status of line 14 - PD14: u1, - /// Interrupt pending status of line 15 - PD15: u1, - /// Interrupt pending status of line 16 - PD16: u1, - /// Interrupt pending status of line 17 - PD17: u1, - /// Interrupt pending status of line 18 - PD18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x14); - }; - - /// FMC - pub const FMC = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022000 - /// wait state counter register - pub const WS = @intToPtr(*volatile Mmio(32, packed struct { - /// wait state counter register - WSCNT: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40022004 - /// Unlock key register 0 - pub const KEY0 = @intToPtr(*volatile Mmio(32, packed struct { - /// FMC_CTL0 unlock key - KEY: u32, - }), base_address + 0x4); - - /// address: 0x40022008 - /// Option byte unlock key register - pub const OBKEY = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4002200c - /// Status register 0 - pub const STAT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// The flash is busy bit - BUSY: u1, - reserved0: u1, - /// Program error flag bit - PGERR: u1, - reserved1: u1, - /// Erase/Program protection error flag bit - WPERR: u1, - /// End of operation flag bit - ENDF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40022010 - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Main flash program for bank0 command bit - PG: u1, - /// Main flash page erase for bank0 command bit - PER: u1, - /// Main flash mass erase for bank0 command bit - MER: u1, - reserved0: u1, - /// Option bytes program command bit - OBPG: u1, - /// Option bytes erase command bit - OBER: u1, - /// Send erase command to FMC bit - START: u1, - /// FMC_CTL0 lock bit - LK: u1, - reserved1: u1, - /// Option byte erase/program enable bit - OBWEN: u1, - /// Error interrupt enable bit - ERRIE: u1, - reserved2: u1, - /// End of operation interrupt enable bit - ENDIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40022014 - /// Address register 0 - pub const ADDR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Flash erase/program command address bits - ADDR: u32, - }), base_address + 0x14); - - /// address: 0x4002201c - /// Option byte status register - pub const OBSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Option bytes read error bit - OBERR: u1, - /// Option bytes security protection code - SPC: u1, - /// Store USER of option bytes block after system reset - USER: u8, - /// Store DATA[15:0] of option bytes block after system reset - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1c); - - /// address: 0x40022020 - /// Erase/Program Protection register - pub const WP = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40022100 - /// Product ID register - pub const PID = @intToPtr(*volatile u32, base_address + 0x100); - }; - - /// free watchdog timer - pub const FWDGT = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Key value - CMD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Prescaler register - pub const PSC = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); - - /// address: 0x40003008 - /// Reload register - pub const RLD = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8); - - /// address: 0x4000300c - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Free watchdog timer prescaler value update - PUD: u1, - /// Free watchdog timer counter reload value update - RUD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - }; - - /// General-purpose I/Os - pub const GPIOA = struct { - pub const base_address = 0x40010800; - - /// address: 0x40010800 - /// port control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 0) - MD0: u2, - /// Port x configuration bits (x = - /// 0) - CTL0: u2, - /// Port x mode bits (x = - /// 1) - MD1: u2, - /// Port x configuration bits (x = - /// 1) - CTL1: u2, - /// Port x mode bits (x = - /// 2 ) - MD2: u2, - /// Port x configuration bits (x = - /// 2) - CTL2: u2, - /// Port x mode bits (x = - /// 3 ) - MD3: u2, - /// Port x configuration bits (x = - /// 3) - CTL3: u2, - /// Port x mode bits (x = - /// 4) - MD4: u2, - /// Port x configuration bits (x = - /// 4) - CTL4: u2, - /// Port x mode bits (x = - /// 5) - MD5: u2, - /// Port x configuration bits (x = - /// 5) - CTL5: u2, - /// Port x mode bits (x = - /// 6) - MD6: u2, - /// Port x configuration bits (x = - /// 6) - CTL6: u2, - /// Port x mode bits (x = - /// 7) - MD7: u2, - /// Port x configuration bits (x = - /// 7) - CTL7: u2, - }), base_address + 0x0); - - /// address: 0x40010804 - /// port control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 8) - MD8: u2, - /// Port x configuration bits (x = - /// 8) - CTL8: u2, - /// Port x mode bits (x = - /// 9) - MD9: u2, - /// Port x configuration bits (x = - /// 9) - CTL9: u2, - /// Port x mode bits (x = - /// 10 ) - MD10: u2, - /// Port x configuration bits (x = - /// 10) - CTL10: u2, - /// Port x mode bits (x = - /// 11 ) - MD11: u2, - /// Port x configuration bits (x = - /// 11) - CTL11: u2, - /// Port x mode bits (x = - /// 12) - MD12: u2, - /// Port x configuration bits (x = - /// 12) - CTL12: u2, - /// Port x mode bits (x = - /// 13) - MD13: u2, - /// Port x configuration bits (x = - /// 13) - CTL13: u2, - /// Port x mode bits (x = - /// 14) - MD14: u2, - /// Port x configuration bits (x = - /// 14) - CTL14: u2, - /// Port x mode bits (x = - /// 15) - MD15: u2, - /// Port x configuration bits (x = - /// 15) - CTL15: u2, - }), base_address + 0x4); - - /// address: 0x40010808 - /// Port input status register - pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001080c - /// Port output control register - pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010810 - /// Port bit operate register - pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), base_address + 0x10); - - /// address: 0x40010814 - /// Port bit clear register - pub const BC = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40010818 - /// GPIO port configuration lock - /// register - pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOB = struct { - pub const base_address = 0x40010c00; - - /// address: 0x40010c00 - /// port control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 0) - MD0: u2, - /// Port x configuration bits (x = - /// 0) - CTL0: u2, - /// Port x mode bits (x = - /// 1) - MD1: u2, - /// Port x configuration bits (x = - /// 1) - CTL1: u2, - /// Port x mode bits (x = - /// 2 ) - MD2: u2, - /// Port x configuration bits (x = - /// 2) - CTL2: u2, - /// Port x mode bits (x = - /// 3 ) - MD3: u2, - /// Port x configuration bits (x = - /// 3) - CTL3: u2, - /// Port x mode bits (x = - /// 4) - MD4: u2, - /// Port x configuration bits (x = - /// 4) - CTL4: u2, - /// Port x mode bits (x = - /// 5) - MD5: u2, - /// Port x configuration bits (x = - /// 5) - CTL5: u2, - /// Port x mode bits (x = - /// 6) - MD6: u2, - /// Port x configuration bits (x = - /// 6) - CTL6: u2, - /// Port x mode bits (x = - /// 7) - MD7: u2, - /// Port x configuration bits (x = - /// 7) - CTL7: u2, - }), base_address + 0x0); - - /// address: 0x40010c04 - /// port control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 8) - MD8: u2, - /// Port x configuration bits (x = - /// 8) - CTL8: u2, - /// Port x mode bits (x = - /// 9) - MD9: u2, - /// Port x configuration bits (x = - /// 9) - CTL9: u2, - /// Port x mode bits (x = - /// 10 ) - MD10: u2, - /// Port x configuration bits (x = - /// 10) - CTL10: u2, - /// Port x mode bits (x = - /// 11 ) - MD11: u2, - /// Port x configuration bits (x = - /// 11) - CTL11: u2, - /// Port x mode bits (x = - /// 12) - MD12: u2, - /// Port x configuration bits (x = - /// 12) - CTL12: u2, - /// Port x mode bits (x = - /// 13) - MD13: u2, - /// Port x configuration bits (x = - /// 13) - CTL13: u2, - /// Port x mode bits (x = - /// 14) - MD14: u2, - /// Port x configuration bits (x = - /// 14) - CTL14: u2, - /// Port x mode bits (x = - /// 15) - MD15: u2, - /// Port x configuration bits (x = - /// 15) - CTL15: u2, - }), base_address + 0x4); - - /// address: 0x40010c08 - /// Port input status register - pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40010c0c - /// Port output control register - pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010c10 - /// Port bit operate register - pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), base_address + 0x10); - - /// address: 0x40010c14 - /// Port bit clear register - pub const BC = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40010c18 - /// GPIO port configuration lock - /// register - pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOC = struct { - pub const base_address = 0x40011000; - - /// address: 0x40011000 - /// port control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 0) - MD0: u2, - /// Port x configuration bits (x = - /// 0) - CTL0: u2, - /// Port x mode bits (x = - /// 1) - MD1: u2, - /// Port x configuration bits (x = - /// 1) - CTL1: u2, - /// Port x mode bits (x = - /// 2 ) - MD2: u2, - /// Port x configuration bits (x = - /// 2) - CTL2: u2, - /// Port x mode bits (x = - /// 3 ) - MD3: u2, - /// Port x configuration bits (x = - /// 3) - CTL3: u2, - /// Port x mode bits (x = - /// 4) - MD4: u2, - /// Port x configuration bits (x = - /// 4) - CTL4: u2, - /// Port x mode bits (x = - /// 5) - MD5: u2, - /// Port x configuration bits (x = - /// 5) - CTL5: u2, - /// Port x mode bits (x = - /// 6) - MD6: u2, - /// Port x configuration bits (x = - /// 6) - CTL6: u2, - /// Port x mode bits (x = - /// 7) - MD7: u2, - /// Port x configuration bits (x = - /// 7) - CTL7: u2, - }), base_address + 0x0); - - /// address: 0x40011004 - /// port control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 8) - MD8: u2, - /// Port x configuration bits (x = - /// 8) - CTL8: u2, - /// Port x mode bits (x = - /// 9) - MD9: u2, - /// Port x configuration bits (x = - /// 9) - CTL9: u2, - /// Port x mode bits (x = - /// 10 ) - MD10: u2, - /// Port x configuration bits (x = - /// 10) - CTL10: u2, - /// Port x mode bits (x = - /// 11 ) - MD11: u2, - /// Port x configuration bits (x = - /// 11) - CTL11: u2, - /// Port x mode bits (x = - /// 12) - MD12: u2, - /// Port x configuration bits (x = - /// 12) - CTL12: u2, - /// Port x mode bits (x = - /// 13) - MD13: u2, - /// Port x configuration bits (x = - /// 13) - CTL13: u2, - /// Port x mode bits (x = - /// 14) - MD14: u2, - /// Port x configuration bits (x = - /// 14) - CTL14: u2, - /// Port x mode bits (x = - /// 15) - MD15: u2, - /// Port x configuration bits (x = - /// 15) - CTL15: u2, - }), base_address + 0x4); - - /// address: 0x40011008 - /// Port input status register - pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001100c - /// Port output control register - pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011010 - /// Port bit operate register - pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), base_address + 0x10); - - /// address: 0x40011014 - /// Port bit clear register - pub const BC = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011018 - /// GPIO port configuration lock - /// register - pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOD = struct { - pub const base_address = 0x40011400; - - /// address: 0x40011400 - /// port control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 0) - MD0: u2, - /// Port x configuration bits (x = - /// 0) - CTL0: u2, - /// Port x mode bits (x = - /// 1) - MD1: u2, - /// Port x configuration bits (x = - /// 1) - CTL1: u2, - /// Port x mode bits (x = - /// 2 ) - MD2: u2, - /// Port x configuration bits (x = - /// 2) - CTL2: u2, - /// Port x mode bits (x = - /// 3 ) - MD3: u2, - /// Port x configuration bits (x = - /// 3) - CTL3: u2, - /// Port x mode bits (x = - /// 4) - MD4: u2, - /// Port x configuration bits (x = - /// 4) - CTL4: u2, - /// Port x mode bits (x = - /// 5) - MD5: u2, - /// Port x configuration bits (x = - /// 5) - CTL5: u2, - /// Port x mode bits (x = - /// 6) - MD6: u2, - /// Port x configuration bits (x = - /// 6) - CTL6: u2, - /// Port x mode bits (x = - /// 7) - MD7: u2, - /// Port x configuration bits (x = - /// 7) - CTL7: u2, - }), base_address + 0x0); - - /// address: 0x40011404 - /// port control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 8) - MD8: u2, - /// Port x configuration bits (x = - /// 8) - CTL8: u2, - /// Port x mode bits (x = - /// 9) - MD9: u2, - /// Port x configuration bits (x = - /// 9) - CTL9: u2, - /// Port x mode bits (x = - /// 10 ) - MD10: u2, - /// Port x configuration bits (x = - /// 10) - CTL10: u2, - /// Port x mode bits (x = - /// 11 ) - MD11: u2, - /// Port x configuration bits (x = - /// 11) - CTL11: u2, - /// Port x mode bits (x = - /// 12) - MD12: u2, - /// Port x configuration bits (x = - /// 12) - CTL12: u2, - /// Port x mode bits (x = - /// 13) - MD13: u2, - /// Port x configuration bits (x = - /// 13) - CTL13: u2, - /// Port x mode bits (x = - /// 14) - MD14: u2, - /// Port x configuration bits (x = - /// 14) - CTL14: u2, - /// Port x mode bits (x = - /// 15) - MD15: u2, - /// Port x configuration bits (x = - /// 15) - CTL15: u2, - }), base_address + 0x4); - - /// address: 0x40011408 - /// Port input status register - pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001140c - /// Port output control register - pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011410 - /// Port bit operate register - pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), base_address + 0x10); - - /// address: 0x40011414 - /// Port bit clear register - pub const BC = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011418 - /// GPIO port configuration lock - /// register - pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOE = struct { - pub const base_address = 0x40011800; - - /// address: 0x40011800 - /// port control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 0) - MD0: u2, - /// Port x configuration bits (x = - /// 0) - CTL0: u2, - /// Port x mode bits (x = - /// 1) - MD1: u2, - /// Port x configuration bits (x = - /// 1) - CTL1: u2, - /// Port x mode bits (x = - /// 2 ) - MD2: u2, - /// Port x configuration bits (x = - /// 2) - CTL2: u2, - /// Port x mode bits (x = - /// 3 ) - MD3: u2, - /// Port x configuration bits (x = - /// 3) - CTL3: u2, - /// Port x mode bits (x = - /// 4) - MD4: u2, - /// Port x configuration bits (x = - /// 4) - CTL4: u2, - /// Port x mode bits (x = - /// 5) - MD5: u2, - /// Port x configuration bits (x = - /// 5) - CTL5: u2, - /// Port x mode bits (x = - /// 6) - MD6: u2, - /// Port x configuration bits (x = - /// 6) - CTL6: u2, - /// Port x mode bits (x = - /// 7) - MD7: u2, - /// Port x configuration bits (x = - /// 7) - CTL7: u2, - }), base_address + 0x0); - - /// address: 0x40011804 - /// port control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x mode bits (x = - /// 8) - MD8: u2, - /// Port x configuration bits (x = - /// 8) - CTL8: u2, - /// Port x mode bits (x = - /// 9) - MD9: u2, - /// Port x configuration bits (x = - /// 9) - CTL9: u2, - /// Port x mode bits (x = - /// 10 ) - MD10: u2, - /// Port x configuration bits (x = - /// 10) - CTL10: u2, - /// Port x mode bits (x = - /// 11 ) - MD11: u2, - /// Port x configuration bits (x = - /// 11) - CTL11: u2, - /// Port x mode bits (x = - /// 12) - MD12: u2, - /// Port x configuration bits (x = - /// 12) - CTL12: u2, - /// Port x mode bits (x = - /// 13) - MD13: u2, - /// Port x configuration bits (x = - /// 13) - CTL13: u2, - /// Port x mode bits (x = - /// 14) - MD14: u2, - /// Port x configuration bits (x = - /// 14) - CTL14: u2, - /// Port x mode bits (x = - /// 15) - MD15: u2, - /// Port x configuration bits (x = - /// 15) - CTL15: u2, - }), base_address + 0x4); - - /// address: 0x40011808 - /// Port input status register - pub const ISTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001180c - /// Port output control register - pub const OCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011810 - /// Port bit operate register - pub const BOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), base_address + 0x10); - - /// address: 0x40011814 - /// Port bit clear register - pub const BC = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011818 - /// GPIO port configuration lock - /// register - pub const LOCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - - /// Inter integrated circuit - pub const I2C0 = struct { - pub const base_address = 0x40005400; - - /// address: 0x40005400 - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C peripheral enable - I2CEN: u1, - /// SMBus/I2C mode switch - SMBEN: u1, - reserved0: u1, - /// SMBusType Selection - SMBSEL: u1, - /// ARP protocol in SMBus switch - ARPEN: u1, - /// PEC Calculation Switch - PECEN: u1, - /// Whether or not to response to a General Call (0x00) - GCEN: u1, - /// Whether to stretch SCL low when data is not ready in slave mode - SS: u1, - /// Generate a START condition on I2C bus - START: u1, - /// Generate a STOP condition on I2C bus - STOP: u1, - /// Whether or not to send an ACK - ACKEN: u1, - /// Position of ACK and PEC when receiving - POAP: u1, - /// PEC Transfer - PECTRANS: u1, - /// SMBus alert - SALT: u1, - reserved1: u1, - /// Software reset - SRESET: u1, - }), base_address + 0x0); - - /// address: 0x40005404 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C Peripheral clock frequency - I2CCLK: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ERRIE: u1, - /// Event interrupt enable - EVIE: u1, - /// Buffer interrupt enable - BUFIE: u1, - /// DMA mode switch - DMAON: u1, - /// Flag indicating DMA last transfer - DMALST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x4); - - /// address: 0x40005408 - /// Slave address register 0 - pub const SADDR0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Bit 0 of a 10-bit address - ADDRESS0: u1, - /// 7-bit address or bits 7:1 of a 10-bit address - ADDRESS7_1: u7, - /// Highest two bits of a 10-bit address - ADDRESS9_8: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Address mode for the I2C slave - ADDFORMAT: u1, - }), base_address + 0x8); - - /// address: 0x4000540c - /// Slave address register 1 - pub const SADDR1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Dual-Address mode switch - DUADEN: u1, - /// Second I2C address for the slave in Dual-Address mode - ADDRESS2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40005410 - /// Transfer buffer register - pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { - /// Transmission or reception data buffer register - TRB: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x10); - - /// address: 0x40005414 - /// Transfer status register 0 - pub const STAT0 = @intToPtr(*volatile Mmio(16, packed struct { - /// START condition sent out in master mode - SBSEND: u1, - /// Address is sent in master mode or received and matches in slave mode - ADDSEND: u1, - /// Byte transmission completed - BTC: u1, - /// Header of 10-bit address is sent in master mode - ADD10SEND: u1, - /// STOP condition detected in slave mode - STPDET: u1, - reserved0: u1, - /// I2C_DATA is not Empty during receiving - RBNE: u1, - /// I2C_DATA is Empty during transmitting - TBE: u1, - /// A bus error occurs indication a unexpected START or STOP condition on I2C bus - BERR: u1, - /// Arbitration Lost in master mode - LOSTARB: u1, - /// Acknowledge error - AERR: u1, - /// Over-run or under-run situation occurs in slave mode - OUERR: u1, - /// PEC error when receiving data - PECERR: u1, - reserved1: u1, - /// Timeout signal in SMBus mode - SMBTO: u1, - /// SMBus Alert status - SMBALT: u1, - }), base_address + 0x14); - - /// address: 0x40005418 - /// Transfer status register 1 - pub const STAT1 = @intToPtr(*volatile Mmio(16, packed struct { - /// A flag indicating whether I2C block is in master or slave mode - MASTER: u1, - /// Busy flag - I2CBSY: u1, - /// Whether the I2C is a transmitter or a receiver - TR: u1, - reserved0: u1, - /// General call address (00h) received - RXGC: u1, - /// Default address of SMBusDevice - DEFSMB: u1, - /// SMBus Host Header detected in slave mode - HSTSMB: u1, - /// Dual Flag in slave mode - DUMODF: u1, - /// Packet Error Checking Value that calculated by hardware when PEC is enabled - PECV: u8, - }), base_address + 0x18); - - /// address: 0x4000541c - /// Clock configure register - pub const CKCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C Clock control in master mode - CLKC: u12, - reserved0: u1, - reserved1: u1, - /// Duty cycle in fast mode - DTCY: u1, - /// I2C speed selection in master mode - FAST: u1, - }), base_address + 0x1c); - - /// address: 0x40005420 - /// Rise time register - pub const RT = @intToPtr(*volatile Mmio(16, packed struct { - /// Maximum rise time in master mode - RISETIME: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x20); - - /// address: 0x40005490 - /// Fast mode plus configure register - pub const FMPCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Fast mode plus enable - FMPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x90); - }; - pub const I2C1 = struct { - pub const base_address = 0x40005800; - - /// address: 0x40005800 - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C peripheral enable - I2CEN: u1, - /// SMBus/I2C mode switch - SMBEN: u1, - reserved0: u1, - /// SMBusType Selection - SMBSEL: u1, - /// ARP protocol in SMBus switch - ARPEN: u1, - /// PEC Calculation Switch - PECEN: u1, - /// Whether or not to response to a General Call (0x00) - GCEN: u1, - /// Whether to stretch SCL low when data is not ready in slave mode - SS: u1, - /// Generate a START condition on I2C bus - START: u1, - /// Generate a STOP condition on I2C bus - STOP: u1, - /// Whether or not to send an ACK - ACKEN: u1, - /// Position of ACK and PEC when receiving - POAP: u1, - /// PEC Transfer - PECTRANS: u1, - /// SMBus alert - SALT: u1, - reserved1: u1, - /// Software reset - SRESET: u1, - }), base_address + 0x0); - - /// address: 0x40005804 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C Peripheral clock frequency - I2CCLK: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ERRIE: u1, - /// Event interrupt enable - EVIE: u1, - /// Buffer interrupt enable - BUFIE: u1, - /// DMA mode switch - DMAON: u1, - /// Flag indicating DMA last transfer - DMALST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x4); - - /// address: 0x40005808 - /// Slave address register 0 - pub const SADDR0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Bit 0 of a 10-bit address - ADDRESS0: u1, - /// 7-bit address or bits 7:1 of a 10-bit address - ADDRESS7_1: u7, - /// Highest two bits of a 10-bit address - ADDRESS9_8: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Address mode for the I2C slave - ADDFORMAT: u1, - }), base_address + 0x8); - - /// address: 0x4000580c - /// Slave address register 1 - pub const SADDR1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Dual-Address mode switch - DUADEN: u1, - /// Second I2C address for the slave in Dual-Address mode - ADDRESS2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40005810 - /// Transfer buffer register - pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { - /// Transmission or reception data buffer register - TRB: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x10); - - /// address: 0x40005814 - /// Transfer status register 0 - pub const STAT0 = @intToPtr(*volatile Mmio(16, packed struct { - /// START condition sent out in master mode - SBSEND: u1, - /// Address is sent in master mode or received and matches in slave mode - ADDSEND: u1, - /// Byte transmission completed - BTC: u1, - /// Header of 10-bit address is sent in master mode - ADD10SEND: u1, - /// STOP condition detected in slave mode - STPDET: u1, - reserved0: u1, - /// I2C_DATA is not Empty during receiving - RBNE: u1, - /// I2C_DATA is Empty during transmitting - TBE: u1, - /// A bus error occurs indication a unexpected START or STOP condition on I2C bus - BERR: u1, - /// Arbitration Lost in master mode - LOSTARB: u1, - /// Acknowledge error - AERR: u1, - /// Over-run or under-run situation occurs in slave mode - OUERR: u1, - /// PEC error when receiving data - PECERR: u1, - reserved1: u1, - /// Timeout signal in SMBus mode - SMBTO: u1, - /// SMBus Alert status - SMBALT: u1, - }), base_address + 0x14); - - /// address: 0x40005818 - /// Transfer status register 1 - pub const STAT1 = @intToPtr(*volatile Mmio(16, packed struct { - /// A flag indicating whether I2C block is in master or slave mode - MASTER: u1, - /// Busy flag - I2CBSY: u1, - /// Whether the I2C is a transmitter or a receiver - TR: u1, - reserved0: u1, - /// General call address (00h) received - RXGC: u1, - /// Default address of SMBusDevice - DEFSMB: u1, - /// SMBus Host Header detected in slave mode - HSTSMB: u1, - /// Dual Flag in slave mode - DUMODF: u1, - /// Packet Error Checking Value that calculated by hardware when PEC is enabled - PECV: u8, - }), base_address + 0x18); - - /// address: 0x4000581c - /// Clock configure register - pub const CKCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// I2C Clock control in master mode - CLKC: u12, - reserved0: u1, - reserved1: u1, - /// Duty cycle in fast mode - DTCY: u1, - /// I2C speed selection in master mode - FAST: u1, - }), base_address + 0x1c); - - /// address: 0x40005820 - /// Rise time register - pub const RT = @intToPtr(*volatile Mmio(16, packed struct { - /// Maximum rise time in master mode - RISETIME: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x20); - - /// address: 0x40005890 - /// Fast mode plus configure register - pub const FMPCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Fast mode plus enable - FMPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x90); - }; - - /// Enhanced Core Local Interrupt Controller - pub const ECLIC = struct { - pub const base_address = 0xd2000000; - - /// address: 0xd2000000 - /// cliccfg Register - pub const CLICCFG = @intToPtr(*volatile Mmio(8, packed struct { - reserved0: u1, - /// NLBITS - NLBITS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0xd2000004 - /// clicinfo Register - pub const CLICINFO = @intToPtr(*volatile Mmio(32, packed struct { - /// NUM_INTERRUPT - NUM_INTERRUPT: u13, - /// VERSION - VERSION: u8, - /// CLICINTCTLBITS - CLICINTCTLBITS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x4); - - /// address: 0xd200000b - /// MTH Register - pub const MTH = @intToPtr(*volatile u8, base_address + 0xb); - }; - - /// Power management unit - pub const PMU = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// power control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// LDO Low Power Mode - LDOLP: u1, - /// Standby Mode - STBMOD: u1, - /// Wakeup Flag Reset - WURST: u1, - /// Standby Flag Reset - STBRST: u1, - /// Low Voltage Detector Enable - LVDEN: u1, - /// Low Voltage Detector Threshold - LVDT: u3, - /// Backup Domain Write Enable - BKPWEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40007004 - /// power control/status register - pub const CS = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup flag - WUF: u1, - /// Standby flag - STBF: u1, - /// Low Voltage Detector Status Flag - LVDF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Enable WKUP pin - WUPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x4); - }; - - /// Reset and clock unit - pub const RCU = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021000 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal 8MHz RC oscillator Enable - IRC8MEN: u1, - /// IRC8M Internal 8MHz RC Oscillator stabilization Flag - IRC8MSTB: u1, - reserved0: u1, - /// Internal 8MHz RC Oscillator clock trim adjust value - IRC8MADJ: u5, - /// Internal 8MHz RC Oscillator calibration value register - IRC8MCALIB: u8, - /// External High Speed oscillator Enable - HXTALEN: u1, - /// External crystal oscillator (HXTAL) clock stabilization flag - HXTALSTB: u1, - /// External crystal oscillator (HXTAL) clock bypass mode enable - HXTALBPS: u1, - /// HXTAL Clock Monitor Enable - CKMEN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PLL enable - PLLEN: u1, - /// PLL Clock Stabilization Flag - PLLSTB: u1, - /// PLL1 enable - PLL1EN: u1, - /// PLL1 Clock Stabilization Flag - PLL1STB: u1, - /// PLL2 enable - PLL2EN: u1, - /// PLL2 Clock Stabilization Flag - PLL2STB: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x40021004 - /// Clock configuration register 0 - /// (RCU_CFG0) - pub const CFG0 = @intToPtr(*volatile Mmio(32, packed struct { - /// System clock switch - SCS: u2, - /// System clock switch status - SCSS: u2, - /// AHB prescaler selection - AHBPSC: u4, - /// APB1 prescaler selection - APB1PSC: u3, - /// APB2 prescaler selection - APB2PSC: u3, - /// ADC clock prescaler selection - ADCPSC_1_0: u2, - /// PLL Clock Source Selection - PLLSEL: u1, - /// The LSB of PREDV0 division factor - PREDV0_LSB: u1, - /// The PLL clock multiplication factor - PLLMF_3_0: u4, - /// USBFS clock prescaler selection - USBFSPSC: u2, - /// CKOUT0 Clock Source Selection - CKOUT0SEL: u4, - /// Bit 2 of ADCPSC - ADCPSC_2: u1, - /// Bit 4 of PLLMF - PLLMF_4: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0x40021008 - /// Clock interrupt register - /// (RCU_INT) - pub const INT = @intToPtr(*volatile Mmio(32, packed struct { - /// IRC40K stabilization interrupt flag - IRC40KSTBIF: u1, - /// LXTAL stabilization interrupt flag - LXTALSTBIF: u1, - /// IRC8M stabilization interrupt flag - IRC8MSTBIF: u1, - /// HXTAL stabilization interrupt flag - HXTALSTBIF: u1, - /// PLL stabilization interrupt flag - PLLSTBIF: u1, - /// PLL1 stabilization interrupt flag - PLL1STBIF: u1, - /// PLL2 stabilization interrupt flag - PLL2STBIF: u1, - /// HXTAL Clock Stuck Interrupt Flag - CKMIF: u1, - /// IRC40K Stabilization interrupt enable - IRC40KSTBIE: u1, - /// LXTAL Stabilization Interrupt Enable - LXTALSTBIE: u1, - /// IRC8M Stabilization Interrupt Enable - IRC8MSTBIE: u1, - /// HXTAL Stabilization Interrupt Enable - HXTALSTBIE: u1, - /// PLL Stabilization Interrupt Enable - PLLSTBIE: u1, - /// PLL1 Stabilization Interrupt Enable - PLL1STBIE: u1, - /// PLL2 Stabilization Interrupt Enable - PLL2STBIE: u1, - reserved0: u1, - /// IRC40K Stabilization Interrupt Clear - IRC40KSTBIC: u1, - /// LXTAL Stabilization Interrupt Clear - LXTALSTBIC: u1, - /// IRC8M Stabilization Interrupt Clear - IRC8MSTBIC: u1, - /// HXTAL Stabilization Interrupt Clear - HXTALSTBIC: u1, - /// PLL stabilization Interrupt Clear - PLLSTBIC: u1, - /// PLL1 stabilization Interrupt Clear - PLL1STBIC: u1, - /// PLL2 stabilization Interrupt Clear - PLL2STBIC: u1, - /// HXTAL Clock Stuck Interrupt Clear - CKMIC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4002100c - /// APB2 reset register - /// (RCU_APB2RST) - pub const APB2RST = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function I/O reset - AFRST: u1, - reserved0: u1, - /// GPIO port A reset - PARST: u1, - /// GPIO port B reset - PBRST: u1, - /// GPIO port C reset - PCRST: u1, - /// GPIO port D reset - PDRST: u1, - /// GPIO port E reset - PERST: u1, - reserved1: u1, - reserved2: u1, - /// ADC0 reset - ADC0RST: u1, - /// ADC1 reset - ADC1RST: u1, - /// Timer 0 reset - TIMER0RST: u1, - /// SPI0 reset - SPI0RST: u1, - reserved3: u1, - /// USART0 Reset - USART0RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40021010 - /// APB1 reset register - /// (RCU_APB1RST) - pub const APB1RST = @intToPtr(*volatile Mmio(32, packed struct { - /// TIMER1 timer reset - TIMER1RST: u1, - /// TIMER2 timer reset - TIMER2RST: u1, - /// TIMER3 timer reset - TIMER3RST: u1, - /// TIMER4 timer reset - TIMER4RST: u1, - /// TIMER5 timer reset - TIMER5RST: u1, - /// TIMER6 timer reset - TIMER6RST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window watchdog timer reset - WWDGTRST: u1, - reserved5: u1, - reserved6: u1, - /// SPI1 reset - SPI1RST: u1, - /// SPI2 reset - SPI2RST: u1, - reserved7: u1, - /// USART1 reset - USART1RST: u1, - /// USART2 reset - USART2RST: u1, - /// UART3 reset - UART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// I2C0 reset - I2C0RST: u1, - /// I2C1 reset - I2C1RST: u1, - reserved8: u1, - reserved9: u1, - /// CAN0 reset - CAN0RST: u1, - /// CAN1 reset - CAN1RST: u1, - /// Backup interface reset - BKPIRST: u1, - /// Power control reset - PMURST: u1, - /// DAC reset - DACRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40021014 - /// AHB enable register - pub const AHBEN = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA0 clock enable - DMA0EN: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// SRAM interface clock enable when sleep mode - SRAMSPEN: u1, - reserved0: u1, - /// FMC clock enable when sleep mode - FMCSPEN: u1, - reserved1: u1, - /// CRC clock enable - CRCEN: u1, - reserved2: u1, - /// EXMC clock enable - EXMCEN: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// USBFS clock enable - USBFSEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x14); - - /// address: 0x40021018 - /// APB2 clock enable register - /// (RCU_APB2EN) - pub const APB2EN = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function IO clock enable - AFEN: u1, - reserved0: u1, - /// GPIO port A clock enable - PAEN: u1, - /// GPIO port B clock enable - PBEN: u1, - /// GPIO port C clock enable - PCEN: u1, - /// GPIO port D clock enable - PDEN: u1, - /// GPIO port E clock enable - PEEN: u1, - reserved1: u1, - reserved2: u1, - /// ADC0 clock enable - ADC0EN: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// TIMER0 clock enable - TIMER0EN: u1, - /// SPI0 clock enable - SPI0EN: u1, - reserved3: u1, - /// USART0 clock enable - USART0EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x4002101c - /// APB1 clock enable register - /// (RCU_APB1EN) - pub const APB1EN = @intToPtr(*volatile Mmio(32, packed struct { - /// TIMER1 timer clock enable - TIMER1EN: u1, - /// TIMER2 timer clock enable - TIMER2EN: u1, - /// TIMER3 timer clock enable - TIMER3EN: u1, - /// TIMER4 timer clock enable - TIMER4EN: u1, - /// TIMER5 timer clock enable - TIMER5EN: u1, - /// TIMER6 timer clock enable - TIMER6EN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window watchdog timer clock enable - WWDGTEN: u1, - reserved5: u1, - reserved6: u1, - /// SPI1 clock enable - SPI1EN: u1, - /// SPI2 clock enable - SPI2EN: u1, - reserved7: u1, - /// USART1 clock enable - USART1EN: u1, - /// USART2 clock enable - USART2EN: u1, - /// UART3 clock enable - UART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// I2C0 clock enable - I2C0EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - reserved8: u1, - reserved9: u1, - /// CAN0 clock enable - CAN0EN: u1, - /// CAN1 clock enable - CAN1EN: u1, - /// Backup interface clock enable - BKPIEN: u1, - /// Power control clock enable - PMUEN: u1, - /// DAC clock enable - DACEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0x40021020 - /// Backup domain control register - /// (RCU_BDCTL) - pub const BDCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// LXTAL enable - LXTALEN: u1, - /// External low-speed oscillator stabilization - LXTALSTB: u1, - /// LXTAL bypass mode enable - LXTALBPS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RTC clock entry selection - RTCSRC: u2, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// RTC clock enable - RTCEN: u1, - /// Backup domain reset - BKPRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x20); - - /// address: 0x40021024 - /// Reset source /clock register - /// (RCU_RSTSCK) - pub const RSTSCK = @intToPtr(*volatile Mmio(32, packed struct { - /// IRC40K enable - IRC40KEN: u1, - /// IRC40K stabilization - IRC40KSTB: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Reset flag clear - RSTFC: u1, - reserved22: u1, - /// External PIN reset flag - EPRSTF: u1, - /// Power reset flag - PORRSTF: u1, - /// Software reset flag - SWRSTF: u1, - /// Free Watchdog timer reset flag - FWDGTRSTF: u1, - /// Window watchdog timer reset flag - WWDGTRSTF: u1, - /// Low-power reset flag - LPRSTF: u1, - }), base_address + 0x24); - - /// address: 0x40021028 - /// AHB reset register - pub const AHBRST = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// USBFS reset - USBFSRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x28); - - /// address: 0x4002102c - /// Clock Configuration register 1 - pub const CFG1 = @intToPtr(*volatile Mmio(32, packed struct { - /// PREDV0 division factor - PREDV0: u4, - /// PREDV1 division factor - PREDV1: u4, - /// The PLL1 clock multiplication factor - PLL1MF: u4, - /// The PLL2 clock multiplication factor - PLL2MF: u4, - /// PREDV0 input Clock Source Selection - PREDV0SEL: u1, - /// I2S1 Clock Source Selection - I2S1SEL: u1, - /// I2S2 Clock Source Selection - I2S2SEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x2c); - - /// address: 0x40021034 - /// Deep sleep mode Voltage register - pub const DSV = @intToPtr(*volatile Mmio(32, packed struct { - /// Deep-sleep mode voltage select - DSLPVS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x34); - }; - - /// Real-time clock - pub const RTC = struct { - pub const base_address = 0x40002800; - - /// address: 0x40002800 - /// RTC interrupt enable register - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Second interrupt - SCIE: u1, - /// Alarm interrupt enable - ALRMIE: u1, - /// Overflow interrupt enable - OVIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40002804 - /// control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Sencond interrupt flag - SCIF: u1, - /// Alarm interrupt flag - ALRMIF: u1, - /// Overflow interrupt flag - OVIF: u1, - /// Registers synchronized flag - RSYNF: u1, - /// Configuration mode flag - CMF: u1, - /// Last write operation finished flag - LWOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// RTC prescaler high register - pub const PSCH = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC prescaler value high - PSC: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x8); - - /// address: 0x4000280c - /// RTC prescaler low - /// register - pub const PSCL = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC prescaler value low - PSC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40002810 - /// RTC divider high register - pub const DIVH = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC divider value high - DIV: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x10); - - /// address: 0x40002814 - /// RTC divider low register - pub const DIVL = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC divider value low - DIV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40002818 - /// RTC counter high register - pub const CNTH = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC counter value high - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000281c - /// RTC counter low register - pub const CNTL = @intToPtr(*volatile Mmio(32, packed struct { - /// RTC counter value low - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40002820 - /// Alarm high register - pub const ALRMH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alarm value high - ALRM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40002824 - /// RTC alarm low register - pub const ALRML = @intToPtr(*volatile Mmio(32, packed struct { - /// alarm value low - ALRM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - }; - - /// Serial peripheral interface - pub const SPI0 = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Clock Phase Selection - CKPH: u1, - /// Clock polarity Selection - CKPL: u1, - /// Master Mode Enable - MSTMOD: u1, - /// Master Clock Prescaler Selection - PSC: u3, - /// SPI enable - SPIEN: u1, - /// LSB First Mode - LF: u1, - /// NSS Pin Selection In NSS Software Mode - SWNSS: u1, - /// NSS Software Mode Selection - SWNSSEN: u1, - /// Receive only - RO: u1, - /// Data frame format - FF16: u1, - /// CRC Next Transfer - CRCNT: u1, - /// CRC Calculation Enable - CRCEN: u1, - /// Bidirectional Transmit output enable - BDOEN: u1, - /// Bidirectional - /// enable - BDEN: u1, - }), base_address + 0x0); - - /// address: 0x40013004 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Rx buffer DMA enable - DMAREN: u1, - /// Transmit Buffer DMA Enable - DMATEN: u1, - /// Drive NSS Output - NSSDRV: u1, - /// SPI NSS pulse mode enable - NSSP: u1, - /// SPI TI mode enable - TMOD: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RBNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TBEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40013008 - /// status register - pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Buffer Not Empty - RBNE: u1, - /// Transmit Buffer Empty - TBE: u1, - /// I2S channel side - I2SCH: u1, - /// Transmission underrun error bit - TXURERR: u1, - /// SPI CRC Error Bit - CRCERR: u1, - /// SPI Configuration error - CONFERR: u1, - /// Reception Overrun Error Bit - RXORERR: u1, - /// Transmitting On-going Bit - TRANS: u1, - /// Format error - FERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x4001300c - /// data register - pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { - /// Data transfer register - SPI_DATA: u16, - }), base_address + 0xc); - - /// address: 0x40013010 - /// CRC polynomial register - pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); - - /// address: 0x40013014 - /// RX CRC register - pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); - - /// address: 0x40013018 - /// TX CRC register - pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); - - /// address: 0x4001301c - /// I2S control register - pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length - DTLEN: u2, - /// Idle state clock polarity - CKPL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization mode - PCMSMOD: u1, - /// I2S operation mode - I2SOPMOD: u2, - /// I2S Enable - I2SEN: u1, - /// I2S mode selection - I2SSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1c); - - /// address: 0x40013020 - /// I2S prescaler register - pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { - /// Dividing factor for the prescaler - DIV: u8, - /// Odd factor for the - /// prescaler - OF: u1, - /// I2S_MCK output enable - MCKOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x20); - }; - pub const SPI1 = struct { - pub const base_address = 0x40003800; - - /// address: 0x40003800 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Clock Phase Selection - CKPH: u1, - /// Clock polarity Selection - CKPL: u1, - /// Master Mode Enable - MSTMOD: u1, - /// Master Clock Prescaler Selection - PSC: u3, - /// SPI enable - SPIEN: u1, - /// LSB First Mode - LF: u1, - /// NSS Pin Selection In NSS Software Mode - SWNSS: u1, - /// NSS Software Mode Selection - SWNSSEN: u1, - /// Receive only - RO: u1, - /// Data frame format - FF16: u1, - /// CRC Next Transfer - CRCNT: u1, - /// CRC Calculation Enable - CRCEN: u1, - /// Bidirectional Transmit output enable - BDOEN: u1, - /// Bidirectional - /// enable - BDEN: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Rx buffer DMA enable - DMAREN: u1, - /// Transmit Buffer DMA Enable - DMATEN: u1, - /// Drive NSS Output - NSSDRV: u1, - /// SPI NSS pulse mode enable - NSSP: u1, - /// SPI TI mode enable - TMOD: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RBNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TBEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40003808 - /// status register - pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Buffer Not Empty - RBNE: u1, - /// Transmit Buffer Empty - TBE: u1, - /// I2S channel side - I2SCH: u1, - /// Transmission underrun error bit - TXURERR: u1, - /// SPI CRC Error Bit - CRCERR: u1, - /// SPI Configuration error - CONFERR: u1, - /// Reception Overrun Error Bit - RXORERR: u1, - /// Transmitting On-going Bit - TRANS: u1, - /// Format error - FERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x4000380c - /// data register - pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { - /// Data transfer register - SPI_DATA: u16, - }), base_address + 0xc); - - /// address: 0x40003810 - /// CRC polynomial register - pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); - - /// address: 0x40003814 - /// RX CRC register - pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); - - /// address: 0x40003818 - /// TX CRC register - pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); - - /// address: 0x4000381c - /// I2S control register - pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length - DTLEN: u2, - /// Idle state clock polarity - CKPL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization mode - PCMSMOD: u1, - /// I2S operation mode - I2SOPMOD: u2, - /// I2S Enable - I2SEN: u1, - /// I2S mode selection - I2SSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1c); - - /// address: 0x40003820 - /// I2S prescaler register - pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { - /// Dividing factor for the prescaler - DIV: u8, - /// Odd factor for the - /// prescaler - OF: u1, - /// I2S_MCK output enable - MCKOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x20); - }; - pub const SPI2 = struct { - pub const base_address = 0x40003c00; - - /// address: 0x40003c00 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Clock Phase Selection - CKPH: u1, - /// Clock polarity Selection - CKPL: u1, - /// Master Mode Enable - MSTMOD: u1, - /// Master Clock Prescaler Selection - PSC: u3, - /// SPI enable - SPIEN: u1, - /// LSB First Mode - LF: u1, - /// NSS Pin Selection In NSS Software Mode - SWNSS: u1, - /// NSS Software Mode Selection - SWNSSEN: u1, - /// Receive only - RO: u1, - /// Data frame format - FF16: u1, - /// CRC Next Transfer - CRCNT: u1, - /// CRC Calculation Enable - CRCEN: u1, - /// Bidirectional Transmit output enable - BDOEN: u1, - /// Bidirectional - /// enable - BDEN: u1, - }), base_address + 0x0); - - /// address: 0x40003c04 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Rx buffer DMA enable - DMAREN: u1, - /// Transmit Buffer DMA Enable - DMATEN: u1, - /// Drive NSS Output - NSSDRV: u1, - /// SPI NSS pulse mode enable - NSSP: u1, - /// SPI TI mode enable - TMOD: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RBNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TBEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40003c08 - /// status register - pub const STAT = @intToPtr(*volatile Mmio(16, packed struct { - /// Receive Buffer Not Empty - RBNE: u1, - /// Transmit Buffer Empty - TBE: u1, - /// I2S channel side - I2SCH: u1, - /// Transmission underrun error bit - TXURERR: u1, - /// SPI CRC Error Bit - CRCERR: u1, - /// SPI Configuration error - CONFERR: u1, - /// Reception Overrun Error Bit - RXORERR: u1, - /// Transmitting On-going Bit - TRANS: u1, - /// Format error - FERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x40003c0c - /// data register - pub const DATA = @intToPtr(*volatile Mmio(16, packed struct { - /// Data transfer register - SPI_DATA: u16, - }), base_address + 0xc); - - /// address: 0x40003c10 - /// CRC polynomial register - pub const CRCPOLY = @intToPtr(*volatile u16, base_address + 0x10); - - /// address: 0x40003c14 - /// RX CRC register - pub const RCRC = @intToPtr(*volatile u16, base_address + 0x14); - - /// address: 0x40003c18 - /// TX CRC register - pub const TCRC = @intToPtr(*volatile u16, base_address + 0x18); - - /// address: 0x40003c1c - /// I2S control register - pub const I2SCTL = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length - DTLEN: u2, - /// Idle state clock polarity - CKPL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization mode - PCMSMOD: u1, - /// I2S operation mode - I2SOPMOD: u2, - /// I2S Enable - I2SEN: u1, - /// I2S mode selection - I2SSEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x1c); - - /// address: 0x40003c20 - /// I2S prescaler register - pub const I2SPSC = @intToPtr(*volatile Mmio(16, packed struct { - /// Dividing factor for the prescaler - DIV: u8, - /// Odd factor for the - /// prescaler - OF: u1, - /// I2S_MCK output enable - MCKOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x20); - }; - - /// Advanced-timers - pub const TIMER0 = struct { - pub const base_address = 0x40012c00; - - /// address: 0x40012c00 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode - /// selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40012c04 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - /// Commutation control shadow enable - CCSE: u1, - reserved0: u1, - /// Commutation control shadow register update control - CCUC: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - /// Idle state of channel 0 output - ISO0: u1, - /// Idle state of channel 0 complementary output - ISO0N: u1, - /// Idle state of channel 1 output - ISO1: u1, - /// Idle state of channel 1 complementary output - ISO1N: u1, - /// Idle state of channel 2 output - ISO2: u1, - /// Idle state of channel 2 complementary output - ISO2N: u1, - /// Idle state of channel 3 output - ISO3: u1, - padding0: u1, - }), base_address + 0x4); - - /// address: 0x40012c08 - /// slave mode configuration register - pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Slave mode selection - SMC: u3, - reserved0: u1, - /// Trigger selection - TRGS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), base_address + 0x8); - - /// address: 0x40012c0c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - /// commutation interrupt enable - CMTIE: u1, - /// Trigger interrupt enable - TRGIE: u1, - /// Break interrupt enable - BRKIE: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - /// Commutation DMA request enable - CMTDEN: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x40012c10 - /// Interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt flag - CH2IF: u1, - /// Channel 3 capture/compare interrupt flag - CH3IF: u1, - /// Channel commutation interrupt flag - CMTIF: u1, - /// Trigger interrupt flag - TRGIF: u1, - /// Break interrupt flag - BRKIF: u1, - reserved0: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0x40012c14 - /// Software event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update event generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - /// Channel commutation event generation - CMTG: u1, - /// Trigger event generation - TRGG: u1, - /// Break event generation - BRKG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x14); - - /// address: 0x40012c18 - /// Channel control register 0 (output - /// mode) - pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), base_address + 0x18); - - /// address: 0x40012c18 - /// Channel control register 0 (input - /// mode) - pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 mode selection - CH0MS: u2, - /// Channel 0 input capture prescaler - CH0CAPPSC: u2, - /// Channel 0 input capture filter control - CH0CAPFLT: u4, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 input capture prescaler - CH1CAPPSC: u2, - /// Channel 1 input capture filter control - CH1CAPFLT: u4, - }), base_address + 0x18); - - /// address: 0x40012c1c - /// Channel control register 1 (output - /// mode) - pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), base_address + 0x1c); - - /// address: 0x40012c1c - /// Channel control register 1 (input - /// mode) - pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 mode selection - CH2MS: u2, - /// Channel 2 input capture prescaler - CH2CAPPSC: u2, - /// Channel 2 input capture filter control - CH2CAPFLT: u4, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 input capture prescaler - CH3CAPPSC: u2, - /// Channel 3 input capture filter control - CH3CAPFLT: u4, - }), base_address + 0x1c); - - /// address: 0x40012c20 - /// Channel control register 2 - pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - /// Channel 0 complementary output enable - CH0NEN: u1, - /// Channel 0 complementary output polarity - CH0NP: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - /// Channel 1 complementary output enable - CH1NEN: u1, - /// Channel 1 complementary output polarity - CH1NP: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - /// Channel 2 complementary output enable - CH2NEN: u1, - /// Channel 2 complementary output polarity - CH2NP: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40012c24 - /// counter - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40012c28 - /// prescaler - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x40012c2c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - - /// address: 0x40012c30 - /// Counter repetition register - pub const CREP = @intToPtr(*volatile MmioInt(16, u8), base_address + 0x30); - - /// address: 0x40012c34 - /// Channel 0 capture/compare value register - pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel0 - CH0VAL: u16, - }), base_address + 0x34); - - /// address: 0x40012c38 - /// Channel 1 capture/compare value register - pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), base_address + 0x38); - - /// address: 0x40012c3c - /// Channel 2 capture/compare value register - pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), base_address + 0x3c); - - /// address: 0x40012c40 - /// Channel 3 capture/compare value register - pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), base_address + 0x40); - - /// address: 0x40012c44 - /// channel complementary protection register - pub const CCHP = @intToPtr(*volatile Mmio(16, packed struct { - /// Dead time configure - DTCFG: u8, - /// Complementary register protect control - PROT: u2, - /// Idle mode off-state configure - IOS: u1, - /// Run mode off-state configure - ROS: u1, - /// Break enable - BRKEN: u1, - /// Break polarity - BRKP: u1, - /// Output automatic enable - OAEN: u1, - /// Primary output enable - POEN: u1, - }), base_address + 0x44); - - /// address: 0x40012c48 - /// DMA configuration register - pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA transfer access start address - DMATA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA transfer count - DMATC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x48); - - /// address: 0x40012c4c - /// DMA transfer buffer register - pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); - }; - - /// General-purpose-timers - pub const TIMER1 = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// slave mode control register - pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Slave mode control - SMC: u3, - reserved0: u1, - /// Trigger selection - TRGS: u3, - /// Master-slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TRGIE: u1, - reserved1: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - reserved2: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x40000010 - /// interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt enable - CH2IF: u1, - /// Channel 3 capture/compare interrupt enable - CH3IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TRGIF: u1, - reserved1: u1, - reserved2: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - reserved0: u1, - /// Trigger event generation - TRGG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// Channel control register 0 (output - /// mode) - pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), base_address + 0x18); - - /// address: 0x40000018 - /// Channel control register 0 (input - /// mode) - pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 mode selection - CH0MS: u2, - /// Channel 0 input capture prescaler - CH0CAPPSC: u2, - /// Channel 0 input capture filter control - CH0CAPFLT: u4, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 input capture prescaler - CH1CAPPSC: u2, - /// Channel 1 input capture filter control - CH1CAPFLT: u4, - }), base_address + 0x18); - - /// address: 0x4000001c - /// Channel control register 1 (output mode) - pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), base_address + 0x1c); - - /// address: 0x4000001c - /// Channel control register 1 (input - /// mode) - pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 mode selection - CH2MS: u2, - /// Channel 2 input capture prescaler - CH2CAPPSC: u2, - /// Channel 2 input capture filter control - CH2CAPFLT: u4, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 input capture prescaler - CH3CAPPSC: u2, - /// Channel 3 input capture filter control - CH3CAPFLT: u4, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// Channel control register 2 - pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - reserved0: u1, - reserved1: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - reserved2: u1, - reserved3: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - reserved4: u1, - reserved5: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40000024 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40000028 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x4000002c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - - /// address: 0x40000034 - /// Channel 0 capture/compare value register - pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 0 - CH0VAL: u16, - }), base_address + 0x34); - - /// address: 0x40000038 - /// Channel 1 capture/compare value register - pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), base_address + 0x38); - - /// address: 0x4000003c - /// Channel 2 capture/compare value register - pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), base_address + 0x3c); - - /// address: 0x40000040 - /// Channel 3 capture/compare value register - pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), base_address + 0x40); - - /// address: 0x40000048 - /// DMA configuration register - pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA transfer access start address - DMATA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA transfer count - DMATC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x48); - - /// address: 0x4000004c - /// DMA transfer buffer register - pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); - }; - pub const TIMER2 = struct { - pub const base_address = 0x40000400; - - /// address: 0x40000400 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40000404 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40000408 - /// slave mode control register - pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Slave mode control - SMC: u3, - reserved0: u1, - /// Trigger selection - TRGS: u3, - /// Master-slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), base_address + 0x8); - - /// address: 0x4000040c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TRGIE: u1, - reserved1: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - reserved2: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x40000410 - /// interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt enable - CH2IF: u1, - /// Channel 3 capture/compare interrupt enable - CH3IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TRGIF: u1, - reserved1: u1, - reserved2: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0x40000414 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - reserved0: u1, - /// Trigger event generation - TRGG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - - /// address: 0x40000418 - /// Channel control register 0 (output - /// mode) - pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), base_address + 0x18); - - /// address: 0x40000418 - /// Channel control register 0 (input - /// mode) - pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 mode selection - CH0MS: u2, - /// Channel 0 input capture prescaler - CH0CAPPSC: u2, - /// Channel 0 input capture filter control - CH0CAPFLT: u4, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 input capture prescaler - CH1CAPPSC: u2, - /// Channel 1 input capture filter control - CH1CAPFLT: u4, - }), base_address + 0x18); - - /// address: 0x4000041c - /// Channel control register 1 (output mode) - pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), base_address + 0x1c); - - /// address: 0x4000041c - /// Channel control register 1 (input - /// mode) - pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 mode selection - CH2MS: u2, - /// Channel 2 input capture prescaler - CH2CAPPSC: u2, - /// Channel 2 input capture filter control - CH2CAPFLT: u4, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 input capture prescaler - CH3CAPPSC: u2, - /// Channel 3 input capture filter control - CH3CAPFLT: u4, - }), base_address + 0x1c); - - /// address: 0x40000420 - /// Channel control register 2 - pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - reserved0: u1, - reserved1: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - reserved2: u1, - reserved3: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - reserved4: u1, - reserved5: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40000424 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40000428 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x4000042c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - - /// address: 0x40000434 - /// Channel 0 capture/compare value register - pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 0 - CH0VAL: u16, - }), base_address + 0x34); - - /// address: 0x40000438 - /// Channel 1 capture/compare value register - pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), base_address + 0x38); - - /// address: 0x4000043c - /// Channel 2 capture/compare value register - pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), base_address + 0x3c); - - /// address: 0x40000440 - /// Channel 3 capture/compare value register - pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), base_address + 0x40); - - /// address: 0x40000448 - /// DMA configuration register - pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA transfer access start address - DMATA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA transfer count - DMATC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x48); - - /// address: 0x4000044c - /// DMA transfer buffer register - pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); - }; - pub const TIMER3 = struct { - pub const base_address = 0x40000800; - - /// address: 0x40000800 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40000804 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40000808 - /// slave mode control register - pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Slave mode control - SMC: u3, - reserved0: u1, - /// Trigger selection - TRGS: u3, - /// Master-slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), base_address + 0x8); - - /// address: 0x4000080c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TRGIE: u1, - reserved1: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - reserved2: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x40000810 - /// interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt enable - CH2IF: u1, - /// Channel 3 capture/compare interrupt enable - CH3IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TRGIF: u1, - reserved1: u1, - reserved2: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - reserved0: u1, - /// Trigger event generation - TRGG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// Channel control register 0 (output - /// mode) - pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), base_address + 0x18); - - /// address: 0x40000818 - /// Channel control register 0 (input - /// mode) - pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 mode selection - CH0MS: u2, - /// Channel 0 input capture prescaler - CH0CAPPSC: u2, - /// Channel 0 input capture filter control - CH0CAPFLT: u4, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 input capture prescaler - CH1CAPPSC: u2, - /// Channel 1 input capture filter control - CH1CAPFLT: u4, - }), base_address + 0x18); - - /// address: 0x4000081c - /// Channel control register 1 (output mode) - pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), base_address + 0x1c); - - /// address: 0x4000081c - /// Channel control register 1 (input - /// mode) - pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 mode selection - CH2MS: u2, - /// Channel 2 input capture prescaler - CH2CAPPSC: u2, - /// Channel 2 input capture filter control - CH2CAPFLT: u4, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 input capture prescaler - CH3CAPPSC: u2, - /// Channel 3 input capture filter control - CH3CAPFLT: u4, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// Channel control register 2 - pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - reserved0: u1, - reserved1: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - reserved2: u1, - reserved3: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - reserved4: u1, - reserved5: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40000824 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40000828 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x4000082c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - - /// address: 0x40000834 - /// Channel 0 capture/compare value register - pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 0 - CH0VAL: u16, - }), base_address + 0x34); - - /// address: 0x40000838 - /// Channel 1 capture/compare value register - pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), base_address + 0x38); - - /// address: 0x4000083c - /// Channel 2 capture/compare value register - pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), base_address + 0x3c); - - /// address: 0x40000840 - /// Channel 3 capture/compare value register - pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), base_address + 0x40); - - /// address: 0x40000848 - /// DMA configuration register - pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA transfer access start address - DMATA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA transfer count - DMATC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x48); - - /// address: 0x4000084c - /// DMA transfer buffer register - pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); - }; - pub const TIMER4 = struct { - pub const base_address = 0x40000c00; - - /// address: 0x40000c00 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40000c04 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40000c08 - /// slave mode control register - pub const SMCFG = @intToPtr(*volatile Mmio(16, packed struct { - /// Slave mode control - SMC: u3, - reserved0: u1, - /// Trigger selection - TRGS: u3, - /// Master-slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), base_address + 0x8); - - /// address: 0x40000c0c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TRGIE: u1, - reserved1: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - reserved2: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x40000c10 - /// interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt enable - CH2IF: u1, - /// Channel 3 capture/compare interrupt enable - CH3IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TRGIF: u1, - reserved1: u1, - reserved2: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - - /// address: 0x40000c14 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - reserved0: u1, - /// Trigger event generation - TRGG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - - /// address: 0x40000c18 - /// Channel control register 0 (output - /// mode) - pub const CHCTL0_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), base_address + 0x18); - - /// address: 0x40000c18 - /// Channel control register 0 (input - /// mode) - pub const CHCTL0_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 mode selection - CH0MS: u2, - /// Channel 0 input capture prescaler - CH0CAPPSC: u2, - /// Channel 0 input capture filter control - CH0CAPFLT: u4, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 input capture prescaler - CH1CAPPSC: u2, - /// Channel 1 input capture filter control - CH1CAPFLT: u4, - }), base_address + 0x18); - - /// address: 0x40000c1c - /// Channel control register 1 (output mode) - pub const CHCTL1_Output = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), base_address + 0x1c); - - /// address: 0x40000c1c - /// Channel control register 1 (input - /// mode) - pub const CHCTL1_Input = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 2 mode selection - CH2MS: u2, - /// Channel 2 input capture prescaler - CH2CAPPSC: u2, - /// Channel 2 input capture filter control - CH2CAPFLT: u4, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 input capture prescaler - CH3CAPPSC: u2, - /// Channel 3 input capture filter control - CH3CAPFLT: u4, - }), base_address + 0x1c); - - /// address: 0x40000c20 - /// Channel control register 2 - pub const CHCTL2 = @intToPtr(*volatile Mmio(16, packed struct { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - reserved0: u1, - reserved1: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - reserved2: u1, - reserved3: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - reserved4: u1, - reserved5: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40000c24 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40000c28 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x40000c2c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - - /// address: 0x40000c34 - /// Channel 0 capture/compare value register - pub const CH0CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 0 - CH0VAL: u16, - }), base_address + 0x34); - - /// address: 0x40000c38 - /// Channel 1 capture/compare value register - pub const CH1CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), base_address + 0x38); - - /// address: 0x40000c3c - /// Channel 2 capture/compare value register - pub const CH2CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), base_address + 0x3c); - - /// address: 0x40000c40 - /// Channel 3 capture/compare value register - pub const CH3CV = @intToPtr(*volatile Mmio(16, packed struct { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), base_address + 0x40); - - /// address: 0x40000c48 - /// DMA configuration register - pub const DMACFG = @intToPtr(*volatile Mmio(16, packed struct { - /// DMA transfer access start address - DMATA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA transfer count - DMATC: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x48); - - /// address: 0x40000c4c - /// DMA transfer buffer register - pub const DMATB = @intToPtr(*volatile u16, base_address + 0x4c); - }; - - /// Basic-timers - pub const TIMER5 = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload shadow enable - ARSE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode control - MMC: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x4); - - /// address: 0x4000100c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UPDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// Interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x14); - - /// address: 0x40001024 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40001028 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x4000102c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - }; - pub const TIMER6 = struct { - pub const base_address = 0x40001400; - - /// address: 0x40001400 - /// control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload shadow enable - ARSE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(16, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode control - MMC: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x4); - - /// address: 0x4000140c - /// DMA/Interrupt enable register - pub const DMAINTEN = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt enable - UPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UPDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// Interrupt flag register - pub const INTF = @intToPtr(*volatile Mmio(16, packed struct { - /// Update interrupt flag - UPIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// event generation register - pub const SWEVG = @intToPtr(*volatile Mmio(16, packed struct { - /// Update generation - UPG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x14); - - /// address: 0x40001424 - /// Counter register - pub const CNT = @intToPtr(*volatile u16, base_address + 0x24); - - /// address: 0x40001428 - /// Prescaler register - pub const PSC = @intToPtr(*volatile u16, base_address + 0x28); - - /// address: 0x4000142c - /// Counter auto reload register - pub const CAR = @intToPtr(*volatile Mmio(16, packed struct { - /// Counter auto reload value - CARL: u16, - }), base_address + 0x2c); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const USART0 = struct { - pub const base_address = 0x40013800; - - /// address: 0x40013800 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS change flag - CTSF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40013804 - /// Data register - pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40013808 - /// Baud rate register - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001380c - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40013810 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART - ADDR: u4, - reserved0: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// CK Length - CLEN: u1, - /// Clock phase - CPH: u1, - /// Clock polarity - CPL: u1, - /// CK pin enable - CKEN: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40013814 - /// Control register 2 - pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - /// Smartcard NACK enable - NKEN: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - /// RTS enable - RTSEN: u1, - /// CTS enable - CTSEN: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40013818 - /// Guard time and prescaler - /// register - pub const GP = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value in Smartcard mode - GUAT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART1 = struct { - pub const base_address = 0x40004400; - - /// address: 0x40004400 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS change flag - CTSF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004404 - /// Data register - pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004408 - /// Baud rate register - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000440c - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004410 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART - ADDR: u4, - reserved0: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// CK Length - CLEN: u1, - /// Clock phase - CPH: u1, - /// Clock polarity - CPL: u1, - /// CK pin enable - CKEN: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004414 - /// Control register 2 - pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - /// Smartcard NACK enable - NKEN: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - /// RTS enable - RTSEN: u1, - /// CTS enable - CTSEN: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40004418 - /// Guard time and prescaler - /// register - pub const GP = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value in Smartcard mode - GUAT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART2 = struct { - pub const base_address = 0x40004800; - - /// address: 0x40004800 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS change flag - CTSF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004804 - /// Data register - pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004808 - /// Baud rate register - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000480c - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004810 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART - ADDR: u4, - reserved0: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// CK Length - CLEN: u1, - /// Clock phase - CPH: u1, - /// Clock polarity - CPL: u1, - /// CK pin enable - CKEN: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004814 - /// Control register 2 - pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - /// Smartcard NACK enable - NKEN: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - /// RTS enable - RTSEN: u1, - /// CTS enable - CTSEN: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40004818 - /// Guard time and prescaler - /// register - pub const GP = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value in Smartcard mode - GUAT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - - /// Universal asynchronous receiver - /// transmitter - pub const UART3 = struct { - pub const base_address = 0x40004c00; - - /// address: 0x40004c00 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40004c04 - /// Data register - pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004c08 - /// Baud rate register - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40004c0c - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004c10 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART - ADDR: u4, - reserved0: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004c14 - /// Control register 2 - pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - reserved0: u1, - reserved1: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40004c18 - /// Guard time and prescaler - /// register - pub const GP = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - }; - pub const UART4 = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Data register - pub const DATA = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40005008 - /// Baud rate register - pub const BAUD = @intToPtr(*volatile Mmio(32, packed struct { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000500c - /// Control register 0 - pub const CTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40005010 - /// Control register 1 - pub const CTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART - ADDR: u4, - reserved0: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40005014 - /// Control register 2 - pub const CTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - reserved0: u1, - reserved1: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40005018 - /// Guard time and prescaler - /// register - pub const GP = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - }; - - /// USB full speed global registers - pub const USBFS_GLOBAL = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000000 - /// Global OTG control and status register - /// (USBFS_GOTGCS) - pub const GOTGCS = @intToPtr(*volatile Mmio(32, packed struct { - /// SRP success - SRPS: u1, - /// SRP request - SRPREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Host success - HNPS: u1, - /// HNP request - HNPREQ: u1, - /// Host HNP enable - HHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// ID pin status - IDPS: u1, - /// Debounce interval - DI: u1, - /// A-session valid - ASV: u1, - /// B-session valid - BSV: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x50000004 - /// Global OTG interrupt flag register - /// (USBFS_GOTGINTF) - pub const GOTGINTF = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Session end - SESEND: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Session request success status - /// change - SRPEND: u1, - /// HNP end - HNPEND: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Host negotiation request detected - HNPDET: u1, - /// A-device timeout - ADTO: u1, - /// Debounce finish - DF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x50000008 - /// Global AHB control and status register - /// (USBFS_GAHBCS) - pub const GAHBCS = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt enable - GINTEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Tx FIFO threshold - TXFTH: u1, - /// Periodic Tx FIFO threshold - PTXFTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x5000000c - /// Global USB control and status register - /// (USBFS_GUSBCSR) - pub const GUSBCS = @intToPtr(*volatile Mmio(32, packed struct { - /// Timeout calibration - TOC: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// SRP capability enable - SRPCEN: u1, - /// HNP capability enable - HNPCEN: u1, - /// USB turnaround time - UTT: u4, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Force host mode - FHM: u1, - /// Force device mode - FDM: u1, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x50000010 - /// Global reset control register (USBFS_GRSTCTL) - pub const GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HCSRST: u1, - /// Host frame counter reset - HFCRST: u1, - reserved0: u1, - /// RxFIFO flush - RXFF: u1, - /// TxFIFO flush - TXFF: u1, - /// TxFIFO number - TXFNUM: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x50000014 - /// Global interrupt flag register (USBFS_GINTF) - pub const GINTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Current operation mode - COPM: u1, - /// Mode fault interrupt flag - MFIF: u1, - /// OTG interrupt flag - OTGIF: u1, - /// Start of frame - SOF: u1, - /// RxFIFO non-empty interrupt flag - RXFNEIF: u1, - /// Non-periodic TxFIFO empty interrupt flag - NPTXFEIF: u1, - /// Global Non-Periodic IN NAK effective - GNPINAK: u1, - /// Global OUT NAK effective - GONAK: u1, - reserved0: u1, - reserved1: u1, - /// Early suspend - ESP: u1, - /// USB suspend - SP: u1, - /// USB reset - RST: u1, - /// Enumeration finished - ENUMF: u1, - /// Isochronous OUT packet dropped - /// interrupt - ISOOPDIF: u1, - /// End of periodic frame - /// interrupt flag - EOPFIF: u1, - reserved2: u1, - reserved3: u1, - /// IN endpoint interrupt flag - IEPIF: u1, - /// OUT endpoint interrupt flag - OEPIF: u1, - /// Isochronous IN transfer Not Complete Interrupt Flag - ISOINCIF: u1, - /// periodic transfer not complete interrupt flag(Host - /// mode)/isochronous OUT transfer not complete interrupt flag(Device - /// mode) - PXNCIF_ISOONCIF: u1, - reserved4: u1, - reserved5: u1, - /// Host port interrupt flag - HPIF: u1, - /// Host channels interrupt flag - HCIF: u1, - /// Periodic TxFIFO empty interrupt flag - PTXFEIF: u1, - reserved6: u1, - /// ID pin status change - IDPSC: u1, - /// Disconnect interrupt flag - DISCIF: u1, - /// Session interrupt flag - SESIF: u1, - /// Wakeup interrupt flag - WKUPIF: u1, - }), base_address + 0x14); - - /// address: 0x50000018 - /// Global interrupt enable register - /// (USBFS_GINTEN) - pub const GINTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Mode fault interrupt - /// enable - MFIE: u1, - /// OTG interrupt enable - OTGIE: u1, - /// Start of frame interrupt enable - SOFIE: u1, - /// Receive FIFO non-empty - /// interrupt enable - RXFNEIE: u1, - /// Non-periodic TxFIFO empty - /// interrupt enable - NPTXFEIE: u1, - /// Global non-periodic IN NAK effective interrupt enable - GNPINAKIE: u1, - /// Global OUT NAK effective - /// interrupt enable - GONAKIE: u1, - reserved1: u1, - reserved2: u1, - /// Early suspend interrupt enable - ESPIE: u1, - /// USB suspend interrupt enable - SPIE: u1, - /// USB reset interrupt enable - RSTIE: u1, - /// Enumeration finish interrupt enable - ENUMFIE: u1, - /// Isochronous OUT packet dropped interrupt enable - ISOOPDIE: u1, - /// End of periodic frame interrupt enable - EOPFIE: u1, - reserved3: u1, - reserved4: u1, - /// IN endpoints interrupt enable - IEPIE: u1, - /// OUT endpoints interrupt enable - OEPIE: u1, - /// isochronous IN transfer not complete - /// interrupt enable - ISOINCIE: u1, - /// periodic transfer not compelete Interrupt enable(Host - /// mode)/isochronous OUT transfer not complete interrupt enable(Device - /// mode) - PXNCIE_ISOONCIE: u1, - reserved5: u1, - reserved6: u1, - /// Host port interrupt enable - HPIE: u1, - /// Host channels interrupt enable - HCIE: u1, - /// Periodic TxFIFO empty interrupt enable - PTXFEIE: u1, - reserved7: u1, - /// ID pin status change interrupt enable - IDPSCIE: u1, - /// Disconnect interrupt enable - DISCIE: u1, - /// Session interrupt enable - SESIE: u1, - /// Wakeup interrupt enable - WKUPIE: u1, - }), base_address + 0x18); - - /// address: 0x5000001c - /// Global Receive status read(Device - /// mode) - pub const GRSTATR_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Recieve packet status - RPCKST: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x1c); - - /// address: 0x5000001c - /// Global Receive status read(Host - /// mode) - pub const GRSTATR_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Reivece packet status - RPCKST: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x1c); - - /// address: 0x50000020 - /// Global Receive status pop(Device - /// mode) - pub const GRSTATP_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Recieve packet status - RPCKST: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x50000020 - /// Global Receive status pop(Host - /// mode) - pub const GRSTATP_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Reivece packet status - RPCKST: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x50000024 - /// Global Receive FIFO size register - /// (USBFS_GRFLEN) - pub const GRFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx FIFO depth - RXFD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x50000028 - /// Host non-periodic transmit FIFO length register - /// (Host mode) - pub const HNPTFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// host non-periodic transmit Tx RAM start - /// address - HNPTXRSAR: u16, - /// host non-periodic TxFIFO depth - HNPTXFD: u16, - }), base_address + 0x28); - - /// address: 0x50000028 - /// Device IN endpoint 0 transmit FIFO length - /// (Device mode) - pub const DIEP0TFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// in endpoint 0 Tx RAM start address - IEP0TXRSAR: u16, - /// in endpoint 0 Tx FIFO depth - IEP0TXFD: u16, - }), base_address + 0x28); - - /// address: 0x5000002c - /// Host non-periodic transmit FIFO/queue - /// status register (HNPTFQSTAT) - pub const HNPTFQSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-periodic TxFIFO space - NPTXFS: u16, - /// Non-periodic transmit request queue - /// space - NPTXRQS: u8, - /// Top of the non-periodic transmit request - /// queue - NPTXRQTOP: u7, - padding0: u1, - }), base_address + 0x2c); - - /// address: 0x50000038 - /// Global core configuration register (USBFS_GCCFG) - pub const GCCFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Power on - PWRON: u1, - reserved16: u1, - /// The VBUS A-device Comparer enable - VBUSACEN: u1, - /// The VBUS B-device Comparer enable - VBUSBCEN: u1, - /// SOF output enable - SOFOEN: u1, - /// VBUS ignored - VBUSIG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x5000003c - /// core ID register - pub const CID = @intToPtr(*volatile u32, base_address + 0x3c); - - /// address: 0x50000100 - /// Host periodic transmit FIFO length register (HPTFLEN) - pub const HPTFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Host periodic TxFIFO start - /// address - HPTXFSAR: u16, - /// Host periodic TxFIFO depth - HPTXFD: u16, - }), base_address + 0x100); - - /// address: 0x50000104 - /// device IN endpoint transmit FIFO size - /// register (DIEP1TFLEN) - pub const DIEP1TFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO transmit RAM start - /// address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), base_address + 0x104); - - /// address: 0x50000108 - /// device IN endpoint transmit FIFO size - /// register (DIEP2TFLEN) - pub const DIEP2TFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO transmit RAM start - /// address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), base_address + 0x108); - - /// address: 0x5000010c - /// device IN endpoint transmit FIFO size - /// register (FS_DIEP3TXFLEN) - pub const DIEP3TFLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO4 transmit RAM start - /// address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), base_address + 0x10c); - }; - - /// USB on the go full speed host - pub const USBFS_HOST = struct { - pub const base_address = 0x50000400; - - /// address: 0x50000400 - /// host configuration register - /// (HCTL) - pub const HCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// clock select for USB clock - CLKSEL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - - /// address: 0x50000404 - /// Host frame interval - /// register - pub const HFT = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interval - FRI: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x50000408 - /// FS host frame number/frame time - /// remaining register (HFINFR) - pub const HFINFR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FRNUM: u16, - /// Frame remaining time - FRT: u16, - }), base_address + 0x8); - - /// address: 0x50000410 - /// Host periodic transmit FIFO/queue - /// status register (HPTFQSTAT) - pub const HPTFQSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic transmit data FIFO space - /// available - PTXFS: u16, - /// Periodic transmit request queue space - /// available - PTXREQS: u8, - /// Top of the periodic transmit request - /// queue - PTXREQT: u8, - }), base_address + 0x10); - - /// address: 0x50000414 - /// Host all channels interrupt - /// register - pub const HACHINT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x14); - - /// address: 0x50000418 - /// host all channels interrupt mask - /// register - pub const HACHINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupt enable - CINTEN: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x50000440 - /// Host port control and status register (USBFS_HPCS) - pub const HPCS = @intToPtr(*volatile Mmio(32, packed struct { - /// Port connect status - PCST: u1, - /// Port connect detected - PCD: u1, - /// Port enable - PE: u1, - /// Port enable/disable change - PEDC: u1, - reserved0: u1, - reserved1: u1, - /// Port resume - PREM: u1, - /// Port suspend - PSP: u1, - /// Port reset - PRST: u1, - reserved2: u1, - /// Port line status - PLST: u2, - /// Port power - PP: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Port speed - PS: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x50000500 - /// host channel-0 characteristics - /// register (HCH0CTL) - pub const HCH0CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x100); - - /// address: 0x50000520 - /// host channel-1 characteristics - /// register (HCH1CTL) - pub const HCH1CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x120); - - /// address: 0x50000540 - /// host channel-2 characteristics - /// register (HCH2CTL) - pub const HCH2CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x140); - - /// address: 0x50000560 - /// host channel-3 characteristics - /// register (HCH3CTL) - pub const HCH3CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x160); - - /// address: 0x50000580 - /// host channel-4 characteristics - /// register (HCH4CTL) - pub const HCH4CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x180); - - /// address: 0x500005a0 - /// host channel-5 characteristics - /// register (HCH5CTL) - pub const HCH5CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x1a0); - - /// address: 0x500005c0 - /// host channel-6 characteristics - /// register (HCH6CTL) - pub const HCH6CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x1c0); - - /// address: 0x500005e0 - /// host channel-7 characteristics - /// register (HCH7CTL) - pub const HCH7CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved1: u1, - reserved2: u1, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), base_address + 0x1e0); - - /// address: 0x50000508 - /// host channel-0 interrupt register - /// (USBFS_HCHxINTF) - pub const HCH0INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x108); - - /// address: 0x50000528 - /// host channel-1 interrupt register - /// (HCH1INTF) - pub const HCH1INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x128); - - /// address: 0x50000548 - /// host channel-2 interrupt register - /// (HCH2INTF) - pub const HCH2INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x148); - - /// address: 0x50000568 - /// host channel-3 interrupt register - /// (HCH3INTF) - pub const HCH3INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x168); - - /// address: 0x50000588 - /// host channel-4 interrupt register - /// (HCH4INTF) - pub const HCH4INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x188); - - /// address: 0x500005a8 - /// host channel-5 interrupt register - /// (HCH5INTF) - pub const HCH5INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1a8); - - /// address: 0x500005c8 - /// host channel-6 interrupt register - /// (HCH6INTF) - pub const HCH6INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c8); - - /// address: 0x500005e8 - /// host channel-7 interrupt register - /// (HCH7INTF) - pub const HCH7INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1e8); - - /// address: 0x5000050c - /// host channel-0 interrupt enable register - /// (HCH0INTEN) - pub const HCH0INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10c); - - /// address: 0x5000052c - /// host channel-1 interrupt enable register - /// (HCH1INTEN) - pub const HCH1INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x12c); - - /// address: 0x5000054c - /// host channel-2 interrupt enable register - /// (HCH2INTEN) - pub const HCH2INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14c); - - /// address: 0x5000056c - /// host channel-3 interrupt enable register - /// (HCH3INTEN) - pub const HCH3INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x16c); - - /// address: 0x5000058c - /// host channel-4 interrupt enable register - /// (HCH4INTEN) - pub const HCH4INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18c); - - /// address: 0x500005ac - /// host channel-5 interrupt enable register - /// (HCH5INTEN) - pub const HCH5INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ac); - - /// address: 0x500005cc - /// host channel-6 interrupt enable register - /// (HCH6INTEN) - pub const HCH6INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1cc); - - /// address: 0x500005ec - /// host channel-7 interrupt enable register - /// (HCH7INTEN) - pub const HCH7INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved0: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved1: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ec); - - /// address: 0x50000510 - /// host channel-0 transfer length - /// register - pub const HCH0LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x110); - - /// address: 0x50000530 - /// host channel-1 transfer length - /// register - pub const HCH1LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000550 - /// host channel-2 transfer length - /// register - pub const HCH2LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000570 - /// host channel-3 transfer length - /// register - pub const HCH3LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000590 - /// host channel-4 transfer length - /// register - pub const HCH4LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x500005b0 - /// host channel-5 transfer length - /// register - pub const HCH5LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x500005d0 - /// host channel-6 transfer length - /// register - pub const HCH6LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1d0); - - /// address: 0x500005f0 - /// host channel-7 transfer length - /// register - pub const HCH7LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1f0); - }; - - /// USB on the go full speed device - pub const USBFS_DEVICE = struct { - pub const base_address = 0x50000800; - - /// address: 0x50000800 - /// device configuration register - /// (DCFG) - pub const DCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Device speed - DS: u2, - /// Non-zero-length status OUT - /// handshake - NZLSOH: u1, - reserved0: u1, - /// Device address - DAR: u7, - /// end of periodic frame time - EOPFT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x0); - - /// address: 0x50000804 - /// device control register - /// (DCTL) - pub const DCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Remote wakeup - RWKUP: u1, - /// Soft disconnect - SD: u1, - /// Global IN NAK status - GINS: u1, - /// Global OUT NAK status - GONS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on initialization flag - POIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x50000808 - /// device status register - /// (DSTAT) - pub const DSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Suspend status - SPST: u1, - /// Enumerated speed - ES: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Frame number of the received - /// SOF - FNRSOF: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x50000810 - /// device IN endpoint common interrupt - /// mask register (DIEPINTEN) - pub const DIEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished interrupt - /// enable - TFEN: u1, - /// Endpoint disabled interrupt - /// enable - EPDISEN: u1, - reserved0: u1, - /// Control IN timeout condition interrupt enable (Non-isochronous - /// endpoints) - CITOEN: u1, - /// Endpoint Tx FIFO underrun interrupt enable bit - EPTXFUDEN: u1, - reserved1: u1, - /// IN endpoint NAK effective - /// interrupt enable - IEPNEEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x10); - - /// address: 0x50000814 - /// device OUT endpoint common interrupt - /// enable register (DOEPINTEN) - pub const DOEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished interrupt - /// enable - TFEN: u1, - /// Endpoint disabled interrupt - /// enable - EPDISEN: u1, - reserved0: u1, - /// SETUP phase finished interrupt enable - STPFEN: u1, - /// Endpoint Rx FIFO overrun interrupt enable - EPRXFOVREN: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// interrupt enable - BTBSTPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x50000818 - /// device all endpoints interrupt - /// register (DAEPINT) - pub const DAEPINT = @intToPtr(*volatile Mmio(32, packed struct { - /// Device all IN endpoint interrupt bits - IEPITB: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Device all OUT endpoint interrupt bits - OEPITB: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x18); - - /// address: 0x5000081c - /// Device all endpoints interrupt enable register - /// (DAEPINTEN) - pub const DAEPINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP interrupt interrupt enable bits - IEPIE: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// OUT endpoint interrupt enable bits - OEPIE: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x1c); - - /// address: 0x50000828 - /// device VBUS discharge time - /// register - pub const DVBUSDT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x5000082c - /// device VBUS pulsing time - /// register - pub const DVBUSPT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x2c); - - /// address: 0x50000834 - /// device IN endpoint FIFO empty - /// interrupt enable register - pub const DIEPFEINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP Tx FIFO empty interrupt enable - /// bits - IEPTXFEIE: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x34); - - /// address: 0x50000900 - /// device IN endpoint 0 control - /// register (DIEP0CTL) - pub const DIEP0CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet length - MPL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// endpoint active - EPACT: u1, - reserved13: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved14: u1, - /// STALL handshake - STALL: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved15: u1, - reserved16: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x100); - - /// address: 0x50000920 - /// device in endpoint-1 control - /// register - pub const DIEP1CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved4: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x120); - - /// address: 0x50000940 - /// device endpoint-2 control - /// register - pub const DIEP2CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved4: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x140); - - /// address: 0x50000960 - /// device endpoint-3 control - /// register - pub const DIEP3CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved4: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x160); - - /// address: 0x50000b00 - /// device endpoint-0 control - /// register - pub const DOEP0CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet length - MPL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Endpoint active - EPACT: u1, - reserved13: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved18: u1, - reserved19: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x300); - - /// address: 0x50000b20 - /// device endpoint-1 control - /// register - pub const DOEP1CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x320); - - /// address: 0x50000b40 - /// device endpoint-2 control - /// register - pub const DOEP2CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x340); - - /// address: 0x50000b60 - /// device endpoint-3 control - /// register - pub const DOEP3CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// maximum packet length - MPL: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), base_address + 0x360); - - /// address: 0x50000908 - /// device endpoint-0 interrupt - /// register - pub const DIEP0INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved0: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved1: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x108); - - /// address: 0x50000928 - /// device endpoint-1 interrupt - /// register - pub const DIEP1INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved0: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved1: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x128); - - /// address: 0x50000948 - /// device endpoint-2 interrupt - /// register - pub const DIEP2INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved0: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved1: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x148); - - /// address: 0x50000968 - /// device endpoint-3 interrupt - /// register - pub const DIEP3INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved0: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved1: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x168); - - /// address: 0x50000b08 - /// device out endpoint-0 interrupt flag - /// register - pub const DOEP0INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved0: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved1: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x308); - - /// address: 0x50000b28 - /// device out endpoint-1 interrupt flag - /// register - pub const DOEP1INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved0: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved1: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x328); - - /// address: 0x50000b48 - /// device out endpoint-2 interrupt flag - /// register - pub const DOEP2INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved0: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved1: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x348); - - /// address: 0x50000b68 - /// device out endpoint-3 interrupt flag - /// register - pub const DOEP3INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved0: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved1: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x368); - - /// address: 0x50000910 - /// device IN endpoint-0 transfer length - /// register - pub const DIEP0LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PCNT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x110); - - /// address: 0x50000b10 - /// device OUT endpoint-0 transfer length - /// register - pub const DOEP0LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PCNT: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// SETUP packet count - STPCNT: u2, - padding0: u1, - }), base_address + 0x310); - - /// address: 0x50000930 - /// device IN endpoint-1 transfer length - /// register - pub const DIEP1LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000950 - /// device IN endpoint-2 transfer length - /// register - pub const DIEP2LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000970 - /// device IN endpoint-3 transfer length - /// register - pub const DIEP3LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000b30 - /// device OUT endpoint-1 transfer length - /// register - pub const DOEP1LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding0: u1, - }), base_address + 0x330); - - /// address: 0x50000b50 - /// device OUT endpoint-2 transfer length - /// register - pub const DOEP2LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding0: u1, - }), base_address + 0x350); - - /// address: 0x50000b70 - /// device OUT endpoint-3 transfer length - /// register - pub const DOEP3LEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding0: u1, - }), base_address + 0x370); - - /// address: 0x50000918 - /// device IN endpoint 0 transmit FIFO - /// status register - pub const DIEP0TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// remaining - IEPTFS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x118); - - /// address: 0x50000938 - /// device IN endpoint 1 transmit FIFO - /// status register - pub const DIEP1TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// remaining - IEPTFS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x138); - - /// address: 0x50000958 - /// device IN endpoint 2 transmit FIFO - /// status register - pub const DIEP2TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// remaining - IEPTFS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x158); - - /// address: 0x50000978 - /// device IN endpoint 3 transmit FIFO - /// status register - pub const DIEP3TFSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// remaining - IEPTFS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x178); - }; - - /// USB on the go full speed - pub const USBFS_PWRCLK = struct { - pub const base_address = 0x50000e00; - - /// address: 0x50000e00 - /// power and clock gating control - /// register (PWRCLKCTL) - pub const PWRCLKCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop the USB clock - SUCLK: u1, - /// Stop HCLK - SHCLK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - }; - - /// Window watchdog timer - pub const WWDGT = struct { - pub const base_address = 0x40002c00; - - /// address: 0x40002c00 - /// Control register - pub const CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit counter - CNT: u7, - /// Activation bit - WDGTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40002c04 - /// Configuration register - pub const CFG = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit window value - WIN: u7, - /// Prescaler - PSC: u2, - /// Early wakeup interrupt - EWIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x40002c08 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Early wakeup interrupt - /// flag - EWIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// Core timer - pub const CTIMER = struct { - pub const base_address = 0xd1000000; - - /// address: 0xd1000000 - /// Timer value (lower half) - pub const mtime_lo = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0xd1000004 - /// Timer value (upper half) - pub const mtime_hi = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0xd1000008 - /// Timer comparison value (lower half) - pub const mtimecmp_lo = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0xd100000c - /// Timer comparison value (upper half) - pub const mtimecmp_hi = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0xd1000ff8 - /// Timer control register - pub const mstop = @intToPtr(*volatile Mmio(32, packed struct { - /// Pause (1) or run (0) the timer - TIMESTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xff8); - - /// address: 0xd1000ffc - /// Software interrupt register - pub const msip = @intToPtr(*volatile Mmio(32, packed struct { - /// Generate software interrupts - MSIP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0xffc); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/lpc1768/lpc1768.zig b/src/modules/chips/lpc1768/lpc1768.zig deleted file mode 100644 index 9239317..0000000 --- a/src/modules/chips/lpc1768/lpc1768.zig +++ /dev/null @@ -1,205 +0,0 @@ -const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("registers.zig"); -const regs = chip.registers; - -pub usingnamespace chip; - -pub const clock = struct { - pub const Domain = enum { - cpu, - }; -}; - -pub const clock_frequencies = .{ - .cpu = 100_000_000, // 100 Mhz -}; - -pub const PinTarget = enum(u2) { - func00 = 0b00, - func01 = 0b01, - func10 = 0b10, - func11 = 0b11, -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme."; - if (spec[0] != 'P') - @compileError(invalid_format_msg); - - const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg); - - const _port: comptime_int = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg); - const _pin: comptime_int = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg); - - const sel_reg_name = std.fmt.comptimePrint("PINSEL{d}", .{(2 * _port + _pin / 16)}); - - const _regs = struct { - const name_suffix = std.fmt.comptimePrint("{d}", .{_port}); - - const pinsel_reg = @field(regs.PINCONNECT, sel_reg_name); - const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin }); - - const dir = @field(regs.GPIO, "DIR" ++ name_suffix); - const pin = @field(regs.GPIO, "PIN" ++ name_suffix); - const set = @field(regs.GPIO, "SET" ++ name_suffix); - const clr = @field(regs.GPIO, "CLR" ++ name_suffix); - const mask = @field(regs.GPIO, "MASK" ++ name_suffix); - }; - - return struct { - pub const port: u3 = _port; - pub const pin: u5 = _pin; - pub const regs = _regs; - const gpio_mask: u32 = (1 << pin); - - pub const Targets = PinTarget; - }; -} - -pub fn routePin(comptime pin: type, function: PinTarget) void { - var val = pin.regs.pinsel_reg.read(); - @field(val, pin.regs.pinsel_field) = @enumToInt(function); - pin.regs.pinsel_reg.write(val); -} - -pub const gpio = struct { - pub fn setOutput(comptime pin: type) void { - pin.regs.dir.raw |= pin.gpio_mask; - } - pub fn setInput(comptime pin: type) void { - pin.regs.dir.raw &= ~pin.gpio_mask; - } - - pub fn read(comptime pin: type) micro.gpio.State { - return if ((pin.regs.pin.raw & pin.gpio_mask) != 0) - micro.gpio.State.high - else - micro.gpio.State.low; - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - if (state == .high) { - pin.regs.set.raw = pin.gpio_mask; - } else { - pin.regs.clr.raw = pin.gpio_mask; - } - } -}; - -pub const uart = struct { - pub const DataBits = enum(u2) { - five = 0, - six = 1, - seven = 2, - eight = 3, - }; - - pub const StopBits = enum(u1) { - one = 0, - two = 1, - }; - - pub const Parity = enum(u2) { - odd = 0, - even = 1, - mark = 2, - space = 3, - }; - - pub const CClkDiv = enum(u2) { - four = 0, - one = 1, - two = 2, - eight = 3, - }; -}; - -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (pins.tx != null or pins.rx != null) - @compileError("TODO: custom pins are not currently supported"); - - return struct { - const UARTn = switch (index) { - 0 => regs.UART0, - 1 => regs.UART1, - 2 => regs.UART2, - 3 => regs.UART3, - else => @compileError("LPC1768 has 4 UARTs available."), - }; - const Self = @This(); - - pub fn init(config: micro.uart.Config) !Self { - micro.debug.write("0"); - switch (index) { - 0 => { - regs.SYSCON.PCONP.modify(.{ .PCUART0 = 1 }); - regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) }); - }, - 1 => { - regs.SYSCON.PCONP.modify(.{ .PCUART1 = 1 }); - regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) }); - }, - 2 => { - regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 }); - regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) }); - }, - 3 => { - regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 }); - regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) }); - }, - else => unreachable, - } - micro.debug.write("1"); - - UARTn.LCR.modify(.{ - // 8N1 - .WLS = @enumToInt(config.data_bits), - .SBS = @enumToInt(config.stop_bits), - .PE = if (config.parity != null) @as(u1, 1) else @as(u1, 0), - .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd), - .BC = 0, - .DLAB = 1, - }); - micro.debug.write("2"); - - // TODO: UARTN_FIFOS_ARE_DISA is not available in all uarts - //UARTn.FCR.modify(.{ .FIFOEN = .UARTN_FIFOS_ARE_DISA }); - - micro.debug.writer().print("clock: {} baud: {} ", .{ - micro.clock.get().cpu, - config.baud_rate, - }) catch {}; - - const pclk = micro.clock.get().cpu / 4; - const divider = (pclk / (16 * config.baud_rate)); - - const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate; - - UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) }); - UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) }); - - UARTn.LCR.modify(.{ .DLAB = 0 }); - - return Self{}; - } - - pub fn canWrite(self: Self) bool { - _ = self; - return (UARTn.LSR.read().THRE == 1); - } - pub fn tx(self: Self, ch: u8) void { - while (!self.canWrite()) {} // Wait for Previous transmission - UARTn.THR.raw = ch; // Load the data to be transmitted - } - - pub fn canRead(self: Self) bool { - _ = self; - return (UARTn.LSR.read().RDR == 1); - } - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - return UARTn.RBR.read().RBR; // Read received data - } - }; -} diff --git a/src/modules/chips/lpc1768/registers.zig b/src/modules/chips/lpc1768/registers.zig deleted file mode 100644 index a30184d..0000000 --- a/src/modules/chips/lpc1768/registers.zig +++ /dev/null @@ -1,18811 +0,0 @@ -// this file is generated by regz -// -// device: LPC176x5x -// cpu: CM3 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - WDT: InterruptVector = unhandled, - TIMER0: InterruptVector = unhandled, - TIMER1: InterruptVector = unhandled, - TIMER2: InterruptVector = unhandled, - TIMER3: InterruptVector = unhandled, - UART0: InterruptVector = unhandled, - UART1: InterruptVector = unhandled, - UART2: InterruptVector = unhandled, - UART3: InterruptVector = unhandled, - PWM1: InterruptVector = unhandled, - I2C0: InterruptVector = unhandled, - I2C1: InterruptVector = unhandled, - I2C2: InterruptVector = unhandled, - SPI: InterruptVector = unhandled, - SSP0: InterruptVector = unhandled, - SSP1: InterruptVector = unhandled, - PLL0: InterruptVector = unhandled, - RTC: InterruptVector = unhandled, - EINT0: InterruptVector = unhandled, - EINT1: InterruptVector = unhandled, - EINT2: InterruptVector = unhandled, - EINT3: InterruptVector = unhandled, - ADC: InterruptVector = unhandled, - BOD: InterruptVector = unhandled, - USB: InterruptVector = unhandled, - CAN: InterruptVector = unhandled, - DMA: InterruptVector = unhandled, - I2S: InterruptVector = unhandled, - ENET: InterruptVector = unhandled, - RIT: InterruptVector = unhandled, - MCPWM: InterruptVector = unhandled, - QEI: InterruptVector = unhandled, - PLL1: InterruptVector = unhandled, - USBActivity: InterruptVector = unhandled, - CANActivity: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// Watchdog Timer (WDT) - pub const WDT = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// Watchdog mode register. This register determines the basic mode and status of - /// the Watchdog Timer. - pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog enable bit. This bit is Set Only. - WDEN: u1, - /// Watchdog reset enable bit. This bit is Set Only. See Table 652. - WDRESET: u1, - /// Watchdog time-out flag. Set when the watchdog timer times out, cleared by - /// software. - WDTOF: u1, - /// Watchdog interrupt flag. Cleared by software. - WDINT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x0); - - /// address: 0x40000004 - /// Watchdog timer constant register. The value in this register determines the - /// time-out value. - pub const TC = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog time-out interval. - Count: u32, - }), base_address + 0x4); - - /// address: 0x40000008 - /// Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register - /// reloads the Watchdog timer with the value contained in WDTC. - pub const FEED = @intToPtr(*volatile Mmio(32, packed struct { - /// Feed value should be 0xAA followed by 0x55. - Feed: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// Watchdog timer value register. This register reads out the current value of the - /// Watchdog timer. - pub const TV = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter timer value. - Count: u32, - }), base_address + 0xc); - - /// address: 0x40000010 - /// Watchdog clock select register. - pub const CLKSEL = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects source of WDT clock - CLKSEL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - reserved28: u1, - /// If this bit is set to one writing to this register does not affect bit 0. The - /// clock source can only be changed by first clearing this bit, then writing the - /// new value of bit 0. - LOCK: u1, - }), base_address + 0x10); - }; - /// Timer0/1/2/3 - pub const TIMER0 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// Interrupt Register. The IR can be written to clear interrupts. The IR can be - /// read to identify which of eight possible interrupt sources are pending. - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag for match channel 0. - MR0INT: u1, - /// Interrupt flag for match channel 1. - MR1INT: u1, - /// Interrupt flag for match channel 2. - MR2INT: u1, - /// Interrupt flag for match channel 3. - MR3INT: u1, - /// Interrupt flag for capture channel 0 event. - CR0INT: u1, - /// Interrupt flag for capture channel 1 event. - CR1INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x0); - - /// address: 0x40004004 - /// Timer Control Register. The TCR is used to control the Timer Counter functions. - /// The Timer Counter can be disabled or reset through the TCR. - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - /// When one, the Timer Counter and Prescale Counter are enabled for counting. When - /// zero, the counters are disabled. - CEN: u1, - /// When one, the Timer Counter and the Prescale Counter are synchronously reset on - /// the next positive edge of PCLK. The counters remain reset until TCR[1] is - /// returned to zero. - CRST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x4); - - /// address: 0x40004008 - /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is - /// controlled through the TCR. - pub const TC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000400c - /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the - /// next clock increments the TC and clears the PC. - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescale counter maximum value. - PM: u32, - }), base_address + 0xc); - - /// address: 0x40004010 - /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value - /// stored in PR. When the value in PR is reached, the TC is incremented and the PC - /// is cleared. The PC is observable and controllable through the bus interface. - pub const PC = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40004014 - /// Match Control Register. The MCR is used to control if an interrupt is generated - /// and if the TC is reset when a Match occurs. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt on MR0 - MR0I: u1, - /// Reset on MR0 - MR0R: u1, - /// Stop on MR0 - MR0S: u1, - /// Interrupt on MR1 - MR1I: u1, - /// Reset on MR1 - MR1R: u1, - /// Stop on MR1 - MR1S: u1, - /// Interrupt on MR2 - MR2I: u1, - /// Reset on MR2 - MR2R: u1, - /// Stop on MR2. - MR2S: u1, - /// Interrupt on MR3 - MR3I: u1, - /// Reset on MR3 - MR3R: u1, - /// Stop on MR3 - MR3S: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x14); - - /// address: 0x40004018 - /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both - /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x18); - - /// address: 0x40004028 - /// Capture Control Register. The CCR controls which edges of the capture inputs are - /// used to load the Capture Registers and whether or not an interrupt is generated - /// when a capture takes place. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture on CAPn.0 rising edge - CAP0RE: u1, - /// Capture on CAPn.0 falling edge - CAP0FE: u1, - /// Interrupt on CAPn.0 event - CAP0I: u1, - /// Capture on CAPn.1 rising edge - CAP1RE: u1, - /// Capture on CAPn.1 falling edge - CAP1FE: u1, - /// Interrupt on CAPn.1 event - CAP1I: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x4000402c - /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on - /// the CAPn.0 input. - pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Timer counter capture value. - CAP: u32, - }), base_address + 0x2c); - - /// address: 0x4000403c - /// External Match Register. The EMR controls the external match pins. - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Match 0. When a match occurs between the TC and MR0, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM0: u1, - /// External Match 1. When a match occurs between the TC and MR1, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this - /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM1: u1, - /// External Match 2. When a match occurs between the TC and MR2, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM2: u1, - /// External Match 3. When a match occurs between the TC and MR3, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM3: u1, - /// External Match Control 0. Determines the functionality of External Match 0. - EMC0: u2, - /// External Match Control 1. Determines the functionality of External Match 1. - EMC1: u2, - /// External Match Control 2. Determines the functionality of External Match 2. - EMC2: u2, - /// External Match Control 3. Determines the functionality of External Match 3. - EMC3: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x3c); - - /// address: 0x40004070 - /// Count Control Register. The CTCR selects between Timer and Counter mode, and in - /// Counter mode selects the signal and edge(s) for counting. - pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter/Timer Mode This field selects which rising PCLK edges can increment - /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). - /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale - /// Register. - CTMODE: u2, - /// Count Input Select When bits 1:0 in this register are not 00, these bits select - /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a - /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture - /// Control Register (TnCCR) must be programmed as 000. However, capture and/or - /// interrupt can be selected for the other 3 CAPn inputs in the same timer. - CINSEL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x70); - }; - pub const TIMER1 = struct { - pub const base_address = 0x40008000; - - /// address: 0x40008000 - /// Interrupt Register. The IR can be written to clear interrupts. The IR can be - /// read to identify which of eight possible interrupt sources are pending. - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag for match channel 0. - MR0INT: u1, - /// Interrupt flag for match channel 1. - MR1INT: u1, - /// Interrupt flag for match channel 2. - MR2INT: u1, - /// Interrupt flag for match channel 3. - MR3INT: u1, - /// Interrupt flag for capture channel 0 event. - CR0INT: u1, - /// Interrupt flag for capture channel 1 event. - CR1INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x0); - - /// address: 0x40008004 - /// Timer Control Register. The TCR is used to control the Timer Counter functions. - /// The Timer Counter can be disabled or reset through the TCR. - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - /// When one, the Timer Counter and Prescale Counter are enabled for counting. When - /// zero, the counters are disabled. - CEN: u1, - /// When one, the Timer Counter and the Prescale Counter are synchronously reset on - /// the next positive edge of PCLK. The counters remain reset until TCR[1] is - /// returned to zero. - CRST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x4); - - /// address: 0x40008008 - /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is - /// controlled through the TCR. - pub const TC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000800c - /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the - /// next clock increments the TC and clears the PC. - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescale counter maximum value. - PM: u32, - }), base_address + 0xc); - - /// address: 0x40008010 - /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value - /// stored in PR. When the value in PR is reached, the TC is incremented and the PC - /// is cleared. The PC is observable and controllable through the bus interface. - pub const PC = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40008014 - /// Match Control Register. The MCR is used to control if an interrupt is generated - /// and if the TC is reset when a Match occurs. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt on MR0 - MR0I: u1, - /// Reset on MR0 - MR0R: u1, - /// Stop on MR0 - MR0S: u1, - /// Interrupt on MR1 - MR1I: u1, - /// Reset on MR1 - MR1R: u1, - /// Stop on MR1 - MR1S: u1, - /// Interrupt on MR2 - MR2I: u1, - /// Reset on MR2 - MR2R: u1, - /// Stop on MR2. - MR2S: u1, - /// Interrupt on MR3 - MR3I: u1, - /// Reset on MR3 - MR3R: u1, - /// Stop on MR3 - MR3S: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x14); - - /// address: 0x40008018 - /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both - /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x18); - - /// address: 0x40008028 - /// Capture Control Register. The CCR controls which edges of the capture inputs are - /// used to load the Capture Registers and whether or not an interrupt is generated - /// when a capture takes place. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture on CAPn.0 rising edge - CAP0RE: u1, - /// Capture on CAPn.0 falling edge - CAP0FE: u1, - /// Interrupt on CAPn.0 event - CAP0I: u1, - /// Capture on CAPn.1 rising edge - CAP1RE: u1, - /// Capture on CAPn.1 falling edge - CAP1FE: u1, - /// Interrupt on CAPn.1 event - CAP1I: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x4000802c - /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on - /// the CAPn.0 input. - pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Timer counter capture value. - CAP: u32, - }), base_address + 0x2c); - - /// address: 0x4000803c - /// External Match Register. The EMR controls the external match pins. - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Match 0. When a match occurs between the TC and MR0, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM0: u1, - /// External Match 1. When a match occurs between the TC and MR1, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this - /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM1: u1, - /// External Match 2. When a match occurs between the TC and MR2, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM2: u1, - /// External Match 3. When a match occurs between the TC and MR3, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM3: u1, - /// External Match Control 0. Determines the functionality of External Match 0. - EMC0: u2, - /// External Match Control 1. Determines the functionality of External Match 1. - EMC1: u2, - /// External Match Control 2. Determines the functionality of External Match 2. - EMC2: u2, - /// External Match Control 3. Determines the functionality of External Match 3. - EMC3: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x3c); - - /// address: 0x40008070 - /// Count Control Register. The CTCR selects between Timer and Counter mode, and in - /// Counter mode selects the signal and edge(s) for counting. - pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter/Timer Mode This field selects which rising PCLK edges can increment - /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). - /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale - /// Register. - CTMODE: u2, - /// Count Input Select When bits 1:0 in this register are not 00, these bits select - /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a - /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture - /// Control Register (TnCCR) must be programmed as 000. However, capture and/or - /// interrupt can be selected for the other 3 CAPn inputs in the same timer. - CINSEL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x70); - }; - /// UART0/2/3 - pub const UART0 = struct { - pub const base_address = 0x4000c000; - - /// address: 0x4000c000 - /// Receiver Buffer Register. Contains the next received character to be read (DLAB - /// =0). - pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Receiver Buffer Register contains the oldest received byte in the - /// UARTn Rx FIFO. - RBR: u8, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x4000c000 - /// Transmit Holding Regiter. The next character to be transmitted is written here - /// (DLAB =0). - pub const THR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing to the UARTn Transmit Holding Register causes the data to be stored in - /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the - /// FIFO and the transmitter is available. - THR: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x0); - - /// address: 0x4000c000 - /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines - /// the baud rate of the UARTn. - DLLSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x0); - - /// address: 0x4000c004 - /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines - /// the baud rate of the UARTn. - DLMSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x4); - - /// address: 0x4000c004 - /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 - /// potential UART interrupts (DLAB =0). - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It - /// also controls the Character Receive Time-out interrupt. - RBRIE: u1, - /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this - /// can be read from UnLSR[5]. - THREIE: u1, - /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. - /// The status of this interrupt can be read from UnLSR[4:1]. - RXIE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// Enables the end of auto-baud interrupt. - ABEOINTEN: u1, - /// Enables the auto-baud time-out interrupt. - ABTOINTEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x4); - - /// address: 0x4000c008 - /// Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be - /// determined by evaluating UnIIR[3:1]. - INTSTATUS: u1, - /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to - /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below - /// are reserved (000,100,101,111). - INTID: u3, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// Copies of UnFCR[0]. - FIFOENABLE: u2, - /// End of auto-baud interrupt. True if auto-baud has finished successfully and - /// interrupt is enabled. - ABEOINT: u1, - /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is - /// enabled. - ABTOINT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x8); - - /// address: 0x4000c008 - /// FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO Enable. - FIFOEN: u1, - /// RX FIFO Reset. - RXFIFORES: u1, - /// TX FIFO Reset. - TXFIFORES: u1, - /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit - /// selects the DMA mode. See Section 18.6.6.1. - DMAMODE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO - /// characters must be written before an interrupt or DMA request is activated. - RXTRIGLVL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x8); - - /// address: 0x4000c00c - /// Line Control Register. Contains controls for frame formatting and break - /// generation. - pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Word Length Select. - WLS: u2, - /// Stop Bit Select - SBS: u1, - /// Parity Enable. - PE: u1, - /// Parity Select - PS: u2, - /// Break Control - BC: u1, - /// Divisor Latch Access Bit - DLAB: u1, - /// Reserved. Read value is undefined, only zero should be written. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x4000c014 - /// Line Status Register. Contains flags for transmit and receive status, including - /// line errors. - pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character - /// and is cleared when the UARTn RBR FIFO is empty. - RDR: u1, - /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR - /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character - /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will - /// not be overwritten and the character in the UARTn RSR will be lost. - OE: u1, - /// Parity Error. When the parity bit of a received character is in the wrong state, - /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error - /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the - /// character at the top of the UARTn RBR FIFO. - PE: u1, - /// Framing Error. When the stop bit of a received character is a logic 0, a framing - /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error - /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx - /// will attempt to resynchronize to the data and assume that the bad stop bit is - /// actually an early start bit. However, it cannot be assumed that the next - /// received byte will be correct even if there is no Framing Error. Note: A framing - /// error is associated with the character at the top of the UARTn RBR FIFO. - FE: u1, - /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one - /// full character transmission (start, data, parity, stop), a break interrupt - /// occurs. Once the break condition has been detected, the receiver goes idle until - /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The - /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is - /// associated with the character at the top of the UARTn RBR FIFO. - BI: u1, - /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an - /// empty UARTn THR and is cleared on a UnTHR write. - THRE: u1, - /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is - /// cleared when either the UnTSR or the UnTHR contain valid data. - TEMT: u1, - /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as - /// framing error, parity error or break interrupt, is loaded into the UnRBR. This - /// bit is cleared when the UnLSR register is read and there are no subsequent - /// errors in the UARTn FIFO. - RXFE: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x14); - - /// address: 0x4000c01c - /// Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - /// A readable, writable byte. - PAD: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x1c); - - /// address: 0x4000c020 - /// Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit. This bit is automatically cleared after auto-baud completion. - START: u1, - /// Auto-baud mode select bit. - MODE: u1, - /// Restart bit. - AUTORESTART: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABEOINTCLR: u1, - /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x20); - - /// address: 0x4000c028 - /// Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional - /// baud-rate generator will not impact the UARTn baudrate. - DIVADDVAL: u4, - /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for - /// UARTn to operate properly, regardless of whether the fractional baud-rate - /// generator is used or not. - MULVAL: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x28); - - /// address: 0x4000c030 - /// Transmit Enable Register. Turns off UART transmitter for use with software flow - /// control. - pub const TER = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u7, - /// When this bit is 1, as it is after a Reset, data written to the THR is output on - /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared - /// to 0 while a character is being sent, the transmission of that character is - /// completed, but no further characters are sent until this bit is set again. In - /// other words, a 0 in this bit blocks the transfer of characters from the THR or - /// TX FIFO into the transmit shift register. Software implementing - /// software-handshaking can clear this bit when it receives an XOFF character - /// (DC3). Software can set this bit again when it receives an XON (DC1) character. - TXEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x30); - - /// address: 0x4000c04c - /// RS-485/EIA-485 Control. Contains controls to configure various aspects of - /// RS-485/EIA-485 modes. - pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// NMM enable. - NMMEN: u1, - /// Receiver enable. - RXDIS: u1, - /// AAD enable. - AADEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Direction control enable. - DCTRL: u1, - /// Direction control pin polarity. This bit reverses the polarity of the direction - /// control signal on the Un_OE pin. - OINV: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x4c); - - /// address: 0x4000c050 - /// RS-485/EIA-485 address match. Contains the address match value for - /// RS-485/EIA-485 mode. - pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the address match value. - ADRMATCH: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x50); - - /// address: 0x4000c054 - /// RS-485/EIA-485 direction control delay. - pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the direction control (UnOE) delay value. This register works in - /// conjunction with an 8-bit counter. - DLY: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED0: u8, - RESERVED1: u16, - }), base_address + 0x54); - }; - /// UART1 - pub const UART1 = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// DLAB =0 Receiver Buffer Register. Contains the next received character to be - /// read. - pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { - /// The UART1 Receiver Buffer Register contains the oldest received byte in the - /// UART1 RX FIFO. - RBR: u8, - /// Reserved, the value read from a reserved bit is not defined. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40010000 - /// DLAB =0. Transmit Holding Register. The next character to be transmitted is - /// written here. - pub const THR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing to the UART1 Transmit Holding Register causes the data to be stored in - /// the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the - /// FIFO and the transmitter is available. - THR: u8, - /// Reserved. Read value is undefined, only zero should be written. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40010000 - /// DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor - /// value. The full divisor is used to generate a baud rate from the fractional rate - /// divider. - pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { - /// The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines - /// the baud rate of the UART1. - DLLSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40010004 - /// DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor - /// value. The full divisor is used to generate a baud rate from the fractional rate - /// divider. - pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { - /// The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines - /// the baud rate of the UART1. - DLMSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40010004 - /// DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits - /// for the 7 potential UART1 interrupts. - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It - /// also controls the Character Receive Time-out interrupt. - RBRIE: u1, - /// THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this - /// interrupt can be read from LSR[5]. - THREIE: u1, - /// RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The - /// status of this interrupt can be read from LSR[4:1]. - RXIE: u1, - /// Modem Status Interrupt Enable. Enables the modem interrupt. The status of this - /// interrupt can be read from MSR[3:0]. - MSIE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u3, - /// CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the - /// modem status interrupt generation on a CTS1 signal transition. If auto-cts mode - /// is disabled a CTS1 transition will generate an interrupt if Modem Status - /// Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition - /// will generate a Modem Status Interrupt unless the interrupt has been disabled by - /// clearing the IER[3] bit in the IER register. In auto-cts mode a transition on - /// the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits - /// are set. - CTSIE: u1, - /// Enables the end of auto-baud interrupt. - ABEOIE: u1, - /// Enables the auto-baud time-out interrupt. - ABTOIE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x4); - - /// address: 0x40010008 - /// Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt status. Note that IIR[0] is active low. The pending interrupt can be - /// determined by evaluating IIR[3:1]. - INTSTATUS: u1, - /// Interrupt identification. IER[3:1] identifies an interrupt corresponding to the - /// UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are - /// reserved (100,101,111). - INTID: u3, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Copies of FCR[0]. - FIFOENABLE: u2, - /// End of auto-baud interrupt. True if auto-baud has finished successfully and - /// interrupt is enabled. - ABEOINT: u1, - /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is - /// enabled. - ABTOINT: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x8); - - /// address: 0x40010008 - /// FIFO Control Register. Controls UART1 FIFO usage and modes. - pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO enable. - FIFOEN: u1, - /// RX FIFO Reset. - RXFIFORES: u1, - /// TX FIFO Reset. - TXFIFORES: u1, - /// DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this - /// bit selects the DMA mode. See Section 36.6.6.1. - DMAMODE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// RX Trigger Level. These two bits determine how many receiver UART1 FIFO - /// characters must be written before an interrupt is activated. - RXTRIGLVL: u2, - /// Reserved, user software should not write ones to reserved bits. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x4001000c - /// Line Control Register. Contains controls for frame formatting and break - /// generation. - pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Word Length Select. - WLS: u2, - /// Stop Bit Select. - SBS: u1, - /// Parity Enable. - PE: u1, - /// Parity Select. - PS: u2, - /// Break Control. - BC: u1, - /// Divisor Latch Access Bit (DLAB) - DLAB: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// Modem Control Register. Contains controls for flow control handshaking and - /// loopback mode. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem - /// loopback mode is active. - DTRCTRL: u1, - /// RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem - /// loopback mode is active. - RTSCTRL: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Loopback Mode Select. The modem loopback mode provides a mechanism to perform - /// diagnostic loopback testing. Serial data from the transmitter is connected - /// internally to serial input of the receiver. Input pin, RXD1, has no effect on - /// loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, - /// DSR, RI and DCD) are disconnected externally. Externally, the modem outputs - /// (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to - /// the 4 modem inputs. As a result of these connections, the upper 4 bits of the - /// MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs - /// in normal mode. This permits modem status interrupts to be generated in loopback - /// mode by writing the lower 4 bits of MCR. - LMS: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// RTS enable. - RTSEN: u1, - /// CTS enable. - CTSEN: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x10); - - /// address: 0x40010014 - /// Line Status Register. Contains flags for transmit and receive status, including - /// line errors. - pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is - /// cleared when the UART1 RBR FIFO is empty. - RDR: u1, - /// Overrun Error. The overrun error condition is set as soon as it occurs. An LSR - /// read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled - /// and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be - /// overwritten and the character in the UART1 RSR will be lost. - OE: u1, - /// Parity Error. When the parity bit of a received character is in the wrong state, - /// a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection - /// is dependent on FCR[0]. Note: A parity error is associated with the character at - /// the top of the UART1 RBR FIFO. - PE: u1, - /// Framing Error. When the stop bit of a received character is a logic 0, a framing - /// error occurs. An LSR read clears LSR[3]. The time of the framing error detection - /// is dependent on FCR0. Upon detection of a framing error, the RX will attempt to - /// resynchronize to the data and assume that the bad stop bit is actually an early - /// start bit. However, it cannot be assumed that the next received byte will be - /// correct even if there is no Framing Error. Note: A framing error is associated - /// with the character at the top of the UART1 RBR FIFO. - FE: u1, - /// Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one - /// full character transmission (start, data, parity, stop), a break interrupt - /// occurs. Once the break condition has been detected, the receiver goes idle until - /// RXD1 goes to marking state (all ones). An LSR read clears this status bit. The - /// time of break detection is dependent on FCR[0]. Note: The break interrupt is - /// associated with the character at the top of the UART1 RBR FIFO. - BI: u1, - /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an - /// empty UART1 THR and is cleared on a THR write. - THRE: u1, - /// Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared - /// when either the TSR or the THR contain valid data. - TEMT: u1, - /// Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing - /// error, parity error or break interrupt, is loaded into the RBR. This bit is - /// cleared when the LSR register is read and there are no subsequent errors in the - /// UART1 FIFO. - RXFE: u1, - /// Reserved, the value read from a reserved bit is not defined. - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40010018 - /// Modem Status Register. Contains handshake signal status flags. - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. - DCTS: u1, - /// Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. - DDSR: u1, - /// Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR - /// read. - TERI: u1, - /// Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. - DDCD: u1, - /// Clear To Send State. Complement of input signal CTS. This bit is connected to - /// MCR[1] in modem loopback mode. - CTS: u1, - /// Data Set Ready State. Complement of input signal DSR. This bit is connected to - /// MCR[0] in modem loopback mode. - DSR: u1, - /// Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in - /// modem loopback mode. - RI: u1, - /// Data Carrier Detect State. Complement of input DCD. This bit is connected to - /// MCR[3] in modem loopback mode. - DCD: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x4001001c - /// Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - /// A readable, writable byte. - Pad: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x1c); - - /// address: 0x40010020 - /// Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto-baud start bit. This bit is automatically cleared after auto-baud - /// completion. - START: u1, - /// Auto-baud mode select bit. - MODE: u1, - /// Auto-baud restart bit. - AUTORESTART: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u5, - /// End of auto-baud interrupt clear bit (write-only). - ABEOINTCLR: u1, - /// Auto-baud time-out interrupt clear bit (write-only). - ABTOINTCLR: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x20); - - /// address: 0x40010028 - /// Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud rate generation pre-scaler divisor value. If this field is 0, fractional - /// baud rate generator will not impact the UART1 baud rate. - DIVADDVAL: u4, - /// Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for - /// UART1 to operate properly, regardless of whether the fractional baud rate - /// generator is used or not. - MULVAL: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x40010030 - /// Transmit Enable Register. Turns off UART transmitter for use with software flow - /// control. - pub const TER = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u7, - /// When this bit is 1, as it is after a Reset, data written to the THR is output on - /// the TXD pin as soon as any preceding data has been sent. If this bit cleared to - /// 0 while a character is being sent, the transmission of that character is - /// completed, but no further characters are sent until this bit is set again. In - /// other words, a 0 in this bit blocks the transfer of characters from the THR or - /// TX FIFO into the transmit shift register. Software can clear this bit when it - /// detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, - /// or with software handshaking, when it receives an XOFF character (DC3). Software - /// can set this bit again when it detects that the TX-permit signal has gone true, - /// or when it receives an XON (DC1) character. - TXEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x30); - - /// address: 0x4001004c - /// RS-485/EIA-485 Control. Contains controls to configure various aspects of - /// RS-485/EIA-485 modes. - pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. - NMMEN: u1, - /// Receive enable. - RXDIS: u1, - /// Auto Address Detect (AAD) enable. - AADEN: u1, - /// Direction control. - SEL: u1, - /// Direction control enable. - DCTRL: u1, - /// Polarity. This bit reverses the polarity of the direction control signal on the - /// RTS (or DTR) pin. - OINV: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x4c); - - /// address: 0x40010050 - /// RS-485/EIA-485 address match. Contains the address match value for - /// RS-485/EIA-485 mode. - pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the address match value. - ADRMATCH: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x50); - - /// address: 0x40010054 - /// RS-485/EIA-485 direction control delay. - pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the direction control (RTS or DTR) delay value. This register works in - /// conjunction with an 8-bit counter. - DLY: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x54); - }; - /// Pulse Width Modulators (PWM1) - pub const PWM1 = struct { - pub const base_address = 0x40018000; - - /// address: 0x40018000 - /// Interrupt Register. The IR can be written to clear interrupts, or read to - /// identify which PWM interrupt sources are pending. - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag for PWM match channel 0. - PWMMR0INT: u1, - /// Interrupt flag for PWM match channel 1. - PWMMR1INT: u1, - /// Interrupt flag for PWM match channel 2. - PWMMR2INT: u1, - /// Interrupt flag for PWM match channel 3. - PWMMR3INT: u1, - /// Interrupt flag for capture input 0 - PWMCAP0INT: u1, - /// Interrupt flag for capture input 1 (available in PWM1IR only; this bit is - /// reserved in PWM0IR). - PWMCAP1INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// Interrupt flag for PWM match channel 4. - PWMMR4INT: u1, - /// Interrupt flag for PWM match channel 5. - PWMMR5INT: u1, - /// Interrupt flag for PWM match channel 6. - PWMMR6INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x0); - - /// address: 0x40018004 - /// Timer Control Register. The TCR is used to control the Timer Counter functions. - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter Enable - CE: u1, - /// Counter Reset - CR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// PWM Enable - PWMEN: u1, - /// Master Disable (PWM0 only). The two PWMs may be synchronized using the Master - /// Disable control bit. The Master disable bit of the Master PWM (PWM0 module) - /// controls a secondary enable input to both PWMs, as shown in Figure 141. This bit - /// has no function in the Slave PWM (PWM1). - MDIS: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0x4); - - /// address: 0x40018008 - /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is - /// controlled through the TCR. - pub const TC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4001800c - /// Prescale Register. Determines how often the PWM counter is incremented. - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescale counter maximum value. - PM: u32, - }), base_address + 0xc); - - /// address: 0x40018010 - /// Prescale Counter. Prescaler for the main PWM counter. - pub const PC = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40018014 - /// Match Control Register. The MCR is used to control whether an interrupt is - /// generated and if the PWM counter is reset when a Match occurs. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt PWM0 - PWMMR0I: u1, - /// Reset PWM0 - PWMMR0R: u1, - /// Stop PWM0 - PWMMR0S: u1, - /// Interrupt PWM1 - PWMMR1I: u1, - /// Reset PWM1 - PWMMR1R: u1, - /// Stop PWM1 - PWMMR1S: u1, - /// Interrupt PWM0 - PWMMR2I: u1, - /// Reset PWM0 - PWMMR2R: u1, - /// Stop PWM0 - PWMMR2S: u1, - /// Interrupt PWM3 - PWMMR3I: u1, - /// Reset PWM3 - PWMMR3R: u1, - /// Stop PWM0 - PWMMR3S: u1, - /// Interrupt PWM4 - PWMMR4I: u1, - /// Reset PWM4 - PWMMR4R: u1, - /// Stop PWM4 - PWMMR4S: u1, - /// Interrupt PWM5 - PWMMR5I: u1, - /// Reset PWM5 - PWMMR5R: u1, - /// Stop PWM5 - PWMMR5S: u1, - /// Interrupt PWM6 - PWMMR6I: u1, - /// Reset PWM6 - PWMMR6R: u1, - /// Stop PWM6 - PWMMR6S: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u11, - }), base_address + 0x14); - - /// address: 0x40018018 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x18); - - /// address: 0x4001801c - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x1c); - - /// address: 0x40018020 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x20); - - /// address: 0x40018024 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x24); - - /// address: 0x40018028 - /// Capture Control Register. The CCR controls which edges of the capture inputs are - /// used to load the Capture Registers and whether or not an interrupt is generated - /// for a capture event. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture on PWMn_CAP0 rising edge - CAP0_R: u1, - /// Capture on PWMn_CAP0 falling edge - CAP0_F: u1, - /// Interrupt on PWMn_CAP0 event - CAP0_I: u1, - /// Capture on PWMn_CAP1 rising edge. Reserved for PWM0. - CAP1_R: u1, - /// Capture on PWMn_CAP1 falling edge. Reserved for PWM0. - CAP1_F: u1, - /// Interrupt on PWMn_CAP1 event. Reserved for PWM0. - CAP1_I: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x4001802c - /// PWM Control Register. Enables PWM outputs and selects either single edge or - /// double edge controlled PWM outputs. - pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Reserved. - RESERVED: u2, - /// PWM[2] output single/double edge mode control. - PWMSEL2: u1, - /// PWM[3] output edge control. - PWMSEL3: u1, - /// PWM[4] output edge control. - PWMSEL4: u1, - /// PWM[5] output edge control. - PWMSEL5: u1, - /// PWM[6] output edge control. - PWMSEL6: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// PWM[1] output enable control. - PWMENA1: u1, - /// PWM[2] output enable control. - PWMENA2: u1, - /// PWM[3] output enable control. - PWMENA3: u1, - /// PWM[4] output enable control. - PWMENA4: u1, - /// PWM[5] output enable control. - PWMENA5: u1, - /// PWM[6] output enable control. See PWMENA1 for details. - PWMENA6: u1, - /// Unused, always zero. - RESERVED: u17, - }), base_address + 0x2c); - - /// address: 0x40018040 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x40); - - /// address: 0x40018044 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x44); - - /// address: 0x40018048 - /// Match Register. Match registers - /// are continuously compared to the PWM counter in order to control PWM - /// output edges. - pub const MR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x48); - - /// address: 0x4001804c - /// PWM Control Register. Enables PWM outputs and selects either single edge or - /// double edge controlled PWM outputs. - pub const PCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u2, - /// PWM[2] output single/double edge mode control. - PWMSEL2: u1, - /// PWM[3] output edge control. - PWMSEL3: u1, - /// PWM[4] output edge control. - PWMSEL4: u1, - /// PWM[5] output edge control. - PWMSEL5: u1, - /// PWM[6] output edge control. - PWMSEL6: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// PWM[1] output enable control. - PWMENA1: u1, - /// PWM[2] output enable control. - PWMENA2: u1, - /// PWM[3] output enable control. - PWMENA3: u1, - /// PWM[4] output enable control. - PWMENA4: u1, - /// PWM[5] output enable control. - PWMENA5: u1, - /// PWM[6] output enable control. See PWMENA1 for details. - PWMENA6: u1, - /// Unused, always zero. - RESERVED: u17, - }), base_address + 0x4c); - - /// address: 0x40018050 - /// Load Enable Register. Enables use of updated PWM match values. - pub const LER = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this - /// bit allows the last value written to the PWM Match Register 0 to be become - /// effective when the timer is next reset by a PWM Match event. See Section 27.6.7. - MAT0LATCHEN: u1, - /// Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for - /// details. - MAT1LATCHEN: u1, - /// Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for - /// details. - MAT2LATCHEN: u1, - /// Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for - /// details. - MAT3LATCHEN: u1, - /// Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for - /// details. - MAT4LATCHEN: u1, - /// Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for - /// details. - MAT5LATCHEN: u1, - /// Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for - /// details. - MAT6LATCHEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u25, - }), base_address + 0x50); - - /// address: 0x40018070 - /// Count Control Register. The CTCR selects between Timer and Counter mode, and in - /// Counter mode selects the signal and edge(s) for counting. - pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter/ Timer Mode - MOD: u2, - /// Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP - /// pin carries the signal used to increment the TC. Other combinations are - /// reserved. - CIS: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x70); - }; - /// I2C bus interface - pub const I2C0 = struct { - pub const base_address = 0x4001c000; - - /// address: 0x4001c000 - /// I2C Control Set Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is set. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge flag. - AA: u1, - /// I2C interrupt flag. - SI: u1, - /// STOP flag. - STO: u1, - /// START flag. - STA: u1, - /// I2C interface enable. - I2EN: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u25, - }), base_address + 0x0); - - /// address: 0x4001c004 - /// I2C Status Register. During I2C operation, this register provides detailed - /// status codes that allow software to determine the next action needed. - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// These bits are unused and are always 0. - RESERVED: u3, - /// These bits give the actual status information about the I 2C interface. - Status: u5, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x4001c008 - /// I2C Data Register. During master or slave transmit mode, data to be transmitted - /// is written to this register. During master or slave receive mode, data that has - /// been received may be read from this register. - pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds data values that have been received or are to be - /// transmitted. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x4001c00c - /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x4001c010 - /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C - /// clock. - pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL HIGH time period selection. - SCLH: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x10); - - /// address: 0x4001c014 - /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. - /// SCLL and SCLH together determine the clock frequency generated by an I2C master - /// and certain times used in slave mode. - pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL low time period selection. - SCLL: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x14); - - /// address: 0x4001c018 - /// I2C Control Clear Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is cleared. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge Clear bit. - AAC: u1, - /// I2C interrupt Clear bit. - SIC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// START flag Clear bit. - STAC: u1, - /// I2C interface Disable bit. - I2ENC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x4001c01c - /// Monitor mode control register. - pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Monitor mode enable. - MM_ENA: u1, - /// SCL output enable. - ENA_SCL: u1, - /// Select interrupt register match. - MATCH_ALL: u1, - /// Reserved. The value read from reserved bits is not defined. - RESERVED: u29, - }), base_address + 0x1c); - - /// address: 0x4001c020 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x20); - - /// address: 0x4001c024 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x24); - - /// address: 0x4001c028 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x4001c02c - /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will - /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of - /// data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds contents of the 8 MSBs of the DAT shift register. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x2c); - - /// address: 0x4001c030 - /// I2C Slave address mask register - pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. This bit reads - /// always back as 0. - RESERVED: u1, - /// Mask bits. - MASK: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x30); - }; - /// SPI - pub const SPI = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// SPI Control Register. This register controls the operation of the SPI. - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// The SPI controller sends and receives 8 bits of data per transfer. - BITENABLE: u1, - /// Clock phase control determines the relationship between the data and the clock - /// on SPI transfers, and controls when a slave transfer is defined as starting and - /// ending. - CPHA: u1, - /// Clock polarity control. - CPOL: u1, - /// Master mode select. - MSTR: u1, - /// LSB First controls which direction each byte is shifted when transferred. - LSBF: u1, - /// Serial peripheral interrupt enable. - SPIE: u1, - /// When bit 2 of this register is 1, this field controls the number of bits per - /// transfer: - BITS: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x0); - - /// address: 0x40020004 - /// SPI Status Register. This register shows the status of the SPI. - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u3, - /// Slave abort. When 1, this bit indicates that a slave abort has occurred. This - /// bit is cleared by reading this register. - ABRT: u1, - /// Mode fault. when 1, this bit indicates that a Mode fault error has occurred. - /// This bit is cleared by reading this register, then writing the SPI0 control - /// register. - MODF: u1, - /// Read overrun. When 1, this bit indicates that a read overrun has occurred. This - /// bit is cleared by reading this register. - ROVR: u1, - /// Write collision. When 1, this bit indicates that a write collision has occurred. - /// This bit is cleared by reading this register, then accessing the SPI Data - /// Register. - WCOL: u1, - /// SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer - /// is complete. When a master, this bit is set at the end of the last cycle of the - /// transfer. When a slave, this bit is set on the last data sampling edge of the - /// SCK. This bit is cleared by first reading this register, then accessing the SPI - /// Data Register. Note: this is not the SPI interrupt flag. This flag is found in - /// the SPINT register. - SPIF: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x40020008 - /// SPI Data Register. This bi-directional register provides the transmit and - /// receive data for the SPI. Transmit data is provided to the SPI0 by writing to - /// this register. Data received by the SPI0 can be read from this register. - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// SPI Bi-directional data port. - DATALOW: u8, - /// If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of - /// these bits contain the additional transmit and receive bits. When less than 16 - /// bits are selected, the more significant among these bits read as zeroes. - DATAHIGH: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x8); - - /// address: 0x4002000c - /// SPI Clock Counter Register. This register controls the frequency of a master's - /// SCK0. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// SPI0 Clock counter setting. - COUNTER: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x4002001c - /// SPI Interrupt Flag. This register contains the interrupt flag for the SPI - /// interface. - pub const INT = @intToPtr(*volatile Mmio(32, packed struct { - /// SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared - /// by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at - /// least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit - /// is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be - /// processed by interrupt handling software. - SPIF: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u7, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x1c); - }; - /// Real Time Clock (RTC) - pub const RTC = struct { - pub const base_address = 0x40024000; - - /// address: 0x40024000 - /// Interrupt Location Register - pub const ILR = @intToPtr(*volatile Mmio(32, packed struct { - /// When one, the Counter Increment Interrupt block generated an interrupt. Writing - /// a one to this bit location clears the counter increment interrupt. - RTCCIF: u1, - /// When one, the alarm registers generated an interrupt. Writing a one to this bit - /// location clears the alarm interrupt. - RTCALF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u11, - }), base_address + 0x0); - - /// address: 0x40024008 - /// Clock Control Register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock Enable. - CLKEN: u1, - /// CTC Reset. - CTCRST: u1, - /// Internal test mode controls. These bits must be 0 for normal RTC operation. - RESERVED: u2, - /// Calibration counter enable. - CCALEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0x8); - - /// address: 0x4002400c - /// Counter Increment Interrupt Register - pub const CIIR = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, an increment of the Second value generates an interrupt. - IMSEC: u1, - /// When 1, an increment of the Minute value generates an interrupt. - IMMIN: u1, - /// When 1, an increment of the Hour value generates an interrupt. - IMHOUR: u1, - /// When 1, an increment of the Day of Month value generates an interrupt. - IMDOM: u1, - /// When 1, an increment of the Day of Week value generates an interrupt. - IMDOW: u1, - /// When 1, an increment of the Day of Year value generates an interrupt. - IMDOY: u1, - /// When 1, an increment of the Month value generates an interrupt. - IMMON: u1, - /// When 1, an increment of the Year value generates an interrupt. - IMYEAR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x40024010 - /// Alarm Mask Register - pub const AMR = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, the Second value is not compared for the alarm. - AMRSEC: u1, - /// When 1, the Minutes value is not compared for the alarm. - AMRMIN: u1, - /// When 1, the Hour value is not compared for the alarm. - AMRHOUR: u1, - /// When 1, the Day of Month value is not compared for the alarm. - AMRDOM: u1, - /// When 1, the Day of Week value is not compared for the alarm. - AMRDOW: u1, - /// When 1, the Day of Year value is not compared for the alarm. - AMRDOY: u1, - /// When 1, the Month value is not compared for the alarm. - AMRMON: u1, - /// When 1, the Year value is not compared for the alarm. - AMRYEAR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x10); - - /// address: 0x40024014 - /// Consolidated Time Register 0 - pub const CTIME0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Seconds value in the range of 0 to 59 - SECONDS: u6, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u2, - /// Minutes value in the range of 0 to 59 - MINUTES: u6, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u2, - /// Hours value in the range of 0 to 23 - HOURS: u5, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u3, - /// Day of week value in the range of 0 to 6 - DOW: u3, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u5, - }), base_address + 0x14); - - /// address: 0x40024018 - /// Consolidated Time Register 1 - pub const CTIME1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the - /// month and whether it is a leap year). - DOM: u5, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u3, - /// Month value in the range of 1 to 12. - MONTH: u4, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u4, - /// Year value in the range of 0 to 4095. - YEAR: u12, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u4, - }), base_address + 0x18); - - /// address: 0x4002401c - /// Consolidated Time Register 2 - pub const CTIME2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of year value in the range of 1 to 365 (366 for leap years). - DOY: u12, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x1c); - - /// address: 0x40024020 - /// Seconds Counter - pub const SEC = @intToPtr(*volatile Mmio(32, packed struct { - /// Seconds value in the range of 0 to 59 - SECONDS: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x20); - - /// address: 0x40024024 - /// Minutes Register - pub const MIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Minutes value in the range of 0 to 59 - MINUTES: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x24); - - /// address: 0x40024028 - /// Hours Register - pub const HRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Hours value in the range of 0 to 23 - HOURS: u5, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0x28); - - /// address: 0x4002402c - /// Day of Month Register - pub const DOM = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the - /// month and whether it is a leap year). - DOM: u5, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0x2c); - - /// address: 0x40024030 - /// Day of Week Register - pub const DOW = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of week value in the range of 0 to 6. - DOW: u3, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u29, - }), base_address + 0x30); - - /// address: 0x40024034 - /// Day of Year Register - pub const DOY = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of year value in the range of 1 to 365 (366 for leap years). - DOY: u9, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u23, - }), base_address + 0x34); - - /// address: 0x40024038 - /// Months Register - pub const MONTH = @intToPtr(*volatile Mmio(32, packed struct { - /// Month value in the range of 1 to 12. - MONTH: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x38); - - /// address: 0x4002403c - /// Years Register - pub const YEAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Year value in the range of 0 to 4095. - YEAR: u12, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x3c); - - /// address: 0x40024040 - /// Calibration Value Register - pub const CALIBRATION = @intToPtr(*volatile Mmio(32, packed struct { - /// If enabled, the calibration counter counts up to this value. The maximum value - /// is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL - /// = 0. - CALVAL: u17, - /// Calibration direction - CALDIR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x40); - - /// address: 0x40024044 - /// General Purpose Register 0 - pub const GPREG0 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose storage. - GP: u32, - }), base_address + 0x44); - - /// address: 0x40024048 - /// General Purpose Register 0 - pub const GPREG1 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose storage. - GP: u32, - }), base_address + 0x48); - - /// address: 0x4002404c - /// General Purpose Register 0 - pub const GPREG2 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose storage. - GP: u32, - }), base_address + 0x4c); - - /// address: 0x40024050 - /// General Purpose Register 0 - pub const GPREG3 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose storage. - GP: u32, - }), base_address + 0x50); - - /// address: 0x40024054 - /// General Purpose Register 0 - pub const GPREG4 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose storage. - GP: u32, - }), base_address + 0x54); - - /// address: 0x4002405c - /// RTC Auxiliary control register - pub const RTC_AUX = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator - /// stops, and when RTC power is first turned on. An interrupt will occur when this - /// bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is - /// enabled in the NVIC. Write: writing a 1 to this bit clears the flag. - RTC_OSCF: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM - /// pin indicates Deep Power-down mode. - RTC_PDOUT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u25, - }), base_address + 0x5c); - - /// address: 0x40024058 - /// RTC Auxiliary Enable register - pub const RTC_AUXEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect - /// interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is - /// enabled. See Section 30.6.2.5. - RTC_OSCFEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0x58); - - /// address: 0x40024060 - /// Alarm value for Seconds - pub const ASEC = @intToPtr(*volatile Mmio(32, packed struct { - /// Seconds value in the range of 0 to 59 - SECONDS: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x60); - - /// address: 0x40024064 - /// Alarm value for Minutes - pub const AMIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Minutes value in the range of 0 to 59 - MINUTES: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x64); - - /// address: 0x40024068 - /// Alarm value for Hours - pub const AHRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Hours value in the range of 0 to 23 - HOURS: u5, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0x68); - - /// address: 0x4002406c - /// Alarm value for Day of Month - pub const ADOM = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the - /// month and whether it is a leap year). - DOM: u5, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0x6c); - - /// address: 0x40024070 - /// Alarm value for Day of Week - pub const ADOW = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of week value in the range of 0 to 6. - DOW: u3, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u29, - }), base_address + 0x70); - - /// address: 0x40024074 - /// Alarm value for Day of Year - pub const ADOY = @intToPtr(*volatile Mmio(32, packed struct { - /// Day of year value in the range of 1 to 365 (366 for leap years). - DOY: u9, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u23, - }), base_address + 0x74); - - /// address: 0x40024078 - /// Alarm value for Months - pub const AMON = @intToPtr(*volatile Mmio(32, packed struct { - /// Month value in the range of 1 to 12. - MONTH: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x78); - - /// address: 0x4002407c - /// Alarm value for Year - pub const AYRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Year value in the range of 0 to 4095. - YEAR: u12, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x7c); - }; - /// GPIO - pub const GPIOINT = struct { - pub const base_address = 0x40028080; - - /// address: 0x40028080 - /// GPIO overall Interrupt Status. - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 GPIO interrupt pending. - P0INT: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u1, - /// Port 2 GPIO interrupt pending. - P2INT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40028084 - /// GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_0REI: u1, - /// Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_1REI: u1, - /// Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_2REI: u1, - /// Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_3REI: u1, - /// Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_4REI: u1, - /// Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_5REI: u1, - /// Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_6REI: u1, - /// Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_7REI: u1, - /// Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_8REI: u1, - /// Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_9REI: u1, - /// Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_10REI: u1, - /// Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_11REI: u1, - /// Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_12REI: u1, - /// Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_13REI: u1, - /// Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_14REI: u1, - /// Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_15REI: u1, - /// Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_16REI: u1, - /// Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_17REI: u1, - /// Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_18REI: u1, - /// Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_19REI: u1, - /// Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_20REI: u1, - /// Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_21REI: u1, - /// Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_22REI: u1, - /// Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_23REI: u1, - /// Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_24REI: u1, - /// Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_25REI: u1, - /// Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_26REI: u1, - /// Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_27REI: u1, - /// Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_28REI: u1, - /// Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_29REI: u1, - /// Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P0_30REI: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0x4); - - /// address: 0x40028088 - /// GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_0FEI: u1, - /// Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_1FEI: u1, - /// Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_2FEI: u1, - /// Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_3FEI: u1, - /// Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_4FEI: u1, - /// Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_5FEI: u1, - /// Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_6FEI: u1, - /// Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_7FEI: u1, - /// Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_8FEI: u1, - /// Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_9FEI: u1, - /// Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_10FEI: u1, - /// Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_11FEI: u1, - /// Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_12FEI: u1, - /// Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_13FEI: u1, - /// Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_14FEI: u1, - /// Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_15FEI: u1, - /// Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_16FEI: u1, - /// Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_17FEI: u1, - /// Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_18FEI: u1, - /// Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_19FEI: u1, - /// Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_20FEI: u1, - /// Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_21FEI: u1, - /// Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_22FEI: u1, - /// Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_23FEI: u1, - /// Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_24FEI: u1, - /// Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_25FEI: u1, - /// Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_26FEI: u1, - /// Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_27FEI: u1, - /// Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_28FEI: u1, - /// Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_29FEI: u1, - /// Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P0_30FEI: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0x8); - - /// address: 0x4002808c - /// GPIO Interrupt Clear. - pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_0CI: u1, - /// Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_1CI: u1, - /// Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_2CI: u1, - /// Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_3CI: u1, - /// Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_4CI: u1, - /// Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_5CI: u1, - /// Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_6CI: u1, - /// Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_7CI: u1, - /// Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_8CI: u1, - /// Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_9CI: u1, - /// Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_10CI: u1, - /// Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_11CI: u1, - /// Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_12CI: u1, - /// Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_13CI: u1, - /// Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_14CI: u1, - /// Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_15CI: u1, - /// Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_16CI: u1, - /// Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_17CI: u1, - /// Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_18CI: u1, - /// Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_19CI: u1, - /// Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_20CI: u1, - /// Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_21CI: u1, - /// Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_22CI: u1, - /// Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_23CI: u1, - /// Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_24CI: u1, - /// Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_25CI: u1, - /// Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_26CI: u1, - /// Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_27CI: u1, - /// Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_28CI: u1, - /// Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_29CI: u1, - /// Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P0_30CI: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0xc); - - /// address: 0x40028090 - /// GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_0ER: u1, - /// Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_1ER: u1, - /// Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_2ER: u1, - /// Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_3ER: u1, - /// Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_4ER: u1, - /// Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_5ER: u1, - /// Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_6ER: u1, - /// Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_7ER: u1, - /// Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_8ER: u1, - /// Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_9ER: u1, - /// Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_10ER: u1, - /// Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_11ER: u1, - /// Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_12ER: u1, - /// Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_13ER: u1, - /// Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_14ER: u1, - /// Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_15ER: u1, - /// Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_16ER: u1, - /// Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_17ER: u1, - /// Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_18ER: u1, - /// Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_19ER: u1, - /// Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_20ER: u1, - /// Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_21ER: u1, - /// Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_22ER: u1, - /// Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_23ER: u1, - /// Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_24ER: u1, - /// Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_25ER: u1, - /// Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_26ER: u1, - /// Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_27ER: u1, - /// Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_28ER: u1, - /// Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_29ER: u1, - /// Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P0_30ER: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0x10); - - /// address: 0x40028094 - /// GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_0EF: u1, - /// Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_1EF: u1, - /// Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_2EF: u1, - /// Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_3EF: u1, - /// Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_4EF: u1, - /// Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_5EF: u1, - /// Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_6EF: u1, - /// Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_7EF: u1, - /// Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_8EF: u1, - /// Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P0_9EF: u1, - /// Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_10EF: u1, - /// Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_11EF: u1, - /// Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_12EF: u1, - /// Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_13EF: u1, - /// Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_14EF: u1, - /// Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_15EF: u1, - /// Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_16EF: u1, - /// Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_17EF: u1, - /// Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_18EF: u1, - /// Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_19EF: u1, - /// Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_20EF: u1, - /// Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_21EF: u1, - /// Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_22EF: u1, - /// Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_23EF: u1, - /// Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_24EF: u1, - /// Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_25EF: u1, - /// Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_26EF: u1, - /// Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_27EF: u1, - /// Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_28EF: u1, - /// Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_29EF: u1, - /// Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P0_30EF: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0x14); - - /// address: 0x400280a4 - /// GPIO Interrupt Status for Rising edge for Port 0. - pub const STATR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_0REI: u1, - /// Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_1REI: u1, - /// Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_2REI: u1, - /// Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_3REI: u1, - /// Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_4REI: u1, - /// Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_5REI: u1, - /// Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_6REI: u1, - /// Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_7REI: u1, - /// Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_8REI: u1, - /// Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_9REI: u1, - /// Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_10REI: u1, - /// Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_11REI: u1, - /// Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_12REI: u1, - /// Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = - /// Rising edge interrupt generated. - P2_13REI: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x24); - - /// address: 0x400280a8 - /// GPIO Interrupt Status for Falling edge for Port 0. - pub const STATF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_0FEI: u1, - /// Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_1FEI: u1, - /// Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_2FEI: u1, - /// Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_3FEI: u1, - /// Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_4FEI: u1, - /// Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_5FEI: u1, - /// Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_6FEI: u1, - /// Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_7FEI: u1, - /// Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_8FEI: u1, - /// Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_9FEI: u1, - /// Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_10FEI: u1, - /// Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_11FEI: u1, - /// Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_12FEI: u1, - /// Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = - /// Falling edge interrupt generated. - P2_13FEI: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x28); - - /// address: 0x400280ac - /// GPIO Interrupt Clear. - pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_0CI: u1, - /// Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_1CI: u1, - /// Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_2CI: u1, - /// Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_3CI: u1, - /// Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_4CI: u1, - /// Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_5CI: u1, - /// Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_6CI: u1, - /// Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_7CI: u1, - /// Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_8CI: u1, - /// Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_9CI: u1, - /// Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_10CI: u1, - /// Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_11CI: u1, - /// Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_12CI: u1, - /// Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding - /// bits in IOnINTSTATR and IOnSTATF. - P2_13CI: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x2c); - - /// address: 0x400280b0 - /// GPIO Interrupt Enable for Rising edge for Port 0. - pub const ENR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_0ER: u1, - /// Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_1ER: u1, - /// Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_2ER: u1, - /// Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_3ER: u1, - /// Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_4ER: u1, - /// Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_5ER: u1, - /// Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_6ER: u1, - /// Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_7ER: u1, - /// Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_8ER: u1, - /// Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_9ER: u1, - /// Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_10ER: u1, - /// Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_11ER: u1, - /// Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_12ER: u1, - /// Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = - /// Enable rising edge interrupt. - P2_13ER: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x30); - - /// address: 0x400280b4 - /// GPIO Interrupt Enable for Falling edge for Port 0. - pub const ENF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_0EF: u1, - /// Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_1EF: u1, - /// Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_2EF: u1, - /// Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_3EF: u1, - /// Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_4EF: u1, - /// Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_5EF: u1, - /// Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_6EF: u1, - /// Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_7EF: u1, - /// Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_8EF: u1, - /// Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = - /// Enable falling edge interrupt. - P2_9EF: u1, - /// Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P2_10EF: u1, - /// Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P2_11EF: u1, - /// Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P2_12EF: u1, - /// Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 - /// = Enable falling edge interrupt. - P2_13EF: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x34); - }; - /// Pin connect block - pub const PINCONNECT = struct { - pub const base_address = 0x4002c000; - - /// address: 0x4002c000 - /// Pin function select register 0. - pub const PINSEL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin function select P0.0. - P0_0: u2, - /// Pin function select P0.1. - P0_1: u2, - /// Pin function select P0.2. - P0_2: u2, - /// Pin function select P0.3. - P0_3: u2, - /// Pin function select P0.4. - P0_4: u2, - /// Pin function select P0.5. - P0_5: u2, - /// Pin function select P0.6. - P0_6: u2, - /// Pin function select P0.7. - P0_7: u2, - /// Pin function select P0.8. - P0_8: u2, - /// Pin function select P0.9. - P0_9: u2, - /// Pin function select P0.10. - P0_10: u2, - /// Pin function select P0.11. - P0_11: u2, - /// Reserved. - RESERVED: u6, - /// Pin function select P0.15. - P0_15: u2, - }), base_address + 0x0); - - /// address: 0x4002c004 - /// Pin function select register 1. - pub const PINSEL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin function select P0.16. - P0_16: u2, - /// Pin function select P0.17. - P0_17: u2, - /// Pin function select P0.18. - P0_18: u2, - /// Pin function select P019. - P0_19: u2, - /// Pin function select P0.20. - P0_20: u2, - /// Pin function select P0.21. - P0_21: u2, - /// Pin function select P022 - P0_22: u2, - /// Pin function select P023. - P0_23: u2, - /// Pin function select P0.24. - P0_24: u2, - /// Pin function select P0.25. - P0_25: u2, - /// Pin function select P0.26. - P0_26: u2, - /// Pin function select P0.27. - P0_27: u2, - /// Pin function select P0.28. - P0_28: u2, - /// Pin function select P0.29 - P0_29: u2, - /// Pin function select P0.30. - P0_30: u2, - /// Reserved - RESERVED: u2, - }), base_address + 0x4); - - /// address: 0x4002c008 - /// Pin function select register 2. - pub const PINSEL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin function select P1.0. - P1_0: u2, - /// Pin function select P1.1. - P1_1: u2, - /// Reserved. - RESERVED: u4, - /// Pin function select P1.4. - P1_4: u2, - /// Reserved. - RESERVED: u6, - /// Pin function select P1.8. - P1_8: u2, - /// Pin function select P1.9. - P1_9: u2, - /// Pin function select P1.10. - P1_10: u2, - /// Pin function select P1.14. - P1_14: u2, - /// Reserved. - RESERVED: u6, - /// Pin function select P1.15. - P1_15: u2, - }), base_address + 0x8); - - /// address: 0x4002c00c - /// Pin function select register 3. - pub const PINSEL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin function select P1.16. - P1_16: u2, - /// Pin function select P1.17. - P1_17: u2, - /// Pin function select P1.18. - P1_18: u2, - /// Pin function select P1.19. - P1_19: u2, - /// Pin function select P1.20. - P1_20: u2, - /// Pin function select P1.21. - P1_21: u2, - /// Pin function select P1.22 - P1_22: u2, - /// Pin function select P1.23. - P1_23: u2, - /// Pin function select P1.24. - P1_24: u2, - /// Pin function select P1.25. - P1_25: u2, - /// Pin function select P1.26. - P1_26: u2, - /// Pin function select P1.27. - P1_27: u2, - /// Pin function select P1.28. - P1_28: u2, - /// Pin function select P1.29 - P1_29: u2, - /// Pin function select P1.30. - P1_30: u2, - /// Pin function select P1.31. - P1_31: u2, - }), base_address + 0xc); - - /// address: 0x4002c010 - /// Pin function select register 4 - pub const PINSEL4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin function select P2.0. - P2_0: u2, - /// Pin function select P2.1. - P2_1: u2, - /// Pin function select P2.2. - P2_2: u2, - /// Pin function select P2.3. - P2_3: u2, - /// Pin function select P2.4. - P2_4: u2, - /// Pin function select P2.5. - P2_5: u2, - /// Pin function select P2.6. - P2_6: u2, - /// Pin function select P2.7. - P2_7: u2, - /// Pin function select P2.8. - P2_8: u2, - /// Pin function select P2.9. - P2_9: u2, - /// Pin function select P2.10. - P2_10: u2, - /// Pin function select P2.11. - P2_11: u2, - /// Pin function select P2.12. - P2_12: u2, - /// Pin function select P2.13. - P2_13: u2, - /// Reserved. - RESERVED: u4, - }), base_address + 0x10); - - /// address: 0x4002c01c - /// Pin function select register 7 - pub const PINSEL7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u18, - /// Pin function select P3.25. - P3_25: u2, - /// Pin function select P3.26. - P3_26: u2, - /// Reserved. - RESERVED: u10, - }), base_address + 0x1c); - - /// address: 0x4002c024 - /// Pin function select register 9 - pub const PINSEL9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u24, - /// Pin function select P4.28. - P4_28: u2, - /// Pin function select P4.29. - P4_29: u2, - /// Reserved. - RESERVED: u4, - }), base_address + 0x24); - - /// address: 0x4002c028 - /// Pin function select register 10 - pub const PINSEL10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Software should not write 1 to these bits. - RESERVED: u3, - /// TPIU interface pins control. - TPIUCTRL: u1, - /// Reserved. Software should not write 1 to these bits. - RESERVED: u28, - }), base_address + 0x28); - - /// address: 0x4002c040 - /// Pin mode select register 0 - pub const PINMODE0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 pin 0 on-chip pull-up/down resistor control. - P0_00MODE: u2, - /// Port 0 pin 1 control. - P0_01MODE: u2, - /// Port 0 pin 2 control. - P0_02MODE: u2, - /// Port 0 pin 3 control. - P0_03MODE: u2, - /// Port 0 pin 4 control. - P0_04MODE: u2, - /// Port 0 pin 5 control. - P0_05MODE: u2, - /// Port 0 pin 6 control. - P0_06MODE: u2, - /// Port 0 pin 7 control. - P0_07MODE: u2, - /// Port 0 pin 8 control. - P0_08MODE: u2, - /// Port 0 pin 9 control. - P0_09MODE: u2, - /// Port 0 pin 10 control. - P0_10MODE: u2, - /// Port 0 pin 11 control. - P0_11MODE: u2, - /// Reserved. - RESERVED: u6, - /// Port 0 pin 15 control. - P0_15MODE: u2, - }), base_address + 0x40); - - /// address: 0x4002c044 - /// Pin mode select register 1 - pub const PINMODE1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 1 pin 16 control. - P0_16MODE: u2, - /// Port 1 pin 17 control. - P0_17MODE: u2, - /// Port 1 pin 18 control. - P0_18MODE: u2, - /// Port 1 pin 19 control. - P0_19MODE: u2, - /// Port 1 pin 20 control. - P0_20MODE: u2, - /// Port 1 pin 21 control. - P0_21MODE: u2, - /// Port 1 pin 22 control. - P0_22MODE: u2, - /// Port 1 pin 23 control. - P0_23MODE: u2, - /// Port 1 pin 24 control. - P0_24MODE: u2, - /// Port 1 pin 25 control. - P0_25MODE: u2, - /// Port 1 pin 26 control. - P0_26MODE: u2, - /// Reserved. - RESERVED: u8, - /// Reserved. - RESERVED: u2, - }), base_address + 0x44); - - /// address: 0x4002c048 - /// Pin mode select register 2 - pub const PINMODE2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 1 pin 0 control. - P1_00MODE: u2, - /// Port 1 pin 1 control. - P1_01MODE: u2, - /// Reserved. - RESERVED: u4, - /// Port 1 pin 4 control. - P1_04MODE: u2, - /// Reserved. - RESERVED: u6, - /// Port 1 pin 8 control. - P1_08MODE: u2, - /// Port 1 pin 9 control. - P1_09MODE: u2, - /// Port 1 pin 10 control. - P1_10MODE: u2, - /// Reserved. - RESERVED: u6, - /// Port 1 pin 14 control. - P1_14MODE: u2, - /// Port 1 pin 15 control. - P1_15MODE: u2, - }), base_address + 0x48); - - /// address: 0x4002c04c - /// Pin mode select register 3. - pub const PINMODE3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 1 pin 16 control. - P1_16MODE: u2, - /// Port 1 pin 17 control. - P1_17MODE: u2, - /// Port 1 pin 18 control. - P1_18MODE: u2, - /// Port 1 pin 19 control. - P1_19MODE: u2, - /// Port 1 pin 20 control. - P1_20MODE: u2, - /// Port 1 pin 21 control. - P1_21MODE: u2, - /// Port 1 pin 22 control. - P1_22MODE: u2, - /// Port 1 pin 23 control. - P1_23MODE: u2, - /// Port 1 pin 24 control. - P1_24MODE: u2, - /// Port 1 pin 25 control. - P1_25MODE: u2, - /// Port 1 pin 26 control. - P1_26MODE: u2, - /// Port 1 pin 27 control. - P1_27MODE: u2, - /// Port 1 pin 28 control. - P1_28MODE: u2, - /// Port 1 pin 29 control. - P1_29MODE: u2, - /// Port 1 pin 30 control. - P1_30MODE: u2, - /// Port 1 pin 31 control. - P1_31MODE: u2, - }), base_address + 0x4c); - - /// address: 0x4002c050 - /// Pin mode select register 4 - pub const PINMODE4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 2 pin 0 control. - P2_00MODE: u2, - /// Port 2 pin 1 control. - P2_01MODE: u2, - /// Port 2 pin 2 control. - P2_02MODE: u2, - /// Port 2 pin 3 control. - P2_03MODE: u2, - /// Port 2 pin 4 control. - P2_04MODE: u2, - /// Port 2 pin 5 control. - P2_05MODE: u2, - /// Port 2 pin 6 control. - P2_06MODE: u2, - /// Port 2 pin 7 control. - P2_07MODE: u2, - /// Port 2 pin 8 control. - P2_08MODE: u2, - /// Port 2 pin 9 control. - P2_09MODE: u2, - /// Port 2 pin 10 control. - P2_10MODE: u2, - /// Port 2 pin 11 control. - P2_11MODE: u2, - /// Port 2 pin 12 control. - P2_12MODE: u2, - /// Port 2 pin 13 control. - P2_13MODE: u2, - /// Reserved. - RESERVED: u4, - }), base_address + 0x50); - - /// address: 0x4002c05c - /// Pin mode select register 7 - pub const PINMODE7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved - RESERVED: u18, - /// Port 3 pin 25 control. - P3_25MODE: u2, - /// Port 3 pin 26 control. - P3_26MODE: u2, - /// Reserved. - RESERVED: u10, - }), base_address + 0x5c); - - /// address: 0x4002c064 - /// Pin mode select register 9 - pub const PINMODE9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u24, - /// Port 4 pin 28 control. - P4_28MODE: u2, - /// Port 4 pin 29 control. - P4_29MODE: u2, - /// Reserved. - RESERVED: u4, - }), base_address + 0x64); - - /// address: 0x4002c068 - /// Open drain mode control register 0 - pub const PINMODE_OD0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses - /// using standard port pins. If so, they should be configured for open drain mode - /// via the related bits in PINMODE_OD0. - P0_00OD: u1, - /// Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses - /// using standard port pins. If so, they should be configured for open drain mode - /// via the related bits in PINMODE_OD0. - P0_01OD: u1, - /// Port 0 pin 2 open drain mode control - P0_02OD: u1, - /// Port 0 pin 3 open drain mode control - P0_03OD: u1, - /// Port 0 pin 4 open drain mode control - P0_04OD: u1, - /// Port 0 pin 5 open drain mode control - P0_05OD: u1, - /// Port 0 pin 6 open drain mode control - P0_06OD: u1, - /// Port 0 pin 7 open drain mode control - P0_07OD: u1, - /// Port 0 pin 8 open drain mode control - P0_08OD: u1, - /// Port 0 pin 9 open drain mode control - P0_09OD: u1, - /// Port 0 pin 10 open drain mode control. Pins may potentially be used for - /// I2C-buses using standard port pins. If so, they should be configured for open - /// drain mode via the related bits in PINMODE_OD0. - P0_10OD: u1, - /// Port 0 pin 11 open drain mode control. Pins may potentially be used for - /// I2C-buses using standard port pins. If so, they should be configured for open - /// drain mode via the related bits in PINMODE_OD0. - P0_11OD: u1, - /// Reserved. - RESERVED: u3, - /// Port 0 pin 15 open drain mode control - P0_15OD: u1, - /// Port 0 pin 16 open drain mode control - P0_16OD: u1, - /// Port 0 pin 17 open drain mode control - P0_17OD: u1, - /// Port 0 pin 18 open drain mode control - P0_18OD: u1, - /// Port 0 pin 19 open drain mode control. Pins may potentially be used for - /// I2C-buses using standard port pins. If so, they should be configured for open - /// drain mode via the related bits in PINMODE_OD0. - P0_19OD: u1, - /// Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses - /// using standard port pins. If so, they should be configured for open drain mode - /// via the related bits in PINMODE_OD0. - P0_20OD: u1, - /// Port 0 pin 21 open drain mode control - P0_21OD: u1, - /// Port 0 pin 22 open drain mode control - P0_22OD: u1, - /// Port 0 pin 23 open drain mode control - P0_23OD: u1, - /// Port 0 pin 24open drain mode control - P0_24OD: u1, - /// Port 0 pin 25 open drain mode control - P0_25OD: u1, - /// Port 0 pin 26 open drain mode control - P0_26OD: u1, - /// Reserved. - RESERVED: u2, - /// Port 0 pin 29 open drain mode control - P0_29OD: u1, - /// Port 0 pin 30 open drain mode control - P0_30OD: u1, - /// Reserved. - RESERVED: u1, - }), base_address + 0x68); - - /// address: 0x4002c06c - /// Open drain mode control register 1 - pub const PINMODE_OD1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 1 pin 0 open drain mode control. - P1_00OD: u1, - /// Port 1 pin 1 open drain mode control, see P1.00OD - P1_01OD: u1, - /// Reserved. - RESERVED: u2, - /// Port 1 pin 4 open drain mode control, see P1.00OD - P1_04OD: u1, - /// Reserved. - RESERVED: u3, - /// Port 1 pin 8 open drain mode control, see P1.00OD - P1_08OD: u1, - /// Port 1 pin 9 open drain mode control, see P1.00OD - P1_09OD: u1, - /// Port 1 pin 10 open drain mode control, see P1.00OD - P1_10OD: u1, - /// Reserved. - RESERVED: u3, - /// Port 1 pin 14 open drain mode control, see P1.00OD - P1_14OD: u1, - /// Port 1 pin 15 open drain mode control, see P1.00OD - P1_15OD: u1, - /// Port 1 pin 16 open drain mode control, see P1.00OD - P1_16OD: u1, - /// Port 1 pin 17 open drain mode control, see P1.00OD - P1_17OD: u1, - /// Port 1 pin 18 open drain mode control, see P1.00OD - P1_18OD: u1, - /// Port 1 pin 19 open drain mode control, see P1.00OD - P1_19OD: u1, - /// Port 1 pin 20open drain mode control, see P1.00OD - P1_20OD: u1, - /// Port 1 pin 21 open drain mode control, see P1.00OD - P1_21OD: u1, - /// Port 1 pin 22 open drain mode control, see P1.00OD - P1_22OD: u1, - /// Port 1 pin 23 open drain mode control, see P1.00OD - P1_23OD: u1, - /// Port 1 pin 24open drain mode control, see P1.00OD - P1_24OD: u1, - /// Port 1 pin 25 open drain mode control, see P1.00OD - P1_25OD: u1, - /// Port 1 pin 26 open drain mode control, see P1.00OD - P1_26OD: u1, - /// Port 1 pin 27 open drain mode control, see P1.00OD - P1_27OD: u1, - /// Port 1 pin 28 open drain mode control, see P1.00OD - P1_28OD: u1, - /// Port 1 pin 29 open drain mode control, see P1.00OD - P1_29OD: u1, - /// Port 1 pin 30 open drain mode control, see P1.00OD - P1_30OD: u1, - /// Port 1 pin 31 open drain mode control. - P1_31OD: u1, - }), base_address + 0x6c); - - /// address: 0x4002c070 - /// Open drain mode control register 2 - pub const PINMODE_OD2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port 2 pin 0 open drain mode control. - P2_00OD: u1, - /// Port 2 pin 1 open drain mode control, see P2.00OD - P2_01OD: u1, - /// Port 2 pin 2 open drain mode control, see P2.00OD - P2_02OD: u1, - /// Port 2 pin 3 open drain mode control, see P2.00OD - P2_03OD: u1, - /// Port 2 pin 4 open drain mode control, see P2.00OD - P2_04OD: u1, - /// Port 2 pin 5 open drain mode control, see P2.00OD - P2_05OD: u1, - /// Port 2 pin 6 open drain mode control, see P2.00OD - P2_06OD: u1, - /// Port 2 pin 7 open drain mode control, see P2.00OD - P2_07OD: u1, - /// Port 2 pin 8 open drain mode control, see P2.00OD - P2_08OD: u1, - /// Port 2 pin 9 open drain mode control, see P2.00OD - P2_09OD: u1, - /// Port 2 pin 10 open drain mode control, see P2.00OD - P2_10OD: u1, - /// Port 2 pin 11 open drain mode control, see P2.00OD - P2_11OD: u1, - /// Port 2 pin 12 open drain mode control, see P2.00OD - P2_12OD: u1, - /// Port 2 pin 13 open drain mode control, see P2.00OD - P2_13OD: u1, - /// Reserved. - RESERVED: u18, - }), base_address + 0x70); - - /// address: 0x4002c074 - /// Open drain mode control register 3 - pub const PINMODE_OD3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u25, - /// Port 3 pin 25 open drain mode control. - P3_25OD: u1, - /// Port 3 pin 26 open drain mode control, see P3.25OD - P3_26OD: u1, - /// Reserved. - RESERVED: u5, - }), base_address + 0x74); - - /// address: 0x4002c078 - /// Open drain mode control register 4 - pub const PINMODE_OD4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - RESERVED: u28, - /// Port 4 pin 28 open drain mode control. - P4_28OD: u1, - /// Port 4 pin 29 open drain mode control, see P4.28OD - P4_29OD: u1, - /// Reserved. - RESERVED: u2, - }), base_address + 0x78); - - /// address: 0x4002c07c - /// I2C Pin Configuration register - pub const I2CPADCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Drive mode control for the SDA0 pin, P0.27. - SDADRV0: u1, - /// I 2C filter mode control for the SDA0 pin, P0.27. - SDAI2C0: u1, - /// Drive mode control for the SCL0 pin, P0.28. - SCLDRV0: u1, - /// I 2C filter mode control for the SCL0 pin, P0.28. - SCLI2C0: u1, - /// Reserved. - RESERVED: u28, - }), base_address + 0x7c); - }; - /// SSP1 controller - pub const SSP1 = struct { - pub const base_address = 0x40030000; - - /// address: 0x40030000 - /// Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Size Select. This field controls the number of bits transferred in each - /// frame. Values 0000-0010 are not supported and should not be used. - DSS: u4, - /// Frame Format. - FRF: u2, - /// Clock Out Polarity. This bit is only used in SPI mode. - CPOL: u1, - /// Clock Out Phase. This bit is only used in SPI mode. - CPHA: u1, - /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, - /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK - /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - SCR: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x0); - - /// address: 0x40030004 - /// Control Register 1. Selects master/slave and other modes. - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Loop Back Mode. - LBM: u1, - /// SSP Enable. - SSE: u1, - /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. - MS: u1, - /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is - /// 1, this blocks this SSP controller from driving the transmit data line (MISO). - SOD: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x4); - - /// address: 0x40030008 - /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write: software can write data to be sent in a future frame to this register - /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is - /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy - /// on the bus, transmission of the data will begin immediately. Otherwise the data - /// written to this register will be sent as soon as all previous data has been sent - /// (and received). If the data length is less than 16 bits, software must - /// right-justify the data written to this register. Read: software can read data - /// from this register whenever the RNE bit in the Status register is 1, indicating - /// that the Rx FIFO is not empty. When software reads this register, the SSP - /// controller returns data from the least recent frame in the Rx FIFO. If the data - /// length is less than 16 bits, the data is right-justified in this field with - /// higher order bits filled with 0s. - DATA: u16, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x8); - - /// address: 0x4003000c - /// Status Register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TFE: u1, - /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - TNF: u1, - /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RNE: u1, - /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - RFF: u1, - /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently - /// sending/receiving a frame and/or the Tx FIFO is not empty. - BSY: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0xc); - - /// address: 0x40030010 - /// Clock Prescale Register - pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { - /// This even value between 2 and 254, by which PCLK is divided to yield the - /// prescaler output clock. Bit 0 always reads as 0. - CPSDVSR: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x10); - - /// address: 0x40030014 - /// Interrupt Mask Set and Clear Register - pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { - /// Software should set this bit to enable interrupt when a Receive Overrun occurs, - /// that is, when the Rx FIFO is full and another frame is completely received. The - /// ARM spec implies that the preceding frame data is overwritten by the new frame - /// data when this occurs. - RORIM: u1, - /// Software should set this bit to enable interrupt when a Receive Time-out - /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and - /// no has not been read for a time-out period. The time-out period is the same for - /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / - /// (CPSDVSR X [SCR+1]). - RTIM: u1, - /// Software should set this bit to enable interrupt when the Rx FIFO is at least - /// half full. - RXIM: u1, - /// Software should set this bit to enable interrupt when the Tx FIFO is at least - /// half empty. - TXIM: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x14); - - /// address: 0x40030018 - /// Raw Interrupt Status Register - pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit is 1 if another frame was completely received while the RxFIFO was - /// full. The ARM spec implies that the preceding frame data is overwritten by the - /// new frame data when this occurs. - RORRIS: u1, - /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out - /// period. The time-out period is the same for master and slave modes and is - /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RTRIS: u1, - /// This bit is 1 if the Rx FIFO is at least half full. - RXRIS: u1, - /// This bit is 1 if the Tx FIFO is at least half empty. - TXRIS: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x18); - - /// address: 0x4003001c - /// Masked Interrupt Status Register - pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit is 1 if another frame was completely received while the RxFIFO was - /// full, and this interrupt is enabled. - RORMIS: u1, - /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out - /// period, and this interrupt is enabled. The time-out period is the same for - /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / - /// (CPSDVSR X [SCR+1]). - RTMIS: u1, - /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is - /// enabled. - RXMIS: u1, - /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is - /// enabled. - TXMIS: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x1c); - - /// address: 0x40030020 - /// SSPICR Interrupt Clear Register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 to this bit clears the frame was received when RxFIFO was full - /// interrupt. - RORIC: u1, - /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read - /// for a time-out period interrupt. The time-out period is the same for master and - /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / - /// [SCR+1]). - RTIC: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30, - }), base_address + 0x20); - - /// address: 0x40030024 - /// SSP0 DMA control register - pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is - /// enabled, otherwise receive DMA is disabled. - RXDMAE: u1, - /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is - /// enabled, otherwise transmit DMA is disabled - TXDMAE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30, - }), base_address + 0x24); - }; - /// Analog-to-Digital Converter (ADC) - pub const ADC = struct { - pub const base_address = 0x40034000; - - /// address: 0x40034000 - /// A/D Control Register. The ADCR register must be written to select the operating - /// mode before A/D conversion can occur. - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For - /// AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In - /// software-controlled mode, only one of these bits should be 1. In hardware scan - /// mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to - /// 0x01. - SEL: u8, - /// The APB clock (PCLK) is divided by (this value plus one) to produce the clock - /// for the A/D converter, which should be less than or equal to 12.4 MHz. - /// Typically, software should program the smallest value in this field that yields - /// a clock of 12.4 MHz or slightly less, but in certain cases (such as a - /// high-impedance analog source) a slower clock may be desirable. - CLKDIV: u8, - /// Burst mode - BURST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// Power down mode - PDN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// When the BURST bit is 0, these bits control whether and when an A/D conversion - /// is started: - START: u3, - /// This bit is significant only when the START field contains 010-111. In these - /// cases: - EDGE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - }), base_address + 0x0); - - /// address: 0x40034004 - /// A/D Global Data Register. This register contains the ADC's DONE bit and the - /// result of the most recent A/D conversion. - pub const GDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// When DONE is 1, this field contains a binary fraction representing the voltage - /// on the AD0[n] pin selected by the SEL field, as it falls within the range of - /// VREFP to VSS. Zero in the field indicates that the voltage on the input pin was - /// less than, equal to, or close to that on VSS, while 0xFFF indicates that the - /// voltage on the input was close to, equal to, or greater than that on VREFP. - RESULT: u12, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// These bits contain the channel from which the RESULT bits were converted (e.g. - /// 000 identifies channel 0, 001 channel 1...). - CHN: u3, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u3, - /// This bit is 1 in burst mode if the results of one or more conversions was (were) - /// lost and overwritten before the conversion that produced the result in the - /// RESULT bits. This bit is cleared by reading this register. - OVERRUN: u1, - /// This bit is set to 1 when an A/D conversion completes. It is cleared when this - /// register is read and when the ADCR is written. If the ADCR is written while a - /// conversion is still in progress, this bit is set and a new conversion is - /// started. - DONE: u1, - }), base_address + 0x4); - - /// address: 0x4003400c - /// A/D Interrupt Enable Register. This register contains enable bits that allow the - /// DONE flag of each A/D channel to be included or excluded from contributing to - /// the generation of an A/D interrupt. - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt enable - ADINTEN0: u1, - /// Interrupt enable - ADINTEN1: u1, - /// Interrupt enable - ADINTEN2: u1, - /// Interrupt enable - ADINTEN3: u1, - /// Interrupt enable - ADINTEN4: u1, - /// Interrupt enable - ADINTEN5: u1, - /// Interrupt enable - ADINTEN6: u1, - /// Interrupt enable - ADINTEN7: u1, - /// Interrupt enable - ADGINTEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u23, - }), base_address + 0xc); - - /// address: 0x40034010 - /// A/D Channel 0 Data Register. This register contains the result of the most - /// recent conversion completed on channel 0. - pub const DR = @intToPtr(*volatile [8]Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// When DONE is 1, this field contains a binary fraction representing the voltage - /// on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the - /// field indicates that the voltage on the input pin was less than, equal to, or - /// close to that on VSS, while 0xFFF indicates that the voltage on the input was - /// close to, equal to, or greater than that on VREFP. - RESULT: u12, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u14, - /// This bit is 1 in burst mode if the results of one or more conversions was (were) - /// lost and overwritten before the conversion that produced the result in the - /// RESULT bits.This bit is cleared by reading this register. - OVERRUN: u1, - /// This bit is set to 1 when an A/D conversion completes. It is cleared when this - /// register is read. - DONE: u1, - }), base_address + 0x10); - - /// address: 0x40034030 - /// A/D Status Register. This register contains DONE and OVERRUN flags for all of - /// the A/D channels, as well as the A/D interrupt/DMA flag. - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 0. - DONE0: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 1. - DONE1: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 2. - DONE2: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 3. - DONE3: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 4. - DONE4: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 5. - DONE5: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 6. - DONE6: u1, - /// This bit mirrors the DONE status flag from the result register for A/D channel - /// 7. - DONE7: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 0. - OVERRUN0: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 1. - OVERRUN1: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 2. - OVERRUN2: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 3. - OVERRUN3: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 4. - OVERRUN4: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 5. - OVERRUN5: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 6. - OVERRUN6: u1, - /// This bit mirrors the OVERRRUN status flag from the result register for A/D - /// channel 7. - OVERRUN7: u1, - /// This bit is the A/D interrupt flag. It is one when any of the individual A/D - /// channel Done flags is asserted and enabled to contribute to the A/D interrupt - /// via the ADINTEN register. - ADINT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u15, - }), base_address + 0x30); - - /// address: 0x40034034 - /// ADC trim register. - pub const TRM = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// Offset trim bits for ADC operation. Initialized by the boot code. Can be - /// overwritten by the user. - ADCOFFS: u4, - /// written-to by boot code. Can not be overwritten by the user. These bits are - /// locked after boot code write. - TRIM: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u20, - }), base_address + 0x34); - }; - /// CAN acceptance filter RAM - pub const CANAFRAM = struct { - pub const base_address = 0x40038000; - - /// address: 0x40038000 - /// CAN AF ram access register - pub const MASK = @intToPtr(*volatile [512]u32, base_address + 0x0); - }; - /// CAN controller acceptance filter - pub const CANAF = struct { - pub const base_address = 0x4003c000; - - /// address: 0x4003c000 - /// Acceptance Filter Register - pub const AFMR = @intToPtr(*volatile Mmio(32, packed struct { - /// if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all - /// CAN buses are ignored. - ACCOFF: u1, - /// All Rx messages are accepted on enabled CAN controllers. Software must set this - /// bit before modifying the contents of any of the registers described below, and - /// before modifying the contents of Lookup Table RAM in any way other than setting - /// or clearing Disable bits in Standard Identifier entries. When both this bit and - /// AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. - ACCBP: u1, - /// FullCAN mode - EFCAN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u29, - }), base_address + 0x0); - - /// address: 0x4003c004 - /// Standard Frame Individual Start Address Register - pub const SFF_SA = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// The start address of the table of individual Standard Identifiers in AF Lookup - /// RAM. If the table is empty, write the same value in this register and the - /// SFF_GRP_sa register described below. For compatibility with possible future - /// devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit - /// in the AFMR is 1, this value also indicates the size of the table of Standard - /// IDs which the Acceptance Filter will search and (if found) automatically store - /// received messages in Acceptance Filter RAM. - SFF_SA: u9, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x4); - - /// address: 0x4003c008 - /// Standard Frame Group Start Address Register - pub const SFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// The start address of the table of grouped Standard Identifiers in AF Lookup RAM. - /// If the table is empty, write the same value in this register and the EFF_sa - /// register described below. The largest value that should be written to this - /// register is 0x800, when only the Standard Individual table is used, and the last - /// word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with - /// possible future devices, please write zeroes in bits 31:12 and 1:0 of this - /// register. - SFF_GRP_SA: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u20, - }), base_address + 0x8); - - /// address: 0x4003c00c - /// Extended Frame Start Address Register - pub const EFF_SA = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// The start address of the table of individual Extended Identifiers in AF Lookup - /// RAM. If the table is empty, write the same value in this register and the - /// EFF_GRP_sa register described below. The largest value that should be written to - /// this register is 0x800, when both Extended Tables are empty and the last word - /// (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible - /// future devices, please write zeroes in bits 31:11 and 1:0 of this register. - EFF_SA: u9, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0xc); - - /// address: 0x4003c010 - /// Extended Frame Group Start Address Register - pub const EFF_GRP_SA = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// The start address of the table of grouped Extended Identifiers in AF Lookup RAM. - /// If the table is empty, write the same value in this register and the ENDofTable - /// register described below. The largest value that should be written to this - /// register is 0x800, when this table is empty and the last word (address 0x7FC) in - /// AF Lookup Table RAM is used. For compatibility with possible future devices, - /// please write zeroes in bits 31:12 and 1:0 of this register. - EFF_GRP_SA: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u20, - }), base_address + 0x10); - - /// address: 0x4003c014 - /// End of AF Tables register - pub const ENDOFTABLE = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// The address above the last active address in the last active AF table. For - /// compatibility with possible future devices, please write zeroes in bits 31:12 - /// and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value - /// that should be written to this register is 0x800, which allows the last word - /// (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR - /// is 1, this value marks the start of the area of Acceptance Filter RAM, into - /// which the Acceptance Filter will automatically receive messages for selected IDs - /// on selected CAN buses. In this case, the maximum value that should be written to - /// this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes - /// of message storage between this address and the end of Acceptance Filter RAM, - /// for each Standard ID that is specified between the start of Acceptance Filter - /// RAM, and the next active AF table. - ENDOFTABLE: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u20, - }), base_address + 0x14); - - /// address: 0x4003c018 - /// LUT Error Address register - pub const LUTERRAD = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// It the LUT Error bit (below) is 1, this read-only field contains the address in - /// AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the - /// content of the tables. - LUTERRAD: u9, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x18); - - /// address: 0x4003c01c - /// LUT Error Register - pub const LUTERR = @intToPtr(*volatile Mmio(32, packed struct { - /// This read-only bit is set to 1 if the Acceptance Filter encounters an error in - /// the content of the tables in AF RAM. It is cleared when software reads the - /// LUTerrAd register. This condition is ORed with the other CAN interrupts from the - /// CAN controllers, to produce the request that is connected to the NVIC. - LUTERR: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u31, - }), base_address + 0x1c); - - /// address: 0x4003c020 - /// FullCAN interrupt enable register - pub const FCANIE = @intToPtr(*volatile Mmio(32, packed struct { - /// Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. - FCANIE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u31, - }), base_address + 0x20); - - /// address: 0x4003c024 - /// FullCAN interrupt and capture register0 - pub const FCANIC0 = @intToPtr(*volatile Mmio(32, packed struct { - /// FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan - /// Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. - INTPND: u32, - }), base_address + 0x24); - - /// address: 0x4003c028 - /// FullCAN interrupt and capture register1 - pub const FCANIC1 = @intToPtr(*volatile Mmio(32, packed struct { - /// FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = - /// FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. - IntPnd32: u32, - }), base_address + 0x28); - }; - /// Central CAN controller - pub const CCAN = struct { - pub const base_address = 0x40040000; - - /// address: 0x40040000 - /// CAN Central Transmit Status Register - pub const TXSR = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). - TS1: u1, - /// When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) - TS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u6, - /// When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same - /// as TBS in CAN1GSR). - TBS1: u1, - /// When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same - /// as TBS in CAN2GSR). - TBS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u6, - /// When 1, all requested transmissions have been completed successfully by the CAN1 - /// controller (same as TCS in CAN1GSR). - TCS1: u1, - /// When 1, all requested transmissions have been completed successfully by the CAN2 - /// controller (same as TCS in CAN2GSR). - TCS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u14, - }), base_address + 0x0); - - /// address: 0x40040004 - /// CAN Central Receive Status Register - pub const RXSR = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, CAN1 is receiving a message (same as RS in CAN1GSR). - RS1: u1, - /// When 1, CAN2 is receiving a message (same as RS in CAN2GSR). - RS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u6, - /// When 1, a received message is available in the CAN1 controller (same as RBS in - /// CAN1GSR). - RB1: u1, - /// When 1, a received message is available in the CAN2 controller (same as RBS in - /// CAN2GSR). - RB2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u6, - /// When 1, a message was lost because the preceding message to CAN1 controller was - /// not read out quickly enough (same as DOS in CAN1GSR). - DOS1: u1, - /// When 1, a message was lost because the preceding message to CAN2 controller was - /// not read out quickly enough (same as DOS in CAN2GSR). - DOS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u14, - }), base_address + 0x4); - - /// address: 0x40040008 - /// CAN Central Miscellaneous Register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit - /// set in the CAN1EWL register (same as ES in CAN1GSR) - E1: u1, - /// When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit - /// set in the CAN2EWL register (same as ES in CAN2GSR) - E2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u6, - /// When 1, the CAN1 controller is currently involved in bus activities (same as BS - /// in CAN1GSR). - BS1: u1, - /// When 1, the CAN2 controller is currently involved in bus activities (same as BS - /// in CAN2GSR). - BS2: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x8); - }; - /// CAN1 controller - pub const CAN1 = struct { - pub const base_address = 0x40044000; - - /// address: 0x40044000 - /// Controls the operating mode of the CAN Controller. - pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset Mode. - RM: u1, - /// Listen Only Mode. - LOM: u1, - /// Self Test Mode. - STM: u1, - /// Transmit Priority Mode. - TPM: u1, - /// Sleep Mode. - SM: u1, - /// Receive Polarity Mode. - RPM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Test Mode. - TM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x40044004 - /// Command bits that affect the state of the CAN Controller - pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Request. - TR: u1, - /// Abort Transmission. - AT: u1, - /// Release Receive Buffer. - RRB: u1, - /// Clear Data Overrun. - CDO: u1, - /// Self Reception Request. - SRR: u1, - /// Select Tx Buffer 1. - STB1: u1, - /// Select Tx Buffer 2. - STB2: u1, - /// Select Tx Buffer 3. - STB3: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x40044008 - /// Global Controller Status and Error Counters. The error counters can only be - /// written when RM in CANMOD is 1. - pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Buffer Status. After reading all messages and releasing their memory - /// space with the command 'Release Receive Buffer,' this bit is cleared. - RBS: u1, - /// Data Overrun Status. If there is not enough space to store the message within - /// the Receive Buffer, that message is dropped and the Data Overrun condition is - /// signalled to the CPU in the moment this message becomes valid. If this message - /// is not completed successfully (e.g. because of an error), no overrun condition - /// is signalled. - DOS: u1, - /// Transmit Buffer Status. - TBS: u1, - /// Transmit Complete Status. The Transmission Complete Status bit is set '0' - /// (incomplete) whenever the Transmission Request bit or the Self Reception Request - /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission - /// Complete Status bit will remain '0' until all messages are transmitted - /// successfully. - TCS: u1, - /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' - /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to - /// become idle again. After hardware reset 11 consecutive recessive bits have to be - /// detected until idle status is reached. After Bus-off this will take 128 times of - /// 11 consecutive recessive bits. - RS: u1, - /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' - /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to - /// become idle again. After hardware reset 11 consecutive recessive bits have to be - /// detected until idle status is reached. After Bus-off this will take 128 times of - /// 11 consecutive recessive bits. - TS: u1, - /// Error Status. Errors detected during reception or transmission will effect the - /// error counters according to the CAN specification. The Error Status bit is set - /// when at least one of the error counters has reached or exceeded the Error - /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default - /// value of the Error Warning Limit after hardware reset is 96 decimal, see also - /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - /// - 0x4004 8018). - ES: u1, - /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, - /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the - /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears - /// the Reset Mode bit. Once this is completed the CAN Controller will wait the - /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting - /// down the Transmit Error Counter. After that, the Bus Status bit is cleared - /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, - /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error - /// Counter during this time gives information about the status of the Bus-Off - /// recovery. - BS: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// The current value of the Rx Error Counter (an 8-bit value). - RXERR: u8, - /// The current value of the Tx Error Counter (an 8-bit value). - TXERR: u8, - }), base_address + 0x8); - - /// address: 0x4004400c - /// Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE - /// bit in CANxIER are both 1, indicating that a new message was received and stored - /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read - /// access to the Interrupt Register. Giving the Command Release Receive Buffer will - /// clear RI temporarily. If there is another message available within the Receive - /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. - RI: u1, - /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), - /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is - /// 1. - TI1: u1, - /// Error Warning Interrupt. This bit is set on every change (set or clear) of - /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set - /// within the Interrupt Enable Register at the time of the change. - EI: u1, - /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 - /// to 1 and the DOIE bit in CANxIER is 1. - DOI: u1, - /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus - /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is - /// also generated if the CPU tries to set the Sleep bit while the CAN controller is - /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also - /// get asserted when the according enable bit WUIE is not set. In this case a - /// Wake-Up Interrupt does not get asserted. - WUI: u1, - /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and - /// the CAN controller switches between Error Passive and Error Active mode in - /// either direction. This is the case when the CAN Controller has reached the Error - /// Passive Status (at least one error counter exceeds the CAN protocol defined - /// level of 127) or if the CAN Controller is in Error Passive Status and enters the - /// Error Active Status again. - EPI: u1, - /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and - /// the CAN controller loses arbitration while attempting to transmit. In this case - /// the CAN node becomes a receiver. - ALI: u1, - /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the - /// CAN controller detects an error on the bus. - BEI: u1, - /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN - /// Identifier has been received (a message was successfully transmitted or - /// aborted). This bit is set whenever a message was successfully transmitted or - /// aborted and the IDIE bit is set in the IER register. - IDI: u1, - /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), - /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is - /// 1. - TI2: u1, - /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), - /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is - /// 1. - TI3: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u5, - /// Error Code Capture: when the CAN controller detects a bus error, the location of - /// the error within the frame is captured in this field. The value reflects an - /// internal state variable, and as a result is not very linear: 00011 = Start of - /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE - /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit - /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = - /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot - /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever - /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. - /// At the same time, the current position of the Bit Stream Processor is captured - /// into the Error Code Capture Register. The content within this register is fixed - /// until the user software has read out its content once. From now on, the capture - /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error - /// Interrupt. - ERRBIT4_0: u5, - /// When the CAN controller detects a bus error, the direction of the current bit is - /// captured in this bit. - ERRDIR: u1, - /// When the CAN controller detects a bus error, the type of error is captured in - /// this field: - ERRC1_0: u2, - /// Each time arbitration is lost while trying to send on the CAN, the bit number - /// within the frame is captured into this field. After the content of ALCBIT is - /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 - /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost - /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE - /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 - /// = arbitration lost in last bit of identifier (extended frame only) 31 = - /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the - /// corresponding arbitration lost interrupt is forced, if enabled. At that time, - /// the current bit position of the Bit Stream Processor is captured into the - /// Arbitration Lost Capture Register. The content within this register is fixed - /// until the user application has read out its contents once. From now on, the - /// capture mechanism is activated again. - ALCBIT: u8, - }), base_address + 0xc); - - /// address: 0x40044010 - /// Interrupt Enable - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN - /// Controller requests the respective interrupt. - RIE: u1, - /// Transmit Interrupt Enable for Buffer1. When a message has been successfully - /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE1: u1, - /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status - /// Register), the CAN Controller requests the respective interrupt. - EIE: u1, - /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status - /// Register), the CAN Controller requests the respective interrupt. - DOIE: u1, - /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the - /// respective interrupt is requested. - WUIE: u1, - /// Error Passive Interrupt Enable. If the error status of the CAN Controller - /// changes from error active to error passive or vice versa, the respective - /// interrupt is requested. - EPIE: u1, - /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, - /// the respective interrupt is requested. - ALIE: u1, - /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller - /// requests the respective interrupt. - BEIE: u1, - /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN - /// Controller requests the respective interrupt. - IDIE: u1, - /// Transmit Interrupt Enable for Buffer2. When a message has been successfully - /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE2: u1, - /// Transmit Interrupt Enable for Buffer3. When a message has been successfully - /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE3: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x10); - - /// address: 0x40044014 - /// Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to - /// produce the CAN clock. - BRP: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// The Synchronization Jump Width is (this value plus one) CAN clocks. - SJW: u2, - /// The delay from the nominal Sync point to the sample point is (this value plus - /// one) CAN clocks. - TESG1: u4, - /// The delay from the sample point to the next nominal sync point is (this value - /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in - /// TSEG1 plus 3) CAN clocks. - TESG2: u3, - /// Sampling - SAM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - }), base_address + 0x14); - - /// address: 0x40044018 - /// Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { - /// During CAN operation, this value is compared to both the Tx and Rx Error - /// Counters. If either of these counter matches this value, the Error Status (ES) - /// bit in CANSR is set. - EWL: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x4004401c - /// Status Register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_1: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_1: u1, - /// Transmit Buffer Status 1. - TBS1_1: u1, - /// Transmission Complete Status. - TCS1_1: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_1: u1, - /// Transmit Status 1. - TS1_1: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_1: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_1: u1, - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_2: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_2: u1, - /// Transmit Buffer Status 2. - TBS2_2: u1, - /// Transmission Complete Status. - TCS2_2: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_2: u1, - /// Transmit Status 2. - TS2_2: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_2: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_2: u1, - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_3: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_3: u1, - /// Transmit Buffer Status 3. - TBS3_3: u1, - /// Transmission Complete Status. - TCS3_3: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_3: u1, - /// Transmit Status 3. - TS3_3: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_3: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_3: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u8, - }), base_address + 0x1c); - - /// address: 0x40044020 - /// Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { - /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the - /// Lookup Table RAM entry at which the Acceptance Filter matched the received - /// Identifier. Disabled entries in the Standard tables are included in this - /// numbering, but will not be matched. See Section 21.17 Examples of acceptance - /// filter tables and ID index values on page 587 for examples of ID Index values. - IDINDEX: u10, - /// If this bit is 1, the current message was received in AF Bypass mode, and the ID - /// Index field (above) is meaningless. - BP: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u5, - /// The field contains the Data Length Code (DLC) field of the current received - /// message. When RTR = 0, this is related to the number of data bytes available in - /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = - /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to - /// be sent back, with the same encoding. - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This bit contains the Remote Transmission Request bit of the current received - /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be - /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote - /// frame, in which case the DLC value identifies the number of data bytes requested - /// to be sent using the same Identifier. - RTR: u1, - /// A 0 in this bit indicates that the current received message included an 11-bit - /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents - /// of the CANid register described below. - FF: u1, - }), base_address + 0x20); - - /// address: 0x40044024 - /// Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these - /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - ID: u11, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u21, - }), base_address + 0x24); - - /// address: 0x40044028 - /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of - /// the current received message. - DATA1: u8, - /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of - /// the current received message. - DATA2: u8, - /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of - /// the current received message. - DATA3: u8, - /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of - /// the current received message. - DATA4: u8, - }), base_address + 0x28); - - /// address: 0x4004402c - /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of - /// the current received message. - DATA5: u8, - /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of - /// the current received message. - DATA6: u8, - /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of - /// the current received message. - DATA7: u8, - /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of - /// the current received message. - DATA8: u8, - }), base_address + 0x2c); - - /// address: 0x40044030 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x30); - - /// address: 0x40044040 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x40); - - /// address: 0x40044050 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x50); - - /// address: 0x40044034 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x34); - - /// address: 0x40044044 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x44); - - /// address: 0x40044054 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x54); - - /// address: 0x40044038 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x38); - - /// address: 0x40044048 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x48); - - /// address: 0x40044058 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x58); - - /// address: 0x4004403c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x3c); - - /// address: 0x4004404c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x4c); - - /// address: 0x4004405c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x5c); - }; - pub const CAN2 = struct { - pub const base_address = 0x40048000; - - /// address: 0x40048000 - /// Controls the operating mode of the CAN Controller. - pub const MOD = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset Mode. - RM: u1, - /// Listen Only Mode. - LOM: u1, - /// Self Test Mode. - STM: u1, - /// Transmit Priority Mode. - TPM: u1, - /// Sleep Mode. - SM: u1, - /// Receive Polarity Mode. - RPM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Test Mode. - TM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x40048004 - /// Command bits that affect the state of the CAN Controller - pub const CMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmission Request. - TR: u1, - /// Abort Transmission. - AT: u1, - /// Release Receive Buffer. - RRB: u1, - /// Clear Data Overrun. - CDO: u1, - /// Self Reception Request. - SRR: u1, - /// Select Tx Buffer 1. - STB1: u1, - /// Select Tx Buffer 2. - STB2: u1, - /// Select Tx Buffer 3. - STB3: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x40048008 - /// Global Controller Status and Error Counters. The error counters can only be - /// written when RM in CANMOD is 1. - pub const GSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Buffer Status. After reading all messages and releasing their memory - /// space with the command 'Release Receive Buffer,' this bit is cleared. - RBS: u1, - /// Data Overrun Status. If there is not enough space to store the message within - /// the Receive Buffer, that message is dropped and the Data Overrun condition is - /// signalled to the CPU in the moment this message becomes valid. If this message - /// is not completed successfully (e.g. because of an error), no overrun condition - /// is signalled. - DOS: u1, - /// Transmit Buffer Status. - TBS: u1, - /// Transmit Complete Status. The Transmission Complete Status bit is set '0' - /// (incomplete) whenever the Transmission Request bit or the Self Reception Request - /// bit is set '1' at least for one of the three Transmit Buffers. The Transmission - /// Complete Status bit will remain '0' until all messages are transmitted - /// successfully. - TCS: u1, - /// Receive Status. If both the Receive Status and the Transmit Status bits are '0' - /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to - /// become idle again. After hardware reset 11 consecutive recessive bits have to be - /// detected until idle status is reached. After Bus-off this will take 128 times of - /// 11 consecutive recessive bits. - RS: u1, - /// Transmit Status. If both the Receive Status and the Transmit Status bits are '0' - /// (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to - /// become idle again. After hardware reset 11 consecutive recessive bits have to be - /// detected until idle status is reached. After Bus-off this will take 128 times of - /// 11 consecutive recessive bits. - TS: u1, - /// Error Status. Errors detected during reception or transmission will effect the - /// error counters according to the CAN specification. The Error Status bit is set - /// when at least one of the error counters has reached or exceeded the Error - /// Warning Limit. An Error Warning Interrupt is generated, if enabled. The default - /// value of the Error Warning Limit after hardware reset is 96 decimal, see also - /// Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - /// - 0x4004 8018). - ES: u1, - /// Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, - /// if enabled. Afterwards the Transmit Error Counter is set to '127', and the - /// Receive Error Counter is cleared. It will stay in this mode until the CPU clears - /// the Reset Mode bit. Once this is completed the CAN Controller will wait the - /// minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting - /// down the Transmit Error Counter. After that, the Bus Status bit is cleared - /// (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, - /// and an Error Warning Interrupt is generated, if enabled. Reading the TX Error - /// Counter during this time gives information about the status of the Bus-Off - /// recovery. - BS: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// The current value of the Rx Error Counter (an 8-bit value). - RXERR: u8, - /// The current value of the Tx Error Counter (an 8-bit value). - TXERR: u8, - }), base_address + 0x8); - - /// address: 0x4004800c - /// Interrupt status, Arbitration Lost Capture, Error Code Capture - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE - /// bit in CANxIER are both 1, indicating that a new message was received and stored - /// in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read - /// access to the Interrupt Register. Giving the Command Release Receive Buffer will - /// clear RI temporarily. If there is another message available within the Receive - /// Buffer after the release command, RI is set again. Otherwise RI remains cleared. - RI: u1, - /// Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB1 was successfully transmitted or aborted), - /// indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is - /// 1. - TI1: u1, - /// Error Warning Interrupt. This bit is set on every change (set or clear) of - /// either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set - /// within the Interrupt Enable Register at the time of the change. - EI: u1, - /// Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 - /// to 1 and the DOIE bit in CANxIER is 1. - DOI: u1, - /// Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus - /// activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is - /// also generated if the CPU tries to set the Sleep bit while the CAN controller is - /// involved in bus activities or a CAN Interrupt is pending. The WUI flag can also - /// get asserted when the according enable bit WUIE is not set. In this case a - /// Wake-Up Interrupt does not get asserted. - WUI: u1, - /// Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and - /// the CAN controller switches between Error Passive and Error Active mode in - /// either direction. This is the case when the CAN Controller has reached the Error - /// Passive Status (at least one error counter exceeds the CAN protocol defined - /// level of 127) or if the CAN Controller is in Error Passive Status and enters the - /// Error Active Status again. - EPI: u1, - /// Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and - /// the CAN controller loses arbitration while attempting to transmit. In this case - /// the CAN node becomes a receiver. - ALI: u1, - /// Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the - /// CAN controller detects an error on the bus. - BEI: u1, - /// ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN - /// Identifier has been received (a message was successfully transmitted or - /// aborted). This bit is set whenever a message was successfully transmitted or - /// aborted and the IDIE bit is set in the IER register. - IDI: u1, - /// Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB2 was successfully transmitted or aborted), - /// indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is - /// 1. - TI2: u1, - /// Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to - /// 1 (whenever a message out of TXB3 was successfully transmitted or aborted), - /// indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is - /// 1. - TI3: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u5, - /// Error Code Capture: when the CAN controller detects a bus error, the location of - /// the error within the frame is captured in this field. The value reflects an - /// internal state variable, and as a result is not very linear: 00011 = Start of - /// Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE - /// bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit - /// 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = - /// Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot - /// 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever - /// a bus error occurs, the corresponding bus error interrupt is forced, if enabled. - /// At the same time, the current position of the Bit Stream Processor is captured - /// into the Error Code Capture Register. The content within this register is fixed - /// until the user software has read out its content once. From now on, the capture - /// mechanism is activated again, i.e. reading the CANxICR enables another Bus Error - /// Interrupt. - ERRBIT4_0: u5, - /// When the CAN controller detects a bus error, the direction of the current bit is - /// captured in this bit. - ERRDIR: u1, - /// When the CAN controller detects a bus error, the type of error is captured in - /// this field: - ERRC1_0: u2, - /// Each time arbitration is lost while trying to send on the CAN, the bit number - /// within the frame is captured into this field. After the content of ALCBIT is - /// read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 - /// = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost - /// in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE - /// bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 - /// = arbitration lost in last bit of identifier (extended frame only) 31 = - /// arbitration lost in RTR bit (extended frame only) On arbitration lost, the - /// corresponding arbitration lost interrupt is forced, if enabled. At that time, - /// the current bit position of the Bit Stream Processor is captured into the - /// Arbitration Lost Capture Register. The content within this register is fixed - /// until the user application has read out its contents once. From now on, the - /// capture mechanism is activated again. - ALCBIT: u8, - }), base_address + 0xc); - - /// address: 0x40048010 - /// Interrupt Enable - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN - /// Controller requests the respective interrupt. - RIE: u1, - /// Transmit Interrupt Enable for Buffer1. When a message has been successfully - /// transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE1: u1, - /// Error Warning Interrupt Enable. If the Error or Bus Status change (see Status - /// Register), the CAN Controller requests the respective interrupt. - EIE: u1, - /// Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status - /// Register), the CAN Controller requests the respective interrupt. - DOIE: u1, - /// Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the - /// respective interrupt is requested. - WUIE: u1, - /// Error Passive Interrupt Enable. If the error status of the CAN Controller - /// changes from error active to error passive or vice versa, the respective - /// interrupt is requested. - EPIE: u1, - /// Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, - /// the respective interrupt is requested. - ALIE: u1, - /// Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller - /// requests the respective interrupt. - BEIE: u1, - /// ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN - /// Controller requests the respective interrupt. - IDIE: u1, - /// Transmit Interrupt Enable for Buffer2. When a message has been successfully - /// transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE2: u1, - /// Transmit Interrupt Enable for Buffer3. When a message has been successfully - /// transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an - /// Abort Transmission command), the CAN Controller requests the respective - /// interrupt. - TIE3: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x10); - - /// address: 0x40048014 - /// Bus Timing. Can only be written when RM in CANMOD is 1. - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud Rate Prescaler. The APB clock is divided by (this value plus one) to - /// produce the CAN clock. - BRP: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// The Synchronization Jump Width is (this value plus one) CAN clocks. - SJW: u2, - /// The delay from the nominal Sync point to the sample point is (this value plus - /// one) CAN clocks. - TESG1: u4, - /// The delay from the sample point to the next nominal sync point is (this value - /// plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in - /// TSEG1 plus 3) CAN clocks. - TESG2: u3, - /// Sampling - SAM: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - }), base_address + 0x14); - - /// address: 0x40048018 - /// Error Warning Limit. Can only be written when RM in CANMOD is 1. - pub const EWL = @intToPtr(*volatile Mmio(32, packed struct { - /// During CAN operation, this value is compared to both the Tx and Rx Error - /// Counters. If either of these counter matches this value, the Error Status (ES) - /// bit in CANSR is set. - EWL: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x4004801c - /// Status Register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_1: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_1: u1, - /// Transmit Buffer Status 1. - TBS1_1: u1, - /// Transmission Complete Status. - TCS1_1: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_1: u1, - /// Transmit Status 1. - TS1_1: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_1: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_1: u1, - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_2: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_2: u1, - /// Transmit Buffer Status 2. - TBS2_2: u1, - /// Transmission Complete Status. - TCS2_2: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_2: u1, - /// Transmit Status 2. - TS2_2: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_2: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_2: u1, - /// Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. - RBS_3: u1, - /// Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. - DOS_3: u1, - /// Transmit Buffer Status 3. - TBS3_3: u1, - /// Transmission Complete Status. - TCS3_3: u1, - /// Receive Status. This bit is identical to the RS bit in the GSR. - RS_3: u1, - /// Transmit Status 3. - TS3_3: u1, - /// Error Status. This bit is identical to the ES bit in the CANxGSR. - ES_3: u1, - /// Bus Status. This bit is identical to the BS bit in the CANxGSR. - BS_3: u1, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u8, - }), base_address + 0x1c); - - /// address: 0x40048020 - /// Receive frame status. Can only be written when RM in CANMOD is 1. - pub const RFS = @intToPtr(*volatile Mmio(32, packed struct { - /// ID Index. If the BP bit (below) is 0, this value is the zero-based number of the - /// Lookup Table RAM entry at which the Acceptance Filter matched the received - /// Identifier. Disabled entries in the Standard tables are included in this - /// numbering, but will not be matched. See Section 21.17 Examples of acceptance - /// filter tables and ID index values on page 587 for examples of ID Index values. - IDINDEX: u10, - /// If this bit is 1, the current message was received in AF Bypass mode, and the ID - /// Index field (above) is meaningless. - BP: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u5, - /// The field contains the Data Length Code (DLC) field of the current received - /// message. When RTR = 0, this is related to the number of data bytes available in - /// the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = - /// 8 bytes With RTR = 1, this value indicates the number of data bytes requested to - /// be sent back, with the same encoding. - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This bit contains the Remote Transmission Request bit of the current received - /// message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be - /// read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote - /// frame, in which case the DLC value identifies the number of data bytes requested - /// to be sent using the same Identifier. - RTR: u1, - /// A 0 in this bit indicates that the current received message included an 11-bit - /// Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents - /// of the CANid register described below. - FF: u1, - }), base_address + 0x20); - - /// address: 0x40048024 - /// Received Identifier. Can only be written when RM in CANMOD is 1. - pub const RID = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier field of the current received message. In CAN 2.0A, these - /// bits are called ID10-0, while in CAN 2.0B they're called ID29-18. - ID: u11, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u21, - }), base_address + 0x24); - - /// address: 0x40048028 - /// Received data bytes 1-4. Can only be written when RM in CANMOD is 1. - pub const RDA = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of - /// the current received message. - DATA1: u8, - /// Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of - /// the current received message. - DATA2: u8, - /// Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of - /// the current received message. - DATA3: u8, - /// Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of - /// the current received message. - DATA4: u8, - }), base_address + 0x28); - - /// address: 0x4004802c - /// Received data bytes 5-8. Can only be written when RM in CANMOD is 1. - pub const RDB = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of - /// the current received message. - DATA5: u8, - /// Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of - /// the current received message. - DATA6: u8, - /// Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of - /// the current received message. - DATA7: u8, - /// Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of - /// the current received message. - DATA8: u8, - }), base_address + 0x2c); - - /// address: 0x40048030 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x30); - - /// address: 0x40048040 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI2 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x40); - - /// address: 0x40048050 - /// Transmit - /// frame info (Tx Buffer ) - pub const TFI3 = @intToPtr(*volatile Mmio(32, packed struct { - /// If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, - /// enabled Tx Buffers contend for the right to send their messages based on this - /// field. The buffer with the lowest TX Priority value wins the prioritization and - /// is sent first. - PRIO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// Data Length Code. This value is sent in the DLC field of the next transmit - /// message. In addition, if RTR = 0, this value controls the number of Data bytes - /// sent in the next transmit message, from the CANxTDA and CANxTDB registers: - /// 0000-0111 = 0-7 bytes 1xxx = 8 bytes - DLC: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u10, - /// This value is sent in the RTR bit of the next transmit message. If this bit is - /// 0, the number of data bytes called out by the DLC field are sent from the - /// CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, - /// containing a request for that number of bytes. - RTR: u1, - /// If this bit is 0, the next transmit message will be sent with an 11-bit - /// Identifier (standard frame format), while if it's 1, the message will be sent - /// with a 29-bit Identifier (extended frame format). - FF: u1, - }), base_address + 0x50); - - /// address: 0x40048034 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID1 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x34); - - /// address: 0x40048044 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID2 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x44); - - /// address: 0x40048054 - /// Transmit - /// Identifier (Tx Buffer) - pub const TID3 = @intToPtr(*volatile Mmio(32, packed struct { - /// The 11-bit Identifier to be sent in the next transmit message. - ID: u11, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u21, - }), base_address + 0x54); - - /// address: 0x40048038 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x38); - - /// address: 0x40048048 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x48); - - /// address: 0x40048058 - /// Transmit - /// data bytes 1-4 (Tx Buffer) - pub const TDA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is - /// sent as the first Data byte of the next transmit message. - DATA1: u8, - /// Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is - /// sent as the 2nd Data byte of the next transmit message. - DATA2: u8, - /// Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is - /// sent as the 3rd Data byte of the next transmit message. - DATA3: u8, - /// Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is - /// sent as the 4th Data byte of the next transmit message. - DATA4: u8, - }), base_address + 0x58); - - /// address: 0x4004803c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x3c); - - /// address: 0x4004804c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x4c); - - /// address: 0x4004805c - /// Transmit - /// data bytes 5-8 (Tx Buffer ) - pub const TDB3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is - /// sent as the 5th Data byte of the next transmit message. - DATA5: u8, - /// Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is - /// sent as the 6th Data byte of the next transmit message. - DATA6: u8, - /// Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is - /// sent as the 7th Data byte of the next transmit message. - DATA7: u8, - /// Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is - /// sent as the 8th Data byte of the next transmit message. - DATA8: u8, - }), base_address + 0x5c); - }; - pub const I2C1 = struct { - pub const base_address = 0x4005c000; - - /// address: 0x4005c000 - /// I2C Control Set Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is set. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge flag. - AA: u1, - /// I2C interrupt flag. - SI: u1, - /// STOP flag. - STO: u1, - /// START flag. - STA: u1, - /// I2C interface enable. - I2EN: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u25, - }), base_address + 0x0); - - /// address: 0x4005c004 - /// I2C Status Register. During I2C operation, this register provides detailed - /// status codes that allow software to determine the next action needed. - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// These bits are unused and are always 0. - RESERVED: u3, - /// These bits give the actual status information about the I 2C interface. - Status: u5, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x4005c008 - /// I2C Data Register. During master or slave transmit mode, data to be transmitted - /// is written to this register. During master or slave receive mode, data that has - /// been received may be read from this register. - pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds data values that have been received or are to be - /// transmitted. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x4005c00c - /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x4005c010 - /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C - /// clock. - pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL HIGH time period selection. - SCLH: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x10); - - /// address: 0x4005c014 - /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. - /// SCLL and SCLH together determine the clock frequency generated by an I2C master - /// and certain times used in slave mode. - pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL low time period selection. - SCLL: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x14); - - /// address: 0x4005c018 - /// I2C Control Clear Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is cleared. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge Clear bit. - AAC: u1, - /// I2C interrupt Clear bit. - SIC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// START flag Clear bit. - STAC: u1, - /// I2C interface Disable bit. - I2ENC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x4005c01c - /// Monitor mode control register. - pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Monitor mode enable. - MM_ENA: u1, - /// SCL output enable. - ENA_SCL: u1, - /// Select interrupt register match. - MATCH_ALL: u1, - /// Reserved. The value read from reserved bits is not defined. - RESERVED: u29, - }), base_address + 0x1c); - - /// address: 0x4005c020 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x20); - - /// address: 0x4005c024 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x24); - - /// address: 0x4005c028 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x4005c02c - /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will - /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of - /// data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds contents of the 8 MSBs of the DAT shift register. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x2c); - - /// address: 0x4005c030 - /// I2C Slave address mask register - pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. This bit reads - /// always back as 0. - RESERVED: u1, - /// Mask bits. - MASK: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x30); - }; - /// SSP controller - pub const SSP0 = struct { - pub const base_address = 0x40088000; - - /// address: 0x40088000 - /// Control Register 0. Selects the serial clock rate, bus type, and data size. - pub const CR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data Size Select. This field controls the number of bits transferred in each - /// frame. Values 0000-0010 are not supported and should not be used. - DSS: u4, - /// Frame Format. - FRF: u2, - /// Clock Out Polarity. This bit is only used in SPI mode. - CPOL: u1, - /// Clock Out Phase. This bit is only used in SPI mode. - CPHA: u1, - /// Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, - /// minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK - /// clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). - SCR: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x0); - - /// address: 0x40088004 - /// Control Register 1. Selects master/slave and other modes. - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Loop Back Mode. - LBM: u1, - /// SSP Enable. - SSE: u1, - /// Master/Slave Mode.This bit can only be written when the SSE bit is 0. - MS: u1, - /// Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is - /// 1, this blocks this SSP controller from driving the transmit data line (MISO). - SOD: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x4); - - /// address: 0x40088008 - /// Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write: software can write data to be sent in a future frame to this register - /// whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is - /// not full. If the Tx FIFO was previously empty and the SSP controller is not busy - /// on the bus, transmission of the data will begin immediately. Otherwise the data - /// written to this register will be sent as soon as all previous data has been sent - /// (and received). If the data length is less than 16 bits, software must - /// right-justify the data written to this register. Read: software can read data - /// from this register whenever the RNE bit in the Status register is 1, indicating - /// that the Rx FIFO is not empty. When software reads this register, the SSP - /// controller returns data from the least recent frame in the Rx FIFO. If the data - /// length is less than 16 bits, the data is right-justified in this field with - /// higher order bits filled with 0s. - DATA: u16, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x8); - - /// address: 0x4008800c - /// Status Register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. - TFE: u1, - /// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. - TNF: u1, - /// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. - RNE: u1, - /// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. - RFF: u1, - /// Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently - /// sending/receiving a frame and/or the Tx FIFO is not empty. - BSY: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0xc); - - /// address: 0x40088010 - /// Clock Prescale Register - pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { - /// This even value between 2 and 254, by which PCLK is divided to yield the - /// prescaler output clock. Bit 0 always reads as 0. - CPSDVSR: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED0: u8 = 0, - RESERVED1: u16 = 0, - }), base_address + 0x10); - - /// address: 0x40088014 - /// Interrupt Mask Set and Clear Register - pub const IMSC = @intToPtr(*volatile Mmio(32, packed struct { - /// Software should set this bit to enable interrupt when a Receive Overrun occurs, - /// that is, when the Rx FIFO is full and another frame is completely received. The - /// ARM spec implies that the preceding frame data is overwritten by the new frame - /// data when this occurs. - RORIM: u1, - /// Software should set this bit to enable interrupt when a Receive Time-out - /// condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and - /// no has not been read for a time-out period. The time-out period is the same for - /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / - /// (CPSDVSR X [SCR+1]). - RTIM: u1, - /// Software should set this bit to enable interrupt when the Rx FIFO is at least - /// half full. - RXIM: u1, - /// Software should set this bit to enable interrupt when the Tx FIFO is at least - /// half empty. - TXIM: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x14); - - /// address: 0x40088018 - /// Raw Interrupt Status Register - pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit is 1 if another frame was completely received while the RxFIFO was - /// full. The ARM spec implies that the preceding frame data is overwritten by the - /// new frame data when this occurs. - RORRIS: u1, - /// This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out - /// period. The time-out period is the same for master and slave modes and is - /// determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). - RTRIS: u1, - /// This bit is 1 if the Rx FIFO is at least half full. - RXRIS: u1, - /// This bit is 1 if the Tx FIFO is at least half empty. - TXRIS: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x18); - - /// address: 0x4008801c - /// Masked Interrupt Status Register - pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit is 1 if another frame was completely received while the RxFIFO was - /// full, and this interrupt is enabled. - RORMIS: u1, - /// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out - /// period, and this interrupt is enabled. The time-out period is the same for - /// master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / - /// (CPSDVSR X [SCR+1]). - RTMIS: u1, - /// This bit is 1 if the Rx FIFO is at least half full, and this interrupt is - /// enabled. - RXMIS: u1, - /// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is - /// enabled. - TXMIS: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x1c); - - /// address: 0x40088020 - /// SSPICR Interrupt Clear Register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 to this bit clears the frame was received when RxFIFO was full - /// interrupt. - RORIC: u1, - /// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read - /// for a time-out period interrupt. The time-out period is the same for master and - /// slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / - /// [SCR+1]). - RTIC: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30, - }), base_address + 0x20); - - /// address: 0x40088024 - /// SSP0 DMA control register - pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is - /// enabled, otherwise receive DMA is disabled. - RXDMAE: u1, - /// Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is - /// enabled, otherwise transmit DMA is disabled - TXDMAE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30, - }), base_address + 0x24); - }; - /// Digital-to-Analog Converter (DAC) - pub const DAC = struct { - pub const base_address = 0x4008c000; - - /// address: 0x4008c000 - /// D/A Converter Register. This register contains the digital value to be converted - /// to analog and a power control bit. - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u6, - /// After the selected settling time after this field is written with a new VALUE, - /// the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V - /// REFN)/1024) + VREFN. - VALUE: u10, - /// Settling time The settling times noted in the description of the BIAS bit are - /// valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load - /// impedance value greater than that value will cause settling time longer than the - /// specified time. One or more graphs of load impedance vs. settling time will be - /// included in the final data sheet. - BIAS: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u15, - }), base_address + 0x0); - - /// address: 0x4008c004 - /// DAC Control register. This register controls DMA and timer operation. - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA interrupt request - INT_DMA_REQ: u1, - /// Double buffering - DBLBUF_ENA: u1, - /// Time-out counter operation - CNT_ENA: u1, - /// DMA access - DMA_ENA: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x4); - - /// address: 0x4008c008 - /// DAC Counter Value register. This register contains the reload value for the DAC - /// DMA/Interrupt timer. - pub const CNTVAL = @intToPtr(*volatile Mmio(32, packed struct { - /// 16-bit reload value for the DAC interrupt/DMA timer. - VALUE: u16, - /// Reserved - RESERVED: u16, - }), base_address + 0x8); - }; - pub const TIMER2 = struct { - pub const base_address = 0x40090000; - - /// address: 0x40090000 - /// Interrupt Register. The IR can be written to clear interrupts. The IR can be - /// read to identify which of eight possible interrupt sources are pending. - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag for match channel 0. - MR0INT: u1, - /// Interrupt flag for match channel 1. - MR1INT: u1, - /// Interrupt flag for match channel 2. - MR2INT: u1, - /// Interrupt flag for match channel 3. - MR3INT: u1, - /// Interrupt flag for capture channel 0 event. - CR0INT: u1, - /// Interrupt flag for capture channel 1 event. - CR1INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x0); - - /// address: 0x40090004 - /// Timer Control Register. The TCR is used to control the Timer Counter functions. - /// The Timer Counter can be disabled or reset through the TCR. - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - /// When one, the Timer Counter and Prescale Counter are enabled for counting. When - /// zero, the counters are disabled. - CEN: u1, - /// When one, the Timer Counter and the Prescale Counter are synchronously reset on - /// the next positive edge of PCLK. The counters remain reset until TCR[1] is - /// returned to zero. - CRST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x4); - - /// address: 0x40090008 - /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is - /// controlled through the TCR. - pub const TC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4009000c - /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the - /// next clock increments the TC and clears the PC. - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescale counter maximum value. - PM: u32, - }), base_address + 0xc); - - /// address: 0x40090010 - /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value - /// stored in PR. When the value in PR is reached, the TC is incremented and the PC - /// is cleared. The PC is observable and controllable through the bus interface. - pub const PC = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40090014 - /// Match Control Register. The MCR is used to control if an interrupt is generated - /// and if the TC is reset when a Match occurs. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt on MR0 - MR0I: u1, - /// Reset on MR0 - MR0R: u1, - /// Stop on MR0 - MR0S: u1, - /// Interrupt on MR1 - MR1I: u1, - /// Reset on MR1 - MR1R: u1, - /// Stop on MR1 - MR1S: u1, - /// Interrupt on MR2 - MR2I: u1, - /// Reset on MR2 - MR2R: u1, - /// Stop on MR2. - MR2S: u1, - /// Interrupt on MR3 - MR3I: u1, - /// Reset on MR3 - MR3R: u1, - /// Stop on MR3 - MR3S: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x14); - - /// address: 0x40090018 - /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both - /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x18); - - /// address: 0x40090028 - /// Capture Control Register. The CCR controls which edges of the capture inputs are - /// used to load the Capture Registers and whether or not an interrupt is generated - /// when a capture takes place. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture on CAPn.0 rising edge - CAP0RE: u1, - /// Capture on CAPn.0 falling edge - CAP0FE: u1, - /// Interrupt on CAPn.0 event - CAP0I: u1, - /// Capture on CAPn.1 rising edge - CAP1RE: u1, - /// Capture on CAPn.1 falling edge - CAP1FE: u1, - /// Interrupt on CAPn.1 event - CAP1I: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x4009002c - /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on - /// the CAPn.0 input. - pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Timer counter capture value. - CAP: u32, - }), base_address + 0x2c); - - /// address: 0x4009003c - /// External Match Register. The EMR controls the external match pins. - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Match 0. When a match occurs between the TC and MR0, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM0: u1, - /// External Match 1. When a match occurs between the TC and MR1, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this - /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM1: u1, - /// External Match 2. When a match occurs between the TC and MR2, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM2: u1, - /// External Match 3. When a match occurs between the TC and MR3, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM3: u1, - /// External Match Control 0. Determines the functionality of External Match 0. - EMC0: u2, - /// External Match Control 1. Determines the functionality of External Match 1. - EMC1: u2, - /// External Match Control 2. Determines the functionality of External Match 2. - EMC2: u2, - /// External Match Control 3. Determines the functionality of External Match 3. - EMC3: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x3c); - - /// address: 0x40090070 - /// Count Control Register. The CTCR selects between Timer and Counter mode, and in - /// Counter mode selects the signal and edge(s) for counting. - pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter/Timer Mode This field selects which rising PCLK edges can increment - /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). - /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale - /// Register. - CTMODE: u2, - /// Count Input Select When bits 1:0 in this register are not 00, these bits select - /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a - /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture - /// Control Register (TnCCR) must be programmed as 000. However, capture and/or - /// interrupt can be selected for the other 3 CAPn inputs in the same timer. - CINSEL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x70); - }; - pub const TIMER3 = struct { - pub const base_address = 0x40094000; - - /// address: 0x40094000 - /// Interrupt Register. The IR can be written to clear interrupts. The IR can be - /// read to identify which of eight possible interrupt sources are pending. - pub const IR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag for match channel 0. - MR0INT: u1, - /// Interrupt flag for match channel 1. - MR1INT: u1, - /// Interrupt flag for match channel 2. - MR2INT: u1, - /// Interrupt flag for match channel 3. - MR3INT: u1, - /// Interrupt flag for capture channel 0 event. - CR0INT: u1, - /// Interrupt flag for capture channel 1 event. - CR1INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x0); - - /// address: 0x40094004 - /// Timer Control Register. The TCR is used to control the Timer Counter functions. - /// The Timer Counter can be disabled or reset through the TCR. - pub const TCR = @intToPtr(*volatile Mmio(32, packed struct { - /// When one, the Timer Counter and Prescale Counter are enabled for counting. When - /// zero, the counters are disabled. - CEN: u1, - /// When one, the Timer Counter and the Prescale Counter are synchronously reset on - /// the next positive edge of PCLK. The counters remain reset until TCR[1] is - /// returned to zero. - CRST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x4); - - /// address: 0x40094008 - /// Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is - /// controlled through the TCR. - pub const TC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4009400c - /// Prescale Register. When the Prescale Counter (PC) is equal to this value, the - /// next clock increments the TC and clears the PC. - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescale counter maximum value. - PM: u32, - }), base_address + 0xc); - - /// address: 0x40094010 - /// Prescale Counter. The 32 bit PC is a counter which is incremented to the value - /// stored in PR. When the value in PR is reached, the TC is incremented and the PC - /// is cleared. The PC is observable and controllable through the bus interface. - pub const PC = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40094014 - /// Match Control Register. The MCR is used to control if an interrupt is generated - /// and if the TC is reset when a Match occurs. - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt on MR0 - MR0I: u1, - /// Reset on MR0 - MR0R: u1, - /// Stop on MR0 - MR0S: u1, - /// Interrupt on MR1 - MR1I: u1, - /// Reset on MR1 - MR1R: u1, - /// Stop on MR1 - MR1S: u1, - /// Interrupt on MR2 - MR2I: u1, - /// Reset on MR2 - MR2R: u1, - /// Stop on MR2. - MR2S: u1, - /// Interrupt on MR3 - MR3I: u1, - /// Reset on MR3 - MR3R: u1, - /// Stop on MR3 - MR3S: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x14); - - /// address: 0x40094018 - /// Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both - /// the TC and PC, and/or generate an interrupt every time MR0 matches the TC. - pub const MR = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Timer counter match value. - MATCH: u32, - }), base_address + 0x18); - - /// address: 0x40094028 - /// Capture Control Register. The CCR controls which edges of the capture inputs are - /// used to load the Capture Registers and whether or not an interrupt is generated - /// when a capture takes place. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture on CAPn.0 rising edge - CAP0RE: u1, - /// Capture on CAPn.0 falling edge - CAP0FE: u1, - /// Interrupt on CAPn.0 event - CAP0I: u1, - /// Capture on CAPn.1 rising edge - CAP1RE: u1, - /// Capture on CAPn.1 falling edge - CAP1FE: u1, - /// Interrupt on CAPn.1 event - CAP1I: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x4009402c - /// Capture Register 0. CR0 is loaded with the value of TC when there is an event on - /// the CAPn.0 input. - pub const CR = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// Timer counter capture value. - CAP: u32, - }), base_address + 0x2c); - - /// address: 0x4009403c - /// External Match Register. The EMR controls the external match pins. - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Match 0. When a match occurs between the TC and MR0, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 5:4 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM0: u1, - /// External Match 1. When a match occurs between the TC and MR1, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 7:6 of this - /// register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM1: u1, - /// External Match 2. When a match occurs between the TC and MR2, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 9:8 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM2: u1, - /// External Match 3. When a match occurs between the TC and MR3, this bit can - /// either toggle, go low, go high, or do nothing, depending on bits 11:10 of this - /// register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner - /// (0 = low, 1 = high). - EM3: u1, - /// External Match Control 0. Determines the functionality of External Match 0. - EMC0: u2, - /// External Match Control 1. Determines the functionality of External Match 1. - EMC1: u2, - /// External Match Control 2. Determines the functionality of External Match 2. - EMC2: u2, - /// External Match Control 3. Determines the functionality of External Match 3. - EMC3: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0x3c); - - /// address: 0x40094070 - /// Count Control Register. The CTCR selects between Timer and Counter mode, and in - /// Counter mode selects the signal and edge(s) for counting. - pub const CTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter/Timer Mode This field selects which rising PCLK edges can increment - /// Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). - /// Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale - /// Register. - CTMODE: u2, - /// Count Input Select When bits 1:0 in this register are not 00, these bits select - /// which CAP pin is sampled for clocking. Note: If Counter mode is selected for a - /// particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture - /// Control Register (TnCCR) must be programmed as 000. However, capture and/or - /// interrupt can be selected for the other 3 CAPn inputs in the same timer. - CINSEL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x70); - }; - pub const UART2 = struct { - pub const base_address = 0x40098000; - - /// address: 0x40098000 - /// Receiver Buffer Register. Contains the next received character to be read (DLAB - /// =0). - pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Receiver Buffer Register contains the oldest received byte in the - /// UARTn Rx FIFO. - RBR: u8, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x40098000 - /// Transmit Holding Regiter. The next character to be transmitted is written here - /// (DLAB =0). - pub const THR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing to the UARTn Transmit Holding Register causes the data to be stored in - /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the - /// FIFO and the transmitter is available. - THR: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x40098000 - /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines - /// the baud rate of the UARTn. - DLLSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x40098004 - /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines - /// the baud rate of the UARTn. - DLMSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x40098004 - /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 - /// potential UART interrupts (DLAB =0). - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It - /// also controls the Character Receive Time-out interrupt. - RBRIE: u1, - /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this - /// can be read from UnLSR[5]. - THREIE: u1, - /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. - /// The status of this interrupt can be read from UnLSR[4:1]. - RXIE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// Enables the end of auto-baud interrupt. - ABEOINTEN: u1, - /// Enables the auto-baud time-out interrupt. - ABTOINTEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x4); - - /// address: 0x40098008 - /// Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be - /// determined by evaluating UnIIR[3:1]. - INTSTATUS: u1, - /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to - /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below - /// are reserved (000,100,101,111). - INTID: u3, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// Copies of UnFCR[0]. - FIFOENABLE: u2, - /// End of auto-baud interrupt. True if auto-baud has finished successfully and - /// interrupt is enabled. - ABEOINT: u1, - /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is - /// enabled. - ABTOINT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x8); - - /// address: 0x40098008 - /// FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO Enable. - FIFOEN: u1, - /// RX FIFO Reset. - RXFIFORES: u1, - /// TX FIFO Reset. - TXFIFORES: u1, - /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit - /// selects the DMA mode. See Section 18.6.6.1. - DMAMODE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO - /// characters must be written before an interrupt or DMA request is activated. - RXTRIGLVL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x4009800c - /// Line Control Register. Contains controls for frame formatting and break - /// generation. - pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Word Length Select. - WLS: u2, - /// Stop Bit Select - SBS: u1, - /// Parity Enable. - PE: u1, - /// Parity Select - PS: u2, - /// Break Control - BC: u1, - /// Divisor Latch Access Bit - DLAB: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x40098014 - /// Line Status Register. Contains flags for transmit and receive status, including - /// line errors. - pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character - /// and is cleared when the UARTn RBR FIFO is empty. - RDR: u1, - /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR - /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character - /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will - /// not be overwritten and the character in the UARTn RSR will be lost. - OE: u1, - /// Parity Error. When the parity bit of a received character is in the wrong state, - /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error - /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the - /// character at the top of the UARTn RBR FIFO. - PE: u1, - /// Framing Error. When the stop bit of a received character is a logic 0, a framing - /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error - /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx - /// will attempt to resynchronize to the data and assume that the bad stop bit is - /// actually an early start bit. However, it cannot be assumed that the next - /// received byte will be correct even if there is no Framing Error. Note: A framing - /// error is associated with the character at the top of the UARTn RBR FIFO. - FE: u1, - /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one - /// full character transmission (start, data, parity, stop), a break interrupt - /// occurs. Once the break condition has been detected, the receiver goes idle until - /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The - /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is - /// associated with the character at the top of the UARTn RBR FIFO. - BI: u1, - /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an - /// empty UARTn THR and is cleared on a UnTHR write. - THRE: u1, - /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is - /// cleared when either the UnTSR or the UnTHR contain valid data. - TEMT: u1, - /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as - /// framing error, parity error or break interrupt, is loaded into the UnRBR. This - /// bit is cleared when the UnLSR register is read and there are no subsequent - /// errors in the UARTn FIFO. - RXFE: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x14); - - /// address: 0x4009801c - /// Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - /// A readable, writable byte. - PAD: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x1c); - - /// address: 0x40098020 - /// Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit. This bit is automatically cleared after auto-baud completion. - START: u1, - /// Auto-baud mode select bit. - MODE: u1, - /// Restart bit. - AUTORESTART: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABEOINTCLR: u1, - /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x20); - - /// address: 0x40098028 - /// Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional - /// baud-rate generator will not impact the UARTn baudrate. - DIVADDVAL: u4, - /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for - /// UARTn to operate properly, regardless of whether the fractional baud-rate - /// generator is used or not. - MULVAL: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x40098030 - /// Transmit Enable Register. Turns off UART transmitter for use with software flow - /// control. - pub const TER = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u7, - /// When this bit is 1, as it is after a Reset, data written to the THR is output on - /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared - /// to 0 while a character is being sent, the transmission of that character is - /// completed, but no further characters are sent until this bit is set again. In - /// other words, a 0 in this bit blocks the transfer of characters from the THR or - /// TX FIFO into the transmit shift register. Software implementing - /// software-handshaking can clear this bit when it receives an XOFF character - /// (DC3). Software can set this bit again when it receives an XON (DC1) character. - TXEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x30); - - /// address: 0x4009804c - /// RS-485/EIA-485 Control. Contains controls to configure various aspects of - /// RS-485/EIA-485 modes. - pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// NMM enable. - NMMEN: u1, - /// Receiver enable. - RXDIS: u1, - /// AAD enable. - AADEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Direction control enable. - DCTRL: u1, - /// Direction control pin polarity. This bit reverses the polarity of the direction - /// control signal on the Un_OE pin. - OINV: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x4c); - - /// address: 0x40098050 - /// RS-485/EIA-485 address match. Contains the address match value for - /// RS-485/EIA-485 mode. - pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the address match value. - ADRMATCH: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x50); - - /// address: 0x40098054 - /// RS-485/EIA-485 direction control delay. - pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the direction control (UnOE) delay value. This register works in - /// conjunction with an 8-bit counter. - DLY: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x54); - }; - pub const UART3 = struct { - pub const base_address = 0x4009c000; - - /// address: 0x4009c000 - /// Receiver Buffer Register. Contains the next received character to be read (DLAB - /// =0). - pub const RBR = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Receiver Buffer Register contains the oldest received byte in the - /// UARTn Rx FIFO. - RBR: u8, - /// Reserved, the value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x4009c000 - /// Transmit Holding Regiter. The next character to be transmitted is written here - /// (DLAB =0). - pub const THR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing to the UARTn Transmit Holding Register causes the data to be stored in - /// the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the - /// FIFO and the transmitter is available. - THR: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x4009c000 - /// Divisor Latch LSB. Least significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLL = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines - /// the baud rate of the UARTn. - DLLSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x4009c004 - /// Divisor Latch MSB. Most significant byte of the baud rate divisor value. The - /// full divisor is used to generate a baud rate from the fractional rate divider - /// (DLAB =1). - pub const DLM = @intToPtr(*volatile Mmio(32, packed struct { - /// The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines - /// the baud rate of the UARTn. - DLMSB: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x4009c004 - /// Interrupt Enable Register. Contains individual interrupt enable bits for the 7 - /// potential UART interrupts (DLAB =0). - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It - /// also controls the Character Receive Time-out interrupt. - RBRIE: u1, - /// THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this - /// can be read from UnLSR[5]. - THREIE: u1, - /// RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. - /// The status of this interrupt can be read from UnLSR[4:1]. - RXIE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// Enables the end of auto-baud interrupt. - ABEOINTEN: u1, - /// Enables the auto-baud time-out interrupt. - ABTOINTEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x4); - - /// address: 0x4009c008 - /// Interrupt ID Register. Identifies which interrupt(s) are pending. - pub const IIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be - /// determined by evaluating UnIIR[3:1]. - INTSTATUS: u1, - /// Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to - /// the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below - /// are reserved (000,100,101,111). - INTID: u3, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// Copies of UnFCR[0]. - FIFOENABLE: u2, - /// End of auto-baud interrupt. True if auto-baud has finished successfully and - /// interrupt is enabled. - ABEOINT: u1, - /// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is - /// enabled. - ABTOINT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x8); - - /// address: 0x4009c008 - /// FIFO Control Register. Controls UART FIFO usage and modes. - pub const FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO Enable. - FIFOEN: u1, - /// RX FIFO Reset. - RXFIFORES: u1, - /// TX FIFO Reset. - TXFIFORES: u1, - /// DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit - /// selects the DMA mode. See Section 18.6.6.1. - DMAMODE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// RX Trigger Level. These two bits determine how many receiver UARTn FIFO - /// characters must be written before an interrupt or DMA request is activated. - RXTRIGLVL: u2, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x4009c00c - /// Line Control Register. Contains controls for frame formatting and break - /// generation. - pub const LCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Word Length Select. - WLS: u2, - /// Stop Bit Select - SBS: u1, - /// Parity Enable. - PE: u1, - /// Parity Select - PS: u2, - /// Break Control - BC: u1, - /// Divisor Latch Access Bit - DLAB: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x4009c014 - /// Line Status Register. Contains flags for transmit and receive status, including - /// line errors. - pub const LSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character - /// and is cleared when the UARTn RBR FIFO is empty. - RDR: u1, - /// Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR - /// read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character - /// assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will - /// not be overwritten and the character in the UARTn RSR will be lost. - OE: u1, - /// Parity Error. When the parity bit of a received character is in the wrong state, - /// a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error - /// detection is dependent on UnFCR[0]. Note: A parity error is associated with the - /// character at the top of the UARTn RBR FIFO. - PE: u1, - /// Framing Error. When the stop bit of a received character is a logic 0, a framing - /// error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error - /// detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx - /// will attempt to resynchronize to the data and assume that the bad stop bit is - /// actually an early start bit. However, it cannot be assumed that the next - /// received byte will be correct even if there is no Framing Error. Note: A framing - /// error is associated with the character at the top of the UARTn RBR FIFO. - FE: u1, - /// Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one - /// full character transmission (start, data, parity, stop), a break interrupt - /// occurs. Once the break condition has been detected, the receiver goes idle until - /// RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The - /// time of break detection is dependent on UnFCR[0]. Note: The break interrupt is - /// associated with the character at the top of the UARTn RBR FIFO. - BI: u1, - /// Transmitter Holding Register Empty. THRE is set immediately upon detection of an - /// empty UARTn THR and is cleared on a UnTHR write. - THRE: u1, - /// Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is - /// cleared when either the UnTSR or the UnTHR contain valid data. - TEMT: u1, - /// Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as - /// framing error, parity error or break interrupt, is loaded into the UnRBR. This - /// bit is cleared when the UnLSR register is read and there are no subsequent - /// errors in the UARTn FIFO. - RXFE: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x14); - - /// address: 0x4009c01c - /// Scratch Pad Register. 8-bit temporary storage for software. - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - /// A readable, writable byte. - PAD: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x1c); - - /// address: 0x4009c020 - /// Auto-baud Control Register. Contains controls for the auto-baud feature. - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit. This bit is automatically cleared after auto-baud completion. - START: u1, - /// Auto-baud mode select bit. - MODE: u1, - /// Restart bit. - AUTORESTART: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABEOINTCLR: u1, - /// Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will - /// clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. - ABTOINTCLR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x20); - - /// address: 0x4009c028 - /// Fractional Divider Register. Generates a clock input for the baud rate divider. - pub const FDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Baud-rate generation pre-scaler divisor value. If this field is 0, fractional - /// baud-rate generator will not impact the UARTn baudrate. - DIVADDVAL: u4, - /// Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for - /// UARTn to operate properly, regardless of whether the fractional baud-rate - /// generator is used or not. - MULVAL: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x4009c030 - /// Transmit Enable Register. Turns off UART transmitter for use with software flow - /// control. - pub const TER = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u7, - /// When this bit is 1, as it is after a Reset, data written to the THR is output on - /// the TXD pin as soon as any preceding data has been sent. If this bit is cleared - /// to 0 while a character is being sent, the transmission of that character is - /// completed, but no further characters are sent until this bit is set again. In - /// other words, a 0 in this bit blocks the transfer of characters from the THR or - /// TX FIFO into the transmit shift register. Software implementing - /// software-handshaking can clear this bit when it receives an XOFF character - /// (DC3). Software can set this bit again when it receives an XON (DC1) character. - TXEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x30); - - /// address: 0x4009c04c - /// RS-485/EIA-485 Control. Contains controls to configure various aspects of - /// RS-485/EIA-485 modes. - pub const RS485CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// NMM enable. - NMMEN: u1, - /// Receiver enable. - RXDIS: u1, - /// AAD enable. - AADEN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Direction control enable. - DCTRL: u1, - /// Direction control pin polarity. This bit reverses the polarity of the direction - /// control signal on the Un_OE pin. - OINV: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x4c); - - /// address: 0x4009c050 - /// RS-485/EIA-485 address match. Contains the address match value for - /// RS-485/EIA-485 mode. - pub const RS485ADRMATCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the address match value. - ADRMATCH: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x50); - - /// address: 0x4009c054 - /// RS-485/EIA-485 direction control delay. - pub const RS485DLY = @intToPtr(*volatile Mmio(32, packed struct { - /// Contains the direction control (UnOE) delay value. This register works in - /// conjunction with an 8-bit counter. - DLY: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x54); - }; - pub const I2C2 = struct { - pub const base_address = 0x400a0000; - - /// address: 0x400a0000 - /// I2C Control Set Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is set. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge flag. - AA: u1, - /// I2C interrupt flag. - SI: u1, - /// STOP flag. - STO: u1, - /// START flag. - STA: u1, - /// I2C interface enable. - I2EN: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u25, - }), base_address + 0x0); - - /// address: 0x400a0004 - /// I2C Status Register. During I2C operation, this register provides detailed - /// status codes that allow software to determine the next action needed. - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// These bits are unused and are always 0. - RESERVED: u3, - /// These bits give the actual status information about the I 2C interface. - Status: u5, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x400a0008 - /// I2C Data Register. During master or slave transmit mode, data to be transmitted - /// is written to this register. During master or slave receive mode, data that has - /// been received may be read from this register. - pub const DAT = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds data values that have been received or are to be - /// transmitted. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x400a000c - /// I2C Slave Address Register 0. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x400a0010 - /// SCH Duty Cycle Register High Half Word. Determines the high time of the I2C - /// clock. - pub const SCLH = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL HIGH time period selection. - SCLH: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x10); - - /// address: 0x400a0014 - /// SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. - /// SCLL and SCLH together determine the clock frequency generated by an I2C master - /// and certain times used in slave mode. - pub const SCLL = @intToPtr(*volatile Mmio(32, packed struct { - /// Count for SCL low time period selection. - SCLL: u16, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x14); - - /// address: 0x400a0018 - /// I2C Control Clear Register. When a one is written to a bit of this register, the - /// corresponding bit in the I2C control register is cleared. Writing a zero has no - /// effect on the corresponding bit in the I2C control register. - pub const CONCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u2, - /// Assert acknowledge Clear bit. - AAC: u1, - /// I2C interrupt Clear bit. - SIC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// START flag Clear bit. - STAC: u1, - /// I2C interface Disable bit. - I2ENC: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x400a001c - /// Monitor mode control register. - pub const MMCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Monitor mode enable. - MM_ENA: u1, - /// SCL output enable. - ENA_SCL: u1, - /// Select interrupt register match. - MATCH_ALL: u1, - /// Reserved. The value read from reserved bits is not defined. - RESERVED: u29, - }), base_address + 0x1c); - - /// address: 0x400a0020 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x20); - - /// address: 0x400a0024 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x24); - - /// address: 0x400a0028 - /// I2C Slave Address Register. Contains the 7-bit slave address for operation of - /// the I2C interface in slave mode, and is not used in master mode. The least - /// significant bit determines whether a slave responds to the General Call address. - pub const ADR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// General Call enable bit. - GC: u1, - /// The I2C device address for slave mode. - Address: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x28); - - /// address: 0x400a002c - /// Data buffer register. The contents of the 8 MSBs of the DAT shift register will - /// be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of - /// data plus ACK or NACK) has been received on the bus. - pub const DATA_BUFFER = @intToPtr(*volatile Mmio(32, packed struct { - /// This register holds contents of the 8 MSBs of the DAT shift register. - Data: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x2c); - - /// address: 0x400a0030 - /// I2C Slave address mask register - pub const MASK = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. This bit reads - /// always back as 0. - RESERVED: u1, - /// Mask bits. - MASK: u7, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x30); - }; - /// I2S interface - pub const I2S = struct { - pub const base_address = 0x400a8000; - - /// address: 0x400a8000 - /// I2S Digital Audio Output Register. Contains control bits for the I2S transmit - /// channel. - pub const DAO = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the number of bytes in data as follows: - WORDWIDTH: u2, - /// When 1, data is of monaural format. When 0, the data is in stereo format. - MONO: u1, - /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - STOP: u1, - /// When 1, asynchronously resets the transmit channel and FIFO. - RESET: u1, - /// When 0, the interface is in master mode. When 1, the interface is in slave mode. - /// See Section 34.7.2 for a summary of useful combinations for this bit with - /// TXMODE. - WS_SEL: u1, - /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - WS_HALFPERIOD: u9, - /// When 1, the transmit channel sends only zeroes. - MUTE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x0); - - /// address: 0x400a8004 - /// I2S Digital Audio Input Register. Contains control bits for the I2S receive - /// channel. - pub const DAI = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the number of bytes in data as follows: - WORDWIDTH: u2, - /// When 1, data is of monaural format. When 0, the data is in stereo format. - MONO: u1, - /// When 1, disables accesses on FIFOs, places the transmit channel in mute mode. - STOP: u1, - /// When 1, asynchronously reset the transmit channel and FIFO. - RESET: u1, - /// When 0, the interface is in master mode. When 1, the interface is in slave mode. - /// See Section 34.7.2 for a summary of useful combinations for this bit with - /// RXMODE. - WS_SEL: u1, - /// Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. - WS_HALFPERIOD: u9, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u17, - }), base_address + 0x4); - - /// address: 0x400a8008 - /// I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. - pub const TXFIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// 8 x 32-bit transmit FIFO. - I2STXFIFO: u32, - }), base_address + 0x8); - - /// address: 0x400a800c - /// I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. - pub const RXFIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// 8 x 32-bit transmit FIFO. - I2SRXFIFO: u32, - }), base_address + 0xc); - - /// address: 0x400a8010 - /// I2S Status Feedback Register. Contains status information about the I2S - /// interface. - pub const STATE = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This - /// is determined by comparing the current FIFO levels to the rx_depth_irq and - /// tx_depth_irq fields in the IRQ register. - IRQ: u1, - /// This bit reflects the presence of Receive or Transmit DMA Request 1. This is - /// determined by comparing the current FIFO levels to the rx_depth_dma1 and - /// tx_depth_dma1 fields in the DMA1 register. - DMAREQ1: u1, - /// This bit reflects the presence of Receive or Transmit DMA Request 2. This is - /// determined by comparing the current FIFO levels to the rx_depth_dma2 and - /// tx_depth_dma2 fields in the DMA2 register. - DMAREQ2: u1, - /// Reserved. - RESERVED: u5, - /// Reflects the current level of the Receive FIFO. - RX_LEVEL: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u4, - /// Reflects the current level of the Transmit FIFO. - TX_LEVEL: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u12, - }), base_address + 0x10); - - /// address: 0x400a8014 - /// I2S DMA Configuration Register 1. Contains control information for DMA request - /// 1. - pub const DMA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, enables DMA1 for I2S receive. - RX_DMA1_ENABLE: u1, - /// When 1, enables DMA1 for I2S transmit. - TX_DMA1_ENABLE: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u6, - /// Set the FIFO level that triggers a receive DMA request on DMA1. - RX_DEPTH_DMA1: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u4, - /// Set the FIFO level that triggers a transmit DMA request on DMA1. - TX_DEPTH_DMA1: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u12, - }), base_address + 0x14); - - /// address: 0x400a8018 - /// I2S DMA Configuration Register 2. Contains control information for DMA request - /// 2. - pub const DMA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, enables DMA1 for I2S receive. - RX_DMA2_ENABLE: u1, - /// When 1, enables DMA1 for I2S transmit. - TX_DMA2_ENABLE: u1, - /// Reserved. - RESERVED: u6, - /// Set the FIFO level that triggers a receive DMA request on DMA2. - RX_DEPTH_DMA2: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u4, - /// Set the FIFO level that triggers a transmit DMA request on DMA2. - TX_DEPTH_DMA2: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u12, - }), base_address + 0x18); - - /// address: 0x400a801c - /// I2S Interrupt Request Control Register. Contains bits that control how the I2S - /// interrupt request is generated. - pub const IRQ = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, enables I2S receive interrupt. - RX_IRQ_ENABLE: u1, - /// When 1, enables I2S transmit interrupt. - TX_IRQ_ENABLE: u1, - /// Reserved. - RESERVED: u6, - /// Set the FIFO level on which to create an irq request. - RX_DEPTH_IRQ: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u4, - /// Set the FIFO level on which to create an irq request. - TX_DEPTH_IRQ: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u12, - }), base_address + 0x1c); - - /// address: 0x400a8020 - /// I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by - /// specifying the value to divide PCLK by in order to produce MCLK. - pub const TXRATE = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce - /// the transmit MCLK. Eight bits of fractional divide supports a wide range of - /// possibilities. A value of 0 stops the clock. - Y_DIVIDER: u8, - /// I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to - /// produce the transmit MCLK. A value of 0 stops the clock. Eight bits of - /// fractional divide supports a wide range of possibilities. Note: the resulting - /// ratio X/Y is divided by 2. - X_DIVIDER: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x20); - - /// address: 0x400a8024 - /// I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by - /// specifying the value to divide PCLK by in order to produce MCLK. - pub const RXRATE = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S receive MCLK rate denominator. This value is used to divide PCLK to produce - /// the receive MCLK. Eight bits of fractional divide supports a wide range of - /// possibilities. A value of 0 stops the clock. - Y_DIVIDER: u8, - /// I2S receive MCLK rate numerator. This value is used to multiply PCLK by to - /// produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional - /// divide supports a wide range of possibilities. Note: the resulting ratio X/Y is - /// divided by 2. - X_DIVIDER: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u16, - }), base_address + 0x24); - - /// address: 0x400a8028 - /// I2S Transmit bit rate divider. This register determines the I2S transmit bit - /// rate by specifying the value to divide TX_MCLK by in order to produce the - /// transmit bit clock. - pub const TXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce - /// the transmit bit clock. - TX_BITRATE: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x28); - - /// address: 0x400a802c - /// I2S Receive bit rate divider. This register determines the I2S receive bit rate - /// by specifying the value to divide RX_MCLK by in order to produce the receive bit - /// clock. - pub const RXBITRATE = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce - /// the receive bit clock. - RX_BITRATE: u6, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u26, - }), base_address + 0x2c); - - /// address: 0x400a8030 - /// I2S Transmit mode control. - pub const TXMODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock source selection for the transmit bit clock divider. - TXCLKSEL: u2, - /// Transmit 4-pin mode selection. When 1, enables 4-pin mode. - TX4PIN: u1, - /// Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, - /// output of TX_MCLK is enabled. - TXMCENA: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x30); - - /// address: 0x400a8034 - /// I2S Receive mode control. - pub const RXMODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock source selection for the receive bit clock divider. - RXCLKSEL: u2, - /// Receive 4-pin mode selection. When 1, enables 4-pin mode. - RX4PIN: u1, - /// Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, - /// output of RX_MCLK is enabled. - RXMCENA: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x34); - }; - /// Repetitive Interrupt Timer (RIT) - pub const RITIMER = struct { - pub const base_address = 0x400b0000; - - /// address: 0x400b0000 - /// Compare register - pub const COMPVAL = @intToPtr(*volatile Mmio(32, packed struct { - /// Compare register. Holds the compare value which is compared to the counter. - RICOMP: u32, - }), base_address + 0x0); - - /// address: 0x400b0004 - /// Mask register. This register holds the 32-bit mask value. A 1 written to any bit - /// will force a compare on the corresponding bit of the counter and compare - /// register. - pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { - /// Mask register. This register holds the 32-bit mask value. A one written to any - /// bit overrides the result of the comparison for the corresponding bit of the - /// counter and compare register (causes the comparison of the register bits to be - /// always true). - RIMASK: u32, - }), base_address + 0x4); - - /// address: 0x400b0008 - /// Control register. - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt flag - RITINT: u1, - /// Timer enable clear - RITENCLR: u1, - /// Timer enable for debug - RITENBR: u1, - /// Timer enable. - RITEN: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x8); - - /// address: 0x400b000c - /// 32-bit counter - pub const COUNTER = @intToPtr(*volatile Mmio(32, packed struct { - /// 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is - /// cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can - /// be loaded to any value in software. - RICOUNTER: u32, - }), base_address + 0xc); - }; - /// Motor Control PWM - pub const MCPWM = struct { - pub const base_address = 0x400b8000; - - /// address: 0x400b8000 - /// PWM Control read address - pub const CON = @intToPtr(*volatile Mmio(32, packed struct { - /// Stops/starts timer channel 0. - RUN0: u1, - /// Edge/center aligned operation for channel 0. - CENTER0: u1, - /// Selects polarity of the MCOA0 and MCOB0 pins. - POLA0: u1, - /// Controls the dead-time feature for channel 0. - DTE0: u1, - /// Enable/disable updates of functional registers for channel 0 (see Section - /// 24.8.2). - DISUP0: u1, - /// Reserved. - RESERVED: u3, - /// Stops/starts timer channel 1. - RUN1: u1, - /// Edge/center aligned operation for channel 1. - CENTER1: u1, - /// Selects polarity of the MCOA1 and MCOB1 pins. - POLA1: u1, - /// Controls the dead-time feature for channel 1. - DTE1: u1, - /// Enable/disable updates of functional registers for channel 1 (see Section - /// 24.8.2). - DISUP1: u1, - /// Reserved. - RESERVED: u3, - /// Stops/starts timer channel 2. - RUN2: u1, - /// Edge/center aligned operation for channel 2. - CENTER2: u1, - /// Selects polarity of the MCOA2 and MCOB2 pins. - POLA2: u1, - /// Controls the dead-time feature for channel 1. - DTE2: u1, - /// Enable/disable updates of functional registers for channel 2 (see Section - /// 24.8.2). - DISUP2: u1, - /// Reserved. - RESERVED: u8, - /// Controls the polarity of the MCOB outputs for all 3 channels. This bit is - /// typically set to 1 only in 3-phase DC mode. - INVBDC: u1, - /// 3-phase AC mode select (see Section 24.8.7). - ACMODE: u1, - /// 3-phase DC mode select (see Section 24.8.6). - DCMODE: u1, - }), base_address + 0x0); - - /// address: 0x400b8004 - /// PWM Control set address - pub const CON_SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one sets the corresponding bit in the CON register. - RUN0_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - CENTER0_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - POLA0_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DTE0_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DISUP0_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - RESERVED: u3, - /// Writing a one sets the corresponding bit in the CON register. - RUN1_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - CENTER1_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - POLA1_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DTE1_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DISUP1_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - RESERVED: u3, - /// Writing a one sets the corresponding bit in the CON register. - RUN2_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - CENTER2_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - POLA2_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DTE2_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DISUP2_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - RESERVED: u8, - /// Writing a one sets the corresponding bit in the CON register. - INVBDC_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - ACMODE_SET: u1, - /// Writing a one sets the corresponding bit in the CON register. - DCMODE_SET: u1, - }), base_address + 0x4); - - /// address: 0x400b8008 - /// PWM Control clear address - pub const CON_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one clears the corresponding bit in the CON register. - RUN0_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - CENTER0_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - POLA0_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DTE0_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DISUP0_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - RESERVED: u3, - /// Writing a one clears the corresponding bit in the CON register. - RUN1_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - CENTER1_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - POLA1_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DTE1_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DISUP1_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - RESERVED: u3, - /// Writing a one clears the corresponding bit in the CON register. - RUN2_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - CENTER2_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - POLA2_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DTE2_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DISUP2_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - RESERVED: u8, - /// Writing a one clears the corresponding bit in the CON register. - INVBDC_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - ACMOD_CLR: u1, - /// Writing a one clears the corresponding bit in the CON register. - DCMODE_CLR: u1, - }), base_address + 0x8); - - /// address: 0x400b800c - /// Capture Control read address - pub const CAPCON = @intToPtr(*volatile Mmio(32, packed struct { - /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. - CAP0MCI0_RE: u1, - /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. - CAP0MCI0_FE: u1, - /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. - CAP0MCI1_RE: u1, - /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. - CAP0MCI1_FE: u1, - /// A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. - CAP0MCI2_RE: u1, - /// A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. - CAP0MCI2_FE: u1, - /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. - CAP1MCI0_RE: u1, - /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. - CAP1MCI0_FE: u1, - /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. - CAP1MCI1_RE: u1, - /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. - CAP1MCI1_FE: u1, - /// A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. - CAP1MCI2_RE: u1, - /// A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. - CAP1MCI2_FE: u1, - /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. - CAP2MCI0_RE: u1, - /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. - CAP2MCI0_FE: u1, - /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. - CAP2MCI1_RE: u1, - /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. - CAP2MCI1_FE: u1, - /// A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. - CAP2MCI2_RE: u1, - /// A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. - CAP2MCI2_FE: u1, - /// If this bit is 1, TC0 is reset by a channel 0 capture event. - RT0: u1, - /// If this bit is 1, TC1 is reset by a channel 1 capture event. - RT1: u1, - /// If this bit is 1, TC2 is reset by a channel 2 capture event. - RT2: u1, - /// Reserved. - RESERVED: u11, - }), base_address + 0xc); - - /// address: 0x400b8010 - /// Capture Control set address - pub const CAPCON_SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP0MCI2_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP1MCI2_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - CAP2MCI2_FE_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - RT0_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - RT1_SET: u1, - /// Writing a one sets the corresponding bits in the CAPCON register. - RT2_SET: u1, - /// Reserved. - RESERVED: u11, - }), base_address + 0x10); - - /// address: 0x400b8014 - /// Event Control clear address - pub const CAPCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP0MCI2_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP1MCI2_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_RE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - CAP2MCI2_FE_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - RT0_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - RT1_CLR: u1, - /// Writing a one clears the corresponding bits in the CAPCON register. - RT2_CLR: u1, - /// Reserved. - RESERVED: u11, - }), base_address + 0x14); - - /// address: 0x400b8018 - /// Timer Counter register - pub const TC = @intToPtr(*volatile [3]Mmio(32, packed struct { - /// Timer/Counter value. - MCTC: u32, - }), base_address + 0x18); - - /// address: 0x400b8024 - /// Limit register - pub const LIM = @intToPtr(*volatile [3]Mmio(32, packed struct { - /// Limit value. - MCLIM: u32, - }), base_address + 0x24); - - /// address: 0x400b8030 - /// Match register - pub const MAT = @intToPtr(*volatile [3]Mmio(32, packed struct { - /// Match value. - MCMAT: u32, - }), base_address + 0x30); - - /// address: 0x400b803c - /// Dead time register - pub const DT = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead time for channel 0.[1] - DT0: u10, - /// Dead time for channel 1.[2] - DT1: u10, - /// Dead time for channel 2.[2] - DT2: u10, - /// reserved - RESERVED: u2, - }), base_address + 0x3c); - - /// address: 0x400b8040 - /// Communication Pattern register - pub const CP = @intToPtr(*volatile Mmio(32, packed struct { - /// Communication pattern output A, channel 0. - CCPA0: u1, - /// Communication pattern output B, channel 0. - CCPB0: u1, - /// Communication pattern output A, channel 1. - CCPA1: u1, - /// Communication pattern output B, channel 1. - CCPB1: u1, - /// Communication pattern output A, channel 2. - CCPA2: u1, - /// Communication pattern output B, channel 2. - CCPB2: u1, - /// Reserved. - RESERVED: u26, - }), base_address + 0x40); - - /// address: 0x400b8044 - /// Capture register - pub const CAP = @intToPtr(*volatile [3]u32, base_address + 0x44); - - /// address: 0x400b8050 - /// Interrupt Enable read address - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Limit interrupt for channel 0. - ILIM0: u1, - /// Match interrupt for channel 0. - IMAT0: u1, - /// Capture interrupt for channel 0. - ICAP0: u1, - /// Reserved. - RESERVED: u1, - /// Limit interrupt for channel 1. - ILIM1: u1, - /// Match interrupt for channel 1. - IMAT1: u1, - /// Capture interrupt for channel 1. - ICAP1: u1, - /// Reserved. - RESERVED: u1, - /// Limit interrupt for channel 2. - ILIM2: u1, - /// Match interrupt for channel 2. - IMAT2: u1, - /// Capture interrupt for channel 2. - ICAP2: u1, - /// Reserved. - RESERVED: u4, - /// Fast abort interrupt. - ABORT: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x50); - - /// address: 0x400b8054 - /// Interrupt Enable set address - pub const INTEN_SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ILIM0_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT0_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP0_SET: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ILIM1_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT1_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP1_SET: u1, - /// Reserved. - RESERVED: u1, - reserved0: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ILIM2_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - IMAT2_SET: u1, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ICAP2_SET: u1, - /// Reserved. - RESERVED: u3, - /// Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. - ABORT_SET: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x54); - - /// address: 0x400b8058 - /// Interrupt Enable clear address - pub const INTEN_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ILIM0_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT0_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP0_CLR: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ILIM1_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT1_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP1_CLR: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ILIM2_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT2_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP2_CLR: u1, - /// Reserved. - RESERVED: u4, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ABORT_CLR: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x58); - - /// address: 0x400b8068 - /// Interrupt flags read address - pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { - /// Limit interrupt flag for channel 0. - ILIM0_F: u1, - /// Match interrupt flag for channel 0. - IMAT0_F: u1, - /// Capture interrupt flag for channel 0. - ICAP0_F: u1, - /// Reserved. - RESERVED: u1, - /// Limit interrupt flag for channel 1. - ILIM1_F: u1, - /// Match interrupt flag for channel 1. - IMAT1_F: u1, - /// Capture interrupt flag for channel 1. - ICAP1_F: u1, - /// Reserved. - RESERVED: u1, - /// Limit interrupt flag for channel 2. - ILIM2_F: u1, - /// Match interrupt flag for channel 2. - IMAT2_F: u1, - /// Capture interrupt flag for channel 2. - ICAP2_F: u1, - /// Reserved. - RESERVED: u4, - /// Fast abort interrupt flag. - ABORT_F: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x68); - - /// address: 0x400b806c - /// Interrupt flags set address - pub const INTF_SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ILIM0_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - IMAT0_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ICAP0_F_SET: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ILIM1_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - IMAT1_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ICAP1_F_SET: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ILIM2_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - IMAT2_F_SET: u1, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ICAP2_F_SET: u1, - /// Reserved. - RESERVED: u4, - /// Writing a one sets the corresponding bit in the INTF register, thus possibly - /// simulating hardware interrupt. - ABORT_F_SET: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x6c); - - /// address: 0x400b8070 - /// Interrupt flags clear address - pub const INTF_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one clears the corresponding bit in the INTF register, thus clearing - /// the corresponding interrupt request. - ILIM0_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT0_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP0_F_CLR: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ILIM1_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT1_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP1_F_CLR: u1, - /// Reserved. - RESERVED: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ILIM2_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - IMAT2_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ICAP2_F_CLR: u1, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - RESERVED: u4, - /// Writing a one clears the corresponding bit in INTEN, thus disabling the - /// interrupt. - ABORT_F_CLR: u1, - /// Reserved. - RESERVED: u16, - }), base_address + 0x70); - - /// address: 0x400b805c - /// Count Control read address - pub const CNTCON = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter 0 rising edge mode, channel 0. - TC0MCI0_RE: u1, - /// Counter 0 falling edge mode, channel 0. - TC0MCI0_FE: u1, - /// Counter 0 rising edge mode, channel 1. - TC0MCI1_RE: u1, - /// Counter 0 falling edge mode, channel 1. - TC0MCI1_FE: u1, - /// Counter 0 rising edge mode, channel 2. - TC0MCI2_RE: u1, - /// Counter 0 falling edge mode, channel 2. - TC0MCI2_FE: u1, - /// Counter 1 rising edge mode, channel 0. - TC1MCI0_RE: u1, - /// Counter 1 falling edge mode, channel 0. - TC1MCI0_FE: u1, - /// Counter 1 rising edge mode, channel 1. - TC1MCI1_RE: u1, - /// Counter 1 falling edge mode, channel 1. - TC1MCI1_FE: u1, - /// Counter 1 rising edge mode, channel 2. - TC1MCI2_RE: u1, - /// Counter 1 falling edge mode, channel 2. - TC1MCI2_FE: u1, - /// Counter 2 rising edge mode, channel 0. - TC2MCI0_RE: u1, - /// Counter 2 falling edge mode, channel 0. - TC2MCI0_FE: u1, - /// Counter 2 rising edge mode, channel 1. - TC2MCI1_RE: u1, - /// Counter 2 falling edge mode, channel 1. - TC2MCI1_FE: u1, - /// Counter 2 rising edge mode, channel 2. - TC2MCI2_RE: u1, - /// Counter 2 falling edge mode, channel 2. - TC2MCI2_FE: u1, - /// Reserved. - RESERVED: u11, - /// Channel 0 counter/timer mode. - CNTR0: u1, - /// Channel 1 counter/timer mode. - CNTR1: u1, - /// Channel 2 counter/timer mode. - CNTR2: u1, - }), base_address + 0x5c); - - /// address: 0x400b8060 - /// Count Control set address - pub const CNTCON_SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC0MCI2_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC1MCI2_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI0_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI1_FE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_RE_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - TC2MCI2_FE_SET: u1, - /// Reserved. - RESERVED: u11, - /// Writing a one sets the corresponding bit in the CNTCON register. - CNTR0_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - CNTR1_SET: u1, - /// Writing a one sets the corresponding bit in the CNTCON register. - CNTR2_SET: u1, - }), base_address + 0x60); - - /// address: 0x400b8064 - /// Count Control clear address - pub const CNTCON_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_RE: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC0MCI2_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC1MCI2_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI0_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI1_FE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_RE_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - TC2MCI2_FE_CLR: u1, - /// Reserved. - RESERVED: u11, - /// Writing a one clears the corresponding bit in the CNTCON register. - CNTR0_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - CNTR1_CLR: u1, - /// Writing a one clears the corresponding bit in the CNTCON register. - CNTR2_CLR: u1, - }), base_address + 0x64); - - /// address: 0x400b8074 - /// Capture clear address - pub const CAP_CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 to this bit clears the CAP0 register. - CAP_CLR0: u1, - /// Writing a 1 to this bit clears the CAP1 register. - CAP_CLR1: u1, - /// Writing a 1 to this bit clears the CAP2 register. - CAP_CLR2: u1, - /// Reserved - RESERVED: u29, - }), base_address + 0x74); - }; - /// Quadrature Encoder Interface (QEI) - pub const QEI = struct { - pub const base_address = 0x400bc000; - - /// address: 0x400bc000 - /// Control register - pub const CON = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset position counter. When set = 1, resets the position counter to all zeros. - /// Autoclears when the position counter is cleared. - RESP: u1, - /// Reset position counter on index. When set = 1, resets the position counter to - /// all zeros once only the first time an index pulse occurs. Autoclears when the - /// position counter is cleared. - RESPI: u1, - /// Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads - /// the velocity timer, and presets the velocity compare register. Autoclears when - /// the velocity counter is cleared. - RESV: u1, - /// Reset index counter. When set = 1, resets the index counter to all zeros. - /// Autoclears when the index counter is cleared. - RESI: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x0); - - /// address: 0x400bc008 - /// Configuration register - pub const CONF = @intToPtr(*volatile Mmio(32, packed struct { - /// Direction invert. When 1, complements the DIR bit. - DIRINV: u1, - /// Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, - /// PhA functions as the direction signal and PhB functions as the clock signal. - SIGMODE: u1, - /// Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB - /// edges are counted (4X), increasing resolution but decreasing range. - CAPMODE: u1, - /// Invert Index. When 1, inverts the sense of the index input. - INVINX: u1, - /// Continuously reset the position counter on index. When 1, resets the position - /// counter to all zeros whenever an index pulse occurs after the next position - /// increase (recalibration). - CRESPI: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u11, - /// Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 - /// and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when - /// PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index - /// when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the - /// index when PHA = 0 and PHB = 0, otherwise block index. - INXGATE: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u12, - }), base_address + 0x8); - - /// address: 0x400bc004 - /// Status register - pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Direction bit. In combination with DIRINV bit indicates forward or reverse - /// direction. See Table 597. - DIR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u31, - }), base_address + 0x4); - - /// address: 0x400bc00c - /// Position register - pub const POS = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x400bc010 - /// Maximum position register - pub const MAXPOS = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x400bc014 - /// Position compare register 0 - pub const CMPOS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Position compare value 0. - PCMP0: u32, - }), base_address + 0x14); - - /// address: 0x400bc018 - /// Position compare register 1 - pub const CMPOS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Position compare value 1. - PCMP1: u32, - }), base_address + 0x18); - - /// address: 0x400bc01c - /// Position compare register 2 - pub const CMPOS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Position compare value 2. - PCMP2: u32, - }), base_address + 0x1c); - - /// address: 0x400bc020 - /// Index count register 0 - pub const INXCNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Current index counter value. - ENCPOS: u32, - }), base_address + 0x20); - - /// address: 0x400bc024 - /// Index compare register 0 - pub const INXCMP0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Index compare value 0. - ICMP0: u32, - }), base_address + 0x24); - - /// address: 0x400bc028 - /// Velocity timer reload register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - /// Current velocity timer load value. - VELLOAD: u32, - }), base_address + 0x28); - - /// address: 0x400bc02c - /// Velocity timer register - pub const TIME = @intToPtr(*volatile Mmio(32, packed struct { - /// Current velocity timer value. - VELVAL: u32, - }), base_address + 0x2c); - - /// address: 0x400bc030 - /// Velocity counter register - pub const VEL = @intToPtr(*volatile Mmio(32, packed struct { - /// Current velocity pulse count. - VELPC: u32, - }), base_address + 0x30); - - /// address: 0x400bc034 - /// Velocity capture register - pub const CAP = @intToPtr(*volatile Mmio(32, packed struct { - /// Last velocity capture. - VELCAP: u32, - }), base_address + 0x34); - - /// address: 0x400bc038 - /// Velocity compare register - pub const VELCOMP = @intToPtr(*volatile Mmio(32, packed struct { - /// Compare velocity pulse count. - VELPC: u32, - }), base_address + 0x38); - - /// address: 0x400bc03c - /// Digital filter register - pub const FILTER = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital filter sampling delay. - FILTA: u32, - }), base_address + 0x3c); - - /// address: 0x400bcfe0 - /// Interrupt status register - pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Indicates that an index pulse was detected. - INX_INT: u1, - /// Indicates that a velocity timer overflow occurred - TIM_INT: u1, - /// Indicates that captured velocity is less than compare velocity. - VELC_INT: u1, - /// Indicates that a change of direction was detected. - DIR_INT: u1, - /// Indicates that an encoder phase error was detected. - ERR_INT: u1, - /// Indicates that and encoder clock pulse was detected. - ENCLK_INT: u1, - /// Indicates that the position 0 compare value is equal to the current position. - POS0_INT: u1, - /// Indicates that the position 1compare value is equal to the current position. - POS1_INT: u1, - /// Indicates that the position 2 compare value is equal to the current position. - POS2_INT: u1, - /// Indicates that the index compare 0 value is equal to the current index count. - REV0_INT: u1, - /// Combined position 0 and revolution count interrupt. Set when both the POS0_Int - /// bit is set and the REV0_Int is set. - POS0REV_INT: u1, - /// Combined position 1 and revolution count interrupt. Set when both the POS1_Int - /// bit is set and the REV1_Int is set. - POS1REV_INT: u1, - /// Combined position 2 and revolution count interrupt. Set when both the POS2_Int - /// bit is set and the REV2_Int is set. - POS2REV_INT: u1, - /// Indicates that the index compare 1value is equal to the current index count. - REV1_INT: u1, - /// Indicates that the index compare 2 value is equal to the current index count. - REV2_INT: u1, - /// Indicates that the current position count goes through the MAXPOS value to zero - /// in the forward direction, or through zero to MAXPOS in the reverse direction. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfe0); - - /// address: 0x400bcfec - /// Interrupt status set register - pub const SET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 sets the INX_Int bit in QEIINTSTAT. - INX_INT: u1, - /// Writing a 1 sets the TIN_Int bit in QEIINTSTAT. - TIM_INT: u1, - /// Writing a 1 sets the VELC_Int bit in QEIINTSTAT. - VELC_INT: u1, - /// Writing a 1 sets the DIR_Int bit in QEIINTSTAT. - DIR_INT: u1, - /// Writing a 1 sets the ERR_Int bit in QEIINTSTAT. - ERR_INT: u1, - /// Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. - ENCLK_INT: u1, - /// Writing a 1 sets the POS0_Int bit in QEIINTSTAT. - POS0_INT: u1, - /// Writing a 1 sets the POS1_Int bit in QEIINTSTAT. - POS1_INT: u1, - /// Writing a 1 sets the POS2_Int bit in QEIINTSTAT. - POS2_INT: u1, - /// Writing a 1 sets the REV0_Int bit in QEIINTSTAT. - REV0_INT: u1, - /// Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. - POS0REV_INT: u1, - /// Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, - /// Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, - /// Writing a 1 sets the REV1_Int bit in QEIINTSTAT. - REV1_INT: u1, - /// Writing a 1 sets the REV2_Int bit in QEIINTSTAT. - REV2_INT: u1, - /// Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfec); - - /// address: 0x400bcfe8 - /// Interrupt status clear register - pub const CLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 clears the INX_Int bit in QEIINTSTAT. - INX_INT: u1, - /// Writing a 1 clears the TIN_Int bit in QEIINTSTAT. - TIM_INT: u1, - /// Writing a 1 clears the VELC_Int bit in QEIINTSTAT. - VELC_INT: u1, - /// Writing a 1 clears the DIR_Int bit in QEIINTSTAT. - DIR_INT: u1, - /// Writing a 1 clears the ERR_Int bit in QEIINTSTAT. - ERR_INT: u1, - /// Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. - ENCLK_INT: u1, - /// Writing a 1 clears the POS0_Int bit in QEIINTSTAT. - POS0_INT: u1, - /// Writing a 1 clears the POS1_Int bit in QEIINTSTAT. - POS1_INT: u1, - /// Writing a 1 clears the POS2_Int bit in QEIINTSTAT. - POS2_INT: u1, - /// Writing a 1 clears the REV0_Int bit in QEIINTSTAT. - REV0_INT: u1, - /// Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. - POS0REV_INT: u1, - /// Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. - POS1REV_INT: u1, - /// Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. - POS2REV_INT: u1, - /// Writing a 1 clears the REV1_Int bit in QEIINTSTAT. - REV1_INT: u1, - /// Writing a 1 clears the REV2_Int bit in QEIINTSTAT. - REV2_INT: u1, - /// Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfe8); - - /// address: 0x400bcfe4 - /// Interrupt enable register - pub const IE = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1, the INX_Int interrupt is enabled. - INX_INT: u1, - /// When 1, the TIN_Int interrupt is enabled. - TIM_INT: u1, - /// When 1, the VELC_Int interrupt is enabled. - VELC_INT: u1, - /// When 1, the DIR_Int interrupt is enabled. - DIR_INT: u1, - /// When 1, the ERR_Int interrupt is enabled. - ERR_INT: u1, - /// When 1, the ENCLK_Int interrupt is enabled. - ENCLK_INT: u1, - /// When 1, the POS0_Int interrupt is enabled. - POS0_INT: u1, - /// When 1, the POS1_Int interrupt is enabled. - POS1_INT: u1, - /// When 1, the POS2_Int interrupt is enabled. - POS2_INT: u1, - /// When 1, the REV0_Int interrupt is enabled. - REV0_INT: u1, - /// When 1, the POS0REV_Int interrupt is enabled. - POS0REV_INT: u1, - /// When 1, the POS1REV_Int interrupt is enabled. - POS1REV_INT: u1, - /// When 1, the POS2REV_Int interrupt is enabled. - POS2REV_INT: u1, - /// When 1, the REV1_Int interrupt is enabled. - REV1_INT: u1, - /// When 1, the REV2_Int interrupt is enabled. - REV2_INT: u1, - /// When 1, the MAXPOS_Int interrupt is enabled. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfe4); - - /// address: 0x400bcfdc - /// Interrupt enable set register - pub const IES = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 enables the INX_Int interrupt in the QEIIE register. - INX_INT: u1, - /// Writing a 1 enables the TIN_Int interrupt in the QEIIE register. - TIM_INT: u1, - /// Writing a 1 enables the VELC_Int interrupt in the QEIIE register. - VELC_INT: u1, - /// Writing a 1 enables the DIR_Int interrupt in the QEIIE register. - DIR_INT: u1, - /// Writing a 1 enables the ERR_Int interrupt in the QEIIE register. - ERR_INT: u1, - /// Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. - ENCLK_INT: u1, - /// Writing a 1 enables the POS0_Int interrupt in the QEIIE register. - POS0_INT: u1, - /// Writing a 1 enables the POS1_Int interrupt in the QEIIE register. - POS1_INT: u1, - /// Writing a 1 enables the POS2_Int interrupt in the QEIIE register. - POS2_INT: u1, - /// Writing a 1 enables the REV0_Int interrupt in the QEIIE register. - REV0_INT: u1, - /// Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. - POS0REV_INT: u1, - /// Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, - /// Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, - /// Writing a 1 enables the REV1_Int interrupt in the QEIIE register. - REV1_INT: u1, - /// Writing a 1 enables the REV2_Int interrupt in the QEIIE register. - REV2_INT: u1, - /// Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfdc); - - /// address: 0x400bcfd8 - /// Interrupt enable clear register - pub const IEC = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 disables the INX_Int interrupt in the QEIIE register. - INX_INT: u1, - /// Writing a 1 disables the TIN_Int interrupt in the QEIIE register. - TIM_INT: u1, - /// Writing a 1 disables the VELC_Int interrupt in the QEIIE register. - VELC_INT: u1, - /// Writing a 1 disables the DIR_Int interrupt in the QEIIE register. - DIR_INT: u1, - /// Writing a 1 disables the ERR_Int interrupt in the QEIIE register. - ERR_INT: u1, - /// Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. - ENCLK_INT: u1, - /// Writing a 1 disables the POS0_Int interrupt in the QEIIE register. - POS0_INT: u1, - /// Writing a 1 disables the POS1_Int interrupt in the QEIIE register. - POS1_INT: u1, - /// Writing a 1 disables the POS2_Int interrupt in the QEIIE register. - POS2_INT: u1, - /// Writing a 1 disables the REV0_Int interrupt in the QEIIE register. - REV0_INT: u1, - /// Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. - POS0REV_INT: u1, - /// Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. - POS1REV_INT: u1, - /// Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. - POS2REV_INT: u1, - /// Writing a 1 disables the REV1_Int interrupt in the QEIIE register. - REV1_INT: u1, - /// Writing a 1 disables the REV2_Int interrupt in the QEIIE register. - REV2_INT: u1, - /// Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. - MAXPOS_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0xfd8); - }; - /// System and clock control - pub const SYSCON = struct { - pub const base_address = 0x400fc000; - - /// address: 0x400fc000 - /// Flash Accelerator Configuration Register. Controls flash access timing. - pub const FLASHCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, user software should not change these bits from the reset value. - reserved0: u12 = 0, - /// Flash access time. The value of this field plus 1 gives the number of CPU clocks - /// used for a flash access. Warning: improper setting of this value may result in - /// incorrect operation of the device. Other values are reserved. - FLASHTIM: u4, - /// Reserved. The value read from a reserved bit is not defined. - reserved1: u16 = 0, - }), base_address + 0x0); - - /// address: 0x400fc080 - /// PLL0 Control Register - pub const PLL0CON = @intToPtr(*volatile Mmio(32, packed struct { - /// PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 - /// and allow it to lock to the requested frequency. See PLL0STAT register. - PLLE0: u1, - /// PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then - /// followed by a valid PLL0 feed sequence causes PLL0 to become the clock source - /// for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. - /// The PLL0 output may potentially be used to clock the USB subsystem if the - /// frequency is 48 MHz. See PLL0STAT register. - PLLC0: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30 = 0, - }), base_address + 0x80); - - /// address: 0x400fc084 - /// PLL0 Configuration Register - pub const PLL0CFG = @intToPtr(*volatile Mmio(32, packed struct { - /// PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The - /// value stored here is M - 1. Note: Not all values of M are needed, and therefore - /// some are not supported by hardware. - MSEL0: u15, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - reserved0: u1 = 0, - /// PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The - /// value stored here is N - 1. Supported values for N are 1 through 32. - NSEL0: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - reserved1: u8 = 0, - }), base_address + 0x84); - - /// address: 0x400fc088 - /// PLL0 Status Register - pub const PLL0STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Read-back for the PLL0 Multiplier value. This is the value currently used by - /// PLL0, and is one less than the actual multiplier. - MSEL0: u15, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// Read-back for the PLL0 Pre-Divider value. This is the value currently used by - /// PLL0, and is one less than the actual divider. - NSEL0: u8, - /// Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit - /// in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When - /// zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode - /// is entered. - PLLE0_STAT: u1, - /// Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit - /// in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is - /// connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, - /// PLL0 is bypassed. This bit is automatically cleared when Power-down mode is - /// entered. - PLLC0_STAT: u1, - /// Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is - /// locked onto the requested frequency. See text for details. - PLOCK0: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u5, - }), base_address + 0x88); - - /// address: 0x400fc08c - /// PLL0 Feed Register - pub const PLL0FEED = @intToPtr(*volatile Mmio(32, packed struct { - /// The PLL0 feed sequence must be written to this register in order for PLL0 - /// configuration and control register changes to take effect. - PLL0FEED: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - padding22: u1 = 0, - padding23: u1 = 0, - }), base_address + 0x8c); - - /// address: 0x400fc0a0 - /// PLL1 Control Register - pub const PLL1CON = @intToPtr(*volatile Mmio(32, packed struct { - /// PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 - /// and allow it to lock to the requested frequency. - PLLE1: u1, - /// PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then - /// followed by a valid PLL1 feed sequence causes PLL1 to become the clock source - /// for the USB subsystem via the USB clock divider. See PLL1STAT register. - PLLC1: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30, - }), base_address + 0xa0); - - /// address: 0x400fc0a4 - /// PLL1 Configuration Register - pub const PLL1CFG = @intToPtr(*volatile Mmio(32, packed struct { - /// PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations. - MSEL1: u5, - /// PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations. - PSEL1: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u25, - }), base_address + 0xa4); - - /// address: 0x400fc0a8 - /// PLL1 Status Register - pub const PLL1STAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Read-back for the PLL1 Multiplier value. This is the value currently used by - /// PLL1. - MSEL1: u5, - /// Read-back for the PLL1 Divider value. This is the value currently used by PLL1. - PSEL1: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u1, - /// Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When - /// zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode - /// is activated. - PLLE1_STAT: u1, - /// Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is - /// connected as the clock source for the microcontroller. When either PLLC or PLLE - /// is zero, PLL1 is bypassed and the oscillator clock is used directly by the - /// microcontroller. This bit is automatically cleared when Power-down mode is - /// activated. - PLLC1_STAT: u1, - /// Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is - /// locked onto the requested frequency. - PLOCK1: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u21, - }), base_address + 0xa8); - - /// address: 0x400fc0ac - /// PLL1 Feed Register - pub const PLL1FEED = @intToPtr(*volatile Mmio(32, packed struct { - /// The PLL1 feed sequence must be written to this register in order for PLL1 - /// configuration and control register changes to take effect. - PLL1FEED: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xac); - - /// address: 0x400fc0c0 - /// Power Control Register - pub const PCON = @intToPtr(*volatile Mmio(32, packed struct { - /// Power mode control bit 0. This bit controls entry to the Power-down mode. - PM0: u1, - /// Power mode control bit 1. This bit controls entry to the Deep Power-down mode. - PM1: u1, - /// Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry - /// will be turned off when chip Power-down mode or Deep Sleep mode is entered, - /// resulting in a further reduction in power usage. However, the possibility of - /// using Brown-Out Detect as a wake-up source from the reduced power mode will be - /// lost. When 0, the Brown-Out Detect function remains active during Power-down and - /// Deep Sleep modes. See the System Control Block chapter for details of Brown-Out - /// detection. - BODRPM: u1, - /// Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is - /// fully disabled at all times, and does not consume power. When 0, the Brown-Out - /// Detect circuitry is enabled. See the System Control Block chapter for details of - /// Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) - /// and the Brown-Out Interrupt (xx) must be disabled when software changes the - /// value of this bit. - BOGD: u1, - /// Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when - /// the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The - /// Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. - BORD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared - /// by software writing a one to this bit. - SMFLAG: u1, - /// Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. - /// Cleared by software writing a one to this bit. - DSFLAG: u1, - /// Power-down entry flag. Set when the Power-down mode is successfully entered. - /// Cleared by software writing a one to this bit. - PDFLAG: u1, - /// Deep Power-down entry flag. Set when the Deep Power-down mode is successfully - /// entered. Cleared by software writing a one to this bit. - DPDFLAG: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0xc0); - - /// address: 0x400fc0c4 - /// Power Control for Peripherals Register - pub const PCONP = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. - reserved0: u1, - /// Timer/Counter 0 power/clock control bit. - PCTIM0: u1, - /// Timer/Counter 1 power/clock control bit. - PCTIM1: u1, - /// UART0 power/clock control bit. - PCUART0: u1, - /// UART1 power/clock control bit. - PCUART1: u1, - /// Reserved. - reserved1: u1, - /// PWM1 power/clock control bit. - PCPWM1: u1, - /// The I2C0 interface power/clock control bit. - PCI2C0: u1, - /// The SPI interface power/clock control bit. - PCSPI: u1, - /// The RTC power/clock control bit. - PCRTC: u1, - /// The SSP 1 interface power/clock control bit. - PCSSP1: u1, - /// Reserved. - reserved2: u1, - /// A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the - /// AD0CR before clearing this bit, and set this bit before setting PDN. - PCADC: u1, - /// CAN Controller 1 power/clock control bit. - PCCAN1: u1, - /// CAN Controller 2 power/clock control bit. - PCCAN2: u1, - /// Power/clock control bit for IOCON, GPIO, and GPIO interrupts. - PCGPIO: u1, - /// Repetitive Interrupt Timer power/clock control bit. - PCRIT: u1, - /// Motor Control PWM - PCMCPWM: u1, - /// Quadrature Encoder Interface power/clock control bit. - PCQEI: u1, - /// The I2C1 interface power/clock control bit. - PCI2C1: u1, - /// Reserved. - reserved3: u1, - /// The SSP0 interface power/clock control bit. - PCSSP0: u1, - /// Timer 2 power/clock control bit. - PCTIM2: u1, - /// Timer 3 power/clock control bit. - PCTIM3: u1, - /// UART 2 power/clock control bit. - PCUART2: u1, - /// UART 3 power/clock control bit. - PCUART3: u1, - /// I2C interface 2 power/clock control bit. - PCI2C2: u1, - /// I2S interface power/clock control bit. - PCI2S: u1, - /// Reserved. - reserved4: u1, - /// GPDMA function power/clock control bit. - PCGPDMA: u1, - /// Ethernet block power/clock control bit. - PCENET: u1, - /// USB interface power/clock control bit. - PCUSB: u1, - }), base_address + 0xc4); - - /// address: 0x400fc104 - /// CPU Clock Configuration Register - pub const CCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. - /// 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed - /// when the PLL0 is connected, because the rate would always be greater than the - /// maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. - /// This setting is not allowed when the PLL0 is connected, because the rate would - /// always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 - /// to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. - /// ... 255 = pllclk is divided by 256 to produce the CPU clock. - CCLKSEL: u8, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - padding22: u1 = 0, - padding23: u1 = 0, - }), base_address + 0x104); - - /// address: 0x400fc108 - /// USB Clock Configuration Register - pub const USBCLKCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the divide value for creating the USB clock from the PLL0 output. Only - /// the values shown below can produce even number multiples of 48 MHz from the PLL0 - /// output. Warning: Improper setting of this value will result in incorrect - /// operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output - /// must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 - /// = PLL0 output is divided by 10. PLL0 output must be 480 MHz. - USBSEL: u4, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x108); - - /// address: 0x400fc10c - /// Clock Source Select Register - pub const CLKSRCSEL = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the clock source for PLL0 as follows. Warning: Improper setting of this - /// value, or an incorrect sequence of changing this value may result in incorrect - /// operation of the device. - CLKSRC: u2, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u30 = 0, - }), base_address + 0x10c); - - /// address: 0x400fc110 - /// Allows clearing the current CAN channel sleep state as well as reading that - /// state. - pub const CANSLEEPCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN - /// channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored - /// to CAN channel 1. - CAN1SLEEP: u1, - /// Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN - /// channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored - /// to CAN channel 2. - CAN2SLEEP: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u29, - }), base_address + 0x110); - - /// address: 0x400fc114 - /// Allows reading the wake-up state of the CAN channels. - pub const CANWAKEFLAGS = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge - /// has occurred on the receive data line of CAN channel 1. Write: writing a 1 - /// clears this bit. - CAN1WAKE: u1, - /// Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge - /// has occurred on the receive data line of CAN channel 2. Write: writing a 1 - /// clears this bit. - CAN2WAKE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u29, - }), base_address + 0x114); - - /// address: 0x400fc140 - /// External Interrupt Flag Register - pub const EXTINT = @intToPtr(*volatile Mmio(32, packed struct { - /// In level-sensitive mode, this bit is set if the EINT0 function is selected for - /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is - /// set if the EINT0 function is selected for its pin, and the selected edge occurs - /// on the pin. This bit is cleared by writing a one to it, except in level - /// sensitive mode when the pin is in its active state. - EINT0: u1, - /// In level-sensitive mode, this bit is set if the EINT1 function is selected for - /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is - /// set if the EINT1 function is selected for its pin, and the selected edge occurs - /// on the pin. This bit is cleared by writing a one to it, except in level - /// sensitive mode when the pin is in its active state. - EINT1: u1, - /// In level-sensitive mode, this bit is set if the EINT2 function is selected for - /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is - /// set if the EINT2 function is selected for its pin, and the selected edge occurs - /// on the pin. This bit is cleared by writing a one to it, except in level - /// sensitive mode when the pin is in its active state. - EINT2: u1, - /// In level-sensitive mode, this bit is set if the EINT3 function is selected for - /// its pin, and the pin is in its active state. In edge-sensitive mode, this bit is - /// set if the EINT3 function is selected for its pin, and the selected edge occurs - /// on the pin. This bit is cleared by writing a one to it, except in level - /// sensitive mode when the pin is in its active state. - EINT3: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x140); - - /// address: 0x400fc148 - /// External Interrupt Mode register - pub const EXTMODE = @intToPtr(*volatile Mmio(32, packed struct { - /// External interrupt 0 EINT0 mode. - EXTMODE0: u1, - /// External interrupt 1 EINT1 mode. - EXTMODE1: u1, - /// External interrupt 2 EINT2 mode. - EXTMODE2: u1, - /// External interrupt 3 EINT3 mode. - EXTMODE3: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x148); - - /// address: 0x400fc14c - /// External Interrupt Polarity Register - pub const EXTPOLAR = @intToPtr(*volatile Mmio(32, packed struct { - /// External interrupt 0 EINT0 polarity. - EXTPOLAR0: u1, - /// External interrupt 1 EINT1 polarity. - EXTPOLAR1: u1, - /// External interrupt 2 EINT2 polarity. - EXTPOLAR2: u1, - /// External interrupt 3 EINT3 polarity. - EXTPOLAR3: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x14c); - - /// address: 0x400fc180 - /// Reset Source Identification Register - pub const RSID = @intToPtr(*volatile Mmio(32, packed struct { - /// Assertion of the POR signal sets this bit, and clears all of the other bits in - /// this register. But if another Reset signal (e.g., External Reset) remains - /// asserted after the POR signal is negated, then its bit is set. This bit is not - /// affected by any of the other sources of Reset. - POR: u1, - /// Assertion of the RESET signal sets this bit. This bit is cleared only by - /// software or POR. - EXTR: u1, - /// This bit is set when the Watchdog Timer times out and the WDTRESET bit in the - /// Watchdog Mode Register is 1. This bit is cleared only by software or POR. - WDTR: u1, - /// This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD - /// reset trip level (typically 1.85 V under nominal room temperature conditions). - /// If the VDD(REG)(3V3) voltage dips from the normal operating range to below the - /// BOD reset trip level and recovers, the BODR bit will be set to 1. If the - /// VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD - /// reset trip level and continues to decline to the level at which POR is asserted - /// (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises - /// continuously from below 1 V to a level above the BOD reset trip level, the BODR - /// will be set to 1. This bit is cleared only by software or POR. Note: Only in the - /// case where a reset occurs and the POR = 0, the BODR bit indicates if the - /// VDD(REG)(3V3) voltage was below the BOD reset trip level or not. - BODR: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u28, - }), base_address + 0x180); - - /// address: 0x400fc1a0 - /// System control and status - pub const SCS = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u4, - /// Main oscillator range select. - OSCRANGE: u1, - /// Main oscillator enable. - OSCEN: u1, - /// Main oscillator status. - OSCSTAT: u1, - /// Reserved. User software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u25, - }), base_address + 0x1a0); - - /// address: 0x400fc1a8 - /// Peripheral Clock Selection register 0. - pub const PCLKSEL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock selection for WDT. - PCLK_WDT: u2, - /// Peripheral clock selection for TIMER0. - PCLK_TIMER0: u2, - /// Peripheral clock selection for TIMER1. - PCLK_TIMER1: u2, - /// Peripheral clock selection for UART0. - PCLK_UART0: u2, - /// Peripheral clock selection for UART1. - PCLK_UART1: u2, - /// Reserved. - reserved0: u2, - /// Peripheral clock selection for PWM1. - PCLK_PWM1: u2, - /// Peripheral clock selection for I2C0. - PCLK_I2C0: u2, - /// Peripheral clock selection for SPI. - PCLK_SPI: u2, - /// Reserved. - reserved1: u2, - /// Peripheral clock selection for SSP1. - PCLK_SSP1: u2, - /// Peripheral clock selection for DAC. - PCLK_DAC: u2, - /// Peripheral clock selection for ADC. - PCLK_ADC: u2, - /// Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same - /// PCLK divide value when the CAN function is used. - PCLK_CAN1: u2, - /// Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same - /// PCLK divide value when the CAN function is used. - PCLK_CAN2: u2, - /// Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 - /// must have the same PCLK divide value when the CAN function is used. - PCLK_ACF: u2, - }), base_address + 0x1a8); - - /// address: 0x400fc1ac - /// Peripheral Clock Selection register 1. - pub const PCLKSEL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock selection for the Quadrature Encoder Interface. - PCLK_QEI: u2, - /// Peripheral clock selection for GPIO interrupts. - PCLK_GPIOINT: u2, - /// Peripheral clock selection for the Pin Connect block. - PCLK_PCB: u2, - /// Peripheral clock selection for I2C1. - PCLK_I2C1: u2, - /// Reserved. - RESERVED0: u2 = 1, - /// Peripheral clock selection for SSP0. - PCLK_SSP0: u2, - /// Peripheral clock selection for TIMER2. - PCLK_TIMER2: u2, - /// Peripheral clock selection for TIMER3. - PCLK_TIMER3: u2, - /// Peripheral clock selection for UART2. - PCLK_UART2: u2, - /// Peripheral clock selection for UART3. - PCLK_UART3: u2, - /// Peripheral clock selection for I2C2. - PCLK_I2C2: u2, - /// Peripheral clock selection for I2S. - PCLK_I2S: u2, - /// Reserved. - RESERVED1: u2 = 1, - /// Peripheral clock selection for Repetitive Interrupt Timer. - PCLK_RIT: u2, - /// Peripheral clock selection for the System Control block. - PCLK_SYSCON: u2, - /// Peripheral clock selection for the Motor Control PWM. - PCLK_MC: u2, - }), base_address + 0x1ac); - - /// address: 0x400fc1c0 - /// USB Interrupt Status - pub const USBINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// Low priority interrupt line status. This bit is read-only. - USB_INT_REQ_LP: u1, - /// High priority interrupt line status. This bit is read-only. - USB_INT_REQ_HP: u1, - /// DMA interrupt line status. This bit is read-only. - USB_INT_REQ_DMA: u1, - /// USB host interrupt line status. This bit is read-only. - USB_HOST_INT: u1, - /// External ATX interrupt line status. This bit is read-only. - USB_ATX_INT: u1, - /// OTG interrupt line status. This bit is read-only. - USB_OTG_INT: u1, - /// I2C module interrupt line status. This bit is read-only. - USB_I2C_INT: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// USB need clock indicator. This bit is read-only. This bit is set to 1 when USB - /// activity or a change of state on the USB data pins is detected, and it indicates - /// that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it - /// resets to zero 5 ms after the last packet has been received/sent, or 2 ms after - /// the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 - /// to 1 can wake up the microcontroller if activity on the USB bus is selected to - /// wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from - /// Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down - /// mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F - /// C0C4) for considerations about the PLL and invoking the Power-down mode. This - /// bit is read-only. - USB_NEED_CLK: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - /// Enable all USB interrupts. When this bit is cleared, the NVIC does not see the - /// ORed output of the USB interrupt lines. - EN_USB_INTS: u1, - }), base_address + 0x1c0); - - /// address: 0x400fc1c4 - /// Selects between alternative requests on DMA channels 0 through 7 and 10 through - /// 15 - pub const DMACREQSEL = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is - /// selected. - DMASEL08: u1, - /// Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is - /// selected. - DMASEL09: u1, - /// Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer - /// 1 match 0 is selected. - DMASEL10: u1, - /// Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer - /// 1 match 1 is selected. - DMASEL11: u1, - /// Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer - /// 2 match 0 is selected. - DMASEL12: u1, - /// Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer - /// 2 match 1 is selected. - DMASEL13: u1, - /// Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S - /// channel 0 is selected. - DMASEL14: u1, - /// Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S - /// channel 1 is selected. - DMASEL15: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x1c4); - - /// address: 0x400fc1c8 - /// Clock Output Configuration Register - pub const CLKOUTCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects the clock source for the CLKOUT function. Other values are reserved. Do - /// not use. - CLKOUTSEL: u4, - /// Integer value to divide the output clock by, minus one. 0 = Clock is divided by - /// 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is - /// divided by 16. - CLKOUTDIV: u4, - /// CLKOUT enable control, allows switching the CLKOUT source without glitches. - /// Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. - CLKOUT_EN: u1, - /// CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when - /// CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being - /// stopped. - CLKOUT_ACT: u1, - /// Reserved, user software should not write ones to reserved bits. The value read - /// from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x1c8); - }; - /// Ethernet - pub const EMAC = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000000 - /// MAC configuration register 1. - pub const MAC1 = @intToPtr(*volatile Mmio(32, packed struct { - /// RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the - /// MAC synchronizes this control bit to the incoming receive stream. - RXENABLE: u1, - /// PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames - /// regardless of type (normal vs. Control). When disabled, the MAC does not pass - /// valid Control frames. - PARF: u1, - /// RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow - /// Control frames. When disabled, received PAUSE Flow Control frames are ignored. - RXFLOWCTRL: u1, - /// TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed - /// to be transmitted. When disabled, Flow Control frames are blocked. - TXFLOWCTRL: u1, - /// Setting this bit will cause the MAC Transmit interface to be looped back to the - /// MAC Receive interface. Clearing this bit results in normal operation. - LOOPBACK: u1, - /// Unused - RESERVED: u3, - /// Setting this bit will put the Transmit Function logic in reset. - RESETTX: u1, - /// Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic - /// implements flow control. - RESETMCSTX: u1, - /// Setting this bit will put the Ethernet receive logic in reset. - RESETRX: u1, - /// Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic - /// implements flow control. - RESETMCSRX: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// SIMULATION RESET. Setting this bit will cause a reset to the random number - /// generator within the Transmit Function. - SIMRESET: u1, - /// SOFT RESET. Setting this bit will put all modules within the MAC in reset except - /// the Host Interface. - SOFTRESET: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x0); - - /// address: 0x50000004 - /// MAC configuration register 2. - pub const MAC2 = @intToPtr(*volatile Mmio(32, packed struct { - /// When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, - /// the MAC operates in Half-Duplex mode. - FULLDUPLEX: u1, - /// FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame - /// lengths are compared to the Length/Type field. If the Length/Type field - /// represents a length then the check is performed. Mismatches are reported in the - /// StatusInfo word for each received frame. - FLC: u1, - /// HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted - /// and received. - HFEN: u1, - /// DELAYED CRC. This bit determines the number of bytes, if any, of proprietary - /// header information that exist on the front of IEEE 802.3 frames. When 1, four - /// bytes of header (ignored by the CRC function) are added. When 0, there is no - /// proprietary header. - DELAYEDCRC: u1, - /// CRC ENABLESet this bit to append a CRC to every frame whether padding was - /// required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames - /// presented to the MAC contain a CRC. - CRCEN: u1, - /// PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this - /// bit if frames presented to the MAC have a valid length. This bit is used in - /// conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad - /// Operation for details on the pad function. - PADCRCEN: u1, - /// VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 - /// bytes and append a valid CRC. Consult Table 153 - Pad Operation for more - /// information on the various padding features. Note: This bit is ignored if PAD / - /// CRC ENABLE is cleared. - VLANPADEN: u1, - /// AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the - /// type of frame, either tagged or un-tagged, by comparing the two octets following - /// the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - /// - Pad Operation provides a description of the pad function based on the - /// configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is - /// cleared. - AUTODETPADEN: u1, - /// PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the - /// content of the preamble to ensure it contains 0x55 and is error-free. A packet - /// with an incorrect preamble is discarded. When disabled, no preamble checking is - /// performed. - PPENF: u1, - /// LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive - /// packets which contain preamble fields less than 12 bytes in length. When - /// disabled, the MAC allows any length preamble as per the Standard. - LPENF: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u2, - /// When enabled (set to 1), the MAC will immediately retransmit following a - /// collision rather than using the Binary Exponential Backoff algorithm as - /// specified in the Standard. - NOBACKOFF: u1, - /// BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally - /// causes a collision during back pressure, it will immediately retransmit without - /// backoff, reducing the chance of further collisions and ensuring transmit packets - /// get sent. - BP_NOBACKOFF: u1, - /// When enabled (set to 1) the MAC will defer to carrier indefinitely as per the - /// Standard. When disabled, the MAC will abort when the excessive deferral limit is - /// reached. - EXCESSDEFER: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u17, - }), base_address + 0x4); - - /// address: 0x50000008 - /// Back-to-Back Inter-Packet-Gap register. - pub const IPGT = @intToPtr(*volatile Mmio(32, packed struct { - /// BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the - /// nibble time offset of the minimum possible period between the end of any - /// transmitted packet to the beginning of the next. In Full-Duplex mode, the - /// register value should be the desired period in nibble times minus 3. In - /// Half-Duplex mode, the register value should be the desired period in nibble - /// times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which - /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps - /// mode). In Half-Duplex the recommended setting is 0x12 (18d), which also - /// represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps - /// mode). - BTOBINTEGAP: u7, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u25, - }), base_address + 0x8); - - /// address: 0x5000000c - /// Non Back-to-Back Inter-Packet-Gap register. - pub const IPGR = @intToPtr(*volatile Mmio(32, packed struct { - /// NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field - /// representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is - /// 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 - /// us (in 10 Mbps mode). - NBTOBINTEGAP2: u7, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field - /// representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 - /// 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC - /// defers to carrier. If, however, carrier becomes active after IPGR1, the MAC - /// continues timing IPGR2 and transmits, knowingly causing a collision, thus - /// ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The - /// recommended value is 0xC (12d) - NBTOBINTEGAP1: u7, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u17, - }), base_address + 0xc); - - /// address: 0x50000010 - /// Collision window / Retry register. - pub const CLRT = @intToPtr(*volatile Mmio(32, packed struct { - /// RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of - /// retransmission attempts following a collision before aborting the packet due to - /// excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). - /// See IEEE 802.3/4.2.3.2.5. - RETRANSMAX: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u4, - /// COLLISION WINDOW. This is a programmable field representing the slot time or - /// collision window during which collisions occur in properly configured networks. - /// The default value of 0x37 (55d) represents a 56 byte window following the - /// preamble and SFD. - COLLWIN: u6, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u18, - }), base_address + 0x10); - - /// address: 0x50000014 - /// Maximum Frame register. - pub const MAXF = @intToPtr(*volatile Mmio(32, packed struct { - /// MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a - /// maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is - /// 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a - /// shorter maximum length restriction is desired, program this 16-bit field. - MAXFLEN: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x14); - - /// address: 0x50000018 - /// PHY Support register. - pub const SUPP = @intToPtr(*volatile Mmio(32, packed struct { - /// Unused - RESERVED: u8, - /// This bit configures the Reduced MII logic for the current operating speed. When - /// set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. - SPEED: u1, - /// Unused - RESERVED: u23, - }), base_address + 0x18); - - /// address: 0x5000001c - /// Test register. - pub const TEST = @intToPtr(*volatile Mmio(32, packed struct { - /// SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 - /// byte-times to 1 byte-time. - SCPQ: u1, - /// This bit causes the MAC Control sublayer to inhibit transmissions, just as if a - /// PAUSE Receive Control frame with a nonzero pause time parameter was received. - TESTPAUSE: u1, - /// TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on - /// the link. Backpressure causes preamble to be transmitted, raising carrier sense. - /// A transmit packet from the system will be sent during backpressure. - TESTBP: u1, - /// Unused - RESERVED: u29, - }), base_address + 0x1c); - - /// address: 0x50000020 - /// MII Mgmt Configuration register. - pub const MCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform - /// read cycles across a range of PHYs. When set, the MII Management hardware will - /// perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. - /// Clear this bit to allow continuous reads of the same PHY. - SCANINC: u1, - /// SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform - /// read/write cycles without the 32-bit preamble field. Clear this bit to cause - /// normal cycles to be performed. Some PHYs support suppressed preamble. - SUPPPREAMBLE: u1, - /// CLOCK SELECT. This field is used by the clock divide logic in creating the MII - /// Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. - /// Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) - /// is divided by the specified amount. Refer to Table 160 below for the definition - /// of values for this field. - CLOCKSEL: u4, - /// Unused - reserved0: u9, - /// RESET MII MGMT. This bit resets the MII Management hardware. - RESETMIIMGMT: u1, - /// Unused - reserved1: u16, - }), base_address + 0x20); - - /// address: 0x50000024 - /// MII Mgmt Command register. - pub const MCMD = @intToPtr(*volatile Mmio(32, packed struct { - /// This bit causes the MII Management hardware to perform a single Read cycle. The - /// Read data is returned in Register MRDD (MII Mgmt Read Data). - READ: u1, - /// This bit causes the MII Management hardware to perform Read cycles continuously. - /// This is useful for monitoring Link Fail for example. - SCAN: u1, - /// Unused - RESERVED: u30, - }), base_address + 0x24); - - /// address: 0x50000028 - /// MII Mgmt Address register. - pub const MADR = @intToPtr(*volatile Mmio(32, packed struct { - /// REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt - /// cycles. Up to 32 registers can be accessed. - REGADDR: u5, - /// Unused - RESERVED: u3, - /// PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. - /// Up to 31 PHYs can be addressed (0 is reserved). - PHYADDR: u5, - /// Unused - RESERVED: u19, - }), base_address + 0x28); - - /// address: 0x5000002c - /// MII Mgmt Write Data register. - pub const MWTD = @intToPtr(*volatile Mmio(32, packed struct { - /// WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit - /// data and the pre-configured PHY and Register addresses from the MII Mgmt Address - /// register (MADR). - WRITEDATA: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x2c); - - /// address: 0x50000030 - /// MII Mgmt Read Data register. - pub const MRDD = @intToPtr(*volatile Mmio(32, packed struct { - /// READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from - /// this location. - READDATA: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x30); - - /// address: 0x50000034 - /// MII Mgmt Indicators register. - pub const MIND = @intToPtr(*volatile Mmio(32, packed struct { - /// When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read - /// or Write cycle. - BUSY: u1, - /// When 1 is returned - indicates a scan operation (continuous MII Mgmt Read - /// cycles) is in progress. - SCANNING: u1, - /// When 1 is returned - indicates MII Mgmt Read cycle has not completed and the - /// Read Data is not yet valid. - NOTVALID: u1, - /// When 1 is returned - indicates that an MII Mgmt link fail has occurred. - MIILINKFAIL: u1, - /// Unused - RESERVED: u28, - }), base_address + 0x34); - - /// address: 0x50000040 - /// Station Address 0 register. - pub const SA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// STATION ADDRESS, 2nd octet. This field holds the second octet of the station - /// address. - SADDR2: u8, - /// STATION ADDRESS, 1st octet. This field holds the first octet of the station - /// address. - SADDR1: u8, - /// Unused - RESERVED: u16, - }), base_address + 0x40); - - /// address: 0x50000044 - /// Station Address 1 register. - pub const SA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// STATION ADDRESS, 4th octet. This field holds the fourth octet of the station - /// address. - SADDR4: u8, - /// STATION ADDRESS, 3rd octet. This field holds the third octet of the station - /// address. - SADDR3: u8, - /// Unused - RESERVED: u16, - }), base_address + 0x44); - - /// address: 0x50000048 - /// Station Address 2 register. - pub const SA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// STATION ADDRESS, 6th octet. This field holds the sixth octet of the station - /// address. - SADDR6: u8, - /// STATION ADDRESS, 5th octet. This field holds the fifth octet of the station - /// address. - SADDR5: u8, - /// Unused - RESERVED: u16, - }), base_address + 0x48); - - /// address: 0x50000100 - /// Command register. - pub const COMMAND = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable receive. - RXENABLE: u1, - /// Enable transmit. - TXENABLE: u1, - /// Unused - RESERVED: u1, - /// When a 1 is written, all datapaths and the host registers are reset. The MAC - /// needs to be reset separately. - REGRESET: u1, - /// When a 1 is written, the transmit datapath is reset. - TXRESET: u1, - /// When a 1 is written, the receive datapath is reset. - RXRESET: u1, - /// When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they - /// have a CRC error. If 0 runt frames are filtered out. - PASSRUNTFRAME: u1, - /// When set to 1 , disables receive filtering i.e. all frames received are written - /// to memory. - PASSRXFILTER: u1, - /// Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex - /// and continuous preamble in half duplex. - TXFLOWCONTROL: u1, - /// When set to 1 , RMII mode is selected; if 0, MII mode is selected. - RMII: u1, - /// When set to 1 , indicates full duplex operation. - FULLDUPLEX: u1, - /// Unused - RESERVED: u21, - }), base_address + 0x100); - - /// address: 0x50000104 - /// Status register. - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// If 1, the receive channel is active. If 0, the receive channel is inactive. - RXSTATUS: u1, - /// If 1, the transmit channel is active. If 0, the transmit channel is inactive. - TXSTATUS: u1, - /// Unused - RESERVED: u30, - }), base_address + 0x104); - - /// address: 0x50000108 - /// Receive descriptor base address register. - pub const RXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Fixed to 00 - RESERVED: u2, - /// MSBs of receive descriptor base address. - RXDESCRIPTOR: u30, - }), base_address + 0x108); - - /// address: 0x5000010c - /// Receive status base address register. - pub const RXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Fixed to 000 - RESERVED: u3, - /// MSBs of receive status base address. - RXSTATUS: u29, - }), base_address + 0x10c); - - /// address: 0x50000110 - /// Receive number of descriptors register. - pub const RXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { - /// RxDescriptorNumber. Number of descriptors in the descriptor array for which - /// RxDescriptor is the base address. The number of descriptors is minus one - /// encoded. - RXDESCRIPTORN: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x110); - - /// address: 0x50000114 - /// Receive produce index register. - pub const RXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { - /// Index of the descriptor that is going to be filled next by the receive datapath. - RXPRODUCEIX: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x114); - - /// address: 0x50000118 - /// Receive consume index register. - pub const RXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { - /// Index of the descriptor that is going to be processed next by the receive - RXCONSUMEIX: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x118); - - /// address: 0x5000011c - /// Transmit descriptor base address register. - pub const TXDESCRIPTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Fixed to 00 - RESERVED: u2, - /// TxDescriptor. MSBs of transmit descriptor base address. - TXD: u30, - }), base_address + 0x11c); - - /// address: 0x50000120 - /// Transmit status base address register. - pub const TXSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Fixed to 00 - RESERVED: u2, - /// TxStatus. MSBs of transmit status base address. - TXSTAT: u30, - }), base_address + 0x120); - - /// address: 0x50000124 - /// Transmit number of descriptors register. - pub const TXDESCRIPTORNUMBER = @intToPtr(*volatile Mmio(32, packed struct { - /// TxDescriptorNumber. Number of descriptors in the descriptor array for which - /// TxDescriptor is the base address. The register is minus one encoded. - TXDN: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x124); - - /// address: 0x50000128 - /// Transmit produce index register. - pub const TXPRODUCEINDEX = @intToPtr(*volatile Mmio(32, packed struct { - /// TxProduceIndex. Index of the descriptor that is going to be filled next by the - /// transmit software driver. - TXPI: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x128); - - /// address: 0x5000012c - /// Transmit consume index register. - pub const TXCONSUMEINDEX = @intToPtr(*volatile Mmio(32, packed struct { - /// TxConsumeIndex. Index of the descriptor that is going to be transmitted next by - /// the transmit datapath. - TXCI: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x12c); - - /// address: 0x50000158 - /// Transmit status vector 0 register. - pub const TSV0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC error. The attached CRC in the packet did not match the internally generated - /// CRC. - CRCERR: u1, - /// Length check error. Indicates the frame length field does not match the actual - /// number of data items and is not a type field. - LCE: u1, - /// Length out of range. Indicates that frame type/length field was larger than 1500 - /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. - /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame - /// type with the max length and gives the "Length out of range" error. In fact, - /// this bit is not an error indication, but simply a statement by the chip - /// regarding the status of the received frame. - LOR: u1, - /// Transmission of packet was completed. - DONE: u1, - /// Packet's destination was a multicast address. - MULTICAST: u1, - /// Packet's destination was a broadcast address. - BROADCAST: u1, - /// Packet was deferred for at least one attempt, but less than an excessive defer. - PACKETDEFER: u1, - /// Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps - /// or 24287 bit times in 10 Mbps mode. - EXDF: u1, - /// Excessive Collision. Packet was aborted due to exceeding of maximum allowed - /// number of collisions. - EXCOL: u1, - /// Late Collision. Collision occurred beyond collision window, 512 bit times. - LCOL: u1, - /// Byte count in frame was greater than can be represented in the transmit byte - /// count field in TSV1. - GIANT: u1, - /// Host side caused buffer underrun. - UNDERRUN: u1, - /// The total number of bytes transferred including collided attempts. - TOTALBYTES: u16, - /// The frame was a control frame. - CONTROLFRAME: u1, - /// The frame was a control frame with a valid PAUSE opcode. - PAUSE: u1, - /// Carrier-sense method backpressure was previously applied. - BACKPRESSURE: u1, - /// Frame's length/type field contained 0x8100 which is the VLAN protocol - /// identifier. - VLAN: u1, - }), base_address + 0x158); - - /// address: 0x5000015c - /// Transmit status vector 1 register. - pub const TSV1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit byte count. The total number of bytes in the frame, not counting the - /// collided bytes. - TBC: u16, - /// Transmit collision count. Number of collisions the current packet incurred - /// during transmission attempts. The maximum number of collisions (16) cannot be - /// represented. - TCC: u4, - /// Unused - RESERVED: u12, - }), base_address + 0x15c); - - /// address: 0x50000160 - /// Receive status vector register. - pub const RSV = @intToPtr(*volatile Mmio(32, packed struct { - /// Received byte count. Indicates length of received frame. - RBC: u16, - /// Packet previously ignored. Indicates that a packet was dropped. - PPI: u1, - /// RXDV event previously seen. Indicates that the last receive event seen was not - /// long enough to be a valid packet. - RXDVSEEN: u1, - /// Carrier event previously seen. Indicates that at some time since the last - /// receive statistics, a carrier event was detected. - CESEEN: u1, - /// Receive code violation. Indicates that received PHY data does not represent a - /// valid receive code. - RCV: u1, - /// CRC error. The attached CRC in the packet did not match the internally generated - /// CRC. - CRCERR: u1, - /// Length check error. Indicates the frame length field does not match the actual - /// number of data items and is not a type field. - LCERR: u1, - /// Length out of range. Indicates that frame type/length field was larger than 1518 - /// bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. - /// when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame - /// type with the max length and gives the "Length out of range" error. In fact, - /// this bit is not an error indication, but simply a statement by the chip - /// regarding the status of the received frame. - LOR: u1, - /// Receive OK. The packet had valid CRC and no symbol errors. - ROK: u1, - /// The packet destination was a multicast address. - MULTICAST: u1, - /// The packet destination was a broadcast address. - BROADCAST: u1, - /// Indicates that after the end of packet another 1-7 bits were received. A single - /// nibble, called dribble nibble, is formed but not sent out. - DRIBBLENIBBLE: u1, - /// The frame was a control frame. - CONTROLFRAME: u1, - /// The frame was a control frame with a valid PAUSE opcode. - PAUSE: u1, - /// Unsupported Opcode. The current frame was recognized as a Control Frame but - /// contains an unknown opcode. - UO: u1, - /// Frame's length/type field contained 0x8100 which is the VLAN protocol - /// identifier. - VLAN: u1, - /// Unused - RESERVED: u1, - }), base_address + 0x160); - - /// address: 0x50000170 - /// Flow control counter register. - pub const FLOWCONTROLCOUNTER = @intToPtr(*volatile Mmio(32, packed struct { - /// MirrorCounter. In full duplex mode the MirrorCounter specifies the number of - /// cycles before re-issuing the Pause control frame. - MC: u16, - /// PauseTimer. In full-duplex mode the PauseTimer specifies the value that is - /// inserted into the pause timer field of a pause flow control frame. In half - /// duplex mode the PauseTimer specifies the number of backpressure cycles. - PT: u16, - }), base_address + 0x170); - - /// address: 0x50000174 - /// Flow control status register. - pub const FLOWCONTROLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// MirrorCounterCurrent. In full duplex mode this register represents the current - /// value of the datapath's mirror counter which counts up to the value specified by - /// the MirrorCounter field in the FlowControlCounter register. In half duplex mode - /// the register counts until it reaches the value of the PauseTimer bits in the - /// FlowControlCounter register. - MCC: u16, - /// Unused - RESERVED: u16, - }), base_address + 0x174); - - /// address: 0x50000200 - /// Receive filter control register. - pub const RXFILTERCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// AcceptUnicastEn. When set to 1, all unicast frames are accepted. - AUE: u1, - /// AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. - ABE: u1, - /// AcceptMulticastEn. When set to 1, all multicast frames are accepted. - AME: u1, - /// AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash - /// filter are accepted. - AUHE: u1, - /// AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect - /// hash filter are accepted. - AMHE: u1, - /// AcceptPerfectEn. When set to 1, the frames with a destination address identical - /// to the station address are accepted. - APE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u6, - /// MagicPacketEnWoL. When set to 1, the result of the magic packet filter will - /// generate a WoL interrupt when there is a match. - MPEW: u1, - /// RxFilterEnWoL. When set to 1, the result of the perfect address matching filter - /// and the imperfect hash filter will generate a WoL interrupt when there is a - /// match. - RFEW: u1, - /// Unused - RESERVED: u18, - }), base_address + 0x200); - - /// address: 0x50000204 - /// Receive filter WoL status register. - pub const RXFILTERWOLSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. - AUW: u1, - /// AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. - ABW: u1, - /// AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. - AMW: u1, - /// AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the - /// imperfect hash filter caused WoL. - AUHW: u1, - /// AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the - /// imperfect hash filter caused WoL. - AMHW: u1, - /// AcceptPerfectWoL. When the value is 1, the perfect address matching filter - /// caused WoL. - APW: u1, - /// Unused - RESERVED: u1, - /// RxFilterWoL. When the value is 1, the receive filter caused WoL. - RFW: u1, - /// MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. - MPW: u1, - /// Unused - RESERVED: u23, - }), base_address + 0x204); - - /// address: 0x50000208 - /// Receive filter WoL clear register. - pub const RXFILTERWOLCLEAR = @intToPtr(*volatile Mmio(32, packed struct { - /// AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - AUWCLR: u1, - /// AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - ABWCLR: u1, - /// AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - AMWCLR: u1, - /// AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in - /// the RxFilterWoLStatus register is cleared. - AUHWCLR: u1, - /// AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in - /// the RxFilterWoLStatus register is cleared. - AMHWCLR: u1, - /// AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - APWCLR: u1, - /// Unused - RESERVED: u1, - /// RxFilterWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - RFWCLR: u1, - /// MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the - /// RxFilterWoLStatus register is cleared. - MPWCLR: u1, - /// Unused - RESERVED: u23, - }), base_address + 0x208); - - /// address: 0x50000210 - /// Hash filter table LSBs register. - pub const HASHFILTERL = @intToPtr(*volatile Mmio(32, packed struct { - /// HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. - HFL: u32, - }), base_address + 0x210); - - /// address: 0x50000214 - /// Hash filter table MSBs register. - pub const HASHFILTERH = @intToPtr(*volatile Mmio(32, packed struct { - /// Bits 63:32 of the imperfect filter hash table for receive filtering. - HFH: u32, - }), base_address + 0x214); - - /// address: 0x50000fe0 - /// Interrupt status register. - pub const INTSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt - /// should be resolved by a Rx soft-reset. The bit is not set when there is a - /// nonfatal overrun error. - RXOVERRUNINT: u1, - /// Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, - /// SymbolError, CRCError or NoDescriptor or Overrun. - RXERRORINT: u1, - /// Interrupt triggered when all receive descriptors have been processed i.e. on the - /// transition to the situation where ProduceIndex == ConsumeIndex. - RXFINISHEDINT: u1, - /// Interrupt triggered when a receive descriptor has been processed while the - /// Interrupt bit in the Control field of the descriptor was set. - RXDONEINT: u1, - /// Interrupt set on a fatal underrun error in the transmit queue. The fatal - /// interrupt should be resolved by a Tx soft-reset. The bit is not set when there - /// is a nonfatal underrun error. - TXUNDERRUNINT: u1, - /// Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and - /// ExcessiveDefer, NoDescriptor or Underrun. - TXERRORINT: u1, - /// Interrupt triggered when all transmit descriptors have been processed i.e. on - /// the transition to the situation where ProduceIndex == ConsumeIndex. - TXFINISHEDINT: u1, - /// Interrupt triggered when a descriptor has been transmitted while the Interrupt - /// bit in the Control field of the descriptor was set. - TXDONEINT: u1, - /// Unused - RESERVED: u4, - /// Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet - /// register. - SOFTINT: u1, - /// Interrupt triggered by a Wake-up event detected by the receive filter. - WAKEUPINT: u1, - /// Unused - RESERVED: u18, - }), base_address + 0xfe0); - - /// address: 0x50000fe4 - /// Interrupt enable register. - pub const INTENABLE = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable for interrupt trigger on receive buffer overrun or descriptor underrun - /// situations. - RXOVERRUNINTEN: u1, - /// Enable for interrupt trigger on receive errors. - RXERRORINTEN: u1, - /// Enable for interrupt triggered when all receive descriptors have been processed - /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - RXFINISHEDINTEN: u1, - /// Enable for interrupt triggered when a receive descriptor has been processed - /// while the Interrupt bit in the Control field of the descriptor was set. - RXDONEINTEN: u1, - /// Enable for interrupt trigger on transmit buffer or descriptor underrun - /// situations. - TXUNDERRUNINTEN: u1, - /// Enable for interrupt trigger on transmit errors. - TXERRORINTEN: u1, - /// Enable for interrupt triggered when all transmit descriptors have been processed - /// i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. - TXFINISHEDINTEN: u1, - /// Enable for interrupt triggered when a descriptor has been transmitted while the - /// Interrupt bit in the Control field of the descriptor was set. - TXDONEINTEN: u1, - /// Unused - RESERVED: u4, - /// Enable for interrupt triggered by the SoftInt bit in the IntStatus register, - /// caused by software writing a 1 to the SoftIntSet bit in the IntSet register. - SOFTINTEN: u1, - /// Enable for interrupt triggered by a Wake-up event detected by the receive - /// filter. - WAKEUPINTEN: u1, - /// Unused - RESERVED: u18, - }), base_address + 0xfe4); - - /// address: 0x50000fe8 - /// Interrupt clear register. - pub const INTCLEAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - RXOVERRUNINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - RXERRORINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - RXFINISHEDINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - RXDONEINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - TXUNDERRUNINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - TXERRORINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - TXFINISHEDINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - TXDONEINTCLR: u1, - /// Unused - RESERVED: u4, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - SOFTINTCLR: u1, - /// Writing a 1 clears the corresponding status bit in interrupt status register - /// IntStatus. - WAKEUPINTCLR: u1, - /// Unused - RESERVED: u18, - }), base_address + 0xfe8); - - /// address: 0x50000fec - /// Interrupt set register. - pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - RXOVERRUNINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - RXERRORINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - RXFINISHEDINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - RXDONEINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - TXUNDERRUNINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - TXERRORINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - TXFINISHEDINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - TXDONEINTSET: u1, - /// Unused - RESERVED: u4, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - SOFTINTSET: u1, - /// Writing a 1 to one sets the corresponding status bit in interrupt status - /// register IntStatus. - WAKEUPINTSET: u1, - /// Unused - RESERVED: u18, - }), base_address + 0xfec); - - /// address: 0x50000ff4 - /// Power-down register. - pub const POWERDOWN = @intToPtr(*volatile Mmio(32, packed struct { - /// Unused - RESERVED: u31, - /// PowerDownMACAHB. If true, all AHB accesses will return a read/write error, - /// except accesses to the Power-Down register. - PD: u1, - }), base_address + 0xff4); - }; - /// General purpose DMA controller - pub const GPDMA = struct { - pub const base_address = 0x50004000; - - /// address: 0x50004000 - /// DMA Interrupt Status Register - pub const INTSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT0: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT1: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT2: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT3: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT4: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT5: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT6: u1, - /// Status of DMA channel interrupts after masking. Each bit represents one channel: - /// 0 - the corresponding channel has no active interrupt request. 1 - the - /// corresponding channel does have an active interrupt request. - INTSTAT7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x0); - - /// address: 0x50004004 - /// DMA Interrupt Terminal Count Request Status Register - pub const INTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT0: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT1: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT2: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT3: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT4: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT5: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT6: u1, - /// Terminal count interrupt request status for DMA channels. Each bit represents - /// one channel: 0 - the corresponding channel has no active terminal count - /// interrupt request. 1 - the corresponding channel does have an active terminal - /// count interrupt request. - INTTCSTAT7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x4); - - /// address: 0x50004008 - /// DMA Interrupt Terminal Count Request Clear Register - pub const INTTCCLEAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR0: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR1: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR2: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR3: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR4: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR5: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR6: u1, - /// Allows clearing the Terminal count interrupt request (IntTCStat) for DMA - /// channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - - /// clears the corresponding channel terminal count interrupt. - INTTCCLEAR7: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x8); - - /// address: 0x5000400c - /// DMA Interrupt Error Status Register - pub const INTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT0: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT1: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT2: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT3: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT4: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT5: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT6: u1, - /// Interrupt error status for DMA channels. Each bit represents one channel: 0 - - /// the corresponding channel has no active error interrupt request. 1 - the - /// corresponding channel does have an active error interrupt request. - INTERRSTAT7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0xc); - - /// address: 0x50004010 - /// DMA Interrupt Error Clear Register - pub const INTERRCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR0: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR1: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR2: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR3: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR4: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR5: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR6: u1, - /// Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. - /// Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the - /// corresponding channel error interrupt. - INTERRCLR7: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x10); - - /// address: 0x50004014 - /// DMA Raw Interrupt Terminal Count Status Register - pub const RAWINTTCSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT0: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT1: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT2: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT3: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT4: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT5: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT6: u1, - /// Status of the terminal count interrupt for DMA channels prior to masking. Each - /// bit represents one channel: 0 - the corresponding channel has no active terminal - /// count interrupt request. 1 - the corresponding channel does have an active - /// terminal count interrupt request. - RAWINTTCSTAT7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x14); - - /// address: 0x50004018 - /// DMA Raw Error Interrupt Status Register - pub const RAWINTERRSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT0: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT1: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT2: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT3: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT4: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT5: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT6: u1, - /// Status of the error interrupt for DMA channels prior to masking. Each bit - /// represents one channel: 0 - the corresponding channel has no active error - /// interrupt request. 1 - the corresponding channel does have an active error - /// interrupt request. - RAWINTERRSTAT7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x18); - - /// address: 0x5000401c - /// DMA Enabled Channel Register - pub const ENBLDCHNS = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS0: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS1: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS2: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS3: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS4: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS5: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS6: u1, - /// Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel - /// is disabled. 1 - DMA channel is enabled. - ENABLEDCHANNELS7: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x1c); - - /// address: 0x50004020 - /// DMA Software Burst Request Register - pub const SOFTBREQ = @intToPtr(*volatile Mmio(32, packed struct { - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ0: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ1: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ2: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ3: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ4: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ5: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ6: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ7: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ8: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ9: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ10: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ11: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ12: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ13: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ14: u1, - /// Software burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral Description (refer to Table 672 - /// for peripheral hardware connections to the DMA controller): 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA burst request for the corresponding - /// request line. - SOFTBREQ15: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x20); - - /// address: 0x50004024 - /// DMA Software Single Request Register - pub const SOFTSREQ = @intToPtr(*volatile Mmio(32, packed struct { - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ0: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ1: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ2: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ3: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ4: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ5: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ6: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ7: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ8: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ9: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ10: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ11: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ12: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ13: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ14: u1, - /// Software single transfer request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA single transfer request for the - /// corresponding request line. - SOFTSREQ15: u1, - /// Reserved. Read undefined. Write reserved bits as zero. - RESERVED: u16, - }), base_address + 0x24); - - /// address: 0x50004028 - /// DMA Software Last Burst Request Register - pub const SOFTLBREQ = @intToPtr(*volatile Mmio(32, packed struct { - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ0: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ1: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ2: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ3: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ4: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ5: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ6: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ7: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ8: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ9: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ10: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ11: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ12: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ13: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ14: u1, - /// Software last burst request flags for each of 16 possible sources. Each bit - /// represents one DMA request line or peripheral function: 0 - writing 0 has no - /// effect. 1 - writing 1 generates a DMA last burst request for the corresponding - /// request line. - SOFTLBREQ15: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x28); - - /// address: 0x5000402c - /// DMA Software Last Single Request Register - pub const SOFTLSREQ = @intToPtr(*volatile Mmio(32, packed struct { - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ0: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ1: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ2: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ3: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ4: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ5: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ6: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ7: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ8: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ9: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ10: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ11: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ12: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ13: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ14: u1, - /// Software last single transfer request flags for each of 16 possible sources. - /// Each bit represents one DMA request line or peripheral function: 0 - writing 0 - /// has no effect. 1 - writing 1 generates a DMA last single transfer request for - /// the corresponding request line. - SOFTLSREQ15: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x2c); - - /// address: 0x50004030 - /// DMA Configuration Register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller - /// reduces power consumption. 1 = enabled. - E: u1, - /// AHB Master endianness configuration: 0 = little-endian mode (default). 1 = - /// big-endian mode. - M: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x30); - - /// address: 0x50004034 - /// DMA Synchronization Register - pub const SYNC = @intToPtr(*volatile Mmio(32, packed struct { - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC0: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC1: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC2: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC3: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC4: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC5: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC6: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC7: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC8: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC9: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC10: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC11: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC12: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC13: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC14: u1, - /// Controls the synchronization logic for DMA request signals. Each bit represents - /// one set of DMA request lines as described in the preceding text: 0 - - /// synchronization logic for the corresponding DMA request signals are enabled. 1 - - /// synchronization logic for the corresponding DMA request signals are disabled. - DMACSYNC15: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x34); - - /// address: 0x50004100 - /// DMA Channel 0 Source Address Register - pub const SRCADDR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x100); - - /// address: 0x50004120 - /// DMA Channel 0 Source Address Register - pub const SRCADDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x120); - - /// address: 0x50004140 - /// DMA Channel 0 Source Address Register - pub const SRCADDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x140); - - /// address: 0x50004160 - /// DMA Channel 0 Source Address Register - pub const SRCADDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x160); - - /// address: 0x50004180 - /// DMA Channel 0 Source Address Register - pub const SRCADDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x180); - - /// address: 0x500041a0 - /// DMA Channel 0 Source Address Register - pub const SRCADDR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x1a0); - - /// address: 0x500041c0 - /// DMA Channel 0 Source Address Register - pub const SRCADDR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x1c0); - - /// address: 0x500041e0 - /// DMA Channel 0 Source Address Register - pub const SRCADDR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA source address. Reading this register will return the current source - /// address. - SRCADDR: u32, - }), base_address + 0x1e0); - - /// address: 0x50004104 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x104); - - /// address: 0x50004124 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x124); - - /// address: 0x50004144 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x144); - - /// address: 0x50004164 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x164); - - /// address: 0x50004184 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x184); - - /// address: 0x500041a4 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x1a4); - - /// address: 0x500041c4 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x1c4); - - /// address: 0x500041e4 - /// DMA Channel 0 Destination Address Register - pub const DESTADDR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA Destination address. Reading this register will return the current - /// destination address. - DESTADDR: u32, - }), base_address + 0x1e4); - - /// address: 0x50004108 - /// DMA Channel 0 Linked List Item Register - pub const LLI0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x108); - - /// address: 0x50004128 - /// DMA Channel 0 Linked List Item Register - pub const LLI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x128); - - /// address: 0x50004148 - /// DMA Channel 0 Linked List Item Register - pub const LLI2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x148); - - /// address: 0x50004168 - /// DMA Channel 0 Linked List Item Register - pub const LLI3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x168); - - /// address: 0x50004188 - /// DMA Channel 0 Linked List Item Register - pub const LLI4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x188); - - /// address: 0x500041a8 - /// DMA Channel 0 Linked List Item Register - pub const LLI5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x1a8); - - /// address: 0x500041c8 - /// DMA Channel 0 Linked List Item Register - pub const LLI6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x1c8); - - /// address: 0x500041e8 - /// DMA Channel 0 Linked List Item Register - pub const LLI7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Linked list item. Bits [31:2] of the address for the next LLI. Address bits - /// [1:0] are 0. - LLI: u30, - }), base_address + 0x1e8); - - /// address: 0x5000410c - /// DMA Channel 0 Control Register - pub const CONTROL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x10c); - - /// address: 0x5000412c - /// DMA Channel 0 Control Register - pub const CONTROL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x12c); - - /// address: 0x5000414c - /// DMA Channel 0 Control Register - pub const CONTROL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x14c); - - /// address: 0x5000416c - /// DMA Channel 0 Control Register - pub const CONTROL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x16c); - - /// address: 0x5000418c - /// DMA Channel 0 Control Register - pub const CONTROL4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x18c); - - /// address: 0x500041ac - /// DMA Channel 0 Control Register - pub const CONTROL5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x1ac); - - /// address: 0x500041cc - /// DMA Channel 0 Control Register - pub const CONTROL6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x1cc); - - /// address: 0x500041ec - /// DMA Channel 0 Control Register - pub const CONTROL7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size. This field sets the size of the transfer when the DMA controller - /// is the flow controller, in which case the value must be set before the channel - /// is enabled. Transfer size is updated as data transfers are completed. A read - /// from this field indicates the number of transfers completed on the destination - /// bus. Reading the register when the channel is active does not give useful - /// information because by the time that the software has processed the value read, - /// the channel might have progressed. It is intended to be used only when a channel - /// is enabled and then disabled. The transfer size value is not used if a - /// peripheral is the flow controller. - TRANSFERSIZE: u12, - /// Source burst size. Indicates the number of transfers that make up a source - /// burst. This value must be set to the burst size of the source peripheral, or if - /// the source is memory, to the memory boundary size. The burst size is the amount - /// of data that is transferred when the DMACBREQ signal goes active in the source - /// peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - - /// 256 - SBSIZE: u3, - /// Destination burst size. Indicates the number of transfers that make up a - /// destination burst transfer request. This value must be set to the burst size of - /// the destination peripheral or, if the destination is memory, to the memory - /// boundary size. The burst size is the amount of data that is transferred when the - /// DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - - /// 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 - DBSIZE: u3, - /// Source transfer width. The source and destination widths can be different from - /// each other. The hardware automatically packs and unpacks the data as required. - /// 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - - /// Reserved - SWIDTH: u3, - /// Destination transfer width. The source and destination widths can be different - /// from each other. The hardware automatically packs and unpacks the data as - /// required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to - /// 111 - Reserved - DWIDTH: u3, - /// Reserved, and must be written as 0. - RESERVED: u2, - /// Source increment: 0 - the source address is not incremented after each transfer. - /// 1 - the source address is incremented after each transfer. - SI: u1, - /// Destination increment: 0 - the destination address is not incremented after each - /// transfer. 1 - the destination address is incremented after each transfer. - DI: u1, - /// This is provided to the peripheral during a DMA bus access and indicates that - /// the access is in user mode or privileged mode. This information is not used in - /// the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. - PROT1: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is bufferable or not bufferable. This information is - /// not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is - /// bufferable. - PROT2: u1, - /// This is provided to the peripheral during a DMA bus access and indicates to the - /// peripheral that the access is cacheable or not cacheable. This information is - /// not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is - /// cacheable. - PROT3: u1, - /// Terminal count interrupt enable bit. 0 - the terminal count interrupt is - /// disabled. 1 - the terminal count interrupt is enabled. - I: u1, - }), base_address + 0x1ec); - - /// address: 0x50004110 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x110); - - /// address: 0x50004130 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x130); - - /// address: 0x50004150 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x150); - - /// address: 0x50004170 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x170); - - /// address: 0x50004190 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x190); - - /// address: 0x500041b0 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x1b0); - - /// address: 0x500041d0 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x1d0); - - /// address: 0x500041f0 - /// DMA Channel 0 Configuration Register[1] - pub const CONFIG7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable. Reading this bit indicates whether a channel is currently - /// enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel - /// Enable bit status can also be found by reading the DMACEnbldChns Register. A - /// channel is enabled by setting this bit. A channel can be disabled by clearing - /// the Enable bit. This causes the current AHB transfer (if one is in progress) to - /// complete and the channel is then disabled. Any data in the FIFO of the relevant - /// channel is lost. Restarting the channel by setting the Channel Enable bit has - /// unpredictable effects, the channel must be fully re-initialized. The channel is - /// also disabled, and Channel Enable bit cleared, when the last LLI is reached, the - /// DMA transfer is completed, or if a channel error is encountered. If a channel - /// must be disabled without losing data in the FIFO, the Halt bit must be set so - /// that further DMA requests are ignored. The Active bit must then be polled until - /// it reaches 0, indicating that there is no data left in the FIFO. Finally, the - /// Channel Enable bit can be cleared. - E: u1, - /// Source peripheral. This value selects the DMA source request peripheral. This - /// field is ignored if the source of the transfer is from memory. See Table 672 for - /// peripheral identification. - SRCPERIPHERAL: u5, - /// Destination peripheral. This value selects the DMA destination request - /// peripheral. This field is ignored if the destination of the transfer is to - /// memory. See Table 672 for peripheral identification. - DESTPERIPHERAL: u5, - /// This value indicates the type of transfer and specifies the flow controller. The - /// transfer type can be memory-to-memory, memory-to-peripheral, - /// peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the - /// DMA controller, the source peripheral, or the destination peripheral. Refer to - /// Table 694 for the encoding of this field. - TRANSFERTYPE: u3, - /// Interrupt error mask. When cleared, this bit masks out the error interrupt of - /// the relevant channel. - IE: u1, - /// Terminal count interrupt mask. When cleared, this bit masks out the terminal - /// count interrupt of the relevant channel. - ITC: u1, - /// Lock. When set, this bit enables locked transfers. This information is not used - /// in the LPC178x/177x. - L: u1, - /// Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO - /// has data. This value can be used with the Halt and Channel Enable bits to - /// cleanly disable a DMA channel. This is a read-only bit. - A: u1, - /// Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The - /// contents of the channel FIFO are drained. This value can be used with the Active - /// and Channel Enable bits to cleanly disable a DMA channel. - H: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u13, - }), base_address + 0x1f0); - }; - /// USB device/host/OTG controller - pub const USB = struct { - pub const base_address = 0x50008000; - - /// address: 0x50008100 - /// OTG Interrupt Status - pub const INTST = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer time-out. - TMR: u1, - /// Remove pull-up. This bit is set by hardware to indicate that software needs to - /// disable the D+ pull-up resistor. - REMOVE_PU: u1, - /// HNP failed. This bit is set by hardware to indicate that the HNP switching has - /// failed. - HNP_FAILURE: u1, - /// HNP succeeded. This bit is set by hardware to indicate that the HNP switching - /// has succeeded. - HNP_SUCCESS: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x100); - - /// address: 0x50008104 - /// OTG Interrupt Enable - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// 1 = enable the corresponding bit in the IntSt register. - TMR_EN: u1, - /// 1 = enable the corresponding bit in the IntSt register. - REMOVE_PU_EN: u1, - /// 1 = enable the corresponding bit in the IntSt register. - HNP_FAILURE_EN: u1, - /// 1 = enable the corresponding bit in the IntSt register. - HNP_SUCCES_EN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x104); - - /// address: 0x50008108 - /// OTG Interrupt Set - pub const INTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. - TMR_SET: u1, - /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. - REMOVE_PU_SET: u1, - /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_FAILURE_SET: u1, - /// 0 = no effect. 1 = set the corresponding bit in the IntSt register. - HNP_SUCCES_SET: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x108); - - /// address: 0x5000810c - /// OTG Interrupt Clear - pub const INTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - TMR_CLR: u1, - /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - REMOVE_PU_CLR: u1, - /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_FAILURE_CLR: u1, - /// 0 = no effect. 1 = clear the corresponding bit in the IntSt register. - HNP_SUCCES_CLR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u28, - }), base_address + 0x10c); - - /// address: 0x50008110 - /// OTG Status and Control and USB port select - pub const STCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by - /// hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section - /// 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: - /// Reserved 11: U1 = host, U2 = device In a device-only configuration, the - /// following values are allowed: 00: U1 = device. The USB device controller signals - /// are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = - /// device. The USB device controller signals are mapped to the U2 port: - /// USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. - PORT_FUNC: u2, - /// Timer scale selection. This field determines the duration of each timer count. - /// 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved - TMR_SCALE: u2, - /// Timer mode selection. 0: monoshot 1: free running - TMR_MODE: u1, - /// Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. - TMR_EN: u1, - /// Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single - /// bit control for the software to restart the timer when the timer is enabled. - TMR_RST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears - /// this bit when HNP_SUCCESS or HNP_FAILURE is set. - B_HNP_TRACK: u1, - /// Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this - /// bit when HNP_SUCCESS or HNP_FAILURE is set. - A_HNP_TRACK: u1, - /// When the B-device changes its role from peripheral to host, software sets this - /// bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit - /// when HNP_SUCCESS or HNP_FAILURE is set. - PU_REMOVED: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u5, - /// Current timer count value. - TMR_CNT: u16, - }), base_address + 0x110); - - /// address: 0x50008114 - /// OTG Timer - pub const TMR = @intToPtr(*volatile Mmio(32, packed struct { - /// The TMR interrupt is set when TMR_CNT reaches this value. - TIMEOUT_CNT: u16, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u16, - }), base_address + 0x114); - - /// address: 0x50008200 - /// USB Device Interrupt Status - pub const DEVINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// The frame interrupt occurs every 1 ms. This is used in isochronous packet - /// transfers. - FRAME: u1, - /// Fast endpoint interrupt. If an Endpoint Interrupt Priority register - /// (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to - /// this bit. - EP_FAST: u1, - /// Slow endpoints interrupt. If an Endpoint Interrupt Priority Register - /// (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be - /// routed to this bit. - EP_SLOW: u1, - /// Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer - /// to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page - /// 366. - DEV_STAT: u1, - /// The command code register (USBCmdCode) is empty (New command can be written). - CCEMPTY: u1, - /// Command data register (USBCmdData) is full (Data can be read now). - CDFULL: u1, - /// The current packet in the endpoint buffer is transferred to the CPU. - RxENDPKT: u1, - /// The number of data bytes transferred to the endpoint buffer equals the number of - /// bytes programmed in the TxPacket length register (USBTxPLen). - TxENDPKT: u1, - /// Endpoints realized. Set when Realize Endpoint register (USBReEp) or - /// MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation - /// is completed. - EP_RLZED: u1, - /// Error Interrupt. Any bus error interrupt from the USB device. Refer to Section - /// 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 - ERR_INT: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u22, - }), base_address + 0x200); - - /// address: 0x50008204 - /// USB Device Interrupt Enable - pub const DEVINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - FRAMEEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_FASTEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_SLOWEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - DEV_STATEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CCEMPTYEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - CDFULLEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - RxENDPKTEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - TxENDPKTEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - EP_RLZEDEN: u1, - /// 0 = No interrupt is generated. 1 = An interrupt will be generated when the - /// corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table - /// 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt - /// line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the - /// USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. - ERR_INTEN: u1, - /// Reserved - RESERVED: u22, - }), base_address + 0x204); - - /// address: 0x50008208 - /// USB Device Interrupt Clear - pub const DEVINTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - FRAMECLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - EP_FASTCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - EP_SLOWCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - DEV_STATCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - CCEMPTYCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - CDFULLCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - RxENDPKTCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - TxENDPKTCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - EP_RLZEDCLR: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// cleared. - ERR_INTCLR: u1, - /// Reserved - RESERVED: u22, - }), base_address + 0x208); - - /// address: 0x5000820c - /// USB Device Interrupt Set - pub const DEVINTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - FRAMESET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - EP_FASTSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - EP_SLOWSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - DEV_STATSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - CCEMPTYSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - CDFULLSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - RxENDPKTSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - TxENDPKTSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - EP_RLZEDSET: u1, - /// 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is - /// set. - ERR_INTSET: u1, - /// Reserved - RESERVED: u22, - }), base_address + 0x20c); - - /// address: 0x50008210 - /// USB Command Code - pub const CMDCODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - /// The command phase: - CMD_PHASE: u8, - /// This is a multi-purpose field. When CMD_PHASE is Command or Read, this field - /// contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this - /// field contains the command write data (CMD_WDATA). - CMD_CODE_WDATA: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u8, - }), base_address + 0x210); - - /// address: 0x50008214 - /// USB Command Data - pub const CMDDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Command Read Data. - CMD_RDATA: u8, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u24, - }), base_address + 0x214); - - /// address: 0x50008218 - /// USB Receive Data - pub const RXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Data received. - RX_DATA: u32, - }), base_address + 0x218); - - /// address: 0x5000821c - /// USB Transmit Data - pub const TXDATA = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit Data. - TX_DATA: u32, - }), base_address + 0x21c); - - /// address: 0x500080dc - /// USB Receive Packet Length - pub const RXPLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// The remaining number of bytes to be read from the currently selected endpoint's - /// buffer. When this field decrements to 0, the RxENDPKT bit will be set in - /// USBDevIntSt. - PKT_LNGTH: u10, - /// Data valid. This bit is useful for isochronous endpoints. Non-isochronous - /// endpoints do not raise an interrupt when an erroneous data packet is received. - /// But invalid data packet can be produced with a bus reset. For isochronous - /// endpoints, data transfer will happen even if an erroneous packet is received. In - /// this case DV bit will not be set for the packet. - DV: u1, - /// The PKT_LNGTH field is valid and the packet is ready for reading. - PKT_RDY: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u20, - }), base_address + 0xdc); - - /// address: 0x50008224 - /// USB Transmit Packet Length - pub const TXPLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// The remaining number of bytes to be written to the selected endpoint buffer. - /// This field is decremented by 4 by hardware after each write to USBTxData. When - /// this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. - PKT_LNGTH: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x224); - - /// address: 0x50008228 - /// USB Control - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Read mode control. Enables reading data from the OUT endpoint buffer for the - /// endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This - /// bit is cleared by hardware when the last word of the current packet is read from - /// USBRxData. - RD_EN: u1, - /// Write mode control. Enables writing data to the IN endpoint buffer for the - /// endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This - /// bit is cleared by hardware when the number of bytes in USBTxLen have been sent. - WR_EN: u1, - /// Logical Endpoint number. - LOG_ENDPOINT: u4, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u26, - }), base_address + 0x228); - - /// address: 0x5000822c - /// USB Device Interrupt Priority - pub const DEVINTPRI = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interrupt routing - FRAME: u1, - /// Fast endpoint interrupt routing - EP_FAST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u30, - }), base_address + 0x22c); - - /// address: 0x50008230 - /// USB Endpoint Interrupt Status - pub const EPINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST0: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST1: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST2: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST3: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST4: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST5: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST6: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST7: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST8: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST9: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST10: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST11: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST12: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST13: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST14: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST15: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST16: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST17: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST18: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST19: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST20: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST21: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST22: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST23: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST24: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST25: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST26: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST27: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST28: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST29: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST30: u1, - /// 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, - /// ..., 31) Interrupt received. - EPST31: u1, - }), base_address + 0x230); - - /// address: 0x50008234 - /// USB Endpoint Interrupt Enable - pub const EPINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN0: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN1: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN2: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN3: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN4: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN5: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN6: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN7: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN8: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN9: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN10: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN11: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN12: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN13: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN14: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN15: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN16: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN17: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN18: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN19: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN20: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN21: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN22: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN23: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN24: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN25: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN26: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN27: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN28: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN29: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN30: u1, - /// 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this - /// endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt - /// occurs for this endpoint. Implies Slave mode for this endpoint. - EPEN31: u1, - }), base_address + 0x234); - - /// address: 0x50008238 - /// USB Endpoint Interrupt Clear - pub const EPINTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR0: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR1: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR2: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR3: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR4: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR5: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR6: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR7: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR8: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR9: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR10: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR11: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR12: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR13: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR14: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR15: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR16: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR17: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR18: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR19: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR20: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR21: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR22: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR23: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR24: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR25: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR26: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR27: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR28: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR29: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR30: u1, - /// 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the - /// SIE Select Endpoint/Clear Interrupt command for this endpoint. - EPCLR31: u1, - }), base_address + 0x238); - - /// address: 0x5000823c - /// USB Endpoint Interrupt Set - pub const EPINTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET0: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET1: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET2: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET3: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET4: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET5: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET6: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET7: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET8: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET9: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET10: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET11: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET12: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET13: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET14: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET15: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET16: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET17: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET18: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET19: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET20: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET21: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET22: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET23: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET24: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET25: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET26: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET27: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET28: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET29: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET30: u1, - /// 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. - EPSET31: u1, - }), base_address + 0x23c); - - /// address: 0x50008240 - /// USB Endpoint Priority - pub const EPINTPRI = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI0: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI1: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI2: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI3: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI4: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI5: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI6: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI7: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI8: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI9: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI10: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI11: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI12: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI13: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI14: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI15: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI16: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI17: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI18: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI19: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI20: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI21: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI22: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI23: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI24: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI25: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI26: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI27: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI28: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI29: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI30: u1, - /// 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = - /// The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt - EPPRI31: u1, - }), base_address + 0x240); - - /// address: 0x50008244 - /// USB Realize Endpoint - pub const REEP = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR0: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR1: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR2: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR3: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR4: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR5: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR6: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR7: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR8: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR9: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR10: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR11: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR12: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR13: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR14: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR15: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR16: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR17: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR18: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR19: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR20: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR21: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR22: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR23: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR24: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR25: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR26: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR27: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR28: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR29: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR30: u1, - /// 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. - EPR31: u1, - }), base_address + 0x244); - - /// address: 0x50008248 - /// USB Endpoint Index - pub const EPIND = @intToPtr(*volatile Mmio(32, packed struct { - /// Physical endpoint number (0-31) - PHY_EP: u5, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0x248); - - /// address: 0x5000824c - /// USB MaxPacketSize - pub const MAXPSIZE = @intToPtr(*volatile Mmio(32, packed struct { - /// The maximum packet size value. - MPS: u10, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x24c); - - /// address: 0x50008250 - /// USB DMA Request Status - pub const DMARST = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must - /// be 0). - EPRST0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be - /// 0). - EPRST1: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST2: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST3: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST4: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST5: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST6: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST7: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST8: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST9: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST10: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST11: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST12: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST13: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST14: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST15: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST16: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST17: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST18: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST19: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST20: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST21: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST22: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST23: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST24: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST25: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST26: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST27: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST28: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST29: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST30: u1, - /// Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 - /// = DMA requested by endpoint xx. - EPRST31: u1, - }), base_address + 0x250); - - /// address: 0x50008254 - /// USB DMA Request Clear - pub const DMARCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit - /// must be 0). - EPRCLR0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit - /// must be 0). - EPRCLR1: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR2: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR3: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR4: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR5: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR6: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR7: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR8: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR9: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR10: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR11: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR12: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR13: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR14: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR15: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR16: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR17: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR18: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR19: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR20: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR21: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR22: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR23: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR24: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR25: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR26: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR27: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR28: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR29: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR30: u1, - /// Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the - /// corresponding bit in USBDMARSt. - EPRCLR31: u1, - }), base_address + 0x254); - - /// address: 0x50008258 - /// USB DMA Request Set - pub const DMARSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit - /// must be 0). - EPRSET0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit - /// must be 0). - EPRSET1: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET2: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET3: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET4: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET5: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET6: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET7: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET8: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET9: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET10: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET11: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET12: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET13: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET14: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET15: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET16: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET17: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET18: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET19: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET20: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET21: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET22: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET23: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET24: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET25: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET26: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET27: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET28: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET29: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET30: u1, - /// Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the - /// corresponding bit in USBDMARSt. - EPRSET31: u1, - }), base_address + 0x258); - - /// address: 0x50008280 - /// USB UDCA Head - pub const UDCAH = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. The UDCA is - /// aligned to 128-byte boundaries. - RESERVED: u7, - /// Start address of the UDCA. - UDCA_ADDR: u25, - }), base_address + 0x280); - - /// address: 0x50008284 - /// USB Endpoint DMA Status - pub const EPDMAST = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the - /// EP0_DMA_ENABLE bit must be 0). - EP_DMA_ST0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and the - /// EP1_DMA_ENABLE bit must be 0). - EP_DMA_ST1: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST2: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST3: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST4: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST5: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST6: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST7: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST8: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST9: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST10: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST11: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST12: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST13: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST14: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST15: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST16: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST17: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST18: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST19: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST20: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST21: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST22: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST23: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST24: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST25: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST26: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST27: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST28: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST29: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST30: u1, - /// Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is - /// disabled. 1 = The DMA for endpoint EPxx is enabled. - EP_DMA_ST31: u1, - }), base_address + 0x284); - - /// address: 0x50008288 - /// USB Endpoint DMA Enable - pub const EPDMAEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the - /// EP0_DMA_ENABLE bit value must be 0). - EP_DMA_EN0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and the - /// EP1_DMA_ENABLE bit must be 0). - EP_DMA_EN1: u1, - /// Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the - /// DMA operation for endpoint EPxx. - EP_DMA_EN: u30, - }), base_address + 0x288); - - /// address: 0x5000828c - /// USB Endpoint DMA Disable - pub const EPDMADIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Control endpoint OUT (DMA cannot be enabled for this endpoint and the - /// EP0_DMA_DISABLE bit value must be 0). - EP_DMA_DIS0: u1, - /// Control endpoint IN (DMA cannot be enabled for this endpoint and the - /// EP1_DMA_DISABLE bit value must be 0). - EP_DMA_DIS1: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS2: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS3: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS4: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS5: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS6: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS7: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS8: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS9: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS10: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS11: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS12: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS13: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS14: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS15: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS16: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS17: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS18: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS19: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS20: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS21: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS22: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS23: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS24: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS25: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS26: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS27: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS28: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS29: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS30: u1, - /// Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable - /// the DMA operation for endpoint EPxx. - EP_DMA_DIS31: u1, - }), base_address + 0x28c); - - /// address: 0x50008290 - /// USB DMA Interrupt Status - pub const DMAINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// End of Transfer Interrupt bit. - EOT: u1, - /// New DD Request Interrupt bit. - NDDR: u1, - /// System Error Interrupt bit. - ERR: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u29, - }), base_address + 0x290); - - /// address: 0x50008294 - /// USB DMA Interrupt Enable - pub const DMAINTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// End of Transfer Interrupt enable bit. - EOT: u1, - /// New DD Request Interrupt enable bit. - NDDR: u1, - /// System Error Interrupt enable bit. - ERR: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u29, - }), base_address + 0x294); - - /// address: 0x500082a0 - /// USB End of Transfer Interrupt Status - pub const EOTINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST0: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST1: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST2: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST3: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST4: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST5: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST6: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST7: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST8: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST9: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST10: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST11: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST12: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST13: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST14: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST15: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST16: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST17: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST18: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST19: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST20: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST21: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST22: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST23: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST24: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST25: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST26: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST27: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST28: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST29: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST30: u1, - /// Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no - /// End of Transfer interrupt request for endpoint xx. 1 = There is an End of - /// Transfer Interrupt request for endpoint xx. - EPTXINTST31: u1, - }), base_address + 0x2a0); - - /// address: 0x500082a4 - /// USB End of Transfer Interrupt Clear - pub const EOTINTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR0: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR1: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR2: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR3: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR4: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR5: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR6: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR7: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR8: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR9: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR10: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR11: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR12: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR13: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR14: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR15: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR16: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR17: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR18: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR19: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR20: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR21: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR22: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR23: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR24: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR25: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR26: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR27: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR28: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR29: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR30: u1, - /// Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTCLR31: u1, - }), base_address + 0x2a4); - - /// address: 0x500082a8 - /// USB End of Transfer Interrupt Set - pub const EOTINTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET0: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET1: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET2: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET3: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET4: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET5: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET6: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET7: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET8: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET9: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET10: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET11: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET12: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET13: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET14: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET15: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET16: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET17: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET18: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET19: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET20: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET21: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET22: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET23: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET24: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET25: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET26: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET27: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET28: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET29: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET30: u1, - /// Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No - /// effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt - /// register. - EPTXINTSET31: u1, - }), base_address + 0x2a8); - - /// address: 0x500082ac - /// USB New DD Request Interrupt Status - pub const NDDRINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST0: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST1: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST2: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST3: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST4: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST5: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST6: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST7: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST8: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST9: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST10: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST11: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST12: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST13: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST14: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST15: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST16: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST17: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST18: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST19: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST20: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST21: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST22: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST23: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST24: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST25: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST26: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST27: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST28: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST29: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST30: u1, - /// Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD - /// interrupt request for endpoint xx. 1 = There is a new DD interrupt request for - /// endpoint xx. - EPNDDINTST31: u1, - }), base_address + 0x2ac); - - /// address: 0x500082b0 - /// USB New DD Request Interrupt Clear - pub const NDDRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR0: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR1: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR2: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR3: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR4: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR5: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR6: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR7: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR8: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR9: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR10: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR11: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR12: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR13: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR14: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR15: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR16: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR17: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR18: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR19: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR20: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR21: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR22: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR23: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR24: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR25: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR26: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR27: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR28: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR29: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR30: u1, - /// Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = - /// Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTCLR31: u1, - }), base_address + 0x2b0); - - /// address: 0x500082b4 - /// USB New DD Request Interrupt Set - pub const NDDRINTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET0: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET1: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET2: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET3: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET4: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET5: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET6: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET7: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET8: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET9: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET10: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET11: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET12: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET13: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET14: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET15: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET16: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET17: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET18: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET19: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET20: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET21: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET22: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET23: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET24: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET25: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET26: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET27: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET28: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET29: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET30: u1, - /// Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set - /// the EPxx new DD interrupt request in the USBNDDRIntSt register. - EPNDDINTSET31: u1, - }), base_address + 0x2b4); - - /// address: 0x500082b8 - /// USB System Error Interrupt Status - pub const SYSERRINTST = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST0: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST1: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST2: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST3: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST4: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST5: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST6: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST7: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST8: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST9: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST10: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST11: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST12: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST13: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST14: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST15: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST16: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST17: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST18: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST19: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST20: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST21: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST22: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST23: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST24: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST25: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST26: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST27: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST28: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST29: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST30: u1, - /// Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no - /// System Error Interrupt request for endpoint xx. 1 = There is a System Error - /// Interrupt request for endpoint xx. - EPERRINTST31: u1, - }), base_address + 0x2b8); - - /// address: 0x500082bc - /// USB System Error Interrupt Clear - pub const SYSERRINTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR0: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR1: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR2: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR3: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR4: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR5: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR6: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR7: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR8: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR9: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR10: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR11: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR12: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR13: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR14: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR15: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR16: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR17: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR18: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR19: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR20: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR21: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR22: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR23: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR24: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR25: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR26: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR27: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR28: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR29: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR30: u1, - /// Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. - /// 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt - /// register. - EPERRINTCLR31: u1, - }), base_address + 0x2bc); - - /// address: 0x500082c0 - /// USB System Error Interrupt Set - pub const SYSERRINTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET0: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET1: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET2: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET3: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET4: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET5: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET6: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET7: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET8: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET9: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET10: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET11: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET12: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET13: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET14: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET15: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET16: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET17: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET18: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET19: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET20: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET21: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET22: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET23: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET24: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET25: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET26: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET27: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET28: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET29: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET30: u1, - /// Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 - /// = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. - EPERRINTSET31: u1, - }), base_address + 0x2c0); - - /// address: 0x50008300 - /// I2C Receive - pub const I2C_RX = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive data. - RXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x300); - - /// address: 0x50008300 - /// I2C Transmit - pub const I2C_WO = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit data. - TXDATA: u8, - /// When 1, issue a START condition before transmitting this byte. - START: u1, - /// When 1, issue a STOP condition after transmitting this byte. - STOP: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u22, - }), base_address + 0x300); - - /// address: 0x50008304 - /// I2C Status - pub const I2C_STS = @intToPtr(*volatile Mmio(32, packed struct { - /// Transaction Done Interrupt. This flag is set if a transaction completes - /// successfully. It is cleared by writing a one to bit 0 of the status register. It - /// is unaffected by slave transactions. - TDI: u1, - /// Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT - /// is high, then this I2C has lost the arbitration to another device on the bus. - /// The Arbitration Failure bit is set when this happens. It is cleared by writing a - /// one to bit 1 of the status register. - AFI: u1, - /// No Acknowledge Interrupt. After every byte of data is sent, the transmitter - /// expects an acknowledge from the receiver. This bit is set if the acknowledge is - /// not received. It is cleared when a byte is written to the master TX FIFO. - NAI: u1, - /// Master Data Request Interrupt. Once a transmission is started, the transmitter - /// must have data to transmit as long as it isn't followed by a stop condition or - /// it will hold SCL low until more data is available. The Master Data Request bit - /// is set when the master transmitter is data-starved. If the master TX FIFO is - /// empty and the last byte did not have a STOP condition flag, then SCL is held low - /// until the CPU writes another byte to transmit. This bit is cleared when a byte - /// is written to the master TX FIFO. - DRMI: u1, - /// Slave Data Request Interrupt. Once a transmission is started, the transmitter - /// must have data to transmit as long as it isn't followed by a STOP condition or - /// it will hold SCL low until more data is available. The Slave Data Request bit is - /// set when the slave transmitter is data-starved. If the slave TX FIFO is empty - /// and the last byte transmitted was acknowledged, then SCL is held low until the - /// CPU writes another byte to transmit. This bit is cleared when a byte is written - /// to the slave Tx FIFO. - DRSI: u1, - /// Indicates whether the bus is busy. This bit is set when a START condition has - /// been seen. It is cleared when a STOP condition is seen.. - Active: u1, - /// The current value of the SCL signal. - SCL: u1, - /// The current value of the SDA signal. - SDA: u1, - /// Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot - /// accept any more data. It is cleared when the RX FIFO is not full. If a byte - /// arrives when the Receive FIFO is full, the SCL is held low until the CPU reads - /// the RX FIFO and makes room for it. - RFF: u1, - /// Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the - /// RX FIFO contains valid data. - RFE: u1, - /// Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the - /// TX FIFO is not full. - TFF: u1, - /// Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when - /// the TX FIFO contains valid data. - TFE: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u20, - }), base_address + 0x304); - - /// address: 0x50008308 - /// I2C Control - pub const I2C_CTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that - /// this I2C issued a STOP condition. - TDIE: u1, - /// Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt - /// which is asserted during transmission when trying to set SDA high, but the bus - /// is driven low by another device. - AFIE: u1, - /// Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt - /// signalling that transmitted byte was not acknowledged. - NAIE: u1, - /// Master Transmitter Data Request Interrupt Enable. This enables the DRMI - /// interrupt which signals that the master transmitter has run out of data, has not - /// issued a STOP, and is holding the SCL line low. - DRMIE: u1, - /// Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt - /// which signals that the slave transmitter has run out of data and the last byte - /// was acknowledged, so the SCL line is being held low. - DRSIE: u1, - /// Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt - /// to indicate that the receive FIFO cannot accept any more data. - REFIE: u1, - /// Receive Data Available Interrupt Enable. This enables the DAI interrupt to - /// indicate that data is available in the receive FIFO (i.e. not empty). - RFDAIE: u1, - /// Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full - /// interrupt to indicate that the more data can be written to the transmit FIFO. - /// Note that this is not full. It is intended help the CPU to write to the I2C - /// block only when there is room in the FIFO and do this without polling the status - /// register. - TFFIE: u1, - /// Soft reset. This is only needed in unusual circumstances. If a device issues a - /// start condition without issuing a stop condition. A system timer may be used to - /// reset the I2C if the bus remains busy longer than the time-out period. On a soft - /// reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all - /// internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and - /// I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. - SRST: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u23, - }), base_address + 0x308); - - /// address: 0x5000830c - /// I2C Clock High - pub const I2C_CLKHI = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock divisor high. This value is the number of 48 MHz clocks the serial clock - /// (SCL) will be high. - CDHI: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x30c); - - /// address: 0x50008310 - /// I2C Clock Low - pub const I2C_CLKLO = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock divisor low. This value is the number of 48 MHz clocks the serial clock - /// (SCL) will be low. - CDLO: u8, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u24, - }), base_address + 0x310); - - /// address: 0x50008ff4 - /// USB Clock Control - pub const USBCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Device clock enable. Enables the usbclk input to the device controller - DEV_CLK_EN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Port select register clock enable. - PORTSEL_CLK_EN: u1, - /// AHB clock enable - AHB_CLK_EN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0xff4); - - /// address: 0x50008ff4 - /// OTG clock controller - pub const OTGCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Host clock enable - HOST_CLK_EN: u1, - /// Device clock enable - DEV_CLK_EN: u1, - /// I2C clock enable - I2C_CLK_EN: u1, - /// OTG clock enable. In device-only applications, this bit enables access to the - /// PORTSEL register. - OTG_CLK_EN: u1, - /// AHB master clock enable - AHB_CLK_EN: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0xff4); - - /// address: 0x50008ff8 - /// USB Clock Status - pub const USBCLKST = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Device clock on. The usbclk input to the device controller is active . - DEV_CLK_ON: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u1, - /// Port select register clock on. - PORTSEL_CLK_ON: u1, - /// AHB clock on. - AHB_CLK_ON: u1, - /// Reserved. The value read from a reserved bit is not defined. - RESERVED: u27, - }), base_address + 0xff8); - - /// address: 0x50008ff8 - /// OTG clock status - pub const OTGCLKST = @intToPtr(*volatile Mmio(32, packed struct { - /// Host clock status. - HOST_CLK_ON: u1, - /// Device clock status. - DEV_CLK_ON: u1, - /// I2C clock status. - I2C_CLK_ON: u1, - /// OTG clock status. - OTG_CLK_ON: u1, - /// AHB master clock status. - AHB_CLK_ON: u1, - /// Reserved. Read value is undefined, only zero should be written. - RESERVED: u27, - }), base_address + 0xff8); - }; - /// General Purpose I/O - pub const GPIO = struct { - pub const base_address = 0x2009c000; - - /// address: 0x2009c000 - /// GPIO Port Direction control register. - pub const DIR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR0: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR1: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR2: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR3: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR4: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR5: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR6: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR7: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR8: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR9: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR10: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR11: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR12: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR13: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR14: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR15: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR16: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR17: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR18: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR19: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR20: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR21: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR22: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR23: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR24: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR25: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR26: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR27: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR28: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR29: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR30: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR31: u1, - }), base_address + 0x0); - - /// address: 0x2009c020 - /// GPIO Port Direction control register. - pub const DIR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR0: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR1: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR2: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR3: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR4: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR5: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR6: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR7: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR8: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR9: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR10: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR11: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR12: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR13: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR14: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR15: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR16: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR17: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR18: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR19: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR20: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR21: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR22: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR23: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR24: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR25: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR26: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR27: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR28: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR29: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR30: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR31: u1, - }), base_address + 0x20); - - /// address: 0x2009c040 - /// GPIO Port Direction control register. - pub const DIR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR0: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR1: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR2: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR3: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR4: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR5: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR6: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR7: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR8: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR9: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR10: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR11: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR12: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR13: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR14: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR15: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR16: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR17: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR18: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR19: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR20: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR21: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR22: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR23: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR24: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR25: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR26: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR27: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR28: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR29: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR30: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR31: u1, - }), base_address + 0x40); - - /// address: 0x2009c060 - /// GPIO Port Direction control register. - pub const DIR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR0: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR1: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR2: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR3: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR4: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR5: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR6: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR7: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR8: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR9: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR10: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR11: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR12: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR13: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR14: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR15: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR16: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR17: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR18: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR19: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR20: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR21: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR22: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR23: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR24: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR25: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR26: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR27: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR28: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR29: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR30: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR31: u1, - }), base_address + 0x60); - - /// address: 0x2009c080 - /// GPIO Port Direction control register. - pub const DIR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR0: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR1: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR2: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR3: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR4: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR5: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR6: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR7: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR8: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR9: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR10: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR11: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR12: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR13: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR14: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR15: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR16: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR17: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR18: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR19: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR20: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR21: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR22: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR23: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR24: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR25: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR26: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR27: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR28: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR29: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR30: u1, - /// Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 - /// in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is - /// output. - PINDIR31: u1, - }), base_address + 0x80); - - /// address: 0x2009c010 - /// Mask register for Port. - pub const MASK0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK0: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK1: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK2: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK3: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK4: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK5: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK6: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK7: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK8: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK9: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK10: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK11: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK12: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK13: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK14: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK15: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK16: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK17: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK18: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK19: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK20: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK21: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK22: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK23: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK24: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK25: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK26: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK27: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK28: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK29: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK30: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK31: u1, - }), base_address + 0x10); - - /// address: 0x2009c030 - /// Mask register for Port. - pub const MASK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK0: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK1: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK2: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK3: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK4: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK5: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK6: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK7: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK8: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK9: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK10: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK11: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK12: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK13: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK14: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK15: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK16: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK17: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK18: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK19: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK20: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK21: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK22: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK23: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK24: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK25: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK26: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK27: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK28: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK29: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK30: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK31: u1, - }), base_address + 0x30); - - /// address: 0x2009c050 - /// Mask register for Port. - pub const MASK2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK0: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK1: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK2: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK3: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK4: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK5: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK6: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK7: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK8: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK9: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK10: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK11: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK12: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK13: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK14: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK15: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK16: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK17: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK18: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK19: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK20: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK21: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK22: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK23: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK24: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK25: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK26: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK27: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK28: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK29: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK30: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK31: u1, - }), base_address + 0x50); - - /// address: 0x2009c070 - /// Mask register for Port. - pub const MASK3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK0: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK1: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK2: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK3: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK4: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK5: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK6: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK7: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK8: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK9: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK10: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK11: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK12: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK13: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK14: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK15: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK16: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK17: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK18: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK19: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK20: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK21: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK22: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK23: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK24: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK25: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK26: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK27: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK28: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK29: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK30: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK31: u1, - }), base_address + 0x70); - - /// address: 0x2009c090 - /// Mask register for Port. - pub const MASK4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK0: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK1: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK2: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK3: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK4: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK5: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK6: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK7: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK8: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK9: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK10: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK11: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK12: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK13: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK14: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK15: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK16: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK17: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK18: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK19: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK20: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK21: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK22: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK23: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK24: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK25: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK26: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK27: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK28: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK29: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK30: u1, - /// Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes - /// to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be - /// read from the PINx register. 1 = Controlled pin is not affected by writes into - /// the port's SETx, CLRx and PINx register(s). When the PINx register is read, this - /// bit will not be updated with the state of the physical pin. - PINMASK31: u1, - }), base_address + 0x90); - - /// address: 0x2009c014 - /// Port Pin value register using FIOMASK. - pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL0: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL1: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL2: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL3: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL4: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL5: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL6: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL7: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL8: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL9: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL10: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL11: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL12: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL13: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL14: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL15: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL16: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL17: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL18: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL19: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL20: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL21: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL22: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL23: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL24: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL25: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL26: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL27: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL28: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL29: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL30: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL31: u1, - }), base_address + 0x14); - - /// address: 0x2009c034 - /// Port Pin value register using FIOMASK. - pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL0: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL1: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL2: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL3: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL4: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL5: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL6: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL7: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL8: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL9: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL10: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL11: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL12: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL13: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL14: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL15: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL16: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL17: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL18: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL19: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL20: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL21: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL22: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL23: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL24: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL25: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL26: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL27: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL28: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL29: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL30: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL31: u1, - }), base_address + 0x34); - - /// address: 0x2009c054 - /// Port Pin value register using FIOMASK. - pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL0: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL1: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL2: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL3: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL4: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL5: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL6: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL7: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL8: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL9: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL10: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL11: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL12: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL13: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL14: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL15: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL16: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL17: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL18: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL19: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL20: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL21: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL22: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL23: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL24: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL25: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL26: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL27: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL28: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL29: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL30: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL31: u1, - }), base_address + 0x54); - - /// address: 0x2009c074 - /// Port Pin value register using FIOMASK. - pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL0: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL1: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL2: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL3: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL4: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL5: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL6: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL7: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL8: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL9: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL10: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL11: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL12: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL13: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL14: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL15: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL16: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL17: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL18: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL19: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL20: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL21: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL22: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL23: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL24: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL25: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL26: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL27: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL28: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL29: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL30: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL31: u1, - }), base_address + 0x74); - - /// address: 0x2009c094 - /// Port Pin value register using FIOMASK. - pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL0: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL1: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL2: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL3: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL4: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL5: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL6: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL7: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL8: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL9: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL10: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL11: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL12: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL13: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL14: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL15: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL16: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL17: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL18: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL19: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL20: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL21: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL22: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL23: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL24: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL25: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL26: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL27: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL28: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL29: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL30: u1, - /// Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 - /// in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = - /// Controlled pin output is set to HIGH. - PINVAL31: u1, - }), base_address + 0x94); - - /// address: 0x2009c018 - /// Port Output Set register using FIOMASK. - pub const SET0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET0: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET1: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET2: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET3: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET4: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET5: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET6: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET7: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET8: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET9: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET10: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET11: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET12: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET13: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET14: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET15: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET16: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET17: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET18: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET19: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET20: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET21: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET22: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET23: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET24: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET25: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET26: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET27: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET28: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET29: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET30: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET31: u1, - }), base_address + 0x18); - - /// address: 0x2009c038 - /// Port Output Set register using FIOMASK. - pub const SET1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET0: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET1: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET2: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET3: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET4: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET5: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET6: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET7: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET8: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET9: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET10: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET11: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET12: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET13: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET14: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET15: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET16: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET17: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET18: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET19: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET20: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET21: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET22: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET23: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET24: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET25: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET26: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET27: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET28: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET29: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET30: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET31: u1, - }), base_address + 0x38); - - /// address: 0x2009c058 - /// Port Output Set register using FIOMASK. - pub const SET2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET0: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET1: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET2: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET3: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET4: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET5: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET6: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET7: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET8: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET9: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET10: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET11: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET12: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET13: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET14: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET15: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET16: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET17: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET18: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET19: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET20: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET21: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET22: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET23: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET24: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET25: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET26: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET27: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET28: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET29: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET30: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET31: u1, - }), base_address + 0x58); - - /// address: 0x2009c078 - /// Port Output Set register using FIOMASK. - pub const SET3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET0: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET1: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET2: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET3: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET4: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET5: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET6: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET7: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET8: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET9: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET10: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET11: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET12: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET13: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET14: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET15: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET16: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET17: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET18: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET19: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET20: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET21: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET22: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET23: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET24: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET25: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET26: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET27: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET28: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET29: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET30: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET31: u1, - }), base_address + 0x78); - - /// address: 0x2009c098 - /// Port Output Set register using FIOMASK. - pub const SET4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET0: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET1: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET2: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET3: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET4: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET5: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET6: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET7: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET8: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET9: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET10: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET11: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET12: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET13: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET14: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET15: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET16: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET17: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET18: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET19: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET20: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET21: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET22: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET23: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET24: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET25: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET26: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET27: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET28: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET29: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET30: u1, - /// Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in - /// SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to HIGH. - PINSET31: u1, - }), base_address + 0x98); - - /// address: 0x2009c01c - /// Port Output Clear register using FIOMASK. - pub const CLR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR0: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR1: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR2: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR3: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR4: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR5: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR6: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR7: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR8: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR9: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR10: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR11: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR12: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR13: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR14: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR15: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR16: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR17: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR18: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR19: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR20: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR21: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR22: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR23: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR24: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR25: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR26: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR27: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR28: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR29: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR30: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR31: u1, - }), base_address + 0x1c); - - /// address: 0x2009c03c - /// Port Output Clear register using FIOMASK. - pub const CLR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR0: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR1: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR2: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR3: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR4: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR5: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR6: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR7: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR8: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR9: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR10: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR11: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR12: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR13: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR14: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR15: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR16: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR17: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR18: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR19: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR20: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR21: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR22: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR23: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR24: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR25: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR26: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR27: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR28: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR29: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR30: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR31: u1, - }), base_address + 0x3c); - - /// address: 0x2009c05c - /// Port Output Clear register using FIOMASK. - pub const CLR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR0: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR1: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR2: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR3: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR4: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR5: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR6: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR7: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR8: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR9: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR10: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR11: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR12: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR13: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR14: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR15: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR16: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR17: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR18: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR19: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR20: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR21: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR22: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR23: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR24: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR25: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR26: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR27: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR28: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR29: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR30: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR31: u1, - }), base_address + 0x5c); - - /// address: 0x2009c07c - /// Port Output Clear register using FIOMASK. - pub const CLR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR0: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR1: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR2: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR3: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR4: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR5: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR6: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR7: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR8: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR9: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR10: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR11: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR12: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR13: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR14: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR15: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR16: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR17: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR18: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR19: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR20: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR21: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR22: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR23: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR24: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR25: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR26: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR27: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR28: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR29: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR30: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR31: u1, - }), base_address + 0x7c); - - /// address: 0x2009c09c - /// Port Output Clear register using FIOMASK. - pub const CLR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR0: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR1: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR2: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR3: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR4: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR5: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR6: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR7: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR8: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR9: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR10: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR11: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR12: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR13: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR14: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR15: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR16: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR17: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR18: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR19: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR20: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR21: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR22: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR23: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR24: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR25: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR26: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR27: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR28: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR29: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR30: u1, - /// Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in - /// CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled - /// pin output is set to LOW. - PINCLR31: u1, - }), base_address + 0x9c); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: *const fn () callconv(.C) void, - Naked: *const fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/nrf52/nrf52.zig b/src/modules/chips/nrf52/nrf52.zig deleted file mode 100644 index f9865cd..0000000 --- a/src/modules/chips/nrf52/nrf52.zig +++ /dev/null @@ -1,3 +0,0 @@ -pub const cpu = @import("cpu"); -pub const registers = @import("registers.zig"); -pub const VectorTable = registers.VectorTable; diff --git a/src/modules/chips/nrf52/registers.zig b/src/modules/chips/nrf52/registers.zig deleted file mode 100644 index a2333fd..0000000 --- a/src/modules/chips/nrf52/registers.zig +++ /dev/null @@ -1,16816 +0,0 @@ -// this file is generated by regz -// -// vendor: Nordic Semiconductor -// device: nrf52 -// cpu: CM4 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - POWER_CLOCK: InterruptVector = unhandled, - RADIO: InterruptVector = unhandled, - UARTE0_UART0: InterruptVector = unhandled, - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: InterruptVector = unhandled, - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: InterruptVector = unhandled, - NFCT: InterruptVector = unhandled, - GPIOTE: InterruptVector = unhandled, - SAADC: InterruptVector = unhandled, - TIMER0: InterruptVector = unhandled, - TIMER1: InterruptVector = unhandled, - TIMER2: InterruptVector = unhandled, - RTC0: InterruptVector = unhandled, - TEMP: InterruptVector = unhandled, - RNG: InterruptVector = unhandled, - ECB: InterruptVector = unhandled, - CCM_AAR: InterruptVector = unhandled, - WDT: InterruptVector = unhandled, - RTC1: InterruptVector = unhandled, - QDEC: InterruptVector = unhandled, - COMP_LPCOMP: InterruptVector = unhandled, - SWI0_EGU0: InterruptVector = unhandled, - SWI1_EGU1: InterruptVector = unhandled, - SWI2_EGU2: InterruptVector = unhandled, - SWI3_EGU3: InterruptVector = unhandled, - SWI4_EGU4: InterruptVector = unhandled, - SWI5_EGU5: InterruptVector = unhandled, - TIMER3: InterruptVector = unhandled, - TIMER4: InterruptVector = unhandled, - PWM0: InterruptVector = unhandled, - PDM: InterruptVector = unhandled, - reserved2: u32 = undefined, - reserved3: u32 = undefined, - MWU: InterruptVector = unhandled, - PWM1: InterruptVector = unhandled, - PWM2: InterruptVector = unhandled, - SPIM2_SPIS2_SPI2: InterruptVector = unhandled, - RTC2: InterruptVector = unhandled, - I2S: InterruptVector = unhandled, - FPU: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// Factory Information Configuration Registers - pub const FICR = struct { - pub const base_address = 0x10000000; - - /// address: 0x10000010 - /// Code memory page size - pub const CODEPAGESIZE = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x10000014 - /// Code memory size - pub const CODESIZE = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x10000060 - /// Description collection[0]: Device identifier - pub const DEVICEID = @intToPtr(*volatile [2]u32, base_address + 0x60); - - /// address: 0x10000080 - /// Description collection[0]: Encryption Root, word 0 - pub const ER = @intToPtr(*volatile [4]u32, base_address + 0x80); - - /// address: 0x10000090 - /// Description collection[0]: Identity Root, word 0 - pub const IR = @intToPtr(*volatile [4]u32, base_address + 0x90); - - /// address: 0x100000a0 - /// Device address type - pub const DEVICEADDRTYPE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa0); - - /// address: 0x100000a4 - /// Description collection[0]: Device address 0 - pub const DEVICEADDR = @intToPtr(*volatile [2]u32, base_address + 0xa4); - - /// Device info - pub const INFO = struct { - /// address: 0x10000000 - /// Part code - pub const PART = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x10000004 - /// Part Variant, Hardware version and Production configuration - pub const VARIANT = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x10000008 - /// Package option - pub const PACKAGE = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x1000000c - /// RAM variant - pub const RAM = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x10000010 - /// Flash variant - pub const FLASH = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x10000014 - /// Description collection[0]: Unspecified - pub const UNUSED0 = @intToPtr(*volatile [3]u32, base_address + 0x14); - }; - - /// Registers storing factory TEMP module linearization coefficients - pub const TEMP = struct { - /// address: 0x10000000 - /// Slope definition A0. - pub const A0 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x10000004 - /// Slope definition A1. - pub const A1 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x10000008 - /// Slope definition A2. - pub const A2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x1000000c - /// Slope definition A3. - pub const A3 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0xc); - - /// address: 0x10000010 - /// Slope definition A4. - pub const A4 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x10); - - /// address: 0x10000014 - /// Slope definition A5. - pub const A5 = @intToPtr(*volatile Mmio(32, packed struct { - /// A (slope definition) register. - A: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x10000018 - /// y-intercept B0. - pub const B0 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x18); - - /// address: 0x1000001c - /// y-intercept B1. - pub const B1 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c); - - /// address: 0x10000020 - /// y-intercept B2. - pub const B2 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x10000024 - /// y-intercept B3. - pub const B3 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x24); - - /// address: 0x10000028 - /// y-intercept B4. - pub const B4 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x28); - - /// address: 0x1000002c - /// y-intercept B5. - pub const B5 = @intToPtr(*volatile Mmio(32, packed struct { - /// B (y-intercept) - B: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x2c); - - /// address: 0x10000030 - /// Segment end T0. - pub const T0 = @intToPtr(*volatile Mmio(32, packed struct { - /// T (segment end)register. - T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x10000034 - /// Segment end T1. - pub const T1 = @intToPtr(*volatile Mmio(32, packed struct { - /// T (segment end)register. - T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x34); - - /// address: 0x10000038 - /// Segment end T2. - pub const T2 = @intToPtr(*volatile Mmio(32, packed struct { - /// T (segment end)register. - T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x38); - - /// address: 0x1000003c - /// Segment end T3. - pub const T3 = @intToPtr(*volatile Mmio(32, packed struct { - /// T (segment end)register. - T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x3c); - - /// address: 0x10000040 - /// Segment end T4. - pub const T4 = @intToPtr(*volatile Mmio(32, packed struct { - /// T (segment end)register. - T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x40); - }; - - pub const NFC = struct { - /// address: 0x10000000 - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F - MFGID: u8, - /// Unique identifier byte 1 - UD1: u8, - /// Unique identifier byte 2 - UD2: u8, - /// Unique identifier byte 3 - UD3: u8, - }), base_address + 0x0); - - /// address: 0x10000004 - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Unique identifier byte 4 - UD4: u8, - /// Unique identifier byte 5 - UD5: u8, - /// Unique identifier byte 6 - UD6: u8, - /// Unique identifier byte 7 - UD7: u8, - }), base_address + 0x4); - - /// address: 0x10000008 - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Unique identifier byte 8 - UD8: u8, - /// Unique identifier byte 9 - UD9: u8, - /// Unique identifier byte 10 - UD10: u8, - /// Unique identifier byte 11 - UD11: u8, - }), base_address + 0x8); - - /// address: 0x1000000c - /// Default header for NFC Tag. Software can read these values to populate - /// NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. - pub const TAGHEADER3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Unique identifier byte 12 - UD12: u8, - /// Unique identifier byte 13 - UD13: u8, - /// Unique identifier byte 14 - UD14: u8, - /// Unique identifier byte 15 - UD15: u8, - }), base_address + 0xc); - }; - }; - /// User Information Configuration Registers - pub const UICR = struct { - pub const base_address = 0x10001000; - - /// address: 0x10001000 - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x10001004 - /// Unspecified - pub const UNUSED1 = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x10001008 - /// Unspecified - pub const UNUSED2 = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x10001010 - /// Unspecified - pub const UNUSED3 = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x10001014 - /// Description collection[0]: Reserved for Nordic firmware design - pub const NRFFW = @intToPtr(*volatile [15]u32, base_address + 0x14); - - /// address: 0x10001050 - /// Description collection[0]: Reserved for Nordic hardware design - pub const NRFHW = @intToPtr(*volatile [12]u32, base_address + 0x50); - - /// address: 0x10001080 - /// Description collection[0]: Reserved for customer - pub const CUSTOMER = @intToPtr(*volatile [32]u32, base_address + 0x80); - - /// address: 0x10001200 - /// Description collection[0]: Mapping of the nRESET function (see POWER chapter for - /// details) - pub const PSELRESET = @intToPtr(*volatile [2]Mmio(32, packed struct { - /// GPIO number P0.n onto which Reset is exposed - PIN: u6, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x200); - - /// address: 0x10001208 - /// Access Port protection - pub const APPROTECT = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable Access Port protection. Any other value than 0xFF being - /// written to this field will enable protection. - PALL: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x208); - - /// address: 0x1000120c - /// Setting of pins dedicated to NFC functionality: NFC antenna or GPIO - pub const NFCPINS = @intToPtr(*volatile Mmio(32, packed struct { - /// Setting of pins dedicated to NFC functionality - PROTECT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x20c); - }; - /// Block Protect - pub const BPROT = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000600 - /// Block protect configuration register 0 - pub const CONFIG0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable protection for region 0. Write '0' has no effect. - REGION0: u1, - /// Enable protection for region 1. Write '0' has no effect. - REGION1: u1, - /// Enable protection for region 2. Write '0' has no effect. - REGION2: u1, - /// Enable protection for region 3. Write '0' has no effect. - REGION3: u1, - /// Enable protection for region 4. Write '0' has no effect. - REGION4: u1, - /// Enable protection for region 5. Write '0' has no effect. - REGION5: u1, - /// Enable protection for region 6. Write '0' has no effect. - REGION6: u1, - /// Enable protection for region 7. Write '0' has no effect. - REGION7: u1, - /// Enable protection for region 8. Write '0' has no effect. - REGION8: u1, - /// Enable protection for region 9. Write '0' has no effect. - REGION9: u1, - /// Enable protection for region 10. Write '0' has no effect. - REGION10: u1, - /// Enable protection for region 11. Write '0' has no effect. - REGION11: u1, - /// Enable protection for region 12. Write '0' has no effect. - REGION12: u1, - /// Enable protection for region 13. Write '0' has no effect. - REGION13: u1, - /// Enable protection for region 14. Write '0' has no effect. - REGION14: u1, - /// Enable protection for region 15. Write '0' has no effect. - REGION15: u1, - /// Enable protection for region 16. Write '0' has no effect. - REGION16: u1, - /// Enable protection for region 17. Write '0' has no effect. - REGION17: u1, - /// Enable protection for region 18. Write '0' has no effect. - REGION18: u1, - /// Enable protection for region 19. Write '0' has no effect. - REGION19: u1, - /// Enable protection for region 20. Write '0' has no effect. - REGION20: u1, - /// Enable protection for region 21. Write '0' has no effect. - REGION21: u1, - /// Enable protection for region 22. Write '0' has no effect. - REGION22: u1, - /// Enable protection for region 23. Write '0' has no effect. - REGION23: u1, - /// Enable protection for region 24. Write '0' has no effect. - REGION24: u1, - /// Enable protection for region 25. Write '0' has no effect. - REGION25: u1, - /// Enable protection for region 26. Write '0' has no effect. - REGION26: u1, - /// Enable protection for region 27. Write '0' has no effect. - REGION27: u1, - /// Enable protection for region 28. Write '0' has no effect. - REGION28: u1, - /// Enable protection for region 29. Write '0' has no effect. - REGION29: u1, - /// Enable protection for region 30. Write '0' has no effect. - REGION30: u1, - /// Enable protection for region 31. Write '0' has no effect. - REGION31: u1, - }), base_address + 0x600); - - /// address: 0x40000604 - /// Block protect configuration register 1 - pub const CONFIG1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable protection for region 32. Write '0' has no effect. - REGION32: u1, - /// Enable protection for region 33. Write '0' has no effect. - REGION33: u1, - /// Enable protection for region 34. Write '0' has no effect. - REGION34: u1, - /// Enable protection for region 35. Write '0' has no effect. - REGION35: u1, - /// Enable protection for region 36. Write '0' has no effect. - REGION36: u1, - /// Enable protection for region 37. Write '0' has no effect. - REGION37: u1, - /// Enable protection for region 38. Write '0' has no effect. - REGION38: u1, - /// Enable protection for region 39. Write '0' has no effect. - REGION39: u1, - /// Enable protection for region 40. Write '0' has no effect. - REGION40: u1, - /// Enable protection for region 41. Write '0' has no effect. - REGION41: u1, - /// Enable protection for region 42. Write '0' has no effect. - REGION42: u1, - /// Enable protection for region 43. Write '0' has no effect. - REGION43: u1, - /// Enable protection for region 44. Write '0' has no effect. - REGION44: u1, - /// Enable protection for region 45. Write '0' has no effect. - REGION45: u1, - /// Enable protection for region 46. Write '0' has no effect. - REGION46: u1, - /// Enable protection for region 47. Write '0' has no effect. - REGION47: u1, - /// Enable protection for region 48. Write '0' has no effect. - REGION48: u1, - /// Enable protection for region 49. Write '0' has no effect. - REGION49: u1, - /// Enable protection for region 50. Write '0' has no effect. - REGION50: u1, - /// Enable protection for region 51. Write '0' has no effect. - REGION51: u1, - /// Enable protection for region 52. Write '0' has no effect. - REGION52: u1, - /// Enable protection for region 53. Write '0' has no effect. - REGION53: u1, - /// Enable protection for region 54. Write '0' has no effect. - REGION54: u1, - /// Enable protection for region 55. Write '0' has no effect. - REGION55: u1, - /// Enable protection for region 56. Write '0' has no effect. - REGION56: u1, - /// Enable protection for region 57. Write '0' has no effect. - REGION57: u1, - /// Enable protection for region 58. Write '0' has no effect. - REGION58: u1, - /// Enable protection for region 59. Write '0' has no effect. - REGION59: u1, - /// Enable protection for region 60. Write '0' has no effect. - REGION60: u1, - /// Enable protection for region 61. Write '0' has no effect. - REGION61: u1, - /// Enable protection for region 62. Write '0' has no effect. - REGION62: u1, - /// Enable protection for region 63. Write '0' has no effect. - REGION63: u1, - }), base_address + 0x604); - - /// address: 0x40000608 - /// Disable protection mechanism in debug interface mode - pub const DISABLEINDEBUG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x608); - - /// address: 0x4000060c - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x60c); - - /// address: 0x40000610 - /// Block protect configuration register 2 - pub const CONFIG2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable protection for region 64. Write '0' has no effect. - REGION64: u1, - /// Enable protection for region 65. Write '0' has no effect. - REGION65: u1, - /// Enable protection for region 66. Write '0' has no effect. - REGION66: u1, - /// Enable protection for region 67. Write '0' has no effect. - REGION67: u1, - /// Enable protection for region 68. Write '0' has no effect. - REGION68: u1, - /// Enable protection for region 69. Write '0' has no effect. - REGION69: u1, - /// Enable protection for region 70. Write '0' has no effect. - REGION70: u1, - /// Enable protection for region 71. Write '0' has no effect. - REGION71: u1, - /// Enable protection for region 72. Write '0' has no effect. - REGION72: u1, - /// Enable protection for region 73. Write '0' has no effect. - REGION73: u1, - /// Enable protection for region 74. Write '0' has no effect. - REGION74: u1, - /// Enable protection for region 75. Write '0' has no effect. - REGION75: u1, - /// Enable protection for region 76. Write '0' has no effect. - REGION76: u1, - /// Enable protection for region 77. Write '0' has no effect. - REGION77: u1, - /// Enable protection for region 78. Write '0' has no effect. - REGION78: u1, - /// Enable protection for region 79. Write '0' has no effect. - REGION79: u1, - /// Enable protection for region 80. Write '0' has no effect. - REGION80: u1, - /// Enable protection for region 81. Write '0' has no effect. - REGION81: u1, - /// Enable protection for region 82. Write '0' has no effect. - REGION82: u1, - /// Enable protection for region 83. Write '0' has no effect. - REGION83: u1, - /// Enable protection for region 84. Write '0' has no effect. - REGION84: u1, - /// Enable protection for region 85. Write '0' has no effect. - REGION85: u1, - /// Enable protection for region 86. Write '0' has no effect. - REGION86: u1, - /// Enable protection for region 87. Write '0' has no effect. - REGION87: u1, - /// Enable protection for region 88. Write '0' has no effect. - REGION88: u1, - /// Enable protection for region 89. Write '0' has no effect. - REGION89: u1, - /// Enable protection for region 90. Write '0' has no effect. - REGION90: u1, - /// Enable protection for region 91. Write '0' has no effect. - REGION91: u1, - /// Enable protection for region 92. Write '0' has no effect. - REGION92: u1, - /// Enable protection for region 93. Write '0' has no effect. - REGION93: u1, - /// Enable protection for region 94. Write '0' has no effect. - REGION94: u1, - /// Enable protection for region 95. Write '0' has no effect. - REGION95: u1, - }), base_address + 0x610); - - /// address: 0x40000614 - /// Block protect configuration register 3 - pub const CONFIG3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable protection for region 96. Write '0' has no effect. - REGION96: u1, - /// Enable protection for region 97. Write '0' has no effect. - REGION97: u1, - /// Enable protection for region 98. Write '0' has no effect. - REGION98: u1, - /// Enable protection for region 99. Write '0' has no effect. - REGION99: u1, - /// Enable protection for region 100. Write '0' has no effect. - REGION100: u1, - /// Enable protection for region 101. Write '0' has no effect. - REGION101: u1, - /// Enable protection for region 102. Write '0' has no effect. - REGION102: u1, - /// Enable protection for region 103. Write '0' has no effect. - REGION103: u1, - /// Enable protection for region 104. Write '0' has no effect. - REGION104: u1, - /// Enable protection for region 105. Write '0' has no effect. - REGION105: u1, - /// Enable protection for region 106. Write '0' has no effect. - REGION106: u1, - /// Enable protection for region 107. Write '0' has no effect. - REGION107: u1, - /// Enable protection for region 108. Write '0' has no effect. - REGION108: u1, - /// Enable protection for region 109. Write '0' has no effect. - REGION109: u1, - /// Enable protection for region 110. Write '0' has no effect. - REGION110: u1, - /// Enable protection for region 111. Write '0' has no effect. - REGION111: u1, - /// Enable protection for region 112. Write '0' has no effect. - REGION112: u1, - /// Enable protection for region 113. Write '0' has no effect. - REGION113: u1, - /// Enable protection for region 114. Write '0' has no effect. - REGION114: u1, - /// Enable protection for region 115. Write '0' has no effect. - REGION115: u1, - /// Enable protection for region 116. Write '0' has no effect. - REGION116: u1, - /// Enable protection for region 117. Write '0' has no effect. - REGION117: u1, - /// Enable protection for region 118. Write '0' has no effect. - REGION118: u1, - /// Enable protection for region 119. Write '0' has no effect. - REGION119: u1, - /// Enable protection for region 120. Write '0' has no effect. - REGION120: u1, - /// Enable protection for region 121. Write '0' has no effect. - REGION121: u1, - /// Enable protection for region 122. Write '0' has no effect. - REGION122: u1, - /// Enable protection for region 123. Write '0' has no effect. - REGION123: u1, - /// Enable protection for region 124. Write '0' has no effect. - REGION124: u1, - /// Enable protection for region 125. Write '0' has no effect. - REGION125: u1, - /// Enable protection for region 126. Write '0' has no effect. - REGION126: u1, - /// Enable protection for region 127. Write '0' has no effect. - REGION127: u1, - }), base_address + 0x614); - }; - /// Power control - pub const POWER = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000078 - /// Enable constant latency mode - pub const TASKS_CONSTLAT = @intToPtr(*volatile u32, base_address + 0x78); - - /// address: 0x4000007c - /// Enable low power mode (variable latency) - pub const TASKS_LOWPWR = @intToPtr(*volatile u32, base_address + 0x7c); - - /// address: 0x40000108 - /// Power failure warning - pub const EVENTS_POFWARN = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40000114 - /// CPU entered WFI/WFE sleep - pub const EVENTS_SLEEPENTER = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x40000118 - /// CPU exited WFI/WFE sleep - pub const EVENTS_SLEEPEXIT = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x40000304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for POFWARN event - POFWARN: u1, - reserved2: u1, - reserved3: u1, - /// Write '1' to Enable interrupt for SLEEPENTER event - SLEEPENTER: u1, - /// Write '1' to Enable interrupt for SLEEPEXIT event - SLEEPEXIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x304); - - /// address: 0x40000308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for POFWARN event - POFWARN: u1, - reserved2: u1, - reserved3: u1, - /// Write '1' to Disable interrupt for SLEEPENTER event - SLEEPENTER: u1, - /// Write '1' to Disable interrupt for SLEEPEXIT event - SLEEPEXIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x308); - - /// address: 0x40000400 - /// Reset reason - pub const RESETREAS = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset from pin-reset detected - RESETPIN: u1, - /// Reset from watchdog detected - DOG: u1, - /// Reset from soft reset detected - SREQ: u1, - /// Reset from CPU lock-up detected - LOCKUP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Reset due to wake up from System OFF mode when wakeup is triggered from DETECT - /// signal from GPIO - OFF: u1, - /// Reset due to wake up from System OFF mode when wakeup is triggered from - /// ANADETECT signal from LPCOMP - LPCOMP: u1, - /// Reset due to wake up from System OFF mode when wakeup is triggered from entering - /// into debug interface mode - DIF: u1, - /// Reset due to wake up from System OFF mode by NFC field detect - NFC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x400); - - /// address: 0x40000428 - /// Deprecated register - RAM status register - pub const RAMSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// RAM block 0 is on or off/powering up - RAMBLOCK0: u1, - /// RAM block 1 is on or off/powering up - RAMBLOCK1: u1, - /// RAM block 2 is on or off/powering up - RAMBLOCK2: u1, - /// RAM block 3 is on or off/powering up - RAMBLOCK3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x428); - - /// address: 0x40000500 - /// System OFF register - pub const SYSTEMOFF = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x40000510 - /// Power failure comparator configuration - pub const POFCON = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable power failure comparator - POF: u1, - /// Power failure comparator threshold setting - THRESHOLD: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x510); - - /// address: 0x4000051c - /// General purpose retention register - pub const GPREGRET = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40000520 - /// General purpose retention register - pub const GPREGRET2 = @intToPtr(*volatile Mmio(32, packed struct { - /// General purpose retention register - GPREGRET: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x520); - - /// address: 0x40000524 - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMON = @intToPtr(*volatile Mmio(32, packed struct { - /// Keep RAM block 0 on or off in system ON Mode - ONRAM0: u1, - /// Keep RAM block 1 on or off in system ON Mode - ONRAM1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Keep retention on RAM block 0 when RAM block is switched off - OFFRAM0: u1, - /// Keep retention on RAM block 1 when RAM block is switched off - OFFRAM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x524); - - /// address: 0x40000554 - /// Deprecated register - RAM on/off register (this register is retained) - pub const RAMONB = @intToPtr(*volatile Mmio(32, packed struct { - /// Keep RAM block 2 on or off in system ON Mode - ONRAM2: u1, - /// Keep RAM block 3 on or off in system ON Mode - ONRAM3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Keep retention on RAM block 2 when RAM block is switched off - OFFRAM2: u1, - /// Keep retention on RAM block 3 when RAM block is switched off - OFFRAM3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x554); - - /// address: 0x40000578 - /// DC/DC enable register - pub const DCDCEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x578); - - pub const RAM = @ptrCast(*volatile [8]packed struct { - /// Description cluster[0]: RAM0 power control register - POWER: Mmio(32, packed struct { - /// Keep RAM section S0 ON or OFF in System ON mode. - S0POWER: u1, - /// Keep RAM section S1 ON or OFF in System ON mode. - S1POWER: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Keep retention on RAM section S0 when RAM section is in OFF - S0RETENTION: u1, - /// Keep retention on RAM section S1 when RAM section is in OFF - S1RETENTION: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), - - /// Description cluster[0]: RAM0 power control set register - POWERSET: Mmio(32, packed struct { - /// Keep RAM section S0 of RAM0 on or off in System ON mode - S0POWER: u1, - /// Keep RAM section S1 of RAM0 on or off in System ON mode - S1POWER: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Keep retention on RAM section S0 when RAM section is switched off - S0RETENTION: u1, - /// Keep retention on RAM section S1 when RAM section is switched off - S1RETENTION: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), - - /// Description cluster[0]: RAM0 power control clear register - POWERCLR: Mmio(32, packed struct { - /// Keep RAM section S0 of RAM0 on or off in System ON mode - S0POWER: u1, - /// Keep RAM section S1 of RAM0 on or off in System ON mode - S1POWER: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Keep retention on RAM section S0 when RAM section is switched off - S0RETENTION: u1, - /// Keep retention on RAM section S1 when RAM section is switched off - S1RETENTION: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), - padding0: u32, - }, base_address + 0x900); - }; - /// Clock control - pub const CLOCK = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// Start HFCLK crystal oscillator - pub const TASKS_HFCLKSTART = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40000004 - /// Stop HFCLK crystal oscillator - pub const TASKS_HFCLKSTOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40000008 - /// Start LFCLK source - pub const TASKS_LFCLKSTART = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000000c - /// Stop LFCLK source - pub const TASKS_LFCLKSTOP = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40000010 - /// Start calibration of LFRC oscillator - pub const TASKS_CAL = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40000014 - /// Start calibration timer - pub const TASKS_CTSTART = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x40000018 - /// Stop calibration timer - pub const TASKS_CTSTOP = @intToPtr(*volatile u32, base_address + 0x18); - - /// address: 0x40000100 - /// HFCLK oscillator started - pub const EVENTS_HFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40000104 - /// LFCLK started - pub const EVENTS_LFCLKSTARTED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4000010c - /// Calibration of LFCLK RC oscillator complete event - pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40000110 - /// Calibration timer timeout - pub const EVENTS_CTTO = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40000304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1, - /// Write '1' to Enable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1, - reserved0: u1, - /// Write '1' to Enable interrupt for DONE event - DONE: u1, - /// Write '1' to Enable interrupt for CTTO event - CTTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x304); - - /// address: 0x40000308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for HFCLKSTARTED event - HFCLKSTARTED: u1, - /// Write '1' to Disable interrupt for LFCLKSTARTED event - LFCLKSTARTED: u1, - reserved0: u1, - /// Write '1' to Disable interrupt for DONE event - DONE: u1, - /// Write '1' to Disable interrupt for CTTO event - CTTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x308); - - /// address: 0x40000408 - /// Status indicating that HFCLKSTART task has been triggered - pub const HFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct { - /// HFCLKSTART task triggered or not - STATUS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x408); - - /// address: 0x4000040c - /// HFCLK status - pub const HFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Source of HFCLK - SRC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// HFCLK state - STATE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x40c); - - /// address: 0x40000414 - /// Status indicating that LFCLKSTART task has been triggered - pub const LFCLKRUN = @intToPtr(*volatile Mmio(32, packed struct { - /// LFCLKSTART task triggered or not - STATUS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x414); - - /// address: 0x40000418 - /// LFCLK status - pub const LFCLKSTAT = @intToPtr(*volatile Mmio(32, packed struct { - /// Source of LFCLK - SRC: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// LFCLK state - STATE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x418); - - /// address: 0x4000041c - /// Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - pub const LFCLKSRCCOPY = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock source - SRC: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x41c); - - /// address: 0x40000518 - /// Clock source for the LFCLK - pub const LFCLKSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock source - SRC: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Enable or disable bypass of LFCLK crystal oscillator with external clock source - BYPASS: u1, - /// Enable or disable external source for LFCLK - EXTERNAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x518); - - /// address: 0x40000538 - /// Calibration timer interval - pub const CTIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x538); - - /// address: 0x4000055c - /// Clocking options for the Trace Port debug interface - pub const TRACECONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Speed of Trace Port clock. Note that the TRACECLK pin will output this clock - /// divided by two. - TRACEPORTSPEED: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Pin multiplexing of trace signals. - TRACEMUX: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x55c); - }; - /// 2.4 GHz Radio - pub const RADIO = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// Enable RADIO in TX mode - pub const TASKS_TXEN = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40001004 - /// Enable RADIO in RX mode - pub const TASKS_RXEN = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40001008 - /// Start RADIO - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000100c - /// Stop RADIO - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40001010 - /// Disable RADIO - pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40001014 - /// Start the RSSI and take one single sample of the receive signal strength. - pub const TASKS_RSSISTART = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x40001018 - /// Stop the RSSI measurement - pub const TASKS_RSSISTOP = @intToPtr(*volatile u32, base_address + 0x18); - - /// address: 0x4000101c - /// Start the bit counter - pub const TASKS_BCSTART = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40001020 - /// Stop the bit counter - pub const TASKS_BCSTOP = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40001100 - /// RADIO has ramped up and is ready to be started - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40001104 - /// Address sent or received - pub const EVENTS_ADDRESS = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40001108 - /// Packet payload sent or received - pub const EVENTS_PAYLOAD = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000110c - /// Packet sent or received - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40001110 - /// RADIO has been disabled - pub const EVENTS_DISABLED = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40001114 - /// A device address match occurred on the last received packet - pub const EVENTS_DEVMATCH = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x40001118 - /// No device address match occurred on the last received packet - pub const EVENTS_DEVMISS = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x4000111c - /// Sampling of receive signal strength complete. - pub const EVENTS_RSSIEND = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40001128 - /// Bit counter reached bit count value. - pub const EVENTS_BCMATCH = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x40001130 - /// Packet received with CRC ok - pub const EVENTS_CRCOK = @intToPtr(*volatile u32, base_address + 0x130); - - /// address: 0x40001134 - /// Packet received with CRC error - pub const EVENTS_CRCERROR = @intToPtr(*volatile u32, base_address + 0x134); - - /// address: 0x40001200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between READY event and START task - READY_START: u1, - /// Shortcut between END event and DISABLE task - END_DISABLE: u1, - /// Shortcut between DISABLED event and TXEN task - DISABLED_TXEN: u1, - /// Shortcut between DISABLED event and RXEN task - DISABLED_RXEN: u1, - /// Shortcut between ADDRESS event and RSSISTART task - ADDRESS_RSSISTART: u1, - /// Shortcut between END event and START task - END_START: u1, - /// Shortcut between ADDRESS event and BCSTART task - ADDRESS_BCSTART: u1, - reserved0: u1, - /// Shortcut between DISABLED event and RSSISTOP task - DISABLED_RSSISTOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x200); - - /// address: 0x40001304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1, - /// Write '1' to Enable interrupt for ADDRESS event - ADDRESS: u1, - /// Write '1' to Enable interrupt for PAYLOAD event - PAYLOAD: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - /// Write '1' to Enable interrupt for DISABLED event - DISABLED: u1, - /// Write '1' to Enable interrupt for DEVMATCH event - DEVMATCH: u1, - /// Write '1' to Enable interrupt for DEVMISS event - DEVMISS: u1, - /// Write '1' to Enable interrupt for RSSIEND event - RSSIEND: u1, - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for BCMATCH event - BCMATCH: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for CRCOK event - CRCOK: u1, - /// Write '1' to Enable interrupt for CRCERROR event - CRCERROR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x304); - - /// address: 0x40001308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1, - /// Write '1' to Disable interrupt for ADDRESS event - ADDRESS: u1, - /// Write '1' to Disable interrupt for PAYLOAD event - PAYLOAD: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - /// Write '1' to Disable interrupt for DISABLED event - DISABLED: u1, - /// Write '1' to Disable interrupt for DEVMATCH event - DEVMATCH: u1, - /// Write '1' to Disable interrupt for DEVMISS event - DEVMISS: u1, - /// Write '1' to Disable interrupt for RSSIEND event - RSSIEND: u1, - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for BCMATCH event - BCMATCH: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for CRCOK event - CRCOK: u1, - /// Write '1' to Disable interrupt for CRCERROR event - CRCERROR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x308); - - /// address: 0x40001400 - /// CRC status - pub const CRCSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x40001408 - /// Received address - pub const RXMATCH = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x408); - - /// address: 0x4000140c - /// CRC field of previously received packet - pub const RXCRC = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x40c); - - /// address: 0x40001410 - /// Device address match index - pub const DAI = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x410); - - /// address: 0x40001504 - /// Packet pointer - pub const PACKETPTR = @intToPtr(*volatile u32, base_address + 0x504); - - /// address: 0x40001508 - /// Frequency - pub const FREQUENCY = @intToPtr(*volatile Mmio(32, packed struct { - /// Radio channel frequency - FREQUENCY: u7, - reserved0: u1, - /// Channel map selection. - MAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x508); - - /// address: 0x4000150c - /// Output power - pub const TXPOWER = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x50c); - - /// address: 0x40001510 - /// Data rate and modulation - pub const MODE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x40001514 - /// Packet configuration register 0 - pub const PCNF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Length on air of LENGTH field in number of bits. - LFLEN: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Length on air of S0 field in number of bytes. - S0LEN: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Length on air of S1 field in number of bits. - S1LEN: u4, - /// Include or exclude S1 field in RAM - S1INCL: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Length of preamble on air. Decision point: TASKS_START task - PLEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x514); - - /// address: 0x40001518 - /// Packet configuration register 1 - pub const PCNF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum length of packet payload. If the packet payload is larger than MAXLEN, - /// the radio will truncate the payload to MAXLEN. - MAXLEN: u8, - /// Static length in number of bytes - STATLEN: u8, - /// Base address length in number of bytes - BALEN: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD - /// fields. - ENDIAN: u1, - /// Enable or disable packet whitening - WHITEEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x518); - - /// address: 0x4000151c - /// Base address 0 - pub const BASE0 = @intToPtr(*volatile u32, base_address + 0x51c); - - /// address: 0x40001520 - /// Base address 1 - pub const BASE1 = @intToPtr(*volatile u32, base_address + 0x520); - - /// address: 0x40001524 - /// Prefixes bytes for logical addresses 0-3 - pub const PREFIX0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address prefix 0. - AP0: u8, - /// Address prefix 1. - AP1: u8, - /// Address prefix 2. - AP2: u8, - /// Address prefix 3. - AP3: u8, - }), base_address + 0x524); - - /// address: 0x40001528 - /// Prefixes bytes for logical addresses 4-7 - pub const PREFIX1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address prefix 4. - AP4: u8, - /// Address prefix 5. - AP5: u8, - /// Address prefix 6. - AP6: u8, - /// Address prefix 7. - AP7: u8, - }), base_address + 0x528); - - /// address: 0x4000152c - /// Transmit address select - pub const TXADDRESS = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x52c); - - /// address: 0x40001530 - /// Receive address select - pub const RXADDRESSES = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable reception on logical address 0. - ADDR0: u1, - /// Enable or disable reception on logical address 1. - ADDR1: u1, - /// Enable or disable reception on logical address 2. - ADDR2: u1, - /// Enable or disable reception on logical address 3. - ADDR3: u1, - /// Enable or disable reception on logical address 4. - ADDR4: u1, - /// Enable or disable reception on logical address 5. - ADDR5: u1, - /// Enable or disable reception on logical address 6. - ADDR6: u1, - /// Enable or disable reception on logical address 7. - ADDR7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x530); - - /// address: 0x40001534 - /// CRC configuration - pub const CRCCNF = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC length in number of bytes. - LEN: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Include or exclude packet address field out of CRC calculation. - SKIPADDR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x534); - - /// address: 0x40001538 - /// CRC polynomial - pub const CRCPOLY = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x538); - - /// address: 0x4000153c - /// CRC initial value - pub const CRCINIT = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x53c); - - /// address: 0x40001540 - /// Unspecified - pub const UNUSED0 = @intToPtr(*volatile u32, base_address + 0x540); - - /// address: 0x40001544 - /// Inter Frame Spacing in us - pub const TIFS = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x544); - - /// address: 0x40001548 - /// RSSI sample - pub const RSSISAMPLE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x548); - - /// address: 0x40001550 - /// Current radio state - pub const STATE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x550); - - /// address: 0x40001554 - /// Data whitening initial value - pub const DATAWHITEIV = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x554); - - /// address: 0x40001560 - /// Bit counter compare - pub const BCC = @intToPtr(*volatile u32, base_address + 0x560); - - /// address: 0x40001600 - /// Description collection[0]: Device address base segment 0 - pub const DAB = @intToPtr(*volatile [8]u32, base_address + 0x600); - - /// address: 0x40001620 - /// Description collection[0]: Device address prefix 0 - pub const DAP = @intToPtr(*volatile [8]MmioInt(32, u16), base_address + 0x620); - - /// address: 0x40001640 - /// Device address match configuration - pub const DACNF = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable device address matching using device address 0 - ENA0: u1, - /// Enable or disable device address matching using device address 1 - ENA1: u1, - /// Enable or disable device address matching using device address 2 - ENA2: u1, - /// Enable or disable device address matching using device address 3 - ENA3: u1, - /// Enable or disable device address matching using device address 4 - ENA4: u1, - /// Enable or disable device address matching using device address 5 - ENA5: u1, - /// Enable or disable device address matching using device address 6 - ENA6: u1, - /// Enable or disable device address matching using device address 7 - ENA7: u1, - /// TxAdd for device address 0 - TXADD0: u1, - /// TxAdd for device address 1 - TXADD1: u1, - /// TxAdd for device address 2 - TXADD2: u1, - /// TxAdd for device address 3 - TXADD3: u1, - /// TxAdd for device address 4 - TXADD4: u1, - /// TxAdd for device address 5 - TXADD5: u1, - /// TxAdd for device address 6 - TXADD6: u1, - /// TxAdd for device address 7 - TXADD7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x640); - - /// address: 0x40001650 - /// Radio mode configuration register 0 - pub const MODECNF0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Radio ramp-up time - RU: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Default TX value - DTX: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x650); - - /// address: 0x40001ffc - /// Peripheral power control - pub const POWER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xffc); - }; - /// UART with EasyDMA - pub const UARTE0 = struct { - pub const base_address = 0x40002000; - - /// address: 0x40002000 - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40002004 - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40002008 - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000200c - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4000202c - /// Flush RX FIFO into RX buffer - pub const TASKS_FLUSHRX = @intToPtr(*volatile u32, base_address + 0x2c); - - /// address: 0x40002100 - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40002104 - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40002108 - /// Data received in RXD (but potentially not yet transferred to Data RAM) - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40002110 - /// Receive buffer is filled up - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x4000211c - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40002120 - /// Last TX byte transmitted - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x40002124 - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40002144 - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); - - /// address: 0x4000214c - /// UART receiver has started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40002150 - /// UART transmitter has started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x40002158 - /// Transmitter stopped - pub const EVENTS_TXSTOPPED = @intToPtr(*volatile u32, base_address + 0x158); - - /// address: 0x40002200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Shortcut between ENDRX event and STARTRX task - ENDRX_STARTRX: u1, - /// Shortcut between ENDRX event and STOPRX task - ENDRX_STOPRX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x200); - - /// address: 0x40002300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for CTS event - CTS: u1, - /// Enable or disable interrupt for NCTS event - NCTS: u1, - /// Enable or disable interrupt for RXDRDY event - RXDRDY: u1, - reserved0: u1, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1, - reserved1: u1, - reserved2: u1, - /// Enable or disable interrupt for TXDRDY event - TXDRDY: u1, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Enable or disable interrupt for RXTO event - RXTO: u1, - reserved10: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved11: u1, - /// Enable or disable interrupt for TXSTOPPED event - TXSTOPPED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x300); - - /// address: 0x40002304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1, - reserved0: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1, - reserved10: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved11: u1, - /// Write '1' to Enable interrupt for TXSTOPPED event - TXSTOPPED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x304); - - /// address: 0x40002308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1, - reserved0: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1, - reserved10: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved11: u1, - /// Write '1' to Disable interrupt for TXSTOPPED event - TXSTOPPED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x308); - - /// address: 0x40002480 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// Parity error - PARITY: u1, - /// Framing error occurred - FRAMING: u1, - /// Break condition - BREAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x480); - - /// address: 0x40002500 - /// Enable UART - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40002524 - /// Baud rate. Accuracy depends on the HFCLK source selected. - pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x4000256c - /// Configuration of parity and hardware flow control - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Hardware flow control - HWFC: u1, - /// Parity - PARITY: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x56c); - - pub const PSEL = struct { - /// address: 0x40002000 - /// Pin select for RTS signal - pub const RTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40002004 - /// Pin select for TXD signal - pub const TXD = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - - /// address: 0x40002008 - /// Pin select for CTS signal - pub const CTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x8); - - /// address: 0x4000200c - /// Pin select for RXD signal - pub const RXD = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0xc); - }; - - /// RXD EasyDMA channel - pub const RXD = struct { - /// address: 0x40002000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40002004 - /// Maximum number of bytes in receive buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40002008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - - /// TXD EasyDMA channel - pub const TXD = struct { - /// address: 0x40002000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40002004 - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40002008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - }; - /// Universal Asynchronous Receiver/Transmitter - pub const UART0 = struct { - pub const base_address = 0x40002000; - - /// address: 0x40002000 - /// Start UART receiver - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40002004 - /// Stop UART receiver - pub const TASKS_STOPRX = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40002008 - /// Start UART transmitter - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000200c - /// Stop UART transmitter - pub const TASKS_STOPTX = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4000201c - /// Suspend UART - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40002100 - /// CTS is activated (set low). Clear To Send. - pub const EVENTS_CTS = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40002104 - /// CTS is deactivated (set high). Not Clear To Send. - pub const EVENTS_NCTS = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40002108 - /// Data received in RXD - pub const EVENTS_RXDRDY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000211c - /// Data sent from TXD - pub const EVENTS_TXDRDY = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40002124 - /// Error detected - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40002144 - /// Receiver timeout - pub const EVENTS_RXTO = @intToPtr(*volatile u32, base_address + 0x144); - - /// address: 0x40002200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Shortcut between CTS event and STARTRX task - CTS_STARTRX: u1, - /// Shortcut between NCTS event and STOPRX task - NCTS_STOPRX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x40002304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for CTS event - CTS: u1, - /// Write '1' to Enable interrupt for NCTS event - NCTS: u1, - /// Write '1' to Enable interrupt for RXDRDY event - RXDRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Write '1' to Enable interrupt for TXDRDY event - TXDRDY: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Write '1' to Enable interrupt for RXTO event - RXTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x304); - - /// address: 0x40002308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for CTS event - CTS: u1, - /// Write '1' to Disable interrupt for NCTS event - NCTS: u1, - /// Write '1' to Disable interrupt for RXDRDY event - RXDRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Write '1' to Disable interrupt for TXDRDY event - TXDRDY: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Write '1' to Disable interrupt for RXTO event - RXTO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x308); - - /// address: 0x40002480 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// Parity error - PARITY: u1, - /// Framing error occurred - FRAMING: u1, - /// Break condition - BREAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x480); - - /// address: 0x40002500 - /// Enable UART - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40002508 - /// Pin select for RTS - pub const PSELRTS = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000250c - /// Pin select for TXD - pub const PSELTXD = @intToPtr(*volatile u32, base_address + 0x50c); - - /// address: 0x40002510 - /// Pin select for CTS - pub const PSELCTS = @intToPtr(*volatile u32, base_address + 0x510); - - /// address: 0x40002514 - /// Pin select for RXD - pub const PSELRXD = @intToPtr(*volatile u32, base_address + 0x514); - - /// address: 0x40002518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4000251c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40002524 - /// Baud rate - pub const BAUDRATE = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x4000256c - /// Configuration of parity and hardware flow control - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Hardware flow control - HWFC: u1, - /// Parity - PARITY: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x56c); - }; - /// Serial Peripheral Interface Master with EasyDMA 0 - pub const SPIM0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003010 - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40003014 - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000301c - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40003020 - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40003104 - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40003110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40003118 - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x40003120 - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x4000314c - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40003200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Shortcut between END event and START task - END_START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x200); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x40003500 - /// Enable SPIM - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003524 - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40003554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x400035c0 - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - - pub const PSEL = struct { - /// address: 0x40003000 - /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Pin select for MOSI signal - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// Pin select for MISO signal - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x8); - }; - - /// RXD EasyDMA channel - pub const RXD = struct { - /// address: 0x40003000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in receive buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - - /// address: 0x4000300c - /// EasyDMA list type - pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); - }; - - /// TXD EasyDMA channel - pub const TXD = struct { - /// address: 0x40003000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - - /// address: 0x4000300c - /// EasyDMA list type - pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); - }; - }; - /// SPI Slave 0 - pub const SPIS0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003024 - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x40003028 - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40003104 - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40003110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40003128 - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x40003200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x200); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x308); - - /// address: 0x40003400 - /// Semaphore status register - pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); - - /// address: 0x40003440 - /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x440); - - /// address: 0x40003500 - /// Enable SPI slave - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x4000355c - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); - - /// address: 0x400035c0 - /// Over-read character - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - - pub const PSEL = struct { - /// address: 0x40003000 - /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Pin select for MISO signal - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - - /// address: 0x40003008 - /// Pin select for MOSI signal - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// Pin select for CSN signal - pub const CSN = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0xc); - }; - - pub const RXD = struct { - /// address: 0x40003000 - /// RXD data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in receive buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes received in last granted transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - - pub const TXD = struct { - /// address: 0x40003000 - /// TXD data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transmitted in last granted transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - }; - /// I2C compatible Two-Wire Master Interface with EasyDMA 0 - pub const TWIM0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003008 - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40003014 - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000301c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40003020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40003104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40003124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40003148 - /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic - /// is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x4000314c - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40003150 - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x4000315c - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); - - /// address: 0x40003160 - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); - - /// address: 0x40003200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1, - reserved7: u1, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x200); - - /// address: 0x40003300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x300); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x308); - - /// address: 0x400034c4 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4c4); - - /// address: 0x40003500 - /// Enable TWIM - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003524 - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40003588 - /// Address used in the TWI transfer - pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); - - pub const PSEL = struct { - /// address: 0x40003000 - /// Pin select for SCL signal - pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Pin select for SDA signal - pub const SDA = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - }; - - /// RXD EasyDMA channel - pub const RXD = struct { - /// address: 0x40003000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in receive buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - - /// address: 0x4000300c - /// EasyDMA list type - pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); - }; - - /// TXD EasyDMA channel - pub const TXD = struct { - /// address: 0x40003000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in transmit buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - - /// address: 0x4000300c - /// EasyDMA list type - pub const LIST = @intToPtr(*volatile MmioInt(32, u3), base_address + 0xc); - }; - }; - /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 - pub const TWIS0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003014 - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000301c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40003020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40003030 - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); - - /// address: 0x40003034 - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0x40003104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40003124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x4000314c - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40003150 - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x40003164 - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); - - /// address: 0x40003168 - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); - - /// address: 0x40003200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x200); - - /// address: 0x40003300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Enable or disable interrupt for WRITE event - WRITE: u1, - /// Enable or disable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x300); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1, - /// Write '1' to Enable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1, - /// Write '1' to Disable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x308); - - /// address: 0x400034d0 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1, - reserved0: u1, - /// NACK sent after receiving a data byte - DNACK: u1, - /// TX buffer over-read detected, and prevented - OVERREAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x4d0); - - /// address: 0x400034d4 - /// Status register indicating which address had a match - pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); - - /// address: 0x40003500 - /// Enable TWIS - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003588 - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); - - /// address: 0x40003594 - /// Configuration register for the address match mechanism - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x594); - - /// address: 0x400035c0 - /// Over-read character. Character sent out in case of an over-read of the transmit - /// buffer. - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - - pub const PSEL = struct { - /// address: 0x40003000 - /// Pin select for SCL signal - pub const SCL = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Pin select for SDA signal - pub const SDA = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - }; - - /// RXD EasyDMA channel - pub const RXD = struct { - /// address: 0x40003000 - /// RXD Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in RXD buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last RXD transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - - /// TXD EasyDMA channel - pub const TXD = struct { - /// address: 0x40003000 - /// TXD Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003004 - /// Maximum number of bytes in TXD buffer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40003008 - /// Number of bytes transferred in the last TXD transaction - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x8); - }; - }; - /// Serial Peripheral Interface 0 - pub const SPI0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003108 - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x40003500 - /// Enable SPI - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4000351c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40003524 - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40003554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - pub const PSEL = struct { - /// address: 0x40003000 - /// Pin select for SCK - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number configuration for SPI SCK signal - PSELSCK: u32, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Pin select for MOSI - pub const MOSI = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number configuration for SPI MOSI signal - PSELMOSI: u32, - }), base_address + 0x4); - - /// address: 0x40003008 - /// Pin select for MISO - pub const MISO = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number configuration for SPI MISO signal - PSELMISO: u32, - }), base_address + 0x8); - }; - }; - /// I2C compatible Two-Wire Interface 0 - pub const TWI0 = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40003008 - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40003014 - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000301c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40003020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40003104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40003108 - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000311c - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40003124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40003138 - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); - - /// address: 0x40003148 - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x40003200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1, - /// Shortcut between BB event and STOP task - BB_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x200); - - /// address: 0x40003304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1, - reserved5: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Enable interrupt for BB event - BB: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x304); - - /// address: 0x40003308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1, - reserved5: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Disable interrupt for BB event - BB: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x308); - - /// address: 0x400034c4 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4c4); - - /// address: 0x40003500 - /// Enable TWI - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40003508 - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000350c - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); - - /// address: 0x40003518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4000351c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40003524 - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40003588 - /// Address used in the TWI transfer - pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); - }; - /// Serial Peripheral Interface Master with EasyDMA 1 - pub const SPIM1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004010 - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40004014 - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000401c - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40004020 - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40004104 - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40004110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40004118 - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x40004120 - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x4000414c - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40004200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Shortcut between END event and START task - END_START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x200); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x40004500 - /// Enable SPIM - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004524 - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40004554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x400045c0 - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - }; - /// SPI Slave 1 - pub const SPIS1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004024 - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x40004028 - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40004104 - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40004110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40004128 - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x40004200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x200); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x308); - - /// address: 0x40004400 - /// Semaphore status register - pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); - - /// address: 0x40004440 - /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x440); - - /// address: 0x40004500 - /// Enable SPI slave - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x4000455c - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); - - /// address: 0x400045c0 - /// Over-read character - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - }; - /// I2C compatible Two-Wire Master Interface with EasyDMA 1 - pub const TWIM1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40004008 - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40004014 - /// Stop TWI transaction. Must be issued while the TWI master is not suspended. - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000401c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40004020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40004104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40004124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40004148 - /// Last byte has been sent out after the SUSPEND task has been issued, TWI traffic - /// is now suspended. - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x4000414c - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40004150 - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x4000415c - /// Byte boundary, starting to receive the last byte - pub const EVENTS_LASTRX = @intToPtr(*volatile u32, base_address + 0x15c); - - /// address: 0x40004160 - /// Byte boundary, starting to transmit the last byte - pub const EVENTS_LASTTX = @intToPtr(*volatile u32, base_address + 0x160); - - /// address: 0x40004200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Shortcut between LASTTX event and STARTRX task - LASTTX_STARTRX: u1, - /// Shortcut between LASTTX event and SUSPEND task - LASTTX_SUSPEND: u1, - /// Shortcut between LASTTX event and STOP task - LASTTX_STOP: u1, - /// Shortcut between LASTRX event and STARTTX task - LASTRX_STARTTX: u1, - reserved7: u1, - /// Shortcut between LASTRX event and STOP task - LASTRX_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x200); - - /// address: 0x40004300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable or disable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Enable or disable interrupt for LASTRX event - LASTRX: u1, - /// Enable or disable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x300); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Write '1' to Enable interrupt for LASTRX event - LASTRX: u1, - /// Write '1' to Enable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved16: u1, - reserved17: u1, - /// Write '1' to Disable interrupt for LASTRX event - LASTRX: u1, - /// Write '1' to Disable interrupt for LASTTX event - LASTTX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x308); - - /// address: 0x400044c4 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4c4); - - /// address: 0x40004500 - /// Enable TWIM - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004524 - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40004588 - /// Address used in the TWI transfer - pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); - }; - /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 - pub const TWIS1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004014 - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000401c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40004020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40004030 - /// Prepare the TWI slave to respond to a write command - pub const TASKS_PREPARERX = @intToPtr(*volatile u32, base_address + 0x30); - - /// address: 0x40004034 - /// Prepare the TWI slave to respond to a read command - pub const TASKS_PREPARETX = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0x40004104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40004124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x4000414c - /// Receive sequence started - pub const EVENTS_RXSTARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40004150 - /// Transmit sequence started - pub const EVENTS_TXSTARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x40004164 - /// Write command received - pub const EVENTS_WRITE = @intToPtr(*volatile u32, base_address + 0x164); - - /// address: 0x40004168 - /// Read command received - pub const EVENTS_READ = @intToPtr(*volatile u32, base_address + 0x168); - - /// address: 0x40004200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Shortcut between WRITE event and SUSPEND task - WRITE_SUSPEND: u1, - /// Shortcut between READ event and SUSPEND task - READ_SUSPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x200); - - /// address: 0x40004300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Enable or disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Enable or disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Enable or disable interrupt for WRITE event - WRITE: u1, - /// Enable or disable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x300); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Write '1' to Enable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Enable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Write '1' to Enable interrupt for WRITE event - WRITE: u1, - /// Write '1' to Enable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Write '1' to Disable interrupt for RXSTARTED event - RXSTARTED: u1, - /// Write '1' to Disable interrupt for TXSTARTED event - TXSTARTED: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// Write '1' to Disable interrupt for WRITE event - WRITE: u1, - /// Write '1' to Disable interrupt for READ event - READ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x308); - - /// address: 0x400044d0 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// RX buffer overflow detected, and prevented - OVERFLOW: u1, - reserved0: u1, - /// NACK sent after receiving a data byte - DNACK: u1, - /// TX buffer over-read detected, and prevented - OVERREAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x4d0); - - /// address: 0x400044d4 - /// Status register indicating which address had a match - pub const MATCH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4d4); - - /// address: 0x40004500 - /// Enable TWIS - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004588 - /// Description collection[0]: TWI slave address 0 - pub const ADDRESS = @intToPtr(*volatile [2]MmioInt(32, u7), base_address + 0x588); - - /// address: 0x40004594 - /// Configuration register for the address match mechanism - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable address matching on ADDRESS[0] - ADDRESS0: u1, - /// Enable or disable address matching on ADDRESS[1] - ADDRESS1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x594); - - /// address: 0x400045c0 - /// Over-read character. Character sent out in case of an over-read of the transmit - /// buffer. - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - }; - /// Serial Peripheral Interface 1 - pub const SPI1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004108 - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x40004500 - /// Enable SPI - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4000451c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40004524 - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40004554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - }; - /// I2C compatible Two-Wire Interface 1 - pub const TWI1 = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// Start TWI receive sequence - pub const TASKS_STARTRX = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40004008 - /// Start TWI transmit sequence - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40004014 - /// Stop TWI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4000401c - /// Suspend TWI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40004020 - /// Resume TWI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40004104 - /// TWI stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40004108 - /// TWI RXD byte received - pub const EVENTS_RXDREADY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000411c - /// TWI TXD byte sent - pub const EVENTS_TXDSENT = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40004124 - /// TWI error - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x40004138 - /// TWI byte boundary, generated before each byte that is sent or received - pub const EVENTS_BB = @intToPtr(*volatile u32, base_address + 0x138); - - /// address: 0x40004148 - /// TWI entered the suspended state - pub const EVENTS_SUSPENDED = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x40004200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between BB event and SUSPEND task - BB_SUSPEND: u1, - /// Shortcut between BB event and STOP task - BB_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x200); - - /// address: 0x40004304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for RXDREADY event - RXDREADY: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for TXDSENT event - TXDSENT: u1, - reserved5: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Enable interrupt for BB event - BB: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Write '1' to Enable interrupt for SUSPENDED event - SUSPENDED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x304); - - /// address: 0x40004308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for RXDREADY event - RXDREADY: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for TXDSENT event - TXDSENT: u1, - reserved5: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Write '1' to Disable interrupt for BB event - BB: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Write '1' to Disable interrupt for SUSPENDED event - SUSPENDED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x308); - - /// address: 0x400044c4 - /// Error source - pub const ERRORSRC = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun error - OVERRUN: u1, - /// NACK received after sending the address (write '1' to clear) - ANACK: u1, - /// NACK received after sending a data byte (write '1' to clear) - DNACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4c4); - - /// address: 0x40004500 - /// Enable TWI - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40004508 - /// Pin select for SCL - pub const PSELSCL = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000450c - /// Pin select for SDA - pub const PSELSDA = @intToPtr(*volatile u32, base_address + 0x50c); - - /// address: 0x40004518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4000451c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40004524 - /// TWI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40004588 - /// Address used in the TWI transfer - pub const ADDRESS = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x588); - }; - /// NFC-A compatible radio - pub const NFCT = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// Activate NFC peripheral for incoming and outgoing frames, change state to - /// activated - pub const TASKS_ACTIVATE = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40005004 - /// Disable NFC peripheral - pub const TASKS_DISABLE = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40005008 - /// Enable NFC sense field mode, change state to sense mode - pub const TASKS_SENSE = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000500c - /// Start transmission of a outgoing frame, change state to transmit - pub const TASKS_STARTTX = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4000501c - /// Initializes the EasyDMA for receive. - pub const TASKS_ENABLERXDATA = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40005024 - /// Force state machine to IDLE state - pub const TASKS_GOIDLE = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x40005028 - /// Force state machine to SLEEP_A state - pub const TASKS_GOSLEEP = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40005100 - /// The NFC peripheral is ready to receive and send frames - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40005104 - /// Remote NFC field detected - pub const EVENTS_FIELDDETECTED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40005108 - /// Remote NFC field lost - pub const EVENTS_FIELDLOST = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000510c - /// Marks the start of the first symbol of a transmitted frame - pub const EVENTS_TXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40005110 - /// Marks the end of the last transmitted on-air symbol of a frame - pub const EVENTS_TXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40005114 - /// Marks the end of the first symbol of a received frame - pub const EVENTS_RXFRAMESTART = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x40005118 - /// Received data have been checked (CRC, parity) and transferred to RAM, and - /// EasyDMA has ended accessing the RX buffer - pub const EVENTS_RXFRAMEEND = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x4000511c - /// NFC error reported. The ERRORSTATUS register contains details on the source of - /// the error. - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40005128 - /// NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the - /// source of the error. - pub const EVENTS_RXERROR = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x4000512c - /// RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x12c); - - /// address: 0x40005130 - /// Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX - /// buffer - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x130); - - /// address: 0x40005138 - /// Auto collision resolution process has started - pub const EVENTS_AUTOCOLRESSTARTED = @intToPtr(*volatile u32, base_address + 0x138); - - /// address: 0x40005148 - /// NFC Auto collision resolution error reported. - pub const EVENTS_COLLISION = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x4000514c - /// NFC Auto collision resolution successfully completed - pub const EVENTS_SELECTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40005150 - /// EasyDMA is ready to receive or send frames. - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x40005200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between FIELDDETECTED event and ACTIVATE task - FIELDDETECTED_ACTIVATE: u1, - /// Shortcut between FIELDLOST event and SENSE task - FIELDLOST_SENSE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x200); - - /// address: 0x40005300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1, - /// Enable or disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1, - /// Enable or disable interrupt for FIELDLOST event - FIELDLOST: u1, - /// Enable or disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1, - /// Enable or disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1, - /// Enable or disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1, - /// Enable or disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1, - /// Enable or disable interrupt for ERROR event - ERROR: u1, - reserved0: u1, - reserved1: u1, - /// Enable or disable interrupt for RXERROR event - RXERROR: u1, - /// Enable or disable interrupt for ENDRX event - ENDRX: u1, - /// Enable or disable interrupt for ENDTX event - ENDTX: u1, - reserved2: u1, - /// Enable or disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Enable or disable interrupt for COLLISION event - COLLISION: u1, - /// Enable or disable interrupt for SELECTED event - SELECTED: u1, - /// Enable or disable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x300); - - /// address: 0x40005304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1, - /// Write '1' to Enable interrupt for FIELDDETECTED event - FIELDDETECTED: u1, - /// Write '1' to Enable interrupt for FIELDLOST event - FIELDLOST: u1, - /// Write '1' to Enable interrupt for TXFRAMESTART event - TXFRAMESTART: u1, - /// Write '1' to Enable interrupt for TXFRAMEEND event - TXFRAMEEND: u1, - /// Write '1' to Enable interrupt for RXFRAMESTART event - RXFRAMESTART: u1, - /// Write '1' to Enable interrupt for RXFRAMEEND event - RXFRAMEEND: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for RXERROR event - RXERROR: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Write '1' to Enable interrupt for COLLISION event - COLLISION: u1, - /// Write '1' to Enable interrupt for SELECTED event - SELECTED: u1, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x304); - - /// address: 0x40005308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1, - /// Write '1' to Disable interrupt for FIELDDETECTED event - FIELDDETECTED: u1, - /// Write '1' to Disable interrupt for FIELDLOST event - FIELDLOST: u1, - /// Write '1' to Disable interrupt for TXFRAMESTART event - TXFRAMESTART: u1, - /// Write '1' to Disable interrupt for TXFRAMEEND event - TXFRAMEEND: u1, - /// Write '1' to Disable interrupt for RXFRAMESTART event - RXFRAMESTART: u1, - /// Write '1' to Disable interrupt for RXFRAMEEND event - RXFRAMEEND: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for RXERROR event - RXERROR: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for AUTOCOLRESSTARTED event - AUTOCOLRESSTARTED: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Write '1' to Disable interrupt for COLLISION event - COLLISION: u1, - /// Write '1' to Disable interrupt for SELECTED event - SELECTED: u1, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x308); - - /// address: 0x40005404 - /// NFC Error Status register - pub const ERRORSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - FRAMEDELAYTIMEOUT: u1, - reserved0: u1, - /// Field level is too high at max load resistance - NFCFIELDTOOSTRONG: u1, - /// Field level is too low at min load resistance - NFCFIELDTOOWEAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x404); - - /// address: 0x40005430 - /// Current value driven to the NFC Load Control - pub const CURRENTLOADCTRL = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x430); - - /// address: 0x4000543c - /// Indicates the presence or not of a valid field - pub const FIELDPRESENT = @intToPtr(*volatile Mmio(32, packed struct { - /// Indicates the presence or not of a valid field. Available only in the activated - /// state. - FIELDPRESENT: u1, - /// Indicates if the low level has locked to the field - LOCKDETECT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x43c); - - /// address: 0x40005504 - /// Minimum frame delay - pub const FRAMEDELAYMIN = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x504); - - /// address: 0x40005508 - /// Maximum frame delay - pub const FRAMEDELAYMAX = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x508); - - /// address: 0x4000550c - /// Configuration register for the Frame Delay Timer - pub const FRAMEDELAYMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x50c); - - /// address: 0x40005510 - /// Packet pointer for TXD and RXD data storage in Data RAM - pub const PACKETPTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte - /// aligned RAM address. - PTR: u32, - }), base_address + 0x510); - - /// address: 0x40005514 - /// Size of allocated for TXD and RXD data storage buffer in Data RAM - pub const MAXLEN = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x514); - - /// address: 0x40005590 - /// Last NFCID1 part (4, 7 or 10 bytes ID) - pub const NFCID1_LAST = @intToPtr(*volatile Mmio(32, packed struct { - /// NFCID1 byte Z (very last byte sent) - NFCID1_Z: u8, - /// NFCID1 byte Y - NFCID1_Y: u8, - /// NFCID1 byte X - NFCID1_X: u8, - /// NFCID1 byte W - NFCID1_W: u8, - }), base_address + 0x590); - - /// address: 0x40005594 - /// Second last NFCID1 part (7 or 10 bytes ID) - pub const NFCID1_2ND_LAST = @intToPtr(*volatile Mmio(32, packed struct { - /// NFCID1 byte V - NFCID1_V: u8, - /// NFCID1 byte U - NFCID1_U: u8, - /// NFCID1 byte T - NFCID1_T: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x594); - - /// address: 0x40005598 - /// Third last NFCID1 part (10 bytes ID) - pub const NFCID1_3RD_LAST = @intToPtr(*volatile Mmio(32, packed struct { - /// NFCID1 byte S - NFCID1_S: u8, - /// NFCID1 byte R - NFCID1_R: u8, - /// NFCID1 byte Q - NFCID1_Q: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x598); - - /// address: 0x400055a0 - /// NFC-A SENS_RES auto-response settings - pub const SENSRES = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC - /// Forum, NFC Digital Protocol Technical Specification - BITFRAMESDD: u5, - /// Reserved for future use. Shall be 0. - RFU5: u1, - /// NFCID1 size. This value is used by the Auto collision resolution engine. - NFCIDSIZE: u2, - /// Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES - /// response in the NFC Forum, NFC Digital Protocol Technical Specification - PLATFCONFIG: u4, - /// Reserved for future use. Shall be 0. - RFU74: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5a0); - - /// address: 0x400055a4 - /// NFC-A SEL_RES auto-response settings - pub const SELRES = @intToPtr(*volatile Mmio(32, packed struct { - /// Reserved for future use. Shall be 0. - RFU10: u2, - /// Cascade bit (controlled by hardware, write has no effect) - CASCADE: u1, - /// Reserved for future use. Shall be 0. - RFU43: u2, - /// Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC - /// Digital Protocol Technical Specification - PROTOCOL: u2, - /// Reserved for future use. Shall be 0. - RFU7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x5a4); - - pub const FRAMESTATUS = struct { - /// address: 0x40005000 - /// Result of last incoming frames - pub const RX = @intToPtr(*volatile Mmio(32, packed struct { - /// No valid End of Frame detected - CRCERROR: u1, - reserved0: u1, - /// Parity status of received frame - PARITYSTATUS: u1, - /// Overrun detected - OVERRUN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x0); - }; - - pub const TXD = struct { - /// address: 0x40005000 - /// Configuration of outgoing frames - pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Adding parity or not in the frame - PARITY: u1, - /// Discarding unused bits in start or at end of a Frame - DISCARDMODE: u1, - /// Adding SoF or not in TX frames - SOF: u1, - reserved0: u1, - /// CRC mode for outgoing frames - CRCMODETX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Size of outgoing frame - pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of bits in the last or first byte read from RAM that shall be included in - /// the frame (excluding parity bit). - TXDATABITS: u3, - /// Number of complete bytes that shall be included in the frame, excluding CRC, - /// parity and framing - TXDATABYTES: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - }; - - pub const RXD = struct { - /// address: 0x40005000 - /// Configuration of incoming frames - pub const FRAMECONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity expected or not in RX frame - PARITY: u1, - reserved0: u1, - /// SoF expected or not in RX frames - SOF: u1, - reserved1: u1, - /// CRC mode for incoming frames - CRCMODERX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Size of last incoming frame - pub const AMOUNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of bits in the last byte in the frame, if less than 8 (including CRC, but - /// excluding parity and SoF/EoF framing). - RXDATABITS: u3, - /// Number of complete bytes received in the frame (including CRC, but excluding - /// parity and SoF/EoF framing) - RXDATABYTES: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - }; - }; - /// GPIO Tasks and Events - pub const GPIOTE = struct { - pub const base_address = 0x40006000; - - /// address: 0x40006000 - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. - /// Action on pin is configured in CONFIG[0].POLARITY. - pub const TASKS_OUT = @intToPtr(*volatile [8]u32, base_address + 0x0); - - /// address: 0x40006030 - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. - /// Action on pin is to set it high. - pub const TASKS_SET = @intToPtr(*volatile [8]u32, base_address + 0x30); - - /// address: 0x40006060 - /// Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. - /// Action on pin is to set it low. - pub const TASKS_CLR = @intToPtr(*volatile [8]u32, base_address + 0x60); - - /// address: 0x40006100 - /// Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL - pub const EVENTS_IN = @intToPtr(*volatile [8]u32, base_address + 0x100); - - /// address: 0x4000617c - /// Event generated from multiple input GPIO pins with SENSE mechanism enabled - pub const EVENTS_PORT = @intToPtr(*volatile u32, base_address + 0x17c); - - /// address: 0x40006304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for IN[0] event - IN0: u1, - /// Write '1' to Enable interrupt for IN[1] event - IN1: u1, - /// Write '1' to Enable interrupt for IN[2] event - IN2: u1, - /// Write '1' to Enable interrupt for IN[3] event - IN3: u1, - /// Write '1' to Enable interrupt for IN[4] event - IN4: u1, - /// Write '1' to Enable interrupt for IN[5] event - IN5: u1, - /// Write '1' to Enable interrupt for IN[6] event - IN6: u1, - /// Write '1' to Enable interrupt for IN[7] event - IN7: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// Write '1' to Enable interrupt for PORT event - PORT: u1, - }), base_address + 0x304); - - /// address: 0x40006308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for IN[0] event - IN0: u1, - /// Write '1' to Disable interrupt for IN[1] event - IN1: u1, - /// Write '1' to Disable interrupt for IN[2] event - IN2: u1, - /// Write '1' to Disable interrupt for IN[3] event - IN3: u1, - /// Write '1' to Disable interrupt for IN[4] event - IN4: u1, - /// Write '1' to Disable interrupt for IN[5] event - IN5: u1, - /// Write '1' to Disable interrupt for IN[6] event - IN6: u1, - /// Write '1' to Disable interrupt for IN[7] event - IN7: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// Write '1' to Disable interrupt for PORT event - PORT: u1, - }), base_address + 0x308); - - /// address: 0x40006510 - /// Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and - /// IN[n] event - pub const CONFIG = @intToPtr(*volatile [8]Mmio(32, packed struct { - /// Mode - MODE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - PSEL: u5, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// When In task mode: Operation to be performed on output when OUT[n] task is - /// triggered. When In event mode: Operation on input that shall trigger IN[n] - /// event. - POLARITY: u2, - reserved9: u1, - reserved10: u1, - /// When in task mode: Initial value of the output when the GPIOTE channel is - /// configured. When in event mode: No effect. - OUTINIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x510); - }; - /// Analog to Digital Converter - pub const SAADC = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// Start the ADC and prepare the result buffer in RAM - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40007004 - /// Take one ADC sample, if scan is enabled all channels are sampled - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40007008 - /// Stop the ADC and terminate any on-going conversion - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000700c - /// Starts offset auto-calibration - pub const TASKS_CALIBRATEOFFSET = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40007100 - /// The ADC has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40007104 - /// The ADC has filled up the Result buffer - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40007108 - /// A conversion task has been completed. Depending on the mode, multiple - /// conversions might be needed for a result to be transferred to RAM. - pub const EVENTS_DONE = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000710c - /// A result is ready to get transferred to RAM. - pub const EVENTS_RESULTDONE = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40007110 - /// Calibration is complete - pub const EVENTS_CALIBRATEDONE = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40007114 - /// The ADC has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x40007300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1, - /// Enable or disable interrupt for END event - END: u1, - /// Enable or disable interrupt for DONE event - DONE: u1, - /// Enable or disable interrupt for RESULTDONE event - RESULTDONE: u1, - /// Enable or disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - /// Enable or disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1, - /// Enable or disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1, - /// Enable or disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1, - /// Enable or disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1, - /// Enable or disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1, - /// Enable or disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1, - /// Enable or disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1, - /// Enable or disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1, - /// Enable or disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1, - /// Enable or disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1, - /// Enable or disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1, - /// Enable or disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1, - /// Enable or disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1, - /// Enable or disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1, - /// Enable or disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1, - /// Enable or disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x300); - - /// address: 0x40007304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - /// Write '1' to Enable interrupt for DONE event - DONE: u1, - /// Write '1' to Enable interrupt for RESULTDONE event - RESULTDONE: u1, - /// Write '1' to Enable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for CH[0].LIMITH event - CH0LIMITH: u1, - /// Write '1' to Enable interrupt for CH[0].LIMITL event - CH0LIMITL: u1, - /// Write '1' to Enable interrupt for CH[1].LIMITH event - CH1LIMITH: u1, - /// Write '1' to Enable interrupt for CH[1].LIMITL event - CH1LIMITL: u1, - /// Write '1' to Enable interrupt for CH[2].LIMITH event - CH2LIMITH: u1, - /// Write '1' to Enable interrupt for CH[2].LIMITL event - CH2LIMITL: u1, - /// Write '1' to Enable interrupt for CH[3].LIMITH event - CH3LIMITH: u1, - /// Write '1' to Enable interrupt for CH[3].LIMITL event - CH3LIMITL: u1, - /// Write '1' to Enable interrupt for CH[4].LIMITH event - CH4LIMITH: u1, - /// Write '1' to Enable interrupt for CH[4].LIMITL event - CH4LIMITL: u1, - /// Write '1' to Enable interrupt for CH[5].LIMITH event - CH5LIMITH: u1, - /// Write '1' to Enable interrupt for CH[5].LIMITL event - CH5LIMITL: u1, - /// Write '1' to Enable interrupt for CH[6].LIMITH event - CH6LIMITH: u1, - /// Write '1' to Enable interrupt for CH[6].LIMITL event - CH6LIMITL: u1, - /// Write '1' to Enable interrupt for CH[7].LIMITH event - CH7LIMITH: u1, - /// Write '1' to Enable interrupt for CH[7].LIMITL event - CH7LIMITL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x40007308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - /// Write '1' to Disable interrupt for DONE event - DONE: u1, - /// Write '1' to Disable interrupt for RESULTDONE event - RESULTDONE: u1, - /// Write '1' to Disable interrupt for CALIBRATEDONE event - CALIBRATEDONE: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for CH[0].LIMITH event - CH0LIMITH: u1, - /// Write '1' to Disable interrupt for CH[0].LIMITL event - CH0LIMITL: u1, - /// Write '1' to Disable interrupt for CH[1].LIMITH event - CH1LIMITH: u1, - /// Write '1' to Disable interrupt for CH[1].LIMITL event - CH1LIMITL: u1, - /// Write '1' to Disable interrupt for CH[2].LIMITH event - CH2LIMITH: u1, - /// Write '1' to Disable interrupt for CH[2].LIMITL event - CH2LIMITL: u1, - /// Write '1' to Disable interrupt for CH[3].LIMITH event - CH3LIMITH: u1, - /// Write '1' to Disable interrupt for CH[3].LIMITL event - CH3LIMITL: u1, - /// Write '1' to Disable interrupt for CH[4].LIMITH event - CH4LIMITH: u1, - /// Write '1' to Disable interrupt for CH[4].LIMITL event - CH4LIMITL: u1, - /// Write '1' to Disable interrupt for CH[5].LIMITH event - CH5LIMITH: u1, - /// Write '1' to Disable interrupt for CH[5].LIMITL event - CH5LIMITL: u1, - /// Write '1' to Disable interrupt for CH[6].LIMITH event - CH6LIMITH: u1, - /// Write '1' to Disable interrupt for CH[6].LIMITL event - CH6LIMITL: u1, - /// Write '1' to Disable interrupt for CH[7].LIMITH event - CH7LIMITH: u1, - /// Write '1' to Disable interrupt for CH[7].LIMITL event - CH7LIMITL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x40007400 - /// Status - pub const STATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x40007500 - /// Enable or disable ADC - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x400075f0 - /// Resolution configuration - pub const RESOLUTION = @intToPtr(*volatile Mmio(32, packed struct { - /// Set the resolution - VAL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x5f0); - - /// address: 0x400075f4 - /// Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The - /// RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher - /// RESOLUTION should be used. - pub const OVERSAMPLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x5f4); - - /// address: 0x400075f8 - /// Controls normal or continuous sample rate - pub const SAMPLERATE = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture and compare value. Sample rate is 16 MHz/CC - CC: u11, - reserved0: u1, - /// Select mode for sample rate control - MODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x5f8); - - pub const EVENTS_CH = @ptrCast(*volatile [8]packed struct { - /// Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH - LIMITH: u32, - - /// Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW - LIMITL: u32, - }, base_address + 0x118); - - pub const CH = @ptrCast(*volatile [8]packed struct { - /// Description cluster[0]: Input positive pin selection for CH[0] - PSELP: MmioInt(32, u5), - - /// Description cluster[0]: Input negative pin selection for CH[0] - PSELN: MmioInt(32, u5), - - /// Description cluster[0]: Input configuration for CH[0] - CONFIG: Mmio(32, packed struct { - /// Positive channel resistor control - RESP: u2, - reserved0: u1, - reserved1: u1, - /// Negative channel resistor control - RESN: u2, - reserved2: u1, - reserved3: u1, - /// Gain control - GAIN: u3, - reserved4: u1, - /// Reference control - REFSEL: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Acquisition time, the time the ADC uses to sample the input voltage - TACQ: u3, - reserved8: u1, - /// Enable differential mode - MODE: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Enable burst mode - BURST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), - - /// Description cluster[0]: High/low limits for event monitoring a channel - LIMIT: Mmio(32, packed struct { - /// Low level limit - LOW: u16, - /// High level limit - HIGH: u16, - }), - }, base_address + 0x510); - - /// RESULT EasyDMA channel - pub const RESULT = struct { - /// address: 0x40007000 - /// Data pointer - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40007004 - /// Maximum number of buffer words to transfer - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x4); - - /// address: 0x40007008 - /// Number of buffer words transferred since last START - pub const AMOUNT = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x8); - }; - }; - /// Timer/Counter 0 - pub const TIMER0 = struct { - pub const base_address = 0x40008000; - - /// address: 0x40008000 - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40008004 - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40008008 - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000800c - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40008010 - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40008040 - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); - - /// address: 0x40008140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); - - /// address: 0x40008200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1, - reserved0: u1, - reserved1: u1, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40008304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x40008308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x40008504 - /// Timer mode selection - pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); - - /// address: 0x40008508 - /// Configure the number of bits used by the TIMER - pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); - - /// address: 0x40008510 - /// Timer prescaler register - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x40008540 - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); - }; - /// Timer/Counter 1 - pub const TIMER1 = struct { - pub const base_address = 0x40009000; - - /// address: 0x40009000 - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40009004 - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40009008 - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000900c - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40009010 - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40009040 - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); - - /// address: 0x40009140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); - - /// address: 0x40009200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1, - reserved0: u1, - reserved1: u1, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40009304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x40009308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x40009504 - /// Timer mode selection - pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); - - /// address: 0x40009508 - /// Configure the number of bits used by the TIMER - pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); - - /// address: 0x40009510 - /// Timer prescaler register - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x40009540 - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); - }; - /// Timer/Counter 2 - pub const TIMER2 = struct { - pub const base_address = 0x4000a000; - - /// address: 0x4000a000 - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000a004 - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000a008 - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000a00c - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4000a010 - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x4000a040 - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); - - /// address: 0x4000a140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); - - /// address: 0x4000a200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1, - reserved0: u1, - reserved1: u1, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x4000a304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x4000a308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x4000a504 - /// Timer mode selection - pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); - - /// address: 0x4000a508 - /// Configure the number of bits used by the TIMER - pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); - - /// address: 0x4000a510 - /// Timer prescaler register - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x4000a540 - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); - }; - /// Real time counter 0 - pub const RTC0 = struct { - pub const base_address = 0x4000b000; - - /// address: 0x4000b000 - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000b004 - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000b008 - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000b00c - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4000b100 - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000b104 - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4000b140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); - - /// address: 0x4000b304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x4000b308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x4000b340 - /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x340); - - /// address: 0x4000b344 - /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x344); - - /// address: 0x4000b348 - /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x348); - - /// address: 0x4000b504 - /// Current COUNTER value - pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); - - /// address: 0x4000b508 - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); - - /// address: 0x4000b540 - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Compare value - COMPARE: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x540); - }; - /// Temperature Sensor - pub const TEMP = struct { - pub const base_address = 0x4000c000; - - /// address: 0x4000c000 - /// Start temperature measurement - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000c004 - /// Stop temperature measurement - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000c100 - /// Temperature measurement complete, data ready - pub const EVENTS_DATARDY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000c304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for DATARDY event - DATARDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x304); - - /// address: 0x4000c308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for DATARDY event - DATARDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x308); - - /// address: 0x4000c508 - /// Temperature in degC (0.25deg steps) - pub const TEMP = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000c520 - /// Slope of 1st piece wise linear function - pub const A0 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x520); - - /// address: 0x4000c524 - /// Slope of 2nd piece wise linear function - pub const A1 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x524); - - /// address: 0x4000c528 - /// Slope of 3rd piece wise linear function - pub const A2 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x528); - - /// address: 0x4000c52c - /// Slope of 4th piece wise linear function - pub const A3 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x52c); - - /// address: 0x4000c530 - /// Slope of 5th piece wise linear function - pub const A4 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x530); - - /// address: 0x4000c534 - /// Slope of 6th piece wise linear function - pub const A5 = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x534); - - /// address: 0x4000c540 - /// y-intercept of 1st piece wise linear function - pub const B0 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x540); - - /// address: 0x4000c544 - /// y-intercept of 2nd piece wise linear function - pub const B1 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x544); - - /// address: 0x4000c548 - /// y-intercept of 3rd piece wise linear function - pub const B2 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x548); - - /// address: 0x4000c54c - /// y-intercept of 4th piece wise linear function - pub const B3 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x54c); - - /// address: 0x4000c550 - /// y-intercept of 5th piece wise linear function - pub const B4 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x550); - - /// address: 0x4000c554 - /// y-intercept of 6th piece wise linear function - pub const B5 = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x554); - - /// address: 0x4000c560 - /// End point of 1st piece wise linear function - pub const T0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x560); - - /// address: 0x4000c564 - /// End point of 2nd piece wise linear function - pub const T1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x564); - - /// address: 0x4000c568 - /// End point of 3rd piece wise linear function - pub const T2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x568); - - /// address: 0x4000c56c - /// End point of 4th piece wise linear function - pub const T3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x56c); - - /// address: 0x4000c570 - /// End point of 5th piece wise linear function - pub const T4 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x570); - }; - /// Random Number Generator - pub const RNG = struct { - pub const base_address = 0x4000d000; - - /// address: 0x4000d000 - /// Task starting the random number generator - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000d004 - /// Task stopping the random number generator - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000d100 - /// Event being generated for every new random number written to the VALUE register - pub const EVENTS_VALRDY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000d200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between VALRDY event and STOP task - VALRDY_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x200); - - /// address: 0x4000d304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for VALRDY event - VALRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x304); - - /// address: 0x4000d308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for VALRDY event - VALRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x308); - - /// address: 0x4000d504 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bias correction - DERCEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x504); - - /// address: 0x4000d508 - /// Output random number - pub const VALUE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x508); - }; - /// AES ECB Mode Encryption - pub const ECB = struct { - pub const base_address = 0x4000e000; - - /// address: 0x4000e000 - /// Start ECB block encrypt - pub const TASKS_STARTECB = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000e004 - /// Abort a possible executing ECB operation - pub const TASKS_STOPECB = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000e100 - /// ECB block encrypt complete - pub const EVENTS_ENDECB = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000e104 - /// ECB block encrypt aborted because of a STOPECB task or due to an error - pub const EVENTS_ERRORECB = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4000e304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for ENDECB event - ENDECB: u1, - /// Write '1' to Enable interrupt for ERRORECB event - ERRORECB: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x304); - - /// address: 0x4000e308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for ENDECB event - ENDECB: u1, - /// Write '1' to Disable interrupt for ERRORECB event - ERRORECB: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x308); - - /// address: 0x4000e504 - /// ECB block encrypt memory pointers - pub const ECBDATAPTR = @intToPtr(*volatile u32, base_address + 0x504); - }; - /// AES CCM Mode Encryption - pub const CCM = struct { - pub const base_address = 0x4000f000; - - /// address: 0x4000f000 - /// Start generation of key-stream. This operation will stop by itself when - /// completed. - pub const TASKS_KSGEN = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000f004 - /// Start encryption/decryption. This operation will stop by itself when completed. - pub const TASKS_CRYPT = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4000f008 - /// Stop encryption/decryption - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000f100 - /// Key-stream generation complete - pub const EVENTS_ENDKSGEN = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000f104 - /// Encrypt/decrypt complete - pub const EVENTS_ENDCRYPT = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4000f108 - /// CCM error event - pub const EVENTS_ERROR = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000f200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between ENDKSGEN event and CRYPT task - ENDKSGEN_CRYPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x200); - - /// address: 0x4000f304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for ENDKSGEN event - ENDKSGEN: u1, - /// Write '1' to Enable interrupt for ENDCRYPT event - ENDCRYPT: u1, - /// Write '1' to Enable interrupt for ERROR event - ERROR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x4000f308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for ENDKSGEN event - ENDKSGEN: u1, - /// Write '1' to Disable interrupt for ENDCRYPT event - ENDCRYPT: u1, - /// Write '1' to Disable interrupt for ERROR event - ERROR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x4000f400 - /// MIC check result - pub const MICSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x4000f500 - /// Enable - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); - - /// address: 0x4000f504 - /// Operation mode - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// The mode of operation to be used - MODE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Data rate that the CCM shall run in synch with - DATARATE: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Packet length configuration - LENGTH: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x504); - - /// address: 0x4000f508 - /// Pointer to data structure holding AES key and NONCE vector - pub const CNFPTR = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000f50c - /// Input pointer - pub const INPTR = @intToPtr(*volatile u32, base_address + 0x50c); - - /// address: 0x4000f510 - /// Output pointer - pub const OUTPTR = @intToPtr(*volatile u32, base_address + 0x510); - - /// address: 0x4000f514 - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); - }; - /// Accelerated Address Resolver - pub const AAR = struct { - pub const base_address = 0x4000f000; - - /// address: 0x4000f000 - /// Start resolving addresses based on IRKs specified in the IRK data structure - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4000f008 - /// Stop resolving addresses - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4000f100 - /// Address resolution procedure complete - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4000f104 - /// Address resolved - pub const EVENTS_RESOLVED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4000f108 - /// Address not resolved - pub const EVENTS_NOTRESOLVED = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4000f304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for END event - END: u1, - /// Write '1' to Enable interrupt for RESOLVED event - RESOLVED: u1, - /// Write '1' to Enable interrupt for NOTRESOLVED event - NOTRESOLVED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x4000f308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for END event - END: u1, - /// Write '1' to Disable interrupt for RESOLVED event - RESOLVED: u1, - /// Write '1' to Disable interrupt for NOTRESOLVED event - NOTRESOLVED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x4000f400 - /// Resolution status - pub const STATUS = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x400); - - /// address: 0x4000f500 - /// Enable AAR - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); - - /// address: 0x4000f504 - /// Number of IRKs - pub const NIRK = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x504); - - /// address: 0x4000f508 - /// Pointer to IRK data structure - pub const IRKPTR = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4000f510 - /// Pointer to the resolvable address - pub const ADDRPTR = @intToPtr(*volatile u32, base_address + 0x510); - - /// address: 0x4000f514 - /// Pointer to data area used for temporary storage - pub const SCRATCHPTR = @intToPtr(*volatile u32, base_address + 0x514); - }; - /// Watchdog Timer - pub const WDT = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// Start the watchdog - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40010100 - /// Watchdog timeout - pub const EVENTS_TIMEOUT = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40010304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TIMEOUT event - TIMEOUT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x304); - - /// address: 0x40010308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TIMEOUT event - TIMEOUT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x308); - - /// address: 0x40010400 - /// Run status - pub const RUNSTATUS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x40010404 - /// Request status - pub const REQSTATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// Request status for RR[0] register - RR0: u1, - /// Request status for RR[1] register - RR1: u1, - /// Request status for RR[2] register - RR2: u1, - /// Request status for RR[3] register - RR3: u1, - /// Request status for RR[4] register - RR4: u1, - /// Request status for RR[5] register - RR5: u1, - /// Request status for RR[6] register - RR6: u1, - /// Request status for RR[7] register - RR7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x404); - - /// address: 0x40010504 - /// Counter reload value - pub const CRV = @intToPtr(*volatile u32, base_address + 0x504); - - /// address: 0x40010508 - /// Enable register for reload request registers - pub const RREN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable RR[0] register - RR0: u1, - /// Enable or disable RR[1] register - RR1: u1, - /// Enable or disable RR[2] register - RR2: u1, - /// Enable or disable RR[3] register - RR3: u1, - /// Enable or disable RR[4] register - RR4: u1, - /// Enable or disable RR[5] register - RR5: u1, - /// Enable or disable RR[6] register - RR6: u1, - /// Enable or disable RR[7] register - RR7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x508); - - /// address: 0x4001050c - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Configure the watchdog to either be paused, or kept running, while the CPU is - /// sleeping - SLEEP: u1, - reserved0: u1, - reserved1: u1, - /// Configure the watchdog to either be paused, or kept running, while the CPU is - /// halted by the debugger - HALT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x50c); - - /// address: 0x40010600 - /// Description collection[0]: Reload request 0 - pub const RR = @intToPtr(*volatile [8]u32, base_address + 0x600); - }; - /// Real time counter 1 - pub const RTC1 = struct { - pub const base_address = 0x40011000; - - /// address: 0x40011000 - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40011004 - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40011008 - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4001100c - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40011100 - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40011104 - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40011140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); - - /// address: 0x40011304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x40011308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x40011340 - /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x340); - - /// address: 0x40011344 - /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x344); - - /// address: 0x40011348 - /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x348); - - /// address: 0x40011504 - /// Current COUNTER value - pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); - - /// address: 0x40011508 - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); - - /// address: 0x40011540 - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Compare value - COMPARE: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x540); - }; - /// Quadrature Decoder - pub const QDEC = struct { - pub const base_address = 0x40012000; - - /// address: 0x40012000 - /// Task starting the quadrature decoder - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40012004 - /// Task stopping the quadrature decoder - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40012008 - /// Read and clear ACC and ACCDBL - pub const TASKS_READCLRACC = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4001200c - /// Read and clear ACC - pub const TASKS_RDCLRACC = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40012010 - /// Read and clear ACCDBL - pub const TASKS_RDCLRDBL = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40012100 - /// Event being generated for every new sample value written to the SAMPLE register - pub const EVENTS_SAMPLERDY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40012104 - /// Non-null report ready - pub const EVENTS_REPORTRDY = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40012108 - /// ACC or ACCDBL register overflow - pub const EVENTS_ACCOF = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4001210c - /// Double displacement(s) detected - pub const EVENTS_DBLRDY = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40012110 - /// QDEC has been stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40012200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between REPORTRDY event and READCLRACC task - REPORTRDY_READCLRACC: u1, - /// Shortcut between SAMPLERDY event and STOP task - SAMPLERDY_STOP: u1, - /// Shortcut between REPORTRDY event and RDCLRACC task - REPORTRDY_RDCLRACC: u1, - /// Shortcut between REPORTRDY event and STOP task - REPORTRDY_STOP: u1, - /// Shortcut between DBLRDY event and RDCLRDBL task - DBLRDY_RDCLRDBL: u1, - /// Shortcut between DBLRDY event and STOP task - DBLRDY_STOP: u1, - /// Shortcut between SAMPLERDY event and READCLRACC task - SAMPLERDY_READCLRACC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x200); - - /// address: 0x40012304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for SAMPLERDY event - SAMPLERDY: u1, - /// Write '1' to Enable interrupt for REPORTRDY event - REPORTRDY: u1, - /// Write '1' to Enable interrupt for ACCOF event - ACCOF: u1, - /// Write '1' to Enable interrupt for DBLRDY event - DBLRDY: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x304); - - /// address: 0x40012308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for SAMPLERDY event - SAMPLERDY: u1, - /// Write '1' to Disable interrupt for REPORTRDY event - REPORTRDY: u1, - /// Write '1' to Disable interrupt for ACCOF event - ACCOF: u1, - /// Write '1' to Disable interrupt for DBLRDY event - DBLRDY: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x308); - - /// address: 0x40012500 - /// Enable the quadrature decoder - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x40012504 - /// LED output pin polarity - pub const LEDPOL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x504); - - /// address: 0x40012508 - /// Sample period - pub const SAMPLEPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); - - /// address: 0x4001250c - /// Motion sample value - pub const SAMPLE = @intToPtr(*volatile u32, base_address + 0x50c); - - /// address: 0x40012510 - /// Number of samples to be taken before REPORTRDY and DBLRDY events can be - /// generated - pub const REPORTPER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x40012514 - /// Register accumulating the valid transitions - pub const ACC = @intToPtr(*volatile u32, base_address + 0x514); - - /// address: 0x40012518 - /// Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - pub const ACCREAD = @intToPtr(*volatile u32, base_address + 0x518); - - /// address: 0x40012528 - /// Enable input debounce filters - pub const DBFEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x528); - - /// address: 0x40012540 - /// Time period the LED is switched ON prior to sampling - pub const LEDPRE = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x540); - - /// address: 0x40012544 - /// Register accumulating the number of detected double transitions - pub const ACCDBL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x544); - - /// address: 0x40012548 - /// Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - pub const ACCDBLREAD = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x548); - - pub const PSEL = struct { - /// address: 0x40012000 - /// Pin select for LED signal - pub const LED = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40012004 - /// Pin select for A signal - pub const A = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - - /// address: 0x40012008 - /// Pin select for B signal - pub const B = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x8); - }; - }; - /// Comparator - pub const COMP = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40013004 - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40013008 - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40013100 - /// COMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40013104 - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40013108 - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4001310c - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40013200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1, - /// Shortcut between READY event and STOP task - READY_STOP: u1, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1, - /// Shortcut between UP event and STOP task - UP_STOP: u1, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x40013300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for READY event - READY: u1, - /// Enable or disable interrupt for DOWN event - DOWN: u1, - /// Enable or disable interrupt for UP event - UP: u1, - /// Enable or disable interrupt for CROSS event - CROSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x300); - - /// address: 0x40013304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1, - /// Write '1' to Enable interrupt for UP event - UP: u1, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x304); - - /// address: 0x40013308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1, - /// Write '1' to Disable interrupt for UP event - UP: u1, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x308); - - /// address: 0x40013400 - /// Compare result - pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x40013500 - /// COMP enable - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); - - /// address: 0x40013504 - /// Pin select - pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); - - /// address: 0x40013508 - /// Reference source select for single-ended mode - pub const REFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x508); - - /// address: 0x4001350c - /// External reference select - pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); - - /// address: 0x40013530 - /// Threshold configuration for hysteresis unit - pub const TH = @intToPtr(*volatile Mmio(32, packed struct { - /// VDOWN = (THDOWN+1)/64*VREF - THDOWN: u6, - reserved0: u1, - reserved1: u1, - /// VUP = (THUP+1)/64*VREF - THUP: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x530); - - /// address: 0x40013534 - /// Mode configuration - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Speed and power modes - SP: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Main operation modes - MAIN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x534); - - /// address: 0x40013538 - /// Comparator hysteresis enable - pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); - - /// address: 0x4001353c - /// Current source select on analog input - pub const ISOURCE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x53c); - }; - /// Low Power Comparator - pub const LPCOMP = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// Start comparator - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40013004 - /// Stop comparator - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40013008 - /// Sample comparator value - pub const TASKS_SAMPLE = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x40013100 - /// LPCOMP is ready and output is valid - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40013104 - /// Downward crossing - pub const EVENTS_DOWN = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40013108 - /// Upward crossing - pub const EVENTS_UP = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4001310c - /// Downward or upward crossing - pub const EVENTS_CROSS = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x40013200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between READY event and SAMPLE task - READY_SAMPLE: u1, - /// Shortcut between READY event and STOP task - READY_STOP: u1, - /// Shortcut between DOWN event and STOP task - DOWN_STOP: u1, - /// Shortcut between UP event and STOP task - UP_STOP: u1, - /// Shortcut between CROSS event and STOP task - CROSS_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x40013304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for READY event - READY: u1, - /// Write '1' to Enable interrupt for DOWN event - DOWN: u1, - /// Write '1' to Enable interrupt for UP event - UP: u1, - /// Write '1' to Enable interrupt for CROSS event - CROSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x304); - - /// address: 0x40013308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for READY event - READY: u1, - /// Write '1' to Disable interrupt for DOWN event - DOWN: u1, - /// Write '1' to Disable interrupt for UP event - UP: u1, - /// Write '1' to Disable interrupt for CROSS event - CROSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x308); - - /// address: 0x40013400 - /// Compare result - pub const RESULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x40013500 - /// Enable LPCOMP - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x500); - - /// address: 0x40013504 - /// Input pin select - pub const PSEL = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x504); - - /// address: 0x40013508 - /// Reference select - pub const REFSEL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x508); - - /// address: 0x4001350c - /// External reference select - pub const EXTREFSEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); - - /// address: 0x40013520 - /// Analog detect configuration - pub const ANADETECT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x520); - - /// address: 0x40013538 - /// Comparator hysteresis enable - pub const HYST = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x538); - }; - /// Software interrupt 0 - pub const SWI0 = struct { - pub const base_address = 0x40014000; - - /// address: 0x40014000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 0 - pub const EGU0 = struct { - pub const base_address = 0x40014000; - - /// address: 0x40014000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40014100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40014300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40014304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40014308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Software interrupt 1 - pub const SWI1 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 1 - pub const EGU1 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40015100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40015300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40015304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40015308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Software interrupt 2 - pub const SWI2 = struct { - pub const base_address = 0x40016000; - - /// address: 0x40016000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 2 - pub const EGU2 = struct { - pub const base_address = 0x40016000; - - /// address: 0x40016000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40016100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40016300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40016304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40016308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Software interrupt 3 - pub const SWI3 = struct { - pub const base_address = 0x40017000; - - /// address: 0x40017000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 3 - pub const EGU3 = struct { - pub const base_address = 0x40017000; - - /// address: 0x40017000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40017100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40017300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40017304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40017308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Software interrupt 4 - pub const SWI4 = struct { - pub const base_address = 0x40018000; - - /// address: 0x40018000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 4 - pub const EGU4 = struct { - pub const base_address = 0x40018000; - - /// address: 0x40018000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40018100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40018300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40018304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40018308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Software interrupt 5 - pub const SWI5 = struct { - pub const base_address = 0x40019000; - - /// address: 0x40019000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// Event Generator Unit 5 - pub const EGU5 = struct { - pub const base_address = 0x40019000; - - /// address: 0x40019000 - /// Description collection[0]: Trigger 0 for triggering the corresponding - /// TRIGGERED[0] event - pub const TASKS_TRIGGER = @intToPtr(*volatile [16]u32, base_address + 0x0); - - /// address: 0x40019100 - /// Description collection[0]: Event number 0 generated by triggering the - /// corresponding TRIGGER[0] task - pub const EVENTS_TRIGGERED = @intToPtr(*volatile [16]u32, base_address + 0x100); - - /// address: 0x40019300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Enable or disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Enable or disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Enable or disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Enable or disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Enable or disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Enable or disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Enable or disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Enable or disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Enable or disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Enable or disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Enable or disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Enable or disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Enable or disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Enable or disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Enable or disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x300); - - /// address: 0x40019304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Enable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Enable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Enable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Enable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Enable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Enable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Enable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Enable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Enable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Enable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Enable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Enable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Enable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Enable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Enable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x304); - - /// address: 0x40019308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TRIGGERED[0] event - TRIGGERED0: u1, - /// Write '1' to Disable interrupt for TRIGGERED[1] event - TRIGGERED1: u1, - /// Write '1' to Disable interrupt for TRIGGERED[2] event - TRIGGERED2: u1, - /// Write '1' to Disable interrupt for TRIGGERED[3] event - TRIGGERED3: u1, - /// Write '1' to Disable interrupt for TRIGGERED[4] event - TRIGGERED4: u1, - /// Write '1' to Disable interrupt for TRIGGERED[5] event - TRIGGERED5: u1, - /// Write '1' to Disable interrupt for TRIGGERED[6] event - TRIGGERED6: u1, - /// Write '1' to Disable interrupt for TRIGGERED[7] event - TRIGGERED7: u1, - /// Write '1' to Disable interrupt for TRIGGERED[8] event - TRIGGERED8: u1, - /// Write '1' to Disable interrupt for TRIGGERED[9] event - TRIGGERED9: u1, - /// Write '1' to Disable interrupt for TRIGGERED[10] event - TRIGGERED10: u1, - /// Write '1' to Disable interrupt for TRIGGERED[11] event - TRIGGERED11: u1, - /// Write '1' to Disable interrupt for TRIGGERED[12] event - TRIGGERED12: u1, - /// Write '1' to Disable interrupt for TRIGGERED[13] event - TRIGGERED13: u1, - /// Write '1' to Disable interrupt for TRIGGERED[14] event - TRIGGERED14: u1, - /// Write '1' to Disable interrupt for TRIGGERED[15] event - TRIGGERED15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x308); - }; - /// Timer/Counter 3 - pub const TIMER3 = struct { - pub const base_address = 0x4001a000; - - /// address: 0x4001a000 - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4001a004 - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4001a008 - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4001a00c - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4001a010 - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x4001a040 - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); - - /// address: 0x4001a140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); - - /// address: 0x4001a200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1, - reserved0: u1, - reserved1: u1, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x4001a304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x4001a308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x4001a504 - /// Timer mode selection - pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); - - /// address: 0x4001a508 - /// Configure the number of bits used by the TIMER - pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); - - /// address: 0x4001a510 - /// Timer prescaler register - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x4001a540 - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); - }; - /// Timer/Counter 4 - pub const TIMER4 = struct { - pub const base_address = 0x4001b000; - - /// address: 0x4001b000 - /// Start Timer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4001b004 - /// Stop Timer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4001b008 - /// Increment Timer (Counter mode only) - pub const TASKS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4001b00c - /// Clear time - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x4001b010 - /// Deprecated register - Shut down timer - pub const TASKS_SHUTDOWN = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x4001b040 - /// Description collection[0]: Capture Timer value to CC[0] register - pub const TASKS_CAPTURE = @intToPtr(*volatile [6]u32, base_address + 0x40); - - /// address: 0x4001b140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [6]u32, base_address + 0x140); - - /// address: 0x4001b200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between COMPARE[0] event and CLEAR task - COMPARE0_CLEAR: u1, - /// Shortcut between COMPARE[1] event and CLEAR task - COMPARE1_CLEAR: u1, - /// Shortcut between COMPARE[2] event and CLEAR task - COMPARE2_CLEAR: u1, - /// Shortcut between COMPARE[3] event and CLEAR task - COMPARE3_CLEAR: u1, - /// Shortcut between COMPARE[4] event and CLEAR task - COMPARE4_CLEAR: u1, - /// Shortcut between COMPARE[5] event and CLEAR task - COMPARE5_CLEAR: u1, - reserved0: u1, - reserved1: u1, - /// Shortcut between COMPARE[0] event and STOP task - COMPARE0_STOP: u1, - /// Shortcut between COMPARE[1] event and STOP task - COMPARE1_STOP: u1, - /// Shortcut between COMPARE[2] event and STOP task - COMPARE2_STOP: u1, - /// Shortcut between COMPARE[3] event and STOP task - COMPARE3_STOP: u1, - /// Shortcut between COMPARE[4] event and STOP task - COMPARE4_STOP: u1, - /// Shortcut between COMPARE[5] event and STOP task - COMPARE5_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x4001b304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Enable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Enable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x304); - - /// address: 0x4001b308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - /// Write '1' to Disable interrupt for COMPARE[4] event - COMPARE4: u1, - /// Write '1' to Disable interrupt for COMPARE[5] event - COMPARE5: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x308); - - /// address: 0x4001b504 - /// Timer mode selection - pub const MODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x504); - - /// address: 0x4001b508 - /// Configure the number of bits used by the TIMER - pub const BITMODE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x508); - - /// address: 0x4001b510 - /// Timer prescaler register - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x510); - - /// address: 0x4001b540 - /// Description collection[0]: Capture/Compare register 0 - pub const CC = @intToPtr(*volatile [6]u32, base_address + 0x540); - }; - /// Pulse Width Modulation Unit 0 - pub const PWM0 = struct { - pub const base_address = 0x4001c000; - - /// address: 0x4001c004 - /// Stops PWM pulse generation on all channels at the end of current PWM period, and - /// stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4001c008 - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); - - /// address: 0x4001c010 - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x4001c104 - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4001c108 - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); - - /// address: 0x4001c110 - /// Description collection[0]: Emitted at end of every sequence 0, when last value - /// from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); - - /// address: 0x4001c118 - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x4001c11c - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x4001c200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x4001c300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x300); - - /// address: 0x4001c304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x304); - - /// address: 0x4001c308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x308); - - /// address: 0x4001c500 - /// PWM module enable register - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x4001c504 - /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x504); - - /// address: 0x4001c508 - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); - - /// address: 0x4001c50c - /// Configuration for PWM_CLK - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); - - /// address: 0x4001c510 - /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Selects source for advancing the active sequence - MODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x510); - - /// address: 0x4001c514 - /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x514); - - pub const SEQ = @ptrCast(*volatile [2]packed struct { - /// Description cluster[0]: Beginning address in Data RAM of this sequence - PTR: u32, - - /// Description cluster[0]: Amount of values (duty cycles) in this sequence - CNT: MmioInt(32, u15), - - /// Description cluster[0]: Amount of additional PWM periods between samples loaded - /// into compare register - REFRESH: Mmio(32, packed struct { - /// Amount of additional PWM periods between samples loaded into compare register - /// (load every REFRESH.CNT+1 PWM periods) - CNT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), - - /// Description cluster[0]: Time added after the sequence - ENDDELAY: Mmio(32, packed struct { - /// Time added after the sequence in PWM periods - CNT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), - padding0: u32, - padding1: u32, - padding2: u32, - padding3: u32, - }, base_address + 0x520); - - pub const PSEL = struct { - /// address: 0x4001c000 - /// Description collection[0]: Output pin select for PWM channel 0 - pub const OUT = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - }; - }; - /// Pulse Density Modulation (Digital Microphone) Interface - pub const PDM = struct { - pub const base_address = 0x4001d000; - - /// address: 0x4001d000 - /// Starts continuous PDM transfer - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x4001d004 - /// Stops PDM transfer - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x4001d100 - /// PDM transfer has started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x4001d104 - /// PDM transfer has finished - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x4001d108 - /// The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last - /// sample after a STOP task has been received) to Data RAM - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x4001d300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for STARTED event - STARTED: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - /// Enable or disable interrupt for END event - END: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x300); - - /// address: 0x4001d304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x4001d308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x4001d500 - /// PDM module enable register - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x4001d504 - /// PDM clock generator control - pub const PDMCLKCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// PDM_CLK frequency - FREQ: u32, - }), base_address + 0x504); - - /// address: 0x4001d508 - /// Defines the routing of the connected PDM microphones' signals - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Mono or stereo operation - OPERATION: u1, - /// Defines on which PDM_CLK edge Left (or mono) is sampled - EDGE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x508); - - /// address: 0x4001d518 - /// Left output gain adjustment - pub const GAINL = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x518); - - /// address: 0x4001d51c - /// Right output gain adjustment - pub const GAINR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - pub const PSEL = struct { - /// address: 0x4001d000 - /// Pin number configuration for PDM CLK signal - pub const CLK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x4001d004 - /// Pin number configuration for PDM DIN signal - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - }; - - pub const SAMPLE = struct { - /// address: 0x4001d000 - /// RAM address pointer to write samples to with EasyDMA - pub const PTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Address to write PDM samples to over DMA - SAMPLEPTR: u32, - }), base_address + 0x0); - - /// address: 0x4001d004 - /// Number of samples to allocate memory for in EasyDMA mode - pub const MAXCNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Length of DMA RAM allocation in number of samples - BUFFSIZE: u15, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - }; - }; - /// Non Volatile Memory Controller - pub const NVMC = struct { - pub const base_address = 0x4001e000; - - /// address: 0x4001e400 - /// Ready flag - pub const READY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x400); - - /// address: 0x4001e504 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Program memory access mode. It is strongly recommended to only activate erase - /// and write modes when they are actively used. Enabling write or erase will - /// invalidate the cache and keep it invalidated. - WEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x504); - - /// address: 0x4001e508 - /// Register for erasing a page in Code area - pub const ERASEPAGE = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4001e508 - /// Deprecated register - Register for erasing a page in Code area. Equivalent to - /// ERASEPAGE. - pub const ERASEPCR1 = @intToPtr(*volatile u32, base_address + 0x508); - - /// address: 0x4001e50c - /// Register for erasing all non-volatile user memory - pub const ERASEALL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50c); - - /// address: 0x4001e510 - /// Deprecated register - Register for erasing a page in Code area. Equivalent to - /// ERASEPAGE. - pub const ERASEPCR0 = @intToPtr(*volatile u32, base_address + 0x510); - - /// address: 0x4001e514 - /// Register for erasing User Information Configuration Registers - pub const ERASEUICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x514); - - /// address: 0x4001e540 - /// I-Code cache configuration register. - pub const ICACHECNF = @intToPtr(*volatile Mmio(32, packed struct { - /// Cache enable - CACHEEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Cache profiling enable - CACHEPROFEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x540); - - /// address: 0x4001e548 - /// I-Code cache hit counter. - pub const IHIT = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of cache hits - HITS: u32, - }), base_address + 0x548); - - /// address: 0x4001e54c - /// I-Code cache miss counter. - pub const IMISS = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of cache misses - MISSES: u32, - }), base_address + 0x54c); - }; - /// Programmable Peripheral Interconnect - pub const PPI = struct { - pub const base_address = 0x4001f000; - - /// address: 0x4001f500 - /// Channel enable register - pub const CHEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable channel 0 - CH0: u1, - /// Enable or disable channel 1 - CH1: u1, - /// Enable or disable channel 2 - CH2: u1, - /// Enable or disable channel 3 - CH3: u1, - /// Enable or disable channel 4 - CH4: u1, - /// Enable or disable channel 5 - CH5: u1, - /// Enable or disable channel 6 - CH6: u1, - /// Enable or disable channel 7 - CH7: u1, - /// Enable or disable channel 8 - CH8: u1, - /// Enable or disable channel 9 - CH9: u1, - /// Enable or disable channel 10 - CH10: u1, - /// Enable or disable channel 11 - CH11: u1, - /// Enable or disable channel 12 - CH12: u1, - /// Enable or disable channel 13 - CH13: u1, - /// Enable or disable channel 14 - CH14: u1, - /// Enable or disable channel 15 - CH15: u1, - /// Enable or disable channel 16 - CH16: u1, - /// Enable or disable channel 17 - CH17: u1, - /// Enable or disable channel 18 - CH18: u1, - /// Enable or disable channel 19 - CH19: u1, - /// Enable or disable channel 20 - CH20: u1, - /// Enable or disable channel 21 - CH21: u1, - /// Enable or disable channel 22 - CH22: u1, - /// Enable or disable channel 23 - CH23: u1, - /// Enable or disable channel 24 - CH24: u1, - /// Enable or disable channel 25 - CH25: u1, - /// Enable or disable channel 26 - CH26: u1, - /// Enable or disable channel 27 - CH27: u1, - /// Enable or disable channel 28 - CH28: u1, - /// Enable or disable channel 29 - CH29: u1, - /// Enable or disable channel 30 - CH30: u1, - /// Enable or disable channel 31 - CH31: u1, - }), base_address + 0x500); - - /// address: 0x4001f504 - /// Channel enable set register - pub const CHENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 enable set register. Writing '0' has no effect - CH0: u1, - /// Channel 1 enable set register. Writing '0' has no effect - CH1: u1, - /// Channel 2 enable set register. Writing '0' has no effect - CH2: u1, - /// Channel 3 enable set register. Writing '0' has no effect - CH3: u1, - /// Channel 4 enable set register. Writing '0' has no effect - CH4: u1, - /// Channel 5 enable set register. Writing '0' has no effect - CH5: u1, - /// Channel 6 enable set register. Writing '0' has no effect - CH6: u1, - /// Channel 7 enable set register. Writing '0' has no effect - CH7: u1, - /// Channel 8 enable set register. Writing '0' has no effect - CH8: u1, - /// Channel 9 enable set register. Writing '0' has no effect - CH9: u1, - /// Channel 10 enable set register. Writing '0' has no effect - CH10: u1, - /// Channel 11 enable set register. Writing '0' has no effect - CH11: u1, - /// Channel 12 enable set register. Writing '0' has no effect - CH12: u1, - /// Channel 13 enable set register. Writing '0' has no effect - CH13: u1, - /// Channel 14 enable set register. Writing '0' has no effect - CH14: u1, - /// Channel 15 enable set register. Writing '0' has no effect - CH15: u1, - /// Channel 16 enable set register. Writing '0' has no effect - CH16: u1, - /// Channel 17 enable set register. Writing '0' has no effect - CH17: u1, - /// Channel 18 enable set register. Writing '0' has no effect - CH18: u1, - /// Channel 19 enable set register. Writing '0' has no effect - CH19: u1, - /// Channel 20 enable set register. Writing '0' has no effect - CH20: u1, - /// Channel 21 enable set register. Writing '0' has no effect - CH21: u1, - /// Channel 22 enable set register. Writing '0' has no effect - CH22: u1, - /// Channel 23 enable set register. Writing '0' has no effect - CH23: u1, - /// Channel 24 enable set register. Writing '0' has no effect - CH24: u1, - /// Channel 25 enable set register. Writing '0' has no effect - CH25: u1, - /// Channel 26 enable set register. Writing '0' has no effect - CH26: u1, - /// Channel 27 enable set register. Writing '0' has no effect - CH27: u1, - /// Channel 28 enable set register. Writing '0' has no effect - CH28: u1, - /// Channel 29 enable set register. Writing '0' has no effect - CH29: u1, - /// Channel 30 enable set register. Writing '0' has no effect - CH30: u1, - /// Channel 31 enable set register. Writing '0' has no effect - CH31: u1, - }), base_address + 0x504); - - /// address: 0x4001f508 - /// Channel enable clear register - pub const CHENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 enable clear register. Writing '0' has no effect - CH0: u1, - /// Channel 1 enable clear register. Writing '0' has no effect - CH1: u1, - /// Channel 2 enable clear register. Writing '0' has no effect - CH2: u1, - /// Channel 3 enable clear register. Writing '0' has no effect - CH3: u1, - /// Channel 4 enable clear register. Writing '0' has no effect - CH4: u1, - /// Channel 5 enable clear register. Writing '0' has no effect - CH5: u1, - /// Channel 6 enable clear register. Writing '0' has no effect - CH6: u1, - /// Channel 7 enable clear register. Writing '0' has no effect - CH7: u1, - /// Channel 8 enable clear register. Writing '0' has no effect - CH8: u1, - /// Channel 9 enable clear register. Writing '0' has no effect - CH9: u1, - /// Channel 10 enable clear register. Writing '0' has no effect - CH10: u1, - /// Channel 11 enable clear register. Writing '0' has no effect - CH11: u1, - /// Channel 12 enable clear register. Writing '0' has no effect - CH12: u1, - /// Channel 13 enable clear register. Writing '0' has no effect - CH13: u1, - /// Channel 14 enable clear register. Writing '0' has no effect - CH14: u1, - /// Channel 15 enable clear register. Writing '0' has no effect - CH15: u1, - /// Channel 16 enable clear register. Writing '0' has no effect - CH16: u1, - /// Channel 17 enable clear register. Writing '0' has no effect - CH17: u1, - /// Channel 18 enable clear register. Writing '0' has no effect - CH18: u1, - /// Channel 19 enable clear register. Writing '0' has no effect - CH19: u1, - /// Channel 20 enable clear register. Writing '0' has no effect - CH20: u1, - /// Channel 21 enable clear register. Writing '0' has no effect - CH21: u1, - /// Channel 22 enable clear register. Writing '0' has no effect - CH22: u1, - /// Channel 23 enable clear register. Writing '0' has no effect - CH23: u1, - /// Channel 24 enable clear register. Writing '0' has no effect - CH24: u1, - /// Channel 25 enable clear register. Writing '0' has no effect - CH25: u1, - /// Channel 26 enable clear register. Writing '0' has no effect - CH26: u1, - /// Channel 27 enable clear register. Writing '0' has no effect - CH27: u1, - /// Channel 28 enable clear register. Writing '0' has no effect - CH28: u1, - /// Channel 29 enable clear register. Writing '0' has no effect - CH29: u1, - /// Channel 30 enable clear register. Writing '0' has no effect - CH30: u1, - /// Channel 31 enable clear register. Writing '0' has no effect - CH31: u1, - }), base_address + 0x508); - - /// address: 0x4001f800 - /// Description collection[0]: Channel group 0 - pub const CHG = @intToPtr(*volatile [6]Mmio(32, packed struct { - /// Include or exclude channel 0 - CH0: u1, - /// Include or exclude channel 1 - CH1: u1, - /// Include or exclude channel 2 - CH2: u1, - /// Include or exclude channel 3 - CH3: u1, - /// Include or exclude channel 4 - CH4: u1, - /// Include or exclude channel 5 - CH5: u1, - /// Include or exclude channel 6 - CH6: u1, - /// Include or exclude channel 7 - CH7: u1, - /// Include or exclude channel 8 - CH8: u1, - /// Include or exclude channel 9 - CH9: u1, - /// Include or exclude channel 10 - CH10: u1, - /// Include or exclude channel 11 - CH11: u1, - /// Include or exclude channel 12 - CH12: u1, - /// Include or exclude channel 13 - CH13: u1, - /// Include or exclude channel 14 - CH14: u1, - /// Include or exclude channel 15 - CH15: u1, - /// Include or exclude channel 16 - CH16: u1, - /// Include or exclude channel 17 - CH17: u1, - /// Include or exclude channel 18 - CH18: u1, - /// Include or exclude channel 19 - CH19: u1, - /// Include or exclude channel 20 - CH20: u1, - /// Include or exclude channel 21 - CH21: u1, - /// Include or exclude channel 22 - CH22: u1, - /// Include or exclude channel 23 - CH23: u1, - /// Include or exclude channel 24 - CH24: u1, - /// Include or exclude channel 25 - CH25: u1, - /// Include or exclude channel 26 - CH26: u1, - /// Include or exclude channel 27 - CH27: u1, - /// Include or exclude channel 28 - CH28: u1, - /// Include or exclude channel 29 - CH29: u1, - /// Include or exclude channel 30 - CH30: u1, - /// Include or exclude channel 31 - CH31: u1, - }), base_address + 0x800); - - /// Channel group tasks - pub const TASKS_CHG = @ptrCast(*volatile [6]packed struct { - /// Description cluster[0]: Enable channel group 0 - EN: u32, - - /// Description cluster[0]: Disable channel group 0 - DIS: u32, - }, base_address + 0x0); - - /// PPI Channel - pub const CH = @ptrCast(*volatile [20]packed struct { - /// Description cluster[0]: Channel 0 event end-point - EEP: u32, - - /// Description cluster[0]: Channel 0 task end-point - TEP: u32, - }, base_address + 0x510); - - /// Fork - pub const FORK = @ptrCast(*volatile [32]packed struct { - /// Description cluster[0]: Channel 0 task end-point - TEP: u32, - }, base_address + 0x910); - }; - /// Memory Watch Unit - pub const MWU = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Enable or disable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Enable or disable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Enable or disable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Enable or disable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Enable or disable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Enable or disable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Enable or disable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable or disable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Enable or disable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Enable or disable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Enable or disable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x300); - - /// address: 0x40020304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Write '1' to Enable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Write '1' to Enable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Write '1' to Enable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Write '1' to Enable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Write '1' to Enable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Write '1' to Enable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Write '1' to Enable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Write '1' to Enable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Write '1' to Enable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Write '1' to Enable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x304); - - /// address: 0x40020308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Write '1' to Disable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Write '1' to Disable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Write '1' to Disable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Write '1' to Disable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Write '1' to Disable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Write '1' to Disable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Write '1' to Disable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Write '1' to Disable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Write '1' to Disable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Write '1' to Disable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x308); - - /// address: 0x40020320 - /// Enable or disable non-maskable interrupt - pub const NMIEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Enable or disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Enable or disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Enable or disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Enable or disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Enable or disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Enable or disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Enable or disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable or disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Enable or disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Enable or disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Enable or disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x320); - - /// address: 0x40020324 - /// Enable non-maskable interrupt - pub const NMIENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Write '1' to Enable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Write '1' to Enable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Write '1' to Enable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x324); - - /// address: 0x40020328 - /// Disable non-maskable interrupt - pub const NMIENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable non-maskable interrupt for REGION[0].WA event - REGION0WA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[0].RA event - REGION0RA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[1].WA event - REGION1WA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[1].RA event - REGION1RA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[2].WA event - REGION2WA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[2].RA event - REGION2RA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[3].WA event - REGION3WA: u1, - /// Write '1' to Disable non-maskable interrupt for REGION[3].RA event - REGION3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].WA event - PREGION0WA: u1, - /// Write '1' to Disable non-maskable interrupt for PREGION[0].RA event - PREGION0RA: u1, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].WA event - PREGION1WA: u1, - /// Write '1' to Disable non-maskable interrupt for PREGION[1].RA event - PREGION1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x328); - - /// address: 0x40020510 - /// Enable/disable regions watch - pub const REGIONEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable/disable write access watch in region[0] - RGN0WA: u1, - /// Enable/disable read access watch in region[0] - RGN0RA: u1, - /// Enable/disable write access watch in region[1] - RGN1WA: u1, - /// Enable/disable read access watch in region[1] - RGN1RA: u1, - /// Enable/disable write access watch in region[2] - RGN2WA: u1, - /// Enable/disable read access watch in region[2] - RGN2RA: u1, - /// Enable/disable write access watch in region[3] - RGN3WA: u1, - /// Enable/disable read access watch in region[3] - RGN3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable/disable write access watch in PREGION[0] - PRGN0WA: u1, - /// Enable/disable read access watch in PREGION[0] - PRGN0RA: u1, - /// Enable/disable write access watch in PREGION[1] - PRGN1WA: u1, - /// Enable/disable read access watch in PREGION[1] - PRGN1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x510); - - /// address: 0x40020514 - /// Enable regions watch - pub const REGIONENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable write access watch in region[0] - RGN0WA: u1, - /// Enable read access watch in region[0] - RGN0RA: u1, - /// Enable write access watch in region[1] - RGN1WA: u1, - /// Enable read access watch in region[1] - RGN1RA: u1, - /// Enable write access watch in region[2] - RGN2WA: u1, - /// Enable read access watch in region[2] - RGN2RA: u1, - /// Enable write access watch in region[3] - RGN3WA: u1, - /// Enable read access watch in region[3] - RGN3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Enable write access watch in PREGION[0] - PRGN0WA: u1, - /// Enable read access watch in PREGION[0] - PRGN0RA: u1, - /// Enable write access watch in PREGION[1] - PRGN1WA: u1, - /// Enable read access watch in PREGION[1] - PRGN1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x514); - - /// address: 0x40020518 - /// Disable regions watch - pub const REGIONENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Disable write access watch in region[0] - RGN0WA: u1, - /// Disable read access watch in region[0] - RGN0RA: u1, - /// Disable write access watch in region[1] - RGN1WA: u1, - /// Disable read access watch in region[1] - RGN1RA: u1, - /// Disable write access watch in region[2] - RGN2WA: u1, - /// Disable read access watch in region[2] - RGN2RA: u1, - /// Disable write access watch in region[3] - RGN3WA: u1, - /// Disable read access watch in region[3] - RGN3RA: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Disable write access watch in PREGION[0] - PRGN0WA: u1, - /// Disable read access watch in PREGION[0] - PRGN0RA: u1, - /// Disable write access watch in PREGION[1] - PRGN1WA: u1, - /// Disable read access watch in PREGION[1] - PRGN1RA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x518); - - pub const EVENTS_REGION = @ptrCast(*volatile [4]packed struct { - /// Description cluster[0]: Write access to region 0 detected - WA: u32, - - /// Description cluster[0]: Read access to region 0 detected - RA: u32, - }, base_address + 0x100); - - pub const EVENTS_PREGION = @ptrCast(*volatile [2]packed struct { - /// Description cluster[0]: Write access to peripheral region 0 detected - WA: u32, - - /// Description cluster[0]: Read access to peripheral region 0 detected - RA: u32, - }, base_address + 0x160); - - pub const PERREGION = @ptrCast(*volatile [2]packed struct { - /// Description cluster[0]: Source of event/interrupt in region 0, write access - /// detected while corresponding subregion was enabled for watching - SUBSTATWA: Mmio(32, packed struct { - /// Subregion 0 in region 0 (write '1' to clear) - SR0: u1, - /// Subregion 1 in region 0 (write '1' to clear) - SR1: u1, - /// Subregion 2 in region 0 (write '1' to clear) - SR2: u1, - /// Subregion 3 in region 0 (write '1' to clear) - SR3: u1, - /// Subregion 4 in region 0 (write '1' to clear) - SR4: u1, - /// Subregion 5 in region 0 (write '1' to clear) - SR5: u1, - /// Subregion 6 in region 0 (write '1' to clear) - SR6: u1, - /// Subregion 7 in region 0 (write '1' to clear) - SR7: u1, - /// Subregion 8 in region 0 (write '1' to clear) - SR8: u1, - /// Subregion 9 in region 0 (write '1' to clear) - SR9: u1, - /// Subregion 10 in region 0 (write '1' to clear) - SR10: u1, - /// Subregion 11 in region 0 (write '1' to clear) - SR11: u1, - /// Subregion 12 in region 0 (write '1' to clear) - SR12: u1, - /// Subregion 13 in region 0 (write '1' to clear) - SR13: u1, - /// Subregion 14 in region 0 (write '1' to clear) - SR14: u1, - /// Subregion 15 in region 0 (write '1' to clear) - SR15: u1, - /// Subregion 16 in region 0 (write '1' to clear) - SR16: u1, - /// Subregion 17 in region 0 (write '1' to clear) - SR17: u1, - /// Subregion 18 in region 0 (write '1' to clear) - SR18: u1, - /// Subregion 19 in region 0 (write '1' to clear) - SR19: u1, - /// Subregion 20 in region 0 (write '1' to clear) - SR20: u1, - /// Subregion 21 in region 0 (write '1' to clear) - SR21: u1, - /// Subregion 22 in region 0 (write '1' to clear) - SR22: u1, - /// Subregion 23 in region 0 (write '1' to clear) - SR23: u1, - /// Subregion 24 in region 0 (write '1' to clear) - SR24: u1, - /// Subregion 25 in region 0 (write '1' to clear) - SR25: u1, - /// Subregion 26 in region 0 (write '1' to clear) - SR26: u1, - /// Subregion 27 in region 0 (write '1' to clear) - SR27: u1, - /// Subregion 28 in region 0 (write '1' to clear) - SR28: u1, - /// Subregion 29 in region 0 (write '1' to clear) - SR29: u1, - /// Subregion 30 in region 0 (write '1' to clear) - SR30: u1, - /// Subregion 31 in region 0 (write '1' to clear) - SR31: u1, - }), - - /// Description cluster[0]: Source of event/interrupt in region 0, read access - /// detected while corresponding subregion was enabled for watching - SUBSTATRA: Mmio(32, packed struct { - /// Subregion 0 in region 0 (write '1' to clear) - SR0: u1, - /// Subregion 1 in region 0 (write '1' to clear) - SR1: u1, - /// Subregion 2 in region 0 (write '1' to clear) - SR2: u1, - /// Subregion 3 in region 0 (write '1' to clear) - SR3: u1, - /// Subregion 4 in region 0 (write '1' to clear) - SR4: u1, - /// Subregion 5 in region 0 (write '1' to clear) - SR5: u1, - /// Subregion 6 in region 0 (write '1' to clear) - SR6: u1, - /// Subregion 7 in region 0 (write '1' to clear) - SR7: u1, - /// Subregion 8 in region 0 (write '1' to clear) - SR8: u1, - /// Subregion 9 in region 0 (write '1' to clear) - SR9: u1, - /// Subregion 10 in region 0 (write '1' to clear) - SR10: u1, - /// Subregion 11 in region 0 (write '1' to clear) - SR11: u1, - /// Subregion 12 in region 0 (write '1' to clear) - SR12: u1, - /// Subregion 13 in region 0 (write '1' to clear) - SR13: u1, - /// Subregion 14 in region 0 (write '1' to clear) - SR14: u1, - /// Subregion 15 in region 0 (write '1' to clear) - SR15: u1, - /// Subregion 16 in region 0 (write '1' to clear) - SR16: u1, - /// Subregion 17 in region 0 (write '1' to clear) - SR17: u1, - /// Subregion 18 in region 0 (write '1' to clear) - SR18: u1, - /// Subregion 19 in region 0 (write '1' to clear) - SR19: u1, - /// Subregion 20 in region 0 (write '1' to clear) - SR20: u1, - /// Subregion 21 in region 0 (write '1' to clear) - SR21: u1, - /// Subregion 22 in region 0 (write '1' to clear) - SR22: u1, - /// Subregion 23 in region 0 (write '1' to clear) - SR23: u1, - /// Subregion 24 in region 0 (write '1' to clear) - SR24: u1, - /// Subregion 25 in region 0 (write '1' to clear) - SR25: u1, - /// Subregion 26 in region 0 (write '1' to clear) - SR26: u1, - /// Subregion 27 in region 0 (write '1' to clear) - SR27: u1, - /// Subregion 28 in region 0 (write '1' to clear) - SR28: u1, - /// Subregion 29 in region 0 (write '1' to clear) - SR29: u1, - /// Subregion 30 in region 0 (write '1' to clear) - SR30: u1, - /// Subregion 31 in region 0 (write '1' to clear) - SR31: u1, - }), - }, base_address + 0x400); - - pub const REGION = @ptrCast(*volatile [4]packed struct { - /// Description cluster[0]: Start address for region 0 - START: u32, - - /// Description cluster[0]: End address of region 0 - END: u32, - padding0: u32, - padding1: u32, - }, base_address + 0x600); - - pub const PREGION = @ptrCast(*volatile [2]packed struct { - /// Description cluster[0]: Reserved for future use - START: u32, - - /// Description cluster[0]: Reserved for future use - END: u32, - - /// Description cluster[0]: Subregions of region 0 - SUBS: Mmio(32, packed struct { - /// Include or exclude subregion 0 in region - SR0: u1, - /// Include or exclude subregion 1 in region - SR1: u1, - /// Include or exclude subregion 2 in region - SR2: u1, - /// Include or exclude subregion 3 in region - SR3: u1, - /// Include or exclude subregion 4 in region - SR4: u1, - /// Include or exclude subregion 5 in region - SR5: u1, - /// Include or exclude subregion 6 in region - SR6: u1, - /// Include or exclude subregion 7 in region - SR7: u1, - /// Include or exclude subregion 8 in region - SR8: u1, - /// Include or exclude subregion 9 in region - SR9: u1, - /// Include or exclude subregion 10 in region - SR10: u1, - /// Include or exclude subregion 11 in region - SR11: u1, - /// Include or exclude subregion 12 in region - SR12: u1, - /// Include or exclude subregion 13 in region - SR13: u1, - /// Include or exclude subregion 14 in region - SR14: u1, - /// Include or exclude subregion 15 in region - SR15: u1, - /// Include or exclude subregion 16 in region - SR16: u1, - /// Include or exclude subregion 17 in region - SR17: u1, - /// Include or exclude subregion 18 in region - SR18: u1, - /// Include or exclude subregion 19 in region - SR19: u1, - /// Include or exclude subregion 20 in region - SR20: u1, - /// Include or exclude subregion 21 in region - SR21: u1, - /// Include or exclude subregion 22 in region - SR22: u1, - /// Include or exclude subregion 23 in region - SR23: u1, - /// Include or exclude subregion 24 in region - SR24: u1, - /// Include or exclude subregion 25 in region - SR25: u1, - /// Include or exclude subregion 26 in region - SR26: u1, - /// Include or exclude subregion 27 in region - SR27: u1, - /// Include or exclude subregion 28 in region - SR28: u1, - /// Include or exclude subregion 29 in region - SR29: u1, - /// Include or exclude subregion 30 in region - SR30: u1, - /// Include or exclude subregion 31 in region - SR31: u1, - }), - padding0: u32, - }, base_address + 0x6c0); - }; - /// Pulse Width Modulation Unit 1 - pub const PWM1 = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021004 - /// Stops PWM pulse generation on all channels at the end of current PWM period, and - /// stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40021008 - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); - - /// address: 0x40021010 - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40021104 - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40021108 - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); - - /// address: 0x40021110 - /// Description collection[0]: Emitted at end of every sequence 0, when last value - /// from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); - - /// address: 0x40021118 - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x4002111c - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40021200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x40021300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x300); - - /// address: 0x40021304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x304); - - /// address: 0x40021308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x308); - - /// address: 0x40021500 - /// PWM module enable register - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x40021504 - /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x504); - - /// address: 0x40021508 - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); - - /// address: 0x4002150c - /// Configuration for PWM_CLK - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); - - /// address: 0x40021510 - /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Selects source for advancing the active sequence - MODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x510); - - /// address: 0x40021514 - /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x514); - }; - /// Pulse Width Modulation Unit 2 - pub const PWM2 = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022004 - /// Stops PWM pulse generation on all channels at the end of current PWM period, and - /// stops sequence playback - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40022008 - /// Description collection[0]: Loads the first PWM value on all enabled channels - /// from sequence 0, and starts playing that sequence at the rate defined in - /// SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not - /// running. - pub const TASKS_SEQSTART = @intToPtr(*volatile [2]u32, base_address + 0x8); - - /// address: 0x40022010 - /// Steps by one value in the current sequence on all enabled channels if - /// DECODER.MODE=NextStep. Does not cause PWM generation to start it was not - /// running. - pub const TASKS_NEXTSTEP = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40022104 - /// Response to STOP task, emitted when PWM pulses are no longer generated - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40022108 - /// Description collection[0]: First PWM period started on sequence 0 - pub const EVENTS_SEQSTARTED = @intToPtr(*volatile [2]u32, base_address + 0x108); - - /// address: 0x40022110 - /// Description collection[0]: Emitted at end of every sequence 0, when last value - /// from RAM has been applied to wave counter - pub const EVENTS_SEQEND = @intToPtr(*volatile [2]u32, base_address + 0x110); - - /// address: 0x40022118 - /// Emitted at the end of each PWM period - pub const EVENTS_PWMPERIODEND = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x4002211c - /// Concatenated sequences have been played the amount of times defined in LOOP.CNT - pub const EVENTS_LOOPSDONE = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x40022200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Shortcut between SEQEND[0] event and STOP task - SEQEND0_STOP: u1, - /// Shortcut between SEQEND[1] event and STOP task - SEQEND1_STOP: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[0] task - LOOPSDONE_SEQSTART0: u1, - /// Shortcut between LOOPSDONE event and SEQSTART[1] task - LOOPSDONE_SEQSTART1: u1, - /// Shortcut between LOOPSDONE event and STOP task - LOOPSDONE_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x200); - - /// address: 0x40022300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - /// Enable or disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Enable or disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Enable or disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Enable or disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Enable or disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Enable or disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x300); - - /// address: 0x40022304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Enable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Enable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Enable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Enable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Enable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x304); - - /// address: 0x40022308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[0] event - SEQSTARTED0: u1, - /// Write '1' to Disable interrupt for SEQSTARTED[1] event - SEQSTARTED1: u1, - /// Write '1' to Disable interrupt for SEQEND[0] event - SEQEND0: u1, - /// Write '1' to Disable interrupt for SEQEND[1] event - SEQEND1: u1, - /// Write '1' to Disable interrupt for PWMPERIODEND event - PWMPERIODEND: u1, - /// Write '1' to Disable interrupt for LOOPSDONE event - LOOPSDONE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x308); - - /// address: 0x40022500 - /// PWM module enable register - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - /// address: 0x40022504 - /// Selects operating mode of the wave counter - pub const MODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Selects up or up and down as wave counter mode - UPDOWN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x504); - - /// address: 0x40022508 - /// Value up to which the pulse generator counter counts - pub const COUNTERTOP = @intToPtr(*volatile MmioInt(32, u15), base_address + 0x508); - - /// address: 0x4002250c - /// Configuration for PWM_CLK - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x50c); - - /// address: 0x40022510 - /// Configuration of the decoder - pub const DECODER = @intToPtr(*volatile Mmio(32, packed struct { - /// How a sequence is read from RAM and spread to the compare register - LOAD: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Selects source for advancing the active sequence - MODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x510); - - /// address: 0x40022514 - /// Amount of playback of a loop - pub const LOOP = @intToPtr(*volatile Mmio(32, packed struct { - /// Amount of playback of pattern cycles - CNT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x514); - }; - /// Serial Peripheral Interface Master with EasyDMA 2 - pub const SPIM2 = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023010 - /// Start SPI transaction - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40023014 - /// Stop SPI transaction - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x14); - - /// address: 0x4002301c - /// Suspend SPI transaction - pub const TASKS_SUSPEND = @intToPtr(*volatile u32, base_address + 0x1c); - - /// address: 0x40023020 - /// Resume SPI transaction - pub const TASKS_RESUME = @intToPtr(*volatile u32, base_address + 0x20); - - /// address: 0x40023104 - /// SPI transaction has stopped - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40023110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40023118 - /// End of RXD buffer and TXD buffer reached - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x40023120 - /// End of TXD buffer reached - pub const EVENTS_ENDTX = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x4002314c - /// Transaction started - pub const EVENTS_STARTED = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x40023200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Shortcut between END event and START task - END_START: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x200); - - /// address: 0x40023304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Enable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Enable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x40023308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved4: u1, - /// Write '1' to Disable interrupt for ENDTX event - ENDTX: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Write '1' to Disable interrupt for STARTED event - STARTED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x40023500 - /// Enable SPIM - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40023524 - /// SPI frequency. Accuracy depends on the HFCLK source selected. - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40023554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x400235c0 - /// Over-read character. Character clocked out in case and over-read of the TXD - /// buffer. - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - }; - /// SPI Slave 2 - pub const SPIS2 = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023024 - /// Acquire SPI semaphore - pub const TASKS_ACQUIRE = @intToPtr(*volatile u32, base_address + 0x24); - - /// address: 0x40023028 - /// Release SPI semaphore, enabling the SPI slave to acquire it - pub const TASKS_RELEASE = @intToPtr(*volatile u32, base_address + 0x28); - - /// address: 0x40023104 - /// Granted transaction completed - pub const EVENTS_END = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40023110 - /// End of RXD buffer reached - pub const EVENTS_ENDRX = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x40023128 - /// Semaphore acquired - pub const EVENTS_ACQUIRED = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x40023200 - /// Shortcut register - pub const SHORTS = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Shortcut between END event and ACQUIRE task - END_ACQUIRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x200); - - /// address: 0x40023304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Enable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x304); - - /// address: 0x40023308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for END event - END: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for ENDRX event - ENDRX: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Write '1' to Disable interrupt for ACQUIRED event - ACQUIRED: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x308); - - /// address: 0x40023400 - /// Semaphore status register - pub const SEMSTAT = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x400); - - /// address: 0x40023440 - /// Status from last transaction - pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { - /// TX buffer over-read detected, and prevented - OVERREAD: u1, - /// RX buffer overflow detected, and prevented - OVERFLOW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x440); - - /// address: 0x40023500 - /// Enable SPI slave - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40023554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - - /// address: 0x4002355c - /// Default character. Character clocked out in case of an ignored transaction. - pub const DEF = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x55c); - - /// address: 0x400235c0 - /// Over-read character - pub const ORC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x5c0); - }; - /// Serial Peripheral Interface 2 - pub const SPI2 = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023108 - /// TXD byte sent and RXD byte received - pub const EVENTS_READY = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40023304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Enable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x304); - - /// address: 0x40023308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Write '1' to Disable interrupt for READY event - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x308); - - /// address: 0x40023500 - /// Enable SPI - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x500); - - /// address: 0x40023518 - /// RXD register - pub const RXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x518); - - /// address: 0x4002351c - /// TXD register - pub const TXD = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x51c); - - /// address: 0x40023524 - /// SPI frequency - pub const FREQUENCY = @intToPtr(*volatile u32, base_address + 0x524); - - /// address: 0x40023554 - /// Configuration register - pub const CONFIG = @intToPtr(*volatile Mmio(32, packed struct { - /// Bit order - ORDER: u1, - /// Serial clock (SCK) phase - CPHA: u1, - /// Serial clock (SCK) polarity - CPOL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x554); - }; - /// Real time counter 2 - pub const RTC2 = struct { - pub const base_address = 0x40024000; - - /// address: 0x40024000 - /// Start RTC COUNTER - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40024004 - /// Stop RTC COUNTER - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40024008 - /// Clear RTC COUNTER - pub const TASKS_CLEAR = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4002400c - /// Set COUNTER to 0xFFFFF0 - pub const TASKS_TRIGOVRFLW = @intToPtr(*volatile u32, base_address + 0xc); - - /// address: 0x40024100 - /// Event on COUNTER increment - pub const EVENTS_TICK = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x40024104 - /// Event on COUNTER overflow - pub const EVENTS_OVRFLW = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40024140 - /// Description collection[0]: Compare event on CC[0] match - pub const EVENTS_COMPARE = @intToPtr(*volatile [4]u32, base_address + 0x140); - - /// address: 0x40024304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable interrupt for TICK event - TICK: u1, - /// Write '1' to Enable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x304); - - /// address: 0x40024308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable interrupt for TICK event - TICK: u1, - /// Write '1' to Disable interrupt for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable interrupt for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable interrupt for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable interrupt for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable interrupt for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x308); - - /// address: 0x40024340 - /// Enable or disable event routing - pub const EVTEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable or disable event routing for TICK event - TICK: u1, - /// Enable or disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Enable or disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Enable or disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Enable or disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Enable or disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x340); - - /// address: 0x40024344 - /// Enable event routing - pub const EVTENSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Enable event routing for TICK event - TICK: u1, - /// Write '1' to Enable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Enable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Enable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Enable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Enable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x344); - - /// address: 0x40024348 - /// Disable event routing - pub const EVTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write '1' to Disable event routing for TICK event - TICK: u1, - /// Write '1' to Disable event routing for OVRFLW event - OVRFLW: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Write '1' to Disable event routing for COMPARE[0] event - COMPARE0: u1, - /// Write '1' to Disable event routing for COMPARE[1] event - COMPARE1: u1, - /// Write '1' to Disable event routing for COMPARE[2] event - COMPARE2: u1, - /// Write '1' to Disable event routing for COMPARE[3] event - COMPARE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x348); - - /// address: 0x40024504 - /// Current COUNTER value - pub const COUNTER = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x504); - - /// address: 0x40024508 - /// 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written - /// when RTC is stopped - pub const PRESCALER = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x508); - - /// address: 0x40024540 - /// Description collection[0]: Compare register 0 - pub const CC = @intToPtr(*volatile [4]Mmio(32, packed struct { - /// Compare value - COMPARE: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x540); - }; - /// Inter-IC Sound - pub const I2S = struct { - pub const base_address = 0x40025000; - - /// address: 0x40025000 - /// Starts continuous I2S transfer. Also starts MCK generator when this is enabled. - pub const TASKS_START = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40025004 - /// Stops I2S transfer. Also stops MCK generator. Triggering this task will cause - /// the {event:STOPPED} event to be generated. - pub const TASKS_STOP = @intToPtr(*volatile u32, base_address + 0x4); - - /// address: 0x40025104 - /// The RXD.PTR register has been copied to internal double-buffers. When the I2S - /// module is started and RX is enabled, this event will be generated for every - /// RXTXD.MAXCNT words that are received on the SDIN pin. - pub const EVENTS_RXPTRUPD = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x40025108 - /// I2S transfer stopped. - pub const EVENTS_STOPPED = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x40025114 - /// The TDX.PTR register has been copied to internal double-buffers. When the I2S - /// module is started and TX is enabled, this event will be generated for every - /// RXTXD.MAXCNT words that are sent on the SDOUT pin. - pub const EVENTS_TXPTRUPD = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x40025300 - /// Enable or disable interrupt - pub const INTEN = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Enable or disable interrupt for RXPTRUPD event - RXPTRUPD: u1, - /// Enable or disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Enable or disable interrupt for TXPTRUPD event - TXPTRUPD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x300); - - /// address: 0x40025304 - /// Enable interrupt - pub const INTENSET = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Enable interrupt for RXPTRUPD event - RXPTRUPD: u1, - /// Write '1' to Enable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Enable interrupt for TXPTRUPD event - TXPTRUPD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x304); - - /// address: 0x40025308 - /// Disable interrupt - pub const INTENCLR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Write '1' to Disable interrupt for RXPTRUPD event - RXPTRUPD: u1, - /// Write '1' to Disable interrupt for STOPPED event - STOPPED: u1, - reserved1: u1, - reserved2: u1, - /// Write '1' to Disable interrupt for TXPTRUPD event - TXPTRUPD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x308); - - /// address: 0x40025500 - /// Enable I2S module. - pub const ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x500); - - pub const CONFIG = struct { - /// address: 0x40025000 - /// I2S mode. - pub const MODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); - - /// address: 0x40025004 - /// Reception (RX) enable. - pub const RXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4); - - /// address: 0x40025008 - /// Transmission (TX) enable. - pub const TXEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); - - /// address: 0x4002500c - /// Master clock generator enable. - pub const MCKEN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc); - - /// address: 0x40025010 - /// Master clock generator frequency. - pub const MCKFREQ = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40025014 - /// MCK / LRCK ratio. - pub const RATIO = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x14); - - /// address: 0x40025018 - /// Sample width. - pub const SWIDTH = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x18); - - /// address: 0x4002501c - /// Alignment of sample within a frame. - pub const ALIGN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c); - - /// address: 0x40025020 - /// Frame format. - pub const FORMAT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20); - - /// address: 0x40025024 - /// Enable channels. - pub const CHANNELS = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x24); - }; - - pub const RXD = struct { - /// address: 0x40025000 - /// Receive buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - }; - - pub const TXD = struct { - /// address: 0x40025000 - /// Transmit buffer RAM start address. - pub const PTR = @intToPtr(*volatile u32, base_address + 0x0); - }; - - pub const RXTXD = struct { - /// address: 0x40025000 - /// Size of RXD and TXD buffers. - pub const MAXCNT = @intToPtr(*volatile MmioInt(32, u14), base_address + 0x0); - }; - - pub const PSEL = struct { - /// address: 0x40025000 - /// Pin select for MCK signal. - pub const MCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x0); - - /// address: 0x40025004 - /// Pin select for SCK signal. - pub const SCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x4); - - /// address: 0x40025008 - /// Pin select for LRCK signal. - pub const LRCK = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x8); - - /// address: 0x4002500c - /// Pin select for SDIN signal. - pub const SDIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0xc); - - /// address: 0x40025010 - /// Pin select for SDOUT signal. - pub const SDOUT = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin number - PIN: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - /// Connection - CONNECT: u1, - }), base_address + 0x10); - }; - }; - /// FPU - pub const FPU = struct { - pub const base_address = 0x40026000; - - /// address: 0x40026000 - /// Unused. - pub const UNUSED = @intToPtr(*volatile u32, base_address + 0x0); - }; - /// GPIO Port 1 - pub const P0 = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000504 - /// Write GPIO port - pub const OUT = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin 0 - PIN0: u1, - /// Pin 1 - PIN1: u1, - /// Pin 2 - PIN2: u1, - /// Pin 3 - PIN3: u1, - /// Pin 4 - PIN4: u1, - /// Pin 5 - PIN5: u1, - /// Pin 6 - PIN6: u1, - /// Pin 7 - PIN7: u1, - /// Pin 8 - PIN8: u1, - /// Pin 9 - PIN9: u1, - /// Pin 10 - PIN10: u1, - /// Pin 11 - PIN11: u1, - /// Pin 12 - PIN12: u1, - /// Pin 13 - PIN13: u1, - /// Pin 14 - PIN14: u1, - /// Pin 15 - PIN15: u1, - /// Pin 16 - PIN16: u1, - /// Pin 17 - PIN17: u1, - /// Pin 18 - PIN18: u1, - /// Pin 19 - PIN19: u1, - /// Pin 20 - PIN20: u1, - /// Pin 21 - PIN21: u1, - /// Pin 22 - PIN22: u1, - /// Pin 23 - PIN23: u1, - /// Pin 24 - PIN24: u1, - /// Pin 25 - PIN25: u1, - /// Pin 26 - PIN26: u1, - /// Pin 27 - PIN27: u1, - /// Pin 28 - PIN28: u1, - /// Pin 29 - PIN29: u1, - /// Pin 30 - PIN30: u1, - /// Pin 31 - PIN31: u1, - }), base_address + 0x504); - - /// address: 0x50000508 - /// Set individual bits in GPIO port - pub const OUTSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin 0 - PIN0: u1, - /// Pin 1 - PIN1: u1, - /// Pin 2 - PIN2: u1, - /// Pin 3 - PIN3: u1, - /// Pin 4 - PIN4: u1, - /// Pin 5 - PIN5: u1, - /// Pin 6 - PIN6: u1, - /// Pin 7 - PIN7: u1, - /// Pin 8 - PIN8: u1, - /// Pin 9 - PIN9: u1, - /// Pin 10 - PIN10: u1, - /// Pin 11 - PIN11: u1, - /// Pin 12 - PIN12: u1, - /// Pin 13 - PIN13: u1, - /// Pin 14 - PIN14: u1, - /// Pin 15 - PIN15: u1, - /// Pin 16 - PIN16: u1, - /// Pin 17 - PIN17: u1, - /// Pin 18 - PIN18: u1, - /// Pin 19 - PIN19: u1, - /// Pin 20 - PIN20: u1, - /// Pin 21 - PIN21: u1, - /// Pin 22 - PIN22: u1, - /// Pin 23 - PIN23: u1, - /// Pin 24 - PIN24: u1, - /// Pin 25 - PIN25: u1, - /// Pin 26 - PIN26: u1, - /// Pin 27 - PIN27: u1, - /// Pin 28 - PIN28: u1, - /// Pin 29 - PIN29: u1, - /// Pin 30 - PIN30: u1, - /// Pin 31 - PIN31: u1, - }), base_address + 0x508); - - /// address: 0x5000050c - /// Clear individual bits in GPIO port - pub const OUTCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin 0 - PIN0: u1, - /// Pin 1 - PIN1: u1, - /// Pin 2 - PIN2: u1, - /// Pin 3 - PIN3: u1, - /// Pin 4 - PIN4: u1, - /// Pin 5 - PIN5: u1, - /// Pin 6 - PIN6: u1, - /// Pin 7 - PIN7: u1, - /// Pin 8 - PIN8: u1, - /// Pin 9 - PIN9: u1, - /// Pin 10 - PIN10: u1, - /// Pin 11 - PIN11: u1, - /// Pin 12 - PIN12: u1, - /// Pin 13 - PIN13: u1, - /// Pin 14 - PIN14: u1, - /// Pin 15 - PIN15: u1, - /// Pin 16 - PIN16: u1, - /// Pin 17 - PIN17: u1, - /// Pin 18 - PIN18: u1, - /// Pin 19 - PIN19: u1, - /// Pin 20 - PIN20: u1, - /// Pin 21 - PIN21: u1, - /// Pin 22 - PIN22: u1, - /// Pin 23 - PIN23: u1, - /// Pin 24 - PIN24: u1, - /// Pin 25 - PIN25: u1, - /// Pin 26 - PIN26: u1, - /// Pin 27 - PIN27: u1, - /// Pin 28 - PIN28: u1, - /// Pin 29 - PIN29: u1, - /// Pin 30 - PIN30: u1, - /// Pin 31 - PIN31: u1, - }), base_address + 0x50c); - - /// address: 0x50000510 - /// Read GPIO port - pub const IN = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin 0 - PIN0: u1, - /// Pin 1 - PIN1: u1, - /// Pin 2 - PIN2: u1, - /// Pin 3 - PIN3: u1, - /// Pin 4 - PIN4: u1, - /// Pin 5 - PIN5: u1, - /// Pin 6 - PIN6: u1, - /// Pin 7 - PIN7: u1, - /// Pin 8 - PIN8: u1, - /// Pin 9 - PIN9: u1, - /// Pin 10 - PIN10: u1, - /// Pin 11 - PIN11: u1, - /// Pin 12 - PIN12: u1, - /// Pin 13 - PIN13: u1, - /// Pin 14 - PIN14: u1, - /// Pin 15 - PIN15: u1, - /// Pin 16 - PIN16: u1, - /// Pin 17 - PIN17: u1, - /// Pin 18 - PIN18: u1, - /// Pin 19 - PIN19: u1, - /// Pin 20 - PIN20: u1, - /// Pin 21 - PIN21: u1, - /// Pin 22 - PIN22: u1, - /// Pin 23 - PIN23: u1, - /// Pin 24 - PIN24: u1, - /// Pin 25 - PIN25: u1, - /// Pin 26 - PIN26: u1, - /// Pin 27 - PIN27: u1, - /// Pin 28 - PIN28: u1, - /// Pin 29 - PIN29: u1, - /// Pin 30 - PIN30: u1, - /// Pin 31 - PIN31: u1, - }), base_address + 0x510); - - /// address: 0x50000514 - /// Direction of GPIO pins - pub const DIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin 0 - PIN0: u1, - /// Pin 1 - PIN1: u1, - /// Pin 2 - PIN2: u1, - /// Pin 3 - PIN3: u1, - /// Pin 4 - PIN4: u1, - /// Pin 5 - PIN5: u1, - /// Pin 6 - PIN6: u1, - /// Pin 7 - PIN7: u1, - /// Pin 8 - PIN8: u1, - /// Pin 9 - PIN9: u1, - /// Pin 10 - PIN10: u1, - /// Pin 11 - PIN11: u1, - /// Pin 12 - PIN12: u1, - /// Pin 13 - PIN13: u1, - /// Pin 14 - PIN14: u1, - /// Pin 15 - PIN15: u1, - /// Pin 16 - PIN16: u1, - /// Pin 17 - PIN17: u1, - /// Pin 18 - PIN18: u1, - /// Pin 19 - PIN19: u1, - /// Pin 20 - PIN20: u1, - /// Pin 21 - PIN21: u1, - /// Pin 22 - PIN22: u1, - /// Pin 23 - PIN23: u1, - /// Pin 24 - PIN24: u1, - /// Pin 25 - PIN25: u1, - /// Pin 26 - PIN26: u1, - /// Pin 27 - PIN27: u1, - /// Pin 28 - PIN28: u1, - /// Pin 29 - PIN29: u1, - /// Pin 30 - PIN30: u1, - /// Pin 31 - PIN31: u1, - }), base_address + 0x514); - - /// address: 0x50000518 - /// DIR set register - pub const DIRSET = @intToPtr(*volatile Mmio(32, packed struct { - /// Set as output pin 0 - PIN0: u1, - /// Set as output pin 1 - PIN1: u1, - /// Set as output pin 2 - PIN2: u1, - /// Set as output pin 3 - PIN3: u1, - /// Set as output pin 4 - PIN4: u1, - /// Set as output pin 5 - PIN5: u1, - /// Set as output pin 6 - PIN6: u1, - /// Set as output pin 7 - PIN7: u1, - /// Set as output pin 8 - PIN8: u1, - /// Set as output pin 9 - PIN9: u1, - /// Set as output pin 10 - PIN10: u1, - /// Set as output pin 11 - PIN11: u1, - /// Set as output pin 12 - PIN12: u1, - /// Set as output pin 13 - PIN13: u1, - /// Set as output pin 14 - PIN14: u1, - /// Set as output pin 15 - PIN15: u1, - /// Set as output pin 16 - PIN16: u1, - /// Set as output pin 17 - PIN17: u1, - /// Set as output pin 18 - PIN18: u1, - /// Set as output pin 19 - PIN19: u1, - /// Set as output pin 20 - PIN20: u1, - /// Set as output pin 21 - PIN21: u1, - /// Set as output pin 22 - PIN22: u1, - /// Set as output pin 23 - PIN23: u1, - /// Set as output pin 24 - PIN24: u1, - /// Set as output pin 25 - PIN25: u1, - /// Set as output pin 26 - PIN26: u1, - /// Set as output pin 27 - PIN27: u1, - /// Set as output pin 28 - PIN28: u1, - /// Set as output pin 29 - PIN29: u1, - /// Set as output pin 30 - PIN30: u1, - /// Set as output pin 31 - PIN31: u1, - }), base_address + 0x518); - - /// address: 0x5000051c - /// DIR clear register - pub const DIRCLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set as input pin 0 - PIN0: u1, - /// Set as input pin 1 - PIN1: u1, - /// Set as input pin 2 - PIN2: u1, - /// Set as input pin 3 - PIN3: u1, - /// Set as input pin 4 - PIN4: u1, - /// Set as input pin 5 - PIN5: u1, - /// Set as input pin 6 - PIN6: u1, - /// Set as input pin 7 - PIN7: u1, - /// Set as input pin 8 - PIN8: u1, - /// Set as input pin 9 - PIN9: u1, - /// Set as input pin 10 - PIN10: u1, - /// Set as input pin 11 - PIN11: u1, - /// Set as input pin 12 - PIN12: u1, - /// Set as input pin 13 - PIN13: u1, - /// Set as input pin 14 - PIN14: u1, - /// Set as input pin 15 - PIN15: u1, - /// Set as input pin 16 - PIN16: u1, - /// Set as input pin 17 - PIN17: u1, - /// Set as input pin 18 - PIN18: u1, - /// Set as input pin 19 - PIN19: u1, - /// Set as input pin 20 - PIN20: u1, - /// Set as input pin 21 - PIN21: u1, - /// Set as input pin 22 - PIN22: u1, - /// Set as input pin 23 - PIN23: u1, - /// Set as input pin 24 - PIN24: u1, - /// Set as input pin 25 - PIN25: u1, - /// Set as input pin 26 - PIN26: u1, - /// Set as input pin 27 - PIN27: u1, - /// Set as input pin 28 - PIN28: u1, - /// Set as input pin 29 - PIN29: u1, - /// Set as input pin 30 - PIN30: u1, - /// Set as input pin 31 - PIN31: u1, - }), base_address + 0x51c); - - /// address: 0x50000520 - /// Latch register indicating what GPIO pins that have met the criteria set in the - /// PIN_CNF[n].SENSE registers - pub const LATCH = @intToPtr(*volatile Mmio(32, packed struct { - /// Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write - /// '1' to clear. - PIN0: u1, - /// Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write - /// '1' to clear. - PIN1: u1, - /// Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write - /// '1' to clear. - PIN2: u1, - /// Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write - /// '1' to clear. - PIN3: u1, - /// Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write - /// '1' to clear. - PIN4: u1, - /// Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write - /// '1' to clear. - PIN5: u1, - /// Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write - /// '1' to clear. - PIN6: u1, - /// Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write - /// '1' to clear. - PIN7: u1, - /// Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write - /// '1' to clear. - PIN8: u1, - /// Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write - /// '1' to clear. - PIN9: u1, - /// Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write - /// '1' to clear. - PIN10: u1, - /// Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write - /// '1' to clear. - PIN11: u1, - /// Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write - /// '1' to clear. - PIN12: u1, - /// Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write - /// '1' to clear. - PIN13: u1, - /// Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write - /// '1' to clear. - PIN14: u1, - /// Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write - /// '1' to clear. - PIN15: u1, - /// Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write - /// '1' to clear. - PIN16: u1, - /// Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write - /// '1' to clear. - PIN17: u1, - /// Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write - /// '1' to clear. - PIN18: u1, - /// Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write - /// '1' to clear. - PIN19: u1, - /// Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write - /// '1' to clear. - PIN20: u1, - /// Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write - /// '1' to clear. - PIN21: u1, - /// Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write - /// '1' to clear. - PIN22: u1, - /// Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write - /// '1' to clear. - PIN23: u1, - /// Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write - /// '1' to clear. - PIN24: u1, - /// Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write - /// '1' to clear. - PIN25: u1, - /// Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write - /// '1' to clear. - PIN26: u1, - /// Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write - /// '1' to clear. - PIN27: u1, - /// Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write - /// '1' to clear. - PIN28: u1, - /// Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write - /// '1' to clear. - PIN29: u1, - /// Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write - /// '1' to clear. - PIN30: u1, - /// Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write - /// '1' to clear. - PIN31: u1, - }), base_address + 0x520); - - /// address: 0x50000524 - /// Select between default DETECT signal behaviour and LDETECT mode - pub const DETECTMODE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x524); - - /// address: 0x50000700 - /// Description collection[0]: Configuration of GPIO pins - pub const PIN_CNF = @intToPtr(*volatile [32]Mmio(32, packed struct { - /// Pin direction. Same physical register as DIR register - DIR: u1, - /// Connect or disconnect input buffer - INPUT: u1, - /// Pull configuration - PULL: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Drive configuration - DRIVE: u3, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Pin sensing mechanism - SENSE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x700); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/stm32f103/registers.zig b/src/modules/chips/stm32f103/registers.zig deleted file mode 100644 index dd33829..0000000 --- a/src/modules/chips/stm32f103/registers.zig +++ /dev/null @@ -1,23820 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 341b0177d90a56f4307cc3226d552b39b048e7fa -// -// device: STM32F103xx -// cpu: CM3 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - /// Window Watchdog interrupt - WWDG: InterruptVector = unhandled, - /// PVD through EXTI line detection - /// interrupt - PVD: InterruptVector = unhandled, - /// Tamper interrupt - TAMPER: InterruptVector = unhandled, - /// RTC global interrupt - RTC: InterruptVector = unhandled, - /// Flash global interrupt - FLASH: InterruptVector = unhandled, - /// RCC global interrupt - RCC: InterruptVector = unhandled, - /// EXTI Line0 interrupt - EXTI0: InterruptVector = unhandled, - /// EXTI Line1 interrupt - EXTI1: InterruptVector = unhandled, - /// EXTI Line2 interrupt - EXTI2: InterruptVector = unhandled, - /// EXTI Line3 interrupt - EXTI3: InterruptVector = unhandled, - /// EXTI Line4 interrupt - EXTI4: InterruptVector = unhandled, - /// DMA1 Channel1 global interrupt - DMA1_Channel1: InterruptVector = unhandled, - /// DMA1 Channel2 global interrupt - DMA1_Channel2: InterruptVector = unhandled, - /// DMA1 Channel3 global interrupt - DMA1_Channel3: InterruptVector = unhandled, - /// DMA1 Channel4 global interrupt - DMA1_Channel4: InterruptVector = unhandled, - /// DMA1 Channel5 global interrupt - DMA1_Channel5: InterruptVector = unhandled, - /// DMA1 Channel6 global interrupt - DMA1_Channel6: InterruptVector = unhandled, - /// DMA1 Channel7 global interrupt - DMA1_Channel7: InterruptVector = unhandled, - /// ADC1 global interrupt - ADC: InterruptVector = unhandled, - /// CAN1 TX interrupts - CAN1_TX: InterruptVector = unhandled, - /// CAN1 RX0 interrupts - CAN1_RX0: InterruptVector = unhandled, - /// CAN1 RX1 interrupt - CAN1_RX1: InterruptVector = unhandled, - /// CAN1 SCE interrupt - CAN1_SCE: InterruptVector = unhandled, - /// EXTI Line[9:5] interrupts - EXTI9_5: InterruptVector = unhandled, - /// TIM1 Break interrupt and TIM9 global - /// interrupt - TIM1_BRK_TIM9: InterruptVector = unhandled, - /// TIM1 Update interrupt and TIM10 global - /// interrupt - TIM1_UP_TIM10: InterruptVector = unhandled, - /// TIM1 Trigger and Commutation interrupts and - /// TIM11 global interrupt - TIM1_TRG_COM_TIM11: InterruptVector = unhandled, - /// TIM1 Capture Compare interrupt - TIM1_CC: InterruptVector = unhandled, - /// TIM2 global interrupt - TIM2: InterruptVector = unhandled, - /// TIM3 global interrupt - TIM3: InterruptVector = unhandled, - /// TIM4 global interrupt - TIM4: InterruptVector = unhandled, - /// I2C1 event interrupt - I2C1_EV: InterruptVector = unhandled, - /// I2C1 error interrupt - I2C1_ER: InterruptVector = unhandled, - /// I2C2 event interrupt - I2C2_EV: InterruptVector = unhandled, - /// I2C2 error interrupt - I2C2_ER: InterruptVector = unhandled, - /// SPI1 global interrupt - SPI1: InterruptVector = unhandled, - /// SPI2 global interrupt - SPI2: InterruptVector = unhandled, - /// USART1 global interrupt - USART1: InterruptVector = unhandled, - /// USART2 global interrupt - USART2: InterruptVector = unhandled, - /// USART3 global interrupt - USART3: InterruptVector = unhandled, - /// EXTI Line[15:10] interrupts - EXTI15_10: InterruptVector = unhandled, - /// RTC Alarms through EXTI line - /// interrupt - RTCAlarm: InterruptVector = unhandled, - /// USB Device FS Wakeup through EXTI line - /// interrupt - USB_FS_WKUP: InterruptVector = unhandled, - /// TIM8 Break interrupt and TIM12 global - /// interrupt - TIM8_BRK_TIM12: InterruptVector = unhandled, - /// TIM8 Update interrupt and TIM13 global - /// interrupt - TIM8_UP_TIM13: InterruptVector = unhandled, - /// TIM8 Trigger and Commutation interrupts and - /// TIM14 global interrupt - TIM8_TRG_COM_TIM14: InterruptVector = unhandled, - /// TIM8 Capture Compare interrupt - TIM8_CC: InterruptVector = unhandled, - /// ADC3 global interrupt - ADC3: InterruptVector = unhandled, - /// FSMC global interrupt - FSMC: InterruptVector = unhandled, - /// SDIO global interrupt - SDIO: InterruptVector = unhandled, - /// TIM5 global interrupt - TIM5: InterruptVector = unhandled, - /// SPI3 global interrupt - SPI3: InterruptVector = unhandled, - /// UART4 global interrupt - UART4: InterruptVector = unhandled, - /// UART5 global interrupt - UART5: InterruptVector = unhandled, - /// TIM6 global interrupt - TIM6: InterruptVector = unhandled, - /// TIM7 global interrupt - TIM7: InterruptVector = unhandled, - /// DMA2 Channel1 global interrupt - DMA2_Channel1: InterruptVector = unhandled, - /// DMA2 Channel2 global interrupt - DMA2_Channel2: InterruptVector = unhandled, - /// DMA2 Channel3 global interrupt - DMA2_Channel3: InterruptVector = unhandled, - /// DMA2 Channel4 and DMA2 Channel5 global - /// interrupt - DMA2_Channel4_5: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// System Control Space - pub const SCS = struct { - pub const base_address = 0xe000e000; - - /// System Tick Timer - pub const SysTick = struct { - /// address: 0xe000e010 - /// SysTick Control and Status Register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0xe000e014 - /// SysTick Reload Value Register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x14); - - /// address: 0xe000e018 - /// SysTick Current Value Register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000e01c - /// SysTick Calibration Register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - SKEW: u1, - NOREF: u1, - }), base_address + 0x1c); - }; - }; - - /// Flexible static memory controller - pub const FSMC = struct { - pub const base_address = 0xa0000000; - - /// address: 0xa0000000 - /// SRAM/NOR-Flash chip-select control register - /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - reserved1: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0xa0000004 - /// SRAM/NOR-Flash chip-select timing register - /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0xa0000008 - /// SRAM/NOR-Flash chip-select control register - /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x8); - - /// address: 0xa000000c - /// SRAM/NOR-Flash chip-select timing register - /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0xa0000010 - /// SRAM/NOR-Flash chip-select control register - /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0xa0000014 - /// SRAM/NOR-Flash chip-select timing register - /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0xa0000018 - /// SRAM/NOR-Flash chip-select control register - /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x18); - - /// address: 0xa000001c - /// SRAM/NOR-Flash chip-select timing register - /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0xa0000060 - /// PC Card/NAND Flash control register - /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x60); - - /// address: 0xa0000064 - /// FIFO status and interrupt register - /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x64); - - /// address: 0xa0000068 - /// Common memory space timing register - /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x68); - - /// address: 0xa000006c - /// Attribute memory space timing register - /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Attribute memory x setup - /// time - ATTSETx: u8, - /// Attribute memory x wait - /// time - ATTWAITx: u8, - /// Attribute memory x hold - /// time - ATTHOLDx: u8, - /// Attribute memory x databus HiZ - /// time - ATTHIZx: u8, - }), base_address + 0x6c); - - /// address: 0xa0000074 - /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECC result - ECCx: u32, - }), base_address + 0x74); - - /// address: 0xa0000080 - /// PC Card/NAND Flash control register - /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x80); - - /// address: 0xa0000084 - /// FIFO status and interrupt register - /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x84); - - /// address: 0xa0000088 - /// Common memory space timing register - /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x88); - - /// address: 0xa000008c - /// Attribute memory space timing register - /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x8c); - - /// address: 0xa0000094 - /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x94); - - /// address: 0xa00000a0 - /// PC Card/NAND Flash control register - /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0xa0); - - /// address: 0xa00000a4 - /// FIFO status and interrupt register - /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xa4); - - /// address: 0xa00000a8 - /// Common memory space timing register - /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0xa8); - - /// address: 0xa00000ac - /// Attribute memory space timing register - /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0xac); - - /// address: 0xa00000b0 - /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), base_address + 0xb0); - - /// address: 0xa0000104 - /// SRAM/NOR-Flash write timing registers - /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x104); - - /// address: 0xa000010c - /// SRAM/NOR-Flash write timing registers - /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10c); - - /// address: 0xa0000114 - /// SRAM/NOR-Flash write timing registers - /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x114); - - /// address: 0xa000011c - /// SRAM/NOR-Flash write timing registers - /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x11c); - }; - - /// Power control - pub const PWR = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// Power control register - /// (PWR_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Power Deep Sleep - LPDS: u1, - /// Power Down Deep Sleep - PDDS: u1, - /// Clear Wake-up Flag - CWUF: u1, - /// Clear STANDBY Flag - CSBF: u1, - /// Power Voltage Detector - /// Enable - PVDE: u1, - /// PVD Level Selection - PLS: u3, - /// Disable Backup Domain write - /// protection - DBP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40007004 - /// Power control register - /// (PWR_CR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wake-Up Flag - WUF: u1, - /// STANDBY Flag - SBF: u1, - /// PVD Output - PVDO: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Enable WKUP pin - EWUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x4); - }; - - /// Reset and clock control - pub const RCC = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021000 - /// Clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal High Speed clock - /// enable - HSION: u1, - /// Internal High Speed clock ready - /// flag - HSIRDY: u1, - reserved0: u1, - /// Internal High Speed clock - /// trimming - HSITRIM: u5, - /// Internal High Speed clock - /// Calibration - HSICAL: u8, - /// External High Speed clock - /// enable - HSEON: u1, - /// External High Speed clock ready - /// flag - HSERDY: u1, - /// External High Speed clock - /// Bypass - HSEBYP: u1, - /// Clock Security System - /// enable - CSSON: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40021004 - /// Clock configuration register - /// (RCC_CFGR) - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// System clock Switch - SW: u2, - /// System Clock Switch Status - SWS: u2, - /// AHB prescaler - HPRE: u4, - /// APB Low speed prescaler - /// (APB1) - PPRE1: u3, - /// APB High speed prescaler - /// (APB2) - PPRE2: u3, - /// ADC prescaler - ADCPRE: u2, - /// PLL entry clock source - PLLSRC: u1, - /// HSE divider for PLL entry - PLLXTPRE: u1, - /// PLL Multiplication Factor - PLLMUL: u4, - /// USB OTG FS prescaler - OTGFSPRE: u1, - reserved0: u1, - /// Microcontroller clock - /// output - MCO: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40021008 - /// Clock interrupt register - /// (RCC_CIR) - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved0: u1, - reserved1: u1, - /// Clock Security System Interrupt - /// flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved5: u1, - reserved6: u1, - /// Clock security system interrupt - /// clear - CSSC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4002100c - /// APB2 peripheral reset register - /// (RCC_APB2RSTR) - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function I/O - /// reset - AFIORST: u1, - reserved0: u1, - /// IO port A reset - IOPARST: u1, - /// IO port B reset - IOPBRST: u1, - /// IO port C reset - IOPCRST: u1, - /// IO port D reset - IOPDRST: u1, - /// IO port E reset - IOPERST: u1, - /// IO port F reset - IOPFRST: u1, - /// IO port G reset - IOPGRST: u1, - /// ADC 1 interface reset - ADC1RST: u1, - /// ADC 2 interface reset - ADC2RST: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - /// ADC 3 interface reset - ADC3RST: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TIM9 timer reset - TIM9RST: u1, - /// TIM10 timer reset - TIM10RST: u1, - /// TIM11 timer reset - TIM11RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0xc); - - /// address: 0x40021010 - /// APB1 peripheral reset register - /// (RCC_APB1RSTR) - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 4 reset - TIM4RST: u1, - /// Timer 5 reset - TIM5RST: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - /// Timer 12 reset - TIM12RST: u1, - /// Timer 13 reset - TIM13RST: u1, - /// Timer 14 reset - TIM14RST: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved2: u1, - reserved3: u1, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved4: u1, - /// USART 2 reset - USART2RST: u1, - /// USART 3 reset - USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved5: u1, - /// CAN reset - CANRST: u1, - reserved6: u1, - /// Backup interface reset - BKPRST: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40021014 - /// AHB Peripheral Clock enable register - /// (RCC_AHBENR) - pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock - /// enable - SRAMEN: u1, - reserved0: u1, - /// FLITF clock enable - FLITFEN: u1, - reserved1: u1, - /// CRC clock enable - CRCEN: u1, - reserved2: u1, - /// FSMC clock enable - FSMCEN: u1, - reserved3: u1, - /// SDIO clock enable - SDIOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40021018 - /// APB2 peripheral clock enable register - /// (RCC_APB2ENR) - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function I/O clock - /// enable - AFIOEN: u1, - reserved0: u1, - /// I/O port A clock enable - IOPAEN: u1, - /// I/O port B clock enable - IOPBEN: u1, - /// I/O port C clock enable - IOPCEN: u1, - /// I/O port D clock enable - IOPDEN: u1, - /// I/O port E clock enable - IOPEEN: u1, - /// I/O port F clock enable - IOPFEN: u1, - /// I/O port G clock enable - IOPGEN: u1, - /// ADC 1 interface clock - /// enable - ADC1EN: u1, - /// ADC 2 interface clock - /// enable - ADC2EN: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - /// TIM8 Timer clock enable - TIM8EN: u1, - /// USART1 clock enable - USART1EN: u1, - /// ADC3 interface clock - /// enable - ADC3EN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TIM9 Timer clock enable - TIM9EN: u1, - /// TIM10 Timer clock enable - TIM10EN: u1, - /// TIM11 Timer clock enable - TIM11EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x18); - - /// address: 0x4002101c - /// APB1 peripheral clock enable register - /// (RCC_APB1ENR) - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - /// Timer 5 clock enable - TIM5EN: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - /// Timer 12 clock enable - TIM12EN: u1, - /// Timer 13 clock enable - TIM13EN: u1, - /// Timer 14 clock enable - TIM14EN: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog clock - /// enable - WWDGEN: u1, - reserved2: u1, - reserved3: u1, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved4: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// UART 4 clock enable - UART4EN: u1, - /// UART 5 clock enable - UART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved5: u1, - /// CAN clock enable - CANEN: u1, - reserved6: u1, - /// Backup interface clock - /// enable - BKPEN: u1, - /// Power interface clock - /// enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0x40021020 - /// Backup domain control register - /// (RCC_BDCR) - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Low Speed oscillator - /// enable - LSEON: u1, - /// External Low Speed oscillator - /// ready - LSERDY: u1, - /// External Low Speed oscillator - /// bypass - LSEBYP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RTC clock source selection - RTCSEL: u2, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software - /// reset - BDRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x20); - - /// address: 0x40021024 - /// Control/status register - /// (RCC_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal low speed oscillator - /// enable - LSION: u1, - /// Internal low speed oscillator - /// ready - LSIRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Remove reset flag - RMVF: u1, - reserved22: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset - /// flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), base_address + 0x24); - }; - - /// General purpose I/O - pub const GPIOA = struct { - pub const base_address = 0x40010800; - - /// address: 0x40010800 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40010804 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40010808 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001080c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010810 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40010814 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40010818 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOB = struct { - pub const base_address = 0x40010c00; - - /// address: 0x40010c00 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40010c04 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40010c08 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40010c0c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010c10 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40010c14 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40010c18 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOC = struct { - pub const base_address = 0x40011000; - - /// address: 0x40011000 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40011004 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40011008 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001100c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011010 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40011014 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011018 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOD = struct { - pub const base_address = 0x40011400; - - /// address: 0x40011400 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40011404 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40011408 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001140c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011410 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40011414 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011418 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOE = struct { - pub const base_address = 0x40011800; - - /// address: 0x40011800 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40011804 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40011808 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001180c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011810 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40011814 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011818 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOF = struct { - pub const base_address = 0x40011c00; - - /// address: 0x40011c00 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40011c04 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40011c08 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40011c0c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011c10 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40011c14 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40011c18 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - pub const GPIOG = struct { - pub const base_address = 0x40012000; - - /// address: 0x40012000 - /// Port configuration register low - /// (GPIOn_CRL) - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.0 mode bits - MODE0: u2, - /// Port n.0 configuration - /// bits - CNF0: u2, - /// Port n.1 mode bits - MODE1: u2, - /// Port n.1 configuration - /// bits - CNF1: u2, - /// Port n.2 mode bits - MODE2: u2, - /// Port n.2 configuration - /// bits - CNF2: u2, - /// Port n.3 mode bits - MODE3: u2, - /// Port n.3 configuration - /// bits - CNF3: u2, - /// Port n.4 mode bits - MODE4: u2, - /// Port n.4 configuration - /// bits - CNF4: u2, - /// Port n.5 mode bits - MODE5: u2, - /// Port n.5 configuration - /// bits - CNF5: u2, - /// Port n.6 mode bits - MODE6: u2, - /// Port n.6 configuration - /// bits - CNF6: u2, - /// Port n.7 mode bits - MODE7: u2, - /// Port n.7 configuration - /// bits - CNF7: u2, - }), base_address + 0x0); - - /// address: 0x40012004 - /// Port configuration register high - /// (GPIOn_CRL) - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Port n.8 mode bits - MODE8: u2, - /// Port n.8 configuration - /// bits - CNF8: u2, - /// Port n.9 mode bits - MODE9: u2, - /// Port n.9 configuration - /// bits - CNF9: u2, - /// Port n.10 mode bits - MODE10: u2, - /// Port n.10 configuration - /// bits - CNF10: u2, - /// Port n.11 mode bits - MODE11: u2, - /// Port n.11 configuration - /// bits - CNF11: u2, - /// Port n.12 mode bits - MODE12: u2, - /// Port n.12 configuration - /// bits - CNF12: u2, - /// Port n.13 mode bits - MODE13: u2, - /// Port n.13 configuration - /// bits - CNF13: u2, - /// Port n.14 mode bits - MODE14: u2, - /// Port n.14 configuration - /// bits - CNF14: u2, - /// Port n.15 mode bits - MODE15: u2, - /// Port n.15 configuration - /// bits - CNF15: u2, - }), base_address + 0x4); - - /// address: 0x40012008 - /// Port input data register - /// (GPIOn_IDR) - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data - IDR0: u1, - /// Port input data - IDR1: u1, - /// Port input data - IDR2: u1, - /// Port input data - IDR3: u1, - /// Port input data - IDR4: u1, - /// Port input data - IDR5: u1, - /// Port input data - IDR6: u1, - /// Port input data - IDR7: u1, - /// Port input data - IDR8: u1, - /// Port input data - IDR9: u1, - /// Port input data - IDR10: u1, - /// Port input data - IDR11: u1, - /// Port input data - IDR12: u1, - /// Port input data - IDR13: u1, - /// Port input data - IDR14: u1, - /// Port input data - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001200c - /// Port output data register - /// (GPIOn_ODR) - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data - ODR0: u1, - /// Port output data - ODR1: u1, - /// Port output data - ODR2: u1, - /// Port output data - ODR3: u1, - /// Port output data - ODR4: u1, - /// Port output data - ODR5: u1, - /// Port output data - ODR6: u1, - /// Port output data - ODR7: u1, - /// Port output data - ODR8: u1, - /// Port output data - ODR9: u1, - /// Port output data - ODR10: u1, - /// Port output data - ODR11: u1, - /// Port output data - ODR12: u1, - /// Port output data - ODR13: u1, - /// Port output data - ODR14: u1, - /// Port output data - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40012010 - /// Port bit set/reset register - /// (GPIOn_BSRR) - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Set bit 0 - BS0: u1, - /// Set bit 1 - BS1: u1, - /// Set bit 1 - BS2: u1, - /// Set bit 3 - BS3: u1, - /// Set bit 4 - BS4: u1, - /// Set bit 5 - BS5: u1, - /// Set bit 6 - BS6: u1, - /// Set bit 7 - BS7: u1, - /// Set bit 8 - BS8: u1, - /// Set bit 9 - BS9: u1, - /// Set bit 10 - BS10: u1, - /// Set bit 11 - BS11: u1, - /// Set bit 12 - BS12: u1, - /// Set bit 13 - BS13: u1, - /// Set bit 14 - BS14: u1, - /// Set bit 15 - BS15: u1, - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 2 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - }), base_address + 0x10); - - /// address: 0x40012014 - /// Port bit reset register - /// (GPIOn_BRR) - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit 0 - BR0: u1, - /// Reset bit 1 - BR1: u1, - /// Reset bit 1 - BR2: u1, - /// Reset bit 3 - BR3: u1, - /// Reset bit 4 - BR4: u1, - /// Reset bit 5 - BR5: u1, - /// Reset bit 6 - BR6: u1, - /// Reset bit 7 - BR7: u1, - /// Reset bit 8 - BR8: u1, - /// Reset bit 9 - BR9: u1, - /// Reset bit 10 - BR10: u1, - /// Reset bit 11 - BR11: u1, - /// Reset bit 12 - BR12: u1, - /// Reset bit 13 - BR13: u1, - /// Reset bit 14 - BR14: u1, - /// Reset bit 15 - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40012018 - /// Port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port A Lock bit 0 - LCK0: u1, - /// Port A Lock bit 1 - LCK1: u1, - /// Port A Lock bit 2 - LCK2: u1, - /// Port A Lock bit 3 - LCK3: u1, - /// Port A Lock bit 4 - LCK4: u1, - /// Port A Lock bit 5 - LCK5: u1, - /// Port A Lock bit 6 - LCK6: u1, - /// Port A Lock bit 7 - LCK7: u1, - /// Port A Lock bit 8 - LCK8: u1, - /// Port A Lock bit 9 - LCK9: u1, - /// Port A Lock bit 10 - LCK10: u1, - /// Port A Lock bit 11 - LCK11: u1, - /// Port A Lock bit 12 - LCK12: u1, - /// Port A Lock bit 13 - LCK13: u1, - /// Port A Lock bit 14 - LCK14: u1, - /// Port A Lock bit 15 - LCK15: u1, - /// Lock key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - }; - - /// Alternate function I/O - pub const AFIO = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// Event Control Register - /// (AFIO_EVCR) - pub const EVCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pin selection - PIN: u4, - /// Port selection - PORT: u3, - /// Event Output Enable - EVOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40010004 - /// AF remap and debug I/O configuration - /// register (AFIO_MAPR) - pub const MAPR = @intToPtr(*volatile Mmio(32, packed struct { - /// SPI1 remapping - SPI1_REMAP: u1, - /// I2C1 remapping - I2C1_REMAP: u1, - /// USART1 remapping - USART1_REMAP: u1, - /// USART2 remapping - USART2_REMAP: u1, - /// USART3 remapping - USART3_REMAP: u2, - /// TIM1 remapping - TIM1_REMAP: u2, - /// TIM2 remapping - TIM2_REMAP: u2, - /// TIM3 remapping - TIM3_REMAP: u2, - /// TIM4 remapping - TIM4_REMAP: u1, - /// CAN1 remapping - CAN_REMAP: u2, - /// Port D0/Port D1 mapping on - /// OSCIN/OSCOUT - PD01_REMAP: u1, - /// Set and cleared by - /// software - TIM5CH4_IREMAP: u1, - /// ADC 1 External trigger injected - /// conversion remapping - ADC1_ETRGINJ_REMAP: u1, - /// ADC 1 external trigger regular - /// conversion remapping - ADC1_ETRGREG_REMAP: u1, - /// ADC 2 external trigger injected - /// conversion remapping - ADC2_ETRGINJ_REMAP: u1, - /// ADC 2 external trigger regular - /// conversion remapping - ADC2_ETRGREG_REMAP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Serial wire JTAG - /// configuration - SWJ_CFG: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40010008 - /// External interrupt configuration register 1 - /// (AFIO_EXTICR1) - pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI0 configuration - EXTI0: u4, - /// EXTI1 configuration - EXTI1: u4, - /// EXTI2 configuration - EXTI2: u4, - /// EXTI3 configuration - EXTI3: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001000c - /// External interrupt configuration register 2 - /// (AFIO_EXTICR2) - pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI4 configuration - EXTI4: u4, - /// EXTI5 configuration - EXTI5: u4, - /// EXTI6 configuration - EXTI6: u4, - /// EXTI7 configuration - EXTI7: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// External interrupt configuration register 3 - /// (AFIO_EXTICR3) - pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI8 configuration - EXTI8: u4, - /// EXTI9 configuration - EXTI9: u4, - /// EXTI10 configuration - EXTI10: u4, - /// EXTI11 configuration - EXTI11: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40010014 - /// External interrupt configuration register 4 - /// (AFIO_EXTICR4) - pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI12 configuration - EXTI12: u4, - /// EXTI13 configuration - EXTI13: u4, - /// EXTI14 configuration - EXTI14: u4, - /// EXTI15 configuration - EXTI15: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x4001001c - /// AF remap and debug I/O configuration - /// register - pub const MAPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// TIM9 remapping - TIM9_REMAP: u1, - /// TIM10 remapping - TIM10_REMAP: u1, - /// TIM11 remapping - TIM11_REMAP: u1, - /// TIM13 remapping - TIM13_REMAP: u1, - /// TIM14 remapping - TIM14_REMAP: u1, - /// NADV connect/disconnect - FSMC_NADV: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c); - }; - - /// EXTI - pub const EXTI = struct { - pub const base_address = 0x40010400; - - /// address: 0x40010400 - /// Interrupt mask register - /// (EXTI_IMR) - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1, - /// Interrupt Mask on line 1 - MR1: u1, - /// Interrupt Mask on line 2 - MR2: u1, - /// Interrupt Mask on line 3 - MR3: u1, - /// Interrupt Mask on line 4 - MR4: u1, - /// Interrupt Mask on line 5 - MR5: u1, - /// Interrupt Mask on line 6 - MR6: u1, - /// Interrupt Mask on line 7 - MR7: u1, - /// Interrupt Mask on line 8 - MR8: u1, - /// Interrupt Mask on line 9 - MR9: u1, - /// Interrupt Mask on line 10 - MR10: u1, - /// Interrupt Mask on line 11 - MR11: u1, - /// Interrupt Mask on line 12 - MR12: u1, - /// Interrupt Mask on line 13 - MR13: u1, - /// Interrupt Mask on line 14 - MR14: u1, - /// Interrupt Mask on line 15 - MR15: u1, - /// Interrupt Mask on line 16 - MR16: u1, - /// Interrupt Mask on line 17 - MR17: u1, - /// Interrupt Mask on line 18 - MR18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x40010404 - /// Event mask register (EXTI_EMR) - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Event Mask on line 0 - MR0: u1, - /// Event Mask on line 1 - MR1: u1, - /// Event Mask on line 2 - MR2: u1, - /// Event Mask on line 3 - MR3: u1, - /// Event Mask on line 4 - MR4: u1, - /// Event Mask on line 5 - MR5: u1, - /// Event Mask on line 6 - MR6: u1, - /// Event Mask on line 7 - MR7: u1, - /// Event Mask on line 8 - MR8: u1, - /// Event Mask on line 9 - MR9: u1, - /// Event Mask on line 10 - MR10: u1, - /// Event Mask on line 11 - MR11: u1, - /// Event Mask on line 12 - MR12: u1, - /// Event Mask on line 13 - MR13: u1, - /// Event Mask on line 14 - MR14: u1, - /// Event Mask on line 15 - MR15: u1, - /// Event Mask on line 16 - MR16: u1, - /// Event Mask on line 17 - MR17: u1, - /// Event Mask on line 18 - MR18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x4); - - /// address: 0x40010408 - /// Rising Trigger selection register - /// (EXTI_RTSR) - pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising trigger event configuration of - /// line 0 - TR0: u1, - /// Rising trigger event configuration of - /// line 1 - TR1: u1, - /// Rising trigger event configuration of - /// line 2 - TR2: u1, - /// Rising trigger event configuration of - /// line 3 - TR3: u1, - /// Rising trigger event configuration of - /// line 4 - TR4: u1, - /// Rising trigger event configuration of - /// line 5 - TR5: u1, - /// Rising trigger event configuration of - /// line 6 - TR6: u1, - /// Rising trigger event configuration of - /// line 7 - TR7: u1, - /// Rising trigger event configuration of - /// line 8 - TR8: u1, - /// Rising trigger event configuration of - /// line 9 - TR9: u1, - /// Rising trigger event configuration of - /// line 10 - TR10: u1, - /// Rising trigger event configuration of - /// line 11 - TR11: u1, - /// Rising trigger event configuration of - /// line 12 - TR12: u1, - /// Rising trigger event configuration of - /// line 13 - TR13: u1, - /// Rising trigger event configuration of - /// line 14 - TR14: u1, - /// Rising trigger event configuration of - /// line 15 - TR15: u1, - /// Rising trigger event configuration of - /// line 16 - TR16: u1, - /// Rising trigger event configuration of - /// line 17 - TR17: u1, - /// Rising trigger event configuration of - /// line 18 - TR18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x8); - - /// address: 0x4001040c - /// Falling Trigger selection register - /// (EXTI_FTSR) - pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling trigger event configuration of - /// line 0 - TR0: u1, - /// Falling trigger event configuration of - /// line 1 - TR1: u1, - /// Falling trigger event configuration of - /// line 2 - TR2: u1, - /// Falling trigger event configuration of - /// line 3 - TR3: u1, - /// Falling trigger event configuration of - /// line 4 - TR4: u1, - /// Falling trigger event configuration of - /// line 5 - TR5: u1, - /// Falling trigger event configuration of - /// line 6 - TR6: u1, - /// Falling trigger event configuration of - /// line 7 - TR7: u1, - /// Falling trigger event configuration of - /// line 8 - TR8: u1, - /// Falling trigger event configuration of - /// line 9 - TR9: u1, - /// Falling trigger event configuration of - /// line 10 - TR10: u1, - /// Falling trigger event configuration of - /// line 11 - TR11: u1, - /// Falling trigger event configuration of - /// line 12 - TR12: u1, - /// Falling trigger event configuration of - /// line 13 - TR13: u1, - /// Falling trigger event configuration of - /// line 14 - TR14: u1, - /// Falling trigger event configuration of - /// line 15 - TR15: u1, - /// Falling trigger event configuration of - /// line 16 - TR16: u1, - /// Falling trigger event configuration of - /// line 17 - TR17: u1, - /// Falling trigger event configuration of - /// line 18 - TR18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - - /// address: 0x40010410 - /// Software interrupt event register - /// (EXTI_SWIER) - pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Interrupt on line - /// 0 - SWIER0: u1, - /// Software Interrupt on line - /// 1 - SWIER1: u1, - /// Software Interrupt on line - /// 2 - SWIER2: u1, - /// Software Interrupt on line - /// 3 - SWIER3: u1, - /// Software Interrupt on line - /// 4 - SWIER4: u1, - /// Software Interrupt on line - /// 5 - SWIER5: u1, - /// Software Interrupt on line - /// 6 - SWIER6: u1, - /// Software Interrupt on line - /// 7 - SWIER7: u1, - /// Software Interrupt on line - /// 8 - SWIER8: u1, - /// Software Interrupt on line - /// 9 - SWIER9: u1, - /// Software Interrupt on line - /// 10 - SWIER10: u1, - /// Software Interrupt on line - /// 11 - SWIER11: u1, - /// Software Interrupt on line - /// 12 - SWIER12: u1, - /// Software Interrupt on line - /// 13 - SWIER13: u1, - /// Software Interrupt on line - /// 14 - SWIER14: u1, - /// Software Interrupt on line - /// 15 - SWIER15: u1, - /// Software Interrupt on line - /// 16 - SWIER16: u1, - /// Software Interrupt on line - /// 17 - SWIER17: u1, - /// Software Interrupt on line - /// 18 - SWIER18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x10); - - /// address: 0x40010414 - /// Pending register (EXTI_PR) - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending bit 0 - PR0: u1, - /// Pending bit 1 - PR1: u1, - /// Pending bit 2 - PR2: u1, - /// Pending bit 3 - PR3: u1, - /// Pending bit 4 - PR4: u1, - /// Pending bit 5 - PR5: u1, - /// Pending bit 6 - PR6: u1, - /// Pending bit 7 - PR7: u1, - /// Pending bit 8 - PR8: u1, - /// Pending bit 9 - PR9: u1, - /// Pending bit 10 - PR10: u1, - /// Pending bit 11 - PR11: u1, - /// Pending bit 12 - PR12: u1, - /// Pending bit 13 - PR13: u1, - /// Pending bit 14 - PR14: u1, - /// Pending bit 15 - PR15: u1, - /// Pending bit 16 - PR16: u1, - /// Pending bit 17 - PR17: u1, - /// Pending bit 18 - PR18: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x14); - }; - - /// DMA controller - pub const DMA1 = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// DMA interrupt status register - /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// flag - GIF1: u1, - /// Channel 1 Transfer Complete - /// flag - TCIF1: u1, - /// Channel 1 Half Transfer Complete - /// flag - HTIF1: u1, - /// Channel 1 Transfer Error - /// flag - TEIF1: u1, - /// Channel 2 Global interrupt - /// flag - GIF2: u1, - /// Channel 2 Transfer Complete - /// flag - TCIF2: u1, - /// Channel 2 Half Transfer Complete - /// flag - HTIF2: u1, - /// Channel 2 Transfer Error - /// flag - TEIF2: u1, - /// Channel 3 Global interrupt - /// flag - GIF3: u1, - /// Channel 3 Transfer Complete - /// flag - TCIF3: u1, - /// Channel 3 Half Transfer Complete - /// flag - HTIF3: u1, - /// Channel 3 Transfer Error - /// flag - TEIF3: u1, - /// Channel 4 Global interrupt - /// flag - GIF4: u1, - /// Channel 4 Transfer Complete - /// flag - TCIF4: u1, - /// Channel 4 Half Transfer Complete - /// flag - HTIF4: u1, - /// Channel 4 Transfer Error - /// flag - TEIF4: u1, - /// Channel 5 Global interrupt - /// flag - GIF5: u1, - /// Channel 5 Transfer Complete - /// flag - TCIF5: u1, - /// Channel 5 Half Transfer Complete - /// flag - HTIF5: u1, - /// Channel 5 Transfer Error - /// flag - TEIF5: u1, - /// Channel 6 Global interrupt - /// flag - GIF6: u1, - /// Channel 6 Transfer Complete - /// flag - TCIF6: u1, - /// Channel 6 Half Transfer Complete - /// flag - HTIF6: u1, - /// Channel 6 Transfer Error - /// flag - TEIF6: u1, - /// Channel 7 Global interrupt - /// flag - GIF7: u1, - /// Channel 7 Transfer Complete - /// flag - TCIF7: u1, - /// Channel 7 Half Transfer Complete - /// flag - HTIF7: u1, - /// Channel 7 Transfer Error - /// flag - TEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40020004 - /// DMA interrupt flag clear register - /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// clear - CGIF1: u1, - /// Channel 1 Transfer Complete - /// clear - CTCIF1: u1, - /// Channel 1 Half Transfer - /// clear - CHTIF1: u1, - /// Channel 1 Transfer Error - /// clear - CTEIF1: u1, - /// Channel 2 Global interrupt - /// clear - CGIF2: u1, - /// Channel 2 Transfer Complete - /// clear - CTCIF2: u1, - /// Channel 2 Half Transfer - /// clear - CHTIF2: u1, - /// Channel 2 Transfer Error - /// clear - CTEIF2: u1, - /// Channel 3 Global interrupt - /// clear - CGIF3: u1, - /// Channel 3 Transfer Complete - /// clear - CTCIF3: u1, - /// Channel 3 Half Transfer - /// clear - CHTIF3: u1, - /// Channel 3 Transfer Error - /// clear - CTEIF3: u1, - /// Channel 4 Global interrupt - /// clear - CGIF4: u1, - /// Channel 4 Transfer Complete - /// clear - CTCIF4: u1, - /// Channel 4 Half Transfer - /// clear - CHTIF4: u1, - /// Channel 4 Transfer Error - /// clear - CTEIF4: u1, - /// Channel 5 Global interrupt - /// clear - CGIF5: u1, - /// Channel 5 Transfer Complete - /// clear - CTCIF5: u1, - /// Channel 5 Half Transfer - /// clear - CHTIF5: u1, - /// Channel 5 Transfer Error - /// clear - CTEIF5: u1, - /// Channel 6 Global interrupt - /// clear - CGIF6: u1, - /// Channel 6 Transfer Complete - /// clear - CTCIF6: u1, - /// Channel 6 Half Transfer - /// clear - CHTIF6: u1, - /// Channel 6 Transfer Error - /// clear - CTEIF6: u1, - /// Channel 7 Global interrupt - /// clear - CGIF7: u1, - /// Channel 7 Transfer Complete - /// clear - CTCIF7: u1, - /// Channel 7 Half Transfer - /// clear - CHTIF7: u1, - /// Channel 7 Transfer Error - /// clear - CTEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002000c - /// DMA channel 1 number of data - /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020010 - /// DMA channel 1 peripheral address - /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x10); - - /// address: 0x40020014 - /// DMA channel 1 memory address - /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x14); - - /// address: 0x4002001c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// DMA channel 2 number of data - /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020024 - /// DMA channel 2 peripheral address - /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x24); - - /// address: 0x40020028 - /// DMA channel 2 memory address - /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x28); - - /// address: 0x40020030 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020034 - /// DMA channel 3 number of data - /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020038 - /// DMA channel 3 peripheral address - /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x38); - - /// address: 0x4002003c - /// DMA channel 3 memory address - /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x3c); - - /// address: 0x40020044 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020048 - /// DMA channel 4 number of data - /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002004c - /// DMA channel 4 peripheral address - /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x4c); - - /// address: 0x40020050 - /// DMA channel 4 memory address - /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x50); - - /// address: 0x40020058 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002005c - /// DMA channel 5 number of data - /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020060 - /// DMA channel 5 peripheral address - /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40020064 - /// DMA channel 5 memory address - /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x64); - - /// address: 0x4002006c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x6c); - - /// address: 0x40020070 - /// DMA channel 6 number of data - /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40020074 - /// DMA channel 6 peripheral address - /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x74); - - /// address: 0x40020078 - /// DMA channel 6 memory address - /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x78); - - /// address: 0x40020080 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40020084 - /// DMA channel 7 number of data - /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40020088 - /// DMA channel 7 peripheral address - /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x88); - - /// address: 0x4002008c - /// DMA channel 7 memory address - /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x8c); - }; - pub const DMA2 = struct { - pub const base_address = 0x40020400; - - /// address: 0x40020400 - /// DMA interrupt status register - /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// flag - GIF1: u1, - /// Channel 1 Transfer Complete - /// flag - TCIF1: u1, - /// Channel 1 Half Transfer Complete - /// flag - HTIF1: u1, - /// Channel 1 Transfer Error - /// flag - TEIF1: u1, - /// Channel 2 Global interrupt - /// flag - GIF2: u1, - /// Channel 2 Transfer Complete - /// flag - TCIF2: u1, - /// Channel 2 Half Transfer Complete - /// flag - HTIF2: u1, - /// Channel 2 Transfer Error - /// flag - TEIF2: u1, - /// Channel 3 Global interrupt - /// flag - GIF3: u1, - /// Channel 3 Transfer Complete - /// flag - TCIF3: u1, - /// Channel 3 Half Transfer Complete - /// flag - HTIF3: u1, - /// Channel 3 Transfer Error - /// flag - TEIF3: u1, - /// Channel 4 Global interrupt - /// flag - GIF4: u1, - /// Channel 4 Transfer Complete - /// flag - TCIF4: u1, - /// Channel 4 Half Transfer Complete - /// flag - HTIF4: u1, - /// Channel 4 Transfer Error - /// flag - TEIF4: u1, - /// Channel 5 Global interrupt - /// flag - GIF5: u1, - /// Channel 5 Transfer Complete - /// flag - TCIF5: u1, - /// Channel 5 Half Transfer Complete - /// flag - HTIF5: u1, - /// Channel 5 Transfer Error - /// flag - TEIF5: u1, - /// Channel 6 Global interrupt - /// flag - GIF6: u1, - /// Channel 6 Transfer Complete - /// flag - TCIF6: u1, - /// Channel 6 Half Transfer Complete - /// flag - HTIF6: u1, - /// Channel 6 Transfer Error - /// flag - TEIF6: u1, - /// Channel 7 Global interrupt - /// flag - GIF7: u1, - /// Channel 7 Transfer Complete - /// flag - TCIF7: u1, - /// Channel 7 Half Transfer Complete - /// flag - HTIF7: u1, - /// Channel 7 Transfer Error - /// flag - TEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40020404 - /// DMA interrupt flag clear register - /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// clear - CGIF1: u1, - /// Channel 1 Transfer Complete - /// clear - CTCIF1: u1, - /// Channel 1 Half Transfer - /// clear - CHTIF1: u1, - /// Channel 1 Transfer Error - /// clear - CTEIF1: u1, - /// Channel 2 Global interrupt - /// clear - CGIF2: u1, - /// Channel 2 Transfer Complete - /// clear - CTCIF2: u1, - /// Channel 2 Half Transfer - /// clear - CHTIF2: u1, - /// Channel 2 Transfer Error - /// clear - CTEIF2: u1, - /// Channel 3 Global interrupt - /// clear - CGIF3: u1, - /// Channel 3 Transfer Complete - /// clear - CTCIF3: u1, - /// Channel 3 Half Transfer - /// clear - CHTIF3: u1, - /// Channel 3 Transfer Error - /// clear - CTEIF3: u1, - /// Channel 4 Global interrupt - /// clear - CGIF4: u1, - /// Channel 4 Transfer Complete - /// clear - CTCIF4: u1, - /// Channel 4 Half Transfer - /// clear - CHTIF4: u1, - /// Channel 4 Transfer Error - /// clear - CTEIF4: u1, - /// Channel 5 Global interrupt - /// clear - CGIF5: u1, - /// Channel 5 Transfer Complete - /// clear - CTCIF5: u1, - /// Channel 5 Half Transfer - /// clear - CHTIF5: u1, - /// Channel 5 Transfer Error - /// clear - CTEIF5: u1, - /// Channel 6 Global interrupt - /// clear - CGIF6: u1, - /// Channel 6 Transfer Complete - /// clear - CTCIF6: u1, - /// Channel 6 Half Transfer - /// clear - CHTIF6: u1, - /// Channel 6 Transfer Error - /// clear - CTEIF6: u1, - /// Channel 7 Global interrupt - /// clear - CGIF7: u1, - /// Channel 7 Transfer Complete - /// clear - CTCIF7: u1, - /// Channel 7 Half Transfer - /// clear - CHTIF7: u1, - /// Channel 7 Transfer Error - /// clear - CTEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40020408 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002040c - /// DMA channel 1 number of data - /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020410 - /// DMA channel 1 peripheral address - /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x10); - - /// address: 0x40020414 - /// DMA channel 1 memory address - /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x14); - - /// address: 0x4002041c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020420 - /// DMA channel 2 number of data - /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020424 - /// DMA channel 2 peripheral address - /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x24); - - /// address: 0x40020428 - /// DMA channel 2 memory address - /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x28); - - /// address: 0x40020430 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020434 - /// DMA channel 3 number of data - /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020438 - /// DMA channel 3 peripheral address - /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x38); - - /// address: 0x4002043c - /// DMA channel 3 memory address - /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x3c); - - /// address: 0x40020444 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020448 - /// DMA channel 4 number of data - /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002044c - /// DMA channel 4 peripheral address - /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x4c); - - /// address: 0x40020450 - /// DMA channel 4 memory address - /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x50); - - /// address: 0x40020458 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002045c - /// DMA channel 5 number of data - /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020460 - /// DMA channel 5 peripheral address - /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40020464 - /// DMA channel 5 memory address - /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x64); - - /// address: 0x4002046c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x6c); - - /// address: 0x40020470 - /// DMA channel 6 number of data - /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40020474 - /// DMA channel 6 peripheral address - /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x74); - - /// address: 0x40020478 - /// DMA channel 6 memory address - /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x78); - - /// address: 0x40020480 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40020484 - /// DMA channel 7 number of data - /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40020488 - /// DMA channel 7 peripheral address - /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x88); - - /// address: 0x4002048c - /// DMA channel 7 memory address - /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x8c); - }; - - /// Secure digital input/output - /// interface - pub const SDIO = struct { - pub const base_address = 0x40018000; - - /// address: 0x40018000 - /// Bits 1:0 = PWRCTRL: Power supply control - /// bits - pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { - /// PWRCTRL - PWRCTRL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - - /// address: 0x40018004 - /// SDI clock control register - /// (SDIO_CLKCR) - pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock divide factor - CLKDIV: u8, - /// Clock enable bit - CLKEN: u1, - /// Power saving configuration - /// bit - PWRSAV: u1, - /// Clock divider bypass enable - /// bit - BYPASS: u1, - /// Wide bus mode enable bit - WIDBUS: u2, - /// SDIO_CK dephasing selection - /// bit - NEGEDGE: u1, - /// HW Flow Control enable - HWFC_EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40018008 - /// Bits 31:0 = : Command argument - pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { - /// Command argument - CMDARG: u32, - }), base_address + 0x8); - - /// address: 0x4001800c - /// SDIO command register - /// (SDIO_CMD) - pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { - /// CMDINDEX - CMDINDEX: u6, - /// WAITRESP - WAITRESP: u2, - /// WAITINT - WAITINT: u1, - /// WAITPEND - WAITPEND: u1, - /// CPSMEN - CPSMEN: u1, - /// SDIOSuspend - SDIOSuspend: u1, - /// ENCMDcompl - ENCMDcompl: u1, - /// nIEN - nIEN: u1, - /// CE_ATACMD - CE_ATACMD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40018010 - /// SDIO command register - pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); - - /// address: 0x40018014 - /// Bits 31:0 = CARDSTATUS1 - pub const RESPI1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CARDSTATUS1 - CARDSTATUS1: u32, - }), base_address + 0x14); - - /// address: 0x40018018 - /// Bits 31:0 = CARDSTATUS2 - pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CARDSTATUS2 - CARDSTATUS2: u32, - }), base_address + 0x18); - - /// address: 0x4001801c - /// Bits 31:0 = CARDSTATUS3 - pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { - /// CARDSTATUS3 - CARDSTATUS3: u32, - }), base_address + 0x1c); - - /// address: 0x40018020 - /// Bits 31:0 = CARDSTATUS4 - pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { - /// CARDSTATUS4 - CARDSTATUS4: u32, - }), base_address + 0x20); - - /// address: 0x40018024 - /// Bits 31:0 = DATATIME: Data timeout - /// period - pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { - /// Data timeout period - DATATIME: u32, - }), base_address + 0x24); - - /// address: 0x40018028 - /// Bits 24:0 = DATALENGTH: Data length - /// value - pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length value - DATALENGTH: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x28); - - /// address: 0x4001802c - /// SDIO data control register - /// (SDIO_DCTRL) - pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DTEN - DTEN: u1, - /// DTDIR - DTDIR: u1, - /// DTMODE - DTMODE: u1, - /// DMAEN - DMAEN: u1, - /// DBLOCKSIZE - DBLOCKSIZE: u4, - /// PWSTART - PWSTART: u1, - /// PWSTOP - PWSTOP: u1, - /// RWMOD - RWMOD: u1, - /// SDIOEN - SDIOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40018030 - /// Bits 24:0 = DATACOUNT: Data count - /// value - pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Data count value - DATACOUNT: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - - /// address: 0x40018034 - /// SDIO status register - /// (SDIO_STA) - pub const STA = @intToPtr(*volatile Mmio(32, packed struct { - /// CCRCFAIL - CCRCFAIL: u1, - /// DCRCFAIL - DCRCFAIL: u1, - /// CTIMEOUT - CTIMEOUT: u1, - /// DTIMEOUT - DTIMEOUT: u1, - /// TXUNDERR - TXUNDERR: u1, - /// RXOVERR - RXOVERR: u1, - /// CMDREND - CMDREND: u1, - /// CMDSENT - CMDSENT: u1, - /// DATAEND - DATAEND: u1, - /// STBITERR - STBITERR: u1, - /// DBCKEND - DBCKEND: u1, - /// CMDACT - CMDACT: u1, - /// TXACT - TXACT: u1, - /// RXACT - RXACT: u1, - /// TXFIFOHE - TXFIFOHE: u1, - /// RXFIFOHF - RXFIFOHF: u1, - /// TXFIFOF - TXFIFOF: u1, - /// RXFIFOF - RXFIFOF: u1, - /// TXFIFOE - TXFIFOE: u1, - /// RXFIFOE - RXFIFOE: u1, - /// TXDAVL - TXDAVL: u1, - /// RXDAVL - RXDAVL: u1, - /// SDIOIT - SDIOIT: u1, - /// CEATAEND - CEATAEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x40018038 - /// SDIO interrupt clear register - /// (SDIO_ICR) - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// CCRCFAILC - CCRCFAILC: u1, - /// DCRCFAILC - DCRCFAILC: u1, - /// CTIMEOUTC - CTIMEOUTC: u1, - /// DTIMEOUTC - DTIMEOUTC: u1, - /// TXUNDERRC - TXUNDERRC: u1, - /// RXOVERRC - RXOVERRC: u1, - /// CMDRENDC - CMDRENDC: u1, - /// CMDSENTC - CMDSENTC: u1, - /// DATAENDC - DATAENDC: u1, - /// STBITERRC - STBITERRC: u1, - /// DBCKENDC - DBCKENDC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// SDIOITC - SDIOITC: u1, - /// CEATAENDC - CEATAENDC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x38); - - /// address: 0x4001803c - /// SDIO mask register (SDIO_MASK) - pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { - /// CCRCFAILIE - CCRCFAILIE: u1, - /// DCRCFAILIE - DCRCFAILIE: u1, - /// CTIMEOUTIE - CTIMEOUTIE: u1, - /// DTIMEOUTIE - DTIMEOUTIE: u1, - /// TXUNDERRIE - TXUNDERRIE: u1, - /// RXOVERRIE - RXOVERRIE: u1, - /// CMDRENDIE - CMDRENDIE: u1, - /// CMDSENTIE - CMDSENTIE: u1, - /// DATAENDIE - DATAENDIE: u1, - /// STBITERRIE - STBITERRIE: u1, - /// DBACKENDIE - DBACKENDIE: u1, - /// CMDACTIE - CMDACTIE: u1, - /// TXACTIE - TXACTIE: u1, - /// RXACTIE - RXACTIE: u1, - /// TXFIFOHEIE - TXFIFOHEIE: u1, - /// RXFIFOHFIE - RXFIFOHFIE: u1, - /// TXFIFOFIE - TXFIFOFIE: u1, - /// RXFIFOFIE - RXFIFOFIE: u1, - /// TXFIFOEIE - TXFIFOEIE: u1, - /// RXFIFOEIE - RXFIFOEIE: u1, - /// TXDAVLIE - TXDAVLIE: u1, - /// RXDAVLIE - RXDAVLIE: u1, - /// SDIOITIE - SDIOITIE: u1, - /// CEATENDIE - CEATENDIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x3c); - - /// address: 0x40018048 - /// Bits 23:0 = FIFOCOUNT: Remaining number of - /// words to be written to or read from the - /// FIFO - pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { - /// FIF0COUNT - FIF0COUNT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x48); - - /// address: 0x40018080 - /// bits 31:0 = FIFOData: Receive and transmit - /// FIFO data - pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFOData - FIFOData: u32, - }), base_address + 0x80); - }; - - /// Real time clock - pub const RTC = struct { - pub const base_address = 0x40002800; - - /// address: 0x40002800 - /// RTC Control Register High - pub const CRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Second interrupt Enable - SECIE: u1, - /// Alarm interrupt Enable - ALRIE: u1, - /// Overflow interrupt Enable - OWIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40002804 - /// RTC Control Register Low - pub const CRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Second Flag - SECF: u1, - /// Alarm Flag - ALRF: u1, - /// Overflow Flag - OWF: u1, - /// Registers Synchronized - /// Flag - RSF: u1, - /// Configuration Flag - CNF: u1, - /// RTC operation OFF - RTOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// RTC Prescaler Load Register - /// High - pub const PRLH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x8); - - /// address: 0x4000280c - /// RTC Prescaler Load Register - /// Low - pub const PRLL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40002810 - /// RTC Prescaler Divider Register - /// High - pub const DIVH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x10); - - /// address: 0x40002814 - /// RTC Prescaler Divider Register - /// Low - pub const DIVL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); - - /// address: 0x40002818 - /// RTC Counter Register High - pub const CNTH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); - - /// address: 0x4000281c - /// RTC Counter Register Low - pub const CNTL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); - - /// address: 0x40002820 - /// RTC Alarm Register High - pub const ALRH = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20); - - /// address: 0x40002824 - /// RTC Alarm Register Low - pub const ALRL = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - }; - - /// Backup registers - pub const BKP = struct { - pub const base_address = 0x40006c04; - - /// address: 0x40006c04 - /// Backup data register (BKP_DR) - pub const DR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D1: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40006c08 - /// Backup data register (BKP_DR) - pub const DR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D2: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40006c0c - /// Backup data register (BKP_DR) - pub const DR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D3: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40006c10 - /// Backup data register (BKP_DR) - pub const DR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D4: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40006c14 - /// Backup data register (BKP_DR) - pub const DR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D5: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40006c18 - /// Backup data register (BKP_DR) - pub const DR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D6: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40006c1c - /// Backup data register (BKP_DR) - pub const DR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D7: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40006c20 - /// Backup data register (BKP_DR) - pub const DR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D8: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40006c24 - /// Backup data register (BKP_DR) - pub const DR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D9: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40006c28 - /// Backup data register (BKP_DR) - pub const DR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D10: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x40006c40 - /// Backup data register (BKP_DR) - pub const DR11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40006c44 - /// Backup data register (BKP_DR) - pub const DR12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40006c48 - /// Backup data register (BKP_DR) - pub const DR13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x44); - - /// address: 0x40006c4c - /// Backup data register (BKP_DR) - pub const DR14 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D14: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x40006c50 - /// Backup data register (BKP_DR) - pub const DR15 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D15: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40006c54 - /// Backup data register (BKP_DR) - pub const DR16 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D16: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x50); - - /// address: 0x40006c58 - /// Backup data register (BKP_DR) - pub const DR17 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D17: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x54); - - /// address: 0x40006c5c - /// Backup data register (BKP_DR) - pub const DR18 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D18: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x58); - - /// address: 0x40006c60 - /// Backup data register (BKP_DR) - pub const DR19 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D19: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40006c64 - /// Backup data register (BKP_DR) - pub const DR20 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D20: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x60); - - /// address: 0x40006c68 - /// Backup data register (BKP_DR) - pub const DR21 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D21: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x64); - - /// address: 0x40006c6c - /// Backup data register (BKP_DR) - pub const DR22 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D22: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x68); - - /// address: 0x40006c70 - /// Backup data register (BKP_DR) - pub const DR23 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D23: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x6c); - - /// address: 0x40006c74 - /// Backup data register (BKP_DR) - pub const DR24 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D24: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40006c78 - /// Backup data register (BKP_DR) - pub const DR25 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D25: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x74); - - /// address: 0x40006c7c - /// Backup data register (BKP_DR) - pub const DR26 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D26: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x78); - - /// address: 0x40006c80 - /// Backup data register (BKP_DR) - pub const DR27 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D27: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x7c); - - /// address: 0x40006c84 - /// Backup data register (BKP_DR) - pub const DR28 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D28: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x80); - - /// address: 0x40006c88 - /// Backup data register (BKP_DR) - pub const DR29 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D29: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40006c8c - /// Backup data register (BKP_DR) - pub const DR30 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D30: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x88); - - /// address: 0x40006c90 - /// Backup data register (BKP_DR) - pub const DR31 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D31: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x40006c94 - /// Backup data register (BKP_DR) - pub const DR32 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D32: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x90); - - /// address: 0x40006c98 - /// Backup data register (BKP_DR) - pub const DR33 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D33: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x94); - - /// address: 0x40006c9c - /// Backup data register (BKP_DR) - pub const DR34 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D34: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x98); - - /// address: 0x40006ca0 - /// Backup data register (BKP_DR) - pub const DR35 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D35: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x9c); - - /// address: 0x40006ca4 - /// Backup data register (BKP_DR) - pub const DR36 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D36: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa0); - - /// address: 0x40006ca8 - /// Backup data register (BKP_DR) - pub const DR37 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D37: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa4); - - /// address: 0x40006cac - /// Backup data register (BKP_DR) - pub const DR38 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D38: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa8); - - /// address: 0x40006cb0 - /// Backup data register (BKP_DR) - pub const DR39 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D39: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xac); - - /// address: 0x40006cb4 - /// Backup data register (BKP_DR) - pub const DR40 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D40: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xb0); - - /// address: 0x40006cb8 - /// Backup data register (BKP_DR) - pub const DR41 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D41: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xb4); - - /// address: 0x40006cbc - /// Backup data register (BKP_DR) - pub const DR42 = @intToPtr(*volatile Mmio(32, packed struct { - /// Backup data - D42: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xb8); - - /// address: 0x40006c2c - /// RTC clock calibration register - /// (BKP_RTCCR) - pub const RTCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration value - CAL: u7, - /// Calibration Clock Output - CCO: u1, - /// Alarm or second output - /// enable - ASOE: u1, - /// Alarm or second output - /// selection - ASOS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x28); - - /// address: 0x40006c30 - /// Backup control register - /// (BKP_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper pin enable - TPE: u1, - /// Tamper pin active level - TPAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x2c); - - /// address: 0x40006c34 - /// BKP_CSR control/status register - /// (BKP_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear Tamper event - CTE: u1, - /// Clear Tamper Interrupt - CTI: u1, - /// Tamper Pin interrupt - /// enable - TPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Tamper Event Flag - TEF: u1, - /// Tamper Interrupt Flag - TIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x30); - }; - - /// Independent watchdog - pub const IWDG = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Key register (IWDG_KR) - pub const KR = @intToPtr(*volatile Mmio(32, packed struct { - /// Key value - KEY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Prescaler register (IWDG_PR) - pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); - - /// address: 0x40003008 - /// Reload register (IWDG_RLR) - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog counter reload - /// value - RL: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// Status register (IWDG_SR) - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog prescaler value - /// update - PVU: u1, - /// Watchdog counter reload value - /// update - RVU: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - }; - - /// Window watchdog - pub const WWDG = struct { - pub const base_address = 0x40002c00; - - /// address: 0x40002c00 - /// Control register (WWDG_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit counter (MSB to LSB) - T: u7, - /// Activation bit - WDGA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40002c04 - /// Configuration register - /// (WWDG_CFR) - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit window value - W: u7, - /// Timer Base - WDGTB: u2, - /// Early Wakeup Interrupt - EWI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x40002c08 - /// Status register (WWDG_SR) - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Early Wakeup Interrupt - EWI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// Advanced timer - pub const TIM1 = struct { - pub const base_address = 0x40012c00; - - /// address: 0x40012c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40012c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40012c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40012c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40012c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40012c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40012c18 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40012c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40012c1c - /// capture/compare mode register (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40012c1c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40012c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40012c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40012c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40012c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40012c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40012c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x40012c3c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40012c40 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40012c48 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x40012c4c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40012c30 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40012c44 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - pub const TIM8 = struct { - pub const base_address = 0x40013400; - - /// address: 0x40013400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40013404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40013408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001340c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40013410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40013414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40013418 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40013418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001341c - /// capture/compare mode register (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4001341c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40013420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40013424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40013428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001342c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40013434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40013438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001343c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40013440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40013448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001344c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40013430 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40013444 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - - /// General purpose timer - pub const TIM2 = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved2: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved4: u1, - reserved5: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40000024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40000028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40000034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40000038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4000003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40000040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40000048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM3 = struct { - pub const base_address = 0x40000400; - - /// address: 0x40000400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved2: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved4: u1, - reserved5: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40000424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40000428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40000434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40000438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4000043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40000440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40000448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM4 = struct { - pub const base_address = 0x40000800; - - /// address: 0x40000800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000080c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000081c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000081c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved2: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved4: u1, - reserved5: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40000824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40000828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000082c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40000834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40000838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4000083c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40000840 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40000848 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000084c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM5 = struct { - pub const base_address = 0x40000c00; - - /// address: 0x40000c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40000c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved2: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved4: u1, - reserved5: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40000c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40000c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40000c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40000c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40000c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x40000c3c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40000c40 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40000c48 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x40000c4c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// General purpose timer - pub const TIM9 = struct { - pub const base_address = 0x40014c00; - - /// address: 0x40014c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40014c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40014c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x40014c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40014c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40014c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40014c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40014c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40014c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40014c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40014c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - pub const TIM12 = struct { - pub const base_address = 0x40001800; - - /// address: 0x40001800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40001808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4000180c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40001810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40001814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40001818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40001818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40001820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40001824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000182c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40001838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - - /// General purpose timer - pub const TIM10 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40015004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4001500c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40015010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40015014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40015018 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - reserved0: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40015018 - /// capture/compare mode register (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40015020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40015024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40015028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001502c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40015034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM11 = struct { - pub const base_address = 0x40015400; - - /// address: 0x40015400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40015404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4001540c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40015410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40015414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40015418 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - reserved0: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40015418 - /// capture/compare mode register (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40015420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40015424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40015428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001542c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40015434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM13 = struct { - pub const base_address = 0x40001c00; - - /// address: 0x40001c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40001c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40001c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40001c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40001c18 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - reserved0: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40001c18 - /// capture/compare mode register (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40001c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40001c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40001c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM14 = struct { - pub const base_address = 0x40002000; - - /// address: 0x40002000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40002004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000200c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40002010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40002014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40002018 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - reserved0: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40002018 - /// capture/compare mode register (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40002020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40002024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40002028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000202c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40002034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - - /// Basic timer - pub const TIM6 = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000100c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000102c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - pub const TIM7 = struct { - pub const base_address = 0x40001400; - - /// address: 0x40001400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000140c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000142c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - - /// Inter integrated circuit - pub const I2C1 = struct { - pub const base_address = 0x40005400; - - /// address: 0x40005400 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005404 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005408 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000540c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005410 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005414 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005418 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000541c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005420 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - }; - pub const I2C2 = struct { - pub const base_address = 0x40005800; - - /// address: 0x40005800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005808 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000580c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005810 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005814 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005818 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000581c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005820 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - }; - - /// Serial peripheral interface - pub const SPI1 = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40013008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4001300c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001301c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI2 = struct { - pub const base_address = 0x40003800; - - /// address: 0x40003800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003808 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4000380c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003810 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003818 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000381c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003820 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI3 = struct { - pub const base_address = 0x40003c00; - - /// address: 0x40003c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003c08 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x40003c0c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003c10 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003c14 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003c18 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40003c1c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003c20 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const USART1 = struct { - pub const base_address = 0x40013800; - - /// address: 0x40013800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40013804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40013808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001380c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40013810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40013814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40013818 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART2 = struct { - pub const base_address = 0x40004400; - - /// address: 0x40004400 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004404 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004408 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000440c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004410 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004414 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40004418 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART3 = struct { - pub const base_address = 0x40004800; - - /// address: 0x40004800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000480c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14); - - /// address: 0x40004818 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - - /// Analog to digital converter - pub const ADC1 = struct { - pub const base_address = 0x40012400; - - /// address: 0x40012400 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40012404 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - /// Dual mode selection - DUALMOD: u4, - reserved0: u1, - reserved1: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012408 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// A/D calibration - CAL: u1, - /// Reset calibration - RSTCAL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Direct memory access mode - DMA: u1, - reserved4: u1, - reserved5: u1, - /// Data alignment - ALIGN: u1, - /// External event select for injected - /// group - JEXTSEL: u3, - /// External trigger conversion mode for - /// injected channels - JEXTTRIG: u1, - reserved6: u1, - /// External event select for regular - /// group - EXTSEL: u3, - /// External trigger conversion mode for - /// regular channels - EXTTRIG: u1, - /// Start conversion of injected - /// channels - JSWSTART: u1, - /// Start conversion of regular - /// channels - SWSTART: u1, - /// Temperature sensor and VREFINT - /// enable - TSVREFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4001240c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 10 sample time - /// selection - SMP10: u3, - /// Channel 11 sample time - /// selection - SMP11: u3, - /// Channel 12 sample time - /// selection - SMP12: u3, - /// Channel 13 sample time - /// selection - SMP13: u3, - /// Channel 14 sample time - /// selection - SMP14: u3, - /// Channel 15 sample time - /// selection - SMP15: u3, - /// Channel 16 sample time - /// selection - SMP16: u3, - /// Channel 17 sample time - /// selection - SMP17: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40012410 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 sample time - /// selection - SMP0: u3, - /// Channel 1 sample time - /// selection - SMP1: u3, - /// Channel 2 sample time - /// selection - SMP2: u3, - /// Channel 3 sample time - /// selection - SMP3: u3, - /// Channel 4 sample time - /// selection - SMP4: u3, - /// Channel 5 sample time - /// selection - SMP5: u3, - /// Channel 6 sample time - /// selection - SMP6: u3, - /// Channel 7 sample time - /// selection - SMP7: u3, - /// Channel 8 sample time - /// selection - SMP8: u3, - /// Channel 9 sample time - /// selection - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40012414 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012418 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001241c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012420 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012424 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012428 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001242c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012430 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012434 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012438 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001243c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012440 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012444 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012448 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001244c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - /// ADC2 data - ADC2DATA: u16, - }), base_address + 0x4c); - }; - - /// Analog to digital converter - pub const ADC2 = struct { - pub const base_address = 0x40012800; - - /// address: 0x40012800 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40012804 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012808 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// A/D calibration - CAL: u1, - /// Reset calibration - RSTCAL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Direct memory access mode - DMA: u1, - reserved4: u1, - reserved5: u1, - /// Data alignment - ALIGN: u1, - /// External event select for injected - /// group - JEXTSEL: u3, - /// External trigger conversion mode for - /// injected channels - JEXTTRIG: u1, - reserved6: u1, - /// External event select for regular - /// group - EXTSEL: u3, - /// External trigger conversion mode for - /// regular channels - EXTTRIG: u1, - /// Start conversion of injected - /// channels - JSWSTART: u1, - /// Start conversion of regular - /// channels - SWSTART: u1, - /// Temperature sensor and VREFINT - /// enable - TSVREFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4001280c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 10 sample time - /// selection - SMP10: u3, - /// Channel 11 sample time - /// selection - SMP11: u3, - /// Channel 12 sample time - /// selection - SMP12: u3, - /// Channel 13 sample time - /// selection - SMP13: u3, - /// Channel 14 sample time - /// selection - SMP14: u3, - /// Channel 15 sample time - /// selection - SMP15: u3, - /// Channel 16 sample time - /// selection - SMP16: u3, - /// Channel 17 sample time - /// selection - SMP17: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40012810 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 sample time - /// selection - SMP0: u3, - /// Channel 1 sample time - /// selection - SMP1: u3, - /// Channel 2 sample time - /// selection - SMP2: u3, - /// Channel 3 sample time - /// selection - SMP3: u3, - /// Channel 4 sample time - /// selection - SMP4: u3, - /// Channel 5 sample time - /// selection - SMP5: u3, - /// Channel 6 sample time - /// selection - SMP6: u3, - /// Channel 7 sample time - /// selection - SMP7: u3, - /// Channel 8 sample time - /// selection - SMP8: u3, - /// Channel 9 sample time - /// selection - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40012814 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012818 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001281c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012820 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012824 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012828 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001282c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012830 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012834 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012838 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001283c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012840 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012844 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012848 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001284c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const ADC3 = struct { - pub const base_address = 0x40013c00; - - /// address: 0x40013c00 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - - /// address: 0x40013c04 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40013c08 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - /// A/D calibration - CAL: u1, - /// Reset calibration - RSTCAL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Direct memory access mode - DMA: u1, - reserved4: u1, - reserved5: u1, - /// Data alignment - ALIGN: u1, - /// External event select for injected - /// group - JEXTSEL: u3, - /// External trigger conversion mode for - /// injected channels - JEXTTRIG: u1, - reserved6: u1, - /// External event select for regular - /// group - EXTSEL: u3, - /// External trigger conversion mode for - /// regular channels - EXTTRIG: u1, - /// Start conversion of injected - /// channels - JSWSTART: u1, - /// Start conversion of regular - /// channels - SWSTART: u1, - /// Temperature sensor and VREFINT - /// enable - TSVREFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x40013c0c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 10 sample time - /// selection - SMP10: u3, - /// Channel 11 sample time - /// selection - SMP11: u3, - /// Channel 12 sample time - /// selection - SMP12: u3, - /// Channel 13 sample time - /// selection - SMP13: u3, - /// Channel 14 sample time - /// selection - SMP14: u3, - /// Channel 15 sample time - /// selection - SMP15: u3, - /// Channel 16 sample time - /// selection - SMP16: u3, - /// Channel 17 sample time - /// selection - SMP17: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40013c10 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 0 sample time - /// selection - SMP0: u3, - /// Channel 1 sample time - /// selection - SMP1: u3, - /// Channel 2 sample time - /// selection - SMP2: u3, - /// Channel 3 sample time - /// selection - SMP3: u3, - /// Channel 4 sample time - /// selection - SMP4: u3, - /// Channel 5 sample time - /// selection - SMP5: u3, - /// Channel 6 sample time - /// selection - SMP6: u3, - /// Channel 7 sample time - /// selection - SMP7: u3, - /// Channel 8 sample time - /// selection - SMP8: u3, - /// Channel 9 sample time - /// selection - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40013c14 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40013c18 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x40013c1c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013c20 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40013c24 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40013c28 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x40013c2c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40013c30 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40013c34 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40013c38 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x40013c3c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40013c40 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40013c44 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40013c48 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x40013c4c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// Controller area network - pub const CAN = struct { - pub const base_address = 0x40006400; - - /// address: 0x40006400 - /// CAN_MCR - pub const CAN_MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006404 - /// CAN_MSR - pub const CAN_MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006408 - /// CAN_TSR - pub const CAN_TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000640c - /// CAN_RF0R - pub const CAN_RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006410 - /// CAN_RF1R - pub const CAN_RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006414 - /// CAN_IER - pub const CAN_IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006418 - /// CAN_ESR - pub const CAN_ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000641c - /// CAN_BTR - pub const CAN_BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006580 - /// CAN_TI0R - pub const CAN_TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006584 - /// CAN_TDT0R - pub const CAN_TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006588 - /// CAN_TDL0R - pub const CAN_TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000658c - /// CAN_TDH0R - pub const CAN_TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006590 - /// CAN_TI1R - pub const CAN_TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006594 - /// CAN_TDT1R - pub const CAN_TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006598 - /// CAN_TDL1R - pub const CAN_TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000659c - /// CAN_TDH1R - pub const CAN_TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400065a0 - /// CAN_TI2R - pub const CAN_TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400065a4 - /// CAN_TDT2R - pub const CAN_TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400065a8 - /// CAN_TDL2R - pub const CAN_TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400065ac - /// CAN_TDH2R - pub const CAN_TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400065b0 - /// CAN_RI0R - pub const CAN_RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400065b4 - /// CAN_RDT0R - pub const CAN_RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400065b8 - /// CAN_RDL0R - pub const CAN_RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400065bc - /// CAN_RDH0R - pub const CAN_RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400065c0 - /// CAN_RI1R - pub const CAN_RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400065c4 - /// CAN_RDT1R - pub const CAN_RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400065c8 - /// CAN_RDL1R - pub const CAN_RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400065cc - /// CAN_RDH1R - pub const CAN_RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006600 - /// CAN_FMR - pub const CAN_FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// FINIT - FINIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x200); - - /// address: 0x40006604 - /// CAN_FM1R - pub const CAN_FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x204); - - /// address: 0x4000660c - /// CAN_FS1R - pub const CAN_FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20c); - - /// address: 0x40006614 - /// CAN_FFA1R - pub const CAN_FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x214); - - /// address: 0x4000661c - /// CAN_FA1R - pub const CAN_FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x21c); - - /// address: 0x40006640 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006644 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006648 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x4000664c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006650 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006654 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006658 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x4000665c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006660 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006664 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006668 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x4000666c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006670 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006674 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006678 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x4000667c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006680 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006684 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006688 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x4000668c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006690 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006694 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006698 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x4000669c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x400066a0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x400066a4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x400066a8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x400066ac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - }; - - /// Digital to analog converter - pub const DAC = struct { - pub const base_address = 0x40007400; - - /// address: 0x40007400 - /// Control register (DAC_CR) - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 enable - EN1: u1, - /// DAC channel1 output buffer - /// disable - BOFF1: u1, - /// DAC channel1 trigger - /// enable - TEN1: u1, - /// DAC channel1 trigger - /// selection - TSEL1: u3, - /// DAC channel1 noise/triangle wave - /// generation enable - WAVE1: u2, - /// DAC channel1 mask/amplitude - /// selector - MAMP1: u4, - /// DAC channel1 DMA enable - DMAEN1: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DAC channel2 enable - EN2: u1, - /// DAC channel2 output buffer - /// disable - BOFF2: u1, - /// DAC channel2 trigger - /// enable - TEN2: u1, - /// DAC channel2 trigger - /// selection - TSEL2: u3, - /// DAC channel2 noise/triangle wave - /// generation enable - WAVE2: u2, - /// DAC channel2 mask/amplitude - /// selector - MAMP2: u4, - /// DAC channel2 DMA enable - DMAEN2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x0); - - /// address: 0x40007404 - /// DAC software trigger register - /// (DAC_SWTRIGR) - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 software - /// trigger - SWTRIG1: u1, - /// DAC channel2 software - /// trigger - SWTRIG2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40007408 - /// DAC channel1 12-bit right-aligned data - /// holding register(DAC_DHR12R1) - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000740c - /// DAC channel1 12-bit left aligned data - /// holding register (DAC_DHR12L1) - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007410 - /// DAC channel1 8-bit right aligned data - /// holding register (DAC_DHR8R1) - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40007414 - /// DAC channel2 12-bit right aligned data - /// holding register (DAC_DHR12R2) - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007418 - /// DAC channel2 12-bit left aligned data - /// holding register (DAC_DHR12L2) - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000741c - /// DAC channel2 8-bit right-aligned data - /// holding register (DAC_DHR8R2) - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1c); - - /// address: 0x40007420 - /// Dual DAC 12-bit right-aligned data holding - /// register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 - /// Reserved - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x40007424 - /// DUAL DAC 12-bit left aligned data holding - /// register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 - /// Reserved - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - }), base_address + 0x24); - - /// address: 0x40007428 - /// DUAL DAC 8-bit right aligned data holding - /// register (DAC_DHR8RD), Bits 31:16 Reserved - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000742c - /// DAC channel1 data output register - /// (DAC_DOR1) - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40007430 - /// DAC channel2 data output register - /// (DAC_DOR2) - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - }; - - /// Debug support - pub const DBG = struct { - pub const base_address = 0xe0042000; - - /// address: 0xe0042000 - /// DBGMCU_IDCODE - pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct { - /// DEV_ID - DEV_ID: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// REV_ID - REV_ID: u16, - }), base_address + 0x0); - - /// address: 0xe0042004 - /// DBGMCU_CR - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved0: u1, - reserved1: u1, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - /// DBG_IWDG_STOP - DBG_IWDG_STOP: u1, - /// DBG_WWDG_STOP - DBG_WWDG_STOP: u1, - /// DBG_TIM1_STOP - DBG_TIM1_STOP: u1, - /// DBG_TIM2_STOP - DBG_TIM2_STOP: u1, - /// DBG_TIM3_STOP - DBG_TIM3_STOP: u1, - /// DBG_TIM4_STOP - DBG_TIM4_STOP: u1, - /// DBG_CAN1_STOP - DBG_CAN1_STOP: u1, - /// DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT: u1, - /// DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, - /// DBG_TIM8_STOP - DBG_TIM8_STOP: u1, - /// DBG_TIM5_STOP - DBG_TIM5_STOP: u1, - /// DBG_TIM6_STOP - DBG_TIM6_STOP: u1, - /// DBG_TIM7_STOP - DBG_TIM7_STOP: u1, - /// DBG_CAN2_STOP - DBG_CAN2_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x4); - }; - - /// Universal asynchronous receiver - /// transmitter - pub const UART4 = struct { - pub const base_address = 0x40004c00; - - /// address: 0x40004c00 - /// UART4_SR - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise error flag - NE: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40004c04 - /// UART4_DR - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004c08 - /// UART4_BRR - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// DIV_Fraction - DIV_Fraction: u4, - /// DIV_Mantissa - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40004c0c - /// UART4_CR1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40004c10 - /// UART4_CR2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004c14 - /// UART4_CR3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - }; - - /// Universal asynchronous receiver - /// transmitter - pub const UART5 = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// UART4_SR - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// PE - PE: u1, - /// FE - FE: u1, - /// NE - NE: u1, - /// ORE - ORE: u1, - /// IDLE - IDLE: u1, - /// RXNE - RXNE: u1, - /// TC - TC: u1, - /// TXE - TXE: u1, - /// LBD - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// UART4_DR - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40005008 - /// UART4_BRR - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// DIV_Fraction - DIV_Fraction: u4, - /// DIV_Mantissa - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000500c - /// UART4_CR1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SBK - SBK: u1, - /// RWU - RWU: u1, - /// RE - RE: u1, - /// TE - TE: u1, - /// IDLEIE - IDLEIE: u1, - /// RXNEIE - RXNEIE: u1, - /// TCIE - TCIE: u1, - /// TXEIE - TXEIE: u1, - /// PEIE - PEIE: u1, - /// PS - PS: u1, - /// PCE - PCE: u1, - /// WAKE - WAKE: u1, - /// M - M: u1, - /// UE - UE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0xc); - - /// address: 0x40005010 - /// UART4_CR2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADD - ADD: u4, - reserved0: u1, - /// LBDL - LBDL: u1, - /// LBDIE - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP - STOP: u2, - /// LINEN - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40005014 - /// UART4_CR3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA enable transmitter - DMAT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - }; - - /// CRC calculation unit - pub const CRC = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023000 - /// Data register - pub const DR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40023004 - /// Independent Data register - pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40023008 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reset bit - RESET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// FLASH - pub const FLASH = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022000 - /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Latency - LATENCY: u3, - /// Flash half cycle access - /// enable - HLFCYA: u1, - /// Prefetch buffer enable - PRFTBE: u1, - /// Prefetch buffer status - PRFTBS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40022004 - /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// FPEC key - KEY: u32, - }), base_address + 0x4); - - /// address: 0x40022008 - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option byte key - OPTKEY: u32, - }), base_address + 0x8); - - /// address: 0x4002200c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Busy - BSY: u1, - reserved0: u1, - /// Programming error - PGERR: u1, - reserved1: u1, - /// Write protection error - WRPRTERR: u1, - /// End of operation - EOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40022010 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Programming - PG: u1, - /// Page Erase - PER: u1, - /// Mass Erase - MER: u1, - reserved0: u1, - /// Option byte programming - OPTPG: u1, - /// Option byte erase - OPTER: u1, - /// Start - STRT: u1, - /// Lock - LOCK: u1, - reserved1: u1, - /// Option bytes write enable - OPTWRE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved2: u1, - /// End of operation interrupt - /// enable - EOPIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40022014 - /// Flash address register - pub const AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flash Address - FAR: u32, - }), base_address + 0x14); - - /// address: 0x4002201c - /// Option byte register - pub const OBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option byte error - OPTERR: u1, - /// Read protection - RDPRT: u1, - /// WDG_SW - WDG_SW: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Data0 - Data0: u8, - /// Data1 - Data1: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x1c); - - /// address: 0x40022020 - /// Write protection register - pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write protect - WRP: u32, - }), base_address + 0x20); - }; - - /// Nested Vectored Interrupt - /// Controller - pub const NVIC = struct { - pub const base_address = 0xe000e000; - - /// address: 0xe000e004 - /// Interrupt Controller Type - /// Register - pub const ICTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Total number of interrupt lines in - /// groups - INTLINESNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x4); - - /// address: 0xe000ef00 - /// Software Triggered Interrupt - /// Register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { - /// interrupt to be triggered - INTID: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xf00); - - /// address: 0xe000e100 - /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x100); - - /// address: 0xe000e104 - /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x104); - - /// address: 0xe000e180 - /// Interrupt Clear-Enable - /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x180); - - /// address: 0xe000e184 - /// Interrupt Clear-Enable - /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x184); - - /// address: 0xe000e200 - /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x200); - - /// address: 0xe000e204 - /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x204); - - /// address: 0xe000e280 - /// Interrupt Clear-Pending - /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x280); - - /// address: 0xe000e284 - /// Interrupt Clear-Pending - /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x284); - - /// address: 0xe000e300 - /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x300); - - /// address: 0xe000e304 - /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x304); - - /// address: 0xe000e400 - /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x400); - - /// address: 0xe000e404 - /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x404); - - /// address: 0xe000e408 - /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x408); - - /// address: 0xe000e40c - /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x40c); - - /// address: 0xe000e410 - /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x410); - - /// address: 0xe000e414 - /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x414); - - /// address: 0xe000e418 - /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x418); - - /// address: 0xe000e41c - /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x41c); - - /// address: 0xe000e420 - /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x420); - - /// address: 0xe000e424 - /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x424); - - /// address: 0xe000e428 - /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x428); - - /// address: 0xe000e42c - /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x42c); - - /// address: 0xe000e430 - /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x430); - - /// address: 0xe000e434 - /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x434); - - /// address: 0xe000e438 - /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x438); - }; - - /// Universal serial bus full-speed device - /// interface - pub const USB = struct { - pub const base_address = 0x40005c00; - - /// address: 0x40005c00 - /// endpoint 0 register - pub const EP0R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005c04 - /// endpoint 1 register - pub const EP1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40005c08 - /// endpoint 2 register - pub const EP2R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40005c0c - /// endpoint 3 register - pub const EP3R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005c10 - /// endpoint 4 register - pub const EP4R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40005c14 - /// endpoint 5 register - pub const EP5R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005c18 - /// endpoint 6 register - pub const EP6R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40005c1c - /// endpoint 7 register - pub const EP7R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005c40 - /// control register - pub const CNTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Force USB Reset - FRES: u1, - /// Power down - PDWN: u1, - /// Low-power mode - LPMODE: u1, - /// Force suspend - FSUSP: u1, - /// Resume request - RESUME: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Expected start of frame interrupt - /// mask - ESOFM: u1, - /// Start of frame interrupt - /// mask - SOFM: u1, - /// USB reset interrupt mask - RESETM: u1, - /// Suspend mode interrupt - /// mask - SUSPM: u1, - /// Wakeup interrupt mask - WKUPM: u1, - /// Error interrupt mask - ERRM: u1, - /// Packet memory area over / underrun - /// interrupt mask - PMAOVRM: u1, - /// Correct transfer interrupt - /// mask - CTRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40005c44 - /// interrupt status register - pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint Identifier - EP_ID: u4, - /// Direction of transaction - DIR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Expected start frame - ESOF: u1, - /// start of frame - SOF: u1, - /// reset request - RESET: u1, - /// Suspend mode request - SUSP: u1, - /// Wakeup - WKUP: u1, - /// Error - ERR: u1, - /// Packet memory area over / - /// underrun - PMAOVR: u1, - /// Correct transfer - CTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40005c48 - /// frame number register - pub const FNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FN: u11, - /// Lost SOF - LSOF: u2, - /// Locked - LCK: u1, - /// Receive data - line status - RXDM: u1, - /// Receive data + line status - RXDP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x40005c4c - /// device address - pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Device address - ADD: u7, - /// Enable function - EF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4c); - - /// address: 0x40005c50 - /// Buffer table address - pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/stm32f103/stm32f103.zig b/src/modules/chips/stm32f103/stm32f103.zig deleted file mode 100644 index e2d554e..0000000 --- a/src/modules/chips/stm32f103/stm32f103.zig +++ /dev/null @@ -1,2 +0,0 @@ -pub const cpu = @import("cpu"); -pub usingnamespace @import("registers.zig"); diff --git a/src/modules/chips/stm32f303/registers.zig b/src/modules/chips/stm32f303/registers.zig deleted file mode 100644 index 4ce8ebe..0000000 --- a/src/modules/chips/stm32f303/registers.zig +++ /dev/null @@ -1,34412 +0,0 @@ -// this file is generated by regz -// -// device: STM32F303 -// cpu: CM4 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - /// Window Watchdog interrupt - WWDG: InterruptVector = unhandled, - /// PVD through EXTI line detection - /// interrupt - PVD: InterruptVector = unhandled, - /// Tamper and TimeStamp interrupts - TAMP_STAMP: InterruptVector = unhandled, - /// RTC Wakeup interrupt through the EXTI - /// line - RTC_WKUP: InterruptVector = unhandled, - /// Flash global interrupt - FLASH: InterruptVector = unhandled, - /// RCC global interrupt - RCC: InterruptVector = unhandled, - /// EXTI Line0 interrupt - EXTI0: InterruptVector = unhandled, - /// EXTI Line3 interrupt - EXTI1: InterruptVector = unhandled, - /// EXTI Line2 and Touch sensing - /// interrupts - EXTI2_TSC: InterruptVector = unhandled, - /// EXTI Line3 interrupt - EXTI3: InterruptVector = unhandled, - /// EXTI Line4 interrupt - EXTI4: InterruptVector = unhandled, - /// DMA1 channel 1 interrupt - DMA1_CH1: InterruptVector = unhandled, - /// DMA1 channel 2 interrupt - DMA1_CH2: InterruptVector = unhandled, - /// DMA1 channel 3 interrupt - DMA1_CH3: InterruptVector = unhandled, - /// DMA1 channel 4 interrupt - DMA1_CH4: InterruptVector = unhandled, - /// DMA1 channel 5 interrupt - DMA1_CH5: InterruptVector = unhandled, - /// DMA1 channel 6 interrupt - DMA1_CH6: InterruptVector = unhandled, - /// DMA1 channel 7interrupt - DMA1_CH7: InterruptVector = unhandled, - /// ADC1 and ADC2 global interrupt - ADC1_2: InterruptVector = unhandled, - /// USB High Priority/CAN_TX - /// interrupts - USB_HP_CAN_TX: InterruptVector = unhandled, - /// USB Low Priority/CAN_RX0 - /// interrupts - USB_LP_CAN_RX0: InterruptVector = unhandled, - /// CAN_RX1 interrupt - CAN_RX1: InterruptVector = unhandled, - /// CAN_SCE interrupt - CAN_SCE: InterruptVector = unhandled, - /// EXTI Line5 to Line9 interrupts - EXTI9_5: InterruptVector = unhandled, - /// TIM1 Break/TIM15 global - /// interruts - TIM1_BRK_TIM15: InterruptVector = unhandled, - /// TIM1 Update/TIM16 global - /// interrupts - TIM1_UP_TIM16: InterruptVector = unhandled, - /// TIM1 trigger and commutation/TIM17 - /// interrupts - TIM1_TRG_COM_TIM17: InterruptVector = unhandled, - /// TIM1 capture compare interrupt - TIM1_CC: InterruptVector = unhandled, - /// TIM2 global interrupt - TIM2: InterruptVector = unhandled, - /// TIM3 global interrupt - TIM3: InterruptVector = unhandled, - /// TIM4 global interrupt - TIM4: InterruptVector = unhandled, - /// I2C1 event interrupt and EXTI Line23 - /// interrupt - I2C1_EV_EXTI23: InterruptVector = unhandled, - /// I2C1 error interrupt - I2C1_ER: InterruptVector = unhandled, - /// I2C2 event interrupt & EXTI Line24 - /// interrupt - I2C2_EV_EXTI24: InterruptVector = unhandled, - /// I2C2 error interrupt - I2C2_ER: InterruptVector = unhandled, - /// SPI1 global interrupt - SPI1: InterruptVector = unhandled, - /// SPI2 global interrupt - SPI2: InterruptVector = unhandled, - /// USART1 global interrupt and EXTI Line 25 - /// interrupt - USART1_EXTI25: InterruptVector = unhandled, - /// USART2 global interrupt and EXTI Line 26 - /// interrupt - USART2_EXTI26: InterruptVector = unhandled, - /// USART3 global interrupt and EXTI Line 28 - /// interrupt - USART3_EXTI28: InterruptVector = unhandled, - /// EXTI Line15 to Line10 interrupts - EXTI15_10: InterruptVector = unhandled, - /// RTC alarm interrupt - RTCAlarm: InterruptVector = unhandled, - /// USB wakeup from Suspend - USB_WKUP: InterruptVector = unhandled, - /// TIM8 break interrupt - TIM8_BRK: InterruptVector = unhandled, - /// TIM8 update interrupt - TIM8_UP: InterruptVector = unhandled, - /// TIM8 Trigger and commutation - /// interrupts - TIM8_TRG_COM: InterruptVector = unhandled, - /// TIM8 capture compare interrupt - TIM8_CC: InterruptVector = unhandled, - /// ADC3 global interrupt - ADC3: InterruptVector = unhandled, - /// FSMC global interrupt - FMC: InterruptVector = unhandled, - reserved2: u32 = undefined, - reserved3: u32 = undefined, - /// SPI3 global interrupt - SPI3: InterruptVector = unhandled, - /// UART4 global and EXTI Line 34 - /// interrupts - UART4_EXTI34: InterruptVector = unhandled, - /// UART5 global and EXTI Line 35 - /// interrupts - UART5_EXTI35: InterruptVector = unhandled, - /// TIM6 global and DAC12 underrun - /// interrupts - TIM6_DACUNDER: InterruptVector = unhandled, - /// TIM7 global interrupt - TIM7: InterruptVector = unhandled, - /// DMA2 channel1 global interrupt - DMA2_CH1: InterruptVector = unhandled, - /// DMA2 channel2 global interrupt - DMA2_CH2: InterruptVector = unhandled, - /// DMA2 channel3 global interrupt - DMA2_CH3: InterruptVector = unhandled, - /// DMA2 channel4 global interrupt - DMA2_CH4: InterruptVector = unhandled, - /// DMA2 channel5 global interrupt - DMA2_CH5: InterruptVector = unhandled, - /// ADC4 global interrupt - ADC4: InterruptVector = unhandled, - reserved4: u32 = undefined, - reserved5: u32 = undefined, - /// COMP1 & COMP2 & COMP3 interrupts - /// combined with EXTI Lines 21, 22 and 29 - /// interrupts - COMP123: InterruptVector = unhandled, - /// COMP4 & COMP5 & COMP6 interrupts - /// combined with EXTI Lines 30, 31 and 32 - /// interrupts - COMP456: InterruptVector = unhandled, - /// COMP7 interrupt combined with EXTI Line 33 - /// interrupt - COMP7: InterruptVector = unhandled, - reserved6: u32 = undefined, - reserved7: u32 = undefined, - reserved8: u32 = undefined, - reserved9: u32 = undefined, - reserved10: u32 = undefined, - /// I2C3 Event interrupt - I2C3_EV: InterruptVector = unhandled, - /// I2C3 Error interrupt - I2C3_ER: InterruptVector = unhandled, - /// USB High priority interrupt - USB_HP: InterruptVector = unhandled, - /// USB Low priority interrupt - USB_LP: InterruptVector = unhandled, - /// USB wakeup from Suspend and EXTI Line - /// 18 - USB_WKUP_EXTI: InterruptVector = unhandled, - /// TIM20 Break interrupt - TIM20_BRK: InterruptVector = unhandled, - /// TIM20 Upgrade interrupt - TIM20_UP: InterruptVector = unhandled, - /// TIM20 Trigger and Commutation - /// interrupt - TIM20_TRG_COM: InterruptVector = unhandled, - /// TIM20 Capture Compare interrupt - TIM20_CC: InterruptVector = unhandled, - /// Floating point unit interrupt - FPU: InterruptVector = unhandled, - reserved11: u32 = undefined, - reserved12: u32 = undefined, - /// SPI4 Global interrupt - SPI4: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// General-purpose I/Os - pub const GPIOA = struct { - pub const base_address = 0x48000000; - - /// address: 0x48000000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48000004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48000008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800000c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48000010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48000014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48000018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800001c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48000020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48000024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48000028 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - /// General-purpose I/Os - pub const GPIOB = struct { - pub const base_address = 0x48000400; - - /// address: 0x48000400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48000404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48000408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800040c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48000410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48000414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48000418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800041c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48000420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48000424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48000428 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOC = struct { - pub const base_address = 0x48000800; - - /// address: 0x48000800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48000804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48000808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800080c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48000810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48000814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48000818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800081c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48000820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48000824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48000828 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOD = struct { - pub const base_address = 0x48000c00; - - /// address: 0x48000c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48000c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48000c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x48000c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48000c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48000c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48000c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x48000c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48000c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48000c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48000c28 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOE = struct { - pub const base_address = 0x48001000; - - /// address: 0x48001000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48001004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48001008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800100c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48001010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48001014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48001018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800101c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48001020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48001024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48001028 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOF = struct { - pub const base_address = 0x48001400; - - /// address: 0x48001400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48001404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48001408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800140c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48001410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48001414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48001418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800141c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48001420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48001424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48001428 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOG = struct { - pub const base_address = 0x48001800; - - /// address: 0x48001800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48001804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48001808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4800180c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48001810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48001814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48001818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4800181c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48001820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48001824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48001828 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - pub const GPIOH = struct { - pub const base_address = 0x48001c00; - - /// address: 0x48001c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x48001c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bit 0 - OT0: u1, - /// Port x configuration bit 1 - OT1: u1, - /// Port x configuration bit 2 - OT2: u1, - /// Port x configuration bit 3 - OT3: u1, - /// Port x configuration bit 4 - OT4: u1, - /// Port x configuration bit 5 - OT5: u1, - /// Port x configuration bit 6 - OT6: u1, - /// Port x configuration bit 7 - OT7: u1, - /// Port x configuration bit 8 - OT8: u1, - /// Port x configuration bit 9 - OT9: u1, - /// Port x configuration bit - /// 10 - OT10: u1, - /// Port x configuration bit - /// 11 - OT11: u1, - /// Port x configuration bit - /// 12 - OT12: u1, - /// Port x configuration bit - /// 13 - OT13: u1, - /// Port x configuration bit - /// 14 - OT14: u1, - /// Port x configuration bit - /// 15 - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x48001c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x48001c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x48001c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x48001c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x48001c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x48001c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Lok Key - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x48001c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x48001c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - - /// address: 0x48001c28 - /// Port bit reset register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x Reset bit y - BR0: u1, - /// Port x Reset bit y - BR1: u1, - /// Port x Reset bit y - BR2: u1, - /// Port x Reset bit y - BR3: u1, - /// Port x Reset bit y - BR4: u1, - /// Port x Reset bit y - BR5: u1, - /// Port x Reset bit y - BR6: u1, - /// Port x Reset bit y - BR7: u1, - /// Port x Reset bit y - BR8: u1, - /// Port x Reset bit y - BR9: u1, - /// Port x Reset bit y - BR10: u1, - /// Port x Reset bit y - BR11: u1, - /// Port x Reset bit y - BR12: u1, - /// Port x Reset bit y - BR13: u1, - /// Port x Reset bit y - BR14: u1, - /// Port x Reset bit y - BR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - }; - /// Touch sensing controller - pub const TSC = struct { - pub const base_address = 0x40024000; - - /// address: 0x40024000 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Touch sensing controller - /// enable - TSCE: u1, - /// Start a new acquisition - START: u1, - /// Acquisition mode - AM: u1, - /// Synchronization pin - /// polarity - SYNCPOL: u1, - /// I/O Default mode - IODEF: u1, - /// Max count value - MCV: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// pulse generator prescaler - PGPSC: u3, - /// Spread spectrum prescaler - SSPSC: u1, - /// Spread spectrum enable - SSE: u1, - /// Spread spectrum deviation - SSD: u7, - /// Charge transfer pulse low - CTPL: u4, - /// Charge transfer pulse high - CTPH: u4, - }), base_address + 0x0); - - /// address: 0x40024004 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// End of acquisition interrupt - /// enable - EOAIE: u1, - /// Max count error interrupt - /// enable - MCEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40024008 - /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// End of acquisition interrupt - /// clear - EOAIC: u1, - /// Max count error interrupt - /// clear - MCEIC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x8); - - /// address: 0x4002400c - /// interrupt status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// End of acquisition flag - EOAF: u1, - /// Max count error flag - MCEF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40024010 - /// I/O hysteresis control - /// register - pub const IOHCR = @intToPtr(*volatile Mmio(32, packed struct { - /// G1_IO1 Schmitt trigger hysteresis - /// mode - G1_IO1: u1, - /// G1_IO2 Schmitt trigger hysteresis - /// mode - G1_IO2: u1, - /// G1_IO3 Schmitt trigger hysteresis - /// mode - G1_IO3: u1, - /// G1_IO4 Schmitt trigger hysteresis - /// mode - G1_IO4: u1, - /// G2_IO1 Schmitt trigger hysteresis - /// mode - G2_IO1: u1, - /// G2_IO2 Schmitt trigger hysteresis - /// mode - G2_IO2: u1, - /// G2_IO3 Schmitt trigger hysteresis - /// mode - G2_IO3: u1, - /// G2_IO4 Schmitt trigger hysteresis - /// mode - G2_IO4: u1, - /// G3_IO1 Schmitt trigger hysteresis - /// mode - G3_IO1: u1, - /// G3_IO2 Schmitt trigger hysteresis - /// mode - G3_IO2: u1, - /// G3_IO3 Schmitt trigger hysteresis - /// mode - G3_IO3: u1, - /// G3_IO4 Schmitt trigger hysteresis - /// mode - G3_IO4: u1, - /// G4_IO1 Schmitt trigger hysteresis - /// mode - G4_IO1: u1, - /// G4_IO2 Schmitt trigger hysteresis - /// mode - G4_IO2: u1, - /// G4_IO3 Schmitt trigger hysteresis - /// mode - G4_IO3: u1, - /// G4_IO4 Schmitt trigger hysteresis - /// mode - G4_IO4: u1, - /// G5_IO1 Schmitt trigger hysteresis - /// mode - G5_IO1: u1, - /// G5_IO2 Schmitt trigger hysteresis - /// mode - G5_IO2: u1, - /// G5_IO3 Schmitt trigger hysteresis - /// mode - G5_IO3: u1, - /// G5_IO4 Schmitt trigger hysteresis - /// mode - G5_IO4: u1, - /// G6_IO1 Schmitt trigger hysteresis - /// mode - G6_IO1: u1, - /// G6_IO2 Schmitt trigger hysteresis - /// mode - G6_IO2: u1, - /// G6_IO3 Schmitt trigger hysteresis - /// mode - G6_IO3: u1, - /// G6_IO4 Schmitt trigger hysteresis - /// mode - G6_IO4: u1, - /// G7_IO1 Schmitt trigger hysteresis - /// mode - G7_IO1: u1, - /// G7_IO2 Schmitt trigger hysteresis - /// mode - G7_IO2: u1, - /// G7_IO3 Schmitt trigger hysteresis - /// mode - G7_IO3: u1, - /// G7_IO4 Schmitt trigger hysteresis - /// mode - G7_IO4: u1, - /// G8_IO1 Schmitt trigger hysteresis - /// mode - G8_IO1: u1, - /// G8_IO2 Schmitt trigger hysteresis - /// mode - G8_IO2: u1, - /// G8_IO3 Schmitt trigger hysteresis - /// mode - G8_IO3: u1, - /// G8_IO4 Schmitt trigger hysteresis - /// mode - G8_IO4: u1, - }), base_address + 0x10); - - /// address: 0x40024018 - /// I/O analog switch control - /// register - pub const IOASCR = @intToPtr(*volatile Mmio(32, packed struct { - /// G1_IO1 analog switch - /// enable - G1_IO1: u1, - /// G1_IO2 analog switch - /// enable - G1_IO2: u1, - /// G1_IO3 analog switch - /// enable - G1_IO3: u1, - /// G1_IO4 analog switch - /// enable - G1_IO4: u1, - /// G2_IO1 analog switch - /// enable - G2_IO1: u1, - /// G2_IO2 analog switch - /// enable - G2_IO2: u1, - /// G2_IO3 analog switch - /// enable - G2_IO3: u1, - /// G2_IO4 analog switch - /// enable - G2_IO4: u1, - /// G3_IO1 analog switch - /// enable - G3_IO1: u1, - /// G3_IO2 analog switch - /// enable - G3_IO2: u1, - /// G3_IO3 analog switch - /// enable - G3_IO3: u1, - /// G3_IO4 analog switch - /// enable - G3_IO4: u1, - /// G4_IO1 analog switch - /// enable - G4_IO1: u1, - /// G4_IO2 analog switch - /// enable - G4_IO2: u1, - /// G4_IO3 analog switch - /// enable - G4_IO3: u1, - /// G4_IO4 analog switch - /// enable - G4_IO4: u1, - /// G5_IO1 analog switch - /// enable - G5_IO1: u1, - /// G5_IO2 analog switch - /// enable - G5_IO2: u1, - /// G5_IO3 analog switch - /// enable - G5_IO3: u1, - /// G5_IO4 analog switch - /// enable - G5_IO4: u1, - /// G6_IO1 analog switch - /// enable - G6_IO1: u1, - /// G6_IO2 analog switch - /// enable - G6_IO2: u1, - /// G6_IO3 analog switch - /// enable - G6_IO3: u1, - /// G6_IO4 analog switch - /// enable - G6_IO4: u1, - /// G7_IO1 analog switch - /// enable - G7_IO1: u1, - /// G7_IO2 analog switch - /// enable - G7_IO2: u1, - /// G7_IO3 analog switch - /// enable - G7_IO3: u1, - /// G7_IO4 analog switch - /// enable - G7_IO4: u1, - /// G8_IO1 analog switch - /// enable - G8_IO1: u1, - /// G8_IO2 analog switch - /// enable - G8_IO2: u1, - /// G8_IO3 analog switch - /// enable - G8_IO3: u1, - /// G8_IO4 analog switch - /// enable - G8_IO4: u1, - }), base_address + 0x18); - - /// address: 0x40024020 - /// I/O sampling control register - pub const IOSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// G1_IO1 sampling mode - G1_IO1: u1, - /// G1_IO2 sampling mode - G1_IO2: u1, - /// G1_IO3 sampling mode - G1_IO3: u1, - /// G1_IO4 sampling mode - G1_IO4: u1, - /// G2_IO1 sampling mode - G2_IO1: u1, - /// G2_IO2 sampling mode - G2_IO2: u1, - /// G2_IO3 sampling mode - G2_IO3: u1, - /// G2_IO4 sampling mode - G2_IO4: u1, - /// G3_IO1 sampling mode - G3_IO1: u1, - /// G3_IO2 sampling mode - G3_IO2: u1, - /// G3_IO3 sampling mode - G3_IO3: u1, - /// G3_IO4 sampling mode - G3_IO4: u1, - /// G4_IO1 sampling mode - G4_IO1: u1, - /// G4_IO2 sampling mode - G4_IO2: u1, - /// G4_IO3 sampling mode - G4_IO3: u1, - /// G4_IO4 sampling mode - G4_IO4: u1, - /// G5_IO1 sampling mode - G5_IO1: u1, - /// G5_IO2 sampling mode - G5_IO2: u1, - /// G5_IO3 sampling mode - G5_IO3: u1, - /// G5_IO4 sampling mode - G5_IO4: u1, - /// G6_IO1 sampling mode - G6_IO1: u1, - /// G6_IO2 sampling mode - G6_IO2: u1, - /// G6_IO3 sampling mode - G6_IO3: u1, - /// G6_IO4 sampling mode - G6_IO4: u1, - /// G7_IO1 sampling mode - G7_IO1: u1, - /// G7_IO2 sampling mode - G7_IO2: u1, - /// G7_IO3 sampling mode - G7_IO3: u1, - /// G7_IO4 sampling mode - G7_IO4: u1, - /// G8_IO1 sampling mode - G8_IO1: u1, - /// G8_IO2 sampling mode - G8_IO2: u1, - /// G8_IO3 sampling mode - G8_IO3: u1, - /// G8_IO4 sampling mode - G8_IO4: u1, - }), base_address + 0x20); - - /// address: 0x40024028 - /// I/O channel control register - pub const IOCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// G1_IO1 channel mode - G1_IO1: u1, - /// G1_IO2 channel mode - G1_IO2: u1, - /// G1_IO3 channel mode - G1_IO3: u1, - /// G1_IO4 channel mode - G1_IO4: u1, - /// G2_IO1 channel mode - G2_IO1: u1, - /// G2_IO2 channel mode - G2_IO2: u1, - /// G2_IO3 channel mode - G2_IO3: u1, - /// G2_IO4 channel mode - G2_IO4: u1, - /// G3_IO1 channel mode - G3_IO1: u1, - /// G3_IO2 channel mode - G3_IO2: u1, - /// G3_IO3 channel mode - G3_IO3: u1, - /// G3_IO4 channel mode - G3_IO4: u1, - /// G4_IO1 channel mode - G4_IO1: u1, - /// G4_IO2 channel mode - G4_IO2: u1, - /// G4_IO3 channel mode - G4_IO3: u1, - /// G4_IO4 channel mode - G4_IO4: u1, - /// G5_IO1 channel mode - G5_IO1: u1, - /// G5_IO2 channel mode - G5_IO2: u1, - /// G5_IO3 channel mode - G5_IO3: u1, - /// G5_IO4 channel mode - G5_IO4: u1, - /// G6_IO1 channel mode - G6_IO1: u1, - /// G6_IO2 channel mode - G6_IO2: u1, - /// G6_IO3 channel mode - G6_IO3: u1, - /// G6_IO4 channel mode - G6_IO4: u1, - /// G7_IO1 channel mode - G7_IO1: u1, - /// G7_IO2 channel mode - G7_IO2: u1, - /// G7_IO3 channel mode - G7_IO3: u1, - /// G7_IO4 channel mode - G7_IO4: u1, - /// G8_IO1 channel mode - G8_IO1: u1, - /// G8_IO2 channel mode - G8_IO2: u1, - /// G8_IO3 channel mode - G8_IO3: u1, - /// G8_IO4 channel mode - G8_IO4: u1, - }), base_address + 0x28); - - /// address: 0x40024030 - /// I/O group control status - /// register - pub const IOGCSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog I/O group x enable - G1E: u1, - /// Analog I/O group x enable - G2E: u1, - /// Analog I/O group x enable - G3E: u1, - /// Analog I/O group x enable - G4E: u1, - /// Analog I/O group x enable - G5E: u1, - /// Analog I/O group x enable - G6E: u1, - /// Analog I/O group x enable - G7E: u1, - /// Analog I/O group x enable - G8E: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Analog I/O group x status - G1S: u1, - /// Analog I/O group x status - G2S: u1, - /// Analog I/O group x status - G3S: u1, - /// Analog I/O group x status - G4S: u1, - /// Analog I/O group x status - G5S: u1, - /// Analog I/O group x status - G6S: u1, - /// Analog I/O group x status - G7S: u1, - /// Analog I/O group x status - G8S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x30); - - /// address: 0x40024034 - /// I/O group x counter register - pub const IOG1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x34); - - /// address: 0x40024038 - /// I/O group x counter register - pub const IOG2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x38); - - /// address: 0x4002403c - /// I/O group x counter register - pub const IOG3CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x3c); - - /// address: 0x40024040 - /// I/O group x counter register - pub const IOG4CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x40); - - /// address: 0x40024044 - /// I/O group x counter register - pub const IOG5CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x44); - - /// address: 0x40024048 - /// I/O group x counter register - pub const IOG6CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x48); - - /// address: 0x4002404c - /// I/O group x counter register - pub const IOG7CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x4c); - - /// address: 0x40024050 - /// I/O group x counter register - pub const IOG8CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter value - CNT: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x50); - }; - /// cyclic redundancy check calculation - /// unit - pub const CRC = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023000 - /// Data register - pub const DR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40023004 - /// Independent data register - pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40023008 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// reset bit - RESET: u1, - reserved0: u1, - reserved1: u1, - /// Polynomial size - POLYSIZE: u2, - /// Reverse input data - REV_IN: u2, - /// Reverse output data - REV_OUT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x40023010 - /// Initial CRC value - pub const INIT = @intToPtr(*volatile u32, base_address + 0x10); - - /// address: 0x40023014 - /// CRC polynomial - pub const POL = @intToPtr(*volatile u32, base_address + 0x14); - }; - /// Flash - pub const Flash = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022000 - /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// LATENCY - LATENCY: u3, - reserved0: u1, - /// PRFTBE - PRFTBE: u1, - /// PRFTBS - PRFTBS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40022004 - /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flash Key - FKEYR: u32, - }), base_address + 0x4); - - /// address: 0x40022008 - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile u32, base_address + 0x8); - - /// address: 0x4002200c - /// Flash status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Busy - BSY: u1, - reserved0: u1, - /// Programming error - PGERR: u1, - reserved1: u1, - /// Write protection error - WRPRT: u1, - /// End of operation - EOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40022010 - /// Flash control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Programming - PG: u1, - /// Page erase - PER: u1, - /// Mass erase - MER: u1, - reserved0: u1, - /// Option byte programming - OPTPG: u1, - /// Option byte erase - OPTER: u1, - /// Start - STRT: u1, - /// Lock - LOCK: u1, - reserved1: u1, - /// Option bytes write enable - OPTWRE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved2: u1, - /// End of operation interrupt - /// enable - EOPIE: u1, - /// Force option byte loading - FORCE_OPTLOAD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x10); - - /// address: 0x40022014 - /// Flash address register - pub const AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flash address - FAR: u32, - }), base_address + 0x14); - - /// address: 0x4002201c - /// Option byte register - pub const OBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option byte error - OPTERR: u1, - /// Level 1 protection status - LEVEL1_PROT: u1, - /// Level 2 protection status - LEVEL2_PROT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// WDG_SW - WDG_SW: u1, - /// nRST_STOP - nRST_STOP: u1, - /// nRST_STDBY - nRST_STDBY: u1, - reserved5: u1, - /// BOOT1 - BOOT1: u1, - /// VDDA_MONITOR - VDDA_MONITOR: u1, - /// SRAM_PARITY_CHECK - SRAM_PARITY_CHECK: u1, - reserved6: u1, - /// Data0 - Data0: u8, - /// Data1 - Data1: u8, - }), base_address + 0x1c); - - /// address: 0x40022020 - /// Write protection register - pub const WRPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write protect - WRP: u32, - }), base_address + 0x20); - }; - /// Reset and clock control - pub const RCC = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021000 - /// Clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal High Speed clock - /// enable - HSION: u1, - /// Internal High Speed clock ready - /// flag - HSIRDY: u1, - reserved0: u1, - /// Internal High Speed clock - /// trimming - HSITRIM: u5, - /// Internal High Speed clock - /// Calibration - HSICAL: u8, - /// External High Speed clock - /// enable - HSEON: u1, - /// External High Speed clock ready - /// flag - HSERDY: u1, - /// External High Speed clock - /// Bypass - HSEBYP: u1, - /// Clock Security System - /// enable - CSSON: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PLL enable - PLLON: u1, - /// PLL clock ready flag - PLLRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40021004 - /// Clock configuration register - /// (RCC_CFGR) - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// System clock Switch - SW: u2, - /// System Clock Switch Status - SWS: u2, - /// AHB prescaler - HPRE: u4, - /// APB Low speed prescaler - /// (APB1) - PPRE1: u3, - /// APB high speed prescaler - /// (APB2) - PPRE2: u3, - reserved0: u1, - /// PLL entry clock source - PLLSRC: u2, - /// HSE divider for PLL entry - PLLXTPRE: u1, - /// PLL Multiplication Factor - PLLMUL: u4, - /// USB prescaler - USBPRES: u1, - /// I2S external clock source - /// selection - I2SSRC: u1, - /// Microcontroller clock - /// output - MCO: u3, - reserved1: u1, - /// Microcontroller Clock Output - /// Flag - MCOF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x4); - - /// address: 0x40021008 - /// Clock interrupt register - /// (RCC_CIR) - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSI Ready Interrupt flag - LSIRDYF: u1, - /// LSE Ready Interrupt flag - LSERDYF: u1, - /// HSI Ready Interrupt flag - HSIRDYF: u1, - /// HSE Ready Interrupt flag - HSERDYF: u1, - /// PLL Ready Interrupt flag - PLLRDYF: u1, - reserved0: u1, - reserved1: u1, - /// Clock Security System Interrupt - /// flag - CSSF: u1, - /// LSI Ready Interrupt Enable - LSIRDYIE: u1, - /// LSE Ready Interrupt Enable - LSERDYIE: u1, - /// HSI Ready Interrupt Enable - HSIRDYIE: u1, - /// HSE Ready Interrupt Enable - HSERDYIE: u1, - /// PLL Ready Interrupt Enable - PLLRDYIE: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// LSI Ready Interrupt Clear - LSIRDYC: u1, - /// LSE Ready Interrupt Clear - LSERDYC: u1, - /// HSI Ready Interrupt Clear - HSIRDYC: u1, - /// HSE Ready Interrupt Clear - HSERDYC: u1, - /// PLL Ready Interrupt Clear - PLLRDYC: u1, - reserved5: u1, - reserved6: u1, - /// Clock security system interrupt - /// clear - CSSC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4002100c - /// APB2 peripheral reset register - /// (RCC_APB2RSTR) - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// SYSCFG and COMP reset - SYSCFGRST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TIM1 timer reset - TIM1RST: u1, - /// SPI 1 reset - SPI1RST: u1, - /// TIM8 timer reset - TIM8RST: u1, - /// USART1 reset - USART1RST: u1, - reserved10: u1, - /// TIM15 timer reset - TIM15RST: u1, - /// TIM16 timer reset - TIM16RST: u1, - /// TIM17 timer reset - TIM17RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - - /// address: 0x40021010 - /// APB1 peripheral reset register - /// (RCC_APB1RSTR) - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer 2 reset - TIM2RST: u1, - /// Timer 3 reset - TIM3RST: u1, - /// Timer 14 reset - TIM4RST: u1, - reserved0: u1, - /// Timer 6 reset - TIM6RST: u1, - /// Timer 7 reset - TIM7RST: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved6: u1, - reserved7: u1, - /// SPI2 reset - SPI2RST: u1, - /// SPI3 reset - SPI3RST: u1, - reserved8: u1, - /// USART 2 reset - USART2RST: u1, - /// USART3 reset - USART3RST: u1, - /// UART 4 reset - UART4RST: u1, - /// UART 5 reset - UART5RST: u1, - /// I2C1 reset - I2C1RST: u1, - /// I2C2 reset - I2C2RST: u1, - /// USB reset - USBRST: u1, - reserved9: u1, - /// CAN reset - CANRST: u1, - reserved10: u1, - reserved11: u1, - /// Power interface reset - PWRRST: u1, - /// DAC interface reset - DACRST: u1, - /// I2C3 reset - I2C3RST: u1, - padding0: u1, - }), base_address + 0x10); - - /// address: 0x40021014 - /// AHB Peripheral Clock enable register - /// (RCC_AHBENR) - pub const AHBENR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA1 clock enable - DMAEN: u1, - /// DMA2 clock enable - DMA2EN: u1, - /// SRAM interface clock - /// enable - SRAMEN: u1, - reserved0: u1, - /// FLITF clock enable - FLITFEN: u1, - /// FMC clock enable - FMCEN: u1, - /// CRC clock enable - CRCEN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// IO port H clock enable - IOPHEN: u1, - /// I/O port A clock enable - IOPAEN: u1, - /// I/O port B clock enable - IOPBEN: u1, - /// I/O port C clock enable - IOPCEN: u1, - /// I/O port D clock enable - IOPDEN: u1, - /// I/O port E clock enable - IOPEEN: u1, - /// I/O port F clock enable - IOPFEN: u1, - /// I/O port G clock enable - IOPGEN: u1, - /// Touch sensing controller clock - /// enable - TSCEN: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// ADC1 and ADC2 clock enable - ADC12EN: u1, - /// ADC3 and ADC4 clock enable - ADC34EN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x40021018 - /// APB2 peripheral clock enable register - /// (RCC_APB2ENR) - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// SYSCFG clock enable - SYSCFGEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TIM1 Timer clock enable - TIM1EN: u1, - /// SPI 1 clock enable - SPI1EN: u1, - /// TIM8 Timer clock enable - TIM8EN: u1, - /// USART1 clock enable - USART1EN: u1, - reserved10: u1, - /// TIM15 timer clock enable - TIM15EN: u1, - /// TIM16 timer clock enable - TIM16EN: u1, - /// TIM17 timer clock enable - TIM17EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x18); - - /// address: 0x4002101c - /// APB1 peripheral clock enable register - /// (RCC_APB1ENR) - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Timer 2 clock enable - TIM2EN: u1, - /// Timer 3 clock enable - TIM3EN: u1, - /// Timer 4 clock enable - TIM4EN: u1, - reserved0: u1, - /// Timer 6 clock enable - TIM6EN: u1, - /// Timer 7 clock enable - TIM7EN: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Window watchdog clock - /// enable - WWDGEN: u1, - reserved6: u1, - reserved7: u1, - /// SPI 2 clock enable - SPI2EN: u1, - /// SPI 3 clock enable - SPI3EN: u1, - reserved8: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART 3 clock enable - USART3EN: u1, - /// USART 4 clock enable - USART4EN: u1, - /// USART 5 clock enable - USART5EN: u1, - /// I2C 1 clock enable - I2C1EN: u1, - /// I2C 2 clock enable - I2C2EN: u1, - /// USB clock enable - USBEN: u1, - reserved9: u1, - /// CAN clock enable - CANEN: u1, - /// DAC2 interface clock - /// enable - DAC2EN: u1, - reserved10: u1, - /// Power interface clock - /// enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - /// I2C3 clock enable - I2C3EN: u1, - padding0: u1, - }), base_address + 0x1c); - - /// address: 0x40021020 - /// Backup domain control register - /// (RCC_BDCR) - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// External Low Speed oscillator - /// enable - LSEON: u1, - /// External Low Speed oscillator - /// ready - LSERDY: u1, - /// External Low Speed oscillator - /// bypass - LSEBYP: u1, - /// LSE oscillator drive - /// capability - LSEDRV: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// RTC clock source selection - RTCSEL: u2, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software - /// reset - BDRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x20); - - /// address: 0x40021024 - /// Control/status register - /// (RCC_CSR) - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal low speed oscillator - /// enable - LSION: u1, - /// Internal low speed oscillator - /// ready - LSIRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Remove reset flag - RMVF: u1, - /// Option byte loader reset - /// flag - OBLRSTF: u1, - /// PIN reset flag - PINRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset - /// flag - IWDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), base_address + 0x24); - - /// address: 0x40021028 - /// AHB peripheral reset register - pub const AHBRSTR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// FMC reset - FMCRST: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// I/O port H reset - IOPHRST: u1, - /// I/O port A reset - IOPARST: u1, - /// I/O port B reset - IOPBRST: u1, - /// I/O port C reset - IOPCRST: u1, - /// I/O port D reset - IOPDRST: u1, - /// I/O port E reset - IOPERST: u1, - /// I/O port F reset - IOPFRST: u1, - /// Touch sensing controller - /// reset - IOPGRST: u1, - /// Touch sensing controller - /// reset - TSCRST: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// ADC1 and ADC2 reset - ADC12RST: u1, - /// ADC3 and ADC4 reset - ADC34RST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x28); - - /// address: 0x4002102c - /// Clock configuration register 2 - pub const CFGR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// PREDIV division factor - PREDIV: u4, - /// ADC1 and ADC2 prescaler - ADC12PRES: u5, - /// ADC3 and ADC4 prescaler - ADC34PRES: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x2c); - - /// address: 0x40021030 - /// Clock configuration register 3 - pub const CFGR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART1 clock source - /// selection - USART1SW: u2, - reserved0: u1, - reserved1: u1, - /// I2C1 clock source - /// selection - I2C1SW: u1, - /// I2C2 clock source - /// selection - I2C2SW: u1, - /// I2C3 clock source - /// selection - I2C3SW: u1, - reserved2: u1, - /// Timer1 clock source - /// selection - TIM1SW: u1, - /// Timer8 clock source - /// selection - TIM8SW: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// USART2 clock source - /// selection - USART2SW: u2, - /// USART3 clock source - /// selection - USART3SW: u2, - /// UART4 clock source - /// selection - UART4SW: u2, - /// UART5 clock source - /// selection - UART5SW: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x30); - }; - /// DMA controller 1 - pub const DMA1 = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// DMA interrupt status register - /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// flag - GIF1: u1, - /// Channel 1 Transfer Complete - /// flag - TCIF1: u1, - /// Channel 1 Half Transfer Complete - /// flag - HTIF1: u1, - /// Channel 1 Transfer Error - /// flag - TEIF1: u1, - /// Channel 2 Global interrupt - /// flag - GIF2: u1, - /// Channel 2 Transfer Complete - /// flag - TCIF2: u1, - /// Channel 2 Half Transfer Complete - /// flag - HTIF2: u1, - /// Channel 2 Transfer Error - /// flag - TEIF2: u1, - /// Channel 3 Global interrupt - /// flag - GIF3: u1, - /// Channel 3 Transfer Complete - /// flag - TCIF3: u1, - /// Channel 3 Half Transfer Complete - /// flag - HTIF3: u1, - /// Channel 3 Transfer Error - /// flag - TEIF3: u1, - /// Channel 4 Global interrupt - /// flag - GIF4: u1, - /// Channel 4 Transfer Complete - /// flag - TCIF4: u1, - /// Channel 4 Half Transfer Complete - /// flag - HTIF4: u1, - /// Channel 4 Transfer Error - /// flag - TEIF4: u1, - /// Channel 5 Global interrupt - /// flag - GIF5: u1, - /// Channel 5 Transfer Complete - /// flag - TCIF5: u1, - /// Channel 5 Half Transfer Complete - /// flag - HTIF5: u1, - /// Channel 5 Transfer Error - /// flag - TEIF5: u1, - /// Channel 6 Global interrupt - /// flag - GIF6: u1, - /// Channel 6 Transfer Complete - /// flag - TCIF6: u1, - /// Channel 6 Half Transfer Complete - /// flag - HTIF6: u1, - /// Channel 6 Transfer Error - /// flag - TEIF6: u1, - /// Channel 7 Global interrupt - /// flag - GIF7: u1, - /// Channel 7 Transfer Complete - /// flag - TCIF7: u1, - /// Channel 7 Half Transfer Complete - /// flag - HTIF7: u1, - /// Channel 7 Transfer Error - /// flag - TEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40020004 - /// DMA interrupt flag clear register - /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// clear - CGIF1: u1, - /// Channel 1 Transfer Complete - /// clear - CTCIF1: u1, - /// Channel 1 Half Transfer - /// clear - CHTIF1: u1, - /// Channel 1 Transfer Error - /// clear - CTEIF1: u1, - /// Channel 2 Global interrupt - /// clear - CGIF2: u1, - /// Channel 2 Transfer Complete - /// clear - CTCIF2: u1, - /// Channel 2 Half Transfer - /// clear - CHTIF2: u1, - /// Channel 2 Transfer Error - /// clear - CTEIF2: u1, - /// Channel 3 Global interrupt - /// clear - CGIF3: u1, - /// Channel 3 Transfer Complete - /// clear - CTCIF3: u1, - /// Channel 3 Half Transfer - /// clear - CHTIF3: u1, - /// Channel 3 Transfer Error - /// clear - CTEIF3: u1, - /// Channel 4 Global interrupt - /// clear - CGIF4: u1, - /// Channel 4 Transfer Complete - /// clear - CTCIF4: u1, - /// Channel 4 Half Transfer - /// clear - CHTIF4: u1, - /// Channel 4 Transfer Error - /// clear - CTEIF4: u1, - /// Channel 5 Global interrupt - /// clear - CGIF5: u1, - /// Channel 5 Transfer Complete - /// clear - CTCIF5: u1, - /// Channel 5 Half Transfer - /// clear - CHTIF5: u1, - /// Channel 5 Transfer Error - /// clear - CTEIF5: u1, - /// Channel 6 Global interrupt - /// clear - CGIF6: u1, - /// Channel 6 Transfer Complete - /// clear - CTCIF6: u1, - /// Channel 6 Half Transfer - /// clear - CHTIF6: u1, - /// Channel 6 Transfer Error - /// clear - CTEIF6: u1, - /// Channel 7 Global interrupt - /// clear - CGIF7: u1, - /// Channel 7 Transfer Complete - /// clear - CTCIF7: u1, - /// Channel 7 Half Transfer - /// clear - CHTIF7: u1, - /// Channel 7 Transfer Error - /// clear - CTEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002000c - /// DMA channel 1 number of data - /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020010 - /// DMA channel 1 peripheral address - /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x10); - - /// address: 0x40020014 - /// DMA channel 1 memory address - /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x14); - - /// address: 0x4002001c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// DMA channel 2 number of data - /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020024 - /// DMA channel 2 peripheral address - /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x24); - - /// address: 0x40020028 - /// DMA channel 2 memory address - /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x28); - - /// address: 0x40020030 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020034 - /// DMA channel 3 number of data - /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020038 - /// DMA channel 3 peripheral address - /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x38); - - /// address: 0x4002003c - /// DMA channel 3 memory address - /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x3c); - - /// address: 0x40020044 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020048 - /// DMA channel 4 number of data - /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002004c - /// DMA channel 4 peripheral address - /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x4c); - - /// address: 0x40020050 - /// DMA channel 4 memory address - /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x50); - - /// address: 0x40020058 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002005c - /// DMA channel 5 number of data - /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020060 - /// DMA channel 5 peripheral address - /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40020064 - /// DMA channel 5 memory address - /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x64); - - /// address: 0x4002006c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x6c); - - /// address: 0x40020070 - /// DMA channel 6 number of data - /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40020074 - /// DMA channel 6 peripheral address - /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x74); - - /// address: 0x40020078 - /// DMA channel 6 memory address - /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x78); - - /// address: 0x40020080 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40020084 - /// DMA channel 7 number of data - /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40020088 - /// DMA channel 7 peripheral address - /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x88); - - /// address: 0x4002008c - /// DMA channel 7 memory address - /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x8c); - }; - pub const DMA2 = struct { - pub const base_address = 0x40020400; - - /// address: 0x40020400 - /// DMA interrupt status register - /// (DMA_ISR) - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// flag - GIF1: u1, - /// Channel 1 Transfer Complete - /// flag - TCIF1: u1, - /// Channel 1 Half Transfer Complete - /// flag - HTIF1: u1, - /// Channel 1 Transfer Error - /// flag - TEIF1: u1, - /// Channel 2 Global interrupt - /// flag - GIF2: u1, - /// Channel 2 Transfer Complete - /// flag - TCIF2: u1, - /// Channel 2 Half Transfer Complete - /// flag - HTIF2: u1, - /// Channel 2 Transfer Error - /// flag - TEIF2: u1, - /// Channel 3 Global interrupt - /// flag - GIF3: u1, - /// Channel 3 Transfer Complete - /// flag - TCIF3: u1, - /// Channel 3 Half Transfer Complete - /// flag - HTIF3: u1, - /// Channel 3 Transfer Error - /// flag - TEIF3: u1, - /// Channel 4 Global interrupt - /// flag - GIF4: u1, - /// Channel 4 Transfer Complete - /// flag - TCIF4: u1, - /// Channel 4 Half Transfer Complete - /// flag - HTIF4: u1, - /// Channel 4 Transfer Error - /// flag - TEIF4: u1, - /// Channel 5 Global interrupt - /// flag - GIF5: u1, - /// Channel 5 Transfer Complete - /// flag - TCIF5: u1, - /// Channel 5 Half Transfer Complete - /// flag - HTIF5: u1, - /// Channel 5 Transfer Error - /// flag - TEIF5: u1, - /// Channel 6 Global interrupt - /// flag - GIF6: u1, - /// Channel 6 Transfer Complete - /// flag - TCIF6: u1, - /// Channel 6 Half Transfer Complete - /// flag - HTIF6: u1, - /// Channel 6 Transfer Error - /// flag - TEIF6: u1, - /// Channel 7 Global interrupt - /// flag - GIF7: u1, - /// Channel 7 Transfer Complete - /// flag - TCIF7: u1, - /// Channel 7 Half Transfer Complete - /// flag - HTIF7: u1, - /// Channel 7 Transfer Error - /// flag - TEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40020404 - /// DMA interrupt flag clear register - /// (DMA_IFCR) - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel 1 Global interrupt - /// clear - CGIF1: u1, - /// Channel 1 Transfer Complete - /// clear - CTCIF1: u1, - /// Channel 1 Half Transfer - /// clear - CHTIF1: u1, - /// Channel 1 Transfer Error - /// clear - CTEIF1: u1, - /// Channel 2 Global interrupt - /// clear - CGIF2: u1, - /// Channel 2 Transfer Complete - /// clear - CTCIF2: u1, - /// Channel 2 Half Transfer - /// clear - CHTIF2: u1, - /// Channel 2 Transfer Error - /// clear - CTEIF2: u1, - /// Channel 3 Global interrupt - /// clear - CGIF3: u1, - /// Channel 3 Transfer Complete - /// clear - CTCIF3: u1, - /// Channel 3 Half Transfer - /// clear - CHTIF3: u1, - /// Channel 3 Transfer Error - /// clear - CTEIF3: u1, - /// Channel 4 Global interrupt - /// clear - CGIF4: u1, - /// Channel 4 Transfer Complete - /// clear - CTCIF4: u1, - /// Channel 4 Half Transfer - /// clear - CHTIF4: u1, - /// Channel 4 Transfer Error - /// clear - CTEIF4: u1, - /// Channel 5 Global interrupt - /// clear - CGIF5: u1, - /// Channel 5 Transfer Complete - /// clear - CTCIF5: u1, - /// Channel 5 Half Transfer - /// clear - CHTIF5: u1, - /// Channel 5 Transfer Error - /// clear - CTEIF5: u1, - /// Channel 6 Global interrupt - /// clear - CGIF6: u1, - /// Channel 6 Transfer Complete - /// clear - CTCIF6: u1, - /// Channel 6 Half Transfer - /// clear - CHTIF6: u1, - /// Channel 6 Transfer Error - /// clear - CTEIF6: u1, - /// Channel 7 Global interrupt - /// clear - CGIF7: u1, - /// Channel 7 Transfer Complete - /// clear - CTCIF7: u1, - /// Channel 7 Half Transfer - /// clear - CHTIF7: u1, - /// Channel 7 Transfer Error - /// clear - CTEIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40020408 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x8); - - /// address: 0x4002040c - /// DMA channel 1 number of data - /// register - pub const CNDTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40020410 - /// DMA channel 1 peripheral address - /// register - pub const CPAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x10); - - /// address: 0x40020414 - /// DMA channel 1 memory address - /// register - pub const CMAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x14); - - /// address: 0x4002041c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x1c); - - /// address: 0x40020420 - /// DMA channel 2 number of data - /// register - pub const CNDTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40020424 - /// DMA channel 2 peripheral address - /// register - pub const CPAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x24); - - /// address: 0x40020428 - /// DMA channel 2 memory address - /// register - pub const CMAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x28); - - /// address: 0x40020430 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x30); - - /// address: 0x40020434 - /// DMA channel 3 number of data - /// register - pub const CNDTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40020438 - /// DMA channel 3 peripheral address - /// register - pub const CPAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x38); - - /// address: 0x4002043c - /// DMA channel 3 memory address - /// register - pub const CMAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x3c); - - /// address: 0x40020444 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x44); - - /// address: 0x40020448 - /// DMA channel 4 number of data - /// register - pub const CNDTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002044c - /// DMA channel 4 peripheral address - /// register - pub const CPAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x4c); - - /// address: 0x40020450 - /// DMA channel 4 memory address - /// register - pub const CMAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x50); - - /// address: 0x40020458 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x58); - - /// address: 0x4002045c - /// DMA channel 5 number of data - /// register - pub const CNDTR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40020460 - /// DMA channel 5 peripheral address - /// register - pub const CPAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40020464 - /// DMA channel 5 memory address - /// register - pub const CMAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x64); - - /// address: 0x4002046c - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x6c); - - /// address: 0x40020470 - /// DMA channel 6 number of data - /// register - pub const CNDTR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x70); - - /// address: 0x40020474 - /// DMA channel 6 peripheral address - /// register - pub const CPAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x74); - - /// address: 0x40020478 - /// DMA channel 6 memory address - /// register - pub const CMAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x78); - - /// address: 0x40020480 - /// DMA channel configuration register - /// (DMA_CCR) - pub const CCR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel enable - EN: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Half Transfer interrupt - /// enable - HTIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Data transfer direction - DIR: u1, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral size - PSIZE: u2, - /// Memory size - MSIZE: u2, - /// Channel Priority level - PL: u2, - /// Memory to memory mode - MEM2MEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40020484 - /// DMA channel 7 number of data - /// register - pub const CNDTR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data to transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x40020488 - /// DMA channel 7 peripheral address - /// register - pub const CPAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x88); - - /// address: 0x4002048c - /// DMA channel 7 memory address - /// register - pub const CMAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x8c); - }; - /// General purpose timer - pub const TIM2 = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit3 - SMS_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - /// Output compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40000018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - /// Output compare 3 mode bit3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 4 mode bit3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x4000001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNTL: u16, - /// High counter value - CNTH: u15, - /// if IUFREMAP=0 than CNT with read write - /// access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40000028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARRL: u16, - /// High Auto-reload value - ARRH: u16, - }), base_address + 0x2c); - - /// address: 0x40000034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1L: u16, - /// High Capture/Compare 1 value (on - /// TIM2) - CCR1H: u16, - }), base_address + 0x34); - - /// address: 0x40000038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2L: u16, - /// High Capture/Compare 2 value (on - /// TIM2) - CCR2H: u16, - }), base_address + 0x38); - - /// address: 0x4000003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR3H: u16, - }), base_address + 0x3c); - - /// address: 0x40000040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR4H: u16, - }), base_address + 0x40); - - /// address: 0x40000048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM3 = struct { - pub const base_address = 0x40000400; - - /// address: 0x40000400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40000404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit3 - SMS_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4000040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - /// Output compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40000418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - /// Output compare 3 mode bit3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 4 mode bit3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x4000041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNTL: u16, - /// High counter value - CNTH: u15, - /// if IUFREMAP=0 than CNT with read write - /// access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40000428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARRL: u16, - /// High Auto-reload value - ARRH: u16, - }), base_address + 0x2c); - - /// address: 0x40000434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1L: u16, - /// High Capture/Compare 1 value (on - /// TIM2) - CCR1H: u16, - }), base_address + 0x34); - - /// address: 0x40000438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2L: u16, - /// High Capture/Compare 2 value (on - /// TIM2) - CCR2H: u16, - }), base_address + 0x38); - - /// address: 0x4000043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR3H: u16, - }), base_address + 0x3c); - - /// address: 0x40000440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR4H: u16, - }), base_address + 0x40); - - /// address: 0x40000448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM4 = struct { - pub const base_address = 0x40000800; - - /// address: 0x40000800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40000804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit3 - SMS_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4000080c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output compare 1 fast - /// enable - OC1FE: u1, - /// Output compare 1 preload - /// enable - OC1PE: u1, - /// Output compare 1 mode - OC1M: u3, - /// Output compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output compare 2 fast - /// enable - OC2FE: u1, - /// Output compare 2 preload - /// enable - OC2PE: u1, - /// Output compare 2 mode - OC2M: u3, - /// Output compare 2 clear - /// enable - OC2CE: u1, - /// Output compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40000818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000081c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - O24CE: u1, - /// Output compare 3 mode bit3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output compare 4 mode bit3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x4000081c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 3 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000824 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNTL: u16, - /// High counter value - CNTH: u15, - /// if IUFREMAP=0 than CNT with read write - /// access else UIFCPY with read only - /// access - CNT_or_UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40000828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000082c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARRL: u16, - /// High Auto-reload value - ARRH: u16, - }), base_address + 0x2c); - - /// address: 0x40000834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1L: u16, - /// High Capture/Compare 1 value (on - /// TIM2) - CCR1H: u16, - }), base_address + 0x34); - - /// address: 0x40000838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2L: u16, - /// High Capture/Compare 2 value (on - /// TIM2) - CCR2H: u16, - }), base_address + 0x38); - - /// address: 0x4000083c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR3H: u16, - }), base_address + 0x3c); - - /// address: 0x40000840 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4L: u16, - /// High Capture/Compare value (on - /// TIM2) - CCR4H: u16, - }), base_address + 0x40); - - /// address: 0x40000848 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000084c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - /// General purpose timers - pub const TIM15 = struct { - pub const base_address = 0x40014000; - - /// address: 0x40014000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved3: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40014004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x40014008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Slave mode selection bit 3 - SMS_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4001400c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - reserved2: u1, - reserved3: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40014010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40014014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40014018 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - reserved1: u1, - /// Output Compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Output Compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40014018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PSC: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40014020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved0: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40014024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40014028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001402c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014030 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40014034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x40014044 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x44); - - /// address: 0x40014048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001404c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - /// General-purpose-timers - pub const TIM16 = struct { - pub const base_address = 0x40014400; - - /// address: 0x40014400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved3: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40014404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x4001440c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40014410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved3: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40014418 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Output Compare 1 mode - OC1M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - - /// address: 0x40014418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF Copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40014428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001442c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014430 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40014434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014444 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x44); - - /// address: 0x40014448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001444c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40014450 - /// option register - pub const OR = @intToPtr(*volatile u32, base_address + 0x50); - }; - /// General purpose timer - pub const TIM17 = struct { - pub const base_address = 0x40014800; - - /// address: 0x40014800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved3: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40014804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x4001480c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40014810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved3: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40014818 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Output Compare 1 mode - OC1M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x18); - - /// address: 0x40014818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PSC: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014824 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF Copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40014828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001482c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014830 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40014834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014844 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x44); - - /// address: 0x40014848 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001484c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - /// Universal synchronous asynchronous receiver - /// transmitter - pub const USART1 = struct { - pub const base_address = 0x40013800; - - /// address: 0x40013800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: u1, - /// Word length - M: u1, - /// Mute mode enable - MME: u1, - /// Character match interrupt - /// enable - CMIE: u1, - /// Oversampling mode - OVER8: u1, - /// Driver Enable deassertion - /// time - DEDT: u5, - /// Driver Enable assertion - /// time - DEAT: u5, - /// Receiver timeout interrupt - /// enable - RTOIE: u1, - /// End of Block interrupt - /// enable - EOBIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40013804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// 7-bit Address Detection/4-bit Address - /// Detection - ADDM7: u1, - /// LIN break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved4: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level - /// inversion - RXINV: u1, - /// TX pin active level - /// inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: u1, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: u2, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD0: u4, - /// Address of the USART node - ADD4: u4, - }), base_address + 0x4); - - /// address: 0x40013808 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception - /// Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity - /// selection - DEP: u1, - reserved0: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag - /// selection - WUS: u2, - /// Wakeup from Stop mode interrupt - /// enable - WUFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x4001380c - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40013810 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013814 - /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), base_address + 0x14); - - /// address: 0x40013818 - /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto baud rate request - ABRRQ: u1, - /// Send break request - SBKRQ: u1, - /// Mute mode request - MMRQ: u1, - /// Receive data flush request - RXFRQ: u1, - /// Transmit data flush - /// request - TXFRQ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x18); - - /// address: 0x4001381c - /// Interrupt & status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved0: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute - /// mode - RWU: u1, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge - /// flag - TEACK: u1, - /// Receive enable acknowledge - /// flag - REACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x1c); - - /// address: 0x40013820 - /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error clear flag - PECF: u1, - /// Framing error clear flag - FECF: u1, - /// Noise detected clear flag - NCF: u1, - /// Overrun error clear flag - ORECF: u1, - /// Idle line detected clear - /// flag - IDLECF: u1, - reserved0: u1, - /// Transmission complete clear - /// flag - TCCF: u1, - reserved1: u1, - /// LIN break detection clear - /// flag - LBDCF: u1, - /// CTS clear flag - CTSCF: u1, - reserved2: u1, - /// Receiver timeout clear - /// flag - RTOCF: u1, - /// End of timeout clear flag - EOBCF: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Character match clear flag - CMCF: u1, - reserved7: u1, - reserved8: u1, - /// Wakeup from Stop mode clear - /// flag - WUCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40013824 - /// Receive data register - pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); - - /// address: 0x40013828 - /// Transmit data register - pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); - }; - pub const USART2 = struct { - pub const base_address = 0x40004400; - - /// address: 0x40004400 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: u1, - /// Word length - M: u1, - /// Mute mode enable - MME: u1, - /// Character match interrupt - /// enable - CMIE: u1, - /// Oversampling mode - OVER8: u1, - /// Driver Enable deassertion - /// time - DEDT: u5, - /// Driver Enable assertion - /// time - DEAT: u5, - /// Receiver timeout interrupt - /// enable - RTOIE: u1, - /// End of Block interrupt - /// enable - EOBIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40004404 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// 7-bit Address Detection/4-bit Address - /// Detection - ADDM7: u1, - /// LIN break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved4: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level - /// inversion - RXINV: u1, - /// TX pin active level - /// inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: u1, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: u2, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD0: u4, - /// Address of the USART node - ADD4: u4, - }), base_address + 0x4); - - /// address: 0x40004408 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception - /// Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity - /// selection - DEP: u1, - reserved0: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag - /// selection - WUS: u2, - /// Wakeup from Stop mode interrupt - /// enable - WUFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x4000440c - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004410 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004414 - /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), base_address + 0x14); - - /// address: 0x40004418 - /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto baud rate request - ABRRQ: u1, - /// Send break request - SBKRQ: u1, - /// Mute mode request - MMRQ: u1, - /// Receive data flush request - RXFRQ: u1, - /// Transmit data flush - /// request - TXFRQ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x18); - - /// address: 0x4000441c - /// Interrupt & status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved0: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute - /// mode - RWU: u1, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge - /// flag - TEACK: u1, - /// Receive enable acknowledge - /// flag - REACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x1c); - - /// address: 0x40004420 - /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error clear flag - PECF: u1, - /// Framing error clear flag - FECF: u1, - /// Noise detected clear flag - NCF: u1, - /// Overrun error clear flag - ORECF: u1, - /// Idle line detected clear - /// flag - IDLECF: u1, - reserved0: u1, - /// Transmission complete clear - /// flag - TCCF: u1, - reserved1: u1, - /// LIN break detection clear - /// flag - LBDCF: u1, - /// CTS clear flag - CTSCF: u1, - reserved2: u1, - /// Receiver timeout clear - /// flag - RTOCF: u1, - /// End of timeout clear flag - EOBCF: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Character match clear flag - CMCF: u1, - reserved7: u1, - reserved8: u1, - /// Wakeup from Stop mode clear - /// flag - WUCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40004424 - /// Receive data register - pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); - - /// address: 0x40004428 - /// Transmit data register - pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); - }; - pub const USART3 = struct { - pub const base_address = 0x40004800; - - /// address: 0x40004800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: u1, - /// Word length - M: u1, - /// Mute mode enable - MME: u1, - /// Character match interrupt - /// enable - CMIE: u1, - /// Oversampling mode - OVER8: u1, - /// Driver Enable deassertion - /// time - DEDT: u5, - /// Driver Enable assertion - /// time - DEAT: u5, - /// Receiver timeout interrupt - /// enable - RTOIE: u1, - /// End of Block interrupt - /// enable - EOBIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40004804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// 7-bit Address Detection/4-bit Address - /// Detection - ADDM7: u1, - /// LIN break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved4: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level - /// inversion - RXINV: u1, - /// TX pin active level - /// inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: u1, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: u2, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD0: u4, - /// Address of the USART node - ADD4: u4, - }), base_address + 0x4); - - /// address: 0x40004808 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception - /// Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity - /// selection - DEP: u1, - reserved0: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag - /// selection - WUS: u2, - /// Wakeup from Stop mode interrupt - /// enable - WUFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x4000480c - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004810 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004814 - /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), base_address + 0x14); - - /// address: 0x40004818 - /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto baud rate request - ABRRQ: u1, - /// Send break request - SBKRQ: u1, - /// Mute mode request - MMRQ: u1, - /// Receive data flush request - RXFRQ: u1, - /// Transmit data flush - /// request - TXFRQ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x18); - - /// address: 0x4000481c - /// Interrupt & status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved0: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute - /// mode - RWU: u1, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge - /// flag - TEACK: u1, - /// Receive enable acknowledge - /// flag - REACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x1c); - - /// address: 0x40004820 - /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error clear flag - PECF: u1, - /// Framing error clear flag - FECF: u1, - /// Noise detected clear flag - NCF: u1, - /// Overrun error clear flag - ORECF: u1, - /// Idle line detected clear - /// flag - IDLECF: u1, - reserved0: u1, - /// Transmission complete clear - /// flag - TCCF: u1, - reserved1: u1, - /// LIN break detection clear - /// flag - LBDCF: u1, - /// CTS clear flag - CTSCF: u1, - reserved2: u1, - /// Receiver timeout clear - /// flag - RTOCF: u1, - /// End of timeout clear flag - EOBCF: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Character match clear flag - CMCF: u1, - reserved7: u1, - reserved8: u1, - /// Wakeup from Stop mode clear - /// flag - WUCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40004824 - /// Receive data register - pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); - - /// address: 0x40004828 - /// Transmit data register - pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); - }; - pub const UART4 = struct { - pub const base_address = 0x40004c00; - - /// address: 0x40004c00 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: u1, - /// Word length - M: u1, - /// Mute mode enable - MME: u1, - /// Character match interrupt - /// enable - CMIE: u1, - /// Oversampling mode - OVER8: u1, - /// Driver Enable deassertion - /// time - DEDT: u5, - /// Driver Enable assertion - /// time - DEAT: u5, - /// Receiver timeout interrupt - /// enable - RTOIE: u1, - /// End of Block interrupt - /// enable - EOBIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40004c04 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// 7-bit Address Detection/4-bit Address - /// Detection - ADDM7: u1, - /// LIN break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved4: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level - /// inversion - RXINV: u1, - /// TX pin active level - /// inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: u1, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: u2, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD0: u4, - /// Address of the USART node - ADD4: u4, - }), base_address + 0x4); - - /// address: 0x40004c08 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception - /// Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity - /// selection - DEP: u1, - reserved0: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag - /// selection - WUS: u2, - /// Wakeup from Stop mode interrupt - /// enable - WUFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x40004c0c - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004c10 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004c14 - /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), base_address + 0x14); - - /// address: 0x40004c18 - /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto baud rate request - ABRRQ: u1, - /// Send break request - SBKRQ: u1, - /// Mute mode request - MMRQ: u1, - /// Receive data flush request - RXFRQ: u1, - /// Transmit data flush - /// request - TXFRQ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x18); - - /// address: 0x40004c1c - /// Interrupt & status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved0: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute - /// mode - RWU: u1, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge - /// flag - TEACK: u1, - /// Receive enable acknowledge - /// flag - REACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x1c); - - /// address: 0x40004c20 - /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error clear flag - PECF: u1, - /// Framing error clear flag - FECF: u1, - /// Noise detected clear flag - NCF: u1, - /// Overrun error clear flag - ORECF: u1, - /// Idle line detected clear - /// flag - IDLECF: u1, - reserved0: u1, - /// Transmission complete clear - /// flag - TCCF: u1, - reserved1: u1, - /// LIN break detection clear - /// flag - LBDCF: u1, - /// CTS clear flag - CTSCF: u1, - reserved2: u1, - /// Receiver timeout clear - /// flag - RTOCF: u1, - /// End of timeout clear flag - EOBCF: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Character match clear flag - CMCF: u1, - reserved7: u1, - reserved8: u1, - /// Wakeup from Stop mode clear - /// flag - WUCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40004c24 - /// Receive data register - pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); - - /// address: 0x40004c28 - /// Transmit data register - pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); - }; - pub const UART5 = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// USART enable - UE: u1, - /// USART enable in Stop mode - UESM: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Receiver wakeup method - WAKE: u1, - /// Word length - M: u1, - /// Mute mode enable - MME: u1, - /// Character match interrupt - /// enable - CMIE: u1, - /// Oversampling mode - OVER8: u1, - /// Driver Enable deassertion - /// time - DEDT: u5, - /// Driver Enable assertion - /// time - DEAT: u5, - /// Receiver timeout interrupt - /// enable - RTOIE: u1, - /// End of Block interrupt - /// enable - EOBIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// 7-bit Address Detection/4-bit Address - /// Detection - ADDM7: u1, - /// LIN break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved4: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - /// Swap TX/RX pins - SWAP: u1, - /// RX pin active level - /// inversion - RXINV: u1, - /// TX pin active level - /// inversion - TXINV: u1, - /// Binary data inversion - DATAINV: u1, - /// Most significant bit first - MSBFIRST: u1, - /// Auto baud rate enable - ABREN: u1, - /// Auto baud rate mode - ABRMOD: u2, - /// Receiver timeout enable - RTOEN: u1, - /// Address of the USART node - ADD0: u4, - /// Address of the USART node - ADD4: u4, - }), base_address + 0x4); - - /// address: 0x40005008 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - /// Overrun Disable - OVRDIS: u1, - /// DMA Disable on Reception - /// Error - DDRE: u1, - /// Driver enable mode - DEM: u1, - /// Driver enable polarity - /// selection - DEP: u1, - reserved0: u1, - /// Smartcard auto-retry count - SCARCNT: u3, - /// Wakeup from Stop mode interrupt flag - /// selection - WUS: u2, - /// Wakeup from Stop mode interrupt - /// enable - WUFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x4000500c - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005010 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40005014 - /// Receiver timeout register - pub const RTOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receiver timeout value - RTO: u24, - /// Block Length - BLEN: u8, - }), base_address + 0x14); - - /// address: 0x40005018 - /// Request register - pub const RQR = @intToPtr(*volatile Mmio(32, packed struct { - /// Auto baud rate request - ABRRQ: u1, - /// Send break request - SBKRQ: u1, - /// Mute mode request - MMRQ: u1, - /// Receive data flush request - RXFRQ: u1, - /// Transmit data flush - /// request - TXFRQ: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x18); - - /// address: 0x4000501c - /// Interrupt & status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// Idle line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS interrupt flag - CTSIF: u1, - /// CTS flag - CTS: u1, - /// Receiver timeout - RTOF: u1, - /// End of block flag - EOBF: u1, - reserved0: u1, - /// Auto baud rate error - ABRE: u1, - /// Auto baud rate flag - ABRF: u1, - /// Busy flag - BUSY: u1, - /// character match flag - CMF: u1, - /// Send break flag - SBKF: u1, - /// Receiver wakeup from Mute - /// mode - RWU: u1, - /// Wakeup from Stop mode flag - WUF: u1, - /// Transmit enable acknowledge - /// flag - TEACK: u1, - /// Receive enable acknowledge - /// flag - REACK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x1c); - - /// address: 0x40005020 - /// Interrupt flag clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error clear flag - PECF: u1, - /// Framing error clear flag - FECF: u1, - /// Noise detected clear flag - NCF: u1, - /// Overrun error clear flag - ORECF: u1, - /// Idle line detected clear - /// flag - IDLECF: u1, - reserved0: u1, - /// Transmission complete clear - /// flag - TCCF: u1, - reserved1: u1, - /// LIN break detection clear - /// flag - LBDCF: u1, - /// CTS clear flag - CTSCF: u1, - reserved2: u1, - /// Receiver timeout clear - /// flag - RTOCF: u1, - /// End of timeout clear flag - EOBCF: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Character match clear flag - CMCF: u1, - reserved7: u1, - reserved8: u1, - /// Wakeup from Stop mode clear - /// flag - WUCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40005024 - /// Receive data register - pub const RDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x24); - - /// address: 0x40005028 - /// Transmit data register - pub const TDR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x28); - }; - /// Serial peripheral interface/Inter-IC - /// sound - pub const SPI1 = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40013008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x4001300c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001301c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI2 = struct { - pub const base_address = 0x40003800; - - /// address: 0x40003800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40003808 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x4000380c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003810 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003818 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000381c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003820 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI3 = struct { - pub const base_address = 0x40003c00; - - /// address: 0x40003c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40003c08 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x40003c0c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003c10 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003c14 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003c18 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40003c1c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003c20 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S2ext = struct { - pub const base_address = 0x40003400; - - /// address: 0x40003400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40003408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x4000340c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000341c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S3ext = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40004004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40004008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x4000400c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40004010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40004018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000401c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40004020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI4 = struct { - pub const base_address = 0x40013c00; - - /// address: 0x40013c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// CRC length - CRCL: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - /// NSS pulse management - NSSP: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - /// Data size - DS: u4, - /// FIFO reception threshold - FRXTH: u1, - /// Last DMA transfer for - /// reception - LDMA_RX: u1, - /// Last DMA transfer for - /// transmission - LDMA_TX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40013c08 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - /// FIFO reception level - FRLVL: u2, - /// FIFO transmission level - FTLVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x8); - - /// address: 0x40013c0c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013c10 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013c14 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013c18 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40013c1c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013c20 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - /// External interrupt/event - /// controller - pub const EXTI = struct { - pub const base_address = 0x40010400; - - /// address: 0x40010400 - /// Interrupt mask register - pub const IMR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1, - /// Interrupt Mask on line 1 - MR1: u1, - /// Interrupt Mask on line 2 - MR2: u1, - /// Interrupt Mask on line 3 - MR3: u1, - /// Interrupt Mask on line 4 - MR4: u1, - /// Interrupt Mask on line 5 - MR5: u1, - /// Interrupt Mask on line 6 - MR6: u1, - /// Interrupt Mask on line 7 - MR7: u1, - /// Interrupt Mask on line 8 - MR8: u1, - /// Interrupt Mask on line 9 - MR9: u1, - /// Interrupt Mask on line 10 - MR10: u1, - /// Interrupt Mask on line 11 - MR11: u1, - /// Interrupt Mask on line 12 - MR12: u1, - /// Interrupt Mask on line 13 - MR13: u1, - /// Interrupt Mask on line 14 - MR14: u1, - /// Interrupt Mask on line 15 - MR15: u1, - /// Interrupt Mask on line 16 - MR16: u1, - /// Interrupt Mask on line 17 - MR17: u1, - /// Interrupt Mask on line 18 - MR18: u1, - /// Interrupt Mask on line 19 - MR19: u1, - /// Interrupt Mask on line 20 - MR20: u1, - /// Interrupt Mask on line 21 - MR21: u1, - /// Interrupt Mask on line 22 - MR22: u1, - /// Interrupt Mask on line 23 - MR23: u1, - /// Interrupt Mask on line 24 - MR24: u1, - /// Interrupt Mask on line 25 - MR25: u1, - /// Interrupt Mask on line 26 - MR26: u1, - /// Interrupt Mask on line 27 - MR27: u1, - /// Interrupt Mask on line 28 - MR28: u1, - /// Interrupt Mask on line 29 - MR29: u1, - /// Interrupt Mask on line 30 - MR30: u1, - /// Interrupt Mask on line 31 - MR31: u1, - }), base_address + 0x0); - - /// address: 0x40010404 - /// Event mask register - pub const EMR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Event Mask on line 0 - MR0: u1, - /// Event Mask on line 1 - MR1: u1, - /// Event Mask on line 2 - MR2: u1, - /// Event Mask on line 3 - MR3: u1, - /// Event Mask on line 4 - MR4: u1, - /// Event Mask on line 5 - MR5: u1, - /// Event Mask on line 6 - MR6: u1, - /// Event Mask on line 7 - MR7: u1, - /// Event Mask on line 8 - MR8: u1, - /// Event Mask on line 9 - MR9: u1, - /// Event Mask on line 10 - MR10: u1, - /// Event Mask on line 11 - MR11: u1, - /// Event Mask on line 12 - MR12: u1, - /// Event Mask on line 13 - MR13: u1, - /// Event Mask on line 14 - MR14: u1, - /// Event Mask on line 15 - MR15: u1, - /// Event Mask on line 16 - MR16: u1, - /// Event Mask on line 17 - MR17: u1, - /// Event Mask on line 18 - MR18: u1, - /// Event Mask on line 19 - MR19: u1, - /// Event Mask on line 20 - MR20: u1, - /// Event Mask on line 21 - MR21: u1, - /// Event Mask on line 22 - MR22: u1, - /// Event Mask on line 23 - MR23: u1, - /// Event Mask on line 24 - MR24: u1, - /// Event Mask on line 25 - MR25: u1, - /// Event Mask on line 26 - MR26: u1, - /// Event Mask on line 27 - MR27: u1, - /// Event Mask on line 28 - MR28: u1, - /// Event Mask on line 29 - MR29: u1, - /// Event Mask on line 30 - MR30: u1, - /// Event Mask on line 31 - MR31: u1, - }), base_address + 0x4); - - /// address: 0x40010408 - /// Rising Trigger selection - /// register - pub const RTSR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising trigger event configuration of - /// line 0 - TR0: u1, - /// Rising trigger event configuration of - /// line 1 - TR1: u1, - /// Rising trigger event configuration of - /// line 2 - TR2: u1, - /// Rising trigger event configuration of - /// line 3 - TR3: u1, - /// Rising trigger event configuration of - /// line 4 - TR4: u1, - /// Rising trigger event configuration of - /// line 5 - TR5: u1, - /// Rising trigger event configuration of - /// line 6 - TR6: u1, - /// Rising trigger event configuration of - /// line 7 - TR7: u1, - /// Rising trigger event configuration of - /// line 8 - TR8: u1, - /// Rising trigger event configuration of - /// line 9 - TR9: u1, - /// Rising trigger event configuration of - /// line 10 - TR10: u1, - /// Rising trigger event configuration of - /// line 11 - TR11: u1, - /// Rising trigger event configuration of - /// line 12 - TR12: u1, - /// Rising trigger event configuration of - /// line 13 - TR13: u1, - /// Rising trigger event configuration of - /// line 14 - TR14: u1, - /// Rising trigger event configuration of - /// line 15 - TR15: u1, - /// Rising trigger event configuration of - /// line 16 - TR16: u1, - /// Rising trigger event configuration of - /// line 17 - TR17: u1, - /// Rising trigger event configuration of - /// line 18 - TR18: u1, - /// Rising trigger event configuration of - /// line 19 - TR19: u1, - /// Rising trigger event configuration of - /// line 20 - TR20: u1, - /// Rising trigger event configuration of - /// line 21 - TR21: u1, - /// Rising trigger event configuration of - /// line 22 - TR22: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Rising trigger event configuration of - /// line 29 - TR29: u1, - /// Rising trigger event configuration of - /// line 30 - TR30: u1, - /// Rising trigger event configuration of - /// line 31 - TR31: u1, - }), base_address + 0x8); - - /// address: 0x4001040c - /// Falling Trigger selection - /// register - pub const FTSR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling trigger event configuration of - /// line 0 - TR0: u1, - /// Falling trigger event configuration of - /// line 1 - TR1: u1, - /// Falling trigger event configuration of - /// line 2 - TR2: u1, - /// Falling trigger event configuration of - /// line 3 - TR3: u1, - /// Falling trigger event configuration of - /// line 4 - TR4: u1, - /// Falling trigger event configuration of - /// line 5 - TR5: u1, - /// Falling trigger event configuration of - /// line 6 - TR6: u1, - /// Falling trigger event configuration of - /// line 7 - TR7: u1, - /// Falling trigger event configuration of - /// line 8 - TR8: u1, - /// Falling trigger event configuration of - /// line 9 - TR9: u1, - /// Falling trigger event configuration of - /// line 10 - TR10: u1, - /// Falling trigger event configuration of - /// line 11 - TR11: u1, - /// Falling trigger event configuration of - /// line 12 - TR12: u1, - /// Falling trigger event configuration of - /// line 13 - TR13: u1, - /// Falling trigger event configuration of - /// line 14 - TR14: u1, - /// Falling trigger event configuration of - /// line 15 - TR15: u1, - /// Falling trigger event configuration of - /// line 16 - TR16: u1, - /// Falling trigger event configuration of - /// line 17 - TR17: u1, - /// Falling trigger event configuration of - /// line 18 - TR18: u1, - /// Falling trigger event configuration of - /// line 19 - TR19: u1, - /// Falling trigger event configuration of - /// line 20 - TR20: u1, - /// Falling trigger event configuration of - /// line 21 - TR21: u1, - /// Falling trigger event configuration of - /// line 22 - TR22: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Falling trigger event configuration of - /// line 29 - TR29: u1, - /// Falling trigger event configuration of - /// line 30. - TR30: u1, - /// Falling trigger event configuration of - /// line 31 - TR31: u1, - }), base_address + 0xc); - - /// address: 0x40010410 - /// Software interrupt event - /// register - pub const SWIER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Interrupt on line - /// 0 - SWIER0: u1, - /// Software Interrupt on line - /// 1 - SWIER1: u1, - /// Software Interrupt on line - /// 2 - SWIER2: u1, - /// Software Interrupt on line - /// 3 - SWIER3: u1, - /// Software Interrupt on line - /// 4 - SWIER4: u1, - /// Software Interrupt on line - /// 5 - SWIER5: u1, - /// Software Interrupt on line - /// 6 - SWIER6: u1, - /// Software Interrupt on line - /// 7 - SWIER7: u1, - /// Software Interrupt on line - /// 8 - SWIER8: u1, - /// Software Interrupt on line - /// 9 - SWIER9: u1, - /// Software Interrupt on line - /// 10 - SWIER10: u1, - /// Software Interrupt on line - /// 11 - SWIER11: u1, - /// Software Interrupt on line - /// 12 - SWIER12: u1, - /// Software Interrupt on line - /// 13 - SWIER13: u1, - /// Software Interrupt on line - /// 14 - SWIER14: u1, - /// Software Interrupt on line - /// 15 - SWIER15: u1, - /// Software Interrupt on line - /// 16 - SWIER16: u1, - /// Software Interrupt on line - /// 17 - SWIER17: u1, - /// Software Interrupt on line - /// 18 - SWIER18: u1, - /// Software Interrupt on line - /// 19 - SWIER19: u1, - /// Software Interrupt on line - /// 20 - SWIER20: u1, - /// Software Interrupt on line - /// 21 - SWIER21: u1, - /// Software Interrupt on line - /// 22 - SWIER22: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Software Interrupt on line - /// 29 - SWIER29: u1, - /// Software Interrupt on line - /// 309 - SWIER30: u1, - /// Software Interrupt on line - /// 319 - SWIER31: u1, - }), base_address + 0x10); - - /// address: 0x40010414 - /// Pending register - pub const PR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending bit 0 - PR0: u1, - /// Pending bit 1 - PR1: u1, - /// Pending bit 2 - PR2: u1, - /// Pending bit 3 - PR3: u1, - /// Pending bit 4 - PR4: u1, - /// Pending bit 5 - PR5: u1, - /// Pending bit 6 - PR6: u1, - /// Pending bit 7 - PR7: u1, - /// Pending bit 8 - PR8: u1, - /// Pending bit 9 - PR9: u1, - /// Pending bit 10 - PR10: u1, - /// Pending bit 11 - PR11: u1, - /// Pending bit 12 - PR12: u1, - /// Pending bit 13 - PR13: u1, - /// Pending bit 14 - PR14: u1, - /// Pending bit 15 - PR15: u1, - /// Pending bit 16 - PR16: u1, - /// Pending bit 17 - PR17: u1, - /// Pending bit 18 - PR18: u1, - /// Pending bit 19 - PR19: u1, - /// Pending bit 20 - PR20: u1, - /// Pending bit 21 - PR21: u1, - /// Pending bit 22 - PR22: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Pending bit 29 - PR29: u1, - /// Pending bit 30 - PR30: u1, - /// Pending bit 31 - PR31: u1, - }), base_address + 0x14); - - /// address: 0x40010418 - /// Interrupt mask register - pub const IMR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt Mask on external/internal line - /// 32 - MR32: u1, - /// Interrupt Mask on external/internal line - /// 33 - MR33: u1, - /// Interrupt Mask on external/internal line - /// 34 - MR34: u1, - /// Interrupt Mask on external/internal line - /// 35 - MR35: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x18); - - /// address: 0x4001041c - /// Event mask register - pub const EMR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Event mask on external/internal line - /// 32 - MR32: u1, - /// Event mask on external/internal line - /// 33 - MR33: u1, - /// Event mask on external/internal line - /// 34 - MR34: u1, - /// Event mask on external/internal line - /// 35 - MR35: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x1c); - - /// address: 0x40010420 - /// Rising Trigger selection - /// register - pub const RTSR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising trigger event configuration bit - /// of line 32 - TR32: u1, - /// Rising trigger event configuration bit - /// of line 33 - TR33: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x20); - - /// address: 0x40010424 - /// Falling Trigger selection - /// register - pub const FTSR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling trigger event configuration bit - /// of line 32 - TR32: u1, - /// Falling trigger event configuration bit - /// of line 33 - TR33: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x24); - - /// address: 0x40010428 - /// Software interrupt event - /// register - pub const SWIER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Software interrupt on line - /// 32 - SWIER32: u1, - /// Software interrupt on line - /// 33 - SWIER33: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x28); - - /// address: 0x4001042c - /// Pending register - pub const PR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending bit on line 32 - PR32: u1, - /// Pending bit on line 33 - PR33: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x2c); - }; - /// Power control - pub const PWR = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// power control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: u1, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector - /// enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write - /// protection - DBP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40007004 - /// power control/status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Enable WKUP1 pin - EWUP1: u1, - /// Enable WKUP2 pin - EWUP2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - }; - /// Controller area network - pub const CAN = struct { - pub const base_address = 0x40006400; - - /// address: 0x40006400 - /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006404 - /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006408 - /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000640c - /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006410 - /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006414 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006418 - /// error status register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000641c - /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006580 - /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006584 - /// mailbox data length control and time stamp - /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006588 - /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000658c - /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006590 - /// TX mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006594 - /// mailbox data length control and time stamp - /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006598 - /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000659c - /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400065a0 - /// TX mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400065a4 - /// mailbox data length control and time stamp - /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400065a8 - /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400065ac - /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400065b0 - /// receive FIFO mailbox identifier - /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400065b4 - /// receive FIFO mailbox data length control and - /// time stamp register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400065b8 - /// receive FIFO mailbox data low - /// register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400065bc - /// receive FIFO mailbox data high - /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400065c0 - /// receive FIFO mailbox identifier - /// register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400065c4 - /// receive FIFO mailbox data length control and - /// time stamp register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400065c8 - /// receive FIFO mailbox data low - /// register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400065cc - /// receive FIFO mailbox data high - /// register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006600 - /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter init mode - FINIT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// CAN2 start bank - CAN2SB: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006604 - /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - /// Filter mode - FBM14: u1, - /// Filter mode - FBM15: u1, - /// Filter mode - FBM16: u1, - /// Filter mode - FBM17: u1, - /// Filter mode - FBM18: u1, - /// Filter mode - FBM19: u1, - /// Filter mode - FBM20: u1, - /// Filter mode - FBM21: u1, - /// Filter mode - FBM22: u1, - /// Filter mode - FBM23: u1, - /// Filter mode - FBM24: u1, - /// Filter mode - FBM25: u1, - /// Filter mode - FBM26: u1, - /// Filter mode - FBM27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x4000660c - /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - /// Filter scale configuration - FSC14: u1, - /// Filter scale configuration - FSC15: u1, - /// Filter scale configuration - FSC16: u1, - /// Filter scale configuration - FSC17: u1, - /// Filter scale configuration - FSC18: u1, - /// Filter scale configuration - FSC19: u1, - /// Filter scale configuration - FSC20: u1, - /// Filter scale configuration - FSC21: u1, - /// Filter scale configuration - FSC22: u1, - /// Filter scale configuration - FSC23: u1, - /// Filter scale configuration - FSC24: u1, - /// Filter scale configuration - FSC25: u1, - /// Filter scale configuration - FSC26: u1, - /// Filter scale configuration - FSC27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006614 - /// filter FIFO assignment - /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - /// Filter FIFO assignment for filter - /// 14 - FFA14: u1, - /// Filter FIFO assignment for filter - /// 15 - FFA15: u1, - /// Filter FIFO assignment for filter - /// 16 - FFA16: u1, - /// Filter FIFO assignment for filter - /// 17 - FFA17: u1, - /// Filter FIFO assignment for filter - /// 18 - FFA18: u1, - /// Filter FIFO assignment for filter - /// 19 - FFA19: u1, - /// Filter FIFO assignment for filter - /// 20 - FFA20: u1, - /// Filter FIFO assignment for filter - /// 21 - FFA21: u1, - /// Filter FIFO assignment for filter - /// 22 - FFA22: u1, - /// Filter FIFO assignment for filter - /// 23 - FFA23: u1, - /// Filter FIFO assignment for filter - /// 24 - FFA24: u1, - /// Filter FIFO assignment for filter - /// 25 - FFA25: u1, - /// Filter FIFO assignment for filter - /// 26 - FFA26: u1, - /// Filter FIFO assignment for filter - /// 27 - FFA27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x4000661c - /// CAN filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - /// Filter active - FACT14: u1, - /// Filter active - FACT15: u1, - /// Filter active - FACT16: u1, - /// Filter active - FACT17: u1, - /// Filter active - FACT18: u1, - /// Filter active - FACT19: u1, - /// Filter active - FACT20: u1, - /// Filter active - FACT21: u1, - /// Filter active - FACT22: u1, - /// Filter active - FACT23: u1, - /// Filter active - FACT24: u1, - /// Filter active - FACT25: u1, - /// Filter active - FACT26: u1, - /// Filter active - FACT27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006640 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006644 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006648 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x4000664c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006650 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006654 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006658 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x4000665c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006660 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006664 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006668 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x4000666c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006670 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006674 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006678 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x4000667c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006680 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006684 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006688 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x4000668c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006690 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006694 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006698 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x4000669c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x400066a0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x400066a4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x400066a8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x400066ac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - - /// address: 0x400066b0 - /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b0); - - /// address: 0x400066b4 - /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b4); - - /// address: 0x400066b8 - /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b8); - - /// address: 0x400066bc - /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2bc); - - /// address: 0x400066c0 - /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c0); - - /// address: 0x400066c4 - /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c4); - - /// address: 0x400066c8 - /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c8); - - /// address: 0x400066cc - /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2cc); - - /// address: 0x400066d0 - /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d0); - - /// address: 0x400066d4 - /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d4); - - /// address: 0x400066d8 - /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d8); - - /// address: 0x400066dc - /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2dc); - - /// address: 0x400066e0 - /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e0); - - /// address: 0x400066e4 - /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e4); - - /// address: 0x400066e8 - /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e8); - - /// address: 0x400066ec - /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ec); - - /// address: 0x400066f0 - /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f0); - - /// address: 0x400066f4 - /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f4); - - /// address: 0x400066f8 - /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f8); - - /// address: 0x400066fc - /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006700 - /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x300); - - /// address: 0x40006704 - /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x304); - - /// address: 0x40006708 - /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x308); - - /// address: 0x4000670c - /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x30c); - - /// address: 0x40006710 - /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x310); - - /// address: 0x40006714 - /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x314); - - /// address: 0x40006718 - /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x318); - - /// address: 0x4000671c - /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x31c); - }; - /// Universal serial bus full-speed device - /// interface - pub const USB_FS = struct { - pub const base_address = 0x40005c00; - - /// address: 0x40005c00 - /// endpoint 0 register - pub const USB_EP0R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005c04 - /// endpoint 1 register - pub const USB_EP1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40005c08 - /// endpoint 2 register - pub const USB_EP2R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40005c0c - /// endpoint 3 register - pub const USB_EP3R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005c10 - /// endpoint 4 register - pub const USB_EP4R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40005c14 - /// endpoint 5 register - pub const USB_EP5R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005c18 - /// endpoint 6 register - pub const USB_EP6R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40005c1c - /// endpoint 7 register - pub const USB_EP7R = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint address - EA: u4, - /// Status bits, for transmission - /// transfers - STAT_TX: u2, - /// Data Toggle, for transmission - /// transfers - DTOG_TX: u1, - /// Correct Transfer for - /// transmission - CTR_TX: u1, - /// Endpoint kind - EP_KIND: u1, - /// Endpoint type - EP_TYPE: u2, - /// Setup transaction - /// completed - SETUP: u1, - /// Status bits, for reception - /// transfers - STAT_RX: u2, - /// Data Toggle, for reception - /// transfers - DTOG_RX: u1, - /// Correct transfer for - /// reception - CTR_RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005c40 - /// control register - pub const USB_CNTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Force USB Reset - FRES: u1, - /// Power down - PDWN: u1, - /// Low-power mode - LPMODE: u1, - /// Force suspend - FSUSP: u1, - /// Resume request - RESUME: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Expected start of frame interrupt - /// mask - ESOFM: u1, - /// Start of frame interrupt - /// mask - SOFM: u1, - /// USB reset interrupt mask - RESETM: u1, - /// Suspend mode interrupt - /// mask - SUSPM: u1, - /// Wakeup interrupt mask - WKUPM: u1, - /// Error interrupt mask - ERRM: u1, - /// Packet memory area over / underrun - /// interrupt mask - PMAOVRM: u1, - /// Correct transfer interrupt - /// mask - CTRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40005c44 - /// interrupt status register - pub const ISTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint Identifier - EP_ID: u4, - /// Direction of transaction - DIR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Expected start frame - ESOF: u1, - /// start of frame - SOF: u1, - /// reset request - RESET: u1, - /// Suspend mode request - SUSP: u1, - /// Wakeup - WKUP: u1, - /// Error - ERR: u1, - /// Packet memory area over / - /// underrun - PMAOVR: u1, - /// Correct transfer - CTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40005c48 - /// frame number register - pub const FNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FN: u11, - /// Lost SOF - LSOF: u2, - /// Locked - LCK: u1, - /// Receive data - line status - RXDM: u1, - /// Receive data + line status - RXDP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x40005c4c - /// device address - pub const DADDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Device address - ADD: u1, - /// Device address - ADD1: u1, - /// Device address - ADD2: u1, - /// Device address - ADD3: u1, - /// Device address - ADD4: u1, - /// Device address - ADD5: u1, - /// Device address - ADD6: u1, - /// Enable function - EF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4c); - - /// address: 0x40005c50 - /// Buffer table address - pub const BTABLE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50); - }; - /// Inter-integrated circuit - pub const I2C1 = struct { - pub const base_address = 0x40005400; - - /// address: 0x40005400 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// TX Interrupt enable - TXIE: u1, - /// RX Interrupt enable - RXIE: u1, - /// Address match interrupt enable (slave - /// only) - ADDRIE: u1, - /// Not acknowledge received interrupt - /// enable - NACKIE: u1, - /// STOP detection Interrupt - /// enable - STOPIE: u1, - /// Transfer Complete interrupt - /// enable - TCIE: u1, - /// Error interrupts enable - ERRIE: u1, - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANFOFF: u1, - /// Software reset - SWRST: u1, - /// DMA transmission requests - /// enable - TXDMAEN: u1, - /// DMA reception requests - /// enable - RXDMAEN: u1, - /// Slave byte control - SBC: u1, - /// Clock stretching disable - NOSTRETCH: u1, - /// Wakeup from STOP enable - WUPEN: u1, - /// General call enable - GCEN: u1, - /// SMBus Host address enable - SMBHEN: u1, - /// SMBus Device Default address - /// enable - SMBDEN: u1, - /// SMBUS alert enable - ALERTEN: u1, - /// PEC enable - PECEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40005404 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave address bit 0 (master - /// mode) - SADD0: u1, - /// Slave address bit 7:1 (master - /// mode) - SADD1: u7, - /// Slave address bit 9:8 (master - /// mode) - SADD8: u2, - /// Transfer direction (master - /// mode) - RD_WRN: u1, - /// 10-bit addressing mode (master - /// mode) - ADD10: u1, - /// 10-bit address header only read - /// direction (master receiver mode) - HEAD10R: u1, - /// Start generation - START: u1, - /// Stop generation (master - /// mode) - STOP: u1, - /// NACK generation (slave - /// mode) - NACK: u1, - /// Number of bytes - NBYTES: u8, - /// NBYTES reload mode - RELOAD: u1, - /// Automatic end mode (master - /// mode) - AUTOEND: u1, - /// Packet error checking byte - PECBYTE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40005408 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - OA1_0: u1, - /// Interface address - OA1_1: u7, - /// Interface address - OA1_8: u2, - /// Own Address 1 10-bit mode - OA1MODE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Own Address 1 enable - OA1EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000540c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Interface address - OA2: u7, - /// Own Address 2 masks - OA2MSK: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Own Address 2 enable - OA2EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005410 - /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { - /// SCL low period (master - /// mode) - SCLL: u8, - /// SCL high period (master - /// mode) - SCLH: u8, - /// Data hold time - SDADEL: u4, - /// Data setup time - SCLDEL: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Timing prescaler - PRESC: u4, - }), base_address + 0x10); - - /// address: 0x40005414 - /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Bus timeout A - TIMEOUTA: u12, - /// Idle clock timeout - /// detection - TIDLE: u1, - reserved0: u1, - reserved1: u1, - /// Clock timeout enable - TIMOUTEN: u1, - /// Bus timeout B - TIMEOUTB: u12, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Extended clock timeout - /// enable - TEXTEN: u1, - }), base_address + 0x14); - - /// address: 0x40005418 - /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit data register empty - /// (transmitters) - TXE: u1, - /// Transmit interrupt status - /// (transmitters) - TXIS: u1, - /// Receive data register not empty - /// (receivers) - RXNE: u1, - /// Address matched (slave - /// mode) - ADDR: u1, - /// Not acknowledge received - /// flag - NACKF: u1, - /// Stop detection flag - STOPF: u1, - /// Transfer Complete (master - /// mode) - TC: u1, - /// Transfer Complete Reload - TCR: u1, - /// Bus error - BERR: u1, - /// Arbitration lost - ARLO: u1, - /// Overrun/Underrun (slave - /// mode) - OVR: u1, - /// PEC Error in reception - PECERR: u1, - /// Timeout or t_low detection - /// flag - TIMEOUT: u1, - /// SMBus alert - ALERT: u1, - reserved0: u1, - /// Bus busy - BUSY: u1, - /// Transfer direction (Slave - /// mode) - DIR: u1, - /// Address match code (Slave - /// mode) - ADDCODE: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0x4000541c - /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Address Matched flag clear - ADDRCF: u1, - /// Not Acknowledge flag clear - NACKCF: u1, - /// Stop detection flag clear - STOPCF: u1, - reserved3: u1, - reserved4: u1, - /// Bus error flag clear - BERRCF: u1, - /// Arbitration lost flag - /// clear - ARLOCF: u1, - /// Overrun/Underrun flag - /// clear - OVRCF: u1, - /// PEC Error flag clear - PECCF: u1, - /// Timeout detection flag - /// clear - TIMOUTCF: u1, - /// Alert flag clear - ALERTCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c); - - /// address: 0x40005420 - /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { - /// Packet error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40005424 - /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit receive data - RXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40005428 - /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit transmit data - TXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x28); - }; - pub const I2C2 = struct { - pub const base_address = 0x40005800; - - /// address: 0x40005800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// TX Interrupt enable - TXIE: u1, - /// RX Interrupt enable - RXIE: u1, - /// Address match interrupt enable (slave - /// only) - ADDRIE: u1, - /// Not acknowledge received interrupt - /// enable - NACKIE: u1, - /// STOP detection Interrupt - /// enable - STOPIE: u1, - /// Transfer Complete interrupt - /// enable - TCIE: u1, - /// Error interrupts enable - ERRIE: u1, - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANFOFF: u1, - /// Software reset - SWRST: u1, - /// DMA transmission requests - /// enable - TXDMAEN: u1, - /// DMA reception requests - /// enable - RXDMAEN: u1, - /// Slave byte control - SBC: u1, - /// Clock stretching disable - NOSTRETCH: u1, - /// Wakeup from STOP enable - WUPEN: u1, - /// General call enable - GCEN: u1, - /// SMBus Host address enable - SMBHEN: u1, - /// SMBus Device Default address - /// enable - SMBDEN: u1, - /// SMBUS alert enable - ALERTEN: u1, - /// PEC enable - PECEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40005804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave address bit 0 (master - /// mode) - SADD0: u1, - /// Slave address bit 7:1 (master - /// mode) - SADD1: u7, - /// Slave address bit 9:8 (master - /// mode) - SADD8: u2, - /// Transfer direction (master - /// mode) - RD_WRN: u1, - /// 10-bit addressing mode (master - /// mode) - ADD10: u1, - /// 10-bit address header only read - /// direction (master receiver mode) - HEAD10R: u1, - /// Start generation - START: u1, - /// Stop generation (master - /// mode) - STOP: u1, - /// NACK generation (slave - /// mode) - NACK: u1, - /// Number of bytes - NBYTES: u8, - /// NBYTES reload mode - RELOAD: u1, - /// Automatic end mode (master - /// mode) - AUTOEND: u1, - /// Packet error checking byte - PECBYTE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40005808 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - OA1_0: u1, - /// Interface address - OA1_1: u7, - /// Interface address - OA1_8: u2, - /// Own Address 1 10-bit mode - OA1MODE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Own Address 1 enable - OA1EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000580c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Interface address - OA2: u7, - /// Own Address 2 masks - OA2MSK: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Own Address 2 enable - OA2EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005810 - /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { - /// SCL low period (master - /// mode) - SCLL: u8, - /// SCL high period (master - /// mode) - SCLH: u8, - /// Data hold time - SDADEL: u4, - /// Data setup time - SCLDEL: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Timing prescaler - PRESC: u4, - }), base_address + 0x10); - - /// address: 0x40005814 - /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Bus timeout A - TIMEOUTA: u12, - /// Idle clock timeout - /// detection - TIDLE: u1, - reserved0: u1, - reserved1: u1, - /// Clock timeout enable - TIMOUTEN: u1, - /// Bus timeout B - TIMEOUTB: u12, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Extended clock timeout - /// enable - TEXTEN: u1, - }), base_address + 0x14); - - /// address: 0x40005818 - /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit data register empty - /// (transmitters) - TXE: u1, - /// Transmit interrupt status - /// (transmitters) - TXIS: u1, - /// Receive data register not empty - /// (receivers) - RXNE: u1, - /// Address matched (slave - /// mode) - ADDR: u1, - /// Not acknowledge received - /// flag - NACKF: u1, - /// Stop detection flag - STOPF: u1, - /// Transfer Complete (master - /// mode) - TC: u1, - /// Transfer Complete Reload - TCR: u1, - /// Bus error - BERR: u1, - /// Arbitration lost - ARLO: u1, - /// Overrun/Underrun (slave - /// mode) - OVR: u1, - /// PEC Error in reception - PECERR: u1, - /// Timeout or t_low detection - /// flag - TIMEOUT: u1, - /// SMBus alert - ALERT: u1, - reserved0: u1, - /// Bus busy - BUSY: u1, - /// Transfer direction (Slave - /// mode) - DIR: u1, - /// Address match code (Slave - /// mode) - ADDCODE: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0x4000581c - /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Address Matched flag clear - ADDRCF: u1, - /// Not Acknowledge flag clear - NACKCF: u1, - /// Stop detection flag clear - STOPCF: u1, - reserved3: u1, - reserved4: u1, - /// Bus error flag clear - BERRCF: u1, - /// Arbitration lost flag - /// clear - ARLOCF: u1, - /// Overrun/Underrun flag - /// clear - OVRCF: u1, - /// PEC Error flag clear - PECCF: u1, - /// Timeout detection flag - /// clear - TIMOUTCF: u1, - /// Alert flag clear - ALERTCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c); - - /// address: 0x40005820 - /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { - /// Packet error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40005824 - /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit receive data - RXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40005828 - /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit transmit data - TXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x28); - }; - pub const I2C3 = struct { - pub const base_address = 0x40007800; - - /// address: 0x40007800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// TX Interrupt enable - TXIE: u1, - /// RX Interrupt enable - RXIE: u1, - /// Address match interrupt enable (slave - /// only) - ADDRIE: u1, - /// Not acknowledge received interrupt - /// enable - NACKIE: u1, - /// STOP detection Interrupt - /// enable - STOPIE: u1, - /// Transfer Complete interrupt - /// enable - TCIE: u1, - /// Error interrupts enable - ERRIE: u1, - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANFOFF: u1, - /// Software reset - SWRST: u1, - /// DMA transmission requests - /// enable - TXDMAEN: u1, - /// DMA reception requests - /// enable - RXDMAEN: u1, - /// Slave byte control - SBC: u1, - /// Clock stretching disable - NOSTRETCH: u1, - /// Wakeup from STOP enable - WUPEN: u1, - /// General call enable - GCEN: u1, - /// SMBus Host address enable - SMBHEN: u1, - /// SMBus Device Default address - /// enable - SMBDEN: u1, - /// SMBUS alert enable - ALERTEN: u1, - /// PEC enable - PECEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0x40007804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave address bit 0 (master - /// mode) - SADD0: u1, - /// Slave address bit 7:1 (master - /// mode) - SADD1: u7, - /// Slave address bit 9:8 (master - /// mode) - SADD8: u2, - /// Transfer direction (master - /// mode) - RD_WRN: u1, - /// 10-bit addressing mode (master - /// mode) - ADD10: u1, - /// 10-bit address header only read - /// direction (master receiver mode) - HEAD10R: u1, - /// Start generation - START: u1, - /// Stop generation (master - /// mode) - STOP: u1, - /// NACK generation (slave - /// mode) - NACK: u1, - /// Number of bytes - NBYTES: u8, - /// NBYTES reload mode - RELOAD: u1, - /// Automatic end mode (master - /// mode) - AUTOEND: u1, - /// Packet error checking byte - PECBYTE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40007808 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - OA1_0: u1, - /// Interface address - OA1_1: u7, - /// Interface address - OA1_8: u2, - /// Own Address 1 10-bit mode - OA1MODE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Own Address 1 enable - OA1EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000780c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Interface address - OA2: u7, - /// Own Address 2 masks - OA2MSK: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Own Address 2 enable - OA2EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007810 - /// Timing register - pub const TIMINGR = @intToPtr(*volatile Mmio(32, packed struct { - /// SCL low period (master - /// mode) - SCLL: u8, - /// SCL high period (master - /// mode) - SCLH: u8, - /// Data hold time - SDADEL: u4, - /// Data setup time - SCLDEL: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Timing prescaler - PRESC: u4, - }), base_address + 0x10); - - /// address: 0x40007814 - /// Status register 1 - pub const TIMEOUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Bus timeout A - TIMEOUTA: u12, - /// Idle clock timeout - /// detection - TIDLE: u1, - reserved0: u1, - reserved1: u1, - /// Clock timeout enable - TIMOUTEN: u1, - /// Bus timeout B - TIMEOUTB: u12, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Extended clock timeout - /// enable - TEXTEN: u1, - }), base_address + 0x14); - - /// address: 0x40007818 - /// Interrupt and Status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transmit data register empty - /// (transmitters) - TXE: u1, - /// Transmit interrupt status - /// (transmitters) - TXIS: u1, - /// Receive data register not empty - /// (receivers) - RXNE: u1, - /// Address matched (slave - /// mode) - ADDR: u1, - /// Not acknowledge received - /// flag - NACKF: u1, - /// Stop detection flag - STOPF: u1, - /// Transfer Complete (master - /// mode) - TC: u1, - /// Transfer Complete Reload - TCR: u1, - /// Bus error - BERR: u1, - /// Arbitration lost - ARLO: u1, - /// Overrun/Underrun (slave - /// mode) - OVR: u1, - /// PEC Error in reception - PECERR: u1, - /// Timeout or t_low detection - /// flag - TIMEOUT: u1, - /// SMBus alert - ALERT: u1, - reserved0: u1, - /// Bus busy - BUSY: u1, - /// Transfer direction (Slave - /// mode) - DIR: u1, - /// Address match code (Slave - /// mode) - ADDCODE: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0x4000781c - /// Interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Address Matched flag clear - ADDRCF: u1, - /// Not Acknowledge flag clear - NACKCF: u1, - /// Stop detection flag clear - STOPCF: u1, - reserved3: u1, - reserved4: u1, - /// Bus error flag clear - BERRCF: u1, - /// Arbitration lost flag - /// clear - ARLOCF: u1, - /// Overrun/Underrun flag - /// clear - OVRCF: u1, - /// PEC Error flag clear - PECCF: u1, - /// Timeout detection flag - /// clear - TIMOUTCF: u1, - /// Alert flag clear - ALERTCF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c); - - /// address: 0x40007820 - /// PEC register - pub const PECR = @intToPtr(*volatile Mmio(32, packed struct { - /// Packet error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40007824 - /// Receive data register - pub const RXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit receive data - RXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40007828 - /// Transmit data register - pub const TXDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 8-bit transmit data - TXDATA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x28); - }; - /// Independent watchdog - pub const IWDG = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Key register - pub const KR = @intToPtr(*volatile Mmio(32, packed struct { - /// Key value - KEY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Prescaler register - pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); - - /// address: 0x40003008 - /// Reload register - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog counter reload - /// value - RL: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog prescaler value - /// update - PVU: u1, - /// Watchdog counter reload value - /// update - RVU: u1, - /// Watchdog counter window value - /// update - WVU: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0xc); - - /// address: 0x40003010 - /// Window register - pub const WINR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog counter window - /// value - WIN: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x10); - }; - /// Window watchdog - pub const WWDG = struct { - pub const base_address = 0x40002c00; - - /// address: 0x40002c00 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit counter - T: u7, - /// Activation bit - WDGA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40002c04 - /// Configuration register - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit window value - W: u7, - /// Timer base - WDGTB: u2, - /// Early wakeup interrupt - EWI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x40002c08 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Early wakeup interrupt - /// flag - EWIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - /// Real-time clock - pub const RTC = struct { - pub const base_address = 0x40002800; - - /// address: 0x40002800 - /// time register - pub const TR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved0: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved1: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x0); - - /// address: 0x40002804 - /// date register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup clock selection - WCKSEL: u3, - /// Time-stamp event active - /// edge - TSEDGE: u1, - /// Reference clock detection enable (50 or - /// 60 Hz) - REFCKON: u1, - /// Bypass the shadow - /// registers - BYPSHAD: u1, - /// Hour format - FMT: u1, - reserved0: u1, - /// Alarm A enable - ALRAE: u1, - /// Alarm B enable - ALRBE: u1, - /// Wakeup timer enable - WUTE: u1, - /// Time stamp enable - TSE: u1, - /// Alarm A interrupt enable - ALRAIE: u1, - /// Alarm B interrupt enable - ALRBIE: u1, - /// Wakeup timer interrupt - /// enable - WUTIE: u1, - /// Time-stamp interrupt - /// enable - TSIE: u1, - /// Add 1 hour (summer time - /// change) - ADD1H: u1, - /// Subtract 1 hour (winter time - /// change) - SUB1H: u1, - /// Backup - BKP: u1, - /// Calibration output - /// selection - COSEL: u1, - /// Output polarity - POL: u1, - /// Output selection - OSEL: u2, - /// Calibration output enable - COE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4000280c - /// initialization and status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Alarm A write flag - ALRAWF: u1, - /// Alarm B write flag - ALRBWF: u1, - /// Wakeup timer write flag - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization - /// flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Initialization mode - INIT: u1, - /// Alarm A flag - ALRAF: u1, - /// Alarm B flag - ALRBF: u1, - /// Wakeup timer flag - WUTF: u1, - /// Time-stamp flag - TSF: u1, - /// Time-stamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMP1F: u1, - /// RTC_TAMP2 detection flag - TAMP2F: u1, - /// RTC_TAMP3 detection flag - TAMP3F: u1, - /// Recalibration pending Flag - RECALPF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xc); - - /// address: 0x40002810 - /// prescaler register - pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { - /// Synchronous prescaler - /// factor - PREDIV_S: u15, - reserved0: u1, - /// Asynchronous prescaler - /// factor - PREDIV_A: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x10); - - /// address: 0x40002814 - /// wakeup timer register - pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup auto-reload value - /// bits - WUT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x4000281c - /// alarm A register - pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm A hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm A date mask - MSK4: u1, - }), base_address + 0x1c); - - /// address: 0x40002820 - /// alarm B register - pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm B seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm B minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm B hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm B date mask - MSK4: u1, - }), base_address + 0x20); - - /// address: 0x40002824 - /// write protection register - pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write protection key - KEY: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40002828 - /// sub second register - pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000282c - /// shift control register - pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Subtract a fraction of a - /// second - SUBFS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Add one second - ADD1S: u1, - }), base_address + 0x2c); - - /// address: 0x40002830 - /// time stamp time register - pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved0: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved1: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x30); - - /// address: 0x40002834 - /// time stamp date register - pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40002838 - /// timestamp sub second register - pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x38); - - /// address: 0x4000283c - /// calibration register - pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration minus - CALM: u9, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Use a 16-second calibration cycle - /// period - CALW16: u1, - /// Use an 8-second calibration cycle - /// period - CALW8: u1, - /// Increase frequency of RTC by 488.5 - /// ppm - CALP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40002840 - /// tamper and alternate function configuration - /// register - pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1, - /// Active level for tamper 1 - TAMP1TRG: u1, - /// Tamper interrupt enable - TAMPIE: u1, - /// Tamper 2 detection enable - TAMP2E: u1, - /// Active level for tamper 2 - TAMP2TRG: u1, - /// Tamper 3 detection enable - TAMP3E: u1, - /// Active level for tamper 3 - TAMP3TRG: u1, - /// Activate timestamp on tamper detection - /// event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: u3, - /// Tamper filter count - TAMPFLT: u2, - /// Tamper precharge duration - TAMPPRCH: u2, - /// TAMPER pull-up disable - TAMPPUDIS: u1, - reserved0: u1, - reserved1: u1, - /// PC13 value - PC13VALUE: u1, - /// PC13 mode - PC13MODE: u1, - /// PC14 value - PC14VALUE: u1, - /// PC 14 mode - PC14MODE: u1, - /// PC15 value - PC15VALUE: u1, - /// PC15 mode - PC15MODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x40); - - /// address: 0x40002844 - /// alarm A sub second register - pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x44); - - /// address: 0x40002848 - /// alarm B sub second register - pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x48); - - /// address: 0x40002850 - /// backup register - pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x50); - - /// address: 0x40002854 - /// backup register - pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x54); - - /// address: 0x40002858 - /// backup register - pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x58); - - /// address: 0x4000285c - /// backup register - pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x5c); - - /// address: 0x40002860 - /// backup register - pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x60); - - /// address: 0x40002864 - /// backup register - pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x64); - - /// address: 0x40002868 - /// backup register - pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x68); - - /// address: 0x4000286c - /// backup register - pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x6c); - - /// address: 0x40002870 - /// backup register - pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x70); - - /// address: 0x40002874 - /// backup register - pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x74); - - /// address: 0x40002878 - /// backup register - pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x78); - - /// address: 0x4000287c - /// backup register - pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x7c); - - /// address: 0x40002880 - /// backup register - pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x80); - - /// address: 0x40002884 - /// backup register - pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x84); - - /// address: 0x40002888 - /// backup register - pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x88); - - /// address: 0x4000288c - /// backup register - pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x8c); - - /// address: 0x40002890 - /// backup register - pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x90); - - /// address: 0x40002894 - /// backup register - pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x94); - - /// address: 0x40002898 - /// backup register - pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x98); - - /// address: 0x4000289c - /// backup register - pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x9c); - - /// address: 0x400028a0 - /// backup register - pub const BKP20R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xa0); - - /// address: 0x400028a4 - /// backup register - pub const BKP21R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xa4); - - /// address: 0x400028a8 - /// backup register - pub const BKP22R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xa8); - - /// address: 0x400028ac - /// backup register - pub const BKP23R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xac); - - /// address: 0x400028b0 - /// backup register - pub const BKP24R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xb0); - - /// address: 0x400028b4 - /// backup register - pub const BKP25R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xb4); - - /// address: 0x400028b8 - /// backup register - pub const BKP26R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xb8); - - /// address: 0x400028bc - /// backup register - pub const BKP27R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xbc); - - /// address: 0x400028c0 - /// backup register - pub const BKP28R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xc0); - - /// address: 0x400028c4 - /// backup register - pub const BKP29R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xc4); - - /// address: 0x400028c8 - /// backup register - pub const BKP30R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xc8); - - /// address: 0x400028cc - /// backup register - pub const BKP31R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0xcc); - }; - /// Basic timers - pub const TIM6 = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000100c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF Copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40001028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000102c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - pub const TIM7 = struct { - pub const base_address = 0x40001400; - - /// address: 0x40001400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000140c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF Copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40001428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000142c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - /// Digital-to-analog converter - pub const DAC = struct { - pub const base_address = 0x40007400; - - /// address: 0x40007400 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 enable - EN1: u1, - /// DAC channel1 output buffer - /// disable - BOFF1: u1, - /// DAC channel1 trigger - /// enable - TEN1: u1, - /// DAC channel1 trigger - /// selection - TSEL1: u3, - /// DAC channel1 noise/triangle wave - /// generation enable - WAVE1: u2, - /// DAC channel1 mask/amplitude - /// selector - MAMP1: u4, - /// DAC channel1 DMA enable - DMAEN1: u1, - /// DAC channel1 DMA Underrun Interrupt - /// enable - DMAUDRIE1: u1, - reserved0: u1, - reserved1: u1, - /// DAC channel2 enable - EN2: u1, - /// DAC channel2 output buffer - /// disable - BOFF2: u1, - /// DAC channel2 trigger - /// enable - TEN2: u1, - /// DAC channel2 trigger - /// selection - TSEL2: u3, - /// DAC channel2 noise/triangle wave - /// generation enable - WAVE2: u2, - /// DAC channel2 mask/amplitude - /// selector - MAMP2: u4, - /// DAC channel2 DMA enable - DMAEN2: u1, - /// DAC channel2 DMA underrun interrupt - /// enable - DMAUDRIE2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x40007404 - /// software trigger register - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 software - /// trigger - SWTRIG1: u1, - /// DAC channel2 software - /// trigger - SWTRIG2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40007408 - /// channel1 12-bit right-aligned data holding - /// register - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000740c - /// channel1 12-bit left aligned data holding - /// register - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007410 - /// channel1 8-bit right aligned data holding - /// register - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40007414 - /// channel2 12-bit right aligned data holding - /// register - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007418 - /// channel2 12-bit left aligned data holding - /// register - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000741c - /// channel2 8-bit right-aligned data holding - /// register - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1c); - - /// address: 0x40007420 - /// Dual DAC 12-bit right-aligned data holding - /// register - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x40007424 - /// DUAL DAC 12-bit left aligned data holding - /// register - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - }), base_address + 0x24); - - /// address: 0x40007428 - /// DUAL DAC 8-bit right aligned data holding - /// register - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000742c - /// channel1 data output register - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40007430 - /// channel2 data output register - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - - /// address: 0x40007434 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// DAC channel1 DMA underrun - /// flag - DMAUDR1: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - /// DAC channel2 DMA underrun - /// flag - DMAUDR2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - }; - /// Debug support - pub const DBGMCU = struct { - pub const base_address = 0xe0042000; - - /// address: 0xe0042000 - /// MCU Device ID Code Register - pub const IDCODE = @intToPtr(*volatile Mmio(32, packed struct { - /// Device Identifier - DEV_ID: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Revision Identifier - REV_ID: u16, - }), base_address + 0x0); - - /// address: 0xe0042004 - /// Debug MCU Configuration - /// Register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Debug Sleep mode - DBG_SLEEP: u1, - /// Debug Stop Mode - DBG_STOP: u1, - /// Debug Standby Mode - DBG_STANDBY: u1, - reserved0: u1, - reserved1: u1, - /// Trace pin assignment - /// control - TRACE_IOEN: u1, - /// Trace pin assignment - /// control - TRACE_MODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0xe0042008 - /// APB Low Freeze Register - pub const APB1FZ = @intToPtr(*volatile Mmio(32, packed struct { - /// Debug Timer 2 stopped when Core is - /// halted - DBG_TIM2_STOP: u1, - /// Debug Timer 3 stopped when Core is - /// halted - DBG_TIM3_STOP: u1, - /// Debug Timer 4 stopped when Core is - /// halted - DBG_TIM4_STOP: u1, - /// Debug Timer 5 stopped when Core is - /// halted - DBG_TIM5_STOP: u1, - /// Debug Timer 6 stopped when Core is - /// halted - DBG_TIM6_STOP: u1, - /// Debug Timer 7 stopped when Core is - /// halted - DBG_TIM7_STOP: u1, - /// Debug Timer 12 stopped when Core is - /// halted - DBG_TIM12_STOP: u1, - /// Debug Timer 13 stopped when Core is - /// halted - DBG_TIM13_STOP: u1, - /// Debug Timer 14 stopped when Core is - /// halted - DBG_TIMER14_STOP: u1, - /// Debug Timer 18 stopped when Core is - /// halted - DBG_TIM18_STOP: u1, - /// Debug RTC stopped when Core is - /// halted - DBG_RTC_STOP: u1, - /// Debug Window Wachdog stopped when Core - /// is halted - DBG_WWDG_STOP: u1, - /// Debug Independent Wachdog stopped when - /// Core is halted - DBG_IWDG_STOP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// SMBUS timeout mode stopped when Core is - /// halted - I2C1_SMBUS_TIMEOUT: u1, - /// SMBUS timeout mode stopped when Core is - /// halted - I2C2_SMBUS_TIMEOUT: u1, - reserved8: u1, - reserved9: u1, - /// Debug CAN stopped when core is - /// halted - DBG_CAN_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0xe004200c - /// APB High Freeze Register - pub const APB2FZ = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Debug Timer 15 stopped when Core is - /// halted - DBG_TIM15_STOP: u1, - /// Debug Timer 16 stopped when Core is - /// halted - DBG_TIM16_STOP: u1, - /// Debug Timer 17 stopped when Core is - /// halted - DBG_TIM17_STO: u1, - /// Debug Timer 19 stopped when Core is - /// halted - DBG_TIM19_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - }; - /// Advanced timer - pub const TIM1 = struct { - pub const base_address = 0x40012c00; - - /// address: 0x40012c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40012c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - reserved1: u1, - /// Output Idle state 5 - OIS5: u1, - reserved2: u1, - /// Output Idle state 6 - OIS6: u1, - reserved3: u1, - /// Master mode selection 2 - MMS2: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit 3 - SMS3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x40012c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40012c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - /// Break 2 interrupt flag - B2IF: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 5 interrupt - /// flag - C5IF: u1, - /// Capture/Compare 6 interrupt - /// flag - C6IF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x10); - - /// address: 0x40012c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - /// Break 2 generation - B2G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x14); - - /// address: 0x40012c18 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - /// Output Compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40012c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40012c1c - /// capture/compare mode register (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - /// Output Compare 3 mode bit - /// 3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 4 mode bit - /// 3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x40012c1c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40012c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved0: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - /// Capture/Compare 5 output - /// enable - CC5E: u1, - /// Capture/Compare 5 output - /// Polarity - CC5P: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 6 output - /// enable - CC6E: u1, - /// Capture/Compare 6 output - /// Polarity - CC6P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x20); - - /// address: 0x40012c24 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40012c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40012c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40012c30 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x30); - - /// address: 0x40012c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40012c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x40012c3c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40012c40 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40012c44 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - /// Break 2 filter - BK2F: u4, - /// Break 2 enable - BK2E: u1, - /// Break 2 polarity - BK2P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x44); - - /// address: 0x40012c48 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x40012c4c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40012c54 - /// capture/compare mode register 3 (output - /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Output compare 5 fast - /// enable - OC5FE: u1, - /// Output compare 5 preload - /// enable - OC5PE: u1, - /// Output compare 5 mode - OC5M: u3, - /// Output compare 5 clear - /// enable - OC5CE: u1, - reserved2: u1, - reserved3: u1, - /// Output compare 6 fast - /// enable - OC6FE: u1, - /// Output compare 6 preload - /// enable - OC6PE: u1, - /// Output compare 6 mode - OC6M: u3, - /// Output compare 6 clear - /// enable - OC6CE: u1, - /// Outout Compare 5 mode bit - /// 3 - OC5M_3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Outout Compare 6 mode bit - /// 3 - OC6M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x54); - - /// address: 0x40012c58 - /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 5 value - CCR5: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Group Channel 5 and Channel - /// 1 - GC5C1: u1, - /// Group Channel 5 and Channel - /// 2 - GC5C2: u1, - /// Group Channel 5 and Channel - /// 3 - GC5C3: u1, - }), base_address + 0x58); - - /// address: 0x40012c5c - /// capture/compare register 6 - pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); - - /// address: 0x40012c60 - /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1_ETR_ADC1 remapping - /// capability - TIM1_ETR_ADC1_RMP: u2, - /// TIM1_ETR_ADC4 remapping - /// capability - TIM1_ETR_ADC4_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x60); - }; - pub const TIM20 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40015004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - reserved1: u1, - /// Output Idle state 5 - OIS5: u1, - reserved2: u1, - /// Output Idle state 6 - OIS6: u1, - reserved3: u1, - /// Master mode selection 2 - MMS2: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40015008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit 3 - SMS3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4001500c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40015010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - /// Break 2 interrupt flag - B2IF: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 5 interrupt - /// flag - C5IF: u1, - /// Capture/Compare 6 interrupt - /// flag - C6IF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x10); - - /// address: 0x40015014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - /// Break 2 generation - B2G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x14); - - /// address: 0x40015018 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - /// Output Compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40015018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001501c - /// capture/compare mode register (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - /// Output Compare 3 mode bit - /// 3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 4 mode bit - /// 3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x4001501c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40015020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved0: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - /// Capture/Compare 5 output - /// enable - CC5E: u1, - /// Capture/Compare 5 output - /// Polarity - CC5P: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 6 output - /// enable - CC6E: u1, - /// Capture/Compare 6 output - /// Polarity - CC6P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x20); - - /// address: 0x40015024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40015028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001502c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40015030 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x30); - - /// address: 0x40015034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40015038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001503c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40015040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40015044 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - /// Break 2 filter - BK2F: u4, - /// Break 2 enable - BK2E: u1, - /// Break 2 polarity - BK2P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x44); - - /// address: 0x40015048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001504c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40015054 - /// capture/compare mode register 3 (output - /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Output compare 5 fast - /// enable - OC5FE: u1, - /// Output compare 5 preload - /// enable - OC5PE: u1, - /// Output compare 5 mode - OC5M: u3, - /// Output compare 5 clear - /// enable - OC5CE: u1, - reserved2: u1, - reserved3: u1, - /// Output compare 6 fast - /// enable - OC6FE: u1, - /// Output compare 6 preload - /// enable - OC6PE: u1, - /// Output compare 6 mode - OC6M: u3, - /// Output compare 6 clear - /// enable - OC6CE: u1, - /// Outout Compare 5 mode bit - /// 3 - OC5M_3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Outout Compare 6 mode bit - /// 3 - OC6M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x54); - - /// address: 0x40015058 - /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 5 value - CCR5: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Group Channel 5 and Channel - /// 1 - GC5C1: u1, - /// Group Channel 5 and Channel - /// 2 - GC5C2: u1, - /// Group Channel 5 and Channel - /// 3 - GC5C3: u1, - }), base_address + 0x58); - - /// address: 0x4001505c - /// capture/compare register 6 - pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); - - /// address: 0x40015060 - /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1_ETR_ADC1 remapping - /// capability - TIM1_ETR_ADC1_RMP: u2, - /// TIM1_ETR_ADC4 remapping - /// capability - TIM1_ETR_ADC4_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x60); - }; - /// Advanced-timers - pub const TIM8 = struct { - pub const base_address = 0x40013400; - - /// address: 0x40013400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - reserved0: u1, - /// UIF status bit remapping - UIFREMAP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40013404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - reserved1: u1, - /// Output Idle state 5 - OIS5: u1, - reserved2: u1, - /// Output Idle state 6 - OIS6: u1, - reserved3: u1, - /// Master mode selection 2 - MMS2: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40013408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - /// OCREF clear selection - OCCS: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - /// Slave mode selection bit 3 - SMS3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x8); - - /// address: 0x4001340c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40013410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - /// Break 2 interrupt flag - B2IF: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 5 interrupt - /// flag - C5IF: u1, - /// Capture/Compare 6 interrupt - /// flag - C6IF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x10); - - /// address: 0x40013414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - /// Break 2 generation - B2G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x14); - - /// address: 0x40013418 - /// capture/compare mode register (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - /// Output Compare 1 mode bit - /// 3 - OC1M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 2 mode bit - /// 3 - OC2M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x18); - - /// address: 0x40013418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - IC1PCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001341c - /// capture/compare mode register (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - /// Output Compare 3 mode bit - /// 3 - OC3M_3: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Output Compare 4 mode bit - /// 3 - OC4M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x4001341c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40013420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved0: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - /// Capture/Compare 5 output - /// enable - CC5E: u1, - /// Capture/Compare 5 output - /// Polarity - CC5P: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 6 output - /// enable - CC6E: u1, - /// Capture/Compare 6 output - /// Polarity - CC6P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x20); - - /// address: 0x40013424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// counter value - CNT: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// UIF copy - UIFCPY: u1, - }), base_address + 0x24); - - /// address: 0x40013428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001342c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40013430 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x30); - - /// address: 0x40013434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40013438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001343c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40013440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40013444 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - /// Break filter - BKF: u4, - /// Break 2 filter - BK2F: u4, - /// Break 2 enable - BK2E: u1, - /// Break 2 polarity - BK2P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x44); - - /// address: 0x40013448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001344c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40013454 - /// capture/compare mode register 3 (output - /// mode) - pub const CCMR3_Output = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Output compare 5 fast - /// enable - OC5FE: u1, - /// Output compare 5 preload - /// enable - OC5PE: u1, - /// Output compare 5 mode - OC5M: u3, - /// Output compare 5 clear - /// enable - OC5CE: u1, - reserved2: u1, - reserved3: u1, - /// Output compare 6 fast - /// enable - OC6FE: u1, - /// Output compare 6 preload - /// enable - OC6PE: u1, - /// Output compare 6 mode - OC6M: u3, - /// Output compare 6 clear - /// enable - OC6CE: u1, - /// Outout Compare 5 mode bit - /// 3 - OC5M_3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// Outout Compare 6 mode bit - /// 3 - OC6M_3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x54); - - /// address: 0x40013458 - /// capture/compare register 5 - pub const CCR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 5 value - CCR5: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Group Channel 5 and Channel - /// 1 - GC5C1: u1, - /// Group Channel 5 and Channel - /// 2 - GC5C2: u1, - /// Group Channel 5 and Channel - /// 3 - GC5C3: u1, - }), base_address + 0x58); - - /// address: 0x4001345c - /// capture/compare register 6 - pub const CCR6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); - - /// address: 0x40013460 - /// option registers - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM8_ETR_ADC2 remapping - /// capability - TIM8_ETR_ADC2_RMP: u2, - /// TIM8_ETR_ADC3 remapping - /// capability - TIM8_ETR_ADC3_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x60); - }; - /// Analog-to-Digital Converter - pub const ADC1 = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000000 - /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDY - ADRDY: u1, - /// EOSMP - EOSMP: u1, - /// EOC - EOC: u1, - /// EOS - EOS: u1, - /// OVR - OVR: u1, - /// JEOC - JEOC: u1, - /// JEOS - JEOS: u1, - /// AWD1 - AWD1: u1, - /// AWD2 - AWD2: u1, - /// AWD3 - AWD3: u1, - /// JQOVF - JQOVF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x0); - - /// address: 0x50000004 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDYIE - ADRDYIE: u1, - /// EOSMPIE - EOSMPIE: u1, - /// EOCIE - EOCIE: u1, - /// EOSIE - EOSIE: u1, - /// OVRIE - OVRIE: u1, - /// JEOCIE - JEOCIE: u1, - /// JEOSIE - JEOSIE: u1, - /// AWD1IE - AWD1IE: u1, - /// AWD2IE - AWD2IE: u1, - /// AWD3IE - AWD3IE: u1, - /// JQOVFIE - JQOVFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x50000008 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADEN - ADEN: u1, - /// ADDIS - ADDIS: u1, - /// ADSTART - ADSTART: u1, - /// JADSTART - JADSTART: u1, - /// ADSTP - ADSTP: u1, - /// JADSTP - JADSTP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADVREGEN - ADVREGEN: u1, - /// DEEPPWD - DEEPPWD: u1, - /// ADCALDIF - ADCALDIF: u1, - /// ADCAL - ADCAL: u1, - }), base_address + 0x8); - - /// address: 0x5000000c - /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMAEN - DMAEN: u1, - /// DMACFG - DMACFG: u1, - reserved0: u1, - /// RES - RES: u2, - /// ALIGN - ALIGN: u1, - /// EXTSEL - EXTSEL: u4, - /// EXTEN - EXTEN: u2, - /// OVRMOD - OVRMOD: u1, - /// CONT - CONT: u1, - /// AUTDLY - AUTDLY: u1, - /// AUTOFF - AUTOFF: u1, - /// DISCEN - DISCEN: u1, - /// DISCNUM - DISCNUM: u3, - /// JDISCEN - JDISCEN: u1, - /// JQM - JQM: u1, - /// AWD1SGL - AWD1SGL: u1, - /// AWD1EN - AWD1EN: u1, - /// JAWD1EN - JAWD1EN: u1, - /// JAUTO - JAUTO: u1, - /// AWDCH1CH - AWDCH1CH: u5, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x50000014 - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// SMP1 - SMP1: u3, - /// SMP2 - SMP2: u3, - /// SMP3 - SMP3: u3, - /// SMP4 - SMP4: u3, - /// SMP5 - SMP5: u3, - /// SMP6 - SMP6: u3, - /// SMP7 - SMP7: u3, - /// SMP8 - SMP8: u3, - /// SMP9 - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x50000018 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SMP10 - SMP10: u3, - /// SMP11 - SMP11: u3, - /// SMP12 - SMP12: u3, - /// SMP13 - SMP13: u3, - /// SMP14 - SMP14: u3, - /// SMP15 - SMP15: u3, - /// SMP16 - SMP16: u3, - /// SMP17 - SMP17: u3, - /// SMP18 - SMP18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x50000020 - /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT1 - LT1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// HT1 - HT1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x50000024 - /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT2 - LT2: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT2 - HT2: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x50000028 - /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT3 - LT3: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT3 - HT3: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x28); - - /// address: 0x50000030 - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// L3 - L3: u4, - reserved0: u1, - reserved1: u1, - /// SQ1 - SQ1: u5, - reserved2: u1, - /// SQ2 - SQ2: u5, - reserved3: u1, - /// SQ3 - SQ3: u5, - reserved4: u1, - /// SQ4 - SQ4: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x30); - - /// address: 0x50000034 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ5 - SQ5: u5, - reserved0: u1, - /// SQ6 - SQ6: u5, - reserved1: u1, - /// SQ7 - SQ7: u5, - reserved2: u1, - /// SQ8 - SQ8: u5, - reserved3: u1, - /// SQ9 - SQ9: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x34); - - /// address: 0x50000038 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ10 - SQ10: u5, - reserved0: u1, - /// SQ11 - SQ11: u5, - reserved1: u1, - /// SQ12 - SQ12: u5, - reserved2: u1, - /// SQ13 - SQ13: u5, - reserved3: u1, - /// SQ14 - SQ14: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x38); - - /// address: 0x5000003c - /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ15 - SQ15: u5, - reserved0: u1, - /// SQ16 - SQ16: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x3c); - - /// address: 0x50000040 - /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// regularDATA - regularDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x5000004c - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// JL - JL: u2, - /// JEXTSEL - JEXTSEL: u4, - /// JEXTEN - JEXTEN: u2, - /// JSQ1 - JSQ1: u5, - reserved0: u1, - /// JSQ2 - JSQ2: u5, - reserved1: u1, - /// JSQ3 - JSQ3: u5, - reserved2: u1, - /// JSQ4 - JSQ4: u5, - padding0: u1, - }), base_address + 0x4c); - - /// address: 0x50000060 - /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET1 - OFFSET1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET1_CH - OFFSET1_CH: u5, - /// OFFSET1_EN - OFFSET1_EN: u1, - }), base_address + 0x60); - - /// address: 0x50000064 - /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET2 - OFFSET2: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET2_CH - OFFSET2_CH: u5, - /// OFFSET2_EN - OFFSET2_EN: u1, - }), base_address + 0x64); - - /// address: 0x50000068 - /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET3 - OFFSET3: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET3_CH - OFFSET3_CH: u5, - /// OFFSET3_EN - OFFSET3_EN: u1, - }), base_address + 0x68); - - /// address: 0x5000006c - /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET4 - OFFSET4: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET4_CH - OFFSET4_CH: u5, - /// OFFSET4_EN - OFFSET4_EN: u1, - }), base_address + 0x6c); - - /// address: 0x50000080 - /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA1 - JDATA1: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x80); - - /// address: 0x50000084 - /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA2 - JDATA2: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x50000088 - /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA3 - JDATA3: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x88); - - /// address: 0x5000008c - /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA4 - JDATA4: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x500000a0 - /// Analog Watchdog 2 Configuration - /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD2CH - AWD2CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa0); - - /// address: 0x500000a4 - /// Analog Watchdog 3 Configuration - /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD3CH - AWD3CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa4); - - /// address: 0x500000b0 - /// Differential Mode Selection Register - /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Differential mode for channels 15 to - /// 1 - DIFSEL_1_15: u15, - /// Differential mode for channels 18 to - /// 16 - DIFSEL_16_18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xb0); - - /// address: 0x500000b4 - /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { - /// CALFACT_S - CALFACT_S: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// CALFACT_D - CALFACT_D: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xb4); - }; - pub const ADC2 = struct { - pub const base_address = 0x50000100; - - /// address: 0x50000100 - /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDY - ADRDY: u1, - /// EOSMP - EOSMP: u1, - /// EOC - EOC: u1, - /// EOS - EOS: u1, - /// OVR - OVR: u1, - /// JEOC - JEOC: u1, - /// JEOS - JEOS: u1, - /// AWD1 - AWD1: u1, - /// AWD2 - AWD2: u1, - /// AWD3 - AWD3: u1, - /// JQOVF - JQOVF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x0); - - /// address: 0x50000104 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDYIE - ADRDYIE: u1, - /// EOSMPIE - EOSMPIE: u1, - /// EOCIE - EOCIE: u1, - /// EOSIE - EOSIE: u1, - /// OVRIE - OVRIE: u1, - /// JEOCIE - JEOCIE: u1, - /// JEOSIE - JEOSIE: u1, - /// AWD1IE - AWD1IE: u1, - /// AWD2IE - AWD2IE: u1, - /// AWD3IE - AWD3IE: u1, - /// JQOVFIE - JQOVFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x50000108 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADEN - ADEN: u1, - /// ADDIS - ADDIS: u1, - /// ADSTART - ADSTART: u1, - /// JADSTART - JADSTART: u1, - /// ADSTP - ADSTP: u1, - /// JADSTP - JADSTP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADVREGEN - ADVREGEN: u1, - /// DEEPPWD - DEEPPWD: u1, - /// ADCALDIF - ADCALDIF: u1, - /// ADCAL - ADCAL: u1, - }), base_address + 0x8); - - /// address: 0x5000010c - /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMAEN - DMAEN: u1, - /// DMACFG - DMACFG: u1, - reserved0: u1, - /// RES - RES: u2, - /// ALIGN - ALIGN: u1, - /// EXTSEL - EXTSEL: u4, - /// EXTEN - EXTEN: u2, - /// OVRMOD - OVRMOD: u1, - /// CONT - CONT: u1, - /// AUTDLY - AUTDLY: u1, - /// AUTOFF - AUTOFF: u1, - /// DISCEN - DISCEN: u1, - /// DISCNUM - DISCNUM: u3, - /// JDISCEN - JDISCEN: u1, - /// JQM - JQM: u1, - /// AWD1SGL - AWD1SGL: u1, - /// AWD1EN - AWD1EN: u1, - /// JAWD1EN - JAWD1EN: u1, - /// JAUTO - JAUTO: u1, - /// AWDCH1CH - AWDCH1CH: u5, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x50000114 - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// SMP1 - SMP1: u3, - /// SMP2 - SMP2: u3, - /// SMP3 - SMP3: u3, - /// SMP4 - SMP4: u3, - /// SMP5 - SMP5: u3, - /// SMP6 - SMP6: u3, - /// SMP7 - SMP7: u3, - /// SMP8 - SMP8: u3, - /// SMP9 - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x50000118 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SMP10 - SMP10: u3, - /// SMP11 - SMP11: u3, - /// SMP12 - SMP12: u3, - /// SMP13 - SMP13: u3, - /// SMP14 - SMP14: u3, - /// SMP15 - SMP15: u3, - /// SMP16 - SMP16: u3, - /// SMP17 - SMP17: u3, - /// SMP18 - SMP18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x50000120 - /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT1 - LT1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// HT1 - HT1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x50000124 - /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT2 - LT2: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT2 - HT2: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x50000128 - /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT3 - LT3: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT3 - HT3: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x28); - - /// address: 0x50000130 - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// L3 - L3: u4, - reserved0: u1, - reserved1: u1, - /// SQ1 - SQ1: u5, - reserved2: u1, - /// SQ2 - SQ2: u5, - reserved3: u1, - /// SQ3 - SQ3: u5, - reserved4: u1, - /// SQ4 - SQ4: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x30); - - /// address: 0x50000134 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ5 - SQ5: u5, - reserved0: u1, - /// SQ6 - SQ6: u5, - reserved1: u1, - /// SQ7 - SQ7: u5, - reserved2: u1, - /// SQ8 - SQ8: u5, - reserved3: u1, - /// SQ9 - SQ9: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x34); - - /// address: 0x50000138 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ10 - SQ10: u5, - reserved0: u1, - /// SQ11 - SQ11: u5, - reserved1: u1, - /// SQ12 - SQ12: u5, - reserved2: u1, - /// SQ13 - SQ13: u5, - reserved3: u1, - /// SQ14 - SQ14: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x38); - - /// address: 0x5000013c - /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ15 - SQ15: u5, - reserved0: u1, - /// SQ16 - SQ16: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x3c); - - /// address: 0x50000140 - /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// regularDATA - regularDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x5000014c - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// JL - JL: u2, - /// JEXTSEL - JEXTSEL: u4, - /// JEXTEN - JEXTEN: u2, - /// JSQ1 - JSQ1: u5, - reserved0: u1, - /// JSQ2 - JSQ2: u5, - reserved1: u1, - /// JSQ3 - JSQ3: u5, - reserved2: u1, - /// JSQ4 - JSQ4: u5, - padding0: u1, - }), base_address + 0x4c); - - /// address: 0x50000160 - /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET1 - OFFSET1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET1_CH - OFFSET1_CH: u5, - /// OFFSET1_EN - OFFSET1_EN: u1, - }), base_address + 0x60); - - /// address: 0x50000164 - /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET2 - OFFSET2: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET2_CH - OFFSET2_CH: u5, - /// OFFSET2_EN - OFFSET2_EN: u1, - }), base_address + 0x64); - - /// address: 0x50000168 - /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET3 - OFFSET3: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET3_CH - OFFSET3_CH: u5, - /// OFFSET3_EN - OFFSET3_EN: u1, - }), base_address + 0x68); - - /// address: 0x5000016c - /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET4 - OFFSET4: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET4_CH - OFFSET4_CH: u5, - /// OFFSET4_EN - OFFSET4_EN: u1, - }), base_address + 0x6c); - - /// address: 0x50000180 - /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA1 - JDATA1: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x80); - - /// address: 0x50000184 - /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA2 - JDATA2: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x50000188 - /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA3 - JDATA3: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x88); - - /// address: 0x5000018c - /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA4 - JDATA4: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x500001a0 - /// Analog Watchdog 2 Configuration - /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD2CH - AWD2CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa0); - - /// address: 0x500001a4 - /// Analog Watchdog 3 Configuration - /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD3CH - AWD3CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa4); - - /// address: 0x500001b0 - /// Differential Mode Selection Register - /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Differential mode for channels 15 to - /// 1 - DIFSEL_1_15: u15, - /// Differential mode for channels 18 to - /// 16 - DIFSEL_16_18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xb0); - - /// address: 0x500001b4 - /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { - /// CALFACT_S - CALFACT_S: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// CALFACT_D - CALFACT_D: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xb4); - }; - pub const ADC3 = struct { - pub const base_address = 0x50000400; - - /// address: 0x50000400 - /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDY - ADRDY: u1, - /// EOSMP - EOSMP: u1, - /// EOC - EOC: u1, - /// EOS - EOS: u1, - /// OVR - OVR: u1, - /// JEOC - JEOC: u1, - /// JEOS - JEOS: u1, - /// AWD1 - AWD1: u1, - /// AWD2 - AWD2: u1, - /// AWD3 - AWD3: u1, - /// JQOVF - JQOVF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x0); - - /// address: 0x50000404 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDYIE - ADRDYIE: u1, - /// EOSMPIE - EOSMPIE: u1, - /// EOCIE - EOCIE: u1, - /// EOSIE - EOSIE: u1, - /// OVRIE - OVRIE: u1, - /// JEOCIE - JEOCIE: u1, - /// JEOSIE - JEOSIE: u1, - /// AWD1IE - AWD1IE: u1, - /// AWD2IE - AWD2IE: u1, - /// AWD3IE - AWD3IE: u1, - /// JQOVFIE - JQOVFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x50000408 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADEN - ADEN: u1, - /// ADDIS - ADDIS: u1, - /// ADSTART - ADSTART: u1, - /// JADSTART - JADSTART: u1, - /// ADSTP - ADSTP: u1, - /// JADSTP - JADSTP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADVREGEN - ADVREGEN: u1, - /// DEEPPWD - DEEPPWD: u1, - /// ADCALDIF - ADCALDIF: u1, - /// ADCAL - ADCAL: u1, - }), base_address + 0x8); - - /// address: 0x5000040c - /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMAEN - DMAEN: u1, - /// DMACFG - DMACFG: u1, - reserved0: u1, - /// RES - RES: u2, - /// ALIGN - ALIGN: u1, - /// EXTSEL - EXTSEL: u4, - /// EXTEN - EXTEN: u2, - /// OVRMOD - OVRMOD: u1, - /// CONT - CONT: u1, - /// AUTDLY - AUTDLY: u1, - /// AUTOFF - AUTOFF: u1, - /// DISCEN - DISCEN: u1, - /// DISCNUM - DISCNUM: u3, - /// JDISCEN - JDISCEN: u1, - /// JQM - JQM: u1, - /// AWD1SGL - AWD1SGL: u1, - /// AWD1EN - AWD1EN: u1, - /// JAWD1EN - JAWD1EN: u1, - /// JAUTO - JAUTO: u1, - /// AWDCH1CH - AWDCH1CH: u5, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x50000414 - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// SMP1 - SMP1: u3, - /// SMP2 - SMP2: u3, - /// SMP3 - SMP3: u3, - /// SMP4 - SMP4: u3, - /// SMP5 - SMP5: u3, - /// SMP6 - SMP6: u3, - /// SMP7 - SMP7: u3, - /// SMP8 - SMP8: u3, - /// SMP9 - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x50000418 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SMP10 - SMP10: u3, - /// SMP11 - SMP11: u3, - /// SMP12 - SMP12: u3, - /// SMP13 - SMP13: u3, - /// SMP14 - SMP14: u3, - /// SMP15 - SMP15: u3, - /// SMP16 - SMP16: u3, - /// SMP17 - SMP17: u3, - /// SMP18 - SMP18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x50000420 - /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT1 - LT1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// HT1 - HT1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x50000424 - /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT2 - LT2: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT2 - HT2: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x50000428 - /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT3 - LT3: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT3 - HT3: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x28); - - /// address: 0x50000430 - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// L3 - L3: u4, - reserved0: u1, - reserved1: u1, - /// SQ1 - SQ1: u5, - reserved2: u1, - /// SQ2 - SQ2: u5, - reserved3: u1, - /// SQ3 - SQ3: u5, - reserved4: u1, - /// SQ4 - SQ4: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x30); - - /// address: 0x50000434 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ5 - SQ5: u5, - reserved0: u1, - /// SQ6 - SQ6: u5, - reserved1: u1, - /// SQ7 - SQ7: u5, - reserved2: u1, - /// SQ8 - SQ8: u5, - reserved3: u1, - /// SQ9 - SQ9: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x34); - - /// address: 0x50000438 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ10 - SQ10: u5, - reserved0: u1, - /// SQ11 - SQ11: u5, - reserved1: u1, - /// SQ12 - SQ12: u5, - reserved2: u1, - /// SQ13 - SQ13: u5, - reserved3: u1, - /// SQ14 - SQ14: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x38); - - /// address: 0x5000043c - /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ15 - SQ15: u5, - reserved0: u1, - /// SQ16 - SQ16: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x3c); - - /// address: 0x50000440 - /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// regularDATA - regularDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x5000044c - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// JL - JL: u2, - /// JEXTSEL - JEXTSEL: u4, - /// JEXTEN - JEXTEN: u2, - /// JSQ1 - JSQ1: u5, - reserved0: u1, - /// JSQ2 - JSQ2: u5, - reserved1: u1, - /// JSQ3 - JSQ3: u5, - reserved2: u1, - /// JSQ4 - JSQ4: u5, - padding0: u1, - }), base_address + 0x4c); - - /// address: 0x50000460 - /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET1 - OFFSET1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET1_CH - OFFSET1_CH: u5, - /// OFFSET1_EN - OFFSET1_EN: u1, - }), base_address + 0x60); - - /// address: 0x50000464 - /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET2 - OFFSET2: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET2_CH - OFFSET2_CH: u5, - /// OFFSET2_EN - OFFSET2_EN: u1, - }), base_address + 0x64); - - /// address: 0x50000468 - /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET3 - OFFSET3: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET3_CH - OFFSET3_CH: u5, - /// OFFSET3_EN - OFFSET3_EN: u1, - }), base_address + 0x68); - - /// address: 0x5000046c - /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET4 - OFFSET4: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET4_CH - OFFSET4_CH: u5, - /// OFFSET4_EN - OFFSET4_EN: u1, - }), base_address + 0x6c); - - /// address: 0x50000480 - /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA1 - JDATA1: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x80); - - /// address: 0x50000484 - /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA2 - JDATA2: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x50000488 - /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA3 - JDATA3: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x88); - - /// address: 0x5000048c - /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA4 - JDATA4: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x500004a0 - /// Analog Watchdog 2 Configuration - /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD2CH - AWD2CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa0); - - /// address: 0x500004a4 - /// Analog Watchdog 3 Configuration - /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD3CH - AWD3CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa4); - - /// address: 0x500004b0 - /// Differential Mode Selection Register - /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Differential mode for channels 15 to - /// 1 - DIFSEL_1_15: u15, - /// Differential mode for channels 18 to - /// 16 - DIFSEL_16_18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xb0); - - /// address: 0x500004b4 - /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { - /// CALFACT_S - CALFACT_S: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// CALFACT_D - CALFACT_D: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xb4); - }; - pub const ADC4 = struct { - pub const base_address = 0x50000500; - - /// address: 0x50000500 - /// interrupt and status register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDY - ADRDY: u1, - /// EOSMP - EOSMP: u1, - /// EOC - EOC: u1, - /// EOS - EOS: u1, - /// OVR - OVR: u1, - /// JEOC - JEOC: u1, - /// JEOS - JEOS: u1, - /// AWD1 - AWD1: u1, - /// AWD2 - AWD2: u1, - /// AWD3 - AWD3: u1, - /// JQOVF - JQOVF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x0); - - /// address: 0x50000504 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// ADRDYIE - ADRDYIE: u1, - /// EOSMPIE - EOSMPIE: u1, - /// EOCIE - EOCIE: u1, - /// EOSIE - EOSIE: u1, - /// OVRIE - OVRIE: u1, - /// JEOCIE - JEOCIE: u1, - /// JEOSIE - JEOSIE: u1, - /// AWD1IE - AWD1IE: u1, - /// AWD2IE - AWD2IE: u1, - /// AWD3IE - AWD3IE: u1, - /// JQOVFIE - JQOVFIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x4); - - /// address: 0x50000508 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADEN - ADEN: u1, - /// ADDIS - ADDIS: u1, - /// ADSTART - ADSTART: u1, - /// JADSTART - JADSTART: u1, - /// ADSTP - ADSTP: u1, - /// JADSTP - JADSTP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// ADVREGEN - ADVREGEN: u1, - /// DEEPPWD - DEEPPWD: u1, - /// ADCALDIF - ADCALDIF: u1, - /// ADCAL - ADCAL: u1, - }), base_address + 0x8); - - /// address: 0x5000050c - /// configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMAEN - DMAEN: u1, - /// DMACFG - DMACFG: u1, - reserved0: u1, - /// RES - RES: u2, - /// ALIGN - ALIGN: u1, - /// EXTSEL - EXTSEL: u4, - /// EXTEN - EXTEN: u2, - /// OVRMOD - OVRMOD: u1, - /// CONT - CONT: u1, - /// AUTDLY - AUTDLY: u1, - /// AUTOFF - AUTOFF: u1, - /// DISCEN - DISCEN: u1, - /// DISCNUM - DISCNUM: u3, - /// JDISCEN - JDISCEN: u1, - /// JQM - JQM: u1, - /// AWD1SGL - AWD1SGL: u1, - /// AWD1EN - AWD1EN: u1, - /// JAWD1EN - JAWD1EN: u1, - /// JAUTO - JAUTO: u1, - /// AWDCH1CH - AWDCH1CH: u5, - padding0: u1, - }), base_address + 0xc); - - /// address: 0x50000514 - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// SMP1 - SMP1: u3, - /// SMP2 - SMP2: u3, - /// SMP3 - SMP3: u3, - /// SMP4 - SMP4: u3, - /// SMP5 - SMP5: u3, - /// SMP6 - SMP6: u3, - /// SMP7 - SMP7: u3, - /// SMP8 - SMP8: u3, - /// SMP9 - SMP9: u3, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x50000518 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SMP10 - SMP10: u3, - /// SMP11 - SMP11: u3, - /// SMP12 - SMP12: u3, - /// SMP13 - SMP13: u3, - /// SMP14 - SMP14: u3, - /// SMP15 - SMP15: u3, - /// SMP16 - SMP16: u3, - /// SMP17 - SMP17: u3, - /// SMP18 - SMP18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x50000520 - /// watchdog threshold register 1 - pub const TR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT1 - LT1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// HT1 - HT1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x50000524 - /// watchdog threshold register - pub const TR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT2 - LT2: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT2 - HT2: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x50000528 - /// watchdog threshold register 3 - pub const TR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// LT3 - LT3: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// HT3 - HT3: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x28); - - /// address: 0x50000530 - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// L3 - L3: u4, - reserved0: u1, - reserved1: u1, - /// SQ1 - SQ1: u5, - reserved2: u1, - /// SQ2 - SQ2: u5, - reserved3: u1, - /// SQ3 - SQ3: u5, - reserved4: u1, - /// SQ4 - SQ4: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x30); - - /// address: 0x50000534 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ5 - SQ5: u5, - reserved0: u1, - /// SQ6 - SQ6: u5, - reserved1: u1, - /// SQ7 - SQ7: u5, - reserved2: u1, - /// SQ8 - SQ8: u5, - reserved3: u1, - /// SQ9 - SQ9: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x34); - - /// address: 0x50000538 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ10 - SQ10: u5, - reserved0: u1, - /// SQ11 - SQ11: u5, - reserved1: u1, - /// SQ12 - SQ12: u5, - reserved2: u1, - /// SQ13 - SQ13: u5, - reserved3: u1, - /// SQ14 - SQ14: u5, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x38); - - /// address: 0x5000053c - /// regular sequence register 4 - pub const SQR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// SQ15 - SQ15: u5, - reserved0: u1, - /// SQ16 - SQ16: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x3c); - - /// address: 0x50000540 - /// regular Data Register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// regularDATA - regularDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x5000054c - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// JL - JL: u2, - /// JEXTSEL - JEXTSEL: u4, - /// JEXTEN - JEXTEN: u2, - /// JSQ1 - JSQ1: u5, - reserved0: u1, - /// JSQ2 - JSQ2: u5, - reserved1: u1, - /// JSQ3 - JSQ3: u5, - reserved2: u1, - /// JSQ4 - JSQ4: u5, - padding0: u1, - }), base_address + 0x4c); - - /// address: 0x50000560 - /// offset register 1 - pub const OFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET1 - OFFSET1: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET1_CH - OFFSET1_CH: u5, - /// OFFSET1_EN - OFFSET1_EN: u1, - }), base_address + 0x60); - - /// address: 0x50000564 - /// offset register 2 - pub const OFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET2 - OFFSET2: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET2_CH - OFFSET2_CH: u5, - /// OFFSET2_EN - OFFSET2_EN: u1, - }), base_address + 0x64); - - /// address: 0x50000568 - /// offset register 3 - pub const OFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET3 - OFFSET3: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET3_CH - OFFSET3_CH: u5, - /// OFFSET3_EN - OFFSET3_EN: u1, - }), base_address + 0x68); - - /// address: 0x5000056c - /// offset register 4 - pub const OFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// OFFSET4 - OFFSET4: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// OFFSET4_CH - OFFSET4_CH: u5, - /// OFFSET4_EN - OFFSET4_EN: u1, - }), base_address + 0x6c); - - /// address: 0x50000580 - /// injected data register 1 - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA1 - JDATA1: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x80); - - /// address: 0x50000584 - /// injected data register 2 - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA2 - JDATA2: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x84); - - /// address: 0x50000588 - /// injected data register 3 - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA3 - JDATA3: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x88); - - /// address: 0x5000058c - /// injected data register 4 - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// JDATA4 - JDATA4: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x500005a0 - /// Analog Watchdog 2 Configuration - /// Register - pub const AWD2CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD2CH - AWD2CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa0); - - /// address: 0x500005a4 - /// Analog Watchdog 3 Configuration - /// Register - pub const AWD3CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// AWD3CH - AWD3CH: u18, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xa4); - - /// address: 0x500005b0 - /// Differential Mode Selection Register - /// 2 - pub const DIFSEL = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Differential mode for channels 15 to - /// 1 - DIFSEL_1_15: u15, - /// Differential mode for channels 18 to - /// 16 - DIFSEL_16_18: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xb0); - - /// address: 0x500005b4 - /// Calibration Factors - pub const CALFACT = @intToPtr(*volatile Mmio(32, packed struct { - /// CALFACT_S - CALFACT_S: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// CALFACT_D - CALFACT_D: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xb4); - }; - /// Analog-to-Digital Converter - pub const ADC1_2 = struct { - pub const base_address = 0x50000300; - - /// address: 0x50000300 - /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDRDY_MST - ADDRDY_MST: u1, - /// EOSMP_MST - EOSMP_MST: u1, - /// EOC_MST - EOC_MST: u1, - /// EOS_MST - EOS_MST: u1, - /// OVR_MST - OVR_MST: u1, - /// JEOC_MST - JEOC_MST: u1, - /// JEOS_MST - JEOS_MST: u1, - /// AWD1_MST - AWD1_MST: u1, - /// AWD2_MST - AWD2_MST: u1, - /// AWD3_MST - AWD3_MST: u1, - /// JQOVF_MST - JQOVF_MST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// ADRDY_SLV - ADRDY_SLV: u1, - /// EOSMP_SLV - EOSMP_SLV: u1, - /// End of regular conversion of the slave - /// ADC - EOC_SLV: u1, - /// End of regular sequence flag of the - /// slave ADC - EOS_SLV: u1, - /// Overrun flag of the slave - /// ADC - OVR_SLV: u1, - /// End of injected conversion flag of the - /// slave ADC - JEOC_SLV: u1, - /// End of injected sequence flag of the - /// slave ADC - JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave - /// ADC - AWD1_SLV: u1, - /// Analog watchdog 2 flag of the slave - /// ADC - AWD2_SLV: u1, - /// Analog watchdog 3 flag of the slave - /// ADC - AWD3_SLV: u1, - /// Injected Context Queue Overflow flag of - /// the slave ADC - JQOVF_SLV: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x0); - - /// address: 0x50000308 - /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Multi ADC mode selection - MULT: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Delay between 2 sampling - /// phases - DELAY: u4, - reserved3: u1, - /// DMA configuration (for multi-ADC - /// mode) - DMACFG: u1, - /// Direct memory access mode for multi ADC - /// mode - MDMA: u2, - /// ADC clock mode - CKMODE: u2, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x5000030c - /// ADC common regular data register for dual - /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data of the master - /// ADC - RDATA_MST: u16, - /// Regular data of the slave - /// ADC - RDATA_SLV: u16, - }), base_address + 0xc); - }; - pub const ADC3_4 = struct { - pub const base_address = 0x50000700; - - /// address: 0x50000700 - /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDRDY_MST - ADDRDY_MST: u1, - /// EOSMP_MST - EOSMP_MST: u1, - /// EOC_MST - EOC_MST: u1, - /// EOS_MST - EOS_MST: u1, - /// OVR_MST - OVR_MST: u1, - /// JEOC_MST - JEOC_MST: u1, - /// JEOS_MST - JEOS_MST: u1, - /// AWD1_MST - AWD1_MST: u1, - /// AWD2_MST - AWD2_MST: u1, - /// AWD3_MST - AWD3_MST: u1, - /// JQOVF_MST - JQOVF_MST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// ADRDY_SLV - ADRDY_SLV: u1, - /// EOSMP_SLV - EOSMP_SLV: u1, - /// End of regular conversion of the slave - /// ADC - EOC_SLV: u1, - /// End of regular sequence flag of the - /// slave ADC - EOS_SLV: u1, - /// Overrun flag of the slave - /// ADC - OVR_SLV: u1, - /// End of injected conversion flag of the - /// slave ADC - JEOC_SLV: u1, - /// End of injected sequence flag of the - /// slave ADC - JEOS_SLV: u1, - /// Analog watchdog 1 flag of the slave - /// ADC - AWD1_SLV: u1, - /// Analog watchdog 2 flag of the slave - /// ADC - AWD2_SLV: u1, - /// Analog watchdog 3 flag of the slave - /// ADC - AWD3_SLV: u1, - /// Injected Context Queue Overflow flag of - /// the slave ADC - JQOVF_SLV: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x0); - - /// address: 0x50000708 - /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Multi ADC mode selection - MULT: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Delay between 2 sampling - /// phases - DELAY: u4, - reserved3: u1, - /// DMA configuration (for multi-ADC - /// mode) - DMACFG: u1, - /// Direct memory access mode for multi ADC - /// mode - MDMA: u2, - /// ADC clock mode - CKMODE: u2, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// VREFINT enable - VREFEN: u1, - /// Temperature sensor enable - TSEN: u1, - /// VBAT enable - VBATEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8); - - /// address: 0x5000070c - /// ADC common regular data register for dual - /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data of the master - /// ADC - RDATA_MST: u16, - /// Regular data of the slave - /// ADC - RDATA_SLV: u16, - }), base_address + 0xc); - }; - /// System configuration controller _Comparator and - /// Operational amplifier - pub const SYSCFG_COMP_OPAMP = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// configuration register 1 - pub const SYSCFG_CFGR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory mapping selection - /// bits - MEM_MODE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// USB interrupt remap - USB_IT_RMP: u1, - /// Timer 1 ITR3 selection - TIM1_ITR_RMP: u1, - /// DAC trigger remap (when TSEL = - /// 001) - DAC_TRIG_RMP: u1, - /// ADC24 DMA remapping bit - ADC24_DMA_RMP: u1, - reserved3: u1, - reserved4: u1, - /// TIM16 DMA request remapping - /// bit - TIM16_DMA_RMP: u1, - /// TIM17 DMA request remapping - /// bit - TIM17_DMA_RMP: u1, - /// TIM6 and DAC1 DMA request remapping - /// bit - TIM6_DAC1_DMA_RMP: u1, - /// TIM7 and DAC2 DMA request remapping - /// bit - TIM7_DAC2_DMA_RMP: u1, - reserved5: u1, - /// Fast Mode Plus (FM+) driving capability - /// activation bits. - I2C_PB6_FM: u1, - /// Fast Mode Plus (FM+) driving capability - /// activation bits. - I2C_PB7_FM: u1, - /// Fast Mode Plus (FM+) driving capability - /// activation bits. - I2C_PB8_FM: u1, - /// Fast Mode Plus (FM+) driving capability - /// activation bits. - I2C_PB9_FM: u1, - /// I2C1 Fast Mode Plus - I2C1_FM: u1, - /// I2C2 Fast Mode Plus - I2C2_FM: u1, - /// Encoder mode - ENCODER_MODE: u2, - reserved6: u1, - reserved7: u1, - /// Interrupt enable bits from - /// FPU - FPU_IT: u6, - }), base_address + 0x0); - - /// address: 0x40010008 - /// external interrupt configuration register - /// 1 - pub const SYSCFG_EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 0 configuration bits - EXTI0: u4, - /// EXTI 1 configuration bits - EXTI1: u4, - /// EXTI 2 configuration bits - EXTI2: u4, - /// EXTI 3 configuration bits - EXTI3: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001000c - /// external interrupt configuration register - /// 2 - pub const SYSCFG_EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 4 configuration bits - EXTI4: u4, - /// EXTI 5 configuration bits - EXTI5: u4, - /// EXTI 6 configuration bits - EXTI6: u4, - /// EXTI 7 configuration bits - EXTI7: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// external interrupt configuration register - /// 3 - pub const SYSCFG_EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 8 configuration bits - EXTI8: u4, - /// EXTI 9 configuration bits - EXTI9: u4, - /// EXTI 10 configuration bits - EXTI10: u4, - /// EXTI 11 configuration bits - EXTI11: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40010014 - /// external interrupt configuration register - /// 4 - pub const SYSCFG_EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI 12 configuration bits - EXTI12: u4, - /// EXTI 13 configuration bits - EXTI13: u4, - /// EXTI 14 configuration bits - EXTI14: u4, - /// EXTI 15 configuration bits - EXTI15: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40010018 - /// configuration register 2 - pub const SYSCFG_CFGR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Cortex-M0 LOCKUP bit enable - /// bit - LOCUP_LOCK: u1, - /// SRAM parity lock bit - SRAM_PARITY_LOCK: u1, - /// PVD lock enable bit - PVD_LOCK: u1, - reserved0: u1, - /// Bypass address bit 29 in parity - /// calculation - BYP_ADD_PAR: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// SRAM parity flag - SRAM_PEF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x18); - - /// address: 0x40010004 - /// CCM SRAM protection register - pub const SYSCFG_RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// CCM SRAM page write protection - /// bit - PAGE0_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE1_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE2_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE3_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE4_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE5_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE6_WP: u1, - /// CCM SRAM page write protection - /// bit - PAGE7_WP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x4001001c - /// control and status register - pub const COMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 1 enable - COMP1EN: u1, - /// COMP1_INP_DAC - COMP1_INP_DAC: u1, - /// Comparator 1 mode - COMP1MODE: u2, - /// Comparator 1 inverting input - /// selection - COMP1INSEL: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Comparator 1 output - /// selection - COMP1_OUT_SEL: u4, - reserved3: u1, - /// Comparator 1 output - /// polarity - COMP1POL: u1, - /// Comparator 1 hysteresis - COMP1HYST: u2, - /// Comparator 1 blanking - /// source - COMP1_BLANKING: u3, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Comparator 1 output - COMP1OUT: u1, - /// Comparator 1 lock - COMP1LOCK: u1, - }), base_address + 0x1c); - - /// address: 0x40010020 - /// control and status register - pub const COMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 2 enable - COMP2EN: u1, - reserved0: u1, - /// Comparator 2 mode - COMP2MODE: u2, - /// Comparator 2 inverting input - /// selection - COMP2INSEL: u3, - /// Comparator 2 non inverted input - /// selection - COMP2INPSEL: u1, - reserved1: u1, - /// Comparator 1inverting input - /// selection - COMP2INMSEL: u1, - /// Comparator 2 output - /// selection - COMP2_OUT_SEL: u4, - reserved2: u1, - /// Comparator 2 output - /// polarity - COMP2POL: u1, - /// Comparator 2 hysteresis - COMP2HYST: u2, - /// Comparator 2 blanking - /// source - COMP2_BLANKING: u3, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Comparator 2 lock - COMP2LOCK: u1, - }), base_address + 0x20); - - /// address: 0x40010024 - /// control and status register - pub const COMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 3 enable - COMP3EN: u1, - reserved0: u1, - /// Comparator 3 mode - COMP3MODE: u2, - /// Comparator 3 inverting input - /// selection - COMP3INSEL: u3, - /// Comparator 3 non inverted input - /// selection - COMP3INPSEL: u1, - reserved1: u1, - reserved2: u1, - /// Comparator 3 output - /// selection - COMP3_OUT_SEL: u4, - reserved3: u1, - /// Comparator 3 output - /// polarity - COMP3POL: u1, - /// Comparator 3 hysteresis - COMP3HYST: u2, - /// Comparator 3 blanking - /// source - COMP3_BLANKING: u3, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Comparator 3 output - COMP3OUT: u1, - /// Comparator 3 lock - COMP3LOCK: u1, - }), base_address + 0x24); - - /// address: 0x40010028 - /// control and status register - pub const COMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 4 enable - COMP4EN: u1, - reserved0: u1, - /// Comparator 4 mode - COMP4MODE: u2, - /// Comparator 4 inverting input - /// selection - COMP4INSEL: u3, - /// Comparator 4 non inverted input - /// selection - COMP4INPSEL: u1, - reserved1: u1, - /// Comparator 4 window mode - COM4WINMODE: u1, - /// Comparator 4 output - /// selection - COMP4_OUT_SEL: u4, - reserved2: u1, - /// Comparator 4 output - /// polarity - COMP4POL: u1, - /// Comparator 4 hysteresis - COMP4HYST: u2, - /// Comparator 4 blanking - /// source - COMP4_BLANKING: u3, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Comparator 4 output - COMP4OUT: u1, - /// Comparator 4 lock - COMP4LOCK: u1, - }), base_address + 0x28); - - /// address: 0x4001002c - /// control and status register - pub const COMP5_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 5 enable - COMP5EN: u1, - reserved0: u1, - /// Comparator 5 mode - COMP5MODE: u2, - /// Comparator 5 inverting input - /// selection - COMP5INSEL: u3, - /// Comparator 5 non inverted input - /// selection - COMP5INPSEL: u1, - reserved1: u1, - reserved2: u1, - /// Comparator 5 output - /// selection - COMP5_OUT_SEL: u4, - reserved3: u1, - /// Comparator 5 output - /// polarity - COMP5POL: u1, - /// Comparator 5 hysteresis - COMP5HYST: u2, - /// Comparator 5 blanking - /// source - COMP5_BLANKING: u3, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Comparator51 output - COMP5OUT: u1, - /// Comparator 5 lock - COMP5LOCK: u1, - }), base_address + 0x2c); - - /// address: 0x40010030 - /// control and status register - pub const COMP6_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 6 enable - COMP6EN: u1, - reserved0: u1, - /// Comparator 6 mode - COMP6MODE: u2, - /// Comparator 6 inverting input - /// selection - COMP6INSEL: u3, - /// Comparator 6 non inverted input - /// selection - COMP6INPSEL: u1, - reserved1: u1, - /// Comparator 6 window mode - COM6WINMODE: u1, - /// Comparator 6 output - /// selection - COMP6_OUT_SEL: u4, - reserved2: u1, - /// Comparator 6 output - /// polarity - COMP6POL: u1, - /// Comparator 6 hysteresis - COMP6HYST: u2, - /// Comparator 6 blanking - /// source - COMP6_BLANKING: u3, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Comparator 6 output - COMP6OUT: u1, - /// Comparator 6 lock - COMP6LOCK: u1, - }), base_address + 0x30); - - /// address: 0x40010034 - /// control and status register - pub const COMP7_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Comparator 7 enable - COMP7EN: u1, - reserved0: u1, - /// Comparator 7 mode - COMP7MODE: u2, - /// Comparator 7 inverting input - /// selection - COMP7INSEL: u3, - /// Comparator 7 non inverted input - /// selection - COMP7INPSEL: u1, - reserved1: u1, - reserved2: u1, - /// Comparator 7 output - /// selection - COMP7_OUT_SEL: u4, - reserved3: u1, - /// Comparator 7 output - /// polarity - COMP7POL: u1, - /// Comparator 7 hysteresis - COMP7HYST: u2, - /// Comparator 7 blanking - /// source - COMP7_BLANKING: u3, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// Comparator 7 output - COMP7OUT: u1, - /// Comparator 7 lock - COMP7LOCK: u1, - }), base_address + 0x34); - - /// address: 0x40010038 - /// control register - pub const OPAMP1_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// OPAMP1 enable - OPAMP1_EN: u1, - /// FORCE_VP - FORCE_VP: u1, - /// OPAMP1 Non inverting input - /// selection - VP_SEL: u2, - reserved0: u1, - /// OPAMP1 inverting input - /// selection - VM_SEL: u2, - /// Timer controlled Mux mode - /// enable - TCM_EN: u1, - /// OPAMP1 inverting input secondary - /// selection - VMS_SEL: u1, - /// OPAMP1 Non inverting input secondary - /// selection - VPS_SEL: u2, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CALSEL: u2, - /// Gain in PGA mode - PGA_GAIN: u4, - /// User trimming enable - USER_TRIM: u1, - /// Offset trimming value - /// (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value - /// (NMOS) - TRIMOFFSETN: u5, - /// TSTREF - TSTREF: u1, - /// OPAMP 1 ouput status flag - OUTCAL: u1, - /// OPAMP 1 lock - LOCK: u1, - }), base_address + 0x38); - - /// address: 0x4001003c - /// control register - pub const OPAMP2_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// OPAMP2 enable - OPAMP2EN: u1, - /// FORCE_VP - FORCE_VP: u1, - /// OPAMP2 Non inverting input - /// selection - VP_SEL: u2, - reserved0: u1, - /// OPAMP2 inverting input - /// selection - VM_SEL: u2, - /// Timer controlled Mux mode - /// enable - TCM_EN: u1, - /// OPAMP2 inverting input secondary - /// selection - VMS_SEL: u1, - /// OPAMP2 Non inverting input secondary - /// selection - VPS_SEL: u2, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CAL_SEL: u2, - /// Gain in PGA mode - PGA_GAIN: u4, - /// User trimming enable - USER_TRIM: u1, - /// Offset trimming value - /// (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value - /// (NMOS) - TRIMOFFSETN: u5, - /// TSTREF - TSTREF: u1, - /// OPAMP 2 ouput status flag - OUTCAL: u1, - /// OPAMP 2 lock - LOCK: u1, - }), base_address + 0x3c); - - /// address: 0x40010040 - /// control register - pub const OPAMP3_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// OPAMP3 enable - OPAMP3EN: u1, - /// FORCE_VP - FORCE_VP: u1, - /// OPAMP3 Non inverting input - /// selection - VP_SEL: u2, - reserved0: u1, - /// OPAMP3 inverting input - /// selection - VM_SEL: u2, - /// Timer controlled Mux mode - /// enable - TCM_EN: u1, - /// OPAMP3 inverting input secondary - /// selection - VMS_SEL: u1, - /// OPAMP3 Non inverting input secondary - /// selection - VPS_SEL: u2, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CALSEL: u2, - /// Gain in PGA mode - PGA_GAIN: u4, - /// User trimming enable - USER_TRIM: u1, - /// Offset trimming value - /// (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value - /// (NMOS) - TRIMOFFSETN: u5, - /// TSTREF - TSTREF: u1, - /// OPAMP 3 ouput status flag - OUTCAL: u1, - /// OPAMP 3 lock - LOCK: u1, - }), base_address + 0x40); - - /// address: 0x40010044 - /// control register - pub const OPAMP4_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// OPAMP4 enable - OPAMP4EN: u1, - /// FORCE_VP - FORCE_VP: u1, - /// OPAMP4 Non inverting input - /// selection - VP_SEL: u2, - reserved0: u1, - /// OPAMP4 inverting input - /// selection - VM_SEL: u2, - /// Timer controlled Mux mode - /// enable - TCM_EN: u1, - /// OPAMP4 inverting input secondary - /// selection - VMS_SEL: u1, - /// OPAMP4 Non inverting input secondary - /// selection - VPS_SEL: u2, - /// Calibration mode enable - CALON: u1, - /// Calibration selection - CALSEL: u2, - /// Gain in PGA mode - PGA_GAIN: u4, - /// User trimming enable - USER_TRIM: u1, - /// Offset trimming value - /// (PMOS) - TRIMOFFSETP: u5, - /// Offset trimming value - /// (NMOS) - TRIMOFFSETN: u5, - /// TSTREF - TSTREF: u1, - /// OPAMP 4 ouput status flag - OUTCAL: u1, - /// OPAMP 4 lock - LOCK: u1, - }), base_address + 0x44); - }; - /// Flexible memory controller - pub const FMC = struct { - pub const base_address = 0xa0000400; - - /// address: 0xa0000400 - /// SRAM/NOR-Flash chip-select control register - /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - reserved1: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// CBURSTRW - CBURSTRW: u1, - /// CCLKEN - CCLKEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x0); - - /// address: 0xa0000404 - /// SRAM/NOR-Flash chip-select timing register - /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0xa0000408 - /// SRAM/NOR-Flash chip-select control register - /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x8); - - /// address: 0xa000040c - /// SRAM/NOR-Flash chip-select timing register - /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0xa0000410 - /// SRAM/NOR-Flash chip-select control register - /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0xa0000414 - /// SRAM/NOR-Flash chip-select timing register - /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0xa0000418 - /// SRAM/NOR-Flash chip-select control register - /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x18); - - /// address: 0xa000041c - /// SRAM/NOR-Flash chip-select timing register - /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0xa0000460 - /// PC Card/NAND Flash control register - /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x60); - - /// address: 0xa0000464 - /// FIFO status and interrupt register - /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x64); - - /// address: 0xa0000468 - /// Common memory space timing register - /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x68); - - /// address: 0xa000046c - /// Attribute memory space timing register - /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x6c); - - /// address: 0xa0000474 - /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x74); - - /// address: 0xa0000480 - /// PC Card/NAND Flash control register - /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x80); - - /// address: 0xa0000484 - /// FIFO status and interrupt register - /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x84); - - /// address: 0xa0000488 - /// Common memory space timing register - /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x88); - - /// address: 0xa000048c - /// Attribute memory space timing register - /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x8c); - - /// address: 0xa0000494 - /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x94); - - /// address: 0xa00004a0 - /// PC Card/NAND Flash control register - /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0xa0); - - /// address: 0xa00004a4 - /// FIFO status and interrupt register - /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xa4); - - /// address: 0xa00004a8 - /// Common memory space timing register - /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0xa8); - - /// address: 0xa00004ac - /// Attribute memory space timing register - /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0xac); - - /// address: 0xa00004b0 - /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), base_address + 0xb0); - - /// address: 0xa0000504 - /// SRAM/NOR-Flash write timing registers - /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// Bus turnaround phase - /// duration - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x104); - - /// address: 0xa000050c - /// SRAM/NOR-Flash write timing registers - /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// Bus turnaround phase - /// duration - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10c); - - /// address: 0xa0000514 - /// SRAM/NOR-Flash write timing registers - /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// Bus turnaround phase - /// duration - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x114); - - /// address: 0xa000051c - /// SRAM/NOR-Flash write timing registers - /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// Bus turnaround phase - /// duration - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x11c); - }; - /// Nested Vectored Interrupt - /// Controller - pub const NVIC = struct { - pub const base_address = 0xe000e100; - - /// address: 0xe000e100 - /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x0); - - /// address: 0xe000e104 - /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x4); - - /// address: 0xe000e108 - /// Interrupt Set-Enable Register - pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x8); - - /// address: 0xe000e180 - /// Interrupt Clear-Enable - /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x80); - - /// address: 0xe000e184 - /// Interrupt Clear-Enable - /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x84); - - /// address: 0xe000e188 - /// Interrupt Clear-Enable - /// Register - pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x88); - - /// address: 0xe000e200 - /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x100); - - /// address: 0xe000e204 - /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x104); - - /// address: 0xe000e208 - /// Interrupt Set-Pending Register - pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x108); - - /// address: 0xe000e280 - /// Interrupt Clear-Pending - /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x180); - - /// address: 0xe000e284 - /// Interrupt Clear-Pending - /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x184); - - /// address: 0xe000e288 - /// Interrupt Clear-Pending - /// Register - pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x188); - - /// address: 0xe000e300 - /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x200); - - /// address: 0xe000e304 - /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x204); - - /// address: 0xe000e308 - /// Interrupt Active Bit Register - pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x208); - - /// address: 0xe000e400 - /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x300); - - /// address: 0xe000e404 - /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x304); - - /// address: 0xe000e408 - /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x308); - - /// address: 0xe000e40c - /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x30c); - - /// address: 0xe000e410 - /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x310); - - /// address: 0xe000e414 - /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x314); - - /// address: 0xe000e418 - /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x318); - - /// address: 0xe000e41c - /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x31c); - - /// address: 0xe000e420 - /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x320); - - /// address: 0xe000e424 - /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x324); - - /// address: 0xe000e428 - /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x328); - - /// address: 0xe000e42c - /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x32c); - - /// address: 0xe000e430 - /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x330); - - /// address: 0xe000e434 - /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x334); - - /// address: 0xe000e438 - /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x338); - - /// address: 0xe000e43c - /// Interrupt Priority Register - pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x33c); - - /// address: 0xe000e440 - /// Interrupt Priority Register - pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x340); - - /// address: 0xe000e444 - /// Interrupt Priority Register - pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x344); - - /// address: 0xe000e448 - /// Interrupt Priority Register - pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x348); - - /// address: 0xe000e44c - /// Interrupt Priority Register - pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x34c); - - /// address: 0xe000e450 - /// Interrupt Priority Register - pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x350); - }; - /// Floting point unit - pub const FPU = struct { - pub const base_address = 0xe000ef34; - - /// address: 0xe000ef34 - /// Floating-point context control - /// register - pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSPACT - LSPACT: u1, - /// USER - USER: u1, - reserved0: u1, - /// THREAD - THREAD: u1, - /// HFRDY - HFRDY: u1, - /// MMRDY - MMRDY: u1, - /// BFRDY - BFRDY: u1, - reserved1: u1, - /// MONRDY - MONRDY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// LSPEN - LSPEN: u1, - /// ASPEN - ASPEN: u1, - }), base_address + 0x0); - - /// address: 0xe000ef38 - /// Floating-point context address - /// register - pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Location of unpopulated - /// floating-point - ADDRESS: u29, - }), base_address + 0x4); - - /// address: 0xe000ef3c - /// Floating-point status control - /// register - pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Invalid operation cumulative exception - /// bit - IOC: u1, - /// Division by zero cumulative exception - /// bit. - DZC: u1, - /// Overflow cumulative exception - /// bit - OFC: u1, - /// Underflow cumulative exception - /// bit - UFC: u1, - /// Inexact cumulative exception - /// bit - IXC: u1, - reserved0: u1, - reserved1: u1, - /// Input denormal cumulative exception - /// bit. - IDC: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Rounding Mode control - /// field - RMode: u2, - /// Flush-to-zero mode control - /// bit: - FZ: u1, - /// Default NaN mode control - /// bit - DN: u1, - /// Alternative half-precision control - /// bit - AHP: u1, - reserved16: u1, - /// Overflow condition code - /// flag - V: u1, - /// Carry condition code flag - C: u1, - /// Zero condition code flag - Z: u1, - /// Negative condition code - /// flag - N: u1, - }), base_address + 0x8); - }; - /// Memory protection unit - pub const MPU = struct { - pub const base_address = 0xe000ed90; - - /// address: 0xe000ed90 - /// MPU type register - pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Separate flag - SEPARATE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Number of MPU data regions - DREGION: u8, - /// Number of MPU instruction - /// regions - IREGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0xe000ed94 - /// MPU control register - pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Enables the MPU - ENABLE: u1, - /// Enables the operation of MPU during hard - /// fault - HFNMIENA: u1, - /// Enable priviliged software access to - /// default memory map - PRIVDEFENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0xe000ed98 - /// MPU region number register - pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region - REGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0xe000ed9c - /// MPU region base address - /// register - pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region field - REGION: u4, - /// MPU region number valid - VALID: u1, - /// Region base address field - ADDR: u27, - }), base_address + 0xc); - - /// address: 0xe000eda0 - /// MPU region attribute and size - /// register - pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region enable bit. - ENABLE: u1, - /// Size of the MPU protection - /// region - SIZE: u5, - reserved0: u1, - reserved1: u1, - /// Subregion disable bits - SRD: u8, - /// memory attribute - B: u1, - /// memory attribute - C: u1, - /// Shareable memory attribute - S: u1, - /// memory attribute - TEX: u3, - reserved2: u1, - reserved3: u1, - /// Access permission - AP: u3, - reserved4: u1, - /// Instruction access disable - /// bit - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - }; - /// SysTick timer - pub const STK = struct { - pub const base_address = 0xe000e010; - - /// address: 0xe000e010 - /// SysTick control and status - /// register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - ENABLE: u1, - /// SysTick exception request - /// enable - TICKINT: u1, - /// Clock source selection - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// COUNTFLAG - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0xe000e014 - /// SysTick reload value register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - /// RELOAD value - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0xe000e018 - /// SysTick current value register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - /// Current counter value - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0xe000e01c - /// SysTick calibration value - /// register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration value - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// SKEW flag: Indicates whether the TENMS - /// value is exact - SKEW: u1, - /// NOREF flag. Reads as zero - NOREF: u1, - }), base_address + 0xc); - }; - /// System control block - pub const SCB = struct { - pub const base_address = 0xe000ed00; - - /// address: 0xe000ed00 - /// CPUID base register - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { - /// Revision number - Revision: u4, - /// Part number of the - /// processor - PartNo: u12, - /// Reads as 0xF - Constant: u4, - /// Variant number - Variant: u4, - /// Implementer code - Implementer: u8, - }), base_address + 0x0); - - /// address: 0xe000ed04 - /// Interrupt control and state - /// register - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Active vector - VECTACTIVE: u9, - reserved0: u1, - reserved1: u1, - /// Return to base level - RETTOBASE: u1, - /// Pending vector - VECTPENDING: u7, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Interrupt pending flag - ISRPENDING: u1, - reserved5: u1, - reserved6: u1, - /// SysTick exception clear-pending - /// bit - PENDSTCLR: u1, - /// SysTick exception set-pending - /// bit - PENDSTSET: u1, - /// PendSV clear-pending bit - PENDSVCLR: u1, - /// PendSV set-pending bit - PENDSVSET: u1, - reserved7: u1, - reserved8: u1, - /// NMI set-pending bit. - NMIPENDSET: u1, - }), base_address + 0x4); - - /// address: 0xe000ed08 - /// Vector table offset register - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Vector table base offset - /// field - TBLOFF: u21, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0xe000ed0c - /// Application interrupt and reset control - /// register - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// VECTRESET - VECTRESET: u1, - /// VECTCLRACTIVE - VECTCLRACTIVE: u1, - /// SYSRESETREQ - SYSRESETREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PRIGROUP - PRIGROUP: u3, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ENDIANESS - ENDIANESS: u1, - /// Register key - VECTKEYSTAT: u16, - }), base_address + 0xc); - - /// address: 0xe000ed10 - /// System control register - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// SLEEPONEXIT - SLEEPONEXIT: u1, - /// SLEEPDEEP - SLEEPDEEP: u1, - reserved1: u1, - /// Send Event on Pending bit - SEVEONPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x10); - - /// address: 0xe000ed14 - /// Configuration and control - /// register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Configures how the processor enters - /// Thread mode - NONBASETHRDENA: u1, - /// USERSETMPEND - USERSETMPEND: u1, - reserved0: u1, - /// UNALIGN_ TRP - UNALIGN__TRP: u1, - /// DIV_0_TRP - DIV_0_TRP: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// BFHFNMIGN - BFHFNMIGN: u1, - /// STKALIGN - STKALIGN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x14); - - /// address: 0xe000ed18 - /// System handler priority - /// registers - pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Priority of system handler - /// 4 - PRI_4: u8, - /// Priority of system handler - /// 5 - PRI_5: u8, - /// Priority of system handler - /// 6 - PRI_6: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000ed1c - /// System handler priority - /// registers - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - /// Priority of system handler - /// 11 - PRI_11: u8, - }), base_address + 0x1c); - - /// address: 0xe000ed20 - /// System handler priority - /// registers - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Priority of system handler - /// 14 - PRI_14: u8, - /// Priority of system handler - /// 15 - PRI_15: u8, - }), base_address + 0x20); - - /// address: 0xe000ed24 - /// System handler control and state - /// register - pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory management fault exception active - /// bit - MEMFAULTACT: u1, - /// Bus fault exception active - /// bit - BUSFAULTACT: u1, - reserved0: u1, - /// Usage fault exception active - /// bit - USGFAULTACT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// SVC call active bit - SVCALLACT: u1, - /// Debug monitor active bit - MONITORACT: u1, - reserved4: u1, - /// PendSV exception active - /// bit - PENDSVACT: u1, - /// SysTick exception active - /// bit - SYSTICKACT: u1, - /// Usage fault exception pending - /// bit - USGFAULTPENDED: u1, - /// Memory management fault exception - /// pending bit - MEMFAULTPENDED: u1, - /// Bus fault exception pending - /// bit - BUSFAULTPENDED: u1, - /// SVC call pending bit - SVCALLPENDED: u1, - /// Memory management fault enable - /// bit - MEMFAULTENA: u1, - /// Bus fault enable bit - BUSFAULTENA: u1, - /// Usage fault enable bit - USGFAULTENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x24); - - /// address: 0xe000ed28 - /// Configurable fault status - /// register - pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Instruction access violation - /// flag - IACCVIOL: u1, - reserved1: u1, - /// Memory manager fault on unstacking for a - /// return from exception - MUNSTKERR: u1, - /// Memory manager fault on stacking for - /// exception entry. - MSTKERR: u1, - /// MLSPERR - MLSPERR: u1, - reserved2: u1, - /// Memory Management Fault Address Register - /// (MMAR) valid flag - MMARVALID: u1, - /// Instruction bus error - IBUSERR: u1, - /// Precise data bus error - PRECISERR: u1, - /// Imprecise data bus error - IMPRECISERR: u1, - /// Bus fault on unstacking for a return - /// from exception - UNSTKERR: u1, - /// Bus fault on stacking for exception - /// entry - STKERR: u1, - /// Bus fault on floating-point lazy state - /// preservation - LSPERR: u1, - reserved3: u1, - /// Bus Fault Address Register (BFAR) valid - /// flag - BFARVALID: u1, - /// Undefined instruction usage - /// fault - UNDEFINSTR: u1, - /// Invalid state usage fault - INVSTATE: u1, - /// Invalid PC load usage - /// fault - INVPC: u1, - /// No coprocessor usage - /// fault. - NOCP: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Unaligned access usage - /// fault - UNALIGNED: u1, - /// Divide by zero usage fault - DIVBYZERO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x28); - - /// address: 0xe000ed2c - /// Hard fault status register - pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Vector table hard fault - VECTTBL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - reserved28: u1, - /// Forced hard fault - FORCED: u1, - /// Reserved for Debug use - DEBUG_VT: u1, - }), base_address + 0x2c); - - /// address: 0xe000ed34 - /// Memory management fault address - /// register - pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0xe000ed38 - /// Bus fault address register - pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); - - /// address: 0xe000ed3c - /// Auxiliary fault status - /// register - pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Implementation defined - IMPDEF: u32, - }), base_address + 0x3c); - }; - /// Nested vectored interrupt - /// controller - pub const NVIC_STIR = struct { - pub const base_address = 0xe000ef00; - - /// address: 0xe000ef00 - /// Software trigger interrupt - /// register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Software generated interrupt - /// ID - INTID: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - }; - /// Floating point unit CPACR - pub const FPU_CPACR = struct { - pub const base_address = 0xe000ed88; - - /// address: 0xe000ed88 - /// Coprocessor access control - /// register - pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// CP - CP: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - }; - /// System control block ACTLR - pub const SCB_ACTRL = struct { - pub const base_address = 0xe000e008; - - /// address: 0xe000e008 - /// Auxiliary control register - pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DISMCYCINT - DISMCYCINT: u1, - /// DISDEFWBUF - DISDEFWBUF: u1, - /// DISFOLD - DISFOLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// DISFPCA - DISFPCA: u1, - /// DISOOFP - DISOOFP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: *const fn () callconv(.C) void, - Naked: *const fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/stm32f303/stm32f303.zig b/src/modules/chips/stm32f303/stm32f303.zig deleted file mode 100644 index a4cfb53..0000000 --- a/src/modules/chips/stm32f303/stm32f303.zig +++ /dev/null @@ -1,598 +0,0 @@ -//! For now we keep all clock settings on the chip defaults. -//! This code currently assumes the STM32F303xB / STM32F303xC clock configuration. -//! TODO: Do something useful for other STM32f30x chips. -//! -//! Specifically, TIM6 is running on an 8 MHz clock, -//! HSI = 8 MHz is the SYSCLK after reset -//! default AHB prescaler = /1 (= values 0..7): -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); -//! ``` -//! -//! so also HCLK = 8 MHz. -//! And with the default APB1 prescaler = /2: -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .PPRE1 = 4 }); -//! ``` -//! -//! results in PCLK1, -//! and the resulting implicit factor *2 for TIM2/3/4/6/7 -//! makes TIM6 run at 8MHz/2*2 = 8 MHz. -//! -//! The above default configuration makes U(S)ART2..5 -//! (which use PCLK1 without that implicit *2 factor) -//! run at 4 MHz by default. -//! -//! USART1 uses PCLK2, which uses the APB2 prescaler on HCLK, -//! default APB2 prescaler = /1: -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .PPRE2 = 0 }); -//! ``` -//! -//! and therefore USART1 runs on 8 MHz. - -const std = @import("std"); -const runtime_safety = std.debug.runtime_safety; -const micro = @import("microzig"); -const chip = @import("registers.zig"); -const regs = chip.registers; - -pub usingnamespace chip; - -pub const cpu = @import("cpu"); - -pub const clock = struct { - pub const Domain = enum { - cpu, - ahb, - apb1, - apb2, - }; -}; - -// Default clock frequencies after reset, see top comment for calculation -pub const clock_frequencies = .{ - .cpu = 8_000_000, - .ahb = 8_000_000, - .apb1 = 8_000_000, - .apb2 = 8_000_000, -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec[0] != 'P') - @compileError(invalid_format_msg); - if (spec[1] < 'A' or spec[1] > 'H') - @compileError(invalid_format_msg); - - const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); - - return struct { - /// 'A'...'H' - const gpio_port_name = spec[1..2]; - const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); - const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); - }; -} - -fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { - var temp = reg.read(); - @field(temp, field_name) = value; - reg.write(temp); -} - -pub const gpio = struct { - pub fn setOutput(comptime pin: type) void { - setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); - } - - pub fn setInput(comptime pin: type) void { - setRegField(regs.RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); - } - - pub fn read(comptime pin: type) micro.gpio.State { - const idr_reg = pin.gpio_port.IDR; - const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? - return @intToEnum(micro.gpio.State, reg_value); - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - switch (state) { - .low => setRegField(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1), - .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), - } - } -}; - -pub const uart = struct { - pub const DataBits = enum(u4) { - seven = 7, - eight = 8, - }; - - /// uses the values of USART_CR2.STOP - pub const StopBits = enum(u2) { - one = 0b00, - half = 0b01, - two = 0b10, - one_and_half = 0b11, - }; - - /// uses the values of USART_CR1.PS - pub const Parity = enum(u1) { - even = 0, - odd = 1, - }; -}; - -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (!(index == 1)) @compileError("TODO: only USART1 is currently supported"); - if (pins.tx != null or pins.rx != null) - @compileError("TODO: custom pins are not currently supported"); - - return struct { - parity_read_mask: u8, - - const Self = @This(); - - pub fn init(config: micro.uart.Config) !Self { - // The following must all be written when the USART is disabled (UE=0). - if (regs.USART1.CR1.read().UE == 1) - @panic("Trying to initialize USART1 while it is already enabled"); - // LATER: Alternatively, set UE=0 at this point? Then wait for something? - // Or add a destroy() function which disables the USART? - - // enable the USART1 clock - regs.RCC.APB2ENR.modify(.{ .USART1EN = 1 }); - // enable GPIOC clock - regs.RCC.AHBENR.modify(.{ .IOPCEN = 1 }); - // set PC4+PC5 to alternate function 7, USART1_TX + USART1_RX - regs.GPIOC.MODER.modify(.{ .MODER4 = 0b10, .MODER5 = 0b10 }); - regs.GPIOC.AFRL.modify(.{ .AFRL4 = 7, .AFRL5 = 7 }); - - // clear USART1 configuration to its default - regs.USART1.CR1.raw = 0; - regs.USART1.CR2.raw = 0; - regs.USART1.CR3.raw = 0; - - // set word length - // Per the reference manual, M[1:0] means - // - 00: 8 bits (7 data + 1 parity, or 8 data), probably the chip default - // - 01: 9 bits (8 data + 1 parity) - // - 10: 7 bits (7 data) - // So M1==1 means "7-bit mode" (in which - // "the Smartcard mode, LIN master mode and Auto baud rate [...] are not supported"); - // and M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. - const m1: u1 = if (config.data_bits == .seven and config.parity == null) 1 else 0; - const m0: u1 = if (config.data_bits == .eight and config.parity != null) 1 else 0; - // Note that .padding0 = bit 28 = .M1 (.svd file bug?), and .M == .M0. - regs.USART1.CR1.modify(.{ .padding0 = m1, .M = m0 }); - - // set parity - if (config.parity) |parity| { - regs.USART1.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); - } else regs.USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default - - // set number of stop bits - regs.USART1.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); - - // set the baud rate - // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency - // from the chip, which can be affected by how the board configures the chip. - // In our case, these are accidentally the same at chip reset, - // if the board doesn't configure e.g. an HSE external crystal. - // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) - // TODO: Do a rounding div, instead of a truncating div? - const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate)); - regs.USART1.BRR.raw = usartdiv; - // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction, - // those seem to be for another chipset; .svd file bug? - // TODO: We assume the default OVER8=0 configuration above. - - // enable USART1, and its transmitter and receiver - regs.USART1.CR1.modify(.{ .UE = 1 }); - regs.USART1.CR1.modify(.{ .TE = 1 }); - regs.USART1.CR1.modify(.{ .RE = 1 }); - - // For code simplicity, at cost of one or more register reads, - // we read back the actual configuration from the registers, - // instead of using the `config` values. - return readFromRegisters(); - } - - pub fn getOrInit(config: micro.uart.Config) !Self { - if (regs.USART1.CR1.read().UE == 1) { - // UART1 already enabled, don't reinitialize and disturb things; - // instead read and use the actual configuration. - return readFromRegisters(); - } else return init(config); - } - - fn readFromRegisters() Self { - const cr1 = regs.USART1.CR1.read(); - // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. - // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, - // then we also mask away the 8th bit. - return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; - } - - pub fn canWrite(self: Self) bool { - _ = self; - return switch (regs.USART1.ISR.read().TXE) { - 1 => true, - 0 => false, - }; - } - - pub fn tx(self: Self, ch: u8) void { - while (!self.canWrite()) {} // Wait for Previous transmission - regs.USART1.TDR.modify(ch); - } - - pub fn txflush(_: Self) void { - while (regs.USART1.ISR.read().TC == 0) {} - } - - pub fn canRead(self: Self) bool { - _ = self; - return switch (regs.USART1.ISR.read().RXNE) { - 1 => true, - 0 => false, - }; - } - - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - const data_with_parity_bit: u9 = regs.USART1.RDR.read().RDR; - return @intCast(u8, data_with_parity_bit & self.parity_read_mask); - } - }; -} - -const enable_stm32f303_debug = false; - -fn debugPrint(comptime format: []const u8, args: anytype) void { - if (enable_stm32f303_debug) { - micro.debug.writer().print(format, args) catch {}; - } -} - -/// This implementation does not use AUTOEND=1 -pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { - if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported"); - if (pins.scl != null or pins.sda != null) - @compileError("TODO: custom pins are not currently supported"); - - return struct { - const Self = @This(); - - pub fn init(config: micro.i2c.Config) !Self { - // CONFIGURE I2C1 - // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA, - // if GPIO port B is configured for alternate function 4 for these PB pins. - - // 1. Enable the I2C CLOCK and GPIO CLOCK - regs.RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); - regs.RCC.AHBENR.modify(.{ .IOPBEN = 1 }); - debugPrint("I2C1 configuration step 1 complete\r\n", .{}); - // 2. Configure the I2C PINs for ALternate Functions - // a) Select Alternate Function in MODER Register - regs.GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 }); - // b) Select Open Drain Output - regs.GPIOB.OTYPER.modify(.{ .OT6 = 1, .OT7 = 1 }); - // c) Select High SPEED for the PINs - regs.GPIOB.OSPEEDR.modify(.{ .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); - // d) Select Pull-up for both the Pins - regs.GPIOB.PUPDR.modify(.{ .PUPDR6 = 0b01, .PUPDR7 = 0b01 }); - // e) Configure the Alternate Function in AFR Register - regs.GPIOB.AFRL.modify(.{ .AFRL6 = 4, .AFRL7 = 4 }); - debugPrint("I2C1 configuration step 2 complete\r\n", .{}); - - // 3. Reset the I2C - regs.I2C1.CR1.modify(.{ .PE = 0 }); - while (regs.I2C1.CR1.read().PE == 1) {} - // DO NOT regs.RCC.APB1RSTR.modify(.{ .I2C1RST = 1 }); - debugPrint("I2C1 configuration step 3 complete\r\n", .{}); - - // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz - // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/ - // but copying an example from the reference manual, RM0316 section 28.4.9.) - if (config.target_speed != 100_000) @panic("TODO: Support speeds other than 100 kHz"); - regs.I2C1.TIMINGR.modify(.{ - .PRESC = 1, - .SCLL = 0x13, - .SCLH = 0xF, - .SDADEL = 0x2, - .SCLDEL = 0x4, - }); - debugPrint("I2C1 configuration steps 4-6 complete\r\n", .{}); - - // 7. Program the I2C_CR1 register to enable the peripheral - regs.I2C1.CR1.modify(.{ .PE = 1 }); - debugPrint("I2C1 configuration step 7 complete\r\n", .{}); - - return Self{}; - } - - pub const WriteState = struct { - address: u7, - buffer: [255]u8 = undefined, - buffer_size: u8 = 0, - - pub fn start(address: u7) !WriteState { - return WriteState{ .address = address }; - } - - pub fn writeAll(self: *WriteState, bytes: []const u8) !void { - debugPrint("I2C1 writeAll() with {d} byte(s); buffer={any}\r\n", .{ bytes.len, self.buffer[0..self.buffer_size] }); - - std.debug.assert(self.buffer_size < 255); - for (bytes) |b| { - self.buffer[self.buffer_size] = b; - self.buffer_size += 1; - if (self.buffer_size == 255) { - try self.sendBuffer(1); - } - } - } - - fn sendBuffer(self: *WriteState, reload: u1) !void { - debugPrint("I2C1 sendBuffer() with {d} byte(s); RELOAD={d}; buffer={any}\r\n", .{ self.buffer_size, reload, self.buffer[0..self.buffer_size] }); - if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); - - std.debug.assert(reload == 0 or self.buffer_size == 255); // see TODOs below - - // As master, initiate write from address, 7 bit address - regs.I2C1.CR2.modify(.{ - .ADD10 = 0, - .SADD1 = self.address, - .RD_WRN = 0, // write - .NBYTES = self.buffer_size, - .RELOAD = reload, - }); - if (reload == 0) { - regs.I2C1.CR2.modify(.{ .START = 1 }); - } else { - // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, - // even though we make sure that we set NBYTES=255 per the docs. - } - for (self.buffer[0..self.buffer_size]) |b| { - // wait for empty transmit buffer - while (regs.I2C1.ISR.read().TXE == 0) { - debugPrint("I2C1 waiting for ready to send (TXE=0)\r\n", .{}); - } - debugPrint("I2C1 ready to send (TXE=1)\r\n", .{}); - // Write data byte - regs.I2C1.TXDR.modify(.{ .TXDATA = b }); - } - self.buffer_size = 0; - debugPrint("I2C1 data written\r\n", .{}); - if (reload == 1) { - // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, - // the following loop never seems to finish. - while (regs.I2C1.ISR.read().TCR == 0) { - debugPrint("I2C1 waiting transmit complete (TCR=0)\r\n", .{}); - } - debugPrint("I2C1 transmit complete (TCR=1)\r\n", .{}); - } else { - while (regs.I2C1.ISR.read().TC == 0) { - debugPrint("I2C1 waiting for transmit complete (TC=0)\r\n", .{}); - } - debugPrint("I2C1 transmit complete (TC=1)\r\n", .{}); - } - } - - pub fn stop(self: *WriteState) !void { - try self.sendBuffer(0); - // Communication STOP - debugPrint("I2C1 STOPping\r\n", .{}); - regs.I2C1.CR2.modify(.{ .STOP = 1 }); - while (regs.I2C1.ISR.read().BUSY == 1) {} - debugPrint("I2C1 STOPped\r\n", .{}); - } - - pub fn restartRead(self: *WriteState) !ReadState { - try self.sendBuffer(0); - return ReadState{ .address = self.address }; - } - pub fn restartWrite(self: *WriteState) !WriteState { - try self.sendBuffer(0); - return WriteState{ .address = self.address }; - } - }; - - pub const ReadState = struct { - address: u7, - read_allowed: if (runtime_safety) bool else void = if (runtime_safety) true else {}, - - pub fn start(address: u7) !ReadState { - return ReadState{ .address = address }; - } - - /// Fails with ReadError if incorrect number of bytes is received. - pub fn readNoEof(self: *ReadState, buffer: []u8) !void { - if (runtime_safety and !self.read_allowed) @panic("second read call not allowed"); - std.debug.assert(buffer.len < 256); // TODO: use RELOAD to read more data - - // As master, initiate read from accelerometer, 7 bit address - regs.I2C1.CR2.modify(.{ - .ADD10 = 0, - .SADD1 = self.address, - .RD_WRN = 1, // read - .NBYTES = @intCast(u8, buffer.len), - }); - debugPrint("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address }); - - // Communication START - regs.I2C1.CR2.modify(.{ .START = 1 }); - debugPrint("I2C1 RXNE={}\r\n", .{regs.I2C1.ISR.read().RXNE}); - debugPrint("I2C1 STARTed\r\n", .{}); - debugPrint("I2C1 RXNE={}\r\n", .{regs.I2C1.ISR.read().RXNE}); - - if (runtime_safety) self.read_allowed = false; - - for (buffer) |_, i| { - // Wait for data to be received - while (regs.I2C1.ISR.read().RXNE == 0) { - debugPrint("I2C1 waiting for data (RXNE=0)\r\n", .{}); - } - debugPrint("I2C1 data ready (RXNE=1)\r\n", .{}); - - // Read first data byte - buffer[i] = regs.I2C1.RXDR.read().RXDATA; - } - debugPrint("I2C1 data: {any}\r\n", .{buffer}); - } - - pub fn stop(_: *ReadState) !void { - // Communication STOP - regs.I2C1.CR2.modify(.{ .STOP = 1 }); - while (regs.I2C1.ISR.read().BUSY == 1) {} - debugPrint("I2C1 STOPped\r\n", .{}); - } - - pub fn restartRead(self: *ReadState) !ReadState { - debugPrint("I2C1 no action for restart\r\n", .{}); - return ReadState{ .address = self.address }; - } - pub fn restartWrite(self: *ReadState) !WriteState { - debugPrint("I2C1 no action for restart\r\n", .{}); - return WriteState{ .address = self.address }; - } - }; - }; -} - -/// An STM32F303 SPI bus -pub fn SpiBus(comptime index: usize) type { - if (!(index == 1)) @compileError("TODO: only SPI1 is currently supported"); - - return struct { - const Self = @This(); - - /// Initialize and enable the bus. - pub fn init(config: micro.spi.BusConfig) !Self { - _ = config; // unused for now - - // CONFIGURE SPI1 - // connected to APB2, MCU pins PA5 + PA7 + PA6 = SPC + SDI + SDO, - // if GPIO port A is configured for alternate function 5 for these PA pins. - - // Enable the GPIO CLOCK - regs.RCC.AHBENR.modify(.{ .IOPAEN = 1 }); - - // Configure the I2C PINs for ALternate Functions - // - Select Alternate Function in MODER Register - regs.GPIOA.MODER.modify(.{ .MODER5 = 0b10, .MODER6 = 0b10, .MODER7 = 0b10 }); - // - Select High SPEED for the PINs - regs.GPIOA.OSPEEDR.modify(.{ .OSPEEDR5 = 0b11, .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); - // - Configure the Alternate Function in AFR Register - regs.GPIOA.AFRL.modify(.{ .AFRL5 = 5, .AFRL6 = 5, .AFRL7 = 5 }); - - // Enable the SPI1 CLOCK - regs.RCC.APB2ENR.modify(.{ .SPI1EN = 1 }); - - regs.SPI1.CR1.modify(.{ - .MSTR = 1, - .SSM = 1, - .SSI = 1, - .RXONLY = 0, - .SPE = 1, - }); - // the following configuration is assumed in `transceiveByte()` - regs.SPI1.CR2.raw = 0; - regs.SPI1.CR2.modify(.{ - .DS = 0b0111, // 8-bit data frames, seems default via '0b0000 is interpreted as 0b0111' - .FRXTH = 1, // RXNE event after 1 byte received - }); - - return Self{}; - } - - /// Switch this SPI bus to the given device. - pub fn switchToDevice(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { - _ = config; // for future use - - regs.SPI1.CR1.modify(.{ - .CPOL = 1, // TODO: make configurable - .CPHA = 1, // TODO: make configurable - .BR = 0b111, // 1/256 the of PCLK TODO: make configurable - .LSBFIRST = 0, // MSB first TODO: make configurable - }); - gpio.setOutput(cs_pin); - } - - /// Begin a transfer to the given device. (Assumes `switchToDevice()` was called.) - pub fn beginTransfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { - _ = config; // for future use - gpio.write(cs_pin, .low); // select the given device, TODO: support inverse CS devices - debugPrint("enabled SPI1\r\n", .{}); - } - - /// The basic operation in the current simplistic implementation: - /// send+receive a single byte. - /// Writing `null` writes an arbitrary byte (`undefined`), and - /// reading into `null` ignores the value received. - pub fn transceiveByte(_: Self, optional_write_byte: ?u8, optional_read_pointer: ?*u8) !void { - - // SPIx_DR's least significant byte is `@bitCast([dr_byte_size]u8, ...)[0]` - const dr_byte_size = @sizeOf(@TypeOf(regs.SPI1.DR.raw)); - - // wait unril ready for write - while (regs.SPI1.SR.read().TXE == 0) { - debugPrint("SPI1 TXE == 0\r\n", .{}); - } - debugPrint("SPI1 TXE == 1\r\n", .{}); - - // write - const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value - @bitCast([dr_byte_size]u8, regs.SPI1.DR.*)[0] = write_byte; - debugPrint("Sent: {X:2}.\r\n", .{write_byte}); - - // wait until read processed - while (regs.SPI1.SR.read().RXNE == 0) { - debugPrint("SPI1 RXNE == 0\r\n", .{}); - } - debugPrint("SPI1 RXNE == 1\r\n", .{}); - - // read - var data_read = regs.SPI1.DR.raw; - _ = regs.SPI1.SR.read(); // clear overrun flag - const dr_lsb = @bitCast([dr_byte_size]u8, data_read)[0]; - debugPrint("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read }); - if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb; - } - - /// Write all given bytes on the bus, not reading anything back. - pub fn writeAll(self: Self, bytes: []const u8) !void { - for (bytes) |b| { - try self.transceiveByte(b, null); - } - } - - /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`). - pub fn readInto(self: Self, buffer: []u8) !void { - for (buffer) |_, i| { - try self.transceiveByte(null, &buffer[i]); - } - } - - pub fn endTransfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { - _ = config; // for future use - // no delay should be needed here, since we know SPIx_SR's TXE is 1 - debugPrint("(disabling SPI1)\r\n", .{}); - gpio.write(cs_pin, .high); // deselect the given device, TODO: support inverse CS devices - // HACK: wait long enough to make any device end an ongoing transfer - var i: u8 = 255; // with the default clock, this seems to delay ~185 microseconds - while (i > 0) : (i -= 1) { - asm volatile ("nop"); - } - } - }; -} diff --git a/src/modules/chips/stm32f407/registers.zig b/src/modules/chips/stm32f407/registers.zig deleted file mode 100644 index 9992f7f..0000000 --- a/src/modules/chips/stm32f407/registers.zig +++ /dev/null @@ -1,52844 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 6376709051af4d8920d5c8bb48945ca688af32ae -// -// device: STM32F407 -// cpu: CM4 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - /// Window Watchdog interrupt - WWDG: InterruptVector = unhandled, - /// PVD through EXTI line detection - /// interrupt - PVD: InterruptVector = unhandled, - /// Tamper and TimeStamp interrupts through the - /// EXTI line - TAMP_STAMP: InterruptVector = unhandled, - /// RTC Wakeup interrupt through the EXTI - /// line - RTC_WKUP: InterruptVector = unhandled, - reserved2: u32 = undefined, - /// RCC global interrupt - RCC: InterruptVector = unhandled, - /// EXTI Line0 interrupt - EXTI0: InterruptVector = unhandled, - /// EXTI Line1 interrupt - EXTI1: InterruptVector = unhandled, - /// EXTI Line2 interrupt - EXTI2: InterruptVector = unhandled, - /// EXTI Line3 interrupt - EXTI3: InterruptVector = unhandled, - /// EXTI Line4 interrupt - EXTI4: InterruptVector = unhandled, - /// DMA1 Stream0 global interrupt - DMA1_Stream0: InterruptVector = unhandled, - /// DMA1 Stream1 global interrupt - DMA1_Stream1: InterruptVector = unhandled, - /// DMA1 Stream2 global interrupt - DMA1_Stream2: InterruptVector = unhandled, - /// DMA1 Stream3 global interrupt - DMA1_Stream3: InterruptVector = unhandled, - /// DMA1 Stream4 global interrupt - DMA1_Stream4: InterruptVector = unhandled, - /// DMA1 Stream5 global interrupt - DMA1_Stream5: InterruptVector = unhandled, - /// DMA1 Stream6 global interrupt - DMA1_Stream6: InterruptVector = unhandled, - /// ADC1 global interrupt - ADC: InterruptVector = unhandled, - /// CAN1 TX interrupts - CAN1_TX: InterruptVector = unhandled, - /// CAN1 RX0 interrupts - CAN1_RX0: InterruptVector = unhandled, - /// CAN1 RX1 interrupts - CAN1_RX1: InterruptVector = unhandled, - /// CAN1 SCE interrupt - CAN1_SCE: InterruptVector = unhandled, - /// EXTI Line[9:5] interrupts - EXTI9_5: InterruptVector = unhandled, - /// TIM1 Break interrupt and TIM9 global - /// interrupt - TIM1_BRK_TIM9: InterruptVector = unhandled, - /// TIM1 Update interrupt and TIM10 global - /// interrupt - TIM1_UP_TIM10: InterruptVector = unhandled, - /// TIM1 Trigger and Commutation interrupts and - /// TIM11 global interrupt - TIM1_TRG_COM_TIM11: InterruptVector = unhandled, - /// TIM1 Capture Compare interrupt - TIM1_CC: InterruptVector = unhandled, - /// TIM2 global interrupt - TIM2: InterruptVector = unhandled, - /// TIM3 global interrupt - TIM3: InterruptVector = unhandled, - /// TIM4 global interrupt - TIM4: InterruptVector = unhandled, - /// I2C1 event interrupt - I2C1_EV: InterruptVector = unhandled, - /// I2C1 error interrupt - I2C1_ER: InterruptVector = unhandled, - /// I2C2 event interrupt - I2C2_EV: InterruptVector = unhandled, - /// I2C2 error interrupt - I2C2_ER: InterruptVector = unhandled, - /// SPI1 global interrupt - SPI1: InterruptVector = unhandled, - /// SPI2 global interrupt - SPI2: InterruptVector = unhandled, - /// USART1 global interrupt - USART1: InterruptVector = unhandled, - /// USART2 global interrupt - USART2: InterruptVector = unhandled, - /// USART3 global interrupt - USART3: InterruptVector = unhandled, - /// EXTI Line[15:10] interrupts - EXTI15_10: InterruptVector = unhandled, - /// RTC Alarms (A and B) through EXTI line - /// interrupt - RTC_Alarm: InterruptVector = unhandled, - /// USB On-The-Go FS Wakeup through EXTI line - /// interrupt - OTG_FS_WKUP: InterruptVector = unhandled, - /// TIM8 Break interrupt and TIM12 global - /// interrupt - TIM8_BRK_TIM12: InterruptVector = unhandled, - /// TIM8 Update interrupt and TIM13 global - /// interrupt - TIM8_UP_TIM13: InterruptVector = unhandled, - /// TIM8 Trigger and Commutation interrupts and - /// TIM14 global interrupt - TIM8_TRG_COM_TIM14: InterruptVector = unhandled, - /// TIM8 Capture Compare interrupt - TIM8_CC: InterruptVector = unhandled, - /// DMA1 Stream7 global interrupt - DMA1_Stream7: InterruptVector = unhandled, - /// FSMC global interrupt - FSMC: InterruptVector = unhandled, - /// SDIO global interrupt - SDIO: InterruptVector = unhandled, - /// TIM5 global interrupt - TIM5: InterruptVector = unhandled, - /// SPI3 global interrupt - SPI3: InterruptVector = unhandled, - /// UART4 global interrupt - UART4: InterruptVector = unhandled, - /// UART5 global interrupt - UART5: InterruptVector = unhandled, - /// TIM6 global interrupt, DAC1 and DAC2 underrun - /// error interrupt - TIM6_DAC: InterruptVector = unhandled, - /// TIM7 global interrupt - TIM7: InterruptVector = unhandled, - /// DMA2 Stream0 global interrupt - DMA2_Stream0: InterruptVector = unhandled, - /// DMA2 Stream1 global interrupt - DMA2_Stream1: InterruptVector = unhandled, - /// DMA2 Stream2 global interrupt - DMA2_Stream2: InterruptVector = unhandled, - /// DMA2 Stream3 global interrupt - DMA2_Stream3: InterruptVector = unhandled, - /// DMA2 Stream4 global interrupt - DMA2_Stream4: InterruptVector = unhandled, - /// Ethernet global interrupt - ETH: InterruptVector = unhandled, - /// Ethernet Wakeup through EXTI line - /// interrupt - ETH_WKUP: InterruptVector = unhandled, - /// CAN2 TX interrupts - CAN2_TX: InterruptVector = unhandled, - /// CAN2 RX0 interrupts - CAN2_RX0: InterruptVector = unhandled, - /// CAN2 RX1 interrupts - CAN2_RX1: InterruptVector = unhandled, - /// CAN2 SCE interrupt - CAN2_SCE: InterruptVector = unhandled, - /// USB On The Go FS global - /// interrupt - OTG_FS: InterruptVector = unhandled, - /// DMA2 Stream5 global interrupt - DMA2_Stream5: InterruptVector = unhandled, - /// DMA2 Stream6 global interrupt - DMA2_Stream6: InterruptVector = unhandled, - /// DMA2 Stream7 global interrupt - DMA2_Stream7: InterruptVector = unhandled, - /// USART6 global interrupt - USART6: InterruptVector = unhandled, - /// I2C3 event interrupt - I2C3_EV: InterruptVector = unhandled, - /// I2C3 error interrupt - I2C3_ER: InterruptVector = unhandled, - /// USB On The Go HS End Point 1 Out global - /// interrupt - OTG_HS_EP1_OUT: InterruptVector = unhandled, - /// USB On The Go HS End Point 1 In global - /// interrupt - OTG_HS_EP1_IN: InterruptVector = unhandled, - /// USB On The Go HS Wakeup through EXTI - /// interrupt - OTG_HS_WKUP: InterruptVector = unhandled, - /// USB On The Go HS global - /// interrupt - OTG_HS: InterruptVector = unhandled, - /// DCMI global interrupt - DCMI: InterruptVector = unhandled, - /// CRYP crypto global interrupt - CRYP: InterruptVector = unhandled, - /// Hash and Rng global interrupt - HASH_RNG: InterruptVector = unhandled, - /// FPU interrupt - FPU: InterruptVector = unhandled, - reserved3: u32 = undefined, - reserved4: u32 = undefined, - reserved5: u32 = undefined, - reserved6: u32 = undefined, - reserved7: u32 = undefined, - reserved8: u32 = undefined, - /// LTDC global interrupt - LCD_TFT: InterruptVector = unhandled, - /// LTDC global error interrupt - LCD_TFT_1: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// Random number generator - pub const RNG = struct { - pub const base_address = 0x50060800; - - /// address: 0x50060800 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Random number generator - /// enable - RNGEN: u1, - /// Interrupt enable - IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x0); - - /// address: 0x50060804 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data ready - DRDY: u1, - /// Clock error current status - CECS: u1, - /// Seed error current status - SECS: u1, - reserved0: u1, - reserved1: u1, - /// Clock error interrupt - /// status - CEIS: u1, - /// Seed error interrupt - /// status - SEIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x50060808 - /// data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Random data - RNDATA: u32, - }), base_address + 0x8); - }; - - /// Digital camera interface - pub const DCMI = struct { - pub const base_address = 0x50050000; - - /// address: 0x50050000 - /// control register 1 - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture enable - CAPTURE: u1, - /// Capture mode - CM: u1, - /// Crop feature - CROP: u1, - /// JPEG format - JPEG: u1, - /// Embedded synchronization - /// select - ESS: u1, - /// Pixel clock polarity - PCKPOL: u1, - /// Horizontal synchronization - /// polarity - HSPOL: u1, - /// Vertical synchronization - /// polarity - VSPOL: u1, - /// Frame capture rate control - FCRC: u2, - /// Extended data mode - EDM: u2, - reserved0: u1, - reserved1: u1, - /// DCMI enable - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x0); - - /// address: 0x50050004 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// HSYNC - HSYNC: u1, - /// VSYNC - VSYNC: u1, - /// FIFO not empty - FNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0x50050008 - /// raw interrupt status register - pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete raw interrupt - /// status - FRAME_RIS: u1, - /// Overrun raw interrupt - /// status - OVR_RIS: u1, - /// Synchronization error raw interrupt - /// status - ERR_RIS: u1, - /// VSYNC raw interrupt status - VSYNC_RIS: u1, - /// Line raw interrupt status - LINE_RIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x8); - - /// address: 0x5005000c - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete interrupt - /// enable - FRAME_IE: u1, - /// Overrun interrupt enable - OVR_IE: u1, - /// Synchronization error interrupt - /// enable - ERR_IE: u1, - /// VSYNC interrupt enable - VSYNC_IE: u1, - /// Line interrupt enable - LINE_IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xc); - - /// address: 0x50050010 - /// masked interrupt status - /// register - pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete masked interrupt - /// status - FRAME_MIS: u1, - /// Overrun masked interrupt - /// status - OVR_MIS: u1, - /// Synchronization error masked interrupt - /// status - ERR_MIS: u1, - /// VSYNC masked interrupt - /// status - VSYNC_MIS: u1, - /// Line masked interrupt - /// status - LINE_MIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x10); - - /// address: 0x50050014 - /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete interrupt status - /// clear - FRAME_ISC: u1, - /// Overrun interrupt status - /// clear - OVR_ISC: u1, - /// Synchronization error interrupt status - /// clear - ERR_ISC: u1, - /// Vertical synch interrupt status - /// clear - VSYNC_ISC: u1, - /// line interrupt status - /// clear - LINE_ISC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x14); - - /// address: 0x50050018 - /// embedded synchronization code - /// register - pub const ESCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame start delimiter code - FSC: u8, - /// Line start delimiter code - LSC: u8, - /// Line end delimiter code - LEC: u8, - /// Frame end delimiter code - FEC: u8, - }), base_address + 0x18); - - /// address: 0x5005001c - /// embedded synchronization unmask - /// register - pub const ESUR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame start delimiter - /// unmask - FSU: u8, - /// Line start delimiter - /// unmask - LSU: u8, - /// Line end delimiter unmask - LEU: u8, - /// Frame end delimiter unmask - FEU: u8, - }), base_address + 0x1c); - - /// address: 0x50050020 - /// crop window start - pub const CWSTRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Horizontal offset count - HOFFCNT: u14, - reserved0: u1, - reserved1: u1, - /// Vertical start line count - VST: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x20); - - /// address: 0x50050024 - /// crop window size - pub const CWSIZE = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture count - CAPCNT: u14, - reserved0: u1, - reserved1: u1, - /// Vertical line count - VLINE: u14, - padding0: u1, - padding1: u1, - }), base_address + 0x24); - - /// address: 0x50050028 - /// data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - Byte0: u8, - /// Data byte 1 - Byte1: u8, - /// Data byte 2 - Byte2: u8, - /// Data byte 3 - Byte3: u8, - }), base_address + 0x28); - }; - - /// Flexible static memory controller - pub const FSMC = struct { - pub const base_address = 0xa0000000; - - /// address: 0xa0000000 - /// SRAM/NOR-Flash chip-select control register - /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - reserved1: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0xa0000004 - /// SRAM/NOR-Flash chip-select timing register - /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0xa0000008 - /// SRAM/NOR-Flash chip-select control register - /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x8); - - /// address: 0xa000000c - /// SRAM/NOR-Flash chip-select timing register - /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0xa0000010 - /// SRAM/NOR-Flash chip-select control register - /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0xa0000014 - /// SRAM/NOR-Flash chip-select timing register - /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0xa0000018 - /// SRAM/NOR-Flash chip-select control register - /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x18); - - /// address: 0xa000001c - /// SRAM/NOR-Flash chip-select timing register - /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0xa0000060 - /// PC Card/NAND Flash control register - /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x60); - - /// address: 0xa0000064 - /// FIFO status and interrupt register - /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x64); - - /// address: 0xa0000068 - /// Common memory space timing register - /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x68); - - /// address: 0xa000006c - /// Attribute memory space timing register - /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x6c); - - /// address: 0xa0000074 - /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x74); - - /// address: 0xa0000080 - /// PC Card/NAND Flash control register - /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x80); - - /// address: 0xa0000084 - /// FIFO status and interrupt register - /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x84); - - /// address: 0xa0000088 - /// Common memory space timing register - /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x88); - - /// address: 0xa000008c - /// Attribute memory space timing register - /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x8c); - - /// address: 0xa0000094 - /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x94); - - /// address: 0xa00000a0 - /// PC Card/NAND Flash control register - /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0xa0); - - /// address: 0xa00000a4 - /// FIFO status and interrupt register - /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xa4); - - /// address: 0xa00000a8 - /// Common memory space timing register - /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0xa8); - - /// address: 0xa00000ac - /// Attribute memory space timing register - /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0xac); - - /// address: 0xa00000b0 - /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), base_address + 0xb0); - - /// address: 0xa0000104 - /// SRAM/NOR-Flash write timing registers - /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x104); - - /// address: 0xa000010c - /// SRAM/NOR-Flash write timing registers - /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10c); - - /// address: 0xa0000114 - /// SRAM/NOR-Flash write timing registers - /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x114); - - /// address: 0xa000011c - /// SRAM/NOR-Flash write timing registers - /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x11c); - }; - - /// Debug support - pub const DBG = struct { - pub const base_address = 0xe0042000; - - /// address: 0xe0042000 - /// IDCODE - pub const DBGMCU_IDCODE = @intToPtr(*volatile Mmio(32, packed struct { - /// DEV_ID - DEV_ID: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// REV_ID - REV_ID: u16, - }), base_address + 0x0); - - /// address: 0xe0042004 - /// Control Register - pub const DBGMCU_CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved0: u1, - reserved1: u1, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT: u1, - /// DBG_TIM8_STOP - DBG_TIM8_STOP: u1, - /// DBG_TIM5_STOP - DBG_TIM5_STOP: u1, - /// DBG_TIM6_STOP - DBG_TIM6_STOP: u1, - /// DBG_TIM7_STOP - DBG_TIM7_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x4); - - /// address: 0xe0042008 - /// Debug MCU APB1 Freeze registe - pub const DBGMCU_APB1_FZ = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG_TIM2_STOP - DBG_TIM2_STOP: u1, - /// DBG_TIM3 _STOP - DBG_TIM3_STOP: u1, - /// DBG_TIM4_STOP - DBG_TIM4_STOP: u1, - /// DBG_TIM5_STOP - DBG_TIM5_STOP: u1, - /// DBG_TIM6_STOP - DBG_TIM6_STOP: u1, - /// DBG_TIM7_STOP - DBG_TIM7_STOP: u1, - /// DBG_TIM12_STOP - DBG_TIM12_STOP: u1, - /// DBG_TIM13_STOP - DBG_TIM13_STOP: u1, - /// DBG_TIM14_STOP - DBG_TIM14_STOP: u1, - reserved0: u1, - reserved1: u1, - /// DBG_WWDG_STOP - DBG_WWDG_STOP: u1, - /// DBG_IWDEG_STOP - DBG_IWDEG_STOP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// DBG_J2C1_SMBUS_TIMEOUT - DBG_J2C1_SMBUS_TIMEOUT: u1, - /// DBG_J2C2_SMBUS_TIMEOUT - DBG_J2C2_SMBUS_TIMEOUT: u1, - /// DBG_J2C3SMBUS_TIMEOUT - DBG_J2C3SMBUS_TIMEOUT: u1, - reserved10: u1, - /// DBG_CAN1_STOP - DBG_CAN1_STOP: u1, - /// DBG_CAN2_STOP - DBG_CAN2_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x8); - - /// address: 0xe004200c - /// Debug MCU APB2 Freeze registe - pub const DBGMCU_APB2_FZ = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 counter stopped when core is - /// halted - DBG_TIM1_STOP: u1, - /// TIM8 counter stopped when core is - /// halted - DBG_TIM8_STOP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TIM9 counter stopped when core is - /// halted - DBG_TIM9_STOP: u1, - /// TIM10 counter stopped when core is - /// halted - DBG_TIM10_STOP: u1, - /// TIM11 counter stopped when core is - /// halted - DBG_TIM11_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - }; - - /// DMA controller - pub const DMA2 = struct { - pub const base_address = 0x40026400; - - /// address: 0x40026400 - /// low interrupt status register - pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF0: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF0: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF0: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF0: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF0: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF1: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF1: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF1: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF1: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF2: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF2: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF2: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF2: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF2: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF3: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF3: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF3: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF3: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40026404 - /// high interrupt status register - pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF4: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF4: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF4: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF4: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF4: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF5: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF5: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF5: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF5: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF6: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF6: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF6: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF6: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF6: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF7: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF7: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF7: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF7: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40026408 - /// low interrupt flag clear - /// register - pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF0: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF0: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF0: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF0: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF0: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF1: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF1: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF1: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF1: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF2: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF2: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF2: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF2: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF2: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF3: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF3: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF3: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF3: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4002640c - /// high interrupt flag clear - /// register - pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF4: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF4: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF4: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF4: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF4: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF5: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF5: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF5: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF5: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF6: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF6: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF6: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF6: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF6: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF7: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF7: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF7: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF7: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x40026410 - /// stream x configuration - /// register - pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - reserved0: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x40026414 - /// stream x number of data - /// register - pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40026418 - /// stream x peripheral address - /// register - pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x18); - - /// address: 0x4002641c - /// stream x memory 0 address - /// register - pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x1c); - - /// address: 0x40026420 - /// stream x memory 1 address - /// register - pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x20); - - /// address: 0x40026424 - /// stream x FIFO control register - pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40026428 - /// stream x configuration - /// register - pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x28); - - /// address: 0x4002642c - /// stream x number of data - /// register - pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x40026430 - /// stream x peripheral address - /// register - pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x30); - - /// address: 0x40026434 - /// stream x memory 0 address - /// register - pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x34); - - /// address: 0x40026438 - /// stream x memory 1 address - /// register - pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x38); - - /// address: 0x4002643c - /// stream x FIFO control register - pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x3c); - - /// address: 0x40026440 - /// stream x configuration - /// register - pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x40); - - /// address: 0x40026444 - /// stream x number of data - /// register - pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40026448 - /// stream x peripheral address - /// register - pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x48); - - /// address: 0x4002644c - /// stream x memory 0 address - /// register - pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x4c); - - /// address: 0x40026450 - /// stream x memory 1 address - /// register - pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x50); - - /// address: 0x40026454 - /// stream x FIFO control register - pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40026458 - /// stream x configuration - /// register - pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x58); - - /// address: 0x4002645c - /// stream x number of data - /// register - pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40026460 - /// stream x peripheral address - /// register - pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40026464 - /// stream x memory 0 address - /// register - pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x64); - - /// address: 0x40026468 - /// stream x memory 1 address - /// register - pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x68); - - /// address: 0x4002646c - /// stream x FIFO control register - pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x6c); - - /// address: 0x40026470 - /// stream x configuration - /// register - pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x70); - - /// address: 0x40026474 - /// stream x number of data - /// register - pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x74); - - /// address: 0x40026478 - /// stream x peripheral address - /// register - pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x78); - - /// address: 0x4002647c - /// stream x memory 0 address - /// register - pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x7c); - - /// address: 0x40026480 - /// stream x memory 1 address - /// register - pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x80); - - /// address: 0x40026484 - /// stream x FIFO control register - pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x84); - - /// address: 0x40026488 - /// stream x configuration - /// register - pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4002648c - /// stream x number of data - /// register - pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x40026490 - /// stream x peripheral address - /// register - pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x90); - - /// address: 0x40026494 - /// stream x memory 0 address - /// register - pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x94); - - /// address: 0x40026498 - /// stream x memory 1 address - /// register - pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x98); - - /// address: 0x4002649c - /// stream x FIFO control register - pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x9c); - - /// address: 0x400264a0 - /// stream x configuration - /// register - pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xa0); - - /// address: 0x400264a4 - /// stream x number of data - /// register - pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa4); - - /// address: 0x400264a8 - /// stream x peripheral address - /// register - pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xa8); - - /// address: 0x400264ac - /// stream x memory 0 address - /// register - pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xac); - - /// address: 0x400264b0 - /// stream x memory 1 address - /// register - pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xb0); - - /// address: 0x400264b4 - /// stream x FIFO control register - pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xb4); - - /// address: 0x400264b8 - /// stream x configuration - /// register - pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xb8); - - /// address: 0x400264bc - /// stream x number of data - /// register - pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xbc); - - /// address: 0x400264c0 - /// stream x peripheral address - /// register - pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xc0); - - /// address: 0x400264c4 - /// stream x memory 0 address - /// register - pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xc4); - - /// address: 0x400264c8 - /// stream x memory 1 address - /// register - pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xc8); - - /// address: 0x400264cc - /// stream x FIFO control register - pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xcc); - }; - pub const DMA1 = struct { - pub const base_address = 0x40026000; - - /// address: 0x40026000 - /// low interrupt status register - pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF0: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF0: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF0: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF0: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF0: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF1: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF1: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF1: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF1: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF2: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF2: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF2: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF2: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF2: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF3: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF3: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF3: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF3: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40026004 - /// high interrupt status register - pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF4: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF4: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF4: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF4: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF4: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF5: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF5: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF5: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF5: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF6: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF6: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF6: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF6: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF6: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF7: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF7: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF7: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF7: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40026008 - /// low interrupt flag clear - /// register - pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF0: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF0: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF0: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF0: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF0: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF1: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF1: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF1: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF1: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF2: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF2: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF2: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF2: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF2: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF3: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF3: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF3: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF3: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4002600c - /// high interrupt flag clear - /// register - pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF4: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF4: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF4: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF4: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF4: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF5: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF5: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF5: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF5: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF6: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF6: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF6: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF6: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF6: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF7: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF7: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF7: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF7: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x40026010 - /// stream x configuration - /// register - pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - reserved0: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x40026014 - /// stream x number of data - /// register - pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40026018 - /// stream x peripheral address - /// register - pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x18); - - /// address: 0x4002601c - /// stream x memory 0 address - /// register - pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x1c); - - /// address: 0x40026020 - /// stream x memory 1 address - /// register - pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x20); - - /// address: 0x40026024 - /// stream x FIFO control register - pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40026028 - /// stream x configuration - /// register - pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x28); - - /// address: 0x4002602c - /// stream x number of data - /// register - pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x40026030 - /// stream x peripheral address - /// register - pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x30); - - /// address: 0x40026034 - /// stream x memory 0 address - /// register - pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x34); - - /// address: 0x40026038 - /// stream x memory 1 address - /// register - pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x38); - - /// address: 0x4002603c - /// stream x FIFO control register - pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x3c); - - /// address: 0x40026040 - /// stream x configuration - /// register - pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x40); - - /// address: 0x40026044 - /// stream x number of data - /// register - pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40026048 - /// stream x peripheral address - /// register - pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x48); - - /// address: 0x4002604c - /// stream x memory 0 address - /// register - pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x4c); - - /// address: 0x40026050 - /// stream x memory 1 address - /// register - pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x50); - - /// address: 0x40026054 - /// stream x FIFO control register - pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40026058 - /// stream x configuration - /// register - pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x58); - - /// address: 0x4002605c - /// stream x number of data - /// register - pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40026060 - /// stream x peripheral address - /// register - pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40026064 - /// stream x memory 0 address - /// register - pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x64); - - /// address: 0x40026068 - /// stream x memory 1 address - /// register - pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x68); - - /// address: 0x4002606c - /// stream x FIFO control register - pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x6c); - - /// address: 0x40026070 - /// stream x configuration - /// register - pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x70); - - /// address: 0x40026074 - /// stream x number of data - /// register - pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x74); - - /// address: 0x40026078 - /// stream x peripheral address - /// register - pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x78); - - /// address: 0x4002607c - /// stream x memory 0 address - /// register - pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x7c); - - /// address: 0x40026080 - /// stream x memory 1 address - /// register - pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x80); - - /// address: 0x40026084 - /// stream x FIFO control register - pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x84); - - /// address: 0x40026088 - /// stream x configuration - /// register - pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4002608c - /// stream x number of data - /// register - pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x40026090 - /// stream x peripheral address - /// register - pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x90); - - /// address: 0x40026094 - /// stream x memory 0 address - /// register - pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x94); - - /// address: 0x40026098 - /// stream x memory 1 address - /// register - pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x98); - - /// address: 0x4002609c - /// stream x FIFO control register - pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x9c); - - /// address: 0x400260a0 - /// stream x configuration - /// register - pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xa0); - - /// address: 0x400260a4 - /// stream x number of data - /// register - pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa4); - - /// address: 0x400260a8 - /// stream x peripheral address - /// register - pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xa8); - - /// address: 0x400260ac - /// stream x memory 0 address - /// register - pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xac); - - /// address: 0x400260b0 - /// stream x memory 1 address - /// register - pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xb0); - - /// address: 0x400260b4 - /// stream x FIFO control register - pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xb4); - - /// address: 0x400260b8 - /// stream x configuration - /// register - pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xb8); - - /// address: 0x400260bc - /// stream x number of data - /// register - pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xbc); - - /// address: 0x400260c0 - /// stream x peripheral address - /// register - pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xc0); - - /// address: 0x400260c4 - /// stream x memory 0 address - /// register - pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xc4); - - /// address: 0x400260c8 - /// stream x memory 1 address - /// register - pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xc8); - - /// address: 0x400260cc - /// stream x FIFO control register - pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xcc); - }; - - /// Reset and clock control - pub const RCC = struct { - pub const base_address = 0x40023800; - - /// address: 0x40023800 - /// clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal high-speed clock - /// enable - HSION: u1, - /// Internal high-speed clock ready - /// flag - HSIRDY: u1, - reserved0: u1, - /// Internal high-speed clock - /// trimming - HSITRIM: u5, - /// Internal high-speed clock - /// calibration - HSICAL: u8, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system - /// enable - CSSON: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Main PLL (PLL) enable - PLLON: u1, - /// Main PLL (PLL) clock ready - /// flag - PLLRDY: u1, - /// PLLI2S enable - PLLI2SON: u1, - /// PLLI2S clock ready flag - PLLI2SRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40023804 - /// PLL configuration register - pub const PLLCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM0: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM1: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM2: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM3: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM4: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM5: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN0: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN1: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN2: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN3: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN4: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN5: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN6: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN7: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN8: u1, - reserved0: u1, - /// Main PLL (PLL) division factor for main - /// system clock - PLLP0: u1, - /// Main PLL (PLL) division factor for main - /// system clock - PLLP1: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Main PLL(PLL) and audio PLL (PLLI2S) - /// entry clock source - PLLSRC: u1, - reserved5: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ0: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ1: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ2: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40023808 - /// clock configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// System clock switch - SW0: u1, - /// System clock switch - SW1: u1, - /// System clock switch status - SWS0: u1, - /// System clock switch status - SWS1: u1, - /// AHB prescaler - HPRE: u4, - reserved0: u1, - reserved1: u1, - /// APB Low speed prescaler - /// (APB1) - PPRE1: u3, - /// APB high-speed prescaler - /// (APB2) - PPRE2: u3, - /// HSE division factor for RTC - /// clock - RTCPRE: u5, - /// Microcontroller clock output - /// 1 - MCO1: u2, - /// I2S clock selection - I2SSRC: u1, - /// MCO1 prescaler - MCO1PRE: u3, - /// MCO2 prescaler - MCO2PRE: u3, - /// Microcontroller clock output - /// 2 - MCO2: u2, - }), base_address + 0x8); - - /// address: 0x4002380c - /// clock interrupt register - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// Main PLL (PLL) ready interrupt - /// flag - PLLRDYF: u1, - /// PLLI2S ready interrupt - /// flag - PLLI2SRDYF: u1, - reserved0: u1, - /// Clock security system interrupt - /// flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// Main PLL (PLL) ready interrupt - /// enable - PLLRDYIE: u1, - /// PLLI2S ready interrupt - /// enable - PLLI2SRDYIE: u1, - reserved1: u1, - reserved2: u1, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// Main PLL(PLL) ready interrupt - /// clear - PLLRDYC: u1, - /// PLLI2S ready interrupt - /// clear - PLLI2SRDYC: u1, - reserved3: u1, - /// Clock security system interrupt - /// clear - CSSC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40023810 - /// AHB1 peripheral reset register - pub const AHB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC reset - CRCRST: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved11: u1, - reserved12: u1, - /// Ethernet MAC reset - ETHMACRST: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// USB OTG HS module reset - OTGHSRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40023814 - /// AHB2 peripheral reset register - pub const AHB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface reset - DCMIRST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Random number generator module - /// reset - RNGRST: u1, - /// USB OTG FS module reset - OTGFSRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40023818 - /// AHB3 peripheral reset register - pub const AHB3RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible static memory controller module - /// reset - FSMCRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x18); - - /// address: 0x40023820 - /// APB1 peripheral reset register - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 reset - TIM2RST: u1, - /// TIM3 reset - TIM3RST: u1, - /// TIM4 reset - TIM4RST: u1, - /// TIM5 reset - TIM5RST: u1, - /// TIM6 reset - TIM6RST: u1, - /// TIM7 reset - TIM7RST: u1, - /// TIM12 reset - TIM12RST: u1, - /// TIM13 reset - TIM13RST: u1, - /// TIM14 reset - TIM14RST: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved2: u1, - reserved3: u1, - /// SPI 2 reset - SPI2RST: u1, - /// SPI 3 reset - SPI3RST: u1, - reserved4: u1, - /// USART 2 reset - UART2RST: u1, - /// USART 3 reset - UART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - reserved5: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - reserved6: u1, - /// Power interface reset - PWRRST: u1, - /// DAC reset - DACRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40023824 - /// APB2 peripheral reset register - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 reset - TIM1RST: u1, - /// TIM8 reset - TIM8RST: u1, - reserved0: u1, - reserved1: u1, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - reserved2: u1, - reserved3: u1, - /// ADC interface reset (common to all - /// ADCs) - ADCRST: u1, - reserved4: u1, - reserved5: u1, - /// SDIO reset - SDIORST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved6: u1, - /// System configuration controller - /// reset - SYSCFGRST: u1, - reserved7: u1, - /// TIM9 reset - TIM9RST: u1, - /// TIM10 reset - TIM10RST: u1, - /// TIM11 reset - TIM11RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x24); - - /// address: 0x40023830 - /// AHB1 peripheral clock register - pub const AHB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC clock enable - CRCEN: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Backup SRAM interface clock - /// enable - BKPSRAMEN: u1, - reserved8: u1, - reserved9: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved10: u1, - reserved11: u1, - /// Ethernet MAC clock enable - ETHMACEN: u1, - /// Ethernet Transmission clock - /// enable - ETHMACTXEN: u1, - /// Ethernet Reception clock - /// enable - ETHMACRXEN: u1, - /// Ethernet PTP clock enable - ETHMACPTPEN: u1, - /// USB OTG HS clock enable - OTGHSEN: u1, - /// USB OTG HSULPI clock - /// enable - OTGHSULPIEN: u1, - padding0: u1, - }), base_address + 0x30); - - /// address: 0x40023834 - /// AHB2 peripheral clock enable - /// register - pub const AHB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface enable - DCMIEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Random number generator clock - /// enable - RNGEN: u1, - /// USB OTG FS clock enable - OTGFSEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x34); - - /// address: 0x40023838 - /// AHB3 peripheral clock enable - /// register - pub const AHB3ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible static memory controller module - /// clock enable - FSMCEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x38); - - /// address: 0x40023840 - /// APB1 peripheral clock enable - /// register - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 clock enable - TIM2EN: u1, - /// TIM3 clock enable - TIM3EN: u1, - /// TIM4 clock enable - TIM4EN: u1, - /// TIM5 clock enable - TIM5EN: u1, - /// TIM6 clock enable - TIM6EN: u1, - /// TIM7 clock enable - TIM7EN: u1, - /// TIM12 clock enable - TIM12EN: u1, - /// TIM13 clock enable - TIM13EN: u1, - /// TIM14 clock enable - TIM14EN: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog clock - /// enable - WWDGEN: u1, - reserved2: u1, - reserved3: u1, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved4: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - reserved5: u1, - /// CAN 1 clock enable - CAN1EN: u1, - /// CAN 2 clock enable - CAN2EN: u1, - reserved6: u1, - /// Power interface clock - /// enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x40); - - /// address: 0x40023844 - /// APB2 peripheral clock enable - /// register - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 clock enable - TIM1EN: u1, - /// TIM8 clock enable - TIM8EN: u1, - reserved0: u1, - reserved1: u1, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - reserved2: u1, - reserved3: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// ADC2 clock enable - ADC2EN: u1, - /// ADC3 clock enable - ADC3EN: u1, - /// SDIO clock enable - SDIOEN: u1, - /// SPI1 clock enable - SPI1EN: u1, - reserved4: u1, - /// System configuration controller clock - /// enable - SYSCFGEN: u1, - reserved5: u1, - /// TIM9 clock enable - TIM9EN: u1, - /// TIM10 clock enable - TIM10EN: u1, - /// TIM11 clock enable - TIM11EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x44); - - /// address: 0x40023850 - /// AHB1 peripheral clock enable in low power - /// mode register - pub const AHB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A clock enable during sleep - /// mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep - /// mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep - /// mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep - /// mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep - /// mode - GPIOELPEN: u1, - /// IO port F clock enable during Sleep - /// mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep - /// mode - GPIOGLPEN: u1, - /// IO port H clock enable during Sleep - /// mode - GPIOHLPEN: u1, - /// IO port I clock enable during Sleep - /// mode - GPIOILPEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC clock enable during Sleep - /// mode - CRCLPEN: u1, - reserved3: u1, - reserved4: u1, - /// Flash interface clock enable during - /// Sleep mode - FLITFLPEN: u1, - /// SRAM 1interface clock enable during - /// Sleep mode - SRAM1LPEN: u1, - /// SRAM 2 interface clock enable during - /// Sleep mode - SRAM2LPEN: u1, - /// Backup SRAM interface clock enable - /// during Sleep mode - BKPSRAMLPEN: u1, - reserved5: u1, - reserved6: u1, - /// DMA1 clock enable during Sleep - /// mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep - /// mode - DMA2LPEN: u1, - reserved7: u1, - reserved8: u1, - /// Ethernet MAC clock enable during Sleep - /// mode - ETHMACLPEN: u1, - /// Ethernet transmission clock enable - /// during Sleep mode - ETHMACTXLPEN: u1, - /// Ethernet reception clock enable during - /// Sleep mode - ETHMACRXLPEN: u1, - /// Ethernet PTP clock enable during Sleep - /// mode - ETHMACPTPLPEN: u1, - /// USB OTG HS clock enable during Sleep - /// mode - OTGHSLPEN: u1, - /// USB OTG HS ULPI clock enable during - /// Sleep mode - OTGHSULPILPEN: u1, - padding0: u1, - }), base_address + 0x50); - - /// address: 0x40023854 - /// AHB2 peripheral clock enable in low power - /// mode register - pub const AHB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface enable during Sleep - /// mode - DCMILPEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Random number generator clock enable - /// during Sleep mode - RNGLPEN: u1, - /// USB OTG FS clock enable during Sleep - /// mode - OTGFSLPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40023858 - /// AHB3 peripheral clock enable in low power - /// mode register - pub const AHB3LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible static memory controller module - /// clock enable during Sleep mode - FSMCLPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x58); - - /// address: 0x40023860 - /// APB1 peripheral clock enable in low power - /// mode register - pub const APB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 clock enable during Sleep - /// mode - TIM2LPEN: u1, - /// TIM3 clock enable during Sleep - /// mode - TIM3LPEN: u1, - /// TIM4 clock enable during Sleep - /// mode - TIM4LPEN: u1, - /// TIM5 clock enable during Sleep - /// mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep - /// mode - TIM6LPEN: u1, - /// TIM7 clock enable during Sleep - /// mode - TIM7LPEN: u1, - /// TIM12 clock enable during Sleep - /// mode - TIM12LPEN: u1, - /// TIM13 clock enable during Sleep - /// mode - TIM13LPEN: u1, - /// TIM14 clock enable during Sleep - /// mode - TIM14LPEN: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog clock enable during - /// Sleep mode - WWDGLPEN: u1, - reserved2: u1, - reserved3: u1, - /// SPI2 clock enable during Sleep - /// mode - SPI2LPEN: u1, - /// SPI3 clock enable during Sleep - /// mode - SPI3LPEN: u1, - reserved4: u1, - /// USART2 clock enable during Sleep - /// mode - USART2LPEN: u1, - /// USART3 clock enable during Sleep - /// mode - USART3LPEN: u1, - /// UART4 clock enable during Sleep - /// mode - UART4LPEN: u1, - /// UART5 clock enable during Sleep - /// mode - UART5LPEN: u1, - /// I2C1 clock enable during Sleep - /// mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep - /// mode - I2C2LPEN: u1, - /// I2C3 clock enable during Sleep - /// mode - I2C3LPEN: u1, - reserved5: u1, - /// CAN 1 clock enable during Sleep - /// mode - CAN1LPEN: u1, - /// CAN 2 clock enable during Sleep - /// mode - CAN2LPEN: u1, - reserved6: u1, - /// Power interface clock enable during - /// Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep - /// mode - DACLPEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x60); - - /// address: 0x40023864 - /// APB2 peripheral clock enabled in low power - /// mode register - pub const APB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 clock enable during Sleep - /// mode - TIM1LPEN: u1, - /// TIM8 clock enable during Sleep - /// mode - TIM8LPEN: u1, - reserved0: u1, - reserved1: u1, - /// USART1 clock enable during Sleep - /// mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep - /// mode - USART6LPEN: u1, - reserved2: u1, - reserved3: u1, - /// ADC1 clock enable during Sleep - /// mode - ADC1LPEN: u1, - /// ADC2 clock enable during Sleep - /// mode - ADC2LPEN: u1, - /// ADC 3 clock enable during Sleep - /// mode - ADC3LPEN: u1, - /// SDIO clock enable during Sleep - /// mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep - /// mode - SPI1LPEN: u1, - reserved4: u1, - /// System configuration controller clock - /// enable during Sleep mode - SYSCFGLPEN: u1, - reserved5: u1, - /// TIM9 clock enable during sleep - /// mode - TIM9LPEN: u1, - /// TIM10 clock enable during Sleep - /// mode - TIM10LPEN: u1, - /// TIM11 clock enable during Sleep - /// mode - TIM11LPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x64); - - /// address: 0x40023870 - /// Backup domain control register - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// External low-speed oscillator - /// enable - LSEON: u1, - /// External low-speed oscillator - /// ready - LSERDY: u1, - /// External low-speed oscillator - /// bypass - LSEBYP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RTC clock source selection - RTCSEL0: u1, - /// RTC clock source selection - RTCSEL1: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software - /// reset - BDRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x70); - - /// address: 0x40023874 - /// clock control & status - /// register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal low-speed oscillator - /// enable - LSION: u1, - /// Internal low-speed oscillator - /// ready - LSIRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Remove reset flag - RMVF: u1, - /// BOR reset flag - BORRSTF: u1, - /// PIN reset flag - PADRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset - /// flag - WDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), base_address + 0x74); - - /// address: 0x40023880 - /// spread spectrum clock generation - /// register - pub const SSCGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved0: u1, - reserved1: u1, - /// Spread Select - SPREADSEL: u1, - /// Spread spectrum modulation - /// enable - SSCGEN: u1, - }), base_address + 0x80); - - /// address: 0x40023884 - /// PLLI2S configuration register - pub const PLLI2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// PLLI2S multiplication factor for - /// VCO - PLLI2SNx: u9, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// PLLI2S division factor for I2S - /// clocks - PLLI2SRx: u3, - padding0: u1, - }), base_address + 0x84); - }; - - /// General-purpose I/Os - pub const GPIOI = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002200c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002201c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOH = struct { - pub const base_address = 0x40021c00; - - /// address: 0x40021c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x40021c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x40021c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOG = struct { - pub const base_address = 0x40021800; - - /// address: 0x40021800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002180c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002181c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOF = struct { - pub const base_address = 0x40021400; - - /// address: 0x40021400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002140c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002141c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOE = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002100c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002101c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOD = struct { - pub const base_address = 0x40020c00; - - /// address: 0x40020c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x40020c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x40020c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOC = struct { - pub const base_address = 0x40020800; - - /// address: 0x40020800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002080c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002081c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOJ = struct { - pub const base_address = 0x40022400; - - /// address: 0x40022400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002240c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002241c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOK = struct { - pub const base_address = 0x40022800; - - /// address: 0x40022800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002280c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002281c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// General-purpose I/Os - pub const GPIOB = struct { - pub const base_address = 0x40020400; - - /// address: 0x40020400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002040c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002041c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// General-purpose I/Os - pub const GPIOA = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002000c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002001c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// System configuration controller - pub const SYSCFG = struct { - pub const base_address = 0x40013800; - - /// address: 0x40013800 - /// memory remap register - pub const MEMRM = @intToPtr(*volatile Mmio(32, packed struct { - /// MEM_MODE - MEM_MODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - - /// address: 0x40013804 - /// peripheral mode configuration - /// register - pub const PMC = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// Ethernet PHY interface - /// selection - MII_RMII_SEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40013808 - /// external interrupt configuration register - /// 1 - pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 0 to - /// 3) - EXTI0: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI1: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI2: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI3: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001380c - /// external interrupt configuration register - /// 2 - pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 4 to - /// 7) - EXTI4: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI5: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI6: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI7: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40013810 - /// external interrupt configuration register - /// 3 - pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 8 to - /// 11) - EXTI8: u4, - /// EXTI x configuration (x = 8 to - /// 11) - EXTI9: u4, - /// EXTI10 - EXTI10: u4, - /// EXTI x configuration (x = 8 to - /// 11) - EXTI11: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013814 - /// external interrupt configuration register - /// 4 - pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 12 to - /// 15) - EXTI12: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI13: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI14: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI15: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013820 - /// Compensation cell control - /// register - pub const CMPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Compensation cell - /// power-down - CMP_PD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// READY - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x20); - }; - - /// Serial peripheral interface - pub const SPI1 = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40013008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001300c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001301c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI2 = struct { - pub const base_address = 0x40003800; - - /// address: 0x40003800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003808 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000380c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003810 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003818 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000381c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003820 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI3 = struct { - pub const base_address = 0x40003c00; - - /// address: 0x40003c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003c08 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x40003c0c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003c10 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003c14 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003c18 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40003c1c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003c20 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S2ext = struct { - pub const base_address = 0x40003400; - - /// address: 0x40003400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000340c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000341c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S3ext = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40004004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40004008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000400c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40004010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40004018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000401c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40004020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI4 = struct { - pub const base_address = 0x40013400; - - /// address: 0x40013400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40013408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001340c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001341c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI5 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40015004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40015008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001500c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40015010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40015014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40015018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001501c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40015020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI6 = struct { - pub const base_address = 0x40015400; - - /// address: 0x40015400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40015404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40015408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001540c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40015410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40015414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40015418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001541c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40015420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - - /// Secure digital input/output - /// interface - pub const SDIO = struct { - pub const base_address = 0x40012c00; - - /// address: 0x40012c00 - /// power control register - pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { - /// PWRCTRL - PWRCTRL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - - /// address: 0x40012c04 - /// SDI clock control register - pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock divide factor - CLKDIV: u8, - /// Clock enable bit - CLKEN: u1, - /// Power saving configuration - /// bit - PWRSAV: u1, - /// Clock divider bypass enable - /// bit - BYPASS: u1, - /// Wide bus mode enable bit - WIDBUS: u2, - /// SDIO_CK dephasing selection - /// bit - NEGEDGE: u1, - /// HW Flow Control enable - HWFC_EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40012c08 - /// argument register - pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { - /// Command argument - CMDARG: u32, - }), base_address + 0x8); - - /// address: 0x40012c0c - /// command register - pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { - /// Command index - CMDINDEX: u6, - /// Wait for response bits - WAITRESP: u2, - /// CPSM waits for interrupt - /// request - WAITINT: u1, - /// CPSM Waits for ends of data transfer - /// (CmdPend internal signal). - WAITPEND: u1, - /// Command path state machine (CPSM) Enable - /// bit - CPSMEN: u1, - /// SD I/O suspend command - SDIOSuspend: u1, - /// Enable CMD completion - ENCMDcompl: u1, - /// not Interrupt Enable - nIEN: u1, - /// CE-ATA command - CE_ATACMD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40012c10 - /// command response register - pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); - - /// address: 0x40012c14 - /// response 1..4 register - pub const RESP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS1: u32, - }), base_address + 0x14); - - /// address: 0x40012c18 - /// response 1..4 register - pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS2: u32, - }), base_address + 0x18); - - /// address: 0x40012c1c - /// response 1..4 register - pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS3: u32, - }), base_address + 0x1c); - - /// address: 0x40012c20 - /// response 1..4 register - pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS4: u32, - }), base_address + 0x20); - - /// address: 0x40012c24 - /// data timer register - pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { - /// Data timeout period - DATATIME: u32, - }), base_address + 0x24); - - /// address: 0x40012c28 - /// data length register - pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length value - DATALENGTH: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x28); - - /// address: 0x40012c2c - /// data control register - pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DTEN - DTEN: u1, - /// Data transfer direction - /// selection - DTDIR: u1, - /// Data transfer mode selection 1: Stream - /// or SDIO multibyte data transfer. - DTMODE: u1, - /// DMA enable bit - DMAEN: u1, - /// Data block size - DBLOCKSIZE: u4, - /// Read wait start - RWSTART: u1, - /// Read wait stop - RWSTOP: u1, - /// Read wait mode - RWMOD: u1, - /// SD I/O enable functions - SDIOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40012c30 - /// data counter register - pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Data count value - DATACOUNT: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - - /// address: 0x40012c34 - /// status register - pub const STA = @intToPtr(*volatile Mmio(32, packed struct { - /// Command response received (CRC check - /// failed) - CCRCFAIL: u1, - /// Data block sent/received (CRC check - /// failed) - DCRCFAIL: u1, - /// Command response timeout - CTIMEOUT: u1, - /// Data timeout - DTIMEOUT: u1, - /// Transmit FIFO underrun - /// error - TXUNDERR: u1, - /// Received FIFO overrun - /// error - RXOVERR: u1, - /// Command response received (CRC check - /// passed) - CMDREND: u1, - /// Command sent (no response - /// required) - CMDSENT: u1, - /// Data end (data counter, SDIDCOUNT, is - /// zero) - DATAEND: u1, - /// Start bit not detected on all data - /// signals in wide bus mode - STBITERR: u1, - /// Data block sent/received (CRC check - /// passed) - DBCKEND: u1, - /// Command transfer in - /// progress - CMDACT: u1, - /// Data transmit in progress - TXACT: u1, - /// Data receive in progress - RXACT: u1, - /// Transmit FIFO half empty: at least 8 - /// words can be written into the FIFO - TXFIFOHE: u1, - /// Receive FIFO half full: there are at - /// least 8 words in the FIFO - RXFIFOHF: u1, - /// Transmit FIFO full - TXFIFOF: u1, - /// Receive FIFO full - RXFIFOF: u1, - /// Transmit FIFO empty - TXFIFOE: u1, - /// Receive FIFO empty - RXFIFOE: u1, - /// Data available in transmit - /// FIFO - TXDAVL: u1, - /// Data available in receive - /// FIFO - RXDAVL: u1, - /// SDIO interrupt received - SDIOIT: u1, - /// CE-ATA command completion signal - /// received for CMD61 - CEATAEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x40012c38 - /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// CCRCFAIL flag clear bit - CCRCFAILC: u1, - /// DCRCFAIL flag clear bit - DCRCFAILC: u1, - /// CTIMEOUT flag clear bit - CTIMEOUTC: u1, - /// DTIMEOUT flag clear bit - DTIMEOUTC: u1, - /// TXUNDERR flag clear bit - TXUNDERRC: u1, - /// RXOVERR flag clear bit - RXOVERRC: u1, - /// CMDREND flag clear bit - CMDRENDC: u1, - /// CMDSENT flag clear bit - CMDSENTC: u1, - /// DATAEND flag clear bit - DATAENDC: u1, - /// STBITERR flag clear bit - STBITERRC: u1, - /// DBCKEND flag clear bit - DBCKENDC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// SDIOIT flag clear bit - SDIOITC: u1, - /// CEATAEND flag clear bit - CEATAENDC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x38); - - /// address: 0x40012c3c - /// mask register - pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { - /// Command CRC fail interrupt - /// enable - CCRCFAILIE: u1, - /// Data CRC fail interrupt - /// enable - DCRCFAILIE: u1, - /// Command timeout interrupt - /// enable - CTIMEOUTIE: u1, - /// Data timeout interrupt - /// enable - DTIMEOUTIE: u1, - /// Tx FIFO underrun error interrupt - /// enable - TXUNDERRIE: u1, - /// Rx FIFO overrun error interrupt - /// enable - RXOVERRIE: u1, - /// Command response received interrupt - /// enable - CMDRENDIE: u1, - /// Command sent interrupt - /// enable - CMDSENTIE: u1, - /// Data end interrupt enable - DATAENDIE: u1, - /// Start bit error interrupt - /// enable - STBITERRIE: u1, - /// Data block end interrupt - /// enable - DBCKENDIE: u1, - /// Command acting interrupt - /// enable - CMDACTIE: u1, - /// Data transmit acting interrupt - /// enable - TXACTIE: u1, - /// Data receive acting interrupt - /// enable - RXACTIE: u1, - /// Tx FIFO half empty interrupt - /// enable - TXFIFOHEIE: u1, - /// Rx FIFO half full interrupt - /// enable - RXFIFOHFIE: u1, - /// Tx FIFO full interrupt - /// enable - TXFIFOFIE: u1, - /// Rx FIFO full interrupt - /// enable - RXFIFOFIE: u1, - /// Tx FIFO empty interrupt - /// enable - TXFIFOEIE: u1, - /// Rx FIFO empty interrupt - /// enable - RXFIFOEIE: u1, - /// Data available in Tx FIFO interrupt - /// enable - TXDAVLIE: u1, - /// Data available in Rx FIFO interrupt - /// enable - RXDAVLIE: u1, - /// SDIO mode interrupt received interrupt - /// enable - SDIOITIE: u1, - /// CE-ATA command completion signal - /// received interrupt enable - CEATAENDIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x3c); - - /// address: 0x40012c48 - /// FIFO counter register - pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Remaining number of words to be written - /// to or read from the FIFO. - FIFOCOUNT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x48); - - /// address: 0x40012c80 - /// data FIFO register - pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive and transmit FIFO - /// data - FIFOData: u32, - }), base_address + 0x80); - }; - - /// Analog-to-digital converter - pub const ADC1 = struct { - pub const base_address = 0x40012000; - - /// address: 0x40012000 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012004 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012008 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001200c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012010 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012014 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012018 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001201c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012020 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012024 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012028 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001202c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012030 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012034 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012038 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001203c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012040 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012044 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012048 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001204c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const ADC2 = struct { - pub const base_address = 0x40012100; - - /// address: 0x40012100 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012104 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012108 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001210c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012110 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012114 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012118 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001211c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012120 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012124 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012128 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001212c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012130 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012134 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012138 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001213c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012140 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012144 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012148 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001214c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const ADC3 = struct { - pub const base_address = 0x40012200; - - /// address: 0x40012200 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012204 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012208 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001220c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012210 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012214 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012218 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001221c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012220 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012224 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012228 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001222c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012230 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012234 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012238 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001223c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012240 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012244 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012248 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001224c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const USART6 = struct { - pub const base_address = 0x40011400; - - /// address: 0x40011400 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40011404 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40011408 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001140c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011410 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40011414 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40011418 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART1 = struct { - pub const base_address = 0x40011000; - - /// address: 0x40011000 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40011004 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40011008 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001100c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011010 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40011014 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40011018 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART2 = struct { - pub const base_address = 0x40004400; - - /// address: 0x40004400 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004404 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004408 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000440c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004410 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004414 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40004418 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART3 = struct { - pub const base_address = 0x40004800; - - /// address: 0x40004800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000480c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40004818 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - - /// Digital-to-analog converter - pub const DAC = struct { - pub const base_address = 0x40007400; - - /// address: 0x40007400 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 enable - EN1: u1, - /// DAC channel1 output buffer - /// disable - BOFF1: u1, - /// DAC channel1 trigger - /// enable - TEN1: u1, - /// DAC channel1 trigger - /// selection - TSEL1: u3, - /// DAC channel1 noise/triangle wave - /// generation enable - WAVE1: u2, - /// DAC channel1 mask/amplitude - /// selector - MAMP1: u4, - /// DAC channel1 DMA enable - DMAEN1: u1, - /// DAC channel1 DMA Underrun Interrupt - /// enable - DMAUDRIE1: u1, - reserved0: u1, - reserved1: u1, - /// DAC channel2 enable - EN2: u1, - /// DAC channel2 output buffer - /// disable - BOFF2: u1, - /// DAC channel2 trigger - /// enable - TEN2: u1, - /// DAC channel2 trigger - /// selection - TSEL2: u3, - /// DAC channel2 noise/triangle wave - /// generation enable - WAVE2: u2, - /// DAC channel2 mask/amplitude - /// selector - MAMP2: u4, - /// DAC channel2 DMA enable - DMAEN2: u1, - /// DAC channel2 DMA underrun interrupt - /// enable - DMAUDRIE2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x40007404 - /// software trigger register - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 software - /// trigger - SWTRIG1: u1, - /// DAC channel2 software - /// trigger - SWTRIG2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40007408 - /// channel1 12-bit right-aligned data holding - /// register - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000740c - /// channel1 12-bit left aligned data holding - /// register - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007410 - /// channel1 8-bit right aligned data holding - /// register - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40007414 - /// channel2 12-bit right aligned data holding - /// register - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007418 - /// channel2 12-bit left aligned data holding - /// register - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000741c - /// channel2 8-bit right-aligned data holding - /// register - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1c); - - /// address: 0x40007420 - /// Dual DAC 12-bit right-aligned data holding - /// register - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x40007424 - /// DUAL DAC 12-bit left aligned data holding - /// register - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - }), base_address + 0x24); - - /// address: 0x40007428 - /// DUAL DAC 8-bit right aligned data holding - /// register - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000742c - /// channel1 data output register - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40007430 - /// channel2 data output register - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - - /// address: 0x40007434 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// DAC channel1 DMA underrun - /// flag - DMAUDR1: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - /// DAC channel2 DMA underrun - /// flag - DMAUDR2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - }; - - /// Power control - pub const PWR = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// power control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: u1, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector - /// enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write - /// protection - DBP: u1, - /// Flash power down in Stop - /// mode - FPDS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40007004 - /// power control/status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Backup regulator ready - BRR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Enable WKUP pin - EWUP: u1, - /// Backup regulator enable - BRE: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Regulator voltage scaling output - /// selection ready bit - VOSRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - }; - - /// Inter-integrated circuit - pub const I2C3 = struct { - pub const base_address = 0x40005c00; - - /// address: 0x40005c00 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005c04 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005c08 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40005c0c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005c10 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005c14 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005c18 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40005c1c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005c20 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - }; - pub const I2C2 = struct { - pub const base_address = 0x40005800; - - /// address: 0x40005800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005808 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000580c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005810 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005814 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005818 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000581c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005820 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - }; - pub const I2C1 = struct { - pub const base_address = 0x40005400; - - /// address: 0x40005400 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005404 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005408 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000540c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005410 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005414 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005418 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000541c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005420 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - }; - - /// Independent watchdog - pub const IWDG = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Key register - pub const KR = @intToPtr(*volatile Mmio(32, packed struct { - /// Key value (write only, read - /// 0000h) - KEY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Prescaler register - pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); - - /// address: 0x40003008 - /// Reload register - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog counter reload - /// value - RL: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog prescaler value - /// update - PVU: u1, - /// Watchdog counter reload value - /// update - RVU: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - }; - - /// Window watchdog - pub const WWDG = struct { - pub const base_address = 0x40002c00; - - /// address: 0x40002c00 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit counter (MSB to LSB) - T: u7, - /// Activation bit - WDGA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40002c04 - /// Configuration register - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit window value - W: u7, - /// Timer base - WDGTB0: u1, - /// Timer base - WDGTB1: u1, - /// Early wakeup interrupt - EWI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x40002c08 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Early wakeup interrupt - /// flag - EWIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// Real-time clock - pub const RTC = struct { - pub const base_address = 0x40002800; - - /// address: 0x40002800 - /// time register - pub const TR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved0: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved1: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x0); - - /// address: 0x40002804 - /// date register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup clock selection - WCKSEL: u3, - /// Time-stamp event active - /// edge - TSEDGE: u1, - /// Reference clock detection enable (50 or - /// 60 Hz) - REFCKON: u1, - reserved0: u1, - /// Hour format - FMT: u1, - /// Coarse digital calibration - /// enable - DCE: u1, - /// Alarm A enable - ALRAE: u1, - /// Alarm B enable - ALRBE: u1, - /// Wakeup timer enable - WUTE: u1, - /// Time stamp enable - TSE: u1, - /// Alarm A interrupt enable - ALRAIE: u1, - /// Alarm B interrupt enable - ALRBIE: u1, - /// Wakeup timer interrupt - /// enable - WUTIE: u1, - /// Time-stamp interrupt - /// enable - TSIE: u1, - /// Add 1 hour (summer time - /// change) - ADD1H: u1, - /// Subtract 1 hour (winter time - /// change) - SUB1H: u1, - /// Backup - BKP: u1, - reserved1: u1, - /// Output polarity - POL: u1, - /// Output selection - OSEL: u2, - /// Calibration output enable - COE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4000280c - /// initialization and status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Alarm A write flag - ALRAWF: u1, - /// Alarm B write flag - ALRBWF: u1, - /// Wakeup timer write flag - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization - /// flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Initialization mode - INIT: u1, - /// Alarm A flag - ALRAF: u1, - /// Alarm B flag - ALRBF: u1, - /// Wakeup timer flag - WUTF: u1, - /// Time-stamp flag - TSF: u1, - /// Time-stamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMP1F: u1, - /// TAMPER2 detection flag - TAMP2F: u1, - reserved0: u1, - /// Recalibration pending Flag - RECALPF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xc); - - /// address: 0x40002810 - /// prescaler register - pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { - /// Synchronous prescaler - /// factor - PREDIV_S: u15, - reserved0: u1, - /// Asynchronous prescaler - /// factor - PREDIV_A: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x10); - - /// address: 0x40002814 - /// wakeup timer register - pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup auto-reload value - /// bits - WUT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40002818 - /// calibration register - pub const CALIBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital calibration - DC: u5, - reserved0: u1, - reserved1: u1, - /// Digital calibration sign - DCS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x4000281c - /// alarm A register - pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm A hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm A date mask - MSK4: u1, - }), base_address + 0x1c); - - /// address: 0x40002820 - /// alarm B register - pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm B seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm B minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm B hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm B date mask - MSK4: u1, - }), base_address + 0x20); - - /// address: 0x40002824 - /// write protection register - pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write protection key - KEY: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40002828 - /// sub second register - pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000282c - /// shift control register - pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Subtract a fraction of a - /// second - SUBFS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Add one second - ADD1S: u1, - }), base_address + 0x2c); - - /// address: 0x40002830 - /// time stamp time register - pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1, - /// Active level for tamper 1 - TAMP1TRG: u1, - /// Tamper interrupt enable - TAMPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// TAMPER1 mapping - TAMP1INSEL: u1, - /// TIMESTAMP mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x30); - - /// address: 0x40002834 - /// time stamp date register - pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40002838 - /// timestamp sub second register - pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x38); - - /// address: 0x4000283c - /// calibration register - pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration minus - CALM: u9, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Use a 16-second calibration cycle - /// period - CALW16: u1, - /// Use an 8-second calibration cycle - /// period - CALW8: u1, - /// Increase frequency of RTC by 488.5 - /// ppm - CALP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40002840 - /// tamper and alternate function configuration - /// register - pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1, - /// Active level for tamper 1 - TAMP1TRG: u1, - /// Tamper interrupt enable - TAMPIE: u1, - /// Tamper 2 detection enable - TAMP2E: u1, - /// Active level for tamper 2 - TAMP2TRG: u1, - reserved0: u1, - reserved1: u1, - /// Activate timestamp on tamper detection - /// event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: u3, - /// Tamper filter count - TAMPFLT: u2, - /// Tamper precharge duration - TAMPPRCH: u2, - /// TAMPER pull-up disable - TAMPPUDIS: u1, - /// TAMPER1 mapping - TAMP1INSEL: u1, - /// TIMESTAMP mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x40002844 - /// alarm A sub second register - pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x44); - - /// address: 0x40002848 - /// alarm B sub second register - pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x48); - - /// address: 0x40002850 - /// backup register - pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x50); - - /// address: 0x40002854 - /// backup register - pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x54); - - /// address: 0x40002858 - /// backup register - pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x58); - - /// address: 0x4000285c - /// backup register - pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x5c); - - /// address: 0x40002860 - /// backup register - pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x60); - - /// address: 0x40002864 - /// backup register - pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x64); - - /// address: 0x40002868 - /// backup register - pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x68); - - /// address: 0x4000286c - /// backup register - pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x6c); - - /// address: 0x40002870 - /// backup register - pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x70); - - /// address: 0x40002874 - /// backup register - pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x74); - - /// address: 0x40002878 - /// backup register - pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x78); - - /// address: 0x4000287c - /// backup register - pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x7c); - - /// address: 0x40002880 - /// backup register - pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x80); - - /// address: 0x40002884 - /// backup register - pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x84); - - /// address: 0x40002888 - /// backup register - pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x88); - - /// address: 0x4000288c - /// backup register - pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x8c); - - /// address: 0x40002890 - /// backup register - pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x90); - - /// address: 0x40002894 - /// backup register - pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x94); - - /// address: 0x40002898 - /// backup register - pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x98); - - /// address: 0x4000289c - /// backup register - pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x9c); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const UART4 = struct { - pub const base_address = 0x40004c00; - - /// address: 0x40004c00 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40004c04 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004c08 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40004c0c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004c10 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004c14 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - pub const UART5 = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40005008 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000500c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005010 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40005014 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - pub const UART7 = struct { - pub const base_address = 0x40007800; - - /// address: 0x40007800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40007804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40007808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000780c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40007814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - pub const UART8 = struct { - pub const base_address = 0x40007c00; - - /// address: 0x40007c00 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40007c04 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40007c08 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40007c0c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007c10 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40007c14 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - - /// Common ADC registers - pub const C_ADC = struct { - pub const base_address = 0x40012300; - - /// address: 0x40012300 - /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag of ADC - /// 1 - AWD1: u1, - /// End of conversion of ADC 1 - EOC1: u1, - /// Injected channel end of conversion of - /// ADC 1 - JEOC1: u1, - /// Injected channel Start flag of ADC - /// 1 - JSTRT1: u1, - /// Regular channel Start flag of ADC - /// 1 - STRT1: u1, - /// Overrun flag of ADC 1 - OVR1: u1, - reserved0: u1, - reserved1: u1, - /// Analog watchdog flag of ADC - /// 2 - AWD2: u1, - /// End of conversion of ADC 2 - EOC2: u1, - /// Injected channel end of conversion of - /// ADC 2 - JEOC2: u1, - /// Injected channel Start flag of ADC - /// 2 - JSTRT2: u1, - /// Regular channel Start flag of ADC - /// 2 - STRT2: u1, - /// Overrun flag of ADC 2 - OVR2: u1, - reserved2: u1, - reserved3: u1, - /// Analog watchdog flag of ADC - /// 3 - AWD3: u1, - /// End of conversion of ADC 3 - EOC3: u1, - /// Injected channel end of conversion of - /// ADC 3 - JEOC3: u1, - /// Injected channel Start flag of ADC - /// 3 - JSTRT3: u1, - /// Regular channel Start flag of ADC - /// 3 - STRT3: u1, - /// Overrun flag of ADC3 - OVR3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x0); - - /// address: 0x40012304 - /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Multi ADC mode selection - MULT: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Delay between 2 sampling - /// phases - DELAY: u4, - reserved3: u1, - /// DMA disable selection for multi-ADC - /// mode - DDS: u1, - /// Direct memory access mode for multi ADC - /// mode - DMA: u2, - /// ADC prescaler - ADCPRE: u2, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// VBAT enable - VBATE: u1, - /// Temperature sensor and VREFINT - /// enable - TSVREFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012308 - /// ADC common regular data register for dual - /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st data item of a pair of regular - /// conversions - DATA1: u16, - /// 2nd data item of a pair of regular - /// conversions - DATA2: u16, - }), base_address + 0x8); - }; - - /// Advanced-timers - pub const TIM1 = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40010004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40010008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40010014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40010018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40010018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4001001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40010020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40010024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40010028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40010034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40010038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40010040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40010048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40010030 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40010044 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - pub const TIM8 = struct { - pub const base_address = 0x40010400; - - /// address: 0x40010400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40010404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40010408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40010410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40010414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40010418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40010418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4001041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40010420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40010424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40010428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40010434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40010438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40010440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40010448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40010430 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40010444 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - - /// General purpose timers - pub const TIM2 = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40000050 - /// TIM5 option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Timer Input 4 remap - ITR1_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x50); - }; - - /// General purpose timers - pub const TIM3 = struct { - pub const base_address = 0x40000400; - - /// address: 0x40000400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM4 = struct { - pub const base_address = 0x40000800; - - /// address: 0x40000800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000080c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000081c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000081c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000824 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000082c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000083c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000840 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000848 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000084c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// General-purpose-timers - pub const TIM5 = struct { - pub const base_address = 0x40000c00; - - /// address: 0x40000c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40000c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000c24 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40000c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x40000c3c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000c40 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000c48 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x40000c4c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40000c50 - /// TIM5 option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Timer Input 4 remap - IT4_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x50); - }; - - /// General purpose timers - pub const TIM9 = struct { - pub const base_address = 0x40014000; - - /// address: 0x40014000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40014004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40014008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4001400c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40014010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40014014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40014018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40014018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40014020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40014024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001402c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - pub const TIM12 = struct { - pub const base_address = 0x40001800; - - /// address: 0x40001800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40001808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4000180c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40001810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40001814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40001818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40001818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40001820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40001824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000182c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40001838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - - /// General-purpose-timers - pub const TIM10 = struct { - pub const base_address = 0x40014400; - - /// address: 0x40014400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4001440c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40014410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40014418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40014418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001442c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM13 = struct { - pub const base_address = 0x40001c00; - - /// address: 0x40001c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40001c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40001c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40001c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40001c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40001c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40001c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40001c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM14 = struct { - pub const base_address = 0x40002000; - - /// address: 0x40002000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4000200c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40002010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40002014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40002018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40002018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40002020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40002024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40002028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000202c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40002034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - - /// General-purpose-timers - pub const TIM11 = struct { - pub const base_address = 0x40014800; - - /// address: 0x40014800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4001480c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40014810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40014818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40014818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001482c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014850 - /// option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input 1 remapping - /// capability - RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x50); - }; - - /// Basic timers - pub const TIM6 = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000100c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000102c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - pub const TIM7 = struct { - pub const base_address = 0x40001400; - - /// address: 0x40001400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000140c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000142c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - - /// Ethernet: media access control - /// (MAC) - pub const Ethernet_MAC = struct { - pub const base_address = 0x40028000; - - /// address: 0x40028000 - /// Ethernet MAC configuration - /// register - pub const MACCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// RE - RE: u1, - /// TE - TE: u1, - /// DC - DC: u1, - /// BL - BL: u2, - /// APCS - APCS: u1, - reserved2: u1, - /// RD - RD: u1, - /// IPCO - IPCO: u1, - /// DM - DM: u1, - /// LM - LM: u1, - /// ROD - ROD: u1, - /// FES - FES: u1, - reserved3: u1, - /// CSD - CSD: u1, - /// IFG - IFG: u3, - reserved4: u1, - reserved5: u1, - /// JD - JD: u1, - /// WD - WD: u1, - reserved6: u1, - /// CSTF - CSTF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40028004 - /// Ethernet MAC frame filter - /// register - pub const MACFFR = @intToPtr(*volatile Mmio(32, packed struct { - /// PM - PM: u1, - /// HU - HU: u1, - /// HM - HM: u1, - /// DAIF - DAIF: u1, - /// RAM - RAM: u1, - /// BFD - BFD: u1, - /// PCF - PCF: u1, - /// SAIF - SAIF: u1, - /// SAF - SAF: u1, - /// HPF - HPF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// RA - RA: u1, - }), base_address + 0x4); - - /// address: 0x40028008 - /// Ethernet MAC hash table high - /// register - pub const MACHTHR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTH - HTH: u32, - }), base_address + 0x8); - - /// address: 0x4002800c - /// Ethernet MAC hash table low - /// register - pub const MACHTLR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTL - HTL: u32, - }), base_address + 0xc); - - /// address: 0x40028010 - /// Ethernet MAC MII address - /// register - pub const MACMIIAR = @intToPtr(*volatile Mmio(32, packed struct { - /// MB - MB: u1, - /// MW - MW: u1, - /// CR - CR: u3, - reserved0: u1, - /// MR - MR: u5, - /// PA - PA: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40028014 - /// Ethernet MAC MII data register - pub const MACMIIDR = @intToPtr(*volatile Mmio(32, packed struct { - /// TD - TD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40028018 - /// Ethernet MAC flow control - /// register - pub const MACFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FCB - FCB: u1, - /// TFCE - TFCE: u1, - /// RFCE - RFCE: u1, - /// UPFD - UPFD: u1, - /// PLT - PLT: u2, - reserved0: u1, - /// ZQPD - ZQPD: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// PT - PT: u16, - }), base_address + 0x18); - - /// address: 0x4002801c - /// Ethernet MAC VLAN tag register - pub const MACVLANTR = @intToPtr(*volatile Mmio(32, packed struct { - /// VLANTI - VLANTI: u16, - /// VLANTC - VLANTC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x4002802c - /// Ethernet MAC PMT control and status - /// register - pub const MACPMTCSR = @intToPtr(*volatile Mmio(32, packed struct { - /// PD - PD: u1, - /// MPE - MPE: u1, - /// WFE - WFE: u1, - reserved0: u1, - reserved1: u1, - /// MPR - MPR: u1, - /// WFR - WFR: u1, - reserved2: u1, - reserved3: u1, - /// GU - GU: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - /// WFFRPR - WFFRPR: u1, - }), base_address + 0x2c); - - /// address: 0x40028034 - /// Ethernet MAC debug register - pub const MACDBGR = @intToPtr(*volatile Mmio(32, packed struct { - /// CR - CR: u1, - /// CSR - CSR: u1, - /// ROR - ROR: u1, - /// MCF - MCF: u1, - /// MCP - MCP: u1, - /// MCFHP - MCFHP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x34); - - /// address: 0x40028038 - /// Ethernet MAC interrupt status - /// register - pub const MACSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// PMTS - PMTS: u1, - /// MMCS - MMCS: u1, - /// MMCRS - MMCRS: u1, - /// MMCTS - MMCTS: u1, - reserved3: u1, - reserved4: u1, - /// TSTS - TSTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x38); - - /// address: 0x4002803c - /// Ethernet MAC interrupt mask - /// register - pub const MACIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// PMTIM - PMTIM: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// TSTIM - TSTIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x3c); - - /// address: 0x40028040 - /// Ethernet MAC address 0 high - /// register - pub const MACA0HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MAC address0 high - MACA0H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Always 1 - MO: u1, - }), base_address + 0x40); - - /// address: 0x40028044 - /// Ethernet MAC address 0 low - /// register - pub const MACA0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 - MACA0L: u32, - }), base_address + 0x44); - - /// address: 0x40028048 - /// Ethernet MAC address 1 high - /// register - pub const MACA1HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA1H - MACA1H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x48); - - /// address: 0x4002804c - /// Ethernet MAC address1 low - /// register - pub const MACA1LR = @intToPtr(*volatile u32, base_address + 0x4c); - - /// address: 0x40028050 - /// Ethernet MAC address 2 high - /// register - pub const MACA2HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MAC2AH - MAC2AH: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x50); - - /// address: 0x40028054 - /// Ethernet MAC address 2 low - /// register - pub const MACA2LR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA2L - MACA2L: u31, - padding0: u1, - }), base_address + 0x54); - - /// address: 0x40028058 - /// Ethernet MAC address 3 high - /// register - pub const MACA3HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA3H - MACA3H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x58); - - /// address: 0x4002805c - /// Ethernet MAC address 3 low - /// register - pub const MACA3LR = @intToPtr(*volatile Mmio(32, packed struct { - /// MBCA3L - MBCA3L: u32, - }), base_address + 0x5c); - }; - - /// Ethernet: MAC management counters - pub const Ethernet_MMC = struct { - pub const base_address = 0x40028100; - - /// address: 0x40028100 - /// Ethernet MMC control register - pub const MMCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// CR - CR: u1, - /// CSR - CSR: u1, - /// ROR - ROR: u1, - /// MCF - MCF: u1, - /// MCP - MCP: u1, - /// MCFHP - MCFHP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40028104 - /// Ethernet MMC receive interrupt - /// register - pub const MMCRIR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RFCES - RFCES: u1, - /// RFAES - RFAES: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// RGUFS - RGUFS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x4); - - /// address: 0x40028108 - /// Ethernet MMC transmit interrupt - /// register - pub const MMCTIR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TGFSCS - TGFSCS: u1, - /// TGFMSCS - TGFMSCS: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// TGFS - TGFS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x4002810c - /// Ethernet MMC receive interrupt mask - /// register - pub const MMCRIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RFCEM - RFCEM: u1, - /// RFAEM - RFAEM: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// RGUFM - RGUFM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0xc); - - /// address: 0x40028110 - /// Ethernet MMC transmit interrupt mask - /// register - pub const MMCTIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TGFSCM - TGFSCM: u1, - /// TGFMSCM - TGFMSCM: u1, - /// TGFM - TGFM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0x4002814c - /// Ethernet MMC transmitted good frames after a - /// single collision counter - pub const MMCTGFSCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TGFSCC - TGFSCC: u32, - }), base_address + 0x4c); - - /// address: 0x40028150 - /// Ethernet MMC transmitted good frames after - /// more than a single collision - pub const MMCTGFMSCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TGFMSCC - TGFMSCC: u32, - }), base_address + 0x50); - - /// address: 0x40028168 - /// Ethernet MMC transmitted good frames counter - /// register - pub const MMCTGFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTL - TGFC: u32, - }), base_address + 0x68); - - /// address: 0x40028194 - /// Ethernet MMC received frames with CRC error - /// counter register - pub const MMCRFCECR = @intToPtr(*volatile Mmio(32, packed struct { - /// RFCFC - RFCFC: u32, - }), base_address + 0x94); - - /// address: 0x40028198 - /// Ethernet MMC received frames with alignment - /// error counter register - pub const MMCRFAECR = @intToPtr(*volatile Mmio(32, packed struct { - /// RFAEC - RFAEC: u32, - }), base_address + 0x98); - - /// address: 0x400281c4 - /// MMC received good unicast frames counter - /// register - pub const MMCRGUFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// RGUFC - RGUFC: u32, - }), base_address + 0xc4); - }; - - /// Ethernet: Precision time protocol - pub const Ethernet_PTP = struct { - pub const base_address = 0x40028700; - - /// address: 0x40028700 - /// Ethernet PTP time stamp control - /// register - pub const PTPTSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSE - TSE: u1, - /// TSFCU - TSFCU: u1, - /// TSSTI - TSSTI: u1, - /// TSSTU - TSSTU: u1, - /// TSITE - TSITE: u1, - /// TTSARU - TTSARU: u1, - reserved0: u1, - reserved1: u1, - /// TSSARFE - TSSARFE: u1, - /// TSSSR - TSSSR: u1, - /// TSPTPPSV2E - TSPTPPSV2E: u1, - /// TSSPTPOEFE - TSSPTPOEFE: u1, - /// TSSIPV6FE - TSSIPV6FE: u1, - /// TSSIPV4FE - TSSIPV4FE: u1, - /// TSSEME - TSSEME: u1, - /// TSSMRME - TSSMRME: u1, - /// TSCNT - TSCNT: u2, - /// TSPFFMAE - TSPFFMAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x40028704 - /// Ethernet PTP subsecond increment - /// register - pub const PTPSSIR = @intToPtr(*volatile Mmio(32, packed struct { - /// STSSI - STSSI: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40028708 - /// Ethernet PTP time stamp high - /// register - pub const PTPTSHR = @intToPtr(*volatile Mmio(32, packed struct { - /// STS - STS: u32, - }), base_address + 0x8); - - /// address: 0x4002870c - /// Ethernet PTP time stamp low - /// register - pub const PTPTSLR = @intToPtr(*volatile Mmio(32, packed struct { - /// STSS - STSS: u31, - /// STPNS - STPNS: u1, - }), base_address + 0xc); - - /// address: 0x40028710 - /// Ethernet PTP time stamp high update - /// register - pub const PTPTSHUR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSUS - TSUS: u32, - }), base_address + 0x10); - - /// address: 0x40028714 - /// Ethernet PTP time stamp low update - /// register - pub const PTPTSLUR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSUSS - TSUSS: u31, - /// TSUPNS - TSUPNS: u1, - }), base_address + 0x14); - - /// address: 0x40028718 - /// Ethernet PTP time stamp addend - /// register - pub const PTPTSAR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSA - TSA: u32, - }), base_address + 0x18); - - /// address: 0x4002871c - /// Ethernet PTP target time high - /// register - pub const PTPTTHR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 - TTSH: u32, - }), base_address + 0x1c); - - /// address: 0x40028720 - /// Ethernet PTP target time low - /// register - pub const PTPTTLR = @intToPtr(*volatile Mmio(32, packed struct { - /// TTSL - TTSL: u32, - }), base_address + 0x20); - - /// address: 0x40028728 - /// Ethernet PTP time stamp status - /// register - pub const PTPTSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x28); - - /// address: 0x4002872c - /// Ethernet PTP PPS control - /// register - pub const PTPPPSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x2c); - }; - - /// Ethernet: DMA controller operation - pub const Ethernet_DMA = struct { - pub const base_address = 0x40029000; - - /// address: 0x40029000 - /// Ethernet DMA bus mode register - pub const DMABMR = @intToPtr(*volatile Mmio(32, packed struct { - /// SR - SR: u1, - /// DA - DA: u1, - /// DSL - DSL: u5, - /// EDFE - EDFE: u1, - /// PBL - PBL: u6, - /// RTPR - RTPR: u2, - /// FB - FB: u1, - /// RDP - RDP: u6, - /// USP - USP: u1, - /// FPM - FPM: u1, - /// AAB - AAB: u1, - /// MB - MB: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x0); - - /// address: 0x40029004 - /// Ethernet DMA transmit poll demand - /// register - pub const DMATPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// TPD - TPD: u32, - }), base_address + 0x4); - - /// address: 0x40029008 - /// EHERNET DMA receive poll demand - /// register - pub const DMARPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// RPD - RPD: u32, - }), base_address + 0x8); - - /// address: 0x4002900c - /// Ethernet DMA receive descriptor list address - /// register - pub const DMARDLAR = @intToPtr(*volatile Mmio(32, packed struct { - /// SRL - SRL: u32, - }), base_address + 0xc); - - /// address: 0x40029010 - /// Ethernet DMA transmit descriptor list - /// address register - pub const DMATDLAR = @intToPtr(*volatile Mmio(32, packed struct { - /// STL - STL: u32, - }), base_address + 0x10); - - /// address: 0x40029014 - /// Ethernet DMA status register - pub const DMASR = @intToPtr(*volatile Mmio(32, packed struct { - /// TS - TS: u1, - /// TPSS - TPSS: u1, - /// TBUS - TBUS: u1, - /// TJTS - TJTS: u1, - /// ROS - ROS: u1, - /// TUS - TUS: u1, - /// RS - RS: u1, - /// RBUS - RBUS: u1, - /// RPSS - RPSS: u1, - /// PWTS - PWTS: u1, - /// ETS - ETS: u1, - reserved0: u1, - reserved1: u1, - /// FBES - FBES: u1, - /// ERS - ERS: u1, - /// AIS - AIS: u1, - /// NIS - NIS: u1, - /// RPS - RPS: u3, - /// TPS - TPS: u3, - /// EBS - EBS: u3, - reserved2: u1, - /// MMCS - MMCS: u1, - /// PMTS - PMTS: u1, - /// TSTS - TSTS: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x40029018 - /// Ethernet DMA operation mode - /// register - pub const DMAOMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// SR - SR: u1, - /// OSF - OSF: u1, - /// RTC - RTC: u2, - reserved1: u1, - /// FUGF - FUGF: u1, - /// FEF - FEF: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// ST - ST: u1, - /// TTC - TTC: u3, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// FTF - FTF: u1, - /// TSF - TSF: u1, - reserved10: u1, - reserved11: u1, - /// DFRF - DFRF: u1, - /// RSF - RSF: u1, - /// DTCEFD - DTCEFD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x4002901c - /// Ethernet DMA interrupt enable - /// register - pub const DMAIER = @intToPtr(*volatile Mmio(32, packed struct { - /// TIE - TIE: u1, - /// TPSIE - TPSIE: u1, - /// TBUIE - TBUIE: u1, - /// TJTIE - TJTIE: u1, - /// ROIE - ROIE: u1, - /// TUIE - TUIE: u1, - /// RIE - RIE: u1, - /// RBUIE - RBUIE: u1, - /// RPSIE - RPSIE: u1, - /// RWTIE - RWTIE: u1, - /// ETIE - ETIE: u1, - reserved0: u1, - reserved1: u1, - /// FBEIE - FBEIE: u1, - /// ERIE - ERIE: u1, - /// AISE - AISE: u1, - /// NISE - NISE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40029020 - /// Ethernet DMA missed frame and buffer - /// overflow counter register - pub const DMAMFBOCR = @intToPtr(*volatile Mmio(32, packed struct { - /// MFC - MFC: u16, - /// OMFC - OMFC: u1, - /// MFA - MFA: u11, - /// OFOC - OFOC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x20); - - /// address: 0x40029024 - /// Ethernet DMA receive status watchdog timer - /// register - pub const DMARSWTR = @intToPtr(*volatile Mmio(32, packed struct { - /// RSWTC - RSWTC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40029048 - /// Ethernet DMA current host transmit - /// descriptor register - pub const DMACHTDR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTDAP - HTDAP: u32, - }), base_address + 0x48); - - /// address: 0x4002904c - /// Ethernet DMA current host receive descriptor - /// register - pub const DMACHRDR = @intToPtr(*volatile Mmio(32, packed struct { - /// HRDAP - HRDAP: u32, - }), base_address + 0x4c); - - /// address: 0x40029050 - /// Ethernet DMA current host transmit buffer - /// address register - pub const DMACHTBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTBAP - HTBAP: u32, - }), base_address + 0x50); - - /// address: 0x40029054 - /// Ethernet DMA current host receive buffer - /// address register - pub const DMACHRBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// HRBAP - HRBAP: u32, - }), base_address + 0x54); - }; - - /// Cryptographic processor - pub const CRC = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023000 - /// Data register - pub const DR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40023004 - /// Independent Data register - pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40023008 - /// Control register - pub const CR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); - }; - - /// USB on the go full speed - pub const OTG_FS_GLOBAL = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000000 - /// OTG_FS control and status register - /// (OTG_FS_GOTGCTL) - pub const FS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Session request success - SRQSCS: u1, - /// Session request - SRQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Host negotiation success - HNGSCS: u1, - /// HNP request - HNPRQ: u1, - /// Host set HNP enable - HSHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Connector ID status - CIDSTS: u1, - /// Long/short debounce time - DBCT: u1, - /// A-session valid - ASVLD: u1, - /// B-session valid - BSVLD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x50000004 - /// OTG_FS interrupt register - /// (OTG_FS_GOTGINT) - pub const FS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Session end detected - SEDET: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Session request success status - /// change - SRSSCHG: u1, - /// Host negotiation success status - /// change - HNSSCHG: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Host negotiation detected - HNGDET: u1, - /// A-device timeout change - ADTOCHG: u1, - /// Debounce done - DBCDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x50000008 - /// OTG_FS AHB configuration register - /// (OTG_FS_GAHBCFG) - pub const FS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt mask - GINT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TxFIFO empty level - TXFELVL: u1, - /// Periodic TxFIFO empty - /// level - PTXFELVL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x5000000c - /// OTG_FS USB configuration register - /// (OTG_FS_GUSBCFG) - pub const FS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS timeout calibration - TOCAL: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Full Speed serial transceiver - /// select - PHYSEL: u1, - reserved3: u1, - /// SRP-capable - SRPCAP: u1, - /// HNP-capable - HNPCAP: u1, - /// USB turnaround time - TRDT: u4, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// Force host mode - FHMOD: u1, - /// Force device mode - FDMOD: u1, - /// Corrupt Tx packet - CTXPKT: u1, - }), base_address + 0xc); - - /// address: 0x50000010 - /// OTG_FS reset register - /// (OTG_FS_GRSTCTL) - pub const FS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HSRST: u1, - /// Host frame counter reset - FCRST: u1, - reserved0: u1, - /// RxFIFO flush - RXFFLSH: u1, - /// TxFIFO flush - TXFFLSH: u1, - /// TxFIFO number - TXFNUM: u5, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// AHB master idle - AHBIDL: u1, - }), base_address + 0x10); - - /// address: 0x50000014 - /// OTG_FS core interrupt register - /// (OTG_FS_GINTSTS) - pub const FS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Current mode of operation - CMOD: u1, - /// Mode mismatch interrupt - MMIS: u1, - /// OTG interrupt - OTGINT: u1, - /// Start of frame - SOF: u1, - /// RxFIFO non-empty - RXFLVL: u1, - /// Non-periodic TxFIFO empty - NPTXFE: u1, - /// Global IN non-periodic NAK - /// effective - GINAKEFF: u1, - /// Global OUT NAK effective - GOUTNAKEFF: u1, - reserved0: u1, - reserved1: u1, - /// Early suspend - ESUSP: u1, - /// USB suspend - USBSUSP: u1, - /// USB reset - USBRST: u1, - /// Enumeration done - ENUMDNE: u1, - /// Isochronous OUT packet dropped - /// interrupt - ISOODRP: u1, - /// End of periodic frame - /// interrupt - EOPF: u1, - reserved2: u1, - reserved3: u1, - /// IN endpoint interrupt - IEPINT: u1, - /// OUT endpoint interrupt - OEPINT: u1, - /// Incomplete isochronous IN - /// transfer - IISOIXFR: u1, - /// Incomplete periodic transfer(Host - /// mode)/Incomplete isochronous OUT transfer(Device - /// mode) - IPXFR_INCOMPISOOUT: u1, - reserved4: u1, - reserved5: u1, - /// Host port interrupt - HPRTINT: u1, - /// Host channels interrupt - HCINT: u1, - /// Periodic TxFIFO empty - PTXFE: u1, - reserved6: u1, - /// Connector ID status change - CIDSCHG: u1, - /// Disconnect detected - /// interrupt - DISCINT: u1, - /// Session request/new session detected - /// interrupt - SRQINT: u1, - /// Resume/remote wakeup detected - /// interrupt - WKUPINT: u1, - }), base_address + 0x14); - - /// address: 0x50000018 - /// OTG_FS interrupt mask register - /// (OTG_FS_GINTMSK) - pub const FS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Mode mismatch interrupt - /// mask - MMISM: u1, - /// OTG interrupt mask - OTGINT: u1, - /// Start of frame mask - SOFM: u1, - /// Receive FIFO non-empty - /// mask - RXFLVLM: u1, - /// Non-periodic TxFIFO empty - /// mask - NPTXFEM: u1, - /// Global non-periodic IN NAK effective - /// mask - GINAKEFFM: u1, - /// Global OUT NAK effective - /// mask - GONAKEFFM: u1, - reserved1: u1, - reserved2: u1, - /// Early suspend mask - ESUSPM: u1, - /// USB suspend mask - USBSUSPM: u1, - /// USB reset mask - USBRST: u1, - /// Enumeration done mask - ENUMDNEM: u1, - /// Isochronous OUT packet dropped interrupt - /// mask - ISOODRPM: u1, - /// End of periodic frame interrupt - /// mask - EOPFM: u1, - reserved3: u1, - /// Endpoint mismatch interrupt - /// mask - EPMISM: u1, - /// IN endpoints interrupt - /// mask - IEPINT: u1, - /// OUT endpoints interrupt - /// mask - OEPINT: u1, - /// Incomplete isochronous IN transfer - /// mask - IISOIXFRM: u1, - /// Incomplete periodic transfer mask(Host - /// mode)/Incomplete isochronous OUT transfer mask(Device - /// mode) - IPXFRM_IISOOXFRM: u1, - reserved4: u1, - reserved5: u1, - /// Host port interrupt mask - PRTIM: u1, - /// Host channels interrupt - /// mask - HCIM: u1, - /// Periodic TxFIFO empty mask - PTXFEM: u1, - reserved6: u1, - /// Connector ID status change - /// mask - CIDSCHGM: u1, - /// Disconnect detected interrupt - /// mask - DISCINT: u1, - /// Session request/new session detected - /// interrupt mask - SRQIM: u1, - /// Resume/remote wakeup detected interrupt - /// mask - WUIM: u1, - }), base_address + 0x18); - - /// address: 0x5000001c - /// OTG_FS Receive status debug read(Device - /// mode) - pub const FS_GRXSTSR_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x5000001c - /// OTG_FS Receive status debug read(Host - /// mode) - pub const FS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x50000024 - /// OTG_FS Receive FIFO size register - /// (OTG_FS_GRXFSIZ) - pub const FS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// RxFIFO depth - RXFD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x50000028 - /// OTG_FS non-periodic transmit FIFO size - /// register (Device mode) - pub const FS_GNPTXFSIZ_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint 0 transmit RAM start - /// address - TX0FSA: u16, - /// Endpoint 0 TxFIFO depth - TX0FD: u16, - }), base_address + 0x28); - - /// address: 0x50000028 - /// OTG_FS non-periodic transmit FIFO size - /// register (Host mode) - pub const FS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-periodic transmit RAM start - /// address - NPTXFSA: u16, - /// Non-periodic TxFIFO depth - NPTXFD: u16, - }), base_address + 0x28); - - /// address: 0x5000002c - /// OTG_FS non-periodic transmit FIFO/queue - /// status register (OTG_FS_GNPTXSTS) - pub const FS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-periodic TxFIFO space - /// available - NPTXFSAV: u16, - /// Non-periodic transmit request queue - /// space available - NPTQXSAV: u8, - /// Top of the non-periodic transmit request - /// queue - NPTXQTOP: u7, - padding0: u1, - }), base_address + 0x2c); - - /// address: 0x50000038 - /// OTG_FS general core configuration register - /// (OTG_FS_GCCFG) - pub const FS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Power down - PWRDWN: u1, - reserved16: u1, - /// Enable the VBUS sensing - /// device - VBUSASEN: u1, - /// Enable the VBUS sensing - /// device - VBUSBSEN: u1, - /// SOF output enable - SOFOUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x38); - - /// address: 0x5000003c - /// core ID register - pub const FS_CID = @intToPtr(*volatile Mmio(32, packed struct { - /// Product ID field - PRODUCT_ID: u32, - }), base_address + 0x3c); - - /// address: 0x50000100 - /// OTG_FS Host periodic transmit FIFO size - /// register (OTG_FS_HPTXFSIZ) - pub const FS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// Host periodic TxFIFO start - /// address - PTXSA: u16, - /// Host periodic TxFIFO depth - PTXFSIZ: u16, - }), base_address + 0x100); - - /// address: 0x50000104 - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF2) - pub const FS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO2 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x104); - - /// address: 0x50000108 - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF3) - pub const FS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO3 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x108); - - /// address: 0x5000010c - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF4) - pub const FS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO4 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x10c); - }; - - /// USB on the go full speed - pub const OTG_FS_HOST = struct { - pub const base_address = 0x50000400; - - /// address: 0x50000400 - /// OTG_FS host configuration register - /// (OTG_FS_HCFG) - pub const FS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS/LS PHY clock select - FSLSPCS: u2, - /// FS- and LS-only support - FSLSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x50000404 - /// OTG_FS Host frame interval - /// register - pub const HFIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interval - FRIVL: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x50000408 - /// OTG_FS host frame number/frame time - /// remaining register (OTG_FS_HFNUM) - pub const FS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FRNUM: u16, - /// Frame time remaining - FTREM: u16, - }), base_address + 0x8); - - /// address: 0x50000410 - /// OTG_FS_Host periodic transmit FIFO/queue - /// status register (OTG_FS_HPTXSTS) - pub const FS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic transmit data FIFO space - /// available - PTXFSAVL: u16, - /// Periodic transmit request queue space - /// available - PTXQSAV: u8, - /// Top of the periodic transmit request - /// queue - PTXQTOP: u8, - }), base_address + 0x10); - - /// address: 0x50000414 - /// OTG_FS Host all channels interrupt - /// register - pub const HAINT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); - - /// address: 0x50000418 - /// OTG_FS host all channels interrupt mask - /// register - pub const HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupt mask - HAINTM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x50000440 - /// OTG_FS host port control and status register - /// (OTG_FS_HPRT) - pub const FS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port connect status - PCSTS: u1, - /// Port connect detected - PCDET: u1, - /// Port enable - PENA: u1, - /// Port enable/disable change - PENCHNG: u1, - /// Port overcurrent active - POCA: u1, - /// Port overcurrent change - POCCHNG: u1, - /// Port resume - PRES: u1, - /// Port suspend - PSUSP: u1, - /// Port reset - PRST: u1, - reserved0: u1, - /// Port line status - PLSTS: u2, - /// Port power - PPWR: u1, - /// Port test control - PTCTL: u4, - /// Port speed - PSPD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x50000500 - /// OTG_FS host channel-0 characteristics - /// register (OTG_FS_HCCHAR0) - pub const FS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x100); - - /// address: 0x50000520 - /// OTG_FS host channel-1 characteristics - /// register (OTG_FS_HCCHAR1) - pub const FS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x120); - - /// address: 0x50000540 - /// OTG_FS host channel-2 characteristics - /// register (OTG_FS_HCCHAR2) - pub const FS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x140); - - /// address: 0x50000560 - /// OTG_FS host channel-3 characteristics - /// register (OTG_FS_HCCHAR3) - pub const FS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x160); - - /// address: 0x50000580 - /// OTG_FS host channel-4 characteristics - /// register (OTG_FS_HCCHAR4) - pub const FS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x180); - - /// address: 0x500005a0 - /// OTG_FS host channel-5 characteristics - /// register (OTG_FS_HCCHAR5) - pub const FS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1a0); - - /// address: 0x500005c0 - /// OTG_FS host channel-6 characteristics - /// register (OTG_FS_HCCHAR6) - pub const FS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1c0); - - /// address: 0x500005e0 - /// OTG_FS host channel-7 characteristics - /// register (OTG_FS_HCCHAR7) - pub const FS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1e0); - - /// address: 0x50000508 - /// OTG_FS host channel-0 interrupt register - /// (OTG_FS_HCINT0) - pub const FS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x108); - - /// address: 0x50000528 - /// OTG_FS host channel-1 interrupt register - /// (OTG_FS_HCINT1) - pub const FS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x128); - - /// address: 0x50000548 - /// OTG_FS host channel-2 interrupt register - /// (OTG_FS_HCINT2) - pub const FS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x148); - - /// address: 0x50000568 - /// OTG_FS host channel-3 interrupt register - /// (OTG_FS_HCINT3) - pub const FS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x168); - - /// address: 0x50000588 - /// OTG_FS host channel-4 interrupt register - /// (OTG_FS_HCINT4) - pub const FS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x188); - - /// address: 0x500005a8 - /// OTG_FS host channel-5 interrupt register - /// (OTG_FS_HCINT5) - pub const FS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1a8); - - /// address: 0x500005c8 - /// OTG_FS host channel-6 interrupt register - /// (OTG_FS_HCINT6) - pub const FS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c8); - - /// address: 0x500005e8 - /// OTG_FS host channel-7 interrupt register - /// (OTG_FS_HCINT7) - pub const FS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1e8); - - /// address: 0x5000050c - /// OTG_FS host channel-0 mask register - /// (OTG_FS_HCINTMSK0) - pub const FS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10c); - - /// address: 0x5000052c - /// OTG_FS host channel-1 mask register - /// (OTG_FS_HCINTMSK1) - pub const FS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x12c); - - /// address: 0x5000054c - /// OTG_FS host channel-2 mask register - /// (OTG_FS_HCINTMSK2) - pub const FS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14c); - - /// address: 0x5000056c - /// OTG_FS host channel-3 mask register - /// (OTG_FS_HCINTMSK3) - pub const FS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x16c); - - /// address: 0x5000058c - /// OTG_FS host channel-4 mask register - /// (OTG_FS_HCINTMSK4) - pub const FS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18c); - - /// address: 0x500005ac - /// OTG_FS host channel-5 mask register - /// (OTG_FS_HCINTMSK5) - pub const FS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ac); - - /// address: 0x500005cc - /// OTG_FS host channel-6 mask register - /// (OTG_FS_HCINTMSK6) - pub const FS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1cc); - - /// address: 0x500005ec - /// OTG_FS host channel-7 mask register - /// (OTG_FS_HCINTMSK7) - pub const FS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ec); - - /// address: 0x50000510 - /// OTG_FS host channel-0 transfer size - /// register - pub const FS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x110); - - /// address: 0x50000530 - /// OTG_FS host channel-1 transfer size - /// register - pub const FS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000550 - /// OTG_FS host channel-2 transfer size - /// register - pub const FS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000570 - /// OTG_FS host channel-3 transfer size - /// register - pub const FS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000590 - /// OTG_FS host channel-x transfer size - /// register - pub const FS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x500005b0 - /// OTG_FS host channel-5 transfer size - /// register - pub const FS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x500005d0 - /// OTG_FS host channel-6 transfer size - /// register - pub const FS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1d0); - - /// address: 0x500005f0 - /// OTG_FS host channel-7 transfer size - /// register - pub const FS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1f0); - }; - - /// USB on the go full speed - pub const OTG_FS_DEVICE = struct { - pub const base_address = 0x50000800; - - /// address: 0x50000800 - /// OTG_FS device configuration register - /// (OTG_FS_DCFG) - pub const FS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Device speed - DSPD: u2, - /// Non-zero-length status OUT - /// handshake - NZLSOHSK: u1, - reserved0: u1, - /// Device address - DAD: u7, - /// Periodic frame interval - PFIVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x0); - - /// address: 0x50000804 - /// OTG_FS device control register - /// (OTG_FS_DCTL) - pub const FS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Remote wakeup signaling - RWUSIG: u1, - /// Soft disconnect - SDIS: u1, - /// Global IN NAK status - GINSTS: u1, - /// Global OUT NAK status - GONSTS: u1, - /// Test control - TCTL: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on programming done - POPRGDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x50000808 - /// OTG_FS device status register - /// (OTG_FS_DSTS) - pub const FS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Suspend status - SUSPSTS: u1, - /// Enumerated speed - ENUMSPD: u2, - /// Erratic error - EERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Frame number of the received - /// SOF - FNSOF: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x50000810 - /// OTG_FS device IN endpoint common interrupt - /// mask register (OTG_FS_DIEPMSK) - pub const FS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (Non-isochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x10); - - /// address: 0x50000814 - /// OTG_FS device OUT endpoint common interrupt - /// mask register (OTG_FS_DOEPMSK) - pub const FS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// SETUP phase done mask - STUPM: u1, - /// OUT token received when endpoint - /// disabled mask - OTEPDM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x14); - - /// address: 0x50000818 - /// OTG_FS device all endpoints interrupt - /// register (OTG_FS_DAINT) - pub const FS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint interrupt bits - IEPINT: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x18); - - /// address: 0x5000081c - /// OTG_FS all endpoints interrupt mask register - /// (OTG_FS_DAINTMSK) - pub const FS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP interrupt mask bits - IEPM: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x1c); - - /// address: 0x50000828 - /// OTG_FS device VBUS discharge time - /// register - pub const DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS discharge time - VBUSDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x5000082c - /// OTG_FS device VBUS pulsing time - /// register - pub const DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS pulsing time - DVBUSP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x50000834 - /// OTG_FS device IN endpoint FIFO empty - /// interrupt mask register - pub const DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP Tx FIFO empty interrupt mask - /// bits - INEPTXFEM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x50000900 - /// OTG_FS device control IN endpoint 0 control - /// register (OTG_FS_DIEPCTL0) - pub const FS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USB active endpoint - USBAEP: u1, - reserved13: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved14: u1, - /// STALL handshake - STALL: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved15: u1, - reserved16: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x100); - - /// address: 0x50000920 - /// OTG device endpoint-1 control - /// register - pub const DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM/SD1PID - SODDFRM_SD1PID: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x120); - - /// address: 0x50000940 - /// OTG device endpoint-2 control - /// register - pub const DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x140); - - /// address: 0x50000960 - /// OTG device endpoint-3 control - /// register - pub const DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x160); - - /// address: 0x50000b00 - /// device endpoint-0 control - /// register - pub const DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USBAEP - USBAEP: u1, - reserved13: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - reserved18: u1, - reserved19: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x300); - - /// address: 0x50000b20 - /// device endpoint-1 control - /// register - pub const DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x320); - - /// address: 0x50000b40 - /// device endpoint-2 control - /// register - pub const DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x340); - - /// address: 0x50000b60 - /// device endpoint-3 control - /// register - pub const DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x360); - - /// address: 0x50000908 - /// device endpoint-x interrupt - /// register - pub const DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x108); - - /// address: 0x50000928 - /// device endpoint-1 interrupt - /// register - pub const DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x128); - - /// address: 0x50000948 - /// device endpoint-2 interrupt - /// register - pub const DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x148); - - /// address: 0x50000968 - /// device endpoint-3 interrupt - /// register - pub const DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x168); - - /// address: 0x50000b08 - /// device endpoint-0 interrupt - /// register - pub const DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x308); - - /// address: 0x50000b28 - /// device endpoint-1 interrupt - /// register - pub const DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x328); - - /// address: 0x50000b48 - /// device endpoint-2 interrupt - /// register - pub const DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x348); - - /// address: 0x50000b68 - /// device endpoint-3 interrupt - /// register - pub const DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x368); - - /// address: 0x50000910 - /// device endpoint-0 transfer size - /// register - pub const DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x110); - - /// address: 0x50000b10 - /// device OUT endpoint-0 transfer size - /// register - pub const DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// SETUP packet count - STUPCNT: u2, - padding0: u1, - }), base_address + 0x310); - - /// address: 0x50000930 - /// device endpoint-1 transfer size - /// register - pub const DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000950 - /// device endpoint-2 transfer size - /// register - pub const DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000970 - /// device endpoint-3 transfer size - /// register - pub const DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000918 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x118); - - /// address: 0x50000938 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x138); - - /// address: 0x50000958 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x158); - - /// address: 0x50000978 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x178); - - /// address: 0x50000b30 - /// device OUT endpoint-1 transfer size - /// register - pub const DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x330); - - /// address: 0x50000b50 - /// device OUT endpoint-2 transfer size - /// register - pub const DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x350); - - /// address: 0x50000b70 - /// device OUT endpoint-3 transfer size - /// register - pub const DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x370); - }; - - /// USB on the go full speed - pub const OTG_FS_PWRCLK = struct { - pub const base_address = 0x50000e00; - - /// address: 0x50000e00 - /// OTG_FS power and clock gating control - /// register - pub const FS_PCGCCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop PHY clock - STPPCLK: u1, - /// Gate HCLK - GATEHCLK: u1, - reserved0: u1, - reserved1: u1, - /// PHY Suspended - PHYSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - }; - - /// Controller area network - pub const CAN1 = struct { - pub const base_address = 0x40006400; - - /// address: 0x40006400 - /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006404 - /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006408 - /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000640c - /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006410 - /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006414 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006418 - /// interrupt enable register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000641c - /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006580 - /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006584 - /// mailbox data length control and time stamp - /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006588 - /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000658c - /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006590 - /// mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006594 - /// mailbox data length control and time stamp - /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006598 - /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000659c - /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400065a0 - /// mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400065a4 - /// mailbox data length control and time stamp - /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400065a8 - /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400065ac - /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400065b0 - /// receive FIFO mailbox identifier - /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400065b4 - /// mailbox data high register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400065b8 - /// mailbox data high register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400065bc - /// receive FIFO mailbox data high - /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400065c0 - /// mailbox data high register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400065c4 - /// mailbox data high register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400065c8 - /// mailbox data high register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400065cc - /// mailbox data high register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006600 - /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// FINIT - FINIT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// CAN2SB - CAN2SB: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006604 - /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - /// Filter mode - FBM14: u1, - /// Filter mode - FBM15: u1, - /// Filter mode - FBM16: u1, - /// Filter mode - FBM17: u1, - /// Filter mode - FBM18: u1, - /// Filter mode - FBM19: u1, - /// Filter mode - FBM20: u1, - /// Filter mode - FBM21: u1, - /// Filter mode - FBM22: u1, - /// Filter mode - FBM23: u1, - /// Filter mode - FBM24: u1, - /// Filter mode - FBM25: u1, - /// Filter mode - FBM26: u1, - /// Filter mode - FBM27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x4000660c - /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - /// Filter scale configuration - FSC14: u1, - /// Filter scale configuration - FSC15: u1, - /// Filter scale configuration - FSC16: u1, - /// Filter scale configuration - FSC17: u1, - /// Filter scale configuration - FSC18: u1, - /// Filter scale configuration - FSC19: u1, - /// Filter scale configuration - FSC20: u1, - /// Filter scale configuration - FSC21: u1, - /// Filter scale configuration - FSC22: u1, - /// Filter scale configuration - FSC23: u1, - /// Filter scale configuration - FSC24: u1, - /// Filter scale configuration - FSC25: u1, - /// Filter scale configuration - FSC26: u1, - /// Filter scale configuration - FSC27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006614 - /// filter FIFO assignment - /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - /// Filter FIFO assignment for filter - /// 14 - FFA14: u1, - /// Filter FIFO assignment for filter - /// 15 - FFA15: u1, - /// Filter FIFO assignment for filter - /// 16 - FFA16: u1, - /// Filter FIFO assignment for filter - /// 17 - FFA17: u1, - /// Filter FIFO assignment for filter - /// 18 - FFA18: u1, - /// Filter FIFO assignment for filter - /// 19 - FFA19: u1, - /// Filter FIFO assignment for filter - /// 20 - FFA20: u1, - /// Filter FIFO assignment for filter - /// 21 - FFA21: u1, - /// Filter FIFO assignment for filter - /// 22 - FFA22: u1, - /// Filter FIFO assignment for filter - /// 23 - FFA23: u1, - /// Filter FIFO assignment for filter - /// 24 - FFA24: u1, - /// Filter FIFO assignment for filter - /// 25 - FFA25: u1, - /// Filter FIFO assignment for filter - /// 26 - FFA26: u1, - /// Filter FIFO assignment for filter - /// 27 - FFA27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x4000661c - /// filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - /// Filter active - FACT14: u1, - /// Filter active - FACT15: u1, - /// Filter active - FACT16: u1, - /// Filter active - FACT17: u1, - /// Filter active - FACT18: u1, - /// Filter active - FACT19: u1, - /// Filter active - FACT20: u1, - /// Filter active - FACT21: u1, - /// Filter active - FACT22: u1, - /// Filter active - FACT23: u1, - /// Filter active - FACT24: u1, - /// Filter active - FACT25: u1, - /// Filter active - FACT26: u1, - /// Filter active - FACT27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006640 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006644 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006648 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x4000664c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006650 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006654 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006658 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x4000665c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006660 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006664 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006668 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x4000666c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006670 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006674 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006678 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x4000667c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006680 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006684 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006688 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x4000668c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006690 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006694 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006698 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x4000669c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x400066a0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x400066a4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x400066a8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x400066ac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - - /// address: 0x400066b0 - /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b0); - - /// address: 0x400066b4 - /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b4); - - /// address: 0x400066b8 - /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b8); - - /// address: 0x400066bc - /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2bc); - - /// address: 0x400066c0 - /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c0); - - /// address: 0x400066c4 - /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c4); - - /// address: 0x400066c8 - /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c8); - - /// address: 0x400066cc - /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2cc); - - /// address: 0x400066d0 - /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d0); - - /// address: 0x400066d4 - /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d4); - - /// address: 0x400066d8 - /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d8); - - /// address: 0x400066dc - /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2dc); - - /// address: 0x400066e0 - /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e0); - - /// address: 0x400066e4 - /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e4); - - /// address: 0x400066e8 - /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e8); - - /// address: 0x400066ec - /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ec); - - /// address: 0x400066f0 - /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f0); - - /// address: 0x400066f4 - /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f4); - - /// address: 0x400066f8 - /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f8); - - /// address: 0x400066fc - /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006700 - /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x300); - - /// address: 0x40006704 - /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x304); - - /// address: 0x40006708 - /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x308); - - /// address: 0x4000670c - /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x30c); - - /// address: 0x40006710 - /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x310); - - /// address: 0x40006714 - /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x314); - - /// address: 0x40006718 - /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x318); - - /// address: 0x4000671c - /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x31c); - }; - pub const CAN2 = struct { - pub const base_address = 0x40006800; - - /// address: 0x40006800 - /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006804 - /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006808 - /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000680c - /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006810 - /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006814 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006818 - /// interrupt enable register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000681c - /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006980 - /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006984 - /// mailbox data length control and time stamp - /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006988 - /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000698c - /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006990 - /// mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006994 - /// mailbox data length control and time stamp - /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006998 - /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000699c - /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400069a0 - /// mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400069a4 - /// mailbox data length control and time stamp - /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400069a8 - /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400069ac - /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400069b0 - /// receive FIFO mailbox identifier - /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400069b4 - /// mailbox data high register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400069b8 - /// mailbox data high register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400069bc - /// receive FIFO mailbox data high - /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400069c0 - /// mailbox data high register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400069c4 - /// mailbox data high register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400069c8 - /// mailbox data high register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400069cc - /// mailbox data high register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006a00 - /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// FINIT - FINIT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// CAN2SB - CAN2SB: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006a04 - /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - /// Filter mode - FBM14: u1, - /// Filter mode - FBM15: u1, - /// Filter mode - FBM16: u1, - /// Filter mode - FBM17: u1, - /// Filter mode - FBM18: u1, - /// Filter mode - FBM19: u1, - /// Filter mode - FBM20: u1, - /// Filter mode - FBM21: u1, - /// Filter mode - FBM22: u1, - /// Filter mode - FBM23: u1, - /// Filter mode - FBM24: u1, - /// Filter mode - FBM25: u1, - /// Filter mode - FBM26: u1, - /// Filter mode - FBM27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x40006a0c - /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - /// Filter scale configuration - FSC14: u1, - /// Filter scale configuration - FSC15: u1, - /// Filter scale configuration - FSC16: u1, - /// Filter scale configuration - FSC17: u1, - /// Filter scale configuration - FSC18: u1, - /// Filter scale configuration - FSC19: u1, - /// Filter scale configuration - FSC20: u1, - /// Filter scale configuration - FSC21: u1, - /// Filter scale configuration - FSC22: u1, - /// Filter scale configuration - FSC23: u1, - /// Filter scale configuration - FSC24: u1, - /// Filter scale configuration - FSC25: u1, - /// Filter scale configuration - FSC26: u1, - /// Filter scale configuration - FSC27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006a14 - /// filter FIFO assignment - /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - /// Filter FIFO assignment for filter - /// 14 - FFA14: u1, - /// Filter FIFO assignment for filter - /// 15 - FFA15: u1, - /// Filter FIFO assignment for filter - /// 16 - FFA16: u1, - /// Filter FIFO assignment for filter - /// 17 - FFA17: u1, - /// Filter FIFO assignment for filter - /// 18 - FFA18: u1, - /// Filter FIFO assignment for filter - /// 19 - FFA19: u1, - /// Filter FIFO assignment for filter - /// 20 - FFA20: u1, - /// Filter FIFO assignment for filter - /// 21 - FFA21: u1, - /// Filter FIFO assignment for filter - /// 22 - FFA22: u1, - /// Filter FIFO assignment for filter - /// 23 - FFA23: u1, - /// Filter FIFO assignment for filter - /// 24 - FFA24: u1, - /// Filter FIFO assignment for filter - /// 25 - FFA25: u1, - /// Filter FIFO assignment for filter - /// 26 - FFA26: u1, - /// Filter FIFO assignment for filter - /// 27 - FFA27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x40006a1c - /// filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - /// Filter active - FACT14: u1, - /// Filter active - FACT15: u1, - /// Filter active - FACT16: u1, - /// Filter active - FACT17: u1, - /// Filter active - FACT18: u1, - /// Filter active - FACT19: u1, - /// Filter active - FACT20: u1, - /// Filter active - FACT21: u1, - /// Filter active - FACT22: u1, - /// Filter active - FACT23: u1, - /// Filter active - FACT24: u1, - /// Filter active - FACT25: u1, - /// Filter active - FACT26: u1, - /// Filter active - FACT27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006a40 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006a44 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006a48 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x40006a4c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006a50 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006a54 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006a58 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x40006a5c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006a60 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006a64 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006a68 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x40006a6c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006a70 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006a74 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006a78 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x40006a7c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006a80 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006a84 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006a88 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x40006a8c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006a90 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006a94 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006a98 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x40006a9c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x40006aa0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x40006aa4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x40006aa8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x40006aac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - - /// address: 0x40006ab0 - /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b0); - - /// address: 0x40006ab4 - /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b4); - - /// address: 0x40006ab8 - /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b8); - - /// address: 0x40006abc - /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2bc); - - /// address: 0x40006ac0 - /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c0); - - /// address: 0x40006ac4 - /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c4); - - /// address: 0x40006ac8 - /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c8); - - /// address: 0x40006acc - /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2cc); - - /// address: 0x40006ad0 - /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d0); - - /// address: 0x40006ad4 - /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d4); - - /// address: 0x40006ad8 - /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d8); - - /// address: 0x40006adc - /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2dc); - - /// address: 0x40006ae0 - /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e0); - - /// address: 0x40006ae4 - /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e4); - - /// address: 0x40006ae8 - /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e8); - - /// address: 0x40006aec - /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ec); - - /// address: 0x40006af0 - /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f0); - - /// address: 0x40006af4 - /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f4); - - /// address: 0x40006af8 - /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f8); - - /// address: 0x40006afc - /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006b00 - /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x300); - - /// address: 0x40006b04 - /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x304); - - /// address: 0x40006b08 - /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x308); - - /// address: 0x40006b0c - /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x30c); - - /// address: 0x40006b10 - /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x310); - - /// address: 0x40006b14 - /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x314); - - /// address: 0x40006b18 - /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x318); - - /// address: 0x40006b1c - /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x31c); - }; - - /// FLASH - pub const FLASH = struct { - pub const base_address = 0x40023c00; - - /// address: 0x40023c00 - /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Latency - LATENCY: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x0); - - /// address: 0x40023c04 - /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// FPEC key - KEY: u32, - }), base_address + 0x4); - - /// address: 0x40023c08 - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option byte key - OPTKEY: u32, - }), base_address + 0x8); - - /// address: 0x40023c0c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved0: u1, - reserved1: u1, - /// Write protection error - WRPERR: u1, - /// Programming alignment - /// error - PGAERR: u1, - /// Programming parallelism - /// error - PGPERR: u1, - /// Programming sequence error - PGSERR: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Busy - BSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xc); - - /// address: 0x40023c10 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Programming - PG: u1, - /// Sector Erase - SER: u1, - /// Mass Erase - MER: u1, - /// Sector number - SNB: u4, - reserved0: u1, - /// Program size - PSIZE: u2, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Start - STRT: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// End of operation interrupt - /// enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// Lock - LOCK: u1, - }), base_address + 0x10); - - /// address: 0x40023c14 - /// Flash option control register - pub const OPTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option lock - OPTLOCK: u1, - /// Option start - OPTSTRT: u1, - /// BOR reset Level - BOR_LEV: u2, - reserved0: u1, - /// WDG_SW User option bytes - WDG_SW: u1, - /// nRST_STOP User option - /// bytes - nRST_STOP: u1, - /// nRST_STDBY User option - /// bytes - nRST_STDBY: u1, - /// Read protect - RDP: u8, - /// Not write protect - nWRP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x14); - }; - - /// External interrupt/event - /// controller - pub const EXTI = struct { - pub const base_address = 0x40013c00; - - /// address: 0x40013c00 - /// Interrupt mask register - /// (EXTI_IMR) - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1, - /// Interrupt Mask on line 1 - MR1: u1, - /// Interrupt Mask on line 2 - MR2: u1, - /// Interrupt Mask on line 3 - MR3: u1, - /// Interrupt Mask on line 4 - MR4: u1, - /// Interrupt Mask on line 5 - MR5: u1, - /// Interrupt Mask on line 6 - MR6: u1, - /// Interrupt Mask on line 7 - MR7: u1, - /// Interrupt Mask on line 8 - MR8: u1, - /// Interrupt Mask on line 9 - MR9: u1, - /// Interrupt Mask on line 10 - MR10: u1, - /// Interrupt Mask on line 11 - MR11: u1, - /// Interrupt Mask on line 12 - MR12: u1, - /// Interrupt Mask on line 13 - MR13: u1, - /// Interrupt Mask on line 14 - MR14: u1, - /// Interrupt Mask on line 15 - MR15: u1, - /// Interrupt Mask on line 16 - MR16: u1, - /// Interrupt Mask on line 17 - MR17: u1, - /// Interrupt Mask on line 18 - MR18: u1, - /// Interrupt Mask on line 19 - MR19: u1, - /// Interrupt Mask on line 20 - MR20: u1, - /// Interrupt Mask on line 21 - MR21: u1, - /// Interrupt Mask on line 22 - MR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x0); - - /// address: 0x40013c04 - /// Event mask register (EXTI_EMR) - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Event Mask on line 0 - MR0: u1, - /// Event Mask on line 1 - MR1: u1, - /// Event Mask on line 2 - MR2: u1, - /// Event Mask on line 3 - MR3: u1, - /// Event Mask on line 4 - MR4: u1, - /// Event Mask on line 5 - MR5: u1, - /// Event Mask on line 6 - MR6: u1, - /// Event Mask on line 7 - MR7: u1, - /// Event Mask on line 8 - MR8: u1, - /// Event Mask on line 9 - MR9: u1, - /// Event Mask on line 10 - MR10: u1, - /// Event Mask on line 11 - MR11: u1, - /// Event Mask on line 12 - MR12: u1, - /// Event Mask on line 13 - MR13: u1, - /// Event Mask on line 14 - MR14: u1, - /// Event Mask on line 15 - MR15: u1, - /// Event Mask on line 16 - MR16: u1, - /// Event Mask on line 17 - MR17: u1, - /// Event Mask on line 18 - MR18: u1, - /// Event Mask on line 19 - MR19: u1, - /// Event Mask on line 20 - MR20: u1, - /// Event Mask on line 21 - MR21: u1, - /// Event Mask on line 22 - MR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x4); - - /// address: 0x40013c08 - /// Rising Trigger selection register - /// (EXTI_RTSR) - pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising trigger event configuration of - /// line 0 - TR0: u1, - /// Rising trigger event configuration of - /// line 1 - TR1: u1, - /// Rising trigger event configuration of - /// line 2 - TR2: u1, - /// Rising trigger event configuration of - /// line 3 - TR3: u1, - /// Rising trigger event configuration of - /// line 4 - TR4: u1, - /// Rising trigger event configuration of - /// line 5 - TR5: u1, - /// Rising trigger event configuration of - /// line 6 - TR6: u1, - /// Rising trigger event configuration of - /// line 7 - TR7: u1, - /// Rising trigger event configuration of - /// line 8 - TR8: u1, - /// Rising trigger event configuration of - /// line 9 - TR9: u1, - /// Rising trigger event configuration of - /// line 10 - TR10: u1, - /// Rising trigger event configuration of - /// line 11 - TR11: u1, - /// Rising trigger event configuration of - /// line 12 - TR12: u1, - /// Rising trigger event configuration of - /// line 13 - TR13: u1, - /// Rising trigger event configuration of - /// line 14 - TR14: u1, - /// Rising trigger event configuration of - /// line 15 - TR15: u1, - /// Rising trigger event configuration of - /// line 16 - TR16: u1, - /// Rising trigger event configuration of - /// line 17 - TR17: u1, - /// Rising trigger event configuration of - /// line 18 - TR18: u1, - /// Rising trigger event configuration of - /// line 19 - TR19: u1, - /// Rising trigger event configuration of - /// line 20 - TR20: u1, - /// Rising trigger event configuration of - /// line 21 - TR21: u1, - /// Rising trigger event configuration of - /// line 22 - TR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x40013c0c - /// Falling Trigger selection register - /// (EXTI_FTSR) - pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling trigger event configuration of - /// line 0 - TR0: u1, - /// Falling trigger event configuration of - /// line 1 - TR1: u1, - /// Falling trigger event configuration of - /// line 2 - TR2: u1, - /// Falling trigger event configuration of - /// line 3 - TR3: u1, - /// Falling trigger event configuration of - /// line 4 - TR4: u1, - /// Falling trigger event configuration of - /// line 5 - TR5: u1, - /// Falling trigger event configuration of - /// line 6 - TR6: u1, - /// Falling trigger event configuration of - /// line 7 - TR7: u1, - /// Falling trigger event configuration of - /// line 8 - TR8: u1, - /// Falling trigger event configuration of - /// line 9 - TR9: u1, - /// Falling trigger event configuration of - /// line 10 - TR10: u1, - /// Falling trigger event configuration of - /// line 11 - TR11: u1, - /// Falling trigger event configuration of - /// line 12 - TR12: u1, - /// Falling trigger event configuration of - /// line 13 - TR13: u1, - /// Falling trigger event configuration of - /// line 14 - TR14: u1, - /// Falling trigger event configuration of - /// line 15 - TR15: u1, - /// Falling trigger event configuration of - /// line 16 - TR16: u1, - /// Falling trigger event configuration of - /// line 17 - TR17: u1, - /// Falling trigger event configuration of - /// line 18 - TR18: u1, - /// Falling trigger event configuration of - /// line 19 - TR19: u1, - /// Falling trigger event configuration of - /// line 20 - TR20: u1, - /// Falling trigger event configuration of - /// line 21 - TR21: u1, - /// Falling trigger event configuration of - /// line 22 - TR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xc); - - /// address: 0x40013c10 - /// Software interrupt event register - /// (EXTI_SWIER) - pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Interrupt on line - /// 0 - SWIER0: u1, - /// Software Interrupt on line - /// 1 - SWIER1: u1, - /// Software Interrupt on line - /// 2 - SWIER2: u1, - /// Software Interrupt on line - /// 3 - SWIER3: u1, - /// Software Interrupt on line - /// 4 - SWIER4: u1, - /// Software Interrupt on line - /// 5 - SWIER5: u1, - /// Software Interrupt on line - /// 6 - SWIER6: u1, - /// Software Interrupt on line - /// 7 - SWIER7: u1, - /// Software Interrupt on line - /// 8 - SWIER8: u1, - /// Software Interrupt on line - /// 9 - SWIER9: u1, - /// Software Interrupt on line - /// 10 - SWIER10: u1, - /// Software Interrupt on line - /// 11 - SWIER11: u1, - /// Software Interrupt on line - /// 12 - SWIER12: u1, - /// Software Interrupt on line - /// 13 - SWIER13: u1, - /// Software Interrupt on line - /// 14 - SWIER14: u1, - /// Software Interrupt on line - /// 15 - SWIER15: u1, - /// Software Interrupt on line - /// 16 - SWIER16: u1, - /// Software Interrupt on line - /// 17 - SWIER17: u1, - /// Software Interrupt on line - /// 18 - SWIER18: u1, - /// Software Interrupt on line - /// 19 - SWIER19: u1, - /// Software Interrupt on line - /// 20 - SWIER20: u1, - /// Software Interrupt on line - /// 21 - SWIER21: u1, - /// Software Interrupt on line - /// 22 - SWIER22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x10); - - /// address: 0x40013c14 - /// Pending register (EXTI_PR) - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending bit 0 - PR0: u1, - /// Pending bit 1 - PR1: u1, - /// Pending bit 2 - PR2: u1, - /// Pending bit 3 - PR3: u1, - /// Pending bit 4 - PR4: u1, - /// Pending bit 5 - PR5: u1, - /// Pending bit 6 - PR6: u1, - /// Pending bit 7 - PR7: u1, - /// Pending bit 8 - PR8: u1, - /// Pending bit 9 - PR9: u1, - /// Pending bit 10 - PR10: u1, - /// Pending bit 11 - PR11: u1, - /// Pending bit 12 - PR12: u1, - /// Pending bit 13 - PR13: u1, - /// Pending bit 14 - PR14: u1, - /// Pending bit 15 - PR15: u1, - /// Pending bit 16 - PR16: u1, - /// Pending bit 17 - PR17: u1, - /// Pending bit 18 - PR18: u1, - /// Pending bit 19 - PR19: u1, - /// Pending bit 20 - PR20: u1, - /// Pending bit 21 - PR21: u1, - /// Pending bit 22 - PR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - }; - - /// USB on the go high speed - pub const OTG_HS_GLOBAL = struct { - pub const base_address = 0x40040000; - - /// address: 0x40040000 - /// OTG_HS control and status - /// register - pub const OTG_HS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Session request success - SRQSCS: u1, - /// Session request - SRQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Host negotiation success - HNGSCS: u1, - /// HNP request - HNPRQ: u1, - /// Host set HNP enable - HSHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Connector ID status - CIDSTS: u1, - /// Long/short debounce time - DBCT: u1, - /// A-session valid - ASVLD: u1, - /// B-session valid - BSVLD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x40040004 - /// OTG_HS interrupt register - pub const OTG_HS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Session end detected - SEDET: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Session request success status - /// change - SRSSCHG: u1, - /// Host negotiation success status - /// change - HNSSCHG: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Host negotiation detected - HNGDET: u1, - /// A-device timeout change - ADTOCHG: u1, - /// Debounce done - DBCDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x40040008 - /// OTG_HS AHB configuration - /// register - pub const OTG_HS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt mask - GINT: u1, - /// Burst length/type - HBSTLEN: u4, - /// DMA enable - DMAEN: u1, - reserved0: u1, - /// TxFIFO empty level - TXFELVL: u1, - /// Periodic TxFIFO empty - /// level - PTXFELVL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4004000c - /// OTG_HS USB configuration - /// register - pub const OTG_HS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS timeout calibration - TOCAL: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// USB 2.0 high-speed ULPI PHY or USB 1.1 - /// full-speed serial transceiver select - PHYSEL: u1, - reserved3: u1, - /// SRP-capable - SRPCAP: u1, - /// HNP-capable - HNPCAP: u1, - /// USB turnaround time - TRDT: u4, - reserved4: u1, - /// PHY Low-power clock select - PHYLPCS: u1, - reserved5: u1, - /// ULPI FS/LS select - ULPIFSLS: u1, - /// ULPI Auto-resume - ULPIAR: u1, - /// ULPI Clock SuspendM - ULPICSM: u1, - /// ULPI External VBUS Drive - ULPIEVBUSD: u1, - /// ULPI external VBUS - /// indicator - ULPIEVBUSI: u1, - /// TermSel DLine pulsing - /// selection - TSDPS: u1, - /// Indicator complement - PCCI: u1, - /// Indicator pass through - PTCI: u1, - /// ULPI interface protect - /// disable - ULPIIPD: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Forced host mode - FHMOD: u1, - /// Forced peripheral mode - FDMOD: u1, - /// Corrupt Tx packet - CTXPKT: u1, - }), base_address + 0xc); - - /// address: 0x40040010 - /// OTG_HS reset register - pub const OTG_HS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HSRST: u1, - /// Host frame counter reset - FCRST: u1, - reserved0: u1, - /// RxFIFO flush - RXFFLSH: u1, - /// TxFIFO flush - TXFFLSH: u1, - /// TxFIFO number - TXFNUM: u5, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// DMA request signal - DMAREQ: u1, - /// AHB master idle - AHBIDL: u1, - }), base_address + 0x10); - - /// address: 0x40040014 - /// OTG_HS core interrupt register - pub const OTG_HS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Current mode of operation - CMOD: u1, - /// Mode mismatch interrupt - MMIS: u1, - /// OTG interrupt - OTGINT: u1, - /// Start of frame - SOF: u1, - /// RxFIFO nonempty - RXFLVL: u1, - /// Nonperiodic TxFIFO empty - NPTXFE: u1, - /// Global IN nonperiodic NAK - /// effective - GINAKEFF: u1, - /// Global OUT NAK effective - BOUTNAKEFF: u1, - reserved0: u1, - reserved1: u1, - /// Early suspend - ESUSP: u1, - /// USB suspend - USBSUSP: u1, - /// USB reset - USBRST: u1, - /// Enumeration done - ENUMDNE: u1, - /// Isochronous OUT packet dropped - /// interrupt - ISOODRP: u1, - /// End of periodic frame - /// interrupt - EOPF: u1, - reserved2: u1, - reserved3: u1, - /// IN endpoint interrupt - IEPINT: u1, - /// OUT endpoint interrupt - OEPINT: u1, - /// Incomplete isochronous IN - /// transfer - IISOIXFR: u1, - /// Incomplete periodic - /// transfer - PXFR_INCOMPISOOUT: u1, - /// Data fetch suspended - DATAFSUSP: u1, - reserved4: u1, - /// Host port interrupt - HPRTINT: u1, - /// Host channels interrupt - HCINT: u1, - /// Periodic TxFIFO empty - PTXFE: u1, - reserved5: u1, - /// Connector ID status change - CIDSCHG: u1, - /// Disconnect detected - /// interrupt - DISCINT: u1, - /// Session request/new session detected - /// interrupt - SRQINT: u1, - /// Resume/remote wakeup detected - /// interrupt - WKUINT: u1, - }), base_address + 0x14); - - /// address: 0x40040018 - /// OTG_HS interrupt mask register - pub const OTG_HS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Mode mismatch interrupt - /// mask - MMISM: u1, - /// OTG interrupt mask - OTGINT: u1, - /// Start of frame mask - SOFM: u1, - /// Receive FIFO nonempty mask - RXFLVLM: u1, - /// Nonperiodic TxFIFO empty - /// mask - NPTXFEM: u1, - /// Global nonperiodic IN NAK effective - /// mask - GINAKEFFM: u1, - /// Global OUT NAK effective - /// mask - GONAKEFFM: u1, - reserved1: u1, - reserved2: u1, - /// Early suspend mask - ESUSPM: u1, - /// USB suspend mask - USBSUSPM: u1, - /// USB reset mask - USBRST: u1, - /// Enumeration done mask - ENUMDNEM: u1, - /// Isochronous OUT packet dropped interrupt - /// mask - ISOODRPM: u1, - /// End of periodic frame interrupt - /// mask - EOPFM: u1, - reserved3: u1, - /// Endpoint mismatch interrupt - /// mask - EPMISM: u1, - /// IN endpoints interrupt - /// mask - IEPINT: u1, - /// OUT endpoints interrupt - /// mask - OEPINT: u1, - /// Incomplete isochronous IN transfer - /// mask - IISOIXFRM: u1, - /// Incomplete periodic transfer - /// mask - PXFRM_IISOOXFRM: u1, - /// Data fetch suspended mask - FSUSPM: u1, - reserved4: u1, - /// Host port interrupt mask - PRTIM: u1, - /// Host channels interrupt - /// mask - HCIM: u1, - /// Periodic TxFIFO empty mask - PTXFEM: u1, - reserved5: u1, - /// Connector ID status change - /// mask - CIDSCHGM: u1, - /// Disconnect detected interrupt - /// mask - DISCINT: u1, - /// Session request/new session detected - /// interrupt mask - SRQIM: u1, - /// Resume/remote wakeup detected interrupt - /// mask - WUIM: u1, - }), base_address + 0x18); - - /// address: 0x4004001c - /// OTG_HS Receive status debug read register - /// (host mode) - pub const OTG_HS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CHNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x1c); - - /// address: 0x40040020 - /// OTG_HS status read and pop register (host - /// mode) - pub const OTG_HS_GRXSTSP_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CHNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40040024 - /// OTG_HS Receive FIFO size - /// register - pub const OTG_HS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// RxFIFO depth - RXFD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x40040028 - /// OTG_HS nonperiodic transmit FIFO size - /// register (host mode) - pub const OTG_HS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonperiodic transmit RAM start - /// address - NPTXFSA: u16, - /// Nonperiodic TxFIFO depth - NPTXFD: u16, - }), base_address + 0x28); - - /// address: 0x40040028 - /// Endpoint 0 transmit FIFO size (peripheral - /// mode) - pub const OTG_HS_TX0FSIZ_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint 0 transmit RAM start - /// address - TX0FSA: u16, - /// Endpoint 0 TxFIFO depth - TX0FD: u16, - }), base_address + 0x28); - - /// address: 0x4004002c - /// OTG_HS nonperiodic transmit FIFO/queue - /// status register - pub const OTG_HS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonperiodic TxFIFO space - /// available - NPTXFSAV: u16, - /// Nonperiodic transmit request queue space - /// available - NPTQXSAV: u8, - /// Top of the nonperiodic transmit request - /// queue - NPTXQTOP: u7, - padding0: u1, - }), base_address + 0x2c); - - /// address: 0x40040038 - /// OTG_HS general core configuration - /// register - pub const OTG_HS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Power down - PWRDWN: u1, - /// Enable I2C bus connection for the - /// external I2C PHY interface - I2CPADEN: u1, - /// Enable the VBUS sensing - /// device - VBUSASEN: u1, - /// Enable the VBUS sensing - /// device - VBUSBSEN: u1, - /// SOF output enable - SOFOUTEN: u1, - /// VBUS sensing disable - /// option - NOVBUSSENS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4004003c - /// OTG_HS core ID register - pub const OTG_HS_CID = @intToPtr(*volatile Mmio(32, packed struct { - /// Product ID field - PRODUCT_ID: u32, - }), base_address + 0x3c); - - /// address: 0x40040100 - /// OTG_HS Host periodic transmit FIFO size - /// register - pub const OTG_HS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// Host periodic TxFIFO start - /// address - PTXSA: u16, - /// Host periodic TxFIFO depth - PTXFD: u16, - }), base_address + 0x100); - - /// address: 0x40040104 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x104); - - /// address: 0x40040108 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x108); - - /// address: 0x4004011c - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x11c); - - /// address: 0x40040120 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x120); - - /// address: 0x40040124 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x124); - - /// address: 0x40040128 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x128); - - /// address: 0x4004012c - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x12c); - - /// address: 0x4004001c - /// OTG_HS Receive status debug read register - /// (peripheral mode mode) - pub const OTG_HS_GRXSTSR_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x40040020 - /// OTG_HS status read and pop register - /// (peripheral mode) - pub const OTG_HS_GRXSTSP_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x20); - }; - - /// USB on the go high speed - pub const OTG_HS_HOST = struct { - pub const base_address = 0x40040400; - - /// address: 0x40040400 - /// OTG_HS host configuration - /// register - pub const OTG_HS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS/LS PHY clock select - FSLSPCS: u2, - /// FS- and LS-only support - FSLSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40040404 - /// OTG_HS Host frame interval - /// register - pub const OTG_HS_HFIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interval - FRIVL: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40040408 - /// OTG_HS host frame number/frame time - /// remaining register - pub const OTG_HS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FRNUM: u16, - /// Frame time remaining - FTREM: u16, - }), base_address + 0x8); - - /// address: 0x40040410 - /// OTG_HS_Host periodic transmit FIFO/queue - /// status register - pub const OTG_HS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic transmit data FIFO space - /// available - PTXFSAVL: u16, - /// Periodic transmit request queue space - /// available - PTXQSAV: u8, - /// Top of the periodic transmit request - /// queue - PTXQTOP: u8, - }), base_address + 0x10); - - /// address: 0x40040414 - /// OTG_HS Host all channels interrupt - /// register - pub const OTG_HS_HAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupts - HAINT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40040418 - /// OTG_HS host all channels interrupt mask - /// register - pub const OTG_HS_HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupt mask - HAINTM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40040440 - /// OTG_HS host port control and status - /// register - pub const OTG_HS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port connect status - PCSTS: u1, - /// Port connect detected - PCDET: u1, - /// Port enable - PENA: u1, - /// Port enable/disable change - PENCHNG: u1, - /// Port overcurrent active - POCA: u1, - /// Port overcurrent change - POCCHNG: u1, - /// Port resume - PRES: u1, - /// Port suspend - PSUSP: u1, - /// Port reset - PRST: u1, - reserved0: u1, - /// Port line status - PLSTS: u2, - /// Port power - PPWR: u1, - /// Port test control - PTCTL: u4, - /// Port speed - PSPD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x40040500 - /// OTG_HS host channel-0 characteristics - /// register - pub const OTG_HS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x100); - - /// address: 0x40040520 - /// OTG_HS host channel-1 characteristics - /// register - pub const OTG_HS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x120); - - /// address: 0x40040540 - /// OTG_HS host channel-2 characteristics - /// register - pub const OTG_HS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x140); - - /// address: 0x40040560 - /// OTG_HS host channel-3 characteristics - /// register - pub const OTG_HS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x160); - - /// address: 0x40040580 - /// OTG_HS host channel-4 characteristics - /// register - pub const OTG_HS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x180); - - /// address: 0x400405a0 - /// OTG_HS host channel-5 characteristics - /// register - pub const OTG_HS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1a0); - - /// address: 0x400405c0 - /// OTG_HS host channel-6 characteristics - /// register - pub const OTG_HS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1c0); - - /// address: 0x400405e0 - /// OTG_HS host channel-7 characteristics - /// register - pub const OTG_HS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1e0); - - /// address: 0x40040600 - /// OTG_HS host channel-8 characteristics - /// register - pub const OTG_HS_HCCHAR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x200); - - /// address: 0x40040620 - /// OTG_HS host channel-9 characteristics - /// register - pub const OTG_HS_HCCHAR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x220); - - /// address: 0x40040640 - /// OTG_HS host channel-10 characteristics - /// register - pub const OTG_HS_HCCHAR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x240); - - /// address: 0x40040660 - /// OTG_HS host channel-11 characteristics - /// register - pub const OTG_HS_HCCHAR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x260); - - /// address: 0x40040504 - /// OTG_HS host channel-0 split control - /// register - pub const OTG_HS_HCSPLT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x104); - - /// address: 0x40040524 - /// OTG_HS host channel-1 split control - /// register - pub const OTG_HS_HCSPLT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x124); - - /// address: 0x40040544 - /// OTG_HS host channel-2 split control - /// register - pub const OTG_HS_HCSPLT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x144); - - /// address: 0x40040564 - /// OTG_HS host channel-3 split control - /// register - pub const OTG_HS_HCSPLT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x164); - - /// address: 0x40040584 - /// OTG_HS host channel-4 split control - /// register - pub const OTG_HS_HCSPLT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x184); - - /// address: 0x400405a4 - /// OTG_HS host channel-5 split control - /// register - pub const OTG_HS_HCSPLT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1a4); - - /// address: 0x400405c4 - /// OTG_HS host channel-6 split control - /// register - pub const OTG_HS_HCSPLT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1c4); - - /// address: 0x400405e4 - /// OTG_HS host channel-7 split control - /// register - pub const OTG_HS_HCSPLT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1e4); - - /// address: 0x40040604 - /// OTG_HS host channel-8 split control - /// register - pub const OTG_HS_HCSPLT8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x204); - - /// address: 0x40040624 - /// OTG_HS host channel-9 split control - /// register - pub const OTG_HS_HCSPLT9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x224); - - /// address: 0x40040644 - /// OTG_HS host channel-10 split control - /// register - pub const OTG_HS_HCSPLT10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x244); - - /// address: 0x40040664 - /// OTG_HS host channel-11 split control - /// register - pub const OTG_HS_HCSPLT11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x264); - - /// address: 0x40040508 - /// OTG_HS host channel-11 interrupt - /// register - pub const OTG_HS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x108); - - /// address: 0x40040528 - /// OTG_HS host channel-1 interrupt - /// register - pub const OTG_HS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x128); - - /// address: 0x40040548 - /// OTG_HS host channel-2 interrupt - /// register - pub const OTG_HS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x148); - - /// address: 0x40040568 - /// OTG_HS host channel-3 interrupt - /// register - pub const OTG_HS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x168); - - /// address: 0x40040588 - /// OTG_HS host channel-4 interrupt - /// register - pub const OTG_HS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x188); - - /// address: 0x400405a8 - /// OTG_HS host channel-5 interrupt - /// register - pub const OTG_HS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1a8); - - /// address: 0x400405c8 - /// OTG_HS host channel-6 interrupt - /// register - pub const OTG_HS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c8); - - /// address: 0x400405e8 - /// OTG_HS host channel-7 interrupt - /// register - pub const OTG_HS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1e8); - - /// address: 0x40040608 - /// OTG_HS host channel-8 interrupt - /// register - pub const OTG_HS_HCINT8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x208); - - /// address: 0x40040628 - /// OTG_HS host channel-9 interrupt - /// register - pub const OTG_HS_HCINT9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x228); - - /// address: 0x40040648 - /// OTG_HS host channel-10 interrupt - /// register - pub const OTG_HS_HCINT10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x248); - - /// address: 0x40040668 - /// OTG_HS host channel-11 interrupt - /// register - pub const OTG_HS_HCINT11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x268); - - /// address: 0x4004050c - /// OTG_HS host channel-11 interrupt mask - /// register - pub const OTG_HS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10c); - - /// address: 0x4004052c - /// OTG_HS host channel-1 interrupt mask - /// register - pub const OTG_HS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x12c); - - /// address: 0x4004054c - /// OTG_HS host channel-2 interrupt mask - /// register - pub const OTG_HS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14c); - - /// address: 0x4004056c - /// OTG_HS host channel-3 interrupt mask - /// register - pub const OTG_HS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x16c); - - /// address: 0x4004058c - /// OTG_HS host channel-4 interrupt mask - /// register - pub const OTG_HS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18c); - - /// address: 0x400405ac - /// OTG_HS host channel-5 interrupt mask - /// register - pub const OTG_HS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ac); - - /// address: 0x400405cc - /// OTG_HS host channel-6 interrupt mask - /// register - pub const OTG_HS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1cc); - - /// address: 0x400405ec - /// OTG_HS host channel-7 interrupt mask - /// register - pub const OTG_HS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ec); - - /// address: 0x4004060c - /// OTG_HS host channel-8 interrupt mask - /// register - pub const OTG_HS_HCINTMSK8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x20c); - - /// address: 0x4004062c - /// OTG_HS host channel-9 interrupt mask - /// register - pub const OTG_HS_HCINTMSK9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x22c); - - /// address: 0x4004064c - /// OTG_HS host channel-10 interrupt mask - /// register - pub const OTG_HS_HCINTMSK10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x24c); - - /// address: 0x4004066c - /// OTG_HS host channel-11 interrupt mask - /// register - pub const OTG_HS_HCINTMSK11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x26c); - - /// address: 0x40040510 - /// OTG_HS host channel-11 transfer size - /// register - pub const OTG_HS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x110); - - /// address: 0x40040530 - /// OTG_HS host channel-1 transfer size - /// register - pub const OTG_HS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x40040550 - /// OTG_HS host channel-2 transfer size - /// register - pub const OTG_HS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x40040570 - /// OTG_HS host channel-3 transfer size - /// register - pub const OTG_HS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x40040590 - /// OTG_HS host channel-4 transfer size - /// register - pub const OTG_HS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x400405b0 - /// OTG_HS host channel-5 transfer size - /// register - pub const OTG_HS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x400405d0 - /// OTG_HS host channel-6 transfer size - /// register - pub const OTG_HS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1d0); - - /// address: 0x400405f0 - /// OTG_HS host channel-7 transfer size - /// register - pub const OTG_HS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1f0); - - /// address: 0x40040610 - /// OTG_HS host channel-8 transfer size - /// register - pub const OTG_HS_HCTSIZ8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x210); - - /// address: 0x40040630 - /// OTG_HS host channel-9 transfer size - /// register - pub const OTG_HS_HCTSIZ9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x230); - - /// address: 0x40040650 - /// OTG_HS host channel-10 transfer size - /// register - pub const OTG_HS_HCTSIZ10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x250); - - /// address: 0x40040670 - /// OTG_HS host channel-11 transfer size - /// register - pub const OTG_HS_HCTSIZ11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x270); - - /// address: 0x40040514 - /// OTG_HS host channel-0 DMA address - /// register - pub const OTG_HS_HCDMA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x114); - - /// address: 0x40040534 - /// OTG_HS host channel-1 DMA address - /// register - pub const OTG_HS_HCDMA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x134); - - /// address: 0x40040554 - /// OTG_HS host channel-2 DMA address - /// register - pub const OTG_HS_HCDMA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x154); - - /// address: 0x40040574 - /// OTG_HS host channel-3 DMA address - /// register - pub const OTG_HS_HCDMA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x174); - - /// address: 0x40040594 - /// OTG_HS host channel-4 DMA address - /// register - pub const OTG_HS_HCDMA4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x194); - - /// address: 0x400405b4 - /// OTG_HS host channel-5 DMA address - /// register - pub const OTG_HS_HCDMA5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1b4); - - /// address: 0x400405d4 - /// OTG_HS host channel-6 DMA address - /// register - pub const OTG_HS_HCDMA6 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1d4); - - /// address: 0x400405f4 - /// OTG_HS host channel-7 DMA address - /// register - pub const OTG_HS_HCDMA7 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1f4); - - /// address: 0x40040614 - /// OTG_HS host channel-8 DMA address - /// register - pub const OTG_HS_HCDMA8 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x214); - - /// address: 0x40040634 - /// OTG_HS host channel-9 DMA address - /// register - pub const OTG_HS_HCDMA9 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x234); - - /// address: 0x40040654 - /// OTG_HS host channel-10 DMA address - /// register - pub const OTG_HS_HCDMA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x254); - - /// address: 0x40040674 - /// OTG_HS host channel-11 DMA address - /// register - pub const OTG_HS_HCDMA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x274); - }; - - /// USB on the go high speed - pub const OTG_HS_DEVICE = struct { - pub const base_address = 0x40040800; - - /// address: 0x40040800 - /// OTG_HS device configuration - /// register - pub const OTG_HS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Device speed - DSPD: u2, - /// Nonzero-length status OUT - /// handshake - NZLSOHSK: u1, - reserved0: u1, - /// Device address - DAD: u7, - /// Periodic (micro)frame - /// interval - PFIVL: u2, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Periodic scheduling - /// interval - PERSCHIVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40040804 - /// OTG_HS device control register - pub const OTG_HS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Remote wakeup signaling - RWUSIG: u1, - /// Soft disconnect - SDIS: u1, - /// Global IN NAK status - GINSTS: u1, - /// Global OUT NAK status - GONSTS: u1, - /// Test control - TCTL: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on programming done - POPRGDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40040808 - /// OTG_HS device status register - pub const OTG_HS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Suspend status - SUSPSTS: u1, - /// Enumerated speed - ENUMSPD: u2, - /// Erratic error - EERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Frame number of the received - /// SOF - FNSOF: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x40040810 - /// OTG_HS device IN endpoint common interrupt - /// mask register - pub const OTG_HS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (nonisochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// FIFO underrun mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40040814 - /// OTG_HS device OUT endpoint common interrupt - /// mask register - pub const OTG_HS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// SETUP phase done mask - STUPM: u1, - /// OUT token received when endpoint - /// disabled mask - OTEPDM: u1, - reserved1: u1, - /// Back-to-back SETUP packets received - /// mask - B2BSTUP: u1, - reserved2: u1, - /// OUT packet error mask - OPEM: u1, - /// BNA interrupt mask - BOIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x14); - - /// address: 0x40040818 - /// OTG_HS device all endpoints interrupt - /// register - pub const OTG_HS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint interrupt bits - IEPINT: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x18); - - /// address: 0x4004081c - /// OTG_HS all endpoints interrupt mask - /// register - pub const OTG_HS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP interrupt mask bits - IEPM: u16, - /// OUT EP interrupt mask bits - OEPM: u16, - }), base_address + 0x1c); - - /// address: 0x40040828 - /// OTG_HS device VBUS discharge time - /// register - pub const OTG_HS_DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS discharge time - VBUSDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4004082c - /// OTG_HS device VBUS pulsing time - /// register - pub const OTG_HS_DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS pulsing time - DVBUSP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40040830 - /// OTG_HS Device threshold control - /// register - pub const OTG_HS_DTHRCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonisochronous IN endpoints threshold - /// enable - NONISOTHREN: u1, - /// ISO IN endpoint threshold - /// enable - ISOTHREN: u1, - /// Transmit threshold length - TXTHRLEN: u9, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Receive threshold enable - RXTHREN: u1, - /// Receive threshold length - RXTHRLEN: u9, - reserved5: u1, - /// Arbiter parking enable - ARPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x30); - - /// address: 0x40040834 - /// OTG_HS device IN endpoint FIFO empty - /// interrupt mask register - pub const OTG_HS_DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP Tx FIFO empty interrupt mask - /// bits - INEPTXFEM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40040838 - /// OTG_HS device each endpoint interrupt - /// register - pub const OTG_HS_DEACHINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// IN endpoint 1interrupt bit - IEP1INT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// OUT endpoint 1 interrupt - /// bit - OEP1INT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x38); - - /// address: 0x4004083c - /// OTG_HS device each endpoint interrupt - /// register mask - pub const OTG_HS_DEACHINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// IN Endpoint 1 interrupt mask - /// bit - IEP1INTM: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// OUT Endpoint 1 interrupt mask - /// bit - OEP1INTM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x3c); - - /// address: 0x40040840 - /// OTG_HS device each in endpoint-1 interrupt - /// register - pub const OTG_HS_DIEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (nonisochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// FIFO underrun mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// NAK interrupt mask - NAKM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x40); - - /// address: 0x40040880 - /// OTG_HS device each OUT endpoint-1 interrupt - /// register - pub const OTG_HS_DOEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// OUT packet error mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - reserved2: u1, - reserved3: u1, - /// Bubble error interrupt - /// mask - BERRM: u1, - /// NAK interrupt mask - NAKM: u1, - /// NYET interrupt mask - NYETM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40040900 - /// OTG device endpoint-0 control - /// register - pub const OTG_HS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x100); - - /// address: 0x40040920 - /// OTG device endpoint-1 control - /// register - pub const OTG_HS_DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x120); - - /// address: 0x40040940 - /// OTG device endpoint-2 control - /// register - pub const OTG_HS_DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x140); - - /// address: 0x40040960 - /// OTG device endpoint-3 control - /// register - pub const OTG_HS_DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x160); - - /// address: 0x40040980 - /// OTG device endpoint-4 control - /// register - pub const OTG_HS_DIEPCTL4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x180); - - /// address: 0x400409a0 - /// OTG device endpoint-5 control - /// register - pub const OTG_HS_DIEPCTL5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1a0); - - /// address: 0x400409c0 - /// OTG device endpoint-6 control - /// register - pub const OTG_HS_DIEPCTL6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1c0); - - /// address: 0x400409e0 - /// OTG device endpoint-7 control - /// register - pub const OTG_HS_DIEPCTL7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1e0); - - /// address: 0x40040908 - /// OTG device endpoint-0 interrupt - /// register - pub const OTG_HS_DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x108); - - /// address: 0x40040928 - /// OTG device endpoint-1 interrupt - /// register - pub const OTG_HS_DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x128); - - /// address: 0x40040948 - /// OTG device endpoint-2 interrupt - /// register - pub const OTG_HS_DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x148); - - /// address: 0x40040968 - /// OTG device endpoint-3 interrupt - /// register - pub const OTG_HS_DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x168); - - /// address: 0x40040988 - /// OTG device endpoint-4 interrupt - /// register - pub const OTG_HS_DIEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x188); - - /// address: 0x400409a8 - /// OTG device endpoint-5 interrupt - /// register - pub const OTG_HS_DIEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1a8); - - /// address: 0x400409c8 - /// OTG device endpoint-6 interrupt - /// register - pub const OTG_HS_DIEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c8); - - /// address: 0x400409e8 - /// OTG device endpoint-7 interrupt - /// register - pub const OTG_HS_DIEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1e8); - - /// address: 0x40040910 - /// OTG_HS device IN endpoint 0 transfer size - /// register - pub const OTG_HS_DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x110); - - /// address: 0x40040914 - /// OTG_HS device endpoint-1 DMA address - /// register - pub const OTG_HS_DIEPDMA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x114); - - /// address: 0x40040934 - /// OTG_HS device endpoint-2 DMA address - /// register - pub const OTG_HS_DIEPDMA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x134); - - /// address: 0x40040954 - /// OTG_HS device endpoint-3 DMA address - /// register - pub const OTG_HS_DIEPDMA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x154); - - /// address: 0x40040974 - /// OTG_HS device endpoint-4 DMA address - /// register - pub const OTG_HS_DIEPDMA4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x174); - - /// address: 0x40040994 - /// OTG_HS device endpoint-5 DMA address - /// register - pub const OTG_HS_DIEPDMA5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x194); - - /// address: 0x40040918 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x118); - - /// address: 0x40040938 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x138); - - /// address: 0x40040958 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x158); - - /// address: 0x40040978 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x178); - - /// address: 0x40040998 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x198); - - /// address: 0x400409b8 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1b8); - - /// address: 0x40040930 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x40040950 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x40040970 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x40040990 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x400409b0 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x40040b00 - /// OTG_HS device control OUT endpoint 0 control - /// register - pub const OTG_HS_DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USB active endpoint - USBAEP: u1, - reserved13: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved18: u1, - reserved19: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x300); - - /// address: 0x40040b20 - /// OTG device endpoint-1 control - /// register - pub const OTG_HS_DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x320); - - /// address: 0x40040b40 - /// OTG device endpoint-2 control - /// register - pub const OTG_HS_DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x340); - - /// address: 0x40040b60 - /// OTG device endpoint-3 control - /// register - pub const OTG_HS_DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x360); - - /// address: 0x40040b08 - /// OTG_HS device endpoint-0 interrupt - /// register - pub const OTG_HS_DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x308); - - /// address: 0x40040b28 - /// OTG_HS device endpoint-1 interrupt - /// register - pub const OTG_HS_DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x328); - - /// address: 0x40040b48 - /// OTG_HS device endpoint-2 interrupt - /// register - pub const OTG_HS_DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x348); - - /// address: 0x40040b68 - /// OTG_HS device endpoint-3 interrupt - /// register - pub const OTG_HS_DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x368); - - /// address: 0x40040b88 - /// OTG_HS device endpoint-4 interrupt - /// register - pub const OTG_HS_DOEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x388); - - /// address: 0x40040ba8 - /// OTG_HS device endpoint-5 interrupt - /// register - pub const OTG_HS_DOEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3a8); - - /// address: 0x40040bc8 - /// OTG_HS device endpoint-6 interrupt - /// register - pub const OTG_HS_DOEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3c8); - - /// address: 0x40040be8 - /// OTG_HS device endpoint-7 interrupt - /// register - pub const OTG_HS_DOEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3e8); - - /// address: 0x40040b10 - /// OTG_HS device endpoint-1 transfer size - /// register - pub const OTG_HS_DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// SETUP packet count - STUPCNT: u2, - padding0: u1, - }), base_address + 0x310); - - /// address: 0x40040b30 - /// OTG_HS device endpoint-2 transfer size - /// register - pub const OTG_HS_DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x330); - - /// address: 0x40040b50 - /// OTG_HS device endpoint-3 transfer size - /// register - pub const OTG_HS_DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x350); - - /// address: 0x40040b70 - /// OTG_HS device endpoint-4 transfer size - /// register - pub const OTG_HS_DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x370); - - /// address: 0x40040b90 - /// OTG_HS device endpoint-5 transfer size - /// register - pub const OTG_HS_DOEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x390); - }; - - /// USB on the go high speed - pub const OTG_HS_PWRCLK = struct { - pub const base_address = 0x40040e00; - - /// address: 0x40040e00 - /// Power and clock gating control - /// register - pub const OTG_HS_PCGCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop PHY clock - STPPCLK: u1, - /// Gate HCLK - GATEHCLK: u1, - reserved0: u1, - reserved1: u1, - /// PHY suspended - PHYSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - }; - - /// Nested Vectored Interrupt - /// Controller - pub const NVIC = struct { - pub const base_address = 0xe000e100; - - /// address: 0xe000e100 - /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x0); - - /// address: 0xe000e104 - /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x4); - - /// address: 0xe000e108 - /// Interrupt Set-Enable Register - pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x8); - - /// address: 0xe000e180 - /// Interrupt Clear-Enable - /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x80); - - /// address: 0xe000e184 - /// Interrupt Clear-Enable - /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x84); - - /// address: 0xe000e188 - /// Interrupt Clear-Enable - /// Register - pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x88); - - /// address: 0xe000e200 - /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x100); - - /// address: 0xe000e204 - /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x104); - - /// address: 0xe000e208 - /// Interrupt Set-Pending Register - pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x108); - - /// address: 0xe000e280 - /// Interrupt Clear-Pending - /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x180); - - /// address: 0xe000e284 - /// Interrupt Clear-Pending - /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x184); - - /// address: 0xe000e288 - /// Interrupt Clear-Pending - /// Register - pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x188); - - /// address: 0xe000e300 - /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x200); - - /// address: 0xe000e304 - /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x204); - - /// address: 0xe000e308 - /// Interrupt Active Bit Register - pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x208); - - /// address: 0xe000e400 - /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x300); - - /// address: 0xe000e404 - /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x304); - - /// address: 0xe000e408 - /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x308); - - /// address: 0xe000e40c - /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x30c); - - /// address: 0xe000e410 - /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x310); - - /// address: 0xe000e414 - /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x314); - - /// address: 0xe000e418 - /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x318); - - /// address: 0xe000e41c - /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x31c); - - /// address: 0xe000e420 - /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x320); - - /// address: 0xe000e424 - /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x324); - - /// address: 0xe000e428 - /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x328); - - /// address: 0xe000e42c - /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x32c); - - /// address: 0xe000e430 - /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x330); - - /// address: 0xe000e434 - /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x334); - - /// address: 0xe000e438 - /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x338); - - /// address: 0xe000e43c - /// Interrupt Priority Register - pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x33c); - - /// address: 0xe000e440 - /// Interrupt Priority Register - pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x340); - - /// address: 0xe000e444 - /// Interrupt Priority Register - pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x344); - - /// address: 0xe000e448 - /// Interrupt Priority Register - pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x348); - - /// address: 0xe000e44c - /// Interrupt Priority Register - pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x34c); - }; - - /// Serial audio interface - pub const SAI1 = struct { - pub const base_address = 0x40015800; - - /// address: 0x40015804 - /// SAI AConfiguration register 1 - pub const SAI_ACR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Audio block mode - MODE: u2, - /// Protocol configuration - PRTCFG: u2, - reserved0: u1, - /// Data size - DS: u3, - /// Least significant bit - /// first - LSBFIRST: u1, - /// Clock strobing edge - CKSTR: u1, - /// Synchronization enable - SYNCEN: u2, - /// Mono mode - MONO: u1, - /// Output drive - OUTDRIV: u1, - reserved1: u1, - reserved2: u1, - /// Audio block enable - SAIAEN: u1, - /// DMA enable - DMAEN: u1, - reserved3: u1, - /// No divider - NODIV: u1, - /// Master clock divider - MCKDIV: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40015824 - /// SAI BConfiguration register 1 - pub const SAI_BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Audio block mode - MODE: u2, - /// Protocol configuration - PRTCFG: u2, - reserved0: u1, - /// Data size - DS: u3, - /// Least significant bit - /// first - LSBFIRST: u1, - /// Clock strobing edge - CKSTR: u1, - /// Synchronization enable - SYNCEN: u2, - /// Mono mode - MONO: u1, - /// Output drive - OUTDRIV: u1, - reserved1: u1, - reserved2: u1, - /// Audio block enable - SAIBEN: u1, - /// DMA enable - DMAEN: u1, - reserved3: u1, - /// No divider - NODIV: u1, - /// Master clock divider - MCKDIV: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x40015808 - /// SAI AConfiguration register 2 - pub const SAI_ACR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold - FTH: u3, - /// FIFO flush - FFLUSH: u1, - /// Tristate management on data - /// line - TRIS: u1, - /// Mute - MUTE: u1, - /// Mute value - MUTEVAL: u1, - /// Mute counter - MUTECNT: u6, - /// Complement bit - CPL: u1, - /// Companding mode - COMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40015828 - /// SAI BConfiguration register 2 - pub const SAI_BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold - FTH: u3, - /// FIFO flush - FFLUSH: u1, - /// Tristate management on data - /// line - TRIS: u1, - /// Mute - MUTE: u1, - /// Mute value - MUTEVAL: u1, - /// Mute counter - MUTECNT: u6, - /// Complement bit - CPL: u1, - /// Companding mode - COMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4001580c - /// SAI AFrame configuration - /// register - pub const SAI_AFRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame length - FRL: u8, - /// Frame synchronization active level - /// length - FSALL: u7, - reserved0: u1, - /// Frame synchronization - /// definition - FSDEF: u1, - /// Frame synchronization - /// polarity - FSPOL: u1, - /// Frame synchronization - /// offset - FSOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - - /// address: 0x4001582c - /// SAI BFrame configuration - /// register - pub const SAI_BFRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame length - FRL: u8, - /// Frame synchronization active level - /// length - FSALL: u7, - reserved0: u1, - /// Frame synchronization - /// definition - FSDEF: u1, - /// Frame synchronization - /// polarity - FSPOL: u1, - /// Frame synchronization - /// offset - FSOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x2c); - - /// address: 0x40015810 - /// SAI ASlot register - pub const SAI_ASLOTR = @intToPtr(*volatile Mmio(32, packed struct { - /// First bit offset - FBOFF: u5, - reserved0: u1, - /// Slot size - SLOTSZ: u2, - /// Number of slots in an audio - /// frame - NBSLOT: u4, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Slot enable - SLOTEN: u16, - }), base_address + 0x10); - - /// address: 0x40015830 - /// SAI BSlot register - pub const SAI_BSLOTR = @intToPtr(*volatile Mmio(32, packed struct { - /// First bit offset - FBOFF: u5, - reserved0: u1, - /// Slot size - SLOTSZ: u2, - /// Number of slots in an audio - /// frame - NBSLOT: u4, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Slot enable - SLOTEN: u16, - }), base_address + 0x30); - - /// address: 0x40015814 - /// SAI AInterrupt mask register2 - pub const SAI_AIM = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun/underrun interrupt - /// enable - OVRUDRIE: u1, - /// Mute detection interrupt - /// enable - MUTEDETIE: u1, - /// Wrong clock configuration interrupt - /// enable - WCKCFGIE: u1, - /// FIFO request interrupt - /// enable - FREQIE: u1, - /// Codec not ready interrupt - /// enable - CNRDYIE: u1, - /// Anticipated frame synchronization - /// detection interrupt enable - AFSDETIE: u1, - /// Late frame synchronization detection - /// interrupt enable - LFSDETIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40015834 - /// SAI BInterrupt mask register2 - pub const SAI_BIM = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun/underrun interrupt - /// enable - OVRUDRIE: u1, - /// Mute detection interrupt - /// enable - MUTEDETIE: u1, - /// Wrong clock configuration interrupt - /// enable - WCKCFGIE: u1, - /// FIFO request interrupt - /// enable - FREQIE: u1, - /// Codec not ready interrupt - /// enable - CNRDYIE: u1, - /// Anticipated frame synchronization - /// detection interrupt enable - AFSDETIE: u1, - /// Late frame synchronization detection - /// interrupt enable - LFSDETIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x34); - - /// address: 0x40015818 - /// SAI AStatus register - pub const SAI_ASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun / underrun - OVRUDR: u1, - /// Mute detection - MUTEDET: u1, - /// Wrong clock configuration - /// flag - WCKCFG: u1, - /// FIFO request - FREQ: u1, - /// Codec not ready - CNRDY: u1, - /// Anticipated frame synchronization - /// detection - AFSDET: u1, - /// Late frame synchronization - /// detection - LFSDET: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// FIFO level threshold - FLTH: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x18); - - /// address: 0x40015838 - /// SAI BStatus register - pub const SAI_BSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun / underrun - OVRUDR: u1, - /// Mute detection - MUTEDET: u1, - /// Wrong clock configuration - /// flag - WCKCFG: u1, - /// FIFO request - FREQ: u1, - /// Codec not ready - CNRDY: u1, - /// Anticipated frame synchronization - /// detection - AFSDET: u1, - /// Late frame synchronization - /// detection - LFSDET: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// FIFO level threshold - FLTH: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x38); - - /// address: 0x4001581c - /// SAI AClear flag register - pub const SAI_ACLRFR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear overrun / underrun - COVRUDR: u1, - /// Mute detection flag - CMUTEDET: u1, - /// Clear wrong clock configuration - /// flag - CWCKCFG: u1, - reserved0: u1, - /// Clear codec not ready flag - CCNRDY: u1, - /// Clear anticipated frame synchronization - /// detection flag - CAFSDET: u1, - /// Clear late frame synchronization - /// detection flag - CLFSDET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x1c); - - /// address: 0x4001583c - /// SAI BClear flag register - pub const SAI_BCLRFR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear overrun / underrun - COVRUDR: u1, - /// Mute detection flag - CMUTEDET: u1, - /// Clear wrong clock configuration - /// flag - CWCKCFG: u1, - reserved0: u1, - /// Clear codec not ready flag - CCNRDY: u1, - /// Clear anticipated frame synchronization - /// detection flag - CAFSDET: u1, - /// Clear late frame synchronization - /// detection flag - CLFSDET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x3c); - - /// address: 0x40015820 - /// SAI AData register - pub const SAI_ADR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data - DATA: u32, - }), base_address + 0x20); - - /// address: 0x40015840 - /// SAI BData register - pub const SAI_BDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data - DATA: u32, - }), base_address + 0x40); - }; - - /// LCD-TFT Controller - pub const LTDC = struct { - pub const base_address = 0x40016800; - - /// address: 0x40016808 - /// Synchronization Size Configuration - /// Register - pub const SSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Vertical Synchronization Height (in - /// units of horizontal scan line) - VSH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Horizontal Synchronization Width (in - /// units of pixel clock period) - HSW: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x4001680c - /// Back Porch Configuration - /// Register - pub const BPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Accumulated Vertical back porch (in - /// units of horizontal scan line) - AVBP: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Accumulated Horizontal back porch (in - /// units of pixel clock period) - AHBP: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xc); - - /// address: 0x40016810 - /// Active Width Configuration - /// Register - pub const AWCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Accumulated Active Height (in units of - /// horizontal scan line) - AAH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// AAV - AAV: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x10); - - /// address: 0x40016814 - /// Total Width Configuration - /// Register - pub const TWCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Total Height (in units of horizontal - /// scan line) - TOTALH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Total Width (in units of pixel clock - /// period) - TOTALW: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x40016818 - /// Global Control Register - pub const GCR = @intToPtr(*volatile Mmio(32, packed struct { - /// LCD-TFT controller enable - /// bit - LTDCEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Dither Blue Width - DBW: u3, - reserved3: u1, - /// Dither Green Width - DGW: u3, - reserved4: u1, - /// Dither Red Width - DRW: u3, - reserved5: u1, - /// Dither Enable - DEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Pixel Clock Polarity - PCPOL: u1, - /// Data Enable Polarity - DEPOL: u1, - /// Vertical Synchronization - /// Polarity - VSPOL: u1, - /// Horizontal Synchronization - /// Polarity - HSPOL: u1, - }), base_address + 0x18); - - /// address: 0x40016824 - /// Shadow Reload Configuration - /// Register - pub const SRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Immediate Reload - IMR: u1, - /// Vertical Blanking Reload - VBR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x24); - - /// address: 0x4001682c - /// Background Color Configuration - /// Register - pub const BCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Background Color Red value - BC: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40016834 - /// Interrupt Enable Register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt Enable - LIE: u1, - /// FIFO Underrun Interrupt - /// Enable - FUIE: u1, - /// Transfer Error Interrupt - /// Enable - TERRIE: u1, - /// Register Reload interrupt - /// enable - RRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x34); - - /// address: 0x40016838 - /// Interrupt Status Register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt flag - LIF: u1, - /// FIFO Underrun Interrupt - /// flag - FUIF: u1, - /// Transfer Error interrupt - /// flag - TERRIF: u1, - /// Register Reload Interrupt - /// Flag - RRIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x38); - - /// address: 0x4001683c - /// Interrupt Clear Register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clears the Line Interrupt - /// Flag - CLIF: u1, - /// Clears the FIFO Underrun Interrupt - /// flag - CFUIF: u1, - /// Clears the Transfer Error Interrupt - /// Flag - CTERRIF: u1, - /// Clears Register Reload Interrupt - /// Flag - CRRIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x3c); - - /// address: 0x40016840 - /// Line Interrupt Position Configuration - /// Register - pub const LIPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt Position - LIPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x40); - - /// address: 0x40016844 - /// Current Position Status - /// Register - pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Current Y Position - CYPOS: u16, - /// Current X Position - CXPOS: u16, - }), base_address + 0x44); - - /// address: 0x40016848 - /// Current Display Status - /// Register - pub const CDSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Vertical Data Enable display - /// Status - VDES: u1, - /// Horizontal Data Enable display - /// Status - HDES: u1, - /// Vertical Synchronization display - /// Status - VSYNCS: u1, - /// Horizontal Synchronization display - /// Status - HSYNCS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x48); - - /// address: 0x40016884 - /// Layerx Control Register - pub const L1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Layer Enable - LEN: u1, - /// Color Keying Enable - COLKEN: u1, - reserved0: u1, - reserved1: u1, - /// Color Look-Up Table Enable - CLUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x84); - - /// address: 0x40016888 - /// Layerx Window Horizontal Position - /// Configuration Register - pub const L1WHPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Horizontal Start - /// Position - WHSTPOS: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Window Horizontal Stop - /// Position - WHSPPOS: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4001688c - /// Layerx Window Vertical Position - /// Configuration Register - pub const L1WVPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Vertical Start - /// Position - WVSTPOS: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window Vertical Stop - /// Position - WVSPPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x8c); - - /// address: 0x40016890 - /// Layerx Color Keying Configuration - /// Register - pub const L1CKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Key Blue value - CKBLUE: u8, - /// Color Key Green value - CKGREEN: u8, - /// Color Key Red value - CKRED: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x90); - - /// address: 0x40016894 - /// Layerx Pixel Format Configuration - /// Register - pub const L1PFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pixel Format - PF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x94); - - /// address: 0x40016898 - /// Layerx Constant Alpha Configuration - /// Register - pub const L1CACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Constant Alpha - CONSTA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x98); - - /// address: 0x4001689c - /// Layerx Default Color Configuration - /// Register - pub const L1DCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Default Color Blue - DCBLUE: u8, - /// Default Color Green - DCGREEN: u8, - /// Default Color Red - DCRED: u8, - /// Default Color Alpha - DCALPHA: u8, - }), base_address + 0x9c); - - /// address: 0x400168a0 - /// Layerx Blending Factors Configuration - /// Register - pub const L1BFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blending Factor 2 - BF2: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Blending Factor 1 - BF1: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xa0); - - /// address: 0x400168ac - /// Layerx Color Frame Buffer Address - /// Register - pub const L1CFBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Start - /// Address - CFBADD: u32, - }), base_address + 0xac); - - /// address: 0x400168b0 - /// Layerx Color Frame Buffer Length - /// Register - pub const L1CFBLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Line - /// Length - CFBLL: u13, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Color Frame Buffer Pitch in - /// bytes - CFBP: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0xb0); - - /// address: 0x400168b4 - /// Layerx ColorFrame Buffer Line Number - /// Register - pub const L1CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame Buffer Line Number - CFBLNBR: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xb4); - - /// address: 0x400168c4 - /// Layerx CLUT Write Register - pub const L1CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue value - BLUE: u8, - /// Green value - GREEN: u8, - /// Red value - RED: u8, - /// CLUT Address - CLUTADD: u8, - }), base_address + 0xc4); - - /// address: 0x40016904 - /// Layerx Control Register - pub const L2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Layer Enable - LEN: u1, - /// Color Keying Enable - COLKEN: u1, - reserved0: u1, - reserved1: u1, - /// Color Look-Up Table Enable - CLUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x104); - - /// address: 0x40016908 - /// Layerx Window Horizontal Position - /// Configuration Register - pub const L2WHPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Horizontal Start - /// Position - WHSTPOS: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Window Horizontal Stop - /// Position - WHSPPOS: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x108); - - /// address: 0x4001690c - /// Layerx Window Vertical Position - /// Configuration Register - pub const L2WVPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Vertical Start - /// Position - WVSTPOS: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window Vertical Stop - /// Position - WVSPPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x10c); - - /// address: 0x40016910 - /// Layerx Color Keying Configuration - /// Register - pub const L2CKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Key Blue value - CKBLUE: u8, - /// Color Key Green value - CKGREEN: u7, - /// Color Key Red value - CKRED: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x110); - - /// address: 0x40016914 - /// Layerx Pixel Format Configuration - /// Register - pub const L2PFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pixel Format - PF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x114); - - /// address: 0x40016918 - /// Layerx Constant Alpha Configuration - /// Register - pub const L2CACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Constant Alpha - CONSTA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x118); - - /// address: 0x4001691c - /// Layerx Default Color Configuration - /// Register - pub const L2DCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Default Color Blue - DCBLUE: u8, - /// Default Color Green - DCGREEN: u8, - /// Default Color Red - DCRED: u8, - /// Default Color Alpha - DCALPHA: u8, - }), base_address + 0x11c); - - /// address: 0x40016920 - /// Layerx Blending Factors Configuration - /// Register - pub const L2BFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blending Factor 2 - BF2: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Blending Factor 1 - BF1: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x120); - - /// address: 0x4001692c - /// Layerx Color Frame Buffer Address - /// Register - pub const L2CFBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Start - /// Address - CFBADD: u32, - }), base_address + 0x12c); - - /// address: 0x40016930 - /// Layerx Color Frame Buffer Length - /// Register - pub const L2CFBLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Line - /// Length - CFBLL: u13, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Color Frame Buffer Pitch in - /// bytes - CFBP: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x130); - - /// address: 0x40016934 - /// Layerx ColorFrame Buffer Line Number - /// Register - pub const L2CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame Buffer Line Number - CFBLNBR: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x134); - - /// address: 0x40016944 - /// Layerx CLUT Write Register - pub const L2CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue value - BLUE: u8, - /// Green value - GREEN: u8, - /// Red value - RED: u8, - /// CLUT Address - CLUTADD: u8, - }), base_address + 0x144); - }; - - /// Hash processor - pub const HASH = struct { - pub const base_address = 0x50060400; - - /// address: 0x50060400 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Initialize message digest - /// calculation - INIT: u1, - /// DMA enable - DMAE: u1, - /// Data type selection - DATATYPE: u2, - /// Mode selection - MODE: u1, - /// Algorithm selection - ALGO0: u1, - /// Number of words already - /// pushed - NBW: u4, - /// DIN not empty - DINNE: u1, - /// Multiple DMA Transfers - MDMAT: u1, - reserved2: u1, - reserved3: u1, - /// Long key selection - LKEY: u1, - reserved4: u1, - /// ALGO - ALGO1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x50060404 - /// data input register - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input - DATAIN: u32, - }), base_address + 0x4); - - /// address: 0x50060408 - /// start register - pub const STR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of valid bits in the last word of - /// the message - NBLW: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Digest calculation - DCAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x5006040c - /// digest registers - pub const HR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// H0 - H0: u32, - }), base_address + 0xc); - - /// address: 0x50060410 - /// digest registers - pub const HR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// H1 - H1: u32, - }), base_address + 0x10); - - /// address: 0x50060414 - /// digest registers - pub const HR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// H2 - H2: u32, - }), base_address + 0x14); - - /// address: 0x50060418 - /// digest registers - pub const HR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// H3 - H3: u32, - }), base_address + 0x18); - - /// address: 0x5006041c - /// digest registers - pub const HR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// H4 - H4: u32, - }), base_address + 0x1c); - - /// address: 0x50060420 - /// interrupt enable register - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input interrupt - /// enable - DINIE: u1, - /// Digest calculation completion interrupt - /// enable - DCIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x20); - - /// address: 0x50060424 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input interrupt - /// status - DINIS: u1, - /// Digest calculation completion interrupt - /// status - DCIS: u1, - /// DMA Status - DMAS: u1, - /// Busy bit - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x24); - - /// address: 0x500604f8 - /// context swap registers - pub const CSR0 = @intToPtr(*volatile u32, base_address + 0xf8); - - /// address: 0x500604fc - /// context swap registers - pub const CSR1 = @intToPtr(*volatile u32, base_address + 0xfc); - - /// address: 0x50060500 - /// context swap registers - pub const CSR2 = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x50060504 - /// context swap registers - pub const CSR3 = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x50060508 - /// context swap registers - pub const CSR4 = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x5006050c - /// context swap registers - pub const CSR5 = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x50060510 - /// context swap registers - pub const CSR6 = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x50060514 - /// context swap registers - pub const CSR7 = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x50060518 - /// context swap registers - pub const CSR8 = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x5006051c - /// context swap registers - pub const CSR9 = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x50060520 - /// context swap registers - pub const CSR10 = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x50060524 - /// context swap registers - pub const CSR11 = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x50060528 - /// context swap registers - pub const CSR12 = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x5006052c - /// context swap registers - pub const CSR13 = @intToPtr(*volatile u32, base_address + 0x12c); - - /// address: 0x50060530 - /// context swap registers - pub const CSR14 = @intToPtr(*volatile u32, base_address + 0x130); - - /// address: 0x50060534 - /// context swap registers - pub const CSR15 = @intToPtr(*volatile u32, base_address + 0x134); - - /// address: 0x50060538 - /// context swap registers - pub const CSR16 = @intToPtr(*volatile u32, base_address + 0x138); - - /// address: 0x5006053c - /// context swap registers - pub const CSR17 = @intToPtr(*volatile u32, base_address + 0x13c); - - /// address: 0x50060540 - /// context swap registers - pub const CSR18 = @intToPtr(*volatile u32, base_address + 0x140); - - /// address: 0x50060544 - /// context swap registers - pub const CSR19 = @intToPtr(*volatile u32, base_address + 0x144); - - /// address: 0x50060548 - /// context swap registers - pub const CSR20 = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x5006054c - /// context swap registers - pub const CSR21 = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x50060550 - /// context swap registers - pub const CSR22 = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x50060554 - /// context swap registers - pub const CSR23 = @intToPtr(*volatile u32, base_address + 0x154); - - /// address: 0x50060558 - /// context swap registers - pub const CSR24 = @intToPtr(*volatile u32, base_address + 0x158); - - /// address: 0x5006055c - /// context swap registers - pub const CSR25 = @intToPtr(*volatile u32, base_address + 0x15c); - - /// address: 0x50060560 - /// context swap registers - pub const CSR26 = @intToPtr(*volatile u32, base_address + 0x160); - - /// address: 0x50060564 - /// context swap registers - pub const CSR27 = @intToPtr(*volatile u32, base_address + 0x164); - - /// address: 0x50060568 - /// context swap registers - pub const CSR28 = @intToPtr(*volatile u32, base_address + 0x168); - - /// address: 0x5006056c - /// context swap registers - pub const CSR29 = @intToPtr(*volatile u32, base_address + 0x16c); - - /// address: 0x50060570 - /// context swap registers - pub const CSR30 = @intToPtr(*volatile u32, base_address + 0x170); - - /// address: 0x50060574 - /// context swap registers - pub const CSR31 = @intToPtr(*volatile u32, base_address + 0x174); - - /// address: 0x50060578 - /// context swap registers - pub const CSR32 = @intToPtr(*volatile u32, base_address + 0x178); - - /// address: 0x5006057c - /// context swap registers - pub const CSR33 = @intToPtr(*volatile u32, base_address + 0x17c); - - /// address: 0x50060580 - /// context swap registers - pub const CSR34 = @intToPtr(*volatile u32, base_address + 0x180); - - /// address: 0x50060584 - /// context swap registers - pub const CSR35 = @intToPtr(*volatile u32, base_address + 0x184); - - /// address: 0x50060588 - /// context swap registers - pub const CSR36 = @intToPtr(*volatile u32, base_address + 0x188); - - /// address: 0x5006058c - /// context swap registers - pub const CSR37 = @intToPtr(*volatile u32, base_address + 0x18c); - - /// address: 0x50060590 - /// context swap registers - pub const CSR38 = @intToPtr(*volatile u32, base_address + 0x190); - - /// address: 0x50060594 - /// context swap registers - pub const CSR39 = @intToPtr(*volatile u32, base_address + 0x194); - - /// address: 0x50060598 - /// context swap registers - pub const CSR40 = @intToPtr(*volatile u32, base_address + 0x198); - - /// address: 0x5006059c - /// context swap registers - pub const CSR41 = @intToPtr(*volatile u32, base_address + 0x19c); - - /// address: 0x500605a0 - /// context swap registers - pub const CSR42 = @intToPtr(*volatile u32, base_address + 0x1a0); - - /// address: 0x500605a4 - /// context swap registers - pub const CSR43 = @intToPtr(*volatile u32, base_address + 0x1a4); - - /// address: 0x500605a8 - /// context swap registers - pub const CSR44 = @intToPtr(*volatile u32, base_address + 0x1a8); - - /// address: 0x500605ac - /// context swap registers - pub const CSR45 = @intToPtr(*volatile u32, base_address + 0x1ac); - - /// address: 0x500605b0 - /// context swap registers - pub const CSR46 = @intToPtr(*volatile u32, base_address + 0x1b0); - - /// address: 0x500605b4 - /// context swap registers - pub const CSR47 = @intToPtr(*volatile u32, base_address + 0x1b4); - - /// address: 0x500605b8 - /// context swap registers - pub const CSR48 = @intToPtr(*volatile u32, base_address + 0x1b8); - - /// address: 0x500605bc - /// context swap registers - pub const CSR49 = @intToPtr(*volatile u32, base_address + 0x1bc); - - /// address: 0x500605c0 - /// context swap registers - pub const CSR50 = @intToPtr(*volatile u32, base_address + 0x1c0); - - /// address: 0x500605c4 - /// context swap registers - pub const CSR51 = @intToPtr(*volatile u32, base_address + 0x1c4); - - /// address: 0x500605c8 - /// context swap registers - pub const CSR52 = @intToPtr(*volatile u32, base_address + 0x1c8); - - /// address: 0x500605cc - /// context swap registers - pub const CSR53 = @intToPtr(*volatile u32, base_address + 0x1cc); - - /// address: 0x50060710 - /// HASH digest register - pub const HASH_HR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// H0 - H0: u32, - }), base_address + 0x310); - - /// address: 0x50060714 - /// read-only - pub const HASH_HR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// H1 - H1: u32, - }), base_address + 0x314); - - /// address: 0x50060718 - /// read-only - pub const HASH_HR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// H2 - H2: u32, - }), base_address + 0x318); - - /// address: 0x5006071c - /// read-only - pub const HASH_HR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// H3 - H3: u32, - }), base_address + 0x31c); - - /// address: 0x50060720 - /// read-only - pub const HASH_HR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// H4 - H4: u32, - }), base_address + 0x320); - - /// address: 0x50060724 - /// read-only - pub const HASH_HR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// H5 - H5: u32, - }), base_address + 0x324); - - /// address: 0x50060728 - /// read-only - pub const HASH_HR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// H6 - H6: u32, - }), base_address + 0x328); - - /// address: 0x5006072c - /// read-only - pub const HASH_HR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// H7 - H7: u32, - }), base_address + 0x32c); - }; - - /// Cryptographic processor - pub const CRYP = struct { - pub const base_address = 0x50060000; - - /// address: 0x50060000 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Algorithm direction - ALGODIR: u1, - /// Algorithm mode - ALGOMODE0: u3, - /// Data type selection - DATATYPE: u2, - /// Key size selection (AES mode - /// only) - KEYSIZE: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// FIFO flush - FFLUSH: u1, - /// Cryptographic processor - /// enable - CRYPEN: u1, - /// GCM_CCMPH - GCM_CCMPH: u2, - reserved6: u1, - /// ALGOMODE - ALGOMODE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x50060004 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO empty - IFEM: u1, - /// Input FIFO not full - IFNF: u1, - /// Output FIFO not empty - OFNE: u1, - /// Output FIFO full - OFFU: u1, - /// Busy bit - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x4); - - /// address: 0x50060008 - /// data input register - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input - DATAIN: u32, - }), base_address + 0x8); - - /// address: 0x5006000c - /// data output register - pub const DOUT = @intToPtr(*volatile Mmio(32, packed struct { - /// Data output - DATAOUT: u32, - }), base_address + 0xc); - - /// address: 0x50060010 - /// DMA control register - pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA input enable - DIEN: u1, - /// DMA output enable - DOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x10); - - /// address: 0x50060014 - /// interrupt mask set/clear - /// register - pub const IMSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service interrupt - /// mask - INIM: u1, - /// Output FIFO service interrupt - /// mask - OUTIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x50060018 - /// raw interrupt status register - pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service raw interrupt - /// status - INRIS: u1, - /// Output FIFO service raw interrupt - /// status - OUTRIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x18); - - /// address: 0x5006001c - /// masked interrupt status - /// register - pub const MISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service masked interrupt - /// status - INMIS: u1, - /// Output FIFO service masked interrupt - /// status - OUTMIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x1c); - - /// address: 0x50060020 - /// key registers - pub const K0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b224 - b224: u1, - /// b225 - b225: u1, - /// b226 - b226: u1, - /// b227 - b227: u1, - /// b228 - b228: u1, - /// b229 - b229: u1, - /// b230 - b230: u1, - /// b231 - b231: u1, - /// b232 - b232: u1, - /// b233 - b233: u1, - /// b234 - b234: u1, - /// b235 - b235: u1, - /// b236 - b236: u1, - /// b237 - b237: u1, - /// b238 - b238: u1, - /// b239 - b239: u1, - /// b240 - b240: u1, - /// b241 - b241: u1, - /// b242 - b242: u1, - /// b243 - b243: u1, - /// b244 - b244: u1, - /// b245 - b245: u1, - /// b246 - b246: u1, - /// b247 - b247: u1, - /// b248 - b248: u1, - /// b249 - b249: u1, - /// b250 - b250: u1, - /// b251 - b251: u1, - /// b252 - b252: u1, - /// b253 - b253: u1, - /// b254 - b254: u1, - /// b255 - b255: u1, - }), base_address + 0x20); - - /// address: 0x50060024 - /// key registers - pub const K0RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b192 - b192: u1, - /// b193 - b193: u1, - /// b194 - b194: u1, - /// b195 - b195: u1, - /// b196 - b196: u1, - /// b197 - b197: u1, - /// b198 - b198: u1, - /// b199 - b199: u1, - /// b200 - b200: u1, - /// b201 - b201: u1, - /// b202 - b202: u1, - /// b203 - b203: u1, - /// b204 - b204: u1, - /// b205 - b205: u1, - /// b206 - b206: u1, - /// b207 - b207: u1, - /// b208 - b208: u1, - /// b209 - b209: u1, - /// b210 - b210: u1, - /// b211 - b211: u1, - /// b212 - b212: u1, - /// b213 - b213: u1, - /// b214 - b214: u1, - /// b215 - b215: u1, - /// b216 - b216: u1, - /// b217 - b217: u1, - /// b218 - b218: u1, - /// b219 - b219: u1, - /// b220 - b220: u1, - /// b221 - b221: u1, - /// b222 - b222: u1, - /// b223 - b223: u1, - }), base_address + 0x24); - - /// address: 0x50060028 - /// key registers - pub const K1LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b160 - b160: u1, - /// b161 - b161: u1, - /// b162 - b162: u1, - /// b163 - b163: u1, - /// b164 - b164: u1, - /// b165 - b165: u1, - /// b166 - b166: u1, - /// b167 - b167: u1, - /// b168 - b168: u1, - /// b169 - b169: u1, - /// b170 - b170: u1, - /// b171 - b171: u1, - /// b172 - b172: u1, - /// b173 - b173: u1, - /// b174 - b174: u1, - /// b175 - b175: u1, - /// b176 - b176: u1, - /// b177 - b177: u1, - /// b178 - b178: u1, - /// b179 - b179: u1, - /// b180 - b180: u1, - /// b181 - b181: u1, - /// b182 - b182: u1, - /// b183 - b183: u1, - /// b184 - b184: u1, - /// b185 - b185: u1, - /// b186 - b186: u1, - /// b187 - b187: u1, - /// b188 - b188: u1, - /// b189 - b189: u1, - /// b190 - b190: u1, - /// b191 - b191: u1, - }), base_address + 0x28); - - /// address: 0x5006002c - /// key registers - pub const K1RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b128 - b128: u1, - /// b129 - b129: u1, - /// b130 - b130: u1, - /// b131 - b131: u1, - /// b132 - b132: u1, - /// b133 - b133: u1, - /// b134 - b134: u1, - /// b135 - b135: u1, - /// b136 - b136: u1, - /// b137 - b137: u1, - /// b138 - b138: u1, - /// b139 - b139: u1, - /// b140 - b140: u1, - /// b141 - b141: u1, - /// b142 - b142: u1, - /// b143 - b143: u1, - /// b144 - b144: u1, - /// b145 - b145: u1, - /// b146 - b146: u1, - /// b147 - b147: u1, - /// b148 - b148: u1, - /// b149 - b149: u1, - /// b150 - b150: u1, - /// b151 - b151: u1, - /// b152 - b152: u1, - /// b153 - b153: u1, - /// b154 - b154: u1, - /// b155 - b155: u1, - /// b156 - b156: u1, - /// b157 - b157: u1, - /// b158 - b158: u1, - /// b159 - b159: u1, - }), base_address + 0x2c); - - /// address: 0x50060030 - /// key registers - pub const K2LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b96 - b96: u1, - /// b97 - b97: u1, - /// b98 - b98: u1, - /// b99 - b99: u1, - /// b100 - b100: u1, - /// b101 - b101: u1, - /// b102 - b102: u1, - /// b103 - b103: u1, - /// b104 - b104: u1, - /// b105 - b105: u1, - /// b106 - b106: u1, - /// b107 - b107: u1, - /// b108 - b108: u1, - /// b109 - b109: u1, - /// b110 - b110: u1, - /// b111 - b111: u1, - /// b112 - b112: u1, - /// b113 - b113: u1, - /// b114 - b114: u1, - /// b115 - b115: u1, - /// b116 - b116: u1, - /// b117 - b117: u1, - /// b118 - b118: u1, - /// b119 - b119: u1, - /// b120 - b120: u1, - /// b121 - b121: u1, - /// b122 - b122: u1, - /// b123 - b123: u1, - /// b124 - b124: u1, - /// b125 - b125: u1, - /// b126 - b126: u1, - /// b127 - b127: u1, - }), base_address + 0x30); - - /// address: 0x50060034 - /// key registers - pub const K2RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b64 - b64: u1, - /// b65 - b65: u1, - /// b66 - b66: u1, - /// b67 - b67: u1, - /// b68 - b68: u1, - /// b69 - b69: u1, - /// b70 - b70: u1, - /// b71 - b71: u1, - /// b72 - b72: u1, - /// b73 - b73: u1, - /// b74 - b74: u1, - /// b75 - b75: u1, - /// b76 - b76: u1, - /// b77 - b77: u1, - /// b78 - b78: u1, - /// b79 - b79: u1, - /// b80 - b80: u1, - /// b81 - b81: u1, - /// b82 - b82: u1, - /// b83 - b83: u1, - /// b84 - b84: u1, - /// b85 - b85: u1, - /// b86 - b86: u1, - /// b87 - b87: u1, - /// b88 - b88: u1, - /// b89 - b89: u1, - /// b90 - b90: u1, - /// b91 - b91: u1, - /// b92 - b92: u1, - /// b93 - b93: u1, - /// b94 - b94: u1, - /// b95 - b95: u1, - }), base_address + 0x34); - - /// address: 0x50060038 - /// key registers - pub const K3LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b32 - b32: u1, - /// b33 - b33: u1, - /// b34 - b34: u1, - /// b35 - b35: u1, - /// b36 - b36: u1, - /// b37 - b37: u1, - /// b38 - b38: u1, - /// b39 - b39: u1, - /// b40 - b40: u1, - /// b41 - b41: u1, - /// b42 - b42: u1, - /// b43 - b43: u1, - /// b44 - b44: u1, - /// b45 - b45: u1, - /// b46 - b46: u1, - /// b47 - b47: u1, - /// b48 - b48: u1, - /// b49 - b49: u1, - /// b50 - b50: u1, - /// b51 - b51: u1, - /// b52 - b52: u1, - /// b53 - b53: u1, - /// b54 - b54: u1, - /// b55 - b55: u1, - /// b56 - b56: u1, - /// b57 - b57: u1, - /// b58 - b58: u1, - /// b59 - b59: u1, - /// b60 - b60: u1, - /// b61 - b61: u1, - /// b62 - b62: u1, - /// b63 - b63: u1, - }), base_address + 0x38); - - /// address: 0x5006003c - /// key registers - pub const K3RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b0 - b0: u1, - /// b1 - b1: u1, - /// b2 - b2: u1, - /// b3 - b3: u1, - /// b4 - b4: u1, - /// b5 - b5: u1, - /// b6 - b6: u1, - /// b7 - b7: u1, - /// b8 - b8: u1, - /// b9 - b9: u1, - /// b10 - b10: u1, - /// b11 - b11: u1, - /// b12 - b12: u1, - /// b13 - b13: u1, - /// b14 - b14: u1, - /// b15 - b15: u1, - /// b16 - b16: u1, - /// b17 - b17: u1, - /// b18 - b18: u1, - /// b19 - b19: u1, - /// b20 - b20: u1, - /// b21 - b21: u1, - /// b22 - b22: u1, - /// b23 - b23: u1, - /// b24 - b24: u1, - /// b25 - b25: u1, - /// b26 - b26: u1, - /// b27 - b27: u1, - /// b28 - b28: u1, - /// b29 - b29: u1, - /// b30 - b30: u1, - /// b31 - b31: u1, - }), base_address + 0x3c); - - /// address: 0x50060040 - /// initialization vector - /// registers - pub const IV0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV31 - IV31: u1, - /// IV30 - IV30: u1, - /// IV29 - IV29: u1, - /// IV28 - IV28: u1, - /// IV27 - IV27: u1, - /// IV26 - IV26: u1, - /// IV25 - IV25: u1, - /// IV24 - IV24: u1, - /// IV23 - IV23: u1, - /// IV22 - IV22: u1, - /// IV21 - IV21: u1, - /// IV20 - IV20: u1, - /// IV19 - IV19: u1, - /// IV18 - IV18: u1, - /// IV17 - IV17: u1, - /// IV16 - IV16: u1, - /// IV15 - IV15: u1, - /// IV14 - IV14: u1, - /// IV13 - IV13: u1, - /// IV12 - IV12: u1, - /// IV11 - IV11: u1, - /// IV10 - IV10: u1, - /// IV9 - IV9: u1, - /// IV8 - IV8: u1, - /// IV7 - IV7: u1, - /// IV6 - IV6: u1, - /// IV5 - IV5: u1, - /// IV4 - IV4: u1, - /// IV3 - IV3: u1, - /// IV2 - IV2: u1, - /// IV1 - IV1: u1, - /// IV0 - IV0: u1, - }), base_address + 0x40); - - /// address: 0x50060044 - /// initialization vector - /// registers - pub const IV0RR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV63 - IV63: u1, - /// IV62 - IV62: u1, - /// IV61 - IV61: u1, - /// IV60 - IV60: u1, - /// IV59 - IV59: u1, - /// IV58 - IV58: u1, - /// IV57 - IV57: u1, - /// IV56 - IV56: u1, - /// IV55 - IV55: u1, - /// IV54 - IV54: u1, - /// IV53 - IV53: u1, - /// IV52 - IV52: u1, - /// IV51 - IV51: u1, - /// IV50 - IV50: u1, - /// IV49 - IV49: u1, - /// IV48 - IV48: u1, - /// IV47 - IV47: u1, - /// IV46 - IV46: u1, - /// IV45 - IV45: u1, - /// IV44 - IV44: u1, - /// IV43 - IV43: u1, - /// IV42 - IV42: u1, - /// IV41 - IV41: u1, - /// IV40 - IV40: u1, - /// IV39 - IV39: u1, - /// IV38 - IV38: u1, - /// IV37 - IV37: u1, - /// IV36 - IV36: u1, - /// IV35 - IV35: u1, - /// IV34 - IV34: u1, - /// IV33 - IV33: u1, - /// IV32 - IV32: u1, - }), base_address + 0x44); - - /// address: 0x50060048 - /// initialization vector - /// registers - pub const IV1LR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV95 - IV95: u1, - /// IV94 - IV94: u1, - /// IV93 - IV93: u1, - /// IV92 - IV92: u1, - /// IV91 - IV91: u1, - /// IV90 - IV90: u1, - /// IV89 - IV89: u1, - /// IV88 - IV88: u1, - /// IV87 - IV87: u1, - /// IV86 - IV86: u1, - /// IV85 - IV85: u1, - /// IV84 - IV84: u1, - /// IV83 - IV83: u1, - /// IV82 - IV82: u1, - /// IV81 - IV81: u1, - /// IV80 - IV80: u1, - /// IV79 - IV79: u1, - /// IV78 - IV78: u1, - /// IV77 - IV77: u1, - /// IV76 - IV76: u1, - /// IV75 - IV75: u1, - /// IV74 - IV74: u1, - /// IV73 - IV73: u1, - /// IV72 - IV72: u1, - /// IV71 - IV71: u1, - /// IV70 - IV70: u1, - /// IV69 - IV69: u1, - /// IV68 - IV68: u1, - /// IV67 - IV67: u1, - /// IV66 - IV66: u1, - /// IV65 - IV65: u1, - /// IV64 - IV64: u1, - }), base_address + 0x48); - - /// address: 0x5006004c - /// initialization vector - /// registers - pub const IV1RR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV127 - IV127: u1, - /// IV126 - IV126: u1, - /// IV125 - IV125: u1, - /// IV124 - IV124: u1, - /// IV123 - IV123: u1, - /// IV122 - IV122: u1, - /// IV121 - IV121: u1, - /// IV120 - IV120: u1, - /// IV119 - IV119: u1, - /// IV118 - IV118: u1, - /// IV117 - IV117: u1, - /// IV116 - IV116: u1, - /// IV115 - IV115: u1, - /// IV114 - IV114: u1, - /// IV113 - IV113: u1, - /// IV112 - IV112: u1, - /// IV111 - IV111: u1, - /// IV110 - IV110: u1, - /// IV109 - IV109: u1, - /// IV108 - IV108: u1, - /// IV107 - IV107: u1, - /// IV106 - IV106: u1, - /// IV105 - IV105: u1, - /// IV104 - IV104: u1, - /// IV103 - IV103: u1, - /// IV102 - IV102: u1, - /// IV101 - IV101: u1, - /// IV100 - IV100: u1, - /// IV99 - IV99: u1, - /// IV98 - IV98: u1, - /// IV97 - IV97: u1, - /// IV96 - IV96: u1, - }), base_address + 0x4c); - - /// address: 0x50060050 - /// context swap register - pub const CSGCMCCM0R = @intToPtr(*volatile u32, base_address + 0x50); - - /// address: 0x50060054 - /// context swap register - pub const CSGCMCCM1R = @intToPtr(*volatile u32, base_address + 0x54); - - /// address: 0x50060058 - /// context swap register - pub const CSGCMCCM2R = @intToPtr(*volatile u32, base_address + 0x58); - - /// address: 0x5006005c - /// context swap register - pub const CSGCMCCM3R = @intToPtr(*volatile u32, base_address + 0x5c); - - /// address: 0x50060060 - /// context swap register - pub const CSGCMCCM4R = @intToPtr(*volatile u32, base_address + 0x60); - - /// address: 0x50060064 - /// context swap register - pub const CSGCMCCM5R = @intToPtr(*volatile u32, base_address + 0x64); - - /// address: 0x50060068 - /// context swap register - pub const CSGCMCCM6R = @intToPtr(*volatile u32, base_address + 0x68); - - /// address: 0x5006006c - /// context swap register - pub const CSGCMCCM7R = @intToPtr(*volatile u32, base_address + 0x6c); - - /// address: 0x50060070 - /// context swap register - pub const CSGCM0R = @intToPtr(*volatile u32, base_address + 0x70); - - /// address: 0x50060074 - /// context swap register - pub const CSGCM1R = @intToPtr(*volatile u32, base_address + 0x74); - - /// address: 0x50060078 - /// context swap register - pub const CSGCM2R = @intToPtr(*volatile u32, base_address + 0x78); - - /// address: 0x5006007c - /// context swap register - pub const CSGCM3R = @intToPtr(*volatile u32, base_address + 0x7c); - - /// address: 0x50060080 - /// context swap register - pub const CSGCM4R = @intToPtr(*volatile u32, base_address + 0x80); - - /// address: 0x50060084 - /// context swap register - pub const CSGCM5R = @intToPtr(*volatile u32, base_address + 0x84); - - /// address: 0x50060088 - /// context swap register - pub const CSGCM6R = @intToPtr(*volatile u32, base_address + 0x88); - - /// address: 0x5006008c - /// context swap register - pub const CSGCM7R = @intToPtr(*volatile u32, base_address + 0x8c); - }; - - /// Floting point unit - pub const FPU = struct { - pub const base_address = 0xe000ef34; - - /// address: 0xe000ef34 - /// Floating-point context control - /// register - pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSPACT - LSPACT: u1, - /// USER - USER: u1, - reserved0: u1, - /// THREAD - THREAD: u1, - /// HFRDY - HFRDY: u1, - /// MMRDY - MMRDY: u1, - /// BFRDY - BFRDY: u1, - reserved1: u1, - /// MONRDY - MONRDY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// LSPEN - LSPEN: u1, - /// ASPEN - ASPEN: u1, - }), base_address + 0x0); - - /// address: 0xe000ef38 - /// Floating-point context address - /// register - pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Location of unpopulated - /// floating-point - ADDRESS: u29, - }), base_address + 0x4); - - /// address: 0xe000ef3c - /// Floating-point status control - /// register - pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Invalid operation cumulative exception - /// bit - IOC: u1, - /// Division by zero cumulative exception - /// bit. - DZC: u1, - /// Overflow cumulative exception - /// bit - OFC: u1, - /// Underflow cumulative exception - /// bit - UFC: u1, - /// Inexact cumulative exception - /// bit - IXC: u1, - reserved0: u1, - reserved1: u1, - /// Input denormal cumulative exception - /// bit. - IDC: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Rounding Mode control - /// field - RMode: u2, - /// Flush-to-zero mode control - /// bit: - FZ: u1, - /// Default NaN mode control - /// bit - DN: u1, - /// Alternative half-precision control - /// bit - AHP: u1, - reserved16: u1, - /// Overflow condition code - /// flag - V: u1, - /// Carry condition code flag - C: u1, - /// Zero condition code flag - Z: u1, - /// Negative condition code - /// flag - N: u1, - }), base_address + 0x8); - }; - - /// Memory protection unit - pub const MPU = struct { - pub const base_address = 0xe000ed90; - - /// address: 0xe000ed90 - /// MPU type register - pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Separate flag - SEPARATE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Number of MPU data regions - DREGION: u8, - /// Number of MPU instruction - /// regions - IREGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0xe000ed94 - /// MPU control register - pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Enables the MPU - ENABLE: u1, - /// Enables the operation of MPU during hard - /// fault - HFNMIENA: u1, - /// Enable priviliged software access to - /// default memory map - PRIVDEFENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0xe000ed98 - /// MPU region number register - pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region - REGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0xe000ed9c - /// MPU region base address - /// register - pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region field - REGION: u4, - /// MPU region number valid - VALID: u1, - /// Region base address field - ADDR: u27, - }), base_address + 0xc); - - /// address: 0xe000eda0 - /// MPU region attribute and size - /// register - pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region enable bit. - ENABLE: u1, - /// Size of the MPU protection - /// region - SIZE: u5, - reserved0: u1, - reserved1: u1, - /// Subregion disable bits - SRD: u8, - /// memory attribute - B: u1, - /// memory attribute - C: u1, - /// Shareable memory attribute - S: u1, - /// memory attribute - TEX: u3, - reserved2: u1, - reserved3: u1, - /// Access permission - AP: u3, - reserved4: u1, - /// Instruction access disable - /// bit - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - }; - - /// SysTick timer - pub const STK = struct { - pub const base_address = 0xe000e010; - - /// address: 0xe000e010 - /// SysTick control and status - /// register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - ENABLE: u1, - /// SysTick exception request - /// enable - TICKINT: u1, - /// Clock source selection - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// COUNTFLAG - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0xe000e014 - /// SysTick reload value register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - /// RELOAD value - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0xe000e018 - /// SysTick current value register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - /// Current counter value - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0xe000e01c - /// SysTick calibration value - /// register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration value - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// SKEW flag: Indicates whether the TENMS - /// value is exact - SKEW: u1, - /// NOREF flag. Reads as zero - NOREF: u1, - }), base_address + 0xc); - }; - - /// System control block - pub const SCB = struct { - pub const base_address = 0xe000ed00; - - /// address: 0xe000ed00 - /// CPUID base register - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { - /// Revision number - Revision: u4, - /// Part number of the - /// processor - PartNo: u12, - /// Reads as 0xF - Constant: u4, - /// Variant number - Variant: u4, - /// Implementer code - Implementer: u8, - }), base_address + 0x0); - - /// address: 0xe000ed04 - /// Interrupt control and state - /// register - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Active vector - VECTACTIVE: u9, - reserved0: u1, - reserved1: u1, - /// Return to base level - RETTOBASE: u1, - /// Pending vector - VECTPENDING: u7, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Interrupt pending flag - ISRPENDING: u1, - reserved5: u1, - reserved6: u1, - /// SysTick exception clear-pending - /// bit - PENDSTCLR: u1, - /// SysTick exception set-pending - /// bit - PENDSTSET: u1, - /// PendSV clear-pending bit - PENDSVCLR: u1, - /// PendSV set-pending bit - PENDSVSET: u1, - reserved7: u1, - reserved8: u1, - /// NMI set-pending bit. - NMIPENDSET: u1, - }), base_address + 0x4); - - /// address: 0xe000ed08 - /// Vector table offset register - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Vector table base offset - /// field - TBLOFF: u21, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0xe000ed0c - /// Application interrupt and reset control - /// register - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// VECTRESET - VECTRESET: u1, - /// VECTCLRACTIVE - VECTCLRACTIVE: u1, - /// SYSRESETREQ - SYSRESETREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PRIGROUP - PRIGROUP: u3, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ENDIANESS - ENDIANESS: u1, - /// Register key - VECTKEYSTAT: u16, - }), base_address + 0xc); - - /// address: 0xe000ed10 - /// System control register - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// SLEEPONEXIT - SLEEPONEXIT: u1, - /// SLEEPDEEP - SLEEPDEEP: u1, - reserved1: u1, - /// Send Event on Pending bit - SEVEONPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x10); - - /// address: 0xe000ed14 - /// Configuration and control - /// register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Configures how the processor enters - /// Thread mode - NONBASETHRDENA: u1, - /// USERSETMPEND - USERSETMPEND: u1, - reserved0: u1, - /// UNALIGN_ TRP - UNALIGN__TRP: u1, - /// DIV_0_TRP - DIV_0_TRP: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// BFHFNMIGN - BFHFNMIGN: u1, - /// STKALIGN - STKALIGN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x14); - - /// address: 0xe000ed18 - /// System handler priority - /// registers - pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Priority of system handler - /// 4 - PRI_4: u8, - /// Priority of system handler - /// 5 - PRI_5: u8, - /// Priority of system handler - /// 6 - PRI_6: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000ed1c - /// System handler priority - /// registers - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - /// Priority of system handler - /// 11 - PRI_11: u8, - }), base_address + 0x1c); - - /// address: 0xe000ed20 - /// System handler priority - /// registers - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Priority of system handler - /// 14 - PRI_14: u8, - /// Priority of system handler - /// 15 - PRI_15: u8, - }), base_address + 0x20); - - /// address: 0xe000ed24 - /// System handler control and state - /// register - pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory management fault exception active - /// bit - MEMFAULTACT: u1, - /// Bus fault exception active - /// bit - BUSFAULTACT: u1, - reserved0: u1, - /// Usage fault exception active - /// bit - USGFAULTACT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// SVC call active bit - SVCALLACT: u1, - /// Debug monitor active bit - MONITORACT: u1, - reserved4: u1, - /// PendSV exception active - /// bit - PENDSVACT: u1, - /// SysTick exception active - /// bit - SYSTICKACT: u1, - /// Usage fault exception pending - /// bit - USGFAULTPENDED: u1, - /// Memory management fault exception - /// pending bit - MEMFAULTPENDED: u1, - /// Bus fault exception pending - /// bit - BUSFAULTPENDED: u1, - /// SVC call pending bit - SVCALLPENDED: u1, - /// Memory management fault enable - /// bit - MEMFAULTENA: u1, - /// Bus fault enable bit - BUSFAULTENA: u1, - /// Usage fault enable bit - USGFAULTENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x24); - - /// address: 0xe000ed28 - /// Configurable fault status - /// register - pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Instruction access violation - /// flag - IACCVIOL: u1, - reserved1: u1, - /// Memory manager fault on unstacking for a - /// return from exception - MUNSTKERR: u1, - /// Memory manager fault on stacking for - /// exception entry. - MSTKERR: u1, - /// MLSPERR - MLSPERR: u1, - reserved2: u1, - /// Memory Management Fault Address Register - /// (MMAR) valid flag - MMARVALID: u1, - /// Instruction bus error - IBUSERR: u1, - /// Precise data bus error - PRECISERR: u1, - /// Imprecise data bus error - IMPRECISERR: u1, - /// Bus fault on unstacking for a return - /// from exception - UNSTKERR: u1, - /// Bus fault on stacking for exception - /// entry - STKERR: u1, - /// Bus fault on floating-point lazy state - /// preservation - LSPERR: u1, - reserved3: u1, - /// Bus Fault Address Register (BFAR) valid - /// flag - BFARVALID: u1, - /// Undefined instruction usage - /// fault - UNDEFINSTR: u1, - /// Invalid state usage fault - INVSTATE: u1, - /// Invalid PC load usage - /// fault - INVPC: u1, - /// No coprocessor usage - /// fault. - NOCP: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Unaligned access usage - /// fault - UNALIGNED: u1, - /// Divide by zero usage fault - DIVBYZERO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x28); - - /// address: 0xe000ed2c - /// Hard fault status register - pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Vector table hard fault - VECTTBL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - reserved28: u1, - /// Forced hard fault - FORCED: u1, - /// Reserved for Debug use - DEBUG_VT: u1, - }), base_address + 0x2c); - - /// address: 0xe000ed34 - /// Memory management fault address - /// register - pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0xe000ed38 - /// Bus fault address register - pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); - - /// address: 0xe000ed3c - /// Auxiliary fault status - /// register - pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Implementation defined - IMPDEF: u32, - }), base_address + 0x3c); - }; - - /// Nested vectored interrupt - /// controller - pub const NVIC_STIR = struct { - pub const base_address = 0xe000ef00; - - /// address: 0xe000ef00 - /// Software trigger interrupt - /// register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Software generated interrupt - /// ID - INTID: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - }; - - /// Floating point unit CPACR - pub const FPU_CPACR = struct { - pub const base_address = 0xe000ed88; - - /// address: 0xe000ed88 - /// Coprocessor access control - /// register - pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// CP - CP: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - }; - - /// System control block ACTLR - pub const SCB_ACTRL = struct { - pub const base_address = 0xe000e008; - - /// address: 0xe000e008 - /// Auxiliary control register - pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DISMCYCINT - DISMCYCINT: u1, - /// DISDEFWBUF - DISDEFWBUF: u1, - /// DISFOLD - DISFOLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// DISFPCA - DISFPCA: u1, - /// DISOOFP - DISOOFP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: *const fn () callconv(.C) void, - Naked: *const fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/stm32f407/stm32f407.zig b/src/modules/chips/stm32f407/stm32f407.zig deleted file mode 100644 index 7c3566c..0000000 --- a/src/modules/chips/stm32f407/stm32f407.zig +++ /dev/null @@ -1,625 +0,0 @@ -//! For now we keep all clock settings on the chip defaults. -//! This code currently assumes the STM32F405xx / STM32F407xx clock configuration. -//! TODO: Do something useful for other STM32F40x chips. -//! -//! Specifically, TIM6 is running on a 16 MHz clock, -//! HSI = 16 MHz is the SYSCLK after reset -//! default AHB prescaler = /1 (= values 0..7): -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); -//! ``` -//! -//! so also HCLK = 16 MHz. -//! And with the default APB1 prescaler = /1: -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .PPRE1 = 0 }); -//! ``` -//! -//! results in PCLK1 = 16 MHz. -//! -//! The above default configuration makes U(S)ART2..5 -//! receive a 16 MHz clock by default. -//! -//! USART1 and USART6 use PCLK2, which uses the APB2 prescaler on HCLK, -//! default APB2 prescaler = /1: -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .PPRE2 = 0 }); -//! ``` -//! -//! and therefore USART1 and USART6 receive a 16 MHz clock. -//! - -const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("registers.zig"); -const regs = chip.registers; - -pub usingnamespace chip; - -pub const clock = struct { - pub const Domain = enum { - cpu, - ahb, - apb1, - apb2, - }; -}; - -// Default clock frequencies after reset, see top comment for calculation -pub const clock_frequencies = .{ - .cpu = 16_000_000, - .ahb = 16_000_000, - .apb1 = 16_000_000, - .apb2 = 16_000_000, -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec[0] != 'P') - @compileError(invalid_format_msg); - if (spec[1] < 'A' or spec[1] > 'I') - @compileError(invalid_format_msg); - - return struct { - const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); - /// 'A'...'I' - const gpio_port_name = spec[1..2]; - const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); - const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); - }; -} - -fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { - var temp = reg.read(); - @field(temp, field_name) = value; - reg.write(temp); -} - -pub const gpio = struct { - pub const AlternateFunction = enum(u4) { - af0, - af1, - af2, - af3, - af4, - af5, - af6, - af7, - af8, - af9, - af10, - af11, - af12, - af13, - af14, - af15, - }; - - pub fn setOutput(comptime pin: type) void { - setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); - } - - pub fn setInput(comptime pin: type) void { - setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); - } - - pub fn setAlternateFunction(comptime pin: type, af: AlternateFunction) void { - setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10); - if (pin.pin_number < 8) { - setRegField(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @enumToInt(af)); - } else { - setRegField(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @enumToInt(af)); - } - } - - pub fn read(comptime pin: type) micro.gpio.State { - const idr_reg = pin.gpio_port.IDR; - const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? - return @intToEnum(micro.gpio.State, reg_value); - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - switch (state) { - .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), - .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), - } - } -}; - -pub const uart = struct { - pub const DataBits = enum { - seven, - eight, - nine, - }; - - /// uses the values of USART_CR2.STOP - pub const StopBits = enum(u2) { - one = 0b00, - half = 0b01, - two = 0b10, - one_and_half = 0b11, - }; - - /// uses the values of USART_CR1.PS - pub const Parity = enum(u1) { - even = 0, - odd = 1, - }; - - const PinDirection = std.meta.FieldEnum(micro.uart.Pins); - - /// Checks if a pin is valid for a given uart index and direction - pub fn isValidPin(comptime pin: type, comptime index: usize, comptime direction: PinDirection) bool { - const pin_name = pin.name; - - return switch (direction) { - .tx => switch (index) { - 1 => std.mem.eql(u8, pin_name, "PA9") or std.mem.eql(u8, pin_name, "PB6"), - 2 => std.mem.eql(u8, pin_name, "PA2") or std.mem.eql(u8, pin_name, "PD5"), - 3 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PC10") or std.mem.eql(u8, pin_name, "PD8"), - 4 => std.mem.eql(u8, pin_name, "PA0") or std.mem.eql(u8, pin_name, "PC10"), - 5 => std.mem.eql(u8, pin_name, "PC12"), - 6 => std.mem.eql(u8, pin_name, "PC6") or std.mem.eql(u8, pin_name, "PG14"), - else => unreachable, - }, - // Valid RX pins for the UARTs - .rx => switch (index) { - 1 => std.mem.eql(u8, pin_name, "PA10") or std.mem.eql(u8, pin_name, "PB7"), - 2 => std.mem.eql(u8, pin_name, "PA3") or std.mem.eql(u8, pin_name, "PD6"), - 3 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PC11") or std.mem.eql(u8, pin_name, "PD9"), - 4 => std.mem.eql(u8, pin_name, "PA1") or std.mem.eql(u8, pin_name, "PC11"), - 5 => std.mem.eql(u8, pin_name, "PD2"), - 6 => std.mem.eql(u8, pin_name, "PC7") or std.mem.eql(u8, pin_name, "PG9"), - else => unreachable, - }, - }; - } -}; - -pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { - if (index < 1 or index > 6) @compileError("Valid USART index are 1..6"); - - const usart_name = std.fmt.comptimePrint("USART{d}", .{index}); - const tx_pin = - if (pins.tx) |tx| - if (uart.isValidPin(tx, index, .tx)) - tx - else - @compileError(std.fmt.comptimePrint("Tx pin {s} is not valid for UART{}", .{ tx.name, index })) - else switch (index) { - // Provide default tx pins if no pin is specified - 1 => micro.Pin("PA9"), - 2 => micro.Pin("PA2"), - 3 => micro.Pin("PB10"), - 4 => micro.Pin("PA0"), - 5 => micro.Pin("PC12"), - 6 => micro.Pin("PC6"), - else => unreachable, - }; - - const rx_pin = - if (pins.rx) |rx| - if (uart.isValidPin(rx, index, .rx)) - rx - else - @compileError(std.fmt.comptimePrint("Rx pin {s} is not valid for UART{}", .{ rx.name, index })) - else switch (index) { - // Provide default rx pins if no pin is specified - 1 => micro.Pin("PA10"), - 2 => micro.Pin("PA3"), - 3 => micro.Pin("PB11"), - 4 => micro.Pin("PA1"), - 5 => micro.Pin("PD2"), - 6 => micro.Pin("PC7"), - else => unreachable, - }; - - // USART1..3 are AF7, USART 4..6 are AF8 - const alternate_function = if (index <= 3) .af7 else .af8; - - const tx_gpio = micro.Gpio(tx_pin, .{ - .mode = .alternate_function, - .alternate_function = alternate_function, - }); - const rx_gpio = micro.Gpio(rx_pin, .{ - .mode = .alternate_function, - .alternate_function = alternate_function, - }); - - return struct { - parity_read_mask: u8, - - const Self = @This(); - - pub fn init(config: micro.uart.Config) !Self { - // The following must all be written when the USART is disabled (UE=0). - if (@field(regs, usart_name).CR1.read().UE == 1) - @panic("Trying to initialize " ++ usart_name ++ " while it is already enabled"); - // LATER: Alternatively, set UE=0 at this point? Then wait for something? - // Or add a destroy() function which disables the USART? - - // enable the USART clock - const clk_enable_reg = switch (index) { - 1, 6 => regs.RCC.APB2ENR, - 2...5 => regs.RCC.APB1ENR, - else => unreachable, - }; - setRegField(clk_enable_reg, usart_name ++ "EN", 1); - - tx_gpio.init(); - rx_gpio.init(); - - // clear USART configuration to its default - @field(regs, usart_name).CR1.raw = 0; - @field(regs, usart_name).CR2.raw = 0; - @field(regs, usart_name).CR3.raw = 0; - - // Return error for unsupported combinations - if (config.data_bits == .nine and config.parity != null) { - // TODO: should we consider this an unsupported word size or unsupported parity? - return error.UnsupportedWordSize; - } else if (config.data_bits == .seven and config.parity == null) { - // TODO: should we consider this an unsupported word size or unsupported parity? - return error.UnsupportedWordSize; - } - - // set word length - // Per the reference manual, M means - // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default - // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits - const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0; - @field(regs, usart_name).CR1.modify(.{ .M = m }); - - // set parity - if (config.parity) |parity| { - @field(regs, usart_name).CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); - } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default - - // set number of stop bits - @field(regs, usart_name).CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); - - // set the baud rate - // Despite the reference manual talking about fractional calculation and other buzzwords, - // it is actually just a simple divider. Just ignore DIV_Mantissa and DIV_Fraction and - // set the result of the division as the lower 16 bits of BRR. - // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling). - // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) - // TODO: Do a rounding div, instead of a truncating div? - const clocks = micro.clock.get(); - const bus_frequency = switch (index) { - 1, 6 => clocks.apb2, - 2...5 => clocks.apb1, - else => unreachable, - }; - const usartdiv = @intCast(u16, @divTrunc(bus_frequency, config.baud_rate)); - @field(regs, usart_name).BRR.raw = usartdiv; - - // enable USART, and its transmitter and receiver - @field(regs, usart_name).CR1.modify(.{ .UE = 1 }); - @field(regs, usart_name).CR1.modify(.{ .TE = 1 }); - @field(regs, usart_name).CR1.modify(.{ .RE = 1 }); - - // For code simplicity, at cost of one or more register reads, - // we read back the actual configuration from the registers, - // instead of using the `config` values. - return readFromRegisters(); - } - - pub fn getOrInit(config: micro.uart.Config) !Self { - if (@field(regs, usart_name).CR1.read().UE == 1) { - // UART1 already enabled, don't reinitialize and disturb things; - // instead read and use the actual configuration. - return readFromRegisters(); - } else return init(config); - } - - fn readFromRegisters() Self { - const cr1 = @field(regs, usart_name).CR1.read(); - // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. - // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, - // then we also mask away the 8th bit. - return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; - } - - pub fn canWrite(self: Self) bool { - _ = self; - return switch (@field(regs, usart_name).SR.read().TXE) { - 1 => true, - 0 => false, - }; - } - - pub fn tx(self: Self, ch: u8) void { - while (!self.canWrite()) {} // Wait for Previous transmission - @field(regs, usart_name).DR.modify(ch); - } - - pub fn txflush(_: Self) void { - while (@field(regs, usart_name).SR.read().TC == 0) {} - } - - pub fn canRead(self: Self) bool { - _ = self; - return switch (@field(regs, usart_name).SR.read().RXNE) { - 1 => true, - 0 => false, - }; - } - - pub fn rx(self: Self) u8 { - while (!self.canRead()) {} // Wait till the data is received - const data_with_parity_bit: u9 = @field(regs, usart_name).DR.read(); - return @intCast(u8, data_with_parity_bit & self.parity_read_mask); - } - }; -} - -pub const i2c = struct { - const PinLine = std.meta.FieldEnum(micro.i2c.Pins); - - /// Checks if a pin is valid for a given i2c index and line - pub fn isValidPin(comptime pin: type, comptime index: usize, comptime line: PinLine) bool { - const pin_name = pin.name; - - return switch (line) { - .scl => switch (index) { - 1 => std.mem.eql(u8, pin_name, "PB6") or std.mem.eql(u8, pin_name, "PB8"), - 2 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PF1") or std.mem.eql(u8, pin_name, "PH4"), - 3 => std.mem.eql(u8, pin_name, "PA8") or std.mem.eql(u8, pin_name, "PH7"), - else => unreachable, - }, - // Valid RX pins for the UARTs - .sda => switch (index) { - 1 => std.mem.eql(u8, pin_name, "PB7") or std.mem.eql(u8, pin_name, "PB9"), - 2 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PF0") or std.mem.eql(u8, pin_name, "PH5"), - 3 => std.mem.eql(u8, pin_name, "PC9") or std.mem.eql(u8, pin_name, "PH8"), - else => unreachable, - }, - }; - } -}; - -pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { - if (index < 1 or index > 3) @compileError("Valid I2C index are 1..3"); - - const i2c_name = std.fmt.comptimePrint("I2C{d}", .{index}); - const scl_pin = - if (pins.scl) |scl| - if (uart.isValidPin(scl, index, .scl)) - scl - else - @compileError(std.fmt.comptimePrint("SCL pin {s} is not valid for I2C{}", .{ scl.name, index })) - else switch (index) { - // Provide default scl pins if no pin is specified - 1 => micro.Pin("PB6"), - 2 => micro.Pin("PB10"), - 3 => micro.Pin("PA8"), - else => unreachable, - }; - - const sda_pin = - if (pins.sda) |sda| - if (uart.isValidPin(sda, index, .sda)) - sda - else - @compileError(std.fmt.comptimePrint("SDA pin {s} is not valid for UART{}", .{ sda.name, index })) - else switch (index) { - // Provide default sda pins if no pin is specified - 1 => micro.Pin("PB7"), - 2 => micro.Pin("PB11"), - 3 => micro.Pin("PC9"), - else => unreachable, - }; - - const scl_gpio = micro.Gpio(scl_pin, .{ - .mode = .alternate_function, - .alternate_function = .af4, - }); - const sda_gpio = micro.Gpio(sda_pin, .{ - .mode = .alternate_function, - .alternate_function = .af4, - }); - - // Base field of the specific I2C peripheral - const i2c_base = @field(regs, i2c_name); - - return struct { - const Self = @This(); - - pub fn init(config: micro.i2c.Config) !Self { - // Configure I2C - - // 1. Enable the I2C CLOCK and GPIO CLOCK - regs.RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); - regs.RCC.AHB1ENR.modify(.{ .GPIOBEN = 1 }); - - // 2. Configure the I2C PINs - // This takes care of setting them alternate function mode with the correct AF - scl_gpio.init(); - sda_gpio.init(); - - // TODO: the stuff below will probably use the microzig gpio API in the future - const scl = scl_pin.source_pin; - const sda = sda_pin.source_pin; - // Select Open Drain Output - setRegField(@field(scl.gpio_port, "OTYPER"), "OT" ++ scl.suffix, 1); - setRegField(@field(sda.gpio_port, "OTYPER"), "OT" ++ sda.suffix, 1); - // Select High Speed - setRegField(@field(scl.gpio_port, "OSPEEDR"), "OSPEEDR" ++ scl.suffix, 0b10); - setRegField(@field(sda.gpio_port, "OSPEEDR"), "OSPEEDR" ++ sda.suffix, 0b10); - // Activate Pull-up - setRegField(@field(scl.gpio_port, "PUPDR"), "PUPDR" ++ scl.suffix, 0b01); - setRegField(@field(sda.gpio_port, "PUPDR"), "PUPDR" ++ sda.suffix, 0b01); - - // 3. Reset the I2C - i2c_base.CR1.modify(.{ .PE = 0 }); - while (i2c_base.CR1.read().PE == 1) {} - - // 4. Configure I2C timing - const bus_frequency_hz = micro.clock.get().apb1; - const bus_frequency_mhz: u6 = @intCast(u6, @divExact(bus_frequency_hz, 1_000_000)); - - if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) { - return error.InvalidBusFrequency; - } - - // .FREQ is set to the bus frequency in Mhz - i2c_base.CR2.modify(.{ .FREQ = bus_frequency_mhz }); - - switch (config.target_speed) { - 10_000...100_000 => { - // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed. - const ccr = @intCast(u12, @divFloor(bus_frequency_hz, config.target_speed * 2)); - i2c_base.CCR.modify(.{ .CCR = ccr }); - // Trise is bus frequency in Mhz + 1 - i2c_base.TRISE.modify(bus_frequency_mhz + 1); - }, - 100_001...400_000 => { - // TODO: handle fast mode - return error.InvalidSpeed; - }, - else => return error.InvalidSpeed, - } - - // 5. Program the I2C_CR1 register to enable the peripheral - i2c_base.CR1.modify(.{ .PE = 1 }); - - return Self{}; - } - - pub const WriteState = struct { - address: u7, - buffer: [255]u8 = undefined, - buffer_size: u8 = 0, - - pub fn start(address: u7) !WriteState { - return WriteState{ .address = address }; - } - - pub fn writeAll(self: *WriteState, bytes: []const u8) !void { - std.debug.assert(self.buffer_size < 255); - for (bytes) |b| { - self.buffer[self.buffer_size] = b; - self.buffer_size += 1; - if (self.buffer_size == 255) { - try self.sendBuffer(); - } - } - } - - fn sendBuffer(self: *WriteState) !void { - if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); - - // Wait for the bus to be free - while (i2c_base.SR2.read().BUSY == 1) {} - - // Send start - i2c_base.CR1.modify(.{ .START = 1 }); - - // Wait for the end of the start condition, master mode selected, and BUSY bit set - while ((i2c_base.SR1.read().SB == 0 or - i2c_base.SR2.read().MSL == 0 or - i2c_base.SR2.read().BUSY == 0)) - {} - - // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation - i2c_base.DR.modify(@intCast(u8, self.address) << 1); - - // Wait for address confirmation - while (i2c_base.SR1.read().ADDR == 0) {} - - // Read SR2 to clear address condition - _ = i2c_base.SR2.read(); - - for (self.buffer[0..self.buffer_size]) |b| { - // Write data byte - i2c_base.DR.modify(b); - // Wait for transfer finished - while (i2c_base.SR1.read().BTF == 0) {} - } - self.buffer_size = 0; - } - - pub fn stop(self: *WriteState) !void { - try self.sendBuffer(); - // Communication STOP - i2c_base.CR1.modify(.{ .STOP = 1 }); - while (i2c_base.SR2.read().BUSY == 1) {} - } - - pub fn restartRead(self: *WriteState) !ReadState { - try self.sendBuffer(); - return ReadState{ .address = self.address }; - } - pub fn restartWrite(self: *WriteState) !WriteState { - try self.sendBuffer(); - return WriteState{ .address = self.address }; - } - }; - - pub const ReadState = struct { - address: u7, - - pub fn start(address: u7) !ReadState { - return ReadState{ .address = address }; - } - - /// Fails with ReadError if incorrect number of bytes is received. - pub fn readNoEof(self: *ReadState, buffer: []u8) !void { - std.debug.assert(buffer.len < 256); - - // Send start and enable ACK - i2c_base.CR1.modify(.{ .START = 1, .ACK = 1 }); - - // Wait for the end of the start condition, master mode selected, and BUSY bit set - while ((i2c_base.SR1.read().SB == 0 or - i2c_base.SR2.read().MSL == 0 or - i2c_base.SR2.read().BUSY == 0)) - {} - - // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation - i2c_base.DR.modify((@intCast(u8, self.address) << 1) | 1); - - // Wait for address confirmation - while (i2c_base.SR1.read().ADDR == 0) {} - - // Read SR2 to clear address condition - _ = i2c_base.SR2.read(); - - for (buffer) |_, i| { - if (i == buffer.len - 1) { - // Disable ACK - i2c_base.CR1.modify(.{ .ACK = 0 }); - } - - // Wait for data to be received - while (i2c_base.SR1.read().RxNE == 0) {} - - // Read data byte - buffer[i] = i2c_base.DR.read(); - } - } - - pub fn stop(_: *ReadState) !void { - // Communication STOP - i2c_base.CR1.modify(.{ .STOP = 1 }); - while (i2c_base.SR2.read().BUSY == 1) {} - } - - pub fn restartRead(self: *ReadState) !ReadState { - return ReadState{ .address = self.address }; - } - pub fn restartWrite(self: *ReadState) !WriteState { - return WriteState{ .address = self.address }; - } - }; - }; -} diff --git a/src/modules/chips/stm32f429/registers.zig b/src/modules/chips/stm32f429/registers.zig deleted file mode 100644 index b6b5223..0000000 --- a/src/modules/chips/stm32f429/registers.zig +++ /dev/null @@ -1,53886 +0,0 @@ -// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 6376709051af4d8920d5c8bb48945ca688af32ae -// -// device: STM32F429 -// cpu: CM4 - -pub const VectorTable = extern struct { - initial_stack_pointer: u32, - Reset: InterruptVector = unhandled, - NMI: InterruptVector = unhandled, - HardFault: InterruptVector = unhandled, - MemManage: InterruptVector = unhandled, - BusFault: InterruptVector = unhandled, - UsageFault: InterruptVector = unhandled, - reserved0: [4]u32 = undefined, - SVCall: InterruptVector = unhandled, - reserved1: [2]u32 = undefined, - PendSV: InterruptVector = unhandled, - SysTick: InterruptVector = unhandled, - /// Window Watchdog interrupt - WWDG: InterruptVector = unhandled, - /// PVD through EXTI line detection - /// interrupt - PVD: InterruptVector = unhandled, - /// Tamper and TimeStamp interrupts through the - /// EXTI line - TAMP_STAMP: InterruptVector = unhandled, - /// RTC Wakeup interrupt through the EXTI - /// line - RTC_WKUP: InterruptVector = unhandled, - /// Flash global interrupt - FLASH: InterruptVector = unhandled, - /// RCC global interrupt - RCC: InterruptVector = unhandled, - /// EXTI Line0 interrupt - EXTI0: InterruptVector = unhandled, - /// EXTI Line1 interrupt - EXTI1: InterruptVector = unhandled, - /// EXTI Line2 interrupt - EXTI2: InterruptVector = unhandled, - /// EXTI Line3 interrupt - EXTI3: InterruptVector = unhandled, - /// EXTI Line4 interrupt - EXTI4: InterruptVector = unhandled, - /// DMA1 Stream0 global interrupt - DMA1_Stream0: InterruptVector = unhandled, - /// DMA1 Stream1 global interrupt - DMA1_Stream1: InterruptVector = unhandled, - /// DMA1 Stream2 global interrupt - DMA1_Stream2: InterruptVector = unhandled, - /// DMA1 Stream3 global interrupt - DMA1_Stream3: InterruptVector = unhandled, - /// DMA1 Stream4 global interrupt - DMA1_Stream4: InterruptVector = unhandled, - /// DMA1 Stream5 global interrupt - DMA1_Stream5: InterruptVector = unhandled, - /// DMA1 Stream6 global interrupt - DMA1_Stream6: InterruptVector = unhandled, - /// ADC2 global interrupts - ADC: InterruptVector = unhandled, - /// CAN1 TX interrupts - CAN1_TX: InterruptVector = unhandled, - /// CAN1 RX0 interrupts - CAN1_RX0: InterruptVector = unhandled, - /// CAN1 RX1 interrupts - CAN1_RX1: InterruptVector = unhandled, - /// CAN1 SCE interrupt - CAN1_SCE: InterruptVector = unhandled, - /// EXTI Line[9:5] interrupts - EXTI9_5: InterruptVector = unhandled, - /// TIM1 Break interrupt and TIM9 global - /// interrupt - TIM1_BRK_TIM9: InterruptVector = unhandled, - /// TIM1 Update interrupt and TIM10 global - /// interrupt - TIM1_UP_TIM10: InterruptVector = unhandled, - /// TIM1 Trigger and Commutation interrupts and - /// TIM11 global interrupt - TIM1_TRG_COM_TIM11: InterruptVector = unhandled, - /// TIM1 Capture Compare interrupt - TIM1_CC: InterruptVector = unhandled, - /// TIM2 global interrupt - TIM2: InterruptVector = unhandled, - /// TIM3 global interrupt - TIM3: InterruptVector = unhandled, - /// TIM4 global interrupt - TIM4: InterruptVector = unhandled, - /// I2C1 event interrupt - I2C1_EV: InterruptVector = unhandled, - /// I2C1 error interrupt - I2C1_ER: InterruptVector = unhandled, - /// I2C2 event interrupt - I2C2_EV: InterruptVector = unhandled, - /// I2C2 error interrupt - I2C2_ER: InterruptVector = unhandled, - /// SPI1 global interrupt - SPI1: InterruptVector = unhandled, - /// SPI2 global interrupt - SPI2: InterruptVector = unhandled, - /// USART1 global interrupt - USART1: InterruptVector = unhandled, - /// USART2 global interrupt - USART2: InterruptVector = unhandled, - /// USART3 global interrupt - USART3: InterruptVector = unhandled, - /// EXTI Line[15:10] interrupts - EXTI15_10: InterruptVector = unhandled, - /// RTC Alarms (A and B) through EXTI line - /// interrupt - RTC_Alarm: InterruptVector = unhandled, - /// USB On-The-Go FS Wakeup through EXTI line - /// interrupt - OTG_FS_WKUP: InterruptVector = unhandled, - /// TIM8 Break interrupt and TIM12 global - /// interrupt - TIM8_BRK_TIM12: InterruptVector = unhandled, - /// TIM8 Update interrupt and TIM13 global - /// interrupt - TIM8_UP_TIM13: InterruptVector = unhandled, - /// TIM8 Trigger and Commutation interrupts and - /// TIM14 global interrupt - TIM8_TRG_COM_TIM14: InterruptVector = unhandled, - /// TIM8 Capture Compare interrupt - TIM8_CC: InterruptVector = unhandled, - /// DMA1 Stream7 global interrupt - DMA1_Stream7: InterruptVector = unhandled, - /// FMC global interrupt - FMC: InterruptVector = unhandled, - /// SDIO global interrupt - SDIO: InterruptVector = unhandled, - /// TIM5 global interrupt - TIM5: InterruptVector = unhandled, - /// SPI3 global interrupt - SPI3: InterruptVector = unhandled, - /// UART4 global interrupt - UART4: InterruptVector = unhandled, - /// UART5 global interrupt - UART5: InterruptVector = unhandled, - /// TIM6 global interrupt, DAC1 and DAC2 underrun - /// error interrupt - TIM6_DAC: InterruptVector = unhandled, - /// TIM7 global interrupt - TIM7: InterruptVector = unhandled, - /// DMA2 Stream0 global interrupt - DMA2_Stream0: InterruptVector = unhandled, - /// DMA2 Stream1 global interrupt - DMA2_Stream1: InterruptVector = unhandled, - /// DMA2 Stream2 global interrupt - DMA2_Stream2: InterruptVector = unhandled, - /// DMA2 Stream3 global interrupt - DMA2_Stream3: InterruptVector = unhandled, - /// DMA2 Stream4 global interrupt - DMA2_Stream4: InterruptVector = unhandled, - /// Ethernet global interrupt - ETH: InterruptVector = unhandled, - /// Ethernet Wakeup through EXTI line - /// interrupt - ETH_WKUP: InterruptVector = unhandled, - /// CAN2 TX interrupts - CAN2_TX: InterruptVector = unhandled, - /// CAN2 RX0 interrupts - CAN2_RX0: InterruptVector = unhandled, - /// CAN2 RX1 interrupts - CAN2_RX1: InterruptVector = unhandled, - /// CAN2 SCE interrupt - CAN2_SCE: InterruptVector = unhandled, - /// USB On The Go FS global - /// interrupt - OTG_FS: InterruptVector = unhandled, - /// DMA2 Stream5 global interrupt - DMA2_Stream5: InterruptVector = unhandled, - /// DMA2 Stream6 global interrupt - DMA2_Stream6: InterruptVector = unhandled, - /// DMA2 Stream7 global interrupt - DMA2_Stream7: InterruptVector = unhandled, - /// USART6 global interrupt - USART6: InterruptVector = unhandled, - /// I2C3 event interrupt - I2C3_EV: InterruptVector = unhandled, - /// I2C3 error interrupt - I2C3_ER: InterruptVector = unhandled, - /// USB On The Go HS End Point 1 Out global - /// interrupt - OTG_HS_EP1_OUT: InterruptVector = unhandled, - /// USB On The Go HS End Point 1 In global - /// interrupt - OTG_HS_EP1_IN: InterruptVector = unhandled, - /// USB On The Go HS Wakeup through EXTI - /// interrupt - OTG_HS_WKUP: InterruptVector = unhandled, - /// USB On The Go HS global - /// interrupt - OTG_HS: InterruptVector = unhandled, - /// DCMI global interrupt - DCMI: InterruptVector = unhandled, - /// CRYP crypto global interrupt - CRYP: InterruptVector = unhandled, - /// Hash and Rng global interrupt - HASH_RNG: InterruptVector = unhandled, - /// FPU interrupt - FPU: InterruptVector = unhandled, - /// UART 7 global interrupt - UART7: InterruptVector = unhandled, - /// UART 8 global interrupt - UART8: InterruptVector = unhandled, - /// SPI 4 global interrupt - SPI4: InterruptVector = unhandled, - /// SPI 5 global interrupt - SPI5: InterruptVector = unhandled, - /// SPI 6 global interrupt - SPI6: InterruptVector = unhandled, - /// SAI1 global interrupt - SAI1: InterruptVector = unhandled, - /// LTDC global interrupt - LCD_TFT: InterruptVector = unhandled, - /// LTDC global error interrupt - LCD_TFT_1: InterruptVector = unhandled, - /// DMA2D global interrupt - DMA2D: InterruptVector = unhandled, -}; - -pub const registers = struct { - /// Random number generator - pub const RNG = struct { - pub const base_address = 0x50060800; - - /// address: 0x50060800 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Random number generator - /// enable - RNGEN: u1, - /// Interrupt enable - IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x0); - - /// address: 0x50060804 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data ready - DRDY: u1, - /// Clock error current status - CECS: u1, - /// Seed error current status - SECS: u1, - reserved0: u1, - reserved1: u1, - /// Clock error interrupt - /// status - CEIS: u1, - /// Seed error interrupt - /// status - SEIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x50060808 - /// data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Random data - RNDATA: u32, - }), base_address + 0x8); - }; - - /// Hash processor - pub const HASH = struct { - pub const base_address = 0x50060400; - - /// address: 0x50060400 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Initialize message digest - /// calculation - INIT: u1, - /// DMA enable - DMAE: u1, - /// Data type selection - DATATYPE: u2, - /// Mode selection - MODE: u1, - /// Algorithm selection - ALGO0: u1, - /// Number of words already - /// pushed - NBW: u4, - /// DIN not empty - DINNE: u1, - /// Multiple DMA Transfers - MDMAT: u1, - reserved2: u1, - reserved3: u1, - /// Long key selection - LKEY: u1, - reserved4: u1, - /// ALGO - ALGO1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x50060404 - /// data input register - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input - DATAIN: u32, - }), base_address + 0x4); - - /// address: 0x50060408 - /// start register - pub const STR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of valid bits in the last word of - /// the message - NBLW: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Digest calculation - DCAL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x5006040c - /// digest registers - pub const HR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// H0 - H0: u32, - }), base_address + 0xc); - - /// address: 0x50060410 - /// digest registers - pub const HR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// H1 - H1: u32, - }), base_address + 0x10); - - /// address: 0x50060414 - /// digest registers - pub const HR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// H2 - H2: u32, - }), base_address + 0x14); - - /// address: 0x50060418 - /// digest registers - pub const HR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// H3 - H3: u32, - }), base_address + 0x18); - - /// address: 0x5006041c - /// digest registers - pub const HR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// H4 - H4: u32, - }), base_address + 0x1c); - - /// address: 0x50060420 - /// interrupt enable register - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input interrupt - /// enable - DINIE: u1, - /// Digest calculation completion interrupt - /// enable - DCIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x20); - - /// address: 0x50060424 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input interrupt - /// status - DINIS: u1, - /// Digest calculation completion interrupt - /// status - DCIS: u1, - /// DMA Status - DMAS: u1, - /// Busy bit - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x24); - - /// address: 0x500604f8 - /// context swap registers - pub const CSR0 = @intToPtr(*volatile u32, base_address + 0xf8); - - /// address: 0x500604fc - /// context swap registers - pub const CSR1 = @intToPtr(*volatile u32, base_address + 0xfc); - - /// address: 0x50060500 - /// context swap registers - pub const CSR2 = @intToPtr(*volatile u32, base_address + 0x100); - - /// address: 0x50060504 - /// context swap registers - pub const CSR3 = @intToPtr(*volatile u32, base_address + 0x104); - - /// address: 0x50060508 - /// context swap registers - pub const CSR4 = @intToPtr(*volatile u32, base_address + 0x108); - - /// address: 0x5006050c - /// context swap registers - pub const CSR5 = @intToPtr(*volatile u32, base_address + 0x10c); - - /// address: 0x50060510 - /// context swap registers - pub const CSR6 = @intToPtr(*volatile u32, base_address + 0x110); - - /// address: 0x50060514 - /// context swap registers - pub const CSR7 = @intToPtr(*volatile u32, base_address + 0x114); - - /// address: 0x50060518 - /// context swap registers - pub const CSR8 = @intToPtr(*volatile u32, base_address + 0x118); - - /// address: 0x5006051c - /// context swap registers - pub const CSR9 = @intToPtr(*volatile u32, base_address + 0x11c); - - /// address: 0x50060520 - /// context swap registers - pub const CSR10 = @intToPtr(*volatile u32, base_address + 0x120); - - /// address: 0x50060524 - /// context swap registers - pub const CSR11 = @intToPtr(*volatile u32, base_address + 0x124); - - /// address: 0x50060528 - /// context swap registers - pub const CSR12 = @intToPtr(*volatile u32, base_address + 0x128); - - /// address: 0x5006052c - /// context swap registers - pub const CSR13 = @intToPtr(*volatile u32, base_address + 0x12c); - - /// address: 0x50060530 - /// context swap registers - pub const CSR14 = @intToPtr(*volatile u32, base_address + 0x130); - - /// address: 0x50060534 - /// context swap registers - pub const CSR15 = @intToPtr(*volatile u32, base_address + 0x134); - - /// address: 0x50060538 - /// context swap registers - pub const CSR16 = @intToPtr(*volatile u32, base_address + 0x138); - - /// address: 0x5006053c - /// context swap registers - pub const CSR17 = @intToPtr(*volatile u32, base_address + 0x13c); - - /// address: 0x50060540 - /// context swap registers - pub const CSR18 = @intToPtr(*volatile u32, base_address + 0x140); - - /// address: 0x50060544 - /// context swap registers - pub const CSR19 = @intToPtr(*volatile u32, base_address + 0x144); - - /// address: 0x50060548 - /// context swap registers - pub const CSR20 = @intToPtr(*volatile u32, base_address + 0x148); - - /// address: 0x5006054c - /// context swap registers - pub const CSR21 = @intToPtr(*volatile u32, base_address + 0x14c); - - /// address: 0x50060550 - /// context swap registers - pub const CSR22 = @intToPtr(*volatile u32, base_address + 0x150); - - /// address: 0x50060554 - /// context swap registers - pub const CSR23 = @intToPtr(*volatile u32, base_address + 0x154); - - /// address: 0x50060558 - /// context swap registers - pub const CSR24 = @intToPtr(*volatile u32, base_address + 0x158); - - /// address: 0x5006055c - /// context swap registers - pub const CSR25 = @intToPtr(*volatile u32, base_address + 0x15c); - - /// address: 0x50060560 - /// context swap registers - pub const CSR26 = @intToPtr(*volatile u32, base_address + 0x160); - - /// address: 0x50060564 - /// context swap registers - pub const CSR27 = @intToPtr(*volatile u32, base_address + 0x164); - - /// address: 0x50060568 - /// context swap registers - pub const CSR28 = @intToPtr(*volatile u32, base_address + 0x168); - - /// address: 0x5006056c - /// context swap registers - pub const CSR29 = @intToPtr(*volatile u32, base_address + 0x16c); - - /// address: 0x50060570 - /// context swap registers - pub const CSR30 = @intToPtr(*volatile u32, base_address + 0x170); - - /// address: 0x50060574 - /// context swap registers - pub const CSR31 = @intToPtr(*volatile u32, base_address + 0x174); - - /// address: 0x50060578 - /// context swap registers - pub const CSR32 = @intToPtr(*volatile u32, base_address + 0x178); - - /// address: 0x5006057c - /// context swap registers - pub const CSR33 = @intToPtr(*volatile u32, base_address + 0x17c); - - /// address: 0x50060580 - /// context swap registers - pub const CSR34 = @intToPtr(*volatile u32, base_address + 0x180); - - /// address: 0x50060584 - /// context swap registers - pub const CSR35 = @intToPtr(*volatile u32, base_address + 0x184); - - /// address: 0x50060588 - /// context swap registers - pub const CSR36 = @intToPtr(*volatile u32, base_address + 0x188); - - /// address: 0x5006058c - /// context swap registers - pub const CSR37 = @intToPtr(*volatile u32, base_address + 0x18c); - - /// address: 0x50060590 - /// context swap registers - pub const CSR38 = @intToPtr(*volatile u32, base_address + 0x190); - - /// address: 0x50060594 - /// context swap registers - pub const CSR39 = @intToPtr(*volatile u32, base_address + 0x194); - - /// address: 0x50060598 - /// context swap registers - pub const CSR40 = @intToPtr(*volatile u32, base_address + 0x198); - - /// address: 0x5006059c - /// context swap registers - pub const CSR41 = @intToPtr(*volatile u32, base_address + 0x19c); - - /// address: 0x500605a0 - /// context swap registers - pub const CSR42 = @intToPtr(*volatile u32, base_address + 0x1a0); - - /// address: 0x500605a4 - /// context swap registers - pub const CSR43 = @intToPtr(*volatile u32, base_address + 0x1a4); - - /// address: 0x500605a8 - /// context swap registers - pub const CSR44 = @intToPtr(*volatile u32, base_address + 0x1a8); - - /// address: 0x500605ac - /// context swap registers - pub const CSR45 = @intToPtr(*volatile u32, base_address + 0x1ac); - - /// address: 0x500605b0 - /// context swap registers - pub const CSR46 = @intToPtr(*volatile u32, base_address + 0x1b0); - - /// address: 0x500605b4 - /// context swap registers - pub const CSR47 = @intToPtr(*volatile u32, base_address + 0x1b4); - - /// address: 0x500605b8 - /// context swap registers - pub const CSR48 = @intToPtr(*volatile u32, base_address + 0x1b8); - - /// address: 0x500605bc - /// context swap registers - pub const CSR49 = @intToPtr(*volatile u32, base_address + 0x1bc); - - /// address: 0x500605c0 - /// context swap registers - pub const CSR50 = @intToPtr(*volatile u32, base_address + 0x1c0); - - /// address: 0x500605c4 - /// context swap registers - pub const CSR51 = @intToPtr(*volatile u32, base_address + 0x1c4); - - /// address: 0x500605c8 - /// context swap registers - pub const CSR52 = @intToPtr(*volatile u32, base_address + 0x1c8); - - /// address: 0x500605cc - /// context swap registers - pub const CSR53 = @intToPtr(*volatile u32, base_address + 0x1cc); - - /// address: 0x50060710 - /// HASH digest register - pub const HASH_HR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// H0 - H0: u32, - }), base_address + 0x310); - - /// address: 0x50060714 - /// read-only - pub const HASH_HR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// H1 - H1: u32, - }), base_address + 0x314); - - /// address: 0x50060718 - /// read-only - pub const HASH_HR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// H2 - H2: u32, - }), base_address + 0x318); - - /// address: 0x5006071c - /// read-only - pub const HASH_HR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// H3 - H3: u32, - }), base_address + 0x31c); - - /// address: 0x50060720 - /// read-only - pub const HASH_HR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// H4 - H4: u32, - }), base_address + 0x320); - - /// address: 0x50060724 - /// read-only - pub const HASH_HR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// H5 - H5: u32, - }), base_address + 0x324); - - /// address: 0x50060728 - /// read-only - pub const HASH_HR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// H6 - H6: u32, - }), base_address + 0x328); - - /// address: 0x5006072c - /// read-only - pub const HASH_HR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// H7 - H7: u32, - }), base_address + 0x32c); - }; - - /// Cryptographic processor - pub const CRYP = struct { - pub const base_address = 0x50060000; - - /// address: 0x50060000 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Algorithm direction - ALGODIR: u1, - /// Algorithm mode - ALGOMODE0: u3, - /// Data type selection - DATATYPE: u2, - /// Key size selection (AES mode - /// only) - KEYSIZE: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// FIFO flush - FFLUSH: u1, - /// Cryptographic processor - /// enable - CRYPEN: u1, - /// GCM_CCMPH - GCM_CCMPH: u2, - reserved6: u1, - /// ALGOMODE - ALGOMODE3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x50060004 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO empty - IFEM: u1, - /// Input FIFO not full - IFNF: u1, - /// Output FIFO not empty - OFNE: u1, - /// Output FIFO full - OFFU: u1, - /// Busy bit - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x4); - - /// address: 0x50060008 - /// data input register - pub const DIN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data input - DATAIN: u32, - }), base_address + 0x8); - - /// address: 0x5006000c - /// data output register - pub const DOUT = @intToPtr(*volatile Mmio(32, packed struct { - /// Data output - DATAOUT: u32, - }), base_address + 0xc); - - /// address: 0x50060010 - /// DMA control register - pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA input enable - DIEN: u1, - /// DMA output enable - DOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x10); - - /// address: 0x50060014 - /// interrupt mask set/clear - /// register - pub const IMSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service interrupt - /// mask - INIM: u1, - /// Output FIFO service interrupt - /// mask - OUTIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x50060018 - /// raw interrupt status register - pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service raw interrupt - /// status - INRIS: u1, - /// Output FIFO service raw interrupt - /// status - OUTRIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x18); - - /// address: 0x5006001c - /// masked interrupt status - /// register - pub const MISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input FIFO service masked interrupt - /// status - INMIS: u1, - /// Output FIFO service masked interrupt - /// status - OUTMIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x1c); - - /// address: 0x50060020 - /// key registers - pub const K0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b224 - b224: u1, - /// b225 - b225: u1, - /// b226 - b226: u1, - /// b227 - b227: u1, - /// b228 - b228: u1, - /// b229 - b229: u1, - /// b230 - b230: u1, - /// b231 - b231: u1, - /// b232 - b232: u1, - /// b233 - b233: u1, - /// b234 - b234: u1, - /// b235 - b235: u1, - /// b236 - b236: u1, - /// b237 - b237: u1, - /// b238 - b238: u1, - /// b239 - b239: u1, - /// b240 - b240: u1, - /// b241 - b241: u1, - /// b242 - b242: u1, - /// b243 - b243: u1, - /// b244 - b244: u1, - /// b245 - b245: u1, - /// b246 - b246: u1, - /// b247 - b247: u1, - /// b248 - b248: u1, - /// b249 - b249: u1, - /// b250 - b250: u1, - /// b251 - b251: u1, - /// b252 - b252: u1, - /// b253 - b253: u1, - /// b254 - b254: u1, - /// b255 - b255: u1, - }), base_address + 0x20); - - /// address: 0x50060024 - /// key registers - pub const K0RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b192 - b192: u1, - /// b193 - b193: u1, - /// b194 - b194: u1, - /// b195 - b195: u1, - /// b196 - b196: u1, - /// b197 - b197: u1, - /// b198 - b198: u1, - /// b199 - b199: u1, - /// b200 - b200: u1, - /// b201 - b201: u1, - /// b202 - b202: u1, - /// b203 - b203: u1, - /// b204 - b204: u1, - /// b205 - b205: u1, - /// b206 - b206: u1, - /// b207 - b207: u1, - /// b208 - b208: u1, - /// b209 - b209: u1, - /// b210 - b210: u1, - /// b211 - b211: u1, - /// b212 - b212: u1, - /// b213 - b213: u1, - /// b214 - b214: u1, - /// b215 - b215: u1, - /// b216 - b216: u1, - /// b217 - b217: u1, - /// b218 - b218: u1, - /// b219 - b219: u1, - /// b220 - b220: u1, - /// b221 - b221: u1, - /// b222 - b222: u1, - /// b223 - b223: u1, - }), base_address + 0x24); - - /// address: 0x50060028 - /// key registers - pub const K1LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b160 - b160: u1, - /// b161 - b161: u1, - /// b162 - b162: u1, - /// b163 - b163: u1, - /// b164 - b164: u1, - /// b165 - b165: u1, - /// b166 - b166: u1, - /// b167 - b167: u1, - /// b168 - b168: u1, - /// b169 - b169: u1, - /// b170 - b170: u1, - /// b171 - b171: u1, - /// b172 - b172: u1, - /// b173 - b173: u1, - /// b174 - b174: u1, - /// b175 - b175: u1, - /// b176 - b176: u1, - /// b177 - b177: u1, - /// b178 - b178: u1, - /// b179 - b179: u1, - /// b180 - b180: u1, - /// b181 - b181: u1, - /// b182 - b182: u1, - /// b183 - b183: u1, - /// b184 - b184: u1, - /// b185 - b185: u1, - /// b186 - b186: u1, - /// b187 - b187: u1, - /// b188 - b188: u1, - /// b189 - b189: u1, - /// b190 - b190: u1, - /// b191 - b191: u1, - }), base_address + 0x28); - - /// address: 0x5006002c - /// key registers - pub const K1RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b128 - b128: u1, - /// b129 - b129: u1, - /// b130 - b130: u1, - /// b131 - b131: u1, - /// b132 - b132: u1, - /// b133 - b133: u1, - /// b134 - b134: u1, - /// b135 - b135: u1, - /// b136 - b136: u1, - /// b137 - b137: u1, - /// b138 - b138: u1, - /// b139 - b139: u1, - /// b140 - b140: u1, - /// b141 - b141: u1, - /// b142 - b142: u1, - /// b143 - b143: u1, - /// b144 - b144: u1, - /// b145 - b145: u1, - /// b146 - b146: u1, - /// b147 - b147: u1, - /// b148 - b148: u1, - /// b149 - b149: u1, - /// b150 - b150: u1, - /// b151 - b151: u1, - /// b152 - b152: u1, - /// b153 - b153: u1, - /// b154 - b154: u1, - /// b155 - b155: u1, - /// b156 - b156: u1, - /// b157 - b157: u1, - /// b158 - b158: u1, - /// b159 - b159: u1, - }), base_address + 0x2c); - - /// address: 0x50060030 - /// key registers - pub const K2LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b96 - b96: u1, - /// b97 - b97: u1, - /// b98 - b98: u1, - /// b99 - b99: u1, - /// b100 - b100: u1, - /// b101 - b101: u1, - /// b102 - b102: u1, - /// b103 - b103: u1, - /// b104 - b104: u1, - /// b105 - b105: u1, - /// b106 - b106: u1, - /// b107 - b107: u1, - /// b108 - b108: u1, - /// b109 - b109: u1, - /// b110 - b110: u1, - /// b111 - b111: u1, - /// b112 - b112: u1, - /// b113 - b113: u1, - /// b114 - b114: u1, - /// b115 - b115: u1, - /// b116 - b116: u1, - /// b117 - b117: u1, - /// b118 - b118: u1, - /// b119 - b119: u1, - /// b120 - b120: u1, - /// b121 - b121: u1, - /// b122 - b122: u1, - /// b123 - b123: u1, - /// b124 - b124: u1, - /// b125 - b125: u1, - /// b126 - b126: u1, - /// b127 - b127: u1, - }), base_address + 0x30); - - /// address: 0x50060034 - /// key registers - pub const K2RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b64 - b64: u1, - /// b65 - b65: u1, - /// b66 - b66: u1, - /// b67 - b67: u1, - /// b68 - b68: u1, - /// b69 - b69: u1, - /// b70 - b70: u1, - /// b71 - b71: u1, - /// b72 - b72: u1, - /// b73 - b73: u1, - /// b74 - b74: u1, - /// b75 - b75: u1, - /// b76 - b76: u1, - /// b77 - b77: u1, - /// b78 - b78: u1, - /// b79 - b79: u1, - /// b80 - b80: u1, - /// b81 - b81: u1, - /// b82 - b82: u1, - /// b83 - b83: u1, - /// b84 - b84: u1, - /// b85 - b85: u1, - /// b86 - b86: u1, - /// b87 - b87: u1, - /// b88 - b88: u1, - /// b89 - b89: u1, - /// b90 - b90: u1, - /// b91 - b91: u1, - /// b92 - b92: u1, - /// b93 - b93: u1, - /// b94 - b94: u1, - /// b95 - b95: u1, - }), base_address + 0x34); - - /// address: 0x50060038 - /// key registers - pub const K3LR = @intToPtr(*volatile Mmio(32, packed struct { - /// b32 - b32: u1, - /// b33 - b33: u1, - /// b34 - b34: u1, - /// b35 - b35: u1, - /// b36 - b36: u1, - /// b37 - b37: u1, - /// b38 - b38: u1, - /// b39 - b39: u1, - /// b40 - b40: u1, - /// b41 - b41: u1, - /// b42 - b42: u1, - /// b43 - b43: u1, - /// b44 - b44: u1, - /// b45 - b45: u1, - /// b46 - b46: u1, - /// b47 - b47: u1, - /// b48 - b48: u1, - /// b49 - b49: u1, - /// b50 - b50: u1, - /// b51 - b51: u1, - /// b52 - b52: u1, - /// b53 - b53: u1, - /// b54 - b54: u1, - /// b55 - b55: u1, - /// b56 - b56: u1, - /// b57 - b57: u1, - /// b58 - b58: u1, - /// b59 - b59: u1, - /// b60 - b60: u1, - /// b61 - b61: u1, - /// b62 - b62: u1, - /// b63 - b63: u1, - }), base_address + 0x38); - - /// address: 0x5006003c - /// key registers - pub const K3RR = @intToPtr(*volatile Mmio(32, packed struct { - /// b0 - b0: u1, - /// b1 - b1: u1, - /// b2 - b2: u1, - /// b3 - b3: u1, - /// b4 - b4: u1, - /// b5 - b5: u1, - /// b6 - b6: u1, - /// b7 - b7: u1, - /// b8 - b8: u1, - /// b9 - b9: u1, - /// b10 - b10: u1, - /// b11 - b11: u1, - /// b12 - b12: u1, - /// b13 - b13: u1, - /// b14 - b14: u1, - /// b15 - b15: u1, - /// b16 - b16: u1, - /// b17 - b17: u1, - /// b18 - b18: u1, - /// b19 - b19: u1, - /// b20 - b20: u1, - /// b21 - b21: u1, - /// b22 - b22: u1, - /// b23 - b23: u1, - /// b24 - b24: u1, - /// b25 - b25: u1, - /// b26 - b26: u1, - /// b27 - b27: u1, - /// b28 - b28: u1, - /// b29 - b29: u1, - /// b30 - b30: u1, - /// b31 - b31: u1, - }), base_address + 0x3c); - - /// address: 0x50060040 - /// initialization vector - /// registers - pub const IV0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV31 - IV31: u1, - /// IV30 - IV30: u1, - /// IV29 - IV29: u1, - /// IV28 - IV28: u1, - /// IV27 - IV27: u1, - /// IV26 - IV26: u1, - /// IV25 - IV25: u1, - /// IV24 - IV24: u1, - /// IV23 - IV23: u1, - /// IV22 - IV22: u1, - /// IV21 - IV21: u1, - /// IV20 - IV20: u1, - /// IV19 - IV19: u1, - /// IV18 - IV18: u1, - /// IV17 - IV17: u1, - /// IV16 - IV16: u1, - /// IV15 - IV15: u1, - /// IV14 - IV14: u1, - /// IV13 - IV13: u1, - /// IV12 - IV12: u1, - /// IV11 - IV11: u1, - /// IV10 - IV10: u1, - /// IV9 - IV9: u1, - /// IV8 - IV8: u1, - /// IV7 - IV7: u1, - /// IV6 - IV6: u1, - /// IV5 - IV5: u1, - /// IV4 - IV4: u1, - /// IV3 - IV3: u1, - /// IV2 - IV2: u1, - /// IV1 - IV1: u1, - /// IV0 - IV0: u1, - }), base_address + 0x40); - - /// address: 0x50060044 - /// initialization vector - /// registers - pub const IV0RR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV63 - IV63: u1, - /// IV62 - IV62: u1, - /// IV61 - IV61: u1, - /// IV60 - IV60: u1, - /// IV59 - IV59: u1, - /// IV58 - IV58: u1, - /// IV57 - IV57: u1, - /// IV56 - IV56: u1, - /// IV55 - IV55: u1, - /// IV54 - IV54: u1, - /// IV53 - IV53: u1, - /// IV52 - IV52: u1, - /// IV51 - IV51: u1, - /// IV50 - IV50: u1, - /// IV49 - IV49: u1, - /// IV48 - IV48: u1, - /// IV47 - IV47: u1, - /// IV46 - IV46: u1, - /// IV45 - IV45: u1, - /// IV44 - IV44: u1, - /// IV43 - IV43: u1, - /// IV42 - IV42: u1, - /// IV41 - IV41: u1, - /// IV40 - IV40: u1, - /// IV39 - IV39: u1, - /// IV38 - IV38: u1, - /// IV37 - IV37: u1, - /// IV36 - IV36: u1, - /// IV35 - IV35: u1, - /// IV34 - IV34: u1, - /// IV33 - IV33: u1, - /// IV32 - IV32: u1, - }), base_address + 0x44); - - /// address: 0x50060048 - /// initialization vector - /// registers - pub const IV1LR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV95 - IV95: u1, - /// IV94 - IV94: u1, - /// IV93 - IV93: u1, - /// IV92 - IV92: u1, - /// IV91 - IV91: u1, - /// IV90 - IV90: u1, - /// IV89 - IV89: u1, - /// IV88 - IV88: u1, - /// IV87 - IV87: u1, - /// IV86 - IV86: u1, - /// IV85 - IV85: u1, - /// IV84 - IV84: u1, - /// IV83 - IV83: u1, - /// IV82 - IV82: u1, - /// IV81 - IV81: u1, - /// IV80 - IV80: u1, - /// IV79 - IV79: u1, - /// IV78 - IV78: u1, - /// IV77 - IV77: u1, - /// IV76 - IV76: u1, - /// IV75 - IV75: u1, - /// IV74 - IV74: u1, - /// IV73 - IV73: u1, - /// IV72 - IV72: u1, - /// IV71 - IV71: u1, - /// IV70 - IV70: u1, - /// IV69 - IV69: u1, - /// IV68 - IV68: u1, - /// IV67 - IV67: u1, - /// IV66 - IV66: u1, - /// IV65 - IV65: u1, - /// IV64 - IV64: u1, - }), base_address + 0x48); - - /// address: 0x5006004c - /// initialization vector - /// registers - pub const IV1RR = @intToPtr(*volatile Mmio(32, packed struct { - /// IV127 - IV127: u1, - /// IV126 - IV126: u1, - /// IV125 - IV125: u1, - /// IV124 - IV124: u1, - /// IV123 - IV123: u1, - /// IV122 - IV122: u1, - /// IV121 - IV121: u1, - /// IV120 - IV120: u1, - /// IV119 - IV119: u1, - /// IV118 - IV118: u1, - /// IV117 - IV117: u1, - /// IV116 - IV116: u1, - /// IV115 - IV115: u1, - /// IV114 - IV114: u1, - /// IV113 - IV113: u1, - /// IV112 - IV112: u1, - /// IV111 - IV111: u1, - /// IV110 - IV110: u1, - /// IV109 - IV109: u1, - /// IV108 - IV108: u1, - /// IV107 - IV107: u1, - /// IV106 - IV106: u1, - /// IV105 - IV105: u1, - /// IV104 - IV104: u1, - /// IV103 - IV103: u1, - /// IV102 - IV102: u1, - /// IV101 - IV101: u1, - /// IV100 - IV100: u1, - /// IV99 - IV99: u1, - /// IV98 - IV98: u1, - /// IV97 - IV97: u1, - /// IV96 - IV96: u1, - }), base_address + 0x4c); - - /// address: 0x50060050 - /// context swap register - pub const CSGCMCCM0R = @intToPtr(*volatile u32, base_address + 0x50); - - /// address: 0x50060054 - /// context swap register - pub const CSGCMCCM1R = @intToPtr(*volatile u32, base_address + 0x54); - - /// address: 0x50060058 - /// context swap register - pub const CSGCMCCM2R = @intToPtr(*volatile u32, base_address + 0x58); - - /// address: 0x5006005c - /// context swap register - pub const CSGCMCCM3R = @intToPtr(*volatile u32, base_address + 0x5c); - - /// address: 0x50060060 - /// context swap register - pub const CSGCMCCM4R = @intToPtr(*volatile u32, base_address + 0x60); - - /// address: 0x50060064 - /// context swap register - pub const CSGCMCCM5R = @intToPtr(*volatile u32, base_address + 0x64); - - /// address: 0x50060068 - /// context swap register - pub const CSGCMCCM6R = @intToPtr(*volatile u32, base_address + 0x68); - - /// address: 0x5006006c - /// context swap register - pub const CSGCMCCM7R = @intToPtr(*volatile u32, base_address + 0x6c); - - /// address: 0x50060070 - /// context swap register - pub const CSGCM0R = @intToPtr(*volatile u32, base_address + 0x70); - - /// address: 0x50060074 - /// context swap register - pub const CSGCM1R = @intToPtr(*volatile u32, base_address + 0x74); - - /// address: 0x50060078 - /// context swap register - pub const CSGCM2R = @intToPtr(*volatile u32, base_address + 0x78); - - /// address: 0x5006007c - /// context swap register - pub const CSGCM3R = @intToPtr(*volatile u32, base_address + 0x7c); - - /// address: 0x50060080 - /// context swap register - pub const CSGCM4R = @intToPtr(*volatile u32, base_address + 0x80); - - /// address: 0x50060084 - /// context swap register - pub const CSGCM5R = @intToPtr(*volatile u32, base_address + 0x84); - - /// address: 0x50060088 - /// context swap register - pub const CSGCM6R = @intToPtr(*volatile u32, base_address + 0x88); - - /// address: 0x5006008c - /// context swap register - pub const CSGCM7R = @intToPtr(*volatile u32, base_address + 0x8c); - }; - - /// Digital camera interface - pub const DCMI = struct { - pub const base_address = 0x50050000; - - /// address: 0x50050000 - /// control register 1 - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture enable - CAPTURE: u1, - /// Capture mode - CM: u1, - /// Crop feature - CROP: u1, - /// JPEG format - JPEG: u1, - /// Embedded synchronization - /// select - ESS: u1, - /// Pixel clock polarity - PCKPOL: u1, - /// Horizontal synchronization - /// polarity - HSPOL: u1, - /// Vertical synchronization - /// polarity - VSPOL: u1, - /// Frame capture rate control - FCRC: u2, - /// Extended data mode - EDM: u2, - reserved0: u1, - reserved1: u1, - /// DCMI enable - ENABLE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x0); - - /// address: 0x50050004 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// HSYNC - HSYNC: u1, - /// VSYNC - VSYNC: u1, - /// FIFO not empty - FNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0x50050008 - /// raw interrupt status register - pub const RIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete raw interrupt - /// status - FRAME_RIS: u1, - /// Overrun raw interrupt - /// status - OVR_RIS: u1, - /// Synchronization error raw interrupt - /// status - ERR_RIS: u1, - /// VSYNC raw interrupt status - VSYNC_RIS: u1, - /// Line raw interrupt status - LINE_RIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x8); - - /// address: 0x5005000c - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete interrupt - /// enable - FRAME_IE: u1, - /// Overrun interrupt enable - OVR_IE: u1, - /// Synchronization error interrupt - /// enable - ERR_IE: u1, - /// VSYNC interrupt enable - VSYNC_IE: u1, - /// Line interrupt enable - LINE_IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0xc); - - /// address: 0x50050010 - /// masked interrupt status - /// register - pub const MIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete masked interrupt - /// status - FRAME_MIS: u1, - /// Overrun masked interrupt - /// status - OVR_MIS: u1, - /// Synchronization error masked interrupt - /// status - ERR_MIS: u1, - /// VSYNC masked interrupt - /// status - VSYNC_MIS: u1, - /// Line masked interrupt - /// status - LINE_MIS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x10); - - /// address: 0x50050014 - /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture complete interrupt status - /// clear - FRAME_ISC: u1, - /// Overrun interrupt status - /// clear - OVR_ISC: u1, - /// Synchronization error interrupt status - /// clear - ERR_ISC: u1, - /// Vertical synch interrupt status - /// clear - VSYNC_ISC: u1, - /// line interrupt status - /// clear - LINE_ISC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x14); - - /// address: 0x50050018 - /// embedded synchronization code - /// register - pub const ESCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame start delimiter code - FSC: u8, - /// Line start delimiter code - LSC: u8, - /// Line end delimiter code - LEC: u8, - /// Frame end delimiter code - FEC: u8, - }), base_address + 0x18); - - /// address: 0x5005001c - /// embedded synchronization unmask - /// register - pub const ESUR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame start delimiter - /// unmask - FSU: u8, - /// Line start delimiter - /// unmask - LSU: u8, - /// Line end delimiter unmask - LEU: u8, - /// Frame end delimiter unmask - FEU: u8, - }), base_address + 0x1c); - - /// address: 0x50050020 - /// crop window start - pub const CWSTRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Horizontal offset count - HOFFCNT: u14, - reserved0: u1, - reserved1: u1, - /// Vertical start line count - VST: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x20); - - /// address: 0x50050024 - /// crop window size - pub const CWSIZE = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture count - CAPCNT: u14, - reserved0: u1, - reserved1: u1, - /// Vertical line count - VLINE: u14, - padding0: u1, - padding1: u1, - }), base_address + 0x24); - - /// address: 0x50050028 - /// data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data byte 0 - Byte0: u8, - /// Data byte 1 - Byte1: u8, - /// Data byte 2 - Byte2: u8, - /// Data byte 3 - Byte3: u8, - }), base_address + 0x28); - }; - - /// Flexible memory controller - pub const FMC = struct { - pub const base_address = 0xa0000000; - - /// address: 0xa0000000 - /// SRAM/NOR-Flash chip-select control register - /// 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - reserved1: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// CBURSTRW - CBURSTRW: u1, - /// CCLKEN - CCLKEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x0); - - /// address: 0xa0000004 - /// SRAM/NOR-Flash chip-select timing register - /// 1 - pub const BTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x4); - - /// address: 0xa0000008 - /// SRAM/NOR-Flash chip-select control register - /// 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x8); - - /// address: 0xa000000c - /// SRAM/NOR-Flash chip-select timing register - /// 2 - pub const BTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0xc); - - /// address: 0xa0000010 - /// SRAM/NOR-Flash chip-select control register - /// 3 - pub const BCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x10); - - /// address: 0xa0000014 - /// SRAM/NOR-Flash chip-select timing register - /// 3 - pub const BTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0xa0000018 - /// SRAM/NOR-Flash chip-select control register - /// 4 - pub const BCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MBKEN - MBKEN: u1, - /// MUXEN - MUXEN: u1, - /// MTYP - MTYP: u2, - /// MWID - MWID: u2, - /// FACCEN - FACCEN: u1, - reserved0: u1, - /// BURSTEN - BURSTEN: u1, - /// WAITPOL - WAITPOL: u1, - /// WRAPMOD - WRAPMOD: u1, - /// WAITCFG - WAITCFG: u1, - /// WREN - WREN: u1, - /// WAITEN - WAITEN: u1, - /// EXTMOD - EXTMOD: u1, - /// ASYNCWAIT - ASYNCWAIT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CBURSTRW - CBURSTRW: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x18); - - /// address: 0xa000001c - /// SRAM/NOR-Flash chip-select timing register - /// 4 - pub const BTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - /// BUSTURN - BUSTURN: u4, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x1c); - - /// address: 0xa0000060 - /// PC Card/NAND Flash control register - /// 2 - pub const PCR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x60); - - /// address: 0xa0000064 - /// FIFO status and interrupt register - /// 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x64); - - /// address: 0xa0000068 - /// Common memory space timing register - /// 2 - pub const PMEM2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x68); - - /// address: 0xa000006c - /// Attribute memory space timing register - /// 2 - pub const PATT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x6c); - - /// address: 0xa0000074 - /// ECC result register 2 - pub const ECCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x74); - - /// address: 0xa0000080 - /// PC Card/NAND Flash control register - /// 3 - pub const PCR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x80); - - /// address: 0xa0000084 - /// FIFO status and interrupt register - /// 3 - pub const SR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x84); - - /// address: 0xa0000088 - /// Common memory space timing register - /// 3 - pub const PMEM3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0x88); - - /// address: 0xa000008c - /// Attribute memory space timing register - /// 3 - pub const PATT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0x8c); - - /// address: 0xa0000094 - /// ECC result register 3 - pub const ECCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ECCx - ECCx: u32, - }), base_address + 0x94); - - /// address: 0xa00000a0 - /// PC Card/NAND Flash control register - /// 4 - pub const PCR4 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// PWAITEN - PWAITEN: u1, - /// PBKEN - PBKEN: u1, - /// PTYP - PTYP: u1, - /// PWID - PWID: u2, - /// ECCEN - ECCEN: u1, - reserved1: u1, - reserved2: u1, - /// TCLR - TCLR: u4, - /// TAR - TAR: u4, - /// ECCPS - ECCPS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0xa0); - - /// address: 0xa00000a4 - /// FIFO status and interrupt register - /// 4 - pub const SR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IRS - IRS: u1, - /// ILS - ILS: u1, - /// IFS - IFS: u1, - /// IREN - IREN: u1, - /// ILEN - ILEN: u1, - /// IFEN - IFEN: u1, - /// FEMPT - FEMPT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xa4); - - /// address: 0xa00000a8 - /// Common memory space timing register - /// 4 - pub const PMEM4 = @intToPtr(*volatile Mmio(32, packed struct { - /// MEMSETx - MEMSETx: u8, - /// MEMWAITx - MEMWAITx: u8, - /// MEMHOLDx - MEMHOLDx: u8, - /// MEMHIZx - MEMHIZx: u8, - }), base_address + 0xa8); - - /// address: 0xa00000ac - /// Attribute memory space timing register - /// 4 - pub const PATT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ATTSETx - ATTSETx: u8, - /// ATTWAITx - ATTWAITx: u8, - /// ATTHOLDx - ATTHOLDx: u8, - /// ATTHIZx - ATTHIZx: u8, - }), base_address + 0xac); - - /// address: 0xa00000b0 - /// I/O space timing register 4 - pub const PIO4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IOSETx - IOSETx: u8, - /// IOWAITx - IOWAITx: u8, - /// IOHOLDx - IOHOLDx: u8, - /// IOHIZx - IOHIZx: u8, - }), base_address + 0xb0); - - /// address: 0xa0000104 - /// SRAM/NOR-Flash write timing registers - /// 1 - pub const BWTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x104); - - /// address: 0xa000010c - /// SRAM/NOR-Flash write timing registers - /// 2 - pub const BWTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10c); - - /// address: 0xa0000104 - /// SRAM/NOR-Flash write timing registers - /// 3 - pub const BWTR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x104); - - /// address: 0xa000010c - /// SRAM/NOR-Flash write timing registers - /// 4 - pub const BWTR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// ADDSET - ADDSET: u4, - /// ADDHLD - ADDHLD: u4, - /// DATAST - DATAST: u8, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// CLKDIV - CLKDIV: u4, - /// DATLAT - DATLAT: u4, - /// ACCMOD - ACCMOD: u2, - padding0: u1, - padding1: u1, - }), base_address + 0x10c); - - /// address: 0xa0000140 - /// SDRAM Control Register 1 - pub const SDCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of column address - /// bits - NC: u2, - /// Number of row address bits - NR: u2, - /// Memory data bus width - MWID: u2, - /// Number of internal banks - NB: u1, - /// CAS latency - CAS: u2, - /// Write protection - WP: u1, - /// SDRAM clock configuration - SDCLK: u2, - /// Burst read - RBURST: u1, - /// Read pipe - RPIPE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x140); - - /// address: 0xa0000144 - /// SDRAM Control Register 2 - pub const SDCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of column address - /// bits - NC: u2, - /// Number of row address bits - NR: u2, - /// Memory data bus width - MWID: u2, - /// Number of internal banks - NB: u1, - /// CAS latency - CAS: u2, - /// Write protection - WP: u1, - /// SDRAM clock configuration - SDCLK: u2, - /// Burst read - RBURST: u1, - /// Read pipe - RPIPE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x144); - - /// address: 0xa0000148 - /// SDRAM Timing register 1 - pub const SDTR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Load Mode Register to - /// Active - TMRD: u4, - /// Exit self-refresh delay - TXSR: u4, - /// Self refresh time - TRAS: u4, - /// Row cycle delay - TRC: u4, - /// Recovery delay - TWR: u4, - /// Row precharge delay - TRP: u4, - /// Row to column delay - TRCD: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x148); - - /// address: 0xa000014c - /// SDRAM Timing register 2 - pub const SDTR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Load Mode Register to - /// Active - TMRD: u4, - /// Exit self-refresh delay - TXSR: u4, - /// Self refresh time - TRAS: u4, - /// Row cycle delay - TRC: u4, - /// Recovery delay - TWR: u4, - /// Row precharge delay - TRP: u4, - /// Row to column delay - TRCD: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x14c); - - /// address: 0xa0000150 - /// SDRAM Command Mode register - pub const SDCMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Command mode - MODE: u3, - /// Command target bank 2 - CTB2: u1, - /// Command target bank 1 - CTB1: u1, - /// Number of Auto-refresh - NRFS: u4, - /// Mode Register definition - MRD: u13, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x150); - - /// address: 0xa0000154 - /// SDRAM Refresh Timer register - pub const SDRTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear Refresh error flag - CRE: u1, - /// Refresh Timer Count - COUNT: u13, - /// RES Interrupt Enable - REIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x154); - - /// address: 0xa0000158 - /// SDRAM Status register - pub const SDSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Refresh error flag - RE: u1, - /// Status Mode for Bank 1 - MODES1: u2, - /// Status Mode for Bank 2 - MODES2: u2, - /// Busy status - BUSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x158); - }; - - /// Debug support - pub const DBG = struct { - pub const base_address = 0xe0042000; - - /// address: 0xe0042000 - /// IDCODE - pub const DBGMCU_IDCODE = @intToPtr(*volatile Mmio(32, packed struct { - /// DEV_ID - DEV_ID: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// REV_ID - REV_ID: u16, - }), base_address + 0x0); - - /// address: 0xe0042004 - /// Control Register - pub const DBGMCU_CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG_SLEEP - DBG_SLEEP: u1, - /// DBG_STOP - DBG_STOP: u1, - /// DBG_STANDBY - DBG_STANDBY: u1, - reserved0: u1, - reserved1: u1, - /// TRACE_IOEN - TRACE_IOEN: u1, - /// TRACE_MODE - TRACE_MODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0xe0042008 - /// Debug MCU APB1 Freeze registe - pub const DBGMCU_APB1_FZ = @intToPtr(*volatile Mmio(32, packed struct { - /// DBG_TIM2_STOP - DBG_TIM2_STOP: u1, - /// DBG_TIM3 _STOP - DBG_TIM3_STOP: u1, - /// DBG_TIM4_STOP - DBG_TIM4_STOP: u1, - /// DBG_TIM5_STOP - DBG_TIM5_STOP: u1, - /// DBG_TIM6_STOP - DBG_TIM6_STOP: u1, - /// DBG_TIM7_STOP - DBG_TIM7_STOP: u1, - /// DBG_TIM12_STOP - DBG_TIM12_STOP: u1, - /// DBG_TIM13_STOP - DBG_TIM13_STOP: u1, - /// DBG_TIM14_STOP - DBG_TIM14_STOP: u1, - reserved0: u1, - reserved1: u1, - /// DBG_WWDG_STOP - DBG_WWDG_STOP: u1, - /// DBG_IWDEG_STOP - DBG_IWDEG_STOP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// DBG_J2C1_SMBUS_TIMEOUT - DBG_J2C1_SMBUS_TIMEOUT: u1, - /// DBG_J2C2_SMBUS_TIMEOUT - DBG_J2C2_SMBUS_TIMEOUT: u1, - /// DBG_J2C3SMBUS_TIMEOUT - DBG_J2C3SMBUS_TIMEOUT: u1, - reserved10: u1, - /// DBG_CAN1_STOP - DBG_CAN1_STOP: u1, - /// DBG_CAN2_STOP - DBG_CAN2_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x8); - - /// address: 0xe004200c - /// Debug MCU APB2 Freeze registe - pub const DBGMCU_APB2_FZ = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 counter stopped when core is - /// halted - DBG_TIM1_STOP: u1, - /// TIM8 counter stopped when core is - /// halted - DBG_TIM8_STOP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TIM9 counter stopped when core is - /// halted - DBG_TIM9_STOP: u1, - /// TIM10 counter stopped when core is - /// halted - DBG_TIM10_STOP: u1, - /// TIM11 counter stopped when core is - /// halted - DBG_TIM11_STOP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - }; - - /// DMA controller - pub const DMA2 = struct { - pub const base_address = 0x40026400; - - /// address: 0x40026400 - /// low interrupt status register - pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF0: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF0: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF0: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF0: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF0: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF1: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF1: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF1: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF1: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF2: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF2: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF2: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF2: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF2: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF3: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF3: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF3: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF3: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40026404 - /// high interrupt status register - pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF4: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF4: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF4: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF4: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF4: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF5: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF5: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF5: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF5: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF6: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF6: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF6: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF6: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF6: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF7: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF7: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF7: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF7: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40026408 - /// low interrupt flag clear - /// register - pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF0: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF0: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF0: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF0: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF0: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF1: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF1: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF1: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF1: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF2: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF2: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF2: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF2: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF2: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF3: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF3: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF3: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF3: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4002640c - /// high interrupt flag clear - /// register - pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF4: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF4: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF4: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF4: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF4: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF5: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF5: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF5: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF5: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF6: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF6: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF6: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF6: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF6: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF7: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF7: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF7: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF7: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x40026410 - /// stream x configuration - /// register - pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - reserved0: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x40026414 - /// stream x number of data - /// register - pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40026418 - /// stream x peripheral address - /// register - pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x18); - - /// address: 0x4002641c - /// stream x memory 0 address - /// register - pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x1c); - - /// address: 0x40026420 - /// stream x memory 1 address - /// register - pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x20); - - /// address: 0x40026424 - /// stream x FIFO control register - pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40026428 - /// stream x configuration - /// register - pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x28); - - /// address: 0x4002642c - /// stream x number of data - /// register - pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x40026430 - /// stream x peripheral address - /// register - pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x30); - - /// address: 0x40026434 - /// stream x memory 0 address - /// register - pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x34); - - /// address: 0x40026438 - /// stream x memory 1 address - /// register - pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x38); - - /// address: 0x4002643c - /// stream x FIFO control register - pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x3c); - - /// address: 0x40026440 - /// stream x configuration - /// register - pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x40); - - /// address: 0x40026444 - /// stream x number of data - /// register - pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40026448 - /// stream x peripheral address - /// register - pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x48); - - /// address: 0x4002644c - /// stream x memory 0 address - /// register - pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x4c); - - /// address: 0x40026450 - /// stream x memory 1 address - /// register - pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x50); - - /// address: 0x40026454 - /// stream x FIFO control register - pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40026458 - /// stream x configuration - /// register - pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x58); - - /// address: 0x4002645c - /// stream x number of data - /// register - pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40026460 - /// stream x peripheral address - /// register - pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40026464 - /// stream x memory 0 address - /// register - pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x64); - - /// address: 0x40026468 - /// stream x memory 1 address - /// register - pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x68); - - /// address: 0x4002646c - /// stream x FIFO control register - pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x6c); - - /// address: 0x40026470 - /// stream x configuration - /// register - pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x70); - - /// address: 0x40026474 - /// stream x number of data - /// register - pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x74); - - /// address: 0x40026478 - /// stream x peripheral address - /// register - pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x78); - - /// address: 0x4002647c - /// stream x memory 0 address - /// register - pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x7c); - - /// address: 0x40026480 - /// stream x memory 1 address - /// register - pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x80); - - /// address: 0x40026484 - /// stream x FIFO control register - pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x84); - - /// address: 0x40026488 - /// stream x configuration - /// register - pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4002648c - /// stream x number of data - /// register - pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x40026490 - /// stream x peripheral address - /// register - pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x90); - - /// address: 0x40026494 - /// stream x memory 0 address - /// register - pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x94); - - /// address: 0x40026498 - /// stream x memory 1 address - /// register - pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x98); - - /// address: 0x4002649c - /// stream x FIFO control register - pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x9c); - - /// address: 0x400264a0 - /// stream x configuration - /// register - pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xa0); - - /// address: 0x400264a4 - /// stream x number of data - /// register - pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa4); - - /// address: 0x400264a8 - /// stream x peripheral address - /// register - pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xa8); - - /// address: 0x400264ac - /// stream x memory 0 address - /// register - pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xac); - - /// address: 0x400264b0 - /// stream x memory 1 address - /// register - pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xb0); - - /// address: 0x400264b4 - /// stream x FIFO control register - pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xb4); - - /// address: 0x400264b8 - /// stream x configuration - /// register - pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xb8); - - /// address: 0x400264bc - /// stream x number of data - /// register - pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xbc); - - /// address: 0x400264c0 - /// stream x peripheral address - /// register - pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xc0); - - /// address: 0x400264c4 - /// stream x memory 0 address - /// register - pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xc4); - - /// address: 0x400264c8 - /// stream x memory 1 address - /// register - pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xc8); - - /// address: 0x400264cc - /// stream x FIFO control register - pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xcc); - }; - pub const DMA1 = struct { - pub const base_address = 0x40026000; - - /// address: 0x40026000 - /// low interrupt status register - pub const LISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF0: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF0: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF0: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF0: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF0: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF1: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF1: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF1: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF1: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF2: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF2: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF2: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF2: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF2: u1, - /// Stream x FIFO error interrupt flag - /// (x=3..0) - FEIF3: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=3..0) - DMEIF3: u1, - /// Stream x transfer error interrupt flag - /// (x=3..0) - TEIF3: u1, - /// Stream x half transfer interrupt flag - /// (x=3..0) - HTIF3: u1, - /// Stream x transfer complete interrupt - /// flag (x = 3..0) - TCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40026004 - /// high interrupt status register - pub const HISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF4: u1, - reserved0: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF4: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF4: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF4: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF4: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF5: u1, - reserved1: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF5: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF5: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF5: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF6: u1, - reserved6: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF6: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF6: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF6: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF6: u1, - /// Stream x FIFO error interrupt flag - /// (x=7..4) - FEIF7: u1, - reserved7: u1, - /// Stream x direct mode error interrupt - /// flag (x=7..4) - DMEIF7: u1, - /// Stream x transfer error interrupt flag - /// (x=7..4) - TEIF7: u1, - /// Stream x half transfer interrupt flag - /// (x=7..4) - HTIF7: u1, - /// Stream x transfer complete interrupt - /// flag (x=7..4) - TCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40026008 - /// low interrupt flag clear - /// register - pub const LIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF0: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF0: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF0: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF0: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF0: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF1: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF1: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF1: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF1: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF2: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF2: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF2: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF2: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF2: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 3..0) - CFEIF3: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 3..0) - CDMEIF3: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 3..0) - CTEIF3: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 3..0) - CHTIF3: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 3..0) - CTCIF3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x8); - - /// address: 0x4002600c - /// high interrupt flag clear - /// register - pub const HIFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF4: u1, - reserved0: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF4: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF4: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF4: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF4: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF5: u1, - reserved1: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF5: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF5: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF5: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF5: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF6: u1, - reserved6: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF6: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF6: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF6: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF6: u1, - /// Stream x clear FIFO error interrupt flag - /// (x = 7..4) - CFEIF7: u1, - reserved7: u1, - /// Stream x clear direct mode error - /// interrupt flag (x = 7..4) - CDMEIF7: u1, - /// Stream x clear transfer error interrupt - /// flag (x = 7..4) - CTEIF7: u1, - /// Stream x clear half transfer interrupt - /// flag (x = 7..4) - CHTIF7: u1, - /// Stream x clear transfer complete - /// interrupt flag (x = 7..4) - CTCIF7: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xc); - - /// address: 0x40026010 - /// stream x configuration - /// register - pub const S0CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - reserved0: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x10); - - /// address: 0x40026014 - /// stream x number of data - /// register - pub const S0NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40026018 - /// stream x peripheral address - /// register - pub const S0PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x18); - - /// address: 0x4002601c - /// stream x memory 0 address - /// register - pub const S0M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x1c); - - /// address: 0x40026020 - /// stream x memory 1 address - /// register - pub const S0M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x20); - - /// address: 0x40026024 - /// stream x FIFO control register - pub const S0FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40026028 - /// stream x configuration - /// register - pub const S1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x28); - - /// address: 0x4002602c - /// stream x number of data - /// register - pub const S1NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x2c); - - /// address: 0x40026030 - /// stream x peripheral address - /// register - pub const S1PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x30); - - /// address: 0x40026034 - /// stream x memory 0 address - /// register - pub const S1M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x34); - - /// address: 0x40026038 - /// stream x memory 1 address - /// register - pub const S1M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x38); - - /// address: 0x4002603c - /// stream x FIFO control register - pub const S1FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x3c); - - /// address: 0x40026040 - /// stream x configuration - /// register - pub const S2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x40); - - /// address: 0x40026044 - /// stream x number of data - /// register - pub const S2NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40026048 - /// stream x peripheral address - /// register - pub const S2PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x48); - - /// address: 0x4002604c - /// stream x memory 0 address - /// register - pub const S2M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x4c); - - /// address: 0x40026050 - /// stream x memory 1 address - /// register - pub const S2M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x50); - - /// address: 0x40026054 - /// stream x FIFO control register - pub const S2FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40026058 - /// stream x configuration - /// register - pub const S3CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x58); - - /// address: 0x4002605c - /// stream x number of data - /// register - pub const S3NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x5c); - - /// address: 0x40026060 - /// stream x peripheral address - /// register - pub const S3PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x60); - - /// address: 0x40026064 - /// stream x memory 0 address - /// register - pub const S3M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x64); - - /// address: 0x40026068 - /// stream x memory 1 address - /// register - pub const S3M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x68); - - /// address: 0x4002606c - /// stream x FIFO control register - pub const S3FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x6c); - - /// address: 0x40026070 - /// stream x configuration - /// register - pub const S4CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x70); - - /// address: 0x40026074 - /// stream x number of data - /// register - pub const S4NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x74); - - /// address: 0x40026078 - /// stream x peripheral address - /// register - pub const S4PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x78); - - /// address: 0x4002607c - /// stream x memory 0 address - /// register - pub const S4M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x7c); - - /// address: 0x40026080 - /// stream x memory 1 address - /// register - pub const S4M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x80); - - /// address: 0x40026084 - /// stream x FIFO control register - pub const S4FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x84); - - /// address: 0x40026088 - /// stream x configuration - /// register - pub const S5CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4002608c - /// stream x number of data - /// register - pub const S5NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8c); - - /// address: 0x40026090 - /// stream x peripheral address - /// register - pub const S5PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0x90); - - /// address: 0x40026094 - /// stream x memory 0 address - /// register - pub const S5M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0x94); - - /// address: 0x40026098 - /// stream x memory 1 address - /// register - pub const S5M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0x98); - - /// address: 0x4002609c - /// stream x FIFO control register - pub const S5FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x9c); - - /// address: 0x400260a0 - /// stream x configuration - /// register - pub const S6CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xa0); - - /// address: 0x400260a4 - /// stream x number of data - /// register - pub const S6NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xa4); - - /// address: 0x400260a8 - /// stream x peripheral address - /// register - pub const S6PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xa8); - - /// address: 0x400260ac - /// stream x memory 0 address - /// register - pub const S6M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xac); - - /// address: 0x400260b0 - /// stream x memory 1 address - /// register - pub const S6M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xb0); - - /// address: 0x400260b4 - /// stream x FIFO control register - pub const S6FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xb4); - - /// address: 0x400260b8 - /// stream x configuration - /// register - pub const S7CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stream enable / flag stream ready when - /// read low - EN: u1, - /// Direct mode error interrupt - /// enable - DMEIE: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Half transfer interrupt - /// enable - HTIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Peripheral flow controller - PFCTRL: u1, - /// Data transfer direction - DIR: u2, - /// Circular mode - CIRC: u1, - /// Peripheral increment mode - PINC: u1, - /// Memory increment mode - MINC: u1, - /// Peripheral data size - PSIZE: u2, - /// Memory data size - MSIZE: u2, - /// Peripheral increment offset - /// size - PINCOS: u1, - /// Priority level - PL: u2, - /// Double buffer mode - DBM: u1, - /// Current target (only in double buffer - /// mode) - CT: u1, - /// ACK - ACK: u1, - /// Peripheral burst transfer - /// configuration - PBURST: u2, - /// Memory burst transfer - /// configuration - MBURST: u2, - /// Channel selection - CHSEL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0xb8); - - /// address: 0x400260bc - /// stream x number of data - /// register - pub const S7NDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of data items to - /// transfer - NDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xbc); - - /// address: 0x400260c0 - /// stream x peripheral address - /// register - pub const S7PAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral address - PA: u32, - }), base_address + 0xc0); - - /// address: 0x400260c4 - /// stream x memory 0 address - /// register - pub const S7M0AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 0 address - M0A: u32, - }), base_address + 0xc4); - - /// address: 0x400260c8 - /// stream x memory 1 address - /// register - pub const S7M1AR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory 1 address (used in case of Double - /// buffer mode) - M1A: u32, - }), base_address + 0xc8); - - /// address: 0x400260cc - /// stream x FIFO control register - pub const S7FCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold selection - FTH: u2, - /// Direct mode disable - DMDIS: u1, - /// FIFO status - FS: u3, - reserved0: u1, - /// FIFO error interrupt - /// enable - FEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xcc); - }; - - /// Reset and clock control - pub const RCC = struct { - pub const base_address = 0x40023800; - - /// address: 0x40023800 - /// clock control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal high-speed clock - /// enable - HSION: u1, - /// Internal high-speed clock ready - /// flag - HSIRDY: u1, - reserved0: u1, - /// Internal high-speed clock - /// trimming - HSITRIM: u5, - /// Internal high-speed clock - /// calibration - HSICAL: u8, - /// HSE clock enable - HSEON: u1, - /// HSE clock ready flag - HSERDY: u1, - /// HSE clock bypass - HSEBYP: u1, - /// Clock security system - /// enable - CSSON: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Main PLL (PLL) enable - PLLON: u1, - /// Main PLL (PLL) clock ready - /// flag - PLLRDY: u1, - /// PLLI2S enable - PLLI2SON: u1, - /// PLLI2S clock ready flag - PLLI2SRDY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x0); - - /// address: 0x40023804 - /// PLL configuration register - pub const PLLCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM0: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM1: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM2: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM3: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM4: u1, - /// Division factor for the main PLL (PLL) - /// and audio PLL (PLLI2S) input clock - PLLM5: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN0: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN1: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN2: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN3: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN4: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN5: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN6: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN7: u1, - /// Main PLL (PLL) multiplication factor for - /// VCO - PLLN8: u1, - reserved0: u1, - /// Main PLL (PLL) division factor for main - /// system clock - PLLP0: u1, - /// Main PLL (PLL) division factor for main - /// system clock - PLLP1: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Main PLL(PLL) and audio PLL (PLLI2S) - /// entry clock source - PLLSRC: u1, - reserved5: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ0: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ1: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ2: u1, - /// Main PLL (PLL) division factor for USB - /// OTG FS, SDIO and random number generator - /// clocks - PLLQ3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x4); - - /// address: 0x40023808 - /// clock configuration register - pub const CFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// System clock switch - SW0: u1, - /// System clock switch - SW1: u1, - /// System clock switch status - SWS0: u1, - /// System clock switch status - SWS1: u1, - /// AHB prescaler - HPRE: u4, - reserved0: u1, - reserved1: u1, - /// APB Low speed prescaler - /// (APB1) - PPRE1: u3, - /// APB high-speed prescaler - /// (APB2) - PPRE2: u3, - /// HSE division factor for RTC - /// clock - RTCPRE: u5, - /// Microcontroller clock output - /// 1 - MCO1: u2, - /// I2S clock selection - I2SSRC: u1, - /// MCO1 prescaler - MCO1PRE: u3, - /// MCO2 prescaler - MCO2PRE: u3, - /// Microcontroller clock output - /// 2 - MCO2: u2, - }), base_address + 0x8); - - /// address: 0x4002380c - /// clock interrupt register - pub const CIR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSI ready interrupt flag - LSIRDYF: u1, - /// LSE ready interrupt flag - LSERDYF: u1, - /// HSI ready interrupt flag - HSIRDYF: u1, - /// HSE ready interrupt flag - HSERDYF: u1, - /// Main PLL (PLL) ready interrupt - /// flag - PLLRDYF: u1, - /// PLLI2S ready interrupt - /// flag - PLLI2SRDYF: u1, - reserved0: u1, - /// Clock security system interrupt - /// flag - CSSF: u1, - /// LSI ready interrupt enable - LSIRDYIE: u1, - /// LSE ready interrupt enable - LSERDYIE: u1, - /// HSI ready interrupt enable - HSIRDYIE: u1, - /// HSE ready interrupt enable - HSERDYIE: u1, - /// Main PLL (PLL) ready interrupt - /// enable - PLLRDYIE: u1, - /// PLLI2S ready interrupt - /// enable - PLLI2SRDYIE: u1, - reserved1: u1, - reserved2: u1, - /// LSI ready interrupt clear - LSIRDYC: u1, - /// LSE ready interrupt clear - LSERDYC: u1, - /// HSI ready interrupt clear - HSIRDYC: u1, - /// HSE ready interrupt clear - HSERDYC: u1, - /// Main PLL(PLL) ready interrupt - /// clear - PLLRDYC: u1, - /// PLLI2S ready interrupt - /// clear - PLLI2SRDYC: u1, - reserved3: u1, - /// Clock security system interrupt - /// clear - CSSC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0xc); - - /// address: 0x40023810 - /// AHB1 peripheral reset register - pub const AHB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A reset - GPIOARST: u1, - /// IO port B reset - GPIOBRST: u1, - /// IO port C reset - GPIOCRST: u1, - /// IO port D reset - GPIODRST: u1, - /// IO port E reset - GPIOERST: u1, - /// IO port F reset - GPIOFRST: u1, - /// IO port G reset - GPIOGRST: u1, - /// IO port H reset - GPIOHRST: u1, - /// IO port I reset - GPIOIRST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC reset - CRCRST: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// DMA2 reset - DMA1RST: u1, - /// DMA2 reset - DMA2RST: u1, - reserved11: u1, - reserved12: u1, - /// Ethernet MAC reset - ETHMACRST: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// USB OTG HS module reset - OTGHSRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x10); - - /// address: 0x40023814 - /// AHB2 peripheral reset register - pub const AHB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface reset - DCMIRST: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Cryptographic module reset - CRYPRST: u1, - /// Hash module reset - HSAHRST: u1, - /// Random number generator module - /// reset - RNGRST: u1, - /// USB OTG FS module reset - OTGFSRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40023818 - /// AHB3 peripheral reset register - pub const AHB3RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible memory controller module - /// reset - FMCRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x18); - - /// address: 0x40023820 - /// APB1 peripheral reset register - pub const APB1RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 reset - TIM2RST: u1, - /// TIM3 reset - TIM3RST: u1, - /// TIM4 reset - TIM4RST: u1, - /// TIM5 reset - TIM5RST: u1, - /// TIM6 reset - TIM6RST: u1, - /// TIM7 reset - TIM7RST: u1, - /// TIM12 reset - TIM12RST: u1, - /// TIM13 reset - TIM13RST: u1, - /// TIM14 reset - TIM14RST: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog reset - WWDGRST: u1, - reserved2: u1, - reserved3: u1, - /// SPI 2 reset - SPI2RST: u1, - /// SPI 3 reset - SPI3RST: u1, - reserved4: u1, - /// USART 2 reset - UART2RST: u1, - /// USART 3 reset - UART3RST: u1, - /// USART 4 reset - UART4RST: u1, - /// USART 5 reset - UART5RST: u1, - /// I2C 1 reset - I2C1RST: u1, - /// I2C 2 reset - I2C2RST: u1, - /// I2C3 reset - I2C3RST: u1, - reserved5: u1, - /// CAN1 reset - CAN1RST: u1, - /// CAN2 reset - CAN2RST: u1, - reserved6: u1, - /// Power interface reset - PWRRST: u1, - /// DAC reset - DACRST: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x20); - - /// address: 0x40023824 - /// APB2 peripheral reset register - pub const APB2RSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 reset - TIM1RST: u1, - /// TIM8 reset - TIM8RST: u1, - reserved0: u1, - reserved1: u1, - /// USART1 reset - USART1RST: u1, - /// USART6 reset - USART6RST: u1, - reserved2: u1, - reserved3: u1, - /// ADC interface reset (common to all - /// ADCs) - ADCRST: u1, - reserved4: u1, - reserved5: u1, - /// SDIO reset - SDIORST: u1, - /// SPI 1 reset - SPI1RST: u1, - reserved6: u1, - /// System configuration controller - /// reset - SYSCFGRST: u1, - reserved7: u1, - /// TIM9 reset - TIM9RST: u1, - /// TIM10 reset - TIM10RST: u1, - /// TIM11 reset - TIM11RST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x24); - - /// address: 0x40023830 - /// AHB1 peripheral clock register - pub const AHB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A clock enable - GPIOAEN: u1, - /// IO port B clock enable - GPIOBEN: u1, - /// IO port C clock enable - GPIOCEN: u1, - /// IO port D clock enable - GPIODEN: u1, - /// IO port E clock enable - GPIOEEN: u1, - /// IO port F clock enable - GPIOFEN: u1, - /// IO port G clock enable - GPIOGEN: u1, - /// IO port H clock enable - GPIOHEN: u1, - /// IO port I clock enable - GPIOIEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC clock enable - CRCEN: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Backup SRAM interface clock - /// enable - BKPSRAMEN: u1, - reserved8: u1, - /// CCM data RAM clock enable - CCMDATARAMEN: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// DMA2 clock enable - DMA2EN: u1, - reserved9: u1, - reserved10: u1, - /// Ethernet MAC clock enable - ETHMACEN: u1, - /// Ethernet Transmission clock - /// enable - ETHMACTXEN: u1, - /// Ethernet Reception clock - /// enable - ETHMACRXEN: u1, - /// Ethernet PTP clock enable - ETHMACPTPEN: u1, - /// USB OTG HS clock enable - OTGHSEN: u1, - /// USB OTG HSULPI clock - /// enable - OTGHSULPIEN: u1, - padding0: u1, - }), base_address + 0x30); - - /// address: 0x40023834 - /// AHB2 peripheral clock enable - /// register - pub const AHB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface enable - DCMIEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Cryptographic modules clock - /// enable - CRYPEN: u1, - /// Hash modules clock enable - HASHEN: u1, - /// Random number generator clock - /// enable - RNGEN: u1, - /// USB OTG FS clock enable - OTGFSEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x34); - - /// address: 0x40023838 - /// AHB3 peripheral clock enable - /// register - pub const AHB3ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible memory controller module clock - /// enable - FMCEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x38); - - /// address: 0x40023840 - /// APB1 peripheral clock enable - /// register - pub const APB1ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 clock enable - TIM2EN: u1, - /// TIM3 clock enable - TIM3EN: u1, - /// TIM4 clock enable - TIM4EN: u1, - /// TIM5 clock enable - TIM5EN: u1, - /// TIM6 clock enable - TIM6EN: u1, - /// TIM7 clock enable - TIM7EN: u1, - /// TIM12 clock enable - TIM12EN: u1, - /// TIM13 clock enable - TIM13EN: u1, - /// TIM14 clock enable - TIM14EN: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog clock - /// enable - WWDGEN: u1, - reserved2: u1, - reserved3: u1, - /// SPI2 clock enable - SPI2EN: u1, - /// SPI3 clock enable - SPI3EN: u1, - reserved4: u1, - /// USART 2 clock enable - USART2EN: u1, - /// USART3 clock enable - USART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// UART5 clock enable - UART5EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - /// I2C2 clock enable - I2C2EN: u1, - /// I2C3 clock enable - I2C3EN: u1, - reserved5: u1, - /// CAN 1 clock enable - CAN1EN: u1, - /// CAN 2 clock enable - CAN2EN: u1, - reserved6: u1, - /// Power interface clock - /// enable - PWREN: u1, - /// DAC interface clock enable - DACEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x40); - - /// address: 0x40023844 - /// APB2 peripheral clock enable - /// register - pub const APB2ENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 clock enable - TIM1EN: u1, - /// TIM8 clock enable - TIM8EN: u1, - reserved0: u1, - reserved1: u1, - /// USART1 clock enable - USART1EN: u1, - /// USART6 clock enable - USART6EN: u1, - reserved2: u1, - reserved3: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// ADC2 clock enable - ADC2EN: u1, - /// ADC3 clock enable - ADC3EN: u1, - /// SDIO clock enable - SDIOEN: u1, - /// SPI1 clock enable - SPI1EN: u1, - reserved4: u1, - /// System configuration controller clock - /// enable - SYSCFGEN: u1, - reserved5: u1, - /// TIM9 clock enable - TIM9EN: u1, - /// TIM10 clock enable - TIM10EN: u1, - /// TIM11 clock enable - TIM11EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x44); - - /// address: 0x40023850 - /// AHB1 peripheral clock enable in low power - /// mode register - pub const AHB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// IO port A clock enable during sleep - /// mode - GPIOALPEN: u1, - /// IO port B clock enable during Sleep - /// mode - GPIOBLPEN: u1, - /// IO port C clock enable during Sleep - /// mode - GPIOCLPEN: u1, - /// IO port D clock enable during Sleep - /// mode - GPIODLPEN: u1, - /// IO port E clock enable during Sleep - /// mode - GPIOELPEN: u1, - /// IO port F clock enable during Sleep - /// mode - GPIOFLPEN: u1, - /// IO port G clock enable during Sleep - /// mode - GPIOGLPEN: u1, - /// IO port H clock enable during Sleep - /// mode - GPIOHLPEN: u1, - /// IO port I clock enable during Sleep - /// mode - GPIOILPEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// CRC clock enable during Sleep - /// mode - CRCLPEN: u1, - reserved3: u1, - reserved4: u1, - /// Flash interface clock enable during - /// Sleep mode - FLITFLPEN: u1, - /// SRAM 1interface clock enable during - /// Sleep mode - SRAM1LPEN: u1, - /// SRAM 2 interface clock enable during - /// Sleep mode - SRAM2LPEN: u1, - /// Backup SRAM interface clock enable - /// during Sleep mode - BKPSRAMLPEN: u1, - reserved5: u1, - reserved6: u1, - /// DMA1 clock enable during Sleep - /// mode - DMA1LPEN: u1, - /// DMA2 clock enable during Sleep - /// mode - DMA2LPEN: u1, - reserved7: u1, - reserved8: u1, - /// Ethernet MAC clock enable during Sleep - /// mode - ETHMACLPEN: u1, - /// Ethernet transmission clock enable - /// during Sleep mode - ETHMACTXLPEN: u1, - /// Ethernet reception clock enable during - /// Sleep mode - ETHMACRXLPEN: u1, - /// Ethernet PTP clock enable during Sleep - /// mode - ETHMACPTPLPEN: u1, - /// USB OTG HS clock enable during Sleep - /// mode - OTGHSLPEN: u1, - /// USB OTG HS ULPI clock enable during - /// Sleep mode - OTGHSULPILPEN: u1, - padding0: u1, - }), base_address + 0x50); - - /// address: 0x40023854 - /// AHB2 peripheral clock enable in low power - /// mode register - pub const AHB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Camera interface enable during Sleep - /// mode - DCMILPEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Cryptography modules clock enable during - /// Sleep mode - CRYPLPEN: u1, - /// Hash modules clock enable during Sleep - /// mode - HASHLPEN: u1, - /// Random number generator clock enable - /// during Sleep mode - RNGLPEN: u1, - /// USB OTG FS clock enable during Sleep - /// mode - OTGFSLPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x54); - - /// address: 0x40023858 - /// AHB3 peripheral clock enable in low power - /// mode register - pub const AHB3LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// Flexible memory controller module clock - /// enable during Sleep mode - FMCLPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x58); - - /// address: 0x40023860 - /// APB1 peripheral clock enable in low power - /// mode register - pub const APB1LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM2 clock enable during Sleep - /// mode - TIM2LPEN: u1, - /// TIM3 clock enable during Sleep - /// mode - TIM3LPEN: u1, - /// TIM4 clock enable during Sleep - /// mode - TIM4LPEN: u1, - /// TIM5 clock enable during Sleep - /// mode - TIM5LPEN: u1, - /// TIM6 clock enable during Sleep - /// mode - TIM6LPEN: u1, - /// TIM7 clock enable during Sleep - /// mode - TIM7LPEN: u1, - /// TIM12 clock enable during Sleep - /// mode - TIM12LPEN: u1, - /// TIM13 clock enable during Sleep - /// mode - TIM13LPEN: u1, - /// TIM14 clock enable during Sleep - /// mode - TIM14LPEN: u1, - reserved0: u1, - reserved1: u1, - /// Window watchdog clock enable during - /// Sleep mode - WWDGLPEN: u1, - reserved2: u1, - reserved3: u1, - /// SPI2 clock enable during Sleep - /// mode - SPI2LPEN: u1, - /// SPI3 clock enable during Sleep - /// mode - SPI3LPEN: u1, - reserved4: u1, - /// USART2 clock enable during Sleep - /// mode - USART2LPEN: u1, - /// USART3 clock enable during Sleep - /// mode - USART3LPEN: u1, - /// UART4 clock enable during Sleep - /// mode - UART4LPEN: u1, - /// UART5 clock enable during Sleep - /// mode - UART5LPEN: u1, - /// I2C1 clock enable during Sleep - /// mode - I2C1LPEN: u1, - /// I2C2 clock enable during Sleep - /// mode - I2C2LPEN: u1, - /// I2C3 clock enable during Sleep - /// mode - I2C3LPEN: u1, - reserved5: u1, - /// CAN 1 clock enable during Sleep - /// mode - CAN1LPEN: u1, - /// CAN 2 clock enable during Sleep - /// mode - CAN2LPEN: u1, - reserved6: u1, - /// Power interface clock enable during - /// Sleep mode - PWRLPEN: u1, - /// DAC interface clock enable during Sleep - /// mode - DACLPEN: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x60); - - /// address: 0x40023864 - /// APB2 peripheral clock enabled in low power - /// mode register - pub const APB2LPENR = @intToPtr(*volatile Mmio(32, packed struct { - /// TIM1 clock enable during Sleep - /// mode - TIM1LPEN: u1, - /// TIM8 clock enable during Sleep - /// mode - TIM8LPEN: u1, - reserved0: u1, - reserved1: u1, - /// USART1 clock enable during Sleep - /// mode - USART1LPEN: u1, - /// USART6 clock enable during Sleep - /// mode - USART6LPEN: u1, - reserved2: u1, - reserved3: u1, - /// ADC1 clock enable during Sleep - /// mode - ADC1LPEN: u1, - /// ADC2 clock enable during Sleep - /// mode - ADC2LPEN: u1, - /// ADC 3 clock enable during Sleep - /// mode - ADC3LPEN: u1, - /// SDIO clock enable during Sleep - /// mode - SDIOLPEN: u1, - /// SPI 1 clock enable during Sleep - /// mode - SPI1LPEN: u1, - reserved4: u1, - /// System configuration controller clock - /// enable during Sleep mode - SYSCFGLPEN: u1, - reserved5: u1, - /// TIM9 clock enable during sleep - /// mode - TIM9LPEN: u1, - /// TIM10 clock enable during Sleep - /// mode - TIM10LPEN: u1, - /// TIM11 clock enable during Sleep - /// mode - TIM11LPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x64); - - /// address: 0x40023870 - /// Backup domain control register - pub const BDCR = @intToPtr(*volatile Mmio(32, packed struct { - /// External low-speed oscillator - /// enable - LSEON: u1, - /// External low-speed oscillator - /// ready - LSERDY: u1, - /// External low-speed oscillator - /// bypass - LSEBYP: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RTC clock source selection - RTCSEL0: u1, - /// RTC clock source selection - RTCSEL1: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// RTC clock enable - RTCEN: u1, - /// Backup domain software - /// reset - BDRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x70); - - /// address: 0x40023874 - /// clock control & status - /// register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Internal low-speed oscillator - /// enable - LSION: u1, - /// Internal low-speed oscillator - /// ready - LSIRDY: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - /// Remove reset flag - RMVF: u1, - /// BOR reset flag - BORRSTF: u1, - /// PIN reset flag - PADRSTF: u1, - /// POR/PDR reset flag - PORRSTF: u1, - /// Software reset flag - SFTRSTF: u1, - /// Independent watchdog reset - /// flag - WDGRSTF: u1, - /// Window watchdog reset flag - WWDGRSTF: u1, - /// Low-power reset flag - LPWRRSTF: u1, - }), base_address + 0x74); - - /// address: 0x40023880 - /// spread spectrum clock generation - /// register - pub const SSCGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Modulation period - MODPER: u13, - /// Incrementation step - INCSTEP: u15, - reserved0: u1, - reserved1: u1, - /// Spread Select - SPREADSEL: u1, - /// Spread spectrum modulation - /// enable - SSCGEN: u1, - }), base_address + 0x80); - - /// address: 0x40023884 - /// PLLI2S configuration register - pub const PLLI2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// PLLI2S multiplication factor for - /// VCO - PLLI2SN: u9, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// PLLI2S division factor for SAI1 - /// clock - PLLI2SQ: u4, - /// PLLI2S division factor for I2S - /// clocks - PLLI2SR: u3, - padding0: u1, - }), base_address + 0x84); - - /// address: 0x4002388c - /// RCC Dedicated Clock Configuration - /// Register - pub const DCKCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// PLLI2S division factor for SAI1 - /// clock - PLLI2SDIVQ: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// PLLSAI division factor for SAI1 - /// clock - PLLSAIDIVQ: u5, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// division factor for - /// LCD_CLK - PLLSAIDIVR: u2, - reserved6: u1, - reserved7: u1, - /// SAI1-A clock source - /// selection - SAI1ASRC: u2, - /// SAI1-B clock source - /// selection - SAI1BSRC: u2, - /// Timers clocks prescalers - /// selection - TIMPRE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x8c); - - /// address: 0x40023888 - /// RCC PLL configuration register - pub const PLLSAICFGR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// PLLSAI division factor for - /// VCO - PLLSAIN: u9, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// PLLSAI division factor for SAI1 - /// clock - PLLSAIQ: u4, - /// PLLSAI division factor for LCD - /// clock - PLLSAIR: u3, - padding0: u1, - }), base_address + 0x88); - }; - - /// General-purpose I/Os - pub const GPIOK = struct { - pub const base_address = 0x40022800; - - /// address: 0x40022800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002280c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002281c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOJ = struct { - pub const base_address = 0x40022400; - - /// address: 0x40022400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002240c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002241c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOI = struct { - pub const base_address = 0x40022000; - - /// address: 0x40022000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40022004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40022008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002200c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40022010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40022014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40022018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002201c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40022020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40022024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOH = struct { - pub const base_address = 0x40021c00; - - /// address: 0x40021c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x40021c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x40021c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOG = struct { - pub const base_address = 0x40021800; - - /// address: 0x40021800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002180c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002181c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOF = struct { - pub const base_address = 0x40021400; - - /// address: 0x40021400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002140c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002141c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOE = struct { - pub const base_address = 0x40021000; - - /// address: 0x40021000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40021004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40021008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002100c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40021010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40021014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40021018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002101c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40021020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40021024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOD = struct { - pub const base_address = 0x40020c00; - - /// address: 0x40020c00 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020c04 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020c08 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x40020c0c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020c10 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020c14 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020c18 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x40020c1c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020c20 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020c24 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - pub const GPIOC = struct { - pub const base_address = 0x40020800; - - /// address: 0x40020800 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020804 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020808 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002080c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020810 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020814 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020818 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002081c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020820 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020824 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// General-purpose I/Os - pub const GPIOB = struct { - pub const base_address = 0x40020400; - - /// address: 0x40020400 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020404 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020408 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002040c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020410 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020414 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020418 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002041c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020420 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020424 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// General-purpose I/Os - pub const GPIOA = struct { - pub const base_address = 0x40020000; - - /// address: 0x40020000 - /// GPIO port mode register - pub const MODER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - MODER0: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER1: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER2: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER3: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER4: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER5: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER6: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER7: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER8: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER9: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER10: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER11: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER12: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER13: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER14: u2, - /// Port x configuration bits (y = - /// 0..15) - MODER15: u2, - }), base_address + 0x0); - - /// address: 0x40020004 - /// GPIO port output type register - pub const OTYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OT0: u1, - /// Port x configuration bits (y = - /// 0..15) - OT1: u1, - /// Port x configuration bits (y = - /// 0..15) - OT2: u1, - /// Port x configuration bits (y = - /// 0..15) - OT3: u1, - /// Port x configuration bits (y = - /// 0..15) - OT4: u1, - /// Port x configuration bits (y = - /// 0..15) - OT5: u1, - /// Port x configuration bits (y = - /// 0..15) - OT6: u1, - /// Port x configuration bits (y = - /// 0..15) - OT7: u1, - /// Port x configuration bits (y = - /// 0..15) - OT8: u1, - /// Port x configuration bits (y = - /// 0..15) - OT9: u1, - /// Port x configuration bits (y = - /// 0..15) - OT10: u1, - /// Port x configuration bits (y = - /// 0..15) - OT11: u1, - /// Port x configuration bits (y = - /// 0..15) - OT12: u1, - /// Port x configuration bits (y = - /// 0..15) - OT13: u1, - /// Port x configuration bits (y = - /// 0..15) - OT14: u1, - /// Port x configuration bits (y = - /// 0..15) - OT15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40020008 - /// GPIO port output speed - /// register - pub const OSPEEDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - OSPEEDR15: u2, - }), base_address + 0x8); - - /// address: 0x4002000c - /// GPIO port pull-up/pull-down - /// register - pub const PUPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x configuration bits (y = - /// 0..15) - PUPDR0: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR1: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR2: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR3: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR4: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR5: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR6: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR7: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR8: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR9: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR10: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR11: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR12: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR13: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR14: u2, - /// Port x configuration bits (y = - /// 0..15) - PUPDR15: u2, - }), base_address + 0xc); - - /// address: 0x40020010 - /// GPIO port input data register - pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port input data (y = - /// 0..15) - IDR0: u1, - /// Port input data (y = - /// 0..15) - IDR1: u1, - /// Port input data (y = - /// 0..15) - IDR2: u1, - /// Port input data (y = - /// 0..15) - IDR3: u1, - /// Port input data (y = - /// 0..15) - IDR4: u1, - /// Port input data (y = - /// 0..15) - IDR5: u1, - /// Port input data (y = - /// 0..15) - IDR6: u1, - /// Port input data (y = - /// 0..15) - IDR7: u1, - /// Port input data (y = - /// 0..15) - IDR8: u1, - /// Port input data (y = - /// 0..15) - IDR9: u1, - /// Port input data (y = - /// 0..15) - IDR10: u1, - /// Port input data (y = - /// 0..15) - IDR11: u1, - /// Port input data (y = - /// 0..15) - IDR12: u1, - /// Port input data (y = - /// 0..15) - IDR13: u1, - /// Port input data (y = - /// 0..15) - IDR14: u1, - /// Port input data (y = - /// 0..15) - IDR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40020014 - /// GPIO port output data register - pub const ODR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port output data (y = - /// 0..15) - ODR0: u1, - /// Port output data (y = - /// 0..15) - ODR1: u1, - /// Port output data (y = - /// 0..15) - ODR2: u1, - /// Port output data (y = - /// 0..15) - ODR3: u1, - /// Port output data (y = - /// 0..15) - ODR4: u1, - /// Port output data (y = - /// 0..15) - ODR5: u1, - /// Port output data (y = - /// 0..15) - ODR6: u1, - /// Port output data (y = - /// 0..15) - ODR7: u1, - /// Port output data (y = - /// 0..15) - ODR8: u1, - /// Port output data (y = - /// 0..15) - ODR9: u1, - /// Port output data (y = - /// 0..15) - ODR10: u1, - /// Port output data (y = - /// 0..15) - ODR11: u1, - /// Port output data (y = - /// 0..15) - ODR12: u1, - /// Port output data (y = - /// 0..15) - ODR13: u1, - /// Port output data (y = - /// 0..15) - ODR14: u1, - /// Port output data (y = - /// 0..15) - ODR15: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40020018 - /// GPIO port bit set/reset - /// register - pub const BSRR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x set bit y (y= - /// 0..15) - BS0: u1, - /// Port x set bit y (y= - /// 0..15) - BS1: u1, - /// Port x set bit y (y= - /// 0..15) - BS2: u1, - /// Port x set bit y (y= - /// 0..15) - BS3: u1, - /// Port x set bit y (y= - /// 0..15) - BS4: u1, - /// Port x set bit y (y= - /// 0..15) - BS5: u1, - /// Port x set bit y (y= - /// 0..15) - BS6: u1, - /// Port x set bit y (y= - /// 0..15) - BS7: u1, - /// Port x set bit y (y= - /// 0..15) - BS8: u1, - /// Port x set bit y (y= - /// 0..15) - BS9: u1, - /// Port x set bit y (y= - /// 0..15) - BS10: u1, - /// Port x set bit y (y= - /// 0..15) - BS11: u1, - /// Port x set bit y (y= - /// 0..15) - BS12: u1, - /// Port x set bit y (y= - /// 0..15) - BS13: u1, - /// Port x set bit y (y= - /// 0..15) - BS14: u1, - /// Port x set bit y (y= - /// 0..15) - BS15: u1, - /// Port x set bit y (y= - /// 0..15) - BR0: u1, - /// Port x reset bit y (y = - /// 0..15) - BR1: u1, - /// Port x reset bit y (y = - /// 0..15) - BR2: u1, - /// Port x reset bit y (y = - /// 0..15) - BR3: u1, - /// Port x reset bit y (y = - /// 0..15) - BR4: u1, - /// Port x reset bit y (y = - /// 0..15) - BR5: u1, - /// Port x reset bit y (y = - /// 0..15) - BR6: u1, - /// Port x reset bit y (y = - /// 0..15) - BR7: u1, - /// Port x reset bit y (y = - /// 0..15) - BR8: u1, - /// Port x reset bit y (y = - /// 0..15) - BR9: u1, - /// Port x reset bit y (y = - /// 0..15) - BR10: u1, - /// Port x reset bit y (y = - /// 0..15) - BR11: u1, - /// Port x reset bit y (y = - /// 0..15) - BR12: u1, - /// Port x reset bit y (y = - /// 0..15) - BR13: u1, - /// Port x reset bit y (y = - /// 0..15) - BR14: u1, - /// Port x reset bit y (y = - /// 0..15) - BR15: u1, - }), base_address + 0x18); - - /// address: 0x4002001c - /// GPIO port configuration lock - /// register - pub const LCKR = @intToPtr(*volatile Mmio(32, packed struct { - /// Port x lock bit y (y= - /// 0..15) - LCK0: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK1: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK2: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK3: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK4: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK5: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK6: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK7: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK8: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK9: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK10: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK11: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK12: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK13: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK14: u1, - /// Port x lock bit y (y= - /// 0..15) - LCK15: u1, - /// Port x lock bit y (y= - /// 0..15) - LCKK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40020020 - /// GPIO alternate function low - /// register - pub const AFRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL0: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL1: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL2: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL3: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL4: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL5: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL6: u4, - /// Alternate function selection for port x - /// bit y (y = 0..7) - AFRL7: u4, - }), base_address + 0x20); - - /// address: 0x40020024 - /// GPIO alternate function high - /// register - pub const AFRH = @intToPtr(*volatile Mmio(32, packed struct { - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH8: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH9: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH10: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH11: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH12: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH13: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH14: u4, - /// Alternate function selection for port x - /// bit y (y = 8..15) - AFRH15: u4, - }), base_address + 0x24); - }; - - /// System configuration controller - pub const SYSCFG = struct { - pub const base_address = 0x40013800; - - /// address: 0x40013800 - /// memory remap register - pub const MEMRM = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory mapping selection - MEM_MODE: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Flash bank mode selection - FB_MODE: u1, - reserved5: u1, - /// FMC memory mapping swap - SWP_FMC: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x0); - - /// address: 0x40013804 - /// peripheral mode configuration - /// register - pub const PMC = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// ADC1DC2 - ADC1DC2: u1, - /// ADC2DC2 - ADC2DC2: u1, - /// ADC3DC2 - ADC3DC2: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// Ethernet PHY interface - /// selection - MII_RMII_SEL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40013808 - /// external interrupt configuration register - /// 1 - pub const EXTICR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 0 to - /// 3) - EXTI0: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI1: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI2: u4, - /// EXTI x configuration (x = 0 to - /// 3) - EXTI3: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001380c - /// external interrupt configuration register - /// 2 - pub const EXTICR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 4 to - /// 7) - EXTI4: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI5: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI6: u4, - /// EXTI x configuration (x = 4 to - /// 7) - EXTI7: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40013810 - /// external interrupt configuration register - /// 3 - pub const EXTICR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 8 to - /// 11) - EXTI8: u4, - /// EXTI x configuration (x = 8 to - /// 11) - EXTI9: u4, - /// EXTI10 - EXTI10: u4, - /// EXTI x configuration (x = 8 to - /// 11) - EXTI11: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013814 - /// external interrupt configuration register - /// 4 - pub const EXTICR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// EXTI x configuration (x = 12 to - /// 15) - EXTI12: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI13: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI14: u4, - /// EXTI x configuration (x = 12 to - /// 15) - EXTI15: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013820 - /// Compensation cell control - /// register - pub const CMPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Compensation cell - /// power-down - CMP_PD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// READY - READY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x20); - }; - - /// Serial peripheral interface - pub const SPI1 = struct { - pub const base_address = 0x40013000; - - /// address: 0x40013000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40013008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001300c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001301c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI2 = struct { - pub const base_address = 0x40003800; - - /// address: 0x40003800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003808 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000380c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003810 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003814 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003818 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000381c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003820 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI3 = struct { - pub const base_address = 0x40003c00; - - /// address: 0x40003c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003c08 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x40003c0c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003c10 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003c14 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003c18 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40003c1c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003c20 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S2ext = struct { - pub const base_address = 0x40003400; - - /// address: 0x40003400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40003408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000340c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40003410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40003414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40003418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000341c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40003420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const I2S3ext = struct { - pub const base_address = 0x40004000; - - /// address: 0x40004000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40004004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40004008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4000400c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40004010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40004014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40004018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000401c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40004020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI4 = struct { - pub const base_address = 0x40013400; - - /// address: 0x40013400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40013404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40013408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001340c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40013410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40013414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40013418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001341c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40013420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI5 = struct { - pub const base_address = 0x40015000; - - /// address: 0x40015000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40015004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40015008 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001500c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40015010 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40015014 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40015018 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001501c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40015020 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - pub const SPI6 = struct { - pub const base_address = 0x40015400; - - /// address: 0x40015400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Master selection - MSTR: u1, - /// Baud rate control - BR: u3, - /// SPI enable - SPE: u1, - /// Frame format - LSBFIRST: u1, - /// Internal slave select - SSI: u1, - /// Software slave management - SSM: u1, - /// Receive only - RXONLY: u1, - /// Data frame format - DFF: u1, - /// CRC transfer next - CRCNEXT: u1, - /// Hardware CRC calculation - /// enable - CRCEN: u1, - /// Output enable in bidirectional - /// mode - BIDIOE: u1, - /// Bidirectional data mode - /// enable - BIDIMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40015404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx buffer DMA enable - RXDMAEN: u1, - /// Tx buffer DMA enable - TXDMAEN: u1, - /// SS output enable - SSOE: u1, - reserved0: u1, - /// Frame format - FRF: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt - /// enable - RXNEIE: u1, - /// Tx buffer empty interrupt - /// enable - TXEIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40015408 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive buffer not empty - RXNE: u1, - /// Transmit buffer empty - TXE: u1, - /// Channel side - CHSIDE: u1, - /// Underrun flag - UDR: u1, - /// CRC error flag - CRCERR: u1, - /// Mode fault - MODF: u1, - /// Overrun flag - OVR: u1, - /// Busy flag - BSY: u1, - /// TI frame format error - TIFRFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4001540c - /// data register - pub const DR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc); - - /// address: 0x40015410 - /// CRC polynomial register - pub const CRCPR = @intToPtr(*volatile Mmio(32, packed struct { - /// CRC polynomial register - CRCPOLY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40015414 - /// RX CRC register - pub const RXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rx CRC register - RxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40015418 - /// TX CRC register - pub const TXCRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tx CRC register - TxCRC: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001541c - /// I2S configuration register - pub const I2SCFGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel length (number of bits per audio - /// channel) - CHLEN: u1, - /// Data length to be - /// transferred - DATLEN: u2, - /// Steady state clock - /// polarity - CKPOL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved0: u1, - /// PCM frame synchronization - PCMSYNC: u1, - /// I2S configuration mode - I2SCFG: u2, - /// I2S Enable - I2SE: u1, - /// I2S mode selection - I2SMOD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40015420 - /// I2S prescaler register - pub const I2SPR = @intToPtr(*volatile Mmio(32, packed struct { - /// I2S Linear prescaler - I2SDIV: u8, - /// Odd factor for the - /// prescaler - ODD: u1, - /// Master clock output enable - MCKOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x20); - }; - - /// Secure digital input/output - /// interface - pub const SDIO = struct { - pub const base_address = 0x40012c00; - - /// address: 0x40012c00 - /// power control register - pub const POWER = @intToPtr(*volatile Mmio(32, packed struct { - /// PWRCTRL - PWRCTRL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x0); - - /// address: 0x40012c04 - /// SDI clock control register - pub const CLKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock divide factor - CLKDIV: u8, - /// Clock enable bit - CLKEN: u1, - /// Power saving configuration - /// bit - PWRSAV: u1, - /// Clock divider bypass enable - /// bit - BYPASS: u1, - /// Wide bus mode enable bit - WIDBUS: u2, - /// SDIO_CK dephasing selection - /// bit - NEGEDGE: u1, - /// HW Flow Control enable - HWFC_EN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40012c08 - /// argument register - pub const ARG = @intToPtr(*volatile Mmio(32, packed struct { - /// Command argument - CMDARG: u32, - }), base_address + 0x8); - - /// address: 0x40012c0c - /// command register - pub const CMD = @intToPtr(*volatile Mmio(32, packed struct { - /// Command index - CMDINDEX: u6, - /// Wait for response bits - WAITRESP: u2, - /// CPSM waits for interrupt - /// request - WAITINT: u1, - /// CPSM Waits for ends of data transfer - /// (CmdPend internal signal). - WAITPEND: u1, - /// Command path state machine (CPSM) Enable - /// bit - CPSMEN: u1, - /// SD I/O suspend command - SDIOSuspend: u1, - /// Enable CMD completion - ENCMDcompl: u1, - /// not Interrupt Enable - nIEN: u1, - /// CE-ATA command - CE_ATACMD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40012c10 - /// command response register - pub const RESPCMD = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); - - /// address: 0x40012c14 - /// response 1..4 register - pub const RESP1 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS1: u32, - }), base_address + 0x14); - - /// address: 0x40012c18 - /// response 1..4 register - pub const RESP2 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS2: u32, - }), base_address + 0x18); - - /// address: 0x40012c1c - /// response 1..4 register - pub const RESP3 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS3: u32, - }), base_address + 0x1c); - - /// address: 0x40012c20 - /// response 1..4 register - pub const RESP4 = @intToPtr(*volatile Mmio(32, packed struct { - /// see Table 132. - CARDSTATUS4: u32, - }), base_address + 0x20); - - /// address: 0x40012c24 - /// data timer register - pub const DTIMER = @intToPtr(*volatile Mmio(32, packed struct { - /// Data timeout period - DATATIME: u32, - }), base_address + 0x24); - - /// address: 0x40012c28 - /// data length register - pub const DLEN = @intToPtr(*volatile Mmio(32, packed struct { - /// Data length value - DATALENGTH: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x28); - - /// address: 0x40012c2c - /// data control register - pub const DCTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DTEN - DTEN: u1, - /// Data transfer direction - /// selection - DTDIR: u1, - /// Data transfer mode selection 1: Stream - /// or SDIO multibyte data transfer. - DTMODE: u1, - /// DMA enable bit - DMAEN: u1, - /// Data block size - DBLOCKSIZE: u4, - /// Read wait start - RWSTART: u1, - /// Read wait stop - RWSTOP: u1, - /// Read wait mode - RWMOD: u1, - /// SD I/O enable functions - SDIOEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40012c30 - /// data counter register - pub const DCOUNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Data count value - DATACOUNT: u25, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x30); - - /// address: 0x40012c34 - /// status register - pub const STA = @intToPtr(*volatile Mmio(32, packed struct { - /// Command response received (CRC check - /// failed) - CCRCFAIL: u1, - /// Data block sent/received (CRC check - /// failed) - DCRCFAIL: u1, - /// Command response timeout - CTIMEOUT: u1, - /// Data timeout - DTIMEOUT: u1, - /// Transmit FIFO underrun - /// error - TXUNDERR: u1, - /// Received FIFO overrun - /// error - RXOVERR: u1, - /// Command response received (CRC check - /// passed) - CMDREND: u1, - /// Command sent (no response - /// required) - CMDSENT: u1, - /// Data end (data counter, SDIDCOUNT, is - /// zero) - DATAEND: u1, - /// Start bit not detected on all data - /// signals in wide bus mode - STBITERR: u1, - /// Data block sent/received (CRC check - /// passed) - DBCKEND: u1, - /// Command transfer in - /// progress - CMDACT: u1, - /// Data transmit in progress - TXACT: u1, - /// Data receive in progress - RXACT: u1, - /// Transmit FIFO half empty: at least 8 - /// words can be written into the FIFO - TXFIFOHE: u1, - /// Receive FIFO half full: there are at - /// least 8 words in the FIFO - RXFIFOHF: u1, - /// Transmit FIFO full - TXFIFOF: u1, - /// Receive FIFO full - RXFIFOF: u1, - /// Transmit FIFO empty - TXFIFOE: u1, - /// Receive FIFO empty - RXFIFOE: u1, - /// Data available in transmit - /// FIFO - TXDAVL: u1, - /// Data available in receive - /// FIFO - RXDAVL: u1, - /// SDIO interrupt received - SDIOIT: u1, - /// CE-ATA command completion signal - /// received for CMD61 - CEATAEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x34); - - /// address: 0x40012c38 - /// interrupt clear register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// CCRCFAIL flag clear bit - CCRCFAILC: u1, - /// DCRCFAIL flag clear bit - DCRCFAILC: u1, - /// CTIMEOUT flag clear bit - CTIMEOUTC: u1, - /// DTIMEOUT flag clear bit - DTIMEOUTC: u1, - /// TXUNDERR flag clear bit - TXUNDERRC: u1, - /// RXOVERR flag clear bit - RXOVERRC: u1, - /// CMDREND flag clear bit - CMDRENDC: u1, - /// CMDSENT flag clear bit - CMDSENTC: u1, - /// DATAEND flag clear bit - DATAENDC: u1, - /// STBITERR flag clear bit - STBITERRC: u1, - /// DBCKEND flag clear bit - DBCKENDC: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// SDIOIT flag clear bit - SDIOITC: u1, - /// CEATAEND flag clear bit - CEATAENDC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x38); - - /// address: 0x40012c3c - /// mask register - pub const MASK = @intToPtr(*volatile Mmio(32, packed struct { - /// Command CRC fail interrupt - /// enable - CCRCFAILIE: u1, - /// Data CRC fail interrupt - /// enable - DCRCFAILIE: u1, - /// Command timeout interrupt - /// enable - CTIMEOUTIE: u1, - /// Data timeout interrupt - /// enable - DTIMEOUTIE: u1, - /// Tx FIFO underrun error interrupt - /// enable - TXUNDERRIE: u1, - /// Rx FIFO overrun error interrupt - /// enable - RXOVERRIE: u1, - /// Command response received interrupt - /// enable - CMDRENDIE: u1, - /// Command sent interrupt - /// enable - CMDSENTIE: u1, - /// Data end interrupt enable - DATAENDIE: u1, - /// Start bit error interrupt - /// enable - STBITERRIE: u1, - /// Data block end interrupt - /// enable - DBCKENDIE: u1, - /// Command acting interrupt - /// enable - CMDACTIE: u1, - /// Data transmit acting interrupt - /// enable - TXACTIE: u1, - /// Data receive acting interrupt - /// enable - RXACTIE: u1, - /// Tx FIFO half empty interrupt - /// enable - TXFIFOHEIE: u1, - /// Rx FIFO half full interrupt - /// enable - RXFIFOHFIE: u1, - /// Tx FIFO full interrupt - /// enable - TXFIFOFIE: u1, - /// Rx FIFO full interrupt - /// enable - RXFIFOFIE: u1, - /// Tx FIFO empty interrupt - /// enable - TXFIFOEIE: u1, - /// Rx FIFO empty interrupt - /// enable - RXFIFOEIE: u1, - /// Data available in Tx FIFO interrupt - /// enable - TXDAVLIE: u1, - /// Data available in Rx FIFO interrupt - /// enable - RXDAVLIE: u1, - /// SDIO mode interrupt received interrupt - /// enable - SDIOITIE: u1, - /// CE-ATA command completion signal - /// received interrupt enable - CEATAENDIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x3c); - - /// address: 0x40012c48 - /// FIFO counter register - pub const FIFOCNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Remaining number of words to be written - /// to or read from the FIFO. - FIFOCOUNT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x48); - - /// address: 0x40012c80 - /// data FIFO register - pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { - /// Receive and transmit FIFO - /// data - FIFOData: u32, - }), base_address + 0x80); - }; - - /// Analog-to-digital converter - pub const ADC1 = struct { - pub const base_address = 0x40012000; - - /// address: 0x40012000 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012004 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012008 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001200c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012010 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012014 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012018 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001201c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012020 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012024 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012028 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001202c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012030 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012034 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012038 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001203c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012040 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012044 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012048 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001204c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const ADC2 = struct { - pub const base_address = 0x40012100; - - /// address: 0x40012100 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012104 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012108 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001210c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012110 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012114 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012118 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001211c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012120 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012124 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012128 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001212c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012130 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012134 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012138 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001213c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012140 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012144 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012148 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001214c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const ADC3 = struct { - pub const base_address = 0x40012200; - - /// address: 0x40012200 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag - AWD: u1, - /// Regular channel end of - /// conversion - EOC: u1, - /// Injected channel end of - /// conversion - JEOC: u1, - /// Injected channel start - /// flag - JSTRT: u1, - /// Regular channel start flag - STRT: u1, - /// Overrun - OVR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40012204 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog channel select - /// bits - AWDCH: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Analog watchdog interrupt - /// enable - AWDIE: u1, - /// Interrupt enable for injected - /// channels - JEOCIE: u1, - /// Scan mode - SCAN: u1, - /// Enable the watchdog on a single channel - /// in scan mode - AWDSGL: u1, - /// Automatic injected group - /// conversion - JAUTO: u1, - /// Discontinuous mode on regular - /// channels - DISCEN: u1, - /// Discontinuous mode on injected - /// channels - JDISCEN: u1, - /// Discontinuous mode channel - /// count - DISCNUM: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Analog watchdog enable on injected - /// channels - JAWDEN: u1, - /// Analog watchdog enable on regular - /// channels - AWDEN: u1, - /// Resolution - RES: u2, - /// Overrun interrupt enable - OVRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x4); - - /// address: 0x40012208 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// A/D Converter ON / OFF - ADON: u1, - /// Continuous conversion - CONT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Direct memory access mode (for single - /// ADC mode) - DMA: u1, - /// DMA disable selection (for single ADC - /// mode) - DDS: u1, - /// End of conversion - /// selection - EOCS: u1, - /// Data alignment - ALIGN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// External event select for injected - /// group - JEXTSEL: u4, - /// External trigger enable for injected - /// channels - JEXTEN: u2, - /// Start conversion of injected - /// channels - JSWSTART: u1, - reserved10: u1, - /// External event select for regular - /// group - EXTSEL: u4, - /// External trigger enable for regular - /// channels - EXTEN: u2, - /// Start conversion of regular - /// channels - SWSTART: u1, - padding0: u1, - }), base_address + 0x8); - - /// address: 0x4001220c - /// sample time register 1 - pub const SMPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0xc); - - /// address: 0x40012210 - /// sample time register 2 - pub const SMPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Sample time bits - SMPx_x: u32, - }), base_address + 0x10); - - /// address: 0x40012214 - /// injected channel data offset register - /// x - pub const JOFR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET1: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40012218 - /// injected channel data offset register - /// x - pub const JOFR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET2: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x18); - - /// address: 0x4001221c - /// injected channel data offset register - /// x - pub const JOFR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET3: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x1c); - - /// address: 0x40012220 - /// injected channel data offset register - /// x - pub const JOFR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Data offset for injected channel - /// x - JOFFSET4: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x20); - - /// address: 0x40012224 - /// watchdog higher threshold - /// register - pub const HTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog higher - /// threshold - HT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x24); - - /// address: 0x40012228 - /// watchdog lower threshold - /// register - pub const LTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog lower - /// threshold - LT: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x28); - - /// address: 0x4001222c - /// regular sequence register 1 - pub const SQR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// 13th conversion in regular - /// sequence - SQ13: u5, - /// 14th conversion in regular - /// sequence - SQ14: u5, - /// 15th conversion in regular - /// sequence - SQ15: u5, - /// 16th conversion in regular - /// sequence - SQ16: u5, - /// Regular channel sequence - /// length - L: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40012230 - /// regular sequence register 2 - pub const SQR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// 7th conversion in regular - /// sequence - SQ7: u5, - /// 8th conversion in regular - /// sequence - SQ8: u5, - /// 9th conversion in regular - /// sequence - SQ9: u5, - /// 10th conversion in regular - /// sequence - SQ10: u5, - /// 11th conversion in regular - /// sequence - SQ11: u5, - /// 12th conversion in regular - /// sequence - SQ12: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x30); - - /// address: 0x40012234 - /// regular sequence register 3 - pub const SQR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in regular - /// sequence - SQ1: u5, - /// 2nd conversion in regular - /// sequence - SQ2: u5, - /// 3rd conversion in regular - /// sequence - SQ3: u5, - /// 4th conversion in regular - /// sequence - SQ4: u5, - /// 5th conversion in regular - /// sequence - SQ5: u5, - /// 6th conversion in regular - /// sequence - SQ6: u5, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - - /// address: 0x40012238 - /// injected sequence register - pub const JSQR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st conversion in injected - /// sequence - JSQ1: u5, - /// 2nd conversion in injected - /// sequence - JSQ2: u5, - /// 3rd conversion in injected - /// sequence - JSQ3: u5, - /// 4th conversion in injected - /// sequence - JSQ4: u5, - /// Injected sequence length - JL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4001223c - /// injected data register x - pub const JDR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40012240 - /// injected data register x - pub const JDR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x40); - - /// address: 0x40012244 - /// injected data register x - pub const JDR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - - /// address: 0x40012248 - /// injected data register x - pub const JDR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Injected data - JDATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4001224c - /// regular data register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Regular data - DATA: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const USART6 = struct { - pub const base_address = 0x40011400; - - /// address: 0x40011400 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40011404 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40011408 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001140c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011410 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40011414 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40011418 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART1 = struct { - pub const base_address = 0x40011000; - - /// address: 0x40011000 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40011004 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40011008 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001100c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40011010 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40011014 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40011018 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART2 = struct { - pub const base_address = 0x40004400; - - /// address: 0x40004400 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004404 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004408 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000440c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004410 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004414 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40004418 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const USART3 = struct { - pub const base_address = 0x40004800; - - /// address: 0x40004800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40004804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000480c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40004818 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const UART7 = struct { - pub const base_address = 0x40007800; - - /// address: 0x40007800 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40007804 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40007808 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000780c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007810 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40007814 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007818 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - pub const UART8 = struct { - pub const base_address = 0x40007c00; - - /// address: 0x40007c00 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - /// CTS flag - CTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40007c04 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40007c08 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40007c0c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007c10 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - /// Last bit clock pulse - LBCL: u1, - /// Clock phase - CPHA: u1, - /// Clock polarity - CPOL: u1, - /// Clock enable - CLKEN: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40007c14 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - /// Smartcard NACK enable - NACK: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - /// RTS enable - RTSE: u1, - /// CTS enable - CTSE: u1, - /// CTS interrupt enable - CTSIE: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007c18 - /// Guard time and prescaler - /// register - pub const GTPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Prescaler value - PSC: u8, - /// Guard time value - GT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - }; - - /// Digital-to-analog converter - pub const DAC = struct { - pub const base_address = 0x40007400; - - /// address: 0x40007400 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 enable - EN1: u1, - /// DAC channel1 output buffer - /// disable - BOFF1: u1, - /// DAC channel1 trigger - /// enable - TEN1: u1, - /// DAC channel1 trigger - /// selection - TSEL1: u3, - /// DAC channel1 noise/triangle wave - /// generation enable - WAVE1: u2, - /// DAC channel1 mask/amplitude - /// selector - MAMP1: u4, - /// DAC channel1 DMA enable - DMAEN1: u1, - /// DAC channel1 DMA Underrun Interrupt - /// enable - DMAUDRIE1: u1, - reserved0: u1, - reserved1: u1, - /// DAC channel2 enable - EN2: u1, - /// DAC channel2 output buffer - /// disable - BOFF2: u1, - /// DAC channel2 trigger - /// enable - TEN2: u1, - /// DAC channel2 trigger - /// selection - TSEL2: u3, - /// DAC channel2 noise/triangle wave - /// generation enable - WAVE2: u2, - /// DAC channel2 mask/amplitude - /// selector - MAMP2: u4, - /// DAC channel2 DMA enable - DMAEN2: u1, - /// DAC channel2 DMA underrun interrupt - /// enable - DMAUDRIE2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x0); - - /// address: 0x40007404 - /// software trigger register - pub const SWTRIGR = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 software - /// trigger - SWTRIG1: u1, - /// DAC channel2 software - /// trigger - SWTRIG2: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x4); - - /// address: 0x40007408 - /// channel1 12-bit right-aligned data holding - /// register - pub const DHR12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000740c - /// channel1 12-bit left aligned data holding - /// register - pub const DHR12L1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40007410 - /// channel1 8-bit right aligned data holding - /// register - pub const DHR8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x10); - - /// address: 0x40007414 - /// channel2 12-bit right aligned data holding - /// register - pub const DHR12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - - /// address: 0x40007418 - /// channel2 12-bit left aligned data holding - /// register - pub const DHR12L2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000741c - /// channel2 8-bit right-aligned data holding - /// register - pub const DHR8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x1c); - - /// address: 0x40007420 - /// Dual DAC 12-bit right-aligned data holding - /// register - pub const DHR12RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 12-bit right-aligned - /// data - DACC1DHR: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel2 12-bit right-aligned - /// data - DACC2DHR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20); - - /// address: 0x40007424 - /// DUAL DAC 12-bit left aligned data holding - /// register - pub const DHR12LD = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// DAC channel1 12-bit left-aligned - /// data - DACC1DHR: u12, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// DAC channel2 12-bit left-aligned - /// data - DACC2DHR: u12, - }), base_address + 0x24); - - /// address: 0x40007428 - /// DUAL DAC 8-bit right aligned data holding - /// register - pub const DHR8RD = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 8-bit right-aligned - /// data - DACC1DHR: u8, - /// DAC channel2 8-bit right-aligned - /// data - DACC2DHR: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000742c - /// channel1 data output register - pub const DOR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel1 data output - DACC1DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40007430 - /// channel2 data output register - pub const DOR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DAC channel2 data output - DACC2DOR: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x30); - - /// address: 0x40007434 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// DAC channel1 DMA underrun - /// flag - DMAUDR1: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - /// DAC channel2 DMA underrun - /// flag - DMAUDR2: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x34); - }; - - /// Power control - pub const PWR = struct { - pub const base_address = 0x40007000; - - /// address: 0x40007000 - /// power control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low-power deep sleep - LPDS: u1, - /// Power down deepsleep - PDDS: u1, - /// Clear wakeup flag - CWUF: u1, - /// Clear standby flag - CSBF: u1, - /// Power voltage detector - /// enable - PVDE: u1, - /// PVD level selection - PLS: u3, - /// Disable backup domain write - /// protection - DBP: u1, - /// Flash power down in Stop - /// mode - FPDS: u1, - /// Low-Power Regulator Low Voltage in - /// deepsleep - LPLVDS: u1, - /// Main regulator low voltage in deepsleep - /// mode - MRLVDS: u1, - reserved0: u1, - reserved1: u1, - /// Regulator voltage scaling output - /// selection - VOS: u2, - /// Over-drive enable - ODEN: u1, - /// Over-drive switching - /// enabled - ODSWEN: u1, - /// Under-drive enable in stop - /// mode - UDEN: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x40007004 - /// power control/status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup flag - WUF: u1, - /// Standby flag - SBF: u1, - /// PVD output - PVDO: u1, - /// Backup regulator ready - BRR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Enable WKUP pin - EWUP: u1, - /// Backup regulator enable - BRE: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Regulator voltage scaling output - /// selection ready bit - VOSRDY: u1, - reserved8: u1, - /// Over-drive mode ready - ODRDY: u1, - /// Over-drive mode switching - /// ready - ODSWRDY: u1, - /// Under-drive ready flag - UDRDY: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - }; - - /// Independent watchdog - pub const IWDG = struct { - pub const base_address = 0x40003000; - - /// address: 0x40003000 - /// Key register - pub const KR = @intToPtr(*volatile Mmio(32, packed struct { - /// Key value (write only, read - /// 0000h) - KEY: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40003004 - /// Prescaler register - pub const PR = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x4); - - /// address: 0x40003008 - /// Reload register - pub const RLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog counter reload - /// value - RL: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x8); - - /// address: 0x4000300c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Watchdog prescaler value - /// update - PVU: u1, - /// Watchdog counter reload value - /// update - RVU: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - }; - - /// Window watchdog - pub const WWDG = struct { - pub const base_address = 0x40002c00; - - /// address: 0x40002c00 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit counter (MSB to LSB) - T: u7, - /// Activation bit - WDGA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40002c04 - /// Configuration register - pub const CFR = @intToPtr(*volatile Mmio(32, packed struct { - /// 7-bit window value - W: u7, - /// Timer base - WDGTB0: u1, - /// Timer base - WDGTB1: u1, - /// Early wakeup interrupt - EWI: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x4); - - /// address: 0x40002c08 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Early wakeup interrupt - /// flag - EWIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x8); - }; - - /// Real-time clock - pub const RTC = struct { - pub const base_address = 0x40002800; - - /// address: 0x40002800 - /// time register - pub const TR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - reserved0: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - reserved1: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x0); - - /// address: 0x40002804 - /// date register - pub const DR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - /// Year units in BCD format - YU: u4, - /// Year tens in BCD format - YT: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40002808 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup clock selection - WCKSEL: u3, - /// Time-stamp event active - /// edge - TSEDGE: u1, - /// Reference clock detection enable (50 or - /// 60 Hz) - REFCKON: u1, - reserved0: u1, - /// Hour format - FMT: u1, - /// Coarse digital calibration - /// enable - DCE: u1, - /// Alarm A enable - ALRAE: u1, - /// Alarm B enable - ALRBE: u1, - /// Wakeup timer enable - WUTE: u1, - /// Time stamp enable - TSE: u1, - /// Alarm A interrupt enable - ALRAIE: u1, - /// Alarm B interrupt enable - ALRBIE: u1, - /// Wakeup timer interrupt - /// enable - WUTIE: u1, - /// Time-stamp interrupt - /// enable - TSIE: u1, - /// Add 1 hour (summer time - /// change) - ADD1H: u1, - /// Subtract 1 hour (winter time - /// change) - SUB1H: u1, - /// Backup - BKP: u1, - reserved1: u1, - /// Output polarity - POL: u1, - /// Output selection - OSEL: u2, - /// Calibration output enable - COE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0x4000280c - /// initialization and status - /// register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Alarm A write flag - ALRAWF: u1, - /// Alarm B write flag - ALRBWF: u1, - /// Wakeup timer write flag - WUTWF: u1, - /// Shift operation pending - SHPF: u1, - /// Initialization status flag - INITS: u1, - /// Registers synchronization - /// flag - RSF: u1, - /// Initialization flag - INITF: u1, - /// Initialization mode - INIT: u1, - /// Alarm A flag - ALRAF: u1, - /// Alarm B flag - ALRBF: u1, - /// Wakeup timer flag - WUTF: u1, - /// Time-stamp flag - TSF: u1, - /// Time-stamp overflow flag - TSOVF: u1, - /// Tamper detection flag - TAMP1F: u1, - /// TAMPER2 detection flag - TAMP2F: u1, - reserved0: u1, - /// Recalibration pending Flag - RECALPF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xc); - - /// address: 0x40002810 - /// prescaler register - pub const PRER = @intToPtr(*volatile Mmio(32, packed struct { - /// Synchronous prescaler - /// factor - PREDIV_S: u15, - reserved0: u1, - /// Asynchronous prescaler - /// factor - PREDIV_A: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x10); - - /// address: 0x40002814 - /// wakeup timer register - pub const WUTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Wakeup auto-reload value - /// bits - WUT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40002818 - /// calibration register - pub const CALIBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital calibration - DC: u5, - reserved0: u1, - reserved1: u1, - /// Digital calibration sign - DCS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x4000281c - /// alarm A register - pub const ALRMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm A seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm A minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm A hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm A date mask - MSK4: u1, - }), base_address + 0x1c); - - /// address: 0x40002820 - /// alarm B register - pub const ALRMBR = @intToPtr(*volatile Mmio(32, packed struct { - /// Second units in BCD format - SU: u4, - /// Second tens in BCD format - ST: u3, - /// Alarm B seconds mask - MSK1: u1, - /// Minute units in BCD format - MNU: u4, - /// Minute tens in BCD format - MNT: u3, - /// Alarm B minutes mask - MSK2: u1, - /// Hour units in BCD format - HU: u4, - /// Hour tens in BCD format - HT: u2, - /// AM/PM notation - PM: u1, - /// Alarm B hours mask - MSK3: u1, - /// Date units or day in BCD - /// format - DU: u4, - /// Date tens in BCD format - DT: u2, - /// Week day selection - WDSEL: u1, - /// Alarm B date mask - MSK4: u1, - }), base_address + 0x20); - - /// address: 0x40002824 - /// write protection register - pub const WPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Write protection key - KEY: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40002828 - /// sub second register - pub const SSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4000282c - /// shift control register - pub const SHIFTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Subtract a fraction of a - /// second - SUBFS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Add one second - ADD1S: u1, - }), base_address + 0x2c); - - /// address: 0x40002830 - /// time stamp time register - pub const TSTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1, - /// Active level for tamper 1 - TAMP1TRG: u1, - /// Tamper interrupt enable - TAMPIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// TAMPER1 mapping - TAMP1INSEL: u1, - /// TIMESTAMP mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x30); - - /// address: 0x40002834 - /// time stamp date register - pub const TSDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Date units in BCD format - DU: u4, - /// Date tens in BCD format - DT: u2, - reserved0: u1, - reserved1: u1, - /// Month units in BCD format - MU: u4, - /// Month tens in BCD format - MT: u1, - /// Week day units - WDU: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40002838 - /// timestamp sub second register - pub const TSSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub second value - SS: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x38); - - /// address: 0x4000283c - /// calibration register - pub const CALR = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration minus - CALM: u9, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Use a 16-second calibration cycle - /// period - CALW16: u1, - /// Use an 8-second calibration cycle - /// period - CALW8: u1, - /// Increase frequency of RTC by 488.5 - /// ppm - CALP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x3c); - - /// address: 0x40002840 - /// tamper and alternate function configuration - /// register - pub const TAFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Tamper 1 detection enable - TAMP1E: u1, - /// Active level for tamper 1 - TAMP1TRG: u1, - /// Tamper interrupt enable - TAMPIE: u1, - /// Tamper 2 detection enable - TAMP2E: u1, - /// Active level for tamper 2 - TAMP2TRG: u1, - reserved0: u1, - reserved1: u1, - /// Activate timestamp on tamper detection - /// event - TAMPTS: u1, - /// Tamper sampling frequency - TAMPFREQ: u3, - /// Tamper filter count - TAMPFLT: u2, - /// Tamper precharge duration - TAMPPRCH: u2, - /// TAMPER pull-up disable - TAMPPUDIS: u1, - /// TAMPER1 mapping - TAMP1INSEL: u1, - /// TIMESTAMP mapping - TSINSEL: u1, - /// AFO_ALARM output type - ALARMOUTTYPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x40002844 - /// alarm A sub second register - pub const ALRMASSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x44); - - /// address: 0x40002848 - /// alarm B sub second register - pub const ALRMBSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Sub seconds value - SS: u15, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Mask the most-significant bits starting - /// at this bit - MASKSS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x48); - - /// address: 0x40002850 - /// backup register - pub const BKP0R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x50); - - /// address: 0x40002854 - /// backup register - pub const BKP1R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x54); - - /// address: 0x40002858 - /// backup register - pub const BKP2R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x58); - - /// address: 0x4000285c - /// backup register - pub const BKP3R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x5c); - - /// address: 0x40002860 - /// backup register - pub const BKP4R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x60); - - /// address: 0x40002864 - /// backup register - pub const BKP5R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x64); - - /// address: 0x40002868 - /// backup register - pub const BKP6R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x68); - - /// address: 0x4000286c - /// backup register - pub const BKP7R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x6c); - - /// address: 0x40002870 - /// backup register - pub const BKP8R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x70); - - /// address: 0x40002874 - /// backup register - pub const BKP9R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x74); - - /// address: 0x40002878 - /// backup register - pub const BKP10R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x78); - - /// address: 0x4000287c - /// backup register - pub const BKP11R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x7c); - - /// address: 0x40002880 - /// backup register - pub const BKP12R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x80); - - /// address: 0x40002884 - /// backup register - pub const BKP13R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x84); - - /// address: 0x40002888 - /// backup register - pub const BKP14R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x88); - - /// address: 0x4000288c - /// backup register - pub const BKP15R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x8c); - - /// address: 0x40002890 - /// backup register - pub const BKP16R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x90); - - /// address: 0x40002894 - /// backup register - pub const BKP17R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x94); - - /// address: 0x40002898 - /// backup register - pub const BKP18R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x98); - - /// address: 0x4000289c - /// backup register - pub const BKP19R = @intToPtr(*volatile Mmio(32, packed struct { - /// BKP - BKP: u32, - }), base_address + 0x9c); - }; - - /// Universal synchronous asynchronous receiver - /// transmitter - pub const UART4 = struct { - pub const base_address = 0x40004c00; - - /// address: 0x40004c00 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40004c04 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40004c08 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40004c0c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40004c10 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40004c14 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - pub const UART5 = struct { - pub const base_address = 0x40005000; - - /// address: 0x40005000 - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Parity error - PE: u1, - /// Framing error - FE: u1, - /// Noise detected flag - NF: u1, - /// Overrun error - ORE: u1, - /// IDLE line detected - IDLE: u1, - /// Read data register not - /// empty - RXNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data register - /// empty - TXE: u1, - /// LIN break detection flag - LBD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - - /// address: 0x40005004 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x4); - - /// address: 0x40005008 - /// Baud rate register - pub const BRR = @intToPtr(*volatile Mmio(32, packed struct { - /// fraction of USARTDIV - DIV_Fraction: u4, - /// mantissa of USARTDIV - DIV_Mantissa: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000500c - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Send break - SBK: u1, - /// Receiver wakeup - RWU: u1, - /// Receiver enable - RE: u1, - /// Transmitter enable - TE: u1, - /// IDLE interrupt enable - IDLEIE: u1, - /// RXNE interrupt enable - RXNEIE: u1, - /// Transmission complete interrupt - /// enable - TCIE: u1, - /// TXE interrupt enable - TXEIE: u1, - /// PE interrupt enable - PEIE: u1, - /// Parity selection - PS: u1, - /// Parity control enable - PCE: u1, - /// Wakeup method - WAKE: u1, - /// Word length - M: u1, - /// USART enable - UE: u1, - reserved0: u1, - /// Oversampling mode - OVER8: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0xc); - - /// address: 0x40005010 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Address of the USART node - ADD: u4, - reserved0: u1, - /// lin break detection length - LBDL: u1, - /// LIN break detection interrupt - /// enable - LBDIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// STOP bits - STOP: u2, - /// LIN mode enable - LINEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x10); - - /// address: 0x40005014 - /// Control register 3 - pub const CR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Error interrupt enable - EIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDSEL: u1, - reserved0: u1, - reserved1: u1, - /// DMA enable receiver - DMAR: u1, - /// DMA enable transmitter - DMAT: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// One sample bit method - /// enable - ONEBIT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x14); - }; - - /// Common ADC registers - pub const C_ADC = struct { - pub const base_address = 0x40012300; - - /// address: 0x40012300 - /// ADC Common status register - pub const CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Analog watchdog flag of ADC - /// 1 - AWD1: u1, - /// End of conversion of ADC 1 - EOC1: u1, - /// Injected channel end of conversion of - /// ADC 1 - JEOC1: u1, - /// Injected channel Start flag of ADC - /// 1 - JSTRT1: u1, - /// Regular channel Start flag of ADC - /// 1 - STRT1: u1, - /// Overrun flag of ADC 1 - OVR1: u1, - reserved0: u1, - reserved1: u1, - /// Analog watchdog flag of ADC - /// 2 - AWD2: u1, - /// End of conversion of ADC 2 - EOC2: u1, - /// Injected channel end of conversion of - /// ADC 2 - JEOC2: u1, - /// Injected channel Start flag of ADC - /// 2 - JSTRT2: u1, - /// Regular channel Start flag of ADC - /// 2 - STRT2: u1, - /// Overrun flag of ADC 2 - OVR2: u1, - reserved2: u1, - reserved3: u1, - /// Analog watchdog flag of ADC - /// 3 - AWD3: u1, - /// End of conversion of ADC 3 - EOC3: u1, - /// Injected channel end of conversion of - /// ADC 3 - JEOC3: u1, - /// Injected channel Start flag of ADC - /// 3 - JSTRT3: u1, - /// Regular channel Start flag of ADC - /// 3 - STRT3: u1, - /// Overrun flag of ADC3 - OVR3: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x0); - - /// address: 0x40012304 - /// ADC common control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Multi ADC mode selection - MULT: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Delay between 2 sampling - /// phases - DELAY: u4, - reserved3: u1, - /// DMA disable selection for multi-ADC - /// mode - DDS: u1, - /// Direct memory access mode for multi ADC - /// mode - DMA: u2, - /// ADC prescaler - ADCPRE: u2, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// VBAT enable - VBATE: u1, - /// Temperature sensor and VREFINT - /// enable - TSVREFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40012308 - /// ADC common regular data register for dual - /// and triple modes - pub const CDR = @intToPtr(*volatile Mmio(32, packed struct { - /// 1st data item of a pair of regular - /// conversions - DATA1: u16, - /// 2nd data item of a pair of regular - /// conversions - DATA2: u16, - }), base_address + 0x8); - }; - - /// Advanced-timers - pub const TIM1 = struct { - pub const base_address = 0x40010000; - - /// address: 0x40010000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40010004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40010008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40010010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40010014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40010018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40010018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4001001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40010020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40010024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40010028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40010034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40010038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40010040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40010048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40010030 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40010044 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - pub const TIM8 = struct { - pub const base_address = 0x40010400; - - /// address: 0x40010400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40010404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare preloaded - /// control - CCPC: u1, - reserved0: u1, - /// Capture/compare control update - /// selection - CCUS: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - /// Output Idle state 1 - OIS1: u1, - /// Output Idle state 1 - OIS1N: u1, - /// Output Idle state 2 - OIS2: u1, - /// Output Idle state 2 - OIS2N: u1, - /// Output Idle state 3 - OIS3: u1, - /// Output Idle state 3 - OIS3N: u1, - /// Output Idle state 4 - OIS4: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x4); - - /// address: 0x40010408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - /// COM interrupt enable - COMIE: u1, - /// Trigger interrupt enable - TIE: u1, - /// Break interrupt enable - BIE: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - /// COM DMA request enable - COMDE: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40010410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - /// COM interrupt flag - COMIF: u1, - /// Trigger interrupt flag - TIF: u1, - /// Break interrupt flag - BIF: u1, - reserved0: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40010414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - /// Capture/Compare control update - /// generation - COMG: u1, - /// Trigger generation - TG: u1, - /// Break generation - BG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x14); - - /// address: 0x40010418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - /// Output Compare 1 clear - /// enable - OC1CE: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - /// Output Compare 2 clear - /// enable - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40010418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4001041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 3 - /// selection - CC3S: u2, - /// Output compare 3 fast - /// enable - OC3FE: u1, - /// Output compare 3 preload - /// enable - OC3PE: u1, - /// Output compare 3 mode - OC3M: u3, - /// Output compare 3 clear - /// enable - OC3CE: u1, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Output compare 4 fast - /// enable - OC4FE: u1, - /// Output compare 4 preload - /// enable - OC4PE: u1, - /// Output compare 4 mode - OC4M: u3, - /// Output compare 4 clear - /// enable - OC4CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4001041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40010420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - /// Capture/Compare 1 complementary output - /// enable - CC1NE: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - /// Capture/Compare 2 complementary output - /// enable - CC2NE: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - /// Capture/Compare 3 complementary output - /// enable - CC3NE: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x20); - - /// address: 0x40010424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40010428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40010434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40010438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - - /// address: 0x4001043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c); - - /// address: 0x40010440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40); - - /// address: 0x40010448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4001044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40010430 - /// repetition counter register - pub const RCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Repetition counter value - REP: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x30); - - /// address: 0x40010444 - /// break and dead-time register - pub const BDTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Dead-time generator setup - DTG: u8, - /// Lock configuration - LOCK: u2, - /// Off-state selection for Idle - /// mode - OSSI: u1, - /// Off-state selection for Run - /// mode - OSSR: u1, - /// Break enable - BKE: u1, - /// Break polarity - BKP: u1, - /// Automatic output enable - AOE: u1, - /// Main output enable - MOE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x44); - }; - - /// General purpose timers - pub const TIM2 = struct { - pub const base_address = 0x40000000; - - /// address: 0x40000000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000000c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000001c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000001c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000024 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000002c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000003c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000040 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000048 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000004c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40000050 - /// TIM5 option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Timer Input 4 remap - ITR1_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x50); - }; - - /// General purpose timers - pub const TIM3 = struct { - pub const base_address = 0x40000400; - - /// address: 0x40000400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000408 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000040c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000041c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000041c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000424 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000042c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000438 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000043c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000440 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000448 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000044c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - pub const TIM4 = struct { - pub const base_address = 0x40000800; - - /// address: 0x40000800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000080c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000081c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x4000081c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000824 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000082c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x4000083c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000840 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000848 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x4000084c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - }; - - /// General-purpose-timers - pub const TIM5 = struct { - pub const base_address = 0x40000c00; - - /// address: 0x40000c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - /// Direction - DIR: u1, - /// Center-aligned mode - /// selection - CMS: u2, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40000c04 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Capture/compare DMA - /// selection - CCDS: u1, - /// Master mode selection - MMS: u3, - /// TI1 selection - TI1S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40000c08 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter - ETF: u4, - /// External trigger prescaler - ETPS: u2, - /// External clock enable - ECE: u1, - /// External trigger polarity - ETP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40000c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - /// Capture/Compare 3 interrupt - /// enable - CC3IE: u1, - /// Capture/Compare 4 interrupt - /// enable - CC4IE: u1, - reserved0: u1, - /// Trigger interrupt enable - TIE: u1, - reserved1: u1, - /// Update DMA request enable - UDE: u1, - /// Capture/Compare 1 DMA request - /// enable - CC1DE: u1, - /// Capture/Compare 2 DMA request - /// enable - CC2DE: u1, - /// Capture/Compare 3 DMA request - /// enable - CC3DE: u1, - /// Capture/Compare 4 DMA request - /// enable - CC4DE: u1, - reserved2: u1, - /// Trigger DMA request enable - TDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0xc); - - /// address: 0x40000c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - /// Capture/Compare 3 interrupt - /// flag - CC3IF: u1, - /// Capture/Compare 4 interrupt - /// flag - CC4IF: u1, - reserved0: u1, - /// Trigger interrupt flag - TIF: u1, - reserved1: u1, - reserved2: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - /// Capture/Compare 3 overcapture - /// flag - CC3OF: u1, - /// Capture/Compare 4 overcapture - /// flag - CC4OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x10); - - /// address: 0x40000c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - /// Capture/compare 3 - /// generation - CC3G: u1, - /// Capture/compare 4 - /// generation - CC4G: u1, - reserved0: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC1S - CC1S: u2, - /// OC1FE - OC1FE: u1, - /// OC1PE - OC1PE: u1, - /// OC1M - OC1M: u3, - /// OC1CE - OC1CE: u1, - /// CC2S - CC2S: u2, - /// OC2FE - OC2FE: u1, - /// OC2PE - OC2PE: u1, - /// OC2M - OC2M: u3, - /// OC2CE - OC2CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (output - /// mode) - pub const CCMR2_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// CC3S - CC3S: u2, - /// OC3FE - OC3FE: u1, - /// OC3PE - OC3PE: u1, - /// OC3M - OC3M: u3, - /// OC3CE - OC3CE: u1, - /// CC4S - CC4S: u2, - /// OC4FE - OC4FE: u1, - /// OC4PE - OC4PE: u1, - /// OC4M - OC4M: u3, - /// O24CE - O24CE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c1c - /// capture/compare mode register 2 (input - /// mode) - pub const CCMR2_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/compare 3 - /// selection - CC3S: u2, - /// Input capture 3 prescaler - IC3PSC: u2, - /// Input capture 3 filter - IC3F: u4, - /// Capture/Compare 4 - /// selection - CC4S: u2, - /// Input capture 4 prescaler - IC4PSC: u2, - /// Input capture 4 filter - IC4F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40000c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - /// Capture/Compare 3 output - /// enable - CC3E: u1, - /// Capture/Compare 3 output - /// Polarity - CC3P: u1, - reserved2: u1, - /// Capture/Compare 3 output - /// Polarity - CC3NP: u1, - /// Capture/Compare 4 output - /// enable - CC4E: u1, - /// Capture/Compare 3 output - /// Polarity - CC4P: u1, - reserved3: u1, - /// Capture/Compare 4 output - /// Polarity - CC4NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x20); - - /// address: 0x40000c24 - /// counter - pub const CNT = @intToPtr(*volatile Mmio(32, packed struct { - /// Low counter value - CNT_L: u16, - /// High counter value - CNT_H: u16, - }), base_address + 0x24); - - /// address: 0x40000c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40000c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Auto-reload value - ARR_L: u16, - /// High Auto-reload value - ARR_H: u16, - }), base_address + 0x2c); - - /// address: 0x40000c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 1 - /// value - CCR1_L: u16, - /// High Capture/Compare 1 - /// value - CCR1_H: u16, - }), base_address + 0x34); - - /// address: 0x40000c38 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare 2 - /// value - CCR2_L: u16, - /// High Capture/Compare 2 - /// value - CCR2_H: u16, - }), base_address + 0x38); - - /// address: 0x40000c3c - /// capture/compare register 3 - pub const CCR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR3_L: u16, - /// High Capture/Compare value - CCR3_H: u16, - }), base_address + 0x3c); - - /// address: 0x40000c40 - /// capture/compare register 4 - pub const CCR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Low Capture/Compare value - CCR4_L: u16, - /// High Capture/Compare value - CCR4_H: u16, - }), base_address + 0x40); - - /// address: 0x40000c48 - /// DMA control register - pub const DCR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA base address - DBA: u5, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// DMA burst length - DBL: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x48); - - /// address: 0x40000c4c - /// DMA address for full transfer - pub const DMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA register for burst - /// accesses - DMAB: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x40000c50 - /// TIM5 option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Timer Input 4 remap - IT4_RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x50); - }; - - /// General purpose timers - pub const TIM9 = struct { - pub const base_address = 0x40014000; - - /// address: 0x40014000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40014004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40014008 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4001400c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40014010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40014014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40014018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40014018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40014020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40014024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001402c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014038 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - pub const TIM12 = struct { - pub const base_address = 0x40001800; - - /// address: 0x40001800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001804 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x40001808 - /// slave mode control register - pub const SMCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Slave mode selection - SMS: u3, - reserved0: u1, - /// Trigger selection - TS: u3, - /// Master/Slave mode - MSM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0x4000180c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - /// Capture/Compare 2 interrupt - /// enable - CC2IE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt enable - TIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0xc); - - /// address: 0x40001810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - /// Capture/Compare 2 interrupt - /// flag - CC2IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger interrupt flag - TIF: u1, - reserved3: u1, - reserved4: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - /// Capture/compare 2 overcapture - /// flag - CC2OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10); - - /// address: 0x40001814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - /// Capture/compare 2 - /// generation - CC2G: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Trigger generation - TG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40001818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Output Compare 2 fast - /// enable - OC2FE: u1, - /// Output Compare 2 preload - /// enable - OC2PE: u1, - /// Output Compare 2 mode - OC2M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40001818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u3, - reserved0: u1, - /// Capture/Compare 2 - /// selection - CC2S: u2, - /// Input capture 2 prescaler - IC2PCS: u2, - /// Input capture 2 filter - IC2F: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x18); - - /// address: 0x40001820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - /// Capture/Compare 2 output - /// enable - CC2E: u1, - /// Capture/Compare 2 output - /// Polarity - CC2P: u1, - reserved1: u1, - /// Capture/Compare 2 output - /// Polarity - CC2NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x20); - - /// address: 0x40001824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000182c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40001838 - /// capture/compare register 2 - pub const CCR2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); - }; - - /// General-purpose-timers - pub const TIM10 = struct { - pub const base_address = 0x40014400; - - /// address: 0x40014400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4001440c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40014410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40014418 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40014418 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014420 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001442c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014434 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM13 = struct { - pub const base_address = 0x40001c00; - - /// address: 0x40001c00 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x40001c0c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40001c10 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40001c14 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40001c18 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40001c18 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40001c20 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40001c24 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001c28 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x40001c2c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40001c34 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - pub const TIM14 = struct { - pub const base_address = 0x40002000; - - /// address: 0x40002000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4000200c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40002010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40002014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40002018 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40002018 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40002020 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40002024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40002028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000202c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40002034 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - }; - - /// General-purpose-timers - pub const TIM11 = struct { - pub const base_address = 0x40014800; - - /// address: 0x40014800 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Auto-reload preload enable - ARPE: u1, - /// Clock division - CKD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - - /// address: 0x4001480c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - /// Capture/Compare 1 interrupt - /// enable - CC1IE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0xc); - - /// address: 0x40014810 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - /// Capture/compare 1 interrupt - /// flag - CC1IF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Capture/Compare 1 overcapture - /// flag - CC1OF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40014814 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - /// Capture/compare 1 - /// generation - CC1G: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x14); - - /// address: 0x40014818 - /// capture/compare mode register 1 (output - /// mode) - pub const CCMR1_Output = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Output Compare 1 fast - /// enable - OC1FE: u1, - /// Output Compare 1 preload - /// enable - OC1PE: u1, - /// Output Compare 1 mode - OC1M: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x18); - - /// address: 0x40014818 - /// capture/compare mode register 1 (input - /// mode) - pub const CCMR1_Input = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 - /// selection - CC1S: u2, - /// Input capture 1 prescaler - ICPCS: u2, - /// Input capture 1 filter - IC1F: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x18); - - /// address: 0x40014820 - /// capture/compare enable - /// register - pub const CCER = @intToPtr(*volatile Mmio(32, packed struct { - /// Capture/Compare 1 output - /// enable - CC1E: u1, - /// Capture/Compare 1 output - /// Polarity - CC1P: u1, - reserved0: u1, - /// Capture/Compare 1 output - /// Polarity - CC1NP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x20); - - /// address: 0x40014824 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40014828 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4001482c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - - /// address: 0x40014834 - /// capture/compare register 1 - pub const CCR1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x34); - - /// address: 0x40014850 - /// option register - pub const OR = @intToPtr(*volatile Mmio(32, packed struct { - /// Input 1 remapping - /// capability - RMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x50); - }; - - /// Basic timers - pub const TIM6 = struct { - pub const base_address = 0x40001000; - - /// address: 0x40001000 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001004 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000100c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001010 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001014 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001024 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001028 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000102c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - pub const TIM7 = struct { - pub const base_address = 0x40001400; - - /// address: 0x40001400 - /// control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - CEN: u1, - /// Update disable - UDIS: u1, - /// Update request source - URS: u1, - /// One-pulse mode - OPM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Auto-reload preload enable - ARPE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x0); - - /// address: 0x40001404 - /// control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Master mode selection - MMS: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x4); - - /// address: 0x4000140c - /// DMA/Interrupt enable register - pub const DIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt enable - UIE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Update DMA request enable - UDE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0xc); - - /// address: 0x40001410 - /// status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update interrupt flag - UIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x10); - - /// address: 0x40001414 - /// event generation register - pub const EGR = @intToPtr(*volatile Mmio(32, packed struct { - /// Update generation - UG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - padding30: u1, - }), base_address + 0x14); - - /// address: 0x40001424 - /// counter - pub const CNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); - - /// address: 0x40001428 - /// prescaler - pub const PSC = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x28); - - /// address: 0x4000142c - /// auto-reload register - pub const ARR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x2c); - }; - - /// Ethernet: media access control - /// (MAC) - pub const Ethernet_MAC = struct { - pub const base_address = 0x40028000; - - /// address: 0x40028000 - /// Ethernet MAC configuration - /// register - pub const MACCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// RE - RE: u1, - /// TE - TE: u1, - /// DC - DC: u1, - /// BL - BL: u2, - /// APCS - APCS: u1, - reserved2: u1, - /// RD - RD: u1, - /// IPCO - IPCO: u1, - /// DM - DM: u1, - /// LM - LM: u1, - /// ROD - ROD: u1, - /// FES - FES: u1, - reserved3: u1, - /// CSD - CSD: u1, - /// IFG - IFG: u3, - reserved4: u1, - reserved5: u1, - /// JD - JD: u1, - /// WD - WD: u1, - reserved6: u1, - /// CSTF - CSTF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40028004 - /// Ethernet MAC frame filter - /// register - pub const MACFFR = @intToPtr(*volatile Mmio(32, packed struct { - /// PM - PM: u1, - /// HU - HU: u1, - /// HM - HM: u1, - /// DAIF - DAIF: u1, - /// RAM - RAM: u1, - /// BFD - BFD: u1, - /// PCF - PCF: u1, - /// SAIF - SAIF: u1, - /// SAF - SAF: u1, - /// HPF - HPF: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// RA - RA: u1, - }), base_address + 0x4); - - /// address: 0x40028008 - /// Ethernet MAC hash table high - /// register - pub const MACHTHR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTH - HTH: u32, - }), base_address + 0x8); - - /// address: 0x4002800c - /// Ethernet MAC hash table low - /// register - pub const MACHTLR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTL - HTL: u32, - }), base_address + 0xc); - - /// address: 0x40028010 - /// Ethernet MAC MII address - /// register - pub const MACMIIAR = @intToPtr(*volatile Mmio(32, packed struct { - /// MB - MB: u1, - /// MW - MW: u1, - /// CR - CR: u3, - reserved0: u1, - /// MR - MR: u5, - /// PA - PA: u5, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x10); - - /// address: 0x40028014 - /// Ethernet MAC MII data register - pub const MACMIIDR = @intToPtr(*volatile Mmio(32, packed struct { - /// TD - TD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40028018 - /// Ethernet MAC flow control - /// register - pub const MACFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// FCB - FCB: u1, - /// TFCE - TFCE: u1, - /// RFCE - RFCE: u1, - /// UPFD - UPFD: u1, - /// PLT - PLT: u2, - reserved0: u1, - /// ZQPD - ZQPD: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// PT - PT: u16, - }), base_address + 0x18); - - /// address: 0x4002801c - /// Ethernet MAC VLAN tag register - pub const MACVLANTR = @intToPtr(*volatile Mmio(32, packed struct { - /// VLANTI - VLANTI: u16, - /// VLANTC - VLANTC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x4002802c - /// Ethernet MAC PMT control and status - /// register - pub const MACPMTCSR = @intToPtr(*volatile Mmio(32, packed struct { - /// PD - PD: u1, - /// MPE - MPE: u1, - /// WFE - WFE: u1, - reserved0: u1, - reserved1: u1, - /// MPR - MPR: u1, - /// WFR - WFR: u1, - reserved2: u1, - reserved3: u1, - /// GU - GU: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - /// WFFRPR - WFFRPR: u1, - }), base_address + 0x2c); - - /// address: 0x40028034 - /// Ethernet MAC debug register - pub const MACDBGR = @intToPtr(*volatile Mmio(32, packed struct { - /// CR - CR: u1, - /// CSR - CSR: u1, - /// ROR - ROR: u1, - /// MCF - MCF: u1, - /// MCP - MCP: u1, - /// MCFHP - MCFHP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x34); - - /// address: 0x40028038 - /// Ethernet MAC interrupt status - /// register - pub const MACSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// PMTS - PMTS: u1, - /// MMCS - MMCS: u1, - /// MMCRS - MMCRS: u1, - /// MMCTS - MMCTS: u1, - reserved3: u1, - reserved4: u1, - /// TSTS - TSTS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x38); - - /// address: 0x4002803c - /// Ethernet MAC interrupt mask - /// register - pub const MACIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// PMTIM - PMTIM: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// TSTIM - TSTIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x3c); - - /// address: 0x40028040 - /// Ethernet MAC address 0 high - /// register - pub const MACA0HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MAC address0 high - MACA0H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// Always 1 - MO: u1, - }), base_address + 0x40); - - /// address: 0x40028044 - /// Ethernet MAC address 0 low - /// register - pub const MACA0LR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 - MACA0L: u32, - }), base_address + 0x44); - - /// address: 0x40028048 - /// Ethernet MAC address 1 high - /// register - pub const MACA1HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA1H - MACA1H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x48); - - /// address: 0x4002804c - /// Ethernet MAC address1 low - /// register - pub const MACA1LR = @intToPtr(*volatile u32, base_address + 0x4c); - - /// address: 0x40028050 - /// Ethernet MAC address 2 high - /// register - pub const MACA2HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MAC2AH - MAC2AH: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x50); - - /// address: 0x40028054 - /// Ethernet MAC address 2 low - /// register - pub const MACA2LR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA2L - MACA2L: u31, - padding0: u1, - }), base_address + 0x54); - - /// address: 0x40028058 - /// Ethernet MAC address 3 high - /// register - pub const MACA3HR = @intToPtr(*volatile Mmio(32, packed struct { - /// MACA3H - MACA3H: u16, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// MBC - MBC: u6, - /// SA - SA: u1, - /// AE - AE: u1, - }), base_address + 0x58); - - /// address: 0x4002805c - /// Ethernet MAC address 3 low - /// register - pub const MACA3LR = @intToPtr(*volatile Mmio(32, packed struct { - /// MBCA3L - MBCA3L: u32, - }), base_address + 0x5c); - }; - - /// Ethernet: MAC management counters - pub const Ethernet_MMC = struct { - pub const base_address = 0x40028100; - - /// address: 0x40028100 - /// Ethernet MMC control register - pub const MMCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// CR - CR: u1, - /// CSR - CSR: u1, - /// ROR - ROR: u1, - /// MCF - MCF: u1, - /// MCP - MCP: u1, - /// MCFHP - MCFHP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x0); - - /// address: 0x40028104 - /// Ethernet MMC receive interrupt - /// register - pub const MMCRIR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RFCES - RFCES: u1, - /// RFAES - RFAES: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// RGUFS - RGUFS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x4); - - /// address: 0x40028108 - /// Ethernet MMC transmit interrupt - /// register - pub const MMCTIR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TGFSCS - TGFSCS: u1, - /// TGFMSCS - TGFMSCS: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// TGFS - TGFS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x4002810c - /// Ethernet MMC receive interrupt mask - /// register - pub const MMCRIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// RFCEM - RFCEM: u1, - /// RFAEM - RFAEM: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - /// RGUFM - RGUFM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0xc); - - /// address: 0x40028110 - /// Ethernet MMC transmit interrupt mask - /// register - pub const MMCTIMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// TGFSCM - TGFSCM: u1, - /// TGFMSCM - TGFMSCM: u1, - /// TGFM - TGFM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x10); - - /// address: 0x4002814c - /// Ethernet MMC transmitted good frames after a - /// single collision counter - pub const MMCTGFSCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TGFSCC - TGFSCC: u32, - }), base_address + 0x4c); - - /// address: 0x40028150 - /// Ethernet MMC transmitted good frames after - /// more than a single collision - pub const MMCTGFMSCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TGFMSCC - TGFMSCC: u32, - }), base_address + 0x50); - - /// address: 0x40028168 - /// Ethernet MMC transmitted good frames counter - /// register - pub const MMCTGFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTL - TGFC: u32, - }), base_address + 0x68); - - /// address: 0x40028194 - /// Ethernet MMC received frames with CRC error - /// counter register - pub const MMCRFCECR = @intToPtr(*volatile Mmio(32, packed struct { - /// RFCFC - RFCFC: u32, - }), base_address + 0x94); - - /// address: 0x40028198 - /// Ethernet MMC received frames with alignment - /// error counter register - pub const MMCRFAECR = @intToPtr(*volatile Mmio(32, packed struct { - /// RFAEC - RFAEC: u32, - }), base_address + 0x98); - - /// address: 0x400281c4 - /// MMC received good unicast frames counter - /// register - pub const MMCRGUFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// RGUFC - RGUFC: u32, - }), base_address + 0xc4); - }; - - /// Ethernet: Precision time protocol - pub const Ethernet_PTP = struct { - pub const base_address = 0x40028700; - - /// address: 0x40028700 - /// Ethernet PTP time stamp control - /// register - pub const PTPTSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSE - TSE: u1, - /// TSFCU - TSFCU: u1, - /// TSSTI - TSSTI: u1, - /// TSSTU - TSSTU: u1, - /// TSITE - TSITE: u1, - /// TTSARU - TTSARU: u1, - reserved0: u1, - reserved1: u1, - /// TSSARFE - TSSARFE: u1, - /// TSSSR - TSSSR: u1, - /// TSPTPPSV2E - TSPTPPSV2E: u1, - /// TSSPTPOEFE - TSSPTPOEFE: u1, - /// TSSIPV6FE - TSSIPV6FE: u1, - /// TSSIPV4FE - TSSIPV4FE: u1, - /// TSSEME - TSSEME: u1, - /// TSSMRME - TSSMRME: u1, - /// TSCNT - TSCNT: u2, - /// TSPFFMAE - TSPFFMAE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x0); - - /// address: 0x40028704 - /// Ethernet PTP subsecond increment - /// register - pub const PTPSSIR = @intToPtr(*volatile Mmio(32, packed struct { - /// STSSI - STSSI: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x4); - - /// address: 0x40028708 - /// Ethernet PTP time stamp high - /// register - pub const PTPTSHR = @intToPtr(*volatile Mmio(32, packed struct { - /// STS - STS: u32, - }), base_address + 0x8); - - /// address: 0x4002870c - /// Ethernet PTP time stamp low - /// register - pub const PTPTSLR = @intToPtr(*volatile Mmio(32, packed struct { - /// STSS - STSS: u31, - /// STPNS - STPNS: u1, - }), base_address + 0xc); - - /// address: 0x40028710 - /// Ethernet PTP time stamp high update - /// register - pub const PTPTSHUR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSUS - TSUS: u32, - }), base_address + 0x10); - - /// address: 0x40028714 - /// Ethernet PTP time stamp low update - /// register - pub const PTPTSLUR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSUSS - TSUSS: u31, - /// TSUSS - TSUPNS: u1, - }), base_address + 0x14); - - /// address: 0x40028718 - /// Ethernet PTP time stamp addend - /// register - pub const PTPTSAR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSA - TSA: u32, - }), base_address + 0x18); - - /// address: 0x4002871c - /// Ethernet PTP target time high - /// register - pub const PTPTTHR = @intToPtr(*volatile Mmio(32, packed struct { - /// 0 - TTSH: u32, - }), base_address + 0x1c); - - /// address: 0x40028720 - /// Ethernet PTP target time low - /// register - pub const PTPTTLR = @intToPtr(*volatile Mmio(32, packed struct { - /// TTSL - TTSL: u32, - }), base_address + 0x20); - - /// address: 0x40028728 - /// Ethernet PTP time stamp status - /// register - pub const PTPTSSR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x28); - - /// address: 0x4002872c - /// Ethernet PTP PPS control - /// register - pub const PTPPPSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// TSSO - TSSO: u1, - /// TSTTR - TSTTR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x2c); - }; - - /// Ethernet: DMA controller operation - pub const Ethernet_DMA = struct { - pub const base_address = 0x40029000; - - /// address: 0x40029000 - /// Ethernet DMA bus mode register - pub const DMABMR = @intToPtr(*volatile Mmio(32, packed struct { - /// SR - SR: u1, - /// DA - DA: u1, - /// DSL - DSL: u5, - /// EDFE - EDFE: u1, - /// PBL - PBL: u6, - /// RTPR - RTPR: u2, - /// FB - FB: u1, - /// RDP - RDP: u6, - /// USP - USP: u1, - /// FPM - FPM: u1, - /// AAB - AAB: u1, - /// MB - MB: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x0); - - /// address: 0x40029004 - /// Ethernet DMA transmit poll demand - /// register - pub const DMATPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// TPD - TPD: u32, - }), base_address + 0x4); - - /// address: 0x40029008 - /// EHERNET DMA receive poll demand - /// register - pub const DMARPDR = @intToPtr(*volatile Mmio(32, packed struct { - /// RPD - RPD: u32, - }), base_address + 0x8); - - /// address: 0x4002900c - /// Ethernet DMA receive descriptor list address - /// register - pub const DMARDLAR = @intToPtr(*volatile Mmio(32, packed struct { - /// SRL - SRL: u32, - }), base_address + 0xc); - - /// address: 0x40029010 - /// Ethernet DMA transmit descriptor list - /// address register - pub const DMATDLAR = @intToPtr(*volatile Mmio(32, packed struct { - /// STL - STL: u32, - }), base_address + 0x10); - - /// address: 0x40029014 - /// Ethernet DMA status register - pub const DMASR = @intToPtr(*volatile Mmio(32, packed struct { - /// TS - TS: u1, - /// TPSS - TPSS: u1, - /// TBUS - TBUS: u1, - /// TJTS - TJTS: u1, - /// ROS - ROS: u1, - /// TUS - TUS: u1, - /// RS - RS: u1, - /// RBUS - RBUS: u1, - /// RPSS - RPSS: u1, - /// PWTS - PWTS: u1, - /// ETS - ETS: u1, - reserved0: u1, - reserved1: u1, - /// FBES - FBES: u1, - /// ERS - ERS: u1, - /// AIS - AIS: u1, - /// NIS - NIS: u1, - /// RPS - RPS: u3, - /// TPS - TPS: u3, - /// EBS - EBS: u3, - reserved2: u1, - /// MMCS - MMCS: u1, - /// PMTS - PMTS: u1, - /// TSTS - TSTS: u1, - padding0: u1, - padding1: u1, - }), base_address + 0x14); - - /// address: 0x40029018 - /// Ethernet DMA operation mode - /// register - pub const DMAOMR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// SR - SR: u1, - /// OSF - OSF: u1, - /// RTC - RTC: u2, - reserved1: u1, - /// FUGF - FUGF: u1, - /// FEF - FEF: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// ST - ST: u1, - /// TTC - TTC: u3, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// FTF - FTF: u1, - /// TSF - TSF: u1, - reserved10: u1, - reserved11: u1, - /// DFRF - DFRF: u1, - /// RSF - RSF: u1, - /// DTCEFD - DTCEFD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x18); - - /// address: 0x4002901c - /// Ethernet DMA interrupt enable - /// register - pub const DMAIER = @intToPtr(*volatile Mmio(32, packed struct { - /// TIE - TIE: u1, - /// TPSIE - TPSIE: u1, - /// TBUIE - TBUIE: u1, - /// TJTIE - TJTIE: u1, - /// ROIE - ROIE: u1, - /// TUIE - TUIE: u1, - /// RIE - RIE: u1, - /// RBUIE - RBUIE: u1, - /// RPSIE - RPSIE: u1, - /// RWTIE - RWTIE: u1, - /// ETIE - ETIE: u1, - reserved0: u1, - reserved1: u1, - /// FBEIE - FBEIE: u1, - /// ERIE - ERIE: u1, - /// AISE - AISE: u1, - /// NISE - NISE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x1c); - - /// address: 0x40029020 - /// Ethernet DMA missed frame and buffer - /// overflow counter register - pub const DMAMFBOCR = @intToPtr(*volatile Mmio(32, packed struct { - /// MFC - MFC: u16, - /// OMFC - OMFC: u1, - /// MFA - MFA: u11, - /// OFOC - OFOC: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x20); - - /// address: 0x40029024 - /// Ethernet DMA receive status watchdog timer - /// register - pub const DMARSWTR = @intToPtr(*volatile Mmio(32, packed struct { - /// RSWTC - RSWTC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x24); - - /// address: 0x40029048 - /// Ethernet DMA current host transmit - /// descriptor register - pub const DMACHTDR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTDAP - HTDAP: u32, - }), base_address + 0x48); - - /// address: 0x4002904c - /// Ethernet DMA current host receive descriptor - /// register - pub const DMACHRDR = @intToPtr(*volatile Mmio(32, packed struct { - /// HRDAP - HRDAP: u32, - }), base_address + 0x4c); - - /// address: 0x40029050 - /// Ethernet DMA current host transmit buffer - /// address register - pub const DMACHTBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// HTBAP - HTBAP: u32, - }), base_address + 0x50); - - /// address: 0x40029054 - /// Ethernet DMA current host receive buffer - /// address register - pub const DMACHRBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// HRBAP - HRBAP: u32, - }), base_address + 0x54); - }; - - /// Cryptographic processor - pub const CRC = struct { - pub const base_address = 0x40023000; - - /// address: 0x40023000 - /// Data register - pub const DR = @intToPtr(*volatile u32, base_address + 0x0); - - /// address: 0x40023004 - /// Independent Data register - pub const IDR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x4); - - /// address: 0x40023008 - /// Control register - pub const CR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8); - }; - - /// USB on the go full speed - pub const OTG_FS_GLOBAL = struct { - pub const base_address = 0x50000000; - - /// address: 0x50000000 - /// OTG_FS control and status register - /// (OTG_FS_GOTGCTL) - pub const FS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Session request success - SRQSCS: u1, - /// Session request - SRQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Host negotiation success - HNGSCS: u1, - /// HNP request - HNPRQ: u1, - /// Host set HNP enable - HSHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Connector ID status - CIDSTS: u1, - /// Long/short debounce time - DBCT: u1, - /// A-session valid - ASVLD: u1, - /// B-session valid - BSVLD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x50000004 - /// OTG_FS interrupt register - /// (OTG_FS_GOTGINT) - pub const FS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Session end detected - SEDET: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Session request success status - /// change - SRSSCHG: u1, - /// Host negotiation success status - /// change - HNSSCHG: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Host negotiation detected - HNGDET: u1, - /// A-device timeout change - ADTOCHG: u1, - /// Debounce done - DBCDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x50000008 - /// OTG_FS AHB configuration register - /// (OTG_FS_GAHBCFG) - pub const FS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt mask - GINT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TxFIFO empty level - TXFELVL: u1, - /// Periodic TxFIFO empty - /// level - PTXFELVL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x5000000c - /// OTG_FS USB configuration register - /// (OTG_FS_GUSBCFG) - pub const FS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS timeout calibration - TOCAL: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Full Speed serial transceiver - /// select - PHYSEL: u1, - reserved3: u1, - /// SRP-capable - SRPCAP: u1, - /// HNP-capable - HNPCAP: u1, - /// USB turnaround time - TRDT: u4, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - /// Force host mode - FHMOD: u1, - /// Force device mode - FDMOD: u1, - /// Corrupt Tx packet - CTXPKT: u1, - }), base_address + 0xc); - - /// address: 0x50000010 - /// OTG_FS reset register - /// (OTG_FS_GRSTCTL) - pub const FS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HSRST: u1, - /// Host frame counter reset - FCRST: u1, - reserved0: u1, - /// RxFIFO flush - RXFFLSH: u1, - /// TxFIFO flush - TXFFLSH: u1, - /// TxFIFO number - TXFNUM: u5, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// AHB master idle - AHBIDL: u1, - }), base_address + 0x10); - - /// address: 0x50000014 - /// OTG_FS core interrupt register - /// (OTG_FS_GINTSTS) - pub const FS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Current mode of operation - CMOD: u1, - /// Mode mismatch interrupt - MMIS: u1, - /// OTG interrupt - OTGINT: u1, - /// Start of frame - SOF: u1, - /// RxFIFO non-empty - RXFLVL: u1, - /// Non-periodic TxFIFO empty - NPTXFE: u1, - /// Global IN non-periodic NAK - /// effective - GINAKEFF: u1, - /// Global OUT NAK effective - GOUTNAKEFF: u1, - reserved0: u1, - reserved1: u1, - /// Early suspend - ESUSP: u1, - /// USB suspend - USBSUSP: u1, - /// USB reset - USBRST: u1, - /// Enumeration done - ENUMDNE: u1, - /// Isochronous OUT packet dropped - /// interrupt - ISOODRP: u1, - /// End of periodic frame - /// interrupt - EOPF: u1, - reserved2: u1, - reserved3: u1, - /// IN endpoint interrupt - IEPINT: u1, - /// OUT endpoint interrupt - OEPINT: u1, - /// Incomplete isochronous IN - /// transfer - IISOIXFR: u1, - /// Incomplete periodic transfer(Host - /// mode)/Incomplete isochronous OUT transfer(Device - /// mode) - IPXFR_INCOMPISOOUT: u1, - reserved4: u1, - reserved5: u1, - /// Host port interrupt - HPRTINT: u1, - /// Host channels interrupt - HCINT: u1, - /// Periodic TxFIFO empty - PTXFE: u1, - reserved6: u1, - /// Connector ID status change - CIDSCHG: u1, - /// Disconnect detected - /// interrupt - DISCINT: u1, - /// Session request/new session detected - /// interrupt - SRQINT: u1, - /// Resume/remote wakeup detected - /// interrupt - WKUPINT: u1, - }), base_address + 0x14); - - /// address: 0x50000018 - /// OTG_FS interrupt mask register - /// (OTG_FS_GINTMSK) - pub const FS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Mode mismatch interrupt - /// mask - MMISM: u1, - /// OTG interrupt mask - OTGINT: u1, - /// Start of frame mask - SOFM: u1, - /// Receive FIFO non-empty - /// mask - RXFLVLM: u1, - /// Non-periodic TxFIFO empty - /// mask - NPTXFEM: u1, - /// Global non-periodic IN NAK effective - /// mask - GINAKEFFM: u1, - /// Global OUT NAK effective - /// mask - GONAKEFFM: u1, - reserved1: u1, - reserved2: u1, - /// Early suspend mask - ESUSPM: u1, - /// USB suspend mask - USBSUSPM: u1, - /// USB reset mask - USBRST: u1, - /// Enumeration done mask - ENUMDNEM: u1, - /// Isochronous OUT packet dropped interrupt - /// mask - ISOODRPM: u1, - /// End of periodic frame interrupt - /// mask - EOPFM: u1, - reserved3: u1, - /// Endpoint mismatch interrupt - /// mask - EPMISM: u1, - /// IN endpoints interrupt - /// mask - IEPINT: u1, - /// OUT endpoints interrupt - /// mask - OEPINT: u1, - /// Incomplete isochronous IN transfer - /// mask - IISOIXFRM: u1, - /// Incomplete periodic transfer mask(Host - /// mode)/Incomplete isochronous OUT transfer mask(Device - /// mode) - IPXFRM_IISOOXFRM: u1, - reserved4: u1, - reserved5: u1, - /// Host port interrupt mask - PRTIM: u1, - /// Host channels interrupt - /// mask - HCIM: u1, - /// Periodic TxFIFO empty mask - PTXFEM: u1, - reserved6: u1, - /// Connector ID status change - /// mask - CIDSCHGM: u1, - /// Disconnect detected interrupt - /// mask - DISCINT: u1, - /// Session request/new session detected - /// interrupt mask - SRQIM: u1, - /// Resume/remote wakeup detected interrupt - /// mask - WUIM: u1, - }), base_address + 0x18); - - /// address: 0x5000001c - /// OTG_FS Receive status debug read(Device - /// mode) - pub const FS_GRXSTSR_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x5000001c - /// OTG_FS Receive status debug - /// read(Hostmode) - pub const FS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x50000024 - /// OTG_FS Receive FIFO size register - /// (OTG_FS_GRXFSIZ) - pub const FS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// RxFIFO depth - RXFD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x50000028 - /// OTG_FS non-periodic transmit FIFO size - /// register (Device mode) - pub const FS_GNPTXFSIZ_Device = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint 0 transmit RAM start - /// address - TX0FSA: u16, - /// Endpoint 0 TxFIFO depth - TX0FD: u16, - }), base_address + 0x28); - - /// address: 0x50000028 - /// OTG_FS non-periodic transmit FIFO size - /// register (Host mode) - pub const FS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-periodic transmit RAM start - /// address - NPTXFSA: u16, - /// Non-periodic TxFIFO depth - NPTXFD: u16, - }), base_address + 0x28); - - /// address: 0x5000002c - /// OTG_FS non-periodic transmit FIFO/queue - /// status register (OTG_FS_GNPTXSTS) - pub const FS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Non-periodic TxFIFO space - /// available - NPTXFSAV: u16, - /// Non-periodic transmit request queue - /// space available - NPTQXSAV: u8, - /// Top of the non-periodic transmit request - /// queue - NPTXQTOP: u7, - padding0: u1, - }), base_address + 0x2c); - - /// address: 0x50000038 - /// OTG_FS general core configuration register - /// (OTG_FS_GCCFG) - pub const FS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Power down - PWRDWN: u1, - reserved16: u1, - /// Enable the VBUS sensing - /// device - VBUSASEN: u1, - /// Enable the VBUS sensing - /// device - VBUSBSEN: u1, - /// SOF output enable - SOFOUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x38); - - /// address: 0x5000003c - /// core ID register - pub const FS_CID = @intToPtr(*volatile Mmio(32, packed struct { - /// Product ID field - PRODUCT_ID: u32, - }), base_address + 0x3c); - - /// address: 0x50000100 - /// OTG_FS Host periodic transmit FIFO size - /// register (OTG_FS_HPTXFSIZ) - pub const FS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// Host periodic TxFIFO start - /// address - PTXSA: u16, - /// Host periodic TxFIFO depth - PTXFSIZ: u16, - }), base_address + 0x100); - - /// address: 0x50000104 - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF2) - pub const FS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO2 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x104); - - /// address: 0x50000108 - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF3) - pub const FS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO3 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x108); - - /// address: 0x5000010c - /// OTG_FS device IN endpoint transmit FIFO size - /// register (OTG_FS_DIEPTXF4) - pub const FS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFO4 transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x10c); - }; - - /// USB on the go full speed - pub const OTG_FS_HOST = struct { - pub const base_address = 0x50000400; - - /// address: 0x50000400 - /// OTG_FS host configuration register - /// (OTG_FS_HCFG) - pub const FS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS/LS PHY clock select - FSLSPCS: u2, - /// FS- and LS-only support - FSLSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x50000404 - /// OTG_FS Host frame interval - /// register - pub const HFIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interval - FRIVL: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x50000408 - /// OTG_FS host frame number/frame time - /// remaining register (OTG_FS_HFNUM) - pub const FS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FRNUM: u16, - /// Frame time remaining - FTREM: u16, - }), base_address + 0x8); - - /// address: 0x50000410 - /// OTG_FS_Host periodic transmit FIFO/queue - /// status register (OTG_FS_HPTXSTS) - pub const FS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic transmit data FIFO space - /// available - PTXFSAVL: u16, - /// Periodic transmit request queue space - /// available - PTXQSAV: u8, - /// Top of the periodic transmit request - /// queue - PTXQTOP: u8, - }), base_address + 0x10); - - /// address: 0x50000414 - /// OTG_FS Host all channels interrupt - /// register - pub const HAINT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); - - /// address: 0x50000418 - /// OTG_FS host all channels interrupt mask - /// register - pub const HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupt mask - HAINTM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x50000440 - /// OTG_FS host port control and status register - /// (OTG_FS_HPRT) - pub const FS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port connect status - PCSTS: u1, - /// Port connect detected - PCDET: u1, - /// Port enable - PENA: u1, - /// Port enable/disable change - PENCHNG: u1, - /// Port overcurrent active - POCA: u1, - /// Port overcurrent change - POCCHNG: u1, - /// Port resume - PRES: u1, - /// Port suspend - PSUSP: u1, - /// Port reset - PRST: u1, - reserved0: u1, - /// Port line status - PLSTS: u2, - /// Port power - PPWR: u1, - /// Port test control - PTCTL: u4, - /// Port speed - PSPD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x50000500 - /// OTG_FS host channel-0 characteristics - /// register (OTG_FS_HCCHAR0) - pub const FS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x100); - - /// address: 0x50000520 - /// OTG_FS host channel-1 characteristics - /// register (OTG_FS_HCCHAR1) - pub const FS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x120); - - /// address: 0x50000540 - /// OTG_FS host channel-2 characteristics - /// register (OTG_FS_HCCHAR2) - pub const FS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x140); - - /// address: 0x50000560 - /// OTG_FS host channel-3 characteristics - /// register (OTG_FS_HCCHAR3) - pub const FS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x160); - - /// address: 0x50000580 - /// OTG_FS host channel-4 characteristics - /// register (OTG_FS_HCCHAR4) - pub const FS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x180); - - /// address: 0x500005a0 - /// OTG_FS host channel-5 characteristics - /// register (OTG_FS_HCCHAR5) - pub const FS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1a0); - - /// address: 0x500005c0 - /// OTG_FS host channel-6 characteristics - /// register (OTG_FS_HCCHAR6) - pub const FS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1c0); - - /// address: 0x500005e0 - /// OTG_FS host channel-7 characteristics - /// register (OTG_FS_HCCHAR7) - pub const FS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multicount - MCNT: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1e0); - - /// address: 0x50000508 - /// OTG_FS host channel-0 interrupt register - /// (OTG_FS_HCINT0) - pub const FS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x108); - - /// address: 0x50000528 - /// OTG_FS host channel-1 interrupt register - /// (OTG_FS_HCINT1) - pub const FS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x128); - - /// address: 0x50000548 - /// OTG_FS host channel-2 interrupt register - /// (OTG_FS_HCINT2) - pub const FS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x148); - - /// address: 0x50000568 - /// OTG_FS host channel-3 interrupt register - /// (OTG_FS_HCINT3) - pub const FS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x168); - - /// address: 0x50000588 - /// OTG_FS host channel-4 interrupt register - /// (OTG_FS_HCINT4) - pub const FS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x188); - - /// address: 0x500005a8 - /// OTG_FS host channel-5 interrupt register - /// (OTG_FS_HCINT5) - pub const FS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1a8); - - /// address: 0x500005c8 - /// OTG_FS host channel-6 interrupt register - /// (OTG_FS_HCINT6) - pub const FS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c8); - - /// address: 0x500005e8 - /// OTG_FS host channel-7 interrupt register - /// (OTG_FS_HCINT7) - pub const FS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - reserved0: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - reserved1: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1e8); - - /// address: 0x5000050c - /// OTG_FS host channel-0 mask register - /// (OTG_FS_HCINTMSK0) - pub const FS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10c); - - /// address: 0x5000052c - /// OTG_FS host channel-1 mask register - /// (OTG_FS_HCINTMSK1) - pub const FS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x12c); - - /// address: 0x5000054c - /// OTG_FS host channel-2 mask register - /// (OTG_FS_HCINTMSK2) - pub const FS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14c); - - /// address: 0x5000056c - /// OTG_FS host channel-3 mask register - /// (OTG_FS_HCINTMSK3) - pub const FS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x16c); - - /// address: 0x5000058c - /// OTG_FS host channel-4 mask register - /// (OTG_FS_HCINTMSK4) - pub const FS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18c); - - /// address: 0x500005ac - /// OTG_FS host channel-5 mask register - /// (OTG_FS_HCINTMSK5) - pub const FS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ac); - - /// address: 0x500005cc - /// OTG_FS host channel-6 mask register - /// (OTG_FS_HCINTMSK6) - pub const FS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1cc); - - /// address: 0x500005ec - /// OTG_FS host channel-7 mask register - /// (OTG_FS_HCINTMSK7) - pub const FS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - reserved0: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ec); - - /// address: 0x50000510 - /// OTG_FS host channel-0 transfer size - /// register - pub const FS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x110); - - /// address: 0x50000530 - /// OTG_FS host channel-1 transfer size - /// register - pub const FS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000550 - /// OTG_FS host channel-2 transfer size - /// register - pub const FS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000570 - /// OTG_FS host channel-3 transfer size - /// register - pub const FS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000590 - /// OTG_FS host channel-x transfer size - /// register - pub const FS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x500005b0 - /// OTG_FS host channel-5 transfer size - /// register - pub const FS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x500005d0 - /// OTG_FS host channel-6 transfer size - /// register - pub const FS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1d0); - - /// address: 0x500005f0 - /// OTG_FS host channel-7 transfer size - /// register - pub const FS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1f0); - }; - - /// USB on the go full speed - pub const OTG_FS_DEVICE = struct { - pub const base_address = 0x50000800; - - /// address: 0x50000800 - /// OTG_FS device configuration register - /// (OTG_FS_DCFG) - pub const FS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Device speed - DSPD: u2, - /// Non-zero-length status OUT - /// handshake - NZLSOHSK: u1, - reserved0: u1, - /// Device address - DAD: u7, - /// Periodic frame interval - PFIVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x0); - - /// address: 0x50000804 - /// OTG_FS device control register - /// (OTG_FS_DCTL) - pub const FS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Remote wakeup signaling - RWUSIG: u1, - /// Soft disconnect - SDIS: u1, - /// Global IN NAK status - GINSTS: u1, - /// Global OUT NAK status - GONSTS: u1, - /// Test control - TCTL: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on programming done - POPRGDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x50000808 - /// OTG_FS device status register - /// (OTG_FS_DSTS) - pub const FS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Suspend status - SUSPSTS: u1, - /// Enumerated speed - ENUMSPD: u2, - /// Erratic error - EERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Frame number of the received - /// SOF - FNSOF: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x50000810 - /// OTG_FS device IN endpoint common interrupt - /// mask register (OTG_FS_DIEPMSK) - pub const FS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (Non-isochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x10); - - /// address: 0x50000814 - /// OTG_FS device OUT endpoint common interrupt - /// mask register (OTG_FS_DOEPMSK) - pub const FS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// SETUP phase done mask - STUPM: u1, - /// OUT token received when endpoint - /// disabled mask - OTEPDM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x14); - - /// address: 0x50000818 - /// OTG_FS device all endpoints interrupt - /// register (OTG_FS_DAINT) - pub const FS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint interrupt bits - IEPINT: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x18); - - /// address: 0x5000081c - /// OTG_FS all endpoints interrupt mask register - /// (OTG_FS_DAINTMSK) - pub const FS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP interrupt mask bits - IEPM: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x1c); - - /// address: 0x50000828 - /// OTG_FS device VBUS discharge time - /// register - pub const DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS discharge time - VBUSDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x5000082c - /// OTG_FS device VBUS pulsing time - /// register - pub const DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS pulsing time - DVBUSP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x50000834 - /// OTG_FS device IN endpoint FIFO empty - /// interrupt mask register - pub const DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP Tx FIFO empty interrupt mask - /// bits - INEPTXFEM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x50000900 - /// OTG_FS device control IN endpoint 0 control - /// register (OTG_FS_DIEPCTL0) - pub const FS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USB active endpoint - USBAEP: u1, - reserved13: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved14: u1, - /// STALL handshake - STALL: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved15: u1, - reserved16: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x100); - - /// address: 0x50000920 - /// OTG device endpoint-1 control - /// register - pub const DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM/SD1PID - SODDFRM_SD1PID: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x120); - - /// address: 0x50000940 - /// OTG device endpoint-2 control - /// register - pub const DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x140); - - /// address: 0x50000960 - /// OTG device endpoint-3 control - /// register - pub const DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - reserved4: u1, - /// Stall - Stall: u1, - /// TXFNUM - TXFNUM: u4, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x160); - - /// address: 0x50000b00 - /// device endpoint-0 control - /// register - pub const DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USBAEP - USBAEP: u1, - reserved13: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - reserved18: u1, - reserved19: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x300); - - /// address: 0x50000b20 - /// device endpoint-1 control - /// register - pub const DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x320); - - /// address: 0x50000b40 - /// device endpoint-2 control - /// register - pub const DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x340); - - /// address: 0x50000b60 - /// device endpoint-3 control - /// register - pub const DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// MPSIZ - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USBAEP - USBAEP: u1, - /// EONUM/DPID - EONUM_DPID: u1, - /// NAKSTS - NAKSTS: u1, - /// EPTYP - EPTYP: u2, - /// SNPM - SNPM: u1, - /// Stall - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// CNAK - CNAK: u1, - /// SNAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVNFRM: u1, - /// SODDFRM - SODDFRM: u1, - /// EPDIS - EPDIS: u1, - /// EPENA - EPENA: u1, - }), base_address + 0x360); - - /// address: 0x50000908 - /// device endpoint-x interrupt - /// register - pub const DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x108); - - /// address: 0x50000928 - /// device endpoint-1 interrupt - /// register - pub const DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x128); - - /// address: 0x50000948 - /// device endpoint-2 interrupt - /// register - pub const DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x148); - - /// address: 0x50000968 - /// device endpoint-3 interrupt - /// register - pub const DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// TOC - TOC: u1, - /// ITTXFE - ITTXFE: u1, - reserved1: u1, - /// INEPNE - INEPNE: u1, - /// TXFE - TXFE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x168); - - /// address: 0x50000b08 - /// device endpoint-0 interrupt - /// register - pub const DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x308); - - /// address: 0x50000b28 - /// device endpoint-1 interrupt - /// register - pub const DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x328); - - /// address: 0x50000b48 - /// device endpoint-2 interrupt - /// register - pub const DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x348); - - /// address: 0x50000b68 - /// device endpoint-3 interrupt - /// register - pub const DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// XFRC - XFRC: u1, - /// EPDISD - EPDISD: u1, - reserved0: u1, - /// STUP - STUP: u1, - /// OTEPDIS - OTEPDIS: u1, - reserved1: u1, - /// B2BSTUP - B2BSTUP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x368); - - /// address: 0x50000910 - /// device endpoint-0 transfer size - /// register - pub const DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x110); - - /// address: 0x50000b10 - /// device OUT endpoint-0 transfer size - /// register - pub const DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// SETUP packet count - STUPCNT: u2, - padding0: u1, - }), base_address + 0x310); - - /// address: 0x50000930 - /// device endpoint-1 transfer size - /// register - pub const DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x50000950 - /// device endpoint-2 transfer size - /// register - pub const DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x50000970 - /// device endpoint-3 transfer size - /// register - pub const DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x50000918 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x118); - - /// address: 0x50000938 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x138); - - /// address: 0x50000958 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x158); - - /// address: 0x50000978 - /// OTG_FS device IN endpoint transmit FIFO - /// status register - pub const DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// available - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x178); - - /// address: 0x50000b30 - /// device OUT endpoint-1 transfer size - /// register - pub const DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x330); - - /// address: 0x50000b50 - /// device OUT endpoint-2 transfer size - /// register - pub const DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x350); - - /// address: 0x50000b70 - /// device OUT endpoint-3 transfer size - /// register - pub const DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x370); - }; - - /// USB on the go full speed - pub const OTG_FS_PWRCLK = struct { - pub const base_address = 0x50000e00; - - /// address: 0x50000e00 - /// OTG_FS power and clock gating control - /// register (OTG_FS_PCGCCTL) - pub const FS_PCGCCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop PHY clock - STPPCLK: u1, - /// Gate HCLK - GATEHCLK: u1, - reserved0: u1, - reserved1: u1, - /// PHY Suspended - PHYSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - }; - - /// Controller area network - pub const CAN1 = struct { - pub const base_address = 0x40006400; - - /// address: 0x40006400 - /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006404 - /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006408 - /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000640c - /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006410 - /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006414 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006418 - /// interrupt enable register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000641c - /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006580 - /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006584 - /// mailbox data length control and time stamp - /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006588 - /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000658c - /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006590 - /// mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006594 - /// mailbox data length control and time stamp - /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006598 - /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000659c - /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400065a0 - /// mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400065a4 - /// mailbox data length control and time stamp - /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400065a8 - /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400065ac - /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400065b0 - /// receive FIFO mailbox identifier - /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400065b4 - /// mailbox data high register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400065b8 - /// mailbox data high register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400065bc - /// receive FIFO mailbox data high - /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400065c0 - /// mailbox data high register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400065c4 - /// mailbox data high register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400065c8 - /// mailbox data high register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400065cc - /// mailbox data high register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006600 - /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// FINIT - FINIT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// CAN2SB - CAN2SB: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006604 - /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - /// Filter mode - FBM14: u1, - /// Filter mode - FBM15: u1, - /// Filter mode - FBM16: u1, - /// Filter mode - FBM17: u1, - /// Filter mode - FBM18: u1, - /// Filter mode - FBM19: u1, - /// Filter mode - FBM20: u1, - /// Filter mode - FBM21: u1, - /// Filter mode - FBM22: u1, - /// Filter mode - FBM23: u1, - /// Filter mode - FBM24: u1, - /// Filter mode - FBM25: u1, - /// Filter mode - FBM26: u1, - /// Filter mode - FBM27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x4000660c - /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - /// Filter scale configuration - FSC14: u1, - /// Filter scale configuration - FSC15: u1, - /// Filter scale configuration - FSC16: u1, - /// Filter scale configuration - FSC17: u1, - /// Filter scale configuration - FSC18: u1, - /// Filter scale configuration - FSC19: u1, - /// Filter scale configuration - FSC20: u1, - /// Filter scale configuration - FSC21: u1, - /// Filter scale configuration - FSC22: u1, - /// Filter scale configuration - FSC23: u1, - /// Filter scale configuration - FSC24: u1, - /// Filter scale configuration - FSC25: u1, - /// Filter scale configuration - FSC26: u1, - /// Filter scale configuration - FSC27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006614 - /// filter FIFO assignment - /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - /// Filter FIFO assignment for filter - /// 14 - FFA14: u1, - /// Filter FIFO assignment for filter - /// 15 - FFA15: u1, - /// Filter FIFO assignment for filter - /// 16 - FFA16: u1, - /// Filter FIFO assignment for filter - /// 17 - FFA17: u1, - /// Filter FIFO assignment for filter - /// 18 - FFA18: u1, - /// Filter FIFO assignment for filter - /// 19 - FFA19: u1, - /// Filter FIFO assignment for filter - /// 20 - FFA20: u1, - /// Filter FIFO assignment for filter - /// 21 - FFA21: u1, - /// Filter FIFO assignment for filter - /// 22 - FFA22: u1, - /// Filter FIFO assignment for filter - /// 23 - FFA23: u1, - /// Filter FIFO assignment for filter - /// 24 - FFA24: u1, - /// Filter FIFO assignment for filter - /// 25 - FFA25: u1, - /// Filter FIFO assignment for filter - /// 26 - FFA26: u1, - /// Filter FIFO assignment for filter - /// 27 - FFA27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x4000661c - /// filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - /// Filter active - FACT14: u1, - /// Filter active - FACT15: u1, - /// Filter active - FACT16: u1, - /// Filter active - FACT17: u1, - /// Filter active - FACT18: u1, - /// Filter active - FACT19: u1, - /// Filter active - FACT20: u1, - /// Filter active - FACT21: u1, - /// Filter active - FACT22: u1, - /// Filter active - FACT23: u1, - /// Filter active - FACT24: u1, - /// Filter active - FACT25: u1, - /// Filter active - FACT26: u1, - /// Filter active - FACT27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006640 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006644 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006648 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x4000664c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006650 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006654 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006658 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x4000665c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006660 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006664 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006668 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x4000666c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006670 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006674 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006678 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x4000667c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006680 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006684 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006688 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x4000668c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006690 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006694 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006698 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x4000669c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x400066a0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x400066a4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x400066a8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x400066ac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - - /// address: 0x400066b0 - /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b0); - - /// address: 0x400066b4 - /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b4); - - /// address: 0x400066b8 - /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b8); - - /// address: 0x400066bc - /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2bc); - - /// address: 0x400066c0 - /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c0); - - /// address: 0x400066c4 - /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c4); - - /// address: 0x400066c8 - /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c8); - - /// address: 0x400066cc - /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2cc); - - /// address: 0x400066d0 - /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d0); - - /// address: 0x400066d4 - /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d4); - - /// address: 0x400066d8 - /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d8); - - /// address: 0x400066dc - /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2dc); - - /// address: 0x400066e0 - /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e0); - - /// address: 0x400066e4 - /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e4); - - /// address: 0x400066e8 - /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e8); - - /// address: 0x400066ec - /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ec); - - /// address: 0x400066f0 - /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f0); - - /// address: 0x400066f4 - /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f4); - - /// address: 0x400066f8 - /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f8); - - /// address: 0x400066fc - /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006700 - /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x300); - - /// address: 0x40006704 - /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x304); - - /// address: 0x40006708 - /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x308); - - /// address: 0x4000670c - /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x30c); - - /// address: 0x40006710 - /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x310); - - /// address: 0x40006714 - /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x314); - - /// address: 0x40006718 - /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x318); - - /// address: 0x4000671c - /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x31c); - }; - pub const CAN2 = struct { - pub const base_address = 0x40006800; - - /// address: 0x40006800 - /// master control register - pub const MCR = @intToPtr(*volatile Mmio(32, packed struct { - /// INRQ - INRQ: u1, - /// SLEEP - SLEEP: u1, - /// TXFP - TXFP: u1, - /// RFLM - RFLM: u1, - /// NART - NART: u1, - /// AWUM - AWUM: u1, - /// ABOM - ABOM: u1, - /// TTCM - TTCM: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// RESET - RESET: u1, - /// DBF - DBF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0x40006804 - /// master status register - pub const MSR = @intToPtr(*volatile Mmio(32, packed struct { - /// INAK - INAK: u1, - /// SLAK - SLAK: u1, - /// ERRI - ERRI: u1, - /// WKUI - WKUI: u1, - /// SLAKI - SLAKI: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// TXM - TXM: u1, - /// RXM - RXM: u1, - /// SAMP - SAMP: u1, - /// RX - RX: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40006808 - /// transmit status register - pub const TSR = @intToPtr(*volatile Mmio(32, packed struct { - /// RQCP0 - RQCP0: u1, - /// TXOK0 - TXOK0: u1, - /// ALST0 - ALST0: u1, - /// TERR0 - TERR0: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// ABRQ0 - ABRQ0: u1, - /// RQCP1 - RQCP1: u1, - /// TXOK1 - TXOK1: u1, - /// ALST1 - ALST1: u1, - /// TERR1 - TERR1: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// ABRQ1 - ABRQ1: u1, - /// RQCP2 - RQCP2: u1, - /// TXOK2 - TXOK2: u1, - /// ALST2 - ALST2: u1, - /// TERR2 - TERR2: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ABRQ2 - ABRQ2: u1, - /// CODE - CODE: u2, - /// Lowest priority flag for mailbox - /// 0 - TME0: u1, - /// Lowest priority flag for mailbox - /// 1 - TME1: u1, - /// Lowest priority flag for mailbox - /// 2 - TME2: u1, - /// Lowest priority flag for mailbox - /// 0 - LOW0: u1, - /// Lowest priority flag for mailbox - /// 1 - LOW1: u1, - /// Lowest priority flag for mailbox - /// 2 - LOW2: u1, - }), base_address + 0x8); - - /// address: 0x4000680c - /// receive FIFO 0 register - pub const RF0R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP0 - FMP0: u2, - reserved0: u1, - /// FULL0 - FULL0: u1, - /// FOVR0 - FOVR0: u1, - /// RFOM0 - RFOM0: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0xc); - - /// address: 0x40006810 - /// receive FIFO 1 register - pub const RF1R = @intToPtr(*volatile Mmio(32, packed struct { - /// FMP1 - FMP1: u2, - reserved0: u1, - /// FULL1 - FULL1: u1, - /// FOVR1 - FOVR1: u1, - /// RFOM1 - RFOM1: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x10); - - /// address: 0x40006814 - /// interrupt enable register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// TMEIE - TMEIE: u1, - /// FMPIE0 - FMPIE0: u1, - /// FFIE0 - FFIE0: u1, - /// FOVIE0 - FOVIE0: u1, - /// FMPIE1 - FMPIE1: u1, - /// FFIE1 - FFIE1: u1, - /// FOVIE1 - FOVIE1: u1, - reserved0: u1, - /// EWGIE - EWGIE: u1, - /// EPVIE - EPVIE: u1, - /// BOFIE - BOFIE: u1, - /// LECIE - LECIE: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// ERRIE - ERRIE: u1, - /// WKUIE - WKUIE: u1, - /// SLKIE - SLKIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x14); - - /// address: 0x40006818 - /// interrupt enable register - pub const ESR = @intToPtr(*volatile Mmio(32, packed struct { - /// EWGF - EWGF: u1, - /// EPVF - EPVF: u1, - /// BOFF - BOFF: u1, - reserved0: u1, - /// LEC - LEC: u3, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// TEC - TEC: u8, - /// REC - REC: u8, - }), base_address + 0x18); - - /// address: 0x4000681c - /// bit timing register - pub const BTR = @intToPtr(*volatile Mmio(32, packed struct { - /// BRP - BRP: u10, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// TS1 - TS1: u4, - /// TS2 - TS2: u3, - reserved6: u1, - /// SJW - SJW: u2, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// LBKM - LBKM: u1, - /// SILM - SILM: u1, - }), base_address + 0x1c); - - /// address: 0x40006980 - /// TX mailbox identifier register - pub const TI0R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x180); - - /// address: 0x40006984 - /// mailbox data length control and time stamp - /// register - pub const TDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x184); - - /// address: 0x40006988 - /// mailbox data low register - pub const TDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x188); - - /// address: 0x4000698c - /// mailbox data high register - pub const TDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x18c); - - /// address: 0x40006990 - /// mailbox identifier register - pub const TI1R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x190); - - /// address: 0x40006994 - /// mailbox data length control and time stamp - /// register - pub const TDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x194); - - /// address: 0x40006998 - /// mailbox data low register - pub const TDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x198); - - /// address: 0x4000699c - /// mailbox data high register - pub const TDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x19c); - - /// address: 0x400069a0 - /// mailbox identifier register - pub const TI2R = @intToPtr(*volatile Mmio(32, packed struct { - /// TXRQ - TXRQ: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1a0); - - /// address: 0x400069a4 - /// mailbox data length control and time stamp - /// register - pub const TDT2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// TGT - TGT: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - /// TIME - TIME: u16, - }), base_address + 0x1a4); - - /// address: 0x400069a8 - /// mailbox data low register - pub const TDL2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1a8); - - /// address: 0x400069ac - /// mailbox data high register - pub const TDH2R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1ac); - - /// address: 0x400069b0 - /// receive FIFO mailbox identifier - /// register - pub const RI0R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1b0); - - /// address: 0x400069b4 - /// mailbox data high register - pub const RDT0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1b4); - - /// address: 0x400069b8 - /// mailbox data high register - pub const RDL0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1b8); - - /// address: 0x400069bc - /// receive FIFO mailbox data high - /// register - pub const RDH0R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1bc); - - /// address: 0x400069c0 - /// mailbox data high register - pub const RI1R = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// RTR - RTR: u1, - /// IDE - IDE: u1, - /// EXID - EXID: u18, - /// STID - STID: u11, - }), base_address + 0x1c0); - - /// address: 0x400069c4 - /// mailbox data high register - pub const RDT1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DLC - DLC: u4, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// FMI - FMI: u8, - /// TIME - TIME: u16, - }), base_address + 0x1c4); - - /// address: 0x400069c8 - /// mailbox data high register - pub const RDL1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA0 - DATA0: u8, - /// DATA1 - DATA1: u8, - /// DATA2 - DATA2: u8, - /// DATA3 - DATA3: u8, - }), base_address + 0x1c8); - - /// address: 0x400069cc - /// mailbox data high register - pub const RDH1R = @intToPtr(*volatile Mmio(32, packed struct { - /// DATA4 - DATA4: u8, - /// DATA5 - DATA5: u8, - /// DATA6 - DATA6: u8, - /// DATA7 - DATA7: u8, - }), base_address + 0x1cc); - - /// address: 0x40006a00 - /// filter master register - pub const FMR = @intToPtr(*volatile Mmio(32, packed struct { - /// FINIT - FINIT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// CAN2SB - CAN2SB: u6, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x200); - - /// address: 0x40006a04 - /// filter mode register - pub const FM1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter mode - FBM0: u1, - /// Filter mode - FBM1: u1, - /// Filter mode - FBM2: u1, - /// Filter mode - FBM3: u1, - /// Filter mode - FBM4: u1, - /// Filter mode - FBM5: u1, - /// Filter mode - FBM6: u1, - /// Filter mode - FBM7: u1, - /// Filter mode - FBM8: u1, - /// Filter mode - FBM9: u1, - /// Filter mode - FBM10: u1, - /// Filter mode - FBM11: u1, - /// Filter mode - FBM12: u1, - /// Filter mode - FBM13: u1, - /// Filter mode - FBM14: u1, - /// Filter mode - FBM15: u1, - /// Filter mode - FBM16: u1, - /// Filter mode - FBM17: u1, - /// Filter mode - FBM18: u1, - /// Filter mode - FBM19: u1, - /// Filter mode - FBM20: u1, - /// Filter mode - FBM21: u1, - /// Filter mode - FBM22: u1, - /// Filter mode - FBM23: u1, - /// Filter mode - FBM24: u1, - /// Filter mode - FBM25: u1, - /// Filter mode - FBM26: u1, - /// Filter mode - FBM27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x204); - - /// address: 0x40006a0c - /// filter scale register - pub const FS1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter scale configuration - FSC0: u1, - /// Filter scale configuration - FSC1: u1, - /// Filter scale configuration - FSC2: u1, - /// Filter scale configuration - FSC3: u1, - /// Filter scale configuration - FSC4: u1, - /// Filter scale configuration - FSC5: u1, - /// Filter scale configuration - FSC6: u1, - /// Filter scale configuration - FSC7: u1, - /// Filter scale configuration - FSC8: u1, - /// Filter scale configuration - FSC9: u1, - /// Filter scale configuration - FSC10: u1, - /// Filter scale configuration - FSC11: u1, - /// Filter scale configuration - FSC12: u1, - /// Filter scale configuration - FSC13: u1, - /// Filter scale configuration - FSC14: u1, - /// Filter scale configuration - FSC15: u1, - /// Filter scale configuration - FSC16: u1, - /// Filter scale configuration - FSC17: u1, - /// Filter scale configuration - FSC18: u1, - /// Filter scale configuration - FSC19: u1, - /// Filter scale configuration - FSC20: u1, - /// Filter scale configuration - FSC21: u1, - /// Filter scale configuration - FSC22: u1, - /// Filter scale configuration - FSC23: u1, - /// Filter scale configuration - FSC24: u1, - /// Filter scale configuration - FSC25: u1, - /// Filter scale configuration - FSC26: u1, - /// Filter scale configuration - FSC27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x20c); - - /// address: 0x40006a14 - /// filter FIFO assignment - /// register - pub const FFA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter FIFO assignment for filter - /// 0 - FFA0: u1, - /// Filter FIFO assignment for filter - /// 1 - FFA1: u1, - /// Filter FIFO assignment for filter - /// 2 - FFA2: u1, - /// Filter FIFO assignment for filter - /// 3 - FFA3: u1, - /// Filter FIFO assignment for filter - /// 4 - FFA4: u1, - /// Filter FIFO assignment for filter - /// 5 - FFA5: u1, - /// Filter FIFO assignment for filter - /// 6 - FFA6: u1, - /// Filter FIFO assignment for filter - /// 7 - FFA7: u1, - /// Filter FIFO assignment for filter - /// 8 - FFA8: u1, - /// Filter FIFO assignment for filter - /// 9 - FFA9: u1, - /// Filter FIFO assignment for filter - /// 10 - FFA10: u1, - /// Filter FIFO assignment for filter - /// 11 - FFA11: u1, - /// Filter FIFO assignment for filter - /// 12 - FFA12: u1, - /// Filter FIFO assignment for filter - /// 13 - FFA13: u1, - /// Filter FIFO assignment for filter - /// 14 - FFA14: u1, - /// Filter FIFO assignment for filter - /// 15 - FFA15: u1, - /// Filter FIFO assignment for filter - /// 16 - FFA16: u1, - /// Filter FIFO assignment for filter - /// 17 - FFA17: u1, - /// Filter FIFO assignment for filter - /// 18 - FFA18: u1, - /// Filter FIFO assignment for filter - /// 19 - FFA19: u1, - /// Filter FIFO assignment for filter - /// 20 - FFA20: u1, - /// Filter FIFO assignment for filter - /// 21 - FFA21: u1, - /// Filter FIFO assignment for filter - /// 22 - FFA22: u1, - /// Filter FIFO assignment for filter - /// 23 - FFA23: u1, - /// Filter FIFO assignment for filter - /// 24 - FFA24: u1, - /// Filter FIFO assignment for filter - /// 25 - FFA25: u1, - /// Filter FIFO assignment for filter - /// 26 - FFA26: u1, - /// Filter FIFO assignment for filter - /// 27 - FFA27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x214); - - /// address: 0x40006a1c - /// filter activation register - pub const FA1R = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter active - FACT0: u1, - /// Filter active - FACT1: u1, - /// Filter active - FACT2: u1, - /// Filter active - FACT3: u1, - /// Filter active - FACT4: u1, - /// Filter active - FACT5: u1, - /// Filter active - FACT6: u1, - /// Filter active - FACT7: u1, - /// Filter active - FACT8: u1, - /// Filter active - FACT9: u1, - /// Filter active - FACT10: u1, - /// Filter active - FACT11: u1, - /// Filter active - FACT12: u1, - /// Filter active - FACT13: u1, - /// Filter active - FACT14: u1, - /// Filter active - FACT15: u1, - /// Filter active - FACT16: u1, - /// Filter active - FACT17: u1, - /// Filter active - FACT18: u1, - /// Filter active - FACT19: u1, - /// Filter active - FACT20: u1, - /// Filter active - FACT21: u1, - /// Filter active - FACT22: u1, - /// Filter active - FACT23: u1, - /// Filter active - FACT24: u1, - /// Filter active - FACT25: u1, - /// Filter active - FACT26: u1, - /// Filter active - FACT27: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x21c); - - /// address: 0x40006a40 - /// Filter bank 0 register 1 - pub const F0R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x240); - - /// address: 0x40006a44 - /// Filter bank 0 register 2 - pub const F0R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x244); - - /// address: 0x40006a48 - /// Filter bank 1 register 1 - pub const F1R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x248); - - /// address: 0x40006a4c - /// Filter bank 1 register 2 - pub const F1R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x24c); - - /// address: 0x40006a50 - /// Filter bank 2 register 1 - pub const F2R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x250); - - /// address: 0x40006a54 - /// Filter bank 2 register 2 - pub const F2R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x254); - - /// address: 0x40006a58 - /// Filter bank 3 register 1 - pub const F3R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x258); - - /// address: 0x40006a5c - /// Filter bank 3 register 2 - pub const F3R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x25c); - - /// address: 0x40006a60 - /// Filter bank 4 register 1 - pub const F4R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x260); - - /// address: 0x40006a64 - /// Filter bank 4 register 2 - pub const F4R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x264); - - /// address: 0x40006a68 - /// Filter bank 5 register 1 - pub const F5R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x268); - - /// address: 0x40006a6c - /// Filter bank 5 register 2 - pub const F5R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x26c); - - /// address: 0x40006a70 - /// Filter bank 6 register 1 - pub const F6R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x270); - - /// address: 0x40006a74 - /// Filter bank 6 register 2 - pub const F6R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x274); - - /// address: 0x40006a78 - /// Filter bank 7 register 1 - pub const F7R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x278); - - /// address: 0x40006a7c - /// Filter bank 7 register 2 - pub const F7R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x27c); - - /// address: 0x40006a80 - /// Filter bank 8 register 1 - pub const F8R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x280); - - /// address: 0x40006a84 - /// Filter bank 8 register 2 - pub const F8R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x284); - - /// address: 0x40006a88 - /// Filter bank 9 register 1 - pub const F9R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x288); - - /// address: 0x40006a8c - /// Filter bank 9 register 2 - pub const F9R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x28c); - - /// address: 0x40006a90 - /// Filter bank 10 register 1 - pub const F10R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x290); - - /// address: 0x40006a94 - /// Filter bank 10 register 2 - pub const F10R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x294); - - /// address: 0x40006a98 - /// Filter bank 11 register 1 - pub const F11R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x298); - - /// address: 0x40006a9c - /// Filter bank 11 register 2 - pub const F11R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x29c); - - /// address: 0x40006aa0 - /// Filter bank 4 register 1 - pub const F12R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a0); - - /// address: 0x40006aa4 - /// Filter bank 12 register 2 - pub const F12R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a4); - - /// address: 0x40006aa8 - /// Filter bank 13 register 1 - pub const F13R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2a8); - - /// address: 0x40006aac - /// Filter bank 13 register 2 - pub const F13R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ac); - - /// address: 0x40006ab0 - /// Filter bank 14 register 1 - pub const F14R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b0); - - /// address: 0x40006ab4 - /// Filter bank 14 register 2 - pub const F14R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b4); - - /// address: 0x40006ab8 - /// Filter bank 15 register 1 - pub const F15R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2b8); - - /// address: 0x40006abc - /// Filter bank 15 register 2 - pub const F15R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2bc); - - /// address: 0x40006ac0 - /// Filter bank 16 register 1 - pub const F16R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c0); - - /// address: 0x40006ac4 - /// Filter bank 16 register 2 - pub const F16R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c4); - - /// address: 0x40006ac8 - /// Filter bank 17 register 1 - pub const F17R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2c8); - - /// address: 0x40006acc - /// Filter bank 17 register 2 - pub const F17R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2cc); - - /// address: 0x40006ad0 - /// Filter bank 18 register 1 - pub const F18R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d0); - - /// address: 0x40006ad4 - /// Filter bank 18 register 2 - pub const F18R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d4); - - /// address: 0x40006ad8 - /// Filter bank 19 register 1 - pub const F19R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2d8); - - /// address: 0x40006adc - /// Filter bank 19 register 2 - pub const F19R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2dc); - - /// address: 0x40006ae0 - /// Filter bank 20 register 1 - pub const F20R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e0); - - /// address: 0x40006ae4 - /// Filter bank 20 register 2 - pub const F20R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e4); - - /// address: 0x40006ae8 - /// Filter bank 21 register 1 - pub const F21R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2e8); - - /// address: 0x40006aec - /// Filter bank 21 register 2 - pub const F21R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2ec); - - /// address: 0x40006af0 - /// Filter bank 22 register 1 - pub const F22R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f0); - - /// address: 0x40006af4 - /// Filter bank 22 register 2 - pub const F22R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f4); - - /// address: 0x40006af8 - /// Filter bank 23 register 1 - pub const F23R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2f8); - - /// address: 0x40006afc - /// Filter bank 23 register 2 - pub const F23R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x2fc); - - /// address: 0x40006b00 - /// Filter bank 24 register 1 - pub const F24R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x300); - - /// address: 0x40006b04 - /// Filter bank 24 register 2 - pub const F24R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x304); - - /// address: 0x40006b08 - /// Filter bank 25 register 1 - pub const F25R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x308); - - /// address: 0x40006b0c - /// Filter bank 25 register 2 - pub const F25R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x30c); - - /// address: 0x40006b10 - /// Filter bank 26 register 1 - pub const F26R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x310); - - /// address: 0x40006b14 - /// Filter bank 26 register 2 - pub const F26R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x314); - - /// address: 0x40006b18 - /// Filter bank 27 register 1 - pub const F27R1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x318); - - /// address: 0x40006b1c - /// Filter bank 27 register 2 - pub const F27R2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Filter bits - FB0: u1, - /// Filter bits - FB1: u1, - /// Filter bits - FB2: u1, - /// Filter bits - FB3: u1, - /// Filter bits - FB4: u1, - /// Filter bits - FB5: u1, - /// Filter bits - FB6: u1, - /// Filter bits - FB7: u1, - /// Filter bits - FB8: u1, - /// Filter bits - FB9: u1, - /// Filter bits - FB10: u1, - /// Filter bits - FB11: u1, - /// Filter bits - FB12: u1, - /// Filter bits - FB13: u1, - /// Filter bits - FB14: u1, - /// Filter bits - FB15: u1, - /// Filter bits - FB16: u1, - /// Filter bits - FB17: u1, - /// Filter bits - FB18: u1, - /// Filter bits - FB19: u1, - /// Filter bits - FB20: u1, - /// Filter bits - FB21: u1, - /// Filter bits - FB22: u1, - /// Filter bits - FB23: u1, - /// Filter bits - FB24: u1, - /// Filter bits - FB25: u1, - /// Filter bits - FB26: u1, - /// Filter bits - FB27: u1, - /// Filter bits - FB28: u1, - /// Filter bits - FB29: u1, - /// Filter bits - FB30: u1, - /// Filter bits - FB31: u1, - }), base_address + 0x31c); - }; - - /// Nested Vectored Interrupt - /// Controller - pub const NVIC = struct { - pub const base_address = 0xe000e100; - - /// address: 0xe000e100 - /// Interrupt Set-Enable Register - pub const ISER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x0); - - /// address: 0xe000e104 - /// Interrupt Set-Enable Register - pub const ISER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x4); - - /// address: 0xe000e108 - /// Interrupt Set-Enable Register - pub const ISER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETENA - SETENA: u32, - }), base_address + 0x8); - - /// address: 0xe000e180 - /// Interrupt Clear-Enable - /// Register - pub const ICER0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x80); - - /// address: 0xe000e184 - /// Interrupt Clear-Enable - /// Register - pub const ICER1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x84); - - /// address: 0xe000e188 - /// Interrupt Clear-Enable - /// Register - pub const ICER2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRENA - CLRENA: u32, - }), base_address + 0x88); - - /// address: 0xe000e200 - /// Interrupt Set-Pending Register - pub const ISPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x100); - - /// address: 0xe000e204 - /// Interrupt Set-Pending Register - pub const ISPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x104); - - /// address: 0xe000e208 - /// Interrupt Set-Pending Register - pub const ISPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// SETPEND - SETPEND: u32, - }), base_address + 0x108); - - /// address: 0xe000e280 - /// Interrupt Clear-Pending - /// Register - pub const ICPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x180); - - /// address: 0xe000e284 - /// Interrupt Clear-Pending - /// Register - pub const ICPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x184); - - /// address: 0xe000e288 - /// Interrupt Clear-Pending - /// Register - pub const ICPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// CLRPEND - CLRPEND: u32, - }), base_address + 0x188); - - /// address: 0xe000e300 - /// Interrupt Active Bit Register - pub const IABR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x200); - - /// address: 0xe000e304 - /// Interrupt Active Bit Register - pub const IABR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x204); - - /// address: 0xe000e308 - /// Interrupt Active Bit Register - pub const IABR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// ACTIVE - ACTIVE: u32, - }), base_address + 0x208); - - /// address: 0xe000e400 - /// Interrupt Priority Register - pub const IPR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x300); - - /// address: 0xe000e404 - /// Interrupt Priority Register - pub const IPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x304); - - /// address: 0xe000e408 - /// Interrupt Priority Register - pub const IPR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x308); - - /// address: 0xe000e40c - /// Interrupt Priority Register - pub const IPR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x30c); - - /// address: 0xe000e410 - /// Interrupt Priority Register - pub const IPR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x310); - - /// address: 0xe000e414 - /// Interrupt Priority Register - pub const IPR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x314); - - /// address: 0xe000e418 - /// Interrupt Priority Register - pub const IPR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x318); - - /// address: 0xe000e41c - /// Interrupt Priority Register - pub const IPR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x31c); - - /// address: 0xe000e420 - /// Interrupt Priority Register - pub const IPR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x320); - - /// address: 0xe000e424 - /// Interrupt Priority Register - pub const IPR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x324); - - /// address: 0xe000e428 - /// Interrupt Priority Register - pub const IPR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x328); - - /// address: 0xe000e42c - /// Interrupt Priority Register - pub const IPR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x32c); - - /// address: 0xe000e430 - /// Interrupt Priority Register - pub const IPR12 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x330); - - /// address: 0xe000e434 - /// Interrupt Priority Register - pub const IPR13 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x334); - - /// address: 0xe000e438 - /// Interrupt Priority Register - pub const IPR14 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x338); - - /// address: 0xe000e43c - /// Interrupt Priority Register - pub const IPR15 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x33c); - - /// address: 0xe000e440 - /// Interrupt Priority Register - pub const IPR16 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x340); - - /// address: 0xe000e444 - /// Interrupt Priority Register - pub const IPR17 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x344); - - /// address: 0xe000e448 - /// Interrupt Priority Register - pub const IPR18 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x348); - - /// address: 0xe000e44c - /// Interrupt Priority Register - pub const IPR19 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x34c); - - /// address: 0xe000e450 - /// Interrupt Priority Register - pub const IPR20 = @intToPtr(*volatile Mmio(32, packed struct { - /// IPR_N0 - IPR_N0: u8, - /// IPR_N1 - IPR_N1: u8, - /// IPR_N2 - IPR_N2: u8, - /// IPR_N3 - IPR_N3: u8, - }), base_address + 0x350); - }; - - /// FLASH - pub const FLASH = struct { - pub const base_address = 0x40023c00; - - /// address: 0x40023c00 - /// Flash access control register - pub const ACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Latency - LATENCY: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Prefetch enable - PRFTEN: u1, - /// Instruction cache enable - ICEN: u1, - /// Data cache enable - DCEN: u1, - /// Instruction cache reset - ICRST: u1, - /// Data cache reset - DCRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x0); - - /// address: 0x40023c04 - /// Flash key register - pub const KEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// FPEC key - KEY: u32, - }), base_address + 0x4); - - /// address: 0x40023c08 - /// Flash option key register - pub const OPTKEYR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option byte key - OPTKEY: u32, - }), base_address + 0x8); - - /// address: 0x40023c0c - /// Status register - pub const SR = @intToPtr(*volatile Mmio(32, packed struct { - /// End of operation - EOP: u1, - /// Operation error - OPERR: u1, - reserved0: u1, - reserved1: u1, - /// Write protection error - WRPERR: u1, - /// Programming alignment - /// error - PGAERR: u1, - /// Programming parallelism - /// error - PGPERR: u1, - /// Programming sequence error - PGSERR: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Busy - BSY: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0xc); - - /// address: 0x40023c10 - /// Control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Programming - PG: u1, - /// Sector Erase - SER: u1, - /// Mass Erase of sectors 0 to - /// 11 - MER: u1, - /// Sector number - SNB: u5, - /// Program size - PSIZE: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Mass Erase of sectors 12 to - /// 23 - MER1: u1, - /// Start - STRT: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// End of operation interrupt - /// enable - EOPIE: u1, - /// Error interrupt enable - ERRIE: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Lock - LOCK: u1, - }), base_address + 0x10); - - /// address: 0x40023c14 - /// Flash option control register - pub const OPTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Option lock - OPTLOCK: u1, - /// Option start - OPTSTRT: u1, - /// BOR reset Level - BOR_LEV: u2, - reserved0: u1, - /// WDG_SW User option bytes - WDG_SW: u1, - /// nRST_STOP User option - /// bytes - nRST_STOP: u1, - /// nRST_STDBY User option - /// bytes - nRST_STDBY: u1, - /// Read protect - RDP: u8, - /// Not write protect - nWRP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x14); - - /// address: 0x40023c18 - /// Flash option control register - /// 1 - pub const OPTCR1 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Not write protect - nWRP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x18); - }; - - /// External interrupt/event - /// controller - pub const EXTI = struct { - pub const base_address = 0x40013c00; - - /// address: 0x40013c00 - /// Interrupt mask register - /// (EXTI_IMR) - pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt Mask on line 0 - MR0: u1, - /// Interrupt Mask on line 1 - MR1: u1, - /// Interrupt Mask on line 2 - MR2: u1, - /// Interrupt Mask on line 3 - MR3: u1, - /// Interrupt Mask on line 4 - MR4: u1, - /// Interrupt Mask on line 5 - MR5: u1, - /// Interrupt Mask on line 6 - MR6: u1, - /// Interrupt Mask on line 7 - MR7: u1, - /// Interrupt Mask on line 8 - MR8: u1, - /// Interrupt Mask on line 9 - MR9: u1, - /// Interrupt Mask on line 10 - MR10: u1, - /// Interrupt Mask on line 11 - MR11: u1, - /// Interrupt Mask on line 12 - MR12: u1, - /// Interrupt Mask on line 13 - MR13: u1, - /// Interrupt Mask on line 14 - MR14: u1, - /// Interrupt Mask on line 15 - MR15: u1, - /// Interrupt Mask on line 16 - MR16: u1, - /// Interrupt Mask on line 17 - MR17: u1, - /// Interrupt Mask on line 18 - MR18: u1, - /// Interrupt Mask on line 19 - MR19: u1, - /// Interrupt Mask on line 20 - MR20: u1, - /// Interrupt Mask on line 21 - MR21: u1, - /// Interrupt Mask on line 22 - MR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x0); - - /// address: 0x40013c04 - /// Event mask register (EXTI_EMR) - pub const EMR = @intToPtr(*volatile Mmio(32, packed struct { - /// Event Mask on line 0 - MR0: u1, - /// Event Mask on line 1 - MR1: u1, - /// Event Mask on line 2 - MR2: u1, - /// Event Mask on line 3 - MR3: u1, - /// Event Mask on line 4 - MR4: u1, - /// Event Mask on line 5 - MR5: u1, - /// Event Mask on line 6 - MR6: u1, - /// Event Mask on line 7 - MR7: u1, - /// Event Mask on line 8 - MR8: u1, - /// Event Mask on line 9 - MR9: u1, - /// Event Mask on line 10 - MR10: u1, - /// Event Mask on line 11 - MR11: u1, - /// Event Mask on line 12 - MR12: u1, - /// Event Mask on line 13 - MR13: u1, - /// Event Mask on line 14 - MR14: u1, - /// Event Mask on line 15 - MR15: u1, - /// Event Mask on line 16 - MR16: u1, - /// Event Mask on line 17 - MR17: u1, - /// Event Mask on line 18 - MR18: u1, - /// Event Mask on line 19 - MR19: u1, - /// Event Mask on line 20 - MR20: u1, - /// Event Mask on line 21 - MR21: u1, - /// Event Mask on line 22 - MR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x4); - - /// address: 0x40013c08 - /// Rising Trigger selection register - /// (EXTI_RTSR) - pub const RTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Rising trigger event configuration of - /// line 0 - TR0: u1, - /// Rising trigger event configuration of - /// line 1 - TR1: u1, - /// Rising trigger event configuration of - /// line 2 - TR2: u1, - /// Rising trigger event configuration of - /// line 3 - TR3: u1, - /// Rising trigger event configuration of - /// line 4 - TR4: u1, - /// Rising trigger event configuration of - /// line 5 - TR5: u1, - /// Rising trigger event configuration of - /// line 6 - TR6: u1, - /// Rising trigger event configuration of - /// line 7 - TR7: u1, - /// Rising trigger event configuration of - /// line 8 - TR8: u1, - /// Rising trigger event configuration of - /// line 9 - TR9: u1, - /// Rising trigger event configuration of - /// line 10 - TR10: u1, - /// Rising trigger event configuration of - /// line 11 - TR11: u1, - /// Rising trigger event configuration of - /// line 12 - TR12: u1, - /// Rising trigger event configuration of - /// line 13 - TR13: u1, - /// Rising trigger event configuration of - /// line 14 - TR14: u1, - /// Rising trigger event configuration of - /// line 15 - TR15: u1, - /// Rising trigger event configuration of - /// line 16 - TR16: u1, - /// Rising trigger event configuration of - /// line 17 - TR17: u1, - /// Rising trigger event configuration of - /// line 18 - TR18: u1, - /// Rising trigger event configuration of - /// line 19 - TR19: u1, - /// Rising trigger event configuration of - /// line 20 - TR20: u1, - /// Rising trigger event configuration of - /// line 21 - TR21: u1, - /// Rising trigger event configuration of - /// line 22 - TR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x8); - - /// address: 0x40013c0c - /// Falling Trigger selection register - /// (EXTI_FTSR) - pub const FTSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Falling trigger event configuration of - /// line 0 - TR0: u1, - /// Falling trigger event configuration of - /// line 1 - TR1: u1, - /// Falling trigger event configuration of - /// line 2 - TR2: u1, - /// Falling trigger event configuration of - /// line 3 - TR3: u1, - /// Falling trigger event configuration of - /// line 4 - TR4: u1, - /// Falling trigger event configuration of - /// line 5 - TR5: u1, - /// Falling trigger event configuration of - /// line 6 - TR6: u1, - /// Falling trigger event configuration of - /// line 7 - TR7: u1, - /// Falling trigger event configuration of - /// line 8 - TR8: u1, - /// Falling trigger event configuration of - /// line 9 - TR9: u1, - /// Falling trigger event configuration of - /// line 10 - TR10: u1, - /// Falling trigger event configuration of - /// line 11 - TR11: u1, - /// Falling trigger event configuration of - /// line 12 - TR12: u1, - /// Falling trigger event configuration of - /// line 13 - TR13: u1, - /// Falling trigger event configuration of - /// line 14 - TR14: u1, - /// Falling trigger event configuration of - /// line 15 - TR15: u1, - /// Falling trigger event configuration of - /// line 16 - TR16: u1, - /// Falling trigger event configuration of - /// line 17 - TR17: u1, - /// Falling trigger event configuration of - /// line 18 - TR18: u1, - /// Falling trigger event configuration of - /// line 19 - TR19: u1, - /// Falling trigger event configuration of - /// line 20 - TR20: u1, - /// Falling trigger event configuration of - /// line 21 - TR21: u1, - /// Falling trigger event configuration of - /// line 22 - TR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0xc); - - /// address: 0x40013c10 - /// Software interrupt event register - /// (EXTI_SWIER) - pub const SWIER = @intToPtr(*volatile Mmio(32, packed struct { - /// Software Interrupt on line - /// 0 - SWIER0: u1, - /// Software Interrupt on line - /// 1 - SWIER1: u1, - /// Software Interrupt on line - /// 2 - SWIER2: u1, - /// Software Interrupt on line - /// 3 - SWIER3: u1, - /// Software Interrupt on line - /// 4 - SWIER4: u1, - /// Software Interrupt on line - /// 5 - SWIER5: u1, - /// Software Interrupt on line - /// 6 - SWIER6: u1, - /// Software Interrupt on line - /// 7 - SWIER7: u1, - /// Software Interrupt on line - /// 8 - SWIER8: u1, - /// Software Interrupt on line - /// 9 - SWIER9: u1, - /// Software Interrupt on line - /// 10 - SWIER10: u1, - /// Software Interrupt on line - /// 11 - SWIER11: u1, - /// Software Interrupt on line - /// 12 - SWIER12: u1, - /// Software Interrupt on line - /// 13 - SWIER13: u1, - /// Software Interrupt on line - /// 14 - SWIER14: u1, - /// Software Interrupt on line - /// 15 - SWIER15: u1, - /// Software Interrupt on line - /// 16 - SWIER16: u1, - /// Software Interrupt on line - /// 17 - SWIER17: u1, - /// Software Interrupt on line - /// 18 - SWIER18: u1, - /// Software Interrupt on line - /// 19 - SWIER19: u1, - /// Software Interrupt on line - /// 20 - SWIER20: u1, - /// Software Interrupt on line - /// 21 - SWIER21: u1, - /// Software Interrupt on line - /// 22 - SWIER22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x10); - - /// address: 0x40013c14 - /// Pending register (EXTI_PR) - pub const PR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pending bit 0 - PR0: u1, - /// Pending bit 1 - PR1: u1, - /// Pending bit 2 - PR2: u1, - /// Pending bit 3 - PR3: u1, - /// Pending bit 4 - PR4: u1, - /// Pending bit 5 - PR5: u1, - /// Pending bit 6 - PR6: u1, - /// Pending bit 7 - PR7: u1, - /// Pending bit 8 - PR8: u1, - /// Pending bit 9 - PR9: u1, - /// Pending bit 10 - PR10: u1, - /// Pending bit 11 - PR11: u1, - /// Pending bit 12 - PR12: u1, - /// Pending bit 13 - PR13: u1, - /// Pending bit 14 - PR14: u1, - /// Pending bit 15 - PR15: u1, - /// Pending bit 16 - PR16: u1, - /// Pending bit 17 - PR17: u1, - /// Pending bit 18 - PR18: u1, - /// Pending bit 19 - PR19: u1, - /// Pending bit 20 - PR20: u1, - /// Pending bit 21 - PR21: u1, - /// Pending bit 22 - PR22: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - }), base_address + 0x14); - }; - - /// USB on the go high speed - pub const OTG_HS_GLOBAL = struct { - pub const base_address = 0x40040000; - - /// address: 0x40040000 - /// OTG_HS control and status - /// register - pub const OTG_HS_GOTGCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Session request success - SRQSCS: u1, - /// Session request - SRQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// Host negotiation success - HNGSCS: u1, - /// HNP request - HNPRQ: u1, - /// Host set HNP enable - HSHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - /// Connector ID status - CIDSTS: u1, - /// Long/short debounce time - DBCT: u1, - /// A-session valid - ASVLD: u1, - /// B-session valid - BSVLD: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x0); - - /// address: 0x40040004 - /// OTG_HS interrupt register - pub const OTG_HS_GOTGINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - /// Session end detected - SEDET: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Session request success status - /// change - SRSSCHG: u1, - /// Host negotiation success status - /// change - HNSSCHG: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Host negotiation detected - HNGDET: u1, - /// A-device timeout change - ADTOCHG: u1, - /// Debounce done - DBCDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - }), base_address + 0x4); - - /// address: 0x40040008 - /// OTG_HS AHB configuration - /// register - pub const OTG_HS_GAHBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Global interrupt mask - GINT: u1, - /// Burst length/type - HBSTLEN: u4, - /// DMA enable - DMAEN: u1, - reserved0: u1, - /// TxFIFO empty level - TXFELVL: u1, - /// Periodic TxFIFO empty - /// level - PTXFELVL: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x8); - - /// address: 0x4004000c - /// OTG_HS USB configuration - /// register - pub const OTG_HS_GUSBCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS timeout calibration - TOCAL: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// USB 2.0 high-speed ULPI PHY or USB 1.1 - /// full-speed serial transceiver select - PHYSEL: u1, - reserved3: u1, - /// SRP-capable - SRPCAP: u1, - /// HNP-capable - HNPCAP: u1, - /// USB turnaround time - TRDT: u4, - reserved4: u1, - /// PHY Low-power clock select - PHYLPCS: u1, - reserved5: u1, - /// ULPI FS/LS select - ULPIFSLS: u1, - /// ULPI Auto-resume - ULPIAR: u1, - /// ULPI Clock SuspendM - ULPICSM: u1, - /// ULPI External VBUS Drive - ULPIEVBUSD: u1, - /// ULPI external VBUS - /// indicator - ULPIEVBUSI: u1, - /// TermSel DLine pulsing - /// selection - TSDPS: u1, - /// Indicator complement - PCCI: u1, - /// Indicator pass through - PTCI: u1, - /// ULPI interface protect - /// disable - ULPIIPD: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Forced host mode - FHMOD: u1, - /// Forced peripheral mode - FDMOD: u1, - /// Corrupt Tx packet - CTXPKT: u1, - }), base_address + 0xc); - - /// address: 0x40040010 - /// OTG_HS reset register - pub const OTG_HS_GRSTCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HSRST: u1, - /// Host frame counter reset - FCRST: u1, - reserved0: u1, - /// RxFIFO flush - RXFFLSH: u1, - /// TxFIFO flush - TXFFLSH: u1, - /// TxFIFO number - TXFNUM: u5, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// DMA request signal - DMAREQ: u1, - /// AHB master idle - AHBIDL: u1, - }), base_address + 0x10); - - /// address: 0x40040014 - /// OTG_HS core interrupt register - pub const OTG_HS_GINTSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Current mode of operation - CMOD: u1, - /// Mode mismatch interrupt - MMIS: u1, - /// OTG interrupt - OTGINT: u1, - /// Start of frame - SOF: u1, - /// RxFIFO nonempty - RXFLVL: u1, - /// Nonperiodic TxFIFO empty - NPTXFE: u1, - /// Global IN nonperiodic NAK - /// effective - GINAKEFF: u1, - /// Global OUT NAK effective - BOUTNAKEFF: u1, - reserved0: u1, - reserved1: u1, - /// Early suspend - ESUSP: u1, - /// USB suspend - USBSUSP: u1, - /// USB reset - USBRST: u1, - /// Enumeration done - ENUMDNE: u1, - /// Isochronous OUT packet dropped - /// interrupt - ISOODRP: u1, - /// End of periodic frame - /// interrupt - EOPF: u1, - reserved2: u1, - reserved3: u1, - /// IN endpoint interrupt - IEPINT: u1, - /// OUT endpoint interrupt - OEPINT: u1, - /// Incomplete isochronous IN - /// transfer - IISOIXFR: u1, - /// Incomplete periodic - /// transfer - PXFR_INCOMPISOOUT: u1, - /// Data fetch suspended - DATAFSUSP: u1, - reserved4: u1, - /// Host port interrupt - HPRTINT: u1, - /// Host channels interrupt - HCINT: u1, - /// Periodic TxFIFO empty - PTXFE: u1, - reserved5: u1, - /// Connector ID status change - CIDSCHG: u1, - /// Disconnect detected - /// interrupt - DISCINT: u1, - /// Session request/new session detected - /// interrupt - SRQINT: u1, - /// Resume/remote wakeup detected - /// interrupt - WKUINT: u1, - }), base_address + 0x14); - - /// address: 0x40040018 - /// OTG_HS interrupt mask register - pub const OTG_HS_GINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Mode mismatch interrupt - /// mask - MMISM: u1, - /// OTG interrupt mask - OTGINT: u1, - /// Start of frame mask - SOFM: u1, - /// Receive FIFO nonempty mask - RXFLVLM: u1, - /// Nonperiodic TxFIFO empty - /// mask - NPTXFEM: u1, - /// Global nonperiodic IN NAK effective - /// mask - GINAKEFFM: u1, - /// Global OUT NAK effective - /// mask - GONAKEFFM: u1, - reserved1: u1, - reserved2: u1, - /// Early suspend mask - ESUSPM: u1, - /// USB suspend mask - USBSUSPM: u1, - /// USB reset mask - USBRST: u1, - /// Enumeration done mask - ENUMDNEM: u1, - /// Isochronous OUT packet dropped interrupt - /// mask - ISOODRPM: u1, - /// End of periodic frame interrupt - /// mask - EOPFM: u1, - reserved3: u1, - /// Endpoint mismatch interrupt - /// mask - EPMISM: u1, - /// IN endpoints interrupt - /// mask - IEPINT: u1, - /// OUT endpoints interrupt - /// mask - OEPINT: u1, - /// Incomplete isochronous IN transfer - /// mask - IISOIXFRM: u1, - /// Incomplete periodic transfer - /// mask - PXFRM_IISOOXFRM: u1, - /// Data fetch suspended mask - FSUSPM: u1, - reserved4: u1, - /// Host port interrupt mask - PRTIM: u1, - /// Host channels interrupt - /// mask - HCIM: u1, - /// Periodic TxFIFO empty mask - PTXFEM: u1, - reserved5: u1, - /// Connector ID status change - /// mask - CIDSCHGM: u1, - /// Disconnect detected interrupt - /// mask - DISCINT: u1, - /// Session request/new session detected - /// interrupt mask - SRQIM: u1, - /// Resume/remote wakeup detected interrupt - /// mask - WUIM: u1, - }), base_address + 0x18); - - /// address: 0x4004001c - /// OTG_HS Receive status debug read register - /// (host mode) - pub const OTG_HS_GRXSTSR_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CHNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x1c); - - /// address: 0x40040020 - /// OTG_HS status read and pop register (host - /// mode) - pub const OTG_HS_GRXSTSP_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel number - CHNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x20); - - /// address: 0x40040024 - /// OTG_HS Receive FIFO size - /// register - pub const OTG_HS_GRXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// RxFIFO depth - RXFD: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x24); - - /// address: 0x40040028 - /// OTG_HS nonperiodic transmit FIFO size - /// register (host mode) - pub const OTG_HS_GNPTXFSIZ_Host = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonperiodic transmit RAM start - /// address - NPTXFSA: u16, - /// Nonperiodic TxFIFO depth - NPTXFD: u16, - }), base_address + 0x28); - - /// address: 0x40040028 - /// Endpoint 0 transmit FIFO size (peripheral - /// mode) - pub const OTG_HS_TX0FSIZ_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint 0 transmit RAM start - /// address - TX0FSA: u16, - /// Endpoint 0 TxFIFO depth - TX0FD: u16, - }), base_address + 0x28); - - /// address: 0x4004002c - /// OTG_HS nonperiodic transmit FIFO/queue - /// status register - pub const OTG_HS_GNPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonperiodic TxFIFO space - /// available - NPTXFSAV: u16, - /// Nonperiodic transmit request queue space - /// available - NPTQXSAV: u8, - /// Top of the nonperiodic transmit request - /// queue - NPTXQTOP: u7, - padding0: u1, - }), base_address + 0x2c); - - /// address: 0x40040038 - /// OTG_HS general core configuration - /// register - pub const OTG_HS_GCCFG = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Power down - PWRDWN: u1, - /// Enable I2C bus connection for the - /// external I2C PHY interface - I2CPADEN: u1, - /// Enable the VBUS sensing - /// device - VBUSASEN: u1, - /// Enable the VBUS sensing - /// device - VBUSBSEN: u1, - /// SOF output enable - SOFOUTEN: u1, - /// VBUS sensing disable - /// option - NOVBUSSENS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x38); - - /// address: 0x4004003c - /// OTG_HS core ID register - pub const OTG_HS_CID = @intToPtr(*volatile Mmio(32, packed struct { - /// Product ID field - PRODUCT_ID: u32, - }), base_address + 0x3c); - - /// address: 0x40040100 - /// OTG_HS Host periodic transmit FIFO size - /// register - pub const OTG_HS_HPTXFSIZ = @intToPtr(*volatile Mmio(32, packed struct { - /// Host periodic TxFIFO start - /// address - PTXSA: u16, - /// Host periodic TxFIFO depth - PTXFD: u16, - }), base_address + 0x100); - - /// address: 0x40040104 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x104); - - /// address: 0x40040108 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x108); - - /// address: 0x4004011c - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x11c); - - /// address: 0x40040120 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x120); - - /// address: 0x40040124 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x124); - - /// address: 0x40040128 - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF6 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x128); - - /// address: 0x4004012c - /// OTG_HS device IN endpoint transmit FIFO size - /// register - pub const OTG_HS_DIEPTXF7 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint FIFOx transmit RAM start - /// address - INEPTXSA: u16, - /// IN endpoint TxFIFO depth - INEPTXFD: u16, - }), base_address + 0x12c); - - /// address: 0x4004001c - /// OTG_HS Receive status debug read register - /// (peripheral mode mode) - pub const OTG_HS_GRXSTSR_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x1c); - - /// address: 0x40040020 - /// OTG_HS status read and pop register - /// (peripheral mode) - pub const OTG_HS_GRXSTSP_Peripheral = @intToPtr(*volatile Mmio(32, packed struct { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCNT: u11, - /// Data PID - DPID: u2, - /// Packet status - PKTSTS: u4, - /// Frame number - FRMNUM: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - }), base_address + 0x20); - }; - - /// USB on the go high speed - pub const OTG_HS_HOST = struct { - pub const base_address = 0x40040400; - - /// address: 0x40040400 - /// OTG_HS host configuration - /// register - pub const OTG_HS_HCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// FS/LS PHY clock select - FSLSPCS: u2, - /// FS- and LS-only support - FSLSS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x0); - - /// address: 0x40040404 - /// OTG_HS Host frame interval - /// register - pub const OTG_HS_HFIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame interval - FRIVL: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4); - - /// address: 0x40040408 - /// OTG_HS host frame number/frame time - /// remaining register - pub const OTG_HS_HFNUM = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame number - FRNUM: u16, - /// Frame time remaining - FTREM: u16, - }), base_address + 0x8); - - /// address: 0x40040410 - /// OTG_HS_Host periodic transmit FIFO/queue - /// status register - pub const OTG_HS_HPTXSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Periodic transmit data FIFO space - /// available - PTXFSAVL: u16, - /// Periodic transmit request queue space - /// available - PTXQSAV: u8, - /// Top of the periodic transmit request - /// queue - PTXQTOP: u8, - }), base_address + 0x10); - - /// address: 0x40040414 - /// OTG_HS Host all channels interrupt - /// register - pub const OTG_HS_HAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupts - HAINT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40040418 - /// OTG_HS host all channels interrupt mask - /// register - pub const OTG_HS_HAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Channel interrupt mask - HAINTM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40040440 - /// OTG_HS host port control and status - /// register - pub const OTG_HS_HPRT = @intToPtr(*volatile Mmio(32, packed struct { - /// Port connect status - PCSTS: u1, - /// Port connect detected - PCDET: u1, - /// Port enable - PENA: u1, - /// Port enable/disable change - PENCHNG: u1, - /// Port overcurrent active - POCA: u1, - /// Port overcurrent change - POCCHNG: u1, - /// Port resume - PRES: u1, - /// Port suspend - PSUSP: u1, - /// Port reset - PRST: u1, - reserved0: u1, - /// Port line status - PLSTS: u2, - /// Port power - PPWR: u1, - /// Port test control - PTCTL: u4, - /// Port speed - PSPD: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x40); - - /// address: 0x40040500 - /// OTG_HS host channel-0 characteristics - /// register - pub const OTG_HS_HCCHAR0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x100); - - /// address: 0x40040520 - /// OTG_HS host channel-1 characteristics - /// register - pub const OTG_HS_HCCHAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x120); - - /// address: 0x40040540 - /// OTG_HS host channel-2 characteristics - /// register - pub const OTG_HS_HCCHAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x140); - - /// address: 0x40040560 - /// OTG_HS host channel-3 characteristics - /// register - pub const OTG_HS_HCCHAR3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x160); - - /// address: 0x40040580 - /// OTG_HS host channel-4 characteristics - /// register - pub const OTG_HS_HCCHAR4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x180); - - /// address: 0x400405a0 - /// OTG_HS host channel-5 characteristics - /// register - pub const OTG_HS_HCCHAR5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1a0); - - /// address: 0x400405c0 - /// OTG_HS host channel-6 characteristics - /// register - pub const OTG_HS_HCCHAR6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1c0); - - /// address: 0x400405e0 - /// OTG_HS host channel-7 characteristics - /// register - pub const OTG_HS_HCCHAR7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x1e0); - - /// address: 0x40040600 - /// OTG_HS host channel-8 characteristics - /// register - pub const OTG_HS_HCCHAR8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x200); - - /// address: 0x40040620 - /// OTG_HS host channel-9 characteristics - /// register - pub const OTG_HS_HCCHAR9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x220); - - /// address: 0x40040640 - /// OTG_HS host channel-10 characteristics - /// register - pub const OTG_HS_HCCHAR10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x240); - - /// address: 0x40040660 - /// OTG_HS host channel-11 characteristics - /// register - pub const OTG_HS_HCCHAR11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved0: u1, - /// Low-speed device - LSDEV: u1, - /// Endpoint type - EPTYP: u2, - /// Multi Count (MC) / Error Count - /// (EC) - MC: u2, - /// Device address - DAD: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CHDIS: u1, - /// Channel enable - CHENA: u1, - }), base_address + 0x260); - - /// address: 0x40040504 - /// OTG_HS host channel-0 split control - /// register - pub const OTG_HS_HCSPLT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x104); - - /// address: 0x40040524 - /// OTG_HS host channel-1 split control - /// register - pub const OTG_HS_HCSPLT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x124); - - /// address: 0x40040544 - /// OTG_HS host channel-2 split control - /// register - pub const OTG_HS_HCSPLT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x144); - - /// address: 0x40040564 - /// OTG_HS host channel-3 split control - /// register - pub const OTG_HS_HCSPLT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x164); - - /// address: 0x40040584 - /// OTG_HS host channel-4 split control - /// register - pub const OTG_HS_HCSPLT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x184); - - /// address: 0x400405a4 - /// OTG_HS host channel-5 split control - /// register - pub const OTG_HS_HCSPLT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1a4); - - /// address: 0x400405c4 - /// OTG_HS host channel-6 split control - /// register - pub const OTG_HS_HCSPLT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1c4); - - /// address: 0x400405e4 - /// OTG_HS host channel-7 split control - /// register - pub const OTG_HS_HCSPLT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x1e4); - - /// address: 0x40040604 - /// OTG_HS host channel-8 split control - /// register - pub const OTG_HS_HCSPLT8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x204); - - /// address: 0x40040624 - /// OTG_HS host channel-9 split control - /// register - pub const OTG_HS_HCSPLT9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x224); - - /// address: 0x40040644 - /// OTG_HS host channel-10 split control - /// register - pub const OTG_HS_HCSPLT10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x244); - - /// address: 0x40040664 - /// OTG_HS host channel-11 split control - /// register - pub const OTG_HS_HCSPLT11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Port address - PRTADDR: u7, - /// Hub address - HUBADDR: u7, - /// XACTPOS - XACTPOS: u2, - /// Do complete split - COMPLSPLT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - /// Split enable - SPLITEN: u1, - }), base_address + 0x264); - - /// address: 0x40040508 - /// OTG_HS host channel-11 interrupt - /// register - pub const OTG_HS_HCINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x108); - - /// address: 0x40040528 - /// OTG_HS host channel-1 interrupt - /// register - pub const OTG_HS_HCINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x128); - - /// address: 0x40040548 - /// OTG_HS host channel-2 interrupt - /// register - pub const OTG_HS_HCINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x148); - - /// address: 0x40040568 - /// OTG_HS host channel-3 interrupt - /// register - pub const OTG_HS_HCINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x168); - - /// address: 0x40040588 - /// OTG_HS host channel-4 interrupt - /// register - pub const OTG_HS_HCINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x188); - - /// address: 0x400405a8 - /// OTG_HS host channel-5 interrupt - /// register - pub const OTG_HS_HCINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1a8); - - /// address: 0x400405c8 - /// OTG_HS host channel-6 interrupt - /// register - pub const OTG_HS_HCINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1c8); - - /// address: 0x400405e8 - /// OTG_HS host channel-7 interrupt - /// register - pub const OTG_HS_HCINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1e8); - - /// address: 0x40040608 - /// OTG_HS host channel-8 interrupt - /// register - pub const OTG_HS_HCINT8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x208); - - /// address: 0x40040628 - /// OTG_HS host channel-9 interrupt - /// register - pub const OTG_HS_HCINT9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x228); - - /// address: 0x40040648 - /// OTG_HS host channel-10 interrupt - /// register - pub const OTG_HS_HCINT10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x248); - - /// address: 0x40040668 - /// OTG_HS host channel-11 interrupt - /// register - pub const OTG_HS_HCINT11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - XFRC: u1, - /// Channel halted - CHH: u1, - /// AHB error - AHBERR: u1, - /// STALL response received - /// interrupt - STALL: u1, - /// NAK response received - /// interrupt - NAK: u1, - /// ACK response received/transmitted - /// interrupt - ACK: u1, - /// Response received - /// interrupt - NYET: u1, - /// Transaction error - TXERR: u1, - /// Babble error - BBERR: u1, - /// Frame overrun - FRMOR: u1, - /// Data toggle error - DTERR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x268); - - /// address: 0x4004050c - /// OTG_HS host channel-11 interrupt mask - /// register - pub const OTG_HS_HCINTMSK0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x10c); - - /// address: 0x4004052c - /// OTG_HS host channel-1 interrupt mask - /// register - pub const OTG_HS_HCINTMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x12c); - - /// address: 0x4004054c - /// OTG_HS host channel-2 interrupt mask - /// register - pub const OTG_HS_HCINTMSK2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x14c); - - /// address: 0x4004056c - /// OTG_HS host channel-3 interrupt mask - /// register - pub const OTG_HS_HCINTMSK3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x16c); - - /// address: 0x4004058c - /// OTG_HS host channel-4 interrupt mask - /// register - pub const OTG_HS_HCINTMSK4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x18c); - - /// address: 0x400405ac - /// OTG_HS host channel-5 interrupt mask - /// register - pub const OTG_HS_HCINTMSK5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ac); - - /// address: 0x400405cc - /// OTG_HS host channel-6 interrupt mask - /// register - pub const OTG_HS_HCINTMSK6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1cc); - - /// address: 0x400405ec - /// OTG_HS host channel-7 interrupt mask - /// register - pub const OTG_HS_HCINTMSK7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x1ec); - - /// address: 0x4004060c - /// OTG_HS host channel-8 interrupt mask - /// register - pub const OTG_HS_HCINTMSK8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x20c); - - /// address: 0x4004062c - /// OTG_HS host channel-9 interrupt mask - /// register - pub const OTG_HS_HCINTMSK9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x22c); - - /// address: 0x4004064c - /// OTG_HS host channel-10 interrupt mask - /// register - pub const OTG_HS_HCINTMSK10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x24c); - - /// address: 0x4004066c - /// OTG_HS host channel-11 interrupt mask - /// register - pub const OTG_HS_HCINTMSK11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed mask - XFRCM: u1, - /// Channel halted mask - CHHM: u1, - /// AHB error - AHBERR: u1, - /// STALL response received interrupt - /// mask - STALLM: u1, - /// NAK response received interrupt - /// mask - NAKM: u1, - /// ACK response received/transmitted - /// interrupt mask - ACKM: u1, - /// response received interrupt - /// mask - NYET: u1, - /// Transaction error mask - TXERRM: u1, - /// Babble error mask - BBERRM: u1, - /// Frame overrun mask - FRMORM: u1, - /// Data toggle error mask - DTERRM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x26c); - - /// address: 0x40040510 - /// OTG_HS host channel-11 transfer size - /// register - pub const OTG_HS_HCTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x110); - - /// address: 0x40040530 - /// OTG_HS host channel-1 transfer size - /// register - pub const OTG_HS_HCTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x40040550 - /// OTG_HS host channel-2 transfer size - /// register - pub const OTG_HS_HCTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x40040570 - /// OTG_HS host channel-3 transfer size - /// register - pub const OTG_HS_HCTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x40040590 - /// OTG_HS host channel-4 transfer size - /// register - pub const OTG_HS_HCTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x400405b0 - /// OTG_HS host channel-5 transfer size - /// register - pub const OTG_HS_HCTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x400405d0 - /// OTG_HS host channel-6 transfer size - /// register - pub const OTG_HS_HCTSIZ6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1d0); - - /// address: 0x400405f0 - /// OTG_HS host channel-7 transfer size - /// register - pub const OTG_HS_HCTSIZ7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x1f0); - - /// address: 0x40040610 - /// OTG_HS host channel-8 transfer size - /// register - pub const OTG_HS_HCTSIZ8 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x210); - - /// address: 0x40040630 - /// OTG_HS host channel-9 transfer size - /// register - pub const OTG_HS_HCTSIZ9 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x230); - - /// address: 0x40040650 - /// OTG_HS host channel-10 transfer size - /// register - pub const OTG_HS_HCTSIZ10 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x250); - - /// address: 0x40040670 - /// OTG_HS host channel-11 transfer size - /// register - pub const OTG_HS_HCTSIZ11 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Data PID - DPID: u2, - padding0: u1, - }), base_address + 0x270); - - /// address: 0x40040514 - /// OTG_HS host channel-0 DMA address - /// register - pub const OTG_HS_HCDMA0 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x114); - - /// address: 0x40040534 - /// OTG_HS host channel-1 DMA address - /// register - pub const OTG_HS_HCDMA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x134); - - /// address: 0x40040554 - /// OTG_HS host channel-2 DMA address - /// register - pub const OTG_HS_HCDMA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x154); - - /// address: 0x40040574 - /// OTG_HS host channel-3 DMA address - /// register - pub const OTG_HS_HCDMA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x174); - - /// address: 0x40040594 - /// OTG_HS host channel-4 DMA address - /// register - pub const OTG_HS_HCDMA4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x194); - - /// address: 0x400405b4 - /// OTG_HS host channel-5 DMA address - /// register - pub const OTG_HS_HCDMA5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1b4); - - /// address: 0x400405d4 - /// OTG_HS host channel-6 DMA address - /// register - pub const OTG_HS_HCDMA6 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1d4); - - /// address: 0x400405f4 - /// OTG_HS host channel-7 DMA address - /// register - pub const OTG_HS_HCDMA7 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x1f4); - - /// address: 0x40040614 - /// OTG_HS host channel-8 DMA address - /// register - pub const OTG_HS_HCDMA8 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x214); - - /// address: 0x40040634 - /// OTG_HS host channel-9 DMA address - /// register - pub const OTG_HS_HCDMA9 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x234); - - /// address: 0x40040654 - /// OTG_HS host channel-10 DMA address - /// register - pub const OTG_HS_HCDMA10 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x254); - - /// address: 0x40040674 - /// OTG_HS host channel-11 DMA address - /// register - pub const OTG_HS_HCDMA11 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x274); - }; - - /// USB on the go high speed - pub const OTG_HS_DEVICE = struct { - pub const base_address = 0x40040800; - - /// address: 0x40040800 - /// OTG_HS device configuration - /// register - pub const OTG_HS_DCFG = @intToPtr(*volatile Mmio(32, packed struct { - /// Device speed - DSPD: u2, - /// Nonzero-length status OUT - /// handshake - NZLSOHSK: u1, - reserved0: u1, - /// Device address - DAD: u7, - /// Periodic (micro)frame - /// interval - PFIVL: u2, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Periodic scheduling - /// interval - PERSCHIVL: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x0); - - /// address: 0x40040804 - /// OTG_HS device control register - pub const OTG_HS_DCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Remote wakeup signaling - RWUSIG: u1, - /// Soft disconnect - SDIS: u1, - /// Global IN NAK status - GINSTS: u1, - /// Global OUT NAK status - GONSTS: u1, - /// Test control - TCTL: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on programming done - POPRGDNE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x4); - - /// address: 0x40040808 - /// OTG_HS device status register - pub const OTG_HS_DSTS = @intToPtr(*volatile Mmio(32, packed struct { - /// Suspend status - SUSPSTS: u1, - /// Enumerated speed - ENUMSPD: u2, - /// Erratic error - EERR: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Frame number of the received - /// SOF - FNSOF: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - }), base_address + 0x8); - - /// address: 0x40040810 - /// OTG_HS device IN endpoint common interrupt - /// mask register - pub const OTG_HS_DIEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (nonisochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// FIFO underrun mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x10); - - /// address: 0x40040814 - /// OTG_HS device OUT endpoint common interrupt - /// mask register - pub const OTG_HS_DOEPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// SETUP phase done mask - STUPM: u1, - /// OUT token received when endpoint - /// disabled mask - OTEPDM: u1, - reserved1: u1, - /// Back-to-back SETUP packets received - /// mask - B2BSTUP: u1, - reserved2: u1, - /// OUT packet error mask - OPEM: u1, - /// BNA interrupt mask - BOIM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x14); - - /// address: 0x40040818 - /// OTG_HS device all endpoints interrupt - /// register - pub const OTG_HS_DAINT = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint interrupt bits - IEPINT: u16, - /// OUT endpoint interrupt - /// bits - OEPINT: u16, - }), base_address + 0x18); - - /// address: 0x4004081c - /// OTG_HS all endpoints interrupt mask - /// register - pub const OTG_HS_DAINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP interrupt mask bits - IEPM: u16, - /// OUT EP interrupt mask bits - OEPM: u16, - }), base_address + 0x1c); - - /// address: 0x40040828 - /// OTG_HS device VBUS discharge time - /// register - pub const OTG_HS_DVBUSDIS = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS discharge time - VBUSDT: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4004082c - /// OTG_HS device VBUS pulsing time - /// register - pub const OTG_HS_DVBUSPULSE = @intToPtr(*volatile Mmio(32, packed struct { - /// Device VBUS pulsing time - DVBUSP: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - }), base_address + 0x2c); - - /// address: 0x40040830 - /// OTG_HS Device threshold control - /// register - pub const OTG_HS_DTHRCTL = @intToPtr(*volatile Mmio(32, packed struct { - /// Nonisochronous IN endpoints threshold - /// enable - NONISOTHREN: u1, - /// ISO IN endpoint threshold - /// enable - ISOTHREN: u1, - /// Transmit threshold length - TXTHRLEN: u9, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Receive threshold enable - RXTHREN: u1, - /// Receive threshold length - RXTHRLEN: u9, - reserved5: u1, - /// Arbiter parking enable - ARPEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x30); - - /// address: 0x40040834 - /// OTG_HS device IN endpoint FIFO empty - /// interrupt mask register - pub const OTG_HS_DIEPEMPMSK = @intToPtr(*volatile Mmio(32, packed struct { - /// IN EP Tx FIFO empty interrupt mask - /// bits - INEPTXFEM: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x34); - - /// address: 0x40040838 - /// OTG_HS device each endpoint interrupt - /// register - pub const OTG_HS_DEACHINT = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// IN endpoint 1interrupt bit - IEP1INT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// OUT endpoint 1 interrupt - /// bit - OEP1INT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x38); - - /// address: 0x4004083c - /// OTG_HS device each endpoint interrupt - /// register mask - pub const OTG_HS_DEACHINTMSK = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// IN Endpoint 1 interrupt mask - /// bit - IEP1INTM: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// OUT Endpoint 1 interrupt mask - /// bit - OEP1INTM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x3c); - - /// address: 0x40040840 - /// OTG_HS device each in endpoint-1 interrupt - /// register - pub const OTG_HS_DIEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask (nonisochronous - /// endpoints) - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// FIFO underrun mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// NAK interrupt mask - NAKM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x40); - - /// address: 0x40040880 - /// OTG_HS device each OUT endpoint-1 interrupt - /// register - pub const OTG_HS_DOEPEACHMSK1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed interrupt - /// mask - XFRCM: u1, - /// Endpoint disabled interrupt - /// mask - EPDM: u1, - reserved0: u1, - /// Timeout condition mask - TOM: u1, - /// IN token received when TxFIFO empty - /// mask - ITTXFEMSK: u1, - /// IN token received with EP mismatch - /// mask - INEPNMM: u1, - /// IN endpoint NAK effective - /// mask - INEPNEM: u1, - reserved1: u1, - /// OUT packet error mask - TXFURM: u1, - /// BNA interrupt mask - BIM: u1, - reserved2: u1, - reserved3: u1, - /// Bubble error interrupt - /// mask - BERRM: u1, - /// NAK interrupt mask - NAKM: u1, - /// NYET interrupt mask - NYETM: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x80); - - /// address: 0x40040900 - /// OTG device endpoint-0 control - /// register - pub const OTG_HS_DIEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x100); - - /// address: 0x40040920 - /// OTG device endpoint-1 control - /// register - pub const OTG_HS_DIEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x120); - - /// address: 0x40040940 - /// OTG device endpoint-2 control - /// register - pub const OTG_HS_DIEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x140); - - /// address: 0x40040960 - /// OTG device endpoint-3 control - /// register - pub const OTG_HS_DIEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x160); - - /// address: 0x40040980 - /// OTG device endpoint-4 control - /// register - pub const OTG_HS_DIEPCTL4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x180); - - /// address: 0x400409a0 - /// OTG device endpoint-5 control - /// register - pub const OTG_HS_DIEPCTL5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1a0); - - /// address: 0x400409c0 - /// OTG device endpoint-6 control - /// register - pub const OTG_HS_DIEPCTL6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1c0); - - /// address: 0x400409e0 - /// OTG device endpoint-7 control - /// register - pub const OTG_HS_DIEPCTL7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even/odd frame - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - reserved4: u1, - /// STALL handshake - Stall: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x1e0); - - /// address: 0x40040908 - /// OTG device endpoint-0 interrupt - /// register - pub const OTG_HS_DIEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x108); - - /// address: 0x40040928 - /// OTG device endpoint-1 interrupt - /// register - pub const OTG_HS_DIEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x128); - - /// address: 0x40040948 - /// OTG device endpoint-2 interrupt - /// register - pub const OTG_HS_DIEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x148); - - /// address: 0x40040968 - /// OTG device endpoint-3 interrupt - /// register - pub const OTG_HS_DIEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x168); - - /// address: 0x40040988 - /// OTG device endpoint-4 interrupt - /// register - pub const OTG_HS_DIEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x188); - - /// address: 0x400409a8 - /// OTG device endpoint-5 interrupt - /// register - pub const OTG_HS_DIEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1a8); - - /// address: 0x400409c8 - /// OTG device endpoint-6 interrupt - /// register - pub const OTG_HS_DIEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1c8); - - /// address: 0x400409e8 - /// OTG device endpoint-7 interrupt - /// register - pub const OTG_HS_DIEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// Timeout condition - TOC: u1, - /// IN token received when TxFIFO is - /// empty - ITTXFE: u1, - reserved1: u1, - /// IN endpoint NAK effective - INEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - /// Transmit Fifo Underrun - TXFIFOUDRN: u1, - /// Buffer not available - /// interrupt - BNA: u1, - reserved2: u1, - /// Packet dropped status - PKTDRPSTS: u1, - /// Babble error interrupt - BERR: u1, - /// NAK interrupt - NAK: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x1e8); - - /// address: 0x40040910 - /// OTG_HS device IN endpoint 0 transfer size - /// register - pub const OTG_HS_DIEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - }), base_address + 0x110); - - /// address: 0x40040914 - /// OTG_HS device endpoint-1 DMA address - /// register - pub const OTG_HS_DIEPDMA1 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x114); - - /// address: 0x40040934 - /// OTG_HS device endpoint-2 DMA address - /// register - pub const OTG_HS_DIEPDMA2 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x134); - - /// address: 0x40040954 - /// OTG_HS device endpoint-3 DMA address - /// register - pub const OTG_HS_DIEPDMA3 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x154); - - /// address: 0x40040974 - /// OTG_HS device endpoint-4 DMA address - /// register - pub const OTG_HS_DIEPDMA4 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x174); - - /// address: 0x40040994 - /// OTG_HS device endpoint-5 DMA address - /// register - pub const OTG_HS_DIEPDMA5 = @intToPtr(*volatile Mmio(32, packed struct { - /// DMA address - DMAADDR: u32, - }), base_address + 0x194); - - /// address: 0x40040918 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS0 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x118); - - /// address: 0x40040938 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS1 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x138); - - /// address: 0x40040958 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS2 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x158); - - /// address: 0x40040978 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS3 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x178); - - /// address: 0x40040998 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS4 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x198); - - /// address: 0x400409b8 - /// OTG_HS device IN endpoint transmit FIFO - /// status register - pub const OTG_HS_DTXFSTS5 = @intToPtr(*volatile Mmio(32, packed struct { - /// IN endpoint TxFIFO space - /// avail - INEPTFSAV: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1b8); - - /// address: 0x40040930 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x130); - - /// address: 0x40040950 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x150); - - /// address: 0x40040970 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x170); - - /// address: 0x40040990 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x190); - - /// address: 0x400409b0 - /// OTG_HS device endpoint transfer size - /// register - pub const OTG_HS_DIEPTSIZ5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Multi count - MCNT: u2, - padding0: u1, - }), base_address + 0x1b0); - - /// address: 0x40040b00 - /// OTG_HS device control OUT endpoint 0 control - /// register - pub const OTG_HS_DOEPCTL0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// USB active endpoint - USBAEP: u1, - reserved13: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved18: u1, - reserved19: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x300); - - /// address: 0x40040b20 - /// OTG device endpoint-1 control - /// register - pub const OTG_HS_DOEPCTL1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x320); - - /// address: 0x40040b40 - /// OTG device endpoint-2 control - /// register - pub const OTG_HS_DOEPCTL2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x340); - - /// address: 0x40040b60 - /// OTG device endpoint-3 control - /// register - pub const OTG_HS_DOEPCTL3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Maximum packet size - MPSIZ: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// USB active endpoint - USBAEP: u1, - /// Even odd frame/Endpoint data - /// PID - EONUM_DPID: u1, - /// NAK status - NAKSTS: u1, - /// Endpoint type - EPTYP: u2, - /// Snoop mode - SNPM: u1, - /// STALL handshake - Stall: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// Set DATA0 PID/Set even - /// frame - SD0PID_SEVNFRM: u1, - /// Set odd frame - SODDFRM: u1, - /// Endpoint disable - EPDIS: u1, - /// Endpoint enable - EPENA: u1, - }), base_address + 0x360); - - /// address: 0x40040b08 - /// OTG_HS device endpoint-0 interrupt - /// register - pub const OTG_HS_DOEPINT0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x308); - - /// address: 0x40040b28 - /// OTG_HS device endpoint-1 interrupt - /// register - pub const OTG_HS_DOEPINT1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x328); - - /// address: 0x40040b48 - /// OTG_HS device endpoint-2 interrupt - /// register - pub const OTG_HS_DOEPINT2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x348); - - /// address: 0x40040b68 - /// OTG_HS device endpoint-3 interrupt - /// register - pub const OTG_HS_DOEPINT3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x368); - - /// address: 0x40040b88 - /// OTG_HS device endpoint-4 interrupt - /// register - pub const OTG_HS_DOEPINT4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x388); - - /// address: 0x40040ba8 - /// OTG_HS device endpoint-5 interrupt - /// register - pub const OTG_HS_DOEPINT5 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3a8); - - /// address: 0x40040bc8 - /// OTG_HS device endpoint-6 interrupt - /// register - pub const OTG_HS_DOEPINT6 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3c8); - - /// address: 0x40040be8 - /// OTG_HS device endpoint-7 interrupt - /// register - pub const OTG_HS_DOEPINT7 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer completed - /// interrupt - XFRC: u1, - /// Endpoint disabled - /// interrupt - EPDISD: u1, - reserved0: u1, - /// SETUP phase done - STUP: u1, - /// OUT token received when endpoint - /// disabled - OTEPDIS: u1, - reserved1: u1, - /// Back-to-back SETUP packets - /// received - B2BSTUP: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// NYET interrupt - NYET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - }), base_address + 0x3e8); - - /// address: 0x40040b10 - /// OTG_HS device endpoint-1 transfer size - /// register - pub const OTG_HS_DOEPTSIZ0 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u7, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - /// Packet count - PKTCNT: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - /// SETUP packet count - STUPCNT: u2, - padding0: u1, - }), base_address + 0x310); - - /// address: 0x40040b30 - /// OTG_HS device endpoint-2 transfer size - /// register - pub const OTG_HS_DOEPTSIZ1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x330); - - /// address: 0x40040b50 - /// OTG_HS device endpoint-3 transfer size - /// register - pub const OTG_HS_DOEPTSIZ2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x350); - - /// address: 0x40040b70 - /// OTG_HS device endpoint-4 transfer size - /// register - pub const OTG_HS_DOEPTSIZ3 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x370); - - /// address: 0x40040b90 - /// OTG_HS device endpoint-5 transfer size - /// register - pub const OTG_HS_DOEPTSIZ4 = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer size - XFRSIZ: u19, - /// Packet count - PKTCNT: u10, - /// Received data PID/SETUP packet - /// count - RXDPID_STUPCNT: u2, - padding0: u1, - }), base_address + 0x390); - }; - - /// USB on the go high speed - pub const OTG_HS_PWRCLK = struct { - pub const base_address = 0x40040e00; - - /// address: 0x40040e00 - /// Power and clock gating control - /// register - pub const OTG_HS_PCGCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Stop PHY clock - STPPCLK: u1, - /// Gate HCLK - GATEHCLK: u1, - reserved0: u1, - reserved1: u1, - /// PHY suspended - PHYSUSP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x0); - }; - - /// LCD-TFT Controller - pub const LTDC = struct { - pub const base_address = 0x40016800; - - /// address: 0x40016808 - /// Synchronization Size Configuration - /// Register - pub const SSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Vertical Synchronization Height (in - /// units of horizontal scan line) - VSH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Horizontal Synchronization Width (in - /// units of pixel clock period) - HSW: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x8); - - /// address: 0x4001680c - /// Back Porch Configuration - /// Register - pub const BPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Accumulated Vertical back porch (in - /// units of horizontal scan line) - AVBP: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Accumulated Horizontal back porch (in - /// units of pixel clock period) - AHBP: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0xc); - - /// address: 0x40016810 - /// Active Width Configuration - /// Register - pub const AWCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Accumulated Active Height (in units of - /// horizontal scan line) - AAH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// AAV - AAV: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x10); - - /// address: 0x40016814 - /// Total Width Configuration - /// Register - pub const TWCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Total Height (in units of horizontal - /// scan line) - TOTALH: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Total Width (in units of pixel clock - /// period) - TOTALW: u10, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x14); - - /// address: 0x40016818 - /// Global Control Register - pub const GCR = @intToPtr(*volatile Mmio(32, packed struct { - /// LCD-TFT controller enable - /// bit - LTDCEN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Dither Blue Width - DBW: u3, - reserved3: u1, - /// Dither Green Width - DGW: u3, - reserved4: u1, - /// Dither Red Width - DRW: u3, - reserved5: u1, - /// Dither Enable - DEN: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - /// Pixel Clock Polarity - PCPOL: u1, - /// Data Enable Polarity - DEPOL: u1, - /// Vertical Synchronization - /// Polarity - VSPOL: u1, - /// Horizontal Synchronization - /// Polarity - HSPOL: u1, - }), base_address + 0x18); - - /// address: 0x40016824 - /// Shadow Reload Configuration - /// Register - pub const SRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Immediate Reload - IMR: u1, - /// Vertical Blanking Reload - VBR: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - padding29: u1, - }), base_address + 0x24); - - /// address: 0x4001682c - /// Background Color Configuration - /// Register - pub const BCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Background Color Red value - BC: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x2c); - - /// address: 0x40016834 - /// Interrupt Enable Register - pub const IER = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt Enable - LIE: u1, - /// FIFO Underrun Interrupt - /// Enable - FUIE: u1, - /// Transfer Error Interrupt - /// Enable - TERRIE: u1, - /// Register Reload interrupt - /// enable - RRIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x34); - - /// address: 0x40016838 - /// Interrupt Status Register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt flag - LIF: u1, - /// FIFO Underrun Interrupt - /// flag - FUIF: u1, - /// Transfer Error interrupt - /// flag - TERRIF: u1, - /// Register Reload Interrupt - /// Flag - RRIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x38); - - /// address: 0x4001683c - /// Interrupt Clear Register - pub const ICR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clears the Line Interrupt - /// Flag - CLIF: u1, - /// Clears the FIFO Underrun Interrupt - /// flag - CFUIF: u1, - /// Clears the Transfer Error Interrupt - /// Flag - CTERRIF: u1, - /// Clears Register Reload Interrupt - /// Flag - CRRIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x3c); - - /// address: 0x40016840 - /// Line Interrupt Position Configuration - /// Register - pub const LIPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Interrupt Position - LIPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x40); - - /// address: 0x40016844 - /// Current Position Status - /// Register - pub const CPSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Current Y Position - CYPOS: u16, - /// Current X Position - CXPOS: u16, - }), base_address + 0x44); - - /// address: 0x40016848 - /// Current Display Status - /// Register - pub const CDSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Vertical Data Enable display - /// Status - VDES: u1, - /// Horizontal Data Enable display - /// Status - HDES: u1, - /// Vertical Synchronization display - /// Status - VSYNCS: u1, - /// Horizontal Synchronization display - /// Status - HSYNCS: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - }), base_address + 0x48); - - /// address: 0x40016884 - /// Layerx Control Register - pub const L1CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Layer Enable - LEN: u1, - /// Color Keying Enable - COLKEN: u1, - reserved0: u1, - reserved1: u1, - /// Color Look-Up Table Enable - CLUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x84); - - /// address: 0x40016888 - /// Layerx Window Horizontal Position - /// Configuration Register - pub const L1WHPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Horizontal Start - /// Position - WHSTPOS: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Window Horizontal Stop - /// Position - WHSPPOS: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x88); - - /// address: 0x4001688c - /// Layerx Window Vertical Position - /// Configuration Register - pub const L1WVPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Vertical Start - /// Position - WVSTPOS: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window Vertical Stop - /// Position - WVSPPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x8c); - - /// address: 0x40016890 - /// Layerx Color Keying Configuration - /// Register - pub const L1CKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Key Blue value - CKBLUE: u8, - /// Color Key Green value - CKGREEN: u8, - /// Color Key Red value - CKRED: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x90); - - /// address: 0x40016894 - /// Layerx Pixel Format Configuration - /// Register - pub const L1PFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pixel Format - PF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x94); - - /// address: 0x40016898 - /// Layerx Constant Alpha Configuration - /// Register - pub const L1CACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Constant Alpha - CONSTA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x98); - - /// address: 0x4001689c - /// Layerx Default Color Configuration - /// Register - pub const L1DCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Default Color Blue - DCBLUE: u8, - /// Default Color Green - DCGREEN: u8, - /// Default Color Red - DCRED: u8, - /// Default Color Alpha - DCALPHA: u8, - }), base_address + 0x9c); - - /// address: 0x400168a0 - /// Layerx Blending Factors Configuration - /// Register - pub const L1BFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blending Factor 2 - BF2: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Blending Factor 1 - BF1: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xa0); - - /// address: 0x400168ac - /// Layerx Color Frame Buffer Address - /// Register - pub const L1CFBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Start - /// Address - CFBADD: u32, - }), base_address + 0xac); - - /// address: 0x400168b0 - /// Layerx Color Frame Buffer Length - /// Register - pub const L1CFBLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Line - /// Length - CFBLL: u13, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Color Frame Buffer Pitch in - /// bytes - CFBP: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0xb0); - - /// address: 0x400168b4 - /// Layerx ColorFrame Buffer Line Number - /// Register - pub const L1CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame Buffer Line Number - CFBLNBR: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0xb4); - - /// address: 0x400168c4 - /// Layerx CLUT Write Register - pub const L1CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue value - BLUE: u8, - /// Green value - GREEN: u8, - /// Red value - RED: u8, - /// CLUT Address - CLUTADD: u8, - }), base_address + 0xc4); - - /// address: 0x40016904 - /// Layerx Control Register - pub const L2CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Layer Enable - LEN: u1, - /// Color Keying Enable - COLKEN: u1, - reserved0: u1, - reserved1: u1, - /// Color Look-Up Table Enable - CLUTEN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x104); - - /// address: 0x40016908 - /// Layerx Window Horizontal Position - /// Configuration Register - pub const L2WHPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Horizontal Start - /// Position - WHSTPOS: u12, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// Window Horizontal Stop - /// Position - WHSPPOS: u12, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - }), base_address + 0x108); - - /// address: 0x4001690c - /// Layerx Window Vertical Position - /// Configuration Register - pub const L2WVPCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Window Vertical Start - /// Position - WVSTPOS: u11, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Window Vertical Stop - /// Position - WVSPPOS: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - }), base_address + 0x10c); - - /// address: 0x40016910 - /// Layerx Color Keying Configuration - /// Register - pub const L2CKCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Key Blue value - CKBLUE: u8, - /// Color Key Green value - CKGREEN: u7, - /// Color Key Red value - CKRED: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x110); - - /// address: 0x40016914 - /// Layerx Pixel Format Configuration - /// Register - pub const L2PFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Pixel Format - PF: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x114); - - /// address: 0x40016918 - /// Layerx Constant Alpha Configuration - /// Register - pub const L2CACR = @intToPtr(*volatile Mmio(32, packed struct { - /// Constant Alpha - CONSTA: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x118); - - /// address: 0x4001691c - /// Layerx Default Color Configuration - /// Register - pub const L2DCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Default Color Blue - DCBLUE: u8, - /// Default Color Green - DCGREEN: u8, - /// Default Color Red - DCRED: u8, - /// Default Color Alpha - DCALPHA: u8, - }), base_address + 0x11c); - - /// address: 0x40016920 - /// Layerx Blending Factors Configuration - /// Register - pub const L2BFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blending Factor 2 - BF2: u3, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Blending Factor 1 - BF1: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x120); - - /// address: 0x4001692c - /// Layerx Color Frame Buffer Address - /// Register - pub const L2CFBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Start - /// Address - CFBADD: u32, - }), base_address + 0x12c); - - /// address: 0x40016930 - /// Layerx Color Frame Buffer Length - /// Register - pub const L2CFBLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color Frame Buffer Line - /// Length - CFBLL: u13, - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Color Frame Buffer Pitch in - /// bytes - CFBP: u13, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x130); - - /// address: 0x40016934 - /// Layerx ColorFrame Buffer Line Number - /// Register - pub const L2CFBLNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame Buffer Line Number - CFBLNBR: u11, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - }), base_address + 0x134); - - /// address: 0x40016944 - /// Layerx CLUT Write Register - pub const L2CLUTWR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue value - BLUE: u8, - /// Green value - GREEN: u8, - /// Red value - RED: u8, - /// CLUT Address - CLUTADD: u8, - }), base_address + 0x144); - }; - - /// Serial audio interface - pub const SAI = struct { - pub const base_address = 0x40015800; - - /// address: 0x40015824 - /// BConfiguration register 1 - pub const BCR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Audio block mode - MODE: u2, - /// Protocol configuration - PRTCFG: u2, - reserved0: u1, - /// Data size - DS: u3, - /// Least significant bit - /// first - LSBFIRST: u1, - /// Clock strobing edge - CKSTR: u1, - /// Synchronization enable - SYNCEN: u2, - /// Mono mode - MONO: u1, - /// Output drive - OutDri: u1, - reserved1: u1, - reserved2: u1, - /// Audio block B enable - SAIBEN: u1, - /// DMA enable - DMAEN: u1, - reserved3: u1, - /// No divider - NODIV: u1, - /// Master clock divider - MCJDIV: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x24); - - /// address: 0x40015828 - /// BConfiguration register 2 - pub const BCR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold - FTH: u3, - /// FIFO flush - FFLUS: u1, - /// Tristate management on data - /// line - TRIS: u1, - /// Mute - MUTE: u1, - /// Mute value - MUTEVAL: u1, - /// Mute counter - MUTECN: u6, - /// Complement bit - CPL: u1, - /// Companding mode - COMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x28); - - /// address: 0x4001582c - /// BFRCR - pub const BFRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame length - FRL: u8, - /// Frame synchronization active level - /// length - FSALL: u7, - reserved0: u1, - /// Frame synchronization - /// definition - FSDEF: u1, - /// Frame synchronization - /// polarity - FSPOL: u1, - /// Frame synchronization - /// offset - FSOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x2c); - - /// address: 0x40015830 - /// BSlot register - pub const BSLOTR = @intToPtr(*volatile Mmio(32, packed struct { - /// First bit offset - FBOFF: u5, - reserved0: u1, - /// Slot size - SLOTSZ: u2, - /// Number of slots in an audio - /// frame - NBSLOT: u4, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Slot enable - SLOTEN: u16, - }), base_address + 0x30); - - /// address: 0x40015834 - /// BInterrupt mask register2 - pub const BIM = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun/underrun interrupt - /// enable - OVRUDRIE: u1, - /// Mute detection interrupt - /// enable - MUTEDET: u1, - /// Wrong clock configuration interrupt - /// enable - WCKCFG: u1, - /// FIFO request interrupt - /// enable - FREQIE: u1, - /// Codec not ready interrupt - /// enable - CNRDYIE: u1, - /// Anticipated frame synchronization - /// detection interrupt enable - AFSDETIE: u1, - /// Late frame synchronization detection - /// interrupt enable - LFSDETIE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x34); - - /// address: 0x40015838 - /// BStatus register - pub const BSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun / underrun - OVRUDR: u1, - /// Mute detection - MUTEDET: u1, - /// Wrong clock configuration - /// flag - WCKCFG: u1, - /// FIFO request - FREQ: u1, - /// Codec not ready - CNRDY: u1, - /// Anticipated frame synchronization - /// detection - AFSDET: u1, - /// Late frame synchronization - /// detection - LFSDET: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// FIFO level threshold - FLVL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x38); - - /// address: 0x4001583c - /// BClear flag register - pub const BCLRFR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear overrun / underrun - OVRUDR: u1, - /// Mute detection flag - MUTEDET: u1, - /// Clear wrong clock configuration - /// flag - WCKCFG: u1, - reserved0: u1, - /// Clear codec not ready flag - CNRDY: u1, - /// Clear anticipated frame synchronization - /// detection flag - CAFSDET: u1, - /// Clear late frame synchronization - /// detection flag - LFSDET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x3c); - - /// address: 0x40015840 - /// BData register - pub const BDR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data - DATA: u32, - }), base_address + 0x40); - - /// address: 0x40015804 - /// AConfiguration register 1 - pub const ACR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Audio block mode - MODE: u2, - /// Protocol configuration - PRTCFG: u2, - reserved0: u1, - /// Data size - DS: u3, - /// Least significant bit - /// first - LSBFIRST: u1, - /// Clock strobing edge - CKSTR: u1, - /// Synchronization enable - SYNCEN: u2, - /// Mono mode - MONO: u1, - /// Output drive - OutDri: u1, - reserved1: u1, - reserved2: u1, - /// Audio block A enable - SAIAEN: u1, - /// DMA enable - DMAEN: u1, - reserved3: u1, - /// No divider - NODIV: u1, - /// Master clock divider - MCJDIV: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0x40015808 - /// AConfiguration register 2 - pub const ACR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// FIFO threshold - FTH: u3, - /// FIFO flush - FFLUS: u1, - /// Tristate management on data - /// line - TRIS: u1, - /// Mute - MUTE: u1, - /// Mute value - MUTEVAL: u1, - /// Mute counter - MUTECN: u6, - /// Complement bit - CPL: u1, - /// Companding mode - COMP: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4001580c - /// AFRCR - pub const AFRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Frame length - FRL: u8, - /// Frame synchronization active level - /// length - FSALL: u7, - reserved0: u1, - /// Frame synchronization - /// definition - FSDEF: u1, - /// Frame synchronization - /// polarity - FSPOL: u1, - /// Frame synchronization - /// offset - FSOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0xc); - - /// address: 0x40015810 - /// ASlot register - pub const ASLOTR = @intToPtr(*volatile Mmio(32, packed struct { - /// First bit offset - FBOFF: u5, - reserved0: u1, - /// Slot size - SLOTSZ: u2, - /// Number of slots in an audio - /// frame - NBSLOT: u4, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Slot enable - SLOTEN: u16, - }), base_address + 0x10); - - /// address: 0x40015814 - /// AInterrupt mask register2 - pub const AIM = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun/underrun interrupt - /// enable - OVRUDRIE: u1, - /// Mute detection interrupt - /// enable - MUTEDET: u1, - /// Wrong clock configuration interrupt - /// enable - WCKCFG: u1, - /// FIFO request interrupt - /// enable - FREQIE: u1, - /// Codec not ready interrupt - /// enable - CNRDYIE: u1, - /// Anticipated frame synchronization - /// detection interrupt enable - AFSDETIE: u1, - /// Late frame synchronization detection - /// interrupt enable - LFSDET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x14); - - /// address: 0x40015818 - /// AStatus register - pub const ASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Overrun / underrun - OVRUDR: u1, - /// Mute detection - MUTEDET: u1, - /// Wrong clock configuration flag. This bit - /// is read only. - WCKCFG: u1, - /// FIFO request - FREQ: u1, - /// Codec not ready - CNRDY: u1, - /// Anticipated frame synchronization - /// detection - AFSDET: u1, - /// Late frame synchronization - /// detection - LFSDET: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// FIFO level threshold - FLVL: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x18); - - /// address: 0x4001581c - /// AClear flag register - pub const ACLRFR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear overrun / underrun - OVRUDR: u1, - /// Mute detection flag - MUTEDET: u1, - /// Clear wrong clock configuration - /// flag - WCKCFG: u1, - reserved0: u1, - /// Clear codec not ready flag - CNRDY: u1, - /// Clear anticipated frame synchronization - /// detection flag. - CAFSDET: u1, - /// Clear late frame synchronization - /// detection flag - LFSDET: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - }), base_address + 0x1c); - - /// address: 0x40015820 - /// AData register - pub const ADR = @intToPtr(*volatile Mmio(32, packed struct { - /// Data - DATA: u32, - }), base_address + 0x20); - }; - - /// DMA2D controller - pub const DMA2D = struct { - pub const base_address = 0x4002b000; - - /// address: 0x4002b000 - /// control register - pub const CR = @intToPtr(*volatile Mmio(32, packed struct { - /// Start - START: u1, - /// Suspend - SUSP: u1, - /// Abort - ABORT: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Transfer error interrupt - /// enable - TEIE: u1, - /// Transfer complete interrupt - /// enable - TCIE: u1, - /// Transfer watermark interrupt - /// enable - TWIE: u1, - /// CLUT access error interrupt - /// enable - CAEIE: u1, - /// CLUT transfer complete interrupt - /// enable - CTCIE: u1, - /// Configuration Error Interrupt - /// Enable - CEIE: u1, - reserved5: u1, - reserved6: u1, - /// DMA2D mode - MODE: u2, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - }), base_address + 0x0); - - /// address: 0x4002b004 - /// Interrupt Status Register - pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { - /// Transfer error interrupt - /// flag - TEIF: u1, - /// Transfer complete interrupt - /// flag - TCIF: u1, - /// Transfer watermark interrupt - /// flag - TWIF: u1, - /// CLUT access error interrupt - /// flag - CAEIF: u1, - /// CLUT transfer complete interrupt - /// flag - CTCIF: u1, - /// Configuration error interrupt - /// flag - CEIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x4); - - /// address: 0x4002b008 - /// interrupt flag clear register - pub const IFCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clear Transfer error interrupt - /// flag - CTEIF: u1, - /// Clear transfer complete interrupt - /// flag - CTCIF: u1, - /// Clear transfer watermark interrupt - /// flag - CTWIF: u1, - /// Clear CLUT access error interrupt - /// flag - CAECIF: u1, - /// Clear CLUT transfer complete interrupt - /// flag - CCTCIF: u1, - /// Clear configuration error interrupt - /// flag - CCEIF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - }), base_address + 0x8); - - /// address: 0x4002b00c - /// foreground memory address - /// register - pub const FGMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0xc); - - /// address: 0x4002b010 - /// foreground offset register - pub const FGOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line offset - LO: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x10); - - /// address: 0x4002b014 - /// background memory address - /// register - pub const BGMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x14); - - /// address: 0x4002b018 - /// background offset register - pub const BGOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line offset - LO: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x18); - - /// address: 0x4002b01c - /// foreground PFC control - /// register - pub const FGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color mode - CM: u4, - /// CLUT color mode - CCM: u1, - /// Start - START: u1, - reserved0: u1, - reserved1: u1, - /// CLUT size - CS: u8, - /// Alpha mode - AM: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Alpha value - ALPHA: u8, - }), base_address + 0x1c); - - /// address: 0x4002b020 - /// foreground color register - pub const FGCOLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x20); - - /// address: 0x4002b024 - /// background PFC control - /// register - pub const BGPFCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color mode - CM: u4, - /// CLUT Color mode - CCM: u1, - /// Start - START: u1, - reserved0: u1, - reserved1: u1, - /// CLUT size - CS: u8, - /// Alpha mode - AM: u2, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Alpha value - ALPHA: u8, - }), base_address + 0x24); - - /// address: 0x4002b028 - /// background color register - pub const BGCOLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x28); - - /// address: 0x4002b02c - /// foreground CLUT memory address - /// register - pub const FGCMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory Address - MA: u32, - }), base_address + 0x2c); - - /// address: 0x4002b030 - /// background CLUT memory address - /// register - pub const BGCMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory address - MA: u32, - }), base_address + 0x30); - - /// address: 0x4002b034 - /// output PFC control register - pub const OPFCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Color mode - CM: u3, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x34); - - /// address: 0x4002b038 - /// output color register - pub const OCOLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Blue Value - BLUE: u8, - /// Green Value - GREEN: u8, - /// Red Value - RED: u8, - /// Alpha Channel Value - APLHA: u8, - }), base_address + 0x38); - - /// address: 0x4002b03c - /// output memory address register - pub const OMAR = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory Address - MA: u32, - }), base_address + 0x3c); - - /// address: 0x4002b040 - /// output offset register - pub const OOR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line Offset - LO: u14, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - }), base_address + 0x40); - - /// address: 0x4002b044 - /// number of line register - pub const NLR = @intToPtr(*volatile Mmio(32, packed struct { - /// Number of lines - NL: u16, - /// Pixel per lines - PL: u14, - padding0: u1, - padding1: u1, - }), base_address + 0x44); - - /// address: 0x4002b048 - /// line watermark register - pub const LWR = @intToPtr(*volatile Mmio(32, packed struct { - /// Line watermark - LW: u16, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x48); - - /// address: 0x4002b04c - /// AHB master timer configuration - /// register - pub const AMTCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable - EN: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Dead Time - DT: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x4c); - - /// address: 0x4002b400 - /// FGCLUT - pub const FGCLUT = @intToPtr(*volatile Mmio(32, packed struct { - /// BLUE - BLUE: u8, - /// GREEN - GREEN: u8, - /// RED - RED: u8, - /// APLHA - APLHA: u8, - }), base_address + 0x400); - - /// address: 0x4002b800 - /// BGCLUT - pub const BGCLUT = @intToPtr(*volatile Mmio(32, packed struct { - /// BLUE - BLUE: u8, - /// GREEN - GREEN: u8, - /// RED - RED: u8, - /// APLHA - APLHA: u8, - }), base_address + 0x800); - }; - - /// Inter-integrated circuit - pub const I2C3 = struct { - pub const base_address = 0x40005c00; - - /// address: 0x40005c00 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005c04 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005c08 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x40005c0c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005c10 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005c14 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005c18 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x40005c1c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005c20 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - - /// address: 0x40005c24 - /// I2C FLTR register - pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x24); - }; - pub const I2C2 = struct { - pub const base_address = 0x40005800; - - /// address: 0x40005800 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005804 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005808 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000580c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005810 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005814 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005818 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000581c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005820 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - - /// address: 0x40005824 - /// I2C FLTR register - pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x24); - }; - pub const I2C1 = struct { - pub const base_address = 0x40005400; - - /// address: 0x40005400 - /// Control register 1 - pub const CR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral enable - PE: u1, - /// SMBus mode - SMBUS: u1, - reserved0: u1, - /// SMBus type - SMBTYPE: u1, - /// ARP enable - ENARP: u1, - /// PEC enable - ENPEC: u1, - /// General call enable - ENGC: u1, - /// Clock stretching disable (Slave - /// mode) - NOSTRETCH: u1, - /// Start generation - START: u1, - /// Stop generation - STOP: u1, - /// Acknowledge enable - ACK: u1, - /// Acknowledge/PEC Position (for data - /// reception) - POS: u1, - /// Packet error checking - PEC: u1, - /// SMBus alert - ALERT: u1, - reserved1: u1, - /// Software reset - SWRST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x0); - - /// address: 0x40005404 - /// Control register 2 - pub const CR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Peripheral clock frequency - FREQ: u6, - reserved0: u1, - reserved1: u1, - /// Error interrupt enable - ITERREN: u1, - /// Event interrupt enable - ITEVTEN: u1, - /// Buffer interrupt enable - ITBUFEN: u1, - /// DMA requests enable - DMAEN: u1, - /// DMA last transfer - LAST: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - }), base_address + 0x4); - - /// address: 0x40005408 - /// Own address register 1 - pub const OAR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Interface address - ADD0: u1, - /// Interface address - ADD7: u7, - /// Interface address - ADD10: u2, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Addressing mode (slave - /// mode) - ADDMODE: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x8); - - /// address: 0x4000540c - /// Own address register 2 - pub const OAR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Dual addressing mode - /// enable - ENDUAL: u1, - /// Interface address - ADD2: u7, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0xc); - - /// address: 0x40005410 - /// Data register - pub const DR = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x10); - - /// address: 0x40005414 - /// Status register 1 - pub const SR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Start bit (Master mode) - SB: u1, - /// Address sent (master mode)/matched - /// (slave mode) - ADDR: u1, - /// Byte transfer finished - BTF: u1, - /// 10-bit header sent (Master - /// mode) - ADD10: u1, - /// Stop detection (slave - /// mode) - STOPF: u1, - reserved0: u1, - /// Data register not empty - /// (receivers) - RxNE: u1, - /// Data register empty - /// (transmitters) - TxE: u1, - /// Bus error - BERR: u1, - /// Arbitration lost (master - /// mode) - ARLO: u1, - /// Acknowledge failure - AF: u1, - /// Overrun/Underrun - OVR: u1, - /// PEC Error in reception - PECERR: u1, - reserved1: u1, - /// Timeout or Tlow error - TIMEOUT: u1, - /// SMBus alert - SMBALERT: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x14); - - /// address: 0x40005418 - /// Status register 2 - pub const SR2 = @intToPtr(*volatile Mmio(32, packed struct { - /// Master/slave - MSL: u1, - /// Bus busy - BUSY: u1, - /// Transmitter/receiver - TRA: u1, - reserved0: u1, - /// General call address (Slave - /// mode) - GENCALL: u1, - /// SMBus device default address (Slave - /// mode) - SMBDEFAULT: u1, - /// SMBus host header (Slave - /// mode) - SMBHOST: u1, - /// Dual flag (Slave mode) - DUALF: u1, - /// acket error checking - /// register - PEC: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x18); - - /// address: 0x4000541c - /// Clock control register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Clock control register in Fast/Standard - /// mode (Master mode) - CCR: u12, - reserved0: u1, - reserved1: u1, - /// Fast mode duty cycle - DUTY: u1, - /// I2C master mode selection - F_S: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - }), base_address + 0x1c); - - /// address: 0x40005420 - /// TRISE register - pub const TRISE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x20); - - /// address: 0x40005424 - /// I2C FLTR register - pub const FLTR = @intToPtr(*volatile Mmio(32, packed struct { - /// Digital noise filter - DNF: u4, - /// Analog noise filter OFF - ANOFF: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x24); - }; - - /// Floting point unit - pub const FPU = struct { - pub const base_address = 0xe000ef34; - - /// address: 0xe000ef34 - /// Floating-point context control - /// register - pub const FPCCR = @intToPtr(*volatile Mmio(32, packed struct { - /// LSPACT - LSPACT: u1, - /// USER - USER: u1, - reserved0: u1, - /// THREAD - THREAD: u1, - /// HFRDY - HFRDY: u1, - /// MMRDY - MMRDY: u1, - /// BFRDY - BFRDY: u1, - reserved1: u1, - /// MONRDY - MONRDY: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - /// LSPEN - LSPEN: u1, - /// ASPEN - ASPEN: u1, - }), base_address + 0x0); - - /// address: 0xe000ef38 - /// Floating-point context address - /// register - pub const FPCAR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - /// Location of unpopulated - /// floating-point - ADDRESS: u29, - }), base_address + 0x4); - - /// address: 0xe000ef3c - /// Floating-point status control - /// register - pub const FPSCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Invalid operation cumulative exception - /// bit - IOC: u1, - /// Division by zero cumulative exception - /// bit. - DZC: u1, - /// Overflow cumulative exception - /// bit - OFC: u1, - /// Underflow cumulative exception - /// bit - UFC: u1, - /// Inexact cumulative exception - /// bit - IXC: u1, - reserved0: u1, - reserved1: u1, - /// Input denormal cumulative exception - /// bit. - IDC: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Rounding Mode control - /// field - RMode: u2, - /// Flush-to-zero mode control - /// bit: - FZ: u1, - /// Default NaN mode control - /// bit - DN: u1, - /// Alternative half-precision control - /// bit - AHP: u1, - reserved16: u1, - /// Overflow condition code - /// flag - V: u1, - /// Carry condition code flag - C: u1, - /// Zero condition code flag - Z: u1, - /// Negative condition code - /// flag - N: u1, - }), base_address + 0x8); - }; - - /// Memory protection unit - pub const MPU = struct { - pub const base_address = 0xe000ed90; - - /// address: 0xe000ed90 - /// MPU type register - pub const MPU_TYPER = @intToPtr(*volatile Mmio(32, packed struct { - /// Separate flag - SEPARATE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - /// Number of MPU data regions - DREGION: u8, - /// Number of MPU instruction - /// regions - IREGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - - /// address: 0xe000ed94 - /// MPU control register - pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Enables the MPU - ENABLE: u1, - /// Enables the operation of MPU during hard - /// fault - HFNMIENA: u1, - /// Enable priviliged software access to - /// default memory map - PRIVDEFENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - padding27: u1, - padding28: u1, - }), base_address + 0x4); - - /// address: 0xe000ed98 - /// MPU region number register - pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region - REGION: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - }), base_address + 0x8); - - /// address: 0xe000ed9c - /// MPU region base address - /// register - pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// MPU region field - REGION: u4, - /// MPU region number valid - VALID: u1, - /// Region base address field - ADDR: u27, - }), base_address + 0xc); - - /// address: 0xe000eda0 - /// MPU region attribute and size - /// register - pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Region enable bit. - ENABLE: u1, - /// Size of the MPU protection - /// region - SIZE: u5, - reserved0: u1, - reserved1: u1, - /// Subregion disable bits - SRD: u8, - /// memory attribute - B: u1, - /// memory attribute - C: u1, - /// Shareable memory attribute - S: u1, - /// memory attribute - TEX: u3, - reserved2: u1, - reserved3: u1, - /// Access permission - AP: u3, - reserved4: u1, - /// Instruction access disable - /// bit - XN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - }), base_address + 0x10); - }; - - /// SysTick timer - pub const STK = struct { - pub const base_address = 0xe000e010; - - /// address: 0xe000e010 - /// SysTick control and status - /// register - pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Counter enable - ENABLE: u1, - /// SysTick exception request - /// enable - TICKINT: u1, - /// Clock source selection - CLKSOURCE: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - /// COUNTFLAG - COUNTFLAG: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - }), base_address + 0x0); - - /// address: 0xe000e014 - /// SysTick reload value register - pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { - /// RELOAD value - RELOAD: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x4); - - /// address: 0xe000e018 - /// SysTick current value register - pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { - /// Current counter value - CURRENT: u24, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x8); - - /// address: 0xe000e01c - /// SysTick calibration value - /// register - pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { - /// Calibration value - TENMS: u24, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - /// SKEW flag: Indicates whether the TENMS - /// value is exact - SKEW: u1, - /// NOREF flag. Reads as zero - NOREF: u1, - }), base_address + 0xc); - }; - - /// System control block - pub const SCB = struct { - pub const base_address = 0xe000ed00; - - /// address: 0xe000ed00 - /// CPUID base register - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { - /// Revision number - Revision: u4, - /// Part number of the - /// processor - PartNo: u12, - /// Reads as 0xF - Constant: u4, - /// Variant number - Variant: u4, - /// Implementer code - Implementer: u8, - }), base_address + 0x0); - - /// address: 0xe000ed04 - /// Interrupt control and state - /// register - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Active vector - VECTACTIVE: u9, - reserved0: u1, - reserved1: u1, - /// Return to base level - RETTOBASE: u1, - /// Pending vector - VECTPENDING: u7, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// Interrupt pending flag - ISRPENDING: u1, - reserved5: u1, - reserved6: u1, - /// SysTick exception clear-pending - /// bit - PENDSTCLR: u1, - /// SysTick exception set-pending - /// bit - PENDSTSET: u1, - /// PendSV clear-pending bit - PENDSVCLR: u1, - /// PendSV set-pending bit - PENDSVSET: u1, - reserved7: u1, - reserved8: u1, - /// NMI set-pending bit. - NMIPENDSET: u1, - }), base_address + 0x4); - - /// address: 0xe000ed08 - /// Vector table offset register - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// Vector table base offset - /// field - TBLOFF: u21, - padding0: u1, - padding1: u1, - }), base_address + 0x8); - - /// address: 0xe000ed0c - /// Application interrupt and reset control - /// register - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { - /// VECTRESET - VECTRESET: u1, - /// VECTCLRACTIVE - VECTCLRACTIVE: u1, - /// SYSRESETREQ - SYSRESETREQ: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// PRIGROUP - PRIGROUP: u3, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - /// ENDIANESS - ENDIANESS: u1, - /// Register key - VECTKEYSTAT: u16, - }), base_address + 0xc); - - /// address: 0xe000ed10 - /// System control register - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// SLEEPONEXIT - SLEEPONEXIT: u1, - /// SLEEPDEEP - SLEEPDEEP: u1, - reserved1: u1, - /// Send Event on Pending bit - SEVEONPEND: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - padding23: u1, - padding24: u1, - padding25: u1, - padding26: u1, - }), base_address + 0x10); - - /// address: 0xe000ed14 - /// Configuration and control - /// register - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - /// Configures how the processor enters - /// Thread mode - NONBASETHRDENA: u1, - /// USERSETMPEND - USERSETMPEND: u1, - reserved0: u1, - /// UNALIGN_ TRP - UNALIGN__TRP: u1, - /// DIV_0_TRP - DIV_0_TRP: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// BFHFNMIGN - BFHFNMIGN: u1, - /// STKALIGN - STKALIGN: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x14); - - /// address: 0xe000ed18 - /// System handler priority - /// registers - pub const SHPR1 = @intToPtr(*volatile Mmio(32, packed struct { - /// Priority of system handler - /// 4 - PRI_4: u8, - /// Priority of system handler - /// 5 - PRI_5: u8, - /// Priority of system handler - /// 6 - PRI_6: u8, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x18); - - /// address: 0xe000ed1c - /// System handler priority - /// registers - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - /// Priority of system handler - /// 11 - PRI_11: u8, - }), base_address + 0x1c); - - /// address: 0xe000ed20 - /// System handler priority - /// registers - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - /// Priority of system handler - /// 14 - PRI_14: u8, - /// Priority of system handler - /// 15 - PRI_15: u8, - }), base_address + 0x20); - - /// address: 0xe000ed24 - /// System handler control and state - /// register - pub const SHCRS = @intToPtr(*volatile Mmio(32, packed struct { - /// Memory management fault exception active - /// bit - MEMFAULTACT: u1, - /// Bus fault exception active - /// bit - BUSFAULTACT: u1, - reserved0: u1, - /// Usage fault exception active - /// bit - USGFAULTACT: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - /// SVC call active bit - SVCALLACT: u1, - /// Debug monitor active bit - MONITORACT: u1, - reserved4: u1, - /// PendSV exception active - /// bit - PENDSVACT: u1, - /// SysTick exception active - /// bit - SYSTICKACT: u1, - /// Usage fault exception pending - /// bit - USGFAULTPENDED: u1, - /// Memory management fault exception - /// pending bit - MEMFAULTPENDED: u1, - /// Bus fault exception pending - /// bit - BUSFAULTPENDED: u1, - /// SVC call pending bit - SVCALLPENDED: u1, - /// Memory management fault enable - /// bit - MEMFAULTENA: u1, - /// Bus fault enable bit - BUSFAULTENA: u1, - /// Usage fault enable bit - USGFAULTENA: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - }), base_address + 0x24); - - /// address: 0xe000ed28 - /// Configurable fault status - /// register - pub const CFSR_UFSR_BFSR_MMFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Instruction access violation - /// flag - IACCVIOL: u1, - reserved1: u1, - /// Memory manager fault on unstacking for a - /// return from exception - MUNSTKERR: u1, - /// Memory manager fault on stacking for - /// exception entry. - MSTKERR: u1, - /// MLSPERR - MLSPERR: u1, - reserved2: u1, - /// Memory Management Fault Address Register - /// (MMAR) valid flag - MMARVALID: u1, - /// Instruction bus error - IBUSERR: u1, - /// Precise data bus error - PRECISERR: u1, - /// Imprecise data bus error - IMPRECISERR: u1, - /// Bus fault on unstacking for a return - /// from exception - UNSTKERR: u1, - /// Bus fault on stacking for exception - /// entry - STKERR: u1, - /// Bus fault on floating-point lazy state - /// preservation - LSPERR: u1, - reserved3: u1, - /// Bus Fault Address Register (BFAR) valid - /// flag - BFARVALID: u1, - /// Undefined instruction usage - /// fault - UNDEFINSTR: u1, - /// Invalid state usage fault - INVSTATE: u1, - /// Invalid PC load usage - /// fault - INVPC: u1, - /// No coprocessor usage - /// fault. - NOCP: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - /// Unaligned access usage - /// fault - UNALIGNED: u1, - /// Divide by zero usage fault - DIVBYZERO: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - }), base_address + 0x28); - - /// address: 0xe000ed2c - /// Hard fault status register - pub const HFSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - /// Vector table hard fault - VECTTBL: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - reserved20: u1, - reserved21: u1, - reserved22: u1, - reserved23: u1, - reserved24: u1, - reserved25: u1, - reserved26: u1, - reserved27: u1, - reserved28: u1, - /// Forced hard fault - FORCED: u1, - /// Reserved for Debug use - DEBUG_VT: u1, - }), base_address + 0x2c); - - /// address: 0xe000ed34 - /// Memory management fault address - /// register - pub const MMFAR = @intToPtr(*volatile u32, base_address + 0x34); - - /// address: 0xe000ed38 - /// Bus fault address register - pub const BFAR = @intToPtr(*volatile u32, base_address + 0x38); - - /// address: 0xe000ed3c - /// Auxiliary fault status - /// register - pub const AFSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Implementation defined - IMPDEF: u32, - }), base_address + 0x3c); - }; - - /// Nested vectored interrupt - /// controller - pub const NVIC_STIR = struct { - pub const base_address = 0xe000ef00; - - /// address: 0xe000ef00 - /// Software trigger interrupt - /// register - pub const STIR = @intToPtr(*volatile Mmio(32, packed struct { - /// Software generated interrupt - /// ID - INTID: u9, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - padding22: u1, - }), base_address + 0x0); - }; - - /// Floating point unit CPACR - pub const FPU_CPACR = struct { - pub const base_address = 0xe000ed88; - - /// address: 0xe000ed88 - /// Coprocessor access control - /// register - pub const CPACR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - reserved5: u1, - reserved6: u1, - reserved7: u1, - reserved8: u1, - reserved9: u1, - reserved10: u1, - reserved11: u1, - reserved12: u1, - reserved13: u1, - reserved14: u1, - reserved15: u1, - reserved16: u1, - reserved17: u1, - reserved18: u1, - reserved19: u1, - /// CP - CP: u4, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - }), base_address + 0x0); - }; - - /// System control block ACTLR - pub const SCB_ACTRL = struct { - pub const base_address = 0xe000e008; - - /// address: 0xe000e008 - /// Auxiliary control register - pub const ACTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// DISMCYCINT - DISMCYCINT: u1, - /// DISDEFWBUF - DISDEFWBUF: u1, - /// DISFOLD - DISFOLD: u1, - reserved0: u1, - reserved1: u1, - reserved2: u1, - reserved3: u1, - reserved4: u1, - /// DISFPCA - DISFPCA: u1, - /// DISOOFP - DISOOFP: u1, - padding0: u1, - padding1: u1, - padding2: u1, - padding3: u1, - padding4: u1, - padding5: u1, - padding6: u1, - padding7: u1, - padding8: u1, - padding9: u1, - padding10: u1, - padding11: u1, - padding12: u1, - padding13: u1, - padding14: u1, - padding15: u1, - padding16: u1, - padding17: u1, - padding18: u1, - padding19: u1, - padding20: u1, - padding21: u1, - }), base_address + 0x0); - }; -}; - -const std = @import("std"); - -pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { - return @intToPtr(*volatile Mmio(size, PackedT), addr); -} - -pub fn Mmio(comptime size: u8, comptime PackedT: type) type { - if ((size % 8) != 0) - @compileError("size must be divisible by 8!"); - - if (!std.math.isPowerOfTwo(size / 8)) - @compileError("size must encode a power of two number of bytes!"); - - const IntT = std.meta.Int(.unsigned, size); - - if (@sizeOf(PackedT) != (size / 8)) - @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); - - return extern struct { - const Self = @This(); - - raw: IntT, - - pub const underlying_type = PackedT; - - pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); - } - - pub inline fn write(addr: *volatile Self, val: PackedT) void { - // This is a workaround for a compiler bug related to miscompilation - // If the tmp var is not used, result location will fuck things up - var tmp = @bitCast(IntT, val); - addr.raw = tmp; - } - - pub inline fn modify(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, field.name) = @field(fields, field.name); - } - write(addr, val); - } - - pub inline fn toggle(addr: *volatile Self, fields: anytype) void { - var val = read(addr); - inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { - @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); - } - write(addr, val); - } - }; -} - -pub fn MmioInt(comptime size: u8, comptime T: type) type { - return extern struct { - const Self = @This(); - - raw: std.meta.Int(.unsigned, size), - - pub inline fn read(addr: *volatile Self) T { - return @truncate(T, addr.raw); - } - - pub inline fn modify(addr: *volatile Self, val: T) void { - const Int = std.meta.Int(.unsigned, size); - const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); - - var tmp = addr.raw; - addr.raw = (tmp & mask) | val; - } - }; -} - -pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { - return @intToPtr(*volatile MmioInt(size, T), addr); -} - -pub const InterruptVector = extern union { - C: *const fn () callconv(.C) void, - Naked: *const fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -const unhandled = InterruptVector{ - .C = struct { - fn tmp() callconv(.C) noreturn { - @panic("unhandled interrupt"); - } - }.tmp, -}; diff --git a/src/modules/chips/stm32f429/stm32f429.zig b/src/modules/chips/stm32f429/stm32f429.zig deleted file mode 100644 index 3fa26c1..0000000 --- a/src/modules/chips/stm32f429/stm32f429.zig +++ /dev/null @@ -1,94 +0,0 @@ -//! For now we keep all clock settings on the chip defaults. -//! This code should work with all the STM32F42xx line -//! -//! Specifically, TIM6 is running on a 16 MHz clock, -//! HSI = 16 MHz is the SYSCLK after reset -//! default AHB prescaler = /1 (= values 0..7): -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .HPRE = 0 }); -//! ``` -//! -//! so also HCLK = 16 MHz. -//! And with the default APB1 prescaler = /1: -//! -//! ``` -//! regs.RCC.CFGR.modify(.{ .PPRE1 = 0 }); -//! ``` -//! -//! results in PCLK1 = 16 MHz. -//! -//! TODO: add more clock calculations when adding Uart - -const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("registers.zig"); -const regs = chip.registers; - -pub usingnamespace chip; - -pub const clock = struct { - pub const Domain = enum { - cpu, - ahb, - apb1, - apb2, - }; -}; - -// Default clock frequencies after reset, see top comment for calculation -pub const clock_frequencies = .{ - .cpu = 16_000_000, - .ahb = 16_000_000, - .apb1 = 16_000_000, - .apb2 = 16_000_000, -}; - -pub fn parsePin(comptime spec: []const u8) type { - const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; - - if (spec[0] != 'P') - @compileError(invalid_format_msg); - if (spec[1] < 'A' or spec[1] > 'K') - @compileError(invalid_format_msg); - - const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); - - return struct { - /// 'A'...'K' - const gpio_port_name = spec[1..2]; - const gpio_port = @field(regs, "GPIO" ++ gpio_port_name); - const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); - }; -} - -fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { - var temp = reg.read(); - @field(temp, field_name) = value; - reg.write(temp); -} - -pub const gpio = struct { - pub fn setOutput(comptime pin: type) void { - setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); - } - - pub fn setInput(comptime pin: type) void { - setRegField(regs.RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); - setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); - } - - pub fn read(comptime pin: type) micro.gpio.State { - const idr_reg = pin.gpio_port.IDR; - const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? - return @intToEnum(micro.gpio.State, reg_value); - } - - pub fn write(comptime pin: type, state: micro.gpio.State) void { - switch (state) { - .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), - .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), - } - } -}; diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig index 3cee7c7..a2cf396 100644 --- a/src/modules/cpus.zig +++ b/src/modules/cpus.zig @@ -1,15 +1,15 @@ const std = @import("std"); const Cpu = @import("Cpu.zig"); -fn root() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse "."; } -const root_path = root() ++ "/"; - pub const avr5 = Cpu{ .name = "AVR5", - .path = root_path ++ "cpus/avr/avr5.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/avr5.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .avr, .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, @@ -20,7 +20,9 @@ pub const avr5 = Cpu{ pub const cortex_m0 = Cpu{ .name = "ARM Cortex-M0", - .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, @@ -31,7 +33,9 @@ pub const cortex_m0 = Cpu{ pub const cortex_m0plus = Cpu{ .name = "ARM Cortex-M0+", - .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, @@ -42,7 +46,9 @@ pub const cortex_m0plus = Cpu{ pub const cortex_m3 = Cpu{ .name = "ARM Cortex-M3", - .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, @@ -53,7 +59,9 @@ pub const cortex_m3 = Cpu{ pub const cortex_m4 = Cpu{ .name = "ARM Cortex-M4", - .path = root_path ++ "cpus/cortex-m/cortex-m.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, @@ -64,7 +72,9 @@ pub const cortex_m4 = Cpu{ pub const riscv32_imac = Cpu{ .name = "RISC-V 32-bit", - .path = root_path ++ "cpus/rv32-imac/riscv32.zig", + .source = .{ + .path = std.fmt.comptimePrint("{s}/cpus/riscv32.zig", .{root_dir()}), + }, .target = std.zig.CrossTarget{ .cpu_arch = .riscv32, .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, diff --git a/src/modules/cpus/avr/avr5.zig b/src/modules/cpus/avr5.zig similarity index 98% rename from src/modules/cpus/avr/avr5.zig rename to src/modules/cpus/avr5.zig index 659157d..592a1f5 100644 --- a/src/modules/cpus/avr/avr5.zig +++ b/src/modules/cpus/avr5.zig @@ -73,7 +73,7 @@ pub const vector_table = blk: { break :blk T._start; }; -fn makeIsrHandler(comptime name: []const u8, comptime func: anytype) type { +fn make_isr_handler(comptime name: []const u8, comptime func: anytype) type { const calling_convention = switch (@typeInfo(@TypeOf(func))) { .Fn => |info| info.calling_convention, else => @compileError("Declarations in 'interrupts' namespace must all be functions. '" ++ name ++ "' is not a function"), diff --git a/src/modules/cpus/cortex-m/cortex-m.zig b/src/modules/cpus/cortex-m.zig similarity index 95% rename from src/modules/cpus/cortex-m/cortex-m.zig rename to src/modules/cpus/cortex-m.zig index 2c15dd6..3a1f540 100644 --- a/src/modules/cpus/cortex-m/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -76,7 +76,7 @@ pub const startup_logic = struct { } }; -fn isValidField(field_name: []const u8) bool { +fn is_valid_field(field_name: []const u8) bool { return !std.mem.startsWith(u8, field_name, "reserved") and !std.mem.eql(u8, field_name, "initial_stack_pointer") and !std.mem.eql(u8, field_name, "reset"); @@ -105,7 +105,7 @@ pub var vector_table: VectorTable = blk: { if (!@hasField(VectorTable, decl.name)) { var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { + if (is_valid_field(field.name)) { msg = msg ++ " " ++ field.name ++ "\n"; } } @@ -113,10 +113,10 @@ pub var vector_table: VectorTable = blk: { @compileError(msg); } - if (!isValidField(decl.name)) + if (!is_valid_field(decl.name)) @compileError("You are not allowed to specify '" ++ decl.name ++ "' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang"); - @field(tmp, decl.name) = createInterruptVector(function); + @field(tmp, decl.name) = create_interrupt_vector(function); } } break :blk tmp; @@ -129,7 +129,7 @@ else if (@hasDecl(microzig.hal, "InterruptVector")) else microzig.chip.InterruptVector; -fn createInterruptVector( +fn create_interrupt_vector( comptime function: anytype, ) InterruptVector { const calling_convention = @typeInfo(@TypeOf(function)).Fn.calling_convention; diff --git a/src/modules/cpus/rv32-imac/riscv32.zig b/src/modules/cpus/riscv32.zig similarity index 99% rename from src/modules/cpus/rv32-imac/riscv32.zig rename to src/modules/cpus/riscv32.zig index 57d0bcc..49b3636 100644 --- a/src/modules/cpus/rv32-imac/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -21,7 +21,7 @@ pub fn wfe() void { asm volatile ("csrs 0x810, 0x1"); } -pub fn pmpOpenAllSpace() void { +pub fn pmp_open_all_space() void { // Config entry0 addr to all 1s to make the range cover all space asm volatile ("li x6, 0xffffffff" ::: "x6"); asm volatile ("csrw pmpaddr0, x6"); @@ -30,7 +30,7 @@ pub fn pmpOpenAllSpace() void { asm volatile ("csrw pmpcfg0, x6"); } -pub fn switchM2uMode() void { +pub fn switch_m2u_mode() void { asm volatile ("la x6, 1f " ::: "x6"); asm volatile ("csrw mepc, x6"); asm volatile ("mret"); diff --git a/src/tools/README.md b/src/tools/README.md deleted file mode 100644 index 95becbb..0000000 --- a/src/tools/README.md +++ /dev/null @@ -1,10 +0,0 @@ -# microzig tools - -## `svd2zig.py` - -Converts CMSIS SVD files into zig source code. Requires [cmsis_svd](https://github.com/posborne/cmsis-svd/) installed (can be done with `pip install -U cmsis-svd`). - -## `linkerscript-gen.zig` - -Compiled on-demand by microzig to generate a linkerscript from a board/chip/cpu bundle. - diff --git a/src/tools/svd2zig.py b/src/tools/svd2zig.py deleted file mode 100755 index b13f673..0000000 --- a/src/tools/svd2zig.py +++ /dev/null @@ -1,410 +0,0 @@ -#!/usr/bin/env python3 -import sys -import subprocess -import re -import textwrap - -from cmsis_svd.parser import SVDParser -import cmsis_svd.model as model - - -def cleanup_description(description): - if description is None: - return '' - - return ' '.join(description.replace('\n', ' ').split()) - -def comment_description(description): - if description is None: - return None - - description = ' '.join(description.replace('\n', ' ').split()) - return textwrap.fill(description, width=80, initial_indent='/// ', subsequent_indent='/// ') - - -def escape_field(field): - if not field[0].isdigit() and re.match(r'^[A-Za-z0-9_]+$', field): - return field - else: - return f"@\"{field}\"" - - -class MMIOFileGenerator: - def __init__(self, f): - self.f = f - - def generate_padding(self, count, name, offset): - while count > 0: - self.write_line(f"{name}{offset + count}: u1 = 0,") - count = count - 1 - - def generate_enumerated_field(self, field): - ''' - returns something like: - name: enum(u){ // foo description - name = value, // desc: ... - name = value, // desc: - _, // non-exhustive - }, - - ''' - description = comment_description(field.description) - self.write_line(description) - self.write_line(f"{field.name}: u{field.bit_width} = 0,") - - # TODO: turn enums back on later - #self.write_line(f"{field.name}:enum(u{field.bit_width}){{") - - #total_fields_with_values = 0 - #for e in field.enumerated_values: - # e.description = cleanup_description(e.description) - # if e.value is None or e.name == "RESERVED": - # # reserved fields doesn't have a value so we have to comment them out - # escaped_field_name = escape_field(e.name) - # self.write_line(f"// {escaped_field_name}, // {e.description}") - # else: - # total_fields_with_values = total_fields_with_values + 1 - # escaped_field_name = escape_field(e.name) - # if e.name != e.description: - # self.write_line(f"/// {e.description}") - # self.write_line(f"{escaped_field_name} = {e.value},") - - ## if the fields doesn't use all possible values make the enum non-exhaustive - #if total_fields_with_values < 2**field.bit_width: - # self.write_line("_, // non-exhaustive") - - #self.write_line("},") - return field.bit_offset + field.bit_width - - def generate_register_field(self, field): - ''' - returns something like: - name: u, // foo description - ''' - description = comment_description(field.description) - if field.name != field.description: - self.write_line(description) - self.write_line(f"{field.name}:u{field.bit_width} = 0,") - - return field.bit_offset + field.bit_width - - def generate_fields(self, fields, size): - last_offset = 0 - reserved_index = 0 - for field in sorted(fields, key=lambda f: f.bit_offset): - # workaround for NXP SVD which has overleaping reserved fields - if field.name == "RESERVED": - self.write_line(f"// RESERVED: u{field.bit_width}, // {field.description}") - continue - - if last_offset != field.bit_offset: - reserved_size = field.bit_offset - last_offset - self.generate_padding(reserved_size, "reserved", reserved_index) - reserved_index += reserved_size - - if field.is_enumerated_type: - last_offset = self.generate_enumerated_field(field) - else: - last_offset = self.generate_register_field(field) - - if size is not None and size != last_offset: - self.generate_padding(size - last_offset, "padding", 0) - - def generate_register_declaration_manual(self, name, description, address_offset, fields, size): - num_fields = len(fields) - description = comment_description(description) - - self.write_line("") - self.write_line(description) - if num_fields == 0 or (num_fields == 1 and fields[0].bit_width == 32 and name == fields[0].name): - # TODO: hardcoded 32 bit here - self.write_line(f"pub const {name} = @intToPtr(*volatile u{size}, Address + 0x{address_offset:08x});") - else: - self.write_line(f"pub const {name} = mmio(Address + 0x{address_offset:08x}, {size}, packed struct{{") - self.generate_fields(fields, size) - self.write_line("});") - - def generate_register_declaration(self, register): - size = register.size - if size == None: - size = 32 # hack for now... - - num_fields = len(register.fields) - description = comment_description(register.description) - - self.write_line("") - self.write_line(description) - if num_fields == 0 or (num_fields == 1 and register.fields[0].bit_width == 32 and register.name == register.fields[0].name): - # TODO: hardcoded 32 bit here - self.write_line(f"pub const {register.name} = @intToPtr(*volatile u{size}, Address + 0x{register.address_offset:08x});") - else: - self.write_line(f"pub const {register.name} = mmio(Address + 0x{register.address_offset:08x}, {size}, packed struct{{") - self.generate_fields(register.fields, size) - self.write_line("});") - - def generate_register_cluster(self, cluster): - if cluster.derived_from is not None: - raise Exception("TODO: derived_from") - - self.write_line("") - self.write_line(f"pub const {cluster.name} = struct {{") - for register in cluster._register: - if isinstance(register, model.SVDRegisterArray): - self.generate_register_array(register) - elif isinstance(register, model.SVDRegister): - self.generate_register_declaration(register) - - - self.write_line("};") - - def generate_register_cluster_array(self, cluster): - max_fields = int(cluster.dim_increment / 4) - if len(cluster._register) > max_fields: - raise Exception("not enough room for fields") - - name = cluster.name.replace("[%s]", "") - self.write_line(f"pub const {name} = @intToPtr(*volatile [{cluster.dim}]packed struct {{") - for register in cluster._register: - - size = register.size - if size == None: - size = 32 # hack for now... - last_offset = 0 - reserved_index = 0 - - if size != 32: - raise Exception("TODO: handle registers that are not 32-bit") - - description = comment_description(register.description) - - self.write_line("") - self.write_line(description) - if len(register.fields) == 0 or (len(register.fields) == 1 and register.fields[0].bit_width == size and register.name == register.fields[0].name): - self.write_line(f"{register.name}: u{size},") - else: - self.write_line(register.name + f": MMIO({size}, packed struct {{") - self.generate_fields(register.fields, size) - self.write_line("}),") - - - for i in range(0, max_fields - len(cluster._register)): - self.write_line(f" padding{i}: u32,") - - # TODO: this would be cleaner, but we'll probably run into packed struct bugs - #num_bits = size * (max_fields - len(cluster._register)) - #self.write_line(f"_: u{num_bits},") - - self.write_line(f" }}, Address + 0x{cluster.address_offset:08x});") - - - # TODO: calculate size in here, fine since everything we're working with rn is 32 bit - def generate_register_array(self, register_array): - description = comment_description(register_array.description) - - if register_array.dim_indices.start != 0 or ("%s" in register_array.name and not "[%s]" in register_array.name): - for i in register_array.dim_indices: - fmt = register_array.name.replace("%s", "{}") - name = fmt.format(i) - self.generate_register_declaration_manual(name, - register_array.description, - register_array.address_offset + (i * register_array.dim_increment), - register_array._fields, - 32) - return - - if register_array.dim_increment != 4: - raise Exception("TODO register " + register_array.name + " dim_increment != 4" + ", it is " + str(register_array.dim_increment)) - - name = register_array.name.replace("%s", "").replace("[]", "") - self.write_line(description) - num_fields = len(register_array._fields) - - # TODO: hardcoded 32 bit here - if num_fields == 0 or (num_fields == 1 and register_array._fields[0].bit_width == 32 and name == register_array._fields[0].name): - - # TODO: hardcoded 32 bit here - self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]u32, Address + 0x{register_array.address_offset:08x});") - else: - self.write_line(f"pub const {name} = @intToPtr(*volatile [{register_array.dim}]MMIO(32, packed struct {{") - self.generate_fields(register_array._fields, 32) - - self.write_line(f"}}), Address + 0x{register_array.address_offset:08x});") - - def generate_peripheral_declaration(self, peripheral): - description = comment_description(peripheral.description) - self.write_line("") - self.write_line(description) - self.write_line(f"pub const {peripheral.name} = extern struct {{") - self.write_line(f"pub const Address: u32 = 0x{peripheral.base_address:08x};") - - for register in sorted(peripheral._lookup_possibly_derived_attribute('registers'), key=lambda f: f.address_offset): - self.generate_register_declaration(register) - - for register_array in sorted(peripheral._lookup_possibly_derived_attribute('register_arrays'), key=lambda f: f.address_offset): - self.generate_register_array(register_array) - - for cluster in sorted(peripheral._lookup_possibly_derived_attribute('clusters'), key=lambda f: f.address_offset): - if isinstance(cluster, model.SVDRegisterCluster): - self.generate_register_cluster(cluster) - elif isinstance(cluster, model.SVDRegisterClusterArray): - #self.generate_register_cluster_array(cluster) - pass - else: - raise Exception("unhandled cluster type") - - self.write_line("};") - - # TODO: descriptions on system interrupts/exceptions, turn on system interrupts/exceptions - def generate_startup_and_interrupts(self, interrupts): - self.write_line("") - self.write_line( - """ -const std = @import(\"std\"); -const root = @import(\"root\"); -const cpu = @import(\"cpu\"); -const config = @import(\"microzig-config\"); -const InterruptVector = extern union { - C: fn () callconv(.C) void, - Naked: fn () callconv(.Naked) void, - // Interrupt is not supported on arm -}; - -fn makeUnhandledHandler(comptime str: []const u8) InterruptVector { - return InterruptVector{ - .C = struct { - fn unhandledInterrupt() callconv(.C) noreturn { - @panic(\"unhandled interrupt: \" ++ str); - } - }.unhandledInterrupt, - }; -} - -pub const VectorTable = extern struct { - initial_stack_pointer: u32 = config.end_of_stack, - Reset: InterruptVector = InterruptVector{ .C = cpu.startup_logic._start }, - NMI: InterruptVector = makeUnhandledHandler(\"NMI\"), - HardFault: InterruptVector = makeUnhandledHandler(\"HardFault\"), - MemManage: InterruptVector = makeUnhandledHandler(\"MemManage\"), - BusFault: InterruptVector = makeUnhandledHandler(\"BusFault\"), - UsageFault: InterruptVector = makeUnhandledHandler(\"UsageFault\"), - - reserved: [4]u32 = .{ 0, 0, 0, 0 }, - SVCall: InterruptVector = makeUnhandledHandler(\"SVCall\"), - DebugMonitor: InterruptVector = makeUnhandledHandler(\"DebugMonitor\"), - reserved1: u32 = 0, - - PendSV: InterruptVector = makeUnhandledHandler(\"PendSV\"), - SysTick: InterruptVector = makeUnhandledHandler(\"SysTick\"),\n -""") - - reserved_count = 2 - expected_next_value = 0 - for interrupt in interrupts: - if expected_next_value > interrupt.value: - raise Exception("out of order interrupt list") - - while expected_next_value < interrupt.value: - self.write_line(f" reserved{reserved_count}: u32 = 0,") - expected_next_value += 1 - reserved_count += 1 - - if interrupt.description is not None: - description = comment_description(interrupt.description) - self.write_line(description) - self.write_line(f" {interrupt.name}: InterruptVector = makeUnhandledHandler(\"{interrupt.name}\"),") - expected_next_value += 1 - self.write_line("};") - - self.write_line( - """ -fn isValidField(field_name: []const u8) bool { - return !std.mem.startsWith(u8, field_name, "reserved") and - !std.mem.eql(u8, field_name, "initial_stack_pointer") and - !std.mem.eql(u8, field_name, "reset"); -} - -export const vectors: VectorTable linksection(\"microzig_flash_start\") = blk: { - var temp: VectorTable = .{}; - if (@hasDecl(root, \"vector_table\")) { - const vector_table = root.vector_table; - if (@typeInfo(vector_table) != .Struct) - @compileLog(\"root.vector_table must be a struct\"); - - inline for (@typeInfo(vector_table).Struct.decls) |decl| { - const calling_convention = @typeInfo(@TypeOf(@field(vector_table, decl.name))).Fn.calling_convention; - const handler = @field(vector_table, decl.name); - - if (!@hasField(VectorTable, decl.name)) { - var msg: []const u8 = \"There is no such interrupt as '\" ++ decl.name ++ \"', declarations in 'root.vector_table' must be one of:\\n\"; - inline for (std.meta.fields(VectorTable)) |field| { - if (isValidField(field.name)) { - msg = msg ++ \" \" ++ field.name ++ \"\\n\"; - } - } - - @compileError(msg); - } - - if (!isValidField(decl.name)) - @compileError(\"You are not allowed to specify \'\" ++ decl.name ++ \"\' in the vector table, for your sins you must now pay a $5 fine to the ZSF: https://github.com/sponsors/ziglang\"); - - @field(temp, decl.name) = switch (calling_convention) { - .C => .{ .C = handler }, - .Naked => .{ .Naked = handler }, - // for unspecified calling convention we are going to generate small wrapper - .Unspecified => .{ - .C = struct { - fn wrapper() callconv(.C) void { - if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, handler, .{}); - } - }.wrapper, - }, - - else => @compileError(\"unsupported calling convention for function \" ++ decl.name), - }; - } - } - break :blk temp; -}; -""") - - def generate_file(self, device): - self.write_line("// generated using svd2zig.py\n// DO NOT EDIT") - self.write_line(f"// based on {device.name} version {device.version}") - - - self.write_line("const microzig_mmio = @import(\"microzig-mmio\");") - self.write_line("const mmio = microzig_mmio.mmio;") - self.write_line("const MMIO = microzig_mmio.MMIO;") - self.write_line(f"const Name = \"{device.name}\";") - interrupts = {} - for peripheral in device.peripherals: - self.generate_peripheral_declaration(peripheral) - if peripheral.interrupts != None: - for interrupt in peripheral.interrupts: - if interrupt.value in interrupts and interrupts[interrupt.value].description != interrupt.description: - interrupts[interrupt.value].description += "; " + interrupt.description - else: - interrupts[interrupt.value] = interrupt - - interrupts = list(map(lambda i: i[1], sorted(interrupts.items()))) - for interrupt in interrupts: - if interrupt.description is not None: - interrupt.description = ' '.join(interrupt.description.split()) - - self.generate_startup_and_interrupts(interrupts) - - def write_line(self, line): - self.f.write(line + "\n") - - -def main(): - parser = SVDParser.for_packaged_svd(sys.argv[1], sys.argv[2] + '.svd') - device = parser.get_device() - - generator = MMIOFileGenerator(sys.stdout) - generator.generate_file(device) - -if __name__ == "__main__": - main() diff --git a/test/README.adoc b/test/README.adoc new file mode 100644 index 0000000..83697ac --- /dev/null +++ b/test/README.adoc @@ -0,0 +1,3 @@ += MicroZig Test Area + +These are minimal tests to validate MicroZig behavior. diff --git a/tests/blinky.zig b/test/programs/blinky.zig similarity index 100% rename from tests/blinky.zig rename to test/programs/blinky.zig diff --git a/tests/interrupt.zig b/test/programs/interrupt.zig similarity index 100% rename from tests/interrupt.zig rename to test/programs/interrupt.zig diff --git a/tests/minimal.zig b/test/programs/minimal.zig similarity index 100% rename from tests/minimal.zig rename to test/programs/minimal.zig diff --git a/tests/uart-sync.zig b/test/programs/uart-sync.zig similarity index 100% rename from tests/uart-sync.zig rename to test/programs/uart-sync.zig From 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 17:32:08 -0500 Subject: [PATCH 099/138] fix typo for interrupt creation function (#104) --- src/modules/cpus/avr5.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/modules/cpus/avr5.zig b/src/modules/cpus/avr5.zig index 592a1f5..a7423dd 100644 --- a/src/modules/cpus/avr5.zig +++ b/src/modules/cpus/avr5.zig @@ -53,7 +53,7 @@ pub const vector_table = blk: { if (@hasDecl(microzig.app.interrupts, field.name)) { const handler = @field(microzig.app.interrupts, field.name); - const isr = makeIsrHandler(field.name, handler); + const isr = make_isr_handler(field.name, handler); break :overload "jmp " ++ isr.exported_name; } else { From 417f8fa21f154fb047f31afa09ddf869df9be655 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 10:13:25 -0800 Subject: [PATCH 100/138] Auto pr (#106) * auto update downstream repos on pushes * fix github actions * add workflow dispatch and token --- .github/workflows/auto-pr.yml | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 .github/workflows/auto-pr.yml diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml new file mode 100644 index 0000000..0524e29 --- /dev/null +++ b/.github/workflows/auto-pr.yml @@ -0,0 +1,37 @@ +name: Downstream Updates +on: + workflow_dispatch: + push: + branches: + - main + +jobs: + update: + runs-on: ubuntu-latest + strategy: + matrix: + repo: [ + raspberrypi-rp2040, + ] + steps: + - name: Checkout + uses: actions/checkout@v2 + with: + repository: https://github.com/ZigEmbeddedGroup/${{ matrix.repo }}.git + submodules: recursive + fetch-depth: 0 + + - name: Update + run: | + cd deps/microzig + git pull origin main + + - name: Create Pull Request + uses: peter-evans/create-pull-request@v4.2.3 + with: + token: ${{ secrets.PR_TOKEN }} + branch: update-microzig + commit-message: update microzig + delete-branch: true + title: Update microzig + From c244999bacf4652e363bb123ea2577cc742c4e61 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 10:17:38 -0800 Subject: [PATCH 101/138] fix yaml (#107) --- .github/workflows/auto-pr.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml index 0524e29..7813a40 100644 --- a/.github/workflows/auto-pr.yml +++ b/.github/workflows/auto-pr.yml @@ -17,7 +17,7 @@ jobs: - name: Checkout uses: actions/checkout@v2 with: - repository: https://github.com/ZigEmbeddedGroup/${{ matrix.repo }}.git + repository: ZigEmbeddedGroup/${{ matrix.repo }} submodules: recursive fetch-depth: 0 From 4bb65617a47dc30282ffe340cc45d202b973650b Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 10:47:30 -0800 Subject: [PATCH 102/138] automerge and PR description (#108) --- .github/workflows/auto-pr.yml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml index 7813a40..34b2069 100644 --- a/.github/workflows/auto-pr.yml +++ b/.github/workflows/auto-pr.yml @@ -22,11 +22,14 @@ jobs: fetch-depth: 0 - name: Update + id: update run: | cd deps/microzig git pull origin main + echo "DESCRIPTION=$(git log -1 --pretty=%B | head -n 1)" >> $GITHUB_OUTPUT - name: Create Pull Request + id: cpr uses: peter-evans/create-pull-request@v4.2.3 with: token: ${{ secrets.PR_TOKEN }} @@ -34,4 +37,12 @@ jobs: commit-message: update microzig delete-branch: true title: Update microzig + body: ${{ steps.update.outputs.DESCRIPTION }} + - name: Enable Pull Request Automerge + if: steps.cpr.outputs.pull-request-operation == 'created' + uses: peter-evans/enable-pull-request-automerge@v2 + with: + token: ${{ secrets.PR_TOKEN }} + pull-request-number: ${{ steps.cpr.outputs.pull-request-number }} + merge-method: squash From 831cfff35c259d68ee023ba7bb94dae8b7b94bec Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 11:07:47 -0800 Subject: [PATCH 103/138] Add rest of hardware support libraries (#109) Automerge action step doesn't work with this setup so we'll have to manually merge --- .github/workflows/auto-pr.yml | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml index 34b2069..6ee5ef6 100644 --- a/.github/workflows/auto-pr.yml +++ b/.github/workflows/auto-pr.yml @@ -11,7 +11,13 @@ jobs: strategy: matrix: repo: [ + espressif-esp, + gigadevice-gd32, + microchip-atmega, + nordic-nrf5x, + nxp-lpc, raspberrypi-rp2040, + stmicro-stm32, ] steps: - name: Checkout @@ -29,20 +35,11 @@ jobs: echo "DESCRIPTION=$(git log -1 --pretty=%B | head -n 1)" >> $GITHUB_OUTPUT - name: Create Pull Request - id: cpr uses: peter-evans/create-pull-request@v4.2.3 with: token: ${{ secrets.PR_TOKEN }} - branch: update-microzig + branch: downstream/update-microzig commit-message: update microzig delete-branch: true title: Update microzig body: ${{ steps.update.outputs.DESCRIPTION }} - - - name: Enable Pull Request Automerge - if: steps.cpr.outputs.pull-request-operation == 'created' - uses: peter-evans/enable-pull-request-automerge@v2 - with: - token: ${{ secrets.PR_TOKEN }} - pull-request-number: ${{ steps.cpr.outputs.pull-request-number }} - merge-method: squash From 11214ed8ba05e380a516beef3f3f594571a1c732 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 24 Feb 2023 08:25:18 -0800 Subject: [PATCH 104/138] new for loop syntax and remove import-module.zig (#110) * new for loop syntax and recursive dependencies allowed for removal of import-module.zig * fix chip standard path * move to build.zig * update template too --- .github/workflows/auto-pr.yml | 1 + build.zig | 221 ++++++++++++++++++++++++++++++++- src/core/experimental/spi.zig | 2 +- src/core/import-module.zig | 8 -- src/main.zig | 227 ---------------------------------- src/microzig.zig | 154 +---------------------- src/modules/Chip.zig | 2 +- src/start.zig | 155 +++++++++++++++++++++++ 8 files changed, 375 insertions(+), 395 deletions(-) delete mode 100644 src/core/import-module.zig delete mode 100644 src/main.zig create mode 100644 src/start.zig diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml index 6ee5ef6..850958c 100644 --- a/.github/workflows/auto-pr.yml +++ b/.github/workflows/auto-pr.yml @@ -11,6 +11,7 @@ jobs: strategy: matrix: repo: [ + hardware-support-template, espressif-esp, gigadevice-gd32, microchip-atmega, diff --git a/build.zig b/build.zig index 75b7de7..d453660 100644 --- a/build.zig +++ b/build.zig @@ -3,13 +3,224 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); - -pub const microzig = @import("src/main.zig"); +const LibExeObjStep = std.build.LibExeObjStep; +const Module = std.build.Module; // alias for packages -pub const addEmbeddedExecutable = microzig.addEmbeddedExecutable; -pub const boards = microzig.boards; -pub const Backing = microzig.Backing; +pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig"); +pub const cpus = @import("src/modules/cpus.zig"); +pub const Board = @import("src/modules/Board.zig"); +pub const Chip = @import("src/modules/Chip.zig"); +pub const Cpu = @import("src/modules/Cpu.zig"); +pub const MemoryRegion = @import("src/modules/MemoryRegion.zig"); + +pub const Backing = union(enum) { + board: Board, + chip: Chip, + + pub fn get_target(self: @This()) std.zig.CrossTarget { + return switch (self) { + .board => |brd| brd.chip.cpu.target, + .chip => |chip| chip.cpu.target, + }; + } +}; + +pub const BuildOptions = struct { + optimize: std.builtin.OptimizeMode = .Debug, +}; + +pub const EmbeddedExecutable = struct { + inner: *LibExeObjStep, + + pub fn addModule(exe: *EmbeddedExecutable, name: []const u8, module: *Module) void { + exe.inner.addModule(name, module); + } + + pub fn install(exe: *EmbeddedExecutable) void { + exe.inner.install(); + } + + pub fn installRaw(exe: *EmbeddedExecutable, dest_filename: []const u8, options: std.build.InstallRawStep.CreateOptions) *std.build.InstallRawStep { + return exe.inner.installRaw(dest_filename, options); + } + + pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + exe.inner.addIncludePath(path); + } + + pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + return exe.inner.addSystemIncludePath(path); + } + + pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { + exe.inner.addCSourceFile(file, flags); + } + + pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *std.build.OptionsStep) void { + exe.inner.addOptions(module_name, options); + } + + pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { + exe.inner.addObjectFile(source_file); + } +}; + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +pub fn addEmbeddedExecutable( + builder: *std.build.Builder, + name: []const u8, + source: []const u8, + backing: Backing, + options: BuildOptions, +) *EmbeddedExecutable { + const has_board = (backing == .board); + const chip = switch (backing) { + .chip => |c| c, + .board => |b| b.chip, + }; + + const config_file_name = blk: { + const hash = hash_blk: { + var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); + + hasher.update(chip.name); + // TODO: this will likely crash for generated sources, need to + // properly hook this up to the build cache api + hasher.update(chip.source.getPath(builder)); + hasher.update(chip.cpu.name); + hasher.update(chip.cpu.source.getPath(builder)); + + if (backing == .board) { + hasher.update(backing.board.name); + // TODO: see above + hasher.update(backing.board.source.getPath(builder)); + } + + var mac: [16]u8 = undefined; + hasher.final(&mac); + break :hash_blk mac; + }; + + const file_prefix = "zig-cache/microzig/config-"; + const file_suffix = ".zig"; + + var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; + const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ + file_prefix, + std.fmt.fmtSliceHexLower(&hash), + file_suffix, + }) catch unreachable; + + break :blk builder.dupe(filename); + }; + + { + // TODO: let the user override which ram section to use the stack on, + // for now just using the first ram section in the memory region list + const first_ram = blk: { + for (chip.memory_regions) |region| { + if (region.kind == .ram) + break :blk region; + } else @panic("no ram memory region found for setting the end-of-stack address"); + }; + + std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; + var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; + defer config_file.close(); + + var writer = config_file.writer(); + writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; + if (has_board) + writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; + + writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; + writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; + writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; + } + + const microzig_module = builder.createModule(.{ + .source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/microzig.zig", .{root_dir()}) }, + }); + + microzig_module.dependencies.put("config", builder.createModule(.{ + .source_file = .{ .path = config_file_name }, + })) catch unreachable; + + microzig_module.dependencies.put("chip", builder.createModule(.{ + .source_file = chip.source, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + + microzig_module.dependencies.put("cpu", builder.createModule(.{ + .source_file = chip.cpu.source, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + + microzig_module.dependencies.put("hal", builder.createModule(.{ + .source_file = if (chip.hal) |hal_module_path| + hal_module_path + else + .{ .path = comptime std.fmt.comptimePrint("{s}/src/core/empty.zig", .{root_dir()}) }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + + switch (backing) { + .board => |board| { + microzig_module.dependencies.put("board", builder.createModule(.{ + .source_file = board.source, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + }, + else => {}, + } + + microzig_module.dependencies.put("app", builder.createModule(.{ + .source_file = .{ .path = source }, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + + const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; + exe.* = EmbeddedExecutable{ + .inner = builder.addExecutable(.{ + .name = name, + .root_source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/start.zig", .{root_dir()}) }, + .target = chip.cpu.target, + .optimize = options.optimize, + }), + }; + + exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded + + // might not be true for all machines (Pi Pico), but + // for the HAL it's true (it doesn't know the concept of threading) + exe.inner.single_threaded = true; + + const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; + exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + + // TODO: + // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones. + // - This requires building another tool that runs on the host that compiles those files and emits the linker script. + // - src/tools/linkerscript-gen.zig is the source file for this + exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now + exe.addModule("microzig", microzig_module); + + return exe; +} pub fn build(b: *std.build.Builder) !void { const optimize = b.standardOptimizeOption(.{}); diff --git a/src/core/experimental/spi.zig b/src/core/experimental/spi.zig index e5d9ad3..250e747 100644 --- a/src/core/experimental/spi.zig +++ b/src/core/experimental/spi.zig @@ -68,7 +68,7 @@ pub fn SpiBus(comptime index: usize) type { std.debug.assert(write_buffer.len == read_buffer.len); var transfer = try self.beginTransfer(); defer transfer.end(); - for (write_buffer) |_, i| { + for (write_buffer, 0..) |_, i| { try transfer.transceiveByte(write_buffer[i], &read_buffer[i]); } } diff --git a/src/core/import-module.zig b/src/core/import-module.zig deleted file mode 100644 index 6f7d6f0..0000000 --- a/src/core/import-module.zig +++ /dev/null @@ -1,8 +0,0 @@ -//! This file is meant as a dependency for the "app" package. -//! It will only re-export all symbols from "root" under the name "microzig" -//! So we have a flattened and simplified dependency tree. -//! -//! Each config/module of microzig will also just depend on this file, so we can use -//! the same benefits there. - -pub usingnamespace @import("root"); diff --git a/src/main.zig b/src/main.zig deleted file mode 100644 index 7eb1afc..0000000 --- a/src/main.zig +++ /dev/null @@ -1,227 +0,0 @@ -const std = @import("std"); - -pub const LinkerScriptStep = @import("modules/LinkerScriptStep.zig"); -pub const cpus = @import("modules/cpus.zig"); -pub const Board = @import("modules/Board.zig"); -pub const Chip = @import("modules/Chip.zig"); -pub const Cpu = @import("modules/Cpu.zig"); -pub const MemoryRegion = @import("modules/MemoryRegion.zig"); - -const LibExeObjStep = std.build.LibExeObjStep; - -pub const Backing = union(enum) { - board: Board, - chip: Chip, - - pub fn get_target(self: @This()) std.zig.CrossTarget { - return switch (self) { - .board => |brd| brd.chip.cpu.target, - .chip => |chip| chip.cpu.target, - }; - } -}; - -const Module = std.build.Module; -const root_path = root() ++ "/"; -fn root() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} - -pub const BuildOptions = struct { - optimize: std.builtin.OptimizeMode = .Debug, -}; - -pub const EmbeddedExecutable = struct { - inner: *LibExeObjStep, - - pub fn addModule(exe: *EmbeddedExecutable, name: []const u8, module: *Module) void { - exe.inner.addModule(name, module); - } - - pub fn install(exe: *EmbeddedExecutable) void { - exe.inner.install(); - } - - pub fn installRaw(exe: *EmbeddedExecutable, dest_filename: []const u8, options: std.build.InstallRawStep.CreateOptions) *std.build.InstallRawStep { - return exe.inner.installRaw(dest_filename, options); - } - - pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { - exe.inner.addIncludePath(path); - } - - pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { - return exe.inner.addSystemIncludePath(path); - } - - pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { - exe.inner.addCSourceFile(file, flags); - } - - pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *std.build.OptionsStep) void { - exe.inner.addOptions(module_name, options); - } - - pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { - exe.inner.addObjectFile(source_file); - } -}; - -pub fn addEmbeddedExecutable( - builder: *std.build.Builder, - name: []const u8, - source: []const u8, - backing: Backing, - options: BuildOptions, -) *EmbeddedExecutable { - const has_board = (backing == .board); - const chip = switch (backing) { - .chip => |c| c, - .board => |b| b.chip, - }; - - const config_file_name = blk: { - const hash = hash_blk: { - var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); - - hasher.update(chip.name); - // TODO: this will likely crash for generated sources, need to - // properly hook this up to the build cache api - hasher.update(chip.source.getPath(builder)); - hasher.update(chip.cpu.name); - hasher.update(chip.cpu.source.getPath(builder)); - - if (backing == .board) { - hasher.update(backing.board.name); - // TODO: see above - hasher.update(backing.board.source.getPath(builder)); - } - - var mac: [16]u8 = undefined; - hasher.final(&mac); - break :hash_blk mac; - }; - - const file_prefix = "zig-cache/microzig/config-"; - const file_suffix = ".zig"; - - var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ - file_prefix, - std.fmt.fmtSliceHexLower(&hash), - file_suffix, - }) catch unreachable; - - break :blk builder.dupe(filename); - }; - - { - // TODO: let the user override which ram section to use the stack on, - // for now just using the first ram section in the memory region list - const first_ram = blk: { - for (chip.memory_regions) |region| { - if (region.kind == .ram) - break :blk region; - } else @panic("no ram memory region found for setting the end-of-stack address"); - }; - - std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; - var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; - defer config_file.close(); - - var writer = config_file.writer(); - writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; - if (has_board) - writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; - - writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; - writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; - writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; - } - - builder.addModule(.{ - .name = "microzig", - .source_file = .{ .path = root_path ++ "core/import-module.zig" }, - }); - const microzig = builder.modules.get("microzig").?; - - const config_module = builder.createModule(.{ - .source_file = .{ .path = config_file_name }, - }); - - const chip_module = builder.createModule(.{ - .source_file = chip.source, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig }, - }, - }); - - const cpu_module = builder.createModule(.{ - .source_file = chip.cpu.source, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig }, - }, - }); - - const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; - - exe.* = EmbeddedExecutable{ - .inner = builder.addExecutable(.{ - .name = name, - .root_source_file = .{ .path = root_path ++ "microzig.zig" }, - .target = chip.cpu.target, - .optimize = options.optimize, - }), - }; - - exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded - - // might not be true for all machines (Pi Pico), but - // for the HAL it's true (it doesn't know the concept of threading) - exe.inner.single_threaded = true; - - const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; - exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); - - // TODO: - // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones. - // - This requires building another tool that runs on the host that compiles those files and emits the linker script. - // - src/tools/linkerscript-gen.zig is the source file for this - exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now - - // these modules will be re-exported from core/microzig.zig - exe.inner.addModule("config", config_module); - exe.inner.addModule("chip", chip_module); - exe.inner.addModule("cpu", cpu_module); - - exe.inner.addModule("hal", builder.createModule(.{ - .source_file = if (chip.hal) |hal_module_path| - hal_module_path - else - .{ .path = root_path ++ "core/empty.zig" }, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig }, - }, - })); - - switch (backing) { - .board => |board| { - exe.inner.addModule("board", builder.createModule(.{ - .source_file = board.source, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig }, - }, - })); - }, - else => {}, - } - - exe.inner.addModule("app", builder.createModule(.{ - .source_file = .{ .path = source }, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig }, - }, - })); - - return exe; -} diff --git a/src/microzig.zig b/src/microzig.zig index 701704d..98969cc 100644 --- a/src/microzig.zig +++ b/src/microzig.zig @@ -35,46 +35,8 @@ pub const hal = @import("hal"); pub const core = @import("core.zig"); pub const drivers = @import("drivers.zig"); -const options_override = if (@hasDecl(app, "std_options")) app.std_options else struct {}; -pub const std_options = struct { - pub usingnamespace options_override; - - // Conditionally provide a default no-op logFn if app does not have one - // defined. Parts of microzig use the stdlib logging facility and - // compilations will now fail on freestanding systems that use it but do - // not explicitly set `root.std_options.logFn` - pub usingnamespace if (!@hasDecl(options_override, "logFn")) - struct { - pub fn logFn( - comptime message_level: std.log.Level, - comptime scope: @Type(.EnumLiteral), - comptime format: []const u8, - args: anytype, - ) void { - _ = message_level; - _ = scope; - _ = format; - _ = args; - } - } - else - struct {}; -}; - -// Allow app to override the os API layer -pub const os = if (@hasDecl(app, "os")) - app.os -else - struct {}; - -// Allow app to override the panic handler -pub const panic = if (@hasDecl(app, "panic")) - app.panic -else - microzig_panic; - /// The microzig default panic handler. Will disable interrupts and loop endlessly. -pub fn microzig_panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { +pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { // utilize logging functions std.log.err("microzig PANIC: {s}", .{message}); @@ -107,117 +69,3 @@ pub fn hang() noreturn { asm volatile ("" ::: "memory"); } } - -// Startup logic: -comptime { - // Instantiate the startup logic for the given CPU type. - // This usually implements the `_start` symbol that will populate - // the sections .data and .bss with the correct data. - // .rodata is not always necessary to be populated (flash based systems - // can just index flash, while harvard or flash-less architectures need - // to copy .rodata into RAM). - _ = cpu.startup_logic; - - // Export the vector table to flash start if we have any. - // For a lot of systems, the vector table provides a reset vector - // that is either called (Cortex-M) or executed (AVR) when initalized. - - // Allow board and chip to override CPU vector table. - const export_opts = .{ - .name = "vector_table", - .section = "microzig_flash_start", - .linkage = .Strong, - }; - - if ((board != void and @hasDecl(board, "vector_table"))) - @export(board.vector_table, export_opts) - else if (@hasDecl(chip, "vector_table")) - @export(chip.vector_table, export_opts) - else if (@hasDecl(cpu, "vector_table")) - @export(cpu.vector_table, export_opts) - else if (@hasDecl(app, "interrupts")) - @compileError("interrupts not configured"); -} - -/// This is the logical entry point for microzig. -/// It will invoke the main function from the root source file -/// and provides error return handling as well as a event loop if requested. -/// -/// Why is this function exported? -/// This is due to the modular design of microzig to allow the "chip" dependency of microzig -/// to call into our main function here. If we would use a normal function call, we'd have a -/// circular dependency between the `microzig` and `chip` package. This function is also likely -/// to be invoked from assembly, so it's also convenient in that regard. -export fn microzig_main() noreturn { - if (!@hasDecl(app, "main")) - @compileError("The root source file must provide a public function main!"); - - const main = @field(app, "main"); - const info: std.builtin.Type = @typeInfo(@TypeOf(main)); - - const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; - if (info != .Fn or info.Fn.params.len > 0) - @compileError(invalid_main_msg); - - const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); - - if (info.Fn.calling_convention == .Async) - @compileError("TODO: Embedded event loop not supported yet. Please try again later."); - - // A hal can export a default init function that runs before main for - // procedures like clock configuration. The user may override and customize - // this functionality by providing their own init function. - // function. - if (@hasDecl(app, "init")) - app.init() - else if (@hasDecl(hal, "init")) - hal.init(); - - if (@typeInfo(return_type) == .ErrorUnion) { - main() catch |err| { - // TODO: - // - Compute maximum size on the type of "err" - // - Do not emit error names when std.builtin.strip is set. - var msg: [64]u8 = undefined; - @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); - }; - } else { - main(); - } - - // main returned, just hang around here a bit - hang(); -} - -/// Contains references to the microzig .data and .bss sections, also -/// contains the initial load address for .data if it is in flash. -pub const sections = struct { - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; -}; - -pub fn initialize_system_memories() void { - @setCold(true); - - // fill .bss with zeroes - { - const bss_start = @ptrCast([*]u8, §ions.microzig_bss_start); - const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - - std.mem.set(u8, bss_start[0..bss_len], 0); - } - - // load .data from flash - { - const data_start = @ptrCast([*]u8, §ions.microzig_data_start); - const data_end = @ptrCast([*]u8, §ions.microzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); - const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); - - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); - } -} diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig index 909b389..b26aecd 100644 --- a/src/modules/Chip.zig +++ b/src/modules/Chip.zig @@ -29,7 +29,7 @@ pub fn from_standard_paths(comptime root_dir: []const u8, args: struct { }), }, .hal = .{ - .path = std.fmt.comptimePrint("{s}/chips/{s}.zig", .{ + .path = std.fmt.comptimePrint("{s}/hals/{s}.zig", .{ root_dir, args.name, }), diff --git a/src/start.zig b/src/start.zig new file mode 100644 index 0000000..ef4de2f --- /dev/null +++ b/src/start.zig @@ -0,0 +1,155 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const app = microzig.app; + +const options_override = if (@hasDecl(app, "std_options")) app.std_options else struct {}; +pub const std_options = struct { + pub usingnamespace options_override; + + // Conditionally provide a default no-op logFn if app does not have one + // defined. Parts of microzig use the stdlib logging facility and + // compilations will now fail on freestanding systems that use it but do + // not explicitly set `root.std_options.logFn` + pub usingnamespace if (!@hasDecl(options_override, "logFn")) + struct { + pub fn logFn( + comptime message_level: std.log.Level, + comptime scope: @Type(.EnumLiteral), + comptime format: []const u8, + args: anytype, + ) void { + _ = message_level; + _ = scope; + _ = format; + _ = args; + } + } + else + struct {}; +}; + +// Allow app to override the os API layer +pub const os = if (@hasDecl(app, "os")) + app.os +else + struct {}; + +// Allow app to override the panic handler +pub const panic = if (@hasDecl(app, "panic")) + app.panic +else + microzig.panic; + +// Startup logic: +comptime { + // Instantiate the startup logic for the given CPU type. + // This usually implements the `_start` symbol that will populate + // the sections .data and .bss with the correct data. + // .rodata is not always necessary to be populated (flash based systems + // can just index flash, while harvard or flash-less architectures need + // to copy .rodata into RAM). + _ = microzig.cpu.startup_logic; + + // Export the vector table to flash start if we have any. + // For a lot of systems, the vector table provides a reset vector + // that is either called (Cortex-M) or executed (AVR) when initalized. + + // Allow board and chip to override CPU vector table. + const export_opts = .{ + .name = "vector_table", + .section = "microzig_flash_start", + .linkage = .Strong, + }; + + if ((microzig.board != void and @hasDecl(microzig.board, "vector_table"))) + @export(microzig.board.vector_table, export_opts) + else if (@hasDecl(microzig.chip, "vector_table")) + @export(microzig.chip.vector_table, export_opts) + else if (@hasDecl(microzig.cpu, "vector_table")) + @export(microzig.cpu.vector_table, export_opts) + else if (@hasDecl(app, "interrupts")) + @compileError("interrupts not configured"); +} + +/// This is the logical entry point for microzig. +/// It will invoke the main function from the root source file +/// and provides error return handling as well as a event loop if requested. +/// +/// Why is this function exported? +/// This is due to the modular design of microzig to allow the "chip" dependency of microzig +/// to call into our main function here. If we would use a normal function call, we'd have a +/// circular dependency between the `microzig` and `chip` package. This function is also likely +/// to be invoked from assembly, so it's also convenient in that regard. +export fn microzig_main() noreturn { + if (!@hasDecl(app, "main")) + @compileError("The root source file must provide a public function main!"); + + const main = @field(app, "main"); + const info: std.builtin.Type = @typeInfo(@TypeOf(main)); + + const invalid_main_msg = "main must be either 'pub fn main() void' or 'pub fn main() !void'."; + if (info != .Fn or info.Fn.params.len > 0) + @compileError(invalid_main_msg); + + const return_type = info.Fn.return_type orelse @compileError(invalid_main_msg); + + if (info.Fn.calling_convention == .Async) + @compileError("TODO: Embedded event loop not supported yet. Please try again later."); + + // A hal can export a default init function that runs before main for + // procedures like clock configuration. The user may override and customize + // this functionality by providing their own init function. + // function. + if (@hasDecl(app, "init")) + app.init() + else if (@hasDecl(microzig.hal, "init")) + microzig.hal.init(); + + if (@typeInfo(return_type) == .ErrorUnion) { + main() catch |err| { + // TODO: + // - Compute maximum size on the type of "err" + // - Do not emit error names when std.builtin.strip is set. + var msg: [64]u8 = undefined; + @panic(std.fmt.bufPrint(&msg, "main() returned error {s}", .{@errorName(err)}) catch @panic("main() returned error.")); + }; + } else { + main(); + } + + // main returned, just hang around here a bit + microzig.hang(); +} + +/// Contains references to the microzig .data and .bss sections, also +/// contains the initial load address for .data if it is in flash. +pub const sections = struct { + extern var microzig_data_start: anyopaque; + extern var microzig_data_end: anyopaque; + extern var microzig_bss_start: anyopaque; + extern var microzig_bss_end: anyopaque; + extern const microzig_data_load_start: anyopaque; +}; + +pub fn initialize_system_memories() void { + @setCold(true); + + // fill .bss with zeroes + { + const bss_start = @ptrCast([*]u8, §ions.microzig_bss_start); + const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); + const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + + std.mem.set(u8, bss_start[0..bss_len], 0); + } + + // load .data from flash + { + const data_start = @ptrCast([*]u8, §ions.microzig_data_start); + const data_end = @ptrCast([*]u8, §ions.microzig_data_end); + const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); + + std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + } +} From b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 28 Feb 2023 01:14:06 -0800 Subject: [PATCH 105/138] Mimic new stdlib build API (#111) * start on new docs to match api * tweak the MicroZig dependency tree * use microzig_options * remove empty.zig * add test programs * keep it to one arch, bump flash for debug --- .buildkite/pipeline.yml | 7 ++ .github/workflows/build.yml | 2 +- README.adoc | 124 ++++++++++--------- build.zig | 115 ++++++++++++------ docs/design.adoc | 103 ++++++++++++++++ docs/hardware_support_packages.adoc | 7 ++ docs/images/deps.dot | 23 ++++ docs/images/deps.svg | 171 +++++++++++++++++++++++++++ docs/tricks.adoc | 14 +++ src/microzig.zig | 11 +- src/modules/LinkerScriptStep.zig | 12 +- src/modules/cpus/avr5.zig | 13 +- src/modules/cpus/cortex-m.zig | 24 ++-- src/modules/cpus/riscv32.zig | 1 - src/start.zig | 59 ++++----- test/backings.zig | 67 +++++++++++ src/core/empty.zig => test/board.zig | 0 test/chip.zig | 6 + test/cpu.zig | 3 + test/hal.zig | 0 test/programs/blinky.zig | 12 +- test/programs/has_board.zig | 10 ++ test/programs/has_dependencies.zig | 0 test/programs/has_hal.zig | 10 ++ test/programs/minimal.zig | 12 +- 25 files changed, 641 insertions(+), 165 deletions(-) create mode 100644 .buildkite/pipeline.yml create mode 100644 docs/design.adoc create mode 100644 docs/hardware_support_packages.adoc create mode 100644 docs/images/deps.dot create mode 100644 docs/images/deps.svg create mode 100644 docs/tricks.adoc create mode 100644 test/backings.zig rename src/core/empty.zig => test/board.zig (100%) create mode 100644 test/chip.zig create mode 100644 test/cpu.zig create mode 100644 test/hal.zig create mode 100644 test/programs/has_board.zig create mode 100644 test/programs/has_dependencies.zig create mode 100644 test/programs/has_hal.zig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml new file mode 100644 index 0000000..723f5a2 --- /dev/null +++ b/.buildkite/pipeline.yml @@ -0,0 +1,7 @@ +steps: + - group: Build and Test + steps: + - label: Debug + command: zig build test + - label: ReleaseSmall + command: zig build test -Doptimize=ReleaseSmall diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1026e82..57245c8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -29,4 +29,4 @@ jobs: version: master - name: Build tests - run: zig build -Doptimize=ReleaseSmall + run: zig build test -Doptimize=ReleaseSmall diff --git a/README.adoc b/README.adoc index 8d093a4..dd8fcab 100644 --- a/README.adoc +++ b/README.adoc @@ -12,94 +12,89 @@ toc::[] == Contributing -Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], its used as a place to brainstorm and organize work in ZEG. -There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. +Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], its used as a place to brainstorm and organize work in ZEG. There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. == Introduction -This repo contains the infrastructure for getting started in an embedded Zig project, as well as some code to interact with some chips/boards. -Specifically it offers: +This repo contains the infrastructure for getting started in an embedded Zig project, it "gets you to main()". Specifically it offers: * a single easy-to-use builder function that: ** generates your linker script -** sets up packages and start code +** sets up packages and startup code * generalized interfaces for common devices, such as UART. * device drivers for interacting with external hardware * an uncomplicated method to define xref:interrupts[interrupts] -== How to +== Design -Here's a number of things you might be interested in doing, and how to achieve them with microzig and other ZEG tools. +For MicroZig internals please see the xref:docs/design.adoc[Design Document]. -=== Embedded project with "supported" chip/board +== Does MicroZig support X hardware? -Start with an empty Zig project by running `zig init-exe`, and add microzig as a git submodule (or your choice of package manager). -Then in your `build.zig`: +MicroZig is designed to cover as wide swath of hardware as possible. The https://github.com/ZigEmbeddedGroup[Zig Embedded Group] has some repositories that contain hardware-specific code. You will find them with the `hardware-support-package` label. If you can't find your specific device, it doesn't mean that you can't run Zig on it, it's likely you're just the first! In that case see xref:#getting-microzig-on-new-hardware[Getting MicroZig on New Hardare]. + +Start with an empty Zig project by running `zig init-exe`, and add the hardware support package as a submodule. We'll use `microchip-atmega` in our example: [source,zig] ---- const std = @import("std"); -const microzig = @import("path/to/microzig/src/main.zig"); +const atmega = @import("deps/microchip-atmega/build.zig"); + +// the hardware support package should have microzig as a dependency +const microzig = @import("deps/hardware_support_package/deps/microzig/build.zig"); pub fn build(b: *std.build.Builder) !void { - const backing = .{ - .board = microzig.boards.arduino_nano, - - // if you don't have one of the boards, but do have one of the - // "supported" chips: - // .chip = microzig.chips.atmega328p, - }; - - var exe = microzig.addEmbeddedExecutable( - b, - "my-executable", - "src/main.zig", - backing, - .{ - // optional slice of packages that can be imported into your app: - // .packages = &my_packages, + const optimize = b.standardOptimizeOption(.{}); + var exe = microzig.addEmbeddedExecutable( b, .{ + .name = "my-executable", + .root_source_file = .{ + .path = "src/main.zig", + }, + .backing = .{ + .board = atmega.boards.arduino_nano, + + // instead of a board, you can use the raw chip as well + // .chip = atmega.chips.atmega328p, }, - ); - exe.setBuildMode(.ReleaseSmall); + .optimize = optimize, + }); exe.install(); } ---- -`zig build` and now you have an executable for an Arduino Nano. -In your application you can import `microzig` in order to interact with the hardware: +`zig build` and now you have an executable for an Arduino Nano. In your application you can import `microzig` in order to interact with the hardware: [source,zig] ---- const microzig = @import("microzig"); -// `microzig.chip.registers`: access to register definitions // `microzig.config`: comptime access to configuration -// - chip_name: name of the chip -// - has_board: true if board is configured -// - board_name: name of the board is has_board is true -// - cpu_name: name of the CPU +// `microzig.chip`: access to register definitions, generated code +// `microzig.board`: access to board information +// `microzig.hal`: access to hand-written code for interacting with the hardware +// `microzig.cpu`: access to AVR5 specific functions pub fn main() !void { // your program here } ---- -=== Embedded project with "unsupported" chip +== Getting MicroZig on New Hardware -If you have a board/chip that isn't defined in microzig, you can set it up yourself! -You need to have: +If you have a board/chip that isn't defined in microzig, you can set it up yourself! You need to have: * SVD or ATDF file defining registers * flash and ram address and sizes -First use https://github.com/ZigEmbeddedGroup/regz[regz] to generate the register definitions for your chip and save them to a file. -Then your `build.zig` is going to be the same, but you'll define the chip yourself: +First use https://github.com/ZigEmbeddedGroup/regz[Regz] to generate the register definitions for your chip and save them to a file. Then define the chip: [source,zig] ---- const nrf52832 = Chip{ .name = "nRF52832", - .path = "path/to/generated/file.zig", + .source = .{ + .path = "path/to/generated/file.zig", + }, .cpu = cpus.cortex_m4, .memory_regions = &.{ MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash }, @@ -112,27 +107,48 @@ const backing = .{ }; ---- -[NOTE] -`regz` is also still in development, and while it tends to generate code well, it's possible that there will be errors in the generated code! -Please create an issue if you run into anything fishy. +It's important that the chip name actually match one of the entries under `devices` in the generated code. + +=== Optional: JSON Register Schema + +You can also invoke `regz` to generate a JSON representation of the hardware: + +[source] +---- +regz --json +---- -=== Interrupts +This file could then be used by tooling. You can add it to a `Chip` like so: -The current supported architectures for interrupt vector generation are ARM and AVR. -To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace: [source,zig] ---- -pub const interrupts = struct { - pub fn PCINT0() void { - // interrupt handling code - } +const nrf52832 = Chip{ + .name = "nRF52832", + .json_register_schema = .{ + .path = "path/to.json", + }, + // ... }; +---- + +== Interrupts + +The current supported architectures for interrupt vector generation are ARM and AVR. To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace, which is nested in a `microzig_options` namespace: + +[source,zig] +---- +pub const microzig_options = struct { + pub const interrupts = struct { + pub fn PCINT0() void { + // interrupt handling code + } + }; +} pub fn main() !void { // my application } ---- -We're using compile-time checks along with the generated code to determine the list of interrupts. -If a function is defined whose name is not in this list, you'll get a compiler error with the list of interrupts/valid names. +We're using compile-time checks along with the generated code to determine the list of interrupts. If a function is defined whose name is not in this list, you'll get a compiler error with the list of interrupts/valid names. diff --git a/build.zig b/build.zig index d453660..5e48566 100644 --- a/build.zig +++ b/build.zig @@ -5,6 +5,7 @@ const std = @import("std"); const LibExeObjStep = std.build.LibExeObjStep; const Module = std.build.Module; +const FileSource = std.build.FileSource; // alias for packages pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig"); @@ -26,10 +27,6 @@ pub const Backing = union(enum) { } }; -pub const BuildOptions = struct { - optimize: std.builtin.OptimizeMode = .Debug, -}; - pub const EmbeddedExecutable = struct { inner: *LibExeObjStep, @@ -70,19 +67,25 @@ fn root_dir() []const u8 { return std.fs.path.dirname(@src().file) orelse unreachable; } -pub fn addEmbeddedExecutable( - builder: *std.build.Builder, +pub const EmbeddedExecutableOptions = struct { name: []const u8, - source: []const u8, + source_file: std.build.FileSource, backing: Backing, - options: BuildOptions, + optimize: std.builtin.OptimizeMode = .Debug, + linkerscript_source_file: ?FileSource = null, +}; + +pub fn addEmbeddedExecutable( + builder: *std.build.Builder, + opts: EmbeddedExecutableOptions, ) *EmbeddedExecutable { - const has_board = (backing == .board); - const chip = switch (backing) { + const has_board = (opts.backing == .board); + const chip = switch (opts.backing) { .chip => |c| c, .board => |b| b.chip, }; + const has_hal = chip.hal != null; const config_file_name = blk: { const hash = hash_blk: { var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); @@ -94,10 +97,10 @@ pub fn addEmbeddedExecutable( hasher.update(chip.cpu.name); hasher.update(chip.cpu.source.getPath(builder)); - if (backing == .board) { - hasher.update(backing.board.name); + if (opts.backing == .board) { + hasher.update(opts.backing.board.name); // TODO: see above - hasher.update(backing.board.source.getPath(builder)); + hasher.update(opts.backing.board.source.getPath(builder)); } var mac: [16]u8 = undefined; @@ -133,9 +136,11 @@ pub fn addEmbeddedExecutable( defer config_file.close(); var writer = config_file.writer(); + + writer.print("pub const has_hal = {};\n", .{has_hal}) catch unreachable; writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; if (has_board) - writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(backing.board.name)}) catch unreachable; + writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(opts.backing.board.name)}) catch unreachable; writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; @@ -164,17 +169,16 @@ pub fn addEmbeddedExecutable( }, })) catch unreachable; - microzig_module.dependencies.put("hal", builder.createModule(.{ - .source_file = if (chip.hal) |hal_module_path| - hal_module_path - else - .{ .path = comptime std.fmt.comptimePrint("{s}/src/core/empty.zig", .{root_dir()}) }, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, - }, - })) catch unreachable; + if (chip.hal) |hal_module_source| { + microzig_module.dependencies.put("hal", builder.createModule(.{ + .source_file = hal_module_source, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })) catch unreachable; + } - switch (backing) { + switch (opts.backing) { .board => |board| { microzig_module.dependencies.put("board", builder.createModule(.{ .source_file = board.source, @@ -186,20 +190,13 @@ pub fn addEmbeddedExecutable( else => {}, } - microzig_module.dependencies.put("app", builder.createModule(.{ - .source_file = .{ .path = source }, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, - }, - })) catch unreachable; - const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; exe.* = EmbeddedExecutable{ .inner = builder.addExecutable(.{ - .name = name, + .name = opts.name, .root_source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/start.zig", .{root_dir()}) }, .target = chip.cpu.target, - .optimize = options.optimize, + .optimize = opts.optimize, }), }; @@ -209,23 +206,63 @@ pub fn addEmbeddedExecutable( // for the HAL it's true (it doesn't know the concept of threading) exe.inner.single_threaded = true; - const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; - exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + if (opts.linkerscript_source_file) |linkerscript_source_file| { + exe.inner.setLinkerScriptPath(linkerscript_source_file); + } else { + const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; + exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + } // TODO: // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones. // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this - exe.inner.bundle_compiler_rt = (exe.inner.target.cpu_arch.? != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now + exe.inner.bundle_compiler_rt = (exe.inner.target.getCpuArch() != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now exe.addModule("microzig", microzig_module); + exe.addModule("app", builder.createModule(.{ + .source_file = opts.source_file, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + })); return exe; } +/// This build script validates usage patterns we expect from MicroZig pub fn build(b: *std.build.Builder) !void { + const backings = @import("test/backings.zig"); const optimize = b.standardOptimizeOption(.{}); - const test_step = b.step("test", "Builds and runs the library test suite"); - _ = optimize; - _ = test_step; + const minimal = addEmbeddedExecutable(b, .{ + .name = "minimal", + .source_file = .{ + .path = comptime root_dir() ++ "/test/programs/minimal.zig", + }, + .backing = backings.minimal, + .optimize = optimize, + }); + + const has_hal = addEmbeddedExecutable(b, .{ + .name = "has_hal", + .source_file = .{ + .path = comptime root_dir() ++ "/test/programs/has_hal.zig", + }, + .backing = backings.has_hal, + .optimize = optimize, + }); + + const has_board = addEmbeddedExecutable(b, .{ + .name = "has_board", + .source_file = .{ + .path = comptime root_dir() ++ "/test/programs/has_board.zig", + }, + .backing = backings.has_board, + .optimize = optimize, + }); + + const test_step = b.step("test", "build test programs"); + test_step.dependOn(&minimal.inner.step); + test_step.dependOn(&has_hal.inner.step); + test_step.dependOn(&has_board.inner.step); } diff --git a/docs/design.adoc b/docs/design.adoc new file mode 100644 index 0000000..4e97a2d --- /dev/null +++ b/docs/design.adoc @@ -0,0 +1,103 @@ += MicroZig Design +:imagesdir: images +:toc: macro + +toc::[] + +== Dependency Tree + +The build portion of MicroZig sets up a dependency graph like the following. + +image::deps.svg[] + +Your application lives in `app`, that's where `main()` resides. `root` contains the entry point, and will set up [zero-initialized data] and [uninitialized data]. This is all encapsulated in an `EmbeddedExecutable` object. It has methods to add dependencies acquired from the package manager. + +The `microzig` module has different namespaces, some are static, but the nodes you see in the diagram above are switched out according to your configured hardware. + +== Configurable Modules under `microzig` + +The configurable modules, with the exception of `config`, are able to import `microzig`. This exists so that one module may access another through `microzig`. This allows us to have patterns like the `hal` grabbing the frequency of an external crystal oscillator from `board`. Information stays where it's relevant. Circular dependencies of declarations will result in a compile error. + +=== `cpu` + +This module models your specific CPU, and is important for initializing memory. Generally you shouldn't need to define this yourself, it's likely that MicroZig will have the definition for you. + +Further research is needed for SOCs with multiple, heterogenous CPUs. Likely it means patching together multiple `EmbeddedExecutable`s. + +=== `chip` + +This module is intended for generated code from https://github.com/ZigEmbeddedGroup/regz[Regz]. You can handwrite this code if you like, but needs to be structured as follows: + +[source,zig] +---- +pub const types = struct { + // type definitions for peripherals here +}; + +pub const devices = struct { + pub const chip_name = struct { + // peripherals and interrupt table here ... + }; +}; +---- + +This code generation has a `devices` namespace where your specific hardware will reside. When defining a `Chip`, which is ultimately used in the creation of an `EmbeddedExecutable`, the name must exactly match the name under the `devices` namespace. It's okay if the name has whitespace, for that we can use `@""` notation. + +Let's say we had a device with the name `STM32F103`. We'd define our chip as: + +[source,zig] +---- +pub const stm32f103 = microzig.Chip{ + .name = "STM32F103", + .cpu = microzig.cpus.cortex_m3, + .source = .{ + .path = "path/to/generated.zig", + }, + .json_register_schema = .{ + .path = "path/to/generated.json", + }, + .hal = .{ + .path = "path/to/hal.zig", + }, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + }, +}; +---- + +As discussed, the `name` must match a namespace under `devices` in the `chip` source. + +TODO + +When making a package that defines chips for others, see xref:hardware_support_packages.adoc[Hardware Support Packages] and xref:tricks.adoc#packaging-and-paths[Packaging and Paths]. + +=== `hal` + +This module contains hand-written code for interracting with the chip. + +TODO + +=== `board` + +TODO + +=== `config` + +TODO + +== Static Namespaces under `microzig` + +TODO + +== Linkerscript Generation + +TODO + +== JSON register schema + +TODO + +== Interrupts + +TODO diff --git a/docs/hardware_support_packages.adoc b/docs/hardware_support_packages.adoc new file mode 100644 index 0000000..4b8605f --- /dev/null +++ b/docs/hardware_support_packages.adoc @@ -0,0 +1,7 @@ += Hardware Support Packages +:imagesdir: images +:toc: macro + +toc::[] + +This document goes over the _suggested_ way to structure a hardware support package. At the end of the day, MicroZig is designed for flexibility, we do not require all "supported" hardware be defined in one monorepo. Instead we make it so that you can define your hardware locally if that best suites your project. diff --git a/docs/images/deps.dot b/docs/images/deps.dot new file mode 100644 index 0000000..1577418 --- /dev/null +++ b/docs/images/deps.dot @@ -0,0 +1,23 @@ +digraph { + root -> app + root -> microzig + + app -> microzig + app -> A + app -> B + + subgraph cluster_0 { + style="dotted" + graph [labelloc=b] + A -> C + B -> C + B -> D + label = "Application Dependencies"; + } + + microzig -> config + microzig -> cpu [dir="both"] + microzig -> chip [dir="both"] + microzig -> board [dir="both", style="dashed"] + microzig -> hal [dir="both", style="dashed"] +} diff --git a/docs/images/deps.svg b/docs/images/deps.svg new file mode 100644 index 0000000..20fd6e1 --- /dev/null +++ b/docs/images/deps.svg @@ -0,0 +1,171 @@ + + + + + + + + +cluster_0 + +Application Dependencies + + + +root + +root + + + +app + +app + + + +root->app + + + + + +microzig + +microzig + + + +root->microzig + + + + + +app->microzig + + + + + +A + +A + + + +app->A + + + + + +B + +B + + + +app->B + + + + + +config + +config + + + +microzig->config + + + + + +cpu + +cpu + + + +microzig->cpu + + + + + + +chip + +chip + + + +microzig->chip + + + + + + +board + +board + + + +microzig->board + + + + + + +hal + +hal + + + +microzig->hal + + + + + + +C + +C + + + +A->C + + + + + +B->C + + + + + +D + +D + + + +B->D + + + + + diff --git a/docs/tricks.adoc b/docs/tricks.adoc new file mode 100644 index 0000000..11055a9 --- /dev/null +++ b/docs/tricks.adoc @@ -0,0 +1,14 @@ += Tips and Tricks + +This document has some `build.zig` tricks for other pages to reference. + +== Packaging and Paths + +TODO + +[source,zig] +---- +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} +---- diff --git a/src/microzig.zig b/src/microzig.zig index 98969cc..a40ea53 100644 --- a/src/microzig.zig +++ b/src/microzig.zig @@ -15,6 +15,9 @@ pub const app = @import("app"); /// and so on. pub const config = @import("config"); +/// Provides access to the low level features of the CPU. +pub const cpu = @import("cpu"); + /// Provides access to the low level features of the current microchip. pub const chip = struct { const inner = @import("chip"); @@ -22,16 +25,14 @@ pub const chip = struct { pub usingnamespace @field(inner.devices, config.chip_name); }; +/// Provides higher level APIs for interacting with hardware +pub const hal = if (config.has_hal) @import("hal") else void; + /// Provides access to board features or is `void` when no board is present. pub const board = if (config.has_board) @import("board") else void; -/// Provides access to the low level features of the CPU. -pub const cpu = @import("cpu"); pub const mmio = @import("mmio.zig"); pub const interrupt = @import("interrupt.zig"); - -pub const hal = @import("hal"); - pub const core = @import("core.zig"); pub const drivers = @import("drivers.zig"); diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig index eb6df1d..368b7a1 100644 --- a/src/modules/LinkerScriptStep.zig +++ b/src/modules/LinkerScriptStep.zig @@ -54,11 +54,6 @@ fn make(step: *Step) !void { defer file.close(); const target = linkerscript.chip.cpu.target; - if (target.cpu_arch == null) { - std.log.err("target does not have 'cpu_arch'", .{}); - return error.NoCpuArch; - } - const writer = file.writer(); try writer.print( \\/* @@ -122,14 +117,15 @@ fn make(step: *Step) !void { \\ ); - if (target.cpu_arch.? == .arm or target.cpu_arch.? == .thumb) { - try writer.writeAll( + switch (target.getCpuArch()) { + .arm, .thumb => try writer.writeAll( \\ .ARM.exidx : { \\ *(.ARM.exidx* .gnu.linkonce.armexidx.*) \\ } >flash0 \\ \\ - ); + ), + else => {}, } try writer.writeAll( diff --git a/src/modules/cpus/avr5.zig b/src/modules/cpus/avr5.zig index a7423dd..b24e7cb 100644 --- a/src/modules/cpus/avr5.zig +++ b/src/modules/cpus/avr5.zig @@ -1,5 +1,6 @@ const std = @import("std"); const microzig = @import("microzig"); +const root = @import("root"); pub inline fn sei() void { asm volatile ("sei"); @@ -29,12 +30,13 @@ pub const vector_table = blk: { std.debug.assert(std.mem.eql(u8, "RESET", std.meta.fields(microzig.chip.VectorTable)[0].name)); var asm_str: []const u8 = "jmp microzig_start\n"; - const has_interrupts = @hasDecl(microzig.app, "interrupts"); + const has_interrupts = @hasDecl(root, "microzig_options") and @hasDecl(root.microzig_options, "interrupts"); if (has_interrupts) { - if (@hasDecl(microzig.app.interrupts, "RESET")) + const interrupts = root.microzig_options.interrupts; + if (@hasDecl(interrupts, "RESET")) @compileError("Not allowed to overload the reset vector"); - inline for (std.meta.declarations(microzig.app.interrupts)) |decl| { + inline for (std.meta.declarations(interrupts)) |decl| { if (!@hasField(microzig.chip.VectorTable, decl.name)) { var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. ISRs the 'interrupts' namespace must be one of:\n"; inline for (std.meta.fields(microzig.chip.VectorTable)) |field| { @@ -50,8 +52,9 @@ pub const vector_table = blk: { inline for (std.meta.fields(microzig.chip.VectorTable)[1..]) |field| { const new_insn = if (has_interrupts) overload: { - if (@hasDecl(microzig.app.interrupts, field.name)) { - const handler = @field(microzig.app.interrupts, field.name); + const interrupts = root.microzig_options.interrupts; + if (@hasDecl(interrupts, field.name)) { + const handler = @field(interrupts, field.name); const isr = make_isr_handler(field.name, handler); diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index 3a1f540..4802e9d 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -1,6 +1,6 @@ const std = @import("std"); const microzig = @import("microzig"); -const app = microzig.app; +const root = @import("root"); pub fn sei() void { asm volatile ("cpsie i"); @@ -82,8 +82,8 @@ fn is_valid_field(field_name: []const u8) bool { !std.mem.eql(u8, field_name, "reset"); } -const VectorTable = if (@hasDecl(microzig.app, "VectorTable")) - microzig.app.VectorTable +const VectorTable = if (@hasDecl(root, "microzig_options") and @hasDecl(root.microzig_options, "VectorTable")) + root.microzig_options.VectorTable else if (@hasDecl(microzig.hal, "VectorTable")) microzig.hal.VectorTable else @@ -95,12 +95,13 @@ pub var vector_table: VectorTable = blk: { .initial_stack_pointer = microzig.config.end_of_stack, .Reset = .{ .C = microzig.cpu.startup_logic._start }, }; - if (@hasDecl(app, "interrupts")) { - if (@typeInfo(app.interrupts) != .Struct) + if (@hasDecl(root, "microzig_options") and @hasDecl(root.microzig_options, "interrupts")) { + const interrupts = root.microzig_options.interrupts; + if (@typeInfo(interrupts) != .Struct) @compileLog("root.interrupts must be a struct"); - inline for (@typeInfo(app.interrupts).Struct.decls) |decl| { - const function = @field(app.interrupts, decl.name); + inline for (@typeInfo(interrupts).Struct.decls) |decl| { + const function = @field(interrupts, decl.name); if (!@hasField(VectorTable, decl.name)) { var msg: []const u8 = "There is no such interrupt as '" ++ decl.name ++ "'. Declarations in 'interrupts' must be one of:\n"; @@ -122,16 +123,9 @@ pub var vector_table: VectorTable = blk: { break :blk tmp; }; -const InterruptVector = if (@hasDecl(microzig.app, "InterruptVector")) - microzig.app.InterruptVector -else if (@hasDecl(microzig.hal, "InterruptVector")) - microzig.hal.InterruptVector -else - microzig.chip.InterruptVector; - fn create_interrupt_vector( comptime function: anytype, -) InterruptVector { +) microzig.interrupt.Handler { const calling_convention = @typeInfo(@TypeOf(function)).Fn.calling_convention; return switch (calling_convention) { .C => .{ .C = function }, diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index 49b3636..200b554 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -1,7 +1,6 @@ const std = @import("std"); const root = @import("root"); const microzig = @import("microzig"); -const app = microzig.app; pub fn sei() void { // asm volatile ("sei"); diff --git a/src/start.zig b/src/start.zig index ef4de2f..42a76f1 100644 --- a/src/start.zig +++ b/src/start.zig @@ -1,17 +1,24 @@ const std = @import("std"); const microzig = @import("microzig"); -const app = microzig.app; - -const options_override = if (@hasDecl(app, "std_options")) app.std_options else struct {}; -pub const std_options = struct { - pub usingnamespace options_override; - - // Conditionally provide a default no-op logFn if app does not have one - // defined. Parts of microzig use the stdlib logging facility and - // compilations will now fail on freestanding systems that use it but do - // not explicitly set `root.std_options.logFn` - pub usingnamespace if (!@hasDecl(options_override, "logFn")) - struct { +const app = @import("app"); + +pub usingnamespace app; + +// Use microzig panic handler if not defined by an application +pub usingnamespace if (!@hasDecl(app, "panic")) + struct { + pub const panic = microzig.panic; + } +else + struct {}; + +// Conditionally provide a default no-op logFn if app does not have one +// defined. Parts of microzig use the stdlib logging facility and +// compilations will now fail on freestanding systems that use it but do +// not explicitly set `root.std_options.logFn` +pub usingnamespace if (!@hasDecl(app, "std_options")) + struct { + pub const std_options = struct { pub fn logFn( comptime message_level: std.log.Level, comptime scope: @Type(.EnumLiteral), @@ -23,22 +30,18 @@ pub const std_options = struct { _ = format; _ = args; } - } - else - struct {}; -}; - -// Allow app to override the os API layer -pub const os = if (@hasDecl(app, "os")) - app.os -else - struct {}; - -// Allow app to override the panic handler -pub const panic = if (@hasDecl(app, "panic")) - app.panic + }; + } else - microzig.panic; + struct { + comptime { + // Technically the compiler's errors should be good enough that we + // shouldn't include errors like this, but since we add default + // behavior we should clarify the situation for the user. + if (!@hasDecl(app.std_options, "logFn")) + @compileError("By default MicroZig provides a no-op logging function. Since you are exporting `std_options`, you must export the stdlib logging function yourself."); + } + }; // Startup logic: comptime { @@ -102,7 +105,7 @@ export fn microzig_main() noreturn { // function. if (@hasDecl(app, "init")) app.init() - else if (@hasDecl(microzig.hal, "init")) + else if (microzig.hal != void and @hasDecl(microzig.hal, "init")) microzig.hal.init(); if (@typeInfo(return_type) == .ErrorUnion) { diff --git a/test/backings.zig b/test/backings.zig new file mode 100644 index 0000000..0a08dc5 --- /dev/null +++ b/test/backings.zig @@ -0,0 +1,67 @@ +//! This file contains some backings for different test programs +const std = @import("std"); +const microzig = @import("../build.zig"); + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +const cpu = microzig.Cpu{ + .name = "my_cpu", + .source = .{ + .path = root_dir() ++ "/cpu.zig", + }, + + // this will actually make it a native target, this is still fine + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .none, + }, +}; + +const minimal_chip = microzig.Chip{ + .name = "minimal_chip", + .cpu = cpu, + .source = .{ + .path = root_dir() ++ "/chip.zig", + }, + .memory_regions = &.{ + .{ .offset = 0x00000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000, .length = 0x10000, .kind = .ram }, + }, +}; + +const chip_with_hal = microzig.Chip{ + .name = "chip_with_hal", + .cpu = cpu, + .source = .{ + .path = root_dir() ++ "/chip.zig", + }, + .hal = .{ + .path = root_dir() ++ "/hal.zig", + }, + .memory_regions = &.{ + .{ .offset = 0x00000, .length = 0x10000, .kind = .flash }, + .{ .offset = 0x10000, .length = 0x10000, .kind = .ram }, + }, +}; + +pub const minimal = microzig.Backing{ + .chip = minimal_chip, +}; + +pub const has_hal = microzig.Backing{ + .chip = chip_with_hal, +}; + +pub const has_board = microzig.Backing{ + .board = .{ + .name = "has_board", + .chip = minimal_chip, + .source = .{ + .path = root_dir() ++ "/board.zig", + }, + }, +}; diff --git a/src/core/empty.zig b/test/board.zig similarity index 100% rename from src/core/empty.zig rename to test/board.zig diff --git a/test/chip.zig b/test/chip.zig new file mode 100644 index 0000000..a3ad12e --- /dev/null +++ b/test/chip.zig @@ -0,0 +1,6 @@ +pub const types = struct {}; + +pub const devices = struct { + pub const minimal_chip = struct {}; + pub const chip_with_hal = struct {}; +}; diff --git a/test/cpu.zig b/test/cpu.zig new file mode 100644 index 0000000..7892a04 --- /dev/null +++ b/test/cpu.zig @@ -0,0 +1,3 @@ +pub const startup_logic = struct {}; + +pub fn cli() void {} diff --git a/test/hal.zig b/test/hal.zig new file mode 100644 index 0000000..e69de29 diff --git a/test/programs/blinky.zig b/test/programs/blinky.zig index d84cf96..16a841d 100644 --- a/test/programs/blinky.zig +++ b/test/programs/blinky.zig @@ -6,17 +6,17 @@ const led_pin = if (micro.config.has_board) .@"Arduino Nano" => micro.Pin("D13"), .@"Arduino Uno" => micro.Pin("D13"), .@"mbed LPC1768" => micro.Pin("LED-1"), - .@"STM32F3DISCOVERY" => micro.Pin("LD3"), - .@"STM32F4DISCOVERY" => micro.Pin("LD5"), - .@"STM32F429IDISCOVERY" => micro.Pin("LD4"), + .STM32F3DISCOVERY => micro.Pin("LD3"), + .STM32F4DISCOVERY => micro.Pin("LD5"), + .STM32F429IDISCOVERY => micro.Pin("LD4"), .@"Longan Nano" => micro.Pin("PA2"), else => @compileError("unknown board"), } else switch (micro.config.chip_name) { - .@"ATmega328p" => micro.Pin("PB5"), + .ATmega328p => micro.Pin("PB5"), .@"NXP LPC1768" => micro.Pin("P1.18"), - .@"STM32F103x8" => micro.Pin("PC13"), - .@"GD32VF103x8" => micro.Pin("PA2"), + .STM32F103x8 => micro.Pin("PC13"), + .GD32VF103x8 => micro.Pin("PA2"), else => @compileError("unknown chip"), }; diff --git a/test/programs/has_board.zig b/test/programs/has_board.zig new file mode 100644 index 0000000..8141376 --- /dev/null +++ b/test/programs/has_board.zig @@ -0,0 +1,10 @@ +const std = @import("std"); +const assert = std.debug.assert; +const microzig = @import("microzig"); + +comptime { + assert(microzig.config.has_board); + assert(!microzig.config.has_hal); +} + +pub fn main() void {} diff --git a/test/programs/has_dependencies.zig b/test/programs/has_dependencies.zig new file mode 100644 index 0000000..e69de29 diff --git a/test/programs/has_hal.zig b/test/programs/has_hal.zig new file mode 100644 index 0000000..eed6b0c --- /dev/null +++ b/test/programs/has_hal.zig @@ -0,0 +1,10 @@ +const std = @import("std"); +const assert = std.debug.assert; +const microzig = @import("microzig"); + +comptime { + assert(microzig.config.has_hal); + assert(!microzig.config.has_board); +} + +pub fn main() void {} diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig index 5258ce3..3ef20f7 100644 --- a/test/programs/minimal.zig +++ b/test/programs/minimal.zig @@ -1,5 +1,11 @@ -const micro = @import("microzig"); +const std = @import("std"); +const assert = std.debug.assert; +const microzig = @import("microzig"); +const peripherals = microzig.chip.peripherals; -pub fn main() void { - // This function will contain the application logic. +comptime { + assert(!microzig.config.has_board); + assert(!microzig.config.has_hal); } + +pub fn main() void {} From 08e7d5b01a8ca6a53e3892f763507f1ff3b07725 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 28 Feb 2023 01:44:59 -0800 Subject: [PATCH 106/138] add check for void for microzig.hal (#112) * add check for void for microzig.hal * modify github actions to run on every push --- .github/workflows/build.yml | 5 ----- src/modules/cpus/cortex-m.zig | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 57245c8..f41ccca 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,11 +1,6 @@ name: Build on: push: - branches: [ main ] - pull_request: - branches: [ main ] - schedule: - - cron: "0 0 * * *" jobs: build: diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index 4802e9d..3338ff3 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -84,7 +84,7 @@ fn is_valid_field(field_name: []const u8) bool { const VectorTable = if (@hasDecl(root, "microzig_options") and @hasDecl(root.microzig_options, "VectorTable")) root.microzig_options.VectorTable -else if (@hasDecl(microzig.hal, "VectorTable")) +else if (microzig.hal != void and @hasDecl(microzig.hal, "VectorTable")) microzig.hal.VectorTable else microzig.chip.VectorTable; From 15c5a92a3e343b0d8e17abf6967490ba15526390 Mon Sep 17 00:00:00 2001 From: Jim Tittsler Date: Sun, 19 Mar 2023 02:16:44 +0900 Subject: [PATCH 107/138] Fix typos (#113) --- README.adoc | 14 +++++++------- docs/design.adoc | 8 ++++---- docs/hardware_support_packages.adoc | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/README.adoc b/README.adoc index dd8fcab..cb4e432 100644 --- a/README.adoc +++ b/README.adoc @@ -6,17 +6,17 @@ image::logo-text-auto.svg[] image::https://img.shields.io/discord/824493524413710336.svg?logo=discord[link=https://discord.gg/ShUWykk38X] [NOTE] -This is in development, breaks in the API are bound to happen +This is in development; breaks in the API are bound to happen. toc::[] == Contributing -Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], its used as a place to brainstorm and organize work in ZEG. There will be issues marked as `good first issue`, or drafts for larger ideas that need scoping/breaking ground on. +Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], it's used as a place to brainstorm and organize work in ZEG. There will be issues marked as `good first issue` or drafts for larger ideas that need scoping/breaking ground on. == Introduction -This repo contains the infrastructure for getting started in an embedded Zig project, it "gets you to main()". Specifically it offers: +This repo contains the infrastructure for getting started in an embedded Zig project; it "gets you to main()". Specifically, it offers: * a single easy-to-use builder function that: ** generates your linker script @@ -31,7 +31,7 @@ For MicroZig internals please see the xref:docs/design.adoc[Design Document]. == Does MicroZig support X hardware? -MicroZig is designed to cover as wide swath of hardware as possible. The https://github.com/ZigEmbeddedGroup[Zig Embedded Group] has some repositories that contain hardware-specific code. You will find them with the `hardware-support-package` label. If you can't find your specific device, it doesn't mean that you can't run Zig on it, it's likely you're just the first! In that case see xref:#getting-microzig-on-new-hardware[Getting MicroZig on New Hardare]. +MicroZig is designed to cover as wide a swath of hardware as possible. The https://github.com/ZigEmbeddedGroup[Zig Embedded Group] has some repositories that contain hardware-specific code. You will find them with the `hardware-support-package` label. If you can't find your specific device, it doesn't mean that you can't run Zig on it, it's likely you're just the first! In that case, see xref:#getting-microzig-on-new-hardware[Getting MicroZig on New Hardare]. Start with an empty Zig project by running `zig init-exe`, and add the hardware support package as a submodule. We'll use `microchip-atmega` in our example: @@ -86,7 +86,7 @@ If you have a board/chip that isn't defined in microzig, you can set it up yours * SVD or ATDF file defining registers * flash and ram address and sizes -First use https://github.com/ZigEmbeddedGroup/regz[Regz] to generate the register definitions for your chip and save them to a file. Then define the chip: +First, use https://github.com/ZigEmbeddedGroup/regz[Regz] to generate the register definitions for your chip and save them to a file. Then define the chip: [source,zig] ---- @@ -107,7 +107,7 @@ const backing = .{ }; ---- -It's important that the chip name actually match one of the entries under `devices` in the generated code. +It's important that the chip name actually matches one of the entries under `devices` in the generated code. === Optional: JSON Register Schema @@ -134,7 +134,7 @@ const nrf52832 = Chip{ == Interrupts -The current supported architectures for interrupt vector generation are ARM and AVR. To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace, which is nested in a `microzig_options` namespace: +The currently supported architectures for interrupt vector generation are ARM and AVR. To define the Interrupt Service Routine (ISR) for a given interrupt, you create a function with the same name in an `interrupts` namespace, which is nested in a `microzig_options` namespace: [source,zig] ---- diff --git a/docs/design.adoc b/docs/design.adoc index 4e97a2d..075279a 100644 --- a/docs/design.adoc +++ b/docs/design.adoc @@ -10,7 +10,7 @@ The build portion of MicroZig sets up a dependency graph like the following. image::deps.svg[] -Your application lives in `app`, that's where `main()` resides. `root` contains the entry point, and will set up [zero-initialized data] and [uninitialized data]. This is all encapsulated in an `EmbeddedExecutable` object. It has methods to add dependencies acquired from the package manager. +Your application lives in `app`; that's where `main()` resides. `root` contains the entry point and will set up [zero-initialized data] and [uninitialized data]. This is all encapsulated in an `EmbeddedExecutable` object. It has methods to add dependencies acquired from the package manager. The `microzig` module has different namespaces, some are static, but the nodes you see in the diagram above are switched out according to your configured hardware. @@ -20,9 +20,9 @@ The configurable modules, with the exception of `config`, are able to import `mi === `cpu` -This module models your specific CPU, and is important for initializing memory. Generally you shouldn't need to define this yourself, it's likely that MicroZig will have the definition for you. +This module models your specific CPU and is important for initializing memory. Generally, you shouldn't need to define this yourself, it's likely that MicroZig will have the definition for you. -Further research is needed for SOCs with multiple, heterogenous CPUs. Likely it means patching together multiple `EmbeddedExecutable`s. +Further research is needed for SOCs with multiple, heterogeneous CPUs. Likely it means patching together multiple `EmbeddedExecutable`s. === `chip` @@ -74,7 +74,7 @@ When making a package that defines chips for others, see xref:hardware_support_p === `hal` -This module contains hand-written code for interracting with the chip. +This module contains hand-written code for interacting with the chip. TODO diff --git a/docs/hardware_support_packages.adoc b/docs/hardware_support_packages.adoc index 4b8605f..595f082 100644 --- a/docs/hardware_support_packages.adoc +++ b/docs/hardware_support_packages.adoc @@ -4,4 +4,4 @@ toc::[] -This document goes over the _suggested_ way to structure a hardware support package. At the end of the day, MicroZig is designed for flexibility, we do not require all "supported" hardware be defined in one monorepo. Instead we make it so that you can define your hardware locally if that best suites your project. +This document goes over the _suggested_ way to structure a hardware support package. At the end of the day, MicroZig is designed for flexibility, we do not require all "supported" hardware be defined in one monorepo. Instead, we make it so that you can define your hardware locally if that best suits your project. From 6f5b7268f68f001144bd5ebacc0c0203a7a50fde Mon Sep 17 00:00:00 2001 From: Vesim Date: Sun, 19 Mar 2023 22:25:54 +0100 Subject: [PATCH 108/138] Update to latest zig master (#114) --- src/modules/LinkerScriptStep.zig | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig index 368b7a1..8a25bfe 100644 --- a/src/modules/LinkerScriptStep.zig +++ b/src/modules/LinkerScriptStep.zig @@ -37,7 +37,12 @@ pub fn create(builder: *Builder, chip: Chip) !*LinkerscriptStep { var ret = try builder.allocator.create(LinkerscriptStep); ret.* = LinkerscriptStep{ - .step = Step.init(.custom, "linkerscript", builder.allocator, make), + .step = Step.init(.{ + .id = .custom, + .name = "linkerscript", + .owner = builder, + .makeFn = make, + }), .generated_file = .{ .step = &ret.step, .path = path, @@ -48,7 +53,8 @@ pub fn create(builder: *Builder, chip: Chip) !*LinkerscriptStep { return ret; } -fn make(step: *Step) !void { +fn make(step: *Step, progress: *std.Progress.Node) !void { + _ = progress; const linkerscript = @fieldParentPtr(LinkerscriptStep, "step", step); const file = try std.fs.cwd().createFile(linkerscript.generated_file.path.?, .{}); defer file.close(); From dabc9325cdee394ff66e28c91803cb814954b157 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 22 Mar 2023 00:52:40 -0700 Subject: [PATCH 109/138] improvements from working on RP2040 (#115) * improvements from working on RP2040 * fix missing file bug --- build.zig | 30 ++++++++---- src/modules/LinkerScriptStep.zig | 81 +++++++++++++++++--------------- src/modules/cpus/cortex-m.zig | 2 +- 3 files changed, 66 insertions(+), 47 deletions(-) diff --git a/build.zig b/build.zig index 5e48566..57a2ae3 100644 --- a/build.zig +++ b/build.zig @@ -30,8 +30,18 @@ pub const Backing = union(enum) { pub const EmbeddedExecutable = struct { inner: *LibExeObjStep, - pub fn addModule(exe: *EmbeddedExecutable, name: []const u8, module: *Module) void { - exe.inner.addModule(name, module); + pub const AppDependencyOptions = struct { + depend_on_microzig: bool = false, + }; + + pub fn addAppDependency(exe: *EmbeddedExecutable, name: []const u8, module: *Module, options: AppDependencyOptions) void { + if (options.depend_on_microzig) { + const microzig_module = exe.inner.modules.get("microzig").?; + module.dependencies.put("microzig", microzig_module) catch @panic("OOM"); + } + + const app_module = exe.inner.modules.get("app").?; + app_module.dependencies.put(name, module) catch @panic("OOM"); } pub fn install(exe: *EmbeddedExecutable) void { @@ -190,6 +200,13 @@ pub fn addEmbeddedExecutable( else => {}, } + const app_module = builder.createModule(.{ + .source_file = opts.source_file, + .dependencies = &.{ + .{ .name = "microzig", .module = microzig_module }, + }, + }); + const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; exe.* = EmbeddedExecutable{ .inner = builder.addExecutable(.{ @@ -199,6 +216,8 @@ pub fn addEmbeddedExecutable( .optimize = opts.optimize, }), }; + exe.inner.addModule("app", app_module); + exe.inner.addModule("microzig", microzig_module); exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded @@ -218,13 +237,6 @@ pub fn addEmbeddedExecutable( // - This requires building another tool that runs on the host that compiles those files and emits the linker script. // - src/tools/linkerscript-gen.zig is the source file for this exe.inner.bundle_compiler_rt = (exe.inner.target.getCpuArch() != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now - exe.addModule("microzig", microzig_module); - exe.addModule("app", builder.createModule(.{ - .source_file = opts.source_file, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, - }, - })); return exe; } diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig index 8a25bfe..fb92277 100644 --- a/src/modules/LinkerScriptStep.zig +++ b/src/modules/LinkerScriptStep.zig @@ -2,65 +2,41 @@ const std = @import("std"); const MemoryRegion = @import("MemoryRegion.zig"); const Chip = @import("Chip.zig"); const Step = std.build.Step; -const Builder = std.build.Builder; +const Build = std.Build; const GeneratedFile = std.build.GeneratedFile; const LinkerscriptStep = @This(); step: Step, generated_file: std.build.GeneratedFile, -builder: *Builder, chip: Chip, -pub fn create(builder: *Builder, chip: Chip) !*LinkerscriptStep { - var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); - - hasher.update(chip.name); - hasher.update(chip.source.getPath(builder)); - hasher.update(chip.cpu.name); - hasher.update(chip.cpu.source.getPath(builder)); - - var mac: [16]u8 = undefined; - hasher.final(&mac); - - const filename = try std.fmt.allocPrint(builder.allocator, "{}{s}", .{ - std.fmt.fmtSliceHexLower(&mac), - ".ld", - }); - - const path = try std.fs.path.join(builder.allocator, &.{ - "zig-cache", - "microzig", - filename, - }); - try std.fs.cwd().makePath(std.fs.path.dirname(path).?); - - var ret = try builder.allocator.create(LinkerscriptStep); - ret.* = LinkerscriptStep{ +pub fn create(owner: *Build, chip: Chip) !*LinkerscriptStep { + var linkerscript = try owner.allocator.create(LinkerscriptStep); + linkerscript.* = LinkerscriptStep{ .step = Step.init(.{ .id = .custom, .name = "linkerscript", - .owner = builder, + .owner = owner, .makeFn = make, }), .generated_file = .{ - .step = &ret.step, - .path = path, + .step = &linkerscript.step, }, - .builder = builder, .chip = chip, }; - return ret; + + return linkerscript; } -fn make(step: *Step, progress: *std.Progress.Node) !void { - _ = progress; +fn make(step: *Step, _: *std.Progress.Node) anyerror!void { const linkerscript = @fieldParentPtr(LinkerscriptStep, "step", step); - const file = try std.fs.cwd().createFile(linkerscript.generated_file.path.?, .{}); - defer file.close(); + const owner = linkerscript.step.owner; const target = linkerscript.chip.cpu.target; - const writer = file.writer(); + + var contents = std.ArrayList(u8).init(owner.allocator); + const writer = contents.writer(); try writer.print( \\/* \\ * This file was auto-generated by microzig @@ -162,4 +138,35 @@ fn make(step: *Step, progress: *std.Progress.Node) !void { // \\ ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" ); // \\ // ); + + const filename = try std.fmt.allocPrint(owner.allocator, "{s}_{s}.ld", .{ + linkerscript.chip.name, + linkerscript.chip.cpu.name, + }); + + var hash = owner.cache.hash; + hash.addBytes(linkerscript.chip.name); + hash.addBytes(linkerscript.chip.cpu.name); + + // TODO: hash more information to reduce chance of collision + for (linkerscript.chip.memory_regions) |memory_region| { + hash.add(memory_region.offset); + hash.add(memory_region.length); + } + + const digest = hash.final(); + const dir_path = try owner.cache_root.join(owner.allocator, &.{ + "microzig", + &digest, + }); + + var dir = try owner.cache_root.handle.makeOpenPath(dir_path, .{}); + defer dir.close(); + + const file = try dir.createFile(filename, .{}); + defer file.close(); + + try file.writeAll(contents.items); + const full_path = owner.pathJoin(&.{ dir_path, filename }); + linkerscript.generated_file.path = full_path; } diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index 3338ff3..f69151b 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -135,7 +135,7 @@ fn create_interrupt_vector( .C = struct { fn wrapper() callconv(.C) void { if (calling_convention == .Unspecified) // TODO: workaround for some weird stage1 bug - @call(.{ .modifier = .always_inline }, function, .{}); + @call(.always_inline, function, .{}); } }.wrapper, }, From 5b0176e97781a77420be309b6505dc582713a2a5 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:15:06 -0700 Subject: [PATCH 110/138] specify which version of zig to use (#116) --- README.adoc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.adoc b/README.adoc index cb4e432..4245a4c 100644 --- a/README.adoc +++ b/README.adoc @@ -10,6 +10,10 @@ This is in development; breaks in the API are bound to happen. toc::[] +== What version of Zig to use + +Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. + == Contributing Please see the https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1[project page], it's used as a place to brainstorm and organize work in ZEG. There will be issues marked as `good first issue` or drafts for larger ideas that need scoping/breaking ground on. From ceaa9ddcb080d0687ce2109f23db7db376ac911e Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:37:38 -0700 Subject: [PATCH 111/138] fix link (#117) --- README.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index 4245a4c..10a6866 100644 --- a/README.adoc +++ b/README.adoc @@ -12,7 +12,7 @@ toc::[] == What version of Zig to use -Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. +Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig. == Contributing From 23482a6986252e0eeff54a04abc0aac8a08d25d7 Mon Sep 17 00:00:00 2001 From: Philipp Wendel <41269321+PhilippWendel@users.noreply.github.com> Date: Mon, 3 Apr 2023 00:19:37 +0200 Subject: [PATCH 112/138] Updated parts of gpio and pin to reflect code changes from regz rewrite (#120) --- README.adoc | 2 +- src/core/experimental/gpio.zig | 24 ++++++++++++------------ src/core/experimental/pin.zig | 4 ++-- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/README.adoc b/README.adoc index 10a6866..a71c160 100644 --- a/README.adoc +++ b/README.adoc @@ -51,7 +51,7 @@ pub fn build(b: *std.build.Builder) !void { const optimize = b.standardOptimizeOption(.{}); var exe = microzig.addEmbeddedExecutable( b, .{ .name = "my-executable", - .root_source_file = .{ + .source_file = .{ .path = "src/main.zig", }, .backing = .{ diff --git a/src/core/experimental/gpio.zig b/src/core/experimental/gpio.zig index 552bdde..e7ec33a 100644 --- a/src/core/experimental/gpio.zig +++ b/src/core/experimental/gpio.zig @@ -1,6 +1,6 @@ const std = @import("std"); const micro = @import("microzig"); -const chip = @import("chip"); +const hal = @import("hal"); pub const Mode = enum { input, @@ -59,8 +59,8 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { }); }, .alternate_function => { - if (comptime @hasDecl(chip.gpio, "AlternateFunction")) { - const alternate_function = @as(chip.gpio.AlternateFunction, config.alternate_function); + if (comptime @hasDecl(hal.gpio, "AlternateFunction")) { + const alternate_function = @as(hal.gpio.AlternateFunction, config.alternate_function); set_alternate_function(alternate_function); } else { @compileError("Alternate Function not supported yet"); @@ -70,12 +70,12 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { } fn read() State { - return chip.gpio.read(pin.source_pin); + return hal.gpio.read(pin.source_pin); } // outputs: fn write(state: State) void { - chip.gpio.write(pin.source_pin, state); + hal.gpio.write(pin.source_pin, state); } fn set_to_high() void { @@ -85,8 +85,8 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { write(.low); } fn toggle() void { - if (comptime @hasDecl(chip.gpio, "toggle")) { - chip.gpio.toggle(pin.source_pin); + if (comptime @hasDecl(hal.gpio, "toggle")) { + hal.gpio.toggle(pin.source_pin); } else { write(switch (read()) { .low => State.high, @@ -99,14 +99,14 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { fn set_direction(dir: Direction, output_state: State) void { switch (dir) { .output => { - chip.gpio.setOutput(pin.source_pin); + hal.gpio.setOutput(pin.source_pin); write(output_state); }, - .input => chip.gpio.setInput(pin.source_pin), + .input => hal.gpio.setInput(pin.source_pin), } } fn get_direction() Direction { - if (chip.gpio.isOutput(pin.source_pin)) { + if (hal.gpio.isOutput(pin.source_pin)) { return .output; } else { return .input; @@ -123,8 +123,8 @@ pub fn Gpio(comptime pin: type, comptime config: anytype) type { } // alternate function - fn set_alternate_function(af: chip.gpio.AlternateFunction) void { - chip.gpio.setAlternateFunction(pin.source_pin, af); + fn set_alternate_function(af: hal.gpio.AlternateFunction) void { + hal.gpio.setAlternateFunction(pin.source_pin, af); } }; // return only a subset of Generic for the requested pin. diff --git a/src/core/experimental/pin.zig b/src/core/experimental/pin.zig index ae049e9..42e8492 100644 --- a/src/core/experimental/pin.zig +++ b/src/core/experimental/pin.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("microzig"); +const config = @import("config"); const chip = @import("chip"); const board = @import("board"); const hal = @import("hal"); @@ -23,7 +23,7 @@ pub fn Pin(comptime spec: []const u8) type { hal.parse_pin(@field(board.pin_map, spec[board_namespace.len..])) else if (std.mem.startsWith(u8, spec, chip_namespace)) hal.parse_pin(spec[chip_namespace.len..]) - else if (micro.config.has_board and @hasField(@TypeOf(board.pin_map), spec)) + else if (config.has_board and @hasField(@TypeOf(board.pin_map), spec)) hal.parse_pin(@field(board.pin_map, spec)) else hal.parse_pin(spec); From ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 13 Apr 2023 22:15:18 -0700 Subject: [PATCH 113/138] update to new usage of build api (#122) --- build.zig | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/build.zig b/build.zig index 57a2ae3..dced067 100644 --- a/build.zig +++ b/build.zig @@ -6,6 +6,7 @@ const std = @import("std"); const LibExeObjStep = std.build.LibExeObjStep; const Module = std.build.Module; const FileSource = std.build.FileSource; +const Builder = std.Build; // alias for packages pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig"); @@ -44,12 +45,8 @@ pub const EmbeddedExecutable = struct { app_module.dependencies.put(name, module) catch @panic("OOM"); } - pub fn install(exe: *EmbeddedExecutable) void { - exe.inner.install(); - } - - pub fn installRaw(exe: *EmbeddedExecutable, dest_filename: []const u8, options: std.build.InstallRawStep.CreateOptions) *std.build.InstallRawStep { - return exe.inner.installRaw(dest_filename, options); + pub fn installArtifact(exe: *EmbeddedExecutable, b: *Builder) void { + b.installArtifact(exe.inner); } pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { From 109249913bfe9e04c881b1216c8c258d7b097c44 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 16 Apr 2023 12:47:52 -0700 Subject: [PATCH 114/138] check if the thread of execution is in an ISR on Cortex M (#123) --- src/modules/cpus/cortex-m.zig | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index f69151b..5b9715f 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -1,7 +1,32 @@ const std = @import("std"); const microzig = @import("microzig"); +const mmio = microzig.mmio; const root = @import("root"); +pub const regs = struct { + // Interrupt Control and State Register + pub const ICSR = @intToPtr(*volatile mmio.Mmio(packed struct { + VECTACTIVE: u9, + reserved0: u2, + RETTOBASE: u1, + VECTPENDING: u9, + reserved1: u1, + ISRPENDING: u1, + ISRPREEMPT: u1, + reserved2: u1, + PENDSTCLR: u1, + PENDSTSET: u1, + PENDSVCLR: u1, + PENDSVSET: u1, + reserved3: u2, + NMIPENDSET: u1, + }), 0xE000ED04); +}; + +pub fn executing_isr() bool { + return regs.ICSR.read().VECTACTIVE != 0; +} + pub fn sei() void { asm volatile ("cpsie i"); } From dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab Mon Sep 17 00:00:00 2001 From: David Sugar Date: Sun, 23 Apr 2023 17:31:08 +0200 Subject: [PATCH 115/138] Abstract USB device implementation (#124) --- build.zig | 8 + src/core.zig | 6 + src/core/usb.zig | 875 +++++++++++++++++++++++++++++++++++++++++++ src/core/usb/hid.zig | 458 ++++++++++++++++++++++ 4 files changed, 1347 insertions(+) create mode 100644 src/core/usb.zig create mode 100644 src/core/usb/hid.zig diff --git a/build.zig b/build.zig index dced067..86231e9 100644 --- a/build.zig +++ b/build.zig @@ -270,8 +270,16 @@ pub fn build(b: *std.build.Builder) !void { .optimize = optimize, }); + const core_tests = b.addTest(.{ + .root_source_file = .{ + .path = comptime root_dir() ++ "/src/core.zig", + }, + .optimize = optimize, + }); + const test_step = b.step("test", "build test programs"); test_step.dependOn(&minimal.inner.step); test_step.dependOn(&has_hal.inner.step); test_step.dependOn(&has_board.inner.step); + test_step.dependOn(&b.addRunArtifact(core_tests).step); } diff --git a/src/core.zig b/src/core.zig index c4b9cdd..10b26c2 100644 --- a/src/core.zig +++ b/src/core.zig @@ -1 +1,7 @@ pub const experimental = @import("core/experimental.zig"); +/// USB data types and helper functions +pub const usb = @import("core/usb.zig"); + +test "core tests" { + _ = usb; +} diff --git a/src/core/usb.zig b/src/core/usb.zig new file mode 100644 index 0000000..bfb886c --- /dev/null +++ b/src/core/usb.zig @@ -0,0 +1,875 @@ +//! Abstract USB device implementation +//! +//! This can be used to setup a USB device. +//! +//! ## Usage +//! +//! 1. Define the functions (`pub const F = struct { ... }`) required by `Usb()` (see below) +//! 2. Call `pub const device = Usb(F)` +//! 3. Define the device configuration (DeviceConfiguration) +//! 4. Initialize the device in main by calling `usb.init_clk()` and `usb.init_device(device_conf)` +//! 5. Call `usb.task()` within the main loop + +const std = @import("std"); + +/// USB Human Interface Device (HID) +pub const hid = @import("usb/hid.zig"); + +/// Create a USB device +/// +/// # Arguments +/// +/// This is a abstract USB device implementation that requires a handful of functions +/// to work correctly: +/// +/// * `usb_init_clk() void` - Initialize the USB clock +/// * `usb_init_device(*DeviceConfiguration) - Initialize the USB device controller (e.g. enable interrupts, etc.) +/// * `usb_start_tx(*EndpointConfiguration, []const u8)` - Transmit the given bytes over the specified endpoint +/// * `usb_start_rx(*usb.EndpointConfiguration, n: usize)` - Receive n bytes over the specified endpoint +/// * `get_interrupts() InterruptStatus` - Return which interrupts haven't been handled yet +/// * `get_setup_packet() SetupPacket` - Return the USB setup packet received (called if SetupReq received). Make sure to clear the status flag yourself! +/// * `bus_reset() void` - Called on a bus reset interrupt +/// * `set_address(addr: u7) void` - Set the given address +/// * `get_EPBIter(*const DeviceConfiguration) EPBIter` - Return an endpoint buffer iterator. Each call to next returns an unhandeled endpoint buffer with data. How next is implemented depends on the system. +/// The functions must be grouped under the same name space and passed to the fuction at compile time. +/// The functions will be accessible to the user through the `callbacks` field. +pub fn Usb(comptime f: anytype) type { + return struct { + /// The usb configuration set + var usb_config: ?*DeviceConfiguration = null; + /// The clock has been initialized [Y/n] + var clk_init: bool = false; + + /// Index of enpoint buffer 0 out + pub const EP0_OUT_IDX = 0; + /// Index of enpoint buffer 0 in + pub const EP0_IN_IDX = 1; + /// The callbacks passed provided by the caller + pub const callbacks = f; + + /// Initialize the USB clock + pub fn init_clk() void { + f.usb_init_clk(); + clk_init = true; + } + + /// Initialize the usb device using the given configuration + /// + /// This function will return an error if the clock hasn't been initialized. + pub fn init_device(device_config: *DeviceConfiguration) !void { + if (!clk_init) return error.UninitializedClock; + + f.usb_init_device(device_config); + usb_config = device_config; + } + + /// Usb task function meant to be executed in regular intervals after + /// initializing the device. + /// + /// This function will return an error if the device hasn't been initialized. + pub fn task(debug: bool) !void { + if (usb_config == null) return error.UninitializedDevice; + + // We'll keep some state in Plain Old Static Local Variables: + const S = struct { + // When the host gives us a new address, we can't just slap it into + // registers right away, because we have to do an acknowledgement step using + // our _old_ address. + var new_address: ?u8 = null; + // Flag recording whether the host has configured us with a + // `SetConfiguration` message. + var configured = false; + // Flag recording whether we've set up buffer transfers after being + // configured. + var started = false; + // Some scratch space that we'll use for things like preparing string + // descriptors for transmission. + var tmp: [64]u8 = .{0} ** 64; + }; + + // Check which interrupt flags are set. + const ints = f.get_interrupts(); + + // Setup request received? + if (ints.SetupReq) { + if (debug) std.log.info("setup req", .{}); + + // Get the setup request setup packet + const setup = f.get_setup_packet(); + + // Reset PID to 1 for EP0 IN. Every DATA packet we send in response + // to an IN on EP0 needs to use PID DATA1, and this line will ensure + // that. + usb_config.?.endpoints[EP0_IN_IDX].next_pid_1 = true; + + // Attempt to parse the request type and request into one of our + // known enum values, and then inspect them. (These will return None + // if we get an unexpected numeric value.) + const reqty = Dir.of_endpoint_addr(setup.request_type); + const req = SetupRequest.from_u8(setup.request); + + if (reqty == Dir.Out and req != null and req.? == SetupRequest.SetAddress) { + // The new address is in the bottom 8 bits of the setup + // packet value field. Store it for use later. + S.new_address = @intCast(u8, setup.value & 0xff); + // The address will actually get set later, we have + // to use address 0 to send a status response. + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], //EP0_IN_CFG, + &.{}, // <- see, empty buffer + ); + if (debug) std.log.info(" SetAddress: {}", .{S.new_address.?}); + } else if (reqty == Dir.Out and req != null and req.? == SetupRequest.SetConfiguration) { + // We only have one configuration, and it doesn't really + // mean anything to us -- more of a formality. All we do in + // response to this is: + S.configured = true; + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], //EP0_IN_CFG, + &.{}, // <- see, empty buffer + ); + if (debug) std.log.info(" SetConfiguration", .{}); + } else if (reqty == Dir.Out) { + // This is sort of a hack, but: if we get any other kind of + // OUT, just acknowledge it with the same zero-length status + // phase that we use for control transfers that we _do_ + // understand. This keeps the host from spinning forever + // while we NAK. + // + // This behavior copied shamelessly from the C example. + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], // EP0_IN_CFG, + &.{}, // <- see, empty buffer + ); + if (debug) std.log.info(" Just OUT", .{}); + } else if (reqty == Dir.In and req != null and req.? == SetupRequest.GetDescriptor) { + // Identify the requested descriptor type, which is in the + // _top_ 8 bits of value. + const descriptor_type = DescType.from_u16(setup.value >> 8); + if (debug) std.log.info(" GetDescriptor: {}", .{setup.value >> 8}); + if (descriptor_type) |dt| { + switch (dt) { + .Device => { + if (debug) std.log.info(" Device", .{}); + // TODO: this sure looks like a duplicate, but it's + // a duplicate that was present in the C + // implementation. + usb_config.?.endpoints[EP0_IN_IDX].next_pid_1 = true; + + const dc = usb_config.?.device_descriptor.serialize(); + std.mem.copy(u8, S.tmp[0..dc.len], &dc); + + // Configure EP0 IN to send the device descriptor + // when it's next asked. + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + S.tmp[0..dc.len], + ); + }, + .Config => { + if (debug) std.log.info(" Config", .{}); + // Config descriptor requests are slightly unusual. + // We can respond with just our config descriptor, + // but we can _also_ append our interface and + // endpoint descriptors to the end, saving some + // round trips. We'll choose to do this if the + // number of bytes the host will accept (in the + // `length` field) is large enough. + var used: usize = 0; + + const cd = usb_config.?.config_descriptor.serialize(); + std.mem.copy(u8, S.tmp[used .. used + cd.len], &cd); + used += cd.len; + + if (setup.length > used) { + // Do the rest! + // + // This is slightly incorrect because the host + // might have asked for a number of bytes in + // between the size of a config descriptor, and + // the amount we're going to send back. However, + // in practice, the host always asks for either + // (1) the exact size of a config descriptor, or + // (2) 64 bytes, and this all fits in 64 bytes. + const id = usb_config.?.interface_descriptor.serialize(); + std.mem.copy(u8, S.tmp[used .. used + id.len], &id); + used += id.len; + + // Seems like the host does not bother asking for the + // hid descriptor so we'll just send it with the + // other descriptors. + if (usb_config.?.hid) |hid_conf| { + const hd = hid_conf.hid_descriptor.serialize(); + std.mem.copy(u8, S.tmp[used .. used + hd.len], &hd); + used += hd.len; + } + + // TODO: depending on the number of endpoints + // this might not fit in 64 bytes -> split message + // into multiple packets + for (usb_config.?.endpoints[2..]) |ep| { + const ed = ep.descriptor.serialize(); + std.mem.copy(u8, S.tmp[used .. used + ed.len], &ed); + used += ed.len; + } + } + + // Set up EP0 IN to send the stuff we just composed. + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + S.tmp[0..used], + ); + }, + .String => { + if (debug) std.log.info(" String", .{}); + // String descriptor index is in bottom 8 bits of + // `value`. + const i = @intCast(usize, setup.value & 0xff); + const bytes = StringBlk: { + if (i == 0) { + // Special index 0 requests the language + // descriptor. + break :StringBlk usb_config.?.lang_descriptor; + } else { + // Otherwise, set up one of our strings. + const s = usb_config.?.descriptor_strings[i - 1]; + const len = 2 + s.len; + + S.tmp[0] = @intCast(u8, len); + S.tmp[1] = 0x03; + std.mem.copy(u8, S.tmp[2..len], s); + + break :StringBlk S.tmp[0..len]; + } + }; + // Set up EP0 IN to send whichever thing we just + // decided on. + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + bytes, + ); + }, + .Interface => { + if (debug) std.log.info(" Interface", .{}); + // We don't expect the host to send this because we + // delivered our interface descriptor with the + // config descriptor. + // + // Should probably implement it, though, because + // otherwise the host will be unhappy. TODO. + // + // Note that the C example gets away with ignoring + // this. + }, + .Endpoint => { + if (debug) std.log.info(" Endpoint", .{}); + // Same deal as interface descriptors above. + }, + .DeviceQualifier => { + if (debug) std.log.info(" DeviceQualifier", .{}); + // We will just copy parts of the DeviceDescriptor because + // the DeviceQualifierDescriptor can be seen as a subset. + const dqd = DeviceQualifierDescriptor{ + .bcd_usb = usb_config.?.device_descriptor.bcd_usb, + .device_class = usb_config.?.device_descriptor.device_class, + .device_subclass = usb_config.?.device_descriptor.device_subclass, + .device_protocol = usb_config.?.device_descriptor.device_protocol, + .max_packet_size0 = usb_config.?.device_descriptor.max_packet_size0, + .num_configurations = usb_config.?.device_descriptor.num_configurations, + }; + + const data = dqd.serialize(); + std.mem.copy(u8, S.tmp[0..data.len], &data); + + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + S.tmp[0..data.len], + ); + }, + } + } else { + // Maybe the unknown request type is a hid request + + if (usb_config.?.hid) |hid_conf| { + const _hid_desc_type = hid.DescType.from_u16(setup.value >> 8); + + if (_hid_desc_type) |hid_desc_type| { + switch (hid_desc_type) { + .Hid => { + if (debug) std.log.info(" HID", .{}); + + const hd = hid_conf.hid_descriptor.serialize(); + std.mem.copy(u8, S.tmp[0..hd.len], &hd); + + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + S.tmp[0..hd.len], + ); + }, + .Report => { + if (debug) std.log.info(" Report", .{}); + + // The report descriptor is already a (static) + // u8 array, i.e., we can pass it directly + f.usb_start_tx( + usb_config.?.endpoints[EP0_IN_IDX], + hid_conf.report_descriptor, + ); + }, + .Physical => { + if (debug) std.log.info(" Physical", .{}); + // Ignore for now + }, + } + } else { + // It's not a valid HID request. This can totally happen + // we'll just ignore it for now... + } + } + } + } else if (reqty == Dir.In) { + if (debug) std.log.info(" Just IN", .{}); + // Other IN request. Ignore. + } else { + if (debug) std.log.info(" This is unexpected", .{}); + // Unexpected request type or request bits. This can totally + // happen (yay, hardware!) but is rare in practice. Ignore + // it. + } + } // <-- END of setup request handling + + // Events on one or more buffers? (In practice, always one.) + if (ints.BuffStatus) { + if (debug) std.log.info("buff status", .{}); + var iter = f.get_EPBIter(usb_config.?); + + while (iter.next(&iter)) |epb| { + if (debug) std.log.info(" data: {any}", .{epb.buffer}); + + // Perform any required action on the data. For OUT, the `data` + // will be whatever was sent by the host. For IN, it's a copy of + // whatever we sent. + switch (epb.endpoint.descriptor.endpoint_address) { + EP0_IN_ADDR => { + if (debug) std.log.info(" EP0_IN_ADDR", .{}); + // We use this opportunity to finish the delayed + // SetAddress request, if there is one: + if (S.new_address) |addr| { + // Change our address: + f.set_address(@intCast(u7, addr)); + } else { + // Otherwise, we've just finished sending + // something to the host. We expect an ensuing + // status phase where the host sends us (via EP0 + // OUT) a zero-byte DATA packet, so, set that + // up: + f.usb_start_rx( + usb_config.?.endpoints[EP0_OUT_IDX], // EP0_OUT_CFG, + 0, + ); + } + }, + else => { + if (debug) std.log.info(" ELSE, ep_addr: {}", .{ + epb.endpoint.descriptor.endpoint_address & 0x7f, + }); + // Handle user provided endpoints. + + // Invoke the callback (if the user provides one). + if (epb.endpoint.callback) |callback| callback(usb_config.?, epb.buffer); + }, + } + } + } // <-- END of buf status handling + + // Has the host signaled a bus reset? + if (ints.BusReset) { + if (debug) std.log.info("bus reset", .{}); + + // Reset the device + f.bus_reset(); + + // Reset our state. + S.new_address = null; + S.configured = false; + S.started = false; + } + + // If we have been configured but haven't reached this point yet, set up + // our custom EP OUT's to receive whatever data the host wants to send. + if (S.configured and !S.started) { + // We can skip the first two endpoints because those are EP0_OUT and EP0_IN + for (usb_config.?.endpoints[2..]) |ep| { + if (Dir.of_endpoint_addr(ep.descriptor.endpoint_address) == .Out) { + // Hey host! we expect data! + f.usb_start_rx( + ep, + 64, + ); + } + } + S.started = true; + } + } + }; +} + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Data Types +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +// ------------------------- +// | DeviceDescriptor | +// ------------------------- +// | +// v +// ------------------------- +// | ConfigurationDesc | +// ------------------------- +// | +// v +// ------------------------- +// | InterfaceDescriptor | +// ------------------------- +// | | +// v ------------------------------ +// ------------------------- | +// | EndpointDescriptor | v +// ------------------------- --------------------- +// | HID Descriptor | +// --------------------- + +/// Types of USB descriptor +pub const DescType = enum(u8) { + Device = 0x01, + Config = 0x02, + String = 0x03, + Interface = 0x04, + Endpoint = 0x05, + DeviceQualifier = 0x06, + //-------- Class Specific Descriptors ---------- + // 0x21 ... + + pub fn from_u16(v: u16) ?@This() { + return switch (v) { + 1 => @This().Device, + 2 => @This().Config, + 3 => @This().String, + 4 => @This().Interface, + 5 => @This().Endpoint, + 6 => @This().DeviceQualifier, + else => null, + }; + } +}; + +/// Types of transfer that can be indicated by the `attributes` field on +/// `EndpointDescriptor`. +pub const TransferType = enum(u2) { + Control = 0, + Isochronous = 1, + Bulk = 2, + Interrupt = 3, +}; + +/// The types of USB SETUP requests that we understand. +pub const SetupRequest = enum(u8) { + /// Asks the device to send a certain descriptor back to the host. Always + /// used on an IN request. + GetDescriptor = 0x06, + /// Notifies the device that it's being moved to a different address on the + /// bus. Always an OUT. + SetAddress = 0x05, + /// Configures a device by choosing one of the options listed in its + /// descriptors. Always an OUT. + SetConfiguration = 0x09, + + pub fn from_u8(request: u8) ?@This() { + return switch (request) { + 0x06 => SetupRequest.GetDescriptor, + 0x05 => SetupRequest.SetAddress, + 0x09 => SetupRequest.SetConfiguration, + else => null, + }; + } +}; + +/// USB deals in two different transfer directions, called OUT (host-to-device) +/// and IN (device-to-host). In the vast majority of cases, OUT is represented +/// by a 0 byte, and IN by an `0x80` byte. +pub const Dir = enum(u8) { + Out = 0, + In = 0x80, + + pub inline fn endpoint(self: @This(), num: u8) u8 { + return num | @enumToInt(self); + } + + pub inline fn of_endpoint_addr(addr: u8) @This() { + return if (addr & @enumToInt(@This().In) != 0) @This().In else @This().Out; + } +}; + +/// Describes an endpoint within an interface +pub const EndpointDescriptor = packed struct { + /// Length of this struct, must be 7. + length: u8, + /// Type of this descriptor, must be `Endpoint`. + descriptor_type: DescType, + /// Address of this endpoint, where the bottom 4 bits give the endpoint + /// number (0..15) and the top bit distinguishes IN (1) from OUT (0). + endpoint_address: u8, + /// Endpoint attributes; the most relevant part is the bottom 2 bits, which + /// control the transfer type using the values from `TransferType`. + attributes: u8, + /// Maximum packet size this endpoint can accept/produce. + max_packet_size: u16, + /// Interval for polling interrupt/isochronous endpoints (which we don't + /// currently support) in milliseconds. + interval: u8, + + pub fn serialize(self: *const @This()) [7]u8 { + var out: [7]u8 = undefined; + out[0] = 7; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = self.endpoint_address; + out[3] = self.attributes; + out[4] = @intCast(u8, self.max_packet_size & 0xff); + out[5] = @intCast(u8, (self.max_packet_size >> 8) & 0xff); + out[6] = self.interval; + return out; + } +}; + +/// Description of an interface within a configuration. +pub const InterfaceDescriptor = packed struct { + /// Length of this structure, must be 9. + length: u8, + /// Type of this descriptor, must be `Interface`. + descriptor_type: DescType, + /// ID of this interface. + interface_number: u8, + /// Allows a single `interface_number` to have several alternate interface + /// settings, where each alternate increments this field. Normally there's + /// only one, and `alternate_setting` is zero. + alternate_setting: u8, + /// Number of endpoint descriptors in this interface. + num_endpoints: u8, + /// Interface class code, distinguishing the type of interface. + interface_class: u8, + /// Interface subclass code, refining the class of interface. + interface_subclass: u8, + /// Protocol within the interface class/subclass. + interface_protocol: u8, + /// Index of interface name within string descriptor table. + interface_s: u8, + + pub fn serialize(self: *const @This()) [9]u8 { + var out: [9]u8 = undefined; + out[0] = 9; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = self.interface_number; + out[3] = self.alternate_setting; + out[4] = self.num_endpoints; + out[5] = self.interface_class; + out[6] = self.interface_subclass; + out[7] = self.interface_protocol; + out[8] = self.interface_s; + return out; + } +}; + +/// Description of a single available device configuration. +pub const ConfigurationDescriptor = packed struct { + /// Length of this structure, must be 9. + length: u8, + /// Type of this descriptor, must be `Config`. + descriptor_type: DescType, + /// Total length of all descriptors in this configuration, concatenated. + /// This will include this descriptor, plus at least one interface + /// descriptor, plus each interface descriptor's endpoint descriptors. + total_length: u16, + /// Number of interface descriptors in this configuration. + num_interfaces: u8, + /// Number to use when requesting this configuration via a + /// `SetConfiguration` request. + configuration_value: u8, + /// Index of this configuration's name in the string descriptor table. + configuration_s: u8, + /// Bit set of device attributes: + /// + /// - Bit 7 should be set (indicates that device can be bus powered in USB + /// 1.0). + /// - Bit 6 indicates that the device can be self-powered. + /// - Bit 5 indicates that the device can signal remote wakeup of the host + /// (like a keyboard). + /// - The rest are reserved and should be zero. + attributes: u8, + /// Maximum device power consumption in units of 2mA. + max_power: u8, + + pub fn serialize(self: *const @This()) [9]u8 { + var out: [9]u8 = undefined; + out[0] = 9; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = @intCast(u8, self.total_length & 0xff); + out[3] = @intCast(u8, (self.total_length >> 8) & 0xff); + out[4] = self.num_interfaces; + out[5] = self.configuration_value; + out[6] = self.configuration_s; + out[7] = self.attributes; + out[8] = self.max_power; + return out; + } +}; + +/// Describes a device. This is the most broad description in USB and is +/// typically the first thing the host asks for. +pub const DeviceDescriptor = packed struct { + /// Length of this structure, must be 18. + length: u8, + /// Type of this descriptor, must be `Device`. + descriptor_type: DescType, + /// Version of the device descriptor / USB protocol, in binary-coded + /// decimal. This is typically `0x01_10` for USB 1.1. + bcd_usb: u16, + /// Class of device, giving a broad functional area. + device_class: u8, + /// Subclass of device, refining the class. + device_subclass: u8, + /// Protocol within the subclass. + device_protocol: u8, + /// Maximum unit of data this device can move. + max_packet_size0: u8, + /// ID of product vendor. + vendor: u16, + /// ID of product. + product: u16, + /// Device version number, as BCD again. + bcd_device: u16, + /// Index of manufacturer name in string descriptor table. + manufacturer_s: u8, + /// Index of product name in string descriptor table. + product_s: u8, + /// Index of serial number in string descriptor table. + serial_s: u8, + /// Number of configurations supported by this device. + num_configurations: u8, + + pub fn serialize(self: *const @This()) [18]u8 { + var out: [18]u8 = undefined; + out[0] = 18; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = @intCast(u8, self.bcd_usb & 0xff); + out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); + out[4] = self.device_class; + out[5] = self.device_subclass; + out[6] = self.device_protocol; + out[7] = self.max_packet_size0; + out[8] = @intCast(u8, self.vendor & 0xff); + out[9] = @intCast(u8, (self.vendor >> 8) & 0xff); + out[10] = @intCast(u8, self.product & 0xff); + out[11] = @intCast(u8, (self.product >> 8) & 0xff); + out[12] = @intCast(u8, self.bcd_device & 0xff); + out[13] = @intCast(u8, (self.bcd_device >> 8) & 0xff); + out[14] = self.manufacturer_s; + out[15] = self.product_s; + out[16] = self.serial_s; + out[17] = self.num_configurations; + return out; + } +}; + +/// USB Device Qualifier Descriptor +/// This descriptor is mostly the same as the DeviceDescriptor +pub const DeviceQualifierDescriptor = packed struct { + /// Length of this structure, must be 18. + length: u8 = 10, + /// Type of this descriptor, must be `Device`. + descriptor_type: DescType = DescType.DeviceQualifier, + /// Version of the device descriptor / USB protocol, in binary-coded + /// decimal. This is typically `0x01_10` for USB 1.1. + bcd_usb: u16, + /// Class of device, giving a broad functional area. + device_class: u8, + /// Subclass of device, refining the class. + device_subclass: u8, + /// Protocol within the subclass. + device_protocol: u8, + /// Maximum unit of data this device can move. + max_packet_size0: u8, + /// Number of configurations supported by this device. + num_configurations: u8, + /// Reserved for future use; must be 0 + reserved: u8 = 0, + + pub fn serialize(self: *const @This()) [10]u8 { + var out: [10]u8 = undefined; + out[0] = 10; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = @intCast(u8, self.bcd_usb & 0xff); + out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); + out[4] = self.device_class; + out[5] = self.device_subclass; + out[6] = self.device_protocol; + out[7] = self.max_packet_size0; + out[8] = self.num_configurations; + out[9] = self.reserved; + return out; + } +}; + +/// Layout of an 8-byte USB SETUP packet. +pub const SetupPacket = packed struct { + /// Request type; in practice, this is always either OUT (host-to-device) or + /// IN (device-to-host), whose values are given in the `Dir` enum. + request_type: u8, + /// Request. Standard setup requests are in the `SetupRequest` enum. + /// Devices can extend this with additional types as long as they don't + /// conflict. + request: u8, + /// A simple argument of up to 16 bits, specific to the request. + value: u16, + /// Not used in the requests we support. + index: u16, + /// If data will be transferred after this request (in the direction given + /// by `request_type`), this gives the number of bytes (OUT) or maximum + /// number of bytes (IN). + length: u16, +}; + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Driver support stuctures +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +pub const EndpointConfiguration = struct { + descriptor: *const EndpointDescriptor, + /// Index of this endpoint's control register in the `ep_control` array. + /// + /// TODO: this can be derived from the endpoint address, perhaps it should + /// be. + endpoint_control_index: ?usize, + /// Index of this endpoint's buffer control register in the + /// `ep_buffer_control` array. + /// + /// TODO this, too, can be derived. + buffer_control_index: usize, + + /// Index of this endpoint's data buffer in the array of data buffers + /// allocated from DPRAM. This can be arbitrary, and endpoints can even + /// share buffers if you're careful. + data_buffer_index: usize, + + /// Keeps track of which DATA PID (DATA0/DATA1) is expected on this endpoint + /// next. If `true`, we're expecting `DATA1`, otherwise `DATA0`. + next_pid_1: bool, + + /// Optional callback for custom OUT endpoints. This function will be called + /// if the device receives data on the corresponding endpoint. + callback: ?*const fn (dc: *DeviceConfiguration, data: []const u8) void = null, +}; + +pub const DeviceConfiguration = struct { + device_descriptor: *const DeviceDescriptor, + interface_descriptor: *const InterfaceDescriptor, + config_descriptor: *const ConfigurationDescriptor, + lang_descriptor: []const u8, + descriptor_strings: []const []const u8, + hid: ?struct { + hid_descriptor: *const hid.HidDescriptor, + report_descriptor: []const u8, + } = null, + endpoints: [4]*EndpointConfiguration, +}; + +/// Buffer pointers, once they're prepared and initialized. +pub const Buffers = struct { + /// Fixed EP0 Buffer0, defined by the hardware + ep0_buffer0: [*]u8, + /// Fixed EP0 Buffer1, defined by the hardware and NOT USED in this driver + ep0_buffer1: [*]u8, + /// /// Remaining buffer pool + rest: [16][*]u8, + + /// Gets a buffer corresponding to a `data_buffer_index` in a + /// `EndpointConfiguration`. + pub fn get(self: *@This(), i: usize) [*]u8 { + return switch (i) { + 0 => self.ep0_buffer0, + 1 => self.ep0_buffer1, + else => self.rest[i - 2], + }; + } +}; + +// Handy constants for the endpoints we use here +pub const EP0_IN_ADDR: u8 = Dir.In.endpoint(0); +pub const EP0_OUT_ADDR: u8 = Dir.Out.endpoint(0); +const EP1_OUT_ADDR: u8 = Dir.Out.endpoint(1); +const EP1_IN_ADDR: u8 = Dir.In.endpoint(1); +const EP2_IN_ADDR: u8 = Dir.In.endpoint(2); + +/// USB interrupt status +/// +/// __Note__: Available interrupts may change from device to device. +pub const InterruptStatus = struct { + /// Host: raised every time the host sends a SOF (Start of Frame) + BuffStatus: bool = false, + BusReset: bool = false, + /// Set when the device connection state changes + DevConnDis: bool = false, + /// Set when the device suspend state changes + DevSuspend: bool = false, + /// Set when the device receives a resume from the host + DevResumeFromHost: bool = false, + /// Setup Request + SetupReq: bool = false, +}; + +pub const EPBError = error{ + /// The system has received a buffer event for an unknown endpoint (this is super unlikely) + UnknownEndpoint, + /// The buffer is not available (this is super unlikely) + NotAvailable, +}; + +/// Element returned by the endpoint buffer iterator (EPBIter) +pub const EPB = struct { + /// The endpoint the data belongs to + endpoint: *EndpointConfiguration, + /// Data buffer + buffer: []u8, +}; + +/// Iterator over all input buffers that hold data +pub const EPBIter = struct { + /// Bitmask of the input buffers to handle + bufbits: u32, + /// The last input buffer handled. This can be used to flag the input buffer as handled on the + /// next call. + last_bit: ?u32 = null, + /// Point to the device configuration (to get access to the endpoint buffers defined by the user) + device_config: *const DeviceConfiguration, + /// Get the next available input buffer + next: *const fn (self: *@This()) ?EPB, +}; + +/// Convert an utf8 into an utf16 (little endian) string +pub fn utf8Toutf16Le(comptime s: []const u8) [s.len << 1]u8 { + const l = s.len << 1; + var ret: [l]u8 = .{0} ** l; + var i: usize = 0; + while (i < s.len) : (i += 1) { + ret[i << 1] = s[i]; + } + return ret; +} + +test "tests" { + _ = hid; +} + +test "utf8 to utf16" { + try std.testing.expectEqualSlices(u8, "M\x00y\x00 \x00V\x00e\x00n\x00d\x00o\x00r\x00", &utf8Toutf16Le("My Vendor")); + try std.testing.expectEqualSlices(u8, "R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00", &utf8Toutf16Le("Raspberry Pi")); +} diff --git a/src/core/usb/hid.zig b/src/core/usb/hid.zig new file mode 100644 index 0000000..4993f6c --- /dev/null +++ b/src/core/usb/hid.zig @@ -0,0 +1,458 @@ +//! USB HID +//! +//! ## Interfaces +//! +//! HID class devices use Control and Interrupt pipes for communication +//! +//! 1. Control for USB control and data classes, reports, data from host +//! 2. Interrupt for asynchronous and low latency data to the device +//! +//! ## Settings +//! +//! ### UsbInterfaceDescriptor related settings: +//! The class type for a HID class device is defined by the Interface descriptor. +//! The subclass field is used to identify Boot Devices. +//! +//! * `interface_subclass` - 1 if boot interface, 0 else (most of the time) +//! * `interface_protocol` - 0 if no boot interface, 1 if keyboard boot interface, 2 if mouse BI +//! +//! ## Nice to know +//! +//! The host usually won't ask for the HID descriptor even if the other descriptors +//! indicate that the given device is a HID device, i. e., you should just pass the +//! HID descriptor together with the configuration descriptor. +//! +//! ## Descriptors +//! +//! ### Report +//! +//! A Report descriptor describes each piece of data that the device generates +//! and what the data is actually measuring (e.g., position or button state). The +//! descriptor consists of one or more items and answers the following questions: +//! +//! 1. Where should the input be routed to (e.g., mouse or joystick API)? +//! 2. Should the software assign a functionality to the input? +//! +//! ### Physical +//! +//! ... +//! +//! ### HID +//! +//! The HID descriptor identifies the length and type of subordinate descriptors for device. + +const std = @import("std"); + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Common Data Types +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +// ... +// | +// v +// ------------------------- +// | InterfaceDescriptor | +// ------------------------- +// | | +// | ----------------- +// | | +// v v +// ... -------------------------- +// | HidDescriptor | +// -------------------------- +// | | +// ------ -------- +// | | +// v v +// ----------------------- --------------------- +// | ReportDescriptor | | PhysicalDesc | +// ----------------------- --------------------- + +pub const DescType = enum(u8) { + /// HID descriptor + Hid = 0x21, + /// Report descriptor + Report = 0x22, + /// Physical descriptor + Physical = 0x23, + + pub fn from_u16(v: u16) ?@This() { + return switch (v) { + 0x21 => @This().Hid, + 0x22 => @This().Report, + 0x23 => @This().Physical, + else => null, + }; + } +}; + +/// USB HID descriptor +pub const HidDescriptor = packed struct { + length: u8 = 9, + descriptor_type: DescType = DescType.Hid, + /// Numeric expression identifying the HID Class Specification release + bcd_hid: u16, + /// Numeric expression identifying country code of the localized hardware + country_code: u8, + /// Numeric expression specifying the number of class descriptors + num_descriptors: u8, + /// Type of HID class report + report_type: DescType = DescType.Report, + /// The total size of the Report descriptor + report_length: u16, + + pub fn serialize(self: *const @This()) [9]u8 { + var out: [9]u8 = undefined; + out[0] = 9; // length + out[1] = @enumToInt(self.descriptor_type); + out[2] = @intCast(u8, self.bcd_hid & 0xff); + out[3] = @intCast(u8, (self.bcd_hid >> 8) & 0xff); + out[4] = self.country_code; + out[5] = self.num_descriptors; + out[6] = @enumToInt(self.report_type); + out[7] = @intCast(u8, self.report_length & 0xff); + out[8] = @intCast(u8, (self.report_length >> 8) & 0xff); + return out; + } +}; + +/// HID interface Subclass (for UsbInterfaceDescriptor) +pub const Subclass = enum(u8) { + /// No Subclass + None = 0, + /// Boot Interface Subclass + Boot = 1, +}; + +/// HID interface protocol +pub const Protocol = enum(u8) { + /// No protocol + None = 0, + /// Keyboard (only if boot interface) + Keyboard = 1, + /// Mouse (only if boot interface) + Mouse = 2, +}; + +/// HID request report type +pub const ReportType = enum(u8) { + Invalid = 0, + Input = 1, + Output = 2, + Feature = 3, +}; + +/// HID class specific control request +pub const Request = enum(u8) { + GetReport = 0x01, + GetIdle = 0x02, + GetProtocol = 0x03, + SetReport = 0x09, + SetIdle = 0x0a, + SetProtocol = 0x0b, +}; + +/// HID country codes +pub const CountryCode = enum(u8) { + NotSupported = 0, + Arabic, + Belgian, + CanadianBilingual, + CanadianFrench, + CzechRepublic, + Danish, + Finnish, + French, + German, + Greek, + Hebrew, + Hungary, + International, + Italian, + JapanKatakana, + Korean, + LatinAmerica, + NetherlandsDutch, + Norwegian, + PersianFarsi, + Poland, + Portuguese, + Russia, + Slovakia, + Spanish, + Swedish, + SwissFrench, + SwissGerman, + Switzerland, + Taiwan, + TurkishQ, + Uk, + Us, + Yugoslavia, + TurkishF, +}; + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Report Descriptor Data Types +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +pub const ReportItemTypes = enum(u2) { + Main = 0, + Global = 1, + Local = 2, +}; + +pub const ReportItemMainGroup = enum(u4) { + Input = 8, + Output = 9, + Collection = 10, + Feature = 11, + CollectionEnd = 12, +}; + +pub const CollectionItem = enum(u8) { + Physical = 0, + Application, + Logical, + Report, + NamedArray, + UsageSwitch, + UsageModifier, +}; + +pub const GlobalItem = enum(u4) { + UsagePage = 0, + LogicalMin = 1, + LogicalMax = 2, + PhysicalMin = 3, + PhysicalMax = 4, + UnitExponent = 5, + Unit = 6, + ReportSize = 7, + ReportId = 8, + ReportCount = 9, + Push = 10, + Pop = 11, +}; + +pub const LocalItem = enum(u4) { + Usage = 0, + UsageMin = 1, + UsageMax = 2, + DesignatorIndex = 3, + DesignatorMin = 4, + DesignatorMax = 5, + StringIndex = 7, + StringMin = 8, + StringMax = 9, + Delimiter = 10, +}; + +pub const UsageTable = struct { + const fido: [2]u8 = "\xD0\xF1".*; +}; + +pub const FidoAllianceUsage = struct { + const u2fhid: [1]u8 = "\x01".*; + const data_in: [1]u8 = "\x20".*; + const data_out: [1]u8 = "\x21".*; +}; + +const HID_DATA: u8 = 0 << 0; +const HID_CONSTANT: u8 = 1 << 0; + +const HID_ARRAY = 0 << 1; +const HID_VARIABLE = 1 << 1; + +const HID_ABSOLUTE = 0 << 2; +const HID_RELATIVE = 1 << 2; + +const HID_WRAP_NO = 0 << 3; +const HID_WRAP = 1 << 3; + +const HID_LINEAR = 0 << 4; +const HID_NONLINEAR = 1 << 4; + +const HID_PREFERRED_STATE = 0 << 5; +const HID_PREFERRED_NO = 1 << 5; + +const HID_NO_NULL_POSITION = 0 << 6; +const HID_NULL_STATE = 1 << 6; + +const HID_NON_VOLATILE = 0 << 7; +const HID_VOLATILE = 1 << 7; + +const HID_BITFIELD = 0 << 8; +const HID_BUFFERED_BYTES = 1 << 8; + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Report Descriptor Functions +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +pub fn hid_report_item( + comptime n: u2, + typ: u2, + tag: u4, + data: [n]u8, +) [n + 1]u8 { + var out: [n + 1]u8 = undefined; + + out[0] = (@intCast(u8, tag) << 4) | (@intCast(u8, typ) << 2) | n; + + var i: usize = 0; + while (i < n) : (i += 1) { + out[i + 1] = data[i]; + } + + return out; +} + +// Main Items +// ------------------------------------------------- + +pub fn hid_collection(data: CollectionItem) [2]u8 { + return hid_report_item( + 1, + @enumToInt(ReportItemTypes.Main), + @enumToInt(ReportItemMainGroup.Collection), + std.mem.toBytes(@enumToInt(data)), + ); +} + +pub fn hid_input(data: u8) [2]u8 { + return hid_report_item( + 1, + @enumToInt(ReportItemTypes.Main), + @enumToInt(ReportItemMainGroup.Input), + std.mem.toBytes(data), + ); +} + +pub fn hid_output(data: u8) [2]u8 { + return hid_report_item( + 1, + @enumToInt(ReportItemTypes.Main), + @enumToInt(ReportItemMainGroup.Output), + std.mem.toBytes(data), + ); +} + +pub fn hid_collection_end() [1]u8 { + return hid_report_item( + 0, + @enumToInt(ReportItemTypes.Main), + @enumToInt(ReportItemMainGroup.CollectionEnd), + .{}, + ); +} + +// Global Items +// ------------------------------------------------- + +pub fn hid_usage_page(comptime n: u2, usage: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Global), + @enumToInt(GlobalItem.UsagePage), + usage, + ); +} + +pub fn hid_logical_min(comptime n: u2, data: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Global), + @enumToInt(GlobalItem.LogicalMin), + data, + ); +} + +pub fn hid_logical_max(comptime n: u2, data: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Global), + @enumToInt(GlobalItem.LogicalMax), + data, + ); +} + +pub fn hid_report_size(comptime n: u2, data: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Global), + @enumToInt(GlobalItem.ReportSize), + data, + ); +} + +pub fn hid_report_count(comptime n: u2, data: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Global), + @enumToInt(GlobalItem.ReportCount), + data, + ); +} + +// Local Items +// ------------------------------------------------- + +pub fn hid_usage(comptime n: u2, data: [n]u8) [n + 1]u8 { + return hid_report_item( + n, + @enumToInt(ReportItemTypes.Local), + @enumToInt(LocalItem.Usage), + data, + ); +} + +// +++++++++++++++++++++++++++++++++++++++++++++++++ +// Report Descriptors +// +++++++++++++++++++++++++++++++++++++++++++++++++ + +pub const ReportDescriptorFidoU2f = hid_usage_page(2, UsageTable.fido) // +++ hid_usage(1, FidoAllianceUsage.u2fhid) // +++ hid_collection(CollectionItem.Application) // +// Usage Data In +++ hid_usage(1, FidoAllianceUsage.data_in) // +++ hid_logical_min(1, "\x00".*) // +++ hid_logical_max(2, "\xff\x00".*) // +++ hid_report_size(1, "\x08".*) // +++ hid_report_count(1, "\x40".*) // +++ hid_input(HID_DATA | HID_VARIABLE | HID_ABSOLUTE) // +// Usage Data Out +++ hid_usage(1, FidoAllianceUsage.data_out) // +++ hid_logical_min(1, "\x00".*) // +++ hid_logical_max(2, "\xff\x00".*) // +++ hid_report_size(1, "\x08".*) // +++ hid_report_count(1, "\x40".*) // +++ hid_output(HID_DATA | HID_VARIABLE | HID_ABSOLUTE) // +// End +++ hid_collection_end(); + +test "create hid report item" { + const r = hid_report_item( + 2, + 0, + 3, + "\x22\x11".*, + ); + + try std.testing.expectEqual(@intCast(usize, 3), r.len); + try std.testing.expectEqual(@intCast(u8, 50), r[0]); + try std.testing.expectEqual(@intCast(u8, 0x22), r[1]); + try std.testing.expectEqual(@intCast(u8, 0x11), r[2]); +} + +test "create hid fido usage page" { + const f = hid_usage_page(2, UsageTable.fido); + + try std.testing.expectEqual(@intCast(usize, 3), f.len); + try std.testing.expectEqual(@intCast(u8, 6), f[0]); + try std.testing.expectEqual(@intCast(u8, 0xd0), f[1]); + try std.testing.expectEqual(@intCast(u8, 0xf1), f[2]); +} + +test "report descriptor fido" { + _ = ReportDescriptorFidoU2f; +} From 658648b86ba63762ac45665abe0a06ec279225b1 Mon Sep 17 00:00:00 2001 From: Philipp Wendel <41269321+PhilippWendel@users.noreply.github.com> Date: Tue, 25 Apr 2023 16:55:53 +0200 Subject: [PATCH 116/138] Updated code to regz rewrite and added fix for i2c on ATmega328P (#125) --- README.adoc | 2 +- src/core/experimental/clock.zig | 35 ++++++++++++++++++--------------- src/core/experimental/debug.zig | 9 +++++---- src/core/experimental/i2c.zig | 7 ++++--- src/core/experimental/uart.zig | 14 ++++++------- 5 files changed, 36 insertions(+), 31 deletions(-) diff --git a/README.adoc b/README.adoc index a71c160..bae9b60 100644 --- a/README.adoc +++ b/README.adoc @@ -62,7 +62,7 @@ pub fn build(b: *std.build.Builder) !void { }, .optimize = optimize, }); - exe.install(); + exe.installArtifact(b); } ---- diff --git a/src/core/experimental/clock.zig b/src/core/experimental/clock.zig index f0d5df2..8c51b1f 100644 --- a/src/core/experimental/clock.zig +++ b/src/core/experimental/clock.zig @@ -1,18 +1,21 @@ const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("chip"); +const hal = @import("hal"); +const app = struct {}; // workaround for error: no package named 'app' available within package 'root.microzig' +const board = @import("board"); +const cpu = @import("cpu"); +const config = @import("config"); /// An enumeration of clock sources. pub const Source = enum { none, application, board, - chip, + hal, cpu, }; /// A struct containing the frequency in hertz for each clock domain -pub const Clocks = std.enums.EnumFieldStruct(chip.clock.Domain, u32, null); +pub const Clocks = std.enums.EnumFieldStruct(hal.clock.Domain, u32, null); /// Is `true` when microzig has a clock frequency available. /// Clock can be provided by several clock sources @@ -23,10 +26,10 @@ pub const is_dynamic = has_clock and !@typeInfo(@TypeOf(&@field(clock_source_typ /// Contains the source which provides microzig with clock information. pub const source: Source = switch (clock_source_type) { - micro.app => .application, - micro.board => .board, - micro.chip => .chip, - micro.cpu => .cpu, + app => .application, + board => .board, + hal => .hal, + cpu => .cpu, no_clock_source_type => .none, else => unreachable, }; @@ -46,14 +49,14 @@ pub inline fn get() Clocks { const freq_decl_name = "clock_frequencies"; const no_clock_source_type = opaque {}; -const clock_source_type = if (@hasDecl(micro.app, freq_decl_name)) - micro.app -else if (micro.config.has_board and @hasDecl(micro.board, freq_decl_name)) - micro.board -else if (@hasDecl(micro.chip, freq_decl_name)) - micro.chip -else if (@hasDecl(micro.cpu, freq_decl_name)) - micro.cpu +const clock_source_type = if (@hasDecl(app, freq_decl_name)) + app +else if (config.has_board and @hasDecl(board, freq_decl_name)) + board +else if (@hasDecl(hal, freq_decl_name)) + hal +else if (@hasDecl(cpu, freq_decl_name)) + cpu else no_clock_source_type; diff --git a/src/core/experimental/debug.zig b/src/core/experimental/debug.zig index e3cee22..c74bdba 100644 --- a/src/core/experimental/debug.zig +++ b/src/core/experimental/debug.zig @@ -1,5 +1,6 @@ const std = @import("std"); -const micro = @import("microzig"); +const config = @import("config"); +const board = @import("board"); pub fn busy_sleep(comptime limit: comptime_int) void { if (limit <= 0) @compileError("limit must be non-negative!"); @@ -27,12 +28,12 @@ fn writer_write(ctx: void, string: []const u8) DebugErr!usize { const DebugWriter = std.io.Writer(void, DebugErr, writer_write); pub fn write(string: []const u8) void { - if (!micro.config.has_board) + if (!config.has_board) return; - if (!@hasDecl(micro.board, "debugWrite")) + if (!@hasDecl(board, "debugWrite")) return; - micro.board.debug_write(string); + board.debug_write(string); } pub fn writer() DebugWriter { diff --git a/src/core/experimental/i2c.zig b/src/core/experimental/i2c.zig index 20b0f61..7eefcbd 100644 --- a/src/core/experimental/i2c.zig +++ b/src/core/experimental/i2c.zig @@ -1,9 +1,9 @@ const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("chip"); +const hal = @import("hal"); +const cfg = @import("config"); pub fn I2CController(comptime index: usize, comptime pins: Pins) type { - const SystemI2CController = chip.I2CController(index, pins); + const SystemI2CController = hal.I2CController(index, pins); const I2CDevice = struct { const Device = @This(); @@ -128,6 +128,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { const Self = @This(); internal: SystemI2CController, + variable_so_struct_is_not_of_size_zero_and_mcu_hangs_when_returning_struct_on_avr: if (std.mem.eql(u8, cfg.chip_name, "ATmega328P")) u8 else void = undefined, pub fn init(config: Config) InitError!Self { return Self{ diff --git a/src/core/experimental/uart.zig b/src/core/experimental/uart.zig index b9c385c..bba29da 100644 --- a/src/core/experimental/uart.zig +++ b/src/core/experimental/uart.zig @@ -1,9 +1,9 @@ const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("chip"); +const hal = @import("hal"); +const clock = @import("clock.zig"); pub fn Uart(comptime index: usize, comptime pins: Pins) type { - const SystemUart = chip.Uart(index, pins); + const SystemUart = hal.Uart(index, pins); return struct { const Self = @This(); @@ -11,7 +11,7 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type { /// Initializes the UART with the given config and returns a handle to the uart. pub fn init(config: Config) InitError!Self { - micro.clock.ensure(); + clock.ensure(); return Self{ .internal = try SystemUart.init(config), }; @@ -81,9 +81,9 @@ pub const Config = struct { }; // TODO: comptime verify that the enums are valid -pub const DataBits = chip.uart.DataBits; -pub const StopBits = chip.uart.StopBits; -pub const Parity = chip.uart.Parity; +pub const DataBits = hal.uart.DataBits; +pub const StopBits = hal.uart.StopBits; +pub const Parity = hal.uart.Parity; pub const InitError = error{ UnsupportedWordSize, From d1f1374c089f9ce6e85f63223c5b954459052320 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 26 Apr 2023 00:09:45 -0700 Subject: [PATCH 117/138] rename disable/enable interrupt functions (#126) --- src/interrupt.zig | 12 ++++++------ src/microzig.zig | 3 +-- src/modules/cpus/cortex-m.zig | 4 ++-- test/cpu.zig | 3 ++- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/interrupt.zig b/src/interrupt.zig index b08e8df..1be5c91 100644 --- a/src/interrupt.zig +++ b/src/interrupt.zig @@ -22,14 +22,14 @@ pub fn is_enabled(comptime interrupt: anytype) bool { /// *Set Enable Interrupt*, will enable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. -pub fn sei() void { - micro.cpu.sei(); +pub fn enable_interrupts() void { + micro.cpu.enable_interrupts(); } /// *Clear Enable Interrupt*, will disable IRQs globally, but keep the masking done via /// `enable` and `disable` intact. -pub fn cli() void { - micro.cpu.cli(); +pub fn disable_interrupts() void { + micro.cpu.disable_interrupts(); } /// Returns true, when interrupts are globally enabled via `sei()`. @@ -43,7 +43,7 @@ pub fn enter_critical_section() CriticalSection { var section = CriticalSection{ .enable_on_leave = globally_enabled(), }; - cli(); + disable_interrupts(); return section; } @@ -55,7 +55,7 @@ const CriticalSection = struct { /// Leaves the critical section and restores the interrupt state. pub fn leave(self: @This()) void { if (self.enable_on_leave) { - sei(); + enable_interrupts(); } } }; diff --git a/src/microzig.zig b/src/microzig.zig index a40ea53..348889c 100644 --- a/src/microzig.zig +++ b/src/microzig.zig @@ -63,9 +63,8 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu /// Hangs the processor and will stop doing anything useful. Use with caution! pub fn hang() noreturn { + cpu.disable_interrupts(); while (true) { - interrupt.cli(); - // "this loop has side effects, don't optimize the endless loop away please. thanks!" asm volatile ("" ::: "memory"); } diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index 5b9715f..33eb3d2 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -27,11 +27,11 @@ pub fn executing_isr() bool { return regs.ICSR.read().VECTACTIVE != 0; } -pub fn sei() void { +pub fn enable_interrupts() void { asm volatile ("cpsie i"); } -pub fn cli() void { +pub fn disable_interrupts() void { asm volatile ("cpsid i"); } diff --git a/test/cpu.zig b/test/cpu.zig index 7892a04..43dee20 100644 --- a/test/cpu.zig +++ b/test/cpu.zig @@ -1,3 +1,4 @@ pub const startup_logic = struct {}; -pub fn cli() void {} +pub fn enable_interrupts() void {} +pub fn disable_interrupts() void {} From b5edf6da6b540215f03689c3cc07d00478255f7d Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 26 Apr 2023 00:25:08 -0700 Subject: [PATCH 118/138] interrupt enable/disable for riscv and air (#127) * rename disable/enable interrupt functions * enable/disable interrupt functions for avr and riscv * add todo panic --- src/modules/cpus/avr5.zig | 4 ++-- src/modules/cpus/riscv32.zig | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/modules/cpus/avr5.zig b/src/modules/cpus/avr5.zig index b24e7cb..c0059ba 100644 --- a/src/modules/cpus/avr5.zig +++ b/src/modules/cpus/avr5.zig @@ -2,11 +2,11 @@ const std = @import("std"); const microzig = @import("microzig"); const root = @import("root"); -pub inline fn sei() void { +pub fn enable_interrupts() void { asm volatile ("sei"); } -pub inline fn cli() void { +pub fn disable_interrupts() void { asm volatile ("cli"); } diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index 200b554..740f611 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -2,11 +2,13 @@ const std = @import("std"); const root = @import("root"); const microzig = @import("microzig"); -pub fn sei() void { +pub fn enable_interrupts() void { + @panic("TODO"); // asm volatile ("sei"); } -pub fn cli() void { +pub fn disable_interrupts() void { + @panic("TODO"); // asm volatile ("cli"); } From 4e62e99e3cf8ad2b8805bc6138c53995bd9745be Mon Sep 17 00:00:00 2001 From: binarycraft007 <107379182+binarycraft007@users.noreply.github.com> Date: Thu, 4 May 2023 12:36:50 +0800 Subject: [PATCH 119/138] update to zig master: use @memset, @memcpy builtin (#128) Co-authored-by: Binary Craft --- src/core/usb.zig | 16 ++++++++-------- src/modules/cpus/cortex-m.zig | 4 ++-- src/modules/cpus/riscv32.zig | 4 ++-- src/start.zig | 4 ++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/core/usb.zig b/src/core/usb.zig index bfb886c..7e2d183 100644 --- a/src/core/usb.zig +++ b/src/core/usb.zig @@ -157,7 +157,7 @@ pub fn Usb(comptime f: anytype) type { usb_config.?.endpoints[EP0_IN_IDX].next_pid_1 = true; const dc = usb_config.?.device_descriptor.serialize(); - std.mem.copy(u8, S.tmp[0..dc.len], &dc); + @memcpy(S.tmp[0..dc.len], &dc); // Configure EP0 IN to send the device descriptor // when it's next asked. @@ -178,7 +178,7 @@ pub fn Usb(comptime f: anytype) type { var used: usize = 0; const cd = usb_config.?.config_descriptor.serialize(); - std.mem.copy(u8, S.tmp[used .. used + cd.len], &cd); + @memcpy(S.tmp[used .. used + cd.len], &cd); used += cd.len; if (setup.length > used) { @@ -192,7 +192,7 @@ pub fn Usb(comptime f: anytype) type { // (1) the exact size of a config descriptor, or // (2) 64 bytes, and this all fits in 64 bytes. const id = usb_config.?.interface_descriptor.serialize(); - std.mem.copy(u8, S.tmp[used .. used + id.len], &id); + @memcpy(S.tmp[used .. used + id.len], &id); used += id.len; // Seems like the host does not bother asking for the @@ -200,7 +200,7 @@ pub fn Usb(comptime f: anytype) type { // other descriptors. if (usb_config.?.hid) |hid_conf| { const hd = hid_conf.hid_descriptor.serialize(); - std.mem.copy(u8, S.tmp[used .. used + hd.len], &hd); + @memcpy(S.tmp[used .. used + hd.len], &hd); used += hd.len; } @@ -209,7 +209,7 @@ pub fn Usb(comptime f: anytype) type { // into multiple packets for (usb_config.?.endpoints[2..]) |ep| { const ed = ep.descriptor.serialize(); - std.mem.copy(u8, S.tmp[used .. used + ed.len], &ed); + @memcpy(S.tmp[used .. used + ed.len], &ed); used += ed.len; } } @@ -237,7 +237,7 @@ pub fn Usb(comptime f: anytype) type { S.tmp[0] = @intCast(u8, len); S.tmp[1] = 0x03; - std.mem.copy(u8, S.tmp[2..len], s); + @memcpy(S.tmp[2..len], s); break :StringBlk S.tmp[0..len]; } @@ -279,7 +279,7 @@ pub fn Usb(comptime f: anytype) type { }; const data = dqd.serialize(); - std.mem.copy(u8, S.tmp[0..data.len], &data); + @memcpy(S.tmp[0..data.len], &data); f.usb_start_tx( usb_config.?.endpoints[EP0_IN_IDX], @@ -299,7 +299,7 @@ pub fn Usb(comptime f: anytype) type { if (debug) std.log.info(" HID", .{}); const hd = hid_conf.hid_descriptor.serialize(); - std.mem.copy(u8, S.tmp[0..hd.len], &hd); + @memcpy(S.tmp[0..hd.len], &hd); f.usb_start_tx( usb_config.?.endpoints[EP0_IN_IDX], diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index 33eb3d2..f6f92bc 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -84,7 +84,7 @@ pub const startup_logic = struct { const bss_end = @ptrCast([*]u8, µzig_bss_end); const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - std.mem.set(u8, bss_start[0..bss_len], 0); + @memset(bss_start[0..bss_len], 0); } // load .data from flash @@ -94,7 +94,7 @@ pub const startup_logic = struct { const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); const data_src = @ptrCast([*]const u8, µzig_data_load_start); - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + @memcpy(data_start[0..data_len], data_src[0..data_len]); } microzig_main(); diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index 740f611..d788df0 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -61,7 +61,7 @@ pub const startup_logic = struct { const bss_end = @ptrCast([*]u8, µzig_bss_end); const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - std.mem.set(u8, bss_start[0..bss_len], 0); + @memset(bss_start[0..bss_len], 0); } // load .data from flash @@ -71,7 +71,7 @@ pub const startup_logic = struct { const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); const data_src = @ptrCast([*]const u8, µzig_data_load_start); - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + @memcpy(data_start[0..data_len], data_src[0..data_len]); } microzig_main(); diff --git a/src/start.zig b/src/start.zig index 42a76f1..97c6dc1 100644 --- a/src/start.zig +++ b/src/start.zig @@ -143,7 +143,7 @@ pub fn initialize_system_memories() void { const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); - std.mem.set(u8, bss_start[0..bss_len], 0); + @memset(bss_start[0..bss_len], 0); } // load .data from flash @@ -153,6 +153,6 @@ pub fn initialize_system_memories() void { const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); - std.mem.copy(u8, data_start[0..data_len], data_src[0..data_len]); + @memcpy(data_start[0..data_len], data_src[0..data_len]); } } From 95889419155b7ffb1b11055549540096eaa2a6c5 Mon Sep 17 00:00:00 2001 From: Nicolas Goy Date: Tue, 16 May 2023 06:32:26 +0200 Subject: [PATCH 120/138] When adding an option, set it as app module dependency to make it available in the app root (#129) --- build.zig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/build.zig b/build.zig index 86231e9..55e2ac8 100644 --- a/build.zig +++ b/build.zig @@ -63,6 +63,9 @@ pub const EmbeddedExecutable = struct { pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *std.build.OptionsStep) void { exe.inner.addOptions(module_name, options); + const app_module = exe.inner.modules.get("app").?; + const opt_module = exe.inner.modules.get(module_name).?; + app_module.dependencies.put(module_name, opt_module) catch @panic("OOM"); } pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { From 3f8dd68f0dab8119e7e40bf21858a3034d432efa Mon Sep 17 00:00:00 2001 From: Pavel Burgr Date: Sat, 3 Jun 2023 15:52:07 +0200 Subject: [PATCH 121/138] Fix @call parameter for zig 0.11 (#130) --- src/modules/cpus/avr5.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/modules/cpus/avr5.zig b/src/modules/cpus/avr5.zig index c0059ba..117a70f 100644 --- a/src/modules/cpus/avr5.zig +++ b/src/modules/cpus/avr5.zig @@ -91,7 +91,7 @@ fn make_isr_handler(comptime name: []const u8, comptime func: anytype) type { pub const exported_name = "microzig_isr_" ++ name; pub fn isr_vector() callconv(.Signal) void { - @call(.{ .modifier = .always_inline }, func, .{}); + @call(.always_inline, func, .{}); } comptime { From 39bf0b5d555b7d22febcf450efeb22baff03146a Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 3 Jun 2023 08:06:03 -0700 Subject: [PATCH 122/138] update pr creation step (#131) --- .github/workflows/auto-pr.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml index 850958c..fc80d70 100644 --- a/.github/workflows/auto-pr.yml +++ b/.github/workflows/auto-pr.yml @@ -36,7 +36,7 @@ jobs: echo "DESCRIPTION=$(git log -1 --pretty=%B | head -n 1)" >> $GITHUB_OUTPUT - name: Create Pull Request - uses: peter-evans/create-pull-request@v4.2.3 + uses: peter-evans/create-pull-request@v5.0.1 with: token: ${{ secrets.PR_TOKEN }} branch: downstream/update-microzig From a49fad973077dffd5fa0b392720295ad033f076e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Sun, 25 Jun 2023 20:03:59 +0200 Subject: [PATCH 123/138] Runs zig fmt (#133) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- src/core/experimental/gpio.zig | 2 +- src/core/usb.zig | 14 +++++------ src/core/usb/hid.zig | 46 +++++++++++++++++----------------- src/modules/cpus/cortex-m.zig | 6 ++--- src/modules/cpus/riscv32.zig | 4 +-- src/start.zig | 4 +-- test/programs/uart-sync.zig | 6 ++--- 7 files changed, 41 insertions(+), 41 deletions(-) diff --git a/src/core/experimental/gpio.zig b/src/core/experimental/gpio.zig index e7ec33a..bddaf10 100644 --- a/src/core/experimental/gpio.zig +++ b/src/core/experimental/gpio.zig @@ -16,7 +16,7 @@ pub const State = enum(u1) { high = 1, pub fn value(self: State) u1 { - return @enumToInt(self); + return @intFromEnum(self); } }; diff --git a/src/core/usb.zig b/src/core/usb.zig index 7e2d183..7c6d24b 100644 --- a/src/core/usb.zig +++ b/src/core/usb.zig @@ -502,11 +502,11 @@ pub const Dir = enum(u8) { In = 0x80, pub inline fn endpoint(self: @This(), num: u8) u8 { - return num | @enumToInt(self); + return num | @intFromEnum(self); } pub inline fn of_endpoint_addr(addr: u8) @This() { - return if (addr & @enumToInt(@This().In) != 0) @This().In else @This().Out; + return if (addr & @intFromEnum(@This().In) != 0) @This().In else @This().Out; } }; @@ -531,7 +531,7 @@ pub const EndpointDescriptor = packed struct { pub fn serialize(self: *const @This()) [7]u8 { var out: [7]u8 = undefined; out[0] = 7; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = self.endpoint_address; out[3] = self.attributes; out[4] = @intCast(u8, self.max_packet_size & 0xff); @@ -567,7 +567,7 @@ pub const InterfaceDescriptor = packed struct { pub fn serialize(self: *const @This()) [9]u8 { var out: [9]u8 = undefined; out[0] = 9; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = self.interface_number; out[3] = self.alternate_setting; out[4] = self.num_endpoints; @@ -611,7 +611,7 @@ pub const ConfigurationDescriptor = packed struct { pub fn serialize(self: *const @This()) [9]u8 { var out: [9]u8 = undefined; out[0] = 9; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = @intCast(u8, self.total_length & 0xff); out[3] = @intCast(u8, (self.total_length >> 8) & 0xff); out[4] = self.num_interfaces; @@ -659,7 +659,7 @@ pub const DeviceDescriptor = packed struct { pub fn serialize(self: *const @This()) [18]u8 { var out: [18]u8 = undefined; out[0] = 18; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = @intCast(u8, self.bcd_usb & 0xff); out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); out[4] = self.device_class; @@ -706,7 +706,7 @@ pub const DeviceQualifierDescriptor = packed struct { pub fn serialize(self: *const @This()) [10]u8 { var out: [10]u8 = undefined; out[0] = 10; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = @intCast(u8, self.bcd_usb & 0xff); out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); out[4] = self.device_class; diff --git a/src/core/usb/hid.zig b/src/core/usb/hid.zig index 4993f6c..758e1c1 100644 --- a/src/core/usb/hid.zig +++ b/src/core/usb/hid.zig @@ -104,12 +104,12 @@ pub const HidDescriptor = packed struct { pub fn serialize(self: *const @This()) [9]u8 { var out: [9]u8 = undefined; out[0] = 9; // length - out[1] = @enumToInt(self.descriptor_type); + out[1] = @intFromEnum(self.descriptor_type); out[2] = @intCast(u8, self.bcd_hid & 0xff); out[3] = @intCast(u8, (self.bcd_hid >> 8) & 0xff); out[4] = self.country_code; out[5] = self.num_descriptors; - out[6] = @enumToInt(self.report_type); + out[6] = @intFromEnum(self.report_type); out[7] = @intCast(u8, self.report_length & 0xff); out[8] = @intCast(u8, (self.report_length >> 8) & 0xff); return out; @@ -313,17 +313,17 @@ pub fn hid_report_item( pub fn hid_collection(data: CollectionItem) [2]u8 { return hid_report_item( 1, - @enumToInt(ReportItemTypes.Main), - @enumToInt(ReportItemMainGroup.Collection), - std.mem.toBytes(@enumToInt(data)), + @intFromEnum(ReportItemTypes.Main), + @intFromEnum(ReportItemMainGroup.Collection), + std.mem.toBytes(@intFromEnum(data)), ); } pub fn hid_input(data: u8) [2]u8 { return hid_report_item( 1, - @enumToInt(ReportItemTypes.Main), - @enumToInt(ReportItemMainGroup.Input), + @intFromEnum(ReportItemTypes.Main), + @intFromEnum(ReportItemMainGroup.Input), std.mem.toBytes(data), ); } @@ -331,8 +331,8 @@ pub fn hid_input(data: u8) [2]u8 { pub fn hid_output(data: u8) [2]u8 { return hid_report_item( 1, - @enumToInt(ReportItemTypes.Main), - @enumToInt(ReportItemMainGroup.Output), + @intFromEnum(ReportItemTypes.Main), + @intFromEnum(ReportItemMainGroup.Output), std.mem.toBytes(data), ); } @@ -340,8 +340,8 @@ pub fn hid_output(data: u8) [2]u8 { pub fn hid_collection_end() [1]u8 { return hid_report_item( 0, - @enumToInt(ReportItemTypes.Main), - @enumToInt(ReportItemMainGroup.CollectionEnd), + @intFromEnum(ReportItemTypes.Main), + @intFromEnum(ReportItemMainGroup.CollectionEnd), .{}, ); } @@ -352,8 +352,8 @@ pub fn hid_collection_end() [1]u8 { pub fn hid_usage_page(comptime n: u2, usage: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Global), - @enumToInt(GlobalItem.UsagePage), + @intFromEnum(ReportItemTypes.Global), + @intFromEnum(GlobalItem.UsagePage), usage, ); } @@ -361,8 +361,8 @@ pub fn hid_usage_page(comptime n: u2, usage: [n]u8) [n + 1]u8 { pub fn hid_logical_min(comptime n: u2, data: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Global), - @enumToInt(GlobalItem.LogicalMin), + @intFromEnum(ReportItemTypes.Global), + @intFromEnum(GlobalItem.LogicalMin), data, ); } @@ -370,8 +370,8 @@ pub fn hid_logical_min(comptime n: u2, data: [n]u8) [n + 1]u8 { pub fn hid_logical_max(comptime n: u2, data: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Global), - @enumToInt(GlobalItem.LogicalMax), + @intFromEnum(ReportItemTypes.Global), + @intFromEnum(GlobalItem.LogicalMax), data, ); } @@ -379,8 +379,8 @@ pub fn hid_logical_max(comptime n: u2, data: [n]u8) [n + 1]u8 { pub fn hid_report_size(comptime n: u2, data: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Global), - @enumToInt(GlobalItem.ReportSize), + @intFromEnum(ReportItemTypes.Global), + @intFromEnum(GlobalItem.ReportSize), data, ); } @@ -388,8 +388,8 @@ pub fn hid_report_size(comptime n: u2, data: [n]u8) [n + 1]u8 { pub fn hid_report_count(comptime n: u2, data: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Global), - @enumToInt(GlobalItem.ReportCount), + @intFromEnum(ReportItemTypes.Global), + @intFromEnum(GlobalItem.ReportCount), data, ); } @@ -400,8 +400,8 @@ pub fn hid_report_count(comptime n: u2, data: [n]u8) [n + 1]u8 { pub fn hid_usage(comptime n: u2, data: [n]u8) [n + 1]u8 { return hid_report_item( n, - @enumToInt(ReportItemTypes.Local), - @enumToInt(LocalItem.Usage), + @intFromEnum(ReportItemTypes.Local), + @intFromEnum(LocalItem.Usage), data, ); } diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index f6f92bc..a9ad3fa 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -5,7 +5,7 @@ const root = @import("root"); pub const regs = struct { // Interrupt Control and State Register - pub const ICSR = @intToPtr(*volatile mmio.Mmio(packed struct { + pub const ICSR = @ptrFromInt(*volatile mmio.Mmio(packed struct { VECTACTIVE: u9, reserved0: u2, RETTOBASE: u1, @@ -82,7 +82,7 @@ pub const startup_logic = struct { { const bss_start = @ptrCast([*]u8, µzig_bss_start); const bss_end = @ptrCast([*]u8, µzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); } @@ -91,7 +91,7 @@ pub const startup_logic = struct { { const data_start = @ptrCast([*]u8, µzig_data_start); const data_end = @ptrCast([*]u8, µzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); const data_src = @ptrCast([*]const u8, µzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index d788df0..e005904 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -59,7 +59,7 @@ pub const startup_logic = struct { { const bss_start = @ptrCast([*]u8, µzig_bss_start); const bss_end = @ptrCast([*]u8, µzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); } @@ -68,7 +68,7 @@ pub const startup_logic = struct { { const data_start = @ptrCast([*]u8, µzig_data_start); const data_end = @ptrCast([*]u8, µzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); const data_src = @ptrCast([*]const u8, µzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); diff --git a/src/start.zig b/src/start.zig index 97c6dc1..69cf81a 100644 --- a/src/start.zig +++ b/src/start.zig @@ -141,7 +141,7 @@ pub fn initialize_system_memories() void { { const bss_start = @ptrCast([*]u8, §ions.microzig_bss_start); const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); - const bss_len = @ptrToInt(bss_end) - @ptrToInt(bss_start); + const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); } @@ -150,7 +150,7 @@ pub fn initialize_system_memories() void { { const data_start = @ptrCast([*]u8, §ions.microzig_data_start); const data_end = @ptrCast([*]u8, §ions.microzig_data_end); - const data_len = @ptrToInt(data_end) - @ptrToInt(data_start); + const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); diff --git a/test/programs/uart-sync.zig b/test/programs/uart-sync.zig index 019b328..7d58367 100644 --- a/test/programs/uart-sync.zig +++ b/test/programs/uart-sync.zig @@ -8,12 +8,12 @@ const cfg = if (micro.config.has_board) .uart_idx = 1, .pins = .{}, }, - .@"STM32F3DISCOVERY" => .{ + .STM32F3DISCOVERY => .{ .led_pin = micro.Pin("LD3"), .uart_idx = 1, .pins = .{}, }, - .@"STM32F4DISCOVERY" => .{ + .STM32F4DISCOVERY => .{ .led_pin = micro.Pin("LD5"), .uart_idx = 2, .pins = .{ .tx = micro.Pin("PA2"), .rx = micro.Pin("PA3") }, @@ -32,7 +32,7 @@ const cfg = if (micro.config.has_board) } else switch (micro.config.chip_name) { .@"NXP LPC1768" => .{ .led_pin = micro.Pin("P1.18"), .uart_idx = 1, .pins = .{} }, - .@"GD32VF103x8" => .{ .led_pin = micro.Pin("PA2"), .uart_idx = 1, .pins = .{} }, + .GD32VF103x8 => .{ .led_pin = micro.Pin("PA2"), .uart_idx = 1, .pins = .{} }, else => @compileError("unknown chip"), }; From 9392fe0f7bddde26155c181ab80b70097b49c791 Mon Sep 17 00:00:00 2001 From: Vesim Date: Wed, 28 Jun 2023 00:38:29 +0200 Subject: [PATCH 124/138] Update to master and add system registers for cortex-m (#134) * Update to zig 0.11.0-dev.3826+7a197f124 * Add cortex-m system registers --- src/core/usb.zig | 36 +++++----- src/core/usb/hid.zig | 26 +++---- src/mmio.zig | 4 +- src/modules/cpus/cortex-m.zig | 127 ++++++++++++++++++++++++++++++++-- src/modules/cpus/riscv32.zig | 10 +-- src/start.zig | 10 +-- 6 files changed, 163 insertions(+), 50 deletions(-) diff --git a/src/core/usb.zig b/src/core/usb.zig index 7c6d24b..3d76c3b 100644 --- a/src/core/usb.zig +++ b/src/core/usb.zig @@ -111,7 +111,7 @@ pub fn Usb(comptime f: anytype) type { if (reqty == Dir.Out and req != null and req.? == SetupRequest.SetAddress) { // The new address is in the bottom 8 bits of the setup // packet value field. Store it for use later. - S.new_address = @intCast(u8, setup.value & 0xff); + S.new_address = @as(u8, @intCast(setup.value & 0xff)); // The address will actually get set later, we have // to use address 0 to send a status response. f.usb_start_tx( @@ -224,7 +224,7 @@ pub fn Usb(comptime f: anytype) type { if (debug) std.log.info(" String", .{}); // String descriptor index is in bottom 8 bits of // `value`. - const i = @intCast(usize, setup.value & 0xff); + const i: usize = @intCast(setup.value & 0xff); const bytes = StringBlk: { if (i == 0) { // Special index 0 requests the language @@ -235,7 +235,7 @@ pub fn Usb(comptime f: anytype) type { const s = usb_config.?.descriptor_strings[i - 1]; const len = 2 + s.len; - S.tmp[0] = @intCast(u8, len); + S.tmp[0] = @intCast(len); S.tmp[1] = 0x03; @memcpy(S.tmp[2..len], s); @@ -356,7 +356,7 @@ pub fn Usb(comptime f: anytype) type { // SetAddress request, if there is one: if (S.new_address) |addr| { // Change our address: - f.set_address(@intCast(u7, addr)); + f.set_address(@intCast(addr)); } else { // Otherwise, we've just finished sending // something to the host. We expect an ensuing @@ -534,8 +534,8 @@ pub const EndpointDescriptor = packed struct { out[1] = @intFromEnum(self.descriptor_type); out[2] = self.endpoint_address; out[3] = self.attributes; - out[4] = @intCast(u8, self.max_packet_size & 0xff); - out[5] = @intCast(u8, (self.max_packet_size >> 8) & 0xff); + out[4] = @intCast(self.max_packet_size & 0xff); + out[5] = @intCast((self.max_packet_size >> 8) & 0xff); out[6] = self.interval; return out; } @@ -612,8 +612,8 @@ pub const ConfigurationDescriptor = packed struct { var out: [9]u8 = undefined; out[0] = 9; // length out[1] = @intFromEnum(self.descriptor_type); - out[2] = @intCast(u8, self.total_length & 0xff); - out[3] = @intCast(u8, (self.total_length >> 8) & 0xff); + out[2] = @intCast(self.total_length & 0xff); + out[3] = @intCast((self.total_length >> 8) & 0xff); out[4] = self.num_interfaces; out[5] = self.configuration_value; out[6] = self.configuration_s; @@ -660,18 +660,18 @@ pub const DeviceDescriptor = packed struct { var out: [18]u8 = undefined; out[0] = 18; // length out[1] = @intFromEnum(self.descriptor_type); - out[2] = @intCast(u8, self.bcd_usb & 0xff); - out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); + out[2] = @intCast(self.bcd_usb & 0xff); + out[3] = @intCast((self.bcd_usb >> 8) & 0xff); out[4] = self.device_class; out[5] = self.device_subclass; out[6] = self.device_protocol; out[7] = self.max_packet_size0; - out[8] = @intCast(u8, self.vendor & 0xff); - out[9] = @intCast(u8, (self.vendor >> 8) & 0xff); - out[10] = @intCast(u8, self.product & 0xff); - out[11] = @intCast(u8, (self.product >> 8) & 0xff); - out[12] = @intCast(u8, self.bcd_device & 0xff); - out[13] = @intCast(u8, (self.bcd_device >> 8) & 0xff); + out[8] = @intCast(self.vendor & 0xff); + out[9] = @intCast((self.vendor >> 8) & 0xff); + out[10] = @intCast(self.product & 0xff); + out[11] = @intCast((self.product >> 8) & 0xff); + out[12] = @intCast(self.bcd_device & 0xff); + out[13] = @intCast((self.bcd_device >> 8) & 0xff); out[14] = self.manufacturer_s; out[15] = self.product_s; out[16] = self.serial_s; @@ -707,8 +707,8 @@ pub const DeviceQualifierDescriptor = packed struct { var out: [10]u8 = undefined; out[0] = 10; // length out[1] = @intFromEnum(self.descriptor_type); - out[2] = @intCast(u8, self.bcd_usb & 0xff); - out[3] = @intCast(u8, (self.bcd_usb >> 8) & 0xff); + out[2] = @intCast(self.bcd_usb & 0xff); + out[3] = @intCast((self.bcd_usb >> 8) & 0xff); out[4] = self.device_class; out[5] = self.device_subclass; out[6] = self.device_protocol; diff --git a/src/core/usb/hid.zig b/src/core/usb/hid.zig index 758e1c1..e2c6d7f 100644 --- a/src/core/usb/hid.zig +++ b/src/core/usb/hid.zig @@ -105,13 +105,13 @@ pub const HidDescriptor = packed struct { var out: [9]u8 = undefined; out[0] = 9; // length out[1] = @intFromEnum(self.descriptor_type); - out[2] = @intCast(u8, self.bcd_hid & 0xff); - out[3] = @intCast(u8, (self.bcd_hid >> 8) & 0xff); + out[2] = @intCast(self.bcd_hid & 0xff); + out[3] = @intCast((self.bcd_hid >> 8) & 0xff); out[4] = self.country_code; out[5] = self.num_descriptors; out[6] = @intFromEnum(self.report_type); - out[7] = @intCast(u8, self.report_length & 0xff); - out[8] = @intCast(u8, (self.report_length >> 8) & 0xff); + out[7] = @intCast(self.report_length & 0xff); + out[8] = @intCast((self.report_length >> 8) & 0xff); return out; } }; @@ -297,7 +297,7 @@ pub fn hid_report_item( ) [n + 1]u8 { var out: [n + 1]u8 = undefined; - out[0] = (@intCast(u8, tag) << 4) | (@intCast(u8, typ) << 2) | n; + out[0] = (@as(u8, @intCast(tag)) << 4) | (@as(u8, @intCast(typ)) << 2) | n; var i: usize = 0; while (i < n) : (i += 1) { @@ -438,19 +438,19 @@ test "create hid report item" { "\x22\x11".*, ); - try std.testing.expectEqual(@intCast(usize, 3), r.len); - try std.testing.expectEqual(@intCast(u8, 50), r[0]); - try std.testing.expectEqual(@intCast(u8, 0x22), r[1]); - try std.testing.expectEqual(@intCast(u8, 0x11), r[2]); + try std.testing.expectEqual(@as(usize, @intCast(3)), r.len); + try std.testing.expectEqual(@as(u8, @intCast(50)), r[0]); + try std.testing.expectEqual(@as(u8, @intCast(0x22)), r[1]); + try std.testing.expectEqual(@as(u8, @intCast(0x11)), r[2]); } test "create hid fido usage page" { const f = hid_usage_page(2, UsageTable.fido); - try std.testing.expectEqual(@intCast(usize, 3), f.len); - try std.testing.expectEqual(@intCast(u8, 6), f[0]); - try std.testing.expectEqual(@intCast(u8, 0xd0), f[1]); - try std.testing.expectEqual(@intCast(u8, 0xf1), f[2]); + try std.testing.expectEqual(@as(usize, @intCast(3)), f.len); + try std.testing.expectEqual(@as(u8, @intCast(6)), f[0]); + try std.testing.expectEqual(@as(u8, @intCast(0xd0)), f[1]); + try std.testing.expectEqual(@as(u8, @intCast(0xf1)), f[2]); } test "report descriptor fido" { diff --git a/src/mmio.zig b/src/mmio.zig index 2d6b760..83c7699 100644 --- a/src/mmio.zig +++ b/src/mmio.zig @@ -22,14 +22,14 @@ pub fn Mmio(comptime PackedT: type) type { pub const underlying_type = PackedT; pub inline fn read(addr: *volatile Self) PackedT { - return @bitCast(PackedT, addr.raw); + return @bitCast(addr.raw); } pub inline fn write(addr: *volatile Self, val: PackedT) void { comptime { assert(@bitSizeOf(PackedT) == @bitSizeOf(IntT)); } - addr.write_raw(@bitCast(IntT, val)); + addr.write_raw(@bitCast(val)); } pub fn write_raw(addr: *volatile Self, val: IntT) void { diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index a9ad3fa..b37e12b 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -5,7 +5,7 @@ const root = @import("root"); pub const regs = struct { // Interrupt Control and State Register - pub const ICSR = @ptrFromInt(*volatile mmio.Mmio(packed struct { + pub const ICSR: *volatile mmio.Mmio(packed struct { VECTACTIVE: u9, reserved0: u2, RETTOBASE: u1, @@ -20,7 +20,7 @@ pub const regs = struct { PENDSVSET: u1, reserved3: u2, NMIPENDSET: u1, - }), 0xE000ED04); + }) = @ptrFromInt(0xE000ED04); }; pub fn executing_isr() bool { @@ -80,8 +80,8 @@ pub const startup_logic = struct { // fill .bss with zeroes { - const bss_start = @ptrCast([*]u8, µzig_bss_start); - const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_start: [*]u8 = @ptrCast(µzig_bss_start); + const bss_end: [*]u8 = @ptrCast(µzig_bss_end); const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); @@ -89,10 +89,10 @@ pub const startup_logic = struct { // load .data from flash { - const data_start = @ptrCast([*]u8, µzig_data_start); - const data_end = @ptrCast([*]u8, µzig_data_end); + const data_start: [*]u8 = @ptrCast(µzig_data_start); + const data_end: [*]u8 = @ptrCast(µzig_data_end); const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); - const data_src = @ptrCast([*]const u8, µzig_data_load_start); + const data_src: [*]const u8 = @ptrCast(µzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); } @@ -175,3 +175,116 @@ fn create_interrupt_vector( }, }; } + +pub const peripherals = struct { + /// System Tick Timer + pub const SysTick = @as(*volatile types.peripherals.SysTick, @ptrFromInt(0xe000e010)); + + /// System Control Space + pub const NVIC = @compileError("TODO"); // @ptrFromInt(*volatile types.peripherals.NVIC, 0xe000e100); + + /// System Control Block + pub const SCB = @as(*volatile types.peripherals.SCB, @ptrFromInt(0xe000ed00)); +}; + +pub const types = struct { + pub const peripherals = struct { + /// System Tick Timer + pub const SysTick = extern struct { + /// SysTick Control and Status Register + CTRL: mmio.Mmio(packed struct(u32) { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved16: u13, + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick Reload Value Register + LOAD: mmio.Mmio(packed struct(u32) { + RELOAD: u24, + padding: u8, + }), + /// SysTick Current Value Register + VAL: mmio.Mmio(packed struct(u32) { + CURRENT: u24, + padding: u8, + }), + /// SysTick Calibration Register + CALIB: mmio.Mmio(packed struct(u32) { + TENMS: u24, + reserved30: u6, + SKEW: u1, + NOREF: u1, + }), + }; + + /// System Control Block + pub const SCB = extern struct { + CPUID: mmio.Mmio(packed struct(u32) { + REVISION: u4, + PARTNO: u12, + ARCHITECTURE: u4, + VARIANT: u4, + IMPLEMENTER: u8, + }), + /// Interrupt Control and State Register + ICSR: mmio.Mmio(packed struct(u32) { + VECTACTIVE: u9, + reserved12: u3, + VECTPENDING: u9, + reserved22: u1, + ISRPENDING: u1, + ISRPREEMPT: u1, + reserved25: u1, + PENDSTCLR: u1, + PENDSTSET: u1, + PENDSVCLR: u1, + PENDSVSET: u1, + reserved31: u2, + NMIPENDSET: u1, + }), + /// Vector Table Offset Register + VTOR: mmio.Mmio(packed struct(u32) { + reserved8: u8, + TBLOFF: u24, + }), + /// Application Interrupt and Reset Control Register + AIRCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + VECTCLRACTIVE: u1, + SYSRESETREQ: u1, + reserved15: u12, + ENDIANESS: u1, + VECTKEY: u16, + }), + /// System Control Register + SCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + SLEEPONEXIT: u1, + SLEEPDEEP: u1, + reserved4: u1, + SEVONPEND: u1, + padding: u27, + }), + /// Configuration Control Register + CCR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + UNALIGN_TRP: u1, + reserved9: u5, + STKALIGN: u1, + padding: u22, + }), + reserved28: [4]u8, + /// System Handlers Priority Registers. [0] is RESERVED + SHP: u32, + reserved36: [4]u8, + /// System Handler Control and State Register + SHCSR: mmio.Mmio(packed struct(u32) { + reserved15: u15, + SVCALLPENDED: u1, + padding: u16, + }), + }; + }; +}; diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index e005904..fea883b 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -57,8 +57,8 @@ pub const startup_logic = struct { // fill .bss with zeroes { - const bss_start = @ptrCast([*]u8, µzig_bss_start); - const bss_end = @ptrCast([*]u8, µzig_bss_end); + const bss_start: [*]u8 = @ptrCast(µzig_bss_start); + const bss_end: [*]u8 = @ptrCast(µzig_bss_end); const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); @@ -66,10 +66,10 @@ pub const startup_logic = struct { // load .data from flash { - const data_start = @ptrCast([*]u8, µzig_data_start); - const data_end = @ptrCast([*]u8, µzig_data_end); + const data_start: [*]u8 = @ptrCast(µzig_data_start); + const data_end: [*]u8 = @ptrCast(µzig_data_end); const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); - const data_src = @ptrCast([*]const u8, µzig_data_load_start); + const data_src: [*]const u8 = @ptrCast(µzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); } diff --git a/src/start.zig b/src/start.zig index 69cf81a..59ec4cd 100644 --- a/src/start.zig +++ b/src/start.zig @@ -139,8 +139,8 @@ pub fn initialize_system_memories() void { // fill .bss with zeroes { - const bss_start = @ptrCast([*]u8, §ions.microzig_bss_start); - const bss_end = @ptrCast([*]u8, §ions.microzig_bss_end); + const bss_start: [*]u8 = @ptrCast(§ions.microzig_bss_start); + const bss_end: [*]u8 = @ptrCast(§ions.microzig_bss_end); const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start); @memset(bss_start[0..bss_len], 0); @@ -148,10 +148,10 @@ pub fn initialize_system_memories() void { // load .data from flash { - const data_start = @ptrCast([*]u8, §ions.microzig_data_start); - const data_end = @ptrCast([*]u8, §ions.microzig_data_end); + const data_start: [*]u8 = @ptrCast(§ions.microzig_data_start); + const data_end: [*]u8 = @ptrCast(§ions.microzig_data_end); const data_len = @intFromPtr(data_end) - @intFromPtr(data_start); - const data_src = @ptrCast([*]const u8, §ions.microzig_data_load_start); + const data_src: [*]const u8 = @ptrCast(§ions.microzig_data_load_start); @memcpy(data_start[0..data_len], data_src[0..data_len]); } From c1ac2f4cf3430bd9ce6861dbff66a287c814a395 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 3 Aug 2023 21:04:54 -0700 Subject: [PATCH 125/138] FileSource -> LazyPath (#136) --- .github/workflows/auto-pr.yml | 46 ------------- .github/workflows/build.yml | 1 + build.zig | 117 +++++++++++----------------------- docs/tricks.adoc | 11 ---- src/modules/Board.zig | 2 +- src/modules/Chip.zig | 8 +-- src/modules/Cpu.zig | 2 +- 7 files changed, 44 insertions(+), 143 deletions(-) delete mode 100644 .github/workflows/auto-pr.yml diff --git a/.github/workflows/auto-pr.yml b/.github/workflows/auto-pr.yml deleted file mode 100644 index fc80d70..0000000 --- a/.github/workflows/auto-pr.yml +++ /dev/null @@ -1,46 +0,0 @@ -name: Downstream Updates -on: - workflow_dispatch: - push: - branches: - - main - -jobs: - update: - runs-on: ubuntu-latest - strategy: - matrix: - repo: [ - hardware-support-template, - espressif-esp, - gigadevice-gd32, - microchip-atmega, - nordic-nrf5x, - nxp-lpc, - raspberrypi-rp2040, - stmicro-stm32, - ] - steps: - - name: Checkout - uses: actions/checkout@v2 - with: - repository: ZigEmbeddedGroup/${{ matrix.repo }} - submodules: recursive - fetch-depth: 0 - - - name: Update - id: update - run: | - cd deps/microzig - git pull origin main - echo "DESCRIPTION=$(git log -1 --pretty=%B | head -n 1)" >> $GITHUB_OUTPUT - - - name: Create Pull Request - uses: peter-evans/create-pull-request@v5.0.1 - with: - token: ${{ secrets.PR_TOKEN }} - branch: downstream/update-microzig - commit-message: update microzig - delete-branch: true - title: Update microzig - body: ${{ steps.update.outputs.DESCRIPTION }} diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index f41ccca..90decfa 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -8,6 +8,7 @@ jobs: strategy: matrix: os: [ + linux-latest, windows-latest, macos-latest, ] diff --git a/build.zig b/build.zig index 55e2ac8..275882a 100644 --- a/build.zig +++ b/build.zig @@ -5,8 +5,9 @@ const std = @import("std"); const LibExeObjStep = std.build.LibExeObjStep; const Module = std.build.Module; -const FileSource = std.build.FileSource; -const Builder = std.Build; +const LazyPath = std.build.LazyPath; +const OptionsStep = std.build.OptionsStep; +const Build = std.Build; // alias for packages pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig"); @@ -45,7 +46,7 @@ pub const EmbeddedExecutable = struct { app_module.dependencies.put(name, module) catch @panic("OOM"); } - pub fn installArtifact(exe: *EmbeddedExecutable, b: *Builder) void { + pub fn installArtifact(exe: *EmbeddedExecutable, b: *Build) void { b.installArtifact(exe.inner); } @@ -61,7 +62,7 @@ pub const EmbeddedExecutable = struct { exe.inner.addCSourceFile(file, flags); } - pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *std.build.OptionsStep) void { + pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *OptionsStep) void { exe.inner.addOptions(module_name, options); const app_module = exe.inner.modules.get("app").?; const opt_module = exe.inner.modules.get(module_name).?; @@ -79,100 +80,56 @@ fn root_dir() []const u8 { pub const EmbeddedExecutableOptions = struct { name: []const u8, - source_file: std.build.FileSource, + source_file: LazyPath, backing: Backing, optimize: std.builtin.OptimizeMode = .Debug, - linkerscript_source_file: ?FileSource = null, + linkerscript_source_file: ?LazyPath = null, }; -pub fn addEmbeddedExecutable( - builder: *std.build.Builder, - opts: EmbeddedExecutableOptions, -) *EmbeddedExecutable { +pub fn addEmbeddedExecutable(b: *Build, opts: EmbeddedExecutableOptions) *EmbeddedExecutable { const has_board = (opts.backing == .board); const chip = switch (opts.backing) { - .chip => |c| c, - .board => |b| b.chip, + .chip => |chip| chip, + .board => |board| board.chip, }; const has_hal = chip.hal != null; - const config_file_name = blk: { - const hash = hash_blk: { - var hasher = std.hash.SipHash128(1, 2).init("abcdefhijklmnopq"); - - hasher.update(chip.name); - // TODO: this will likely crash for generated sources, need to - // properly hook this up to the build cache api - hasher.update(chip.source.getPath(builder)); - hasher.update(chip.cpu.name); - hasher.update(chip.cpu.source.getPath(builder)); - - if (opts.backing == .board) { - hasher.update(opts.backing.board.name); - // TODO: see above - hasher.update(opts.backing.board.source.getPath(builder)); - } - - var mac: [16]u8 = undefined; - hasher.final(&mac); - break :hash_blk mac; - }; - - const file_prefix = "zig-cache/microzig/config-"; - const file_suffix = ".zig"; - var ld_file_name: [file_prefix.len + 2 * hash.len + file_suffix.len]u8 = undefined; - const filename = std.fmt.bufPrint(&ld_file_name, "{s}{}{s}", .{ - file_prefix, - std.fmt.fmtSliceHexLower(&hash), - file_suffix, - }) catch unreachable; - - break :blk builder.dupe(filename); + // TODO: let the user override which ram section to use the stack on, + // for now just using the first ram section in the memory region list + const first_ram = blk: { + for (chip.memory_regions) |region| { + if (region.kind == .ram) + break :blk region; + } else @panic("no ram memory region found for setting the end-of-stack address"); }; - { - // TODO: let the user override which ram section to use the stack on, - // for now just using the first ram section in the memory region list - const first_ram = blk: { - for (chip.memory_regions) |region| { - if (region.kind == .ram) - break :blk region; - } else @panic("no ram memory region found for setting the end-of-stack address"); - }; - - std.fs.cwd().makeDir(std.fs.path.dirname(config_file_name).?) catch {}; - var config_file = std.fs.cwd().createFile(config_file_name, .{}) catch unreachable; - defer config_file.close(); - - var writer = config_file.writer(); + const config = b.addOptions(); + config.addOption(bool, "has_hal", has_hal); + config.addOption(bool, "has_board", has_board); + if (has_board) + config.addOption([]const u8, "board_name", opts.backing.board.name); - writer.print("pub const has_hal = {};\n", .{has_hal}) catch unreachable; - writer.print("pub const has_board = {};\n", .{has_board}) catch unreachable; - if (has_board) - writer.print("pub const board_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(opts.backing.board.name)}) catch unreachable; - - writer.print("pub const chip_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.name)}) catch unreachable; - writer.print("pub const cpu_name = \"{}\";\n", .{std.fmt.fmtSliceEscapeUpper(chip.cpu.name)}) catch unreachable; - writer.print("pub const end_of_stack = 0x{X:0>8};\n\n", .{first_ram.offset + first_ram.length}) catch unreachable; - } + config.addOption([]const u8, "chip_name", chip.name); + config.addOption([]const u8, "cpu_name", chip.name); + config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length); - const microzig_module = builder.createModule(.{ + const microzig_module = b.createModule(.{ .source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/microzig.zig", .{root_dir()}) }, }); - microzig_module.dependencies.put("config", builder.createModule(.{ - .source_file = .{ .path = config_file_name }, + microzig_module.dependencies.put("config", b.createModule(.{ + .source_file = config.getSource(), })) catch unreachable; - microzig_module.dependencies.put("chip", builder.createModule(.{ + microzig_module.dependencies.put("chip", b.createModule(.{ .source_file = chip.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig_module }, }, })) catch unreachable; - microzig_module.dependencies.put("cpu", builder.createModule(.{ + microzig_module.dependencies.put("cpu", b.createModule(.{ .source_file = chip.cpu.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig_module }, @@ -180,7 +137,7 @@ pub fn addEmbeddedExecutable( })) catch unreachable; if (chip.hal) |hal_module_source| { - microzig_module.dependencies.put("hal", builder.createModule(.{ + microzig_module.dependencies.put("hal", b.createModule(.{ .source_file = hal_module_source, .dependencies = &.{ .{ .name = "microzig", .module = microzig_module }, @@ -190,7 +147,7 @@ pub fn addEmbeddedExecutable( switch (opts.backing) { .board => |board| { - microzig_module.dependencies.put("board", builder.createModule(.{ + microzig_module.dependencies.put("board", b.createModule(.{ .source_file = board.source, .dependencies = &.{ .{ .name = "microzig", .module = microzig_module }, @@ -200,16 +157,16 @@ pub fn addEmbeddedExecutable( else => {}, } - const app_module = builder.createModule(.{ + const app_module = b.createModule(.{ .source_file = opts.source_file, .dependencies = &.{ .{ .name = "microzig", .module = microzig_module }, }, }); - const exe = builder.allocator.create(EmbeddedExecutable) catch unreachable; + const exe = b.allocator.create(EmbeddedExecutable) catch unreachable; exe.* = EmbeddedExecutable{ - .inner = builder.addExecutable(.{ + .inner = b.addExecutable(.{ .name = opts.name, .root_source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/start.zig", .{root_dir()}) }, .target = chip.cpu.target, @@ -228,7 +185,7 @@ pub fn addEmbeddedExecutable( if (opts.linkerscript_source_file) |linkerscript_source_file| { exe.inner.setLinkerScriptPath(linkerscript_source_file); } else { - const linkerscript = LinkerScriptStep.create(builder, chip) catch unreachable; + const linkerscript = LinkerScriptStep.create(b, chip) catch unreachable; exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); } @@ -242,7 +199,7 @@ pub fn addEmbeddedExecutable( } /// This build script validates usage patterns we expect from MicroZig -pub fn build(b: *std.build.Builder) !void { +pub fn build(b: *Build) !void { const backings = @import("test/backings.zig"); const optimize = b.standardOptimizeOption(.{}); diff --git a/docs/tricks.adoc b/docs/tricks.adoc index 11055a9..6eda21f 100644 --- a/docs/tricks.adoc +++ b/docs/tricks.adoc @@ -1,14 +1,3 @@ = Tips and Tricks This document has some `build.zig` tricks for other pages to reference. - -== Packaging and Paths - -TODO - -[source,zig] ----- -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} ----- diff --git a/src/modules/Board.zig b/src/modules/Board.zig index eb114bf..8e09b4a 100644 --- a/src/modules/Board.zig +++ b/src/modules/Board.zig @@ -2,5 +2,5 @@ const std = @import("std"); const Chip = @import("Chip.zig"); name: []const u8, -source: std.build.FileSource, +source: std.build.LazyPath, chip: Chip, diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig index b26aecd..3676fc9 100644 --- a/src/modules/Chip.zig +++ b/src/modules/Chip.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const FileSource = std.build.FileSource; +const LazyPath = std.build.LazyPath; const MemoryRegion = @import("MemoryRegion.zig"); const Cpu = @import("Cpu.zig"); @@ -7,10 +7,10 @@ const Cpu = @import("Cpu.zig"); const Chip = @This(); name: []const u8, -source: FileSource, +source: LazyPath, cpu: Cpu, -hal: ?FileSource = null, -json_register_schema: ?FileSource = null, +hal: ?LazyPath = null, +json_register_schema: ?LazyPath = null, memory_regions: []const MemoryRegion, pub fn from_standard_paths(comptime root_dir: []const u8, args: struct { diff --git a/src/modules/Cpu.zig b/src/modules/Cpu.zig index 4f9bcb9..e4cd307 100644 --- a/src/modules/Cpu.zig +++ b/src/modules/Cpu.zig @@ -1,5 +1,5 @@ const std = @import("std"); name: []const u8, -source: std.build.FileSource, +source: std.build.LazyPath, target: std.zig.CrossTarget, From d4a48f65fac24dcfe789d217a9154086b6a011e5 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 3 Aug 2023 21:16:54 -0700 Subject: [PATCH 126/138] anyopaque to u8 (#137) --- src/modules/cpus/cortex-m.zig | 13 ++++++++----- src/modules/cpus/riscv32.zig | 13 ++++++++----- src/start.zig | 13 ++++++++----- 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/src/modules/cpus/cortex-m.zig b/src/modules/cpus/cortex-m.zig index b37e12b..b9b5828 100644 --- a/src/modules/cpus/cortex-m.zig +++ b/src/modules/cpus/cortex-m.zig @@ -70,11 +70,14 @@ pub fn clrex() void { pub const startup_logic = struct { extern fn microzig_main() noreturn; - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; + // it looks odd to just use a u8 here, but in C it's common to use a + // char when linking these values from the linkerscript. What's + // important is the addresses of these values. + extern var microzig_data_start: u8; + extern var microzig_data_end: u8; + extern var microzig_bss_start: u8; + extern var microzig_bss_end: u8; + extern const microzig_data_load_start: u8; pub fn _start() callconv(.C) noreturn { diff --git a/src/modules/cpus/riscv32.zig b/src/modules/cpus/riscv32.zig index fea883b..b7c1b96 100644 --- a/src/modules/cpus/riscv32.zig +++ b/src/modules/cpus/riscv32.zig @@ -47,11 +47,14 @@ pub const REGBYTES = (1 << LOG_REGBYTES); pub const startup_logic = struct { extern fn microzig_main() noreturn; - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; + // it looks odd to just use a u8 here, but in C it's common to use a + // char when linking these values from the linkerscript. What's + // important is the addresses of these values. + extern var microzig_data_start: u8; + extern var microzig_data_end: u8; + extern var microzig_bss_start: u8; + extern var microzig_bss_end: u8; + extern const microzig_data_load_start: u8; pub fn _start() callconv(.C) noreturn { diff --git a/src/start.zig b/src/start.zig index 59ec4cd..7271ad2 100644 --- a/src/start.zig +++ b/src/start.zig @@ -127,11 +127,14 @@ export fn microzig_main() noreturn { /// Contains references to the microzig .data and .bss sections, also /// contains the initial load address for .data if it is in flash. pub const sections = struct { - extern var microzig_data_start: anyopaque; - extern var microzig_data_end: anyopaque; - extern var microzig_bss_start: anyopaque; - extern var microzig_bss_end: anyopaque; - extern const microzig_data_load_start: anyopaque; + // it looks odd to just use a u8 here, but in C it's common to use a + // char when linking these values from the linkerscript. What's + // important is the addresses of these values. + extern var microzig_data_start: u8; + extern var microzig_data_end: u8; + extern var microzig_bss_start: u8; + extern var microzig_bss_end: u8; + extern const microzig_data_load_start: u8; }; pub fn initialize_system_memories() void { From 6ccee6d13aa5ccc0e0d94548610e7c97e428ca6d Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 4 Aug 2023 00:47:18 -0700 Subject: [PATCH 127/138] build against 0.11.0 (#138) * build against 0.11.0 * fix typo --- .github/workflows/build.yml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 90decfa..e387a38 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -8,21 +8,17 @@ jobs: strategy: matrix: os: [ - linux-latest, + ubuntu-latest, windows-latest, macos-latest, ] steps: - - name: Checkout - uses: actions/checkout@v2 - with: - submodules: recursive - fetch-depth: 0 + - uses: actions/checkout@v2 - name: Setup Zig uses: goto-bus-stop/setup-zig@v1.3.0 with: - version: master + version: 0.11.0 - name: Build tests run: zig build test -Doptimize=ReleaseSmall From 0b3be0a4cc7e6d45714cb09961efc771e364723c Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 4 Aug 2023 00:50:02 -0700 Subject: [PATCH 128/138] Update README.adoc (#139) --- README.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index bae9b60..b72a346 100644 --- a/README.adoc +++ b/README.adoc @@ -12,7 +12,7 @@ toc::[] == What version of Zig to use -Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig. +0.11.0 == Contributing From 2859530ac26c9f714f70131a983ded8cb5057b1a Mon Sep 17 00:00:00 2001 From: Francisco Llobet <39483951+FranciscoLlobet@users.noreply.github.com> Date: Sat, 5 Aug 2023 17:43:06 +0200 Subject: [PATCH 129/138] Fixing issues in Build to achieve v0.11.0 compatibility (#140) --- build.zig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/build.zig b/build.zig index 275882a..f66b2b5 100644 --- a/build.zig +++ b/build.zig @@ -3,10 +3,10 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); -const LibExeObjStep = std.build.LibExeObjStep; -const Module = std.build.Module; -const LazyPath = std.build.LazyPath; -const OptionsStep = std.build.OptionsStep; +const LibExeObjStep = std.Build.LibExeObjStep; +const Module = std.Build.Module; +const LazyPath = std.Build.LazyPath; +const OptionsStep = std.Build.OptionsStep; const Build = std.Build; // alias for packages @@ -50,16 +50,16 @@ pub const EmbeddedExecutable = struct { b.installArtifact(exe.inner); } - pub fn addIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + pub fn addIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void { exe.inner.addIncludePath(path); } - pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: []const u8) void { + pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void { return exe.inner.addSystemIncludePath(path); } - pub fn addCSourceFile(exe: *EmbeddedExecutable, file: []const u8, flags: []const []const u8) void { - exe.inner.addCSourceFile(file, flags); + pub fn addCSourceFile(exe: *EmbeddedExecutable, source: Build.Step.Compile.CSourceFile) void { + exe.inner.addCSourceFile(source); } pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *OptionsStep) void { @@ -69,8 +69,8 @@ pub const EmbeddedExecutable = struct { app_module.dependencies.put(module_name, opt_module) catch @panic("OOM"); } - pub fn addObjectFile(exe: *EmbeddedExecutable, source_file: []const u8) void { - exe.inner.addObjectFile(source_file); + pub fn addObjectFile(exe: *EmbeddedExecutable, source: LazyPath) void { + exe.inner.addObjectFile(source); } }; From f0a6aa9ce1829df91f2d7f160bbc6f5bc41a3c80 Mon Sep 17 00:00:00 2001 From: L1ucas <69647369+L1ucas@users.noreply.github.com> Date: Sat, 12 Aug 2023 12:23:57 -0300 Subject: [PATCH 130/138] Fix README typo (#141) --- README.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index b72a346..903b390 100644 --- a/README.adoc +++ b/README.adoc @@ -35,7 +35,7 @@ For MicroZig internals please see the xref:docs/design.adoc[Design Document]. == Does MicroZig support X hardware? -MicroZig is designed to cover as wide a swath of hardware as possible. The https://github.com/ZigEmbeddedGroup[Zig Embedded Group] has some repositories that contain hardware-specific code. You will find them with the `hardware-support-package` label. If you can't find your specific device, it doesn't mean that you can't run Zig on it, it's likely you're just the first! In that case, see xref:#getting-microzig-on-new-hardware[Getting MicroZig on New Hardare]. +MicroZig is designed to cover as wide a swath of hardware as possible. The https://github.com/ZigEmbeddedGroup[Zig Embedded Group] has some repositories that contain hardware-specific code. You will find them with the `hardware-support-package` label. If you can't find your specific device, it doesn't mean that you can't run Zig on it, it's likely you're just the first! In that case, see xref:#getting-microzig-on-new-hardware[Getting MicroZig on New Hardware]. Start with an empty Zig project by running `zig init-exe`, and add the hardware support package as a submodule. We'll use `microchip-atmega` in our example: From 3bdb7381be3f066aa2ea0ed1c2c7ea796141ac55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 22 Sep 2023 09:01:19 +0200 Subject: [PATCH 131/138] Microzig Generation 2 Build Interface (#144) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Starts to rework build framework. * Fully reworks build API, builds with RP2040 again. * Adds docs and doc generation. * Renames source to register_definitions, makes Target.configure optional. * Adds issue tracking links. * Drops CI for now --------- Co-authored-by: Felix "xq" Queißner --- .buildkite/pipeline.yml | 7 - .github/workflows/build.yml | 24 - build.zig | 1063 ++++++++++++++++++++++----- build.zig.zon | 14 + src/{modules => }/cpus/avr5.zig | 0 src/{modules => }/cpus/cortex-m.zig | 0 src/{modules => }/cpus/riscv32.zig | 0 src/modules/Board.zig | 6 - src/modules/Chip.zig | 44 -- src/modules/Cpu.zig | 5 - src/modules/LinkerScriptStep.zig | 172 ----- src/modules/MemoryRegion.zig | 18 - src/modules/cpus.zig | 84 --- 13 files changed, 911 insertions(+), 526 deletions(-) delete mode 100644 .buildkite/pipeline.yml delete mode 100644 .github/workflows/build.yml create mode 100644 build.zig.zon rename src/{modules => }/cpus/avr5.zig (100%) rename src/{modules => }/cpus/cortex-m.zig (100%) rename src/{modules => }/cpus/riscv32.zig (100%) delete mode 100644 src/modules/Board.zig delete mode 100644 src/modules/Chip.zig delete mode 100644 src/modules/Cpu.zig delete mode 100644 src/modules/LinkerScriptStep.zig delete mode 100644 src/modules/MemoryRegion.zig delete mode 100644 src/modules/cpus.zig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml deleted file mode 100644 index 723f5a2..0000000 --- a/.buildkite/pipeline.yml +++ /dev/null @@ -1,7 +0,0 @@ -steps: - - group: Build and Test - steps: - - label: Debug - command: zig build test - - label: ReleaseSmall - command: zig build test -Doptimize=ReleaseSmall diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml deleted file mode 100644 index e387a38..0000000 --- a/.github/workflows/build.yml +++ /dev/null @@ -1,24 +0,0 @@ -name: Build -on: - push: - -jobs: - build: - runs-on: ${{ matrix.os }} - strategy: - matrix: - os: [ - ubuntu-latest, - windows-latest, - macos-latest, - ] - steps: - - uses: actions/checkout@v2 - - - name: Setup Zig - uses: goto-bus-stop/setup-zig@v1.3.0 - with: - version: 0.11.0 - - - name: Build tests - run: zig build test -Doptimize=ReleaseSmall diff --git a/build.zig b/build.zig index f66b2b5..9b92d6b 100644 --- a/build.zig +++ b/build.zig @@ -3,97 +3,419 @@ //! This means we need to use addExecutable() instead of using const std = @import("std"); -const LibExeObjStep = std.Build.LibExeObjStep; -const Module = std.Build.Module; -const LazyPath = std.Build.LazyPath; -const OptionsStep = std.Build.OptionsStep; -const Build = std.Build; - -// alias for packages -pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig"); -pub const cpus = @import("src/modules/cpus.zig"); -pub const Board = @import("src/modules/Board.zig"); -pub const Chip = @import("src/modules/Chip.zig"); -pub const Cpu = @import("src/modules/Cpu.zig"); -pub const MemoryRegion = @import("src/modules/MemoryRegion.zig"); - -pub const Backing = union(enum) { - board: Board, - chip: Chip, +const uf2 = @import("uf2"); + +//////////////////////////////////////// +// MicroZig Gen 2 Interface // +//////////////////////////////////////// + +fn root() []const u8 { + return comptime (std.fs.path.dirname(@src().file) orelse "."); +} +const build_root = root(); + +const MicroZig = @This(); + +b: *std.Build, +self: *std.Build.Dependency, + +/// Creates a new instance of the MicroZig build support. +/// +/// This is necessary as we need to keep track of some internal state to prevent +/// duplicated work per firmware built. +pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig { + const mz = b.allocator.create(MicroZig) catch @panic("out of memory"); + mz.* = MicroZig{ + .b = b, + .self = b.dependency(dependency_name, .{}), + }; + return mz; +} + +/// This build script validates usage patterns we expect from MicroZig +pub fn build(b: *std.Build) !void { + const uf2_dep = b.dependency("uf2", .{}); - pub fn get_target(self: @This()) std.zig.CrossTarget { - return switch (self) { - .board => |brd| brd.chip.cpu.target, - .chip => |chip| chip.cpu.target, + const build_test = b.addTest(.{ + .root_source_file = .{ .path = "build.zig" }, + }); + + build_test.addAnonymousModule("uf2", .{ + .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") }, + }); + + const install_docs = b.addInstallDirectory(.{ + .source_dir = build_test.getEmittedDocs(), + .install_dir = .prefix, + .install_subdir = "docs", + }); + + b.getInstallStep().dependOn(&install_docs.step); + + // const backings = @import("test/backings.zig"); + // const optimize = b.standardOptimizeOption(.{}); + + // const minimal = addEmbeddedExecutable(b, .{ + // .name = "minimal", + // .source_file = .{ + // .path = comptime root_dir() ++ "/test/programs/minimal.zig", + // }, + // .backing = backings.minimal, + // .optimize = optimize, + // }); + + // const has_hal = addEmbeddedExecutable(b, .{ + // .name = "has_hal", + // .source_file = .{ + // .path = comptime root_dir() ++ "/test/programs/has_hal.zig", + // }, + // .backing = backings.has_hal, + // .optimize = optimize, + // }); + + // const has_board = addEmbeddedExecutable(b, .{ + // .name = "has_board", + // .source_file = .{ + // .path = comptime root_dir() ++ "/test/programs/has_board.zig", + // }, + // .backing = backings.has_board, + // .optimize = optimize, + // }); + + // const core_tests = b.addTest(.{ + // .root_source_file = .{ + // .path = comptime root_dir() ++ "/src/core.zig", + // }, + // .optimize = optimize, + // }); + + // const test_step = b.step("test", "build test programs"); + // test_step.dependOn(&minimal.inner.step); + // test_step.dependOn(&has_hal.inner.step); + // test_step.dependOn(&has_board.inner.step); + // test_step.dependOn(&b.addRunArtifact(core_tests).step); +} + +/// The resulting binary format for the firmware file. +/// A lot of embedded systems don't use plain ELF files, thus we provide means +/// to convert the resulting ELF into other common formats. +pub const BinaryFormat = union(enum) { + /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler. + elf, + + /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset. + bin, + + /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains + /// an ASCII description of what memory to load where. + hex, + + /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file. + dfu, + + /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft. + uf2: uf2.FamilyId, + + /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader. + esp, + + /// Custom option for non-standard formats. + custom: *Custom, + + /// Returns the standard extension for the resulting binary file. + pub fn getExtension(format: BinaryFormat) []const u8 { + return switch (format) { + .elf => ".elf", + .bin => ".bin", + .hex => ".hex", + .dfu => ".dfu", + .uf2 => ".uf2", + .esp => ".bin", + + .custom => |c| c.extension, }; } -}; -pub const EmbeddedExecutable = struct { - inner: *LibExeObjStep, + pub const Custom = struct { + /// The standard extension of the format. + extension: []const u8, - pub const AppDependencyOptions = struct { - depend_on_microzig: bool = false, + /// A function that will convert a given `elf` file into the custom output format. + /// + /// The `*Custom` format is passed so contextual information can be obtained by using + /// `@fieldParentPtr` to provide access to tooling. + convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath, }; - pub fn addAppDependency(exe: *EmbeddedExecutable, name: []const u8, module: *Module, options: AppDependencyOptions) void { - if (options.depend_on_microzig) { - const microzig_module = exe.inner.modules.get("microzig").?; - module.dependencies.put("microzig", microzig_module) catch @panic("OOM"); + const Enum = std.meta.Tag(BinaryFormat); + + const Context = struct { + pub fn hash(self: @This(), fmt: BinaryFormat) u32 { + _ = self; + + var hasher = std.hash.XxHash32.init(0x1337_42_21); + + hasher.update(@tagName(fmt)); + + switch (fmt) { + .elf, .bin, .hex, .dfu, .esp => |val| { + if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!"); + }, + + .uf2 => |family_id| hasher.update(@tagName(family_id)), + .custom => |custom| hasher.update(std.mem.asBytes(custom)), + } + + return hasher.final(); } - const app_module = exe.inner.modules.get("app").?; - app_module.dependencies.put(name, module) catch @panic("OOM"); - } + pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool { + _ = self; + _ = index; + if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b)) + return false; - pub fn installArtifact(exe: *EmbeddedExecutable, b: *Build) void { - b.installArtifact(exe.inner); - } + return switch (fmt_a) { + .elf, .bin, .hex, .dfu, .esp => |val| { + if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!"); + return true; + }, - pub fn addIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void { - exe.inner.addIncludePath(path); - } + .uf2 => |a| (a == fmt_b.uf2), + .custom => |a| (a == fmt_b.custom), + }; + } + }; +}; - pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void { - return exe.inner.addSystemIncludePath(path); +/// The CPU model a target uses. +/// +/// The CPUs usually require special care on how to do interrupts, and getting an entry point. +/// +/// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided +/// via the `custom` field. +pub const CpuModel = union(enum) { + avr5, + cortex_m0, + cortex_m0plus, + cortex_m3, + cortex_m4, + riscv32_imac, + + custom: *const Cpu, + + pub fn getDescriptor(model: CpuModel) *const Cpu { + return switch (@as(std.meta.Tag(CpuModel), model)) { + inline else => |tag| &@field(cpus, @tagName(tag)), + .custom => model.custom, + }; } +}; - pub fn addCSourceFile(exe: *EmbeddedExecutable, source: Build.Step.Compile.CSourceFile) void { - exe.inner.addCSourceFile(source); - } +/// A cpu descriptor. +pub const Cpu = struct { + /// Display name of the CPU. + name: []const u8, - pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *OptionsStep) void { - exe.inner.addOptions(module_name, options); - const app_module = exe.inner.modules.get("app").?; - const opt_module = exe.inner.modules.get(module_name).?; - app_module.dependencies.put(module_name, opt_module) catch @panic("OOM"); - } + /// Source file providing startup code and memory initialization routines. + source_file: std.build.LazyPath, - pub fn addObjectFile(exe: *EmbeddedExecutable, source: LazyPath) void { - exe.inner.addObjectFile(source); - } + /// The compiler target we use to compile all the code. + target: std.zig.CrossTarget, }; -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} +/// A descriptor for memory regions in a microcontroller. +pub const MemoryRegion = struct { + /// The type of the memory region for generating a proper linker script. + kind: Kind, + offset: u64, + length: u64, + + pub const Kind = union(enum) { + /// This is a (normally) immutable memory region where the code is stored. + flash, + + /// This is a mutable memory region for data storage. + ram, + + /// This is a memory region that maps MMIO devices. + io, + + /// This is a memory region that exists, but is reserved and must not be used. + reserved, + + /// This is a memory region used for internal linking tasks required by the board support package. + private: PrivateRegion, + }; + + pub const PrivateRegion = struct { + /// The name of the memory region. Will not have an automatic numeric counter and must be unique. + name: []const u8, + + /// Is the memory region executable? + executable: bool, + + /// Is the memory region readable? + readable: bool, -pub const EmbeddedExecutableOptions = struct { + /// Is the memory region writable? + writeable: bool, + }; +}; + +/// Defines a custom microcontroller. +pub const Chip = struct { + /// The display name of the controller. name: []const u8, - source_file: LazyPath, - backing: Backing, - optimize: std.builtin.OptimizeMode = .Debug, - linkerscript_source_file: ?LazyPath = null, + + /// (optional) link to the documentation/vendor page of the controller. + url: ?[]const u8 = null, + + /// The cpu model this controller uses. + cpu: CpuModel, + + /// The provider for register definitions. + register_definition: union(enum) { + /// Use `regz` to create a zig file from a JSON schema. + json: std.Build.LazyPath, + + /// Use `regz` to create a json file from a SVD schema. + svd: std.Build.LazyPath, + + /// Use `regz` to create a zig file from an ATDF schema. + atdf: std.Build.LazyPath, + + /// Use the provided file directly as the chip file. + zig: std.Build.LazyPath, + }, + + /// The memory regions that are present in this chip. + memory_regions: []const MemoryRegion, }; -pub fn addEmbeddedExecutable(b: *Build, opts: EmbeddedExecutableOptions) *EmbeddedExecutable { - const has_board = (opts.backing == .board); - const chip = switch (opts.backing) { - .chip => |chip| chip, - .board => |board| board.chip, - }; +/// Defines a hardware abstraction layer. +pub const HardwareAbstractionLayer = struct { + /// Root source file for this HAL. + source_file: std.Build.LazyPath, +}; + +/// Provides a description of a board. +/// +/// Boards provide additional information to a chip and HAL package. +/// For example, they can list attached peripherials, external crystal frequencies, +/// flash sizes, ... +pub const BoardDefinition = struct { + /// Display name of the board + name: []const u8, + + /// (optional) link to the documentation/vendor page of the board. + url: ?[]const u8 = null, + + /// Provides the root file for the board definition. + source_file: std.Build.LazyPath, +}; + +/// The linker script used to link the firmware. +pub const LinkerScript = union(enum) { + /// Auto-generated linker script derived from the memory regions of the chip. + generated, + + /// Externally defined linker script. + source_file: std.build.LazyPath, +}; + +/// A compilation target for MicroZig. Provides information about the chip, +/// hal, board and so on. +/// +/// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware. +pub const Target = struct { + /// The preferred binary format of this MicroZig target. If `null`, the user must + /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps. + preferred_format: ?BinaryFormat, + + /// The chip this target uses, + chip: Chip, + + /// Usually, embedded projects are single-threaded and single-core applications. Platforms that + /// support multiple CPUs should set this to `false`. + single_threaded: bool = true, + + /// Determines whether the compiler_rt package is bundled with the application or not. + /// This should always be true except for platforms where compiler_rt cannot be built right now. + bundle_compiler_rt: bool = true, + + /// (optional) Provides a default hardware abstraction layer that is used. + /// If `null`, no `microzig.hal` will be available. + hal: ?HardwareAbstractionLayer = null, + + /// (optional) Provides description of external hardware and connected devices + /// like oscillators and such. + /// + /// This structure isn't used by MicroZig itself, but can be utilized from the HAL + /// if present. + board: ?BoardDefinition = null, + + /// (optional) Provide a custom linker script for the hardware or define a custom generation. + linker_script: LinkerScript = .generated, + + /// (optional) Further configures the created firmware depending on the chip and/or board settings. + /// This can be used to set/change additional properties on the created `*Firmware` object. + configure: ?*const fn (host_build: *std.Build, *Firmware) void = null, - const has_hal = chip.hal != null; + /// (optional) Post processing step that will patch up and modify the elf file if necessary. + binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null, +}; + +/// Options to the `addFirmware` function. +pub const FirmwareOptions = struct { + /// The name of the firmware file. + name: []const u8, + + /// The MicroZig target that the firmware is built for. Either a board or a chip. + target: Target, + + /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice. + /// Also using `std.Build.standardOptimizeOption` is a good idea. + optimize: std.builtin.OptimizeMode, + + /// The root source file for the application. This is your `src/main.zig` file. + source_file: std.Build.LazyPath, + + // Overrides: + + /// If set, overrides the `single_threaded` property of the target. + single_threaded: ?bool = null, + + /// If set, overrides the `bundle_compiler_rt` property of the target. + bundle_compiler_rt: ?bool = null, + + /// If set, overrides the `hal` property of the target. + hal: ?HardwareAbstractionLayer = null, + + /// If set, overrides the `board` property of the target. + board: ?BoardDefinition = null, + + /// If set, overrides the `linker_script` property of the target. + linker_script: ?LinkerScript = null, +}; + +/// Declares a new MicroZig firmware file. +pub fn addFirmware( + /// The MicroZig instance that should be used to create the firmware. + mz: *MicroZig, + /// The instance of the `build.zig` that is calling this function. + host_build: *std.Build, + /// Options that define how the firmware is built. + options: FirmwareOptions, +) *Firmware { + const micro_build = mz.self.builder; + + const chip = &options.target.chip; + const cpu = chip.cpu.getDescriptor(); + const maybe_hal = options.hal orelse options.target.hal; + const maybe_board = options.board orelse options.target.board; + + const linker_script = options.linker_script orelse options.target.linker_script; // TODO: let the user override which ram section to use the stack on, // for now just using the first ram section in the memory region list @@ -104,142 +426,551 @@ pub fn addEmbeddedExecutable(b: *Build, opts: EmbeddedExecutableOptions) *Embedd } else @panic("no ram memory region found for setting the end-of-stack address"); }; - const config = b.addOptions(); - config.addOption(bool, "has_hal", has_hal); - config.addOption(bool, "has_board", has_board); - if (has_board) - config.addOption([]const u8, "board_name", opts.backing.board.name); + // On demand, generate chip definitions via regz: + const chip_source = switch (chip.register_definition) { + .json, .atdf, .svd => |file| blk: { + const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz"); + + const regz_gen = host_build.addRunArtifact(regz_exe); + + regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json + regz_gen.addArg(@tagName(chip.register_definition)); + + regz_gen.addArg("--output_path"); // Write to a file + const zig_file = regz_gen.addOutputFileArg("chip.zig"); + + regz_gen.addFileArg(file); + + break :blk zig_file; + }, + + .zig => |src| src, + }; + + const config = host_build.addOptions(); + config.addOption(bool, "has_hal", (maybe_hal != null)); + config.addOption(bool, "has_board", (maybe_board != null)); + + config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null); config.addOption([]const u8, "chip_name", chip.name); config.addOption([]const u8, "cpu_name", chip.name); config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length); - const microzig_module = b.createModule(.{ - .source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/microzig.zig", .{root_dir()}) }, - }); + const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory"); + fw.* = Firmware{ + .mz = mz, + .host_build = host_build, + .artifact = host_build.addExecutable(.{ + .name = options.name, + .optimize = options.optimize, + .target = cpu.target, + .linkage = .static, + .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") }, + }), + .target = options.target, + .output_files = Firmware.OutputFileMap.init(host_build.allocator), + + .config = config, - microzig_module.dependencies.put("config", b.createModule(.{ - .source_file = config.getSource(), - })) catch unreachable; + .modules = .{ + .microzig = micro_build.createModule(.{ + .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") }, + .dependencies = &.{ + .{ + .name = "config", + .module = micro_build.createModule(.{ .source_file = config.getSource() }), + }, + }, + }), + + .cpu = undefined, + .chip = undefined, + + .board = null, + .hal = null, - microzig_module.dependencies.put("chip", b.createModule(.{ - .source_file = chip.source, + .app = undefined, + }, + }; + errdefer fw.output_files.deinit(); + + fw.modules.chip = micro_build.createModule(.{ + .source_file = chip_source, .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, + .{ .name = "microzig", .module = fw.modules.microzig }, }, - })) catch unreachable; + }); + fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory"); - microzig_module.dependencies.put("cpu", b.createModule(.{ - .source_file = chip.cpu.source, + fw.modules.cpu = micro_build.createModule(.{ + .source_file = cpu.source_file, .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, + .{ .name = "microzig", .module = fw.modules.microzig }, }, - })) catch unreachable; + }); + fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory"); - if (chip.hal) |hal_module_source| { - microzig_module.dependencies.put("hal", b.createModule(.{ - .source_file = hal_module_source, + if (maybe_hal) |hal| { + fw.modules.hal = micro_build.createModule(.{ + .source_file = hal.source_file, .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, + .{ .name = "microzig", .module = fw.modules.microzig }, }, - })) catch unreachable; + }); + fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory"); } - switch (opts.backing) { - .board => |board| { - microzig_module.dependencies.put("board", b.createModule(.{ - .source_file = board.source, - .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, - }, - })) catch unreachable; - }, - else => {}, + if (maybe_board) |brd| { + fw.modules.board = micro_build.createModule(.{ + .source_file = brd.source_file, + .dependencies = &.{ + .{ .name = "microzig", .module = fw.modules.microzig }, + }, + }); + fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory"); } - const app_module = b.createModule(.{ - .source_file = opts.source_file, + fw.modules.app = host_build.createModule(.{ + .source_file = options.source_file, .dependencies = &.{ - .{ .name = "microzig", .module = microzig_module }, + .{ .name = "microzig", .module = fw.modules.microzig }, }, }); - const exe = b.allocator.create(EmbeddedExecutable) catch unreachable; - exe.* = EmbeddedExecutable{ - .inner = b.addExecutable(.{ - .name = opts.name, - .root_source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/start.zig", .{root_dir()}) }, - .target = chip.cpu.target, - .optimize = opts.optimize, - }), - }; - exe.inner.addModule("app", app_module); - exe.inner.addModule("microzig", microzig_module); + fw.artifact.addModule("app", fw.modules.app); + fw.artifact.addModule("microzig", fw.modules.microzig); - exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded + fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded + fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded; + fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt; - // might not be true for all machines (Pi Pico), but - // for the HAL it's true (it doesn't know the concept of threading) - exe.inner.single_threaded = true; + switch (linker_script) { + .generated => { + fw.artifact.setLinkerScript( + generateLinkerScript(host_build, chip.*) catch @panic("out of memory"), + ); + }, - if (opts.linkerscript_source_file) |linkerscript_source_file| { - exe.inner.setLinkerScriptPath(linkerscript_source_file); - } else { - const linkerscript = LinkerScriptStep.create(b, chip) catch unreachable; - exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file }); + .source_file => |source| { + fw.artifact.setLinkerScriptPath(source); + }, } - // TODO: - // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones. - // - This requires building another tool that runs on the host that compiles those files and emits the linker script. - // - src/tools/linkerscript-gen.zig is the source file for this - exe.inner.bundle_compiler_rt = (exe.inner.target.getCpuArch() != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now + if (options.target.configure) |configure| { + configure(host_build, fw); + } - return exe; + return fw; } -/// This build script validates usage patterns we expect from MicroZig -pub fn build(b: *Build) !void { - const backings = @import("test/backings.zig"); - const optimize = b.standardOptimizeOption(.{}); - - const minimal = addEmbeddedExecutable(b, .{ - .name = "minimal", - .source_file = .{ - .path = comptime root_dir() ++ "/test/programs/minimal.zig", - }, - .backing = backings.minimal, - .optimize = optimize, +/// Configuration options for firmware installation. +pub const InstallFirmwareOptions = struct { + /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used. + format: ?BinaryFormat = null, +}; + +/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`. +pub fn installFirmware( + /// The MicroZig instance that was used to create the firmware. + mz: *MicroZig, + /// The instance of the `build.zig` that should perform installation. + b: *std.Build, + /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`. + firmware: *Firmware, + /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here. + options: InstallFirmwareOptions, +) void { + std.debug.assert(mz == firmware.mz); + const install_step = addInstallFirmware(mz, b, firmware, options); + b.getInstallStep().dependOn(&install_step.step); +} + +/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`. +/// +/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step. +/// If you want to just install the firmware, use `installFirmware` instead! +pub fn addInstallFirmware( + /// The MicroZig instance that was used to create the firmware. + mz: *MicroZig, + /// The instance of the `build.zig` that should perform installation. + b: *std.Build, + /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`. + firmware: *Firmware, + /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here. + options: InstallFirmwareOptions, +) *std.Build.Step.InstallFile { + const format = firmware.resolveFormat(options.format); + + const basename = b.fmt("{s}{s}", .{ + firmware.artifact.name, + format.getExtension(), }); - const has_hal = addEmbeddedExecutable(b, .{ - .name = "has_hal", - .source_file = .{ - .path = comptime root_dir() ++ "/test/programs/has_hal.zig", + _ = mz; + + return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename); +} + +/// Declaration of a firmware build. +pub const Firmware = struct { + const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false); + + const Modules = struct { + app: *std.Build.Module, + cpu: *std.Build.Module, + chip: *std.Build.Module, + board: ?*std.Build.Module, + hal: ?*std.Build.Module, + microzig: *std.Build.Module, + }; + + // privates: + mz: *MicroZig, + host_build: *std.Build, + target: Target, + output_files: OutputFileMap, + + // publics: + + /// The artifact that is built by Zig. + artifact: *std.Build.Step.Compile, + + /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here. + config: *std.Build.Step.Options, + + /// Declaration of the MicroZig modules used by this firmware. + modules: Modules, + + /// Path to the emitted elf file, if any. + emitted_elf: ?std.Build.LazyPath = null, + + /// Returns the emitted ELF file for this firmware. This is useful if you need debug information + /// or want to use a debugger like Segger, ST-Link or similar. + /// + /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does + /// not include post processing of the ELF files necessary by certain targets. + pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath { + if (firmware.emitted_elf == null) { + const raw_elf = firmware.artifact.getEmittedBin(); + firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process| + binary_post_process(firmware.host_build, raw_elf) + else + raw_elf; + } + return firmware.emitted_elf.?; + } + + /// Returns the emitted binary for this firmware. The file is either in the preferred file format for + /// the target or in `format` if not null. + /// + /// **NOTE:** The file returned here is the same file that will be installed. + pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath { + const actual_format = firmware.resolveFormat(format); + + const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory"); + if (!gop.found_existing) { + const elf_file = firmware.getEmittedElf(); + + const basename = firmware.host_build.fmt("{s}{s}", .{ + firmware.artifact.name, + actual_format.getExtension(), + }); + + gop.value_ptr.* = switch (actual_format) { + .elf => elf_file, + + .bin => blk: { + const objcopy = firmware.host_build.addObjCopy(elf_file, .{ + .basename = basename, + .format = .bin, + }); + + break :blk objcopy.getOutput(); + }, + + .hex => blk: { + const objcopy = firmware.host_build.addObjCopy(elf_file, .{ + .basename = basename, + .format = .hex, + }); + + break :blk objcopy.getOutput(); + }, + + .uf2 => |family_id| blk: { + const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2"); + + const convert = firmware.host_build.addRunArtifact(uf2_exe); + + convert.addArg("--family-id"); + convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)})); + + convert.addArg("--elf-path"); + convert.addFileArg(elf_file); + + convert.addArg("--output-path"); + break :blk convert.addOutputFileArg(basename); + }, + + .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}), + .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}), + + .custom => |generator| generator.convert(generator, elf_file), + }; + } + return gop.value_ptr.*; + } + + pub const AppDependencyOptions = struct { + depend_on_microzig: bool = false, + }; + + /// Adds a regular dependency to your application. + pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void { + if (options.depend_on_microzig) { + module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM"); + } + fw.modules.app.dependencies.put(name, module) catch @panic("OOM"); + } + + pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void { + fw.artifact.addIncludePath(path); + } + + pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void { + fw.artifact.addSystemIncludePath(path); + } + + pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void { + fw.artifact.addCSourceFile(source); + } + + pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void { + fw.artifact.addOptions(module_name, options); + fw.modules.app.dependencies.put( + module_name, + fw.host_build.createModule(.{ + .source_file = options.getOutput(), + }), + ) catch @panic("OOM"); + } + + pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void { + fw.artifact.addObjectFile(source); + } + + fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat { + if (format) |fmt| return fmt; + + if (firmware.target.preferred_format) |fmt| return fmt; + + buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{ + firmware.target.chip.name, + }); + } +}; + +pub const cpus = struct { + pub const avr5 = Cpu{ + .name = "AVR5", + .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .avr, + .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, + .os_tag = .freestanding, + .abi = .eabi, }, - .backing = backings.has_hal, - .optimize = optimize, - }); + }; - const has_board = addEmbeddedExecutable(b, .{ - .name = "has_board", - .source_file = .{ - .path = comptime root_dir() ++ "/test/programs/has_board.zig", + pub const cortex_m0 = Cpu{ + .name = "ARM Cortex-M0", + .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, + .os_tag = .freestanding, + .abi = .none, }, - .backing = backings.has_board, - .optimize = optimize, - }); + }; + + pub const cortex_m0plus = Cpu{ + .name = "ARM Cortex-M0+", + .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .none, + }, + }; + + pub const cortex_m3 = Cpu{ + .name = "ARM Cortex-M3", + .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, + .os_tag = .freestanding, + .abi = .none, + }, + }; + + pub const cortex_m4 = Cpu{ + .name = "ARM Cortex-M4", + .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, + .os_tag = .freestanding, + .abi = .none, + }, + }; - const core_tests = b.addTest(.{ - .root_source_file = .{ - .path = comptime root_dir() ++ "/src/core.zig", + pub const riscv32_imac = Cpu{ + .name = "RISC-V 32-bit", + .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" }, + .target = std.zig.CrossTarget{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, + .os_tag = .freestanding, + .abi = .none, }, - .optimize = optimize, + }; +}; + +fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn { + const msg = b.fmt(fmt, args); + @panic(msg); +} + +fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency { + return mz.self.builder.dependency(name, args); +} + +fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath { + const cpu = chip.cpu.getDescriptor(); + + var contents = std.ArrayList(u8).init(b.allocator); + const writer = contents.writer(); + try writer.print( + \\/* + \\ * This file was auto-generated by microzig + \\ * + \\ * Target CPU: {[cpu]s} + \\ * Target Chip: {[chip]s} + \\ */ + \\ + // This is not the "true" entry point, but there's no such thing on embedded platforms + // anyways. This is the logical entrypoint that should be invoked when + // stack, .data and .bss are set up and the CPU is ready to be used. + \\ENTRY(microzig_main); + \\ + \\ + , .{ + .cpu = cpu.name, + .chip = chip.name, }); - const test_step = b.step("test", "build test programs"); - test_step.dependOn(&minimal.inner.step); - test_step.dependOn(&has_hal.inner.step); - test_step.dependOn(&has_board.inner.step); - test_step.dependOn(&b.addRunArtifact(core_tests).step); + try writer.writeAll("MEMORY\n{\n"); + { + var counters = [4]usize{ 0, 0, 0, 0 }; + for (chip.memory_regions) |region| { + // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k + + switch (region.kind) { + .flash => { + try writer.print(" flash{d} (rx!w)", .{counters[0]}); + counters[0] += 1; + }, + + .ram => { + try writer.print(" ram{d} (rw!x)", .{counters[1]}); + counters[1] += 1; + }, + + .io => { + try writer.print(" io{d} (rw!x)", .{counters[2]}); + counters[2] += 1; + }, + + .reserved => { + try writer.print(" reserved{d} (rw!x)", .{counters[3]}); + counters[3] += 1; + }, + + .private => |custom| { + try writer.print(" {s} (", .{custom.name}); + if (custom.readable) try writer.writeAll("r"); + if (custom.writeable) try writer.writeAll("w"); + if (custom.executable) try writer.writeAll("x"); + + if (!custom.readable or !custom.writeable or !custom.executable) { + try writer.writeAll("!"); + if (!custom.readable) try writer.writeAll("r"); + if (!custom.writeable) try writer.writeAll("w"); + if (!custom.executable) try writer.writeAll("x"); + } + try writer.writeAll(")"); + }, + } + try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length }); + } + } + + try writer.writeAll("}\n\nSECTIONS\n{\n"); + { + try writer.writeAll( + \\ .text : + \\ { + \\ KEEP(*(microzig_flash_start)) + \\ *(.text*) + \\ } > flash0 + \\ + \\ + ); + + switch (cpu.target.getCpuArch()) { + .arm, .thumb => try writer.writeAll( + \\ .ARM.exidx : { + \\ *(.ARM.exidx* .gnu.linkonce.armexidx.*) + \\ } >flash0 + \\ + \\ + ), + else => {}, + } + + try writer.writeAll( + \\ .data : + \\ { + \\ microzig_data_start = .; + \\ *(.rodata*) + \\ *(.data*) + \\ microzig_data_end = .; + \\ } > ram0 AT> flash0 + \\ + \\ .bss (NOLOAD) : + \\ { + \\ microzig_bss_start = .; + \\ *(.bss*) + \\ microzig_bss_end = .; + \\ } > ram0 + \\ + \\ microzig_data_load_start = LOADADDR(.data); + \\ + ); + } + try writer.writeAll("}\n"); + + // TODO: Assert that the flash can actually hold all data! + // try writer.writeAll( + // \\ + // \\ ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" ); + // \\ + // ); + + const write = b.addWriteFiles(); + + return write.add("linker.ld", contents.items); } diff --git a/build.zig.zon b/build.zig.zon new file mode 100644 index 0000000..5f0ac76 --- /dev/null +++ b/build.zig.zon @@ -0,0 +1,14 @@ +.{ + .name = "microzig", + .version = "0.1.0", + .dependencies = .{ + .uf2 = .{ + .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/c523a4d23469282f95658a879f5ba925757dc9d9.tar.gz", + .hash = "12208530bdc194e8c1f3405ad681a409c7fabfe82735cd3972ec07c221a7786db03a", + }, + .regz = .{ + .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz", + .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2", + }, + }, +} diff --git a/src/modules/cpus/avr5.zig b/src/cpus/avr5.zig similarity index 100% rename from src/modules/cpus/avr5.zig rename to src/cpus/avr5.zig diff --git a/src/modules/cpus/cortex-m.zig b/src/cpus/cortex-m.zig similarity index 100% rename from src/modules/cpus/cortex-m.zig rename to src/cpus/cortex-m.zig diff --git a/src/modules/cpus/riscv32.zig b/src/cpus/riscv32.zig similarity index 100% rename from src/modules/cpus/riscv32.zig rename to src/cpus/riscv32.zig diff --git a/src/modules/Board.zig b/src/modules/Board.zig deleted file mode 100644 index 8e09b4a..0000000 --- a/src/modules/Board.zig +++ /dev/null @@ -1,6 +0,0 @@ -const std = @import("std"); -const Chip = @import("Chip.zig"); - -name: []const u8, -source: std.build.LazyPath, -chip: Chip, diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig deleted file mode 100644 index 3676fc9..0000000 --- a/src/modules/Chip.zig +++ /dev/null @@ -1,44 +0,0 @@ -const std = @import("std"); -const LazyPath = std.build.LazyPath; - -const MemoryRegion = @import("MemoryRegion.zig"); -const Cpu = @import("Cpu.zig"); - -const Chip = @This(); - -name: []const u8, -source: LazyPath, -cpu: Cpu, -hal: ?LazyPath = null, -json_register_schema: ?LazyPath = null, -memory_regions: []const MemoryRegion, - -pub fn from_standard_paths(comptime root_dir: []const u8, args: struct { - name: []const u8, - cpu: Cpu, - memory_regions: []const MemoryRegion, -}) Chip { - return Chip{ - .name = args.name, - .cpu = args.cpu, - .memory_regions = args.memory_regions, - .source = .{ - .path = std.fmt.comptimePrint("{s}/chips/{s}.zig", .{ - root_dir, - args.name, - }), - }, - .hal = .{ - .path = std.fmt.comptimePrint("{s}/hals/{s}.zig", .{ - root_dir, - args.name, - }), - }, - .json_register_schema = .{ - .path = std.fmt.comptimePrint("{s}/chips/{s}.json", .{ - root_dir, - args.name, - }), - }, - }; -} diff --git a/src/modules/Cpu.zig b/src/modules/Cpu.zig deleted file mode 100644 index e4cd307..0000000 --- a/src/modules/Cpu.zig +++ /dev/null @@ -1,5 +0,0 @@ -const std = @import("std"); - -name: []const u8, -source: std.build.LazyPath, -target: std.zig.CrossTarget, diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig deleted file mode 100644 index fb92277..0000000 --- a/src/modules/LinkerScriptStep.zig +++ /dev/null @@ -1,172 +0,0 @@ -const std = @import("std"); -const MemoryRegion = @import("MemoryRegion.zig"); -const Chip = @import("Chip.zig"); -const Step = std.build.Step; -const Build = std.Build; -const GeneratedFile = std.build.GeneratedFile; - -const LinkerscriptStep = @This(); - -step: Step, -generated_file: std.build.GeneratedFile, -chip: Chip, - -pub fn create(owner: *Build, chip: Chip) !*LinkerscriptStep { - var linkerscript = try owner.allocator.create(LinkerscriptStep); - linkerscript.* = LinkerscriptStep{ - .step = Step.init(.{ - .id = .custom, - .name = "linkerscript", - .owner = owner, - .makeFn = make, - }), - .generated_file = .{ - .step = &linkerscript.step, - }, - .chip = chip, - }; - - return linkerscript; -} - -fn make(step: *Step, _: *std.Progress.Node) anyerror!void { - const linkerscript = @fieldParentPtr(LinkerscriptStep, "step", step); - - const owner = linkerscript.step.owner; - const target = linkerscript.chip.cpu.target; - - var contents = std.ArrayList(u8).init(owner.allocator); - const writer = contents.writer(); - try writer.print( - \\/* - \\ * This file was auto-generated by microzig - \\ * - \\ * Target CPU: {s} - \\ * Target Chip: {s} - \\ */ - \\ - // This is not the "true" entry point, but there's no such thing on embedded platforms - // anyways. This is the logical entrypoint that should be invoked when - // stack, .data and .bss are set up and the CPU is ready to be used. - \\ENTRY(microzig_main); - \\ - \\ - , .{ linkerscript.chip.cpu.name, linkerscript.chip.name }); - - try writer.writeAll("MEMORY\n{\n"); - { - var counters = [2]usize{ 0, 0 }; - for (linkerscript.chip.memory_regions) |region| { - // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k - - switch (region.kind) { - .flash => { - try writer.print(" flash{d} (rx!w)", .{counters[0]}); - counters[0] += 1; - }, - .ram => { - try writer.print(" ram{d} (rw!x)", .{counters[1]}); - counters[1] += 1; - }, - .custom => |custom| { - try writer.print(" {s} (", .{custom.name}); - if (custom.readable) try writer.writeAll("r"); - if (custom.writeable) try writer.writeAll("w"); - if (custom.executable) try writer.writeAll("x"); - - if (!custom.readable or !custom.writeable or !custom.executable) { - try writer.writeAll("!"); - if (!custom.readable) try writer.writeAll("r"); - if (!custom.writeable) try writer.writeAll("w"); - if (!custom.executable) try writer.writeAll("x"); - } - try writer.writeAll(")"); - }, - } - try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length }); - } - } - - try writer.writeAll("}\n\nSECTIONS\n{\n"); - { - try writer.writeAll( - \\ .text : - \\ { - \\ KEEP(*(microzig_flash_start)) - \\ *(.text*) - \\ } > flash0 - \\ - \\ - ); - - switch (target.getCpuArch()) { - .arm, .thumb => try writer.writeAll( - \\ .ARM.exidx : { - \\ *(.ARM.exidx* .gnu.linkonce.armexidx.*) - \\ } >flash0 - \\ - \\ - ), - else => {}, - } - - try writer.writeAll( - \\ .data : - \\ { - \\ microzig_data_start = .; - \\ *(.rodata*) - \\ *(.data*) - \\ microzig_data_end = .; - \\ } > ram0 AT> flash0 - \\ - \\ .bss (NOLOAD) : - \\ { - \\ microzig_bss_start = .; - \\ *(.bss*) - \\ microzig_bss_end = .; - \\ } > ram0 - \\ - \\ microzig_data_load_start = LOADADDR(.data); - \\ - ); - } - try writer.writeAll("}\n"); - - // TODO: Assert that the flash can actually hold all data! - // try writer.writeAll( - // \\ - // \\ ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" ); - // \\ - // ); - - const filename = try std.fmt.allocPrint(owner.allocator, "{s}_{s}.ld", .{ - linkerscript.chip.name, - linkerscript.chip.cpu.name, - }); - - var hash = owner.cache.hash; - hash.addBytes(linkerscript.chip.name); - hash.addBytes(linkerscript.chip.cpu.name); - - // TODO: hash more information to reduce chance of collision - for (linkerscript.chip.memory_regions) |memory_region| { - hash.add(memory_region.offset); - hash.add(memory_region.length); - } - - const digest = hash.final(); - const dir_path = try owner.cache_root.join(owner.allocator, &.{ - "microzig", - &digest, - }); - - var dir = try owner.cache_root.handle.makeOpenPath(dir_path, .{}); - defer dir.close(); - - const file = try dir.createFile(filename, .{}); - defer file.close(); - - try file.writeAll(contents.items); - const full_path = owner.pathJoin(&.{ dir_path, filename }); - linkerscript.generated_file.path = full_path; -} diff --git a/src/modules/MemoryRegion.zig b/src/modules/MemoryRegion.zig deleted file mode 100644 index 048b2b5..0000000 --- a/src/modules/MemoryRegion.zig +++ /dev/null @@ -1,18 +0,0 @@ -//! This module is meant to be used to define linking apis - -kind: Kind, -offset: u64, -length: u64, - -pub const Kind = union(enum) { - flash, - ram, - custom: RegionSpec, -}; - -pub const RegionSpec = struct { - name: []const u8, - executable: bool, - readable: bool, - writeable: bool, -}; diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig deleted file mode 100644 index a2cf396..0000000 --- a/src/modules/cpus.zig +++ /dev/null @@ -1,84 +0,0 @@ -const std = @import("std"); -const Cpu = @import("Cpu.zig"); - -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse "."; -} - -pub const avr5 = Cpu{ - .name = "AVR5", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/avr5.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .avr, - .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 }, - .os_tag = .freestanding, - .abi = .eabi, - }, -}; - -pub const cortex_m0 = Cpu{ - .name = "ARM Cortex-M0", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, - .os_tag = .freestanding, - .abi = .none, - }, -}; - -pub const cortex_m0plus = Cpu{ - .name = "ARM Cortex-M0+", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, - .os_tag = .freestanding, - .abi = .none, - }, -}; - -pub const cortex_m3 = Cpu{ - .name = "ARM Cortex-M3", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, - .os_tag = .freestanding, - .abi = .none, - }, -}; - -pub const cortex_m4 = Cpu{ - .name = "ARM Cortex-M4", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .thumb, - .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, - .os_tag = .freestanding, - .abi = .none, - }, -}; - -pub const riscv32_imac = Cpu{ - .name = "RISC-V 32-bit", - .source = .{ - .path = std.fmt.comptimePrint("{s}/cpus/riscv32.zig", .{root_dir()}), - }, - .target = std.zig.CrossTarget{ - .cpu_arch = .riscv32, - .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 }, - .os_tag = .freestanding, - .abi = .none, - }, -}; From d361a622baeaf827831507163f5fba090e049b65 Mon Sep 17 00:00:00 2001 From: Vesim Date: Tue, 26 Sep 2023 17:57:22 +0200 Subject: [PATCH 132/138] add umm allocator (#148) --- build.zig | 3 +++ build.zig.zon | 4 ++++ src/core.zig | 2 ++ src/core/heap.zig | 5 +++++ 4 files changed, 14 insertions(+) create mode 100644 src/core/heap.zig diff --git a/build.zig b/build.zig index 9b92d6b..f801a55 100644 --- a/build.zig +++ b/build.zig @@ -538,6 +538,9 @@ pub fn addFirmware( }, }); + const umm = mz.dependency("umm-zig", .{}).module("umm"); + fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory"); + fw.artifact.addModule("app", fw.modules.app); fw.artifact.addModule("microzig", fw.modules.microzig); diff --git a/build.zig.zon b/build.zig.zon index 5f0ac76..e790e7d 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -10,5 +10,9 @@ .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz", .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2", }, + .@"umm-zig" = .{ + .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz", + .hash = "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f", + }, }, } diff --git a/src/core.zig b/src/core.zig index 10b26c2..232f0f7 100644 --- a/src/core.zig +++ b/src/core.zig @@ -1,7 +1,9 @@ pub const experimental = @import("core/experimental.zig"); +pub const heap = @import("core/heap.zig"); /// USB data types and helper functions pub const usb = @import("core/usb.zig"); test "core tests" { _ = usb; + _ = heap; } diff --git a/src/core/heap.zig b/src/core/heap.zig new file mode 100644 index 0000000..ae6501a --- /dev/null +++ b/src/core/heap.zig @@ -0,0 +1,5 @@ +pub const UmmAllocator = @import("umm").UmmAllocator; + +test "heap tests" { + _ = UmmAllocator; +} From f286bc8e25837131a4bc0eb0adb0ccb5175c3cd3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ardelean=20C=C4=83lin?= <9417983+Ardelean-Calin@users.noreply.github.com> Date: Tue, 26 Sep 2023 21:39:06 +0300 Subject: [PATCH 133/138] Corrected Cortex-M ABI (#149) --- build.zig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/build.zig b/build.zig index f801a55..748833f 100644 --- a/build.zig +++ b/build.zig @@ -793,7 +793,7 @@ pub const cpus = struct { .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 }, .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }, }; @@ -804,7 +804,7 @@ pub const cpus = struct { .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }, }; @@ -815,7 +815,7 @@ pub const cpus = struct { .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 }, .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }, }; @@ -826,7 +826,7 @@ pub const cpus = struct { .cpu_arch = .thumb, .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 }, .os_tag = .freestanding, - .abi = .none, + .abi = .eabi, }, }; From 2873e9e0b109ce55aab083e56225c783f2b7ff2a Mon Sep 17 00:00:00 2001 From: Marnix Klooster Date: Thu, 26 Oct 2023 21:29:28 +0200 Subject: [PATCH 134/138] Change the HAL API to snake_case() from camelCase() (#151) --- src/core/experimental/debug.zig | 2 +- src/core/experimental/i2c.zig | 22 ++++++++++---------- src/core/experimental/spi.zig | 36 ++++++++++++++++----------------- src/core/experimental/uart.zig | 8 ++++---- 4 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/core/experimental/debug.zig b/src/core/experimental/debug.zig index c74bdba..767f8c3 100644 --- a/src/core/experimental/debug.zig +++ b/src/core/experimental/debug.zig @@ -30,7 +30,7 @@ const DebugWriter = std.io.Writer(void, DebugErr, writer_write); pub fn write(string: []const u8) void { if (!config.has_board) return; - if (!@hasDecl(board, "debugWrite")) + if (!@hasDecl(board, "debug_write")) return; board.debug_write(string); diff --git a/src/core/experimental/i2c.zig b/src/core/experimental/i2c.zig index 7eefcbd..52fbaa3 100644 --- a/src/core/experimental/i2c.zig +++ b/src/core/experimental/i2c.zig @@ -28,7 +28,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { } fn read_some(self: *Self, buffer: []u8) ReadError!usize { - try self.state.readNoEof(buffer); + try self.state.read_no_eof(buffer); return buffer.len; } @@ -41,7 +41,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// Note that some platforms set the repeated START condition /// on the first read or write call. pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { - return Transfer(direction){ .state = try self.state.restartTransfer(new_direction) }; + return Transfer(direction){ .state = try self.state.restart_transfer(new_direction) }; } }, .write => struct { @@ -59,7 +59,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { } fn write_some(self: *Self, buffer: []const u8) WriteError!usize { - try self.state.writeAll(buffer); + try self.state.write_all(buffer); return buffer.len; } @@ -73,8 +73,8 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// on the first read or write call. pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) { return switch (new_direction) { - .read => Transfer(new_direction){ .state = try self.state.restartRead() }, - .write => Transfer(new_direction){ .state = try self.state.restartWrite() }, + .read => Transfer(new_direction){ .state = try self.state.restart_read() }, + .write => Transfer(new_direction){ .state = try self.state.restart_write() }, }; } }, @@ -93,12 +93,12 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// Shorthand for 'register-based' devices pub fn write_register(self: Device, register_address: u8, byte: u8) ReadError!void { - try self.writeRegisters(register_address, &.{byte}); + try self.write_registers(register_address, &.{byte}); } /// Shorthand for 'register-based' devices - pub fn write_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void { - var wt = try self.startTransfer(.write); + pub fn write_registers(self: Device, register_address: u8, buffer: []const u8) ReadError!void { + var wt = try self.start_transfer(.write); defer wt.stop() catch {}; try wt.writer().writeByte(register_address); try wt.writer().writeAll(buffer); @@ -107,17 +107,17 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type { /// Shorthand for 'register-based' devices pub fn read_register(self: Device, register_address: u8) ReadError!u8 { var buffer: [1]u8 = undefined; - try self.readRegisters(register_address, &buffer); + try self.read_registers(register_address, &buffer); return buffer[0]; } /// Shorthand for 'register-based' devices pub fn read_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void { var rt = write_and_restart: { - var wt = try self.startTransfer(.write); + var wt = try self.start_transfer(.write); errdefer wt.stop() catch {}; try wt.writer().writeByte(1 << 7 | register_address); // MSB == 'keep sending until I STOP' - break :write_and_restart try wt.restartTransfer(.read); + break :write_and_restart try wt.restart_transfer(.read); }; defer rt.stop() catch {}; try rt.reader().readNoEof(buffer); diff --git a/src/core/experimental/spi.zig b/src/core/experimental/spi.zig index 250e747..7db6ab5 100644 --- a/src/core/experimental/spi.zig +++ b/src/core/experimental/spi.zig @@ -1,16 +1,16 @@ const std = @import("std"); -const micro = @import("microzig"); -const chip = @import("chip"); +const hal = @import("hal"); +const clock = @import("clock.zig"); // Is there a different/better way? /// The SPI bus with the given environment-specific number. /// Only 'master' mode is supported currently. pub fn SpiBus(comptime index: usize) type { - const SystemSpi = chip.SpiBus(index); + const SystemSpi = hal.SpiBus(index); return struct { /// A SPI 'slave' device, selected via the given CS pin. /// (Default is CS=low to select.) - pub fn SpiDevice(comptime cs_pin: type, config: DeviceConfig) type { + pub fn SpiDevice(comptime cs_pin: type, comptime config: DeviceConfig) type { return struct { const SelfSpiDevice = @This(); @@ -24,7 +24,7 @@ pub fn SpiBus(comptime index: usize) type { device: SelfSpiDevice, fn transceive_byte(self: *SelfTransfer, write_byte: u8, read_pointer: *u8) !void { - try self.device.internal.transceiveByte(write_byte, read_pointer); + try self.device.internal.transceive_byte(write_byte, read_pointer); } pub const Writer = std.io.Writer(*SelfTransfer, WriteError, write_some); @@ -35,7 +35,7 @@ pub fn SpiBus(comptime index: usize) type { } fn write_some(self: *SelfTransfer, buffer: []const u8) WriteError!usize { - try self.device.internal.writeAll(buffer); + try self.device.internal.write_all(buffer); return buffer.len; } @@ -47,40 +47,40 @@ pub fn SpiBus(comptime index: usize) type { } fn read_some(self: *SelfTransfer, buffer: []u8) ReadError!usize { - try self.device.internal.readInto(buffer); + try self.device.internal.read_into(buffer); return buffer.len; } /// end the current transfer, releasing via the CS pin pub fn end(self: *SelfTransfer) void { - self.device.internal.endTransfer(cs_pin, config); + self.device.internal.end_transfer(cs_pin, config); } }; /// start a new transfer, selecting using the CS pin pub fn begin_transfer(self: SelfSpiDevice) !Transfer { - self.internal.switchToDevice(cs_pin, config); - self.internal.beginTransfer(cs_pin, config); + self.internal.switch_to_device(cs_pin, config); + self.internal.begin_transfer(cs_pin, config); return Transfer{ .device = self }; } pub fn transceive(self: SelfSpiDevice, write_buffer: []const u8, read_buffer: []u8) !void { std.debug.assert(write_buffer.len == read_buffer.len); - var transfer = try self.beginTransfer(); + var transfer = try self.begin_transfer(); defer transfer.end(); for (write_buffer, 0..) |_, i| { - try transfer.transceiveByte(write_buffer[i], &read_buffer[i]); + try transfer.transceive_byte(write_buffer[i], &read_buffer[i]); } } /// Shorthand for 'register-based' devices pub fn write_register(self: SelfSpiDevice, register_address: u8, byte: u8) ReadError!void { - try self.writeRegisters(register_address, &.{byte}); + try self.write_registers(register_address, &.{byte}); } /// Shorthand for 'register-based' devices - pub fn write_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { - var transfer = try self.beginTransfer(); + pub fn write_registers(self: SelfSpiDevice, register_address: u8, buffer: []const u8) ReadError!void { + var transfer = try self.begin_transfer(); defer transfer.end(); // write auto-increment, starting at given register try transfer.writer().writeByte(0b01_000000 | register_address); @@ -90,13 +90,13 @@ pub fn SpiBus(comptime index: usize) type { /// Shorthand for 'register-based' devices pub fn read_register(self: SelfSpiDevice, register_address: u8) ReadError!u8 { var buffer: [1]u8 = undefined; - try self.readRegisters(register_address, &buffer); + try self.read_registers(register_address, &buffer); return buffer[0]; } /// Shorthand for 'register-based' devices pub fn read_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void { - var transfer = try self.beginTransfer(); + var transfer = try self.begin_transfer(); defer transfer.end(); // read auto-increment, starting at given register try transfer.writer().writeByte(0b11_000000 | register_address); @@ -111,7 +111,7 @@ pub fn SpiBus(comptime index: usize) type { /// Initialize this SPI bus and return a handle to it. pub fn init(config: BusConfig) InitError!SelfSpiBus { - micro.clock.ensure(); // TODO: Wat? + clock.ensure(); // TODO: Wat? return SelfSpiBus{ .internal = try SystemSpi.init(config), }; diff --git a/src/core/experimental/uart.zig b/src/core/experimental/uart.zig index bba29da..e64dd5e 100644 --- a/src/core/experimental/uart.zig +++ b/src/core/experimental/uart.zig @@ -20,21 +20,21 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type { /// If the UART is already initialized, try to return a handle to it, /// else initialize with the given config. pub fn get_or_init(config: Config) InitError!Self { - if (!@hasDecl(SystemUart, "getOrInit")) { + if (!@hasDecl(SystemUart, "get_or_init")) { // fallback to reinitializing the UART return init(config); } return Self{ - .internal = try SystemUart.getOrInit(config), + .internal = try SystemUart.get_or_init(config), }; } pub fn can_read(self: Self) bool { - return self.internal.canRead(); + return self.internal.can_read(); } pub fn can_write(self: Self) bool { - return self.internal.canWrite(); + return self.internal.can_write(); } pub fn reader(self: Self) Reader { From f8a506ccc28447ff6f20bba13ad04e7ce8d26318 Mon Sep 17 00:00:00 2001 From: Prince Bett <75972193+kodesafi@users.noreply.github.com> Date: Mon, 6 Nov 2023 22:13:50 +0300 Subject: [PATCH 135/138] doc: add getting started tip (#156) direct new users to microzig-examples for ease the onboarding experience. --- README.adoc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.adoc b/README.adoc index 903b390..d21a7d2 100644 --- a/README.adoc +++ b/README.adoc @@ -29,6 +29,10 @@ This repo contains the infrastructure for getting started in an embedded Zig pro * device drivers for interacting with external hardware * an uncomplicated method to define xref:interrupts[interrupts] +== Getting Started + +Visit https://github.com/ZigEmbeddedGroup/microzig-examples to find examples for your specific board. + == Design For MicroZig internals please see the xref:docs/design.adoc[Design Document]. From c3baa4a2777634a2b5cd366b87b453e9b72b4b26 Mon Sep 17 00:00:00 2001 From: Jacob Young Date: Mon, 20 Nov 2023 12:48:34 -0800 Subject: [PATCH 136/138] Update dependencies and add paths (#158) --- build.zig.zon | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/build.zig.zon b/build.zig.zon index e790e7d..a237901 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -1,14 +1,25 @@ .{ .name = "microzig", .version = "0.1.0", + .paths = .{ + "build.zig", + "build.zig.zon", + "design", + "docs", + "LICENSE", + "README.adoc", + "src", + "test", + "thoughts.md", + }, .dependencies = .{ .uf2 = .{ - .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/c523a4d23469282f95658a879f5ba925757dc9d9.tar.gz", - .hash = "12208530bdc194e8c1f3405ad681a409c7fabfe82735cd3972ec07c221a7786db03a", + .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/0550d4b1519264669b4ac5d944c370b41ebd6579.tar.gz", + .hash = "122058e26facbba3f6e06881ec0d356c7f9046e88edc46b9f244b50d366062528471", }, .regz = .{ - .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz", - .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2", + .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz", + .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823", }, .@"umm-zig" = .{ .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz", From 8ac1db65743a79a6794a77c4d14a777388a1780f Mon Sep 17 00:00:00 2001 From: Sreehari Sreedev Date: Tue, 21 Nov 2023 16:19:54 -0700 Subject: [PATCH 137/138] packed struct => extern struct for USB (#159) --- src/core/usb.zig | 12 ++++++------ src/core/usb/hid.zig | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/core/usb.zig b/src/core/usb.zig index 3d76c3b..a7b4e56 100644 --- a/src/core/usb.zig +++ b/src/core/usb.zig @@ -511,7 +511,7 @@ pub const Dir = enum(u8) { }; /// Describes an endpoint within an interface -pub const EndpointDescriptor = packed struct { +pub const EndpointDescriptor = extern struct { /// Length of this struct, must be 7. length: u8, /// Type of this descriptor, must be `Endpoint`. @@ -542,7 +542,7 @@ pub const EndpointDescriptor = packed struct { }; /// Description of an interface within a configuration. -pub const InterfaceDescriptor = packed struct { +pub const InterfaceDescriptor = extern struct { /// Length of this structure, must be 9. length: u8, /// Type of this descriptor, must be `Interface`. @@ -580,7 +580,7 @@ pub const InterfaceDescriptor = packed struct { }; /// Description of a single available device configuration. -pub const ConfigurationDescriptor = packed struct { +pub const ConfigurationDescriptor = extern struct { /// Length of this structure, must be 9. length: u8, /// Type of this descriptor, must be `Config`. @@ -625,7 +625,7 @@ pub const ConfigurationDescriptor = packed struct { /// Describes a device. This is the most broad description in USB and is /// typically the first thing the host asks for. -pub const DeviceDescriptor = packed struct { +pub const DeviceDescriptor = extern struct { /// Length of this structure, must be 18. length: u8, /// Type of this descriptor, must be `Device`. @@ -682,7 +682,7 @@ pub const DeviceDescriptor = packed struct { /// USB Device Qualifier Descriptor /// This descriptor is mostly the same as the DeviceDescriptor -pub const DeviceQualifierDescriptor = packed struct { +pub const DeviceQualifierDescriptor = extern struct { /// Length of this structure, must be 18. length: u8 = 10, /// Type of this descriptor, must be `Device`. @@ -720,7 +720,7 @@ pub const DeviceQualifierDescriptor = packed struct { }; /// Layout of an 8-byte USB SETUP packet. -pub const SetupPacket = packed struct { +pub const SetupPacket = extern struct { /// Request type; in practice, this is always either OUT (host-to-device) or /// IN (device-to-host), whose values are given in the `Dir` enum. request_type: u8, diff --git a/src/core/usb/hid.zig b/src/core/usb/hid.zig index e2c6d7f..c63e28a 100644 --- a/src/core/usb/hid.zig +++ b/src/core/usb/hid.zig @@ -87,7 +87,7 @@ pub const DescType = enum(u8) { }; /// USB HID descriptor -pub const HidDescriptor = packed struct { +pub const HidDescriptor = extern struct { length: u8 = 9, descriptor_type: DescType = DescType.Hid, /// Numeric expression identifying the HID Class Specification release From 57e4379062e396b354d70d5b924d5da2e8905bd4 Mon Sep 17 00:00:00 2001 From: Jacob Young Date: Tue, 28 Nov 2023 10:58:44 -0500 Subject: [PATCH 138/138] Update uf2 dependency (#160) --- build.zig.zon | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.zig.zon b/build.zig.zon index a237901..437acb5 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -14,8 +14,8 @@ }, .dependencies = .{ .uf2 = .{ - .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/0550d4b1519264669b4ac5d944c370b41ebd6579.tar.gz", - .hash = "122058e26facbba3f6e06881ec0d356c7f9046e88edc46b9f244b50d366062528471", + .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz", + .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a", }, .regz = .{ .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",